Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 42
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 22
1 00:37:40.954374 lava-dispatcher, installed at version: 2024.03
2 00:37:40.954579 start: 0 validate
3 00:37:40.954718 Start time: 2024-06-05 00:37:40.954711+00:00 (UTC)
4 00:37:40.954845 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:37:40.954986 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:37:41.206076 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:37:41.206293 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:37:41.465918 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:37:41.466675 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:37:56.597063 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:37:56.597765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:37:57.108524 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:37:57.109315 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:37:57.379658 validate duration: 16.42
16 00:37:57.380998 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:37:57.381608 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:37:57.382099 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:37:57.382724 Not decompressing ramdisk as can be used compressed.
20 00:37:57.383209 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 00:37:57.383566 saving as /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/ramdisk/initrd.cpio.gz
22 00:37:57.383930 total size: 5628182 (5 MB)
23 00:38:00.204441 progress 0 % (0 MB)
24 00:38:00.208676 progress 5 % (0 MB)
25 00:38:00.210265 progress 10 % (0 MB)
26 00:38:00.211629 progress 15 % (0 MB)
27 00:38:00.213205 progress 20 % (1 MB)
28 00:38:00.214654 progress 25 % (1 MB)
29 00:38:00.216174 progress 30 % (1 MB)
30 00:38:00.217773 progress 35 % (1 MB)
31 00:38:00.219114 progress 40 % (2 MB)
32 00:38:00.220603 progress 45 % (2 MB)
33 00:38:00.222001 progress 50 % (2 MB)
34 00:38:00.223543 progress 55 % (2 MB)
35 00:38:00.225160 progress 60 % (3 MB)
36 00:38:00.226722 progress 65 % (3 MB)
37 00:38:00.228317 progress 70 % (3 MB)
38 00:38:00.229738 progress 75 % (4 MB)
39 00:38:00.231228 progress 80 % (4 MB)
40 00:38:00.232557 progress 85 % (4 MB)
41 00:38:00.234069 progress 90 % (4 MB)
42 00:38:00.235558 progress 95 % (5 MB)
43 00:38:00.236908 progress 100 % (5 MB)
44 00:38:00.237166 5 MB downloaded in 2.85 s (1.88 MB/s)
45 00:38:00.237318 end: 1.1.1 http-download (duration 00:00:03) [common]
47 00:38:00.237547 end: 1.1 download-retry (duration 00:00:03) [common]
48 00:38:00.237632 start: 1.2 download-retry (timeout 00:09:57) [common]
49 00:38:00.237718 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 00:38:00.237857 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:38:00.237925 saving as /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/kernel/Image
52 00:38:00.237985 total size: 54682112 (52 MB)
53 00:38:00.238046 No compression specified
54 00:38:00.239287 progress 0 % (0 MB)
55 00:38:00.253796 progress 5 % (2 MB)
56 00:38:00.267558 progress 10 % (5 MB)
57 00:38:00.281508 progress 15 % (7 MB)
58 00:38:00.295237 progress 20 % (10 MB)
59 00:38:00.309142 progress 25 % (13 MB)
60 00:38:00.322978 progress 30 % (15 MB)
61 00:38:00.336980 progress 35 % (18 MB)
62 00:38:00.351092 progress 40 % (20 MB)
63 00:38:00.364866 progress 45 % (23 MB)
64 00:38:00.378817 progress 50 % (26 MB)
65 00:38:00.392765 progress 55 % (28 MB)
66 00:38:00.406605 progress 60 % (31 MB)
67 00:38:00.420173 progress 65 % (33 MB)
68 00:38:00.434057 progress 70 % (36 MB)
69 00:38:00.448058 progress 75 % (39 MB)
70 00:38:00.462298 progress 80 % (41 MB)
71 00:38:00.476207 progress 85 % (44 MB)
72 00:38:00.490058 progress 90 % (46 MB)
73 00:38:00.503713 progress 95 % (49 MB)
74 00:38:00.517123 progress 100 % (52 MB)
75 00:38:00.517345 52 MB downloaded in 0.28 s (186.68 MB/s)
76 00:38:00.517497 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:38:00.517731 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:38:00.517817 start: 1.3 download-retry (timeout 00:09:57) [common]
80 00:38:00.517902 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 00:38:00.518038 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:38:00.518109 saving as /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/dtb/mt8192-asurada-spherion-r0.dtb
83 00:38:00.518170 total size: 47258 (0 MB)
84 00:38:00.518230 No compression specified
85 00:38:00.519313 progress 69 % (0 MB)
86 00:38:00.519591 progress 100 % (0 MB)
87 00:38:00.519746 0 MB downloaded in 0.00 s (28.64 MB/s)
88 00:38:00.519868 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:38:00.520087 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:38:00.520171 start: 1.4 download-retry (timeout 00:09:57) [common]
92 00:38:00.520253 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 00:38:00.520365 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 00:38:00.520432 saving as /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/nfsrootfs/full.rootfs.tar
95 00:38:00.520493 total size: 107552908 (102 MB)
96 00:38:00.520554 Using unxz to decompress xz
97 00:38:00.524502 progress 0 % (0 MB)
98 00:38:00.804290 progress 5 % (5 MB)
99 00:38:01.122945 progress 10 % (10 MB)
100 00:38:01.442600 progress 15 % (15 MB)
101 00:38:01.771832 progress 20 % (20 MB)
102 00:38:02.039930 progress 25 % (25 MB)
103 00:38:02.333815 progress 30 % (30 MB)
104 00:38:02.656838 progress 35 % (35 MB)
105 00:38:02.826062 progress 40 % (41 MB)
106 00:38:03.023274 progress 45 % (46 MB)
107 00:38:03.343357 progress 50 % (51 MB)
108 00:38:03.658805 progress 55 % (56 MB)
109 00:38:03.997952 progress 60 % (61 MB)
110 00:38:04.327330 progress 65 % (66 MB)
111 00:38:04.649643 progress 70 % (71 MB)
112 00:38:04.982102 progress 75 % (76 MB)
113 00:38:05.282016 progress 80 % (82 MB)
114 00:38:05.597598 progress 85 % (87 MB)
115 00:38:05.909904 progress 90 % (92 MB)
116 00:38:06.222363 progress 95 % (97 MB)
117 00:38:06.546233 progress 100 % (102 MB)
118 00:38:06.551425 102 MB downloaded in 6.03 s (17.01 MB/s)
119 00:38:06.551726 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:38:06.552034 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:38:06.552125 start: 1.5 download-retry (timeout 00:09:51) [common]
123 00:38:06.552209 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 00:38:06.552354 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:38:06.552424 saving as /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/modules/modules.tar
126 00:38:06.552484 total size: 8605984 (8 MB)
127 00:38:06.552546 Using unxz to decompress xz
128 00:38:06.556882 progress 0 % (0 MB)
129 00:38:06.575937 progress 5 % (0 MB)
130 00:38:06.603042 progress 10 % (0 MB)
131 00:38:06.633855 progress 15 % (1 MB)
132 00:38:06.658571 progress 20 % (1 MB)
133 00:38:06.682522 progress 25 % (2 MB)
134 00:38:06.706493 progress 30 % (2 MB)
135 00:38:06.731949 progress 35 % (2 MB)
136 00:38:06.760044 progress 40 % (3 MB)
137 00:38:06.783221 progress 45 % (3 MB)
138 00:38:06.807992 progress 50 % (4 MB)
139 00:38:06.833384 progress 55 % (4 MB)
140 00:38:06.858516 progress 60 % (4 MB)
141 00:38:06.883346 progress 65 % (5 MB)
142 00:38:06.908618 progress 70 % (5 MB)
143 00:38:06.932522 progress 75 % (6 MB)
144 00:38:06.960685 progress 80 % (6 MB)
145 00:38:06.985514 progress 85 % (7 MB)
146 00:38:07.011182 progress 90 % (7 MB)
147 00:38:07.036626 progress 95 % (7 MB)
148 00:38:07.061980 progress 100 % (8 MB)
149 00:38:07.067379 8 MB downloaded in 0.51 s (15.94 MB/s)
150 00:38:07.067711 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:38:07.068126 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:38:07.068260 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 00:38:07.068394 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 00:38:09.140486 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq
156 00:38:09.140686 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:38:09.140788 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 00:38:09.140954 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r
159 00:38:09.141183 makedir: /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin
160 00:38:09.141290 makedir: /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/tests
161 00:38:09.141388 makedir: /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/results
162 00:38:09.141489 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-add-keys
163 00:38:09.141630 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-add-sources
164 00:38:09.141758 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-background-process-start
165 00:38:09.141886 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-background-process-stop
166 00:38:09.142011 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-common-functions
167 00:38:09.142170 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-echo-ipv4
168 00:38:09.142296 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-install-packages
169 00:38:09.142420 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-installed-packages
170 00:38:09.142544 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-os-build
171 00:38:09.142667 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-probe-channel
172 00:38:09.142791 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-probe-ip
173 00:38:09.142915 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-target-ip
174 00:38:09.143037 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-target-mac
175 00:38:09.143160 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-target-storage
176 00:38:09.143285 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-case
177 00:38:09.143407 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-event
178 00:38:09.143531 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-feedback
179 00:38:09.143653 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-raise
180 00:38:09.143774 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-reference
181 00:38:09.143897 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-runner
182 00:38:09.144018 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-set
183 00:38:09.144250 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-test-shell
184 00:38:09.144380 Updating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-install-packages (oe)
185 00:38:09.144531 Updating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/bin/lava-installed-packages (oe)
186 00:38:09.144652 Creating /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/environment
187 00:38:09.144748 LAVA metadata
188 00:38:09.144815 - LAVA_JOB_ID=14173496
189 00:38:09.144877 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:38:09.144981 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
191 00:38:09.145083 skipped lava-vland-overlay
192 00:38:09.145157 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:38:09.145235 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
194 00:38:09.145296 skipped lava-multinode-overlay
195 00:38:09.145367 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:38:09.145442 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
197 00:38:09.145514 Loading test definitions
198 00:38:09.145600 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
199 00:38:09.145670 Using /lava-14173496 at stage 0
200 00:38:09.145976 uuid=14173496_1.6.2.3.1 testdef=None
201 00:38:09.146084 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:38:09.146183 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
203 00:38:09.146681 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:38:09.146899 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
206 00:38:09.147522 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:38:09.147750 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
209 00:38:09.148350 runner path: /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/0/tests/0_dmesg test_uuid 14173496_1.6.2.3.1
210 00:38:09.148506 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:38:09.148710 Creating lava-test-runner.conf files
213 00:38:09.148773 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173496/lava-overlay-y6_h5u7r/lava-14173496/0 for stage 0
214 00:38:09.148860 - 0_dmesg
215 00:38:09.148955 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:38:09.149234 start: 1.6.2.4 compress-overlay (timeout 00:09:48) [common]
217 00:38:09.155050 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:38:09.155150 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:48) [common]
219 00:38:09.155233 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:38:09.155315 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:38:09.155398 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:48) [common]
222 00:38:09.321086 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:38:09.321478 start: 1.6.4 extract-modules (timeout 00:09:48) [common]
224 00:38:09.321588 extracting modules file /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq
225 00:38:09.535472 extracting modules file /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173496/extract-overlay-ramdisk-8kn10mdo/ramdisk
226 00:38:09.752839 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:38:09.753027 start: 1.6.5 apply-overlay-tftp (timeout 00:09:48) [common]
228 00:38:09.753122 [common] Applying overlay to NFS
229 00:38:09.753191 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173496/compress-overlay-bm7v2vb1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq
230 00:38:09.759610 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:38:09.759749 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
232 00:38:09.759846 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:38:09.759934 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
234 00:38:09.760016 Building ramdisk /var/lib/lava/dispatcher/tmp/14173496/extract-overlay-ramdisk-8kn10mdo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173496/extract-overlay-ramdisk-8kn10mdo/ramdisk
235 00:38:10.097721 >> 130348 blocks
236 00:38:12.132113 rename /var/lib/lava/dispatcher/tmp/14173496/extract-overlay-ramdisk-8kn10mdo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/ramdisk/ramdisk.cpio.gz
237 00:38:12.132584 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:38:12.132715 start: 1.6.8 prepare-kernel (timeout 00:09:45) [common]
239 00:38:12.132826 start: 1.6.8.1 prepare-fit (timeout 00:09:45) [common]
240 00:38:12.132926 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/kernel/Image']
241 00:38:26.020056 Returned 0 in 13 seconds
242 00:38:26.120717 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/kernel/image.itb
243 00:38:26.493747 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:38:26.494123 output: Created: Wed Jun 5 01:38:26 2024
245 00:38:26.494200 output: Image 0 (kernel-1)
246 00:38:26.494262 output: Description:
247 00:38:26.494325 output: Created: Wed Jun 5 01:38:26 2024
248 00:38:26.494388 output: Type: Kernel Image
249 00:38:26.494447 output: Compression: lzma compressed
250 00:38:26.494506 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
251 00:38:26.494565 output: Architecture: AArch64
252 00:38:26.494624 output: OS: Linux
253 00:38:26.494683 output: Load Address: 0x00000000
254 00:38:26.494743 output: Entry Point: 0x00000000
255 00:38:26.494801 output: Hash algo: crc32
256 00:38:26.494857 output: Hash value: 4c96ec19
257 00:38:26.494915 output: Image 1 (fdt-1)
258 00:38:26.494972 output: Description: mt8192-asurada-spherion-r0
259 00:38:26.495029 output: Created: Wed Jun 5 01:38:26 2024
260 00:38:26.495086 output: Type: Flat Device Tree
261 00:38:26.495139 output: Compression: uncompressed
262 00:38:26.495193 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 00:38:26.495246 output: Architecture: AArch64
264 00:38:26.495299 output: Hash algo: crc32
265 00:38:26.495352 output: Hash value: 0f8e4d2e
266 00:38:26.495405 output: Image 2 (ramdisk-1)
267 00:38:26.495458 output: Description: unavailable
268 00:38:26.495511 output: Created: Wed Jun 5 01:38:26 2024
269 00:38:26.495564 output: Type: RAMDisk Image
270 00:38:26.495617 output: Compression: Unknown Compression
271 00:38:26.495670 output: Data Size: 18728312 Bytes = 18289.37 KiB = 17.86 MiB
272 00:38:26.495723 output: Architecture: AArch64
273 00:38:26.495776 output: OS: Linux
274 00:38:26.495829 output: Load Address: unavailable
275 00:38:26.495882 output: Entry Point: unavailable
276 00:38:26.495935 output: Hash algo: crc32
277 00:38:26.495988 output: Hash value: 8c91aca8
278 00:38:26.496041 output: Default Configuration: 'conf-1'
279 00:38:26.496093 output: Configuration 0 (conf-1)
280 00:38:26.496146 output: Description: mt8192-asurada-spherion-r0
281 00:38:26.496198 output: Kernel: kernel-1
282 00:38:26.496251 output: Init Ramdisk: ramdisk-1
283 00:38:26.496303 output: FDT: fdt-1
284 00:38:26.496356 output: Loadables: kernel-1
285 00:38:26.496408 output:
286 00:38:26.496619 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 00:38:26.496756 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 00:38:26.496901 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 00:38:26.497028 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
290 00:38:26.497108 No LXC device requested
291 00:38:26.497189 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:38:26.497277 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
293 00:38:26.497357 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:38:26.497426 Checking files for TFTP limit of 4294967296 bytes.
295 00:38:26.497939 end: 1 tftp-deploy (duration 00:00:29) [common]
296 00:38:26.498046 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:38:26.498140 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:38:26.498265 substitutions:
299 00:38:26.498331 - {DTB}: 14173496/tftp-deploy-80fc64l7/dtb/mt8192-asurada-spherion-r0.dtb
300 00:38:26.498398 - {INITRD}: 14173496/tftp-deploy-80fc64l7/ramdisk/ramdisk.cpio.gz
301 00:38:26.498458 - {KERNEL}: 14173496/tftp-deploy-80fc64l7/kernel/Image
302 00:38:26.498516 - {LAVA_MAC}: None
303 00:38:26.498575 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq
304 00:38:26.498631 - {NFS_SERVER_IP}: 192.168.201.1
305 00:38:26.498687 - {PRESEED_CONFIG}: None
306 00:38:26.498743 - {PRESEED_LOCAL}: None
307 00:38:26.498798 - {RAMDISK}: 14173496/tftp-deploy-80fc64l7/ramdisk/ramdisk.cpio.gz
308 00:38:26.498853 - {ROOT_PART}: None
309 00:38:26.498908 - {ROOT}: None
310 00:38:26.498962 - {SERVER_IP}: 192.168.201.1
311 00:38:26.499016 - {TEE}: None
312 00:38:26.499070 Parsed boot commands:
313 00:38:26.499126 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:38:26.499309 Parsed boot commands: tftpboot 192.168.201.1 14173496/tftp-deploy-80fc64l7/kernel/image.itb 14173496/tftp-deploy-80fc64l7/kernel/cmdline
315 00:38:26.499403 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:38:26.499494 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:38:26.499588 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:38:26.499677 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:38:26.499748 Not connected, no need to disconnect.
320 00:38:26.499823 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:38:26.499903 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:38:26.499971 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
323 00:38:26.503763 Setting prompt string to ['lava-test: # ']
324 00:38:26.504148 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:38:26.504257 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:38:26.504357 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:38:26.504481 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:38:26.504698 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
329 00:38:31.638840 >> Command sent successfully.
330 00:38:31.641353 Returned 0 in 5 seconds
331 00:38:31.741778 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 00:38:31.742120 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 00:38:31.742220 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 00:38:31.742314 Setting prompt string to 'Starting depthcharge on Spherion...'
336 00:38:31.742381 Changing prompt to 'Starting depthcharge on Spherion...'
337 00:38:31.742450 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 00:38:31.742851 [Enter `^Ec?' for help]
339 00:38:31.916871
340 00:38:31.917085
341 00:38:31.917162 F0: 102B 0000
342 00:38:31.917226
343 00:38:31.917288 F3: 1001 0000 [0200]
344 00:38:31.920834
345 00:38:31.920922 F3: 1001 0000
346 00:38:31.921034
347 00:38:31.921129 F7: 102D 0000
348 00:38:31.921190
349 00:38:31.923733 F1: 0000 0000
350 00:38:31.923820
351 00:38:31.923887 V0: 0000 0000 [0001]
352 00:38:31.923951
353 00:38:31.926625 00: 0007 8000
354 00:38:31.926716
355 00:38:31.926783 01: 0000 0000
356 00:38:31.926847
357 00:38:31.929904 BP: 0C00 0209 [0000]
358 00:38:31.929989
359 00:38:31.930056 G0: 1182 0000
360 00:38:31.930118
361 00:38:31.933617 EC: 0000 0021 [4000]
362 00:38:31.933704
363 00:38:31.933772 S7: 0000 0000 [0000]
364 00:38:31.933834
365 00:38:31.937917 CC: 0000 0000 [0001]
366 00:38:31.938006
367 00:38:31.938073 T0: 0000 0040 [010F]
368 00:38:31.938135
369 00:38:31.938195 Jump to BL
370 00:38:31.938253
371 00:38:31.964501
372 00:38:31.964664
373 00:38:31.971284 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 00:38:31.974532 ARM64: Exception handlers installed.
375 00:38:31.978108 ARM64: Testing exception
376 00:38:31.981775 ARM64: Done test exception
377 00:38:31.988491 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 00:38:31.999022 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 00:38:32.005974 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 00:38:32.015614 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 00:38:32.022327 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 00:38:32.029326 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 00:38:32.041115 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 00:38:32.048656 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 00:38:32.067101 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 00:38:32.070519 WDT: Last reset was cold boot
387 00:38:32.073864 SPI1(PAD0) initialized at 2873684 Hz
388 00:38:32.077507 SPI5(PAD0) initialized at 992727 Hz
389 00:38:32.080930 VBOOT: Loading verstage.
390 00:38:32.087031 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 00:38:32.090377 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 00:38:32.093733 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 00:38:32.097176 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 00:38:32.104337 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 00:38:32.110559 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 00:38:32.121621 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
397 00:38:32.121760
398 00:38:32.121829
399 00:38:32.132141 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 00:38:32.135268 ARM64: Exception handlers installed.
401 00:38:32.138332 ARM64: Testing exception
402 00:38:32.138424 ARM64: Done test exception
403 00:38:32.145564 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 00:38:32.148403 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 00:38:32.163290 Probing TPM: . done!
406 00:38:32.163452 TPM ready after 0 ms
407 00:38:32.170068 Connected to device vid:did:rid of 1ae0:0028:00
408 00:38:32.176470 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 00:38:32.235129 Initialized TPM device CR50 revision 0
410 00:38:32.247004 tlcl_send_startup: Startup return code is 0
411 00:38:32.247159 TPM: setup succeeded
412 00:38:32.258849 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 00:38:32.268364 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 00:38:32.279804 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 00:38:32.289876 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 00:38:32.293151 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 00:38:32.297722 in-header: 03 07 00 00 08 00 00 00
418 00:38:32.301689 in-data: aa e4 47 04 13 02 00 00
419 00:38:32.304749 Chrome EC: UHEPI supported
420 00:38:32.312432 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 00:38:32.316593 in-header: 03 ad 00 00 08 00 00 00
422 00:38:32.316709 in-data: 00 20 20 08 00 00 00 00
423 00:38:32.319730 Phase 1
424 00:38:32.323490 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 00:38:32.327466 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 00:38:32.334897 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 00:38:32.338678 Recovery requested (1009000e)
428 00:38:32.348801 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 00:38:32.351796 tlcl_extend: response is 0
430 00:38:32.360986 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 00:38:32.366830 tlcl_extend: response is 0
432 00:38:32.374419 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 00:38:32.392996 read SPI 0x210d4 0x2173b: 15149 us, 9044 KB/s, 72.352 Mbps
434 00:38:32.399895 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 00:38:32.400036
436 00:38:32.400107
437 00:38:32.411034 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 00:38:32.415177 ARM64: Exception handlers installed.
439 00:38:32.415286 ARM64: Testing exception
440 00:38:32.417729 ARM64: Done test exception
441 00:38:32.438402 pmic_efuse_setting: Set efuses in 11 msecs
442 00:38:32.441829 pmwrap_interface_init: Select PMIF_VLD_RDY
443 00:38:32.448716 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 00:38:32.452107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 00:38:32.459176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 00:38:32.463587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 00:38:32.466524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 00:38:32.470070 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 00:38:32.478320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 00:38:32.481777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 00:38:32.485174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 00:38:32.492903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 00:38:32.496611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 00:38:32.500530 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 00:38:32.503871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 00:38:32.511322 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 00:38:32.515451 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 00:38:32.522930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 00:38:32.526352 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 00:38:32.534639 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 00:38:32.540906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 00:38:32.544967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 00:38:32.549291 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 00:38:32.555796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 00:38:32.560185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 00:38:32.568089 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 00:38:32.571206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 00:38:32.578869 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 00:38:32.582223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 00:38:32.590311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 00:38:32.593755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 00:38:32.597475 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 00:38:32.601089 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 00:38:32.608196 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 00:38:32.612179 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 00:38:32.619799 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 00:38:32.622809 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 00:38:32.626591 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 00:38:32.633765 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 00:38:32.637610 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 00:38:32.641161 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 00:38:32.645398 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 00:38:32.649049 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 00:38:32.656788 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 00:38:32.659948 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 00:38:32.664206 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 00:38:32.667849 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 00:38:32.671270 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 00:38:32.674830 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 00:38:32.682248 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 00:38:32.685833 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 00:38:32.689545 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 00:38:32.693751 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 00:38:32.700686 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 00:38:32.708363 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 00:38:32.715572 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 00:38:32.723193 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 00:38:32.730448 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 00:38:32.734015 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 00:38:32.742445 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 00:38:32.745542 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:38:32.752463 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
503 00:38:32.756598 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 00:38:32.763846 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
505 00:38:32.767282 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 00:38:32.776129 [RTC]rtc_get_frequency_meter,154: input=15, output=790
507 00:38:32.785316 [RTC]rtc_get_frequency_meter,154: input=23, output=979
508 00:38:32.795028 [RTC]rtc_get_frequency_meter,154: input=19, output=884
509 00:38:32.805171 [RTC]rtc_get_frequency_meter,154: input=17, output=837
510 00:38:32.814849 [RTC]rtc_get_frequency_meter,154: input=16, output=812
511 00:38:32.824565 [RTC]rtc_get_frequency_meter,154: input=15, output=789
512 00:38:32.834017 [RTC]rtc_get_frequency_meter,154: input=16, output=813
513 00:38:32.837746 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
514 00:38:32.842587 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
515 00:38:32.845528 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 00:38:32.852905 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 00:38:32.857338 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 00:38:32.860069 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 00:38:32.864177 ADC[4]: Raw value=901697 ID=7
520 00:38:32.864266 ADC[3]: Raw value=213336 ID=1
521 00:38:32.866855 RAM Code: 0x71
522 00:38:32.870642 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 00:38:32.875486 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 00:38:32.885624 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 00:38:32.890891 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 00:38:32.892492 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 00:38:32.897011 in-header: 03 07 00 00 08 00 00 00
528 00:38:32.900463 in-data: aa e4 47 04 13 02 00 00
529 00:38:32.904494 Chrome EC: UHEPI supported
530 00:38:32.908329 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 00:38:32.911930 in-header: 03 ed 00 00 08 00 00 00
532 00:38:32.915631 in-data: 80 20 60 08 00 00 00 00
533 00:38:32.919092 MRC: failed to locate region type 0.
534 00:38:32.927043 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 00:38:32.930855 DRAM-K: Running full calibration
536 00:38:32.934655 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 00:38:32.937730 header.status = 0x0
538 00:38:32.940996 header.version = 0x6 (expected: 0x6)
539 00:38:32.945110 header.size = 0xd00 (expected: 0xd00)
540 00:38:32.945228 header.flags = 0x0
541 00:38:32.952251 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 00:38:32.970134 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
543 00:38:32.978329 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 00:38:32.978437 dram_init: ddr_geometry: 2
545 00:38:32.982122 [EMI] MDL number = 2
546 00:38:32.985657 [EMI] Get MDL freq = 0
547 00:38:32.985746 dram_init: ddr_type: 0
548 00:38:32.989792 is_discrete_lpddr4: 1
549 00:38:32.989877 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 00:38:32.989944
551 00:38:32.993347
552 00:38:32.993432 [Bian_co] ETT version 0.0.0.1
553 00:38:32.996510 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 00:38:33.000588
555 00:38:33.004322 dramc_set_vcore_voltage set vcore to 650000
556 00:38:33.004411 Read voltage for 800, 4
557 00:38:33.004506 Vio18 = 0
558 00:38:33.008368 Vcore = 650000
559 00:38:33.008493 Vdram = 0
560 00:38:33.008652 Vddq = 0
561 00:38:33.011006 Vmddr = 0
562 00:38:33.011090 dram_init: config_dvfs: 1
563 00:38:33.018712 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 00:38:33.022393 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 00:38:33.025452 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
566 00:38:33.029435 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
567 00:38:33.033593 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
568 00:38:33.038739 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
569 00:38:33.038823 MEM_TYPE=3, freq_sel=18
570 00:38:33.042893 sv_algorithm_assistance_LP4_1600
571 00:38:33.046286 ============ PULL DRAM RESETB DOWN ============
572 00:38:33.052578 ========== PULL DRAM RESETB DOWN end =========
573 00:38:33.055734 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 00:38:33.058907 ===================================
575 00:38:33.062361 LPDDR4 DRAM CONFIGURATION
576 00:38:33.065758 ===================================
577 00:38:33.065842 EX_ROW_EN[0] = 0x0
578 00:38:33.069443 EX_ROW_EN[1] = 0x0
579 00:38:33.069526 LP4Y_EN = 0x0
580 00:38:33.072541 WORK_FSP = 0x0
581 00:38:33.072629 WL = 0x2
582 00:38:33.076297 RL = 0x2
583 00:38:33.076381 BL = 0x2
584 00:38:33.079612 RPST = 0x0
585 00:38:33.079695 RD_PRE = 0x0
586 00:38:33.082814 WR_PRE = 0x1
587 00:38:33.086832 WR_PST = 0x0
588 00:38:33.086915 DBI_WR = 0x0
589 00:38:33.089444 DBI_RD = 0x0
590 00:38:33.089529 OTF = 0x1
591 00:38:33.093459 ===================================
592 00:38:33.096037 ===================================
593 00:38:33.096120 ANA top config
594 00:38:33.099390 ===================================
595 00:38:33.102582 DLL_ASYNC_EN = 0
596 00:38:33.106118 ALL_SLAVE_EN = 1
597 00:38:33.109788 NEW_RANK_MODE = 1
598 00:38:33.109900 DLL_IDLE_MODE = 1
599 00:38:33.113203 LP45_APHY_COMB_EN = 1
600 00:38:33.116155 TX_ODT_DIS = 1
601 00:38:33.119584 NEW_8X_MODE = 1
602 00:38:33.123732 ===================================
603 00:38:33.126314 ===================================
604 00:38:33.130006 data_rate = 1600
605 00:38:33.130090 CKR = 1
606 00:38:33.133272 DQ_P2S_RATIO = 8
607 00:38:33.136347 ===================================
608 00:38:33.140286 CA_P2S_RATIO = 8
609 00:38:33.142829 DQ_CA_OPEN = 0
610 00:38:33.146288 DQ_SEMI_OPEN = 0
611 00:38:33.146378 CA_SEMI_OPEN = 0
612 00:38:33.149568 CA_FULL_RATE = 0
613 00:38:33.153525 DQ_CKDIV4_EN = 1
614 00:38:33.156535 CA_CKDIV4_EN = 1
615 00:38:33.160348 CA_PREDIV_EN = 0
616 00:38:33.163227 PH8_DLY = 0
617 00:38:33.163314 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 00:38:33.166466 DQ_AAMCK_DIV = 4
619 00:38:33.170006 CA_AAMCK_DIV = 4
620 00:38:33.173311 CA_ADMCK_DIV = 4
621 00:38:33.177284 DQ_TRACK_CA_EN = 0
622 00:38:33.180641 CA_PICK = 800
623 00:38:33.180756 CA_MCKIO = 800
624 00:38:33.183310 MCKIO_SEMI = 0
625 00:38:33.187419 PLL_FREQ = 3068
626 00:38:33.190978 DQ_UI_PI_RATIO = 32
627 00:38:33.194899 CA_UI_PI_RATIO = 0
628 00:38:33.197760 ===================================
629 00:38:33.197845 ===================================
630 00:38:33.201525 memory_type:LPDDR4
631 00:38:33.205935 GP_NUM : 10
632 00:38:33.206027 SRAM_EN : 1
633 00:38:33.209120 MD32_EN : 0
634 00:38:33.213561 ===================================
635 00:38:33.213650 [ANA_INIT] >>>>>>>>>>>>>>
636 00:38:33.217675 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 00:38:33.220695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 00:38:33.223801 ===================================
639 00:38:33.227825 data_rate = 1600,PCW = 0X7600
640 00:38:33.230602 ===================================
641 00:38:33.234034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 00:38:33.237564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 00:38:33.243987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:38:33.247364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 00:38:33.250932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 00:38:33.254115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:38:33.257230 [ANA_INIT] flow start
648 00:38:33.260915 [ANA_INIT] PLL >>>>>>>>
649 00:38:33.261024 [ANA_INIT] PLL <<<<<<<<
650 00:38:33.264211 [ANA_INIT] MIDPI >>>>>>>>
651 00:38:33.267901 [ANA_INIT] MIDPI <<<<<<<<
652 00:38:33.267989 [ANA_INIT] DLL >>>>>>>>
653 00:38:33.270835 [ANA_INIT] flow end
654 00:38:33.274819 ============ LP4 DIFF to SE enter ============
655 00:38:33.278256 ============ LP4 DIFF to SE exit ============
656 00:38:33.281430 [ANA_INIT] <<<<<<<<<<<<<
657 00:38:33.284657 [Flow] Enable top DCM control >>>>>
658 00:38:33.287815 [Flow] Enable top DCM control <<<<<
659 00:38:33.291812 Enable DLL master slave shuffle
660 00:38:33.298236 ==============================================================
661 00:38:33.298326 Gating Mode config
662 00:38:33.304371 ==============================================================
663 00:38:33.304461 Config description:
664 00:38:33.314974 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 00:38:33.321679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 00:38:33.328588 SELPH_MODE 0: By rank 1: By Phase
667 00:38:33.331766 ==============================================================
668 00:38:33.335207 GAT_TRACK_EN = 1
669 00:38:33.338352 RX_GATING_MODE = 2
670 00:38:33.342032 RX_GATING_TRACK_MODE = 2
671 00:38:33.344661 SELPH_MODE = 1
672 00:38:33.347994 PICG_EARLY_EN = 1
673 00:38:33.351486 VALID_LAT_VALUE = 1
674 00:38:33.354857 ==============================================================
675 00:38:33.358248 Enter into Gating configuration >>>>
676 00:38:33.361544 Exit from Gating configuration <<<<
677 00:38:33.364927 Enter into DVFS_PRE_config >>>>>
678 00:38:33.375072 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 00:38:33.378557 Exit from DVFS_PRE_config <<<<<
680 00:38:33.381776 Enter into PICG configuration >>>>
681 00:38:33.384999 Exit from PICG configuration <<<<
682 00:38:33.388386 [RX_INPUT] configuration >>>>>
683 00:38:33.391744 [RX_INPUT] configuration <<<<<
684 00:38:33.395494 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 00:38:33.402309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 00:38:33.408929 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 00:38:33.416103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 00:38:33.418896 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 00:38:33.426056 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 00:38:33.429602 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 00:38:33.436755 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 00:38:33.438877 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 00:38:33.442178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 00:38:33.445631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 00:38:33.452582 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 00:38:33.456201 ===================================
697 00:38:33.456279 LPDDR4 DRAM CONFIGURATION
698 00:38:33.459352 ===================================
699 00:38:33.462569 EX_ROW_EN[0] = 0x0
700 00:38:33.466092 EX_ROW_EN[1] = 0x0
701 00:38:33.466184 LP4Y_EN = 0x0
702 00:38:33.469179 WORK_FSP = 0x0
703 00:38:33.469265 WL = 0x2
704 00:38:33.472796 RL = 0x2
705 00:38:33.472881 BL = 0x2
706 00:38:33.476134 RPST = 0x0
707 00:38:33.476221 RD_PRE = 0x0
708 00:38:33.479972 WR_PRE = 0x1
709 00:38:33.480065 WR_PST = 0x0
710 00:38:33.482343 DBI_WR = 0x0
711 00:38:33.482427 DBI_RD = 0x0
712 00:38:33.486400 OTF = 0x1
713 00:38:33.488942 ===================================
714 00:38:33.492726 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 00:38:33.496293 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 00:38:33.502458 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 00:38:33.505966 ===================================
718 00:38:33.506070 LPDDR4 DRAM CONFIGURATION
719 00:38:33.509308 ===================================
720 00:38:33.512782 EX_ROW_EN[0] = 0x10
721 00:38:33.512902 EX_ROW_EN[1] = 0x0
722 00:38:33.516243 LP4Y_EN = 0x0
723 00:38:33.516321 WORK_FSP = 0x0
724 00:38:33.519169 WL = 0x2
725 00:38:33.522619 RL = 0x2
726 00:38:33.522702 BL = 0x2
727 00:38:33.525869 RPST = 0x0
728 00:38:33.525957 RD_PRE = 0x0
729 00:38:33.529251 WR_PRE = 0x1
730 00:38:33.529334 WR_PST = 0x0
731 00:38:33.532536 DBI_WR = 0x0
732 00:38:33.532615 DBI_RD = 0x0
733 00:38:33.536053 OTF = 0x1
734 00:38:33.539347 ===================================
735 00:38:33.542881 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 00:38:33.548236 nWR fixed to 40
737 00:38:33.551430 [ModeRegInit_LP4] CH0 RK0
738 00:38:33.551517 [ModeRegInit_LP4] CH0 RK1
739 00:38:33.554734 [ModeRegInit_LP4] CH1 RK0
740 00:38:33.558190 [ModeRegInit_LP4] CH1 RK1
741 00:38:33.558266 match AC timing 13
742 00:38:33.564802 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 00:38:33.568327 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 00:38:33.572171 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 00:38:33.578511 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 00:38:33.582002 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 00:38:33.582095 [EMI DOE] emi_dcm 0
748 00:38:33.588327 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 00:38:33.588419 ==
750 00:38:33.592502 Dram Type= 6, Freq= 0, CH_0, rank 0
751 00:38:33.595973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 00:38:33.596063 ==
753 00:38:33.602307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 00:38:33.605108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 00:38:33.615939 [CA 0] Center 37 (7~68) winsize 62
756 00:38:33.619074 [CA 1] Center 37 (6~68) winsize 63
757 00:38:33.622293 [CA 2] Center 35 (5~66) winsize 62
758 00:38:33.625390 [CA 3] Center 34 (4~65) winsize 62
759 00:38:33.629568 [CA 4] Center 34 (4~65) winsize 62
760 00:38:33.632281 [CA 5] Center 33 (3~64) winsize 62
761 00:38:33.632382
762 00:38:33.636933 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 00:38:33.637040
764 00:38:33.639212 [CATrainingPosCal] consider 1 rank data
765 00:38:33.642760 u2DelayCellTimex100 = 270/100 ps
766 00:38:33.645736 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 00:38:33.648919 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
768 00:38:33.655892 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
769 00:38:33.658916 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 00:38:33.662788 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
771 00:38:33.665906 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 00:38:33.666006
773 00:38:33.669407 CA PerBit enable=1, Macro0, CA PI delay=33
774 00:38:33.669498
775 00:38:33.672611 [CBTSetCACLKResult] CA Dly = 33
776 00:38:33.672699 CS Dly: 5 (0~36)
777 00:38:33.672765 ==
778 00:38:33.676167 Dram Type= 6, Freq= 0, CH_0, rank 1
779 00:38:33.682602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:38:33.682739 ==
781 00:38:33.685891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:38:33.692652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:38:33.702460 [CA 0] Center 37 (6~68) winsize 63
784 00:38:33.704952 [CA 1] Center 37 (7~68) winsize 62
785 00:38:33.709264 [CA 2] Center 35 (4~66) winsize 63
786 00:38:33.711874 [CA 3] Center 34 (4~65) winsize 62
787 00:38:33.715812 [CA 4] Center 34 (4~65) winsize 62
788 00:38:33.718784 [CA 5] Center 33 (3~64) winsize 62
789 00:38:33.718867
790 00:38:33.722024 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:38:33.722107
792 00:38:33.725213 [CATrainingPosCal] consider 2 rank data
793 00:38:33.729246 u2DelayCellTimex100 = 270/100 ps
794 00:38:33.732393 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 00:38:33.736584 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 00:38:33.739094 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 00:38:33.745987 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:38:33.749369 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:38:33.752174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:38:33.752258
801 00:38:33.756174 CA PerBit enable=1, Macro0, CA PI delay=33
802 00:38:33.756257
803 00:38:33.759027 [CBTSetCACLKResult] CA Dly = 33
804 00:38:33.759110 CS Dly: 6 (0~38)
805 00:38:33.759175
806 00:38:33.762889 ----->DramcWriteLeveling(PI) begin...
807 00:38:33.762977 ==
808 00:38:33.765719 Dram Type= 6, Freq= 0, CH_0, rank 0
809 00:38:33.773310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:38:33.773435 ==
811 00:38:33.773502 Write leveling (Byte 0): 29 => 29
812 00:38:33.776915 Write leveling (Byte 1): 28 => 28
813 00:38:33.780545 DramcWriteLeveling(PI) end<-----
814 00:38:33.780631
815 00:38:33.780696 ==
816 00:38:33.785396 Dram Type= 6, Freq= 0, CH_0, rank 0
817 00:38:33.788279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 00:38:33.788384 ==
819 00:38:33.792137 [Gating] SW mode calibration
820 00:38:33.798963 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 00:38:33.802562 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 00:38:33.809325 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 00:38:33.812438 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 00:38:33.815744 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
825 00:38:33.822109 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:38:33.825518 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:38:33.828970 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:38:33.836260 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:38:33.839291 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:38:33.842676 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:38:33.845618 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:38:33.852817 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:38:33.855659 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 00:38:33.859599 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 00:38:33.866200 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 00:38:33.869799 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 00:38:33.872932 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:38:33.879343 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 00:38:33.883714 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 00:38:33.887333 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
841 00:38:33.893119 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 00:38:33.896873 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 00:38:33.900371 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:38:33.902991 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:38:33.909410 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:38:33.913098 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:38:33.916060 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 00:38:33.922734 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 00:38:33.927210 0 9 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
850 00:38:33.930206 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 00:38:33.936128 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 00:38:33.939530 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 00:38:33.942983 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 00:38:33.950203 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 00:38:33.953690 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 00:38:33.956404 0 10 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
857 00:38:33.959607 0 10 12 | B1->B0 | 2727 2424 | 0 0 | (0 0) (1 0)
858 00:38:33.966776 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:38:33.969654 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:38:33.973924 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:38:33.979897 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:38:33.983678 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:38:33.986835 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:38:33.993692 0 11 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
865 00:38:33.997215 0 11 12 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
866 00:38:34.000493 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:38:34.006724 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:38:34.010146 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 00:38:34.013906 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 00:38:34.016713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 00:38:34.023574 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 00:38:34.026867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 00:38:34.030636 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 00:38:34.036989 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:38:34.040486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:38:34.043854 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:38:34.050545 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:38:34.054001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:38:34.057835 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:38:34.063843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:38:34.067385 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:38:34.070865 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:38:34.074058 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:38:34.081348 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 00:38:34.084558 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 00:38:34.087552 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 00:38:34.094560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
888 00:38:34.097906 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 00:38:34.100956 Total UI for P1: 0, mck2ui 16
890 00:38:34.105011 best dqsien dly found for B0: ( 0, 14, 4)
891 00:38:34.108815 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 00:38:34.111435 Total UI for P1: 0, mck2ui 16
893 00:38:34.114502 best dqsien dly found for B1: ( 0, 14, 8)
894 00:38:34.118152 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
895 00:38:34.121834 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
896 00:38:34.121921
897 00:38:34.124472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
898 00:38:34.128052 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 00:38:34.131376 [Gating] SW calibration Done
900 00:38:34.131491 ==
901 00:38:34.136005 Dram Type= 6, Freq= 0, CH_0, rank 0
902 00:38:34.142202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 00:38:34.142328 ==
904 00:38:34.142441 RX Vref Scan: 0
905 00:38:34.142541
906 00:38:34.144593 RX Vref 0 -> 0, step: 1
907 00:38:34.144675
908 00:38:34.148392 RX Delay -130 -> 252, step: 16
909 00:38:34.151449 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
910 00:38:34.154994 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
911 00:38:34.158033 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
912 00:38:34.161420 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
913 00:38:34.168385 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
914 00:38:34.171738 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
915 00:38:34.175037 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
916 00:38:34.178336 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
917 00:38:34.182708 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
918 00:38:34.185899 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
919 00:38:34.192160 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
920 00:38:34.195679 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
921 00:38:34.198516 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
922 00:38:34.201877 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
923 00:38:34.206080 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
924 00:38:34.211857 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
925 00:38:34.212007 ==
926 00:38:34.216224 Dram Type= 6, Freq= 0, CH_0, rank 0
927 00:38:34.219072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 00:38:34.219189 ==
929 00:38:34.219292 DQS Delay:
930 00:38:34.222255 DQS0 = 0, DQS1 = 0
931 00:38:34.222377 DQM Delay:
932 00:38:34.225674 DQM0 = 84, DQM1 = 76
933 00:38:34.225790 DQ Delay:
934 00:38:34.228916 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
935 00:38:34.232636 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
936 00:38:34.235840 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
937 00:38:34.238895 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
938 00:38:34.238984
939 00:38:34.239055
940 00:38:34.239117 ==
941 00:38:34.242471 Dram Type= 6, Freq= 0, CH_0, rank 0
942 00:38:34.245826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 00:38:34.245909 ==
944 00:38:34.246023
945 00:38:34.246092
946 00:38:34.248874 TX Vref Scan disable
947 00:38:34.252558 == TX Byte 0 ==
948 00:38:34.255905 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
949 00:38:34.259409 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
950 00:38:34.262686 == TX Byte 1 ==
951 00:38:34.266148 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
952 00:38:34.269203 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
953 00:38:34.269292 ==
954 00:38:34.272390 Dram Type= 6, Freq= 0, CH_0, rank 0
955 00:38:34.276198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 00:38:34.279995 ==
957 00:38:34.290884 TX Vref=22, minBit 0, minWin=27, winSum=439
958 00:38:34.294388 TX Vref=24, minBit 3, minWin=27, winSum=440
959 00:38:34.297947 TX Vref=26, minBit 3, minWin=27, winSum=445
960 00:38:34.300908 TX Vref=28, minBit 3, minWin=27, winSum=452
961 00:38:34.304232 TX Vref=30, minBit 2, minWin=28, winSum=455
962 00:38:34.307504 TX Vref=32, minBit 9, minWin=27, winSum=453
963 00:38:34.314625 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
964 00:38:34.314757
965 00:38:34.317659 Final TX Range 1 Vref 30
966 00:38:34.317772
967 00:38:34.317870 ==
968 00:38:34.320889 Dram Type= 6, Freq= 0, CH_0, rank 0
969 00:38:34.324160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 00:38:34.324272 ==
971 00:38:34.324367
972 00:38:34.324455
973 00:38:34.327410 TX Vref Scan disable
974 00:38:34.330997 == TX Byte 0 ==
975 00:38:34.334297 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
976 00:38:34.338110 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
977 00:38:34.340846 == TX Byte 1 ==
978 00:38:34.344429 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
979 00:38:34.347864 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
980 00:38:34.347949
981 00:38:34.350913 [DATLAT]
982 00:38:34.351013 Freq=800, CH0 RK0
983 00:38:34.351080
984 00:38:34.354512 DATLAT Default: 0xa
985 00:38:34.354620 0, 0xFFFF, sum = 0
986 00:38:34.358299 1, 0xFFFF, sum = 0
987 00:38:34.358438 2, 0xFFFF, sum = 0
988 00:38:34.361224 3, 0xFFFF, sum = 0
989 00:38:34.361309 4, 0xFFFF, sum = 0
990 00:38:34.365313 5, 0xFFFF, sum = 0
991 00:38:34.365418 6, 0xFFFF, sum = 0
992 00:38:34.368040 7, 0xFFFF, sum = 0
993 00:38:34.368166 8, 0xFFFF, sum = 0
994 00:38:34.371392 9, 0x0, sum = 1
995 00:38:34.371502 10, 0x0, sum = 2
996 00:38:34.374673 11, 0x0, sum = 3
997 00:38:34.374759 12, 0x0, sum = 4
998 00:38:34.378373 best_step = 10
999 00:38:34.378456
1000 00:38:34.378560 ==
1001 00:38:34.381522 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 00:38:34.385189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 00:38:34.385275 ==
1004 00:38:34.385342 RX Vref Scan: 1
1005 00:38:34.388107
1006 00:38:34.388191 Set Vref Range= 32 -> 127
1007 00:38:34.388256
1008 00:38:34.391298 RX Vref 32 -> 127, step: 1
1009 00:38:34.391384
1010 00:38:34.394815 RX Delay -111 -> 252, step: 8
1011 00:38:34.394899
1012 00:38:34.398367 Set Vref, RX VrefLevel [Byte0]: 32
1013 00:38:34.401762 [Byte1]: 32
1014 00:38:34.401844
1015 00:38:34.405498 Set Vref, RX VrefLevel [Byte0]: 33
1016 00:38:34.408590 [Byte1]: 33
1017 00:38:34.408676
1018 00:38:34.412579 Set Vref, RX VrefLevel [Byte0]: 34
1019 00:38:34.416547 [Byte1]: 34
1020 00:38:34.416673
1021 00:38:34.419619 Set Vref, RX VrefLevel [Byte0]: 35
1022 00:38:34.422255 [Byte1]: 35
1023 00:38:34.427032
1024 00:38:34.427119 Set Vref, RX VrefLevel [Byte0]: 36
1025 00:38:34.429684 [Byte1]: 36
1026 00:38:34.434314
1027 00:38:34.434400 Set Vref, RX VrefLevel [Byte0]: 37
1028 00:38:34.437525 [Byte1]: 37
1029 00:38:34.442598
1030 00:38:34.442692 Set Vref, RX VrefLevel [Byte0]: 38
1031 00:38:34.445489 [Byte1]: 38
1032 00:38:34.449682
1033 00:38:34.449773 Set Vref, RX VrefLevel [Byte0]: 39
1034 00:38:34.453810 [Byte1]: 39
1035 00:38:34.457374
1036 00:38:34.457459 Set Vref, RX VrefLevel [Byte0]: 40
1037 00:38:34.460924 [Byte1]: 40
1038 00:38:34.465053
1039 00:38:34.465147 Set Vref, RX VrefLevel [Byte0]: 41
1040 00:38:34.468190 [Byte1]: 41
1041 00:38:34.473984
1042 00:38:34.474076 Set Vref, RX VrefLevel [Byte0]: 42
1043 00:38:34.476184 [Byte1]: 42
1044 00:38:34.479732
1045 00:38:34.479816 Set Vref, RX VrefLevel [Byte0]: 43
1046 00:38:34.483366 [Byte1]: 43
1047 00:38:34.487342
1048 00:38:34.487424 Set Vref, RX VrefLevel [Byte0]: 44
1049 00:38:34.490800 [Byte1]: 44
1050 00:38:34.495752
1051 00:38:34.495839 Set Vref, RX VrefLevel [Byte0]: 45
1052 00:38:34.498368 [Byte1]: 45
1053 00:38:34.503148
1054 00:38:34.503231 Set Vref, RX VrefLevel [Byte0]: 46
1055 00:38:34.506527 [Byte1]: 46
1056 00:38:34.510555
1057 00:38:34.510641 Set Vref, RX VrefLevel [Byte0]: 47
1058 00:38:34.514342 [Byte1]: 47
1059 00:38:34.519371
1060 00:38:34.519457 Set Vref, RX VrefLevel [Byte0]: 48
1061 00:38:34.521669 [Byte1]: 48
1062 00:38:34.526030
1063 00:38:34.526113 Set Vref, RX VrefLevel [Byte0]: 49
1064 00:38:34.529195 [Byte1]: 49
1065 00:38:34.533880
1066 00:38:34.533964 Set Vref, RX VrefLevel [Byte0]: 50
1067 00:38:34.536639 [Byte1]: 50
1068 00:38:34.541197
1069 00:38:34.541283 Set Vref, RX VrefLevel [Byte0]: 51
1070 00:38:34.544496 [Byte1]: 51
1071 00:38:34.548969
1072 00:38:34.549075 Set Vref, RX VrefLevel [Byte0]: 52
1073 00:38:34.551996 [Byte1]: 52
1074 00:38:34.556283
1075 00:38:34.556366 Set Vref, RX VrefLevel [Byte0]: 53
1076 00:38:34.560637 [Byte1]: 53
1077 00:38:34.563871
1078 00:38:34.563952 Set Vref, RX VrefLevel [Byte0]: 54
1079 00:38:34.568188 [Byte1]: 54
1080 00:38:34.571989
1081 00:38:34.572073 Set Vref, RX VrefLevel [Byte0]: 55
1082 00:38:34.575109 [Byte1]: 55
1083 00:38:34.579175
1084 00:38:34.579257 Set Vref, RX VrefLevel [Byte0]: 56
1085 00:38:34.582834 [Byte1]: 56
1086 00:38:34.587854
1087 00:38:34.587936 Set Vref, RX VrefLevel [Byte0]: 57
1088 00:38:34.590526 [Byte1]: 57
1089 00:38:34.594686
1090 00:38:34.594766 Set Vref, RX VrefLevel [Byte0]: 58
1091 00:38:34.598432 [Byte1]: 58
1092 00:38:34.602653
1093 00:38:34.602733 Set Vref, RX VrefLevel [Byte0]: 59
1094 00:38:34.605744 [Byte1]: 59
1095 00:38:34.609738
1096 00:38:34.609820 Set Vref, RX VrefLevel [Byte0]: 60
1097 00:38:34.613310 [Byte1]: 60
1098 00:38:34.617813
1099 00:38:34.617896 Set Vref, RX VrefLevel [Byte0]: 61
1100 00:38:34.621257 [Byte1]: 61
1101 00:38:34.625030
1102 00:38:34.625113 Set Vref, RX VrefLevel [Byte0]: 62
1103 00:38:34.628397 [Byte1]: 62
1104 00:38:34.633278
1105 00:38:34.633360 Set Vref, RX VrefLevel [Byte0]: 63
1106 00:38:34.636012 [Byte1]: 63
1107 00:38:34.640602
1108 00:38:34.640684 Set Vref, RX VrefLevel [Byte0]: 64
1109 00:38:34.644484 [Byte1]: 64
1110 00:38:34.648188
1111 00:38:34.648269 Set Vref, RX VrefLevel [Byte0]: 65
1112 00:38:34.651628 [Byte1]: 65
1113 00:38:34.655939
1114 00:38:34.656020 Set Vref, RX VrefLevel [Byte0]: 66
1115 00:38:34.659043 [Byte1]: 66
1116 00:38:34.663332
1117 00:38:34.663415 Set Vref, RX VrefLevel [Byte0]: 67
1118 00:38:34.667136 [Byte1]: 67
1119 00:38:34.671213
1120 00:38:34.671295 Set Vref, RX VrefLevel [Byte0]: 68
1121 00:38:34.674759 [Byte1]: 68
1122 00:38:34.679674
1123 00:38:34.679756 Set Vref, RX VrefLevel [Byte0]: 69
1124 00:38:34.682234 [Byte1]: 69
1125 00:38:34.686881
1126 00:38:34.686963 Set Vref, RX VrefLevel [Byte0]: 70
1127 00:38:34.690132 [Byte1]: 70
1128 00:38:34.694278
1129 00:38:34.694361 Set Vref, RX VrefLevel [Byte0]: 71
1130 00:38:34.697296 [Byte1]: 71
1131 00:38:34.701471
1132 00:38:34.701553 Set Vref, RX VrefLevel [Byte0]: 72
1133 00:38:34.705107 [Byte1]: 72
1134 00:38:34.709368
1135 00:38:34.709451 Set Vref, RX VrefLevel [Byte0]: 73
1136 00:38:34.713876 [Byte1]: 73
1137 00:38:34.717382
1138 00:38:34.717464 Set Vref, RX VrefLevel [Byte0]: 74
1139 00:38:34.720659 [Byte1]: 74
1140 00:38:34.725156
1141 00:38:34.725239 Set Vref, RX VrefLevel [Byte0]: 75
1142 00:38:34.728515 [Byte1]: 75
1143 00:38:34.732437
1144 00:38:34.732519 Set Vref, RX VrefLevel [Byte0]: 76
1145 00:38:34.735557 [Byte1]: 76
1146 00:38:34.739885
1147 00:38:34.739968 Set Vref, RX VrefLevel [Byte0]: 77
1148 00:38:34.742936 [Byte1]: 77
1149 00:38:34.747455
1150 00:38:34.747538 Final RX Vref Byte 0 = 62 to rank0
1151 00:38:34.751135 Final RX Vref Byte 1 = 59 to rank0
1152 00:38:34.754867 Final RX Vref Byte 0 = 62 to rank1
1153 00:38:34.757425 Final RX Vref Byte 1 = 59 to rank1==
1154 00:38:34.761094 Dram Type= 6, Freq= 0, CH_0, rank 0
1155 00:38:34.767667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 00:38:34.767751 ==
1157 00:38:34.767817 DQS Delay:
1158 00:38:34.767878 DQS0 = 0, DQS1 = 0
1159 00:38:34.772162 DQM Delay:
1160 00:38:34.772244 DQM0 = 88, DQM1 = 79
1161 00:38:34.774741 DQ Delay:
1162 00:38:34.777343 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1163 00:38:34.777425 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1164 00:38:34.780898 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1165 00:38:34.784418 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1166 00:38:34.784500
1167 00:38:34.787644
1168 00:38:34.794215 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1169 00:38:34.797692 CH0 RK0: MR19=606, MR18=2C14
1170 00:38:34.804725 CH0_RK0: MR19=0x606, MR18=0x2C14, DQSOSC=398, MR23=63, INC=93, DEC=62
1171 00:38:34.804809
1172 00:38:34.808099 ----->DramcWriteLeveling(PI) begin...
1173 00:38:34.808183 ==
1174 00:38:34.811547 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 00:38:34.814699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 00:38:34.814786 ==
1177 00:38:34.818275 Write leveling (Byte 0): 33 => 33
1178 00:38:34.821657 Write leveling (Byte 1): 28 => 28
1179 00:38:34.824827 DramcWriteLeveling(PI) end<-----
1180 00:38:34.824910
1181 00:38:34.824983 ==
1182 00:38:34.828656 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 00:38:34.831469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 00:38:34.831551 ==
1185 00:38:34.835042 [Gating] SW mode calibration
1186 00:38:34.841726 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1187 00:38:34.844833 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1188 00:38:34.851793 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1189 00:38:34.895935 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1190 00:38:34.896470 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1191 00:38:34.896562 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:38:34.896886 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:38:34.897528 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:38:34.898277 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:38:34.898830 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:38:34.898913 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 00:38:34.899162 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 00:38:34.899764 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:38:34.904010 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:38:34.907585 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:38:34.907677 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 00:38:34.911106 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 00:38:34.918052 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 00:38:34.920987 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:38:34.924158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1206 00:38:34.931156 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1207 00:38:34.934266 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 00:38:34.937489 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 00:38:34.944119 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 00:38:34.948008 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 00:38:34.950744 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 00:38:34.957853 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 00:38:34.960840 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 00:38:34.964511 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1215 00:38:34.971225 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
1216 00:38:34.974185 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 00:38:34.978111 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 00:38:34.984649 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 00:38:34.987868 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 00:38:34.990863 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 00:38:34.994343 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1222 00:38:35.000879 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
1223 00:38:35.004799 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:38:35.008737 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:38:35.015837 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:38:35.017908 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:38:35.021604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:38:35.024988 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:38:35.032293 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
1230 00:38:35.036024 0 11 8 | B1->B0 | 2c2c 4343 | 0 0 | (0 0) (0 0)
1231 00:38:35.040287 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1232 00:38:35.042744 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 00:38:35.049835 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 00:38:35.053584 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 00:38:35.057013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 00:38:35.060740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 00:38:35.067203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1238 00:38:35.071217 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1239 00:38:35.074398 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 00:38:35.080654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 00:38:35.084242 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 00:38:35.087207 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 00:38:35.093742 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 00:38:35.097205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 00:38:35.100136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 00:38:35.107688 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 00:38:35.110661 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 00:38:35.113702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 00:38:35.121037 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 00:38:35.123438 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 00:38:35.126970 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 00:38:35.133798 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 00:38:35.137127 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1254 00:38:35.140321 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1255 00:38:35.143539 Total UI for P1: 0, mck2ui 16
1256 00:38:35.147452 best dqsien dly found for B0: ( 0, 14, 4)
1257 00:38:35.150206 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 00:38:35.154331 Total UI for P1: 0, mck2ui 16
1259 00:38:35.157412 best dqsien dly found for B1: ( 0, 14, 8)
1260 00:38:35.160900 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1261 00:38:35.163693 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1262 00:38:35.163778
1263 00:38:35.170888 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1264 00:38:35.174121 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1265 00:38:35.174209 [Gating] SW calibration Done
1266 00:38:35.178104 ==
1267 00:38:35.178187 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 00:38:35.184360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 00:38:35.184451 ==
1270 00:38:35.184516 RX Vref Scan: 0
1271 00:38:35.184576
1272 00:38:35.187452 RX Vref 0 -> 0, step: 1
1273 00:38:35.187534
1274 00:38:35.191213 RX Delay -130 -> 252, step: 16
1275 00:38:35.194212 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1276 00:38:35.197266 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1277 00:38:35.201731 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1278 00:38:35.207473 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1279 00:38:35.210718 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1280 00:38:35.214342 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1281 00:38:35.217455 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1282 00:38:35.221313 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1283 00:38:35.228103 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1284 00:38:35.231143 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1285 00:38:35.234313 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1286 00:38:35.238215 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1287 00:38:35.241635 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1288 00:38:35.247560 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1289 00:38:35.251514 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1290 00:38:35.254243 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1291 00:38:35.254327 ==
1292 00:38:35.258080 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 00:38:35.262113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 00:38:35.262197 ==
1295 00:38:35.265788 DQS Delay:
1296 00:38:35.265870 DQS0 = 0, DQS1 = 0
1297 00:38:35.265935 DQM Delay:
1298 00:38:35.267559 DQM0 = 86, DQM1 = 76
1299 00:38:35.267640 DQ Delay:
1300 00:38:35.271178 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1301 00:38:35.274427 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1302 00:38:35.278331 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1303 00:38:35.281393 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1304 00:38:35.281477
1305 00:38:35.281542
1306 00:38:35.281601 ==
1307 00:38:35.284957 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 00:38:35.292013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 00:38:35.292104 ==
1310 00:38:35.292170
1311 00:38:35.292230
1312 00:38:35.292288 TX Vref Scan disable
1313 00:38:35.295324 == TX Byte 0 ==
1314 00:38:35.298136 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1315 00:38:35.302184 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1316 00:38:35.305936 == TX Byte 1 ==
1317 00:38:35.308845 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1318 00:38:35.311876 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1319 00:38:35.311962 ==
1320 00:38:35.315495 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 00:38:35.321954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 00:38:35.322042 ==
1323 00:38:35.335675 TX Vref=22, minBit 5, minWin=27, winSum=443
1324 00:38:35.339097 TX Vref=24, minBit 9, minWin=27, winSum=448
1325 00:38:35.341381 TX Vref=26, minBit 8, minWin=27, winSum=449
1326 00:38:35.344821 TX Vref=28, minBit 3, minWin=28, winSum=456
1327 00:38:35.348468 TX Vref=30, minBit 2, minWin=28, winSum=456
1328 00:38:35.352485 TX Vref=32, minBit 1, minWin=28, winSum=454
1329 00:38:35.358418 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 28
1330 00:38:35.358520
1331 00:38:35.361718 Final TX Range 1 Vref 28
1332 00:38:35.361801
1333 00:38:35.361864 ==
1334 00:38:35.365645 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 00:38:35.367971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 00:38:35.368074 ==
1337 00:38:35.368140
1338 00:38:35.368200
1339 00:38:35.371588 TX Vref Scan disable
1340 00:38:35.374598 == TX Byte 0 ==
1341 00:38:35.378008 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1342 00:38:35.381572 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1343 00:38:35.385499 == TX Byte 1 ==
1344 00:38:35.388191 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1345 00:38:35.391249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1346 00:38:35.394672
1347 00:38:35.394756 [DATLAT]
1348 00:38:35.394821 Freq=800, CH0 RK1
1349 00:38:35.394881
1350 00:38:35.398300 DATLAT Default: 0xa
1351 00:38:35.398382 0, 0xFFFF, sum = 0
1352 00:38:35.401206 1, 0xFFFF, sum = 0
1353 00:38:35.401355 2, 0xFFFF, sum = 0
1354 00:38:35.404690 3, 0xFFFF, sum = 0
1355 00:38:35.404774 4, 0xFFFF, sum = 0
1356 00:38:35.408355 5, 0xFFFF, sum = 0
1357 00:38:35.408440 6, 0xFFFF, sum = 0
1358 00:38:35.411508 7, 0xFFFF, sum = 0
1359 00:38:35.411592 8, 0xFFFF, sum = 0
1360 00:38:35.414792 9, 0x0, sum = 1
1361 00:38:35.414876 10, 0x0, sum = 2
1362 00:38:35.418041 11, 0x0, sum = 3
1363 00:38:35.418127 12, 0x0, sum = 4
1364 00:38:35.421756 best_step = 10
1365 00:38:35.421838
1366 00:38:35.421934 ==
1367 00:38:35.425469 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 00:38:35.428133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 00:38:35.428215 ==
1370 00:38:35.431969 RX Vref Scan: 0
1371 00:38:35.432051
1372 00:38:35.432115 RX Vref 0 -> 0, step: 1
1373 00:38:35.432174
1374 00:38:35.435158 RX Delay -95 -> 252, step: 8
1375 00:38:35.442779 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1376 00:38:35.445422 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1377 00:38:35.448580 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1378 00:38:35.452161 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1379 00:38:35.455332 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1380 00:38:35.458539 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1381 00:38:35.465443 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1382 00:38:35.468383 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1383 00:38:35.472775 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1384 00:38:35.476184 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1385 00:38:35.478340 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1386 00:38:35.485117 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1387 00:38:35.488583 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1388 00:38:35.491721 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1389 00:38:35.495568 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1390 00:38:35.499095 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1391 00:38:35.502895 ==
1392 00:38:35.505374 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 00:38:35.508316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 00:38:35.508401 ==
1395 00:38:35.508465 DQS Delay:
1396 00:38:35.512086 DQS0 = 0, DQS1 = 0
1397 00:38:35.512167 DQM Delay:
1398 00:38:35.515202 DQM0 = 87, DQM1 = 78
1399 00:38:35.515283 DQ Delay:
1400 00:38:35.519304 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1401 00:38:35.522041 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1402 00:38:35.525355 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1403 00:38:35.528535 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1404 00:38:35.528616
1405 00:38:35.528680
1406 00:38:35.536362 [DQSOSCAuto] RK1, (LSB)MR18= 0x3019, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1407 00:38:35.538974 CH0 RK1: MR19=606, MR18=3019
1408 00:38:35.545628 CH0_RK1: MR19=0x606, MR18=0x3019, DQSOSC=397, MR23=63, INC=93, DEC=62
1409 00:38:35.549185 [RxdqsGatingPostProcess] freq 800
1410 00:38:35.552560 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1411 00:38:35.556142 Pre-setting of DQS Precalculation
1412 00:38:35.562405 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1413 00:38:35.562487 ==
1414 00:38:35.566219 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 00:38:35.568691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 00:38:35.568772 ==
1417 00:38:35.575571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 00:38:35.578855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 00:38:35.589245 [CA 0] Center 36 (6~66) winsize 61
1420 00:38:35.592869 [CA 1] Center 36 (6~66) winsize 61
1421 00:38:35.596252 [CA 2] Center 34 (4~65) winsize 62
1422 00:38:35.599638 [CA 3] Center 34 (3~65) winsize 63
1423 00:38:35.603656 [CA 4] Center 34 (4~65) winsize 62
1424 00:38:35.606625 [CA 5] Center 34 (4~64) winsize 61
1425 00:38:35.606706
1426 00:38:35.609606 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1427 00:38:35.609689
1428 00:38:35.613394 [CATrainingPosCal] consider 1 rank data
1429 00:38:35.616512 u2DelayCellTimex100 = 270/100 ps
1430 00:38:35.620160 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1431 00:38:35.623137 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1432 00:38:35.626702 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 00:38:35.629990 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1434 00:38:35.636845 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 00:38:35.639767 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1436 00:38:35.639850
1437 00:38:35.643928 CA PerBit enable=1, Macro0, CA PI delay=34
1438 00:38:35.644010
1439 00:38:35.646646 [CBTSetCACLKResult] CA Dly = 34
1440 00:38:35.646729 CS Dly: 4 (0~35)
1441 00:38:35.646794 ==
1442 00:38:35.650312 Dram Type= 6, Freq= 0, CH_1, rank 1
1443 00:38:35.656576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 00:38:35.656662 ==
1445 00:38:35.660037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 00:38:35.667162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 00:38:35.675389 [CA 0] Center 36 (6~66) winsize 61
1448 00:38:35.678865 [CA 1] Center 36 (6~66) winsize 61
1449 00:38:35.682931 [CA 2] Center 34 (4~64) winsize 61
1450 00:38:35.685980 [CA 3] Center 33 (3~64) winsize 62
1451 00:38:35.689323 [CA 4] Center 34 (4~65) winsize 62
1452 00:38:35.693137 [CA 5] Center 33 (3~64) winsize 62
1453 00:38:35.693222
1454 00:38:35.696481 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1455 00:38:35.696569
1456 00:38:35.700359 [CATrainingPosCal] consider 2 rank data
1457 00:38:35.704211 u2DelayCellTimex100 = 270/100 ps
1458 00:38:35.708469 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1459 00:38:35.711620 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 00:38:35.715614 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1461 00:38:35.719452 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1462 00:38:35.723240 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 00:38:35.723326 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1464 00:38:35.723391
1465 00:38:35.729772 CA PerBit enable=1, Macro0, CA PI delay=33
1466 00:38:35.729857
1467 00:38:35.733962 [CBTSetCACLKResult] CA Dly = 33
1468 00:38:35.734045 CS Dly: 4 (0~36)
1469 00:38:35.734110
1470 00:38:35.736938 ----->DramcWriteLeveling(PI) begin...
1471 00:38:35.737040 ==
1472 00:38:35.740000 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 00:38:35.743415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 00:38:35.743499 ==
1475 00:38:35.746602 Write leveling (Byte 0): 29 => 29
1476 00:38:35.750531 Write leveling (Byte 1): 30 => 30
1477 00:38:35.753954 DramcWriteLeveling(PI) end<-----
1478 00:38:35.754038
1479 00:38:35.754103 ==
1480 00:38:35.757172 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 00:38:35.760300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 00:38:35.763763 ==
1483 00:38:35.763846 [Gating] SW mode calibration
1484 00:38:35.770833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1485 00:38:35.777890 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1486 00:38:35.780551 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1487 00:38:35.787342 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 1)
1488 00:38:35.790288 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1489 00:38:35.793863 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:38:35.800632 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:38:35.803725 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:38:35.807345 0 6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1493 00:38:35.810694 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:38:35.817131 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 00:38:35.820854 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 00:38:35.824459 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 00:38:35.830671 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1498 00:38:35.834687 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1499 00:38:35.838011 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1500 00:38:35.844432 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 00:38:35.847431 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1502 00:38:35.851252 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:38:35.857597 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1504 00:38:35.860935 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1505 00:38:35.864431 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 00:38:35.867808 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 00:38:35.874359 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1508 00:38:35.878085 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1509 00:38:35.881308 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 00:38:35.888404 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 00:38:35.891187 0 9 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1512 00:38:35.894490 0 9 8 | B1->B0 | 2929 2727 | 1 1 | (1 1) (1 1)
1513 00:38:35.901800 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1514 00:38:35.905888 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 00:38:35.908664 0 9 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1516 00:38:35.914648 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 00:38:35.918412 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1518 00:38:35.921322 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 00:38:35.924956 0 10 4 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
1520 00:38:35.931611 0 10 8 | B1->B0 | 2a2a 2e2e | 0 0 | (0 0) (0 0)
1521 00:38:35.935412 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1522 00:38:35.939115 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:38:35.944628 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:38:35.947983 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1525 00:38:35.951539 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:38:35.958697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:38:35.962203 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:38:35.965412 0 11 8 | B1->B0 | 2e2e 2f2f | 1 0 | (0 0) (0 0)
1529 00:38:35.971628 0 11 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1530 00:38:35.975042 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 00:38:35.978475 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 00:38:35.982395 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 00:38:35.988664 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 00:38:35.992100 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 00:38:35.995075 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 00:38:36.002053 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1537 00:38:36.005439 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1538 00:38:36.008852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 00:38:36.015626 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 00:38:36.019694 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 00:38:36.022534 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 00:38:36.028615 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 00:38:36.032600 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 00:38:36.035275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 00:38:36.039776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 00:38:36.045857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 00:38:36.048961 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 00:38:36.052495 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 00:38:36.058753 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 00:38:36.062199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 00:38:36.065391 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 00:38:36.072380 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1553 00:38:36.076226 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 00:38:36.079362 Total UI for P1: 0, mck2ui 16
1555 00:38:36.082602 best dqsien dly found for B0: ( 0, 14, 8)
1556 00:38:36.085614 Total UI for P1: 0, mck2ui 16
1557 00:38:36.089347 best dqsien dly found for B1: ( 0, 14, 10)
1558 00:38:36.092555 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1559 00:38:36.095843 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1560 00:38:36.095954
1561 00:38:36.099390 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1562 00:38:36.102552 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1563 00:38:36.105719 [Gating] SW calibration Done
1564 00:38:36.105808 ==
1565 00:38:36.109425 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 00:38:36.112898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 00:38:36.113007 ==
1568 00:38:36.115845 RX Vref Scan: 0
1569 00:38:36.115928
1570 00:38:36.119135 RX Vref 0 -> 0, step: 1
1571 00:38:36.119219
1572 00:38:36.119284 RX Delay -130 -> 252, step: 16
1573 00:38:36.126092 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1574 00:38:36.129371 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1575 00:38:36.132473 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1576 00:38:36.136025 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1577 00:38:36.139604 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1578 00:38:36.146359 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1579 00:38:36.149508 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1580 00:38:36.152727 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1581 00:38:36.157104 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1582 00:38:36.159888 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1583 00:38:36.163191 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1584 00:38:36.169697 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1585 00:38:36.172997 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1586 00:38:36.176286 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1587 00:38:36.180136 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1588 00:38:36.186595 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1589 00:38:36.186688 ==
1590 00:38:36.190094 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 00:38:36.193188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 00:38:36.193272 ==
1593 00:38:36.193338 DQS Delay:
1594 00:38:36.196959 DQS0 = 0, DQS1 = 0
1595 00:38:36.197057 DQM Delay:
1596 00:38:36.199783 DQM0 = 84, DQM1 = 77
1597 00:38:36.199865 DQ Delay:
1598 00:38:36.203176 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1599 00:38:36.206392 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1600 00:38:36.209859 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1601 00:38:36.213609 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1602 00:38:36.213693
1603 00:38:36.213758
1604 00:38:36.213818 ==
1605 00:38:36.216397 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 00:38:36.219860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 00:38:36.219945 ==
1608 00:38:36.220010
1609 00:38:36.220070
1610 00:38:36.223484 TX Vref Scan disable
1611 00:38:36.226707 == TX Byte 0 ==
1612 00:38:36.230746 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1613 00:38:36.233817 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1614 00:38:36.236625 == TX Byte 1 ==
1615 00:38:36.241969 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1616 00:38:36.243526 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1617 00:38:36.243609 ==
1618 00:38:36.246621 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 00:38:36.250268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 00:38:36.250351 ==
1621 00:38:36.264130 TX Vref=22, minBit 11, minWin=26, winSum=437
1622 00:38:36.267448 TX Vref=24, minBit 1, minWin=27, winSum=442
1623 00:38:36.271252 TX Vref=26, minBit 4, minWin=27, winSum=445
1624 00:38:36.275373 TX Vref=28, minBit 1, minWin=27, winSum=446
1625 00:38:36.278706 TX Vref=30, minBit 0, minWin=28, winSum=451
1626 00:38:36.282062 TX Vref=32, minBit 0, minWin=28, winSum=450
1627 00:38:36.288204 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1628 00:38:36.288290
1629 00:38:36.292224 Final TX Range 1 Vref 30
1630 00:38:36.292308
1631 00:38:36.292373 ==
1632 00:38:36.295042 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 00:38:36.298945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 00:38:36.299029 ==
1635 00:38:36.299095
1636 00:38:36.299155
1637 00:38:36.302072 TX Vref Scan disable
1638 00:38:36.305854 == TX Byte 0 ==
1639 00:38:36.308896 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1640 00:38:36.312467 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1641 00:38:36.315243 == TX Byte 1 ==
1642 00:38:36.318416 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1643 00:38:36.321995 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1644 00:38:36.322080
1645 00:38:36.322145 [DATLAT]
1646 00:38:36.325549 Freq=800, CH1 RK0
1647 00:38:36.325633
1648 00:38:36.325698 DATLAT Default: 0xa
1649 00:38:36.328570 0, 0xFFFF, sum = 0
1650 00:38:36.332562 1, 0xFFFF, sum = 0
1651 00:38:36.332647 2, 0xFFFF, sum = 0
1652 00:38:36.335581 3, 0xFFFF, sum = 0
1653 00:38:36.335665 4, 0xFFFF, sum = 0
1654 00:38:36.338937 5, 0xFFFF, sum = 0
1655 00:38:36.339022 6, 0xFFFF, sum = 0
1656 00:38:36.342476 7, 0xFFFF, sum = 0
1657 00:38:36.342560 8, 0xFFFF, sum = 0
1658 00:38:36.346354 9, 0x0, sum = 1
1659 00:38:36.346437 10, 0x0, sum = 2
1660 00:38:36.346504 11, 0x0, sum = 3
1661 00:38:36.350300 12, 0x0, sum = 4
1662 00:38:36.350384 best_step = 10
1663 00:38:36.350449
1664 00:38:36.350510 ==
1665 00:38:36.352637 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 00:38:36.359416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 00:38:36.359502 ==
1668 00:38:36.359567 RX Vref Scan: 1
1669 00:38:36.359627
1670 00:38:36.362219 Set Vref Range= 32 -> 127
1671 00:38:36.362301
1672 00:38:36.366018 RX Vref 32 -> 127, step: 1
1673 00:38:36.366100
1674 00:38:36.369266 RX Delay -95 -> 252, step: 8
1675 00:38:36.369348
1676 00:38:36.372355 Set Vref, RX VrefLevel [Byte0]: 32
1677 00:38:36.372436 [Byte1]: 32
1678 00:38:36.376798
1679 00:38:36.376878 Set Vref, RX VrefLevel [Byte0]: 33
1680 00:38:36.380333 [Byte1]: 33
1681 00:38:36.384828
1682 00:38:36.384938 Set Vref, RX VrefLevel [Byte0]: 34
1683 00:38:36.388347 [Byte1]: 34
1684 00:38:36.392023
1685 00:38:36.392103 Set Vref, RX VrefLevel [Byte0]: 35
1686 00:38:36.395394 [Byte1]: 35
1687 00:38:36.399349
1688 00:38:36.399430 Set Vref, RX VrefLevel [Byte0]: 36
1689 00:38:36.403005 [Byte1]: 36
1690 00:38:36.406963
1691 00:38:36.407044 Set Vref, RX VrefLevel [Byte0]: 37
1692 00:38:36.410553 [Byte1]: 37
1693 00:38:36.414830
1694 00:38:36.414911 Set Vref, RX VrefLevel [Byte0]: 38
1695 00:38:36.418685 [Byte1]: 38
1696 00:38:36.422388
1697 00:38:36.422469 Set Vref, RX VrefLevel [Byte0]: 39
1698 00:38:36.425553 [Byte1]: 39
1699 00:38:36.429830
1700 00:38:36.429912 Set Vref, RX VrefLevel [Byte0]: 40
1701 00:38:36.434119 [Byte1]: 40
1702 00:38:36.437943
1703 00:38:36.438024 Set Vref, RX VrefLevel [Byte0]: 41
1704 00:38:36.440772 [Byte1]: 41
1705 00:38:36.445236
1706 00:38:36.445317 Set Vref, RX VrefLevel [Byte0]: 42
1707 00:38:36.448525 [Byte1]: 42
1708 00:38:36.452864
1709 00:38:36.452971 Set Vref, RX VrefLevel [Byte0]: 43
1710 00:38:36.456133 [Byte1]: 43
1711 00:38:36.460546
1712 00:38:36.460626 Set Vref, RX VrefLevel [Byte0]: 44
1713 00:38:36.463812 [Byte1]: 44
1714 00:38:36.467882
1715 00:38:36.467963 Set Vref, RX VrefLevel [Byte0]: 45
1716 00:38:36.471652 [Byte1]: 45
1717 00:38:36.475378
1718 00:38:36.475459 Set Vref, RX VrefLevel [Byte0]: 46
1719 00:38:36.479381 [Byte1]: 46
1720 00:38:36.483860
1721 00:38:36.483941 Set Vref, RX VrefLevel [Byte0]: 47
1722 00:38:36.486385 [Byte1]: 47
1723 00:38:36.491519
1724 00:38:36.491599 Set Vref, RX VrefLevel [Byte0]: 48
1725 00:38:36.494212 [Byte1]: 48
1726 00:38:36.498265
1727 00:38:36.498346 Set Vref, RX VrefLevel [Byte0]: 49
1728 00:38:36.501853 [Byte1]: 49
1729 00:38:36.506083
1730 00:38:36.506164 Set Vref, RX VrefLevel [Byte0]: 50
1731 00:38:36.509270 [Byte1]: 50
1732 00:38:36.513695
1733 00:38:36.513780 Set Vref, RX VrefLevel [Byte0]: 51
1734 00:38:36.517866 [Byte1]: 51
1735 00:38:36.521813
1736 00:38:36.521895 Set Vref, RX VrefLevel [Byte0]: 52
1737 00:38:36.524333 [Byte1]: 52
1738 00:38:36.528775
1739 00:38:36.528857 Set Vref, RX VrefLevel [Byte0]: 53
1740 00:38:36.532804 [Byte1]: 53
1741 00:38:36.536521
1742 00:38:36.536603 Set Vref, RX VrefLevel [Byte0]: 54
1743 00:38:36.540057 [Byte1]: 54
1744 00:38:36.544148
1745 00:38:36.544230 Set Vref, RX VrefLevel [Byte0]: 55
1746 00:38:36.547683 [Byte1]: 55
1747 00:38:36.551719
1748 00:38:36.551800 Set Vref, RX VrefLevel [Byte0]: 56
1749 00:38:36.554866 [Byte1]: 56
1750 00:38:36.559258
1751 00:38:36.559341 Set Vref, RX VrefLevel [Byte0]: 57
1752 00:38:36.562756 [Byte1]: 57
1753 00:38:36.566944
1754 00:38:36.567025 Set Vref, RX VrefLevel [Byte0]: 58
1755 00:38:36.570602 [Byte1]: 58
1756 00:38:36.574758
1757 00:38:36.574839 Set Vref, RX VrefLevel [Byte0]: 59
1758 00:38:36.577826 [Byte1]: 59
1759 00:38:36.581987
1760 00:38:36.582083 Set Vref, RX VrefLevel [Byte0]: 60
1761 00:38:36.584897 [Byte1]: 60
1762 00:38:36.589563
1763 00:38:36.589652 Set Vref, RX VrefLevel [Byte0]: 61
1764 00:38:36.593036 [Byte1]: 61
1765 00:38:36.596962
1766 00:38:36.597079 Set Vref, RX VrefLevel [Byte0]: 62
1767 00:38:36.600542 [Byte1]: 62
1768 00:38:36.604849
1769 00:38:36.604969 Set Vref, RX VrefLevel [Byte0]: 63
1770 00:38:36.608204 [Byte1]: 63
1771 00:38:36.612341
1772 00:38:36.612458 Set Vref, RX VrefLevel [Byte0]: 64
1773 00:38:36.615970 [Byte1]: 64
1774 00:38:36.620010
1775 00:38:36.620086 Set Vref, RX VrefLevel [Byte0]: 65
1776 00:38:36.623502 [Byte1]: 65
1777 00:38:36.627344
1778 00:38:36.627420 Set Vref, RX VrefLevel [Byte0]: 66
1779 00:38:36.631206 [Byte1]: 66
1780 00:38:36.634840
1781 00:38:36.634908 Set Vref, RX VrefLevel [Byte0]: 67
1782 00:38:36.638253 [Byte1]: 67
1783 00:38:36.642439
1784 00:38:36.642513 Set Vref, RX VrefLevel [Byte0]: 68
1785 00:38:36.645827 [Byte1]: 68
1786 00:38:36.650774
1787 00:38:36.650857 Set Vref, RX VrefLevel [Byte0]: 69
1788 00:38:36.654033 [Byte1]: 69
1789 00:38:36.658028
1790 00:38:36.658123 Set Vref, RX VrefLevel [Byte0]: 70
1791 00:38:36.661653 [Byte1]: 70
1792 00:38:36.665314
1793 00:38:36.665395 Set Vref, RX VrefLevel [Byte0]: 71
1794 00:38:36.668888 [Byte1]: 71
1795 00:38:36.673284
1796 00:38:36.673372 Set Vref, RX VrefLevel [Byte0]: 72
1797 00:38:36.676321 [Byte1]: 72
1798 00:38:36.680873
1799 00:38:36.680956 Set Vref, RX VrefLevel [Byte0]: 73
1800 00:38:36.684063 [Byte1]: 73
1801 00:38:36.688052
1802 00:38:36.688133 Set Vref, RX VrefLevel [Byte0]: 74
1803 00:38:36.692712 [Byte1]: 74
1804 00:38:36.696056
1805 00:38:36.696138 Set Vref, RX VrefLevel [Byte0]: 75
1806 00:38:36.699389 [Byte1]: 75
1807 00:38:36.704233
1808 00:38:36.704315 Set Vref, RX VrefLevel [Byte0]: 76
1809 00:38:36.706961 [Byte1]: 76
1810 00:38:36.711341
1811 00:38:36.711424 Set Vref, RX VrefLevel [Byte0]: 77
1812 00:38:36.714458 [Byte1]: 77
1813 00:38:36.718616
1814 00:38:36.718697 Set Vref, RX VrefLevel [Byte0]: 78
1815 00:38:36.721871 [Byte1]: 78
1816 00:38:36.726177
1817 00:38:36.726258 Set Vref, RX VrefLevel [Byte0]: 79
1818 00:38:36.729979 [Byte1]: 79
1819 00:38:36.733942
1820 00:38:36.734023 Set Vref, RX VrefLevel [Byte0]: 80
1821 00:38:36.736960 [Byte1]: 80
1822 00:38:36.741855
1823 00:38:36.741937 Final RX Vref Byte 0 = 60 to rank0
1824 00:38:36.745168 Final RX Vref Byte 1 = 60 to rank0
1825 00:38:36.748863 Final RX Vref Byte 0 = 60 to rank1
1826 00:38:36.751519 Final RX Vref Byte 1 = 60 to rank1==
1827 00:38:36.755271 Dram Type= 6, Freq= 0, CH_1, rank 0
1828 00:38:36.758618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 00:38:36.758701 ==
1830 00:38:36.762053 DQS Delay:
1831 00:38:36.762135 DQS0 = 0, DQS1 = 0
1832 00:38:36.765459 DQM Delay:
1833 00:38:36.765540 DQM0 = 84, DQM1 = 75
1834 00:38:36.765604 DQ Delay:
1835 00:38:36.768872 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1836 00:38:36.771887 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1837 00:38:36.776281 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1838 00:38:36.778999 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1839 00:38:36.779081
1840 00:38:36.779145
1841 00:38:36.788878 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1842 00:38:36.792373 CH1 RK0: MR19=605, MR18=27FC
1843 00:38:36.795301 CH1_RK0: MR19=0x605, MR18=0x27FC, DQSOSC=400, MR23=63, INC=92, DEC=61
1844 00:38:36.795383
1845 00:38:36.799094 ----->DramcWriteLeveling(PI) begin...
1846 00:38:36.802270 ==
1847 00:38:36.805104 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 00:38:36.809486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 00:38:36.809595 ==
1850 00:38:36.812049 Write leveling (Byte 0): 27 => 27
1851 00:38:36.815315 Write leveling (Byte 1): 27 => 27
1852 00:38:36.819044 DramcWriteLeveling(PI) end<-----
1853 00:38:36.819114
1854 00:38:36.819178 ==
1855 00:38:36.822170 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 00:38:36.825253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 00:38:36.825349 ==
1858 00:38:36.828717 [Gating] SW mode calibration
1859 00:38:36.836037 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1860 00:38:36.838880 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1861 00:38:36.846070 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 00:38:36.848859 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1863 00:38:36.852597 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:38:36.860288 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:38:36.862205 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1866 00:38:36.865632 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 00:38:36.872614 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 00:38:36.875374 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 00:38:36.879156 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 00:38:36.885635 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 00:38:36.889624 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 00:38:36.892944 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 00:38:36.895733 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1874 00:38:36.902669 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1875 00:38:36.906491 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1876 00:38:36.909710 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1877 00:38:36.916320 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1878 00:38:36.919411 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1879 00:38:36.922569 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1880 00:38:36.929590 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:38:36.932993 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:38:36.936435 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:38:36.942653 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1884 00:38:36.946078 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:38:36.949814 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:38:36.952846 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:38:36.959391 0 9 8 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
1888 00:38:36.962964 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1889 00:38:36.967305 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 00:38:36.973413 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 00:38:36.977319 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1892 00:38:36.980039 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 00:38:36.986657 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1894 00:38:36.990060 0 10 4 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
1895 00:38:36.992963 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1896 00:38:36.999795 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:38:37.003666 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:38:37.006218 0 10 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1899 00:38:37.013330 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:38:37.017168 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:38:37.019692 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:38:37.023479 0 11 4 | B1->B0 | 2828 3838 | 0 0 | (0 0) (0 0)
1903 00:38:37.029984 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1904 00:38:37.033677 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 00:38:37.037248 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 00:38:37.044145 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 00:38:37.046527 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 00:38:37.050053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 00:38:37.057063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 00:38:37.060254 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1911 00:38:37.063876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 00:38:37.070575 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 00:38:37.074218 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 00:38:37.077111 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 00:38:37.080621 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 00:38:37.087181 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 00:38:37.090294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 00:38:37.093937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 00:38:37.100554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 00:38:37.103993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 00:38:37.107750 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 00:38:37.115007 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 00:38:37.117206 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 00:38:37.120971 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 00:38:37.127094 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 00:38:37.130925 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1927 00:38:37.135546 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1928 00:38:37.137505 Total UI for P1: 0, mck2ui 16
1929 00:38:37.140835 best dqsien dly found for B0: ( 0, 14, 4)
1930 00:38:37.143930 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 00:38:37.147951 Total UI for P1: 0, mck2ui 16
1932 00:38:37.151153 best dqsien dly found for B1: ( 0, 14, 6)
1933 00:38:37.154192 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1934 00:38:37.157631 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1935 00:38:37.161394
1936 00:38:37.164277 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1937 00:38:37.167883 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1938 00:38:37.167965 [Gating] SW calibration Done
1939 00:38:37.170864 ==
1940 00:38:37.174570 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 00:38:37.178466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 00:38:37.178548 ==
1943 00:38:37.178612 RX Vref Scan: 0
1944 00:38:37.178687
1945 00:38:37.180787 RX Vref 0 -> 0, step: 1
1946 00:38:37.180869
1947 00:38:37.184416 RX Delay -130 -> 252, step: 16
1948 00:38:37.187580 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1949 00:38:37.191176 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1950 00:38:37.194874 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1951 00:38:37.201754 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1952 00:38:37.204531 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1953 00:38:37.207907 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1954 00:38:37.211438 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1955 00:38:37.214571 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1956 00:38:37.221923 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1957 00:38:37.224590 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1958 00:38:37.228064 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1959 00:38:37.231067 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1960 00:38:37.234957 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1961 00:38:37.241869 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1962 00:38:37.244906 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1963 00:38:37.248137 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1964 00:38:37.248219 ==
1965 00:38:37.251265 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 00:38:37.254810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 00:38:37.254893 ==
1968 00:38:37.258596 DQS Delay:
1969 00:38:37.258677 DQS0 = 0, DQS1 = 0
1970 00:38:37.258741 DQM Delay:
1971 00:38:37.262052 DQM0 = 79, DQM1 = 77
1972 00:38:37.262132 DQ Delay:
1973 00:38:37.265160 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1974 00:38:37.268800 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1975 00:38:37.272816 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1976 00:38:37.274995 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1977 00:38:37.275077
1978 00:38:37.275141
1979 00:38:37.275200 ==
1980 00:38:37.278618 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 00:38:37.285185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 00:38:37.285267 ==
1983 00:38:37.285330
1984 00:38:37.285389
1985 00:38:37.285445 TX Vref Scan disable
1986 00:38:37.288586 == TX Byte 0 ==
1987 00:38:37.291908 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1988 00:38:37.298480 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1989 00:38:37.298591 == TX Byte 1 ==
1990 00:38:37.302025 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1991 00:38:37.304914 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1992 00:38:37.308578 ==
1993 00:38:37.311843 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 00:38:37.315049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 00:38:37.315125 ==
1996 00:38:37.327445 TX Vref=22, minBit 0, minWin=27, winSum=439
1997 00:38:37.330723 TX Vref=24, minBit 1, minWin=27, winSum=443
1998 00:38:37.334248 TX Vref=26, minBit 10, minWin=27, winSum=445
1999 00:38:37.337396 TX Vref=28, minBit 12, minWin=27, winSum=448
2000 00:38:37.340907 TX Vref=30, minBit 0, minWin=28, winSum=454
2001 00:38:37.344358 TX Vref=32, minBit 0, minWin=28, winSum=452
2002 00:38:37.351079 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
2003 00:38:37.351172
2004 00:38:37.354618 Final TX Range 1 Vref 30
2005 00:38:37.354703
2006 00:38:37.354767 ==
2007 00:38:37.357862 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 00:38:37.360863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 00:38:37.360948 ==
2010 00:38:37.361053
2011 00:38:37.361114
2012 00:38:37.364229 TX Vref Scan disable
2013 00:38:37.368181 == TX Byte 0 ==
2014 00:38:37.371099 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 00:38:37.374307 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 00:38:37.377924 == TX Byte 1 ==
2017 00:38:37.381376 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2018 00:38:37.384274 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2019 00:38:37.384357
2020 00:38:37.387889 [DATLAT]
2021 00:38:37.387972 Freq=800, CH1 RK1
2022 00:38:37.388038
2023 00:38:37.390887 DATLAT Default: 0xa
2024 00:38:37.390970 0, 0xFFFF, sum = 0
2025 00:38:37.394612 1, 0xFFFF, sum = 0
2026 00:38:37.394696 2, 0xFFFF, sum = 0
2027 00:38:37.398967 3, 0xFFFF, sum = 0
2028 00:38:37.399052 4, 0xFFFF, sum = 0
2029 00:38:37.401684 5, 0xFFFF, sum = 0
2030 00:38:37.401767 6, 0xFFFF, sum = 0
2031 00:38:37.405095 7, 0xFFFF, sum = 0
2032 00:38:37.405178 8, 0xFFFF, sum = 0
2033 00:38:37.407884 9, 0x0, sum = 1
2034 00:38:37.407967 10, 0x0, sum = 2
2035 00:38:37.411083 11, 0x0, sum = 3
2036 00:38:37.411189 12, 0x0, sum = 4
2037 00:38:37.415239 best_step = 10
2038 00:38:37.415326
2039 00:38:37.415391 ==
2040 00:38:37.418128 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 00:38:37.421116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 00:38:37.421199 ==
2043 00:38:37.424586 RX Vref Scan: 0
2044 00:38:37.424668
2045 00:38:37.424732 RX Vref 0 -> 0, step: 1
2046 00:38:37.424793
2047 00:38:37.427828 RX Delay -95 -> 252, step: 8
2048 00:38:37.435492 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2049 00:38:37.438465 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2050 00:38:37.441239 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2051 00:38:37.445290 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2052 00:38:37.447881 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2053 00:38:37.451070 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2054 00:38:37.458331 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2055 00:38:37.462283 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2056 00:38:37.465235 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2057 00:38:37.468823 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2058 00:38:37.471210 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2059 00:38:37.479671 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2060 00:38:37.482399 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2061 00:38:37.485122 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2062 00:38:37.488100 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2063 00:38:37.491831 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2064 00:38:37.494946 ==
2065 00:38:37.498266 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 00:38:37.502325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 00:38:37.502440 ==
2068 00:38:37.502504 DQS Delay:
2069 00:38:37.504833 DQS0 = 0, DQS1 = 0
2070 00:38:37.504917 DQM Delay:
2071 00:38:37.508312 DQM0 = 80, DQM1 = 76
2072 00:38:37.508394 DQ Delay:
2073 00:38:37.511719 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2074 00:38:37.515198 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2075 00:38:37.518669 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2076 00:38:37.521912 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2077 00:38:37.521995
2078 00:38:37.522060
2079 00:38:37.528345 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2080 00:38:37.532019 CH1 RK1: MR19=606, MR18=222D
2081 00:38:37.538833 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2082 00:38:37.542064 [RxdqsGatingPostProcess] freq 800
2083 00:38:37.545446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2084 00:38:37.548631 Pre-setting of DQS Precalculation
2085 00:38:37.555924 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2086 00:38:37.562600 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2087 00:38:37.569300 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2088 00:38:37.569418
2089 00:38:37.569512
2090 00:38:37.571973 [Calibration Summary] 1600 Mbps
2091 00:38:37.572081 CH 0, Rank 0
2092 00:38:37.575751 SW Impedance : PASS
2093 00:38:37.578868 DUTY Scan : NO K
2094 00:38:37.578997 ZQ Calibration : PASS
2095 00:38:37.581984 Jitter Meter : NO K
2096 00:38:37.585453 CBT Training : PASS
2097 00:38:37.585543 Write leveling : PASS
2098 00:38:37.588772 RX DQS gating : PASS
2099 00:38:37.588898 RX DQ/DQS(RDDQC) : PASS
2100 00:38:37.591930 TX DQ/DQS : PASS
2101 00:38:37.595207 RX DATLAT : PASS
2102 00:38:37.595293 RX DQ/DQS(Engine): PASS
2103 00:38:37.599104 TX OE : NO K
2104 00:38:37.599189 All Pass.
2105 00:38:37.599255
2106 00:38:37.602085 CH 0, Rank 1
2107 00:38:37.602169 SW Impedance : PASS
2108 00:38:37.605296 DUTY Scan : NO K
2109 00:38:37.609281 ZQ Calibration : PASS
2110 00:38:37.609364 Jitter Meter : NO K
2111 00:38:37.612310 CBT Training : PASS
2112 00:38:37.615422 Write leveling : PASS
2113 00:38:37.615507 RX DQS gating : PASS
2114 00:38:37.619666 RX DQ/DQS(RDDQC) : PASS
2115 00:38:37.619775 TX DQ/DQS : PASS
2116 00:38:37.622959 RX DATLAT : PASS
2117 00:38:37.625772 RX DQ/DQS(Engine): PASS
2118 00:38:37.625891 TX OE : NO K
2119 00:38:37.629333 All Pass.
2120 00:38:37.629457
2121 00:38:37.629538 CH 1, Rank 0
2122 00:38:37.632943 SW Impedance : PASS
2123 00:38:37.633075 DUTY Scan : NO K
2124 00:38:37.635705 ZQ Calibration : PASS
2125 00:38:37.639130 Jitter Meter : NO K
2126 00:38:37.639228 CBT Training : PASS
2127 00:38:37.642483 Write leveling : PASS
2128 00:38:37.646105 RX DQS gating : PASS
2129 00:38:37.646224 RX DQ/DQS(RDDQC) : PASS
2130 00:38:37.649877 TX DQ/DQS : PASS
2131 00:38:37.649962 RX DATLAT : PASS
2132 00:38:37.652666 RX DQ/DQS(Engine): PASS
2133 00:38:37.655886 TX OE : NO K
2134 00:38:37.655971 All Pass.
2135 00:38:37.656037
2136 00:38:37.656113 CH 1, Rank 1
2137 00:38:37.659207 SW Impedance : PASS
2138 00:38:37.662497 DUTY Scan : NO K
2139 00:38:37.662583 ZQ Calibration : PASS
2140 00:38:37.666505 Jitter Meter : NO K
2141 00:38:37.669833 CBT Training : PASS
2142 00:38:37.669918 Write leveling : PASS
2143 00:38:37.672863 RX DQS gating : PASS
2144 00:38:37.676497 RX DQ/DQS(RDDQC) : PASS
2145 00:38:37.676585 TX DQ/DQS : PASS
2146 00:38:37.679922 RX DATLAT : PASS
2147 00:38:37.682613 RX DQ/DQS(Engine): PASS
2148 00:38:37.682703 TX OE : NO K
2149 00:38:37.682772 All Pass.
2150 00:38:37.687262
2151 00:38:37.687354 DramC Write-DBI off
2152 00:38:37.689461 PER_BANK_REFRESH: Hybrid Mode
2153 00:38:37.689549 TX_TRACKING: ON
2154 00:38:37.693523 [GetDramInforAfterCalByMRR] Vendor 6.
2155 00:38:37.695862 [GetDramInforAfterCalByMRR] Revision 606.
2156 00:38:37.703207 [GetDramInforAfterCalByMRR] Revision 2 0.
2157 00:38:37.703350 MR0 0x3b3b
2158 00:38:37.703450 MR8 0x5151
2159 00:38:37.706354 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 00:38:37.706460
2161 00:38:37.709860 MR0 0x3b3b
2162 00:38:37.709941 MR8 0x5151
2163 00:38:37.712866 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 00:38:37.712985
2165 00:38:37.722475 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2166 00:38:37.726094 [FAST_K] Save calibration result to emmc
2167 00:38:37.729787 [FAST_K] Save calibration result to emmc
2168 00:38:37.733571 dram_init: config_dvfs: 1
2169 00:38:37.736100 dramc_set_vcore_voltage set vcore to 662500
2170 00:38:37.736176 Read voltage for 1200, 2
2171 00:38:37.741115 Vio18 = 0
2172 00:38:37.741197 Vcore = 662500
2173 00:38:37.741262 Vdram = 0
2174 00:38:37.743156 Vddq = 0
2175 00:38:37.743228 Vmddr = 0
2176 00:38:37.746306 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2177 00:38:37.753242 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2178 00:38:37.757163 MEM_TYPE=3, freq_sel=15
2179 00:38:37.759858 sv_algorithm_assistance_LP4_1600
2180 00:38:37.763280 ============ PULL DRAM RESETB DOWN ============
2181 00:38:37.766262 ========== PULL DRAM RESETB DOWN end =========
2182 00:38:37.770447 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 00:38:37.773571 ===================================
2184 00:38:37.776910 LPDDR4 DRAM CONFIGURATION
2185 00:38:37.779824 ===================================
2186 00:38:37.783165 EX_ROW_EN[0] = 0x0
2187 00:38:37.783270 EX_ROW_EN[1] = 0x0
2188 00:38:37.786561 LP4Y_EN = 0x0
2189 00:38:37.786663 WORK_FSP = 0x0
2190 00:38:37.790862 WL = 0x4
2191 00:38:37.790970 RL = 0x4
2192 00:38:37.794629 BL = 0x2
2193 00:38:37.794733 RPST = 0x0
2194 00:38:37.799780 RD_PRE = 0x0
2195 00:38:37.799888 WR_PRE = 0x1
2196 00:38:37.800816 WR_PST = 0x0
2197 00:38:37.800930 DBI_WR = 0x0
2198 00:38:37.803380 DBI_RD = 0x0
2199 00:38:37.803482 OTF = 0x1
2200 00:38:37.806986 ===================================
2201 00:38:37.810908 ===================================
2202 00:38:37.813773 ANA top config
2203 00:38:37.816677 ===================================
2204 00:38:37.820098 DLL_ASYNC_EN = 0
2205 00:38:37.820184 ALL_SLAVE_EN = 0
2206 00:38:37.823486 NEW_RANK_MODE = 1
2207 00:38:37.827356 DLL_IDLE_MODE = 1
2208 00:38:37.830144 LP45_APHY_COMB_EN = 1
2209 00:38:37.830230 TX_ODT_DIS = 1
2210 00:38:37.833357 NEW_8X_MODE = 1
2211 00:38:37.837142 ===================================
2212 00:38:37.840235 ===================================
2213 00:38:37.843606 data_rate = 2400
2214 00:38:37.847161 CKR = 1
2215 00:38:37.850912 DQ_P2S_RATIO = 8
2216 00:38:37.853827 ===================================
2217 00:38:37.857223 CA_P2S_RATIO = 8
2218 00:38:37.857297 DQ_CA_OPEN = 0
2219 00:38:37.860488 DQ_SEMI_OPEN = 0
2220 00:38:37.864244 CA_SEMI_OPEN = 0
2221 00:38:37.867210 CA_FULL_RATE = 0
2222 00:38:37.870221 DQ_CKDIV4_EN = 0
2223 00:38:37.870321 CA_CKDIV4_EN = 0
2224 00:38:37.873606 CA_PREDIV_EN = 0
2225 00:38:37.877438 PH8_DLY = 17
2226 00:38:37.880529 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2227 00:38:37.883951 DQ_AAMCK_DIV = 4
2228 00:38:37.886973 CA_AAMCK_DIV = 4
2229 00:38:37.887073 CA_ADMCK_DIV = 4
2230 00:38:37.890710 DQ_TRACK_CA_EN = 0
2231 00:38:37.894620 CA_PICK = 1200
2232 00:38:37.897232 CA_MCKIO = 1200
2233 00:38:37.900856 MCKIO_SEMI = 0
2234 00:38:37.904184 PLL_FREQ = 2366
2235 00:38:37.907493 DQ_UI_PI_RATIO = 32
2236 00:38:37.907568 CA_UI_PI_RATIO = 0
2237 00:38:37.910967 ===================================
2238 00:38:37.914302 ===================================
2239 00:38:37.917388 memory_type:LPDDR4
2240 00:38:37.921084 GP_NUM : 10
2241 00:38:37.921160 SRAM_EN : 1
2242 00:38:37.924303 MD32_EN : 0
2243 00:38:37.927522 ===================================
2244 00:38:37.930838 [ANA_INIT] >>>>>>>>>>>>>>
2245 00:38:37.930913 <<<<<< [CONFIGURE PHASE]: ANA_TX
2246 00:38:37.934018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2247 00:38:37.937400 ===================================
2248 00:38:37.940682 data_rate = 2400,PCW = 0X5b00
2249 00:38:37.945374 ===================================
2250 00:38:37.947569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2251 00:38:37.954009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 00:38:37.961041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 00:38:37.964121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2254 00:38:37.967718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2255 00:38:37.970862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2256 00:38:37.974036 [ANA_INIT] flow start
2257 00:38:37.974110 [ANA_INIT] PLL >>>>>>>>
2258 00:38:37.977606 [ANA_INIT] PLL <<<<<<<<
2259 00:38:37.980727 [ANA_INIT] MIDPI >>>>>>>>
2260 00:38:37.980805 [ANA_INIT] MIDPI <<<<<<<<
2261 00:38:37.984252 [ANA_INIT] DLL >>>>>>>>
2262 00:38:37.987323 [ANA_INIT] DLL <<<<<<<<
2263 00:38:37.987423 [ANA_INIT] flow end
2264 00:38:37.994112 ============ LP4 DIFF to SE enter ============
2265 00:38:37.997571 ============ LP4 DIFF to SE exit ============
2266 00:38:37.997674 [ANA_INIT] <<<<<<<<<<<<<
2267 00:38:38.001101 [Flow] Enable top DCM control >>>>>
2268 00:38:38.004202 [Flow] Enable top DCM control <<<<<
2269 00:38:38.007847 Enable DLL master slave shuffle
2270 00:38:38.014907 ==============================================================
2271 00:38:38.017675 Gating Mode config
2272 00:38:38.020780 ==============================================================
2273 00:38:38.024342 Config description:
2274 00:38:38.034575 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2275 00:38:38.041196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2276 00:38:38.044421 SELPH_MODE 0: By rank 1: By Phase
2277 00:38:38.051675 ==============================================================
2278 00:38:38.054246 GAT_TRACK_EN = 1
2279 00:38:38.054324 RX_GATING_MODE = 2
2280 00:38:38.057648 RX_GATING_TRACK_MODE = 2
2281 00:38:38.061552 SELPH_MODE = 1
2282 00:38:38.064441 PICG_EARLY_EN = 1
2283 00:38:38.067822 VALID_LAT_VALUE = 1
2284 00:38:38.074746 ==============================================================
2285 00:38:38.077892 Enter into Gating configuration >>>>
2286 00:38:38.081317 Exit from Gating configuration <<<<
2287 00:38:38.084322 Enter into DVFS_PRE_config >>>>>
2288 00:38:38.095254 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2289 00:38:38.098830 Exit from DVFS_PRE_config <<<<<
2290 00:38:38.101598 Enter into PICG configuration >>>>
2291 00:38:38.104696 Exit from PICG configuration <<<<
2292 00:38:38.108148 [RX_INPUT] configuration >>>>>
2293 00:38:38.108222 [RX_INPUT] configuration <<<<<
2294 00:38:38.114847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2295 00:38:38.121484 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2296 00:38:38.125325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 00:38:38.131545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 00:38:38.138104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 00:38:38.144854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 00:38:38.148341 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2301 00:38:38.151715 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2302 00:38:38.158282 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2303 00:38:38.162258 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2304 00:38:38.164721 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2305 00:38:38.168268 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 00:38:38.171866 ===================================
2307 00:38:38.175079 LPDDR4 DRAM CONFIGURATION
2308 00:38:38.178341 ===================================
2309 00:38:38.181639 EX_ROW_EN[0] = 0x0
2310 00:38:38.181728 EX_ROW_EN[1] = 0x0
2311 00:38:38.184898 LP4Y_EN = 0x0
2312 00:38:38.185005 WORK_FSP = 0x0
2313 00:38:38.188389 WL = 0x4
2314 00:38:38.188462 RL = 0x4
2315 00:38:38.191972 BL = 0x2
2316 00:38:38.192076 RPST = 0x0
2317 00:38:38.195134 RD_PRE = 0x0
2318 00:38:38.195236 WR_PRE = 0x1
2319 00:38:38.198664 WR_PST = 0x0
2320 00:38:38.198768 DBI_WR = 0x0
2321 00:38:38.201648 DBI_RD = 0x0
2322 00:38:38.201725 OTF = 0x1
2323 00:38:38.205531 ===================================
2324 00:38:38.212234 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2325 00:38:38.215265 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2326 00:38:38.218702 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 00:38:38.222014 ===================================
2328 00:38:38.225537 LPDDR4 DRAM CONFIGURATION
2329 00:38:38.228317 ===================================
2330 00:38:38.228404 EX_ROW_EN[0] = 0x10
2331 00:38:38.231977 EX_ROW_EN[1] = 0x0
2332 00:38:38.235340 LP4Y_EN = 0x0
2333 00:38:38.235422 WORK_FSP = 0x0
2334 00:38:38.238944 WL = 0x4
2335 00:38:38.239025 RL = 0x4
2336 00:38:38.242213 BL = 0x2
2337 00:38:38.242295 RPST = 0x0
2338 00:38:38.245672 RD_PRE = 0x0
2339 00:38:38.245753 WR_PRE = 0x1
2340 00:38:38.249570 WR_PST = 0x0
2341 00:38:38.249653 DBI_WR = 0x0
2342 00:38:38.252105 DBI_RD = 0x0
2343 00:38:38.252186 OTF = 0x1
2344 00:38:38.255634 ===================================
2345 00:38:38.262628 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2346 00:38:38.262712 ==
2347 00:38:38.265714 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 00:38:38.268920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2349 00:38:38.269027 ==
2350 00:38:38.272309 [Duty_Offset_Calibration]
2351 00:38:38.275259 B0:2 B1:-1 CA:1
2352 00:38:38.275341
2353 00:38:38.278963 [DutyScan_Calibration_Flow] k_type=0
2354 00:38:38.286746
2355 00:38:38.286833 ==CLK 0==
2356 00:38:38.289537 Final CLK duty delay cell = -4
2357 00:38:38.292837 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2358 00:38:38.296947 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2359 00:38:38.299459 [-4] AVG Duty = 4953%(X100)
2360 00:38:38.299568
2361 00:38:38.302855 CH0 CLK Duty spec in!! Max-Min= 156%
2362 00:38:38.306200 [DutyScan_Calibration_Flow] ====Done====
2363 00:38:38.306283
2364 00:38:38.310042 [DutyScan_Calibration_Flow] k_type=1
2365 00:38:38.324210
2366 00:38:38.324313 ==DQS 0 ==
2367 00:38:38.327601 Final DQS duty delay cell = -4
2368 00:38:38.330944 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2369 00:38:38.334630 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2370 00:38:38.337941 [-4] AVG Duty = 4938%(X100)
2371 00:38:38.338023
2372 00:38:38.338088 ==DQS 1 ==
2373 00:38:38.341121 Final DQS duty delay cell = -4
2374 00:38:38.344316 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2375 00:38:38.347807 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2376 00:38:38.351184 [-4] AVG Duty = 5046%(X100)
2377 00:38:38.351322
2378 00:38:38.355003 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2379 00:38:38.355086
2380 00:38:38.357859 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2381 00:38:38.362210 [DutyScan_Calibration_Flow] ====Done====
2382 00:38:38.362292
2383 00:38:38.364719 [DutyScan_Calibration_Flow] k_type=3
2384 00:38:38.381904
2385 00:38:38.382005 ==DQM 0 ==
2386 00:38:38.385317 Final DQM duty delay cell = 0
2387 00:38:38.388203 [0] MAX Duty = 5000%(X100), DQS PI = 46
2388 00:38:38.391466 [0] MIN Duty = 4907%(X100), DQS PI = 2
2389 00:38:38.391549 [0] AVG Duty = 4953%(X100)
2390 00:38:38.394934
2391 00:38:38.395015 ==DQM 1 ==
2392 00:38:38.399005 Final DQM duty delay cell = 0
2393 00:38:38.401698 [0] MAX Duty = 5124%(X100), DQS PI = 32
2394 00:38:38.404738 [0] MIN Duty = 4969%(X100), DQS PI = 10
2395 00:38:38.404820 [0] AVG Duty = 5046%(X100)
2396 00:38:38.407872
2397 00:38:38.411164 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2398 00:38:38.411272
2399 00:38:38.414813 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2400 00:38:38.418221 [DutyScan_Calibration_Flow] ====Done====
2401 00:38:38.418308
2402 00:38:38.421766 [DutyScan_Calibration_Flow] k_type=2
2403 00:38:38.436954
2404 00:38:38.437082 ==DQ 0 ==
2405 00:38:38.440522 Final DQ duty delay cell = -4
2406 00:38:38.443615 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2407 00:38:38.447632 [-4] MIN Duty = 4875%(X100), DQS PI = 18
2408 00:38:38.447715 [-4] AVG Duty = 4968%(X100)
2409 00:38:38.450811
2410 00:38:38.450893 ==DQ 1 ==
2411 00:38:38.454615 Final DQ duty delay cell = 0
2412 00:38:38.457729 [0] MAX Duty = 5031%(X100), DQS PI = 18
2413 00:38:38.460336 [0] MIN Duty = 4907%(X100), DQS PI = 46
2414 00:38:38.460418 [0] AVG Duty = 4969%(X100)
2415 00:38:38.460483
2416 00:38:38.464241 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2417 00:38:38.467009
2418 00:38:38.470294 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2419 00:38:38.474131 [DutyScan_Calibration_Flow] ====Done====
2420 00:38:38.474214 ==
2421 00:38:38.477989 Dram Type= 6, Freq= 0, CH_1, rank 0
2422 00:38:38.480520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2423 00:38:38.480621 ==
2424 00:38:38.484067 [Duty_Offset_Calibration]
2425 00:38:38.484150 B0:1 B1:1 CA:2
2426 00:38:38.484215
2427 00:38:38.487603 [DutyScan_Calibration_Flow] k_type=0
2428 00:38:38.497475
2429 00:38:38.497564 ==CLK 0==
2430 00:38:38.500626 Final CLK duty delay cell = 0
2431 00:38:38.504236 [0] MAX Duty = 5187%(X100), DQS PI = 24
2432 00:38:38.507544 [0] MIN Duty = 4969%(X100), DQS PI = 40
2433 00:38:38.507627 [0] AVG Duty = 5078%(X100)
2434 00:38:38.510696
2435 00:38:38.510778 CH1 CLK Duty spec in!! Max-Min= 218%
2436 00:38:38.517140 [DutyScan_Calibration_Flow] ====Done====
2437 00:38:38.517231
2438 00:38:38.520199 [DutyScan_Calibration_Flow] k_type=1
2439 00:38:38.536672
2440 00:38:38.536789 ==DQS 0 ==
2441 00:38:38.540565 Final DQS duty delay cell = 0
2442 00:38:38.543500 [0] MAX Duty = 5031%(X100), DQS PI = 18
2443 00:38:38.546945 [0] MIN Duty = 4813%(X100), DQS PI = 50
2444 00:38:38.550390 [0] AVG Duty = 4922%(X100)
2445 00:38:38.550473
2446 00:38:38.550538 ==DQS 1 ==
2447 00:38:38.554215 Final DQS duty delay cell = 0
2448 00:38:38.557230 [0] MAX Duty = 5062%(X100), DQS PI = 36
2449 00:38:38.559646 [0] MIN Duty = 4875%(X100), DQS PI = 14
2450 00:38:38.565653 [0] AVG Duty = 4968%(X100)
2451 00:38:38.565738
2452 00:38:38.566985 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2453 00:38:38.567067
2454 00:38:38.570449 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2455 00:38:38.574196 [DutyScan_Calibration_Flow] ====Done====
2456 00:38:38.574279
2457 00:38:38.576441 [DutyScan_Calibration_Flow] k_type=3
2458 00:38:38.593029
2459 00:38:38.593145 ==DQM 0 ==
2460 00:38:38.596571 Final DQM duty delay cell = 0
2461 00:38:38.599679 [0] MAX Duty = 5093%(X100), DQS PI = 18
2462 00:38:38.602940 [0] MIN Duty = 4875%(X100), DQS PI = 48
2463 00:38:38.603040 [0] AVG Duty = 4984%(X100)
2464 00:38:38.606969
2465 00:38:38.607073 ==DQM 1 ==
2466 00:38:38.610651 Final DQM duty delay cell = 0
2467 00:38:38.613235 [0] MAX Duty = 5125%(X100), DQS PI = 0
2468 00:38:38.616457 [0] MIN Duty = 4938%(X100), DQS PI = 22
2469 00:38:38.616542 [0] AVG Duty = 5031%(X100)
2470 00:38:38.616627
2471 00:38:38.620053 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2472 00:38:38.623740
2473 00:38:38.627377 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2474 00:38:38.629865 [DutyScan_Calibration_Flow] ====Done====
2475 00:38:38.629950
2476 00:38:38.633359 [DutyScan_Calibration_Flow] k_type=2
2477 00:38:38.650386
2478 00:38:38.650501 ==DQ 0 ==
2479 00:38:38.653520 Final DQ duty delay cell = 0
2480 00:38:38.656405 [0] MAX Duty = 5156%(X100), DQS PI = 18
2481 00:38:38.659708 [0] MIN Duty = 4907%(X100), DQS PI = 50
2482 00:38:38.659791 [0] AVG Duty = 5031%(X100)
2483 00:38:38.659857
2484 00:38:38.662786 ==DQ 1 ==
2485 00:38:38.666217 Final DQ duty delay cell = 0
2486 00:38:38.670107 [0] MAX Duty = 5093%(X100), DQS PI = 10
2487 00:38:38.672922 [0] MIN Duty = 5031%(X100), DQS PI = 2
2488 00:38:38.673023 [0] AVG Duty = 5062%(X100)
2489 00:38:38.673119
2490 00:38:38.677219 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2491 00:38:38.677303
2492 00:38:38.680003 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2493 00:38:38.686316 [DutyScan_Calibration_Flow] ====Done====
2494 00:38:38.689640 nWR fixed to 30
2495 00:38:38.689725 [ModeRegInit_LP4] CH0 RK0
2496 00:38:38.693113 [ModeRegInit_LP4] CH0 RK1
2497 00:38:38.696731 [ModeRegInit_LP4] CH1 RK0
2498 00:38:38.696843 [ModeRegInit_LP4] CH1 RK1
2499 00:38:38.699505 match AC timing 7
2500 00:38:38.703308 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2501 00:38:38.706333 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2502 00:38:38.712927 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2503 00:38:38.716823 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2504 00:38:38.722978 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2505 00:38:38.723084 ==
2506 00:38:38.726880 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 00:38:38.730086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 00:38:38.730168 ==
2509 00:38:38.733811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 00:38:38.740121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 00:38:38.749482 [CA 0] Center 40 (10~71) winsize 62
2512 00:38:38.753143 [CA 1] Center 39 (9~70) winsize 62
2513 00:38:38.756651 [CA 2] Center 36 (6~67) winsize 62
2514 00:38:38.759962 [CA 3] Center 35 (5~66) winsize 62
2515 00:38:38.762707 [CA 4] Center 34 (4~65) winsize 62
2516 00:38:38.766250 [CA 5] Center 34 (4~64) winsize 61
2517 00:38:38.766332
2518 00:38:38.769824 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 00:38:38.769907
2520 00:38:38.773545 [CATrainingPosCal] consider 1 rank data
2521 00:38:38.776201 u2DelayCellTimex100 = 270/100 ps
2522 00:38:38.779662 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2523 00:38:38.783584 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2524 00:38:38.789789 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2525 00:38:38.793140 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2526 00:38:38.796163 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2527 00:38:38.799499 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2528 00:38:38.799621
2529 00:38:38.802838 CA PerBit enable=1, Macro0, CA PI delay=34
2530 00:38:38.802920
2531 00:38:38.806616 [CBTSetCACLKResult] CA Dly = 34
2532 00:38:38.806701 CS Dly: 7 (0~38)
2533 00:38:38.806806 ==
2534 00:38:38.809780 Dram Type= 6, Freq= 0, CH_0, rank 1
2535 00:38:38.816174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 00:38:38.816258 ==
2537 00:38:38.819888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 00:38:38.826420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2539 00:38:38.835335 [CA 0] Center 39 (9~70) winsize 62
2540 00:38:38.839774 [CA 1] Center 39 (9~70) winsize 62
2541 00:38:38.842219 [CA 2] Center 36 (6~67) winsize 62
2542 00:38:38.845395 [CA 3] Center 36 (5~67) winsize 63
2543 00:38:38.849211 [CA 4] Center 34 (4~65) winsize 62
2544 00:38:38.852031 [CA 5] Center 34 (4~64) winsize 61
2545 00:38:38.852113
2546 00:38:38.855220 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 00:38:38.855302
2548 00:38:38.858570 [CATrainingPosCal] consider 2 rank data
2549 00:38:38.862678 u2DelayCellTimex100 = 270/100 ps
2550 00:38:38.865439 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2551 00:38:38.869478 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2552 00:38:38.875971 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2553 00:38:38.880014 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2554 00:38:38.882235 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2555 00:38:38.885699 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2556 00:38:38.885781
2557 00:38:38.891210 CA PerBit enable=1, Macro0, CA PI delay=34
2558 00:38:38.891293
2559 00:38:38.892559 [CBTSetCACLKResult] CA Dly = 34
2560 00:38:38.892642 CS Dly: 8 (0~41)
2561 00:38:38.892707
2562 00:38:38.896564 ----->DramcWriteLeveling(PI) begin...
2563 00:38:38.896657 ==
2564 00:38:38.899018 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 00:38:38.905849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 00:38:38.905972 ==
2567 00:38:38.909811 Write leveling (Byte 0): 31 => 31
2568 00:38:38.913381 Write leveling (Byte 1): 28 => 28
2569 00:38:38.913468 DramcWriteLeveling(PI) end<-----
2570 00:38:38.913535
2571 00:38:38.916235 ==
2572 00:38:38.919278 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 00:38:38.922759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 00:38:38.922850 ==
2575 00:38:38.926175 [Gating] SW mode calibration
2576 00:38:38.932820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2577 00:38:38.935811 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2578 00:38:38.943175 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 00:38:38.946009 0 15 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2580 00:38:38.950110 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2581 00:38:38.952833 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 00:38:38.960379 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 00:38:38.963616 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 00:38:38.966368 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 00:38:38.972896 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 00:38:38.976194 1 0 0 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
2587 00:38:38.979974 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2588 00:38:38.986300 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 00:38:38.989715 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 00:38:38.993169 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 00:38:39.000181 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 00:38:39.003080 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 00:38:39.006176 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 00:38:39.012917 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2595 00:38:39.016445 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2596 00:38:39.019721 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 00:38:39.023524 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 00:38:39.030223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 00:38:39.033507 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 00:38:39.036876 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 00:38:39.042979 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 00:38:39.046914 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2603 00:38:39.049859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 00:38:39.056517 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 00:38:39.059762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 00:38:39.063128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 00:38:39.070387 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 00:38:39.073430 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 00:38:39.076876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 00:38:39.083324 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 00:38:39.086950 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 00:38:39.089712 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 00:38:39.097959 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 00:38:39.100774 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 00:38:39.103324 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 00:38:39.106661 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 00:38:39.113461 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 00:38:39.116714 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2619 00:38:39.120104 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2620 00:38:39.123341 Total UI for P1: 0, mck2ui 16
2621 00:38:39.127870 best dqsien dly found for B0: ( 1, 4, 0)
2622 00:38:39.133384 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 00:38:39.133464 Total UI for P1: 0, mck2ui 16
2624 00:38:39.140300 best dqsien dly found for B1: ( 1, 4, 2)
2625 00:38:39.143311 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2626 00:38:39.146809 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2627 00:38:39.146913
2628 00:38:39.151189 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2629 00:38:39.153886 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2630 00:38:39.156872 [Gating] SW calibration Done
2631 00:38:39.156998 ==
2632 00:38:39.160546 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 00:38:39.163646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 00:38:39.163749 ==
2635 00:38:39.163841 RX Vref Scan: 0
2636 00:38:39.167257
2637 00:38:39.167358 RX Vref 0 -> 0, step: 1
2638 00:38:39.167453
2639 00:38:39.170522 RX Delay -40 -> 252, step: 8
2640 00:38:39.174042 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2641 00:38:39.177190 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2642 00:38:39.183814 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2643 00:38:39.189109 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2644 00:38:39.190677 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2645 00:38:39.193629 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2646 00:38:39.196914 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2647 00:38:39.203655 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2648 00:38:39.207558 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2649 00:38:39.210555 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2650 00:38:39.213926 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2651 00:38:39.217117 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2652 00:38:39.221359 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2653 00:38:39.228111 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2654 00:38:39.230692 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2655 00:38:39.234148 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2656 00:38:39.234254 ==
2657 00:38:39.237291 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 00:38:39.240409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 00:38:39.240503 ==
2660 00:38:39.244085 DQS Delay:
2661 00:38:39.244199 DQS0 = 0, DQS1 = 0
2662 00:38:39.247532 DQM Delay:
2663 00:38:39.247626 DQM0 = 115, DQM1 = 106
2664 00:38:39.250880 DQ Delay:
2665 00:38:39.254978 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2666 00:38:39.257128 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2667 00:38:39.260574 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2668 00:38:39.264018 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2669 00:38:39.264128
2670 00:38:39.264195
2671 00:38:39.264256 ==
2672 00:38:39.267973 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 00:38:39.271764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 00:38:39.271869 ==
2675 00:38:39.271936
2676 00:38:39.271997
2677 00:38:39.275087 TX Vref Scan disable
2678 00:38:39.275170 == TX Byte 0 ==
2679 00:38:39.281249 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2680 00:38:39.284771 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2681 00:38:39.284870 == TX Byte 1 ==
2682 00:38:39.291128 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2683 00:38:39.294225 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2684 00:38:39.294308 ==
2685 00:38:39.297652 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 00:38:39.300800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 00:38:39.300923 ==
2688 00:38:39.314728 TX Vref=22, minBit 1, minWin=25, winSum=415
2689 00:38:39.317829 TX Vref=24, minBit 1, minWin=25, winSum=420
2690 00:38:39.321011 TX Vref=26, minBit 0, minWin=26, winSum=424
2691 00:38:39.324397 TX Vref=28, minBit 0, minWin=26, winSum=432
2692 00:38:39.327267 TX Vref=30, minBit 1, minWin=26, winSum=434
2693 00:38:39.330809 TX Vref=32, minBit 0, minWin=26, winSum=430
2694 00:38:39.338475 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
2695 00:38:39.338561
2696 00:38:39.341937 Final TX Range 1 Vref 30
2697 00:38:39.342020
2698 00:38:39.342085 ==
2699 00:38:39.344238 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 00:38:39.347697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 00:38:39.347781 ==
2702 00:38:39.347846
2703 00:38:39.347907
2704 00:38:39.351018 TX Vref Scan disable
2705 00:38:39.354615 == TX Byte 0 ==
2706 00:38:39.358617 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2707 00:38:39.361110 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2708 00:38:39.364766 == TX Byte 1 ==
2709 00:38:39.368007 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2710 00:38:39.371073 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2711 00:38:39.371156
2712 00:38:39.374330 [DATLAT]
2713 00:38:39.374412 Freq=1200, CH0 RK0
2714 00:38:39.374478
2715 00:38:39.378018 DATLAT Default: 0xd
2716 00:38:39.378099 0, 0xFFFF, sum = 0
2717 00:38:39.381464 1, 0xFFFF, sum = 0
2718 00:38:39.381548 2, 0xFFFF, sum = 0
2719 00:38:39.384061 3, 0xFFFF, sum = 0
2720 00:38:39.384162 4, 0xFFFF, sum = 0
2721 00:38:39.387935 5, 0xFFFF, sum = 0
2722 00:38:39.388019 6, 0xFFFF, sum = 0
2723 00:38:39.391865 7, 0xFFFF, sum = 0
2724 00:38:39.391948 8, 0xFFFF, sum = 0
2725 00:38:39.394327 9, 0xFFFF, sum = 0
2726 00:38:39.394411 10, 0xFFFF, sum = 0
2727 00:38:39.397539 11, 0xFFFF, sum = 0
2728 00:38:39.397622 12, 0x0, sum = 1
2729 00:38:39.401512 13, 0x0, sum = 2
2730 00:38:39.401596 14, 0x0, sum = 3
2731 00:38:39.404168 15, 0x0, sum = 4
2732 00:38:39.404251 best_step = 13
2733 00:38:39.404348
2734 00:38:39.404409 ==
2735 00:38:39.408231 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 00:38:39.414986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 00:38:39.415071 ==
2738 00:38:39.415136 RX Vref Scan: 1
2739 00:38:39.415197
2740 00:38:39.418215 Set Vref Range= 32 -> 127
2741 00:38:39.418296
2742 00:38:39.421936 RX Vref 32 -> 127, step: 1
2743 00:38:39.422019
2744 00:38:39.422084 RX Delay -21 -> 252, step: 4
2745 00:38:39.422145
2746 00:38:39.424349 Set Vref, RX VrefLevel [Byte0]: 32
2747 00:38:39.428114 [Byte1]: 32
2748 00:38:39.432841
2749 00:38:39.432940 Set Vref, RX VrefLevel [Byte0]: 33
2750 00:38:39.435646 [Byte1]: 33
2751 00:38:39.440204
2752 00:38:39.440285 Set Vref, RX VrefLevel [Byte0]: 34
2753 00:38:39.443869 [Byte1]: 34
2754 00:38:39.448559
2755 00:38:39.448641 Set Vref, RX VrefLevel [Byte0]: 35
2756 00:38:39.451322 [Byte1]: 35
2757 00:38:39.456142
2758 00:38:39.456224 Set Vref, RX VrefLevel [Byte0]: 36
2759 00:38:39.459897 [Byte1]: 36
2760 00:38:39.463919
2761 00:38:39.464000 Set Vref, RX VrefLevel [Byte0]: 37
2762 00:38:39.467307 [Byte1]: 37
2763 00:38:39.471823
2764 00:38:39.471906 Set Vref, RX VrefLevel [Byte0]: 38
2765 00:38:39.475355 [Byte1]: 38
2766 00:38:39.479676
2767 00:38:39.479789 Set Vref, RX VrefLevel [Byte0]: 39
2768 00:38:39.483165 [Byte1]: 39
2769 00:38:39.487551
2770 00:38:39.487633 Set Vref, RX VrefLevel [Byte0]: 40
2771 00:38:39.490863 [Byte1]: 40
2772 00:38:39.495786
2773 00:38:39.495869 Set Vref, RX VrefLevel [Byte0]: 41
2774 00:38:39.499352 [Byte1]: 41
2775 00:38:39.504414
2776 00:38:39.504498 Set Vref, RX VrefLevel [Byte0]: 42
2777 00:38:39.507154 [Byte1]: 42
2778 00:38:39.512425
2779 00:38:39.512508 Set Vref, RX VrefLevel [Byte0]: 43
2780 00:38:39.514730 [Byte1]: 43
2781 00:38:39.519368
2782 00:38:39.519450 Set Vref, RX VrefLevel [Byte0]: 44
2783 00:38:39.522887 [Byte1]: 44
2784 00:38:39.527481
2785 00:38:39.527563 Set Vref, RX VrefLevel [Byte0]: 45
2786 00:38:39.531367 [Byte1]: 45
2787 00:38:39.536059
2788 00:38:39.536140 Set Vref, RX VrefLevel [Byte0]: 46
2789 00:38:39.539994 [Byte1]: 46
2790 00:38:39.544242
2791 00:38:39.544325 Set Vref, RX VrefLevel [Byte0]: 47
2792 00:38:39.546393 [Byte1]: 47
2793 00:38:39.551502
2794 00:38:39.551583 Set Vref, RX VrefLevel [Byte0]: 48
2795 00:38:39.554747 [Byte1]: 48
2796 00:38:39.559302
2797 00:38:39.559384 Set Vref, RX VrefLevel [Byte0]: 49
2798 00:38:39.562737 [Byte1]: 49
2799 00:38:39.566961
2800 00:38:39.567118 Set Vref, RX VrefLevel [Byte0]: 50
2801 00:38:39.570026 [Byte1]: 50
2802 00:38:39.574663
2803 00:38:39.574747 Set Vref, RX VrefLevel [Byte0]: 51
2804 00:38:39.578413 [Byte1]: 51
2805 00:38:39.582897
2806 00:38:39.583001 Set Vref, RX VrefLevel [Byte0]: 52
2807 00:38:39.586525 [Byte1]: 52
2808 00:38:39.590921
2809 00:38:39.591074 Set Vref, RX VrefLevel [Byte0]: 53
2810 00:38:39.594305 [Byte1]: 53
2811 00:38:39.598915
2812 00:38:39.599031 Set Vref, RX VrefLevel [Byte0]: 54
2813 00:38:39.601921 [Byte1]: 54
2814 00:38:39.606686
2815 00:38:39.606805 Set Vref, RX VrefLevel [Byte0]: 55
2816 00:38:39.610339 [Byte1]: 55
2817 00:38:39.614622
2818 00:38:39.614707 Set Vref, RX VrefLevel [Byte0]: 56
2819 00:38:39.618059 [Byte1]: 56
2820 00:38:39.622822
2821 00:38:39.622903 Set Vref, RX VrefLevel [Byte0]: 57
2822 00:38:39.625821 [Byte1]: 57
2823 00:38:39.630294
2824 00:38:39.630376 Set Vref, RX VrefLevel [Byte0]: 58
2825 00:38:39.633904 [Byte1]: 58
2826 00:38:39.638260
2827 00:38:39.638342 Set Vref, RX VrefLevel [Byte0]: 59
2828 00:38:39.641518 [Byte1]: 59
2829 00:38:39.646599
2830 00:38:39.646682 Set Vref, RX VrefLevel [Byte0]: 60
2831 00:38:39.649725 [Byte1]: 60
2832 00:38:39.654460
2833 00:38:39.654542 Set Vref, RX VrefLevel [Byte0]: 61
2834 00:38:39.657722 [Byte1]: 61
2835 00:38:39.661962
2836 00:38:39.662043 Set Vref, RX VrefLevel [Byte0]: 62
2837 00:38:39.665516 [Byte1]: 62
2838 00:38:39.669968
2839 00:38:39.670049 Set Vref, RX VrefLevel [Byte0]: 63
2840 00:38:39.673675 [Byte1]: 63
2841 00:38:39.678007
2842 00:38:39.678088 Set Vref, RX VrefLevel [Byte0]: 64
2843 00:38:39.680962 [Byte1]: 64
2844 00:38:39.685818
2845 00:38:39.685900 Set Vref, RX VrefLevel [Byte0]: 65
2846 00:38:39.689119 [Byte1]: 65
2847 00:38:39.693863
2848 00:38:39.693944 Set Vref, RX VrefLevel [Byte0]: 66
2849 00:38:39.697330 [Byte1]: 66
2850 00:38:39.702366
2851 00:38:39.702448 Set Vref, RX VrefLevel [Byte0]: 67
2852 00:38:39.705020 [Byte1]: 67
2853 00:38:39.709828
2854 00:38:39.709909 Final RX Vref Byte 0 = 53 to rank0
2855 00:38:39.713270 Final RX Vref Byte 1 = 52 to rank0
2856 00:38:39.716278 Final RX Vref Byte 0 = 53 to rank1
2857 00:38:39.719429 Final RX Vref Byte 1 = 52 to rank1==
2858 00:38:39.722959 Dram Type= 6, Freq= 0, CH_0, rank 0
2859 00:38:39.729608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 00:38:39.729691 ==
2861 00:38:39.729756 DQS Delay:
2862 00:38:39.729816 DQS0 = 0, DQS1 = 0
2863 00:38:39.733247 DQM Delay:
2864 00:38:39.733329 DQM0 = 115, DQM1 = 104
2865 00:38:39.736962 DQ Delay:
2866 00:38:39.739669 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =114
2867 00:38:39.743476 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2868 00:38:39.746974 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2869 00:38:39.749924 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2870 00:38:39.750006
2871 00:38:39.750071
2872 00:38:39.756846 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2873 00:38:39.760063 CH0 RK0: MR19=303, MR18=FEEE
2874 00:38:39.766704 CH0_RK0: MR19=0x303, MR18=0xFEEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2875 00:38:39.766786
2876 00:38:39.770235 ----->DramcWriteLeveling(PI) begin...
2877 00:38:39.770318 ==
2878 00:38:39.773104 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 00:38:39.776794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 00:38:39.776876 ==
2881 00:38:39.779858 Write leveling (Byte 0): 31 => 31
2882 00:38:39.783756 Write leveling (Byte 1): 28 => 28
2883 00:38:39.786917 DramcWriteLeveling(PI) end<-----
2884 00:38:39.786998
2885 00:38:39.787063 ==
2886 00:38:39.790114 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 00:38:39.793464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 00:38:39.793546 ==
2889 00:38:39.796503 [Gating] SW mode calibration
2890 00:38:39.803330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2891 00:38:39.810116 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2892 00:38:39.813527 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2893 00:38:39.820040 0 15 4 | B1->B0 | 2b2b 3434 | 1 0 | (0 0) (0 0)
2894 00:38:39.823444 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 00:38:39.826870 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 00:38:39.833808 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 00:38:39.837428 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 00:38:39.840801 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2899 00:38:39.844101 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2900 00:38:39.850731 1 0 0 | B1->B0 | 3030 2929 | 0 0 | (1 0) (0 0)
2901 00:38:39.853701 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 00:38:39.857511 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 00:38:39.863988 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 00:38:39.868024 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 00:38:39.870417 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 00:38:39.877816 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2907 00:38:39.880789 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2908 00:38:39.884028 1 1 0 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
2909 00:38:39.890453 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2910 00:38:39.894573 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 00:38:39.897308 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 00:38:39.900491 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 00:38:39.907317 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 00:38:39.910448 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 00:38:39.913789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2916 00:38:39.920557 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2917 00:38:39.924022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2918 00:38:39.927444 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 00:38:39.933952 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 00:38:39.937004 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 00:38:39.940471 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 00:38:39.947359 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 00:38:39.951154 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 00:38:39.954909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 00:38:39.961166 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 00:38:39.963944 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 00:38:39.967293 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 00:38:39.973942 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 00:38:39.977619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 00:38:39.981355 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 00:38:39.984383 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2932 00:38:39.990861 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2933 00:38:39.994388 Total UI for P1: 0, mck2ui 16
2934 00:38:39.997526 best dqsien dly found for B0: ( 1, 3, 26)
2935 00:38:40.000945 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 00:38:40.004353 Total UI for P1: 0, mck2ui 16
2937 00:38:40.007751 best dqsien dly found for B1: ( 1, 4, 0)
2938 00:38:40.011071 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2939 00:38:40.014538 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2940 00:38:40.014620
2941 00:38:40.018824 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2942 00:38:40.020882 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2943 00:38:40.024497 [Gating] SW calibration Done
2944 00:38:40.024579 ==
2945 00:38:40.028117 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 00:38:40.031263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 00:38:40.031345 ==
2948 00:38:40.034865 RX Vref Scan: 0
2949 00:38:40.034946
2950 00:38:40.037600 RX Vref 0 -> 0, step: 1
2951 00:38:40.037682
2952 00:38:40.037747 RX Delay -40 -> 252, step: 8
2953 00:38:40.044549 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2954 00:38:40.047609 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2955 00:38:40.051026 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2956 00:38:40.054367 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2957 00:38:40.057877 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2958 00:38:40.064497 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2959 00:38:40.068071 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2960 00:38:40.071165 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2961 00:38:40.074602 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2962 00:38:40.077845 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2963 00:38:40.084869 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2964 00:38:40.087758 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2965 00:38:40.091254 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2966 00:38:40.095473 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2967 00:38:40.098543 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2968 00:38:40.101674 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2969 00:38:40.104779 ==
2970 00:38:40.108555 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 00:38:40.111730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 00:38:40.111813 ==
2973 00:38:40.111877 DQS Delay:
2974 00:38:40.114967 DQS0 = 0, DQS1 = 0
2975 00:38:40.115049 DQM Delay:
2976 00:38:40.118779 DQM0 = 115, DQM1 = 106
2977 00:38:40.118860 DQ Delay:
2978 00:38:40.121510 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2979 00:38:40.125778 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2980 00:38:40.128535 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2981 00:38:40.132190 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2982 00:38:40.132272
2983 00:38:40.132336
2984 00:38:40.132396 ==
2985 00:38:40.134892 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 00:38:40.138370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 00:38:40.141949 ==
2988 00:38:40.142030
2989 00:38:40.142094
2990 00:38:40.142154 TX Vref Scan disable
2991 00:38:40.144972 == TX Byte 0 ==
2992 00:38:40.148463 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2993 00:38:40.151707 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2994 00:38:40.155638 == TX Byte 1 ==
2995 00:38:40.158645 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2996 00:38:40.161957 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2997 00:38:40.162039 ==
2998 00:38:40.165107 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 00:38:40.171888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 00:38:40.171970 ==
3001 00:38:40.183556 TX Vref=22, minBit 0, minWin=26, winSum=424
3002 00:38:40.186200 TX Vref=24, minBit 1, minWin=26, winSum=431
3003 00:38:40.189830 TX Vref=26, minBit 1, minWin=26, winSum=433
3004 00:38:40.192789 TX Vref=28, minBit 2, minWin=26, winSum=432
3005 00:38:40.196612 TX Vref=30, minBit 5, minWin=26, winSum=436
3006 00:38:40.199701 TX Vref=32, minBit 5, minWin=26, winSum=437
3007 00:38:40.206982 [TxChooseVref] Worse bit 5, Min win 26, Win sum 437, Final Vref 32
3008 00:38:40.207065
3009 00:38:40.210327 Final TX Range 1 Vref 32
3010 00:38:40.210482
3011 00:38:40.210627 ==
3012 00:38:40.213229 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 00:38:40.216286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 00:38:40.216397 ==
3015 00:38:40.216489
3016 00:38:40.216576
3017 00:38:40.220027 TX Vref Scan disable
3018 00:38:40.223456 == TX Byte 0 ==
3019 00:38:40.226645 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3020 00:38:40.230540 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3021 00:38:40.233171 == TX Byte 1 ==
3022 00:38:40.236447 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3023 00:38:40.240225 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3024 00:38:40.240333
3025 00:38:40.243288 [DATLAT]
3026 00:38:40.243370 Freq=1200, CH0 RK1
3027 00:38:40.243434
3028 00:38:40.246668 DATLAT Default: 0xd
3029 00:38:40.246750 0, 0xFFFF, sum = 0
3030 00:38:40.250071 1, 0xFFFF, sum = 0
3031 00:38:40.250154 2, 0xFFFF, sum = 0
3032 00:38:40.253359 3, 0xFFFF, sum = 0
3033 00:38:40.253447 4, 0xFFFF, sum = 0
3034 00:38:40.257194 5, 0xFFFF, sum = 0
3035 00:38:40.257278 6, 0xFFFF, sum = 0
3036 00:38:40.260588 7, 0xFFFF, sum = 0
3037 00:38:40.260704 8, 0xFFFF, sum = 0
3038 00:38:40.263652 9, 0xFFFF, sum = 0
3039 00:38:40.263754 10, 0xFFFF, sum = 0
3040 00:38:40.266906 11, 0xFFFF, sum = 0
3041 00:38:40.267006 12, 0x0, sum = 1
3042 00:38:40.270126 13, 0x0, sum = 2
3043 00:38:40.270225 14, 0x0, sum = 3
3044 00:38:40.273869 15, 0x0, sum = 4
3045 00:38:40.273972 best_step = 13
3046 00:38:40.274062
3047 00:38:40.274148 ==
3048 00:38:40.276878 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 00:38:40.280100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 00:38:40.283900 ==
3051 00:38:40.283985 RX Vref Scan: 0
3052 00:38:40.284053
3053 00:38:40.286919 RX Vref 0 -> 0, step: 1
3054 00:38:40.287000
3055 00:38:40.290457 RX Delay -21 -> 252, step: 4
3056 00:38:40.294072 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3057 00:38:40.297144 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3058 00:38:40.300320 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3059 00:38:40.307189 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3060 00:38:40.310228 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3061 00:38:40.314121 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3062 00:38:40.317450 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3063 00:38:40.320513 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3064 00:38:40.324354 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3065 00:38:40.330316 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3066 00:38:40.333946 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3067 00:38:40.337584 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3068 00:38:40.340745 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3069 00:38:40.344004 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3070 00:38:40.351447 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3071 00:38:40.354125 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3072 00:38:40.354198 ==
3073 00:38:40.357641 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 00:38:40.361128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 00:38:40.361210 ==
3076 00:38:40.364014 DQS Delay:
3077 00:38:40.364110 DQS0 = 0, DQS1 = 0
3078 00:38:40.364197 DQM Delay:
3079 00:38:40.367744 DQM0 = 114, DQM1 = 105
3080 00:38:40.367838 DQ Delay:
3081 00:38:40.370616 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3082 00:38:40.373956 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3083 00:38:40.378071 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3084 00:38:40.380564 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =114
3085 00:38:40.384372
3086 00:38:40.384443
3087 00:38:40.390941 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 407 ps
3088 00:38:40.393975 CH0 RK1: MR19=403, MR18=6F7
3089 00:38:40.401173 CH0_RK1: MR19=0x403, MR18=0x6F7, DQSOSC=407, MR23=63, INC=39, DEC=26
3090 00:38:40.401256 [RxdqsGatingPostProcess] freq 1200
3091 00:38:40.407616 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3092 00:38:40.410948 best DQS0 dly(2T, 0.5T) = (0, 12)
3093 00:38:40.414245 best DQS1 dly(2T, 0.5T) = (0, 12)
3094 00:38:40.417625 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3095 00:38:40.421110 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3096 00:38:40.424403 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 00:38:40.427927 best DQS1 dly(2T, 0.5T) = (0, 12)
3098 00:38:40.431095 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 00:38:40.434322 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3100 00:38:40.434405 Pre-setting of DQS Precalculation
3101 00:38:40.441194 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3102 00:38:40.441276 ==
3103 00:38:40.444908 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 00:38:40.448175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 00:38:40.448257 ==
3106 00:38:40.454771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 00:38:40.461220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3108 00:38:40.468603 [CA 0] Center 38 (8~68) winsize 61
3109 00:38:40.471477 [CA 1] Center 38 (8~68) winsize 61
3110 00:38:40.475294 [CA 2] Center 35 (5~65) winsize 61
3111 00:38:40.478159 [CA 3] Center 34 (4~65) winsize 62
3112 00:38:40.482544 [CA 4] Center 34 (4~65) winsize 62
3113 00:38:40.485262 [CA 5] Center 34 (4~64) winsize 61
3114 00:38:40.485344
3115 00:38:40.488661 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 00:38:40.488743
3117 00:38:40.491889 [CATrainingPosCal] consider 1 rank data
3118 00:38:40.495398 u2DelayCellTimex100 = 270/100 ps
3119 00:38:40.498758 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3120 00:38:40.501603 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3121 00:38:40.505179 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3122 00:38:40.512209 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3123 00:38:40.515437 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3124 00:38:40.518527 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3125 00:38:40.518610
3126 00:38:40.522227 CA PerBit enable=1, Macro0, CA PI delay=34
3127 00:38:40.522309
3128 00:38:40.526495 [CBTSetCACLKResult] CA Dly = 34
3129 00:38:40.526576 CS Dly: 6 (0~37)
3130 00:38:40.526641 ==
3131 00:38:40.528686 Dram Type= 6, Freq= 0, CH_1, rank 1
3132 00:38:40.535873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 00:38:40.535955 ==
3134 00:38:40.538620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 00:38:40.545397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3136 00:38:40.553903 [CA 0] Center 38 (8~68) winsize 61
3137 00:38:40.557103 [CA 1] Center 38 (9~68) winsize 60
3138 00:38:40.561075 [CA 2] Center 34 (4~65) winsize 62
3139 00:38:40.564116 [CA 3] Center 34 (4~65) winsize 62
3140 00:38:40.567583 [CA 4] Center 34 (4~65) winsize 62
3141 00:38:40.570806 [CA 5] Center 33 (3~64) winsize 62
3142 00:38:40.570888
3143 00:38:40.574153 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3144 00:38:40.574235
3145 00:38:40.577245 [CATrainingPosCal] consider 2 rank data
3146 00:38:40.581165 u2DelayCellTimex100 = 270/100 ps
3147 00:38:40.584269 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3148 00:38:40.587620 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3149 00:38:40.590850 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3150 00:38:40.597504 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3151 00:38:40.600711 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3152 00:38:40.604620 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3153 00:38:40.604702
3154 00:38:40.607678 CA PerBit enable=1, Macro0, CA PI delay=34
3155 00:38:40.607760
3156 00:38:40.611286 [CBTSetCACLKResult] CA Dly = 34
3157 00:38:40.611368 CS Dly: 8 (0~41)
3158 00:38:40.611432
3159 00:38:40.614445 ----->DramcWriteLeveling(PI) begin...
3160 00:38:40.614528 ==
3161 00:38:40.617680 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 00:38:40.624894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 00:38:40.624981 ==
3164 00:38:40.627797 Write leveling (Byte 0): 24 => 24
3165 00:38:40.627879 Write leveling (Byte 1): 30 => 30
3166 00:38:40.631139 DramcWriteLeveling(PI) end<-----
3167 00:38:40.631220
3168 00:38:40.634532 ==
3169 00:38:40.634614 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 00:38:40.641364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 00:38:40.641446 ==
3172 00:38:40.645130 [Gating] SW mode calibration
3173 00:38:40.650958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3174 00:38:40.654430 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3175 00:38:40.661401 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3176 00:38:40.664463 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 00:38:40.668105 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 00:38:40.671446 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 00:38:40.677942 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 00:38:40.681573 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 00:38:40.684826 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 00:38:40.692022 0 15 28 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 0)
3183 00:38:40.694765 1 0 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 0)
3184 00:38:40.698050 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 00:38:40.704929 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 00:38:40.708292 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 00:38:40.711673 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 00:38:40.718602 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 00:38:40.722033 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3190 00:38:40.725127 1 0 28 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (0 0)
3191 00:38:40.728571 1 1 0 | B1->B0 | 4040 3232 | 0 0 | (0 0) (1 1)
3192 00:38:40.735083 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 00:38:40.738256 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 00:38:40.741910 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 00:38:40.748431 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 00:38:40.751732 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 00:38:40.755260 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 00:38:40.761953 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 00:38:40.765097 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 00:38:40.768557 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 00:38:40.774963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 00:38:40.778748 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 00:38:40.781934 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 00:38:40.788354 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 00:38:40.792505 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 00:38:40.795545 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 00:38:40.802195 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 00:38:40.805589 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 00:38:40.808857 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 00:38:40.811931 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 00:38:40.819384 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 00:38:40.822097 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 00:38:40.825846 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 00:38:40.832341 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3215 00:38:40.835379 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 00:38:40.838873 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 00:38:40.842349 Total UI for P1: 0, mck2ui 16
3218 00:38:40.845784 best dqsien dly found for B0: ( 1, 3, 30)
3219 00:38:40.849423 Total UI for P1: 0, mck2ui 16
3220 00:38:40.852695 best dqsien dly found for B1: ( 1, 4, 0)
3221 00:38:40.856121 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3222 00:38:40.859558 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3223 00:38:40.859640
3224 00:38:40.862895 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3225 00:38:40.869161 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3226 00:38:40.869243 [Gating] SW calibration Done
3227 00:38:40.869308 ==
3228 00:38:40.872687 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 00:38:40.879419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 00:38:40.879501 ==
3231 00:38:40.879566 RX Vref Scan: 0
3232 00:38:40.879625
3233 00:38:40.882609 RX Vref 0 -> 0, step: 1
3234 00:38:40.882691
3235 00:38:40.885944 RX Delay -40 -> 252, step: 8
3236 00:38:40.889650 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3237 00:38:40.893187 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3238 00:38:40.896436 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3239 00:38:40.899723 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3240 00:38:40.906299 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3241 00:38:40.909405 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3242 00:38:40.913162 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3243 00:38:40.916092 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3244 00:38:40.919954 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3245 00:38:40.923013 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3246 00:38:40.929692 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3247 00:38:40.933543 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3248 00:38:40.937008 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3249 00:38:40.939719 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3250 00:38:40.943078 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3251 00:38:40.950092 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3252 00:38:40.950174 ==
3253 00:38:40.953307 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 00:38:40.956852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 00:38:40.956935 ==
3256 00:38:40.957005 DQS Delay:
3257 00:38:40.960723 DQS0 = 0, DQS1 = 0
3258 00:38:40.960805 DQM Delay:
3259 00:38:40.963433 DQM0 = 116, DQM1 = 109
3260 00:38:40.963515 DQ Delay:
3261 00:38:40.966630 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3262 00:38:40.970235 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3263 00:38:40.973199 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3264 00:38:40.977493 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3265 00:38:40.977577
3266 00:38:40.977642
3267 00:38:40.980185 ==
3268 00:38:40.980266 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 00:38:40.986687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 00:38:40.986770 ==
3271 00:38:40.986834
3272 00:38:40.986894
3273 00:38:40.986951 TX Vref Scan disable
3274 00:38:40.990308 == TX Byte 0 ==
3275 00:38:40.994157 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3276 00:38:40.997315 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3277 00:38:41.000359 == TX Byte 1 ==
3278 00:38:41.003915 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3279 00:38:41.007349 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3280 00:38:41.010322 ==
3281 00:38:41.014494 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 00:38:41.017046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 00:38:41.017129 ==
3284 00:38:41.028882 TX Vref=22, minBit 3, minWin=24, winSum=406
3285 00:38:41.031888 TX Vref=24, minBit 1, minWin=25, winSum=411
3286 00:38:41.035569 TX Vref=26, minBit 0, minWin=26, winSum=418
3287 00:38:41.038861 TX Vref=28, minBit 0, minWin=26, winSum=425
3288 00:38:41.041840 TX Vref=30, minBit 13, minWin=25, winSum=425
3289 00:38:41.049130 TX Vref=32, minBit 11, minWin=25, winSum=427
3290 00:38:41.051919 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
3291 00:38:41.052001
3292 00:38:41.055573 Final TX Range 1 Vref 28
3293 00:38:41.055662
3294 00:38:41.055732 ==
3295 00:38:41.058646 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 00:38:41.062170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 00:38:41.062252 ==
3298 00:38:41.065647
3299 00:38:41.065728
3300 00:38:41.065792 TX Vref Scan disable
3301 00:38:41.068918 == TX Byte 0 ==
3302 00:38:41.072095 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3303 00:38:41.075435 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3304 00:38:41.078468 == TX Byte 1 ==
3305 00:38:41.081925 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3306 00:38:41.085429 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3307 00:38:41.085511
3308 00:38:41.088718 [DATLAT]
3309 00:38:41.088799 Freq=1200, CH1 RK0
3310 00:38:41.088864
3311 00:38:41.091934 DATLAT Default: 0xd
3312 00:38:41.092016 0, 0xFFFF, sum = 0
3313 00:38:41.095502 1, 0xFFFF, sum = 0
3314 00:38:41.095586 2, 0xFFFF, sum = 0
3315 00:38:41.098906 3, 0xFFFF, sum = 0
3316 00:38:41.098989 4, 0xFFFF, sum = 0
3317 00:38:41.102156 5, 0xFFFF, sum = 0
3318 00:38:41.102239 6, 0xFFFF, sum = 0
3319 00:38:41.105538 7, 0xFFFF, sum = 0
3320 00:38:41.105651 8, 0xFFFF, sum = 0
3321 00:38:41.108720 9, 0xFFFF, sum = 0
3322 00:38:41.112426 10, 0xFFFF, sum = 0
3323 00:38:41.112509 11, 0xFFFF, sum = 0
3324 00:38:41.115522 12, 0x0, sum = 1
3325 00:38:41.115605 13, 0x0, sum = 2
3326 00:38:41.115671 14, 0x0, sum = 3
3327 00:38:41.118888 15, 0x0, sum = 4
3328 00:38:41.118985 best_step = 13
3329 00:38:41.119050
3330 00:38:41.119110 ==
3331 00:38:41.122230 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 00:38:41.128747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 00:38:41.128832 ==
3334 00:38:41.128896 RX Vref Scan: 1
3335 00:38:41.128956
3336 00:38:41.132020 Set Vref Range= 32 -> 127
3337 00:38:41.132127
3338 00:38:41.135741 RX Vref 32 -> 127, step: 1
3339 00:38:41.135822
3340 00:38:41.138798 RX Delay -21 -> 252, step: 4
3341 00:38:41.138879
3342 00:38:41.142268 Set Vref, RX VrefLevel [Byte0]: 32
3343 00:38:41.145471 [Byte1]: 32
3344 00:38:41.145552
3345 00:38:41.148867 Set Vref, RX VrefLevel [Byte0]: 33
3346 00:38:41.152810 [Byte1]: 33
3347 00:38:41.152894
3348 00:38:41.156478 Set Vref, RX VrefLevel [Byte0]: 34
3349 00:38:41.158667 [Byte1]: 34
3350 00:38:41.162618
3351 00:38:41.162699 Set Vref, RX VrefLevel [Byte0]: 35
3352 00:38:41.166459 [Byte1]: 35
3353 00:38:41.170595
3354 00:38:41.170706 Set Vref, RX VrefLevel [Byte0]: 36
3355 00:38:41.174694 [Byte1]: 36
3356 00:38:41.179159
3357 00:38:41.179268 Set Vref, RX VrefLevel [Byte0]: 37
3358 00:38:41.182078 [Byte1]: 37
3359 00:38:41.186859
3360 00:38:41.186940 Set Vref, RX VrefLevel [Byte0]: 38
3361 00:38:41.190249 [Byte1]: 38
3362 00:38:41.194909
3363 00:38:41.194990 Set Vref, RX VrefLevel [Byte0]: 39
3364 00:38:41.198171 [Byte1]: 39
3365 00:38:41.202604
3366 00:38:41.202685 Set Vref, RX VrefLevel [Byte0]: 40
3367 00:38:41.205806 [Byte1]: 40
3368 00:38:41.210756
3369 00:38:41.210838 Set Vref, RX VrefLevel [Byte0]: 41
3370 00:38:41.213579 [Byte1]: 41
3371 00:38:41.218492
3372 00:38:41.218587 Set Vref, RX VrefLevel [Byte0]: 42
3373 00:38:41.221873 [Byte1]: 42
3374 00:38:41.226258
3375 00:38:41.226339 Set Vref, RX VrefLevel [Byte0]: 43
3376 00:38:41.229806 [Byte1]: 43
3377 00:38:41.234616
3378 00:38:41.234696 Set Vref, RX VrefLevel [Byte0]: 44
3379 00:38:41.237604 [Byte1]: 44
3380 00:38:41.242337
3381 00:38:41.242418 Set Vref, RX VrefLevel [Byte0]: 45
3382 00:38:41.245583 [Byte1]: 45
3383 00:38:41.249859
3384 00:38:41.249940 Set Vref, RX VrefLevel [Byte0]: 46
3385 00:38:41.253153 [Byte1]: 46
3386 00:38:41.257897
3387 00:38:41.257977 Set Vref, RX VrefLevel [Byte0]: 47
3388 00:38:41.264270 [Byte1]: 47
3389 00:38:41.264355
3390 00:38:41.267553 Set Vref, RX VrefLevel [Byte0]: 48
3391 00:38:41.270832 [Byte1]: 48
3392 00:38:41.270994
3393 00:38:41.274161 Set Vref, RX VrefLevel [Byte0]: 49
3394 00:38:41.277361 [Byte1]: 49
3395 00:38:41.281856
3396 00:38:41.281956 Set Vref, RX VrefLevel [Byte0]: 50
3397 00:38:41.285001 [Byte1]: 50
3398 00:38:41.289938
3399 00:38:41.290018 Set Vref, RX VrefLevel [Byte0]: 51
3400 00:38:41.293062 [Byte1]: 51
3401 00:38:41.297440
3402 00:38:41.297515 Set Vref, RX VrefLevel [Byte0]: 52
3403 00:38:41.301004 [Byte1]: 52
3404 00:38:41.305209
3405 00:38:41.305285 Set Vref, RX VrefLevel [Byte0]: 53
3406 00:38:41.308834 [Byte1]: 53
3407 00:38:41.313526
3408 00:38:41.313598 Set Vref, RX VrefLevel [Byte0]: 54
3409 00:38:41.316404 [Byte1]: 54
3410 00:38:41.321152
3411 00:38:41.321256 Set Vref, RX VrefLevel [Byte0]: 55
3412 00:38:41.325112 [Byte1]: 55
3413 00:38:41.329182
3414 00:38:41.329266 Set Vref, RX VrefLevel [Byte0]: 56
3415 00:38:41.332581 [Byte1]: 56
3416 00:38:41.337048
3417 00:38:41.337132 Set Vref, RX VrefLevel [Byte0]: 57
3418 00:38:41.340458 [Byte1]: 57
3419 00:38:41.345277
3420 00:38:41.345358 Set Vref, RX VrefLevel [Byte0]: 58
3421 00:38:41.348544 [Byte1]: 58
3422 00:38:41.352900
3423 00:38:41.353007 Set Vref, RX VrefLevel [Byte0]: 59
3424 00:38:41.356392 [Byte1]: 59
3425 00:38:41.361133
3426 00:38:41.361215 Set Vref, RX VrefLevel [Byte0]: 60
3427 00:38:41.364079 [Byte1]: 60
3428 00:38:41.369315
3429 00:38:41.369397 Set Vref, RX VrefLevel [Byte0]: 61
3430 00:38:41.371911 [Byte1]: 61
3431 00:38:41.376743
3432 00:38:41.376825 Set Vref, RX VrefLevel [Byte0]: 62
3433 00:38:41.380121 [Byte1]: 62
3434 00:38:41.384633
3435 00:38:41.384715 Set Vref, RX VrefLevel [Byte0]: 63
3436 00:38:41.388034 [Byte1]: 63
3437 00:38:41.393092
3438 00:38:41.393174 Set Vref, RX VrefLevel [Byte0]: 64
3439 00:38:41.396222 [Byte1]: 64
3440 00:38:41.400687
3441 00:38:41.400770 Set Vref, RX VrefLevel [Byte0]: 65
3442 00:38:41.404019 [Byte1]: 65
3443 00:38:41.408661
3444 00:38:41.408743 Set Vref, RX VrefLevel [Byte0]: 66
3445 00:38:41.411762 [Byte1]: 66
3446 00:38:41.416587
3447 00:38:41.416668 Set Vref, RX VrefLevel [Byte0]: 67
3448 00:38:41.419597 [Byte1]: 67
3449 00:38:41.424249
3450 00:38:41.424331 Set Vref, RX VrefLevel [Byte0]: 68
3451 00:38:41.427378 [Byte1]: 68
3452 00:38:41.432825
3453 00:38:41.432907 Set Vref, RX VrefLevel [Byte0]: 69
3454 00:38:41.435708 [Byte1]: 69
3455 00:38:41.440571
3456 00:38:41.440653 Final RX Vref Byte 0 = 56 to rank0
3457 00:38:41.443786 Final RX Vref Byte 1 = 50 to rank0
3458 00:38:41.446749 Final RX Vref Byte 0 = 56 to rank1
3459 00:38:41.450365 Final RX Vref Byte 1 = 50 to rank1==
3460 00:38:41.453521 Dram Type= 6, Freq= 0, CH_1, rank 0
3461 00:38:41.457143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 00:38:41.460234 ==
3463 00:38:41.460317 DQS Delay:
3464 00:38:41.460382 DQS0 = 0, DQS1 = 0
3465 00:38:41.463128 DQM Delay:
3466 00:38:41.463209 DQM0 = 116, DQM1 = 108
3467 00:38:41.466609 DQ Delay:
3468 00:38:41.470692 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3469 00:38:41.473535 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3470 00:38:41.477088 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =104
3471 00:38:41.480448 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3472 00:38:41.480530
3473 00:38:41.480595
3474 00:38:41.486932 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbe0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
3475 00:38:41.490239 CH1 RK0: MR19=303, MR18=FBE0
3476 00:38:41.496867 CH1_RK0: MR19=0x303, MR18=0xFBE0, DQSOSC=412, MR23=63, INC=38, DEC=25
3477 00:38:41.496950
3478 00:38:41.500222 ----->DramcWriteLeveling(PI) begin...
3479 00:38:41.500305 ==
3480 00:38:41.503669 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 00:38:41.506992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 00:38:41.507107 ==
3483 00:38:41.510579 Write leveling (Byte 0): 26 => 26
3484 00:38:41.513814 Write leveling (Byte 1): 30 => 30
3485 00:38:41.516981 DramcWriteLeveling(PI) end<-----
3486 00:38:41.517098
3487 00:38:41.517162 ==
3488 00:38:41.520607 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 00:38:41.523819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 00:38:41.527243 ==
3491 00:38:41.527424 [Gating] SW mode calibration
3492 00:38:41.534115 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3493 00:38:41.540753 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3494 00:38:41.543605 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3495 00:38:41.550573 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 00:38:41.553872 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 00:38:41.557570 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 00:38:41.564429 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 00:38:41.567405 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3500 00:38:41.570965 0 15 24 | B1->B0 | 3434 2525 | 0 0 | (0 0) (1 0)
3501 00:38:41.577610 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3502 00:38:41.580984 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3503 00:38:41.584009 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 00:38:41.594496 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 00:38:41.594602 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 00:38:41.597531 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 00:38:41.600515 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 00:38:41.607388 1 0 24 | B1->B0 | 2424 3f3f | 0 1 | (0 0) (0 0)
3509 00:38:41.610697 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3510 00:38:41.614068 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 00:38:41.621521 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 00:38:41.624395 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 00:38:41.627477 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 00:38:41.633770 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 00:38:41.637197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 00:38:41.640445 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3517 00:38:41.647514 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3518 00:38:41.650463 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 00:38:41.653636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 00:38:41.660348 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 00:38:41.663843 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 00:38:41.667053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 00:38:41.674082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 00:38:41.677035 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 00:38:41.680685 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 00:38:41.684028 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 00:38:41.690587 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 00:38:41.693790 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 00:38:41.697105 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 00:38:41.704494 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 00:38:41.707579 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 00:38:41.710795 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3533 00:38:41.717677 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3534 00:38:41.720637 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 00:38:41.724233 Total UI for P1: 0, mck2ui 16
3536 00:38:41.728923 best dqsien dly found for B0: ( 1, 3, 26)
3537 00:38:41.732095 Total UI for P1: 0, mck2ui 16
3538 00:38:41.734130 best dqsien dly found for B1: ( 1, 3, 28)
3539 00:38:41.737963 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3540 00:38:41.740857 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3541 00:38:41.740940
3542 00:38:41.744116 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3543 00:38:41.747575 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3544 00:38:41.750849 [Gating] SW calibration Done
3545 00:38:41.750931 ==
3546 00:38:41.755180 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 00:38:41.758188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 00:38:41.758271 ==
3549 00:38:41.761292 RX Vref Scan: 0
3550 00:38:41.761374
3551 00:38:41.764681 RX Vref 0 -> 0, step: 1
3552 00:38:41.764762
3553 00:38:41.764827 RX Delay -40 -> 252, step: 8
3554 00:38:41.771239 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3555 00:38:41.774748 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3556 00:38:41.777549 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3557 00:38:41.781093 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3558 00:38:41.784511 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3559 00:38:41.790770 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3560 00:38:41.794130 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3561 00:38:41.797588 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3562 00:38:41.800890 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3563 00:38:41.804241 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3564 00:38:41.807791 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3565 00:38:41.814256 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3566 00:38:41.817768 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3567 00:38:41.821482 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3568 00:38:41.824164 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3569 00:38:41.831304 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3570 00:38:41.831386 ==
3571 00:38:41.834357 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 00:38:41.837763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 00:38:41.837847 ==
3574 00:38:41.837912 DQS Delay:
3575 00:38:41.841830 DQS0 = 0, DQS1 = 0
3576 00:38:41.841911 DQM Delay:
3577 00:38:41.844890 DQM0 = 114, DQM1 = 109
3578 00:38:41.844971 DQ Delay:
3579 00:38:41.847791 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3580 00:38:41.851247 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107
3581 00:38:41.854076 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99
3582 00:38:41.857534 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
3583 00:38:41.857616
3584 00:38:41.857682
3585 00:38:41.857742 ==
3586 00:38:41.860953 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 00:38:41.867683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 00:38:41.867765 ==
3589 00:38:41.867830
3590 00:38:41.867890
3591 00:38:41.867948 TX Vref Scan disable
3592 00:38:41.871085 == TX Byte 0 ==
3593 00:38:41.874770 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 00:38:41.877993 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 00:38:41.881527 == TX Byte 1 ==
3596 00:38:41.885396 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3597 00:38:41.888054 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3598 00:38:41.891467 ==
3599 00:38:41.891549 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 00:38:41.898291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 00:38:41.898400 ==
3602 00:38:41.909203 TX Vref=22, minBit 15, minWin=24, winSum=414
3603 00:38:41.912631 TX Vref=24, minBit 2, minWin=25, winSum=421
3604 00:38:41.915995 TX Vref=26, minBit 15, minWin=25, winSum=430
3605 00:38:41.919617 TX Vref=28, minBit 2, minWin=26, winSum=431
3606 00:38:41.922540 TX Vref=30, minBit 1, minWin=26, winSum=431
3607 00:38:41.929194 TX Vref=32, minBit 2, minWin=26, winSum=431
3608 00:38:41.932745 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
3609 00:38:41.932828
3610 00:38:41.935952 Final TX Range 1 Vref 28
3611 00:38:41.936034
3612 00:38:41.936099 ==
3613 00:38:41.938902 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 00:38:41.942438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 00:38:41.942521 ==
3616 00:38:41.945776
3617 00:38:41.945860
3618 00:38:41.945925 TX Vref Scan disable
3619 00:38:41.949234 == TX Byte 0 ==
3620 00:38:41.952502 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3621 00:38:41.955586 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3622 00:38:41.959088 == TX Byte 1 ==
3623 00:38:41.962876 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3624 00:38:41.966409 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3625 00:38:41.969479
3626 00:38:41.969560 [DATLAT]
3627 00:38:41.969626 Freq=1200, CH1 RK1
3628 00:38:41.969686
3629 00:38:41.972217 DATLAT Default: 0xd
3630 00:38:41.972298 0, 0xFFFF, sum = 0
3631 00:38:41.976232 1, 0xFFFF, sum = 0
3632 00:38:41.976316 2, 0xFFFF, sum = 0
3633 00:38:41.979177 3, 0xFFFF, sum = 0
3634 00:38:41.979260 4, 0xFFFF, sum = 0
3635 00:38:41.982538 5, 0xFFFF, sum = 0
3636 00:38:41.985987 6, 0xFFFF, sum = 0
3637 00:38:41.986070 7, 0xFFFF, sum = 0
3638 00:38:41.989114 8, 0xFFFF, sum = 0
3639 00:38:41.989198 9, 0xFFFF, sum = 0
3640 00:38:41.992490 10, 0xFFFF, sum = 0
3641 00:38:41.992573 11, 0xFFFF, sum = 0
3642 00:38:41.995649 12, 0x0, sum = 1
3643 00:38:41.995732 13, 0x0, sum = 2
3644 00:38:41.999396 14, 0x0, sum = 3
3645 00:38:41.999479 15, 0x0, sum = 4
3646 00:38:41.999545 best_step = 13
3647 00:38:41.999605
3648 00:38:42.002668 ==
3649 00:38:42.002749 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 00:38:42.009043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 00:38:42.009127 ==
3652 00:38:42.009201 RX Vref Scan: 0
3653 00:38:42.009263
3654 00:38:42.012486 RX Vref 0 -> 0, step: 1
3655 00:38:42.012582
3656 00:38:42.015801 RX Delay -21 -> 252, step: 4
3657 00:38:42.019052 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3658 00:38:42.025617 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3659 00:38:42.028932 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3660 00:38:42.032531 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3661 00:38:42.035598 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3662 00:38:42.039058 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3663 00:38:42.045800 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3664 00:38:42.049073 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3665 00:38:42.052796 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3666 00:38:42.055425 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3667 00:38:42.058928 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3668 00:38:42.062076 iDelay=191, Bit 11, Center 102 (39 ~ 166) 128
3669 00:38:42.069271 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3670 00:38:42.072383 iDelay=191, Bit 13, Center 118 (51 ~ 186) 136
3671 00:38:42.075695 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3672 00:38:42.078930 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3673 00:38:42.079007 ==
3674 00:38:42.082103 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 00:38:42.089454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 00:38:42.089533 ==
3677 00:38:42.089596 DQS Delay:
3678 00:38:42.092552 DQS0 = 0, DQS1 = 0
3679 00:38:42.092622 DQM Delay:
3680 00:38:42.095798 DQM0 = 113, DQM1 = 108
3681 00:38:42.095896 DQ Delay:
3682 00:38:42.098880 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3683 00:38:42.102194 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3684 00:38:42.105453 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =102
3685 00:38:42.108790 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =116
3686 00:38:42.108890
3687 00:38:42.108986
3688 00:38:42.118728 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3689 00:38:42.118836 CH1 RK1: MR19=303, MR18=F5FD
3690 00:38:42.125091 CH1_RK1: MR19=0x303, MR18=0xF5FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3691 00:38:42.128880 [RxdqsGatingPostProcess] freq 1200
3692 00:38:42.135430 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3693 00:38:42.138907 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 00:38:42.142154 best DQS1 dly(2T, 0.5T) = (0, 12)
3695 00:38:42.145712 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 00:38:42.148876 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3697 00:38:42.148998 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 00:38:42.152561 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 00:38:42.156290 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 00:38:42.158724 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 00:38:42.162135 Pre-setting of DQS Precalculation
3702 00:38:42.168884 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3703 00:38:42.175398 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3704 00:38:42.182195 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3705 00:38:42.182300
3706 00:38:42.182391
3707 00:38:42.185819 [Calibration Summary] 2400 Mbps
3708 00:38:42.185894 CH 0, Rank 0
3709 00:38:42.188879 SW Impedance : PASS
3710 00:38:42.192739 DUTY Scan : NO K
3711 00:38:42.192810 ZQ Calibration : PASS
3712 00:38:42.196156 Jitter Meter : NO K
3713 00:38:42.199114 CBT Training : PASS
3714 00:38:42.199216 Write leveling : PASS
3715 00:38:42.202546 RX DQS gating : PASS
3716 00:38:42.202621 RX DQ/DQS(RDDQC) : PASS
3717 00:38:42.205625 TX DQ/DQS : PASS
3718 00:38:42.208725 RX DATLAT : PASS
3719 00:38:42.208827 RX DQ/DQS(Engine): PASS
3720 00:38:42.212482 TX OE : NO K
3721 00:38:42.212580 All Pass.
3722 00:38:42.212669
3723 00:38:42.215504 CH 0, Rank 1
3724 00:38:42.215577 SW Impedance : PASS
3725 00:38:42.218678 DUTY Scan : NO K
3726 00:38:42.222213 ZQ Calibration : PASS
3727 00:38:42.222295 Jitter Meter : NO K
3728 00:38:42.226020 CBT Training : PASS
3729 00:38:42.228844 Write leveling : PASS
3730 00:38:42.228926 RX DQS gating : PASS
3731 00:38:42.232609 RX DQ/DQS(RDDQC) : PASS
3732 00:38:42.235942 TX DQ/DQS : PASS
3733 00:38:42.236023 RX DATLAT : PASS
3734 00:38:42.238871 RX DQ/DQS(Engine): PASS
3735 00:38:42.242384 TX OE : NO K
3736 00:38:42.242466 All Pass.
3737 00:38:42.242531
3738 00:38:42.242591 CH 1, Rank 0
3739 00:38:42.245629 SW Impedance : PASS
3740 00:38:42.248869 DUTY Scan : NO K
3741 00:38:42.248951 ZQ Calibration : PASS
3742 00:38:42.252187 Jitter Meter : NO K
3743 00:38:42.252269 CBT Training : PASS
3744 00:38:42.255674 Write leveling : PASS
3745 00:38:42.259058 RX DQS gating : PASS
3746 00:38:42.259140 RX DQ/DQS(RDDQC) : PASS
3747 00:38:42.262106 TX DQ/DQS : PASS
3748 00:38:42.265438 RX DATLAT : PASS
3749 00:38:42.265545 RX DQ/DQS(Engine): PASS
3750 00:38:42.268914 TX OE : NO K
3751 00:38:42.269004 All Pass.
3752 00:38:42.269070
3753 00:38:42.272124 CH 1, Rank 1
3754 00:38:42.272205 SW Impedance : PASS
3755 00:38:42.275762 DUTY Scan : NO K
3756 00:38:42.278665 ZQ Calibration : PASS
3757 00:38:42.278746 Jitter Meter : NO K
3758 00:38:42.282308 CBT Training : PASS
3759 00:38:42.285552 Write leveling : PASS
3760 00:38:42.285633 RX DQS gating : PASS
3761 00:38:42.289163 RX DQ/DQS(RDDQC) : PASS
3762 00:38:42.292185 TX DQ/DQS : PASS
3763 00:38:42.292267 RX DATLAT : PASS
3764 00:38:42.295670 RX DQ/DQS(Engine): PASS
3765 00:38:42.295751 TX OE : NO K
3766 00:38:42.299096 All Pass.
3767 00:38:42.299177
3768 00:38:42.299242 DramC Write-DBI off
3769 00:38:42.302522 PER_BANK_REFRESH: Hybrid Mode
3770 00:38:42.305245 TX_TRACKING: ON
3771 00:38:42.312211 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3772 00:38:42.315440 [FAST_K] Save calibration result to emmc
3773 00:38:42.318786 dramc_set_vcore_voltage set vcore to 650000
3774 00:38:42.322189 Read voltage for 600, 5
3775 00:38:42.322271 Vio18 = 0
3776 00:38:42.325890 Vcore = 650000
3777 00:38:42.325971 Vdram = 0
3778 00:38:42.326036 Vddq = 0
3779 00:38:42.329193 Vmddr = 0
3780 00:38:42.332015 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3781 00:38:42.339307 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3782 00:38:42.339389 MEM_TYPE=3, freq_sel=19
3783 00:38:42.341995 sv_algorithm_assistance_LP4_1600
3784 00:38:42.348896 ============ PULL DRAM RESETB DOWN ============
3785 00:38:42.352529 ========== PULL DRAM RESETB DOWN end =========
3786 00:38:42.356004 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3787 00:38:42.358924 ===================================
3788 00:38:42.362348 LPDDR4 DRAM CONFIGURATION
3789 00:38:42.365393 ===================================
3790 00:38:42.368651 EX_ROW_EN[0] = 0x0
3791 00:38:42.368733 EX_ROW_EN[1] = 0x0
3792 00:38:42.372443 LP4Y_EN = 0x0
3793 00:38:42.372525 WORK_FSP = 0x0
3794 00:38:42.376060 WL = 0x2
3795 00:38:42.376142 RL = 0x2
3796 00:38:42.379034 BL = 0x2
3797 00:38:42.379116 RPST = 0x0
3798 00:38:42.382055 RD_PRE = 0x0
3799 00:38:42.382136 WR_PRE = 0x1
3800 00:38:42.385701 WR_PST = 0x0
3801 00:38:42.385782 DBI_WR = 0x0
3802 00:38:42.389096 DBI_RD = 0x0
3803 00:38:42.389178 OTF = 0x1
3804 00:38:42.392347 ===================================
3805 00:38:42.395523 ===================================
3806 00:38:42.399332 ANA top config
3807 00:38:42.403146 ===================================
3808 00:38:42.403228 DLL_ASYNC_EN = 0
3809 00:38:42.405582 ALL_SLAVE_EN = 1
3810 00:38:42.409494 NEW_RANK_MODE = 1
3811 00:38:42.412302 DLL_IDLE_MODE = 1
3812 00:38:42.415813 LP45_APHY_COMB_EN = 1
3813 00:38:42.415895 TX_ODT_DIS = 1
3814 00:38:42.418841 NEW_8X_MODE = 1
3815 00:38:42.422293 ===================================
3816 00:38:42.426011 ===================================
3817 00:38:42.428822 data_rate = 1200
3818 00:38:42.432836 CKR = 1
3819 00:38:42.435561 DQ_P2S_RATIO = 8
3820 00:38:42.439106 ===================================
3821 00:38:42.439188 CA_P2S_RATIO = 8
3822 00:38:42.442250 DQ_CA_OPEN = 0
3823 00:38:42.445420 DQ_SEMI_OPEN = 0
3824 00:38:42.449104 CA_SEMI_OPEN = 0
3825 00:38:42.452312 CA_FULL_RATE = 0
3826 00:38:42.452393 DQ_CKDIV4_EN = 1
3827 00:38:42.455512 CA_CKDIV4_EN = 1
3828 00:38:42.459486 CA_PREDIV_EN = 0
3829 00:38:42.462603 PH8_DLY = 0
3830 00:38:42.466152 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3831 00:38:42.469400 DQ_AAMCK_DIV = 4
3832 00:38:42.469482 CA_AAMCK_DIV = 4
3833 00:38:42.472282 CA_ADMCK_DIV = 4
3834 00:38:42.475985 DQ_TRACK_CA_EN = 0
3835 00:38:42.479050 CA_PICK = 600
3836 00:38:42.482645 CA_MCKIO = 600
3837 00:38:42.486309 MCKIO_SEMI = 0
3838 00:38:42.489461 PLL_FREQ = 2288
3839 00:38:42.489543 DQ_UI_PI_RATIO = 32
3840 00:38:42.492664 CA_UI_PI_RATIO = 0
3841 00:38:42.495812 ===================================
3842 00:38:42.499517 ===================================
3843 00:38:42.502365 memory_type:LPDDR4
3844 00:38:42.505858 GP_NUM : 10
3845 00:38:42.505934 SRAM_EN : 1
3846 00:38:42.508962 MD32_EN : 0
3847 00:38:42.512655 ===================================
3848 00:38:42.512756 [ANA_INIT] >>>>>>>>>>>>>>
3849 00:38:42.515979 <<<<<< [CONFIGURE PHASE]: ANA_TX
3850 00:38:42.519404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3851 00:38:42.522393 ===================================
3852 00:38:42.525622 data_rate = 1200,PCW = 0X5800
3853 00:38:42.529545 ===================================
3854 00:38:42.532357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3855 00:38:42.539166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3856 00:38:42.545830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3857 00:38:42.549497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3858 00:38:42.552351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3859 00:38:42.555872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3860 00:38:42.558963 [ANA_INIT] flow start
3861 00:38:42.559070 [ANA_INIT] PLL >>>>>>>>
3862 00:38:42.562330 [ANA_INIT] PLL <<<<<<<<
3863 00:38:42.565601 [ANA_INIT] MIDPI >>>>>>>>
3864 00:38:42.565677 [ANA_INIT] MIDPI <<<<<<<<
3865 00:38:42.569274 [ANA_INIT] DLL >>>>>>>>
3866 00:38:42.572388 [ANA_INIT] flow end
3867 00:38:42.575793 ============ LP4 DIFF to SE enter ============
3868 00:38:42.579551 ============ LP4 DIFF to SE exit ============
3869 00:38:42.582608 [ANA_INIT] <<<<<<<<<<<<<
3870 00:38:42.586075 [Flow] Enable top DCM control >>>>>
3871 00:38:42.588910 [Flow] Enable top DCM control <<<<<
3872 00:38:42.592267 Enable DLL master slave shuffle
3873 00:38:42.595544 ==============================================================
3874 00:38:42.599051 Gating Mode config
3875 00:38:42.605433 ==============================================================
3876 00:38:42.605511 Config description:
3877 00:38:42.616447 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3878 00:38:42.622549 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3879 00:38:42.626158 SELPH_MODE 0: By rank 1: By Phase
3880 00:38:42.632449 ==============================================================
3881 00:38:42.636140 GAT_TRACK_EN = 1
3882 00:38:42.639879 RX_GATING_MODE = 2
3883 00:38:42.642694 RX_GATING_TRACK_MODE = 2
3884 00:38:42.645971 SELPH_MODE = 1
3885 00:38:42.649355 PICG_EARLY_EN = 1
3886 00:38:42.649431 VALID_LAT_VALUE = 1
3887 00:38:42.656241 ==============================================================
3888 00:38:42.659411 Enter into Gating configuration >>>>
3889 00:38:42.662441 Exit from Gating configuration <<<<
3890 00:38:42.666386 Enter into DVFS_PRE_config >>>>>
3891 00:38:42.676496 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3892 00:38:42.679098 Exit from DVFS_PRE_config <<<<<
3893 00:38:42.682565 Enter into PICG configuration >>>>
3894 00:38:42.685739 Exit from PICG configuration <<<<
3895 00:38:42.689545 [RX_INPUT] configuration >>>>>
3896 00:38:42.692495 [RX_INPUT] configuration <<<<<
3897 00:38:42.696571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3898 00:38:42.702816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3899 00:38:42.709310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 00:38:42.715948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 00:38:42.723173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 00:38:42.726544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 00:38:42.729423 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3904 00:38:42.736514 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3905 00:38:42.739305 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3906 00:38:42.743126 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3907 00:38:42.746536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3908 00:38:42.753064 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 00:38:42.755827 ===================================
3910 00:38:42.759535 LPDDR4 DRAM CONFIGURATION
3911 00:38:42.759623 ===================================
3912 00:38:42.763017 EX_ROW_EN[0] = 0x0
3913 00:38:42.765985 EX_ROW_EN[1] = 0x0
3914 00:38:42.766056 LP4Y_EN = 0x0
3915 00:38:42.769622 WORK_FSP = 0x0
3916 00:38:42.769691 WL = 0x2
3917 00:38:42.773035 RL = 0x2
3918 00:38:42.773131 BL = 0x2
3919 00:38:42.776434 RPST = 0x0
3920 00:38:42.776532 RD_PRE = 0x0
3921 00:38:42.779749 WR_PRE = 0x1
3922 00:38:42.779824 WR_PST = 0x0
3923 00:38:42.782813 DBI_WR = 0x0
3924 00:38:42.782882 DBI_RD = 0x0
3925 00:38:42.786128 OTF = 0x1
3926 00:38:42.789339 ===================================
3927 00:38:42.792809 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3928 00:38:42.796156 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3929 00:38:42.803635 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 00:38:42.806482 ===================================
3931 00:38:42.806559 LPDDR4 DRAM CONFIGURATION
3932 00:38:42.809823 ===================================
3933 00:38:42.812818 EX_ROW_EN[0] = 0x10
3934 00:38:42.816113 EX_ROW_EN[1] = 0x0
3935 00:38:42.816184 LP4Y_EN = 0x0
3936 00:38:42.819606 WORK_FSP = 0x0
3937 00:38:42.819681 WL = 0x2
3938 00:38:42.823148 RL = 0x2
3939 00:38:42.823221 BL = 0x2
3940 00:38:42.826185 RPST = 0x0
3941 00:38:42.826255 RD_PRE = 0x0
3942 00:38:42.829321 WR_PRE = 0x1
3943 00:38:42.829421 WR_PST = 0x0
3944 00:38:42.833366 DBI_WR = 0x0
3945 00:38:42.833440 DBI_RD = 0x0
3946 00:38:42.835993 OTF = 0x1
3947 00:38:42.839366 ===================================
3948 00:38:42.846197 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3949 00:38:42.849475 nWR fixed to 30
3950 00:38:42.849577 [ModeRegInit_LP4] CH0 RK0
3951 00:38:42.853283 [ModeRegInit_LP4] CH0 RK1
3952 00:38:42.855959 [ModeRegInit_LP4] CH1 RK0
3953 00:38:42.856032 [ModeRegInit_LP4] CH1 RK1
3954 00:38:42.859595 match AC timing 17
3955 00:38:42.862857 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3956 00:38:42.866318 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3957 00:38:42.872906 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3958 00:38:42.876396 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3959 00:38:42.883708 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3960 00:38:42.883808 ==
3961 00:38:42.886083 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 00:38:42.889733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 00:38:42.889809 ==
3964 00:38:42.896180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 00:38:42.899704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3966 00:38:42.904051 [CA 0] Center 36 (6~67) winsize 62
3967 00:38:42.908670 [CA 1] Center 36 (6~66) winsize 61
3968 00:38:42.910665 [CA 2] Center 34 (4~65) winsize 62
3969 00:38:42.914119 [CA 3] Center 34 (4~64) winsize 61
3970 00:38:42.917079 [CA 4] Center 33 (3~64) winsize 62
3971 00:38:42.920836 [CA 5] Center 33 (3~64) winsize 62
3972 00:38:42.920959
3973 00:38:42.923920 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3974 00:38:42.924005
3975 00:38:42.927167 [CATrainingPosCal] consider 1 rank data
3976 00:38:42.930560 u2DelayCellTimex100 = 270/100 ps
3977 00:38:42.933694 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3978 00:38:42.936890 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3979 00:38:42.944005 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 00:38:42.946780 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3981 00:38:42.950840 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 00:38:42.953518 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 00:38:42.953650
3984 00:38:42.957779 CA PerBit enable=1, Macro0, CA PI delay=33
3985 00:38:42.957862
3986 00:38:42.960211 [CBTSetCACLKResult] CA Dly = 33
3987 00:38:42.960319 CS Dly: 5 (0~36)
3988 00:38:42.964202 ==
3989 00:38:42.964327 Dram Type= 6, Freq= 0, CH_0, rank 1
3990 00:38:42.970407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 00:38:42.970537 ==
3992 00:38:42.973564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 00:38:42.980722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3994 00:38:42.983964 [CA 0] Center 36 (6~66) winsize 61
3995 00:38:42.987364 [CA 1] Center 36 (6~66) winsize 61
3996 00:38:42.990379 [CA 2] Center 34 (4~65) winsize 62
3997 00:38:42.994008 [CA 3] Center 34 (4~64) winsize 61
3998 00:38:42.997294 [CA 4] Center 33 (3~64) winsize 62
3999 00:38:43.000603 [CA 5] Center 33 (3~64) winsize 62
4000 00:38:43.000715
4001 00:38:43.003971 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4002 00:38:43.004086
4003 00:38:43.007393 [CATrainingPosCal] consider 2 rank data
4004 00:38:43.011362 u2DelayCellTimex100 = 270/100 ps
4005 00:38:43.014021 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4006 00:38:43.017060 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4007 00:38:43.023882 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4008 00:38:43.026987 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4009 00:38:43.030547 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 00:38:43.033867 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4011 00:38:43.033977
4012 00:38:43.037499 CA PerBit enable=1, Macro0, CA PI delay=33
4013 00:38:43.037607
4014 00:38:43.040857 [CBTSetCACLKResult] CA Dly = 33
4015 00:38:43.040958 CS Dly: 5 (0~36)
4016 00:38:43.041066
4017 00:38:43.044162 ----->DramcWriteLeveling(PI) begin...
4018 00:38:43.047067 ==
4019 00:38:43.047150 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 00:38:43.053810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 00:38:43.053942 ==
4022 00:38:43.057323 Write leveling (Byte 0): 34 => 34
4023 00:38:43.060918 Write leveling (Byte 1): 29 => 29
4024 00:38:43.061050 DramcWriteLeveling(PI) end<-----
4025 00:38:43.064413
4026 00:38:43.064520 ==
4027 00:38:43.067419 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 00:38:43.071305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 00:38:43.071389 ==
4030 00:38:43.074120 [Gating] SW mode calibration
4031 00:38:43.080543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4032 00:38:43.084103 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4033 00:38:43.090872 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 00:38:43.093855 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 00:38:43.097199 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 00:38:43.104486 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4037 00:38:43.107470 0 9 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
4038 00:38:43.110642 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4039 00:38:43.117405 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 00:38:43.121009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 00:38:43.124647 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 00:38:43.130851 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 00:38:43.133981 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 00:38:43.137438 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4045 00:38:43.140888 0 10 16 | B1->B0 | 3131 3939 | 0 0 | (1 1) (1 1)
4046 00:38:43.147446 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 00:38:43.150608 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 00:38:43.154308 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 00:38:43.160827 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 00:38:43.164196 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 00:38:43.167372 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 00:38:43.174111 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 00:38:43.177167 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4054 00:38:43.180451 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4055 00:38:43.187304 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 00:38:43.190518 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 00:38:43.194168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 00:38:43.200675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 00:38:43.203814 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 00:38:43.207800 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 00:38:43.213813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 00:38:43.217836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 00:38:43.220576 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 00:38:43.227160 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 00:38:43.230575 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 00:38:43.234378 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 00:38:43.240440 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 00:38:43.244033 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 00:38:43.247790 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4070 00:38:43.253926 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 00:38:43.254027 Total UI for P1: 0, mck2ui 16
4072 00:38:43.257048 best dqsien dly found for B0: ( 0, 13, 16)
4073 00:38:43.260955 Total UI for P1: 0, mck2ui 16
4074 00:38:43.264149 best dqsien dly found for B1: ( 0, 13, 16)
4075 00:38:43.267423 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4076 00:38:43.274490 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4077 00:38:43.274566
4078 00:38:43.277093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4079 00:38:43.281195 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4080 00:38:43.284023 [Gating] SW calibration Done
4081 00:38:43.284104 ==
4082 00:38:43.287302 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 00:38:43.290490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 00:38:43.290566 ==
4085 00:38:43.290628 RX Vref Scan: 0
4086 00:38:43.293770
4087 00:38:43.293848 RX Vref 0 -> 0, step: 1
4088 00:38:43.293910
4089 00:38:43.297193 RX Delay -230 -> 252, step: 16
4090 00:38:43.301103 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4091 00:38:43.307420 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4092 00:38:43.310944 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4093 00:38:43.314309 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4094 00:38:43.317710 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4095 00:38:43.320500 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4096 00:38:43.327019 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4097 00:38:43.330451 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4098 00:38:43.334060 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4099 00:38:43.337416 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4100 00:38:43.340556 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4101 00:38:43.347223 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4102 00:38:43.351028 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4103 00:38:43.354127 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4104 00:38:43.357529 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4105 00:38:43.363821 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4106 00:38:43.363950 ==
4107 00:38:43.367701 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 00:38:43.370489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 00:38:43.370583 ==
4110 00:38:43.370651 DQS Delay:
4111 00:38:43.374037 DQS0 = 0, DQS1 = 0
4112 00:38:43.374114 DQM Delay:
4113 00:38:43.377533 DQM0 = 40, DQM1 = 32
4114 00:38:43.377710 DQ Delay:
4115 00:38:43.380603 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4116 00:38:43.384187 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4117 00:38:43.387577 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4118 00:38:43.390537 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4119 00:38:43.390694
4120 00:38:43.390818
4121 00:38:43.390932 ==
4122 00:38:43.394054 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 00:38:43.397389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 00:38:43.397575 ==
4125 00:38:43.400731
4126 00:38:43.400902
4127 00:38:43.401066 TX Vref Scan disable
4128 00:38:43.404044 == TX Byte 0 ==
4129 00:38:43.407566 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4130 00:38:43.411722 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4131 00:38:43.414141 == TX Byte 1 ==
4132 00:38:43.417384 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4133 00:38:43.420676 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4134 00:38:43.420861 ==
4135 00:38:43.424215 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 00:38:43.430773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 00:38:43.430939 ==
4138 00:38:43.431136
4139 00:38:43.431273
4140 00:38:43.431391 TX Vref Scan disable
4141 00:38:43.435771 == TX Byte 0 ==
4142 00:38:43.438534 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4143 00:38:43.442134 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4144 00:38:43.446750 == TX Byte 1 ==
4145 00:38:43.448706 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4146 00:38:43.452009 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4147 00:38:43.456023
4148 00:38:43.456126 [DATLAT]
4149 00:38:43.456215 Freq=600, CH0 RK0
4150 00:38:43.456304
4151 00:38:43.458878 DATLAT Default: 0x9
4152 00:38:43.458984 0, 0xFFFF, sum = 0
4153 00:38:43.461974 1, 0xFFFF, sum = 0
4154 00:38:43.462079 2, 0xFFFF, sum = 0
4155 00:38:43.465669 3, 0xFFFF, sum = 0
4156 00:38:43.465744 4, 0xFFFF, sum = 0
4157 00:38:43.468619 5, 0xFFFF, sum = 0
4158 00:38:43.468708 6, 0xFFFF, sum = 0
4159 00:38:43.472078 7, 0xFFFF, sum = 0
4160 00:38:43.472170 8, 0x0, sum = 1
4161 00:38:43.475334 9, 0x0, sum = 2
4162 00:38:43.475454 10, 0x0, sum = 3
4163 00:38:43.478790 11, 0x0, sum = 4
4164 00:38:43.478870 best_step = 9
4165 00:38:43.478962
4166 00:38:43.479058 ==
4167 00:38:43.482649 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 00:38:43.489036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 00:38:43.489168 ==
4170 00:38:43.489334 RX Vref Scan: 1
4171 00:38:43.489428
4172 00:38:43.491826 RX Vref 0 -> 0, step: 1
4173 00:38:43.491939
4174 00:38:43.495606 RX Delay -195 -> 252, step: 8
4175 00:38:43.495698
4176 00:38:43.498417 Set Vref, RX VrefLevel [Byte0]: 53
4177 00:38:43.502223 [Byte1]: 52
4178 00:38:43.502374
4179 00:38:43.505546 Final RX Vref Byte 0 = 53 to rank0
4180 00:38:43.508758 Final RX Vref Byte 1 = 52 to rank0
4181 00:38:43.512515 Final RX Vref Byte 0 = 53 to rank1
4182 00:38:43.515764 Final RX Vref Byte 1 = 52 to rank1==
4183 00:38:43.518362 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 00:38:43.521826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 00:38:43.521940 ==
4186 00:38:43.524957 DQS Delay:
4187 00:38:43.525102 DQS0 = 0, DQS1 = 0
4188 00:38:43.525204 DQM Delay:
4189 00:38:43.528497 DQM0 = 42, DQM1 = 33
4190 00:38:43.528602 DQ Delay:
4191 00:38:43.532226 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4192 00:38:43.535101 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4193 00:38:43.538417 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4194 00:38:43.541789 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4195 00:38:43.541890
4196 00:38:43.541983
4197 00:38:43.551904 [DQSOSCAuto] RK0, (LSB)MR18= 0x4524, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4198 00:38:43.555223 CH0 RK0: MR19=808, MR18=4524
4199 00:38:43.558425 CH0_RK0: MR19=0x808, MR18=0x4524, DQSOSC=396, MR23=63, INC=167, DEC=111
4200 00:38:43.558526
4201 00:38:43.561912 ----->DramcWriteLeveling(PI) begin...
4202 00:38:43.565860 ==
4203 00:38:43.565941 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 00:38:43.572134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 00:38:43.572240 ==
4206 00:38:43.575481 Write leveling (Byte 0): 31 => 31
4207 00:38:43.578766 Write leveling (Byte 1): 31 => 31
4208 00:38:43.582167 DramcWriteLeveling(PI) end<-----
4209 00:38:43.582301
4210 00:38:43.582418 ==
4211 00:38:43.585766 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 00:38:43.588758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 00:38:43.588864 ==
4214 00:38:43.591993 [Gating] SW mode calibration
4215 00:38:43.599216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4216 00:38:43.602195 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4217 00:38:43.609113 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 00:38:43.612036 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 00:38:43.616008 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 00:38:43.622417 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4221 00:38:43.625554 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4222 00:38:43.628835 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 00:38:43.635270 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 00:38:43.638853 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 00:38:43.642656 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 00:38:43.648833 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 00:38:43.651912 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4228 00:38:43.656073 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4229 00:38:43.662208 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4230 00:38:43.665176 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 00:38:43.669174 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 00:38:43.671971 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 00:38:43.678436 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 00:38:43.681985 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 00:38:43.685243 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 00:38:43.691960 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4237 00:38:43.695322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4238 00:38:43.699219 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4239 00:38:43.705211 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 00:38:43.708715 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 00:38:43.711855 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 00:38:43.718583 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 00:38:43.722454 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 00:38:43.725245 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 00:38:43.732123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 00:38:43.735324 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 00:38:43.739435 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 00:38:43.745391 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 00:38:43.749133 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 00:38:43.752032 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 00:38:43.758780 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 00:38:43.763005 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4253 00:38:43.765199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4254 00:38:43.768787 Total UI for P1: 0, mck2ui 16
4255 00:38:43.772349 best dqsien dly found for B0: ( 0, 13, 12)
4256 00:38:43.775459 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 00:38:43.778593 Total UI for P1: 0, mck2ui 16
4258 00:38:43.782073 best dqsien dly found for B1: ( 0, 13, 14)
4259 00:38:43.785348 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4260 00:38:43.791870 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4261 00:38:43.791952
4262 00:38:43.795605 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4263 00:38:43.798502 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4264 00:38:43.802183 [Gating] SW calibration Done
4265 00:38:43.802264 ==
4266 00:38:43.805467 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 00:38:43.808883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 00:38:43.809013 ==
4269 00:38:43.809095 RX Vref Scan: 0
4270 00:38:43.809155
4271 00:38:43.812159 RX Vref 0 -> 0, step: 1
4272 00:38:43.812240
4273 00:38:43.815554 RX Delay -230 -> 252, step: 16
4274 00:38:43.819098 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4275 00:38:43.825392 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4276 00:38:43.828938 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4277 00:38:43.832062 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4278 00:38:43.835815 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4279 00:38:43.839268 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4280 00:38:43.845708 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4281 00:38:43.848836 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4282 00:38:43.852225 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4283 00:38:43.856004 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4284 00:38:43.859239 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4285 00:38:43.865714 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4286 00:38:43.869644 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4287 00:38:43.872420 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4288 00:38:43.875839 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4289 00:38:43.882826 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4290 00:38:43.882907 ==
4291 00:38:43.885578 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 00:38:43.889190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 00:38:43.889272 ==
4294 00:38:43.889337 DQS Delay:
4295 00:38:43.892024 DQS0 = 0, DQS1 = 0
4296 00:38:43.892105 DQM Delay:
4297 00:38:43.895414 DQM0 = 39, DQM1 = 31
4298 00:38:43.895495 DQ Delay:
4299 00:38:43.899064 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4300 00:38:43.902304 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4301 00:38:43.905587 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4302 00:38:43.909110 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4303 00:38:43.909192
4304 00:38:43.909256
4305 00:38:43.909316 ==
4306 00:38:43.912316 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 00:38:43.916226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 00:38:43.916308 ==
4309 00:38:43.916372
4310 00:38:43.918769
4311 00:38:43.918850 TX Vref Scan disable
4312 00:38:43.922299 == TX Byte 0 ==
4313 00:38:43.925782 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4314 00:38:43.928896 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4315 00:38:43.931962 == TX Byte 1 ==
4316 00:38:43.935473 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4317 00:38:43.939173 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4318 00:38:43.939254 ==
4319 00:38:43.941982 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 00:38:43.949151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 00:38:43.949233 ==
4322 00:38:43.949297
4323 00:38:43.949356
4324 00:38:43.949413 TX Vref Scan disable
4325 00:38:43.953506 == TX Byte 0 ==
4326 00:38:43.956390 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4327 00:38:43.963396 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4328 00:38:43.963477 == TX Byte 1 ==
4329 00:38:43.966762 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4330 00:38:43.973220 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4331 00:38:43.973301
4332 00:38:43.973363 [DATLAT]
4333 00:38:43.973422 Freq=600, CH0 RK1
4334 00:38:43.973480
4335 00:38:43.976453 DATLAT Default: 0x9
4336 00:38:43.976533 0, 0xFFFF, sum = 0
4337 00:38:43.980081 1, 0xFFFF, sum = 0
4338 00:38:43.980219 2, 0xFFFF, sum = 0
4339 00:38:43.983144 3, 0xFFFF, sum = 0
4340 00:38:43.986757 4, 0xFFFF, sum = 0
4341 00:38:43.986838 5, 0xFFFF, sum = 0
4342 00:38:43.990270 6, 0xFFFF, sum = 0
4343 00:38:43.990352 7, 0xFFFF, sum = 0
4344 00:38:43.993152 8, 0x0, sum = 1
4345 00:38:43.993234 9, 0x0, sum = 2
4346 00:38:43.993301 10, 0x0, sum = 3
4347 00:38:43.996669 11, 0x0, sum = 4
4348 00:38:43.996751 best_step = 9
4349 00:38:43.996815
4350 00:38:43.996874 ==
4351 00:38:43.999907 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 00:38:44.006716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 00:38:44.006799 ==
4354 00:38:44.006864 RX Vref Scan: 0
4355 00:38:44.006936
4356 00:38:44.009667 RX Vref 0 -> 0, step: 1
4357 00:38:44.009737
4358 00:38:44.013130 RX Delay -195 -> 252, step: 8
4359 00:38:44.016353 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4360 00:38:44.023130 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4361 00:38:44.026425 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4362 00:38:44.029743 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4363 00:38:44.033160 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4364 00:38:44.036605 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4365 00:38:44.042998 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4366 00:38:44.046771 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4367 00:38:44.049970 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4368 00:38:44.053160 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4369 00:38:44.059749 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4370 00:38:44.063039 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4371 00:38:44.066386 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4372 00:38:44.069925 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4373 00:38:44.077445 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4374 00:38:44.079734 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4375 00:38:44.079815 ==
4376 00:38:44.083280 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 00:38:44.086796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 00:38:44.086877 ==
4379 00:38:44.086940 DQS Delay:
4380 00:38:44.090091 DQS0 = 0, DQS1 = 0
4381 00:38:44.090171 DQM Delay:
4382 00:38:44.093489 DQM0 = 39, DQM1 = 33
4383 00:38:44.093569 DQ Delay:
4384 00:38:44.096799 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4385 00:38:44.100024 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4386 00:38:44.103151 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4387 00:38:44.106421 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4388 00:38:44.106502
4389 00:38:44.106566
4390 00:38:44.116641 [DQSOSCAuto] RK1, (LSB)MR18= 0x5134, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4391 00:38:44.116723 CH0 RK1: MR19=808, MR18=5134
4392 00:38:44.123170 CH0_RK1: MR19=0x808, MR18=0x5134, DQSOSC=394, MR23=63, INC=168, DEC=112
4393 00:38:44.126266 [RxdqsGatingPostProcess] freq 600
4394 00:38:44.133398 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4395 00:38:44.136572 Pre-setting of DQS Precalculation
4396 00:38:44.140469 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4397 00:38:44.140551 ==
4398 00:38:44.143470 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 00:38:44.146780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 00:38:44.146861 ==
4401 00:38:44.153303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 00:38:44.159809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4403 00:38:44.163320 [CA 0] Center 35 (5~66) winsize 62
4404 00:38:44.166634 [CA 1] Center 35 (5~66) winsize 62
4405 00:38:44.170516 [CA 2] Center 33 (3~64) winsize 62
4406 00:38:44.173187 [CA 3] Center 33 (3~64) winsize 62
4407 00:38:44.176657 [CA 4] Center 34 (3~65) winsize 63
4408 00:38:44.180051 [CA 5] Center 33 (2~64) winsize 63
4409 00:38:44.180136
4410 00:38:44.183383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4411 00:38:44.183465
4412 00:38:44.186622 [CATrainingPosCal] consider 1 rank data
4413 00:38:44.189795 u2DelayCellTimex100 = 270/100 ps
4414 00:38:44.193420 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4415 00:38:44.196889 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 00:38:44.200366 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 00:38:44.203632 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 00:38:44.207119 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4419 00:38:44.210442 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4420 00:38:44.210539
4421 00:38:44.217150 CA PerBit enable=1, Macro0, CA PI delay=33
4422 00:38:44.217238
4423 00:38:44.220411 [CBTSetCACLKResult] CA Dly = 33
4424 00:38:44.220504 CS Dly: 4 (0~35)
4425 00:38:44.220567 ==
4426 00:38:44.223522 Dram Type= 6, Freq= 0, CH_1, rank 1
4427 00:38:44.226864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 00:38:44.226940 ==
4429 00:38:44.233426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4430 00:38:44.239980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4431 00:38:44.244027 [CA 0] Center 35 (5~66) winsize 62
4432 00:38:44.246586 [CA 1] Center 35 (5~66) winsize 62
4433 00:38:44.250048 [CA 2] Center 34 (3~65) winsize 63
4434 00:38:44.253345 [CA 3] Center 33 (3~64) winsize 62
4435 00:38:44.256644 [CA 4] Center 34 (3~65) winsize 63
4436 00:38:44.260326 [CA 5] Center 33 (2~64) winsize 63
4437 00:38:44.260402
4438 00:38:44.263705 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4439 00:38:44.263774
4440 00:38:44.267057 [CATrainingPosCal] consider 2 rank data
4441 00:38:44.270325 u2DelayCellTimex100 = 270/100 ps
4442 00:38:44.273358 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4443 00:38:44.276740 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4444 00:38:44.280314 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 00:38:44.283472 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4446 00:38:44.286820 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4447 00:38:44.290332 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4448 00:38:44.293457
4449 00:38:44.296483 CA PerBit enable=1, Macro0, CA PI delay=33
4450 00:38:44.296552
4451 00:38:44.300659 [CBTSetCACLKResult] CA Dly = 33
4452 00:38:44.300727 CS Dly: 5 (0~37)
4453 00:38:44.300785
4454 00:38:44.303552 ----->DramcWriteLeveling(PI) begin...
4455 00:38:44.303621 ==
4456 00:38:44.306713 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 00:38:44.310148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 00:38:44.313739 ==
4459 00:38:44.313809 Write leveling (Byte 0): 30 => 30
4460 00:38:44.316688 Write leveling (Byte 1): 30 => 30
4461 00:38:44.320086 DramcWriteLeveling(PI) end<-----
4462 00:38:44.320157
4463 00:38:44.320217 ==
4464 00:38:44.323237 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 00:38:44.329871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 00:38:44.329946 ==
4467 00:38:44.330009 [Gating] SW mode calibration
4468 00:38:44.340319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4469 00:38:44.343154 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4470 00:38:44.346953 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 00:38:44.353410 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 00:38:44.357285 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 00:38:44.360207 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 00:38:44.366862 0 9 16 | B1->B0 | 2a2a 2828 | 1 0 | (1 0) (0 0)
4475 00:38:44.370123 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4476 00:38:44.373462 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 00:38:44.380761 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 00:38:44.383822 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 00:38:44.387183 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 00:38:44.393565 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 00:38:44.396917 0 10 12 | B1->B0 | 2727 2e2d | 0 1 | (0 0) (0 0)
4482 00:38:44.400343 0 10 16 | B1->B0 | 3d3d 4242 | 0 1 | (0 0) (1 1)
4483 00:38:44.407198 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 00:38:44.410600 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 00:38:44.413658 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 00:38:44.420460 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 00:38:44.423325 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 00:38:44.427351 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 00:38:44.430300 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4490 00:38:44.436638 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 00:38:44.440231 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 00:38:44.443445 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 00:38:44.450472 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 00:38:44.453712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 00:38:44.456758 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 00:38:44.463584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 00:38:44.466986 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 00:38:44.470246 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 00:38:44.476992 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 00:38:44.480464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 00:38:44.483289 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 00:38:44.489911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 00:38:44.493255 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 00:38:44.497065 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 00:38:44.503438 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4506 00:38:44.506491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4507 00:38:44.510190 Total UI for P1: 0, mck2ui 16
4508 00:38:44.513626 best dqsien dly found for B0: ( 0, 13, 12)
4509 00:38:44.517519 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 00:38:44.520343 Total UI for P1: 0, mck2ui 16
4511 00:38:44.523462 best dqsien dly found for B1: ( 0, 13, 14)
4512 00:38:44.526544 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4513 00:38:44.530717 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4514 00:38:44.530794
4515 00:38:44.533797 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4516 00:38:44.540296 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4517 00:38:44.540373 [Gating] SW calibration Done
4518 00:38:44.540443 ==
4519 00:38:44.543357 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 00:38:44.550065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 00:38:44.550139 ==
4522 00:38:44.550207 RX Vref Scan: 0
4523 00:38:44.550265
4524 00:38:44.553584 RX Vref 0 -> 0, step: 1
4525 00:38:44.553655
4526 00:38:44.557215 RX Delay -230 -> 252, step: 16
4527 00:38:44.561519 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4528 00:38:44.563460 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4529 00:38:44.566833 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4530 00:38:44.573804 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4531 00:38:44.576883 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4532 00:38:44.580415 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4533 00:38:44.583642 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4534 00:38:44.590218 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4535 00:38:44.593524 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4536 00:38:44.596907 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4537 00:38:44.600327 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4538 00:38:44.603792 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4539 00:38:44.610318 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4540 00:38:44.614002 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4541 00:38:44.616766 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4542 00:38:44.620447 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4543 00:38:44.620529 ==
4544 00:38:44.623476 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 00:38:44.630308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 00:38:44.630391 ==
4547 00:38:44.630456 DQS Delay:
4548 00:38:44.633933 DQS0 = 0, DQS1 = 0
4549 00:38:44.634014 DQM Delay:
4550 00:38:44.634080 DQM0 = 44, DQM1 = 35
4551 00:38:44.637260 DQ Delay:
4552 00:38:44.640444 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4553 00:38:44.644118 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =33
4554 00:38:44.646897 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4555 00:38:44.650398 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =33
4556 00:38:44.650480
4557 00:38:44.650545
4558 00:38:44.650604 ==
4559 00:38:44.654372 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:38:44.657097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:38:44.657180 ==
4562 00:38:44.657245
4563 00:38:44.657304
4564 00:38:44.660666 TX Vref Scan disable
4565 00:38:44.660747 == TX Byte 0 ==
4566 00:38:44.667456 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4567 00:38:44.670960 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4568 00:38:44.671043 == TX Byte 1 ==
4569 00:38:44.677193 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4570 00:38:44.680369 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4571 00:38:44.680453 ==
4572 00:38:44.683920 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 00:38:44.687139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 00:38:44.687224 ==
4575 00:38:44.687309
4576 00:38:44.687388
4577 00:38:44.690439 TX Vref Scan disable
4578 00:38:44.694030 == TX Byte 0 ==
4579 00:38:44.697358 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4580 00:38:44.700559 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4581 00:38:44.703794 == TX Byte 1 ==
4582 00:38:44.707212 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4583 00:38:44.710882 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4584 00:38:44.710965
4585 00:38:44.713771 [DATLAT]
4586 00:38:44.713852 Freq=600, CH1 RK0
4587 00:38:44.713917
4588 00:38:44.717422 DATLAT Default: 0x9
4589 00:38:44.717519 0, 0xFFFF, sum = 0
4590 00:38:44.720706 1, 0xFFFF, sum = 0
4591 00:38:44.720839 2, 0xFFFF, sum = 0
4592 00:38:44.723811 3, 0xFFFF, sum = 0
4593 00:38:44.723906 4, 0xFFFF, sum = 0
4594 00:38:44.727867 5, 0xFFFF, sum = 0
4595 00:38:44.727951 6, 0xFFFF, sum = 0
4596 00:38:44.730401 7, 0xFFFF, sum = 0
4597 00:38:44.730486 8, 0x0, sum = 1
4598 00:38:44.733806 9, 0x0, sum = 2
4599 00:38:44.733889 10, 0x0, sum = 3
4600 00:38:44.737243 11, 0x0, sum = 4
4601 00:38:44.737326 best_step = 9
4602 00:38:44.737391
4603 00:38:44.737450 ==
4604 00:38:44.740404 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 00:38:44.747349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 00:38:44.747431 ==
4607 00:38:44.747495 RX Vref Scan: 1
4608 00:38:44.747555
4609 00:38:44.750602 RX Vref 0 -> 0, step: 1
4610 00:38:44.750683
4611 00:38:44.754093 RX Delay -195 -> 252, step: 8
4612 00:38:44.754177
4613 00:38:44.757336 Set Vref, RX VrefLevel [Byte0]: 56
4614 00:38:44.760481 [Byte1]: 50
4615 00:38:44.760562
4616 00:38:44.763805 Final RX Vref Byte 0 = 56 to rank0
4617 00:38:44.767235 Final RX Vref Byte 1 = 50 to rank0
4618 00:38:44.770318 Final RX Vref Byte 0 = 56 to rank1
4619 00:38:44.774297 Final RX Vref Byte 1 = 50 to rank1==
4620 00:38:44.777073 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 00:38:44.780808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 00:38:44.780894 ==
4623 00:38:44.784021 DQS Delay:
4624 00:38:44.784105 DQS0 = 0, DQS1 = 0
4625 00:38:44.784189 DQM Delay:
4626 00:38:44.787406 DQM0 = 41, DQM1 = 32
4627 00:38:44.787491 DQ Delay:
4628 00:38:44.790980 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4629 00:38:44.793824 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4630 00:38:44.797593 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4631 00:38:44.800508 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4632 00:38:44.800592
4633 00:38:44.800677
4634 00:38:44.810796 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
4635 00:38:44.810883 CH1 RK0: MR19=808, MR18=4A10
4636 00:38:44.817563 CH1_RK0: MR19=0x808, MR18=0x4A10, DQSOSC=395, MR23=63, INC=168, DEC=112
4637 00:38:44.817648
4638 00:38:44.820811 ----->DramcWriteLeveling(PI) begin...
4639 00:38:44.820896 ==
4640 00:38:44.824208 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 00:38:44.831139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 00:38:44.831225 ==
4643 00:38:44.833934 Write leveling (Byte 0): 31 => 31
4644 00:38:44.837517 Write leveling (Byte 1): 31 => 31
4645 00:38:44.837601 DramcWriteLeveling(PI) end<-----
4646 00:38:44.837685
4647 00:38:44.840502 ==
4648 00:38:44.844117 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 00:38:44.847300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 00:38:44.847382 ==
4651 00:38:44.851152 [Gating] SW mode calibration
4652 00:38:44.857483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4653 00:38:44.860605 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4654 00:38:44.867714 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 00:38:44.870746 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 00:38:44.873899 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4657 00:38:44.880609 0 9 12 | B1->B0 | 3131 2727 | 0 0 | (1 0) (0 0)
4658 00:38:44.883813 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4659 00:38:44.887627 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 00:38:44.893832 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 00:38:44.897488 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 00:38:44.901096 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4663 00:38:44.904148 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 00:38:44.910921 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4665 00:38:44.913900 0 10 12 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
4666 00:38:44.917200 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4667 00:38:44.923735 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 00:38:44.927354 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 00:38:44.930461 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 00:38:44.937584 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 00:38:44.941396 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 00:38:44.943934 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 00:38:44.950484 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4674 00:38:44.953805 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 00:38:44.957354 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 00:38:44.965001 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 00:38:44.967756 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 00:38:44.970905 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 00:38:44.977574 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 00:38:44.981099 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 00:38:44.984053 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 00:38:44.987852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 00:38:44.993885 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 00:38:44.997459 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 00:38:45.001654 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 00:38:45.007727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 00:38:45.010905 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 00:38:45.014067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4689 00:38:45.020886 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4690 00:38:45.024052 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 00:38:45.027861 Total UI for P1: 0, mck2ui 16
4692 00:38:45.030855 best dqsien dly found for B0: ( 0, 13, 10)
4693 00:38:45.034425 Total UI for P1: 0, mck2ui 16
4694 00:38:45.037683 best dqsien dly found for B1: ( 0, 13, 14)
4695 00:38:45.040780 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4696 00:38:45.044188 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4697 00:38:45.044284
4698 00:38:45.047564 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4699 00:38:45.050633 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4700 00:38:45.054293 [Gating] SW calibration Done
4701 00:38:45.054367 ==
4702 00:38:45.057735 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 00:38:45.061073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 00:38:45.064760 ==
4705 00:38:45.064866 RX Vref Scan: 0
4706 00:38:45.064957
4707 00:38:45.067981 RX Vref 0 -> 0, step: 1
4708 00:38:45.068084
4709 00:38:45.071259 RX Delay -230 -> 252, step: 16
4710 00:38:45.074368 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4711 00:38:45.077334 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4712 00:38:45.080879 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4713 00:38:45.087430 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4714 00:38:45.091503 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4715 00:38:45.094047 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4716 00:38:45.097485 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4717 00:38:45.100620 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4718 00:38:45.107362 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4719 00:38:45.110444 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4720 00:38:45.114428 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4721 00:38:45.117501 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4722 00:38:45.124208 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4723 00:38:45.127564 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4724 00:38:45.130467 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4725 00:38:45.134200 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4726 00:38:45.134275 ==
4727 00:38:45.136942 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 00:38:45.144039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 00:38:45.144123 ==
4730 00:38:45.144188 DQS Delay:
4731 00:38:45.147014 DQS0 = 0, DQS1 = 0
4732 00:38:45.147090 DQM Delay:
4733 00:38:45.147151 DQM0 = 39, DQM1 = 33
4734 00:38:45.150973 DQ Delay:
4735 00:38:45.153716 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4736 00:38:45.157099 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4737 00:38:45.160431 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4738 00:38:45.163609 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4739 00:38:45.163682
4740 00:38:45.163744
4741 00:38:45.163808 ==
4742 00:38:45.166873 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 00:38:45.170265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 00:38:45.170339 ==
4745 00:38:45.170401
4746 00:38:45.170464
4747 00:38:45.173982 TX Vref Scan disable
4748 00:38:45.174054 == TX Byte 0 ==
4749 00:38:45.180371 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4750 00:38:45.183600 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4751 00:38:45.183680 == TX Byte 1 ==
4752 00:38:45.190785 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4753 00:38:45.193933 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4754 00:38:45.194039 ==
4755 00:38:45.196816 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 00:38:45.200793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 00:38:45.200878 ==
4758 00:38:45.200985
4759 00:38:45.203822
4760 00:38:45.203905 TX Vref Scan disable
4761 00:38:45.207651 == TX Byte 0 ==
4762 00:38:45.210922 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4763 00:38:45.217300 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4764 00:38:45.217385 == TX Byte 1 ==
4765 00:38:45.220189 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4766 00:38:45.224050 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4767 00:38:45.226913
4768 00:38:45.226996 [DATLAT]
4769 00:38:45.227080 Freq=600, CH1 RK1
4770 00:38:45.227159
4771 00:38:45.230297 DATLAT Default: 0x9
4772 00:38:45.230411 0, 0xFFFF, sum = 0
4773 00:38:45.234118 1, 0xFFFF, sum = 0
4774 00:38:45.234195 2, 0xFFFF, sum = 0
4775 00:38:45.237509 3, 0xFFFF, sum = 0
4776 00:38:45.237585 4, 0xFFFF, sum = 0
4777 00:38:45.240114 5, 0xFFFF, sum = 0
4778 00:38:45.243803 6, 0xFFFF, sum = 0
4779 00:38:45.243899 7, 0xFFFF, sum = 0
4780 00:38:45.243993 8, 0x0, sum = 1
4781 00:38:45.247484 9, 0x0, sum = 2
4782 00:38:45.247556 10, 0x0, sum = 3
4783 00:38:45.250768 11, 0x0, sum = 4
4784 00:38:45.250840 best_step = 9
4785 00:38:45.250904
4786 00:38:45.250962 ==
4787 00:38:45.253828 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 00:38:45.260712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 00:38:45.260789 ==
4790 00:38:45.260867 RX Vref Scan: 0
4791 00:38:45.260955
4792 00:38:45.264097 RX Vref 0 -> 0, step: 1
4793 00:38:45.264166
4794 00:38:45.267086 RX Delay -195 -> 252, step: 8
4795 00:38:45.270593 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4796 00:38:45.276935 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4797 00:38:45.281294 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4798 00:38:45.283608 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4799 00:38:45.287139 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4800 00:38:45.290346 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4801 00:38:45.297292 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4802 00:38:45.300366 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4803 00:38:45.304160 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4804 00:38:45.307455 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4805 00:38:45.310768 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4806 00:38:45.317247 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4807 00:38:45.320641 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4808 00:38:45.324089 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4809 00:38:45.327576 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4810 00:38:45.334169 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4811 00:38:45.334255 ==
4812 00:38:45.337464 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 00:38:45.340286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 00:38:45.340392 ==
4815 00:38:45.340490 DQS Delay:
4816 00:38:45.343941 DQS0 = 0, DQS1 = 0
4817 00:38:45.344022 DQM Delay:
4818 00:38:45.347430 DQM0 = 37, DQM1 = 32
4819 00:38:45.347521 DQ Delay:
4820 00:38:45.350593 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4821 00:38:45.353631 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4822 00:38:45.357240 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4823 00:38:45.360750 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4824 00:38:45.360822
4825 00:38:45.360883
4826 00:38:45.367068 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b4c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4827 00:38:45.370508 CH1 RK1: MR19=808, MR18=3B4C
4828 00:38:45.377200 CH1_RK1: MR19=0x808, MR18=0x3B4C, DQSOSC=395, MR23=63, INC=168, DEC=112
4829 00:38:45.380317 [RxdqsGatingPostProcess] freq 600
4830 00:38:45.387071 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4831 00:38:45.390749 Pre-setting of DQS Precalculation
4832 00:38:45.394216 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4833 00:38:45.400581 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4834 00:38:45.407497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4835 00:38:45.407581
4836 00:38:45.407682
4837 00:38:45.411195 [Calibration Summary] 1200 Mbps
4838 00:38:45.414060 CH 0, Rank 0
4839 00:38:45.414144 SW Impedance : PASS
4840 00:38:45.417355 DUTY Scan : NO K
4841 00:38:45.420500 ZQ Calibration : PASS
4842 00:38:45.420584 Jitter Meter : NO K
4843 00:38:45.423987 CBT Training : PASS
4844 00:38:45.427491 Write leveling : PASS
4845 00:38:45.427573 RX DQS gating : PASS
4846 00:38:45.431129 RX DQ/DQS(RDDQC) : PASS
4847 00:38:45.431211 TX DQ/DQS : PASS
4848 00:38:45.434489 RX DATLAT : PASS
4849 00:38:45.437271 RX DQ/DQS(Engine): PASS
4850 00:38:45.437352 TX OE : NO K
4851 00:38:45.440438 All Pass.
4852 00:38:45.440519
4853 00:38:45.440584 CH 0, Rank 1
4854 00:38:45.444555 SW Impedance : PASS
4855 00:38:45.444636 DUTY Scan : NO K
4856 00:38:45.447796 ZQ Calibration : PASS
4857 00:38:45.450953 Jitter Meter : NO K
4858 00:38:45.451034 CBT Training : PASS
4859 00:38:45.454313 Write leveling : PASS
4860 00:38:45.457291 RX DQS gating : PASS
4861 00:38:45.457372 RX DQ/DQS(RDDQC) : PASS
4862 00:38:45.460409 TX DQ/DQS : PASS
4863 00:38:45.463701 RX DATLAT : PASS
4864 00:38:45.463782 RX DQ/DQS(Engine): PASS
4865 00:38:45.467065 TX OE : NO K
4866 00:38:45.467147 All Pass.
4867 00:38:45.467211
4868 00:38:45.470676 CH 1, Rank 0
4869 00:38:45.470757 SW Impedance : PASS
4870 00:38:45.474378 DUTY Scan : NO K
4871 00:38:45.474460 ZQ Calibration : PASS
4872 00:38:45.477046 Jitter Meter : NO K
4873 00:38:45.480533 CBT Training : PASS
4874 00:38:45.480614 Write leveling : PASS
4875 00:38:45.484271 RX DQS gating : PASS
4876 00:38:45.487525 RX DQ/DQS(RDDQC) : PASS
4877 00:38:45.487606 TX DQ/DQS : PASS
4878 00:38:45.490491 RX DATLAT : PASS
4879 00:38:45.494113 RX DQ/DQS(Engine): PASS
4880 00:38:45.494194 TX OE : NO K
4881 00:38:45.497021 All Pass.
4882 00:38:45.497103
4883 00:38:45.497167 CH 1, Rank 1
4884 00:38:45.500651 SW Impedance : PASS
4885 00:38:45.500732 DUTY Scan : NO K
4886 00:38:45.504489 ZQ Calibration : PASS
4887 00:38:45.507475 Jitter Meter : NO K
4888 00:38:45.507559 CBT Training : PASS
4889 00:38:45.510343 Write leveling : PASS
4890 00:38:45.514275 RX DQS gating : PASS
4891 00:38:45.514356 RX DQ/DQS(RDDQC) : PASS
4892 00:38:45.517519 TX DQ/DQS : PASS
4893 00:38:45.517600 RX DATLAT : PASS
4894 00:38:45.520660 RX DQ/DQS(Engine): PASS
4895 00:38:45.523912 TX OE : NO K
4896 00:38:45.524009 All Pass.
4897 00:38:45.524075
4898 00:38:45.527448 DramC Write-DBI off
4899 00:38:45.527530 PER_BANK_REFRESH: Hybrid Mode
4900 00:38:45.530718 TX_TRACKING: ON
4901 00:38:45.537294 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4902 00:38:45.544533 [FAST_K] Save calibration result to emmc
4903 00:38:45.547575 dramc_set_vcore_voltage set vcore to 662500
4904 00:38:45.547656 Read voltage for 933, 3
4905 00:38:45.550507 Vio18 = 0
4906 00:38:45.550588 Vcore = 662500
4907 00:38:45.550652 Vdram = 0
4908 00:38:45.554275 Vddq = 0
4909 00:38:45.554355 Vmddr = 0
4910 00:38:45.557461 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4911 00:38:45.563879 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4912 00:38:45.567661 MEM_TYPE=3, freq_sel=17
4913 00:38:45.570526 sv_algorithm_assistance_LP4_1600
4914 00:38:45.574304 ============ PULL DRAM RESETB DOWN ============
4915 00:38:45.577695 ========== PULL DRAM RESETB DOWN end =========
4916 00:38:45.580662 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4917 00:38:45.583925 ===================================
4918 00:38:45.587404 LPDDR4 DRAM CONFIGURATION
4919 00:38:45.590885 ===================================
4920 00:38:45.593850 EX_ROW_EN[0] = 0x0
4921 00:38:45.593932 EX_ROW_EN[1] = 0x0
4922 00:38:45.597228 LP4Y_EN = 0x0
4923 00:38:45.597309 WORK_FSP = 0x0
4924 00:38:45.600695 WL = 0x3
4925 00:38:45.600776 RL = 0x3
4926 00:38:45.603837 BL = 0x2
4927 00:38:45.603918 RPST = 0x0
4928 00:38:45.607886 RD_PRE = 0x0
4929 00:38:45.607967 WR_PRE = 0x1
4930 00:38:45.610847 WR_PST = 0x0
4931 00:38:45.614415 DBI_WR = 0x0
4932 00:38:45.614496 DBI_RD = 0x0
4933 00:38:45.617297 OTF = 0x1
4934 00:38:45.621004 ===================================
4935 00:38:45.623780 ===================================
4936 00:38:45.623862 ANA top config
4937 00:38:45.627551 ===================================
4938 00:38:45.630864 DLL_ASYNC_EN = 0
4939 00:38:45.630946 ALL_SLAVE_EN = 1
4940 00:38:45.633666 NEW_RANK_MODE = 1
4941 00:38:45.637345 DLL_IDLE_MODE = 1
4942 00:38:45.640424 LP45_APHY_COMB_EN = 1
4943 00:38:45.643971 TX_ODT_DIS = 1
4944 00:38:45.644053 NEW_8X_MODE = 1
4945 00:38:45.647710 ===================================
4946 00:38:45.650569 ===================================
4947 00:38:45.654171 data_rate = 1866
4948 00:38:45.657141 CKR = 1
4949 00:38:45.660927 DQ_P2S_RATIO = 8
4950 00:38:45.663987 ===================================
4951 00:38:45.667211 CA_P2S_RATIO = 8
4952 00:38:45.670639 DQ_CA_OPEN = 0
4953 00:38:45.670720 DQ_SEMI_OPEN = 0
4954 00:38:45.673883 CA_SEMI_OPEN = 0
4955 00:38:45.677555 CA_FULL_RATE = 0
4956 00:38:45.681147 DQ_CKDIV4_EN = 1
4957 00:38:45.684380 CA_CKDIV4_EN = 1
4958 00:38:45.684461 CA_PREDIV_EN = 0
4959 00:38:45.687413 PH8_DLY = 0
4960 00:38:45.691120 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4961 00:38:45.694072 DQ_AAMCK_DIV = 4
4962 00:38:45.697693 CA_AAMCK_DIV = 4
4963 00:38:45.700690 CA_ADMCK_DIV = 4
4964 00:38:45.700765 DQ_TRACK_CA_EN = 0
4965 00:38:45.703903 CA_PICK = 933
4966 00:38:45.707552 CA_MCKIO = 933
4967 00:38:45.710625 MCKIO_SEMI = 0
4968 00:38:45.714761 PLL_FREQ = 3732
4969 00:38:45.717595 DQ_UI_PI_RATIO = 32
4970 00:38:45.720881 CA_UI_PI_RATIO = 0
4971 00:38:45.724331 ===================================
4972 00:38:45.724414 ===================================
4973 00:38:45.727901 memory_type:LPDDR4
4974 00:38:45.731054 GP_NUM : 10
4975 00:38:45.731135 SRAM_EN : 1
4976 00:38:45.734226 MD32_EN : 0
4977 00:38:45.737584 ===================================
4978 00:38:45.741385 [ANA_INIT] >>>>>>>>>>>>>>
4979 00:38:45.744882 <<<<<< [CONFIGURE PHASE]: ANA_TX
4980 00:38:45.747403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4981 00:38:45.750735 ===================================
4982 00:38:45.750816 data_rate = 1866,PCW = 0X8f00
4983 00:38:45.754151 ===================================
4984 00:38:45.757587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4985 00:38:45.764714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4986 00:38:45.770711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 00:38:45.774159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4988 00:38:45.777553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4989 00:38:45.781590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4990 00:38:45.784339 [ANA_INIT] flow start
4991 00:38:45.784439 [ANA_INIT] PLL >>>>>>>>
4992 00:38:45.787649 [ANA_INIT] PLL <<<<<<<<
4993 00:38:45.790775 [ANA_INIT] MIDPI >>>>>>>>
4994 00:38:45.794712 [ANA_INIT] MIDPI <<<<<<<<
4995 00:38:45.794784 [ANA_INIT] DLL >>>>>>>>
4996 00:38:45.797373 [ANA_INIT] flow end
4997 00:38:45.801387 ============ LP4 DIFF to SE enter ============
4998 00:38:45.804293 ============ LP4 DIFF to SE exit ============
4999 00:38:45.807829 [ANA_INIT] <<<<<<<<<<<<<
5000 00:38:45.811062 [Flow] Enable top DCM control >>>>>
5001 00:38:45.814872 [Flow] Enable top DCM control <<<<<
5002 00:38:45.817581 Enable DLL master slave shuffle
5003 00:38:45.824428 ==============================================================
5004 00:38:45.824534 Gating Mode config
5005 00:38:45.830822 ==============================================================
5006 00:38:45.830925 Config description:
5007 00:38:45.840954 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5008 00:38:45.847477 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5009 00:38:45.854350 SELPH_MODE 0: By rank 1: By Phase
5010 00:38:45.857738 ==============================================================
5011 00:38:45.860972 GAT_TRACK_EN = 1
5012 00:38:45.864410 RX_GATING_MODE = 2
5013 00:38:45.867935 RX_GATING_TRACK_MODE = 2
5014 00:38:45.871029 SELPH_MODE = 1
5015 00:38:45.874340 PICG_EARLY_EN = 1
5016 00:38:45.878292 VALID_LAT_VALUE = 1
5017 00:38:45.881296 ==============================================================
5018 00:38:45.885897 Enter into Gating configuration >>>>
5019 00:38:45.888806 Exit from Gating configuration <<<<
5020 00:38:45.890917 Enter into DVFS_PRE_config >>>>>
5021 00:38:45.904237 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5022 00:38:45.904356 Exit from DVFS_PRE_config <<<<<
5023 00:38:45.907966 Enter into PICG configuration >>>>
5024 00:38:45.911363 Exit from PICG configuration <<<<
5025 00:38:45.914289 [RX_INPUT] configuration >>>>>
5026 00:38:45.918106 [RX_INPUT] configuration <<<<<
5027 00:38:45.924867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5028 00:38:45.927547 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5029 00:38:45.934590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 00:38:45.941518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 00:38:45.947769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 00:38:45.954443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 00:38:45.957777 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5034 00:38:45.961448 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5035 00:38:45.964871 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5036 00:38:45.971110 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5037 00:38:45.974347 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5038 00:38:45.978169 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 00:38:45.980947 ===================================
5040 00:38:45.984638 LPDDR4 DRAM CONFIGURATION
5041 00:38:45.987632 ===================================
5042 00:38:45.987707 EX_ROW_EN[0] = 0x0
5043 00:38:45.991291 EX_ROW_EN[1] = 0x0
5044 00:38:45.991372 LP4Y_EN = 0x0
5045 00:38:45.994490 WORK_FSP = 0x0
5046 00:38:45.999109 WL = 0x3
5047 00:38:45.999190 RL = 0x3
5048 00:38:46.000962 BL = 0x2
5049 00:38:46.001065 RPST = 0x0
5050 00:38:46.004616 RD_PRE = 0x0
5051 00:38:46.004703 WR_PRE = 0x1
5052 00:38:46.007901 WR_PST = 0x0
5053 00:38:46.007985 DBI_WR = 0x0
5054 00:38:46.011003 DBI_RD = 0x0
5055 00:38:46.011088 OTF = 0x1
5056 00:38:46.014797 ===================================
5057 00:38:46.017638 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5058 00:38:46.024445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5059 00:38:46.027763 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5060 00:38:46.031147 ===================================
5061 00:38:46.034193 LPDDR4 DRAM CONFIGURATION
5062 00:38:46.038009 ===================================
5063 00:38:46.038095 EX_ROW_EN[0] = 0x10
5064 00:38:46.040938 EX_ROW_EN[1] = 0x0
5065 00:38:46.041061 LP4Y_EN = 0x0
5066 00:38:46.044351 WORK_FSP = 0x0
5067 00:38:46.044435 WL = 0x3
5068 00:38:46.047490 RL = 0x3
5069 00:38:46.047574 BL = 0x2
5070 00:38:46.051955 RPST = 0x0
5071 00:38:46.052039 RD_PRE = 0x0
5072 00:38:46.054387 WR_PRE = 0x1
5073 00:38:46.057738 WR_PST = 0x0
5074 00:38:46.057822 DBI_WR = 0x0
5075 00:38:46.061131 DBI_RD = 0x0
5076 00:38:46.061215 OTF = 0x1
5077 00:38:46.064419 ===================================
5078 00:38:46.071129 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5079 00:38:46.074595 nWR fixed to 30
5080 00:38:46.077850 [ModeRegInit_LP4] CH0 RK0
5081 00:38:46.077934 [ModeRegInit_LP4] CH0 RK1
5082 00:38:46.081214 [ModeRegInit_LP4] CH1 RK0
5083 00:38:46.085118 [ModeRegInit_LP4] CH1 RK1
5084 00:38:46.085202 match AC timing 9
5085 00:38:46.091165 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5086 00:38:46.094498 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5087 00:38:46.097702 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5088 00:38:46.105393 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5089 00:38:46.108297 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5090 00:38:46.108399 ==
5091 00:38:46.111457 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 00:38:46.114760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 00:38:46.114860 ==
5094 00:38:46.121250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 00:38:46.127773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5096 00:38:46.131420 [CA 0] Center 38 (8~69) winsize 62
5097 00:38:46.134675 [CA 1] Center 38 (7~69) winsize 63
5098 00:38:46.138034 [CA 2] Center 35 (5~66) winsize 62
5099 00:38:46.141064 [CA 3] Center 35 (5~65) winsize 61
5100 00:38:46.144555 [CA 4] Center 34 (4~65) winsize 62
5101 00:38:46.148354 [CA 5] Center 33 (3~64) winsize 62
5102 00:38:46.148430
5103 00:38:46.151149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5104 00:38:46.151247
5105 00:38:46.155010 [CATrainingPosCal] consider 1 rank data
5106 00:38:46.157759 u2DelayCellTimex100 = 270/100 ps
5107 00:38:46.161820 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5108 00:38:46.164484 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5109 00:38:46.168719 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5110 00:38:46.171072 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5111 00:38:46.174926 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5112 00:38:46.178338 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5113 00:38:46.178416
5114 00:38:46.184803 CA PerBit enable=1, Macro0, CA PI delay=33
5115 00:38:46.184888
5116 00:38:46.184980 [CBTSetCACLKResult] CA Dly = 33
5117 00:38:46.188203 CS Dly: 6 (0~37)
5118 00:38:46.188286 ==
5119 00:38:46.191151 Dram Type= 6, Freq= 0, CH_0, rank 1
5120 00:38:46.195049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 00:38:46.195135 ==
5122 00:38:46.201421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5123 00:38:46.208169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5124 00:38:46.211398 [CA 0] Center 38 (8~69) winsize 62
5125 00:38:46.214524 [CA 1] Center 38 (7~69) winsize 63
5126 00:38:46.217935 [CA 2] Center 35 (5~66) winsize 62
5127 00:38:46.221540 [CA 3] Center 35 (4~66) winsize 63
5128 00:38:46.224883 [CA 4] Center 34 (3~65) winsize 63
5129 00:38:46.228583 [CA 5] Center 33 (3~64) winsize 62
5130 00:38:46.228660
5131 00:38:46.231445 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5132 00:38:46.231515
5133 00:38:46.234897 [CATrainingPosCal] consider 2 rank data
5134 00:38:46.238145 u2DelayCellTimex100 = 270/100 ps
5135 00:38:46.241533 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5136 00:38:46.244953 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5137 00:38:46.247984 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5138 00:38:46.251213 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5139 00:38:46.254991 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5140 00:38:46.258072 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5141 00:38:46.258146
5142 00:38:46.264893 CA PerBit enable=1, Macro0, CA PI delay=33
5143 00:38:46.264964
5144 00:38:46.265071 [CBTSetCACLKResult] CA Dly = 33
5145 00:38:46.268167 CS Dly: 7 (0~39)
5146 00:38:46.268234
5147 00:38:46.271409 ----->DramcWriteLeveling(PI) begin...
5148 00:38:46.271477 ==
5149 00:38:46.274503 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 00:38:46.278580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 00:38:46.278654 ==
5152 00:38:46.281697 Write leveling (Byte 0): 31 => 31
5153 00:38:46.284574 Write leveling (Byte 1): 27 => 27
5154 00:38:46.288141 DramcWriteLeveling(PI) end<-----
5155 00:38:46.288221
5156 00:38:46.288284 ==
5157 00:38:46.291386 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 00:38:46.295241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 00:38:46.298188 ==
5160 00:38:46.298259 [Gating] SW mode calibration
5161 00:38:46.304830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5162 00:38:46.311948 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5163 00:38:46.315412 0 14 0 | B1->B0 | 2323 3131 | 1 0 | (0 0) (0 0)
5164 00:38:46.321505 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5165 00:38:46.324922 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 00:38:46.328224 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 00:38:46.335338 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 00:38:46.338478 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 00:38:46.341230 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 00:38:46.348269 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5171 00:38:46.351440 0 15 0 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 0)
5172 00:38:46.354794 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5173 00:38:46.357892 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 00:38:46.364683 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 00:38:46.368198 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 00:38:46.371548 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 00:38:46.378007 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 00:38:46.381412 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 00:38:46.384920 1 0 0 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
5180 00:38:46.391781 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5181 00:38:46.395517 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 00:38:46.398488 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 00:38:46.404862 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 00:38:46.408468 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 00:38:46.411388 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 00:38:46.418251 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 00:38:46.421751 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 00:38:46.425267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 00:38:46.431547 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 00:38:46.434812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 00:38:46.438596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 00:38:46.441909 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 00:38:46.447972 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 00:38:46.451475 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 00:38:46.454650 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 00:38:46.461546 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 00:38:46.464860 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 00:38:46.468116 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 00:38:46.475051 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 00:38:46.478076 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 00:38:46.481655 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 00:38:46.488024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 00:38:46.491447 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 00:38:46.494607 Total UI for P1: 0, mck2ui 16
5205 00:38:46.498194 best dqsien dly found for B0: ( 1, 2, 30)
5206 00:38:46.501242 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5207 00:38:46.508431 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 00:38:46.508515 Total UI for P1: 0, mck2ui 16
5209 00:38:46.516128 best dqsien dly found for B1: ( 1, 3, 2)
5210 00:38:46.519535 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5211 00:38:46.521656 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5212 00:38:46.521728
5213 00:38:46.524689 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5214 00:38:46.527929 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5215 00:38:46.531401 [Gating] SW calibration Done
5216 00:38:46.531481 ==
5217 00:38:46.534545 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 00:38:46.538259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 00:38:46.538330 ==
5220 00:38:46.541372 RX Vref Scan: 0
5221 00:38:46.541440
5222 00:38:46.541499 RX Vref 0 -> 0, step: 1
5223 00:38:46.541557
5224 00:38:46.544752 RX Delay -80 -> 252, step: 8
5225 00:38:46.547787 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5226 00:38:46.551823 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5227 00:38:46.558367 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5228 00:38:46.561423 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5229 00:38:46.564509 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5230 00:38:46.568220 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5231 00:38:46.571219 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5232 00:38:46.574518 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5233 00:38:46.581526 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5234 00:38:46.584592 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5235 00:38:46.587921 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5236 00:38:46.591033 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5237 00:38:46.594740 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5238 00:38:46.601416 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5239 00:38:46.604518 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5240 00:38:46.607946 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5241 00:38:46.608026 ==
5242 00:38:46.611314 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 00:38:46.614924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 00:38:46.615005 ==
5245 00:38:46.617734 DQS Delay:
5246 00:38:46.617814 DQS0 = 0, DQS1 = 0
5247 00:38:46.617878 DQM Delay:
5248 00:38:46.621037 DQM0 = 98, DQM1 = 88
5249 00:38:46.621132 DQ Delay:
5250 00:38:46.624439 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5251 00:38:46.627755 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5252 00:38:46.631721 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5253 00:38:46.634642 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5254 00:38:46.634722
5255 00:38:46.634786
5256 00:38:46.634844 ==
5257 00:38:46.637588 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 00:38:46.645052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 00:38:46.645134 ==
5260 00:38:46.645200
5261 00:38:46.645261
5262 00:38:46.647661 TX Vref Scan disable
5263 00:38:46.647732 == TX Byte 0 ==
5264 00:38:46.651496 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5265 00:38:46.657686 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5266 00:38:46.657764 == TX Byte 1 ==
5267 00:38:46.661135 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5268 00:38:46.668368 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5269 00:38:46.668442 ==
5270 00:38:46.670751 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 00:38:46.675002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 00:38:46.675081 ==
5273 00:38:46.675144
5274 00:38:46.675203
5275 00:38:46.677672 TX Vref Scan disable
5276 00:38:46.681034 == TX Byte 0 ==
5277 00:38:46.684335 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5278 00:38:46.687720 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5279 00:38:46.691215 == TX Byte 1 ==
5280 00:38:46.694440 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5281 00:38:46.697536 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5282 00:38:46.697610
5283 00:38:46.697671 [DATLAT]
5284 00:38:46.700948 Freq=933, CH0 RK0
5285 00:38:46.701042
5286 00:38:46.704352 DATLAT Default: 0xd
5287 00:38:46.704418 0, 0xFFFF, sum = 0
5288 00:38:46.708197 1, 0xFFFF, sum = 0
5289 00:38:46.708280 2, 0xFFFF, sum = 0
5290 00:38:46.711282 3, 0xFFFF, sum = 0
5291 00:38:46.711364 4, 0xFFFF, sum = 0
5292 00:38:46.714349 5, 0xFFFF, sum = 0
5293 00:38:46.714430 6, 0xFFFF, sum = 0
5294 00:38:46.717785 7, 0xFFFF, sum = 0
5295 00:38:46.717866 8, 0xFFFF, sum = 0
5296 00:38:46.721246 9, 0xFFFF, sum = 0
5297 00:38:46.721328 10, 0x0, sum = 1
5298 00:38:46.724557 11, 0x0, sum = 2
5299 00:38:46.724647 12, 0x0, sum = 3
5300 00:38:46.727599 13, 0x0, sum = 4
5301 00:38:46.727681 best_step = 11
5302 00:38:46.727745
5303 00:38:46.727805 ==
5304 00:38:46.731316 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 00:38:46.734777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 00:38:46.734858 ==
5307 00:38:46.738434 RX Vref Scan: 1
5308 00:38:46.738514
5309 00:38:46.741000 RX Vref 0 -> 0, step: 1
5310 00:38:46.741097
5311 00:38:46.741160 RX Delay -61 -> 252, step: 4
5312 00:38:46.741222
5313 00:38:46.744554 Set Vref, RX VrefLevel [Byte0]: 53
5314 00:38:46.747814 [Byte1]: 52
5315 00:38:46.752391
5316 00:38:46.752471 Final RX Vref Byte 0 = 53 to rank0
5317 00:38:46.755850 Final RX Vref Byte 1 = 52 to rank0
5318 00:38:46.759245 Final RX Vref Byte 0 = 53 to rank1
5319 00:38:46.762717 Final RX Vref Byte 1 = 52 to rank1==
5320 00:38:46.765754 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 00:38:46.772420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 00:38:46.772501 ==
5323 00:38:46.772564 DQS Delay:
5324 00:38:46.772624 DQS0 = 0, DQS1 = 0
5325 00:38:46.775865 DQM Delay:
5326 00:38:46.775945 DQM0 = 97, DQM1 = 88
5327 00:38:46.779343 DQ Delay:
5328 00:38:46.782483 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5329 00:38:46.785674 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5330 00:38:46.785754 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5331 00:38:46.789066 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5332 00:38:46.792460
5333 00:38:46.792539
5334 00:38:46.799103 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5335 00:38:46.802949 CH0 RK0: MR19=504, MR18=12FD
5336 00:38:46.809135 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5337 00:38:46.809216
5338 00:38:46.812852 ----->DramcWriteLeveling(PI) begin...
5339 00:38:46.812933 ==
5340 00:38:46.815951 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 00:38:46.819383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 00:38:46.819464 ==
5343 00:38:46.822611 Write leveling (Byte 0): 30 => 30
5344 00:38:46.825973 Write leveling (Byte 1): 30 => 30
5345 00:38:46.829121 DramcWriteLeveling(PI) end<-----
5346 00:38:46.829197
5347 00:38:46.829261 ==
5348 00:38:46.832414 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 00:38:46.836061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 00:38:46.836134 ==
5351 00:38:46.839940 [Gating] SW mode calibration
5352 00:38:46.846356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 00:38:46.852506 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 00:38:46.855789 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5355 00:38:46.859434 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5356 00:38:46.866609 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 00:38:46.869296 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 00:38:46.872915 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 00:38:46.879469 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 00:38:46.882577 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5361 00:38:46.885839 0 14 28 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (1 1)
5362 00:38:46.892561 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
5363 00:38:46.896156 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 00:38:46.899430 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 00:38:46.902980 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 00:38:46.909558 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 00:38:46.912576 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 00:38:46.916239 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5369 00:38:46.922917 0 15 28 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
5370 00:38:46.926102 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5371 00:38:46.929489 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 00:38:46.936503 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 00:38:46.939471 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 00:38:46.942621 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 00:38:46.949638 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 00:38:46.952700 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5377 00:38:46.956337 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 00:38:46.963005 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5379 00:38:46.966270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 00:38:46.970235 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 00:38:46.975942 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 00:38:46.979638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 00:38:46.982721 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 00:38:46.985907 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 00:38:46.992826 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 00:38:46.996307 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 00:38:46.999425 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 00:38:47.006697 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 00:38:47.009571 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 00:38:47.012834 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 00:38:47.019392 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:38:47.022883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:38:47.026014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5394 00:38:47.032543 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5395 00:38:47.032624 Total UI for P1: 0, mck2ui 16
5396 00:38:47.039521 best dqsien dly found for B0: ( 1, 2, 28)
5397 00:38:47.042965 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5398 00:38:47.045876 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 00:38:47.050042 Total UI for P1: 0, mck2ui 16
5400 00:38:47.053162 best dqsien dly found for B1: ( 1, 3, 2)
5401 00:38:47.056318 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5402 00:38:47.059399 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5403 00:38:47.059479
5404 00:38:47.062570 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5405 00:38:47.069585 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5406 00:38:47.069665 [Gating] SW calibration Done
5407 00:38:47.069730 ==
5408 00:38:47.072933 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 00:38:47.079280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 00:38:47.079361 ==
5411 00:38:47.079425 RX Vref Scan: 0
5412 00:38:47.079483
5413 00:38:47.083089 RX Vref 0 -> 0, step: 1
5414 00:38:47.083169
5415 00:38:47.086058 RX Delay -80 -> 252, step: 8
5416 00:38:47.089771 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5417 00:38:47.092464 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5418 00:38:47.096199 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5419 00:38:47.099294 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5420 00:38:47.105829 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5421 00:38:47.109393 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5422 00:38:47.112670 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5423 00:38:47.115883 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5424 00:38:47.119803 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5425 00:38:47.122740 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5426 00:38:47.129625 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5427 00:38:47.132830 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5428 00:38:47.135909 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5429 00:38:47.139539 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5430 00:38:47.143497 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5431 00:38:47.149669 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5432 00:38:47.149749 ==
5433 00:38:47.153256 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 00:38:47.156218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 00:38:47.156299 ==
5436 00:38:47.156363 DQS Delay:
5437 00:38:47.159431 DQS0 = 0, DQS1 = 0
5438 00:38:47.159512 DQM Delay:
5439 00:38:47.163014 DQM0 = 95, DQM1 = 86
5440 00:38:47.163115 DQ Delay:
5441 00:38:47.165841 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5442 00:38:47.169132 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5443 00:38:47.172754 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5444 00:38:47.176437 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5445 00:38:47.176513
5446 00:38:47.176575
5447 00:38:47.176633 ==
5448 00:38:47.179430 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 00:38:47.182785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 00:38:47.182860 ==
5451 00:38:47.182929
5452 00:38:47.182988
5453 00:38:47.186187 TX Vref Scan disable
5454 00:38:47.189386 == TX Byte 0 ==
5455 00:38:47.192709 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5456 00:38:47.196294 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5457 00:38:47.199844 == TX Byte 1 ==
5458 00:38:47.203023 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5459 00:38:47.206440 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5460 00:38:47.206518 ==
5461 00:38:47.209249 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 00:38:47.212855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 00:38:47.215884 ==
5464 00:38:47.215957
5465 00:38:47.216019
5466 00:38:47.216078 TX Vref Scan disable
5467 00:38:47.219639 == TX Byte 0 ==
5468 00:38:47.223476 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5469 00:38:47.226611 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5470 00:38:47.230316 == TX Byte 1 ==
5471 00:38:47.232894 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5472 00:38:47.237188 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5473 00:38:47.239950
5474 00:38:47.240026 [DATLAT]
5475 00:38:47.240090 Freq=933, CH0 RK1
5476 00:38:47.240158
5477 00:38:47.243091 DATLAT Default: 0xb
5478 00:38:47.243170 0, 0xFFFF, sum = 0
5479 00:38:47.247332 1, 0xFFFF, sum = 0
5480 00:38:47.247425 2, 0xFFFF, sum = 0
5481 00:38:47.249756 3, 0xFFFF, sum = 0
5482 00:38:47.249832 4, 0xFFFF, sum = 0
5483 00:38:47.253276 5, 0xFFFF, sum = 0
5484 00:38:47.256197 6, 0xFFFF, sum = 0
5485 00:38:47.256274 7, 0xFFFF, sum = 0
5486 00:38:47.260020 8, 0xFFFF, sum = 0
5487 00:38:47.260095 9, 0xFFFF, sum = 0
5488 00:38:47.263289 10, 0x0, sum = 1
5489 00:38:47.263368 11, 0x0, sum = 2
5490 00:38:47.263440 12, 0x0, sum = 3
5491 00:38:47.266843 13, 0x0, sum = 4
5492 00:38:47.266918 best_step = 11
5493 00:38:47.266980
5494 00:38:47.267045 ==
5495 00:38:47.269923 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 00:38:47.276276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 00:38:47.276379 ==
5498 00:38:47.276482 RX Vref Scan: 0
5499 00:38:47.276572
5500 00:38:47.280107 RX Vref 0 -> 0, step: 1
5501 00:38:47.280178
5502 00:38:47.283243 RX Delay -69 -> 252, step: 4
5503 00:38:47.286404 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5504 00:38:47.290229 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5505 00:38:47.297038 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5506 00:38:47.300267 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5507 00:38:47.303185 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5508 00:38:47.306792 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5509 00:38:47.310062 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5510 00:38:47.313610 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5511 00:38:47.319754 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5512 00:38:47.323118 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5513 00:38:47.326438 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5514 00:38:47.329911 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5515 00:38:47.333629 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5516 00:38:47.336545 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5517 00:38:47.343070 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5518 00:38:47.346728 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5519 00:38:47.346809 ==
5520 00:38:47.349853 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 00:38:47.353368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 00:38:47.353449 ==
5523 00:38:47.356877 DQS Delay:
5524 00:38:47.356959 DQS0 = 0, DQS1 = 0
5525 00:38:47.357045 DQM Delay:
5526 00:38:47.360299 DQM0 = 95, DQM1 = 88
5527 00:38:47.360381 DQ Delay:
5528 00:38:47.363537 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5529 00:38:47.366665 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =102
5530 00:38:47.370618 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5531 00:38:47.373694 DQ12 =90, DQ13 =94, DQ14 =100, DQ15 =96
5532 00:38:47.373797
5533 00:38:47.373896
5534 00:38:47.383435 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5535 00:38:47.387179 CH0 RK1: MR19=505, MR18=1F0C
5536 00:38:47.390318 CH0_RK1: MR19=0x505, MR18=0x1F0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5537 00:38:47.393081 [RxdqsGatingPostProcess] freq 933
5538 00:38:47.399721 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5539 00:38:47.403132 best DQS0 dly(2T, 0.5T) = (0, 10)
5540 00:38:47.406913 best DQS1 dly(2T, 0.5T) = (0, 11)
5541 00:38:47.409843 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5542 00:38:47.413286 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5543 00:38:47.416966 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 00:38:47.417071 best DQS1 dly(2T, 0.5T) = (0, 11)
5545 00:38:47.419874 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 00:38:47.423369 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5547 00:38:47.426726 Pre-setting of DQS Precalculation
5548 00:38:47.433114 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5549 00:38:47.433195 ==
5550 00:38:47.437021 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 00:38:47.440072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 00:38:47.440147 ==
5553 00:38:47.447179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 00:38:47.453087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5555 00:38:47.456676 [CA 0] Center 36 (6~67) winsize 62
5556 00:38:47.459827 [CA 1] Center 36 (6~67) winsize 62
5557 00:38:47.463361 [CA 2] Center 34 (4~64) winsize 61
5558 00:38:47.466849 [CA 3] Center 33 (3~64) winsize 62
5559 00:38:47.470080 [CA 4] Center 34 (4~64) winsize 61
5560 00:38:47.473920 [CA 5] Center 33 (3~64) winsize 62
5561 00:38:47.473996
5562 00:38:47.476518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5563 00:38:47.476596
5564 00:38:47.480194 [CATrainingPosCal] consider 1 rank data
5565 00:38:47.483180 u2DelayCellTimex100 = 270/100 ps
5566 00:38:47.486881 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 00:38:47.489628 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5568 00:38:47.493371 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 00:38:47.497086 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 00:38:47.499702 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 00:38:47.504218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 00:38:47.504295
5573 00:38:47.506498 CA PerBit enable=1, Macro0, CA PI delay=33
5574 00:38:47.506574
5575 00:38:47.510128 [CBTSetCACLKResult] CA Dly = 33
5576 00:38:47.513285 CS Dly: 4 (0~35)
5577 00:38:47.513362 ==
5578 00:38:47.516605 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 00:38:47.520927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 00:38:47.521043 ==
5581 00:38:47.526759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 00:38:47.533282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5583 00:38:47.536942 [CA 0] Center 36 (6~67) winsize 62
5584 00:38:47.540058 [CA 1] Center 37 (7~67) winsize 61
5585 00:38:47.543112 [CA 2] Center 33 (3~64) winsize 62
5586 00:38:47.546682 [CA 3] Center 33 (3~64) winsize 62
5587 00:38:47.550252 [CA 4] Center 34 (4~65) winsize 62
5588 00:38:47.550326 [CA 5] Center 32 (2~63) winsize 62
5589 00:38:47.553353
5590 00:38:47.556789 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5591 00:38:47.556893
5592 00:38:47.560140 [CATrainingPosCal] consider 2 rank data
5593 00:38:47.563690 u2DelayCellTimex100 = 270/100 ps
5594 00:38:47.567220 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 00:38:47.570601 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 00:38:47.573319 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5597 00:38:47.577502 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 00:38:47.580478 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5599 00:38:47.583521 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5600 00:38:47.583594
5601 00:38:47.587523 CA PerBit enable=1, Macro0, CA PI delay=33
5602 00:38:47.587607
5603 00:38:47.590090 [CBTSetCACLKResult] CA Dly = 33
5604 00:38:47.594042 CS Dly: 5 (0~37)
5605 00:38:47.594118
5606 00:38:47.597199 ----->DramcWriteLeveling(PI) begin...
5607 00:38:47.597277 ==
5608 00:38:47.600271 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 00:38:47.603590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 00:38:47.603665 ==
5611 00:38:47.607521 Write leveling (Byte 0): 27 => 27
5612 00:38:47.610385 Write leveling (Byte 1): 28 => 28
5613 00:38:47.613481 DramcWriteLeveling(PI) end<-----
5614 00:38:47.613557
5615 00:38:47.613620 ==
5616 00:38:47.617762 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 00:38:47.620317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 00:38:47.620398 ==
5619 00:38:47.623945 [Gating] SW mode calibration
5620 00:38:47.630542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5621 00:38:47.637070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5622 00:38:47.640781 0 14 0 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (1 1)
5623 00:38:47.643734 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 00:38:47.650635 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 00:38:47.654189 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 00:38:47.656877 0 14 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5627 00:38:47.663820 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5628 00:38:47.667315 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 00:38:47.670608 0 14 28 | B1->B0 | 3030 3030 | 0 1 | (0 0) (1 0)
5630 00:38:47.677428 0 15 0 | B1->B0 | 2b2b 2c2c | 1 0 | (1 0) (1 0)
5631 00:38:47.680257 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 00:38:47.683764 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 00:38:47.690808 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 00:38:47.693571 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 00:38:47.697069 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 00:38:47.703773 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 00:38:47.707666 0 15 28 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
5638 00:38:47.710288 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 00:38:47.714810 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 00:38:47.720707 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 00:38:47.723838 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 00:38:47.727608 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 00:38:47.733707 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 00:38:47.737010 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 00:38:47.740786 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 00:38:47.747183 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 00:38:47.751176 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 00:38:47.754050 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 00:38:47.761979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 00:38:47.764231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 00:38:47.767361 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 00:38:47.774141 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 00:38:47.777166 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 00:38:47.780833 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 00:38:47.787431 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 00:38:47.790682 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 00:38:47.794007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 00:38:47.797192 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 00:38:47.804171 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 00:38:47.807501 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 00:38:47.810789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5662 00:38:47.817228 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5663 00:38:47.817308 Total UI for P1: 0, mck2ui 16
5664 00:38:47.824220 best dqsien dly found for B1: ( 1, 2, 28)
5665 00:38:47.827534 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 00:38:47.831534 Total UI for P1: 0, mck2ui 16
5667 00:38:47.833913 best dqsien dly found for B0: ( 1, 2, 30)
5668 00:38:47.837296 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5669 00:38:47.841565 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5670 00:38:47.841646
5671 00:38:47.844011 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5672 00:38:47.847241 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5673 00:38:47.850794 [Gating] SW calibration Done
5674 00:38:47.850875 ==
5675 00:38:47.854334 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 00:38:47.857953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 00:38:47.858034 ==
5678 00:38:47.861356 RX Vref Scan: 0
5679 00:38:47.861436
5680 00:38:47.864057 RX Vref 0 -> 0, step: 1
5681 00:38:47.864137
5682 00:38:47.864201 RX Delay -80 -> 252, step: 8
5683 00:38:47.871182 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5684 00:38:47.874092 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5685 00:38:47.877999 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5686 00:38:47.881754 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5687 00:38:47.884741 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5688 00:38:47.887559 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5689 00:38:47.894530 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5690 00:38:47.897748 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5691 00:38:47.901490 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5692 00:38:47.905110 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5693 00:38:47.907545 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5694 00:38:47.911338 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5695 00:38:47.917896 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5696 00:38:47.920932 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5697 00:38:47.924843 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5698 00:38:47.928218 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5699 00:38:47.928300 ==
5700 00:38:47.931033 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 00:38:47.934776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 00:38:47.938089 ==
5703 00:38:47.938170 DQS Delay:
5704 00:38:47.938234 DQS0 = 0, DQS1 = 0
5705 00:38:47.940962 DQM Delay:
5706 00:38:47.941078 DQM0 = 95, DQM1 = 89
5707 00:38:47.945016 DQ Delay:
5708 00:38:47.945097 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5709 00:38:47.948039 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5710 00:38:47.950791 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5711 00:38:47.954262 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5712 00:38:47.957884
5713 00:38:47.957963
5714 00:38:47.958027 ==
5715 00:38:47.960745 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 00:38:47.964160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 00:38:47.964241 ==
5718 00:38:47.964304
5719 00:38:47.964362
5720 00:38:47.967618 TX Vref Scan disable
5721 00:38:47.967698 == TX Byte 0 ==
5722 00:38:47.974588 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5723 00:38:47.978107 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5724 00:38:47.978188 == TX Byte 1 ==
5725 00:38:47.984641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5726 00:38:47.987456 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5727 00:38:47.987537 ==
5728 00:38:47.991063 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 00:38:47.994614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 00:38:47.994695 ==
5731 00:38:47.994758
5732 00:38:47.994816
5733 00:38:47.997299 TX Vref Scan disable
5734 00:38:48.000698 == TX Byte 0 ==
5735 00:38:48.004434 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 00:38:48.007466 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 00:38:48.010619 == TX Byte 1 ==
5738 00:38:48.014117 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5739 00:38:48.017432 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5740 00:38:48.017516
5741 00:38:48.020857 [DATLAT]
5742 00:38:48.020937 Freq=933, CH1 RK0
5743 00:38:48.021040
5744 00:38:48.024147 DATLAT Default: 0xd
5745 00:38:48.024227 0, 0xFFFF, sum = 0
5746 00:38:48.027329 1, 0xFFFF, sum = 0
5747 00:38:48.027411 2, 0xFFFF, sum = 0
5748 00:38:48.031091 3, 0xFFFF, sum = 0
5749 00:38:48.031172 4, 0xFFFF, sum = 0
5750 00:38:48.034014 5, 0xFFFF, sum = 0
5751 00:38:48.034095 6, 0xFFFF, sum = 0
5752 00:38:48.037384 7, 0xFFFF, sum = 0
5753 00:38:48.037466 8, 0xFFFF, sum = 0
5754 00:38:48.041216 9, 0xFFFF, sum = 0
5755 00:38:48.041298 10, 0x0, sum = 1
5756 00:38:48.044356 11, 0x0, sum = 2
5757 00:38:48.044437 12, 0x0, sum = 3
5758 00:38:48.047648 13, 0x0, sum = 4
5759 00:38:48.047730 best_step = 11
5760 00:38:48.047793
5761 00:38:48.047852 ==
5762 00:38:48.050858 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 00:38:48.054431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 00:38:48.057629 ==
5765 00:38:48.057709 RX Vref Scan: 1
5766 00:38:48.057772
5767 00:38:48.061375 RX Vref 0 -> 0, step: 1
5768 00:38:48.061455
5769 00:38:48.061519 RX Delay -61 -> 252, step: 4
5770 00:38:48.064190
5771 00:38:48.064270 Set Vref, RX VrefLevel [Byte0]: 56
5772 00:38:48.067299 [Byte1]: 50
5773 00:38:48.072658
5774 00:38:48.072737 Final RX Vref Byte 0 = 56 to rank0
5775 00:38:48.075938 Final RX Vref Byte 1 = 50 to rank0
5776 00:38:48.079206 Final RX Vref Byte 0 = 56 to rank1
5777 00:38:48.083020 Final RX Vref Byte 1 = 50 to rank1==
5778 00:38:48.086380 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 00:38:48.092313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 00:38:48.092393 ==
5781 00:38:48.092457 DQS Delay:
5782 00:38:48.092515 DQS0 = 0, DQS1 = 0
5783 00:38:48.096046 DQM Delay:
5784 00:38:48.096126 DQM0 = 97, DQM1 = 91
5785 00:38:48.099576 DQ Delay:
5786 00:38:48.102260 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5787 00:38:48.106209 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =94
5788 00:38:48.109351 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =84
5789 00:38:48.112715 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =96
5790 00:38:48.112797
5791 00:38:48.112861
5792 00:38:48.119050 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5793 00:38:48.122900 CH1 RK0: MR19=504, MR18=15F2
5794 00:38:48.129506 CH1_RK0: MR19=0x504, MR18=0x15F2, DQSOSC=415, MR23=63, INC=62, DEC=41
5795 00:38:48.129587
5796 00:38:48.132722 ----->DramcWriteLeveling(PI) begin...
5797 00:38:48.132804 ==
5798 00:38:48.136146 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 00:38:48.139186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 00:38:48.139267 ==
5801 00:38:48.142969 Write leveling (Byte 0): 27 => 27
5802 00:38:48.145771 Write leveling (Byte 1): 28 => 28
5803 00:38:48.149334 DramcWriteLeveling(PI) end<-----
5804 00:38:48.149414
5805 00:38:48.149478 ==
5806 00:38:48.153042 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 00:38:48.156202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 00:38:48.156283 ==
5809 00:38:48.159153 [Gating] SW mode calibration
5810 00:38:48.165927 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 00:38:48.173153 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 00:38:48.176524 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 00:38:48.179710 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 00:38:48.185981 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 00:38:48.189705 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 00:38:48.193252 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 00:38:48.199851 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5818 00:38:48.203021 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 0)
5819 00:38:48.206365 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5820 00:38:48.212432 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 00:38:48.216085 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 00:38:48.219875 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 00:38:48.225861 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 00:38:48.229017 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 00:38:48.232527 0 15 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5826 00:38:48.239176 0 15 24 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
5827 00:38:48.242846 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5828 00:38:48.246219 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 00:38:48.252679 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 00:38:48.256175 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 00:38:48.259255 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 00:38:48.263567 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 00:38:48.270423 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5834 00:38:48.272400 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5835 00:38:48.275697 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5836 00:38:48.282512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 00:38:48.286338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 00:38:48.289104 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 00:38:48.295741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 00:38:48.299937 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 00:38:48.303486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 00:38:48.309271 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 00:38:48.313407 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 00:38:48.315864 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 00:38:48.322513 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 00:38:48.326402 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 00:38:48.329170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 00:38:48.336255 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 00:38:48.339124 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:38:48.342904 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5851 00:38:48.346180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5852 00:38:48.349840 Total UI for P1: 0, mck2ui 16
5853 00:38:48.352614 best dqsien dly found for B0: ( 1, 2, 24)
5854 00:38:48.359132 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 00:38:48.363125 Total UI for P1: 0, mck2ui 16
5856 00:38:48.366398 best dqsien dly found for B1: ( 1, 2, 26)
5857 00:38:48.369489 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5858 00:38:48.372515 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5859 00:38:48.372589
5860 00:38:48.375947 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5861 00:38:48.379824 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5862 00:38:48.383237 [Gating] SW calibration Done
5863 00:38:48.383311 ==
5864 00:38:48.386367 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 00:38:48.389329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 00:38:48.389402 ==
5867 00:38:48.392849 RX Vref Scan: 0
5868 00:38:48.392947
5869 00:38:48.393032 RX Vref 0 -> 0, step: 1
5870 00:38:48.395890
5871 00:38:48.395960 RX Delay -80 -> 252, step: 8
5872 00:38:48.402677 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5873 00:38:48.406240 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5874 00:38:48.410039 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5875 00:38:48.412854 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5876 00:38:48.416166 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5877 00:38:48.419287 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5878 00:38:48.422809 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5879 00:38:48.429239 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5880 00:38:48.433382 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5881 00:38:48.435977 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5882 00:38:48.439829 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5883 00:38:48.442749 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5884 00:38:48.446116 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5885 00:38:48.452699 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5886 00:38:48.455973 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5887 00:38:48.459446 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5888 00:38:48.459521 ==
5889 00:38:48.462737 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 00:38:48.466415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 00:38:48.466491 ==
5892 00:38:48.469869 DQS Delay:
5893 00:38:48.469948 DQS0 = 0, DQS1 = 0
5894 00:38:48.470010 DQM Delay:
5895 00:38:48.473352 DQM0 = 94, DQM1 = 88
5896 00:38:48.473431 DQ Delay:
5897 00:38:48.476414 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5898 00:38:48.479438 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5899 00:38:48.482963 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5900 00:38:48.486369 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5901 00:38:48.486451
5902 00:38:48.486515
5903 00:38:48.486573 ==
5904 00:38:48.489438 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 00:38:48.496226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 00:38:48.496307 ==
5907 00:38:48.496370
5908 00:38:48.496429
5909 00:38:48.496485 TX Vref Scan disable
5910 00:38:48.499865 == TX Byte 0 ==
5911 00:38:48.503118 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 00:38:48.510268 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 00:38:48.510350 == TX Byte 1 ==
5914 00:38:48.513519 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5915 00:38:48.516706 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5916 00:38:48.520233 ==
5917 00:38:48.523280 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 00:38:48.526580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 00:38:48.526660 ==
5920 00:38:48.526732
5921 00:38:48.526793
5922 00:38:48.530308 TX Vref Scan disable
5923 00:38:48.530387 == TX Byte 0 ==
5924 00:38:48.536808 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 00:38:48.540358 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 00:38:48.540455 == TX Byte 1 ==
5927 00:38:48.546465 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5928 00:38:48.549953 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5929 00:38:48.550034
5930 00:38:48.550098 [DATLAT]
5931 00:38:48.553250 Freq=933, CH1 RK1
5932 00:38:48.553331
5933 00:38:48.553395 DATLAT Default: 0xb
5934 00:38:48.556684 0, 0xFFFF, sum = 0
5935 00:38:48.556766 1, 0xFFFF, sum = 0
5936 00:38:48.560158 2, 0xFFFF, sum = 0
5937 00:38:48.560240 3, 0xFFFF, sum = 0
5938 00:38:48.563378 4, 0xFFFF, sum = 0
5939 00:38:48.563460 5, 0xFFFF, sum = 0
5940 00:38:48.567040 6, 0xFFFF, sum = 0
5941 00:38:48.567122 7, 0xFFFF, sum = 0
5942 00:38:48.569965 8, 0xFFFF, sum = 0
5943 00:38:48.570047 9, 0xFFFF, sum = 0
5944 00:38:48.573271 10, 0x0, sum = 1
5945 00:38:48.573353 11, 0x0, sum = 2
5946 00:38:48.576498 12, 0x0, sum = 3
5947 00:38:48.576579 13, 0x0, sum = 4
5948 00:38:48.580851 best_step = 11
5949 00:38:48.580947
5950 00:38:48.581032 ==
5951 00:38:48.583337 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 00:38:48.586951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 00:38:48.587032 ==
5954 00:38:48.590073 RX Vref Scan: 0
5955 00:38:48.590153
5956 00:38:48.590216 RX Vref 0 -> 0, step: 1
5957 00:38:48.590275
5958 00:38:48.594901 RX Delay -61 -> 252, step: 4
5959 00:38:48.600253 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5960 00:38:48.603842 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5961 00:38:48.607408 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5962 00:38:48.610699 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5963 00:38:48.614067 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5964 00:38:48.616888 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5965 00:38:48.623740 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5966 00:38:48.627224 iDelay=199, Bit 7, Center 88 (-1 ~ 178) 180
5967 00:38:48.630438 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5968 00:38:48.633923 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5969 00:38:48.636901 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5970 00:38:48.643628 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5971 00:38:48.647153 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5972 00:38:48.650696 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5973 00:38:48.653755 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5974 00:38:48.656863 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5975 00:38:48.656943 ==
5976 00:38:48.660947 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 00:38:48.666803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 00:38:48.666884 ==
5979 00:38:48.666949 DQS Delay:
5980 00:38:48.670761 DQS0 = 0, DQS1 = 0
5981 00:38:48.670850 DQM Delay:
5982 00:38:48.670940 DQM0 = 95, DQM1 = 90
5983 00:38:48.673938 DQ Delay:
5984 00:38:48.676817 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5985 00:38:48.680205 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =88
5986 00:38:48.683869 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
5987 00:38:48.686930 DQ12 =96, DQ13 =100, DQ14 =100, DQ15 =98
5988 00:38:48.687006
5989 00:38:48.687070
5990 00:38:48.693772 [DQSOSCAuto] RK1, (LSB)MR18= 0xe18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5991 00:38:48.697219 CH1 RK1: MR19=505, MR18=E18
5992 00:38:48.703564 CH1_RK1: MR19=0x505, MR18=0xE18, DQSOSC=414, MR23=63, INC=63, DEC=42
5993 00:38:48.706864 [RxdqsGatingPostProcess] freq 933
5994 00:38:48.710223 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 00:38:48.713405 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 00:38:48.717211 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 00:38:48.720014 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 00:38:48.723673 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 00:38:48.726974 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 00:38:48.730344 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 00:38:48.733459 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 00:38:48.737124 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 00:38:48.740111 Pre-setting of DQS Precalculation
6004 00:38:48.743939 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 00:38:48.750610 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 00:38:48.760024 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 00:38:48.760103
6008 00:38:48.760174
6009 00:38:48.763395 [Calibration Summary] 1866 Mbps
6010 00:38:48.763471 CH 0, Rank 0
6011 00:38:48.766751 SW Impedance : PASS
6012 00:38:48.766832 DUTY Scan : NO K
6013 00:38:48.770473 ZQ Calibration : PASS
6014 00:38:48.770547 Jitter Meter : NO K
6015 00:38:48.773896 CBT Training : PASS
6016 00:38:48.777029 Write leveling : PASS
6017 00:38:48.777107 RX DQS gating : PASS
6018 00:38:48.780334 RX DQ/DQS(RDDQC) : PASS
6019 00:38:48.784035 TX DQ/DQS : PASS
6020 00:38:48.784110 RX DATLAT : PASS
6021 00:38:48.787054 RX DQ/DQS(Engine): PASS
6022 00:38:48.790179 TX OE : NO K
6023 00:38:48.790260 All Pass.
6024 00:38:48.790324
6025 00:38:48.790382 CH 0, Rank 1
6026 00:38:48.793747 SW Impedance : PASS
6027 00:38:48.797090 DUTY Scan : NO K
6028 00:38:48.797172 ZQ Calibration : PASS
6029 00:38:48.800409 Jitter Meter : NO K
6030 00:38:48.803959 CBT Training : PASS
6031 00:38:48.804040 Write leveling : PASS
6032 00:38:48.807084 RX DQS gating : PASS
6033 00:38:48.807165 RX DQ/DQS(RDDQC) : PASS
6034 00:38:48.810720 TX DQ/DQS : PASS
6035 00:38:48.813739 RX DATLAT : PASS
6036 00:38:48.813824 RX DQ/DQS(Engine): PASS
6037 00:38:48.817474 TX OE : NO K
6038 00:38:48.817556 All Pass.
6039 00:38:48.817620
6040 00:38:48.820289 CH 1, Rank 0
6041 00:38:48.820369 SW Impedance : PASS
6042 00:38:48.823775 DUTY Scan : NO K
6043 00:38:48.827192 ZQ Calibration : PASS
6044 00:38:48.827274 Jitter Meter : NO K
6045 00:38:48.830694 CBT Training : PASS
6046 00:38:48.834871 Write leveling : PASS
6047 00:38:48.834977 RX DQS gating : PASS
6048 00:38:48.837058 RX DQ/DQS(RDDQC) : PASS
6049 00:38:48.841008 TX DQ/DQS : PASS
6050 00:38:48.841123 RX DATLAT : PASS
6051 00:38:48.843858 RX DQ/DQS(Engine): PASS
6052 00:38:48.847287 TX OE : NO K
6053 00:38:48.847407 All Pass.
6054 00:38:48.847519
6055 00:38:48.847630 CH 1, Rank 1
6056 00:38:48.851904 SW Impedance : PASS
6057 00:38:48.852004 DUTY Scan : NO K
6058 00:38:48.854082 ZQ Calibration : PASS
6059 00:38:48.857454 Jitter Meter : NO K
6060 00:38:48.857554 CBT Training : PASS
6061 00:38:48.860280 Write leveling : PASS
6062 00:38:48.863778 RX DQS gating : PASS
6063 00:38:48.863903 RX DQ/DQS(RDDQC) : PASS
6064 00:38:48.867246 TX DQ/DQS : PASS
6065 00:38:48.870461 RX DATLAT : PASS
6066 00:38:48.870542 RX DQ/DQS(Engine): PASS
6067 00:38:48.873768 TX OE : NO K
6068 00:38:48.873850 All Pass.
6069 00:38:48.873914
6070 00:38:48.877442 DramC Write-DBI off
6071 00:38:48.880790 PER_BANK_REFRESH: Hybrid Mode
6072 00:38:48.880876 TX_TRACKING: ON
6073 00:38:48.890385 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 00:38:48.894198 [FAST_K] Save calibration result to emmc
6075 00:38:48.897599 dramc_set_vcore_voltage set vcore to 650000
6076 00:38:48.900580 Read voltage for 400, 6
6077 00:38:48.900680 Vio18 = 0
6078 00:38:48.900754 Vcore = 650000
6079 00:38:48.904005 Vdram = 0
6080 00:38:48.904077 Vddq = 0
6081 00:38:48.904146 Vmddr = 0
6082 00:38:48.911025 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 00:38:48.914110 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 00:38:48.917483 MEM_TYPE=3, freq_sel=20
6085 00:38:48.920574 sv_algorithm_assistance_LP4_800
6086 00:38:48.924249 ============ PULL DRAM RESETB DOWN ============
6087 00:38:48.927344 ========== PULL DRAM RESETB DOWN end =========
6088 00:38:48.934264 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 00:38:48.937374 ===================================
6090 00:38:48.937451 LPDDR4 DRAM CONFIGURATION
6091 00:38:48.940675 ===================================
6092 00:38:48.944286 EX_ROW_EN[0] = 0x0
6093 00:38:48.947216 EX_ROW_EN[1] = 0x0
6094 00:38:48.947297 LP4Y_EN = 0x0
6095 00:38:48.950642 WORK_FSP = 0x0
6096 00:38:48.950717 WL = 0x2
6097 00:38:48.954565 RL = 0x2
6098 00:38:48.954641 BL = 0x2
6099 00:38:48.957373 RPST = 0x0
6100 00:38:48.957447 RD_PRE = 0x0
6101 00:38:48.960994 WR_PRE = 0x1
6102 00:38:48.961073 WR_PST = 0x0
6103 00:38:48.964443 DBI_WR = 0x0
6104 00:38:48.964523 DBI_RD = 0x0
6105 00:38:48.968208 OTF = 0x1
6106 00:38:48.970827 ===================================
6107 00:38:48.973784 ===================================
6108 00:38:48.973866 ANA top config
6109 00:38:48.977536 ===================================
6110 00:38:48.980909 DLL_ASYNC_EN = 0
6111 00:38:48.983891 ALL_SLAVE_EN = 1
6112 00:38:48.983971 NEW_RANK_MODE = 1
6113 00:38:48.987221 DLL_IDLE_MODE = 1
6114 00:38:48.990678 LP45_APHY_COMB_EN = 1
6115 00:38:48.993989 TX_ODT_DIS = 1
6116 00:38:48.997495 NEW_8X_MODE = 1
6117 00:38:49.001219 ===================================
6118 00:38:49.004341 ===================================
6119 00:38:49.004422 data_rate = 800
6120 00:38:49.007396 CKR = 1
6121 00:38:49.010170 DQ_P2S_RATIO = 4
6122 00:38:49.013863 ===================================
6123 00:38:49.017369 CA_P2S_RATIO = 4
6124 00:38:49.020306 DQ_CA_OPEN = 0
6125 00:38:49.024006 DQ_SEMI_OPEN = 1
6126 00:38:49.024090 CA_SEMI_OPEN = 1
6127 00:38:49.026986 CA_FULL_RATE = 0
6128 00:38:49.030427 DQ_CKDIV4_EN = 0
6129 00:38:49.033960 CA_CKDIV4_EN = 1
6130 00:38:49.037220 CA_PREDIV_EN = 0
6131 00:38:49.040728 PH8_DLY = 0
6132 00:38:49.040808 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 00:38:49.043478 DQ_AAMCK_DIV = 0
6134 00:38:49.046888 CA_AAMCK_DIV = 0
6135 00:38:49.050097 CA_ADMCK_DIV = 4
6136 00:38:49.053805 DQ_TRACK_CA_EN = 0
6137 00:38:49.056641 CA_PICK = 800
6138 00:38:49.060662 CA_MCKIO = 400
6139 00:38:49.060742 MCKIO_SEMI = 400
6140 00:38:49.063955 PLL_FREQ = 3016
6141 00:38:49.066964 DQ_UI_PI_RATIO = 32
6142 00:38:49.070337 CA_UI_PI_RATIO = 32
6143 00:38:49.074628 ===================================
6144 00:38:49.077240 ===================================
6145 00:38:49.080416 memory_type:LPDDR4
6146 00:38:49.080497 GP_NUM : 10
6147 00:38:49.083795 SRAM_EN : 1
6148 00:38:49.083876 MD32_EN : 0
6149 00:38:49.087408 ===================================
6150 00:38:49.090447 [ANA_INIT] >>>>>>>>>>>>>>
6151 00:38:49.093930 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 00:38:49.097530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 00:38:49.100412 ===================================
6154 00:38:49.103564 data_rate = 800,PCW = 0X7400
6155 00:38:49.107030 ===================================
6156 00:38:49.110306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 00:38:49.116689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 00:38:49.126817 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 00:38:49.130154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 00:38:49.133631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 00:38:49.137186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 00:38:49.140416 [ANA_INIT] flow start
6163 00:38:49.143729 [ANA_INIT] PLL >>>>>>>>
6164 00:38:49.143809 [ANA_INIT] PLL <<<<<<<<
6165 00:38:49.146831 [ANA_INIT] MIDPI >>>>>>>>
6166 00:38:49.150302 [ANA_INIT] MIDPI <<<<<<<<
6167 00:38:49.154136 [ANA_INIT] DLL >>>>>>>>
6168 00:38:49.154216 [ANA_INIT] flow end
6169 00:38:49.156926 ============ LP4 DIFF to SE enter ============
6170 00:38:49.163206 ============ LP4 DIFF to SE exit ============
6171 00:38:49.163287 [ANA_INIT] <<<<<<<<<<<<<
6172 00:38:49.167113 [Flow] Enable top DCM control >>>>>
6173 00:38:49.170773 [Flow] Enable top DCM control <<<<<
6174 00:38:49.173306 Enable DLL master slave shuffle
6175 00:38:49.180611 ==============================================================
6176 00:38:49.180692 Gating Mode config
6177 00:38:49.187069 ==============================================================
6178 00:38:49.190205 Config description:
6179 00:38:49.196888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 00:38:49.203539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 00:38:49.210167 SELPH_MODE 0: By rank 1: By Phase
6182 00:38:49.216637 ==============================================================
6183 00:38:49.216747 GAT_TRACK_EN = 0
6184 00:38:49.220524 RX_GATING_MODE = 2
6185 00:38:49.223792 RX_GATING_TRACK_MODE = 2
6186 00:38:49.226692 SELPH_MODE = 1
6187 00:38:49.230775 PICG_EARLY_EN = 1
6188 00:38:49.233842 VALID_LAT_VALUE = 1
6189 00:38:49.240164 ==============================================================
6190 00:38:49.243888 Enter into Gating configuration >>>>
6191 00:38:49.247013 Exit from Gating configuration <<<<
6192 00:38:49.250306 Enter into DVFS_PRE_config >>>>>
6193 00:38:49.260752 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 00:38:49.263865 Exit from DVFS_PRE_config <<<<<
6195 00:38:49.266806 Enter into PICG configuration >>>>
6196 00:38:49.270515 Exit from PICG configuration <<<<
6197 00:38:49.270599 [RX_INPUT] configuration >>>>>
6198 00:38:49.273464 [RX_INPUT] configuration <<<<<
6199 00:38:49.280503 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 00:38:49.284243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 00:38:49.290984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 00:38:49.297096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 00:38:49.303962 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 00:38:49.310526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 00:38:49.313519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 00:38:49.316869 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 00:38:49.323923 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 00:38:49.327110 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 00:38:49.330334 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 00:38:49.333838 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 00:38:49.337508 ===================================
6212 00:38:49.340213 LPDDR4 DRAM CONFIGURATION
6213 00:38:49.343717 ===================================
6214 00:38:49.347172 EX_ROW_EN[0] = 0x0
6215 00:38:49.347254 EX_ROW_EN[1] = 0x0
6216 00:38:49.350941 LP4Y_EN = 0x0
6217 00:38:49.351018 WORK_FSP = 0x0
6218 00:38:49.353908 WL = 0x2
6219 00:38:49.353983 RL = 0x2
6220 00:38:49.356779 BL = 0x2
6221 00:38:49.356851 RPST = 0x0
6222 00:38:49.360516 RD_PRE = 0x0
6223 00:38:49.360590 WR_PRE = 0x1
6224 00:38:49.363885 WR_PST = 0x0
6225 00:38:49.363960 DBI_WR = 0x0
6226 00:38:49.367031 DBI_RD = 0x0
6227 00:38:49.367106 OTF = 0x1
6228 00:38:49.370154 ===================================
6229 00:38:49.376858 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 00:38:49.380512 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 00:38:49.383738 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 00:38:49.387164 ===================================
6233 00:38:49.390569 LPDDR4 DRAM CONFIGURATION
6234 00:38:49.393951 ===================================
6235 00:38:49.394028 EX_ROW_EN[0] = 0x10
6236 00:38:49.398954 EX_ROW_EN[1] = 0x0
6237 00:38:49.400778 LP4Y_EN = 0x0
6238 00:38:49.400870 WORK_FSP = 0x0
6239 00:38:49.404070 WL = 0x2
6240 00:38:49.404141 RL = 0x2
6241 00:38:49.407508 BL = 0x2
6242 00:38:49.407587 RPST = 0x0
6243 00:38:49.410620 RD_PRE = 0x0
6244 00:38:49.410745 WR_PRE = 0x1
6245 00:38:49.413794 WR_PST = 0x0
6246 00:38:49.413876 DBI_WR = 0x0
6247 00:38:49.417549 DBI_RD = 0x0
6248 00:38:49.417630 OTF = 0x1
6249 00:38:49.421073 ===================================
6250 00:38:49.427662 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 00:38:49.431578 nWR fixed to 30
6252 00:38:49.434850 [ModeRegInit_LP4] CH0 RK0
6253 00:38:49.434931 [ModeRegInit_LP4] CH0 RK1
6254 00:38:49.437956 [ModeRegInit_LP4] CH1 RK0
6255 00:38:49.441763 [ModeRegInit_LP4] CH1 RK1
6256 00:38:49.441844 match AC timing 19
6257 00:38:49.448623 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 00:38:49.451270 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 00:38:49.455060 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 00:38:49.461193 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 00:38:49.465329 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 00:38:49.465411 ==
6263 00:38:49.468299 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 00:38:49.471403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 00:38:49.471486 ==
6266 00:38:49.478741 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 00:38:49.484589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6268 00:38:49.487861 [CA 0] Center 36 (8~64) winsize 57
6269 00:38:49.492042 [CA 1] Center 36 (8~64) winsize 57
6270 00:38:49.492123 [CA 2] Center 36 (8~64) winsize 57
6271 00:38:49.494576 [CA 3] Center 36 (8~64) winsize 57
6272 00:38:49.498010 [CA 4] Center 36 (8~64) winsize 57
6273 00:38:49.501478 [CA 5] Center 36 (8~64) winsize 57
6274 00:38:49.501560
6275 00:38:49.505282 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6276 00:38:49.505365
6277 00:38:49.508876 [CATrainingPosCal] consider 1 rank data
6278 00:38:49.511295 u2DelayCellTimex100 = 270/100 ps
6279 00:38:49.515074 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 00:38:49.521518 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 00:38:49.525603 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 00:38:49.528078 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 00:38:49.531934 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 00:38:49.535083 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 00:38:49.535165
6286 00:38:49.538200 CA PerBit enable=1, Macro0, CA PI delay=36
6287 00:38:49.538281
6288 00:38:49.541453 [CBTSetCACLKResult] CA Dly = 36
6289 00:38:49.541535 CS Dly: 1 (0~32)
6290 00:38:49.544699 ==
6291 00:38:49.548513 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 00:38:49.551293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 00:38:49.551375 ==
6294 00:38:49.555018 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 00:38:49.562102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 00:38:49.564749 [CA 0] Center 36 (8~64) winsize 57
6297 00:38:49.568057 [CA 1] Center 36 (8~64) winsize 57
6298 00:38:49.571250 [CA 2] Center 36 (8~64) winsize 57
6299 00:38:49.574645 [CA 3] Center 36 (8~64) winsize 57
6300 00:38:49.578246 [CA 4] Center 36 (8~64) winsize 57
6301 00:38:49.581458 [CA 5] Center 36 (8~64) winsize 57
6302 00:38:49.581540
6303 00:38:49.584486 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 00:38:49.584567
6305 00:38:49.588128 [CATrainingPosCal] consider 2 rank data
6306 00:38:49.591564 u2DelayCellTimex100 = 270/100 ps
6307 00:38:49.594770 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 00:38:49.598060 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 00:38:49.601411 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 00:38:49.605103 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 00:38:49.608237 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 00:38:49.615202 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 00:38:49.615286
6314 00:38:49.618817 CA PerBit enable=1, Macro0, CA PI delay=36
6315 00:38:49.618899
6316 00:38:49.621583 [CBTSetCACLKResult] CA Dly = 36
6317 00:38:49.621665 CS Dly: 1 (0~32)
6318 00:38:49.621731
6319 00:38:49.624540 ----->DramcWriteLeveling(PI) begin...
6320 00:38:49.624623 ==
6321 00:38:49.628123 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 00:38:49.631304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 00:38:49.634605 ==
6324 00:38:49.634686 Write leveling (Byte 0): 40 => 8
6325 00:38:49.637935 Write leveling (Byte 1): 32 => 0
6326 00:38:49.641417 DramcWriteLeveling(PI) end<-----
6327 00:38:49.641499
6328 00:38:49.641563 ==
6329 00:38:49.644514 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 00:38:49.651580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 00:38:49.651662 ==
6332 00:38:49.651726 [Gating] SW mode calibration
6333 00:38:49.661554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 00:38:49.664849 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 00:38:49.668608 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 00:38:49.675185 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 00:38:49.678190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 00:38:49.681155 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 00:38:49.688125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 00:38:49.691153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 00:38:49.694531 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 00:38:49.701281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 00:38:49.704936 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 00:38:49.708336 Total UI for P1: 0, mck2ui 16
6345 00:38:49.711193 best dqsien dly found for B0: ( 0, 14, 24)
6346 00:38:49.714771 Total UI for P1: 0, mck2ui 16
6347 00:38:49.717968 best dqsien dly found for B1: ( 0, 14, 24)
6348 00:38:49.721469 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 00:38:49.724567 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 00:38:49.724648
6351 00:38:49.728440 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 00:38:49.731250 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 00:38:49.735137 [Gating] SW calibration Done
6354 00:38:49.735220 ==
6355 00:38:49.738221 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 00:38:49.741903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 00:38:49.744630 ==
6358 00:38:49.744712 RX Vref Scan: 0
6359 00:38:49.744777
6360 00:38:49.748301 RX Vref 0 -> 0, step: 1
6361 00:38:49.748382
6362 00:38:49.751369 RX Delay -410 -> 252, step: 16
6363 00:38:49.754804 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6364 00:38:49.758437 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6365 00:38:49.761951 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6366 00:38:49.768292 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6367 00:38:49.771417 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6368 00:38:49.775146 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6369 00:38:49.778631 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6370 00:38:49.781735 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6371 00:38:49.788920 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6372 00:38:49.791592 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6373 00:38:49.795034 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6374 00:38:49.801509 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6375 00:38:49.804637 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6376 00:38:49.808659 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6377 00:38:49.811962 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6378 00:38:49.818006 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6379 00:38:49.818090 ==
6380 00:38:49.821292 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 00:38:49.824912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 00:38:49.825044 ==
6383 00:38:49.825141 DQS Delay:
6384 00:38:49.828130 DQS0 = 35, DQS1 = 51
6385 00:38:49.828212 DQM Delay:
6386 00:38:49.832493 DQM0 = 7, DQM1 = 10
6387 00:38:49.832575 DQ Delay:
6388 00:38:49.835756 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6389 00:38:49.837972 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6390 00:38:49.841329 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6391 00:38:49.844559 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6392 00:38:49.844640
6393 00:38:49.844705
6394 00:38:49.844764 ==
6395 00:38:49.847797 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 00:38:49.851743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 00:38:49.851825 ==
6398 00:38:49.851889
6399 00:38:49.851948
6400 00:38:49.854802 TX Vref Scan disable
6401 00:38:49.854883 == TX Byte 0 ==
6402 00:38:49.861195 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 00:38:49.864404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 00:38:49.864486 == TX Byte 1 ==
6405 00:38:49.870944 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6406 00:38:49.874510 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6407 00:38:49.874603 ==
6408 00:38:49.877575 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 00:38:49.881572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 00:38:49.881654 ==
6411 00:38:49.881718
6412 00:38:49.881778
6413 00:38:49.884694 TX Vref Scan disable
6414 00:38:49.888223 == TX Byte 0 ==
6415 00:38:49.890941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 00:38:49.894581 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 00:38:49.897754 == TX Byte 1 ==
6418 00:38:49.901304 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6419 00:38:49.904501 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6420 00:38:49.904582
6421 00:38:49.904647 [DATLAT]
6422 00:38:49.907887 Freq=400, CH0 RK0
6423 00:38:49.907969
6424 00:38:49.908034 DATLAT Default: 0xf
6425 00:38:49.911089 0, 0xFFFF, sum = 0
6426 00:38:49.911172 1, 0xFFFF, sum = 0
6427 00:38:49.914515 2, 0xFFFF, sum = 0
6428 00:38:49.914597 3, 0xFFFF, sum = 0
6429 00:38:49.918404 4, 0xFFFF, sum = 0
6430 00:38:49.921676 5, 0xFFFF, sum = 0
6431 00:38:49.921759 6, 0xFFFF, sum = 0
6432 00:38:49.924596 7, 0xFFFF, sum = 0
6433 00:38:49.924679 8, 0xFFFF, sum = 0
6434 00:38:49.927908 9, 0xFFFF, sum = 0
6435 00:38:49.927990 10, 0xFFFF, sum = 0
6436 00:38:49.931445 11, 0xFFFF, sum = 0
6437 00:38:49.931528 12, 0xFFFF, sum = 0
6438 00:38:49.934311 13, 0x0, sum = 1
6439 00:38:49.934393 14, 0x0, sum = 2
6440 00:38:49.937620 15, 0x0, sum = 3
6441 00:38:49.937702 16, 0x0, sum = 4
6442 00:38:49.940992 best_step = 14
6443 00:38:49.941087
6444 00:38:49.941151 ==
6445 00:38:49.944681 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 00:38:49.948559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 00:38:49.948641 ==
6448 00:38:49.948706 RX Vref Scan: 1
6449 00:38:49.948766
6450 00:38:49.950990 RX Vref 0 -> 0, step: 1
6451 00:38:49.951071
6452 00:38:49.954582 RX Delay -343 -> 252, step: 8
6453 00:38:49.954664
6454 00:38:49.958304 Set Vref, RX VrefLevel [Byte0]: 53
6455 00:38:49.960985 [Byte1]: 52
6456 00:38:49.965089
6457 00:38:49.965170 Final RX Vref Byte 0 = 53 to rank0
6458 00:38:49.968442 Final RX Vref Byte 1 = 52 to rank0
6459 00:38:49.971995 Final RX Vref Byte 0 = 53 to rank1
6460 00:38:49.974829 Final RX Vref Byte 1 = 52 to rank1==
6461 00:38:49.978105 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 00:38:49.984963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 00:38:49.985107 ==
6464 00:38:49.985203 DQS Delay:
6465 00:38:49.988299 DQS0 = 44, DQS1 = 60
6466 00:38:49.988380 DQM Delay:
6467 00:38:49.988445 DQM0 = 11, DQM1 = 14
6468 00:38:49.991683 DQ Delay:
6469 00:38:49.995336 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6470 00:38:49.995419 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6471 00:38:49.998052 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6472 00:38:50.001854 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6473 00:38:50.001935
6474 00:38:50.004919
6475 00:38:50.011644 [DQSOSCAuto] RK0, (LSB)MR18= 0x814f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6476 00:38:50.014977 CH0 RK0: MR19=C0C, MR18=814F
6477 00:38:50.021793 CH0_RK0: MR19=0xC0C, MR18=0x814F, DQSOSC=393, MR23=63, INC=382, DEC=254
6478 00:38:50.021875 ==
6479 00:38:50.025144 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 00:38:50.028513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 00:38:50.028615 ==
6482 00:38:50.031877 [Gating] SW mode calibration
6483 00:38:50.038422 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 00:38:50.042162 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 00:38:50.048474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 00:38:50.051754 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 00:38:50.055550 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 00:38:50.062183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 00:38:50.065879 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 00:38:50.068515 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 00:38:50.075424 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 00:38:50.078653 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 00:38:50.081716 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 00:38:50.085114 Total UI for P1: 0, mck2ui 16
6495 00:38:50.088391 best dqsien dly found for B0: ( 0, 14, 24)
6496 00:38:50.091697 Total UI for P1: 0, mck2ui 16
6497 00:38:50.095340 best dqsien dly found for B1: ( 0, 14, 24)
6498 00:38:50.098454 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 00:38:50.102431 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 00:38:50.102513
6501 00:38:50.108888 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 00:38:50.112209 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 00:38:50.112291 [Gating] SW calibration Done
6504 00:38:50.115216 ==
6505 00:38:50.119065 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 00:38:50.121845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 00:38:50.121927 ==
6508 00:38:50.121992 RX Vref Scan: 0
6509 00:38:50.122052
6510 00:38:50.125114 RX Vref 0 -> 0, step: 1
6511 00:38:50.125196
6512 00:38:50.128325 RX Delay -410 -> 252, step: 16
6513 00:38:50.131953 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6514 00:38:50.135411 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6515 00:38:50.142104 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6516 00:38:50.145452 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6517 00:38:50.148221 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6518 00:38:50.151926 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6519 00:38:50.158808 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6520 00:38:50.161558 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6521 00:38:50.165226 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6522 00:38:50.168515 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6523 00:38:50.174914 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6524 00:38:50.178378 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6525 00:38:50.181443 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6526 00:38:50.185140 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6527 00:38:50.191576 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6528 00:38:50.195092 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6529 00:38:50.195173 ==
6530 00:38:50.198539 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 00:38:50.202148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 00:38:50.202231 ==
6533 00:38:50.205035 DQS Delay:
6534 00:38:50.205116 DQS0 = 51, DQS1 = 51
6535 00:38:50.208387 DQM Delay:
6536 00:38:50.208489 DQM0 = 18, DQM1 = 10
6537 00:38:50.208582 DQ Delay:
6538 00:38:50.211403 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6539 00:38:50.214850 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6540 00:38:50.218526 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6541 00:38:50.221521 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6542 00:38:50.221601
6543 00:38:50.221666
6544 00:38:50.221726 ==
6545 00:38:50.225108 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 00:38:50.231953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 00:38:50.232036 ==
6548 00:38:50.232101
6549 00:38:50.232161
6550 00:38:50.232217 TX Vref Scan disable
6551 00:38:50.235202 == TX Byte 0 ==
6552 00:38:50.238213 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6553 00:38:50.241558 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6554 00:38:50.245108 == TX Byte 1 ==
6555 00:38:50.248366 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6556 00:38:50.252066 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6557 00:38:50.252147 ==
6558 00:38:50.255781 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 00:38:50.261457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 00:38:50.261538 ==
6561 00:38:50.261606
6562 00:38:50.261682
6563 00:38:50.261741 TX Vref Scan disable
6564 00:38:50.265933 == TX Byte 0 ==
6565 00:38:50.268654 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6566 00:38:50.271602 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6567 00:38:50.275037 == TX Byte 1 ==
6568 00:38:50.278187 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6569 00:38:50.282004 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6570 00:38:50.282085
6571 00:38:50.285861 [DATLAT]
6572 00:38:50.285942 Freq=400, CH0 RK1
6573 00:38:50.286007
6574 00:38:50.288881 DATLAT Default: 0xe
6575 00:38:50.288995 0, 0xFFFF, sum = 0
6576 00:38:50.291817 1, 0xFFFF, sum = 0
6577 00:38:50.291900 2, 0xFFFF, sum = 0
6578 00:38:50.296675 3, 0xFFFF, sum = 0
6579 00:38:50.296758 4, 0xFFFF, sum = 0
6580 00:38:50.298320 5, 0xFFFF, sum = 0
6581 00:38:50.298414 6, 0xFFFF, sum = 0
6582 00:38:50.301804 7, 0xFFFF, sum = 0
6583 00:38:50.301887 8, 0xFFFF, sum = 0
6584 00:38:50.304951 9, 0xFFFF, sum = 0
6585 00:38:50.305073 10, 0xFFFF, sum = 0
6586 00:38:50.308193 11, 0xFFFF, sum = 0
6587 00:38:50.311781 12, 0xFFFF, sum = 0
6588 00:38:50.311895 13, 0x0, sum = 1
6589 00:38:50.311961 14, 0x0, sum = 2
6590 00:38:50.315242 15, 0x0, sum = 3
6591 00:38:50.315324 16, 0x0, sum = 4
6592 00:38:50.318620 best_step = 14
6593 00:38:50.318701
6594 00:38:50.318765 ==
6595 00:38:50.322026 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 00:38:50.325476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 00:38:50.325558 ==
6598 00:38:50.328718 RX Vref Scan: 0
6599 00:38:50.328799
6600 00:38:50.328863 RX Vref 0 -> 0, step: 1
6601 00:38:50.328923
6602 00:38:50.332089 RX Delay -343 -> 252, step: 8
6603 00:38:50.339691 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6604 00:38:50.343459 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6605 00:38:50.346380 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6606 00:38:50.350143 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6607 00:38:50.356677 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6608 00:38:50.359790 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6609 00:38:50.363390 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6610 00:38:50.366379 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6611 00:38:50.373026 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6612 00:38:50.376464 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6613 00:38:50.380019 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6614 00:38:50.383488 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6615 00:38:50.389784 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6616 00:38:50.393270 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6617 00:38:50.396486 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6618 00:38:50.399968 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6619 00:38:50.403900 ==
6620 00:38:50.406535 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 00:38:50.410108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 00:38:50.410190 ==
6623 00:38:50.410255 DQS Delay:
6624 00:38:50.413894 DQS0 = 48, DQS1 = 60
6625 00:38:50.413976 DQM Delay:
6626 00:38:50.416934 DQM0 = 12, DQM1 = 13
6627 00:38:50.417055 DQ Delay:
6628 00:38:50.420578 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6629 00:38:50.423375 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6630 00:38:50.426962 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6631 00:38:50.430324 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6632 00:38:50.430439
6633 00:38:50.430533
6634 00:38:50.436888 [DQSOSCAuto] RK1, (LSB)MR18= 0x9a6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6635 00:38:50.439946 CH0 RK1: MR19=C0C, MR18=9A6D
6636 00:38:50.446784 CH0_RK1: MR19=0xC0C, MR18=0x9A6D, DQSOSC=390, MR23=63, INC=388, DEC=258
6637 00:38:50.450217 [RxdqsGatingPostProcess] freq 400
6638 00:38:50.453708 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 00:38:50.456807 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 00:38:50.459885 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 00:38:50.463967 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 00:38:50.466751 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 00:38:50.470196 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 00:38:50.473927 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 00:38:50.476857 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 00:38:50.480538 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 00:38:50.483265 Pre-setting of DQS Precalculation
6648 00:38:50.486842 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 00:38:50.486939 ==
6650 00:38:50.490046 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 00:38:50.496653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 00:38:50.496734 ==
6653 00:38:50.500339 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 00:38:50.507055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 00:38:50.510126 [CA 0] Center 36 (8~64) winsize 57
6656 00:38:50.513979 [CA 1] Center 36 (8~64) winsize 57
6657 00:38:50.516808 [CA 2] Center 36 (8~64) winsize 57
6658 00:38:50.520378 [CA 3] Center 36 (8~64) winsize 57
6659 00:38:50.523614 [CA 4] Center 36 (8~64) winsize 57
6660 00:38:50.526925 [CA 5] Center 36 (8~64) winsize 57
6661 00:38:50.527001
6662 00:38:50.530316 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 00:38:50.530386
6664 00:38:50.533687 [CATrainingPosCal] consider 1 rank data
6665 00:38:50.536840 u2DelayCellTimex100 = 270/100 ps
6666 00:38:50.540155 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 00:38:50.543583 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 00:38:50.546823 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 00:38:50.550509 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 00:38:50.553280 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 00:38:50.556853 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 00:38:50.556938
6673 00:38:50.563244 CA PerBit enable=1, Macro0, CA PI delay=36
6674 00:38:50.563326
6675 00:38:50.563391 [CBTSetCACLKResult] CA Dly = 36
6676 00:38:50.567033 CS Dly: 1 (0~32)
6677 00:38:50.567114 ==
6678 00:38:50.570064 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 00:38:50.573383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 00:38:50.573465 ==
6681 00:38:50.579939 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 00:38:50.587056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6683 00:38:50.590173 [CA 0] Center 36 (8~64) winsize 57
6684 00:38:50.593345 [CA 1] Center 36 (8~64) winsize 57
6685 00:38:50.597086 [CA 2] Center 36 (8~64) winsize 57
6686 00:38:50.597167 [CA 3] Center 36 (8~64) winsize 57
6687 00:38:50.600186 [CA 4] Center 36 (8~64) winsize 57
6688 00:38:50.603556 [CA 5] Center 36 (8~64) winsize 57
6689 00:38:50.603638
6690 00:38:50.610394 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6691 00:38:50.610476
6692 00:38:50.614294 [CATrainingPosCal] consider 2 rank data
6693 00:38:50.614375 u2DelayCellTimex100 = 270/100 ps
6694 00:38:50.620713 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 00:38:50.623442 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 00:38:50.626911 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 00:38:50.630234 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 00:38:50.633203 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 00:38:50.636838 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 00:38:50.636944
6701 00:38:50.639985 CA PerBit enable=1, Macro0, CA PI delay=36
6702 00:38:50.640069
6703 00:38:50.643980 [CBTSetCACLKResult] CA Dly = 36
6704 00:38:50.646895 CS Dly: 1 (0~32)
6705 00:38:50.646977
6706 00:38:50.650186 ----->DramcWriteLeveling(PI) begin...
6707 00:38:50.650268 ==
6708 00:38:50.653634 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 00:38:50.657355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 00:38:50.657437 ==
6711 00:38:50.660133 Write leveling (Byte 0): 40 => 8
6712 00:38:50.663990 Write leveling (Byte 1): 40 => 8
6713 00:38:50.666977 DramcWriteLeveling(PI) end<-----
6714 00:38:50.667083
6715 00:38:50.667175 ==
6716 00:38:50.670547 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 00:38:50.673754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 00:38:50.673836 ==
6719 00:38:50.676869 [Gating] SW mode calibration
6720 00:38:50.684371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 00:38:50.690191 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 00:38:50.694156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 00:38:50.696682 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 00:38:50.700631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 00:38:50.707005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 00:38:50.710539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 00:38:50.713648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 00:38:50.720473 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 00:38:50.723348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 00:38:50.726960 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 00:38:50.730624 Total UI for P1: 0, mck2ui 16
6732 00:38:50.733510 best dqsien dly found for B0: ( 0, 14, 24)
6733 00:38:50.737202 Total UI for P1: 0, mck2ui 16
6734 00:38:50.740292 best dqsien dly found for B1: ( 0, 14, 24)
6735 00:38:50.743841 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 00:38:50.747100 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 00:38:50.747182
6738 00:38:50.753903 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 00:38:50.756918 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 00:38:50.760448 [Gating] SW calibration Done
6741 00:38:50.760531 ==
6742 00:38:50.763572 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 00:38:50.767256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 00:38:50.767339 ==
6745 00:38:50.767403 RX Vref Scan: 0
6746 00:38:50.767465
6747 00:38:50.770510 RX Vref 0 -> 0, step: 1
6748 00:38:50.770592
6749 00:38:50.773779 RX Delay -410 -> 252, step: 16
6750 00:38:50.776851 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6751 00:38:50.780549 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6752 00:38:50.787168 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6753 00:38:50.790524 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6754 00:38:50.794261 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6755 00:38:50.797156 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6756 00:38:50.804023 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6757 00:38:50.807219 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6758 00:38:50.811140 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6759 00:38:50.813987 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6760 00:38:50.820282 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6761 00:38:50.823666 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6762 00:38:50.827127 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6763 00:38:50.830820 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6764 00:38:50.837128 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6765 00:38:50.840456 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6766 00:38:50.840539 ==
6767 00:38:50.843800 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 00:38:50.847570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 00:38:50.847652 ==
6770 00:38:50.850759 DQS Delay:
6771 00:38:50.850841 DQS0 = 51, DQS1 = 59
6772 00:38:50.853736 DQM Delay:
6773 00:38:50.853818 DQM0 = 19, DQM1 = 18
6774 00:38:50.853882 DQ Delay:
6775 00:38:50.857634 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6776 00:38:50.860664 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6777 00:38:50.864269 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6778 00:38:50.867223 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6779 00:38:50.867304
6780 00:38:50.867368
6781 00:38:50.867427 ==
6782 00:38:50.870428 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 00:38:50.877488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 00:38:50.877570 ==
6785 00:38:50.877635
6786 00:38:50.877693
6787 00:38:50.877750 TX Vref Scan disable
6788 00:38:50.880776 == TX Byte 0 ==
6789 00:38:50.884056 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 00:38:50.887296 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 00:38:50.890415 == TX Byte 1 ==
6792 00:38:50.893568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 00:38:50.897457 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 00:38:50.897539 ==
6795 00:38:50.900459 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 00:38:50.907392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 00:38:50.907475 ==
6798 00:38:50.907540
6799 00:38:50.907600
6800 00:38:50.910784 TX Vref Scan disable
6801 00:38:50.910864 == TX Byte 0 ==
6802 00:38:50.913647 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 00:38:50.916863 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 00:38:50.920221 == TX Byte 1 ==
6805 00:38:50.923794 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 00:38:50.927076 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 00:38:50.927157
6808 00:38:50.930661 [DATLAT]
6809 00:38:50.930742 Freq=400, CH1 RK0
6810 00:38:50.930807
6811 00:38:50.934184 DATLAT Default: 0xf
6812 00:38:50.934265 0, 0xFFFF, sum = 0
6813 00:38:50.936844 1, 0xFFFF, sum = 0
6814 00:38:50.936926 2, 0xFFFF, sum = 0
6815 00:38:50.940366 3, 0xFFFF, sum = 0
6816 00:38:50.940449 4, 0xFFFF, sum = 0
6817 00:38:50.943909 5, 0xFFFF, sum = 0
6818 00:38:50.943992 6, 0xFFFF, sum = 0
6819 00:38:50.947005 7, 0xFFFF, sum = 0
6820 00:38:50.947088 8, 0xFFFF, sum = 0
6821 00:38:50.950237 9, 0xFFFF, sum = 0
6822 00:38:50.953679 10, 0xFFFF, sum = 0
6823 00:38:50.953761 11, 0xFFFF, sum = 0
6824 00:38:50.956927 12, 0xFFFF, sum = 0
6825 00:38:50.957019 13, 0x0, sum = 1
6826 00:38:50.960534 14, 0x0, sum = 2
6827 00:38:50.960616 15, 0x0, sum = 3
6828 00:38:50.960681 16, 0x0, sum = 4
6829 00:38:50.964163 best_step = 14
6830 00:38:50.964249
6831 00:38:50.964315 ==
6832 00:38:50.967753 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 00:38:50.970932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 00:38:50.971014 ==
6835 00:38:50.973840 RX Vref Scan: 1
6836 00:38:50.973971
6837 00:38:50.974051 RX Vref 0 -> 0, step: 1
6838 00:38:50.974111
6839 00:38:50.977130 RX Delay -359 -> 252, step: 8
6840 00:38:50.977214
6841 00:38:50.980741 Set Vref, RX VrefLevel [Byte0]: 56
6842 00:38:50.983941 [Byte1]: 50
6843 00:38:50.988937
6844 00:38:50.989026 Final RX Vref Byte 0 = 56 to rank0
6845 00:38:50.992167 Final RX Vref Byte 1 = 50 to rank0
6846 00:38:50.995866 Final RX Vref Byte 0 = 56 to rank1
6847 00:38:50.999037 Final RX Vref Byte 1 = 50 to rank1==
6848 00:38:51.002351 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 00:38:51.008932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 00:38:51.009036 ==
6851 00:38:51.009101 DQS Delay:
6852 00:38:51.009161 DQS0 = 48, DQS1 = 60
6853 00:38:51.012070 DQM Delay:
6854 00:38:51.012150 DQM0 = 12, DQM1 = 12
6855 00:38:51.015499 DQ Delay:
6856 00:38:51.018848 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6857 00:38:51.018930 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6858 00:38:51.022166 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6859 00:38:51.026293 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6860 00:38:51.026376
6861 00:38:51.026440
6862 00:38:51.035565 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c34, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6863 00:38:51.038985 CH1 RK0: MR19=C0C, MR18=8C34
6864 00:38:51.045578 CH1_RK0: MR19=0xC0C, MR18=0x8C34, DQSOSC=392, MR23=63, INC=384, DEC=256
6865 00:38:51.045660 ==
6866 00:38:51.049001 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 00:38:51.052771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 00:38:51.052854 ==
6869 00:38:51.055817 [Gating] SW mode calibration
6870 00:38:51.062337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 00:38:51.065893 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 00:38:51.072513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 00:38:51.076090 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 00:38:51.079583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 00:38:51.085809 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 00:38:51.089182 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 00:38:51.092364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 00:38:51.099478 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 00:38:51.102327 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 00:38:51.105618 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 00:38:51.109505 Total UI for P1: 0, mck2ui 16
6882 00:38:51.112995 best dqsien dly found for B0: ( 0, 14, 24)
6883 00:38:51.115766 Total UI for P1: 0, mck2ui 16
6884 00:38:51.119306 best dqsien dly found for B1: ( 0, 14, 24)
6885 00:38:51.122674 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 00:38:51.126462 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 00:38:51.126544
6888 00:38:51.129768 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 00:38:51.136425 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 00:38:51.136508 [Gating] SW calibration Done
6891 00:38:51.136573 ==
6892 00:38:51.139325 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 00:38:51.146162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 00:38:51.146270 ==
6895 00:38:51.146363 RX Vref Scan: 0
6896 00:38:51.146451
6897 00:38:51.150103 RX Vref 0 -> 0, step: 1
6898 00:38:51.150184
6899 00:38:51.153188 RX Delay -410 -> 252, step: 16
6900 00:38:51.156228 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6901 00:38:51.159292 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6902 00:38:51.163238 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6903 00:38:51.169613 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6904 00:38:51.173111 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6905 00:38:51.176129 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6906 00:38:51.179831 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6907 00:38:51.186378 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6908 00:38:51.189521 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6909 00:38:51.192887 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6910 00:38:51.196087 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6911 00:38:51.202687 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6912 00:38:51.206208 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6913 00:38:51.209331 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6914 00:38:51.216067 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6915 00:38:51.219892 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6916 00:38:51.219973 ==
6917 00:38:51.222888 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 00:38:51.226548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 00:38:51.226630 ==
6920 00:38:51.226694 DQS Delay:
6921 00:38:51.229720 DQS0 = 43, DQS1 = 51
6922 00:38:51.229801 DQM Delay:
6923 00:38:51.233333 DQM0 = 11, DQM1 = 10
6924 00:38:51.233414 DQ Delay:
6925 00:38:51.236640 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6926 00:38:51.239308 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6927 00:38:51.243071 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6928 00:38:51.246129 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6929 00:38:51.246211
6930 00:38:51.246275
6931 00:38:51.246334 ==
6932 00:38:51.249786 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 00:38:51.252969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 00:38:51.253089 ==
6935 00:38:51.253154
6936 00:38:51.253213
6937 00:38:51.256374 TX Vref Scan disable
6938 00:38:51.259478 == TX Byte 0 ==
6939 00:38:51.262921 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6940 00:38:51.266429 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6941 00:38:51.266513 == TX Byte 1 ==
6942 00:38:51.272972 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6943 00:38:51.276343 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6944 00:38:51.276424 ==
6945 00:38:51.279808 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 00:38:51.283177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 00:38:51.283258 ==
6948 00:38:51.283322
6949 00:38:51.283381
6950 00:38:51.286218 TX Vref Scan disable
6951 00:38:51.289720 == TX Byte 0 ==
6952 00:38:51.292889 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6953 00:38:51.296524 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6954 00:38:51.296605 == TX Byte 1 ==
6955 00:38:51.302731 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6956 00:38:51.306110 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6957 00:38:51.306189
6958 00:38:51.306254 [DATLAT]
6959 00:38:51.310072 Freq=400, CH1 RK1
6960 00:38:51.310173
6961 00:38:51.310275 DATLAT Default: 0xe
6962 00:38:51.312908 0, 0xFFFF, sum = 0
6963 00:38:51.313066 1, 0xFFFF, sum = 0
6964 00:38:51.316399 2, 0xFFFF, sum = 0
6965 00:38:51.316510 3, 0xFFFF, sum = 0
6966 00:38:51.319476 4, 0xFFFF, sum = 0
6967 00:38:51.319586 5, 0xFFFF, sum = 0
6968 00:38:51.322928 6, 0xFFFF, sum = 0
6969 00:38:51.323029 7, 0xFFFF, sum = 0
6970 00:38:51.326769 8, 0xFFFF, sum = 0
6971 00:38:51.326875 9, 0xFFFF, sum = 0
6972 00:38:51.329678 10, 0xFFFF, sum = 0
6973 00:38:51.332971 11, 0xFFFF, sum = 0
6974 00:38:51.333129 12, 0xFFFF, sum = 0
6975 00:38:51.336501 13, 0x0, sum = 1
6976 00:38:51.336603 14, 0x0, sum = 2
6977 00:38:51.336700 15, 0x0, sum = 3
6978 00:38:51.339988 16, 0x0, sum = 4
6979 00:38:51.340096 best_step = 14
6980 00:38:51.340194
6981 00:38:51.343340 ==
6982 00:38:51.343414 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 00:38:51.349784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 00:38:51.349860 ==
6985 00:38:51.349939 RX Vref Scan: 0
6986 00:38:51.350002
6987 00:38:51.352685 RX Vref 0 -> 0, step: 1
6988 00:38:51.352788
6989 00:38:51.356092 RX Delay -343 -> 252, step: 8
6990 00:38:51.363070 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6991 00:38:51.366654 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6992 00:38:51.369645 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6993 00:38:51.373312 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6994 00:38:51.380147 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6995 00:38:51.383532 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6996 00:38:51.386350 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6997 00:38:51.389945 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6998 00:38:51.396343 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6999 00:38:51.399697 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7000 00:38:51.403186 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7001 00:38:51.406502 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7002 00:38:51.413856 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7003 00:38:51.416527 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7004 00:38:51.419725 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7005 00:38:51.426353 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7006 00:38:51.426435 ==
7007 00:38:51.429739 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 00:38:51.433110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 00:38:51.433192 ==
7010 00:38:51.433256 DQS Delay:
7011 00:38:51.436176 DQS0 = 48, DQS1 = 56
7012 00:38:51.436258 DQM Delay:
7013 00:38:51.439552 DQM0 = 9, DQM1 = 9
7014 00:38:51.439633 DQ Delay:
7015 00:38:51.442960 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7016 00:38:51.446503 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7017 00:38:51.449557 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7018 00:38:51.452782 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7019 00:38:51.452863
7020 00:38:51.452928
7021 00:38:51.459927 [DQSOSCAuto] RK1, (LSB)MR18= 0x758c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7022 00:38:51.463499 CH1 RK1: MR19=C0C, MR18=758C
7023 00:38:51.469973 CH1_RK1: MR19=0xC0C, MR18=0x758C, DQSOSC=392, MR23=63, INC=384, DEC=256
7024 00:38:51.473176 [RxdqsGatingPostProcess] freq 400
7025 00:38:51.476147 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 00:38:51.480181 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 00:38:51.483081 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 00:38:51.486605 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 00:38:51.490021 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 00:38:51.492960 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 00:38:51.496753 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 00:38:51.500248 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 00:38:51.503413 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 00:38:51.507086 Pre-setting of DQS Precalculation
7035 00:38:51.510569 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 00:38:51.516762 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 00:38:51.526758 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 00:38:51.526863
7039 00:38:51.526955
7040 00:38:51.529962 [Calibration Summary] 800 Mbps
7041 00:38:51.530062 CH 0, Rank 0
7042 00:38:51.533539 SW Impedance : PASS
7043 00:38:51.533620 DUTY Scan : NO K
7044 00:38:51.536744 ZQ Calibration : PASS
7045 00:38:51.536847 Jitter Meter : NO K
7046 00:38:51.539898 CBT Training : PASS
7047 00:38:51.543393 Write leveling : PASS
7048 00:38:51.543500 RX DQS gating : PASS
7049 00:38:51.546499 RX DQ/DQS(RDDQC) : PASS
7050 00:38:51.549830 TX DQ/DQS : PASS
7051 00:38:51.549903 RX DATLAT : PASS
7052 00:38:51.553338 RX DQ/DQS(Engine): PASS
7053 00:38:51.556654 TX OE : NO K
7054 00:38:51.556758 All Pass.
7055 00:38:51.556852
7056 00:38:51.556939 CH 0, Rank 1
7057 00:38:51.559738 SW Impedance : PASS
7058 00:38:51.563223 DUTY Scan : NO K
7059 00:38:51.563300 ZQ Calibration : PASS
7060 00:38:51.566308 Jitter Meter : NO K
7061 00:38:51.570167 CBT Training : PASS
7062 00:38:51.570264 Write leveling : NO K
7063 00:38:51.573489 RX DQS gating : PASS
7064 00:38:51.573569 RX DQ/DQS(RDDQC) : PASS
7065 00:38:51.576483 TX DQ/DQS : PASS
7066 00:38:51.579804 RX DATLAT : PASS
7067 00:38:51.579902 RX DQ/DQS(Engine): PASS
7068 00:38:51.583590 TX OE : NO K
7069 00:38:51.583663 All Pass.
7070 00:38:51.583753
7071 00:38:51.586648 CH 1, Rank 0
7072 00:38:51.586748 SW Impedance : PASS
7073 00:38:51.589966 DUTY Scan : NO K
7074 00:38:51.593126 ZQ Calibration : PASS
7075 00:38:51.593223 Jitter Meter : NO K
7076 00:38:51.596618 CBT Training : PASS
7077 00:38:51.599769 Write leveling : PASS
7078 00:38:51.599870 RX DQS gating : PASS
7079 00:38:51.603453 RX DQ/DQS(RDDQC) : PASS
7080 00:38:51.607230 TX DQ/DQS : PASS
7081 00:38:51.607337 RX DATLAT : PASS
7082 00:38:51.609758 RX DQ/DQS(Engine): PASS
7083 00:38:51.613754 TX OE : NO K
7084 00:38:51.613851 All Pass.
7085 00:38:51.613948
7086 00:38:51.614036 CH 1, Rank 1
7087 00:38:51.616231 SW Impedance : PASS
7088 00:38:51.619791 DUTY Scan : NO K
7089 00:38:51.619891 ZQ Calibration : PASS
7090 00:38:51.623844 Jitter Meter : NO K
7091 00:38:51.623945 CBT Training : PASS
7092 00:38:51.626547 Write leveling : NO K
7093 00:38:51.630234 RX DQS gating : PASS
7094 00:38:51.630335 RX DQ/DQS(RDDQC) : PASS
7095 00:38:51.633503 TX DQ/DQS : PASS
7096 00:38:51.636678 RX DATLAT : PASS
7097 00:38:51.636779 RX DQ/DQS(Engine): PASS
7098 00:38:51.639948 TX OE : NO K
7099 00:38:51.640046 All Pass.
7100 00:38:51.640135
7101 00:38:51.643506 DramC Write-DBI off
7102 00:38:51.646410 PER_BANK_REFRESH: Hybrid Mode
7103 00:38:51.646489 TX_TRACKING: ON
7104 00:38:51.657052 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 00:38:51.660182 [FAST_K] Save calibration result to emmc
7106 00:38:51.663465 dramc_set_vcore_voltage set vcore to 725000
7107 00:38:51.666829 Read voltage for 1600, 0
7108 00:38:51.666912 Vio18 = 0
7109 00:38:51.666980 Vcore = 725000
7110 00:38:51.669660 Vdram = 0
7111 00:38:51.669731 Vddq = 0
7112 00:38:51.669797 Vmddr = 0
7113 00:38:51.676867 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 00:38:51.679650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 00:38:51.683668 MEM_TYPE=3, freq_sel=13
7116 00:38:51.686975 sv_algorithm_assistance_LP4_3733
7117 00:38:51.689677 ============ PULL DRAM RESETB DOWN ============
7118 00:38:51.693199 ========== PULL DRAM RESETB DOWN end =========
7119 00:38:51.699844 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 00:38:51.703457 ===================================
7121 00:38:51.703556 LPDDR4 DRAM CONFIGURATION
7122 00:38:51.706593 ===================================
7123 00:38:51.710207 EX_ROW_EN[0] = 0x0
7124 00:38:51.713460 EX_ROW_EN[1] = 0x0
7125 00:38:51.713557 LP4Y_EN = 0x0
7126 00:38:51.716588 WORK_FSP = 0x1
7127 00:38:51.716690 WL = 0x5
7128 00:38:51.719848 RL = 0x5
7129 00:38:51.719946 BL = 0x2
7130 00:38:51.723299 RPST = 0x0
7131 00:38:51.723396 RD_PRE = 0x0
7132 00:38:51.726383 WR_PRE = 0x1
7133 00:38:51.726486 WR_PST = 0x1
7134 00:38:51.729840 DBI_WR = 0x0
7135 00:38:51.729941 DBI_RD = 0x0
7136 00:38:51.733363 OTF = 0x1
7137 00:38:51.736758 ===================================
7138 00:38:51.740022 ===================================
7139 00:38:51.740130 ANA top config
7140 00:38:51.743236 ===================================
7141 00:38:51.746914 DLL_ASYNC_EN = 0
7142 00:38:51.749984 ALL_SLAVE_EN = 0
7143 00:38:51.750066 NEW_RANK_MODE = 1
7144 00:38:51.753061 DLL_IDLE_MODE = 1
7145 00:38:51.756582 LP45_APHY_COMB_EN = 1
7146 00:38:51.760249 TX_ODT_DIS = 0
7147 00:38:51.763609 NEW_8X_MODE = 1
7148 00:38:51.766672 ===================================
7149 00:38:51.770037 ===================================
7150 00:38:51.770137 data_rate = 3200
7151 00:38:51.773499 CKR = 1
7152 00:38:51.776674 DQ_P2S_RATIO = 8
7153 00:38:51.780138 ===================================
7154 00:38:51.783375 CA_P2S_RATIO = 8
7155 00:38:51.786513 DQ_CA_OPEN = 0
7156 00:38:51.789883 DQ_SEMI_OPEN = 0
7157 00:38:51.789958 CA_SEMI_OPEN = 0
7158 00:38:51.793273 CA_FULL_RATE = 0
7159 00:38:51.796876 DQ_CKDIV4_EN = 0
7160 00:38:51.799875 CA_CKDIV4_EN = 0
7161 00:38:51.803889 CA_PREDIV_EN = 0
7162 00:38:51.807260 PH8_DLY = 12
7163 00:38:51.807358 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 00:38:51.810015 DQ_AAMCK_DIV = 4
7165 00:38:51.813140 CA_AAMCK_DIV = 4
7166 00:38:51.816691 CA_ADMCK_DIV = 4
7167 00:38:51.820147 DQ_TRACK_CA_EN = 0
7168 00:38:51.823679 CA_PICK = 1600
7169 00:38:51.823783 CA_MCKIO = 1600
7170 00:38:51.826571 MCKIO_SEMI = 0
7171 00:38:51.829858 PLL_FREQ = 3068
7172 00:38:51.833473 DQ_UI_PI_RATIO = 32
7173 00:38:51.836871 CA_UI_PI_RATIO = 0
7174 00:38:51.840293 ===================================
7175 00:38:51.843633 ===================================
7176 00:38:51.847027 memory_type:LPDDR4
7177 00:38:51.847105 GP_NUM : 10
7178 00:38:51.850389 SRAM_EN : 1
7179 00:38:51.850474 MD32_EN : 0
7180 00:38:51.853319 ===================================
7181 00:38:51.857243 [ANA_INIT] >>>>>>>>>>>>>>
7182 00:38:51.860259 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 00:38:51.863560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 00:38:51.866891 ===================================
7185 00:38:51.870419 data_rate = 3200,PCW = 0X7600
7186 00:38:51.873436 ===================================
7187 00:38:51.877164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 00:38:51.880519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 00:38:51.886988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 00:38:51.890249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 00:38:51.897125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 00:38:51.900107 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 00:38:51.900217 [ANA_INIT] flow start
7194 00:38:51.903443 [ANA_INIT] PLL >>>>>>>>
7195 00:38:51.903548 [ANA_INIT] PLL <<<<<<<<
7196 00:38:51.906916 [ANA_INIT] MIDPI >>>>>>>>
7197 00:38:51.910429 [ANA_INIT] MIDPI <<<<<<<<
7198 00:38:51.913730 [ANA_INIT] DLL >>>>>>>>
7199 00:38:51.913833 [ANA_INIT] DLL <<<<<<<<
7200 00:38:51.916796 [ANA_INIT] flow end
7201 00:38:51.920224 ============ LP4 DIFF to SE enter ============
7202 00:38:51.923492 ============ LP4 DIFF to SE exit ============
7203 00:38:51.926988 [ANA_INIT] <<<<<<<<<<<<<
7204 00:38:51.930066 [Flow] Enable top DCM control >>>>>
7205 00:38:51.933407 [Flow] Enable top DCM control <<<<<
7206 00:38:51.937083 Enable DLL master slave shuffle
7207 00:38:51.943910 ==============================================================
7208 00:38:51.944033 Gating Mode config
7209 00:38:51.950487 ==============================================================
7210 00:38:51.950600 Config description:
7211 00:38:51.960013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 00:38:51.966763 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 00:38:51.973801 SELPH_MODE 0: By rank 1: By Phase
7214 00:38:51.977290 ==============================================================
7215 00:38:51.980644 GAT_TRACK_EN = 1
7216 00:38:51.983861 RX_GATING_MODE = 2
7217 00:38:51.987177 RX_GATING_TRACK_MODE = 2
7218 00:38:51.989906 SELPH_MODE = 1
7219 00:38:51.993231 PICG_EARLY_EN = 1
7220 00:38:51.996854 VALID_LAT_VALUE = 1
7221 00:38:52.000225 ==============================================================
7222 00:38:52.003156 Enter into Gating configuration >>>>
7223 00:38:52.006821 Exit from Gating configuration <<<<
7224 00:38:52.009892 Enter into DVFS_PRE_config >>>>>
7225 00:38:52.023474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 00:38:52.026591 Exit from DVFS_PRE_config <<<<<
7227 00:38:52.030254 Enter into PICG configuration >>>>
7228 00:38:52.030358 Exit from PICG configuration <<<<
7229 00:38:52.033556 [RX_INPUT] configuration >>>>>
7230 00:38:52.036949 [RX_INPUT] configuration <<<<<
7231 00:38:52.043438 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 00:38:52.047316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 00:38:52.053610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 00:38:52.060467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 00:38:52.066991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 00:38:52.073531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 00:38:52.076903 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 00:38:52.080425 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 00:38:52.083374 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 00:38:52.089905 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 00:38:52.093531 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 00:38:52.096873 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 00:38:52.100140 ===================================
7244 00:38:52.103574 LPDDR4 DRAM CONFIGURATION
7245 00:38:52.106510 ===================================
7246 00:38:52.111150 EX_ROW_EN[0] = 0x0
7247 00:38:52.111260 EX_ROW_EN[1] = 0x0
7248 00:38:52.113765 LP4Y_EN = 0x0
7249 00:38:52.113866 WORK_FSP = 0x1
7250 00:38:52.116776 WL = 0x5
7251 00:38:52.116890 RL = 0x5
7252 00:38:52.120187 BL = 0x2
7253 00:38:52.120284 RPST = 0x0
7254 00:38:52.123542 RD_PRE = 0x0
7255 00:38:52.123644 WR_PRE = 0x1
7256 00:38:52.126745 WR_PST = 0x1
7257 00:38:52.126849 DBI_WR = 0x0
7258 00:38:52.130200 DBI_RD = 0x0
7259 00:38:52.130311 OTF = 0x1
7260 00:38:52.133534 ===================================
7261 00:38:52.137125 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 00:38:52.143838 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 00:38:52.146637 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 00:38:52.150103 ===================================
7265 00:38:52.153260 LPDDR4 DRAM CONFIGURATION
7266 00:38:52.156374 ===================================
7267 00:38:52.156485 EX_ROW_EN[0] = 0x10
7268 00:38:52.159884 EX_ROW_EN[1] = 0x0
7269 00:38:52.159983 LP4Y_EN = 0x0
7270 00:38:52.163377 WORK_FSP = 0x1
7271 00:38:52.163463 WL = 0x5
7272 00:38:52.166601 RL = 0x5
7273 00:38:52.170161 BL = 0x2
7274 00:38:52.170239 RPST = 0x0
7275 00:38:52.173525 RD_PRE = 0x0
7276 00:38:52.173598 WR_PRE = 0x1
7277 00:38:52.176832 WR_PST = 0x1
7278 00:38:52.176930 DBI_WR = 0x0
7279 00:38:52.179902 DBI_RD = 0x0
7280 00:38:52.180011 OTF = 0x1
7281 00:38:52.183720 ===================================
7282 00:38:52.190305 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 00:38:52.190383 ==
7284 00:38:52.193994 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 00:38:52.196889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 00:38:52.196971 ==
7287 00:38:52.200372 [Duty_Offset_Calibration]
7288 00:38:52.203521 B0:2 B1:-1 CA:1
7289 00:38:52.203630
7290 00:38:52.207439 [DutyScan_Calibration_Flow] k_type=0
7291 00:38:52.214475
7292 00:38:52.214565 ==CLK 0==
7293 00:38:52.217417 Final CLK duty delay cell = -4
7294 00:38:52.221105 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7295 00:38:52.224215 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7296 00:38:52.227424 [-4] AVG Duty = 4937%(X100)
7297 00:38:52.227506
7298 00:38:52.230703 CH0 CLK Duty spec in!! Max-Min= 187%
7299 00:38:52.234290 [DutyScan_Calibration_Flow] ====Done====
7300 00:38:52.234372
7301 00:38:52.237487 [DutyScan_Calibration_Flow] k_type=1
7302 00:38:52.253745
7303 00:38:52.253826 ==DQS 0 ==
7304 00:38:52.257425 Final DQS duty delay cell = 0
7305 00:38:52.261105 [0] MAX Duty = 5125%(X100), DQS PI = 20
7306 00:38:52.263805 [0] MIN Duty = 5000%(X100), DQS PI = 14
7307 00:38:52.263887 [0] AVG Duty = 5062%(X100)
7308 00:38:52.266770
7309 00:38:52.266878 ==DQS 1 ==
7310 00:38:52.270528 Final DQS duty delay cell = -4
7311 00:38:52.273680 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7312 00:38:52.276921 [-4] MIN Duty = 5000%(X100), DQS PI = 38
7313 00:38:52.280155 [-4] AVG Duty = 5046%(X100)
7314 00:38:52.280237
7315 00:38:52.283466 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7316 00:38:52.283548
7317 00:38:52.287249 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7318 00:38:52.290234 [DutyScan_Calibration_Flow] ====Done====
7319 00:38:52.290315
7320 00:38:52.293717 [DutyScan_Calibration_Flow] k_type=3
7321 00:38:52.311086
7322 00:38:52.311166 ==DQM 0 ==
7323 00:38:52.314295 Final DQM duty delay cell = 0
7324 00:38:52.317995 [0] MAX Duty = 5000%(X100), DQS PI = 18
7325 00:38:52.321009 [0] MIN Duty = 4875%(X100), DQS PI = 6
7326 00:38:52.321131 [0] AVG Duty = 4937%(X100)
7327 00:38:52.324655
7328 00:38:52.324735 ==DQM 1 ==
7329 00:38:52.327748 Final DQM duty delay cell = 0
7330 00:38:52.330908 [0] MAX Duty = 5187%(X100), DQS PI = 58
7331 00:38:52.334142 [0] MIN Duty = 4969%(X100), DQS PI = 18
7332 00:38:52.334227 [0] AVG Duty = 5078%(X100)
7333 00:38:52.337974
7334 00:38:52.341278 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7335 00:38:52.341360
7336 00:38:52.344383 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7337 00:38:52.347550 [DutyScan_Calibration_Flow] ====Done====
7338 00:38:52.347631
7339 00:38:52.350738 [DutyScan_Calibration_Flow] k_type=2
7340 00:38:52.368040
7341 00:38:52.368120 ==DQ 0 ==
7342 00:38:52.371344 Final DQ duty delay cell = 0
7343 00:38:52.374749 [0] MAX Duty = 5187%(X100), DQS PI = 56
7344 00:38:52.378174 [0] MIN Duty = 5031%(X100), DQS PI = 4
7345 00:38:52.378256 [0] AVG Duty = 5109%(X100)
7346 00:38:52.378320
7347 00:38:52.381708 ==DQ 1 ==
7348 00:38:52.384624 Final DQ duty delay cell = 0
7349 00:38:52.388308 [0] MAX Duty = 5000%(X100), DQS PI = 0
7350 00:38:52.391623 [0] MIN Duty = 4938%(X100), DQS PI = 4
7351 00:38:52.391704 [0] AVG Duty = 4969%(X100)
7352 00:38:52.391768
7353 00:38:52.394550 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7354 00:38:52.394630
7355 00:38:52.397770 CH0 DQ 1 Duty spec in!! Max-Min= 62%
7356 00:38:52.405018 [DutyScan_Calibration_Flow] ====Done====
7357 00:38:52.405099 ==
7358 00:38:52.407801 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 00:38:52.411764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 00:38:52.411845 ==
7361 00:38:52.415027 [Duty_Offset_Calibration]
7362 00:38:52.415108 B0:1 B1:1 CA:2
7363 00:38:52.415172
7364 00:38:52.417772 [DutyScan_Calibration_Flow] k_type=0
7365 00:38:52.427985
7366 00:38:52.428089 ==CLK 0==
7367 00:38:52.431413 Final CLK duty delay cell = 0
7368 00:38:52.434691 [0] MAX Duty = 5187%(X100), DQS PI = 24
7369 00:38:52.437863 [0] MIN Duty = 4969%(X100), DQS PI = 40
7370 00:38:52.437944 [0] AVG Duty = 5078%(X100)
7371 00:38:52.441560
7372 00:38:52.444923 CH1 CLK Duty spec in!! Max-Min= 218%
7373 00:38:52.448094 [DutyScan_Calibration_Flow] ====Done====
7374 00:38:52.448175
7375 00:38:52.451166 [DutyScan_Calibration_Flow] k_type=1
7376 00:38:52.467375
7377 00:38:52.467456 ==DQS 0 ==
7378 00:38:52.470891 Final DQS duty delay cell = 0
7379 00:38:52.473908 [0] MAX Duty = 5062%(X100), DQS PI = 22
7380 00:38:52.477680 [0] MIN Duty = 4813%(X100), DQS PI = 52
7381 00:38:52.480958 [0] AVG Duty = 4937%(X100)
7382 00:38:52.481075
7383 00:38:52.481138 ==DQS 1 ==
7384 00:38:52.484766 Final DQS duty delay cell = 0
7385 00:38:52.487495 [0] MAX Duty = 5031%(X100), DQS PI = 34
7386 00:38:52.490733 [0] MIN Duty = 4938%(X100), DQS PI = 14
7387 00:38:52.493949 [0] AVG Duty = 4984%(X100)
7388 00:38:52.494030
7389 00:38:52.497499 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7390 00:38:52.497581
7391 00:38:52.501134 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7392 00:38:52.504161 [DutyScan_Calibration_Flow] ====Done====
7393 00:38:52.504243
7394 00:38:52.507821 [DutyScan_Calibration_Flow] k_type=3
7395 00:38:52.524325
7396 00:38:52.524407 ==DQM 0 ==
7397 00:38:52.527547 Final DQM duty delay cell = 0
7398 00:38:52.530965 [0] MAX Duty = 5156%(X100), DQS PI = 20
7399 00:38:52.534422 [0] MIN Duty = 4844%(X100), DQS PI = 50
7400 00:38:52.537865 [0] AVG Duty = 5000%(X100)
7401 00:38:52.537947
7402 00:38:52.538011 ==DQM 1 ==
7403 00:38:52.540876 Final DQM duty delay cell = 0
7404 00:38:52.544267 [0] MAX Duty = 5125%(X100), DQS PI = 10
7405 00:38:52.547986 [0] MIN Duty = 4875%(X100), DQS PI = 22
7406 00:38:52.548093 [0] AVG Duty = 5000%(X100)
7407 00:38:52.551247
7408 00:38:52.554289 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7409 00:38:52.554370
7410 00:38:52.557738 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7411 00:38:52.561130 [DutyScan_Calibration_Flow] ====Done====
7412 00:38:52.561211
7413 00:38:52.564596 [DutyScan_Calibration_Flow] k_type=2
7414 00:38:52.581995
7415 00:38:52.582076 ==DQ 0 ==
7416 00:38:52.584451 Final DQ duty delay cell = 0
7417 00:38:52.587940 [0] MAX Duty = 5156%(X100), DQS PI = 20
7418 00:38:52.591204 [0] MIN Duty = 4938%(X100), DQS PI = 52
7419 00:38:52.591286 [0] AVG Duty = 5047%(X100)
7420 00:38:52.594769
7421 00:38:52.594850 ==DQ 1 ==
7422 00:38:52.597900 Final DQ duty delay cell = 0
7423 00:38:52.601103 [0] MAX Duty = 5093%(X100), DQS PI = 8
7424 00:38:52.604448 [0] MIN Duty = 5031%(X100), DQS PI = 0
7425 00:38:52.604531 [0] AVG Duty = 5062%(X100)
7426 00:38:52.604596
7427 00:38:52.607881 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7428 00:38:52.607963
7429 00:38:52.611796 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7430 00:38:52.618128 [DutyScan_Calibration_Flow] ====Done====
7431 00:38:52.621104 nWR fixed to 30
7432 00:38:52.621187 [ModeRegInit_LP4] CH0 RK0
7433 00:38:52.624317 [ModeRegInit_LP4] CH0 RK1
7434 00:38:52.627770 [ModeRegInit_LP4] CH1 RK0
7435 00:38:52.627852 [ModeRegInit_LP4] CH1 RK1
7436 00:38:52.631059 match AC timing 5
7437 00:38:52.634669 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 00:38:52.637917 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 00:38:52.644156 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 00:38:52.647968 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 00:38:52.654347 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 00:38:52.654433 [MiockJmeterHQA]
7443 00:38:52.654499
7444 00:38:52.657623 [DramcMiockJmeter] u1RxGatingPI = 0
7445 00:38:52.657705 0 : 4252, 4027
7446 00:38:52.661299 4 : 4252, 4027
7447 00:38:52.661383 8 : 4257, 4029
7448 00:38:52.664806 12 : 4260, 4032
7449 00:38:52.664916 16 : 4255, 4029
7450 00:38:52.667998 20 : 4252, 4027
7451 00:38:52.668081 24 : 4257, 4029
7452 00:38:52.671080 28 : 4252, 4027
7453 00:38:52.671164 32 : 4250, 4027
7454 00:38:52.671231 36 : 4252, 4026
7455 00:38:52.674441 40 : 4253, 4029
7456 00:38:52.674524 44 : 4363, 4137
7457 00:38:52.678202 48 : 4363, 4140
7458 00:38:52.678285 52 : 4252, 4027
7459 00:38:52.680944 56 : 4255, 4029
7460 00:38:52.681041 60 : 4255, 4029
7461 00:38:52.684416 64 : 4365, 4140
7462 00:38:52.684500 68 : 4363, 4140
7463 00:38:52.684566 72 : 4255, 4029
7464 00:38:52.687870 76 : 4253, 4029
7465 00:38:52.687980 80 : 4255, 4029
7466 00:38:52.691413 84 : 4250, 4027
7467 00:38:52.691496 88 : 4360, 4138
7468 00:38:52.694278 92 : 4250, 4027
7469 00:38:52.694362 96 : 4250, 3531
7470 00:38:52.694428 100 : 4363, 0
7471 00:38:52.698051 104 : 4250, 0
7472 00:38:52.698134 108 : 4255, 0
7473 00:38:52.701299 112 : 4250, 0
7474 00:38:52.701382 116 : 4255, 0
7475 00:38:52.701448 120 : 4257, 0
7476 00:38:52.704292 124 : 4361, 0
7477 00:38:52.704375 128 : 4360, 0
7478 00:38:52.707592 132 : 4252, 0
7479 00:38:52.707675 136 : 4254, 0
7480 00:38:52.707741 140 : 4252, 0
7481 00:38:52.711039 144 : 4363, 0
7482 00:38:52.711122 148 : 4368, 0
7483 00:38:52.711188 152 : 4252, 0
7484 00:38:52.714679 156 : 4253, 0
7485 00:38:52.714762 160 : 4255, 0
7486 00:38:52.717815 164 : 4252, 0
7487 00:38:52.717899 168 : 4250, 0
7488 00:38:52.717964 172 : 4252, 0
7489 00:38:52.721271 176 : 4253, 0
7490 00:38:52.721354 180 : 4361, 0
7491 00:38:52.724018 184 : 4252, 0
7492 00:38:52.724101 188 : 4252, 0
7493 00:38:52.724167 192 : 4250, 0
7494 00:38:52.727861 196 : 4360, 0
7495 00:38:52.727945 200 : 4366, 0
7496 00:38:52.731117 204 : 4363, 0
7497 00:38:52.731200 208 : 4360, 0
7498 00:38:52.731266 212 : 4252, 88
7499 00:38:52.734678 216 : 4250, 3189
7500 00:38:52.734762 220 : 4252, 4029
7501 00:38:52.737970 224 : 4250, 4027
7502 00:38:52.738053 228 : 4363, 4140
7503 00:38:52.741349 232 : 4363, 4138
7504 00:38:52.741433 236 : 4253, 4029
7505 00:38:52.744409 240 : 4363, 4138
7506 00:38:52.744492 244 : 4250, 4027
7507 00:38:52.744558 248 : 4252, 4029
7508 00:38:52.747704 252 : 4253, 4026
7509 00:38:52.747787 256 : 4257, 4029
7510 00:38:52.750976 260 : 4250, 4026
7511 00:38:52.751060 264 : 4360, 4137
7512 00:38:52.754466 268 : 4250, 4027
7513 00:38:52.754549 272 : 4255, 4029
7514 00:38:52.757345 276 : 4252, 4027
7515 00:38:52.757428 280 : 4250, 4027
7516 00:38:52.761054 284 : 4363, 4138
7517 00:38:52.761137 288 : 4250, 4027
7518 00:38:52.764538 292 : 4362, 4140
7519 00:38:52.764621 296 : 4250, 4027
7520 00:38:52.767708 300 : 4255, 4029
7521 00:38:52.767791 304 : 4366, 4140
7522 00:38:52.767858 308 : 4252, 4027
7523 00:38:52.771204 312 : 4255, 4029
7524 00:38:52.771287 316 : 4252, 4030
7525 00:38:52.774649 320 : 4250, 4026
7526 00:38:52.774733 324 : 4363, 4139
7527 00:38:52.777663 328 : 4250, 4027
7528 00:38:52.777746 332 : 4255, 3010
7529 00:38:52.780907 336 : 4255, 208
7530 00:38:52.781032
7531 00:38:52.784068 MIOCK jitter meter ch=0
7532 00:38:52.784149
7533 00:38:52.784214 1T = (336-100) = 236 dly cells
7534 00:38:52.790778 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7535 00:38:52.790862 ==
7536 00:38:52.794755 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 00:38:52.797921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 00:38:52.798003 ==
7539 00:38:52.804354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 00:38:52.808290 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 00:38:52.814504 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 00:38:52.817318 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 00:38:52.827629 [CA 0] Center 44 (14~75) winsize 62
7544 00:38:52.830766 [CA 1] Center 44 (13~75) winsize 63
7545 00:38:52.834469 [CA 2] Center 40 (11~69) winsize 59
7546 00:38:52.837844 [CA 3] Center 39 (10~69) winsize 60
7547 00:38:52.841273 [CA 4] Center 38 (8~68) winsize 61
7548 00:38:52.844255 [CA 5] Center 37 (7~67) winsize 61
7549 00:38:52.844337
7550 00:38:52.847560 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 00:38:52.847643
7552 00:38:52.850652 [CATrainingPosCal] consider 1 rank data
7553 00:38:52.854571 u2DelayCellTimex100 = 275/100 ps
7554 00:38:52.857617 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7555 00:38:52.864753 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7556 00:38:52.867497 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7557 00:38:52.870983 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7558 00:38:52.874195 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7559 00:38:52.877799 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 00:38:52.877881
7561 00:38:52.881328 CA PerBit enable=1, Macro0, CA PI delay=37
7562 00:38:52.881410
7563 00:38:52.884290 [CBTSetCACLKResult] CA Dly = 37
7564 00:38:52.887766 CS Dly: 10 (0~41)
7565 00:38:52.890917 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 00:38:52.894354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 00:38:52.894436 ==
7568 00:38:52.898017 Dram Type= 6, Freq= 0, CH_0, rank 1
7569 00:38:52.901015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 00:38:52.904079 ==
7571 00:38:52.908167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 00:38:52.911686 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 00:38:52.917453 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 00:38:52.920872 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 00:38:52.931175 [CA 0] Center 44 (14~75) winsize 62
7576 00:38:52.935239 [CA 1] Center 44 (14~75) winsize 62
7577 00:38:52.938169 [CA 2] Center 40 (11~69) winsize 59
7578 00:38:52.942054 [CA 3] Center 39 (10~69) winsize 60
7579 00:38:52.944773 [CA 4] Center 37 (8~67) winsize 60
7580 00:38:52.948735 [CA 5] Center 37 (7~67) winsize 61
7581 00:38:52.948817
7582 00:38:52.952135 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 00:38:52.952218
7584 00:38:52.955264 [CATrainingPosCal] consider 2 rank data
7585 00:38:52.958282 u2DelayCellTimex100 = 275/100 ps
7586 00:38:52.961624 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7587 00:38:52.968508 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7588 00:38:52.971445 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7589 00:38:52.974860 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7590 00:38:52.977979 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7591 00:38:52.981555 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7592 00:38:52.981637
7593 00:38:52.984677 CA PerBit enable=1, Macro0, CA PI delay=37
7594 00:38:52.984758
7595 00:38:52.988060 [CBTSetCACLKResult] CA Dly = 37
7596 00:38:52.991612 CS Dly: 11 (0~44)
7597 00:38:52.994731 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 00:38:52.998684 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 00:38:52.998767
7600 00:38:53.002061 ----->DramcWriteLeveling(PI) begin...
7601 00:38:53.002144 ==
7602 00:38:53.005256 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 00:38:53.008412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 00:38:53.011932 ==
7605 00:38:53.012012 Write leveling (Byte 0): 34 => 34
7606 00:38:53.015250 Write leveling (Byte 1): 26 => 26
7607 00:38:53.018772 DramcWriteLeveling(PI) end<-----
7608 00:38:53.018853
7609 00:38:53.018917 ==
7610 00:38:53.022141 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 00:38:53.028412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 00:38:53.028494 ==
7613 00:38:53.028559 [Gating] SW mode calibration
7614 00:38:53.038728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7615 00:38:53.042019 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7616 00:38:53.045716 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 00:38:53.052145 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 00:38:53.055216 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 00:38:53.058598 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 00:38:53.065319 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7621 00:38:53.068522 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7622 00:38:53.072429 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7623 00:38:53.078906 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 00:38:53.082115 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 00:38:53.085515 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 00:38:53.091800 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 00:38:53.095533 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7628 00:38:53.098666 1 5 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
7629 00:38:53.105211 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
7630 00:38:53.108631 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7631 00:38:53.112161 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 00:38:53.115645 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 00:38:53.122263 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 00:38:53.125500 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 00:38:53.128823 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 00:38:53.135292 1 6 16 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7637 00:38:53.138800 1 6 20 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
7638 00:38:53.141991 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 00:38:53.148615 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 00:38:53.152498 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 00:38:53.155676 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 00:38:53.162406 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 00:38:53.165434 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 00:38:53.169204 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 00:38:53.175541 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7646 00:38:53.178833 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 00:38:53.182605 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 00:38:53.188875 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 00:38:53.192337 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 00:38:53.195399 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 00:38:53.199763 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 00:38:53.205365 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 00:38:53.208861 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 00:38:53.212133 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 00:38:53.218732 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 00:38:53.222130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 00:38:53.225818 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 00:38:53.232084 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 00:38:53.235663 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 00:38:53.238562 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7661 00:38:53.245736 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7662 00:38:53.245819 Total UI for P1: 0, mck2ui 16
7663 00:38:53.251992 best dqsien dly found for B0: ( 1, 9, 14)
7664 00:38:53.255712 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 00:38:53.258542 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 00:38:53.262398 Total UI for P1: 0, mck2ui 16
7667 00:38:53.266071 best dqsien dly found for B1: ( 1, 9, 22)
7668 00:38:53.268850 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7669 00:38:53.272402 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7670 00:38:53.272485
7671 00:38:53.278673 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7672 00:38:53.282430 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7673 00:38:53.282513 [Gating] SW calibration Done
7674 00:38:53.285316 ==
7675 00:38:53.288900 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 00:38:53.292457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 00:38:53.292541 ==
7678 00:38:53.292606 RX Vref Scan: 0
7679 00:38:53.292667
7680 00:38:53.295653 RX Vref 0 -> 0, step: 1
7681 00:38:53.295740
7682 00:38:53.298783 RX Delay 0 -> 252, step: 8
7683 00:38:53.302569 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7684 00:38:53.305456 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7685 00:38:53.309081 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7686 00:38:53.315384 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7687 00:38:53.318584 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7688 00:38:53.322683 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7689 00:38:53.325247 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7690 00:38:53.328802 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7691 00:38:53.332787 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7692 00:38:53.338946 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7693 00:38:53.342680 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7694 00:38:53.345327 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7695 00:38:53.348609 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7696 00:38:53.355241 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7697 00:38:53.359133 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7698 00:38:53.361960 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7699 00:38:53.362043 ==
7700 00:38:53.365454 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 00:38:53.368875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 00:38:53.368958 ==
7703 00:38:53.372489 DQS Delay:
7704 00:38:53.372571 DQS0 = 0, DQS1 = 0
7705 00:38:53.376160 DQM Delay:
7706 00:38:53.376242 DQM0 = 132, DQM1 = 125
7707 00:38:53.376307 DQ Delay:
7708 00:38:53.378945 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7709 00:38:53.382054 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7710 00:38:53.388943 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7711 00:38:53.392267 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7712 00:38:53.392349
7713 00:38:53.392412
7714 00:38:53.392471 ==
7715 00:38:53.395970 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 00:38:53.399310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 00:38:53.399392 ==
7718 00:38:53.399456
7719 00:38:53.399516
7720 00:38:53.402613 TX Vref Scan disable
7721 00:38:53.402705 == TX Byte 0 ==
7722 00:38:53.408884 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7723 00:38:53.412103 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7724 00:38:53.412184 == TX Byte 1 ==
7725 00:38:53.419612 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7726 00:38:53.422190 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7727 00:38:53.422272 ==
7728 00:38:53.425584 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 00:38:53.428569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 00:38:53.428651 ==
7731 00:38:53.445004
7732 00:38:53.448866 TX Vref early break, caculate TX vref
7733 00:38:53.452437 TX Vref=16, minBit 7, minWin=21, winSum=358
7734 00:38:53.455000 TX Vref=18, minBit 4, minWin=22, winSum=371
7735 00:38:53.458641 TX Vref=20, minBit 8, minWin=22, winSum=381
7736 00:38:53.461960 TX Vref=22, minBit 9, minWin=23, winSum=392
7737 00:38:53.465195 TX Vref=24, minBit 1, minWin=24, winSum=400
7738 00:38:53.468946 TX Vref=26, minBit 0, minWin=25, winSum=414
7739 00:38:53.475368 TX Vref=28, minBit 4, minWin=25, winSum=420
7740 00:38:53.478854 TX Vref=30, minBit 4, minWin=25, winSum=418
7741 00:38:53.482167 TX Vref=32, minBit 0, minWin=24, winSum=409
7742 00:38:53.485548 TX Vref=34, minBit 0, minWin=24, winSum=400
7743 00:38:53.489103 TX Vref=36, minBit 4, minWin=23, winSum=388
7744 00:38:53.495426 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 28
7745 00:38:53.495509
7746 00:38:53.498590 Final TX Range 0 Vref 28
7747 00:38:53.498671
7748 00:38:53.498736 ==
7749 00:38:53.502201 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 00:38:53.505589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 00:38:53.505671 ==
7752 00:38:53.505742
7753 00:38:53.505811
7754 00:38:53.508425 TX Vref Scan disable
7755 00:38:53.515864 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7756 00:38:53.515947 == TX Byte 0 ==
7757 00:38:53.518589 u2DelayCellOfst[0]=17 cells (5 PI)
7758 00:38:53.521862 u2DelayCellOfst[1]=21 cells (6 PI)
7759 00:38:53.525145 u2DelayCellOfst[2]=10 cells (3 PI)
7760 00:38:53.528647 u2DelayCellOfst[3]=14 cells (4 PI)
7761 00:38:53.531885 u2DelayCellOfst[4]=10 cells (3 PI)
7762 00:38:53.535093 u2DelayCellOfst[5]=0 cells (0 PI)
7763 00:38:53.539105 u2DelayCellOfst[6]=21 cells (6 PI)
7764 00:38:53.541896 u2DelayCellOfst[7]=21 cells (6 PI)
7765 00:38:53.545932 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7766 00:38:53.548720 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7767 00:38:53.552002 == TX Byte 1 ==
7768 00:38:53.552085 u2DelayCellOfst[8]=0 cells (0 PI)
7769 00:38:53.554977 u2DelayCellOfst[9]=0 cells (0 PI)
7770 00:38:53.558520 u2DelayCellOfst[10]=7 cells (2 PI)
7771 00:38:53.561930 u2DelayCellOfst[11]=0 cells (0 PI)
7772 00:38:53.565195 u2DelayCellOfst[12]=10 cells (3 PI)
7773 00:38:53.568406 u2DelayCellOfst[13]=10 cells (3 PI)
7774 00:38:53.572182 u2DelayCellOfst[14]=17 cells (5 PI)
7775 00:38:53.575028 u2DelayCellOfst[15]=10 cells (3 PI)
7776 00:38:53.578508 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7777 00:38:53.585503 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7778 00:38:53.585585 DramC Write-DBI on
7779 00:38:53.585651 ==
7780 00:38:53.588822 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 00:38:53.591739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 00:38:53.595316 ==
7783 00:38:53.595398
7784 00:38:53.595463
7785 00:38:53.595522 TX Vref Scan disable
7786 00:38:53.598755 == TX Byte 0 ==
7787 00:38:53.602180 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7788 00:38:53.605180 == TX Byte 1 ==
7789 00:38:53.608684 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7790 00:38:53.612287 DramC Write-DBI off
7791 00:38:53.612369
7792 00:38:53.612434 [DATLAT]
7793 00:38:53.612494 Freq=1600, CH0 RK0
7794 00:38:53.612554
7795 00:38:53.615527 DATLAT Default: 0xf
7796 00:38:53.615634 0, 0xFFFF, sum = 0
7797 00:38:53.618953 1, 0xFFFF, sum = 0
7798 00:38:53.619036 2, 0xFFFF, sum = 0
7799 00:38:53.623168 3, 0xFFFF, sum = 0
7800 00:38:53.623252 4, 0xFFFF, sum = 0
7801 00:38:53.625945 5, 0xFFFF, sum = 0
7802 00:38:53.629442 6, 0xFFFF, sum = 0
7803 00:38:53.629525 7, 0xFFFF, sum = 0
7804 00:38:53.632200 8, 0xFFFF, sum = 0
7805 00:38:53.632283 9, 0xFFFF, sum = 0
7806 00:38:53.635944 10, 0xFFFF, sum = 0
7807 00:38:53.636027 11, 0xFFFF, sum = 0
7808 00:38:53.639520 12, 0xFFFF, sum = 0
7809 00:38:53.639604 13, 0xFFFF, sum = 0
7810 00:38:53.642294 14, 0x0, sum = 1
7811 00:38:53.642377 15, 0x0, sum = 2
7812 00:38:53.645995 16, 0x0, sum = 3
7813 00:38:53.646078 17, 0x0, sum = 4
7814 00:38:53.646144 best_step = 15
7815 00:38:53.649290
7816 00:38:53.649371 ==
7817 00:38:53.652206 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 00:38:53.655739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 00:38:53.655822 ==
7820 00:38:53.655887 RX Vref Scan: 1
7821 00:38:53.655949
7822 00:38:53.659149 Set Vref Range= 24 -> 127
7823 00:38:53.659231
7824 00:38:53.662850 RX Vref 24 -> 127, step: 1
7825 00:38:53.662932
7826 00:38:53.665706 RX Delay 11 -> 252, step: 4
7827 00:38:53.665788
7828 00:38:53.669211 Set Vref, RX VrefLevel [Byte0]: 24
7829 00:38:53.672510 [Byte1]: 24
7830 00:38:53.672591
7831 00:38:53.675647 Set Vref, RX VrefLevel [Byte0]: 25
7832 00:38:53.678894 [Byte1]: 25
7833 00:38:53.678976
7834 00:38:53.682454 Set Vref, RX VrefLevel [Byte0]: 26
7835 00:38:53.685627 [Byte1]: 26
7836 00:38:53.689307
7837 00:38:53.689389 Set Vref, RX VrefLevel [Byte0]: 27
7838 00:38:53.692501 [Byte1]: 27
7839 00:38:53.696866
7840 00:38:53.696980 Set Vref, RX VrefLevel [Byte0]: 28
7841 00:38:53.700793 [Byte1]: 28
7842 00:38:53.704085
7843 00:38:53.704192 Set Vref, RX VrefLevel [Byte0]: 29
7844 00:38:53.707848 [Byte1]: 29
7845 00:38:53.712116
7846 00:38:53.712198 Set Vref, RX VrefLevel [Byte0]: 30
7847 00:38:53.715419 [Byte1]: 30
7848 00:38:53.719384
7849 00:38:53.719465 Set Vref, RX VrefLevel [Byte0]: 31
7850 00:38:53.723380 [Byte1]: 31
7851 00:38:53.727432
7852 00:38:53.727514 Set Vref, RX VrefLevel [Byte0]: 32
7853 00:38:53.730783 [Byte1]: 32
7854 00:38:53.735314
7855 00:38:53.735395 Set Vref, RX VrefLevel [Byte0]: 33
7856 00:38:53.738365 [Byte1]: 33
7857 00:38:53.742507
7858 00:38:53.742588 Set Vref, RX VrefLevel [Byte0]: 34
7859 00:38:53.745854 [Byte1]: 34
7860 00:38:53.750946
7861 00:38:53.751028 Set Vref, RX VrefLevel [Byte0]: 35
7862 00:38:53.753446 [Byte1]: 35
7863 00:38:53.757534
7864 00:38:53.757616 Set Vref, RX VrefLevel [Byte0]: 36
7865 00:38:53.760765 [Byte1]: 36
7866 00:38:53.765446
7867 00:38:53.765528 Set Vref, RX VrefLevel [Byte0]: 37
7868 00:38:53.769195 [Byte1]: 37
7869 00:38:53.772801
7870 00:38:53.772909 Set Vref, RX VrefLevel [Byte0]: 38
7871 00:38:53.776001 [Byte1]: 38
7872 00:38:53.780181
7873 00:38:53.780263 Set Vref, RX VrefLevel [Byte0]: 39
7874 00:38:53.783965 [Byte1]: 39
7875 00:38:53.788325
7876 00:38:53.788406 Set Vref, RX VrefLevel [Byte0]: 40
7877 00:38:53.791347 [Byte1]: 40
7878 00:38:53.795749
7879 00:38:53.795831 Set Vref, RX VrefLevel [Byte0]: 41
7880 00:38:53.799292 [Byte1]: 41
7881 00:38:53.803652
7882 00:38:53.803734 Set Vref, RX VrefLevel [Byte0]: 42
7883 00:38:53.806922 [Byte1]: 42
7884 00:38:53.810737
7885 00:38:53.810819 Set Vref, RX VrefLevel [Byte0]: 43
7886 00:38:53.814093 [Byte1]: 43
7887 00:38:53.818608
7888 00:38:53.818689 Set Vref, RX VrefLevel [Byte0]: 44
7889 00:38:53.821912 [Byte1]: 44
7890 00:38:53.826045
7891 00:38:53.826126 Set Vref, RX VrefLevel [Byte0]: 45
7892 00:38:53.829425 [Byte1]: 45
7893 00:38:53.834165
7894 00:38:53.834247 Set Vref, RX VrefLevel [Byte0]: 46
7895 00:38:53.836953 [Byte1]: 46
7896 00:38:53.841407
7897 00:38:53.841489 Set Vref, RX VrefLevel [Byte0]: 47
7898 00:38:53.844582 [Byte1]: 47
7899 00:38:53.848695
7900 00:38:53.848777 Set Vref, RX VrefLevel [Byte0]: 48
7901 00:38:53.852802 [Byte1]: 48
7902 00:38:53.856711
7903 00:38:53.856793 Set Vref, RX VrefLevel [Byte0]: 49
7904 00:38:53.860042 [Byte1]: 49
7905 00:38:53.864390
7906 00:38:53.864471 Set Vref, RX VrefLevel [Byte0]: 50
7907 00:38:53.868056 [Byte1]: 50
7908 00:38:53.872026
7909 00:38:53.872108 Set Vref, RX VrefLevel [Byte0]: 51
7910 00:38:53.875018 [Byte1]: 51
7911 00:38:53.879643
7912 00:38:53.879777 Set Vref, RX VrefLevel [Byte0]: 52
7913 00:38:53.882744 [Byte1]: 52
7914 00:38:53.886860
7915 00:38:53.886944 Set Vref, RX VrefLevel [Byte0]: 53
7916 00:38:53.890268 [Byte1]: 53
7917 00:38:53.894890
7918 00:38:53.894971 Set Vref, RX VrefLevel [Byte0]: 54
7919 00:38:53.897816 [Byte1]: 54
7920 00:38:53.902087
7921 00:38:53.902168 Set Vref, RX VrefLevel [Byte0]: 55
7922 00:38:53.908840 [Byte1]: 55
7923 00:38:53.908922
7924 00:38:53.911968 Set Vref, RX VrefLevel [Byte0]: 56
7925 00:38:53.915366 [Byte1]: 56
7926 00:38:53.915448
7927 00:38:53.918749 Set Vref, RX VrefLevel [Byte0]: 57
7928 00:38:53.922121 [Byte1]: 57
7929 00:38:53.922204
7930 00:38:53.925445 Set Vref, RX VrefLevel [Byte0]: 58
7931 00:38:53.929278 [Byte1]: 58
7932 00:38:53.932540
7933 00:38:53.932640 Set Vref, RX VrefLevel [Byte0]: 59
7934 00:38:53.935781 [Byte1]: 59
7935 00:38:53.940045
7936 00:38:53.940155 Set Vref, RX VrefLevel [Byte0]: 60
7937 00:38:53.943923 [Byte1]: 60
7938 00:38:53.947943
7939 00:38:53.948027 Set Vref, RX VrefLevel [Byte0]: 61
7940 00:38:53.951112 [Byte1]: 61
7941 00:38:53.955562
7942 00:38:53.955644 Set Vref, RX VrefLevel [Byte0]: 62
7943 00:38:53.958824 [Byte1]: 62
7944 00:38:53.962859
7945 00:38:53.962941 Set Vref, RX VrefLevel [Byte0]: 63
7946 00:38:53.966463 [Byte1]: 63
7947 00:38:53.970890
7948 00:38:53.970974 Set Vref, RX VrefLevel [Byte0]: 64
7949 00:38:53.974177 [Byte1]: 64
7950 00:38:53.978381
7951 00:38:53.978464 Set Vref, RX VrefLevel [Byte0]: 65
7952 00:38:53.981955 [Byte1]: 65
7953 00:38:53.986346
7954 00:38:53.986453 Set Vref, RX VrefLevel [Byte0]: 66
7955 00:38:53.989108 [Byte1]: 66
7956 00:38:53.993773
7957 00:38:53.993858 Set Vref, RX VrefLevel [Byte0]: 67
7958 00:38:53.996854 [Byte1]: 67
7959 00:38:54.000886
7960 00:38:54.000992 Set Vref, RX VrefLevel [Byte0]: 68
7961 00:38:54.004436 [Byte1]: 68
7962 00:38:54.008848
7963 00:38:54.008931 Set Vref, RX VrefLevel [Byte0]: 69
7964 00:38:54.012334 [Byte1]: 69
7965 00:38:54.017117
7966 00:38:54.017198 Set Vref, RX VrefLevel [Byte0]: 70
7967 00:38:54.019575 [Byte1]: 70
7968 00:38:54.023773
7969 00:38:54.023855 Set Vref, RX VrefLevel [Byte0]: 71
7970 00:38:54.027261 [Byte1]: 71
7971 00:38:54.031768
7972 00:38:54.031870 Set Vref, RX VrefLevel [Byte0]: 72
7973 00:38:54.034835 [Byte1]: 72
7974 00:38:54.039493
7975 00:38:54.039599 Set Vref, RX VrefLevel [Byte0]: 73
7976 00:38:54.042736 [Byte1]: 73
7977 00:38:54.046882
7978 00:38:54.046966 Set Vref, RX VrefLevel [Byte0]: 74
7979 00:38:54.049954 [Byte1]: 74
7980 00:38:54.054907
7981 00:38:54.054991 Set Vref, RX VrefLevel [Byte0]: 75
7982 00:38:54.058239 [Byte1]: 75
7983 00:38:54.062218
7984 00:38:54.062303 Final RX Vref Byte 0 = 54 to rank0
7985 00:38:54.065720 Final RX Vref Byte 1 = 62 to rank0
7986 00:38:54.068883 Final RX Vref Byte 0 = 54 to rank1
7987 00:38:54.072286 Final RX Vref Byte 1 = 62 to rank1==
7988 00:38:54.075996 Dram Type= 6, Freq= 0, CH_0, rank 0
7989 00:38:54.078710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 00:38:54.082149 ==
7991 00:38:54.082233 DQS Delay:
7992 00:38:54.082299 DQS0 = 0, DQS1 = 0
7993 00:38:54.085645 DQM Delay:
7994 00:38:54.085727 DQM0 = 129, DQM1 = 122
7995 00:38:54.089340 DQ Delay:
7996 00:38:54.092605 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =126
7997 00:38:54.095974 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138
7998 00:38:54.098827 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7999 00:38:54.102481 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
8000 00:38:54.102564
8001 00:38:54.102630
8002 00:38:54.102689
8003 00:38:54.105781 [DramC_TX_OE_Calibration] TA2
8004 00:38:54.108698 Original DQ_B0 (3 6) =30, OEN = 27
8005 00:38:54.112044 Original DQ_B1 (3 6) =30, OEN = 27
8006 00:38:54.115842 24, 0x0, End_B0=24 End_B1=24
8007 00:38:54.115925 25, 0x0, End_B0=25 End_B1=25
8008 00:38:54.118795 26, 0x0, End_B0=26 End_B1=26
8009 00:38:54.121944 27, 0x0, End_B0=27 End_B1=27
8010 00:38:54.125247 28, 0x0, End_B0=28 End_B1=28
8011 00:38:54.125331 29, 0x0, End_B0=29 End_B1=29
8012 00:38:54.128821 30, 0x0, End_B0=30 End_B1=30
8013 00:38:54.132086 31, 0x4141, End_B0=30 End_B1=30
8014 00:38:54.135944 Byte0 end_step=30 best_step=27
8015 00:38:54.138703 Byte1 end_step=30 best_step=27
8016 00:38:54.142493 Byte0 TX OE(2T, 0.5T) = (3, 3)
8017 00:38:54.142576 Byte1 TX OE(2T, 0.5T) = (3, 3)
8018 00:38:54.142645
8019 00:38:54.142706
8020 00:38:54.151873 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8021 00:38:54.155437 CH0 RK0: MR19=303, MR18=1408
8022 00:38:54.162110 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
8023 00:38:54.162193
8024 00:38:54.165931 ----->DramcWriteLeveling(PI) begin...
8025 00:38:54.166015 ==
8026 00:38:54.168813 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 00:38:54.172476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 00:38:54.172559 ==
8029 00:38:54.175517 Write leveling (Byte 0): 34 => 34
8030 00:38:54.179072 Write leveling (Byte 1): 27 => 27
8031 00:38:54.183112 DramcWriteLeveling(PI) end<-----
8032 00:38:54.183194
8033 00:38:54.183259 ==
8034 00:38:54.185763 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 00:38:54.188805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 00:38:54.188887 ==
8037 00:38:54.192331 [Gating] SW mode calibration
8038 00:38:54.198738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8039 00:38:54.205482 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8040 00:38:54.208847 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 00:38:54.212068 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 00:38:54.218856 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 00:38:54.222482 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8044 00:38:54.225681 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8045 00:38:54.228921 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8046 00:38:54.235702 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8047 00:38:54.239284 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 00:38:54.242407 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 00:38:54.249030 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 00:38:54.252179 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
8051 00:38:54.256520 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8052 00:38:54.262433 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8053 00:38:54.265522 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8054 00:38:54.269317 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 00:38:54.275836 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 00:38:54.279049 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 00:38:54.282390 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 00:38:54.288950 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8059 00:38:54.292699 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8060 00:38:54.296116 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8061 00:38:54.299422 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8062 00:38:54.306125 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 00:38:54.308956 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 00:38:54.312620 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 00:38:54.319874 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 00:38:54.322514 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 00:38:54.325733 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8068 00:38:54.332446 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8069 00:38:54.335717 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8070 00:38:54.339281 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8071 00:38:54.346156 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 00:38:54.348840 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 00:38:54.352745 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 00:38:54.359435 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 00:38:54.362337 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 00:38:54.365799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 00:38:54.372302 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 00:38:54.375436 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 00:38:54.378725 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 00:38:54.385808 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 00:38:54.388610 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 00:38:54.391887 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8083 00:38:54.398986 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8084 00:38:54.401939 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8085 00:38:54.405295 Total UI for P1: 0, mck2ui 16
8086 00:38:54.408821 best dqsien dly found for B0: ( 1, 9, 10)
8087 00:38:54.411884 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8088 00:38:54.419405 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8089 00:38:54.422068 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 00:38:54.425316 Total UI for P1: 0, mck2ui 16
8091 00:38:54.428911 best dqsien dly found for B1: ( 1, 9, 20)
8092 00:38:54.432149 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8093 00:38:54.435380 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8094 00:38:54.435464
8095 00:38:54.438703 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8096 00:38:54.442223 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8097 00:38:54.445528 [Gating] SW calibration Done
8098 00:38:54.445610 ==
8099 00:38:54.448869 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 00:38:54.452001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 00:38:54.452084 ==
8102 00:38:54.455587 RX Vref Scan: 0
8103 00:38:54.455696
8104 00:38:54.458898 RX Vref 0 -> 0, step: 1
8105 00:38:54.459005
8106 00:38:54.459101 RX Delay 0 -> 252, step: 8
8107 00:38:54.465499 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8108 00:38:54.469252 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8109 00:38:54.472109 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8110 00:38:54.475466 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8111 00:38:54.478933 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8112 00:38:54.485663 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8113 00:38:54.488759 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8114 00:38:54.492066 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8115 00:38:54.495498 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8116 00:38:54.498980 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8117 00:38:54.501916 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8118 00:38:54.509025 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8119 00:38:54.512247 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8120 00:38:54.515514 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8121 00:38:54.518882 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8122 00:38:54.525330 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8123 00:38:54.525432 ==
8124 00:38:54.529087 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 00:38:54.532404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 00:38:54.532506 ==
8127 00:38:54.532602 DQS Delay:
8128 00:38:54.535685 DQS0 = 0, DQS1 = 0
8129 00:38:54.535788 DQM Delay:
8130 00:38:54.538683 DQM0 = 130, DQM1 = 124
8131 00:38:54.538779 DQ Delay:
8132 00:38:54.542456 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8133 00:38:54.545223 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8134 00:38:54.549017 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8135 00:38:54.552526 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8136 00:38:54.552622
8137 00:38:54.552722
8138 00:38:54.555431 ==
8139 00:38:54.555533 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 00:38:54.562103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 00:38:54.562177 ==
8142 00:38:54.562240
8143 00:38:54.562315
8144 00:38:54.565469 TX Vref Scan disable
8145 00:38:54.565554 == TX Byte 0 ==
8146 00:38:54.569481 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8147 00:38:54.575448 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8148 00:38:54.575557 == TX Byte 1 ==
8149 00:38:54.578770 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8150 00:38:54.585684 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8151 00:38:54.585785 ==
8152 00:38:54.588896 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 00:38:54.592394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 00:38:54.592483 ==
8155 00:38:54.606937
8156 00:38:54.610273 TX Vref early break, caculate TX vref
8157 00:38:54.613775 TX Vref=16, minBit 9, minWin=22, winSum=378
8158 00:38:54.617037 TX Vref=18, minBit 8, minWin=23, winSum=386
8159 00:38:54.620621 TX Vref=20, minBit 9, minWin=23, winSum=396
8160 00:38:54.623659 TX Vref=22, minBit 9, minWin=23, winSum=403
8161 00:38:54.626970 TX Vref=24, minBit 3, minWin=25, winSum=411
8162 00:38:54.633863 TX Vref=26, minBit 8, minWin=25, winSum=420
8163 00:38:54.637167 TX Vref=28, minBit 3, minWin=25, winSum=421
8164 00:38:54.640712 TX Vref=30, minBit 13, minWin=25, winSum=423
8165 00:38:54.643700 TX Vref=32, minBit 4, minWin=24, winSum=412
8166 00:38:54.647145 TX Vref=34, minBit 9, minWin=24, winSum=407
8167 00:38:54.650440 TX Vref=36, minBit 0, minWin=24, winSum=396
8168 00:38:54.657114 [TxChooseVref] Worse bit 13, Min win 25, Win sum 423, Final Vref 30
8169 00:38:54.657191
8170 00:38:54.660643 Final TX Range 0 Vref 30
8171 00:38:54.660750
8172 00:38:54.660840 ==
8173 00:38:54.663718 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 00:38:54.667216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 00:38:54.667303 ==
8176 00:38:54.667366
8177 00:38:54.667425
8178 00:38:54.670198 TX Vref Scan disable
8179 00:38:54.677534 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8180 00:38:54.677617 == TX Byte 0 ==
8181 00:38:54.680352 u2DelayCellOfst[0]=14 cells (4 PI)
8182 00:38:54.683931 u2DelayCellOfst[1]=21 cells (6 PI)
8183 00:38:54.687680 u2DelayCellOfst[2]=10 cells (3 PI)
8184 00:38:54.690536 u2DelayCellOfst[3]=14 cells (4 PI)
8185 00:38:54.693714 u2DelayCellOfst[4]=10 cells (3 PI)
8186 00:38:54.697379 u2DelayCellOfst[5]=0 cells (0 PI)
8187 00:38:54.700552 u2DelayCellOfst[6]=21 cells (6 PI)
8188 00:38:54.703942 u2DelayCellOfst[7]=21 cells (6 PI)
8189 00:38:54.707450 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8190 00:38:54.710399 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8191 00:38:54.714114 == TX Byte 1 ==
8192 00:38:54.717233 u2DelayCellOfst[8]=0 cells (0 PI)
8193 00:38:54.717333 u2DelayCellOfst[9]=0 cells (0 PI)
8194 00:38:54.720619 u2DelayCellOfst[10]=3 cells (1 PI)
8195 00:38:54.724215 u2DelayCellOfst[11]=0 cells (0 PI)
8196 00:38:54.727033 u2DelayCellOfst[12]=10 cells (3 PI)
8197 00:38:54.730566 u2DelayCellOfst[13]=10 cells (3 PI)
8198 00:38:54.733527 u2DelayCellOfst[14]=14 cells (4 PI)
8199 00:38:54.737258 u2DelayCellOfst[15]=10 cells (3 PI)
8200 00:38:54.740388 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8201 00:38:54.747015 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8202 00:38:54.747093 DramC Write-DBI on
8203 00:38:54.747162 ==
8204 00:38:54.750655 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 00:38:54.753669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 00:38:54.757377 ==
8207 00:38:54.757456
8208 00:38:54.757520
8209 00:38:54.757584 TX Vref Scan disable
8210 00:38:54.760709 == TX Byte 0 ==
8211 00:38:54.763901 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8212 00:38:54.767122 == TX Byte 1 ==
8213 00:38:54.770911 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8214 00:38:54.773784 DramC Write-DBI off
8215 00:38:54.773860
8216 00:38:54.773927 [DATLAT]
8217 00:38:54.773993 Freq=1600, CH0 RK1
8218 00:38:54.774051
8219 00:38:54.777417 DATLAT Default: 0xf
8220 00:38:54.777491 0, 0xFFFF, sum = 0
8221 00:38:54.780674 1, 0xFFFF, sum = 0
8222 00:38:54.780778 2, 0xFFFF, sum = 0
8223 00:38:54.784120 3, 0xFFFF, sum = 0
8224 00:38:54.784222 4, 0xFFFF, sum = 0
8225 00:38:54.787895 5, 0xFFFF, sum = 0
8226 00:38:54.790897 6, 0xFFFF, sum = 0
8227 00:38:54.791001 7, 0xFFFF, sum = 0
8228 00:38:54.794186 8, 0xFFFF, sum = 0
8229 00:38:54.794263 9, 0xFFFF, sum = 0
8230 00:38:54.797692 10, 0xFFFF, sum = 0
8231 00:38:54.797793 11, 0xFFFF, sum = 0
8232 00:38:54.800842 12, 0xFFFF, sum = 0
8233 00:38:54.800919 13, 0xFFFF, sum = 0
8234 00:38:54.804393 14, 0x0, sum = 1
8235 00:38:54.804498 15, 0x0, sum = 2
8236 00:38:54.807243 16, 0x0, sum = 3
8237 00:38:54.807318 17, 0x0, sum = 4
8238 00:38:54.810962 best_step = 15
8239 00:38:54.811060
8240 00:38:54.811153 ==
8241 00:38:54.814567 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 00:38:54.817668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 00:38:54.817767 ==
8244 00:38:54.817868 RX Vref Scan: 0
8245 00:38:54.817964
8246 00:38:54.820952 RX Vref 0 -> 0, step: 1
8247 00:38:54.821066
8248 00:38:54.824151 RX Delay 11 -> 252, step: 4
8249 00:38:54.827742 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8250 00:38:54.830663 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8251 00:38:54.837817 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8252 00:38:54.840992 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8253 00:38:54.844533 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8254 00:38:54.847882 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8255 00:38:54.851212 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8256 00:38:54.857798 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8257 00:38:54.861558 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8258 00:38:54.864764 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8259 00:38:54.868097 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8260 00:38:54.871103 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8261 00:38:54.877823 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8262 00:38:54.881304 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8263 00:38:54.885153 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8264 00:38:54.888051 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8265 00:38:54.888133 ==
8266 00:38:54.891568 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 00:38:54.898017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 00:38:54.898099 ==
8269 00:38:54.898165 DQS Delay:
8270 00:38:54.898224 DQS0 = 0, DQS1 = 0
8271 00:38:54.901003 DQM Delay:
8272 00:38:54.901131 DQM0 = 126, DQM1 = 122
8273 00:38:54.904576 DQ Delay:
8274 00:38:54.907720 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8275 00:38:54.911099 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =136
8276 00:38:54.914414 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8277 00:38:54.918178 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8278 00:38:54.918260
8279 00:38:54.918326
8280 00:38:54.918385
8281 00:38:54.921683 [DramC_TX_OE_Calibration] TA2
8282 00:38:54.925050 Original DQ_B0 (3 6) =30, OEN = 27
8283 00:38:54.928133 Original DQ_B1 (3 6) =30, OEN = 27
8284 00:38:54.928215 24, 0x0, End_B0=24 End_B1=24
8285 00:38:54.931503 25, 0x0, End_B0=25 End_B1=25
8286 00:38:54.934967 26, 0x0, End_B0=26 End_B1=26
8287 00:38:54.937595 27, 0x0, End_B0=27 End_B1=27
8288 00:38:54.941176 28, 0x0, End_B0=28 End_B1=28
8289 00:38:54.941260 29, 0x0, End_B0=29 End_B1=29
8290 00:38:54.944409 30, 0x0, End_B0=30 End_B1=30
8291 00:38:54.947771 31, 0x4141, End_B0=30 End_B1=30
8292 00:38:54.951024 Byte0 end_step=30 best_step=27
8293 00:38:54.954372 Byte1 end_step=30 best_step=27
8294 00:38:54.957839 Byte0 TX OE(2T, 0.5T) = (3, 3)
8295 00:38:54.957921 Byte1 TX OE(2T, 0.5T) = (3, 3)
8296 00:38:54.957987
8297 00:38:54.961186
8298 00:38:54.968013 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8299 00:38:54.971166 CH0 RK1: MR19=303, MR18=150A
8300 00:38:54.977949 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8301 00:38:54.981317 [RxdqsGatingPostProcess] freq 1600
8302 00:38:54.984813 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8303 00:38:54.987492 best DQS0 dly(2T, 0.5T) = (1, 1)
8304 00:38:54.991348 best DQS1 dly(2T, 0.5T) = (1, 1)
8305 00:38:54.994382 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8306 00:38:54.997503 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8307 00:38:55.001016 best DQS0 dly(2T, 0.5T) = (1, 1)
8308 00:38:55.004084 best DQS1 dly(2T, 0.5T) = (1, 1)
8309 00:38:55.007632 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8310 00:38:55.010751 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8311 00:38:55.010833 Pre-setting of DQS Precalculation
8312 00:38:55.017737 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8313 00:38:55.017819 ==
8314 00:38:55.020988 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 00:38:55.024702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 00:38:55.024786 ==
8317 00:38:55.031233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 00:38:55.034283 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 00:38:55.038021 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 00:38:55.044044 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 00:38:55.054000 [CA 0] Center 43 (14~72) winsize 59
8322 00:38:55.057183 [CA 1] Center 43 (14~72) winsize 59
8323 00:38:55.060871 [CA 2] Center 38 (10~67) winsize 58
8324 00:38:55.063784 [CA 3] Center 37 (9~66) winsize 58
8325 00:38:55.067156 [CA 4] Center 38 (9~68) winsize 60
8326 00:38:55.070481 [CA 5] Center 37 (8~66) winsize 59
8327 00:38:55.070564
8328 00:38:55.073953 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 00:38:55.074035
8330 00:38:55.077104 [CATrainingPosCal] consider 1 rank data
8331 00:38:55.080924 u2DelayCellTimex100 = 275/100 ps
8332 00:38:55.083722 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8333 00:38:55.090414 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8334 00:38:55.093909 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8335 00:38:55.097197 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8336 00:38:55.100687 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8337 00:38:55.103854 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8338 00:38:55.103936
8339 00:38:55.107241 CA PerBit enable=1, Macro0, CA PI delay=37
8340 00:38:55.107323
8341 00:38:55.110531 [CBTSetCACLKResult] CA Dly = 37
8342 00:38:55.110613 CS Dly: 8 (0~39)
8343 00:38:55.117270 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 00:38:55.121295 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 00:38:55.121377 ==
8346 00:38:55.124242 Dram Type= 6, Freq= 0, CH_1, rank 1
8347 00:38:55.127492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 00:38:55.127574 ==
8349 00:38:55.133966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 00:38:55.136880 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 00:38:55.143622 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 00:38:55.147189 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 00:38:55.156948 [CA 0] Center 43 (15~72) winsize 58
8354 00:38:55.160472 [CA 1] Center 43 (14~72) winsize 59
8355 00:38:55.164200 [CA 2] Center 37 (8~67) winsize 60
8356 00:38:55.166920 [CA 3] Center 37 (8~67) winsize 60
8357 00:38:55.170388 [CA 4] Center 38 (9~68) winsize 60
8358 00:38:55.173980 [CA 5] Center 37 (8~66) winsize 59
8359 00:38:55.174090
8360 00:38:55.177687 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8361 00:38:55.177786
8362 00:38:55.180245 [CATrainingPosCal] consider 2 rank data
8363 00:38:55.183493 u2DelayCellTimex100 = 275/100 ps
8364 00:38:55.187107 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8365 00:38:55.193471 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8366 00:38:55.197176 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8367 00:38:55.200285 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8368 00:38:55.203988 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8369 00:38:55.207017 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8370 00:38:55.207105
8371 00:38:55.210196 CA PerBit enable=1, Macro0, CA PI delay=37
8372 00:38:55.210308
8373 00:38:55.213831 [CBTSetCACLKResult] CA Dly = 37
8374 00:38:55.217257 CS Dly: 10 (0~43)
8375 00:38:55.220648 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 00:38:55.223644 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 00:38:55.223728
8378 00:38:55.228029 ----->DramcWriteLeveling(PI) begin...
8379 00:38:55.228112 ==
8380 00:38:55.230497 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 00:38:55.233826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 00:38:55.236825 ==
8383 00:38:55.236939 Write leveling (Byte 0): 24 => 24
8384 00:38:55.240500 Write leveling (Byte 1): 30 => 30
8385 00:38:55.243486 DramcWriteLeveling(PI) end<-----
8386 00:38:55.243599
8387 00:38:55.243691 ==
8388 00:38:55.247194 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 00:38:55.253789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 00:38:55.253898 ==
8391 00:38:55.253991 [Gating] SW mode calibration
8392 00:38:55.263733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8393 00:38:55.267046 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8394 00:38:55.270677 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 00:38:55.277613 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 00:38:55.280496 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 00:38:55.283792 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 00:38:55.290475 1 4 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (1 1)
8399 00:38:55.293682 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 00:38:55.297710 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 00:38:55.304876 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 00:38:55.307516 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 00:38:55.310779 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 00:38:55.318122 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 00:38:55.320676 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8406 00:38:55.323880 1 5 16 | B1->B0 | 2c2c 3232 | 1 1 | (1 0) (1 0)
8407 00:38:55.330641 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8408 00:38:55.334204 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 00:38:55.337311 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 00:38:55.340849 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 00:38:55.347248 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 00:38:55.350463 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 00:38:55.354049 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 00:38:55.360789 1 6 16 | B1->B0 | 3e3e 3b3b | 0 0 | (0 0) (0 0)
8415 00:38:55.364141 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 00:38:55.367706 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 00:38:55.373951 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 00:38:55.377210 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 00:38:55.380625 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 00:38:55.387743 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 00:38:55.390668 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 00:38:55.394245 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8423 00:38:55.400486 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8424 00:38:55.404322 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 00:38:55.407772 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 00:38:55.414250 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 00:38:55.417614 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 00:38:55.421246 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 00:38:55.427541 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 00:38:55.430586 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 00:38:55.433909 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 00:38:55.437502 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 00:38:55.444394 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 00:38:55.447423 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 00:38:55.450700 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 00:38:55.457305 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 00:38:55.460902 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8438 00:38:55.464018 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8439 00:38:55.470507 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8440 00:38:55.470587 Total UI for P1: 0, mck2ui 16
8441 00:38:55.477326 best dqsien dly found for B1: ( 1, 9, 14)
8442 00:38:55.480914 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 00:38:55.483825 Total UI for P1: 0, mck2ui 16
8444 00:38:55.487508 best dqsien dly found for B0: ( 1, 9, 16)
8445 00:38:55.490404 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8446 00:38:55.494046 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8447 00:38:55.494136
8448 00:38:55.497526 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8449 00:38:55.500913 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8450 00:38:55.504463 [Gating] SW calibration Done
8451 00:38:55.504570 ==
8452 00:38:55.508083 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 00:38:55.510656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 00:38:55.510757 ==
8455 00:38:55.514020 RX Vref Scan: 0
8456 00:38:55.514125
8457 00:38:55.517771 RX Vref 0 -> 0, step: 1
8458 00:38:55.517880
8459 00:38:55.517975 RX Delay 0 -> 252, step: 8
8460 00:38:55.525016 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8461 00:38:55.527521 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8462 00:38:55.530666 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8463 00:38:55.534467 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8464 00:38:55.537771 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8465 00:38:55.544029 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8466 00:38:55.547877 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8467 00:38:55.551207 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8468 00:38:55.554259 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8469 00:38:55.557731 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8470 00:38:55.564837 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8471 00:38:55.568078 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8472 00:38:55.570736 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8473 00:38:55.574463 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8474 00:38:55.577709 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8475 00:38:55.584314 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8476 00:38:55.584424 ==
8477 00:38:55.587686 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 00:38:55.590748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 00:38:55.590850 ==
8480 00:38:55.590941 DQS Delay:
8481 00:38:55.594238 DQS0 = 0, DQS1 = 0
8482 00:38:55.594339 DQM Delay:
8483 00:38:55.597416 DQM0 = 135, DQM1 = 126
8484 00:38:55.597517 DQ Delay:
8485 00:38:55.601624 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8486 00:38:55.604298 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8487 00:38:55.607759 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8488 00:38:55.610807 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8489 00:38:55.610915
8490 00:38:55.611009
8491 00:38:55.614330 ==
8492 00:38:55.614431 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 00:38:55.621090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 00:38:55.621170 ==
8495 00:38:55.621235
8496 00:38:55.621303
8497 00:38:55.624136 TX Vref Scan disable
8498 00:38:55.624242 == TX Byte 0 ==
8499 00:38:55.627317 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8500 00:38:55.634772 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 00:38:55.634878 == TX Byte 1 ==
8502 00:38:55.637912 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8503 00:38:55.644365 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8504 00:38:55.644476 ==
8505 00:38:55.647770 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 00:38:55.650736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 00:38:55.650837 ==
8508 00:38:55.664263
8509 00:38:55.667580 TX Vref early break, caculate TX vref
8510 00:38:55.670556 TX Vref=16, minBit 8, minWin=20, winSum=361
8511 00:38:55.674122 TX Vref=18, minBit 8, minWin=21, winSum=366
8512 00:38:55.677207 TX Vref=20, minBit 8, minWin=22, winSum=382
8513 00:38:55.681160 TX Vref=22, minBit 9, minWin=23, winSum=392
8514 00:38:55.684181 TX Vref=24, minBit 8, minWin=23, winSum=401
8515 00:38:55.691036 TX Vref=26, minBit 5, minWin=24, winSum=412
8516 00:38:55.694202 TX Vref=28, minBit 8, minWin=25, winSum=421
8517 00:38:55.697894 TX Vref=30, minBit 1, minWin=25, winSum=419
8518 00:38:55.700944 TX Vref=32, minBit 1, minWin=25, winSum=411
8519 00:38:55.704128 TX Vref=34, minBit 0, minWin=24, winSum=398
8520 00:38:55.711059 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8521 00:38:55.711171
8522 00:38:55.714399 Final TX Range 0 Vref 28
8523 00:38:55.714502
8524 00:38:55.714594 ==
8525 00:38:55.717355 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 00:38:55.721694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 00:38:55.721802 ==
8528 00:38:55.721895
8529 00:38:55.721989
8530 00:38:55.724108 TX Vref Scan disable
8531 00:38:55.730851 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8532 00:38:55.730963 == TX Byte 0 ==
8533 00:38:55.734138 u2DelayCellOfst[0]=17 cells (5 PI)
8534 00:38:55.738008 u2DelayCellOfst[1]=10 cells (3 PI)
8535 00:38:55.741198 u2DelayCellOfst[2]=0 cells (0 PI)
8536 00:38:55.744167 u2DelayCellOfst[3]=7 cells (2 PI)
8537 00:38:55.747806 u2DelayCellOfst[4]=7 cells (2 PI)
8538 00:38:55.747912 u2DelayCellOfst[5]=21 cells (6 PI)
8539 00:38:55.750653 u2DelayCellOfst[6]=17 cells (5 PI)
8540 00:38:55.753943 u2DelayCellOfst[7]=7 cells (2 PI)
8541 00:38:55.760699 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8542 00:38:55.764365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8543 00:38:55.764463 == TX Byte 1 ==
8544 00:38:55.767699 u2DelayCellOfst[8]=0 cells (0 PI)
8545 00:38:55.770694 u2DelayCellOfst[9]=3 cells (1 PI)
8546 00:38:55.774017 u2DelayCellOfst[10]=7 cells (2 PI)
8547 00:38:55.777482 u2DelayCellOfst[11]=3 cells (1 PI)
8548 00:38:55.781100 u2DelayCellOfst[12]=10 cells (3 PI)
8549 00:38:55.784319 u2DelayCellOfst[13]=14 cells (4 PI)
8550 00:38:55.787677 u2DelayCellOfst[14]=14 cells (4 PI)
8551 00:38:55.790960 u2DelayCellOfst[15]=14 cells (4 PI)
8552 00:38:55.793846 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8553 00:38:55.797126 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8554 00:38:55.800784 DramC Write-DBI on
8555 00:38:55.800887 ==
8556 00:38:55.804600 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 00:38:55.807410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 00:38:55.807513 ==
8559 00:38:55.807604
8560 00:38:55.807694
8561 00:38:55.811084 TX Vref Scan disable
8562 00:38:55.814110 == TX Byte 0 ==
8563 00:38:55.817429 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8564 00:38:55.817529 == TX Byte 1 ==
8565 00:38:55.824185 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8566 00:38:55.824291 DramC Write-DBI off
8567 00:38:55.824386
8568 00:38:55.827517 [DATLAT]
8569 00:38:55.827616 Freq=1600, CH1 RK0
8570 00:38:55.827680
8571 00:38:55.830693 DATLAT Default: 0xf
8572 00:38:55.830792 0, 0xFFFF, sum = 0
8573 00:38:55.833964 1, 0xFFFF, sum = 0
8574 00:38:55.834068 2, 0xFFFF, sum = 0
8575 00:38:55.837192 3, 0xFFFF, sum = 0
8576 00:38:55.837292 4, 0xFFFF, sum = 0
8577 00:38:55.840741 5, 0xFFFF, sum = 0
8578 00:38:55.840855 6, 0xFFFF, sum = 0
8579 00:38:55.844575 7, 0xFFFF, sum = 0
8580 00:38:55.844688 8, 0xFFFF, sum = 0
8581 00:38:55.847589 9, 0xFFFF, sum = 0
8582 00:38:55.847691 10, 0xFFFF, sum = 0
8583 00:38:55.851049 11, 0xFFFF, sum = 0
8584 00:38:55.854040 12, 0xFFFF, sum = 0
8585 00:38:55.854147 13, 0xFFFF, sum = 0
8586 00:38:55.857421 14, 0x0, sum = 1
8587 00:38:55.857524 15, 0x0, sum = 2
8588 00:38:55.857623 16, 0x0, sum = 3
8589 00:38:55.860510 17, 0x0, sum = 4
8590 00:38:55.860607 best_step = 15
8591 00:38:55.860706
8592 00:38:55.860794 ==
8593 00:38:55.864037 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 00:38:55.870665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 00:38:55.870741 ==
8596 00:38:55.870804 RX Vref Scan: 1
8597 00:38:55.870864
8598 00:38:55.874034 Set Vref Range= 24 -> 127
8599 00:38:55.874106
8600 00:38:55.877282 RX Vref 24 -> 127, step: 1
8601 00:38:55.877358
8602 00:38:55.880818 RX Delay 11 -> 252, step: 4
8603 00:38:55.880922
8604 00:38:55.884508 Set Vref, RX VrefLevel [Byte0]: 24
8605 00:38:55.887314 [Byte1]: 24
8606 00:38:55.887419
8607 00:38:55.890925 Set Vref, RX VrefLevel [Byte0]: 25
8608 00:38:55.894167 [Byte1]: 25
8609 00:38:55.894268
8610 00:38:55.897522 Set Vref, RX VrefLevel [Byte0]: 26
8611 00:38:55.900730 [Byte1]: 26
8612 00:38:55.900830
8613 00:38:55.904284 Set Vref, RX VrefLevel [Byte0]: 27
8614 00:38:55.907739 [Byte1]: 27
8615 00:38:55.911321
8616 00:38:55.911428 Set Vref, RX VrefLevel [Byte0]: 28
8617 00:38:55.914607 [Byte1]: 28
8618 00:38:55.918802
8619 00:38:55.918914 Set Vref, RX VrefLevel [Byte0]: 29
8620 00:38:55.922096 [Byte1]: 29
8621 00:38:55.926666
8622 00:38:55.926769 Set Vref, RX VrefLevel [Byte0]: 30
8623 00:38:55.929860 [Byte1]: 30
8624 00:38:55.934067
8625 00:38:55.934165 Set Vref, RX VrefLevel [Byte0]: 31
8626 00:38:55.937829 [Byte1]: 31
8627 00:38:55.941774
8628 00:38:55.941882 Set Vref, RX VrefLevel [Byte0]: 32
8629 00:38:55.945119 [Byte1]: 32
8630 00:38:55.949616
8631 00:38:55.949715 Set Vref, RX VrefLevel [Byte0]: 33
8632 00:38:55.952744 [Byte1]: 33
8633 00:38:55.956960
8634 00:38:55.957108 Set Vref, RX VrefLevel [Byte0]: 34
8635 00:38:55.960296 [Byte1]: 34
8636 00:38:55.964732
8637 00:38:55.964842 Set Vref, RX VrefLevel [Byte0]: 35
8638 00:38:55.967858 [Byte1]: 35
8639 00:38:55.972198
8640 00:38:55.972272 Set Vref, RX VrefLevel [Byte0]: 36
8641 00:38:55.975666 [Byte1]: 36
8642 00:38:55.980744
8643 00:38:55.980852 Set Vref, RX VrefLevel [Byte0]: 37
8644 00:38:55.983365 [Byte1]: 37
8645 00:38:55.987919
8646 00:38:55.988019 Set Vref, RX VrefLevel [Byte0]: 38
8647 00:38:55.991148 [Byte1]: 38
8648 00:38:55.995219
8649 00:38:55.995326 Set Vref, RX VrefLevel [Byte0]: 39
8650 00:38:55.998769 [Byte1]: 39
8651 00:38:56.002438
8652 00:38:56.002552 Set Vref, RX VrefLevel [Byte0]: 40
8653 00:38:56.005830 [Byte1]: 40
8654 00:38:56.010635
8655 00:38:56.010712 Set Vref, RX VrefLevel [Byte0]: 41
8656 00:38:56.013409 [Byte1]: 41
8657 00:38:56.017892
8658 00:38:56.018005 Set Vref, RX VrefLevel [Byte0]: 42
8659 00:38:56.021460 [Byte1]: 42
8660 00:38:56.025669
8661 00:38:56.025771 Set Vref, RX VrefLevel [Byte0]: 43
8662 00:38:56.028768 [Byte1]: 43
8663 00:38:56.033406
8664 00:38:56.033507 Set Vref, RX VrefLevel [Byte0]: 44
8665 00:38:56.036463 [Byte1]: 44
8666 00:38:56.040915
8667 00:38:56.041048 Set Vref, RX VrefLevel [Byte0]: 45
8668 00:38:56.043908 [Byte1]: 45
8669 00:38:56.048232
8670 00:38:56.048334 Set Vref, RX VrefLevel [Byte0]: 46
8671 00:38:56.051777 [Byte1]: 46
8672 00:38:56.056216
8673 00:38:56.056324 Set Vref, RX VrefLevel [Byte0]: 47
8674 00:38:56.059323 [Byte1]: 47
8675 00:38:56.063396
8676 00:38:56.063496 Set Vref, RX VrefLevel [Byte0]: 48
8677 00:38:56.067124 [Byte1]: 48
8678 00:38:56.071264
8679 00:38:56.071365 Set Vref, RX VrefLevel [Byte0]: 49
8680 00:38:56.075094 [Byte1]: 49
8681 00:38:56.078885
8682 00:38:56.078989 Set Vref, RX VrefLevel [Byte0]: 50
8683 00:38:56.082113 [Byte1]: 50
8684 00:38:56.086652
8685 00:38:56.086757 Set Vref, RX VrefLevel [Byte0]: 51
8686 00:38:56.089844 [Byte1]: 51
8687 00:38:56.093852
8688 00:38:56.093953 Set Vref, RX VrefLevel [Byte0]: 52
8689 00:38:56.097293 [Byte1]: 52
8690 00:38:56.101661
8691 00:38:56.101762 Set Vref, RX VrefLevel [Byte0]: 53
8692 00:38:56.104878 [Byte1]: 53
8693 00:38:56.109318
8694 00:38:56.109422 Set Vref, RX VrefLevel [Byte0]: 54
8695 00:38:56.112296 [Byte1]: 54
8696 00:38:56.116905
8697 00:38:56.117045 Set Vref, RX VrefLevel [Byte0]: 55
8698 00:38:56.119921 [Byte1]: 55
8699 00:38:56.124817
8700 00:38:56.124924 Set Vref, RX VrefLevel [Byte0]: 56
8701 00:38:56.127823 [Byte1]: 56
8702 00:38:56.131855
8703 00:38:56.131959 Set Vref, RX VrefLevel [Byte0]: 57
8704 00:38:56.135294 [Byte1]: 57
8705 00:38:56.139507
8706 00:38:56.139611 Set Vref, RX VrefLevel [Byte0]: 58
8707 00:38:56.143051 [Byte1]: 58
8708 00:38:56.147452
8709 00:38:56.147555 Set Vref, RX VrefLevel [Byte0]: 59
8710 00:38:56.150558 [Byte1]: 59
8711 00:38:56.155295
8712 00:38:56.155397 Set Vref, RX VrefLevel [Byte0]: 60
8713 00:38:56.158034 [Byte1]: 60
8714 00:38:56.162755
8715 00:38:56.162854 Set Vref, RX VrefLevel [Byte0]: 61
8716 00:38:56.166214 [Byte1]: 61
8717 00:38:56.170462
8718 00:38:56.170573 Set Vref, RX VrefLevel [Byte0]: 62
8719 00:38:56.173653 [Byte1]: 62
8720 00:38:56.177974
8721 00:38:56.178074 Set Vref, RX VrefLevel [Byte0]: 63
8722 00:38:56.180918 [Byte1]: 63
8723 00:38:56.185981
8724 00:38:56.186061 Set Vref, RX VrefLevel [Byte0]: 64
8725 00:38:56.188644 [Byte1]: 64
8726 00:38:56.192725
8727 00:38:56.192827 Set Vref, RX VrefLevel [Byte0]: 65
8728 00:38:56.196306 [Byte1]: 65
8729 00:38:56.200399
8730 00:38:56.200502 Set Vref, RX VrefLevel [Byte0]: 66
8731 00:38:56.203902 [Byte1]: 66
8732 00:38:56.208426
8733 00:38:56.208509 Set Vref, RX VrefLevel [Byte0]: 67
8734 00:38:56.212178 [Byte1]: 67
8735 00:38:56.216102
8736 00:38:56.216210 Set Vref, RX VrefLevel [Byte0]: 68
8737 00:38:56.219286 [Byte1]: 68
8738 00:38:56.223747
8739 00:38:56.223854 Set Vref, RX VrefLevel [Byte0]: 69
8740 00:38:56.226906 [Byte1]: 69
8741 00:38:56.230892
8742 00:38:56.230991 Set Vref, RX VrefLevel [Byte0]: 70
8743 00:38:56.234246 [Byte1]: 70
8744 00:38:56.238473
8745 00:38:56.238571 Set Vref, RX VrefLevel [Byte0]: 71
8746 00:38:56.242050 [Byte1]: 71
8747 00:38:56.246241
8748 00:38:56.246335 Set Vref, RX VrefLevel [Byte0]: 72
8749 00:38:56.249405 [Byte1]: 72
8750 00:38:56.253944
8751 00:38:56.254026 Set Vref, RX VrefLevel [Byte0]: 73
8752 00:38:56.257060 [Byte1]: 73
8753 00:38:56.261812
8754 00:38:56.261892 Set Vref, RX VrefLevel [Byte0]: 74
8755 00:38:56.264989 [Byte1]: 74
8756 00:38:56.269702
8757 00:38:56.269777 Final RX Vref Byte 0 = 56 to rank0
8758 00:38:56.272693 Final RX Vref Byte 1 = 56 to rank0
8759 00:38:56.275887 Final RX Vref Byte 0 = 56 to rank1
8760 00:38:56.278863 Final RX Vref Byte 1 = 56 to rank1==
8761 00:38:56.282391 Dram Type= 6, Freq= 0, CH_1, rank 0
8762 00:38:56.289235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 00:38:56.289341 ==
8764 00:38:56.289433 DQS Delay:
8765 00:38:56.289511 DQS0 = 0, DQS1 = 0
8766 00:38:56.292191 DQM Delay:
8767 00:38:56.292295 DQM0 = 131, DQM1 = 124
8768 00:38:56.295823 DQ Delay:
8769 00:38:56.298927 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8770 00:38:56.302711 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8771 00:38:56.305648 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8772 00:38:56.308796 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8773 00:38:56.308898
8774 00:38:56.309012
8775 00:38:56.309110
8776 00:38:56.312186 [DramC_TX_OE_Calibration] TA2
8777 00:38:56.315959 Original DQ_B0 (3 6) =30, OEN = 27
8778 00:38:56.319043 Original DQ_B1 (3 6) =30, OEN = 27
8779 00:38:56.322523 24, 0x0, End_B0=24 End_B1=24
8780 00:38:56.322626 25, 0x0, End_B0=25 End_B1=25
8781 00:38:56.325517 26, 0x0, End_B0=26 End_B1=26
8782 00:38:56.329143 27, 0x0, End_B0=27 End_B1=27
8783 00:38:56.332588 28, 0x0, End_B0=28 End_B1=28
8784 00:38:56.332698 29, 0x0, End_B0=29 End_B1=29
8785 00:38:56.335734 30, 0x0, End_B0=30 End_B1=30
8786 00:38:56.339104 31, 0x5151, End_B0=30 End_B1=30
8787 00:38:56.342735 Byte0 end_step=30 best_step=27
8788 00:38:56.345870 Byte1 end_step=30 best_step=27
8789 00:38:56.349879 Byte0 TX OE(2T, 0.5T) = (3, 3)
8790 00:38:56.349979 Byte1 TX OE(2T, 0.5T) = (3, 3)
8791 00:38:56.350061
8792 00:38:56.352851
8793 00:38:56.358739 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8794 00:38:56.362461 CH1 RK0: MR19=303, MR18=1701
8795 00:38:56.369134 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8796 00:38:56.369232
8797 00:38:56.372472 ----->DramcWriteLeveling(PI) begin...
8798 00:38:56.372580 ==
8799 00:38:56.375847 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 00:38:56.378722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 00:38:56.378826 ==
8802 00:38:56.383039 Write leveling (Byte 0): 25 => 25
8803 00:38:56.386124 Write leveling (Byte 1): 27 => 27
8804 00:38:56.389001 DramcWriteLeveling(PI) end<-----
8805 00:38:56.389091
8806 00:38:56.389158 ==
8807 00:38:56.392550 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 00:38:56.395991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 00:38:56.396090 ==
8810 00:38:56.398804 [Gating] SW mode calibration
8811 00:38:56.406053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8812 00:38:56.412343 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8813 00:38:56.416035 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 00:38:56.418991 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 00:38:56.425754 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8816 00:38:56.429289 1 4 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8817 00:38:56.432623 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 00:38:56.438976 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 00:38:56.442359 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 00:38:56.445507 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 00:38:56.452374 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 00:38:56.455853 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8823 00:38:56.458988 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8824 00:38:56.465667 1 5 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8825 00:38:56.468790 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 00:38:56.472465 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 00:38:56.475855 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 00:38:56.482072 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 00:38:56.486524 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 00:38:56.489184 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 00:38:56.495474 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8832 00:38:56.499237 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8833 00:38:56.502107 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 00:38:56.509242 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 00:38:56.513196 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 00:38:56.516155 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 00:38:56.522395 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 00:38:56.525351 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 00:38:56.529022 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8840 00:38:56.535533 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8841 00:38:56.538827 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8842 00:38:56.542201 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8843 00:38:56.549440 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 00:38:56.552356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 00:38:56.555717 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 00:38:56.562306 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 00:38:56.565294 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 00:38:56.568956 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 00:38:56.572393 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 00:38:56.579176 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 00:38:56.582404 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 00:38:56.586142 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 00:38:56.592793 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 00:38:56.595448 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8855 00:38:56.599148 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8856 00:38:56.605477 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8857 00:38:56.608806 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 00:38:56.612112 Total UI for P1: 0, mck2ui 16
8859 00:38:56.615373 best dqsien dly found for B0: ( 1, 9, 8)
8860 00:38:56.619280 Total UI for P1: 0, mck2ui 16
8861 00:38:56.622350 best dqsien dly found for B1: ( 1, 9, 12)
8862 00:38:56.625942 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8863 00:38:56.630044 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8864 00:38:56.630119
8865 00:38:56.633194 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8866 00:38:56.635971 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8867 00:38:56.638795 [Gating] SW calibration Done
8868 00:38:56.638908 ==
8869 00:38:56.642386 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 00:38:56.645782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 00:38:56.648661 ==
8872 00:38:56.648762 RX Vref Scan: 0
8873 00:38:56.648854
8874 00:38:56.652474 RX Vref 0 -> 0, step: 1
8875 00:38:56.652567
8876 00:38:56.652659 RX Delay 0 -> 252, step: 8
8877 00:38:56.658655 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8878 00:38:56.662208 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8879 00:38:56.665683 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8880 00:38:56.668676 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8881 00:38:56.672336 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8882 00:38:56.678827 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8883 00:38:56.682270 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8884 00:38:56.685297 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8885 00:38:56.688642 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8886 00:38:56.692288 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8887 00:38:56.698744 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8888 00:38:56.702192 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8889 00:38:56.705676 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8890 00:38:56.708703 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8891 00:38:56.712155 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8892 00:38:56.718665 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8893 00:38:56.718774 ==
8894 00:38:56.722083 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 00:38:56.725696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 00:38:56.725773 ==
8897 00:38:56.725835 DQS Delay:
8898 00:38:56.728687 DQS0 = 0, DQS1 = 0
8899 00:38:56.728787 DQM Delay:
8900 00:38:56.732028 DQM0 = 132, DQM1 = 127
8901 00:38:56.732107 DQ Delay:
8902 00:38:56.735400 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8903 00:38:56.738794 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8904 00:38:56.742405 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8905 00:38:56.745780 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8906 00:38:56.745863
8907 00:38:56.748888
8908 00:38:56.748994 ==
8909 00:38:56.752364 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 00:38:56.756727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 00:38:56.756810 ==
8912 00:38:56.756876
8913 00:38:56.756936
8914 00:38:56.758717 TX Vref Scan disable
8915 00:38:56.758800 == TX Byte 0 ==
8916 00:38:56.762314 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8917 00:38:56.768845 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 00:38:56.768927 == TX Byte 1 ==
8919 00:38:56.771945 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8920 00:38:56.778804 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8921 00:38:56.778887 ==
8922 00:38:56.782174 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 00:38:56.785499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 00:38:56.785582 ==
8925 00:38:56.799685
8926 00:38:56.802903 TX Vref early break, caculate TX vref
8927 00:38:56.806674 TX Vref=16, minBit 11, minWin=22, winSum=381
8928 00:38:56.809748 TX Vref=18, minBit 6, minWin=23, winSum=388
8929 00:38:56.813112 TX Vref=20, minBit 8, minWin=23, winSum=397
8930 00:38:56.816550 TX Vref=22, minBit 8, minWin=24, winSum=407
8931 00:38:56.819724 TX Vref=24, minBit 15, minWin=24, winSum=415
8932 00:38:56.826074 TX Vref=26, minBit 0, minWin=25, winSum=420
8933 00:38:56.829649 TX Vref=28, minBit 5, minWin=25, winSum=424
8934 00:38:56.832910 TX Vref=30, minBit 5, minWin=25, winSum=423
8935 00:38:56.836333 TX Vref=32, minBit 0, minWin=24, winSum=411
8936 00:38:56.839597 TX Vref=34, minBit 0, minWin=25, winSum=407
8937 00:38:56.842800 TX Vref=36, minBit 0, minWin=24, winSum=399
8938 00:38:56.849864 [TxChooseVref] Worse bit 5, Min win 25, Win sum 424, Final Vref 28
8939 00:38:56.849948
8940 00:38:56.852942 Final TX Range 0 Vref 28
8941 00:38:56.853064
8942 00:38:56.853168 ==
8943 00:38:56.856854 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 00:38:56.860276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 00:38:56.860360 ==
8946 00:38:56.860425
8947 00:38:56.860485
8948 00:38:56.863371 TX Vref Scan disable
8949 00:38:56.869867 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8950 00:38:56.869949 == TX Byte 0 ==
8951 00:38:56.872981 u2DelayCellOfst[0]=14 cells (4 PI)
8952 00:38:56.876385 u2DelayCellOfst[1]=14 cells (4 PI)
8953 00:38:56.879748 u2DelayCellOfst[2]=0 cells (0 PI)
8954 00:38:56.883058 u2DelayCellOfst[3]=7 cells (2 PI)
8955 00:38:56.886104 u2DelayCellOfst[4]=7 cells (2 PI)
8956 00:38:56.889867 u2DelayCellOfst[5]=17 cells (5 PI)
8957 00:38:56.893103 u2DelayCellOfst[6]=17 cells (5 PI)
8958 00:38:56.896286 u2DelayCellOfst[7]=7 cells (2 PI)
8959 00:38:56.899790 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8960 00:38:56.903454 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8961 00:38:56.906438 == TX Byte 1 ==
8962 00:38:56.906520 u2DelayCellOfst[8]=0 cells (0 PI)
8963 00:38:56.909956 u2DelayCellOfst[9]=3 cells (1 PI)
8964 00:38:56.913000 u2DelayCellOfst[10]=10 cells (3 PI)
8965 00:38:56.916803 u2DelayCellOfst[11]=7 cells (2 PI)
8966 00:38:56.919544 u2DelayCellOfst[12]=14 cells (4 PI)
8967 00:38:56.923332 u2DelayCellOfst[13]=14 cells (4 PI)
8968 00:38:56.926606 u2DelayCellOfst[14]=17 cells (5 PI)
8969 00:38:56.929584 u2DelayCellOfst[15]=17 cells (5 PI)
8970 00:38:56.933675 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8971 00:38:56.939796 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8972 00:38:56.939900 DramC Write-DBI on
8973 00:38:56.940002 ==
8974 00:38:56.942754 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 00:38:56.946698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 00:38:56.946780 ==
8977 00:38:56.949555
8978 00:38:56.949636
8979 00:38:56.949730 TX Vref Scan disable
8980 00:38:56.952787 == TX Byte 0 ==
8981 00:38:56.956374 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8982 00:38:56.959707 == TX Byte 1 ==
8983 00:38:56.962984 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8984 00:38:56.963084 DramC Write-DBI off
8985 00:38:56.963174
8986 00:38:56.966828 [DATLAT]
8987 00:38:56.966922 Freq=1600, CH1 RK1
8988 00:38:56.967015
8989 00:38:56.970156 DATLAT Default: 0xf
8990 00:38:56.970224 0, 0xFFFF, sum = 0
8991 00:38:56.973059 1, 0xFFFF, sum = 0
8992 00:38:56.973134 2, 0xFFFF, sum = 0
8993 00:38:56.976890 3, 0xFFFF, sum = 0
8994 00:38:56.977006 4, 0xFFFF, sum = 0
8995 00:38:56.980121 5, 0xFFFF, sum = 0
8996 00:38:56.980215 6, 0xFFFF, sum = 0
8997 00:38:56.983397 7, 0xFFFF, sum = 0
8998 00:38:56.983476 8, 0xFFFF, sum = 0
8999 00:38:56.986472 9, 0xFFFF, sum = 0
9000 00:38:56.989934 10, 0xFFFF, sum = 0
9001 00:38:56.990006 11, 0xFFFF, sum = 0
9002 00:38:56.993365 12, 0xFFFF, sum = 0
9003 00:38:56.993434 13, 0xFFFF, sum = 0
9004 00:38:56.996607 14, 0x0, sum = 1
9005 00:38:56.996709 15, 0x0, sum = 2
9006 00:38:57.000445 16, 0x0, sum = 3
9007 00:38:57.000541 17, 0x0, sum = 4
9008 00:38:57.000633 best_step = 15
9009 00:38:57.000722
9010 00:38:57.003576 ==
9011 00:38:57.006756 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 00:38:57.009815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 00:38:57.009886 ==
9014 00:38:57.009947 RX Vref Scan: 0
9015 00:38:57.010004
9016 00:38:57.013322 RX Vref 0 -> 0, step: 1
9017 00:38:57.013392
9018 00:38:57.016357 RX Delay 11 -> 252, step: 4
9019 00:38:57.019908 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9020 00:38:57.023206 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9021 00:38:57.030173 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9022 00:38:57.033246 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9023 00:38:57.036526 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9024 00:38:57.039738 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9025 00:38:57.043168 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9026 00:38:57.049890 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9027 00:38:57.052857 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9028 00:38:57.056387 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9029 00:38:57.059790 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
9030 00:38:57.063399 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9031 00:38:57.069985 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9032 00:38:57.073192 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9033 00:38:57.076343 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9034 00:38:57.079880 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9035 00:38:57.079979 ==
9036 00:38:57.083309 Dram Type= 6, Freq= 0, CH_1, rank 1
9037 00:38:57.090225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9038 00:38:57.090310 ==
9039 00:38:57.090375 DQS Delay:
9040 00:38:57.093452 DQS0 = 0, DQS1 = 0
9041 00:38:57.093540 DQM Delay:
9042 00:38:57.093604 DQM0 = 129, DQM1 = 126
9043 00:38:57.097631 DQ Delay:
9044 00:38:57.100224 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9045 00:38:57.102949 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =124
9046 00:38:57.106383 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
9047 00:38:57.110158 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =136
9048 00:38:57.110262
9049 00:38:57.110353
9050 00:38:57.110440
9051 00:38:57.113265 [DramC_TX_OE_Calibration] TA2
9052 00:38:57.116705 Original DQ_B0 (3 6) =30, OEN = 27
9053 00:38:57.119915 Original DQ_B1 (3 6) =30, OEN = 27
9054 00:38:57.123387 24, 0x0, End_B0=24 End_B1=24
9055 00:38:57.123490 25, 0x0, End_B0=25 End_B1=25
9056 00:38:57.126752 26, 0x0, End_B0=26 End_B1=26
9057 00:38:57.130239 27, 0x0, End_B0=27 End_B1=27
9058 00:38:57.132985 28, 0x0, End_B0=28 End_B1=28
9059 00:38:57.133063 29, 0x0, End_B0=29 End_B1=29
9060 00:38:57.136251 30, 0x0, End_B0=30 End_B1=30
9061 00:38:57.140265 31, 0x4545, End_B0=30 End_B1=30
9062 00:38:57.143117 Byte0 end_step=30 best_step=27
9063 00:38:57.147113 Byte1 end_step=30 best_step=27
9064 00:38:57.149697 Byte0 TX OE(2T, 0.5T) = (3, 3)
9065 00:38:57.149775 Byte1 TX OE(2T, 0.5T) = (3, 3)
9066 00:38:57.153140
9067 00:38:57.153212
9068 00:38:57.159611 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9069 00:38:57.163426 CH1 RK1: MR19=303, MR18=1016
9070 00:38:57.170145 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9071 00:38:57.173204 [RxdqsGatingPostProcess] freq 1600
9072 00:38:57.176564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9073 00:38:57.179943 best DQS0 dly(2T, 0.5T) = (1, 1)
9074 00:38:57.183153 best DQS1 dly(2T, 0.5T) = (1, 1)
9075 00:38:57.186574 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9076 00:38:57.189690 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9077 00:38:57.193519 best DQS0 dly(2T, 0.5T) = (1, 1)
9078 00:38:57.196673 best DQS1 dly(2T, 0.5T) = (1, 1)
9079 00:38:57.199966 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9080 00:38:57.203500 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9081 00:38:57.203599 Pre-setting of DQS Precalculation
9082 00:38:57.210090 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9083 00:38:57.217125 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9084 00:38:57.223302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9085 00:38:57.223380
9086 00:38:57.223450
9087 00:38:57.226740 [Calibration Summary] 3200 Mbps
9088 00:38:57.230199 CH 0, Rank 0
9089 00:38:57.230309 SW Impedance : PASS
9090 00:38:57.233518 DUTY Scan : NO K
9091 00:38:57.236742 ZQ Calibration : PASS
9092 00:38:57.236844 Jitter Meter : NO K
9093 00:38:57.239949 CBT Training : PASS
9094 00:38:57.240047 Write leveling : PASS
9095 00:38:57.243359 RX DQS gating : PASS
9096 00:38:57.246564 RX DQ/DQS(RDDQC) : PASS
9097 00:38:57.246664 TX DQ/DQS : PASS
9098 00:38:57.250711 RX DATLAT : PASS
9099 00:38:57.253557 RX DQ/DQS(Engine): PASS
9100 00:38:57.253653 TX OE : PASS
9101 00:38:57.257294 All Pass.
9102 00:38:57.257393
9103 00:38:57.257482 CH 0, Rank 1
9104 00:38:57.260128 SW Impedance : PASS
9105 00:38:57.260214 DUTY Scan : NO K
9106 00:38:57.263522 ZQ Calibration : PASS
9107 00:38:57.266675 Jitter Meter : NO K
9108 00:38:57.266781 CBT Training : PASS
9109 00:38:57.270612 Write leveling : PASS
9110 00:38:57.270718 RX DQS gating : PASS
9111 00:38:57.273431 RX DQ/DQS(RDDQC) : PASS
9112 00:38:57.276884 TX DQ/DQS : PASS
9113 00:38:57.276967 RX DATLAT : PASS
9114 00:38:57.280499 RX DQ/DQS(Engine): PASS
9115 00:38:57.283470 TX OE : PASS
9116 00:38:57.283552 All Pass.
9117 00:38:57.283617
9118 00:38:57.283677 CH 1, Rank 0
9119 00:38:57.286840 SW Impedance : PASS
9120 00:38:57.290045 DUTY Scan : NO K
9121 00:38:57.290127 ZQ Calibration : PASS
9122 00:38:57.293345 Jitter Meter : NO K
9123 00:38:57.297073 CBT Training : PASS
9124 00:38:57.297183 Write leveling : PASS
9125 00:38:57.300457 RX DQS gating : PASS
9126 00:38:57.303363 RX DQ/DQS(RDDQC) : PASS
9127 00:38:57.303446 TX DQ/DQS : PASS
9128 00:38:57.306804 RX DATLAT : PASS
9129 00:38:57.310827 RX DQ/DQS(Engine): PASS
9130 00:38:57.310908 TX OE : PASS
9131 00:38:57.310974 All Pass.
9132 00:38:57.311035
9133 00:38:57.313761 CH 1, Rank 1
9134 00:38:57.313842 SW Impedance : PASS
9135 00:38:57.316665 DUTY Scan : NO K
9136 00:38:57.319995 ZQ Calibration : PASS
9137 00:38:57.320097 Jitter Meter : NO K
9138 00:38:57.323795 CBT Training : PASS
9139 00:38:57.326712 Write leveling : PASS
9140 00:38:57.326815 RX DQS gating : PASS
9141 00:38:57.330849 RX DQ/DQS(RDDQC) : PASS
9142 00:38:57.333582 TX DQ/DQS : PASS
9143 00:38:57.333693 RX DATLAT : PASS
9144 00:38:57.336617 RX DQ/DQS(Engine): PASS
9145 00:38:57.340084 TX OE : PASS
9146 00:38:57.340201 All Pass.
9147 00:38:57.340302
9148 00:38:57.340390 DramC Write-DBI on
9149 00:38:57.343328 PER_BANK_REFRESH: Hybrid Mode
9150 00:38:57.346573 TX_TRACKING: ON
9151 00:38:57.353528 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9152 00:38:57.363694 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9153 00:38:57.370054 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9154 00:38:57.373423 [FAST_K] Save calibration result to emmc
9155 00:38:57.377066 sync common calibartion params.
9156 00:38:57.380332 sync cbt_mode0:1, 1:1
9157 00:38:57.380438 dram_init: ddr_geometry: 2
9158 00:38:57.383731 dram_init: ddr_geometry: 2
9159 00:38:57.386757 dram_init: ddr_geometry: 2
9160 00:38:57.386852 0:dram_rank_size:100000000
9161 00:38:57.390233 1:dram_rank_size:100000000
9162 00:38:57.397197 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9163 00:38:57.397315 DFS_SHUFFLE_HW_MODE: ON
9164 00:38:57.403910 dramc_set_vcore_voltage set vcore to 725000
9165 00:38:57.404012 Read voltage for 1600, 0
9166 00:38:57.407065 Vio18 = 0
9167 00:38:57.407174 Vcore = 725000
9168 00:38:57.407266 Vdram = 0
9169 00:38:57.410714 Vddq = 0
9170 00:38:57.410788 Vmddr = 0
9171 00:38:57.413751 switch to 3200 Mbps bootup
9172 00:38:57.413826 [DramcRunTimeConfig]
9173 00:38:57.413911 PHYPLL
9174 00:38:57.417110 DPM_CONTROL_AFTERK: ON
9175 00:38:57.417208 PER_BANK_REFRESH: ON
9176 00:38:57.420583 REFRESH_OVERHEAD_REDUCTION: ON
9177 00:38:57.423561 CMD_PICG_NEW_MODE: OFF
9178 00:38:57.423638 XRTWTW_NEW_MODE: ON
9179 00:38:57.427217 XRTRTR_NEW_MODE: ON
9180 00:38:57.427316 TX_TRACKING: ON
9181 00:38:57.430322 RDSEL_TRACKING: OFF
9182 00:38:57.433348 DQS Precalculation for DVFS: ON
9183 00:38:57.433439 RX_TRACKING: OFF
9184 00:38:57.437072 HW_GATING DBG: ON
9185 00:38:57.437147 ZQCS_ENABLE_LP4: ON
9186 00:38:57.440458 RX_PICG_NEW_MODE: ON
9187 00:38:57.440567 TX_PICG_NEW_MODE: ON
9188 00:38:57.443864 ENABLE_RX_DCM_DPHY: ON
9189 00:38:57.447208 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9190 00:38:57.450319 DUMMY_READ_FOR_TRACKING: OFF
9191 00:38:57.453448 !!! SPM_CONTROL_AFTERK: OFF
9192 00:38:57.453529 !!! SPM could not control APHY
9193 00:38:57.456757 IMPEDANCE_TRACKING: ON
9194 00:38:57.456857 TEMP_SENSOR: ON
9195 00:38:57.460217 HW_SAVE_FOR_SR: OFF
9196 00:38:57.464465 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9197 00:38:57.467195 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9198 00:38:57.470728 Read ODT Tracking: ON
9199 00:38:57.470823 Refresh Rate DeBounce: ON
9200 00:38:57.473652 DFS_NO_QUEUE_FLUSH: ON
9201 00:38:57.477250 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9202 00:38:57.480726 ENABLE_DFS_RUNTIME_MRW: OFF
9203 00:38:57.480834 DDR_RESERVE_NEW_MODE: ON
9204 00:38:57.483753 MR_CBT_SWITCH_FREQ: ON
9205 00:38:57.487052 =========================
9206 00:38:57.504453 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9207 00:38:57.508542 dram_init: ddr_geometry: 2
9208 00:38:57.526174 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9209 00:38:57.529260 dram_init: dram init end (result: 0)
9210 00:38:57.535939 DRAM-K: Full calibration passed in 24594 msecs
9211 00:38:57.539465 MRC: failed to locate region type 0.
9212 00:38:57.539572 DRAM rank0 size:0x100000000,
9213 00:38:57.543006 DRAM rank1 size=0x100000000
9214 00:38:57.552765 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9215 00:38:57.559743 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9216 00:38:57.566531 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9217 00:38:57.572958 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9218 00:38:57.576218 DRAM rank0 size:0x100000000,
9219 00:38:57.579408 DRAM rank1 size=0x100000000
9220 00:38:57.579484 CBMEM:
9221 00:38:57.582489 IMD: root @ 0xfffff000 254 entries.
9222 00:38:57.586103 IMD: root @ 0xffffec00 62 entries.
9223 00:38:57.589252 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9224 00:38:57.592842 WARNING: RO_VPD is uninitialized or empty.
9225 00:38:57.599048 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9226 00:38:57.606129 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9227 00:38:57.619059 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9228 00:38:57.630112 BS: romstage times (exec / console): total (unknown) / 24098 ms
9229 00:38:57.630218
9230 00:38:57.630312
9231 00:38:57.640328 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9232 00:38:57.643655 ARM64: Exception handlers installed.
9233 00:38:57.646783 ARM64: Testing exception
9234 00:38:57.650162 ARM64: Done test exception
9235 00:38:57.650251 Enumerating buses...
9236 00:38:57.653887 Show all devs... Before device enumeration.
9237 00:38:57.657187 Root Device: enabled 1
9238 00:38:57.660255 CPU_CLUSTER: 0: enabled 1
9239 00:38:57.660354 CPU: 00: enabled 1
9240 00:38:57.663931 Compare with tree...
9241 00:38:57.664030 Root Device: enabled 1
9242 00:38:57.666724 CPU_CLUSTER: 0: enabled 1
9243 00:38:57.670438 CPU: 00: enabled 1
9244 00:38:57.670538 Root Device scanning...
9245 00:38:57.673553 scan_static_bus for Root Device
9246 00:38:57.676783 CPU_CLUSTER: 0 enabled
9247 00:38:57.680357 scan_static_bus for Root Device done
9248 00:38:57.683838 scan_bus: bus Root Device finished in 8 msecs
9249 00:38:57.683938 done
9250 00:38:57.690154 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9251 00:38:57.693714 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9252 00:38:57.700376 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9253 00:38:57.703931 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9254 00:38:57.706783 Allocating resources...
9255 00:38:57.706860 Reading resources...
9256 00:38:57.713950 Root Device read_resources bus 0 link: 0
9257 00:38:57.714051 DRAM rank0 size:0x100000000,
9258 00:38:57.716721 DRAM rank1 size=0x100000000
9259 00:38:57.720783 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9260 00:38:57.723607 CPU: 00 missing read_resources
9261 00:38:57.727248 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9262 00:38:57.733856 Root Device read_resources bus 0 link: 0 done
9263 00:38:57.733969 Done reading resources.
9264 00:38:57.739882 Show resources in subtree (Root Device)...After reading.
9265 00:38:57.743664 Root Device child on link 0 CPU_CLUSTER: 0
9266 00:38:57.747330 CPU_CLUSTER: 0 child on link 0 CPU: 00
9267 00:38:57.756946 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9268 00:38:57.757053 CPU: 00
9269 00:38:57.759980 Root Device assign_resources, bus 0 link: 0
9270 00:38:57.763574 CPU_CLUSTER: 0 missing set_resources
9271 00:38:57.766862 Root Device assign_resources, bus 0 link: 0 done
9272 00:38:57.769885 Done setting resources.
9273 00:38:57.777161 Show resources in subtree (Root Device)...After assigning values.
9274 00:38:57.780478 Root Device child on link 0 CPU_CLUSTER: 0
9275 00:38:57.783393 CPU_CLUSTER: 0 child on link 0 CPU: 00
9276 00:38:57.793220 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9277 00:38:57.793310 CPU: 00
9278 00:38:57.796834 Done allocating resources.
9279 00:38:57.800440 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9280 00:38:57.803433 Enabling resources...
9281 00:38:57.803535 done.
9282 00:38:57.806784 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9283 00:38:57.809775 Initializing devices...
9284 00:38:57.814001 Root Device init
9285 00:38:57.814081 init hardware done!
9286 00:38:57.816571 0x00000018: ctrlr->caps
9287 00:38:57.816680 52.000 MHz: ctrlr->f_max
9288 00:38:57.820069 0.400 MHz: ctrlr->f_min
9289 00:38:57.823147 0x40ff8080: ctrlr->voltages
9290 00:38:57.823259 sclk: 390625
9291 00:38:57.826480 Bus Width = 1
9292 00:38:57.826583 sclk: 390625
9293 00:38:57.826687 Bus Width = 1
9294 00:38:57.829951 Early init status = 3
9295 00:38:57.833535 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9296 00:38:57.838108 in-header: 03 fc 00 00 01 00 00 00
9297 00:38:57.841244 in-data: 00
9298 00:38:57.844180 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9299 00:38:57.848803 in-header: 03 fd 00 00 00 00 00 00
9300 00:38:57.852222 in-data:
9301 00:38:57.855999 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9302 00:38:57.859252 in-header: 03 fc 00 00 01 00 00 00
9303 00:38:57.862367 in-data: 00
9304 00:38:57.865589 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9305 00:38:57.870202 in-header: 03 fd 00 00 00 00 00 00
9306 00:38:57.873802 in-data:
9307 00:38:57.877170 [SSUSB] Setting up USB HOST controller...
9308 00:38:57.880432 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9309 00:38:57.884034 [SSUSB] phy power-on done.
9310 00:38:57.887166 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9311 00:38:57.893739 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9312 00:38:57.897414 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9313 00:38:57.903962 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9314 00:38:57.910701 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9315 00:38:57.916821 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9316 00:38:57.923681 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9317 00:38:57.930168 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9318 00:38:57.930277 SPM: binary array size = 0x9dc
9319 00:38:57.936844 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9320 00:38:57.943636 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9321 00:38:57.950385 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9322 00:38:57.953594 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9323 00:38:57.957386 configure_display: Starting display init
9324 00:38:57.993977 anx7625_power_on_init: Init interface.
9325 00:38:57.996992 anx7625_disable_pd_protocol: Disabled PD feature.
9326 00:38:58.000222 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9327 00:38:58.028109 anx7625_start_dp_work: Secure OCM version=00
9328 00:38:58.031273 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9329 00:38:58.046442 sp_tx_get_edid_block: EDID Block = 1
9330 00:38:58.148513 Extracted contents:
9331 00:38:58.151909 header: 00 ff ff ff ff ff ff 00
9332 00:38:58.155841 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9333 00:38:58.159048 version: 01 04
9334 00:38:58.161794 basic params: 95 1f 11 78 0a
9335 00:38:58.165451 chroma info: 76 90 94 55 54 90 27 21 50 54
9336 00:38:58.168826 established: 00 00 00
9337 00:38:58.175122 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9338 00:38:58.178600 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9339 00:38:58.186271 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9340 00:38:58.192343 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9341 00:38:58.198957 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9342 00:38:58.202209 extensions: 00
9343 00:38:58.202291 checksum: fb
9344 00:38:58.202355
9345 00:38:58.205814 Manufacturer: IVO Model 57d Serial Number 0
9346 00:38:58.208984 Made week 0 of 2020
9347 00:38:58.209095 EDID version: 1.4
9348 00:38:58.212087 Digital display
9349 00:38:58.215642 6 bits per primary color channel
9350 00:38:58.215725 DisplayPort interface
9351 00:38:58.219053 Maximum image size: 31 cm x 17 cm
9352 00:38:58.219133 Gamma: 220%
9353 00:38:58.222031 Check DPMS levels
9354 00:38:58.225359 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9355 00:38:58.228970 First detailed timing is preferred timing
9356 00:38:58.232621 Established timings supported:
9357 00:38:58.235566 Standard timings supported:
9358 00:38:58.235669 Detailed timings
9359 00:38:58.242122 Hex of detail: 383680a07038204018303c0035ae10000019
9360 00:38:58.245713 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9361 00:38:58.249120 0780 0798 07c8 0820 hborder 0
9362 00:38:58.255630 0438 043b 0447 0458 vborder 0
9363 00:38:58.255709 -hsync -vsync
9364 00:38:58.259011 Did detailed timing
9365 00:38:58.262223 Hex of detail: 000000000000000000000000000000000000
9366 00:38:58.265617 Manufacturer-specified data, tag 0
9367 00:38:58.272134 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9368 00:38:58.272238 ASCII string: InfoVision
9369 00:38:58.278618 Hex of detail: 000000fe00523134304e574635205248200a
9370 00:38:58.278711 ASCII string: R140NWF5 RH
9371 00:38:58.282265 Checksum
9372 00:38:58.282352 Checksum: 0xfb (valid)
9373 00:38:58.288754 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9374 00:38:58.288858 DSI data_rate: 832800000 bps
9375 00:38:58.296302 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9376 00:38:58.300083 anx7625_parse_edid: pixelclock(138800).
9377 00:38:58.302891 hactive(1920), hsync(48), hfp(24), hbp(88)
9378 00:38:58.306576 vactive(1080), vsync(12), vfp(3), vbp(17)
9379 00:38:58.309614 anx7625_dsi_config: config dsi.
9380 00:38:58.316525 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9381 00:38:58.330711 anx7625_dsi_config: success to config DSI
9382 00:38:58.333894 anx7625_dp_start: MIPI phy setup OK.
9383 00:38:58.337623 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9384 00:38:58.340786 mtk_ddp_mode_set invalid vrefresh 60
9385 00:38:58.344565 main_disp_path_setup
9386 00:38:58.344647 ovl_layer_smi_id_en
9387 00:38:58.347651 ovl_layer_smi_id_en
9388 00:38:58.347733 ccorr_config
9389 00:38:58.347798 aal_config
9390 00:38:58.351379 gamma_config
9391 00:38:58.351460 postmask_config
9392 00:38:58.351524 dither_config
9393 00:38:58.357924 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9394 00:38:58.364125 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9395 00:38:58.367919 Root Device init finished in 551 msecs
9396 00:38:58.368001 CPU_CLUSTER: 0 init
9397 00:38:58.377619 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9398 00:38:58.380957 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9399 00:38:58.384209 APU_MBOX 0x190000b0 = 0x10001
9400 00:38:58.388150 APU_MBOX 0x190001b0 = 0x10001
9401 00:38:58.391229 APU_MBOX 0x190005b0 = 0x10001
9402 00:38:58.394417 APU_MBOX 0x190006b0 = 0x10001
9403 00:38:58.397778 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9404 00:38:58.409502 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9405 00:38:58.422187 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9406 00:38:58.428917 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9407 00:38:58.440356 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9408 00:38:58.449904 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9409 00:38:58.452958 CPU_CLUSTER: 0 init finished in 81 msecs
9410 00:38:58.456068 Devices initialized
9411 00:38:58.459925 Show all devs... After init.
9412 00:38:58.460007 Root Device: enabled 1
9413 00:38:58.462816 CPU_CLUSTER: 0: enabled 1
9414 00:38:58.466109 CPU: 00: enabled 1
9415 00:38:58.469756 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9416 00:38:58.472883 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9417 00:38:58.476244 ELOG: NV offset 0x57f000 size 0x1000
9418 00:38:58.482586 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9419 00:38:58.489911 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9420 00:38:58.492864 ELOG: Event(17) added with size 13 at 2024-06-05 00:38:58 UTC
9421 00:38:58.496050 out: cmd=0x121: 03 db 21 01 00 00 00 00
9422 00:38:58.500926 in-header: 03 cb 00 00 2c 00 00 00
9423 00:38:58.514339 in-data: 94 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9424 00:38:58.520983 ELOG: Event(A1) added with size 10 at 2024-06-05 00:38:58 UTC
9425 00:38:58.527469 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9426 00:38:58.534245 ELOG: Event(A0) added with size 9 at 2024-06-05 00:38:58 UTC
9427 00:38:58.537663 elog_add_boot_reason: Logged dev mode boot
9428 00:38:58.541404 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9429 00:38:58.544080 Finalize devices...
9430 00:38:58.544162 Devices finalized
9431 00:38:58.550679 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9432 00:38:58.553836 Writing coreboot table at 0xffe64000
9433 00:38:58.557986 0. 000000000010a000-0000000000113fff: RAMSTAGE
9434 00:38:58.560648 1. 0000000040000000-00000000400fffff: RAM
9435 00:38:58.564327 2. 0000000040100000-000000004032afff: RAMSTAGE
9436 00:38:58.570856 3. 000000004032b000-00000000545fffff: RAM
9437 00:38:58.573978 4. 0000000054600000-000000005465ffff: BL31
9438 00:38:58.577498 5. 0000000054660000-00000000ffe63fff: RAM
9439 00:38:58.580834 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9440 00:38:58.587682 7. 0000000100000000-000000023fffffff: RAM
9441 00:38:58.587767 Passing 5 GPIOs to payload:
9442 00:38:58.594144 NAME | PORT | POLARITY | VALUE
9443 00:38:58.597371 EC in RW | 0x000000aa | low | undefined
9444 00:38:58.600907 EC interrupt | 0x00000005 | low | undefined
9445 00:38:58.607675 TPM interrupt | 0x000000ab | high | undefined
9446 00:38:58.611502 SD card detect | 0x00000011 | high | undefined
9447 00:38:58.617544 speaker enable | 0x00000093 | high | undefined
9448 00:38:58.621509 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9449 00:38:58.624673 in-header: 03 f9 00 00 02 00 00 00
9450 00:38:58.624754 in-data: 02 00
9451 00:38:58.627749 ADC[4]: Raw value=899114 ID=7
9452 00:38:58.631026 ADC[3]: Raw value=213336 ID=1
9453 00:38:58.631112 RAM Code: 0x71
9454 00:38:58.634216 ADC[6]: Raw value=74557 ID=0
9455 00:38:58.637461 ADC[5]: Raw value=212229 ID=1
9456 00:38:58.637543 SKU Code: 0x1
9457 00:38:58.644515 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6bbf
9458 00:38:58.647619 coreboot table: 964 bytes.
9459 00:38:58.650680 IMD ROOT 0. 0xfffff000 0x00001000
9460 00:38:58.654316 IMD SMALL 1. 0xffffe000 0x00001000
9461 00:38:58.657356 RO MCACHE 2. 0xffffc000 0x00001104
9462 00:38:58.660859 CONSOLE 3. 0xfff7c000 0x00080000
9463 00:38:58.664390 FMAP 4. 0xfff7b000 0x00000452
9464 00:38:58.667743 TIME STAMP 5. 0xfff7a000 0x00000910
9465 00:38:58.667843 VBOOT WORK 6. 0xfff66000 0x00014000
9466 00:38:58.671489 RAMOOPS 7. 0xffe66000 0x00100000
9467 00:38:58.674237 COREBOOT 8. 0xffe64000 0x00002000
9468 00:38:58.677632 IMD small region:
9469 00:38:58.681432 IMD ROOT 0. 0xffffec00 0x00000400
9470 00:38:58.684323 VPD 1. 0xffffeb80 0x0000006c
9471 00:38:58.687939 MMC STATUS 2. 0xffffeb60 0x00000004
9472 00:38:58.694070 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9473 00:38:58.694152 Probing TPM: done!
9474 00:38:58.701213 Connected to device vid:did:rid of 1ae0:0028:00
9475 00:38:58.707651 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9476 00:38:58.711552 Initialized TPM device CR50 revision 0
9477 00:38:58.714701 Checking cr50 for pending updates
9478 00:38:58.720309 Reading cr50 TPM mode
9479 00:38:58.728612 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9480 00:38:58.735352 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9481 00:38:58.775732 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9482 00:38:58.778703 Checking segment from ROM address 0x40100000
9483 00:38:58.782339 Checking segment from ROM address 0x4010001c
9484 00:38:58.789259 Loading segment from ROM address 0x40100000
9485 00:38:58.789342 code (compression=0)
9486 00:38:58.795447 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9487 00:38:58.805466 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9488 00:38:58.805550 it's not compressed!
9489 00:38:58.812511 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9490 00:38:58.815657 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9491 00:38:58.835743 Loading segment from ROM address 0x4010001c
9492 00:38:58.835828 Entry Point 0x80000000
9493 00:38:58.839469 Loaded segments
9494 00:38:58.842712 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9495 00:38:58.849236 Jumping to boot code at 0x80000000(0xffe64000)
9496 00:38:58.855857 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9497 00:38:58.862819 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9498 00:38:58.870642 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9499 00:38:58.874130 Checking segment from ROM address 0x40100000
9500 00:38:58.877116 Checking segment from ROM address 0x4010001c
9501 00:38:58.883987 Loading segment from ROM address 0x40100000
9502 00:38:58.884070 code (compression=1)
9503 00:38:58.890466 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9504 00:38:58.900397 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9505 00:38:58.900480 using LZMA
9506 00:38:58.908725 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9507 00:38:58.915213 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9508 00:38:58.918719 Loading segment from ROM address 0x4010001c
9509 00:38:58.918801 Entry Point 0x54601000
9510 00:38:58.922394 Loaded segments
9511 00:38:58.925750 NOTICE: MT8192 bl31_setup
9512 00:38:58.932061 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9513 00:38:58.935885 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9514 00:38:58.938881 WARNING: region 0:
9515 00:38:58.942337 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 00:38:58.942418 WARNING: region 1:
9517 00:38:58.949336 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9518 00:38:58.952600 WARNING: region 2:
9519 00:38:58.956065 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9520 00:38:58.959047 WARNING: region 3:
9521 00:38:58.962866 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9522 00:38:58.965817 WARNING: region 4:
9523 00:38:58.969208 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 00:38:58.972412 WARNING: region 5:
9525 00:38:58.976165 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 00:38:58.979335 WARNING: region 6:
9527 00:38:58.983054 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 00:38:58.983135 WARNING: region 7:
9529 00:38:58.989670 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 00:38:58.996354 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9531 00:38:58.999352 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9532 00:38:59.002850 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9533 00:38:59.009185 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9534 00:38:59.012755 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9535 00:38:59.015983 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9536 00:38:59.022774 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9537 00:38:59.026140 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9538 00:38:59.029604 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9539 00:38:59.036409 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9540 00:38:59.039926 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9541 00:38:59.043158 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9542 00:38:59.050045 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9543 00:38:59.053685 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9544 00:38:59.056606 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9545 00:38:59.063100 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9546 00:38:59.066701 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9547 00:38:59.073499 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9548 00:38:59.076546 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9549 00:38:59.080022 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9550 00:38:59.087303 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9551 00:38:59.090307 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9552 00:38:59.093609 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9553 00:38:59.100243 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9554 00:38:59.103534 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9555 00:38:59.110059 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9556 00:38:59.113582 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9557 00:38:59.117037 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9558 00:38:59.123911 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9559 00:38:59.126968 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9560 00:38:59.133758 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9561 00:38:59.137269 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9562 00:38:59.140410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9563 00:38:59.144004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9564 00:38:59.150625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9565 00:38:59.153804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9566 00:38:59.157272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9567 00:38:59.160307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9568 00:38:59.163944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9569 00:38:59.170832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9570 00:38:59.174169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9571 00:38:59.177849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9572 00:38:59.181217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9573 00:38:59.187472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9574 00:38:59.191258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9575 00:38:59.194206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9576 00:38:59.197641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9577 00:38:59.204953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9578 00:38:59.207833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9579 00:38:59.212023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9580 00:38:59.218107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9581 00:38:59.221362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9582 00:38:59.228362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9583 00:38:59.231457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9584 00:38:59.238129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9585 00:38:59.241504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9586 00:38:59.244727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9587 00:38:59.251649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9588 00:38:59.255156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9589 00:38:59.261347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9590 00:38:59.264736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9591 00:38:59.271848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9592 00:38:59.275308 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9593 00:38:59.278903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9594 00:38:59.285264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9595 00:38:59.288522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9596 00:38:59.295212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9597 00:38:59.298279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9598 00:38:59.301766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9599 00:38:59.308765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9600 00:38:59.311686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9601 00:38:59.318580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9602 00:38:59.322033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9603 00:38:59.328630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9604 00:38:59.332061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9605 00:38:59.335532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9606 00:38:59.342401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9607 00:38:59.345313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9608 00:38:59.351933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9609 00:38:59.355703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9610 00:38:59.362172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9611 00:38:59.365381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9612 00:38:59.369333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9613 00:38:59.375898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9614 00:38:59.379047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9615 00:38:59.385644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9616 00:38:59.388913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9617 00:38:59.392824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9618 00:38:59.399126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9619 00:38:59.402270 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9620 00:38:59.409299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9621 00:38:59.412596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9622 00:38:59.419208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9623 00:38:59.423484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9624 00:38:59.429064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9625 00:38:59.432601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9626 00:38:59.436091 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9627 00:38:59.439048 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9628 00:38:59.445925 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9629 00:38:59.449364 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9630 00:38:59.452704 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9631 00:38:59.459148 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9632 00:38:59.462840 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9633 00:38:59.466271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9634 00:38:59.473612 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9635 00:38:59.476093 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9636 00:38:59.479880 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9637 00:38:59.486062 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9638 00:38:59.489811 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9639 00:38:59.496408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9640 00:38:59.499714 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9641 00:38:59.503711 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9642 00:38:59.509429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9643 00:38:59.513263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9644 00:38:59.519521 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9645 00:38:59.523209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9646 00:38:59.526440 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9647 00:38:59.533289 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9648 00:38:59.536174 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9649 00:38:59.540360 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9650 00:38:59.542953 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9651 00:38:59.549484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9652 00:38:59.553267 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9653 00:38:59.556344 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9654 00:38:59.559964 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9655 00:38:59.566497 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9656 00:38:59.569595 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9657 00:38:59.576287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9658 00:38:59.580094 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9659 00:38:59.583482 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9660 00:38:59.589897 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9661 00:38:59.593176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9662 00:38:59.596854 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9663 00:38:59.603387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9664 00:38:59.606728 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9665 00:38:59.613290 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9666 00:38:59.616934 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9667 00:38:59.621114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9668 00:38:59.627043 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9669 00:38:59.630809 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9670 00:38:59.637721 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9671 00:38:59.640152 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9672 00:38:59.643183 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9673 00:38:59.650490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9674 00:38:59.653356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9675 00:38:59.657065 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9676 00:38:59.663329 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9677 00:38:59.667087 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9678 00:38:59.673862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9679 00:38:59.677109 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9680 00:38:59.680748 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9681 00:38:59.687318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9682 00:38:59.691061 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9683 00:38:59.693721 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9684 00:38:59.700628 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9685 00:38:59.704124 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9686 00:38:59.711230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9687 00:38:59.715405 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9688 00:38:59.718400 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9689 00:38:59.724195 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9690 00:38:59.727844 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9691 00:38:59.730692 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9692 00:38:59.737686 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9693 00:38:59.741226 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9694 00:38:59.747932 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9695 00:38:59.751358 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9696 00:38:59.753982 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9697 00:38:59.761097 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9698 00:38:59.764431 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9699 00:38:59.767263 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9700 00:38:59.774573 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9701 00:38:59.777767 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9702 00:38:59.784016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9703 00:38:59.787856 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9704 00:38:59.791119 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9705 00:38:59.798186 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9706 00:38:59.800992 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9707 00:38:59.807414 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9708 00:38:59.810785 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9709 00:38:59.814118 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9710 00:38:59.820917 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9711 00:38:59.824984 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9712 00:38:59.828377 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9713 00:38:59.833993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9714 00:38:59.837845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9715 00:38:59.844325 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9716 00:38:59.847627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9717 00:38:59.851586 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9718 00:38:59.857500 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9719 00:38:59.861267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9720 00:38:59.867831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9721 00:38:59.870833 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9722 00:38:59.874547 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9723 00:38:59.881237 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9724 00:38:59.884264 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9725 00:38:59.891150 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9726 00:38:59.895201 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9727 00:38:59.897360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9728 00:38:59.904278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9729 00:38:59.907772 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9730 00:38:59.914139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9731 00:38:59.918177 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9732 00:38:59.920921 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9733 00:38:59.927803 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9734 00:38:59.931345 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9735 00:38:59.937882 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9736 00:38:59.942397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9737 00:38:59.944647 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9738 00:38:59.951480 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9739 00:38:59.954923 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9740 00:38:59.961350 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9741 00:38:59.964519 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9742 00:38:59.971363 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9743 00:38:59.974509 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9744 00:38:59.977558 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9745 00:38:59.984574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9746 00:38:59.988127 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9747 00:38:59.994392 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9748 00:38:59.997887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9749 00:39:00.001319 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9750 00:39:00.008016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9751 00:39:00.011246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9752 00:39:00.017935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9753 00:39:00.021442 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9754 00:39:00.024551 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9755 00:39:00.031459 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9756 00:39:00.034584 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9757 00:39:00.041250 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9758 00:39:00.044409 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9759 00:39:00.048340 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9760 00:39:00.054984 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9761 00:39:00.057967 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9762 00:39:00.061603 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9763 00:39:00.064566 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9764 00:39:00.071704 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9765 00:39:00.074746 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9766 00:39:00.077774 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9767 00:39:00.084644 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9768 00:39:00.087665 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9769 00:39:00.090988 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9770 00:39:00.097675 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9771 00:39:00.101681 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9772 00:39:00.108006 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9773 00:39:00.111031 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9774 00:39:00.115096 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9775 00:39:00.121098 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9776 00:39:00.124480 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9777 00:39:00.127775 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9778 00:39:00.134378 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9779 00:39:00.138361 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9780 00:39:00.141240 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9781 00:39:00.148301 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9782 00:39:00.151492 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9783 00:39:00.154792 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9784 00:39:00.161410 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9785 00:39:00.165702 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9786 00:39:00.168101 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9787 00:39:00.174846 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9788 00:39:00.178321 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9789 00:39:00.181511 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9790 00:39:00.188599 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9791 00:39:00.191820 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9792 00:39:00.198115 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9793 00:39:00.202017 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9794 00:39:00.204740 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9795 00:39:00.211396 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9796 00:39:00.214747 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9797 00:39:00.218343 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9798 00:39:00.225138 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9799 00:39:00.228396 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9800 00:39:00.231313 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9801 00:39:00.234857 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9802 00:39:00.239132 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9803 00:39:00.244676 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9804 00:39:00.248465 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9805 00:39:00.251821 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9806 00:39:00.254728 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9807 00:39:00.261721 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9808 00:39:00.264615 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9809 00:39:00.267988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9810 00:39:00.274572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9811 00:39:00.277757 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9812 00:39:00.281405 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9813 00:39:00.288075 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9814 00:39:00.291329 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9815 00:39:00.298358 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9816 00:39:00.301545 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9817 00:39:00.305309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9818 00:39:00.311413 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9819 00:39:00.315277 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9820 00:39:00.318157 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9821 00:39:00.324919 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9822 00:39:00.327790 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9823 00:39:00.335050 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9824 00:39:00.338169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9825 00:39:00.344978 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9826 00:39:00.347922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9827 00:39:00.351268 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9828 00:39:00.358304 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9829 00:39:00.361674 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9830 00:39:00.368466 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9831 00:39:00.371589 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9832 00:39:00.376324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9833 00:39:00.381469 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9834 00:39:00.384637 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9835 00:39:00.388392 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9836 00:39:00.395213 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9837 00:39:00.398008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9838 00:39:00.404812 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9839 00:39:00.408045 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9840 00:39:00.415023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9841 00:39:00.418074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9842 00:39:00.421619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9843 00:39:00.428203 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9844 00:39:00.431572 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9845 00:39:00.438030 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9846 00:39:00.441506 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9847 00:39:00.444833 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9848 00:39:00.451930 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9849 00:39:00.454702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9850 00:39:00.462204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9851 00:39:00.465117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9852 00:39:00.468293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9853 00:39:00.475215 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9854 00:39:00.478299 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9855 00:39:00.484922 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9856 00:39:00.488050 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9857 00:39:00.491884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9858 00:39:00.498519 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9859 00:39:00.501523 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9860 00:39:00.508488 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9861 00:39:00.511732 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9862 00:39:00.515102 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9863 00:39:00.521701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9864 00:39:00.524924 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9865 00:39:00.531946 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9866 00:39:00.535529 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9867 00:39:00.538721 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9868 00:39:00.545118 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9869 00:39:00.548408 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9870 00:39:00.555631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9871 00:39:00.558498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9872 00:39:00.561776 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9873 00:39:00.568578 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9874 00:39:00.571778 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9875 00:39:00.575343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9876 00:39:00.581895 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9877 00:39:00.585305 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9878 00:39:00.592505 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9879 00:39:00.595134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9880 00:39:00.601930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9881 00:39:00.604825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9882 00:39:00.608585 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9883 00:39:00.615091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9884 00:39:00.618412 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9885 00:39:00.625404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9886 00:39:00.628924 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9887 00:39:00.631629 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9888 00:39:00.638930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9889 00:39:00.641986 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9890 00:39:00.648450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9891 00:39:00.651488 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9892 00:39:00.658453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9893 00:39:00.661728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9894 00:39:00.665236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9895 00:39:00.672019 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9896 00:39:00.674989 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9897 00:39:00.681709 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9898 00:39:00.685311 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9899 00:39:00.692029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9900 00:39:00.696048 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9901 00:39:00.699065 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9902 00:39:00.706303 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9903 00:39:00.708876 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9904 00:39:00.715362 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9905 00:39:00.718642 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9906 00:39:00.724967 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9907 00:39:00.728305 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9908 00:39:00.731829 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9909 00:39:00.738513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9910 00:39:00.741678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9911 00:39:00.748577 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9912 00:39:00.751667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9913 00:39:00.758532 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9914 00:39:00.761700 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9915 00:39:00.765098 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9916 00:39:00.772001 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9917 00:39:00.774866 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9918 00:39:00.781743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9919 00:39:00.785159 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9920 00:39:00.792201 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9921 00:39:00.795369 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9922 00:39:00.801997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9923 00:39:00.804953 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9924 00:39:00.808589 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9925 00:39:00.816232 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9926 00:39:00.818994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9927 00:39:00.824943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9928 00:39:00.829138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9929 00:39:00.831641 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9930 00:39:00.838400 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9931 00:39:00.841747 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9932 00:39:00.848293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9933 00:39:00.851876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9934 00:39:00.855395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9935 00:39:00.861692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9936 00:39:00.865442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9937 00:39:00.871858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9938 00:39:00.875109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9939 00:39:00.881793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9940 00:39:00.885158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9941 00:39:00.891866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9942 00:39:00.895020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9943 00:39:00.902177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9944 00:39:00.905006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9945 00:39:00.912119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9946 00:39:00.915105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9947 00:39:00.921738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9948 00:39:00.925212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9949 00:39:00.931768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9950 00:39:00.935650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9951 00:39:00.941648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9952 00:39:00.944866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9953 00:39:00.948678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9954 00:39:00.955165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9955 00:39:00.958977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9956 00:39:00.965165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9957 00:39:00.968693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9958 00:39:00.975209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9959 00:39:00.978479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9960 00:39:00.985975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9961 00:39:00.988658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9962 00:39:00.995099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9963 00:39:00.998475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9964 00:39:01.005473 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9965 00:39:01.005554 INFO: [APUAPC] vio 0
9966 00:39:01.012111 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9967 00:39:01.015812 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9968 00:39:01.019870 INFO: [APUAPC] D0_APC_0: 0x400510
9969 00:39:01.022592 INFO: [APUAPC] D0_APC_1: 0x0
9970 00:39:01.026326 INFO: [APUAPC] D0_APC_2: 0x1540
9971 00:39:01.029258 INFO: [APUAPC] D0_APC_3: 0x0
9972 00:39:01.032511 INFO: [APUAPC] D1_APC_0: 0xffffffff
9973 00:39:01.035936 INFO: [APUAPC] D1_APC_1: 0xffffffff
9974 00:39:01.039985 INFO: [APUAPC] D1_APC_2: 0x3fffff
9975 00:39:01.042624 INFO: [APUAPC] D1_APC_3: 0x0
9976 00:39:01.046079 INFO: [APUAPC] D2_APC_0: 0xffffffff
9977 00:39:01.049220 INFO: [APUAPC] D2_APC_1: 0xffffffff
9978 00:39:01.052768 INFO: [APUAPC] D2_APC_2: 0x3fffff
9979 00:39:01.052880 INFO: [APUAPC] D2_APC_3: 0x0
9980 00:39:01.056183 INFO: [APUAPC] D3_APC_0: 0xffffffff
9981 00:39:01.062684 INFO: [APUAPC] D3_APC_1: 0xffffffff
9982 00:39:01.062765 INFO: [APUAPC] D3_APC_2: 0x3fffff
9983 00:39:01.065971 INFO: [APUAPC] D3_APC_3: 0x0
9984 00:39:01.069558 INFO: [APUAPC] D4_APC_0: 0xffffffff
9985 00:39:01.072506 INFO: [APUAPC] D4_APC_1: 0xffffffff
9986 00:39:01.076276 INFO: [APUAPC] D4_APC_2: 0x3fffff
9987 00:39:01.079285 INFO: [APUAPC] D4_APC_3: 0x0
9988 00:39:01.082752 INFO: [APUAPC] D5_APC_0: 0xffffffff
9989 00:39:01.086180 INFO: [APUAPC] D5_APC_1: 0xffffffff
9990 00:39:01.090142 INFO: [APUAPC] D5_APC_2: 0x3fffff
9991 00:39:01.092742 INFO: [APUAPC] D5_APC_3: 0x0
9992 00:39:01.096212 INFO: [APUAPC] D6_APC_0: 0xffffffff
9993 00:39:01.099403 INFO: [APUAPC] D6_APC_1: 0xffffffff
9994 00:39:01.102549 INFO: [APUAPC] D6_APC_2: 0x3fffff
9995 00:39:01.106599 INFO: [APUAPC] D6_APC_3: 0x0
9996 00:39:01.109890 INFO: [APUAPC] D7_APC_0: 0xffffffff
9997 00:39:01.112438 INFO: [APUAPC] D7_APC_1: 0xffffffff
9998 00:39:01.115763 INFO: [APUAPC] D7_APC_2: 0x3fffff
9999 00:39:01.119565 INFO: [APUAPC] D7_APC_3: 0x0
10000 00:39:01.122424 INFO: [APUAPC] D8_APC_0: 0xffffffff
10001 00:39:01.126035 INFO: [APUAPC] D8_APC_1: 0xffffffff
10002 00:39:01.129511 INFO: [APUAPC] D8_APC_2: 0x3fffff
10003 00:39:01.132830 INFO: [APUAPC] D8_APC_3: 0x0
10004 00:39:01.135757 INFO: [APUAPC] D9_APC_0: 0xffffffff
10005 00:39:01.140186 INFO: [APUAPC] D9_APC_1: 0xffffffff
10006 00:39:01.142963 INFO: [APUAPC] D9_APC_2: 0x3fffff
10007 00:39:01.146053 INFO: [APUAPC] D9_APC_3: 0x0
10008 00:39:01.149440 INFO: [APUAPC] D10_APC_0: 0xffffffff
10009 00:39:01.153319 INFO: [APUAPC] D10_APC_1: 0xffffffff
10010 00:39:01.155709 INFO: [APUAPC] D10_APC_2: 0x3fffff
10011 00:39:01.159358 INFO: [APUAPC] D10_APC_3: 0x0
10012 00:39:01.163613 INFO: [APUAPC] D11_APC_0: 0xffffffff
10013 00:39:01.166066 INFO: [APUAPC] D11_APC_1: 0xffffffff
10014 00:39:01.169490 INFO: [APUAPC] D11_APC_2: 0x3fffff
10015 00:39:01.172615 INFO: [APUAPC] D11_APC_3: 0x0
10016 00:39:01.175698 INFO: [APUAPC] D12_APC_0: 0xffffffff
10017 00:39:01.179039 INFO: [APUAPC] D12_APC_1: 0xffffffff
10018 00:39:01.183062 INFO: [APUAPC] D12_APC_2: 0x3fffff
10019 00:39:01.186127 INFO: [APUAPC] D12_APC_3: 0x0
10020 00:39:01.189131 INFO: [APUAPC] D13_APC_0: 0xffffffff
10021 00:39:01.192893 INFO: [APUAPC] D13_APC_1: 0xffffffff
10022 00:39:01.195823 INFO: [APUAPC] D13_APC_2: 0x3fffff
10023 00:39:01.199345 INFO: [APUAPC] D13_APC_3: 0x0
10024 00:39:01.202790 INFO: [APUAPC] D14_APC_0: 0xffffffff
10025 00:39:01.206147 INFO: [APUAPC] D14_APC_1: 0xffffffff
10026 00:39:01.209312 INFO: [APUAPC] D14_APC_2: 0x3fffff
10027 00:39:01.212403 INFO: [APUAPC] D14_APC_3: 0x0
10028 00:39:01.216333 INFO: [APUAPC] D15_APC_0: 0xffffffff
10029 00:39:01.219247 INFO: [APUAPC] D15_APC_1: 0xffffffff
10030 00:39:01.222407 INFO: [APUAPC] D15_APC_2: 0x3fffff
10031 00:39:01.226057 INFO: [APUAPC] D15_APC_3: 0x0
10032 00:39:01.229139 INFO: [APUAPC] APC_CON: 0x4
10033 00:39:01.232402 INFO: [NOCDAPC] D0_APC_0: 0x0
10034 00:39:01.232485 INFO: [NOCDAPC] D0_APC_1: 0x0
10035 00:39:01.235787 INFO: [NOCDAPC] D1_APC_0: 0x0
10036 00:39:01.238951 INFO: [NOCDAPC] D1_APC_1: 0xfff
10037 00:39:01.242495 INFO: [NOCDAPC] D2_APC_0: 0x0
10038 00:39:01.246220 INFO: [NOCDAPC] D2_APC_1: 0xfff
10039 00:39:01.249437 INFO: [NOCDAPC] D3_APC_0: 0x0
10040 00:39:01.252353 INFO: [NOCDAPC] D3_APC_1: 0xfff
10041 00:39:01.255785 INFO: [NOCDAPC] D4_APC_0: 0x0
10042 00:39:01.259279 INFO: [NOCDAPC] D4_APC_1: 0xfff
10043 00:39:01.262504 INFO: [NOCDAPC] D5_APC_0: 0x0
10044 00:39:01.262587 INFO: [NOCDAPC] D5_APC_1: 0xfff
10045 00:39:01.266040 INFO: [NOCDAPC] D6_APC_0: 0x0
10046 00:39:01.269735 INFO: [NOCDAPC] D6_APC_1: 0xfff
10047 00:39:01.272965 INFO: [NOCDAPC] D7_APC_0: 0x0
10048 00:39:01.276036 INFO: [NOCDAPC] D7_APC_1: 0xfff
10049 00:39:01.279215 INFO: [NOCDAPC] D8_APC_0: 0x0
10050 00:39:01.282681 INFO: [NOCDAPC] D8_APC_1: 0xfff
10051 00:39:01.286227 INFO: [NOCDAPC] D9_APC_0: 0x0
10052 00:39:01.289133 INFO: [NOCDAPC] D9_APC_1: 0xfff
10053 00:39:01.292468 INFO: [NOCDAPC] D10_APC_0: 0x0
10054 00:39:01.295697 INFO: [NOCDAPC] D10_APC_1: 0xfff
10055 00:39:01.295780 INFO: [NOCDAPC] D11_APC_0: 0x0
10056 00:39:01.299419 INFO: [NOCDAPC] D11_APC_1: 0xfff
10057 00:39:01.302891 INFO: [NOCDAPC] D12_APC_0: 0x0
10058 00:39:01.305914 INFO: [NOCDAPC] D12_APC_1: 0xfff
10059 00:39:01.309009 INFO: [NOCDAPC] D13_APC_0: 0x0
10060 00:39:01.312798 INFO: [NOCDAPC] D13_APC_1: 0xfff
10061 00:39:01.316112 INFO: [NOCDAPC] D14_APC_0: 0x0
10062 00:39:01.319131 INFO: [NOCDAPC] D14_APC_1: 0xfff
10063 00:39:01.322991 INFO: [NOCDAPC] D15_APC_0: 0x0
10064 00:39:01.325705 INFO: [NOCDAPC] D15_APC_1: 0xfff
10065 00:39:01.329152 INFO: [NOCDAPC] APC_CON: 0x4
10066 00:39:01.333346 INFO: [APUAPC] set_apusys_apc done
10067 00:39:01.336079 INFO: [DEVAPC] devapc_init done
10068 00:39:01.339436 INFO: GICv3 without legacy support detected.
10069 00:39:01.342783 INFO: ARM GICv3 driver initialized in EL3
10070 00:39:01.346241 INFO: Maximum SPI INTID supported: 639
10071 00:39:01.349632 INFO: BL31: Initializing runtime services
10072 00:39:01.355722 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10073 00:39:01.359663 INFO: SPM: enable CPC mode
10074 00:39:01.362820 INFO: mcdi ready for mcusys-off-idle and system suspend
10075 00:39:01.369219 INFO: BL31: Preparing for EL3 exit to normal world
10076 00:39:01.372872 INFO: Entry point address = 0x80000000
10077 00:39:01.375687 INFO: SPSR = 0x8
10078 00:39:01.380400
10079 00:39:01.380481
10080 00:39:01.380548
10081 00:39:01.384067 Starting depthcharge on Spherion...
10082 00:39:01.384154
10083 00:39:01.384219 Wipe memory regions:
10084 00:39:01.384280
10085 00:39:01.384927 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10086 00:39:01.385064 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10087 00:39:01.385185 Setting prompt string to ['asurada:']
10088 00:39:01.385323 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10089 00:39:01.386817 [0x00000040000000, 0x00000054600000)
10090 00:39:01.509424
10091 00:39:01.509548 [0x00000054660000, 0x00000080000000)
10092 00:39:01.769675
10093 00:39:01.769815 [0x000000821a7280, 0x000000ffe64000)
10094 00:39:02.514933
10095 00:39:02.515073 [0x00000100000000, 0x00000240000000)
10096 00:39:04.404081
10097 00:39:04.407295 Initializing XHCI USB controller at 0x11200000.
10098 00:39:05.444972
10099 00:39:05.448540 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10100 00:39:05.448627
10101 00:39:05.448692
10102 00:39:05.448971 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 00:39:05.549355 asurada: tftpboot 192.168.201.1 14173496/tftp-deploy-80fc64l7/kernel/image.itb 14173496/tftp-deploy-80fc64l7/kernel/cmdline
10105 00:39:05.549724 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 00:39:05.549854 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10107 00:39:05.554189 tftpboot 192.168.201.1 14173496/tftp-deploy-80fc64l7/kernel/image.ittp-deploy-80fc64l7/kernel/cmdline
10108 00:39:05.554273
10109 00:39:05.554337 Waiting for link
10110 00:39:05.714808
10111 00:39:05.714924 R8152: Initializing
10112 00:39:05.714990
10113 00:39:05.718004 Version 6 (ocp_data = 5c30)
10114 00:39:05.718086
10115 00:39:05.721403 R8152: Done initializing
10116 00:39:05.721510
10117 00:39:05.721599 Adding net device
10118 00:39:07.686270
10119 00:39:07.686413 done.
10120 00:39:07.686480
10121 00:39:07.686541 MAC: 00:24:32:30:78:52
10122 00:39:07.686599
10123 00:39:07.689772 Sending DHCP discover... done.
10124 00:39:07.689853
10125 00:39:12.205765 Waiting for reply... done.
10126 00:39:12.205904
10127 00:39:12.205970 Sending DHCP request... done.
10128 00:39:12.208991
10129 00:39:12.212750 Waiting for reply... done.
10130 00:39:12.212832
10131 00:39:12.212896 My ip is 192.168.201.14
10132 00:39:12.212956
10133 00:39:12.216367 The DHCP server ip is 192.168.201.1
10134 00:39:12.216450
10135 00:39:12.222928 TFTP server IP predefined by user: 192.168.201.1
10136 00:39:12.223011
10137 00:39:12.229498 Bootfile predefined by user: 14173496/tftp-deploy-80fc64l7/kernel/image.itb
10138 00:39:12.229580
10139 00:39:12.229645 Sending tftp read request... done.
10140 00:39:12.233183
10141 00:39:12.236636 Waiting for the transfer...
10142 00:39:12.236750
10143 00:39:12.774663 00000000 ################################################################
10144 00:39:12.774802
10145 00:39:13.300333 00080000 ################################################################
10146 00:39:13.300472
10147 00:39:13.839104 00100000 ################################################################
10148 00:39:13.839273
10149 00:39:14.403075 00180000 ################################################################
10150 00:39:14.403215
10151 00:39:14.973119 00200000 ################################################################
10152 00:39:14.973251
10153 00:39:15.573705 00280000 ################################################################
10154 00:39:15.573849
10155 00:39:16.179466 00300000 ################################################################
10156 00:39:16.180007
10157 00:39:16.864845 00380000 ################################################################
10158 00:39:16.865467
10159 00:39:17.520438 00400000 ################################################################
10160 00:39:17.520943
10161 00:39:18.190578 00480000 ################################################################
10162 00:39:18.190727
10163 00:39:18.920771 00500000 ################################################################
10164 00:39:18.920948
10165 00:39:19.573314 00580000 ################################################################
10166 00:39:19.573463
10167 00:39:20.159846 00600000 ################################################################
10168 00:39:20.159995
10169 00:39:20.740342 00680000 ################################################################
10170 00:39:20.740477
10171 00:39:21.313856 00700000 ################################################################
10172 00:39:21.313993
10173 00:39:21.904777 00780000 ################################################################
10174 00:39:21.904916
10175 00:39:22.520332 00800000 ################################################################
10176 00:39:22.520832
10177 00:39:23.106378 00880000 ################################################################
10178 00:39:23.106575
10179 00:39:23.740011 00900000 ################################################################
10180 00:39:23.740545
10181 00:39:24.365526 00980000 ################################################################
10182 00:39:24.365676
10183 00:39:24.954952 00a00000 ################################################################
10184 00:39:24.955092
10185 00:39:25.615155 00a80000 ################################################################
10186 00:39:25.615655
10187 00:39:26.275395 00b00000 ################################################################
10188 00:39:26.275539
10189 00:39:26.842793 00b80000 ################################################################
10190 00:39:26.842950
10191 00:39:27.402158 00c00000 ################################################################
10192 00:39:27.402293
10193 00:39:28.020608 00c80000 ################################################################
10194 00:39:28.020745
10195 00:39:28.634518 00d00000 ################################################################
10196 00:39:28.634653
10197 00:39:29.243745 00d80000 ################################################################
10198 00:39:29.244241
10199 00:39:29.855985 00e00000 ################################################################
10200 00:39:29.856118
10201 00:39:30.456868 00e80000 ################################################################
10202 00:39:30.457065
10203 00:39:31.051418 00f00000 ################################################################
10204 00:39:31.051578
10205 00:39:31.640033 00f80000 ################################################################
10206 00:39:31.640627
10207 00:39:32.285299 01000000 ################################################################
10208 00:39:32.285443
10209 00:39:32.883245 01080000 ################################################################
10210 00:39:32.883413
10211 00:39:33.496377 01100000 ################################################################
10212 00:39:33.496540
10213 00:39:34.099699 01180000 ################################################################
10214 00:39:34.099838
10215 00:39:34.703729 01200000 ################################################################
10216 00:39:34.703874
10217 00:39:35.341446 01280000 ################################################################
10218 00:39:35.341595
10219 00:39:35.952106 01300000 ################################################################
10220 00:39:35.952255
10221 00:39:36.591082 01380000 ################################################################
10222 00:39:36.591236
10223 00:39:37.220907 01400000 ################################################################
10224 00:39:37.221481
10225 00:39:37.898600 01480000 ################################################################
10226 00:39:37.899121
10227 00:39:38.578683 01500000 ################################################################
10228 00:39:38.579343
10229 00:39:39.261136 01580000 ################################################################
10230 00:39:39.261701
10231 00:39:39.931194 01600000 ################################################################
10232 00:39:39.931713
10233 00:39:40.608818 01680000 ################################################################
10234 00:39:40.609420
10235 00:39:41.288324 01700000 ################################################################
10236 00:39:41.288872
10237 00:39:41.974239 01780000 ################################################################
10238 00:39:41.974769
10239 00:39:42.661234 01800000 ################################################################
10240 00:39:42.661746
10241 00:39:43.340801 01880000 ################################################################
10242 00:39:43.341407
10243 00:39:43.997215 01900000 ################################################################
10244 00:39:43.997352
10245 00:39:44.578611 01980000 ################################################################
10246 00:39:44.578751
10247 00:39:45.162824 01a00000 ################################################################
10248 00:39:45.162980
10249 00:39:45.771070 01a80000 ################################################################
10250 00:39:45.771237
10251 00:39:46.383334 01b00000 ################################################################
10252 00:39:46.383485
10253 00:39:46.970569 01b80000 ################################################################
10254 00:39:46.970742
10255 00:39:47.580819 01c00000 ################################################################
10256 00:39:47.580957
10257 00:39:48.133106 01c80000 ################################################################
10258 00:39:48.133242
10259 00:39:48.697344 01d00000 ################################################################
10260 00:39:48.697504
10261 00:39:49.261340 01d80000 ################################################################
10262 00:39:49.261483
10263 00:39:49.669938 01e00000 ############################################### done.
10264 00:39:49.670094
10265 00:39:49.672924 The bootfile was 31837522 bytes long.
10266 00:39:49.673041
10267 00:39:49.676254 Sending tftp read request... done.
10268 00:39:49.676353
10269 00:39:49.676448 Waiting for the transfer...
10270 00:39:49.676539
10271 00:39:49.679437 00000000 # done.
10272 00:39:49.679539
10273 00:39:49.686102 Command line loaded dynamically from TFTP file: 14173496/tftp-deploy-80fc64l7/kernel/cmdline
10274 00:39:49.686181
10275 00:39:49.709778 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10276 00:39:49.709873
10277 00:39:49.709943 Loading FIT.
10278 00:39:49.710009
10279 00:39:49.712855 Image ramdisk-1 has 18728312 bytes.
10280 00:39:49.712950
10281 00:39:49.716318 Image fdt-1 has 47258 bytes.
10282 00:39:49.716410
10283 00:39:49.719644 Image kernel-1 has 13059919 bytes.
10284 00:39:49.719755
10285 00:39:49.729808 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10286 00:39:49.729929
10287 00:39:49.746523 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10288 00:39:49.746703
10289 00:39:49.749722 Choosing best match conf-1 for compat google,spherion-rev2.
10290 00:39:49.752840
10291 00:39:49.757137 Connected to device vid:did:rid of 1ae0:0028:00
10292 00:39:49.768669
10293 00:39:49.772131 tpm_get_response: command 0x17b, return code 0x0
10294 00:39:49.772681
10295 00:39:49.774856 ec_init: CrosEC protocol v3 supported (256, 248)
10296 00:39:49.779119
10297 00:39:49.782495 tpm_cleanup: add release locality here.
10298 00:39:49.782949
10299 00:39:49.783357 Shutting down all USB controllers.
10300 00:39:49.785794
10301 00:39:49.786289 Removing current net device
10302 00:39:49.786618
10303 00:39:49.792363 Exiting depthcharge with code 4 at timestamp: 77824779
10304 00:39:49.792958
10305 00:39:49.796044 LZMA decompressing kernel-1 to 0x821a6718
10306 00:39:49.796626
10307 00:39:49.799092 LZMA decompressing kernel-1 to 0x40000000
10308 00:39:51.408115
10309 00:39:51.408707 jumping to kernel
10310 00:39:51.412373 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10311 00:39:51.413080 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10312 00:39:51.413633 Setting prompt string to ['Linux version [0-9]']
10313 00:39:51.414182 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10314 00:39:51.414723 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10315 00:39:51.493080
10316 00:39:51.495420 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10317 00:39:51.498490 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10318 00:39:51.499021 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10319 00:39:51.499574 Setting prompt string to []
10320 00:39:51.500167 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10321 00:39:51.500712 Using line separator: #'\n'#
10322 00:39:51.501241 No login prompt set.
10323 00:39:51.501775 Parsing kernel messages
10324 00:39:51.502248 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10325 00:39:51.503153 [login-action] Waiting for messages, (timeout 00:03:35)
10326 00:39:51.503587 Waiting using forced prompt support (timeout 00:01:47)
10327 00:39:51.518296 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10328 00:39:51.521483 [ 0.000000] random: crng init done
10329 00:39:51.529029 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10330 00:39:51.531444 [ 0.000000] efi: UEFI not found.
10331 00:39:51.538001 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10332 00:39:51.544963 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10333 00:39:51.554778 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10334 00:39:51.564556 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10335 00:39:51.571695 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10336 00:39:51.574820 [ 0.000000] printk: bootconsole [mtk8250] enabled
10337 00:39:51.583646 [ 0.000000] NUMA: No NUMA configuration found
10338 00:39:51.590018 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10339 00:39:51.597089 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10340 00:39:51.597508 [ 0.000000] Zone ranges:
10341 00:39:51.603965 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10342 00:39:51.606915 [ 0.000000] DMA32 empty
10343 00:39:51.614025 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10344 00:39:51.617386 [ 0.000000] Movable zone start for each node
10345 00:39:51.620283 [ 0.000000] Early memory node ranges
10346 00:39:51.627504 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10347 00:39:51.634062 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10348 00:39:51.640226 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10349 00:39:51.646596 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10350 00:39:51.653682 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10351 00:39:51.659550 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10352 00:39:51.716617 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10353 00:39:51.723479 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10354 00:39:51.729783 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10355 00:39:51.733234 [ 0.000000] psci: probing for conduit method from DT.
10356 00:39:51.739756 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10357 00:39:51.743191 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10358 00:39:51.750114 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10359 00:39:51.753425 [ 0.000000] psci: SMC Calling Convention v1.2
10360 00:39:51.760263 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10361 00:39:51.763120 [ 0.000000] Detected VIPT I-cache on CPU0
10362 00:39:51.770204 [ 0.000000] CPU features: detected: GIC system register CPU interface
10363 00:39:51.777094 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10364 00:39:51.783594 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10365 00:39:51.790305 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10366 00:39:51.796704 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10367 00:39:51.803269 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10368 00:39:51.810944 [ 0.000000] alternatives: applying boot alternatives
10369 00:39:51.813457 [ 0.000000] Fallback order for Node 0: 0
10370 00:39:51.820212 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10371 00:39:51.823248 [ 0.000000] Policy zone: Normal
10372 00:39:51.846122 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10373 00:39:51.859644 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10374 00:39:51.870282 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10375 00:39:51.879915 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10376 00:39:51.886955 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10377 00:39:51.889781 <6>[ 0.000000] software IO TLB: area num 8.
10378 00:39:51.946787 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10379 00:39:52.095677 <6>[ 0.000000] Memory: 7945900K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406868K reserved, 32768K cma-reserved)
10380 00:39:52.102644 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10381 00:39:52.109337 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10382 00:39:52.112767 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10383 00:39:52.119393 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10384 00:39:52.126071 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10385 00:39:52.129209 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10386 00:39:52.139086 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10387 00:39:52.146353 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10388 00:39:52.149470 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10389 00:39:52.157667 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10390 00:39:52.160738 <6>[ 0.000000] GICv3: 608 SPIs implemented
10391 00:39:52.167313 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10392 00:39:52.170060 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10393 00:39:52.174062 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10394 00:39:52.183484 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10395 00:39:52.193212 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10396 00:39:52.206262 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10397 00:39:52.213030 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10398 00:39:52.222227 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10399 00:39:52.235889 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10400 00:39:52.242603 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10401 00:39:52.249297 <6>[ 0.009184] Console: colour dummy device 80x25
10402 00:39:52.259348 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10403 00:39:52.262972 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10404 00:39:52.269717 <6>[ 0.029215] LSM: Security Framework initializing
10405 00:39:52.276032 <6>[ 0.034154] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10406 00:39:52.286070 <6>[ 0.041968] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10407 00:39:52.292756 <6>[ 0.051431] cblist_init_generic: Setting adjustable number of callback queues.
10408 00:39:52.299625 <6>[ 0.058875] cblist_init_generic: Setting shift to 3 and lim to 1.
10409 00:39:52.306260 <6>[ 0.065212] cblist_init_generic: Setting adjustable number of callback queues.
10410 00:39:52.312891 <6>[ 0.072639] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 00:39:52.319346 <6>[ 0.079080] rcu: Hierarchical SRCU implementation.
10412 00:39:52.323136 <6>[ 0.079082] rcu: Max phase no-delay instances is 1000.
10413 00:39:52.329839 <6>[ 0.079106] printk: bootconsole [mtk8250] printing thread started
10414 00:39:52.337738 <6>[ 0.097456] EFI services will not be available.
10415 00:39:52.340920 <6>[ 0.097629] smp: Bringing up secondary CPUs ...
10416 00:39:52.347596 <6>[ 0.097913] Detected VIPT I-cache on CPU1
10417 00:39:52.353876 <6>[ 0.097982] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10418 00:39:52.360848 <6>[ 0.098013] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10419 00:39:52.370879 <6>[ 0.125863] Detected VIPT I-cache on CPU2
10420 00:39:52.377420 <6>[ 0.125915] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10421 00:39:52.383865 <6>[ 0.125933] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10422 00:39:52.390349 <6>[ 0.126191] Detected VIPT I-cache on CPU3
10423 00:39:52.397251 <6>[ 0.126239] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10424 00:39:52.403804 <6>[ 0.126253] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10425 00:39:52.406992 <6>[ 0.126560] CPU features: detected: Spectre-v4
10426 00:39:52.414228 <6>[ 0.126566] CPU features: detected: Spectre-BHB
10427 00:39:52.417547 <6>[ 0.126571] Detected PIPT I-cache on CPU4
10428 00:39:52.423959 <6>[ 0.126631] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10429 00:39:52.430542 <6>[ 0.126647] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10430 00:39:52.437144 <6>[ 0.126936] Detected PIPT I-cache on CPU5
10431 00:39:52.444178 <6>[ 0.126998] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10432 00:39:52.450898 <6>[ 0.127014] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10433 00:39:52.453654 <6>[ 0.127284] Detected PIPT I-cache on CPU6
10434 00:39:52.460890 <6>[ 0.127351] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10435 00:39:52.470859 <6>[ 0.127366] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10436 00:39:52.473748 <6>[ 0.127653] Detected PIPT I-cache on CPU7
10437 00:39:52.480479 <6>[ 0.127717] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10438 00:39:52.487755 <6>[ 0.127733] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10439 00:39:52.490517 <6>[ 0.127779] smp: Brought up 1 node, 8 CPUs
10440 00:39:52.497378 <6>[ 0.127784] SMP: Total of 8 processors activated.
10441 00:39:52.500570 <6>[ 0.127787] CPU features: detected: 32-bit EL0 Support
10442 00:39:52.510400 <6>[ 0.127789] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10443 00:39:52.517506 <6>[ 0.127791] CPU features: detected: Common not Private translations
10444 00:39:52.523925 <6>[ 0.127794] CPU features: detected: CRC32 instructions
10445 00:39:52.527031 <6>[ 0.127796] CPU features: detected: RCpc load-acquire (LDAPR)
10446 00:39:52.533687 <6>[ 0.127798] CPU features: detected: LSE atomic instructions
10447 00:39:52.541143 <6>[ 0.127799] CPU features: detected: Privileged Access Never
10448 00:39:52.547345 <6>[ 0.127801] CPU features: detected: RAS Extension Support
10449 00:39:52.553458 <6>[ 0.127804] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10450 00:39:52.556872 <6>[ 0.127872] CPU: All CPU(s) started at EL2
10451 00:39:52.563466 <6>[ 0.127874] alternatives: applying system-wide alternatives
10452 00:39:52.566966 <6>[ 0.141074] devtmpfs: initialized
10453 00:39:52.577048 <6>[ 0.147393] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10454 00:39:52.583615 <6>[ 0.147406] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10455 00:39:52.590649 <6>[ 0.148099] pinctrl core: initialized pinctrl subsystem
10456 00:39:52.614230 <6>[ 0.374484] printk: <console [ttyS0] printing thread started
10457 00:39:52.617471 6>[ 0.149277] DMI not present or invalid.
10458 00:39:52.624382 <6>[ 0.374492] printk: console [ttyS0] enabled
10459 00:39:52.627785 <6>[ 0.374495] printk: bootconsole [mtk8250] disabled
10460 00:39:52.634550 <6>[ 0.384419] printk: bootconsole [mtk8250] printing thread stopped
10461 00:39:52.641298 <6>[ 0.385905] SuperH (H)SCI(F) driver initialized
10462 00:39:52.644815 <6>[ 0.386382] msm_serial: driver initialized
10463 00:39:52.654880 <6>[ 0.390954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10464 00:39:52.661631 <6>[ 0.390983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10465 00:39:52.671195 <6>[ 0.391012] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10466 00:39:52.682174 <6>[ 0.391041] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10467 00:39:52.687398 <6>[ 0.391061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10468 00:39:52.700288 <6>[ 0.391089] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10469 00:39:52.716697 <6>[ 0.391117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10470 00:39:52.717916 <6>[ 0.391242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10471 00:39:52.722458 <6>[ 0.391272] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10472 00:39:52.727048 <6>[ 0.404278] loop: module loaded
10473 00:39:52.730983 <6>[ 0.406874] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10474 00:39:52.736710 <4>[ 0.423936] mtk-pmic-keys: Failed to locate of_node [id: -1]
10475 00:39:52.740738 <6>[ 0.424934] megasas: 07.719.03.00-rc1
10476 00:39:52.747250 <6>[ 0.436663] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10477 00:39:52.753563 <6>[ 0.440019] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10478 00:39:52.760155 <6>[ 0.452001] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10479 00:39:52.770925 <6>[ 0.505825] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10480 00:39:53.272117 <6>[ 1.029310] Freeing initrd memory: 18284K
10481 00:39:53.278923 <6>[ 1.036583] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10482 00:39:53.282263 <6>[ 1.041240] tun: Universal TUN/TAP device driver, 1.6
10483 00:39:53.285548 <6>[ 1.041987] thunder_xcv, ver 1.0
10484 00:39:53.288633 <6>[ 1.042005] thunder_bgx, ver 1.0
10485 00:39:53.292332 <6>[ 1.042018] nicpf, ver 1.0
10486 00:39:53.299201 <6>[ 1.043064] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10487 00:39:53.306129 <6>[ 1.043067] hns3: Copyright (c) 2017 Huawei Corporation.
10488 00:39:53.308962 <6>[ 1.043091] hclge is initializing
10489 00:39:53.316011 <6>[ 1.043105] e1000: Intel(R) PRO/1000 Network Driver
10490 00:39:53.319842 <6>[ 1.043108] e1000: Copyright (c) 1999-2006 Intel Corporation.
10491 00:39:53.327385 <6>[ 1.043124] e1000e: Intel(R) PRO/1000 Network Driver
10492 00:39:53.330434 <6>[ 1.043125] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10493 00:39:53.338139 <6>[ 1.043143] igb: Intel(R) Gigabit Ethernet Network Driver
10494 00:39:53.344295 <6>[ 1.043145] igb: Copyright (c) 2007-2014 Intel Corporation.
10495 00:39:53.351229 <6>[ 1.043159] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10496 00:39:53.355178 <6>[ 1.043161] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10497 00:39:53.358418 <6>[ 1.043444] sky2: driver version 1.30
10498 00:39:53.365419 <6>[ 1.044443] usbcore: registered new device driver r8152-cfgselector
10499 00:39:53.372305 <6>[ 1.044458] usbcore: registered new interface driver r8152
10500 00:39:53.378292 <6>[ 1.044539] VFIO - User Level meta-driver version: 0.3
10501 00:39:53.385660 <6>[ 1.047381] usbcore: registered new interface driver usb-storage
10502 00:39:53.391818 <6>[ 1.047560] usbcore: registered new device driver onboard-usb-hub
10503 00:39:53.395245 <6>[ 1.050310] mt6397-rtc mt6359-rtc: registered as rtc0
10504 00:39:53.405489 <6>[ 1.050458] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T00:39:53 UTC (1717547993)
10505 00:39:53.408425 <6>[ 1.051065] i2c_dev: i2c /dev entries driver
10506 00:39:53.419298 <6>[ 1.058187] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10507 00:39:53.421812 <4>[ 1.058910] cpu cpu0: supply cpu not found, using dummy regulator
10508 00:39:53.429051 <4>[ 1.058999] cpu cpu1: supply cpu not found, using dummy regulator
10509 00:39:53.435436 <4>[ 1.059052] cpu cpu2: supply cpu not found, using dummy regulator
10510 00:39:53.442130 <4>[ 1.059114] cpu cpu3: supply cpu not found, using dummy regulator
10511 00:39:53.449293 <4>[ 1.059162] cpu cpu4: supply cpu not found, using dummy regulator
10512 00:39:53.455834 <4>[ 1.059215] cpu cpu5: supply cpu not found, using dummy regulator
10513 00:39:53.462140 <4>[ 1.059266] cpu cpu6: supply cpu not found, using dummy regulator
10514 00:39:53.468573 <4>[ 1.059331] cpu cpu7: supply cpu not found, using dummy regulator
10515 00:39:53.471996 <6>[ 1.073612] cpu cpu0: EM: created perf domain
10516 00:39:53.478975 <6>[ 1.073938] cpu cpu4: EM: created perf domain
10517 00:39:53.482125 <6>[ 1.075078] sdhci: Secure Digital Host Controller Interface driver
10518 00:39:53.488711 <6>[ 1.075080] sdhci: Copyright(c) Pierre Ossman
10519 00:39:53.495144 <6>[ 1.075430] Synopsys Designware Multimedia Card Interface Driver
10520 00:39:53.498899 <6>[ 1.075818] sdhci-pltfm: SDHCI platform and OF driver helper
10521 00:39:53.506078 <6>[ 1.080098] ledtrig-cpu: registered to indicate activity on CPUs
10522 00:39:53.511903 <6>[ 1.080824] mmc0: CQHCI version 5.10
10523 00:39:53.519232 <6>[ 1.080953] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10524 00:39:53.522925 <6>[ 1.081243] usbcore: registered new interface driver usbhid
10525 00:39:53.525797 <6>[ 1.081245] usbhid: USB HID core driver
10526 00:39:53.535649 <6>[ 1.081351] spi_master spi0: will run message pump with realtime priority
10527 00:39:53.545309 <6>[ 1.112643] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10528 00:39:53.558538 <6>[ 1.115582] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10529 00:39:53.565354 <6>[ 1.116557] cros-ec-spi spi0.0: Chrome EC device registered
10530 00:39:53.576075 <6>[ 1.129083] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10531 00:39:53.578686 <6>[ 1.130034] NET: Registered PF_PACKET protocol family
10532 00:39:53.585733 <6>[ 1.130112] 9pnet: Installing 9P2000 support
10533 00:39:53.588737 <5>[ 1.130145] Key type dns_resolver registered
10534 00:39:53.592199 <6>[ 1.130570] registered taskstats version 1
10535 00:39:53.598948 <5>[ 1.130586] Loading compiled-in X.509 certificates
10536 00:39:53.609254 <4>[ 1.144677] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10537 00:39:53.619077 <4>[ 1.144789] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 00:39:53.625883 <6>[ 1.149572] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10539 00:39:53.632505 <6>[ 1.150135] xhci-mtk 11200000.usb: xHCI Host Controller
10540 00:39:53.639125 <6>[ 1.150161] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10541 00:39:53.648542 <6>[ 1.150370] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10542 00:39:53.655489 <6>[ 1.150417] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10543 00:39:53.659502 <6>[ 1.150528] xhci-mtk 11200000.usb: xHCI Host Controller
10544 00:39:53.669258 <6>[ 1.150532] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10545 00:39:53.676327 <6>[ 1.150537] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10546 00:39:53.678990 <6>[ 1.150939] hub 1-0:1.0: USB hub found
10547 00:39:53.682606 <6>[ 1.150949] hub 1-0:1.0: 1 port detected
10548 00:39:53.692494 <6>[ 1.151042] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10549 00:39:53.696144 <6>[ 1.151207] hub 2-0:1.0: USB hub found
10550 00:39:53.699591 <6>[ 1.151215] hub 2-0:1.0: 1 port detected
10551 00:39:53.706007 <6>[ 1.153352] mtk-msdc 11f70000.mmc: Got CD GPIO
10552 00:39:53.713236 <6>[ 1.165585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10553 00:39:53.719402 <6>[ 1.165592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10554 00:39:53.729445 <4>[ 1.165674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10555 00:39:53.735950 <6>[ 1.166167] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10556 00:39:53.746317 <6>[ 1.166169] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10557 00:39:53.752442 <6>[ 1.166349] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10558 00:39:53.762642 <6>[ 1.166358] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10559 00:39:53.769775 <6>[ 1.166361] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10560 00:39:53.778998 <6>[ 1.166363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10561 00:39:53.786103 <6>[ 1.167592] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10562 00:39:53.795486 <6>[ 1.167609] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10563 00:39:53.802295 <6>[ 1.167612] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10564 00:39:53.812175 <6>[ 1.167615] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10565 00:39:53.818605 <6>[ 1.167618] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10566 00:39:53.829616 <6>[ 1.167620] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10567 00:39:53.835855 <6>[ 1.167623] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10568 00:39:53.845297 <6>[ 1.167626] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10569 00:39:53.852128 <6>[ 1.167629] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10570 00:39:53.862189 <6>[ 1.167631] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10571 00:39:53.868494 <6>[ 1.167634] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10572 00:39:53.878515 <6>[ 1.167638] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10573 00:39:53.885031 <6>[ 1.167640] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10574 00:39:53.894909 <6>[ 1.167643] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10575 00:39:53.901785 <6>[ 1.167646] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10576 00:39:53.908653 <6>[ 1.167948] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10577 00:39:53.915575 <6>[ 1.168554] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10578 00:39:53.921453 <6>[ 1.168832] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10579 00:39:53.928155 <6>[ 1.169292] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10580 00:39:53.934704 <6>[ 1.169677] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10581 00:39:53.941360 <3>[ 1.169742] mtk-msdc 11f60000.mmc: phase error: [map:0]
10582 00:39:53.947496 <3>[ 1.169743] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10583 00:39:53.954087 <3>[ 1.169745] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10584 00:39:53.957537 <3>[ 1.169751] mmc0: error -5 whilst initialising MMC card
10585 00:39:53.967891 <6>[ 1.169904] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10586 00:39:53.977934 <6>[ 1.169915] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10587 00:39:53.987640 <6>[ 1.169919] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10588 00:39:53.994417 <6>[ 1.169922] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10589 00:39:54.004286 <6>[ 1.169925] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10590 00:39:54.013809 <6>[ 1.169929] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10591 00:39:54.024939 <6>[ 1.169932] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10592 00:39:54.034181 <6>[ 1.169935] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10593 00:39:54.041028 <6>[ 1.169938] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10594 00:39:54.053922 <6>[ 1.169942] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10595 00:39:54.064144 <6>[ 1.169944] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10596 00:39:54.070434 <6>[ 1.170230] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10597 00:39:54.077553 <6>[ 1.192295] Trying to probe devices needed for running init ...
10598 00:39:54.083982 <3>[ 1.275514] mtk-msdc 11f60000.mmc: phase error: [map:0]
10599 00:39:54.087540 <3>[ 1.275521] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10600 00:39:54.094127 <3>[ 1.275523] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10601 00:39:54.100173 <3>[ 1.275529] mmc0: error -5 whilst initialising MMC card
10602 00:39:54.107719 <6>[ 1.572802] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10603 00:39:54.113388 <3>[ 1.617020] mtk-msdc 11f60000.mmc: phase error: [map:0]
10604 00:39:54.120245 <3>[ 1.617027] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10605 00:39:54.123264 <3>[ 1.617028] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10606 00:39:54.130002 <3>[ 1.617035] mmc0: error -5 whilst initialising MMC card
10607 00:39:54.133719 <6>[ 1.732560] hub 1-1:1.0: USB hub found
10608 00:39:54.139740 <6>[ 1.732927] hub 1-1:1.0: 4 ports detected
10609 00:39:54.143218 <6>[ 1.735910] hub 1-1:1.0: USB hub found
10610 00:39:54.146337 <6>[ 1.736216] hub 1-1:1.0: 4 ports detected
10611 00:39:54.152962 <6>[ 1.865039] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10612 00:39:54.156297 <6>[ 1.890513] hub 2-1:1.0: USB hub found
10613 00:39:54.163039 <6>[ 1.890927] hub 2-1:1.0: 3 ports detected
10614 00:39:54.166688 <6>[ 1.894363] hub 2-1:1.0: USB hub found
10615 00:39:54.170155 <6>[ 1.894800] hub 2-1:1.0: 3 ports detected
10616 00:39:54.244373 <6>[ 2.001319] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10617 00:39:54.251953 <6>[ 2.010948] mmc0: Command Queue Engine enabled
10618 00:39:54.259065 <6>[ 2.010967] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 00:39:54.262102 <6>[ 2.011763] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 00:39:54.268593 <6>[ 2.021799] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10621 00:39:54.275042 <6>[ 2.024340] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 00:39:54.278446 <6>[ 2.024982] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10623 00:39:54.285283 <6>[ 2.025628] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10624 00:39:54.291907 <6>[ 2.048770] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10625 00:39:54.420495 <6>[ 2.177057] hub 1-1.4:1.0: USB hub found
10626 00:39:54.423689 <6>[ 2.177526] hub 1-1.4:1.0: 2 ports detected
10627 00:39:54.427173 <6>[ 2.181304] hub 1-1.4:1.0: USB hub found
10628 00:39:54.433778 <6>[ 2.181673] hub 1-1.4:1.0: 2 ports detected
10629 00:39:54.503397 <6>[ 2.257059] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10630 00:39:54.607917 <6>[ 2.361597] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10631 00:39:54.631554 <4>[ 2.388366] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10632 00:39:54.641557 <4>[ 2.388385] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10633 00:39:54.664119 <6>[ 2.421935] r8152 2-1.3:1.0 eth0: v1.12.13
10634 00:39:54.715548 <6>[ 2.468949] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10635 00:39:54.899554 <6>[ 2.652918] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10636 00:39:56.244006 <6>[ 4.001275] r8152 2-1.3:1.0 eth0: carrier on
10637 00:39:59.235580 <5>[ 4.024887] Sending DHCP requests .., OK
10638 00:39:59.242320 <6>[ 6.992826] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10639 00:39:59.245406 <6>[ 6.992846] IP-Config: Complete:
10640 00:39:59.258959 <6>[ 6.992849] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10641 00:39:59.265706 <6>[ 6.992862] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10642 00:39:59.273491 <6>[ 6.992867] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10643 00:39:59.279159 Loading, please <6>[ 6.992874] nameserver0=192.168.201.1
10644 00:39:59.282238 <6>[ 6.993148] clk: Disabling unused clocks
10645 00:39:59.285545 wait...
10646 00:39:59.288880 <6>[ 6.994200] ALSA device list:
10647 00:39:59.291925 <6>[ 6.994213] No soundcards found.
10648 00:39:59.296193 <6>[ 6.998595] Freeing unused kernel memory: 8512K
10649 00:39:59.302248 Starting systemd<6>[ 6.998779] Run /init as init process
10650 00:39:59.306371 -udevd version 252.22-1~deb12u1
10651 00:39:59.536095 <6>[ 7.291359] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10652 00:39:59.560224 <6>[ 7.318331] remoteproc remoteproc0: scp is available
10653 00:39:59.566548 <6>[ 7.318797] remoteproc remoteproc0: powering up scp
10654 00:39:59.573024 <6>[ 7.318805] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10655 00:39:59.581977 <6>[ 7.318833] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10656 00:39:59.589285 <6>[ 7.328420] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10657 00:39:59.599473 <6>[ 7.328450] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10658 00:39:59.609474 <6>[ 7.328460] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10659 00:39:59.616192 <4>[ 7.353309] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10660 00:39:59.622420 <4>[ 7.353465] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10661 00:39:59.632085 <3>[ 7.385619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 00:39:59.638922 <3>[ 7.385638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 00:39:59.648839 <3>[ 7.385643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 00:39:59.652890 <6>[ 7.386450] mc: Linux media interface: v0.10
10665 00:39:59.659261 <3>[ 7.389107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 00:39:59.668650 <3>[ 7.389133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 00:39:59.676124 <3>[ 7.389137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 00:39:59.685068 <3>[ 7.389142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 00:39:59.692012 <3>[ 7.389145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 00:39:59.698861 <3>[ 7.408100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 00:39:59.709667 <3>[ 7.416368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 00:39:59.715990 <3>[ 7.416402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 00:39:59.726327 <3>[ 7.416411] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 00:39:59.733322 <3>[ 7.423116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 00:39:59.740042 <3>[ 7.423231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 00:39:59.749619 <3>[ 7.423243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 00:39:59.756094 <3>[ 7.423265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 00:39:59.766611 <3>[ 7.423279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 00:39:59.773373 <3>[ 7.426499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 00:39:59.779803 <6>[ 7.430703] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10681 00:39:59.789986 <6>[ 7.440314] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10682 00:39:59.796136 <6>[ 7.440323] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10683 00:39:59.803045 <6>[ 7.440329] remoteproc remoteproc0: remote processor scp is now up
10684 00:39:59.809298 <6>[ 7.449902] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10685 00:39:59.815741 <6>[ 7.449910] pci_bus 0000:00: root bus resource [bus 00-ff]
10686 00:39:59.823016 <6>[ 7.449914] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10687 00:39:59.832474 <6>[ 7.449916] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10688 00:39:59.840994 <6>[ 7.449948] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10689 00:39:59.846712 <6>[ 7.449962] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10690 00:39:59.849660 <6>[ 7.450024] pci 0000:00:00.0: supports D1 D2
10691 00:39:59.856312 <6>[ 7.450026] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10692 00:39:59.865635 <6>[ 7.450970] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10693 00:39:59.873535 <6>[ 7.451052] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10694 00:39:59.879489 <6>[ 7.451077] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10695 00:39:59.886161 <6>[ 7.451093] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10696 00:39:59.895541 <6>[ 7.451107] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10697 00:39:59.899083 <6>[ 7.451212] pci 0000:01:00.0: supports D1 D2
10698 00:39:59.905682 <6>[ 7.451214] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10699 00:39:59.912566 <6>[ 7.459063] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10700 00:39:59.923052 <4>[ 7.459424] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10701 00:39:59.928807 <4>[ 7.459424] Fallback method does not support PEC.
10702 00:39:59.935125 <6>[ 7.460164] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10703 00:39:59.941987 <6>[ 7.460678] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10704 00:39:59.952202 <6>[ 7.460715] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10705 00:39:59.959115 <6>[ 7.460719] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10706 00:39:59.965730 <6>[ 7.460727] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10707 00:39:59.975553 <6>[ 7.460740] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10708 00:39:59.982026 <6>[ 7.460752] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10709 00:39:59.989308 <6>[ 7.460764] pci 0000:00:00.0: PCI bridge to [bus 01]
10710 00:39:59.995443 <6>[ 7.460769] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10711 00:40:00.001910 <6>[ 7.460901] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10712 00:40:00.009371 <6>[ 7.461356] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10713 00:40:00.015616 <6>[ 7.461765] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10714 00:40:00.022260 <6>[ 7.464653] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10715 00:40:00.032293 <3>[ 7.474754] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 00:40:00.042484 <6>[ 7.497341] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10717 00:40:00.053806 <6>[ 7.497639] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10718 00:40:00.059077 <3>[ 7.500846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 00:40:00.065497 <6>[ 7.515042] videodev: Linux video capture interface: v2.00
10720 00:40:00.075431 <5>[ 7.524831] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10721 00:40:00.081508 <5>[ 7.546431] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10722 00:40:00.088745 <5>[ 7.546691] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10723 00:40:00.097992 <4>[ 7.546760] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10724 00:40:00.101686 <6>[ 7.546767] cfg80211: failed to load regulatory.db
10725 00:40:00.108391 <6>[ 7.555552] Bluetooth: Core ver 2.22
10726 00:40:00.111039 <6>[ 7.555610] NET: Registered PF_BLUETOOTH protocol family
10727 00:40:00.117992 <6>[ 7.555612] Bluetooth: HCI device and connection manager initialized
10728 00:40:00.124585 <6>[ 7.555627] Bluetooth: HCI socket layer initialized
10729 00:40:00.128231 <6>[ 7.555631] Bluetooth: L2CAP socket layer initialized
10730 00:40:00.134155 <6>[ 7.555637] Bluetooth: SCO socket layer initialized
10731 00:40:00.140802 <6>[ 7.582749] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10732 00:40:00.154334 <6>[ 7.583949] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10733 00:40:00.161523 <6>[ 7.584120] usbcore: registered new interface driver uvcvideo
10734 00:40:00.167688 <6>[ 7.613045] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10735 00:40:00.171183 <6>[ 7.623903] usbcore: registered new interface driver btusb
10736 00:40:00.184011 <4>[ 7.625859] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10737 00:40:00.188074 <3>[ 7.625889] Bluetooth: hci0: Failed to load firmware file (-2)
10738 00:40:00.193989 <3>[ 7.625894] Bluetooth: hci0: Failed to set up firmware (-2)
10739 00:40:00.204398 <4>[ 7.625900] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10740 00:40:00.210307 <6>[ 7.651045] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10741 00:40:00.218014 <6>[ 7.651150] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10742 00:40:00.224647 <6>[ 7.668736] mt7921e 0000:01:00.0: ASIC revision: 79610010
10743 00:40:00.233598 <6>[ 7.764604] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10744 00:40:00.234147 <6>[ 7.764604]
10745 00:40:00.236887 Begin: Loading essential drivers ... done.
10746 00:40:00.244231 Begin: Running /scripts/init-premount ... done.
10747 00:40:00.250631 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10748 00:40:00.257490 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10749 00:40:00.267937 Device /sys/cl<6>[ 8.023644] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10750 00:40:00.270448 ass/net/eth0 found
10751 00:40:00.270905 done.
10752 00:40:00.276824 Begin: Waiting up to 180 secs for any network device to become available ... done.
10753 00:40:00.329304 IP-Config: eth0 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10754 00:40:00.334619 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10755 00:40:00.341627 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10756 00:40:00.347891 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10757 00:40:00.355049 host : mt8192-asurada-spherion-r0-cbg-3
10758 00:40:00.361307 domain : lava-rack
10759 00:40:00.364759 rootserver: 192.168.201.1 rootpath:
10760 00:40:00.367832 filename :
10761 00:40:00.524020 done.
10762 00:40:00.532850 Begin: Running /scripts/nfs-bottom ... done.
10763 00:40:00.551100 Begin: Running /scripts/init-bottom ... done.
10764 00:40:01.951755 <6>[ 9.711787] NET: Registered PF_INET6 protocol family
10765 00:40:01.954891 <6>[ 9.713719] Segment Routing with IPv6
10766 00:40:01.958159 <6>[ 9.713773] In-situ OAM (IOAM) with IPv6
10767 00:40:02.126280 <30>[ 9.859199] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10768 00:40:02.132508 <30>[ 9.859240] systemd[1]: Detected architecture arm64.
10769 00:40:02.133077
10770 00:40:02.139205 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10771 00:40:02.139778
10772 00:40:02.167437 <30>[ 9.926841] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10773 00:40:03.374775 <30>[ 11.132009] systemd[1]: Queued start job for default target graphical.target.
10774 00:40:03.404764 [[0;32m OK [0m] Created slic<30>[ 11.158244] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10775 00:40:03.407560 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10776 00:40:03.432060 [[0;32m OK [0m] Created slic<30>[ 11.186658] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10777 00:40:03.435650 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10778 00:40:03.460157 [[0;32m OK [0m] Created slic<30>[ 11.214658] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10779 00:40:03.467725 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10780 00:40:03.487906 [[0;32m OK [0m] Created slic<30>[ 11.242323] systemd[1]: Created slice user.slice - User and Session Slice.
10781 00:40:03.491475 e [0;1;39muser.slice[0m - User and Session Slice.
10782 00:40:03.517586 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 11.268923] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10783 00:40:03.521359 -passwo…quests to Console Directory Watch.
10784 00:40:03.546177 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 11.297150] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10785 00:40:03.548790 -passwo… Requests to Wall Directory Watch.
10786 00:40:03.583999 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 11.325073] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10787 00:40:03.591441 <30>[ 11.325199] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10788 00:40:03.594007 ice[0m - /dev/ttyS0...
10789 00:40:03.614397 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 11.368901] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10790 00:40:03.617688 tsetup.…get[0m - Local Encrypted Volumes.
10791 00:40:03.641928 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 11.392986] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10792 00:40:03.646279 grityse…Local Integrity Protected Volumes.
10793 00:40:03.666570 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 11.420992] systemd[1]: Reached target paths.target - Path Units.
10794 00:40:03.667120 s.target[0m - Path Units.
10795 00:40:03.691283 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 11.445351] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10796 00:40:03.694160 te-fs.target[0m - Remote File Systems.
10797 00:40:03.715463 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 11.468902] systemd[1]: Reached target slices.target - Slice Units.
10798 00:40:03.717746 es.target[0m - Slice Units.
10799 00:40:03.739044 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 11.492944] systemd[1]: Reached target swap.target - Swaps.
10800 00:40:03.739618 .target[0m - Swaps.
10801 00:40:03.764012 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 11.517471] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10802 00:40:03.769961 tysetup… - Local Verity Protected Volumes.
10803 00:40:03.791173 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.545385] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10804 00:40:03.797803 d-initc… initctl Compatibility Named Pipe.
10805 00:40:03.819786 <30>[ 11.576510] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10806 00:40:03.828906 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10807 00:40:03.848164 [[0;32m OK [0m] Listening on<30>[ 11.602682] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10808 00:40:03.855298 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10809 00:40:03.875351 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.629656] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10810 00:40:03.878580 d-journald.socket[0m - Journal Socket.
10811 00:40:03.900223 [[0;32m OK [0m] Listening on<30>[ 11.654709] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10812 00:40:03.907200 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10813 00:40:03.927168 [[0;32m OK [<30>[ 11.684472] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10814 00:40:03.936325 0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10815 00:40:03.955302 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.709398] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10816 00:40:03.958297 d-udevd…l.socket[0m - udev Kernel Socket.
10817 00:40:04.015000 Mounting [0;1;39mdev-hugepages.mount[<30>[ 11.769480] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10818 00:40:04.018010 0m - Huge Pages File System...
10819 00:40:04.037479 Mountin<30>[ 11.795447] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10820 00:40:04.044205 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10821 00:40:04.075359 Mounting [0;1;39msys-k<30>[ 11.829762] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10822 00:40:04.078956 ernel-debug.…[0m - Kernel Debug File System...
10823 00:40:04.113405 <30>[ 11.861599] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10824 00:40:04.122798 <30>[ 11.866204] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10825 00:40:04.129581 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10826 00:40:04.194941 Starting [0;1;39mmodprobe@configfs…m<30>[ 11.949482] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10827 00:40:04.198518 - Load Kernel Module configfs...
10828 00:40:04.231659 Starting [0;1;39mmodpr<30>[ 11.986389] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10829 00:40:04.235036 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10830 00:40:04.265956 Startin<30>[ 12.023667] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10831 00:40:04.272399 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10832 00:40:04.282867 <6>[ 12.038409] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10833 00:40:04.304448 Startin<30>[ 12.059299] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10834 00:40:04.307372 g [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10835 00:40:04.338798 Starting [0;1;39mmodprobe@fuse.ser…e<30>[ 12.093294] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10836 00:40:04.342220 [0m - Load Kernel Module fuse...
10837 00:40:04.369361 Startin<30>[ 12.127208] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10838 00:40:04.375918 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10839 00:40:04.394731 <6>[ 12.155875] fuse: init (API version 7.37)
10840 00:40:04.412574 Starting [0;1;39msyste<30>[ 12.166875] systemd[1]: Starting systemd-journald.service - Journal Service...
10841 00:40:04.415609 md-journald.service[0m - Journal Service...
10842 00:40:04.491608 Starting [0;1;39msyste<30>[ 12.246130] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10843 00:40:04.495171 md-modules-l…rvice[0m - Load Kernel Modules...
10844 00:40:04.528308 Starting [0;1;39msyste<30>[ 12.279074] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10845 00:40:04.530864 md-network-g… units from Kernel command line...
10846 00:40:04.559064 <30>[ 12.316412] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10847 00:40:04.568366 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10848 00:40:04.582265 <3>[ 12.338786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 00:40:04.599739 Starting [0;1;39msyste<30>[ 12.353673] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10850 00:40:04.602877 md-udev-trig…[0m - Coldplug All udev Devices...
10851 00:40:04.614692 <3>[ 12.369379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 00:40:04.629407 [[0;32m OK [<30>[ 12.387699] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10853 00:40:04.637408 0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10854 00:40:04.647711 <3>[ 12.403130] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 00:40:04.657391 [[0;32m OK [0m] Mounted [0;<30>[ 12.414031] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10856 00:40:04.670754 1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 12.427979] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 00:40:04.674068 File System.
10858 00:40:04.694326 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-<30>[ 12.449144] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10859 00:40:04.704995 debug.m…nt[0m<3>[ 12.451728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 00:40:04.714465 - Kernel Debug <3>[ 12.472012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 00:40:04.714552 File System.
10862 00:40:04.739143 [[0;32m OK [0m] Finished [0;1;39mkmod-stati<30>[ 12.493449] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10863 00:40:04.749174 c-nodes…reate <3>[ 12.493462] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 00:40:04.760109 List of Static D<3>[ 12.513420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 00:40:04.763313 evice Nodes.
10866 00:40:04.779967 [[0;32m OK [0m] Finished [0<3>[ 12.533138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 00:40:04.790451 ;1;39mmodprobe@c<30>[ 12.533919] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10868 00:40:04.797483 <30>[ 12.534428] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10869 00:40:04.807945 onfigfs…[0m - <3>[ 12.562828] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 00:40:04.810369 Load Kernel Module configfs.
10871 00:40:04.829586 [[0;32m OK [0m] Finished [0<30>[ 12.586172] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10872 00:40:04.839426 ;1;39mmodprobe@d<30>[ 12.586780] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10873 00:40:04.849678 <3>[ 12.592479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 00:40:04.854104 m_mod.s…e[0m - Load Kernel Module dm_mod.
10875 00:40:04.866390 <3>[ 12.622569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 00:40:04.880312 [[0;32m OK [<30>[ 12.635519] systemd[1]: modprobe@drm.service: Deactivated successfully.
10877 00:40:04.886180 0m] Finished [0<30>[ 12.636298] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10878 00:40:04.899263 ;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 12.655387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 00:40:04.902494 ule drm.
10880 00:40:04.918751 <3>[ 12.676016] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 00:40:04.925306 <30>[ 12.677851] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10882 00:40:04.935598 <30>[ 12.678288] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10883 00:40:04.945685 <3>[ 12.698121] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 00:40:04.952372 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10885 00:40:04.966396 <3>[ 12.720772] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 00:40:04.979599 [[0;32m OK [<30>[ 12.735466] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10887 00:40:04.989116 0m] Finished [0<30>[ 12.736303] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10888 00:40:04.992307 ;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10889 00:40:05.014337 [[0;32m OK [0m] Finished [0<30>[ 12.770347] systemd[1]: modprobe@loop.service: Deactivated successfully.
10890 00:40:05.024288 ;1;39mmodprobe@l<30>[ 12.771077] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10891 00:40:05.041155 <4>[ 12.787836] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10892 00:40:05.047418 oop.service[0m <3>[ 12.787844] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10893 00:40:05.050741 - Load Kernel Module loop.
10894 00:40:05.071703 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 12.825905] systemd[1]: Started systemd-journald.service - Journal Service.
10895 00:40:05.075275 rnald.service[0m - Journal Service.
10896 00:40:05.098784 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10897 00:40:05.120106 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10898 00:40:05.140296 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10899 00:40:05.160066 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10900 00:40:05.181616 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10901 00:40:05.227912 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10902 00:40:05.252088 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10903 00:40:05.300891 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10904 00:40:05.330673 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10905 00:40:05.366912 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10906 00:40:05.395048 <46>[ 13.152117] systemd-journald[315]: Received client request to flush runtime journal.
10907 00:40:05.433230 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10908 00:40:05.705642 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10909 00:40:05.723072 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10910 00:40:05.744326 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10911 00:40:05.770104 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10912 00:40:06.818878 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10913 00:40:06.840616 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10914 00:40:06.900281 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10915 00:40:07.022760 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10916 00:40:07.039732 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10917 00:40:07.054563 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10918 00:40:07.110983 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10919 00:40:07.133331 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10920 00:40:07.356834 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10921 00:40:07.424544 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10922 00:40:07.472135 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10923 00:40:07.757540 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10924 00:40:07.790217 <6>[ 15.549015] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10925 00:40:07.816783 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10926 00:40:07.848368 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10927 00:40:07.881382 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10928 00:40:07.999313 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10929 00:40:08.024894 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10930 00:40:08.049294 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10931 00:40:08.106933 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10932 00:40:08.137206 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10933 00:40:08.163348 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10934 00:40:08.211608 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10935 00:40:08.236420 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10936 00:40:08.255855 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10937 00:40:08.275471 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10938 00:40:08.302238 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10939 00:40:08.318680 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10940 00:40:08.335994 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10941 00:40:08.365135 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10942 00:40:08.386398 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10943 00:40:08.403178 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10944 00:40:08.426386 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10945 00:40:08.447239 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10946 00:40:08.462954 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10947 00:40:08.480791 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10948 00:40:08.498384 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10949 00:40:08.515865 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10950 00:40:08.559881 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10951 00:40:08.599939 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10952 00:40:08.696815 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10953 00:40:08.726568 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10954 00:40:08.780101 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10955 00:40:08.836708 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10956 00:40:08.889156 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10957 00:40:08.912422 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10958 00:40:08.934752 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10959 00:40:08.973997 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10960 00:40:09.096071 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10961 00:40:09.118500 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10962 00:40:09.135465 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10963 00:40:09.181331 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10964 00:40:09.235836 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10965 00:40:09.313126
10966 00:40:09.316444 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10967 00:40:09.316534
10968 00:40:09.320480 debian-bookworm-arm64 login: root (automatic login)
10969 00:40:09.320562
10970 00:40:09.593582 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10971 00:40:09.593715
10972 00:40:09.599975 The programs included with the Debian GNU/Linux system are free software;
10973 00:40:09.606530 the exact distribution terms for each program are described in the
10974 00:40:09.610524 individual files in /usr/share/doc/*/copyright.
10975 00:40:09.610601
10976 00:40:09.617210 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10977 00:40:09.620565 permitted by applicable law.
10978 00:40:09.724468 Matched prompt #10: / #
10980 00:40:09.725642 Setting prompt string to ['/ #']
10981 00:40:09.726092 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10983 00:40:09.727085 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10984 00:40:09.727529 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
10985 00:40:09.727894 Setting prompt string to ['/ #']
10986 00:40:09.728211 Forcing a shell prompt, looking for ['/ #']
10988 00:40:09.778937 / #
10989 00:40:09.779430 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10990 00:40:09.779796 Waiting using forced prompt support (timeout 00:02:30)
10991 00:40:09.785243
10992 00:40:09.786006 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10993 00:40:09.786470 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
10995 00:40:09.887505 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq'
10996 00:40:09.893670 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173496/extract-nfsrootfs-z3g0g3gq'
10998 00:40:09.995092 / # export NFS_SERVER_IP='192.168.201.1'
10999 00:40:10.001599 export NFS_SERVER_IP='192.168.201.1'
11000 00:40:10.002435 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11001 00:40:10.002959 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11002 00:40:10.003433 end: 2 depthcharge-action (duration 00:01:44) [common]
11003 00:40:10.003916 start: 3 lava-test-retry (timeout 00:01:00) [common]
11004 00:40:10.004403 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11005 00:40:10.004813 Using namespace: common
11007 00:40:10.105892 / # #
11008 00:40:10.106458 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11009 00:40:10.112768 #
11010 00:40:10.113576 Using /lava-14173496
11012 00:40:10.214646 / # export SHELL=/bin/sh
11013 00:40:10.220916 export SHELL=/bin/sh
11015 00:40:10.322370 / # . /lava-14173496/environment
11016 00:40:10.328640 . /lava-14173496/environment
11018 00:40:10.436053 / # /lava-14173496/bin/lava-test-runner /lava-14173496/0
11019 00:40:10.436801 Test shell timeout: 10s (minimum of the action and connection timeout)
11020 00:40:10.443352 /lava-14173496/bin/lava-test-runner /lava-14173496/0
11021 00:40:10.714877 + export TESTRUN_ID=0_dmesg
11022 00:40:10.717882 + cd /lava-14173496/0/tests/0_dmesg
11023 00:40:10.720847 + cat uuid
11024 00:40:10.731927 + UUID=14173496_1.6.2.3.1
11025 00:40:10.732358 + set +x
11026 00:40:10.741880 + KERNELCI_<8>[ 18.497576] <LAVA_SIGNAL_STARTRUN 0_dmesg 14173496_1.6.2.3.1>
11027 00:40:10.742604 Received signal: <STARTRUN> 0_dmesg 14173496_1.6.2.3.1
11028 00:40:10.742978 Starting test lava.0_dmesg (14173496_1.6.2.3.1)
11029 00:40:10.743377 Skipping test definition patterns.
11030 00:40:10.744628 LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11031 00:40:10.869644 <8>[ 18.625077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11032 00:40:10.870400 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11034 00:40:10.953576 <8>[ 18.711415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11035 00:40:10.954318 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11037 00:40:11.036151 + set +x
11038 00:40:11.046317 <8>[ 18.801032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11039 00:40:11.047012 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11041 00:40:11.053802 <LAVA_TEST_RUNNE<8>[ 18.802136] <LAVA_SIGNAL_ENDRUN 0_dmesg 14173496_1.6.2.3.1>
11042 00:40:11.054229 R EXIT>
11043 00:40:11.054823 Received signal: <ENDRUN> 0_dmesg 14173496_1.6.2.3.1
11044 00:40:11.055222 Ending use of test pattern.
11045 00:40:11.055533 Ending test lava.0_dmesg (14173496_1.6.2.3.1), duration 0.31
11047 00:40:30.125134 / # <6>[ 37.889049] vpu: disabling
11048 00:40:30.128302 <6>[ 37.889183] vproc2: disabling
11049 00:40:30.132176 <6>[ 37.889237] vproc1: disabling
11050 00:40:30.134603 <6>[ 37.889291] vaud18: disabling
11051 00:40:30.138221 <6>[ 37.889543] vsram_others: disabling
11052 00:40:30.141120 <6>[ 37.889721] va09: disabling
11053 00:40:30.144562 <6>[ 37.889798] vsram_md: disabling
11054 00:40:30.148185 <6>[ 37.889928] Vgpu: disabling
11056 00:41:10.004665 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11058 00:41:10.004853 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11060 00:41:10.005039 end: 3 lava-test-retry (duration 00:01:00) [common]
11062 00:41:10.005274 Cleaning after the job
11063 00:41:10.005362 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/ramdisk
11064 00:41:10.007586 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/kernel
11065 00:41:10.018177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/dtb
11066 00:41:10.018381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/nfsrootfs
11067 00:41:10.076221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173496/tftp-deploy-80fc64l7/modules
11068 00:41:10.082087 start: 4.1 power-off (timeout 00:00:30) [common]
11069 00:41:10.082274 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11070 00:41:10.158357 >> Command sent successfully.
11071 00:41:10.160660 Returned 0 in 0 seconds
11072 00:41:10.261137 end: 4.1 power-off (duration 00:00:00) [common]
11074 00:41:10.261471 start: 4.2 read-feedback (timeout 00:10:00) [common]
11075 00:41:10.261738 Listened to connection for namespace 'common' for up to 1s
11076 00:41:11.262704 Finalising connection for namespace 'common'
11077 00:41:11.262889 Disconnecting from shell: Finalise
11078 00:41:11.363255 end: 4.2 read-feedback (duration 00:00:01) [common]
11079 00:41:11.363433 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173496
11080 00:41:11.691545 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173496
11081 00:41:11.691746 TestError: A test failed to run, look at the error message.