Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 24
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 19
1 01:36:19.737585 lava-dispatcher, installed at version: 2024.03
2 01:36:19.737783 start: 0 validate
3 01:36:19.737914 Start time: 2024-06-05 01:36:19.737904+00:00 (UTC)
4 01:36:19.738029 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:36:19.738156 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:36:20.010592 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:36:20.011342 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:36:20.266583 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:36:20.267336 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:36:20.521858 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:36:20.522546 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:36:20.783993 validate duration: 1.05
14 01:36:20.785377 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:36:20.785996 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:36:20.786545 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:36:20.787187 Not decompressing ramdisk as can be used compressed.
18 01:36:20.787652 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 01:36:20.788010 saving as /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/ramdisk/rootfs.cpio.gz
20 01:36:20.788359 total size: 39026414 (37 MB)
21 01:36:20.793503 progress 0 % (0 MB)
22 01:36:20.825023 progress 5 % (1 MB)
23 01:36:20.839316 progress 10 % (3 MB)
24 01:36:20.850097 progress 15 % (5 MB)
25 01:36:20.860166 progress 20 % (7 MB)
26 01:36:20.870016 progress 25 % (9 MB)
27 01:36:20.879885 progress 30 % (11 MB)
28 01:36:20.889519 progress 35 % (13 MB)
29 01:36:20.899314 progress 40 % (14 MB)
30 01:36:20.909088 progress 45 % (16 MB)
31 01:36:20.919120 progress 50 % (18 MB)
32 01:36:20.929058 progress 55 % (20 MB)
33 01:36:20.938701 progress 60 % (22 MB)
34 01:36:20.948449 progress 65 % (24 MB)
35 01:36:20.958311 progress 70 % (26 MB)
36 01:36:20.968262 progress 75 % (27 MB)
37 01:36:20.978049 progress 80 % (29 MB)
38 01:36:20.987913 progress 85 % (31 MB)
39 01:36:20.997383 progress 90 % (33 MB)
40 01:36:21.007008 progress 95 % (35 MB)
41 01:36:21.016479 progress 100 % (37 MB)
42 01:36:21.016718 37 MB downloaded in 0.23 s (162.97 MB/s)
43 01:36:21.016869 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:36:21.017100 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:36:21.017187 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:36:21.017266 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:36:21.017457 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:36:21.017525 saving as /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/kernel/Image
50 01:36:21.017590 total size: 54682112 (52 MB)
51 01:36:21.017649 No compression specified
52 01:36:21.018755 progress 0 % (0 MB)
53 01:36:21.032470 progress 5 % (2 MB)
54 01:36:21.045942 progress 10 % (5 MB)
55 01:36:21.059448 progress 15 % (7 MB)
56 01:36:21.073217 progress 20 % (10 MB)
57 01:36:21.087028 progress 25 % (13 MB)
58 01:36:21.100739 progress 30 % (15 MB)
59 01:36:21.114649 progress 35 % (18 MB)
60 01:36:21.128220 progress 40 % (20 MB)
61 01:36:21.141901 progress 45 % (23 MB)
62 01:36:21.155622 progress 50 % (26 MB)
63 01:36:21.169060 progress 55 % (28 MB)
64 01:36:21.182968 progress 60 % (31 MB)
65 01:36:21.196931 progress 65 % (33 MB)
66 01:36:21.211004 progress 70 % (36 MB)
67 01:36:21.224558 progress 75 % (39 MB)
68 01:36:21.238380 progress 80 % (41 MB)
69 01:36:21.252136 progress 85 % (44 MB)
70 01:36:21.265667 progress 90 % (46 MB)
71 01:36:21.279193 progress 95 % (49 MB)
72 01:36:21.292356 progress 100 % (52 MB)
73 01:36:21.292567 52 MB downloaded in 0.27 s (189.65 MB/s)
74 01:36:21.292711 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:36:21.292933 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:36:21.293015 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:36:21.293095 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:36:21.293225 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:36:21.293302 saving as /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/dtb/mt8192-asurada-spherion-r0.dtb
81 01:36:21.293396 total size: 47258 (0 MB)
82 01:36:21.293454 No compression specified
83 01:36:21.294511 progress 69 % (0 MB)
84 01:36:21.294776 progress 100 % (0 MB)
85 01:36:21.294923 0 MB downloaded in 0.00 s (29.55 MB/s)
86 01:36:21.295038 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:36:21.295248 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:36:21.295329 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:36:21.295407 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:36:21.295512 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:36:21.295576 saving as /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/modules/modules.tar
93 01:36:21.295633 total size: 8605984 (8 MB)
94 01:36:21.295690 Using unxz to decompress xz
95 01:36:21.299825 progress 0 % (0 MB)
96 01:36:21.318917 progress 5 % (0 MB)
97 01:36:21.345810 progress 10 % (0 MB)
98 01:36:21.375041 progress 15 % (1 MB)
99 01:36:21.398167 progress 20 % (1 MB)
100 01:36:21.421625 progress 25 % (2 MB)
101 01:36:21.445112 progress 30 % (2 MB)
102 01:36:21.469084 progress 35 % (2 MB)
103 01:36:21.495305 progress 40 % (3 MB)
104 01:36:21.517670 progress 45 % (3 MB)
105 01:36:21.541681 progress 50 % (4 MB)
106 01:36:21.566939 progress 55 % (4 MB)
107 01:36:21.591473 progress 60 % (4 MB)
108 01:36:21.617768 progress 65 % (5 MB)
109 01:36:21.643760 progress 70 % (5 MB)
110 01:36:21.668105 progress 75 % (6 MB)
111 01:36:21.696744 progress 80 % (6 MB)
112 01:36:21.721971 progress 85 % (7 MB)
113 01:36:21.747113 progress 90 % (7 MB)
114 01:36:21.772184 progress 95 % (7 MB)
115 01:36:21.796876 progress 100 % (8 MB)
116 01:36:21.802172 8 MB downloaded in 0.51 s (16.20 MB/s)
117 01:36:21.802397 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:36:21.802661 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:36:21.802757 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:36:21.802850 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:36:21.802929 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:36:21.803010 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:36:21.803237 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we
125 01:36:21.803374 makedir: /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin
126 01:36:21.803477 makedir: /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/tests
127 01:36:21.803573 makedir: /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/results
128 01:36:21.803689 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-add-keys
129 01:36:21.803835 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-add-sources
130 01:36:21.803964 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-background-process-start
131 01:36:21.804094 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-background-process-stop
132 01:36:21.804219 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-common-functions
133 01:36:21.804342 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-echo-ipv4
134 01:36:21.804466 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-install-packages
135 01:36:21.804590 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-installed-packages
136 01:36:21.804715 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-os-build
137 01:36:21.804839 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-probe-channel
138 01:36:21.804961 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-probe-ip
139 01:36:21.805082 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-target-ip
140 01:36:21.805205 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-target-mac
141 01:36:21.805333 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-target-storage
142 01:36:21.805457 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-case
143 01:36:21.805580 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-event
144 01:36:21.805702 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-feedback
145 01:36:21.805824 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-raise
146 01:36:21.805946 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-reference
147 01:36:21.806069 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-runner
148 01:36:21.806191 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-set
149 01:36:21.806315 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-test-shell
150 01:36:21.806440 Updating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-install-packages (oe)
151 01:36:21.806587 Updating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/bin/lava-installed-packages (oe)
152 01:36:21.806708 Creating /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/environment
153 01:36:21.806808 LAVA metadata
154 01:36:21.806881 - LAVA_JOB_ID=14173528
155 01:36:21.806943 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:36:21.807044 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:36:21.807112 skipped lava-vland-overlay
158 01:36:21.807187 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:36:21.807270 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:36:21.807343 skipped lava-multinode-overlay
161 01:36:21.807415 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:36:21.807497 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:36:21.807581 Loading test definitions
164 01:36:21.807675 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:36:21.807747 Using /lava-14173528 at stage 0
166 01:36:21.808046 uuid=14173528_1.5.2.3.1 testdef=None
167 01:36:21.808132 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:36:21.808214 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:36:21.808724 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:36:21.808945 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:36:21.809580 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:36:21.809813 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:36:21.810845 runner path: /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/0/tests/0_cros-ec test_uuid 14173528_1.5.2.3.1
176 01:36:21.811000 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:36:21.811206 Creating lava-test-runner.conf files
179 01:36:21.811270 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173528/lava-overlay-bzbw74we/lava-14173528/0 for stage 0
180 01:36:21.811359 - 0_cros-ec
181 01:36:21.811455 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:36:21.811538 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:36:21.818651 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:36:21.818753 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:36:21.818837 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:36:21.818922 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:36:21.819005 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:36:23.015146 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:36:23.015531 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:36:23.015641 extracting modules file /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173528/extract-overlay-ramdisk-5ui19j9r/ramdisk
191 01:36:23.234798 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:36:23.234971 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:36:23.235059 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173528/compress-overlay-5c5j7d2i/overlay-1.5.2.4.tar.gz to ramdisk
194 01:36:23.235129 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173528/compress-overlay-5c5j7d2i/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173528/extract-overlay-ramdisk-5ui19j9r/ramdisk
195 01:36:23.241716 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:36:23.241830 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:36:23.241918 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:36:23.242005 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:36:23.242084 Building ramdisk /var/lib/lava/dispatcher/tmp/14173528/extract-overlay-ramdisk-5ui19j9r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173528/extract-overlay-ramdisk-5ui19j9r/ramdisk
200 01:36:24.131153 >> 335884 blocks
201 01:36:29.258324 rename /var/lib/lava/dispatcher/tmp/14173528/extract-overlay-ramdisk-5ui19j9r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/ramdisk/ramdisk.cpio.gz
202 01:36:29.258783 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 01:36:29.258911 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 01:36:29.259009 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 01:36:29.259114 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/kernel/Image']
206 01:36:42.050734 Returned 0 in 12 seconds
207 01:36:42.151770 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/kernel/image.itb
208 01:36:42.958601 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:36:42.958978 output: Created: Wed Jun 5 02:36:42 2024
210 01:36:42.959056 output: Image 0 (kernel-1)
211 01:36:42.959118 output: Description:
212 01:36:42.959178 output: Created: Wed Jun 5 02:36:42 2024
213 01:36:42.959239 output: Type: Kernel Image
214 01:36:42.959301 output: Compression: lzma compressed
215 01:36:42.959361 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
216 01:36:42.959419 output: Architecture: AArch64
217 01:36:42.959477 output: OS: Linux
218 01:36:42.959537 output: Load Address: 0x00000000
219 01:36:42.959595 output: Entry Point: 0x00000000
220 01:36:42.959651 output: Hash algo: crc32
221 01:36:42.959708 output: Hash value: 4c96ec19
222 01:36:42.959764 output: Image 1 (fdt-1)
223 01:36:42.959817 output: Description: mt8192-asurada-spherion-r0
224 01:36:42.959870 output: Created: Wed Jun 5 02:36:42 2024
225 01:36:42.959922 output: Type: Flat Device Tree
226 01:36:42.959974 output: Compression: uncompressed
227 01:36:42.960026 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 01:36:42.960078 output: Architecture: AArch64
229 01:36:42.960130 output: Hash algo: crc32
230 01:36:42.960181 output: Hash value: 0f8e4d2e
231 01:36:42.960233 output: Image 2 (ramdisk-1)
232 01:36:42.960284 output: Description: unavailable
233 01:36:42.960336 output: Created: Wed Jun 5 02:36:42 2024
234 01:36:42.960388 output: Type: RAMDisk Image
235 01:36:42.960439 output: Compression: Unknown Compression
236 01:36:42.960491 output: Data Size: 52141278 Bytes = 50919.22 KiB = 49.73 MiB
237 01:36:42.960543 output: Architecture: AArch64
238 01:36:42.960594 output: OS: Linux
239 01:36:42.960646 output: Load Address: unavailable
240 01:36:42.960697 output: Entry Point: unavailable
241 01:36:42.960749 output: Hash algo: crc32
242 01:36:42.960800 output: Hash value: 404ccdd9
243 01:36:42.960851 output: Default Configuration: 'conf-1'
244 01:36:42.960902 output: Configuration 0 (conf-1)
245 01:36:42.960954 output: Description: mt8192-asurada-spherion-r0
246 01:36:42.961005 output: Kernel: kernel-1
247 01:36:42.961056 output: Init Ramdisk: ramdisk-1
248 01:36:42.961107 output: FDT: fdt-1
249 01:36:42.961159 output: Loadables: kernel-1
250 01:36:42.961210 output:
251 01:36:42.961454 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:36:42.961551 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:36:42.961652 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 01:36:42.961746 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 01:36:42.961822 No LXC device requested
256 01:36:42.961900 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:36:42.961982 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 01:36:42.962057 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:36:42.962126 Checking files for TFTP limit of 4294967296 bytes.
260 01:36:42.962625 end: 1 tftp-deploy (duration 00:00:22) [common]
261 01:36:42.962729 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:36:42.962820 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:36:42.962940 substitutions:
264 01:36:42.963007 - {DTB}: 14173528/tftp-deploy-9xqmsftx/dtb/mt8192-asurada-spherion-r0.dtb
265 01:36:42.963069 - {INITRD}: 14173528/tftp-deploy-9xqmsftx/ramdisk/ramdisk.cpio.gz
266 01:36:42.963129 - {KERNEL}: 14173528/tftp-deploy-9xqmsftx/kernel/Image
267 01:36:42.963186 - {LAVA_MAC}: None
268 01:36:42.963242 - {PRESEED_CONFIG}: None
269 01:36:42.963298 - {PRESEED_LOCAL}: None
270 01:36:42.963352 - {RAMDISK}: 14173528/tftp-deploy-9xqmsftx/ramdisk/ramdisk.cpio.gz
271 01:36:42.963407 - {ROOT_PART}: None
272 01:36:42.963460 - {ROOT}: None
273 01:36:42.963513 - {SERVER_IP}: 192.168.201.1
274 01:36:42.963566 - {TEE}: None
275 01:36:42.963620 Parsed boot commands:
276 01:36:42.963672 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:36:42.963848 Parsed boot commands: tftpboot 192.168.201.1 14173528/tftp-deploy-9xqmsftx/kernel/image.itb 14173528/tftp-deploy-9xqmsftx/kernel/cmdline
278 01:36:42.963938 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:36:42.964023 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:36:42.964113 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:36:42.964196 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:36:42.964265 Not connected, no need to disconnect.
283 01:36:42.964337 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:36:42.964415 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:36:42.964487 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 01:36:42.968117 Setting prompt string to ['lava-test: # ']
287 01:36:42.968466 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:36:42.968567 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:36:42.968669 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:36:42.968758 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:36:42.968952 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 01:36:48.108756 >> Command sent successfully.
293 01:36:48.119858 Returned 0 in 5 seconds
294 01:36:48.221201 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:36:48.222787 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:36:48.223496 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:36:48.223987 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:36:48.224346 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:36:48.224719 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:36:48.226679 [Enter `^Ec?' for help]
302 01:36:48.393583
303 01:36:48.394159
304 01:36:48.394543 F0: 102B 0000
305 01:36:48.394904
306 01:36:48.395243 F3: 1001 0000 [0200]
307 01:36:48.395591
308 01:36:48.397419 F3: 1001 0000
309 01:36:48.397917
310 01:36:48.398285 F7: 102D 0000
311 01:36:48.398632
312 01:36:48.398960 F1: 0000 0000
313 01:36:48.399288
314 01:36:48.401071 V0: 0000 0000 [0001]
315 01:36:48.401606
316 01:36:48.401983 00: 0007 8000
317 01:36:48.402339
318 01:36:48.404434 01: 0000 0000
319 01:36:48.404912
320 01:36:48.405363 BP: 0C00 0209 [0000]
321 01:36:48.405786
322 01:36:48.408091 G0: 1182 0000
323 01:36:48.408588
324 01:36:48.408956 EC: 0000 0021 [4000]
325 01:36:48.409343
326 01:36:48.411647 S7: 0000 0000 [0000]
327 01:36:48.412116
328 01:36:48.412489 CC: 0000 0000 [0001]
329 01:36:48.412835
330 01:36:48.414976 T0: 0000 0040 [010F]
331 01:36:48.415462
332 01:36:48.415836 Jump to BL
333 01:36:48.416177
334 01:36:48.440354
335 01:36:48.440878
336 01:36:48.447637 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 01:36:48.451037 ARM64: Exception handlers installed.
338 01:36:48.454812 ARM64: Testing exception
339 01:36:48.458253 ARM64: Done test exception
340 01:36:48.465801 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 01:36:48.472773 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 01:36:48.479917 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 01:36:48.490910 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 01:36:48.497394 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 01:36:48.508093 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 01:36:48.518285 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 01:36:48.524666 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 01:36:48.543030 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 01:36:48.545975 WDT: Last reset was cold boot
350 01:36:48.549497 SPI1(PAD0) initialized at 2873684 Hz
351 01:36:48.552835 SPI5(PAD0) initialized at 992727 Hz
352 01:36:48.556326 VBOOT: Loading verstage.
353 01:36:48.562689 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 01:36:48.565994 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 01:36:48.569400 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 01:36:48.572945 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 01:36:48.580188 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 01:36:48.587038 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 01:36:48.598001 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 01:36:48.598572
361 01:36:48.598945
362 01:36:48.608015 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 01:36:48.611257 ARM64: Exception handlers installed.
364 01:36:48.614920 ARM64: Testing exception
365 01:36:48.615497 ARM64: Done test exception
366 01:36:48.621684 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 01:36:48.624719 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 01:36:48.638958 Probing TPM: . done!
369 01:36:48.639605 TPM ready after 0 ms
370 01:36:48.645845 Connected to device vid:did:rid of 1ae0:0028:00
371 01:36:48.652683 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 01:36:48.701511 Initialized TPM device CR50 revision 0
373 01:36:48.717977 tlcl_send_startup: Startup return code is 0
374 01:36:48.718568 TPM: setup succeeded
375 01:36:48.727049 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 01:36:48.737170 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 01:36:48.746093 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 01:36:48.754851 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 01:36:48.758181 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 01:36:48.761136 in-header: 03 07 00 00 08 00 00 00
381 01:36:48.764796 in-data: aa e4 47 04 13 02 00 00
382 01:36:48.768149 Chrome EC: UHEPI supported
383 01:36:48.774751 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 01:36:48.778261 in-header: 03 95 00 00 08 00 00 00
385 01:36:48.781785 in-data: 18 20 20 08 00 00 00 00
386 01:36:48.782401 Phase 1
387 01:36:48.785507 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 01:36:48.793062 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 01:36:48.796632 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 01:36:48.799933 Recovery requested (1009000e)
391 01:36:48.809487 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 01:36:48.815188 tlcl_extend: response is 0
393 01:36:48.824733 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 01:36:48.829992 tlcl_extend: response is 0
395 01:36:48.837116 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 01:36:48.857271 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 01:36:48.865172 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 01:36:48.865767
399 01:36:48.866144
400 01:36:48.872227 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 01:36:48.876043 ARM64: Exception handlers installed.
402 01:36:48.879257 ARM64: Testing exception
403 01:36:48.882642 ARM64: Done test exception
404 01:36:48.902508 pmic_efuse_setting: Set efuses in 11 msecs
405 01:36:48.905936 pmwrap_interface_init: Select PMIF_VLD_RDY
406 01:36:48.912377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 01:36:48.915862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 01:36:48.922327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 01:36:48.925967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 01:36:48.932347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 01:36:48.935787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 01:36:48.939028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 01:36:48.945926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 01:36:48.948869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 01:36:48.955663 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 01:36:48.958832 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 01:36:48.962441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 01:36:48.969131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 01:36:48.975756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 01:36:48.979464 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 01:36:48.987028 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 01:36:48.990353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 01:36:48.997639 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 01:36:49.005352 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 01:36:49.008969 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 01:36:49.012831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 01:36:49.019966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 01:36:49.027307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 01:36:49.031030 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 01:36:49.034846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 01:36:49.042766 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 01:36:49.045790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 01:36:49.053425 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 01:36:49.057232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 01:36:49.060876 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 01:36:49.068625 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 01:36:49.072044 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 01:36:49.075483 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 01:36:49.082785 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 01:36:49.086441 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 01:36:49.089994 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 01:36:49.097372 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 01:36:49.101026 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 01:36:49.104411 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 01:36:49.111690 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 01:36:49.115141 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 01:36:49.118998 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 01:36:49.122412 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 01:36:49.126407 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 01:36:49.133285 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 01:36:49.136983 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 01:36:49.140604 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 01:36:49.144297 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 01:36:49.148142 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 01:36:49.151841 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 01:36:49.159132 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 01:36:49.166328 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 01:36:49.173534 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 01:36:49.176868 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 01:36:49.187847 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 01:36:49.195181 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 01:36:49.198714 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 01:36:49.202219 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 01:36:49.209570 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:36:49.216565 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
466 01:36:49.219853 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 01:36:49.227152 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 01:36:49.230266 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 01:36:49.240044 [RTC]rtc_get_frequency_meter,154: input=15, output=764
470 01:36:49.249930 [RTC]rtc_get_frequency_meter,154: input=23, output=948
471 01:36:49.258714 [RTC]rtc_get_frequency_meter,154: input=19, output=856
472 01:36:49.268673 [RTC]rtc_get_frequency_meter,154: input=17, output=809
473 01:36:49.278037 [RTC]rtc_get_frequency_meter,154: input=16, output=787
474 01:36:49.287620 [RTC]rtc_get_frequency_meter,154: input=16, output=786
475 01:36:49.297048 [RTC]rtc_get_frequency_meter,154: input=17, output=810
476 01:36:49.300436 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 01:36:49.308095 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 01:36:49.312020 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 01:36:49.315183 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 01:36:49.319523 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 01:36:49.323069 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 01:36:49.326043 ADC[4]: Raw value=670432 ID=5
483 01:36:49.330133 ADC[3]: Raw value=212917 ID=1
484 01:36:49.330599 RAM Code: 0x51
485 01:36:49.333624 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 01:36:49.340895 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 01:36:49.348138 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 01:36:49.351882 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 01:36:49.355237 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 01:36:49.360741 in-header: 03 07 00 00 08 00 00 00
491 01:36:49.364006 in-data: aa e4 47 04 13 02 00 00
492 01:36:49.367336 Chrome EC: UHEPI supported
493 01:36:49.374944 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 01:36:49.377945 in-header: 03 95 00 00 08 00 00 00
495 01:36:49.381424 in-data: 18 20 20 08 00 00 00 00
496 01:36:49.385330 MRC: failed to locate region type 0.
497 01:36:49.388470 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 01:36:49.391958 DRAM-K: Running full calibration
499 01:36:49.399703 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 01:36:49.400194 header.status = 0x0
501 01:36:49.403331 header.version = 0x6 (expected: 0x6)
502 01:36:49.407213 header.size = 0xd00 (expected: 0xd00)
503 01:36:49.410750 header.flags = 0x0
504 01:36:49.413973 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 01:36:49.433671 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 01:36:49.441120 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 01:36:49.444974 dram_init: ddr_geometry: 0
508 01:36:49.445622 [EMI] MDL number = 0
509 01:36:49.448935 [EMI] Get MDL freq = 0
510 01:36:49.449600 dram_init: ddr_type: 0
511 01:36:49.452085 is_discrete_lpddr4: 1
512 01:36:49.455730 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 01:36:49.456216
514 01:36:49.456699
515 01:36:49.457156 [Bian_co] ETT version 0.0.0.1
516 01:36:49.463154 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 01:36:49.463639
518 01:36:49.467284 dramc_set_vcore_voltage set vcore to 650000
519 01:36:49.467765 Read voltage for 800, 4
520 01:36:49.470593 Vio18 = 0
521 01:36:49.471074 Vcore = 650000
522 01:36:49.471631 Vdram = 0
523 01:36:49.472086 Vddq = 0
524 01:36:49.474970 Vmddr = 0
525 01:36:49.475567 dram_init: config_dvfs: 1
526 01:36:49.482220 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 01:36:49.485606 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 01:36:49.489460 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 01:36:49.492835 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 01:36:49.496576 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 01:36:49.500721 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 01:36:49.504396 MEM_TYPE=3, freq_sel=18
533 01:36:49.508213 sv_algorithm_assistance_LP4_1600
534 01:36:49.511843 ============ PULL DRAM RESETB DOWN ============
535 01:36:49.515574 ========== PULL DRAM RESETB DOWN end =========
536 01:36:49.519130 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 01:36:49.522785 ===================================
538 01:36:49.526165 LPDDR4 DRAM CONFIGURATION
539 01:36:49.529788 ===================================
540 01:36:49.530269 EX_ROW_EN[0] = 0x0
541 01:36:49.533680 EX_ROW_EN[1] = 0x0
542 01:36:49.534164 LP4Y_EN = 0x0
543 01:36:49.534656 WORK_FSP = 0x0
544 01:36:49.537128 WL = 0x2
545 01:36:49.537682 RL = 0x2
546 01:36:49.540841 BL = 0x2
547 01:36:49.541357 RPST = 0x0
548 01:36:49.544839 RD_PRE = 0x0
549 01:36:49.545459 WR_PRE = 0x1
550 01:36:49.548496 WR_PST = 0x0
551 01:36:49.549072 DBI_WR = 0x0
552 01:36:49.552034 DBI_RD = 0x0
553 01:36:49.552496 OTF = 0x1
554 01:36:49.555733 ===================================
555 01:36:49.559461 ===================================
556 01:36:49.559927 ANA top config
557 01:36:49.563067 ===================================
558 01:36:49.566982 DLL_ASYNC_EN = 0
559 01:36:49.570744 ALL_SLAVE_EN = 1
560 01:36:49.571207 NEW_RANK_MODE = 1
561 01:36:49.574341 DLL_IDLE_MODE = 1
562 01:36:49.578280 LP45_APHY_COMB_EN = 1
563 01:36:49.578898 TX_ODT_DIS = 1
564 01:36:49.581337 NEW_8X_MODE = 1
565 01:36:49.584609 ===================================
566 01:36:49.588238 ===================================
567 01:36:49.591629 data_rate = 1600
568 01:36:49.594936 CKR = 1
569 01:36:49.598123 DQ_P2S_RATIO = 8
570 01:36:49.601786 ===================================
571 01:36:49.602318 CA_P2S_RATIO = 8
572 01:36:49.605328 DQ_CA_OPEN = 0
573 01:36:49.609056 DQ_SEMI_OPEN = 0
574 01:36:49.612385 CA_SEMI_OPEN = 0
575 01:36:49.612851 CA_FULL_RATE = 0
576 01:36:49.616385 DQ_CKDIV4_EN = 1
577 01:36:49.619662 CA_CKDIV4_EN = 1
578 01:36:49.623428 CA_PREDIV_EN = 0
579 01:36:49.626649 PH8_DLY = 0
580 01:36:49.627117 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 01:36:49.630183 DQ_AAMCK_DIV = 4
582 01:36:49.633461 CA_AAMCK_DIV = 4
583 01:36:49.636919 CA_ADMCK_DIV = 4
584 01:36:49.640530 DQ_TRACK_CA_EN = 0
585 01:36:49.640997 CA_PICK = 800
586 01:36:49.644599 CA_MCKIO = 800
587 01:36:49.647264 MCKIO_SEMI = 0
588 01:36:49.651068 PLL_FREQ = 3068
589 01:36:49.654190 DQ_UI_PI_RATIO = 32
590 01:36:49.657270 CA_UI_PI_RATIO = 0
591 01:36:49.661109 ===================================
592 01:36:49.664627 ===================================
593 01:36:49.665370 memory_type:LPDDR4
594 01:36:49.668059 GP_NUM : 10
595 01:36:49.668582 SRAM_EN : 1
596 01:36:49.672175 MD32_EN : 0
597 01:36:49.675945 ===================================
598 01:36:49.676554 [ANA_INIT] >>>>>>>>>>>>>>
599 01:36:49.679617 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 01:36:49.683361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 01:36:49.686769 ===================================
602 01:36:49.690403 data_rate = 1600,PCW = 0X7600
603 01:36:49.694041 ===================================
604 01:36:49.697787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 01:36:49.700992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 01:36:49.707821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:36:49.711317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 01:36:49.714592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 01:36:49.718196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:36:49.720947 [ANA_INIT] flow start
611 01:36:49.721443 [ANA_INIT] PLL >>>>>>>>
612 01:36:49.724621 [ANA_INIT] PLL <<<<<<<<
613 01:36:49.728034 [ANA_INIT] MIDPI >>>>>>>>
614 01:36:49.731352 [ANA_INIT] MIDPI <<<<<<<<
615 01:36:49.731923 [ANA_INIT] DLL >>>>>>>>
616 01:36:49.734667 [ANA_INIT] flow end
617 01:36:49.738019 ============ LP4 DIFF to SE enter ============
618 01:36:49.741424 ============ LP4 DIFF to SE exit ============
619 01:36:49.744945 [ANA_INIT] <<<<<<<<<<<<<
620 01:36:49.748097 [Flow] Enable top DCM control >>>>>
621 01:36:49.751433 [Flow] Enable top DCM control <<<<<
622 01:36:49.754761 Enable DLL master slave shuffle
623 01:36:49.761278 ==============================================================
624 01:36:49.761872 Gating Mode config
625 01:36:49.768107 ==============================================================
626 01:36:49.768682 Config description:
627 01:36:49.777766 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 01:36:49.784973 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 01:36:49.791368 SELPH_MODE 0: By rank 1: By Phase
630 01:36:49.794557 ==============================================================
631 01:36:49.798155 GAT_TRACK_EN = 1
632 01:36:49.801273 RX_GATING_MODE = 2
633 01:36:49.804489 RX_GATING_TRACK_MODE = 2
634 01:36:49.808069 SELPH_MODE = 1
635 01:36:49.811380 PICG_EARLY_EN = 1
636 01:36:49.814483 VALID_LAT_VALUE = 1
637 01:36:49.817833 ==============================================================
638 01:36:49.821409 Enter into Gating configuration >>>>
639 01:36:49.824533 Exit from Gating configuration <<<<
640 01:36:49.827824 Enter into DVFS_PRE_config >>>>>
641 01:36:49.840944 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 01:36:49.844628 Exit from DVFS_PRE_config <<<<<
643 01:36:49.847640 Enter into PICG configuration >>>>
644 01:36:49.848110 Exit from PICG configuration <<<<
645 01:36:49.850940 [RX_INPUT] configuration >>>>>
646 01:36:49.854127 [RX_INPUT] configuration <<<<<
647 01:36:49.861508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 01:36:49.864444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 01:36:49.871143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 01:36:49.877915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 01:36:49.884551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 01:36:49.891323 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 01:36:49.894368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 01:36:49.897435 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 01:36:49.900699 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 01:36:49.907288 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 01:36:49.910747 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 01:36:49.913980 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 01:36:49.917563 ===================================
660 01:36:49.920941 LPDDR4 DRAM CONFIGURATION
661 01:36:49.924336 ===================================
662 01:36:49.927331 EX_ROW_EN[0] = 0x0
663 01:36:49.927797 EX_ROW_EN[1] = 0x0
664 01:36:49.930682 LP4Y_EN = 0x0
665 01:36:49.931147 WORK_FSP = 0x0
666 01:36:49.934175 WL = 0x2
667 01:36:49.934813 RL = 0x2
668 01:36:49.937623 BL = 0x2
669 01:36:49.938085 RPST = 0x0
670 01:36:49.940628 RD_PRE = 0x0
671 01:36:49.941208 WR_PRE = 0x1
672 01:36:49.943934 WR_PST = 0x0
673 01:36:49.944394 DBI_WR = 0x0
674 01:36:49.947419 DBI_RD = 0x0
675 01:36:49.947886 OTF = 0x1
676 01:36:49.950914 ===================================
677 01:36:49.953932 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 01:36:49.960556 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 01:36:49.964128 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 01:36:49.967107 ===================================
681 01:36:49.970319 LPDDR4 DRAM CONFIGURATION
682 01:36:49.974402 ===================================
683 01:36:49.974975 EX_ROW_EN[0] = 0x10
684 01:36:49.977534 EX_ROW_EN[1] = 0x0
685 01:36:49.980349 LP4Y_EN = 0x0
686 01:36:49.980818 WORK_FSP = 0x0
687 01:36:49.984201 WL = 0x2
688 01:36:49.984778 RL = 0x2
689 01:36:49.987334 BL = 0x2
690 01:36:49.987800 RPST = 0x0
691 01:36:49.990664 RD_PRE = 0x0
692 01:36:49.991128 WR_PRE = 0x1
693 01:36:49.993744 WR_PST = 0x0
694 01:36:49.994207 DBI_WR = 0x0
695 01:36:49.997226 DBI_RD = 0x0
696 01:36:49.997725 OTF = 0x1
697 01:36:50.000473 ===================================
698 01:36:50.007023 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 01:36:50.011383 nWR fixed to 40
700 01:36:50.015045 [ModeRegInit_LP4] CH0 RK0
701 01:36:50.015607 [ModeRegInit_LP4] CH0 RK1
702 01:36:50.018137 [ModeRegInit_LP4] CH1 RK0
703 01:36:50.021609 [ModeRegInit_LP4] CH1 RK1
704 01:36:50.022175 match AC timing 12
705 01:36:50.028341 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 01:36:50.031702 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 01:36:50.034940 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 01:36:50.041516 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 01:36:50.044733 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 01:36:50.045263 [EMI DOE] emi_dcm 0
711 01:36:50.051519 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 01:36:50.052084 ==
713 01:36:50.054906 Dram Type= 6, Freq= 0, CH_0, rank 0
714 01:36:50.058088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 01:36:50.058564 ==
716 01:36:50.064636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 01:36:50.071188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 01:36:50.078702 [CA 0] Center 37 (7~68) winsize 62
719 01:36:50.081960 [CA 1] Center 37 (7~68) winsize 62
720 01:36:50.085552 [CA 2] Center 35 (5~66) winsize 62
721 01:36:50.088584 [CA 3] Center 35 (5~66) winsize 62
722 01:36:50.092319 [CA 4] Center 34 (4~65) winsize 62
723 01:36:50.095513 [CA 5] Center 34 (4~65) winsize 62
724 01:36:50.095980
725 01:36:50.098917 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 01:36:50.099484
727 01:36:50.102304 [CATrainingPosCal] consider 1 rank data
728 01:36:50.105663 u2DelayCellTimex100 = 270/100 ps
729 01:36:50.108890 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
730 01:36:50.112428 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 01:36:50.118918 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 01:36:50.122394 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
733 01:36:50.125668 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 01:36:50.128628 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
735 01:36:50.129100
736 01:36:50.132096 CA PerBit enable=1, Macro0, CA PI delay=34
737 01:36:50.132664
738 01:36:50.135368 [CBTSetCACLKResult] CA Dly = 34
739 01:36:50.135934 CS Dly: 6 (0~37)
740 01:36:50.138704 ==
741 01:36:50.139273 Dram Type= 6, Freq= 0, CH_0, rank 1
742 01:36:50.145665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 01:36:50.146236 ==
744 01:36:50.148362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 01:36:50.155469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 01:36:50.164666 [CA 0] Center 37 (7~68) winsize 62
747 01:36:50.167855 [CA 1] Center 37 (6~68) winsize 63
748 01:36:50.171097 [CA 2] Center 35 (5~66) winsize 62
749 01:36:50.174445 [CA 3] Center 35 (4~66) winsize 63
750 01:36:50.178188 [CA 4] Center 33 (3~64) winsize 62
751 01:36:50.181149 [CA 5] Center 34 (3~65) winsize 63
752 01:36:50.181672
753 01:36:50.184783 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 01:36:50.185409
755 01:36:50.188061 [CATrainingPosCal] consider 2 rank data
756 01:36:50.191222 u2DelayCellTimex100 = 270/100 ps
757 01:36:50.194508 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
758 01:36:50.197906 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 01:36:50.204602 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 01:36:50.207826 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 01:36:50.211477 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
762 01:36:50.214752 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
763 01:36:50.215221
764 01:36:50.217767 CA PerBit enable=1, Macro0, CA PI delay=34
765 01:36:50.218252
766 01:36:50.221256 [CBTSetCACLKResult] CA Dly = 34
767 01:36:50.221763 CS Dly: 6 (0~37)
768 01:36:50.222135
769 01:36:50.224448 ----->DramcWriteLeveling(PI) begin...
770 01:36:50.227563 ==
771 01:36:50.231178 Dram Type= 6, Freq= 0, CH_0, rank 0
772 01:36:50.234546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 01:36:50.235116 ==
774 01:36:50.238165 Write leveling (Byte 0): 27 => 27
775 01:36:50.240987 Write leveling (Byte 1): 28 => 28
776 01:36:50.244924 DramcWriteLeveling(PI) end<-----
777 01:36:50.245576
778 01:36:50.245963 ==
779 01:36:50.246306 Dram Type= 6, Freq= 0, CH_0, rank 0
780 01:36:50.252458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 01:36:50.252991 ==
782 01:36:50.253390 [Gating] SW mode calibration
783 01:36:50.259904 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 01:36:50.266761 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 01:36:50.269961 0 6 0 | B1->B0 | 3434 3131 | 0 1 | (0 1) (1 0)
786 01:36:50.273359 0 6 4 | B1->B0 | 2828 2525 | 0 0 | (1 1) (0 0)
787 01:36:50.280368 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 01:36:50.283669 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 01:36:50.286858 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:36:50.293658 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:36:50.296965 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:36:50.300709 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:36:50.307277 0 7 0 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
794 01:36:50.310186 0 7 4 | B1->B0 | 3a3a 3e3e | 0 0 | (0 0) (0 0)
795 01:36:50.313413 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 01:36:50.320218 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 01:36:50.323416 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 01:36:50.326833 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 01:36:50.333364 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 01:36:50.336810 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 01:36:50.340028 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 01:36:50.343522 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 01:36:50.349877 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 01:36:50.353543 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 01:36:50.356543 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 01:36:50.363563 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 01:36:50.366685 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 01:36:50.369766 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 01:36:50.376403 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 01:36:50.379564 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 01:36:50.383118 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 01:36:50.389899 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 01:36:50.392989 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 01:36:50.396556 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 01:36:50.403409 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 01:36:50.406404 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 01:36:50.409671 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
818 01:36:50.416461 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 01:36:50.419868 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 01:36:50.422980 Total UI for P1: 0, mck2ui 16
821 01:36:50.426244 best dqsien dly found for B0: ( 0, 10, 4)
822 01:36:50.429665 Total UI for P1: 0, mck2ui 16
823 01:36:50.433199 best dqsien dly found for B1: ( 0, 10, 2)
824 01:36:50.436465 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
825 01:36:50.439519 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
826 01:36:50.440012
827 01:36:50.442969 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
828 01:36:50.446364 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 01:36:50.449701 [Gating] SW calibration Done
830 01:36:50.450165 ==
831 01:36:50.452925 Dram Type= 6, Freq= 0, CH_0, rank 0
832 01:36:50.456063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 01:36:50.459588 ==
834 01:36:50.460008 RX Vref Scan: 0
835 01:36:50.460341
836 01:36:50.462776 RX Vref 0 -> 0, step: 1
837 01:36:50.463240
838 01:36:50.466166 RX Delay -130 -> 252, step: 16
839 01:36:50.469550 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 01:36:50.473126 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
841 01:36:50.476240 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 01:36:50.479342 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 01:36:50.486092 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
844 01:36:50.489579 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 01:36:50.492931 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 01:36:50.495929 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 01:36:50.499430 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
848 01:36:50.506136 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 01:36:50.509275 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 01:36:50.512749 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 01:36:50.516382 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 01:36:50.519258 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 01:36:50.526255 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 01:36:50.529392 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 01:36:50.529933 ==
856 01:36:50.532971 Dram Type= 6, Freq= 0, CH_0, rank 0
857 01:36:50.536120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 01:36:50.536591 ==
859 01:36:50.539335 DQS Delay:
860 01:36:50.539800 DQS0 = 0, DQS1 = 0
861 01:36:50.540196 DQM Delay:
862 01:36:50.542682 DQM0 = 80, DQM1 = 75
863 01:36:50.543167 DQ Delay:
864 01:36:50.546001 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
865 01:36:50.549461 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
866 01:36:50.552551 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
867 01:36:50.556409 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 01:36:50.557018
869 01:36:50.557578
870 01:36:50.558034 ==
871 01:36:50.559259 Dram Type= 6, Freq= 0, CH_0, rank 0
872 01:36:50.565990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 01:36:50.566586 ==
874 01:36:50.567080
875 01:36:50.567538
876 01:36:50.567985 TX Vref Scan disable
877 01:36:50.569378 == TX Byte 0 ==
878 01:36:50.573017 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 01:36:50.575920 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 01:36:50.579786 == TX Byte 1 ==
881 01:36:50.582684 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
882 01:36:50.586456 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
883 01:36:50.589397 ==
884 01:36:50.592743 Dram Type= 6, Freq= 0, CH_0, rank 0
885 01:36:50.595652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 01:36:50.596126 ==
887 01:36:50.608208 TX Vref=22, minBit 0, minWin=27, winSum=444
888 01:36:50.611231 TX Vref=24, minBit 3, minWin=27, winSum=447
889 01:36:50.614721 TX Vref=26, minBit 1, minWin=28, winSum=452
890 01:36:50.618436 TX Vref=28, minBit 3, minWin=28, winSum=456
891 01:36:50.621479 TX Vref=30, minBit 0, minWin=28, winSum=456
892 01:36:50.628163 TX Vref=32, minBit 0, minWin=28, winSum=453
893 01:36:50.631454 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 28
894 01:36:50.632025
895 01:36:50.634953 Final TX Range 1 Vref 28
896 01:36:50.635525
897 01:36:50.635895 ==
898 01:36:50.638594 Dram Type= 6, Freq= 0, CH_0, rank 0
899 01:36:50.641837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 01:36:50.642313 ==
901 01:36:50.642746
902 01:36:50.643096
903 01:36:50.645717 TX Vref Scan disable
904 01:36:50.648570 == TX Byte 0 ==
905 01:36:50.652121 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 01:36:50.655653 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 01:36:50.658848 == TX Byte 1 ==
908 01:36:50.661837 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
909 01:36:50.665453 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
910 01:36:50.666043
911 01:36:50.668707 [DATLAT]
912 01:36:50.669194 Freq=800, CH0 RK0
913 01:36:50.669724
914 01:36:50.672163 DATLAT Default: 0xa
915 01:36:50.672756 0, 0xFFFF, sum = 0
916 01:36:50.675387 1, 0xFFFF, sum = 0
917 01:36:50.675882 2, 0xFFFF, sum = 0
918 01:36:50.678488 3, 0xFFFF, sum = 0
919 01:36:50.678980 4, 0xFFFF, sum = 0
920 01:36:50.681934 5, 0xFFFF, sum = 0
921 01:36:50.682425 6, 0xFFFF, sum = 0
922 01:36:50.685389 7, 0xFFFF, sum = 0
923 01:36:50.685884 8, 0x0, sum = 1
924 01:36:50.688816 9, 0x0, sum = 2
925 01:36:50.689485 10, 0x0, sum = 3
926 01:36:50.692100 11, 0x0, sum = 4
927 01:36:50.692602 best_step = 9
928 01:36:50.693083
929 01:36:50.693606 ==
930 01:36:50.695206 Dram Type= 6, Freq= 0, CH_0, rank 0
931 01:36:50.698623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 01:36:50.699111 ==
933 01:36:50.701968 RX Vref Scan: 1
934 01:36:50.702550
935 01:36:50.705128 Set Vref Range= 32 -> 127
936 01:36:50.705649
937 01:36:50.706235 RX Vref 32 -> 127, step: 1
938 01:36:50.708452
939 01:36:50.708934 RX Delay -111 -> 252, step: 8
940 01:36:50.709535
941 01:36:50.711874 Set Vref, RX VrefLevel [Byte0]: 32
942 01:36:50.715094 [Byte1]: 32
943 01:36:50.718883
944 01:36:50.719363 Set Vref, RX VrefLevel [Byte0]: 33
945 01:36:50.722319 [Byte1]: 33
946 01:36:50.726880
947 01:36:50.727461 Set Vref, RX VrefLevel [Byte0]: 34
948 01:36:50.730036 [Byte1]: 34
949 01:36:50.734712
950 01:36:50.735292 Set Vref, RX VrefLevel [Byte0]: 35
951 01:36:50.737455 [Byte1]: 35
952 01:36:50.742104
953 01:36:50.742719 Set Vref, RX VrefLevel [Byte0]: 36
954 01:36:50.745075 [Byte1]: 36
955 01:36:50.749669
956 01:36:50.750247 Set Vref, RX VrefLevel [Byte0]: 37
957 01:36:50.752640 [Byte1]: 37
958 01:36:50.757238
959 01:36:50.757896 Set Vref, RX VrefLevel [Byte0]: 38
960 01:36:50.760700 [Byte1]: 38
961 01:36:50.764952
962 01:36:50.765578 Set Vref, RX VrefLevel [Byte0]: 39
963 01:36:50.767884 [Byte1]: 39
964 01:36:50.772550
965 01:36:50.773127 Set Vref, RX VrefLevel [Byte0]: 40
966 01:36:50.775812 [Byte1]: 40
967 01:36:50.779892
968 01:36:50.780462 Set Vref, RX VrefLevel [Byte0]: 41
969 01:36:50.783571 [Byte1]: 41
970 01:36:50.788028
971 01:36:50.788617 Set Vref, RX VrefLevel [Byte0]: 42
972 01:36:50.791170 [Byte1]: 42
973 01:36:50.795494
974 01:36:50.795973 Set Vref, RX VrefLevel [Byte0]: 43
975 01:36:50.798918 [Byte1]: 43
976 01:36:50.802804
977 01:36:50.803290 Set Vref, RX VrefLevel [Byte0]: 44
978 01:36:50.806464 [Byte1]: 44
979 01:36:50.810650
980 01:36:50.811130 Set Vref, RX VrefLevel [Byte0]: 45
981 01:36:50.813824 [Byte1]: 45
982 01:36:50.818126
983 01:36:50.818603 Set Vref, RX VrefLevel [Byte0]: 46
984 01:36:50.821719 [Byte1]: 46
985 01:36:50.825839
986 01:36:50.826321 Set Vref, RX VrefLevel [Byte0]: 47
987 01:36:50.829277 [Byte1]: 47
988 01:36:50.833906
989 01:36:50.834496 Set Vref, RX VrefLevel [Byte0]: 48
990 01:36:50.836740 [Byte1]: 48
991 01:36:50.841143
992 01:36:50.841789 Set Vref, RX VrefLevel [Byte0]: 49
993 01:36:50.844456 [Byte1]: 49
994 01:36:50.849102
995 01:36:50.849720 Set Vref, RX VrefLevel [Byte0]: 50
996 01:36:50.852688 [Byte1]: 50
997 01:36:50.856621
998 01:36:50.857188 Set Vref, RX VrefLevel [Byte0]: 51
999 01:36:50.860138 [Byte1]: 51
1000 01:36:50.864303
1001 01:36:50.864868 Set Vref, RX VrefLevel [Byte0]: 52
1002 01:36:50.867387 [Byte1]: 52
1003 01:36:50.871957
1004 01:36:50.872527 Set Vref, RX VrefLevel [Byte0]: 53
1005 01:36:50.875299 [Byte1]: 53
1006 01:36:50.879631
1007 01:36:50.880208 Set Vref, RX VrefLevel [Byte0]: 54
1008 01:36:50.882921 [Byte1]: 54
1009 01:36:50.887302
1010 01:36:50.887868 Set Vref, RX VrefLevel [Byte0]: 55
1011 01:36:50.890283 [Byte1]: 55
1012 01:36:50.894827
1013 01:36:50.895398 Set Vref, RX VrefLevel [Byte0]: 56
1014 01:36:50.897871 [Byte1]: 56
1015 01:36:50.902432
1016 01:36:50.902894 Set Vref, RX VrefLevel [Byte0]: 57
1017 01:36:50.905515 [Byte1]: 57
1018 01:36:50.910294
1019 01:36:50.910762 Set Vref, RX VrefLevel [Byte0]: 58
1020 01:36:50.913570 [Byte1]: 58
1021 01:36:50.917849
1022 01:36:50.920962 Set Vref, RX VrefLevel [Byte0]: 59
1023 01:36:50.921584 [Byte1]: 59
1024 01:36:50.925655
1025 01:36:50.926290 Set Vref, RX VrefLevel [Byte0]: 60
1026 01:36:50.928785 [Byte1]: 60
1027 01:36:50.933283
1028 01:36:50.933772 Set Vref, RX VrefLevel [Byte0]: 61
1029 01:36:50.936523 [Byte1]: 61
1030 01:36:50.941276
1031 01:36:50.941881 Set Vref, RX VrefLevel [Byte0]: 62
1032 01:36:50.944561 [Byte1]: 62
1033 01:36:50.948414
1034 01:36:50.948960 Set Vref, RX VrefLevel [Byte0]: 63
1035 01:36:50.951625 [Byte1]: 63
1036 01:36:50.956082
1037 01:36:50.956651 Set Vref, RX VrefLevel [Byte0]: 64
1038 01:36:50.959267 [Byte1]: 64
1039 01:36:50.964120
1040 01:36:50.964664 Set Vref, RX VrefLevel [Byte0]: 65
1041 01:36:50.966849 [Byte1]: 65
1042 01:36:50.971117
1043 01:36:50.971570 Set Vref, RX VrefLevel [Byte0]: 66
1044 01:36:50.974515 [Byte1]: 66
1045 01:36:50.978841
1046 01:36:50.979386 Set Vref, RX VrefLevel [Byte0]: 67
1047 01:36:50.982011 [Byte1]: 67
1048 01:36:50.986695
1049 01:36:50.987269 Set Vref, RX VrefLevel [Byte0]: 68
1050 01:36:50.990064 [Byte1]: 68
1051 01:36:50.994360
1052 01:36:50.994859 Set Vref, RX VrefLevel [Byte0]: 69
1053 01:36:50.997279 [Byte1]: 69
1054 01:36:51.001897
1055 01:36:51.002444 Set Vref, RX VrefLevel [Byte0]: 70
1056 01:36:51.005206 [Byte1]: 70
1057 01:36:51.009334
1058 01:36:51.009835 Set Vref, RX VrefLevel [Byte0]: 71
1059 01:36:51.012683 [Byte1]: 71
1060 01:36:51.016984
1061 01:36:51.017477 Set Vref, RX VrefLevel [Byte0]: 72
1062 01:36:51.020319 [Byte1]: 72
1063 01:36:51.024912
1064 01:36:51.025423 Final RX Vref Byte 0 = 53 to rank0
1065 01:36:51.027833 Final RX Vref Byte 1 = 55 to rank0
1066 01:36:51.031663 Final RX Vref Byte 0 = 53 to rank1
1067 01:36:51.035044 Final RX Vref Byte 1 = 55 to rank1==
1068 01:36:51.038327 Dram Type= 6, Freq= 0, CH_0, rank 0
1069 01:36:51.044974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1070 01:36:51.045587 ==
1071 01:36:51.045962 DQS Delay:
1072 01:36:51.046335 DQS0 = 0, DQS1 = 0
1073 01:36:51.048137 DQM Delay:
1074 01:36:51.048717 DQM0 = 83, DQM1 = 73
1075 01:36:51.051510 DQ Delay:
1076 01:36:51.054565 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1077 01:36:51.055024 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1078 01:36:51.058257 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1079 01:36:51.061549 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1080 01:36:51.064922
1081 01:36:51.065519
1082 01:36:51.071670 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1083 01:36:51.074917 CH0 RK0: MR19=606, MR18=3131
1084 01:36:51.081450 CH0_RK0: MR19=0x606, MR18=0x3131, DQSOSC=397, MR23=63, INC=93, DEC=62
1085 01:36:51.081987
1086 01:36:51.084978 ----->DramcWriteLeveling(PI) begin...
1087 01:36:51.085592 ==
1088 01:36:51.088192 Dram Type= 6, Freq= 0, CH_0, rank 1
1089 01:36:51.091392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1090 01:36:51.091857 ==
1091 01:36:51.094827 Write leveling (Byte 0): 29 => 29
1092 01:36:51.097812 Write leveling (Byte 1): 27 => 27
1093 01:36:51.101663 DramcWriteLeveling(PI) end<-----
1094 01:36:51.102235
1095 01:36:51.102619 ==
1096 01:36:51.104977 Dram Type= 6, Freq= 0, CH_0, rank 1
1097 01:36:51.108200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1098 01:36:51.108755 ==
1099 01:36:51.111403 [Gating] SW mode calibration
1100 01:36:51.118035 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1101 01:36:51.124596 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1102 01:36:51.128042 0 6 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
1103 01:36:51.131474 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1104 01:36:51.137949 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1105 01:36:51.141528 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1106 01:36:51.145085 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1107 01:36:51.151626 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 01:36:51.154517 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 01:36:51.157884 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 01:36:51.164791 0 7 0 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 0)
1111 01:36:51.168326 0 7 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1112 01:36:51.171203 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1113 01:36:51.178032 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1114 01:36:51.181204 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1115 01:36:51.184988 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 01:36:51.188175 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 01:36:51.194486 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 01:36:51.198101 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 01:36:51.201340 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1120 01:36:51.208075 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1121 01:36:51.211799 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1122 01:36:51.214628 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1123 01:36:51.221226 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 01:36:51.224579 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 01:36:51.227725 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 01:36:51.234666 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 01:36:51.238004 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 01:36:51.241393 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 01:36:51.247960 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 01:36:51.251187 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 01:36:51.254156 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 01:36:51.261226 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 01:36:51.264182 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 01:36:51.267766 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1135 01:36:51.274560 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1136 01:36:51.275126 Total UI for P1: 0, mck2ui 16
1137 01:36:51.280840 best dqsien dly found for B0: ( 0, 10, 0)
1138 01:36:51.281349 Total UI for P1: 0, mck2ui 16
1139 01:36:51.287636 best dqsien dly found for B1: ( 0, 10, 0)
1140 01:36:51.290900 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1141 01:36:51.294028 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1142 01:36:51.294491
1143 01:36:51.297483 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1144 01:36:51.300975 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1145 01:36:51.304332 [Gating] SW calibration Done
1146 01:36:51.304930 ==
1147 01:36:51.307552 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 01:36:51.310787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1149 01:36:51.311271 ==
1150 01:36:51.313867 RX Vref Scan: 0
1151 01:36:51.314339
1152 01:36:51.314817 RX Vref 0 -> 0, step: 1
1153 01:36:51.315265
1154 01:36:51.316972 RX Delay -130 -> 252, step: 16
1155 01:36:51.360306 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1156 01:36:51.361495 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1157 01:36:51.361943 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1158 01:36:51.362407 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1159 01:36:51.362851 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1160 01:36:51.363286 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1161 01:36:51.363854 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1162 01:36:51.364296 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1163 01:36:51.364725 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1164 01:36:51.365143 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1165 01:36:51.365615 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1166 01:36:51.366143 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1167 01:36:51.371142 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1168 01:36:51.374685 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1169 01:36:51.378096 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1170 01:36:51.381261 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1171 01:36:51.381888 ==
1172 01:36:51.385050 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 01:36:51.391408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1174 01:36:51.391985 ==
1175 01:36:51.392473 DQS Delay:
1176 01:36:51.394546 DQS0 = 0, DQS1 = 0
1177 01:36:51.395020 DQM Delay:
1178 01:36:51.395507 DQM0 = 86, DQM1 = 73
1179 01:36:51.397828 DQ Delay:
1180 01:36:51.401453 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1181 01:36:51.404833 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1182 01:36:51.408068 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1183 01:36:51.411441 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1184 01:36:51.411921
1185 01:36:51.412427
1186 01:36:51.412878 ==
1187 01:36:51.414726 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 01:36:51.418103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1189 01:36:51.418649 ==
1190 01:36:51.419126
1191 01:36:51.419573
1192 01:36:51.421166 TX Vref Scan disable
1193 01:36:51.421697 == TX Byte 0 ==
1194 01:36:51.428142 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1195 01:36:51.431438 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1196 01:36:51.431998 == TX Byte 1 ==
1197 01:36:51.438267 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1198 01:36:51.441375 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1199 01:36:51.441908 ==
1200 01:36:51.444697 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 01:36:51.447649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1202 01:36:51.448108 ==
1203 01:36:51.461772 TX Vref=22, minBit 0, minWin=27, winSum=441
1204 01:36:51.465384 TX Vref=24, minBit 6, minWin=27, winSum=448
1205 01:36:51.468501 TX Vref=26, minBit 0, minWin=28, winSum=453
1206 01:36:51.471889 TX Vref=28, minBit 2, minWin=28, winSum=457
1207 01:36:51.475435 TX Vref=30, minBit 2, minWin=28, winSum=459
1208 01:36:51.478453 TX Vref=32, minBit 0, minWin=28, winSum=456
1209 01:36:51.485199 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1210 01:36:51.485822
1211 01:36:51.488802 Final TX Range 1 Vref 30
1212 01:36:51.489450
1213 01:36:51.489939 ==
1214 01:36:51.493041 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 01:36:51.496209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1216 01:36:51.496684 ==
1217 01:36:51.497163
1218 01:36:51.497645
1219 01:36:51.499544 TX Vref Scan disable
1220 01:36:51.503205 == TX Byte 0 ==
1221 01:36:51.506625 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1222 01:36:51.510066 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1223 01:36:51.510541 == TX Byte 1 ==
1224 01:36:51.517125 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1225 01:36:51.520681 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1226 01:36:51.521143
1227 01:36:51.521554 [DATLAT]
1228 01:36:51.523928 Freq=800, CH0 RK1
1229 01:36:51.524385
1230 01:36:51.524749 DATLAT Default: 0x9
1231 01:36:51.527433 0, 0xFFFF, sum = 0
1232 01:36:51.527898 1, 0xFFFF, sum = 0
1233 01:36:51.531054 2, 0xFFFF, sum = 0
1234 01:36:51.531622 3, 0xFFFF, sum = 0
1235 01:36:51.534180 4, 0xFFFF, sum = 0
1236 01:36:51.534647 5, 0xFFFF, sum = 0
1237 01:36:51.537358 6, 0xFFFF, sum = 0
1238 01:36:51.537826 7, 0xFFFF, sum = 0
1239 01:36:51.540959 8, 0x0, sum = 1
1240 01:36:51.541464 9, 0x0, sum = 2
1241 01:36:51.544156 10, 0x0, sum = 3
1242 01:36:51.544639 11, 0x0, sum = 4
1243 01:36:51.545140 best_step = 9
1244 01:36:51.547564
1245 01:36:51.548136 ==
1246 01:36:51.550588 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 01:36:51.554132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1248 01:36:51.554649 ==
1249 01:36:51.555150 RX Vref Scan: 0
1250 01:36:51.555601
1251 01:36:51.557361 RX Vref 0 -> 0, step: 1
1252 01:36:51.557834
1253 01:36:51.560696 RX Delay -111 -> 252, step: 8
1254 01:36:51.564101 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1255 01:36:51.570599 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1256 01:36:51.573796 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1257 01:36:51.577595 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1258 01:36:51.580596 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1259 01:36:51.583911 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1260 01:36:51.590903 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1261 01:36:51.593996 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1262 01:36:51.597249 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1263 01:36:51.600526 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1264 01:36:51.603919 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1265 01:36:51.610583 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1266 01:36:51.613872 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1267 01:36:51.617155 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1268 01:36:51.620766 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1269 01:36:51.627452 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1270 01:36:51.628015 ==
1271 01:36:51.630369 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 01:36:51.633695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1273 01:36:51.634157 ==
1274 01:36:51.634517 DQS Delay:
1275 01:36:51.637090 DQS0 = 0, DQS1 = 0
1276 01:36:51.637598 DQM Delay:
1277 01:36:51.640461 DQM0 = 86, DQM1 = 73
1278 01:36:51.640916 DQ Delay:
1279 01:36:51.643620 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1280 01:36:51.647492 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1281 01:36:51.650542 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1282 01:36:51.653892 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1283 01:36:51.654356
1284 01:36:51.654714
1285 01:36:51.660499 [DQSOSCAuto] RK1, (LSB)MR18= 0x4747, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1286 01:36:51.664051 CH0 RK1: MR19=606, MR18=4747
1287 01:36:51.670271 CH0_RK1: MR19=0x606, MR18=0x4747, DQSOSC=392, MR23=63, INC=96, DEC=64
1288 01:36:51.673821 [RxdqsGatingPostProcess] freq 800
1289 01:36:51.677216 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1290 01:36:51.680635 Pre-setting of DQS Precalculation
1291 01:36:51.687184 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1292 01:36:51.687750 ==
1293 01:36:51.690118 Dram Type= 6, Freq= 0, CH_1, rank 0
1294 01:36:51.693483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1295 01:36:51.693937 ==
1296 01:36:51.700386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1297 01:36:51.706673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1298 01:36:51.714417 [CA 0] Center 36 (6~67) winsize 62
1299 01:36:51.717532 [CA 1] Center 36 (6~67) winsize 62
1300 01:36:51.720850 [CA 2] Center 34 (4~65) winsize 62
1301 01:36:51.724205 [CA 3] Center 34 (4~65) winsize 62
1302 01:36:51.727549 [CA 4] Center 33 (2~64) winsize 63
1303 01:36:51.730682 [CA 5] Center 33 (3~64) winsize 62
1304 01:36:51.730918
1305 01:36:51.734724 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1306 01:36:51.735290
1307 01:36:51.738103 [CATrainingPosCal] consider 1 rank data
1308 01:36:51.741104 u2DelayCellTimex100 = 270/100 ps
1309 01:36:51.744556 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1310 01:36:51.748131 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1311 01:36:51.754633 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1312 01:36:51.757671 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1313 01:36:51.761270 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1314 01:36:51.764366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1315 01:36:51.764892
1316 01:36:51.767604 CA PerBit enable=1, Macro0, CA PI delay=33
1317 01:36:51.768115
1318 01:36:51.771131 [CBTSetCACLKResult] CA Dly = 33
1319 01:36:51.771588 CS Dly: 4 (0~35)
1320 01:36:51.771945 ==
1321 01:36:51.774607 Dram Type= 6, Freq= 0, CH_1, rank 1
1322 01:36:51.781003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1323 01:36:51.781612 ==
1324 01:36:51.784431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1325 01:36:51.791278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1326 01:36:51.800689 [CA 0] Center 36 (6~67) winsize 62
1327 01:36:51.803613 [CA 1] Center 36 (5~67) winsize 63
1328 01:36:51.807247 [CA 2] Center 34 (4~65) winsize 62
1329 01:36:51.810232 [CA 3] Center 34 (4~64) winsize 61
1330 01:36:51.813268 [CA 4] Center 33 (3~63) winsize 61
1331 01:36:51.817357 [CA 5] Center 32 (2~63) winsize 62
1332 01:36:51.817922
1333 01:36:51.820017 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1334 01:36:51.820467
1335 01:36:51.823417 [CATrainingPosCal] consider 2 rank data
1336 01:36:51.826860 u2DelayCellTimex100 = 270/100 ps
1337 01:36:51.829876 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1338 01:36:51.836645 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1339 01:36:51.839988 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1340 01:36:51.843457 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1341 01:36:51.846728 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1342 01:36:51.850154 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1343 01:36:51.850714
1344 01:36:51.853423 CA PerBit enable=1, Macro0, CA PI delay=33
1345 01:36:51.853989
1346 01:36:51.856641 [CBTSetCACLKResult] CA Dly = 33
1347 01:36:51.857203 CS Dly: 4 (0~35)
1348 01:36:51.859888
1349 01:36:51.863209 ----->DramcWriteLeveling(PI) begin...
1350 01:36:51.863674 ==
1351 01:36:51.866382 Dram Type= 6, Freq= 0, CH_1, rank 0
1352 01:36:51.869768 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1353 01:36:51.870230 ==
1354 01:36:51.873539 Write leveling (Byte 0): 24 => 24
1355 01:36:51.876719 Write leveling (Byte 1): 22 => 22
1356 01:36:51.880019 DramcWriteLeveling(PI) end<-----
1357 01:36:51.880581
1358 01:36:51.880943 ==
1359 01:36:51.883292 Dram Type= 6, Freq= 0, CH_1, rank 0
1360 01:36:51.886735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1361 01:36:51.887301 ==
1362 01:36:51.889891 [Gating] SW mode calibration
1363 01:36:51.896362 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1364 01:36:51.903050 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1365 01:36:51.906317 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
1366 01:36:51.910001 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1367 01:36:51.916545 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1368 01:36:51.919947 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1369 01:36:51.923166 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1370 01:36:51.926435 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 01:36:51.933022 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 01:36:51.936500 0 6 28 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
1373 01:36:51.939700 0 7 0 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
1374 01:36:51.946527 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1375 01:36:51.950060 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1376 01:36:51.953233 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1377 01:36:51.959564 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1378 01:36:51.962969 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1379 01:36:51.966457 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 01:36:51.973263 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 01:36:51.976142 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1382 01:36:51.979803 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1383 01:36:51.986298 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1384 01:36:51.989742 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1385 01:36:51.992941 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 01:36:51.999564 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 01:36:52.003156 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 01:36:52.006268 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 01:36:52.012933 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 01:36:52.016292 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 01:36:52.019859 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 01:36:52.026435 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 01:36:52.029747 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 01:36:52.033252 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 01:36:52.036745 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 01:36:52.042853 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1397 01:36:52.046259 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1398 01:36:52.049736 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1399 01:36:52.053018 Total UI for P1: 0, mck2ui 16
1400 01:36:52.056432 best dqsien dly found for B0: ( 0, 9, 30)
1401 01:36:52.059419 Total UI for P1: 0, mck2ui 16
1402 01:36:52.062806 best dqsien dly found for B1: ( 0, 10, 0)
1403 01:36:52.066064 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1404 01:36:52.069949 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1405 01:36:52.070514
1406 01:36:52.076174 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1407 01:36:52.079568 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1408 01:36:52.082768 [Gating] SW calibration Done
1409 01:36:52.083271 ==
1410 01:36:52.086367 Dram Type= 6, Freq= 0, CH_1, rank 0
1411 01:36:52.090155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1412 01:36:52.090718 ==
1413 01:36:52.091081 RX Vref Scan: 0
1414 01:36:52.091421
1415 01:36:52.093187 RX Vref 0 -> 0, step: 1
1416 01:36:52.093795
1417 01:36:52.096428 RX Delay -130 -> 252, step: 16
1418 01:36:52.099686 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1419 01:36:52.102689 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1420 01:36:52.109636 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1421 01:36:52.112846 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1422 01:36:52.116098 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1423 01:36:52.119654 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1424 01:36:52.122842 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1425 01:36:52.129659 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1426 01:36:52.132887 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1427 01:36:52.136022 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1428 01:36:52.139559 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1429 01:36:52.143031 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1430 01:36:52.149399 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1431 01:36:52.153517 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1432 01:36:52.156885 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1433 01:36:52.160268 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1434 01:36:52.160734 ==
1435 01:36:52.164182 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 01:36:52.167758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1437 01:36:52.168226 ==
1438 01:36:52.168590 DQS Delay:
1439 01:36:52.171433 DQS0 = 0, DQS1 = 0
1440 01:36:52.171893 DQM Delay:
1441 01:36:52.175579 DQM0 = 82, DQM1 = 74
1442 01:36:52.176143 DQ Delay:
1443 01:36:52.178780 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1444 01:36:52.182613 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1445 01:36:52.183080 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1446 01:36:52.186521 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1447 01:36:52.186982
1448 01:36:52.187344
1449 01:36:52.190808 ==
1450 01:36:52.191409 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 01:36:52.196763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1452 01:36:52.197415 ==
1453 01:36:52.197968
1454 01:36:52.198317
1455 01:36:52.198644 TX Vref Scan disable
1456 01:36:52.200678 == TX Byte 0 ==
1457 01:36:52.204150 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1458 01:36:52.210627 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1459 01:36:52.211189 == TX Byte 1 ==
1460 01:36:52.213911 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1461 01:36:52.220820 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1462 01:36:52.221433 ==
1463 01:36:52.223860 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 01:36:52.227283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1465 01:36:52.227740 ==
1466 01:36:52.239901 TX Vref=22, minBit 0, minWin=27, winSum=450
1467 01:36:52.243198 TX Vref=24, minBit 0, minWin=28, winSum=456
1468 01:36:52.246631 TX Vref=26, minBit 0, minWin=28, winSum=460
1469 01:36:52.249660 TX Vref=28, minBit 3, minWin=28, winSum=461
1470 01:36:52.253133 TX Vref=30, minBit 3, minWin=28, winSum=463
1471 01:36:52.256174 TX Vref=32, minBit 3, minWin=28, winSum=464
1472 01:36:52.263110 [TxChooseVref] Worse bit 3, Min win 28, Win sum 464, Final Vref 32
1473 01:36:52.263710
1474 01:36:52.266425 Final TX Range 1 Vref 32
1475 01:36:52.266881
1476 01:36:52.267234 ==
1477 01:36:52.269848 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 01:36:52.272846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1479 01:36:52.273346 ==
1480 01:36:52.276357
1481 01:36:52.276912
1482 01:36:52.277275 TX Vref Scan disable
1483 01:36:52.279746 == TX Byte 0 ==
1484 01:36:52.282900 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1485 01:36:52.286538 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1486 01:36:52.289876 == TX Byte 1 ==
1487 01:36:52.293108 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1488 01:36:52.296196 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1489 01:36:52.299423
1490 01:36:52.299953 [DATLAT]
1491 01:36:52.300324 Freq=800, CH1 RK0
1492 01:36:52.300667
1493 01:36:52.303058 DATLAT Default: 0xa
1494 01:36:52.303621 0, 0xFFFF, sum = 0
1495 01:36:52.306256 1, 0xFFFF, sum = 0
1496 01:36:52.306829 2, 0xFFFF, sum = 0
1497 01:36:52.309669 3, 0xFFFF, sum = 0
1498 01:36:52.310132 4, 0xFFFF, sum = 0
1499 01:36:52.312822 5, 0xFFFF, sum = 0
1500 01:36:52.316276 6, 0xFFFF, sum = 0
1501 01:36:52.316843 7, 0xFFFF, sum = 0
1502 01:36:52.317219 8, 0x0, sum = 1
1503 01:36:52.319842 9, 0x0, sum = 2
1504 01:36:52.320410 10, 0x0, sum = 3
1505 01:36:52.322816 11, 0x0, sum = 4
1506 01:36:52.323283 best_step = 9
1507 01:36:52.323643
1508 01:36:52.323977 ==
1509 01:36:52.326700 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 01:36:52.333160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1511 01:36:52.333781 ==
1512 01:36:52.334156 RX Vref Scan: 1
1513 01:36:52.334492
1514 01:36:52.336235 Set Vref Range= 32 -> 127
1515 01:36:52.336698
1516 01:36:52.339842 RX Vref 32 -> 127, step: 1
1517 01:36:52.340409
1518 01:36:52.343177 RX Delay -111 -> 252, step: 8
1519 01:36:52.343742
1520 01:36:52.346157 Set Vref, RX VrefLevel [Byte0]: 32
1521 01:36:52.349659 [Byte1]: 32
1522 01:36:52.350226
1523 01:36:52.352817 Set Vref, RX VrefLevel [Byte0]: 33
1524 01:36:52.356414 [Byte1]: 33
1525 01:36:52.356984
1526 01:36:52.359579 Set Vref, RX VrefLevel [Byte0]: 34
1527 01:36:52.362720 [Byte1]: 34
1528 01:36:52.363186
1529 01:36:52.366262 Set Vref, RX VrefLevel [Byte0]: 35
1530 01:36:52.369586 [Byte1]: 35
1531 01:36:52.373727
1532 01:36:52.374306 Set Vref, RX VrefLevel [Byte0]: 36
1533 01:36:52.377020 [Byte1]: 36
1534 01:36:52.381147
1535 01:36:52.381755 Set Vref, RX VrefLevel [Byte0]: 37
1536 01:36:52.384398 [Byte1]: 37
1537 01:36:52.389020
1538 01:36:52.389630 Set Vref, RX VrefLevel [Byte0]: 38
1539 01:36:52.392373 [Byte1]: 38
1540 01:36:52.396846
1541 01:36:52.397541 Set Vref, RX VrefLevel [Byte0]: 39
1542 01:36:52.399793 [Byte1]: 39
1543 01:36:52.404374
1544 01:36:52.404943 Set Vref, RX VrefLevel [Byte0]: 40
1545 01:36:52.407174 [Byte1]: 40
1546 01:36:52.411824
1547 01:36:52.412380 Set Vref, RX VrefLevel [Byte0]: 41
1548 01:36:52.414756 [Byte1]: 41
1549 01:36:52.419488
1550 01:36:52.420039 Set Vref, RX VrefLevel [Byte0]: 42
1551 01:36:52.422698 [Byte1]: 42
1552 01:36:52.427222
1553 01:36:52.427776 Set Vref, RX VrefLevel [Byte0]: 43
1554 01:36:52.430608 [Byte1]: 43
1555 01:36:52.434841
1556 01:36:52.435399 Set Vref, RX VrefLevel [Byte0]: 44
1557 01:36:52.437860 [Byte1]: 44
1558 01:36:52.442665
1559 01:36:52.443259 Set Vref, RX VrefLevel [Byte0]: 45
1560 01:36:52.445474 [Byte1]: 45
1561 01:36:52.449988
1562 01:36:52.450540 Set Vref, RX VrefLevel [Byte0]: 46
1563 01:36:52.453621 [Byte1]: 46
1564 01:36:52.457803
1565 01:36:52.458354 Set Vref, RX VrefLevel [Byte0]: 47
1566 01:36:52.461440 [Byte1]: 47
1567 01:36:52.465187
1568 01:36:52.465830 Set Vref, RX VrefLevel [Byte0]: 48
1569 01:36:52.468690 [Byte1]: 48
1570 01:36:52.472936
1571 01:36:52.473561 Set Vref, RX VrefLevel [Byte0]: 49
1572 01:36:52.476305 [Byte1]: 49
1573 01:36:52.480946
1574 01:36:52.481545 Set Vref, RX VrefLevel [Byte0]: 50
1575 01:36:52.487192 [Byte1]: 50
1576 01:36:52.487749
1577 01:36:52.490731 Set Vref, RX VrefLevel [Byte0]: 51
1578 01:36:52.493870 [Byte1]: 51
1579 01:36:52.494331
1580 01:36:52.497130 Set Vref, RX VrefLevel [Byte0]: 52
1581 01:36:52.500605 [Byte1]: 52
1582 01:36:52.501084
1583 01:36:52.503811 Set Vref, RX VrefLevel [Byte0]: 53
1584 01:36:52.507127 [Byte1]: 53
1585 01:36:52.511301
1586 01:36:52.511855 Set Vref, RX VrefLevel [Byte0]: 54
1587 01:36:52.514459 [Byte1]: 54
1588 01:36:52.518820
1589 01:36:52.519310 Set Vref, RX VrefLevel [Byte0]: 55
1590 01:36:52.522090 [Byte1]: 55
1591 01:36:52.526583
1592 01:36:52.527149 Set Vref, RX VrefLevel [Byte0]: 56
1593 01:36:52.529595 [Byte1]: 56
1594 01:36:52.533856
1595 01:36:52.534335 Set Vref, RX VrefLevel [Byte0]: 57
1596 01:36:52.537509 [Byte1]: 57
1597 01:36:52.541856
1598 01:36:52.542431 Set Vref, RX VrefLevel [Byte0]: 58
1599 01:36:52.545047 [Byte1]: 58
1600 01:36:52.549688
1601 01:36:52.550256 Set Vref, RX VrefLevel [Byte0]: 59
1602 01:36:52.552891 [Byte1]: 59
1603 01:36:52.557375
1604 01:36:52.557945 Set Vref, RX VrefLevel [Byte0]: 60
1605 01:36:52.560150 [Byte1]: 60
1606 01:36:52.565034
1607 01:36:52.565698 Set Vref, RX VrefLevel [Byte0]: 61
1608 01:36:52.567988 [Byte1]: 61
1609 01:36:52.572466
1610 01:36:52.573034 Set Vref, RX VrefLevel [Byte0]: 62
1611 01:36:52.575669 [Byte1]: 62
1612 01:36:52.580026
1613 01:36:52.580597 Set Vref, RX VrefLevel [Byte0]: 63
1614 01:36:52.583032 [Byte1]: 63
1615 01:36:52.587778
1616 01:36:52.588344 Set Vref, RX VrefLevel [Byte0]: 64
1617 01:36:52.590691 [Byte1]: 64
1618 01:36:52.595414
1619 01:36:52.595983 Set Vref, RX VrefLevel [Byte0]: 65
1620 01:36:52.598348 [Byte1]: 65
1621 01:36:52.602707
1622 01:36:52.603196 Set Vref, RX VrefLevel [Byte0]: 66
1623 01:36:52.606105 [Byte1]: 66
1624 01:36:52.610480
1625 01:36:52.610954 Set Vref, RX VrefLevel [Byte0]: 67
1626 01:36:52.613755 [Byte1]: 67
1627 01:36:52.618059
1628 01:36:52.618551 Set Vref, RX VrefLevel [Byte0]: 68
1629 01:36:52.622011 [Byte1]: 68
1630 01:36:52.625828
1631 01:36:52.626401 Set Vref, RX VrefLevel [Byte0]: 69
1632 01:36:52.629079 [Byte1]: 69
1633 01:36:52.633511
1634 01:36:52.633983 Set Vref, RX VrefLevel [Byte0]: 70
1635 01:36:52.637037 [Byte1]: 70
1636 01:36:52.641104
1637 01:36:52.641726 Set Vref, RX VrefLevel [Byte0]: 71
1638 01:36:52.644374 [Byte1]: 71
1639 01:36:52.648790
1640 01:36:52.652145 Set Vref, RX VrefLevel [Byte0]: 72
1641 01:36:52.652722 [Byte1]: 72
1642 01:36:52.656969
1643 01:36:52.657635 Set Vref, RX VrefLevel [Byte0]: 73
1644 01:36:52.659573 [Byte1]: 73
1645 01:36:52.664181
1646 01:36:52.664748 Set Vref, RX VrefLevel [Byte0]: 74
1647 01:36:52.667300 [Byte1]: 74
1648 01:36:52.671843
1649 01:36:52.672417 Set Vref, RX VrefLevel [Byte0]: 75
1650 01:36:52.675094 [Byte1]: 75
1651 01:36:52.679411
1652 01:36:52.679996 Set Vref, RX VrefLevel [Byte0]: 76
1653 01:36:52.682892 [Byte1]: 76
1654 01:36:52.687218
1655 01:36:52.687787 Set Vref, RX VrefLevel [Byte0]: 77
1656 01:36:52.690184 [Byte1]: 77
1657 01:36:52.694778
1658 01:36:52.695340 Final RX Vref Byte 0 = 59 to rank0
1659 01:36:52.698049 Final RX Vref Byte 1 = 55 to rank0
1660 01:36:52.701342 Final RX Vref Byte 0 = 59 to rank1
1661 01:36:52.704663 Final RX Vref Byte 1 = 55 to rank1==
1662 01:36:52.707877 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 01:36:52.714616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1664 01:36:52.715121 ==
1665 01:36:52.715586 DQS Delay:
1666 01:36:52.715934 DQS0 = 0, DQS1 = 0
1667 01:36:52.717925 DQM Delay:
1668 01:36:52.718386 DQM0 = 80, DQM1 = 71
1669 01:36:52.721219 DQ Delay:
1670 01:36:52.724455 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1671 01:36:52.724911 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1672 01:36:52.727915 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1673 01:36:52.735307 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1674 01:36:52.735859
1675 01:36:52.736432
1676 01:36:52.741951 [DQSOSCAuto] RK0, (LSB)MR18= 0x5353, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1677 01:36:52.745276 CH1 RK0: MR19=606, MR18=5353
1678 01:36:52.748639 CH1_RK0: MR19=0x606, MR18=0x5353, DQSOSC=389, MR23=63, INC=97, DEC=65
1679 01:36:52.751577
1680 01:36:52.755147 ----->DramcWriteLeveling(PI) begin...
1681 01:36:52.755710 ==
1682 01:36:52.758322 Dram Type= 6, Freq= 0, CH_1, rank 1
1683 01:36:52.762006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1684 01:36:52.762580 ==
1685 01:36:52.765215 Write leveling (Byte 0): 26 => 26
1686 01:36:52.768630 Write leveling (Byte 1): 25 => 25
1687 01:36:52.771786 DramcWriteLeveling(PI) end<-----
1688 01:36:52.772252
1689 01:36:52.772649 ==
1690 01:36:52.774882 Dram Type= 6, Freq= 0, CH_1, rank 1
1691 01:36:52.778274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1692 01:36:52.778739 ==
1693 01:36:52.781689 [Gating] SW mode calibration
1694 01:36:52.788229 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1695 01:36:52.795354 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1696 01:36:52.798457 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1697 01:36:52.801569 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 01:36:52.805526 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 01:36:52.811908 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 01:36:52.815475 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 01:36:52.818534 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 01:36:52.825139 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 01:36:52.828518 0 6 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
1704 01:36:52.831901 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1705 01:36:52.838643 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 01:36:52.841780 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 01:36:52.845035 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 01:36:52.851819 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 01:36:52.855164 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 01:36:52.858282 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 01:36:52.865255 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1712 01:36:52.868578 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1713 01:36:52.871806 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 01:36:52.878876 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 01:36:52.881893 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 01:36:52.884986 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 01:36:52.891621 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 01:36:52.895074 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 01:36:52.898244 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 01:36:52.904931 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 01:36:52.908441 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 01:36:52.911340 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 01:36:52.918122 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 01:36:52.921266 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 01:36:52.924891 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 01:36:52.931386 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 01:36:52.934624 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1728 01:36:52.938012 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1729 01:36:52.941382 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1730 01:36:52.944765 Total UI for P1: 0, mck2ui 16
1731 01:36:52.948143 best dqsien dly found for B0: ( 0, 9, 30)
1732 01:36:52.951430 Total UI for P1: 0, mck2ui 16
1733 01:36:52.954636 best dqsien dly found for B1: ( 0, 9, 30)
1734 01:36:52.957803 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1735 01:36:52.961392 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1736 01:36:52.964884
1737 01:36:52.967853 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1738 01:36:52.971489 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1739 01:36:52.974497 [Gating] SW calibration Done
1740 01:36:52.974972 ==
1741 01:36:52.978032 Dram Type= 6, Freq= 0, CH_1, rank 1
1742 01:36:52.981245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1743 01:36:52.981708 ==
1744 01:36:52.984843 RX Vref Scan: 0
1745 01:36:52.985261
1746 01:36:52.985626 RX Vref 0 -> 0, step: 1
1747 01:36:52.985930
1748 01:36:52.987990 RX Delay -130 -> 252, step: 16
1749 01:36:52.991107 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1750 01:36:52.994554 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1751 01:36:53.001260 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1752 01:36:53.004737 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1753 01:36:53.007751 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1754 01:36:53.011089 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1755 01:36:53.014474 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1756 01:36:53.021422 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1757 01:36:53.024780 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1758 01:36:53.028171 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1759 01:36:53.031303 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1760 01:36:53.034765 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1761 01:36:53.041329 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1762 01:36:53.044482 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1763 01:36:53.048118 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1764 01:36:53.051385 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1765 01:36:53.051900 ==
1766 01:36:53.054705 Dram Type= 6, Freq= 0, CH_1, rank 1
1767 01:36:53.061256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1768 01:36:53.061757 ==
1769 01:36:53.062086 DQS Delay:
1770 01:36:53.064567 DQS0 = 0, DQS1 = 0
1771 01:36:53.064976 DQM Delay:
1772 01:36:53.065335 DQM0 = 81, DQM1 = 70
1773 01:36:53.068074 DQ Delay:
1774 01:36:53.071238 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1775 01:36:53.074763 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1776 01:36:53.077980 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1777 01:36:53.080950 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1778 01:36:53.081436
1779 01:36:53.081774
1780 01:36:53.082072 ==
1781 01:36:53.084439 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 01:36:53.087710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1783 01:36:53.088125 ==
1784 01:36:53.088449
1785 01:36:53.088747
1786 01:36:53.091200 TX Vref Scan disable
1787 01:36:53.091705 == TX Byte 0 ==
1788 01:36:53.097686 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1789 01:36:53.100910 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1790 01:36:53.101469 == TX Byte 1 ==
1791 01:36:53.107487 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1792 01:36:53.110978 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1793 01:36:53.111501 ==
1794 01:36:53.114461 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 01:36:53.117525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1796 01:36:53.117961 ==
1797 01:36:53.132015 TX Vref=22, minBit 10, minWin=27, winSum=447
1798 01:36:53.135288 TX Vref=24, minBit 0, minWin=28, winSum=454
1799 01:36:53.138351 TX Vref=26, minBit 0, minWin=28, winSum=457
1800 01:36:53.141735 TX Vref=28, minBit 0, minWin=28, winSum=458
1801 01:36:53.145339 TX Vref=30, minBit 0, minWin=28, winSum=455
1802 01:36:53.151795 TX Vref=32, minBit 0, minWin=28, winSum=459
1803 01:36:53.155123 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 32
1804 01:36:53.155679
1805 01:36:53.158294 Final TX Range 1 Vref 32
1806 01:36:53.158877
1807 01:36:53.159238 ==
1808 01:36:53.161569 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 01:36:53.164696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1810 01:36:53.165150 ==
1811 01:36:53.167933
1812 01:36:53.168384
1813 01:36:53.168739 TX Vref Scan disable
1814 01:36:53.171544 == TX Byte 0 ==
1815 01:36:53.175145 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1816 01:36:53.181792 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1817 01:36:53.182352 == TX Byte 1 ==
1818 01:36:53.184846 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1819 01:36:53.191713 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1820 01:36:53.192274
1821 01:36:53.192633 [DATLAT]
1822 01:36:53.192962 Freq=800, CH1 RK1
1823 01:36:53.193278
1824 01:36:53.194806 DATLAT Default: 0x9
1825 01:36:53.195272 0, 0xFFFF, sum = 0
1826 01:36:53.198448 1, 0xFFFF, sum = 0
1827 01:36:53.198916 2, 0xFFFF, sum = 0
1828 01:36:53.201481 3, 0xFFFF, sum = 0
1829 01:36:53.204838 4, 0xFFFF, sum = 0
1830 01:36:53.205343 5, 0xFFFF, sum = 0
1831 01:36:53.208292 6, 0xFFFF, sum = 0
1832 01:36:53.208759 7, 0xFFFF, sum = 0
1833 01:36:53.209128 8, 0x0, sum = 1
1834 01:36:53.211748 9, 0x0, sum = 2
1835 01:36:53.212217 10, 0x0, sum = 3
1836 01:36:53.214732 11, 0x0, sum = 4
1837 01:36:53.215200 best_step = 9
1838 01:36:53.215577
1839 01:36:53.215913 ==
1840 01:36:53.218089 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 01:36:53.225014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1842 01:36:53.225527 ==
1843 01:36:53.225945 RX Vref Scan: 0
1844 01:36:53.226290
1845 01:36:53.228158 RX Vref 0 -> 0, step: 1
1846 01:36:53.228610
1847 01:36:53.231919 RX Delay -111 -> 252, step: 8
1848 01:36:53.235034 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1849 01:36:53.238745 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1850 01:36:53.245201 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1851 01:36:53.248514 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1852 01:36:53.251743 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1853 01:36:53.255573 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1854 01:36:53.258264 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1855 01:36:53.261764 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1856 01:36:53.268198 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1857 01:36:53.272060 iDelay=217, Bit 9, Center 60 (-63 ~ 184) 248
1858 01:36:53.275068 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1859 01:36:53.278581 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1860 01:36:53.281593 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1861 01:36:53.288659 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1862 01:36:53.291747 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1863 01:36:53.295048 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1864 01:36:53.295508 ==
1865 01:36:53.298503 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 01:36:53.301974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1867 01:36:53.304890 ==
1868 01:36:53.305383 DQS Delay:
1869 01:36:53.305753 DQS0 = 0, DQS1 = 0
1870 01:36:53.308129 DQM Delay:
1871 01:36:53.308587 DQM0 = 82, DQM1 = 72
1872 01:36:53.311588 DQ Delay:
1873 01:36:53.312046 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1874 01:36:53.315355 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1875 01:36:53.318247 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1876 01:36:53.321615 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1877 01:36:53.324814
1878 01:36:53.325386
1879 01:36:53.331583 [DQSOSCAuto] RK1, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1880 01:36:53.335130 CH1 RK1: MR19=606, MR18=3232
1881 01:36:53.341514 CH1_RK1: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1882 01:36:53.344738 [RxdqsGatingPostProcess] freq 800
1883 01:36:53.348189 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1884 01:36:53.351419 Pre-setting of DQS Precalculation
1885 01:36:53.355228 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1886 01:36:53.364616 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1887 01:36:53.371556 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1888 01:36:53.372122
1889 01:36:53.372491
1890 01:36:53.374820 [Calibration Summary] 1600 Mbps
1891 01:36:53.375375 CH 0, Rank 0
1892 01:36:53.378377 SW Impedance : PASS
1893 01:36:53.378933 DUTY Scan : NO K
1894 01:36:53.381999 ZQ Calibration : PASS
1895 01:36:53.384910 Jitter Meter : NO K
1896 01:36:53.385540 CBT Training : PASS
1897 01:36:53.388366 Write leveling : PASS
1898 01:36:53.391865 RX DQS gating : PASS
1899 01:36:53.392421 RX DQ/DQS(RDDQC) : PASS
1900 01:36:53.394651 TX DQ/DQS : PASS
1901 01:36:53.398048 RX DATLAT : PASS
1902 01:36:53.398470 RX DQ/DQS(Engine): PASS
1903 01:36:53.401548 TX OE : NO K
1904 01:36:53.402284 All Pass.
1905 01:36:53.402669
1906 01:36:53.404693 CH 0, Rank 1
1907 01:36:53.405156 SW Impedance : PASS
1908 01:36:53.408231 DUTY Scan : NO K
1909 01:36:53.411570 ZQ Calibration : PASS
1910 01:36:53.412127 Jitter Meter : NO K
1911 01:36:53.414533 CBT Training : PASS
1912 01:36:53.417976 Write leveling : PASS
1913 01:36:53.418439 RX DQS gating : PASS
1914 01:36:53.421171 RX DQ/DQS(RDDQC) : PASS
1915 01:36:53.421674 TX DQ/DQS : PASS
1916 01:36:53.424547 RX DATLAT : PASS
1917 01:36:53.428024 RX DQ/DQS(Engine): PASS
1918 01:36:53.428580 TX OE : NO K
1919 01:36:53.431429 All Pass.
1920 01:36:53.431994
1921 01:36:53.432363 CH 1, Rank 0
1922 01:36:53.434611 SW Impedance : PASS
1923 01:36:53.435166 DUTY Scan : NO K
1924 01:36:53.437878 ZQ Calibration : PASS
1925 01:36:53.441643 Jitter Meter : NO K
1926 01:36:53.442199 CBT Training : PASS
1927 01:36:53.444545 Write leveling : PASS
1928 01:36:53.447810 RX DQS gating : PASS
1929 01:36:53.448275 RX DQ/DQS(RDDQC) : PASS
1930 01:36:53.451274 TX DQ/DQS : PASS
1931 01:36:53.454950 RX DATLAT : PASS
1932 01:36:53.455518 RX DQ/DQS(Engine): PASS
1933 01:36:53.457798 TX OE : NO K
1934 01:36:53.458280 All Pass.
1935 01:36:53.458855
1936 01:36:53.461104 CH 1, Rank 1
1937 01:36:53.461720 SW Impedance : PASS
1938 01:36:53.464679 DUTY Scan : NO K
1939 01:36:53.467758 ZQ Calibration : PASS
1940 01:36:53.468215 Jitter Meter : NO K
1941 01:36:53.471344 CBT Training : PASS
1942 01:36:53.471916 Write leveling : PASS
1943 01:36:53.474422 RX DQS gating : PASS
1944 01:36:53.477854 RX DQ/DQS(RDDQC) : PASS
1945 01:36:53.478332 TX DQ/DQS : PASS
1946 01:36:53.481414 RX DATLAT : PASS
1947 01:36:53.484706 RX DQ/DQS(Engine): PASS
1948 01:36:53.485274 TX OE : NO K
1949 01:36:53.487884 All Pass.
1950 01:36:53.488433
1951 01:36:53.488798 DramC Write-DBI off
1952 01:36:53.491608 PER_BANK_REFRESH: Hybrid Mode
1953 01:36:53.492164 TX_TRACKING: ON
1954 01:36:53.494554 [GetDramInforAfterCalByMRR] Vendor 6.
1955 01:36:53.501225 [GetDramInforAfterCalByMRR] Revision 606.
1956 01:36:53.504252 [GetDramInforAfterCalByMRR] Revision 2 0.
1957 01:36:53.504860 MR0 0x3939
1958 01:36:53.505235 MR8 0x1111
1959 01:36:53.507856 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1960 01:36:53.511203
1961 01:36:53.511753 MR0 0x3939
1962 01:36:53.512123 MR8 0x1111
1963 01:36:53.514333 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1964 01:36:53.514800
1965 01:36:53.524390 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1966 01:36:53.527793 [FAST_K] Save calibration result to emmc
1967 01:36:53.531200 [FAST_K] Save calibration result to emmc
1968 01:36:53.534155 dram_init: config_dvfs: 1
1969 01:36:53.537565 dramc_set_vcore_voltage set vcore to 662500
1970 01:36:53.541222 Read voltage for 1200, 2
1971 01:36:53.541808 Vio18 = 0
1972 01:36:53.542175 Vcore = 662500
1973 01:36:53.544333 Vdram = 0
1974 01:36:53.544967 Vddq = 0
1975 01:36:53.545540 Vmddr = 0
1976 01:36:53.550788 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1977 01:36:53.554209 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1978 01:36:53.557711 MEM_TYPE=3, freq_sel=15
1979 01:36:53.560979 sv_algorithm_assistance_LP4_1600
1980 01:36:53.564755 ============ PULL DRAM RESETB DOWN ============
1981 01:36:53.567816 ========== PULL DRAM RESETB DOWN end =========
1982 01:36:53.574072 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1983 01:36:53.577815 ===================================
1984 01:36:53.581166 LPDDR4 DRAM CONFIGURATION
1985 01:36:53.581811 ===================================
1986 01:36:53.584279 EX_ROW_EN[0] = 0x0
1987 01:36:53.587313 EX_ROW_EN[1] = 0x0
1988 01:36:53.587786 LP4Y_EN = 0x0
1989 01:36:53.591057 WORK_FSP = 0x0
1990 01:36:53.591624 WL = 0x4
1991 01:36:53.593954 RL = 0x4
1992 01:36:53.594426 BL = 0x2
1993 01:36:53.597481 RPST = 0x0
1994 01:36:53.598048 RD_PRE = 0x0
1995 01:36:53.600766 WR_PRE = 0x1
1996 01:36:53.601240 WR_PST = 0x0
1997 01:36:53.604704 DBI_WR = 0x0
1998 01:36:53.605535 DBI_RD = 0x0
1999 01:36:53.607448 OTF = 0x1
2000 01:36:53.611105 ===================================
2001 01:36:53.614152 ===================================
2002 01:36:53.614626 ANA top config
2003 01:36:53.617675 ===================================
2004 01:36:53.620876 DLL_ASYNC_EN = 0
2005 01:36:53.624205 ALL_SLAVE_EN = 0
2006 01:36:53.627814 NEW_RANK_MODE = 1
2007 01:36:53.628387 DLL_IDLE_MODE = 1
2008 01:36:53.631209 LP45_APHY_COMB_EN = 1
2009 01:36:53.634166 TX_ODT_DIS = 1
2010 01:36:53.637772 NEW_8X_MODE = 1
2011 01:36:53.641153 ===================================
2012 01:36:53.644598 ===================================
2013 01:36:53.645168 data_rate = 2400
2014 01:36:53.647799 CKR = 1
2015 01:36:53.651515 DQ_P2S_RATIO = 8
2016 01:36:53.654773 ===================================
2017 01:36:53.657827 CA_P2S_RATIO = 8
2018 01:36:53.660808 DQ_CA_OPEN = 0
2019 01:36:53.664001 DQ_SEMI_OPEN = 0
2020 01:36:53.664478 CA_SEMI_OPEN = 0
2021 01:36:53.667505 CA_FULL_RATE = 0
2022 01:36:53.671099 DQ_CKDIV4_EN = 0
2023 01:36:53.674058 CA_CKDIV4_EN = 0
2024 01:36:53.677586 CA_PREDIV_EN = 0
2025 01:36:53.680653 PH8_DLY = 17
2026 01:36:53.684147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2027 01:36:53.684702 DQ_AAMCK_DIV = 4
2028 01:36:53.687206 CA_AAMCK_DIV = 4
2029 01:36:53.690471 CA_ADMCK_DIV = 4
2030 01:36:53.693872 DQ_TRACK_CA_EN = 0
2031 01:36:53.697334 CA_PICK = 1200
2032 01:36:53.700592 CA_MCKIO = 1200
2033 01:36:53.703675 MCKIO_SEMI = 0
2034 01:36:53.704149 PLL_FREQ = 2366
2035 01:36:53.707087 DQ_UI_PI_RATIO = 32
2036 01:36:53.710503 CA_UI_PI_RATIO = 0
2037 01:36:53.714013 ===================================
2038 01:36:53.717073 ===================================
2039 01:36:53.720643 memory_type:LPDDR4
2040 01:36:53.721205 GP_NUM : 10
2041 01:36:53.724011 SRAM_EN : 1
2042 01:36:53.727144 MD32_EN : 0
2043 01:36:53.730252 ===================================
2044 01:36:53.730728 [ANA_INIT] >>>>>>>>>>>>>>
2045 01:36:53.733878 <<<<<< [CONFIGURE PHASE]: ANA_TX
2046 01:36:53.737182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2047 01:36:53.740424 ===================================
2048 01:36:53.743819 data_rate = 2400,PCW = 0X5b00
2049 01:36:53.746987 ===================================
2050 01:36:53.750629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2051 01:36:53.757250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2052 01:36:53.760462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2053 01:36:53.767174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2054 01:36:53.770516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2055 01:36:53.773877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2056 01:36:53.774454 [ANA_INIT] flow start
2057 01:36:53.777854 [ANA_INIT] PLL >>>>>>>>
2058 01:36:53.780443 [ANA_INIT] PLL <<<<<<<<
2059 01:36:53.783543 [ANA_INIT] MIDPI >>>>>>>>
2060 01:36:53.784020 [ANA_INIT] MIDPI <<<<<<<<
2061 01:36:53.786939 [ANA_INIT] DLL >>>>>>>>
2062 01:36:53.790172 [ANA_INIT] DLL <<<<<<<<
2063 01:36:53.790641 [ANA_INIT] flow end
2064 01:36:53.793689 ============ LP4 DIFF to SE enter ============
2065 01:36:53.800102 ============ LP4 DIFF to SE exit ============
2066 01:36:53.800663 [ANA_INIT] <<<<<<<<<<<<<
2067 01:36:53.803677 [Flow] Enable top DCM control >>>>>
2068 01:36:53.807458 [Flow] Enable top DCM control <<<<<
2069 01:36:53.810048 Enable DLL master slave shuffle
2070 01:36:53.816843 ==============================================================
2071 01:36:53.817348 Gating Mode config
2072 01:36:53.823662 ==============================================================
2073 01:36:53.826674 Config description:
2074 01:36:53.837059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2075 01:36:53.843575 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2076 01:36:53.846646 SELPH_MODE 0: By rank 1: By Phase
2077 01:36:53.853457 ==============================================================
2078 01:36:53.856749 GAT_TRACK_EN = 1
2079 01:36:53.859800 RX_GATING_MODE = 2
2080 01:36:53.860279 RX_GATING_TRACK_MODE = 2
2081 01:36:53.863249 SELPH_MODE = 1
2082 01:36:53.866852 PICG_EARLY_EN = 1
2083 01:36:53.870333 VALID_LAT_VALUE = 1
2084 01:36:53.876945 ==============================================================
2085 01:36:53.880490 Enter into Gating configuration >>>>
2086 01:36:53.883593 Exit from Gating configuration <<<<
2087 01:36:53.886741 Enter into DVFS_PRE_config >>>>>
2088 01:36:53.896901 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2089 01:36:53.899963 Exit from DVFS_PRE_config <<<<<
2090 01:36:53.903440 Enter into PICG configuration >>>>
2091 01:36:53.906446 Exit from PICG configuration <<<<
2092 01:36:53.910018 [RX_INPUT] configuration >>>>>
2093 01:36:53.913251 [RX_INPUT] configuration <<<<<
2094 01:36:53.916601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2095 01:36:53.923169 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2096 01:36:53.930115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2097 01:36:53.933759 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2098 01:36:53.940131 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2099 01:36:53.947278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2100 01:36:53.949809 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2101 01:36:53.953729 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2102 01:36:53.960071 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2103 01:36:53.963344 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2104 01:36:53.966505 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2105 01:36:53.973055 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2106 01:36:53.976494 ===================================
2107 01:36:53.976970 LPDDR4 DRAM CONFIGURATION
2108 01:36:53.979979 ===================================
2109 01:36:53.983270 EX_ROW_EN[0] = 0x0
2110 01:36:53.984063 EX_ROW_EN[1] = 0x0
2111 01:36:53.986413 LP4Y_EN = 0x0
2112 01:36:53.989844 WORK_FSP = 0x0
2113 01:36:53.990315 WL = 0x4
2114 01:36:53.993398 RL = 0x4
2115 01:36:53.993875 BL = 0x2
2116 01:36:53.996511 RPST = 0x0
2117 01:36:53.996980 RD_PRE = 0x0
2118 01:36:53.999517 WR_PRE = 0x1
2119 01:36:53.999987 WR_PST = 0x0
2120 01:36:54.003038 DBI_WR = 0x0
2121 01:36:54.003534 DBI_RD = 0x0
2122 01:36:54.006461 OTF = 0x1
2123 01:36:54.009752 ===================================
2124 01:36:54.012955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2125 01:36:54.016241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2126 01:36:54.022881 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 01:36:54.023361 ===================================
2128 01:36:54.026455 LPDDR4 DRAM CONFIGURATION
2129 01:36:54.029855 ===================================
2130 01:36:54.032951 EX_ROW_EN[0] = 0x10
2131 01:36:54.033451 EX_ROW_EN[1] = 0x0
2132 01:36:54.036237 LP4Y_EN = 0x0
2133 01:36:54.036706 WORK_FSP = 0x0
2134 01:36:54.039749 WL = 0x4
2135 01:36:54.040320 RL = 0x4
2136 01:36:54.043013 BL = 0x2
2137 01:36:54.046252 RPST = 0x0
2138 01:36:54.046723 RD_PRE = 0x0
2139 01:36:54.049528 WR_PRE = 0x1
2140 01:36:54.049989 WR_PST = 0x0
2141 01:36:54.052911 DBI_WR = 0x0
2142 01:36:54.053462 DBI_RD = 0x0
2143 01:36:54.056228 OTF = 0x1
2144 01:36:54.059430 ===================================
2145 01:36:54.062636 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2146 01:36:54.066364 ==
2147 01:36:54.069765 Dram Type= 6, Freq= 0, CH_0, rank 0
2148 01:36:54.073054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2149 01:36:54.073879 ==
2150 01:36:54.076238 [Duty_Offset_Calibration]
2151 01:36:54.076698 B0:0 B1:2 CA:1
2152 01:36:54.077062
2153 01:36:54.079445 [DutyScan_Calibration_Flow] k_type=0
2154 01:36:54.089079
2155 01:36:54.089821 ==CLK 0==
2156 01:36:54.092282 Final CLK duty delay cell = 0
2157 01:36:54.095671 [0] MAX Duty = 5093%(X100), DQS PI = 12
2158 01:36:54.098879 [0] MIN Duty = 4938%(X100), DQS PI = 52
2159 01:36:54.099347 [0] AVG Duty = 5015%(X100)
2160 01:36:54.102176
2161 01:36:54.105616 CH0 CLK Duty spec in!! Max-Min= 155%
2162 01:36:54.109013 [DutyScan_Calibration_Flow] ====Done====
2163 01:36:54.109508
2164 01:36:54.112588 [DutyScan_Calibration_Flow] k_type=1
2165 01:36:54.128276
2166 01:36:54.128819 ==DQS 0 ==
2167 01:36:54.131592 Final DQS duty delay cell = 0
2168 01:36:54.135072 [0] MAX Duty = 5125%(X100), DQS PI = 30
2169 01:36:54.138268 [0] MIN Duty = 5031%(X100), DQS PI = 4
2170 01:36:54.141388 [0] AVG Duty = 5078%(X100)
2171 01:36:54.142053
2172 01:36:54.142424 ==DQS 1 ==
2173 01:36:54.144688 Final DQS duty delay cell = 0
2174 01:36:54.147924 [0] MAX Duty = 5031%(X100), DQS PI = 58
2175 01:36:54.152082 [0] MIN Duty = 4875%(X100), DQS PI = 22
2176 01:36:54.155051 [0] AVG Duty = 4953%(X100)
2177 01:36:54.155605
2178 01:36:54.158197 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2179 01:36:54.158663
2180 01:36:54.161711 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2181 01:36:54.164723 [DutyScan_Calibration_Flow] ====Done====
2182 01:36:54.165216
2183 01:36:54.167961 [DutyScan_Calibration_Flow] k_type=3
2184 01:36:54.185664
2185 01:36:54.186211 ==DQM 0 ==
2186 01:36:54.188757 Final DQM duty delay cell = 0
2187 01:36:54.192143 [0] MAX Duty = 5156%(X100), DQS PI = 22
2188 01:36:54.195361 [0] MIN Duty = 4969%(X100), DQS PI = 40
2189 01:36:54.199003 [0] AVG Duty = 5062%(X100)
2190 01:36:54.199461
2191 01:36:54.199822 ==DQM 1 ==
2192 01:36:54.202033 Final DQM duty delay cell = 4
2193 01:36:54.205452 [4] MAX Duty = 5187%(X100), DQS PI = 54
2194 01:36:54.208637 [4] MIN Duty = 5000%(X100), DQS PI = 16
2195 01:36:54.212260 [4] AVG Duty = 5093%(X100)
2196 01:36:54.212719
2197 01:36:54.215781 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2198 01:36:54.216338
2199 01:36:54.218557 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2200 01:36:54.221905 [DutyScan_Calibration_Flow] ====Done====
2201 01:36:54.222457
2202 01:36:54.225121 [DutyScan_Calibration_Flow] k_type=2
2203 01:36:54.240436
2204 01:36:54.240988 ==DQ 0 ==
2205 01:36:54.244357 Final DQ duty delay cell = -4
2206 01:36:54.247157 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2207 01:36:54.250270 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2208 01:36:54.253756 [-4] AVG Duty = 4937%(X100)
2209 01:36:54.254229
2210 01:36:54.254703 ==DQ 1 ==
2211 01:36:54.256966 Final DQ duty delay cell = -4
2212 01:36:54.260274 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2213 01:36:54.263700 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2214 01:36:54.267347 [-4] AVG Duty = 4969%(X100)
2215 01:36:54.267812
2216 01:36:54.270801 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2217 01:36:54.271361
2218 01:36:54.273734 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2219 01:36:54.277108 [DutyScan_Calibration_Flow] ====Done====
2220 01:36:54.277630 ==
2221 01:36:54.280559 Dram Type= 6, Freq= 0, CH_1, rank 0
2222 01:36:54.284239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2223 01:36:54.284796 ==
2224 01:36:54.287408 [Duty_Offset_Calibration]
2225 01:36:54.287883 B0:0 B1:5 CA:-5
2226 01:36:54.288249
2227 01:36:54.290290 [DutyScan_Calibration_Flow] k_type=0
2228 01:36:54.301208
2229 01:36:54.301827 ==CLK 0==
2230 01:36:54.304091 Final CLK duty delay cell = 0
2231 01:36:54.307716 [0] MAX Duty = 5094%(X100), DQS PI = 24
2232 01:36:54.310870 [0] MIN Duty = 4876%(X100), DQS PI = 52
2233 01:36:54.311392 [0] AVG Duty = 4985%(X100)
2234 01:36:54.314259
2235 01:36:54.317562 CH1 CLK Duty spec in!! Max-Min= 218%
2236 01:36:54.321346 [DutyScan_Calibration_Flow] ====Done====
2237 01:36:54.321951
2238 01:36:54.324147 [DutyScan_Calibration_Flow] k_type=1
2239 01:36:54.339755
2240 01:36:54.340316 ==DQS 0 ==
2241 01:36:54.342758 Final DQS duty delay cell = 0
2242 01:36:54.346109 [0] MAX Duty = 5125%(X100), DQS PI = 16
2243 01:36:54.349691 [0] MIN Duty = 4875%(X100), DQS PI = 40
2244 01:36:54.350155 [0] AVG Duty = 5000%(X100)
2245 01:36:54.353103
2246 01:36:54.353720 ==DQS 1 ==
2247 01:36:54.356145 Final DQS duty delay cell = -4
2248 01:36:54.359645 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2249 01:36:54.362680 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2250 01:36:54.366564 [-4] AVG Duty = 4953%(X100)
2251 01:36:54.367115
2252 01:36:54.369402 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2253 01:36:54.369858
2254 01:36:54.372833 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2255 01:36:54.376042 [DutyScan_Calibration_Flow] ====Done====
2256 01:36:54.376500
2257 01:36:54.379795 [DutyScan_Calibration_Flow] k_type=3
2258 01:36:54.395119
2259 01:36:54.395667 ==DQM 0 ==
2260 01:36:54.398182 Final DQM duty delay cell = -4
2261 01:36:54.401670 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2262 01:36:54.404737 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2263 01:36:54.408355 [-4] AVG Duty = 4969%(X100)
2264 01:36:54.408943
2265 01:36:54.409357 ==DQM 1 ==
2266 01:36:54.411489 Final DQM duty delay cell = -4
2267 01:36:54.414541 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2268 01:36:54.418191 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2269 01:36:54.421415 [-4] AVG Duty = 5000%(X100)
2270 01:36:54.421873
2271 01:36:54.424554 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2272 01:36:54.425007
2273 01:36:54.428018 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2274 01:36:54.431114 [DutyScan_Calibration_Flow] ====Done====
2275 01:36:54.431577
2276 01:36:54.434741 [DutyScan_Calibration_Flow] k_type=2
2277 01:36:54.452006
2278 01:36:54.452557 ==DQ 0 ==
2279 01:36:54.455458 Final DQ duty delay cell = 0
2280 01:36:54.458696 [0] MAX Duty = 5062%(X100), DQS PI = 0
2281 01:36:54.461946 [0] MIN Duty = 4938%(X100), DQS PI = 44
2282 01:36:54.462403 [0] AVG Duty = 5000%(X100)
2283 01:36:54.462768
2284 01:36:54.465404 ==DQ 1 ==
2285 01:36:54.468827 Final DQ duty delay cell = 0
2286 01:36:54.471622 [0] MAX Duty = 5031%(X100), DQS PI = 8
2287 01:36:54.475014 [0] MIN Duty = 4907%(X100), DQS PI = 0
2288 01:36:54.475473 [0] AVG Duty = 4969%(X100)
2289 01:36:54.475870
2290 01:36:54.478488 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2291 01:36:54.478943
2292 01:36:54.481878 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2293 01:36:54.488249 [DutyScan_Calibration_Flow] ====Done====
2294 01:36:54.491553 nWR fixed to 30
2295 01:36:54.492155 [ModeRegInit_LP4] CH0 RK0
2296 01:36:54.495215 [ModeRegInit_LP4] CH0 RK1
2297 01:36:54.498578 [ModeRegInit_LP4] CH1 RK0
2298 01:36:54.499001 [ModeRegInit_LP4] CH1 RK1
2299 01:36:54.501815 match AC timing 6
2300 01:36:54.504898 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2301 01:36:54.508457 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2302 01:36:54.515106 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2303 01:36:54.518290 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2304 01:36:54.524976 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2305 01:36:54.525497 ==
2306 01:36:54.528210 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 01:36:54.531592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2308 01:36:54.532046 ==
2309 01:36:54.538228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2310 01:36:54.541315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2311 01:36:54.551523 [CA 0] Center 39 (9~70) winsize 62
2312 01:36:54.554814 [CA 1] Center 39 (8~70) winsize 63
2313 01:36:54.558253 [CA 2] Center 36 (5~67) winsize 63
2314 01:36:54.561564 [CA 3] Center 35 (4~66) winsize 63
2315 01:36:54.565026 [CA 4] Center 34 (3~65) winsize 63
2316 01:36:54.568121 [CA 5] Center 33 (3~64) winsize 62
2317 01:36:54.568674
2318 01:36:54.571556 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2319 01:36:54.572106
2320 01:36:54.574712 [CATrainingPosCal] consider 1 rank data
2321 01:36:54.578016 u2DelayCellTimex100 = 270/100 ps
2322 01:36:54.581284 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2323 01:36:54.587941 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2324 01:36:54.591170 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2325 01:36:54.594382 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2326 01:36:54.598130 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2327 01:36:54.601469 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2328 01:36:54.602015
2329 01:36:54.604728 CA PerBit enable=1, Macro0, CA PI delay=33
2330 01:36:54.605198
2331 01:36:54.608018 [CBTSetCACLKResult] CA Dly = 33
2332 01:36:54.608582 CS Dly: 7 (0~38)
2333 01:36:54.611180 ==
2334 01:36:54.614346 Dram Type= 6, Freq= 0, CH_0, rank 1
2335 01:36:54.617648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2336 01:36:54.618112 ==
2337 01:36:54.624327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2338 01:36:54.627587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2339 01:36:54.637151 [CA 0] Center 39 (8~70) winsize 63
2340 01:36:54.640399 [CA 1] Center 39 (8~70) winsize 63
2341 01:36:54.643755 [CA 2] Center 36 (5~67) winsize 63
2342 01:36:54.647055 [CA 3] Center 35 (4~66) winsize 63
2343 01:36:54.650207 [CA 4] Center 33 (3~64) winsize 62
2344 01:36:54.653529 [CA 5] Center 34 (3~65) winsize 63
2345 01:36:54.654092
2346 01:36:54.657117 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2347 01:36:54.657731
2348 01:36:54.660492 [CATrainingPosCal] consider 2 rank data
2349 01:36:54.663646 u2DelayCellTimex100 = 270/100 ps
2350 01:36:54.666933 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2351 01:36:54.670163 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2352 01:36:54.677082 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2353 01:36:54.680233 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2354 01:36:54.683747 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2355 01:36:54.686878 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2356 01:36:54.687447
2357 01:36:54.690035 CA PerBit enable=1, Macro0, CA PI delay=33
2358 01:36:54.690500
2359 01:36:54.693411 [CBTSetCACLKResult] CA Dly = 33
2360 01:36:54.693977 CS Dly: 7 (0~39)
2361 01:36:54.697202
2362 01:36:54.700226 ----->DramcWriteLeveling(PI) begin...
2363 01:36:54.700802 ==
2364 01:36:54.703289 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 01:36:54.706609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2366 01:36:54.707166 ==
2367 01:36:54.709984 Write leveling (Byte 0): 26 => 26
2368 01:36:54.713166 Write leveling (Byte 1): 24 => 24
2369 01:36:54.716586 DramcWriteLeveling(PI) end<-----
2370 01:36:54.717039
2371 01:36:54.717442 ==
2372 01:36:54.719974 Dram Type= 6, Freq= 0, CH_0, rank 0
2373 01:36:54.723393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2374 01:36:54.723854 ==
2375 01:36:54.726664 [Gating] SW mode calibration
2376 01:36:54.733154 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2377 01:36:54.740072 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2378 01:36:54.743507 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 01:36:54.746730 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 01:36:54.753548 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 01:36:54.756787 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2382 01:36:54.760624 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2383 01:36:54.763843 0 11 20 | B1->B0 | 2d2d 2a2a | 1 0 | (0 1) (0 1)
2384 01:36:54.770235 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 01:36:54.773612 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 01:36:54.776402 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 01:36:54.783297 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 01:36:54.786762 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 01:36:54.789855 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 01:36:54.796892 0 12 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2391 01:36:54.799964 0 12 20 | B1->B0 | 3c3c 4141 | 0 0 | (1 1) (0 0)
2392 01:36:54.803188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 01:36:54.809974 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 01:36:54.812985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 01:36:54.816823 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 01:36:54.823062 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 01:36:54.826428 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 01:36:54.829829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 01:36:54.836428 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2400 01:36:54.840198 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 01:36:54.843109 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 01:36:54.850136 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 01:36:54.853362 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 01:36:54.856239 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 01:36:54.862703 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 01:36:54.866561 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 01:36:54.869254 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 01:36:54.876732 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 01:36:54.879583 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 01:36:54.883026 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 01:36:54.886227 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 01:36:54.893459 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 01:36:54.896535 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 01:36:54.899980 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 01:36:54.906289 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2416 01:36:54.909967 Total UI for P1: 0, mck2ui 16
2417 01:36:54.912862 best dqsien dly found for B0: ( 0, 15, 18)
2418 01:36:54.916563 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2419 01:36:54.919828 Total UI for P1: 0, mck2ui 16
2420 01:36:54.923416 best dqsien dly found for B1: ( 0, 15, 20)
2421 01:36:54.926268 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2422 01:36:54.929365 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2423 01:36:54.929827
2424 01:36:54.933033 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2425 01:36:54.936364 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2426 01:36:54.939498 [Gating] SW calibration Done
2427 01:36:54.939964 ==
2428 01:36:54.943344 Dram Type= 6, Freq= 0, CH_0, rank 0
2429 01:36:54.949823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2430 01:36:54.950384 ==
2431 01:36:54.950748 RX Vref Scan: 0
2432 01:36:54.951085
2433 01:36:54.952852 RX Vref 0 -> 0, step: 1
2434 01:36:54.953352
2435 01:36:54.956179 RX Delay -40 -> 252, step: 8
2436 01:36:54.959494 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2437 01:36:54.962623 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2438 01:36:54.966765 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2439 01:36:54.969595 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2440 01:36:54.976183 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2441 01:36:54.980188 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2442 01:36:54.982992 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2443 01:36:54.986051 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2444 01:36:54.989559 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2445 01:36:54.996265 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2446 01:36:54.999755 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2447 01:36:55.002956 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2448 01:36:55.005929 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2449 01:36:55.009588 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2450 01:36:55.016227 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2451 01:36:55.019291 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2452 01:36:55.019754 ==
2453 01:36:55.022444 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 01:36:55.026238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2455 01:36:55.026812 ==
2456 01:36:55.029468 DQS Delay:
2457 01:36:55.029930 DQS0 = 0, DQS1 = 0
2458 01:36:55.030299 DQM Delay:
2459 01:36:55.032708 DQM0 = 115, DQM1 = 106
2460 01:36:55.033170 DQ Delay:
2461 01:36:55.036087 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2462 01:36:55.039614 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2463 01:36:55.042817 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2464 01:36:55.049164 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2465 01:36:55.049682
2466 01:36:55.050046
2467 01:36:55.050381 ==
2468 01:36:55.052853 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 01:36:55.056012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2470 01:36:55.056580 ==
2471 01:36:55.056951
2472 01:36:55.057328
2473 01:36:55.059261 TX Vref Scan disable
2474 01:36:55.059824 == TX Byte 0 ==
2475 01:36:55.066080 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2476 01:36:55.069489 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2477 01:36:55.070049 == TX Byte 1 ==
2478 01:36:55.076026 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2479 01:36:55.079470 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2480 01:36:55.080036 ==
2481 01:36:55.082714 Dram Type= 6, Freq= 0, CH_0, rank 0
2482 01:36:55.085673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2483 01:36:55.086240 ==
2484 01:36:55.098735 TX Vref=22, minBit 4, minWin=25, winSum=407
2485 01:36:55.102069 TX Vref=24, minBit 5, minWin=25, winSum=412
2486 01:36:55.105048 TX Vref=26, minBit 8, minWin=25, winSum=423
2487 01:36:55.108436 TX Vref=28, minBit 9, minWin=25, winSum=427
2488 01:36:55.111582 TX Vref=30, minBit 5, minWin=26, winSum=426
2489 01:36:55.115070 TX Vref=32, minBit 5, minWin=26, winSum=426
2490 01:36:55.121530 [TxChooseVref] Worse bit 5, Min win 26, Win sum 426, Final Vref 30
2491 01:36:55.121992
2492 01:36:55.124740 Final TX Range 1 Vref 30
2493 01:36:55.125202
2494 01:36:55.125599 ==
2495 01:36:55.128459 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 01:36:55.131423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2497 01:36:55.131885 ==
2498 01:36:55.135144
2499 01:36:55.135616
2500 01:36:55.135978 TX Vref Scan disable
2501 01:36:55.138014 == TX Byte 0 ==
2502 01:36:55.141484 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2503 01:36:55.144654 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2504 01:36:55.147992 == TX Byte 1 ==
2505 01:36:55.151346 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2506 01:36:55.154524 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2507 01:36:55.154716
2508 01:36:55.158315 [DATLAT]
2509 01:36:55.158584 Freq=1200, CH0 RK0
2510 01:36:55.158751
2511 01:36:55.161438 DATLAT Default: 0xd
2512 01:36:55.161631 0, 0xFFFF, sum = 0
2513 01:36:55.164595 1, 0xFFFF, sum = 0
2514 01:36:55.164787 2, 0xFFFF, sum = 0
2515 01:36:55.168181 3, 0xFFFF, sum = 0
2516 01:36:55.168453 4, 0xFFFF, sum = 0
2517 01:36:55.171440 5, 0xFFFF, sum = 0
2518 01:36:55.171757 6, 0xFFFF, sum = 0
2519 01:36:55.174624 7, 0xFFFF, sum = 0
2520 01:36:55.177703 8, 0xFFFF, sum = 0
2521 01:36:55.178019 9, 0xFFFF, sum = 0
2522 01:36:55.181144 10, 0xFFFF, sum = 0
2523 01:36:55.181395 11, 0x0, sum = 1
2524 01:36:55.184495 12, 0x0, sum = 2
2525 01:36:55.184697 13, 0x0, sum = 3
2526 01:36:55.184851 14, 0x0, sum = 4
2527 01:36:55.187807 best_step = 12
2528 01:36:55.188010
2529 01:36:55.188169 ==
2530 01:36:55.191002 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 01:36:55.194536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2532 01:36:55.194695 ==
2533 01:36:55.197852 RX Vref Scan: 1
2534 01:36:55.197988
2535 01:36:55.201141 Set Vref Range= 32 -> 127
2536 01:36:55.201275
2537 01:36:55.201397 RX Vref 32 -> 127, step: 1
2538 01:36:55.201511
2539 01:36:55.204752 RX Delay -21 -> 252, step: 4
2540 01:36:55.204886
2541 01:36:55.207759 Set Vref, RX VrefLevel [Byte0]: 32
2542 01:36:55.211194 [Byte1]: 32
2543 01:36:55.214774
2544 01:36:55.214910 Set Vref, RX VrefLevel [Byte0]: 33
2545 01:36:55.218098 [Byte1]: 33
2546 01:36:55.222650
2547 01:36:55.223256 Set Vref, RX VrefLevel [Byte0]: 34
2548 01:36:55.225892 [Byte1]: 34
2549 01:36:55.230644
2550 01:36:55.231353 Set Vref, RX VrefLevel [Byte0]: 35
2551 01:36:55.233787 [Byte1]: 35
2552 01:36:55.238366
2553 01:36:55.238662 Set Vref, RX VrefLevel [Byte0]: 36
2554 01:36:55.241694 [Byte1]: 36
2555 01:36:55.246296
2556 01:36:55.246533 Set Vref, RX VrefLevel [Byte0]: 37
2557 01:36:55.249610 [Byte1]: 37
2558 01:36:55.253984
2559 01:36:55.254134 Set Vref, RX VrefLevel [Byte0]: 38
2560 01:36:55.257277 [Byte1]: 38
2561 01:36:55.261815
2562 01:36:55.261945 Set Vref, RX VrefLevel [Byte0]: 39
2563 01:36:55.265214 [Byte1]: 39
2564 01:36:55.269869
2565 01:36:55.269998 Set Vref, RX VrefLevel [Byte0]: 40
2566 01:36:55.273033 [Byte1]: 40
2567 01:36:55.277814
2568 01:36:55.277999 Set Vref, RX VrefLevel [Byte0]: 41
2569 01:36:55.281164 [Byte1]: 41
2570 01:36:55.285792
2571 01:36:55.285922 Set Vref, RX VrefLevel [Byte0]: 42
2572 01:36:55.288806 [Byte1]: 42
2573 01:36:55.293938
2574 01:36:55.294126 Set Vref, RX VrefLevel [Byte0]: 43
2575 01:36:55.296836 [Byte1]: 43
2576 01:36:55.301420
2577 01:36:55.301548 Set Vref, RX VrefLevel [Byte0]: 44
2578 01:36:55.304746 [Byte1]: 44
2579 01:36:55.309410
2580 01:36:55.309544 Set Vref, RX VrefLevel [Byte0]: 45
2581 01:36:55.312586 [Byte1]: 45
2582 01:36:55.317607
2583 01:36:55.317778 Set Vref, RX VrefLevel [Byte0]: 46
2584 01:36:55.320676 [Byte1]: 46
2585 01:36:55.325331
2586 01:36:55.325462 Set Vref, RX VrefLevel [Byte0]: 47
2587 01:36:55.328510 [Byte1]: 47
2588 01:36:55.333790
2589 01:36:55.334310 Set Vref, RX VrefLevel [Byte0]: 48
2590 01:36:55.336685 [Byte1]: 48
2591 01:36:55.341349
2592 01:36:55.341765 Set Vref, RX VrefLevel [Byte0]: 49
2593 01:36:55.344687 [Byte1]: 49
2594 01:36:55.349268
2595 01:36:55.349720 Set Vref, RX VrefLevel [Byte0]: 50
2596 01:36:55.352961 [Byte1]: 50
2597 01:36:55.357462
2598 01:36:55.357964 Set Vref, RX VrefLevel [Byte0]: 51
2599 01:36:55.360908 [Byte1]: 51
2600 01:36:55.365151
2601 01:36:55.365875 Set Vref, RX VrefLevel [Byte0]: 52
2602 01:36:55.368487 [Byte1]: 52
2603 01:36:55.372889
2604 01:36:55.373472 Set Vref, RX VrefLevel [Byte0]: 53
2605 01:36:55.376551 [Byte1]: 53
2606 01:36:55.381196
2607 01:36:55.381664 Set Vref, RX VrefLevel [Byte0]: 54
2608 01:36:55.384579 [Byte1]: 54
2609 01:36:55.389467
2610 01:36:55.389984 Set Vref, RX VrefLevel [Byte0]: 55
2611 01:36:55.392917 [Byte1]: 55
2612 01:36:55.397060
2613 01:36:55.397613 Set Vref, RX VrefLevel [Byte0]: 56
2614 01:36:55.400414 [Byte1]: 56
2615 01:36:55.405095
2616 01:36:55.405575 Set Vref, RX VrefLevel [Byte0]: 57
2617 01:36:55.408097 [Byte1]: 57
2618 01:36:55.412728
2619 01:36:55.413256 Set Vref, RX VrefLevel [Byte0]: 58
2620 01:36:55.415927 [Byte1]: 58
2621 01:36:55.420827
2622 01:36:55.421239 Set Vref, RX VrefLevel [Byte0]: 59
2623 01:36:55.424061 [Byte1]: 59
2624 01:36:55.428884
2625 01:36:55.429451 Set Vref, RX VrefLevel [Byte0]: 60
2626 01:36:55.432163 [Byte1]: 60
2627 01:36:55.436867
2628 01:36:55.437762 Set Vref, RX VrefLevel [Byte0]: 61
2629 01:36:55.439825 [Byte1]: 61
2630 01:36:55.444313
2631 01:36:55.444754 Set Vref, RX VrefLevel [Byte0]: 62
2632 01:36:55.447787 [Byte1]: 62
2633 01:36:55.452642
2634 01:36:55.453056 Set Vref, RX VrefLevel [Byte0]: 63
2635 01:36:55.455851 [Byte1]: 63
2636 01:36:55.460423
2637 01:36:55.460941 Set Vref, RX VrefLevel [Byte0]: 64
2638 01:36:55.463599 [Byte1]: 64
2639 01:36:55.468256
2640 01:36:55.468669 Set Vref, RX VrefLevel [Byte0]: 65
2641 01:36:55.471631 [Byte1]: 65
2642 01:36:55.476610
2643 01:36:55.477113 Final RX Vref Byte 0 = 51 to rank0
2644 01:36:55.479781 Final RX Vref Byte 1 = 48 to rank0
2645 01:36:55.482821 Final RX Vref Byte 0 = 51 to rank1
2646 01:36:55.485999 Final RX Vref Byte 1 = 48 to rank1==
2647 01:36:55.489787 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 01:36:55.496382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2649 01:36:55.496953 ==
2650 01:36:55.497339 DQS Delay:
2651 01:36:55.497663 DQS0 = 0, DQS1 = 0
2652 01:36:55.499358 DQM Delay:
2653 01:36:55.499770 DQM0 = 114, DQM1 = 105
2654 01:36:55.502556 DQ Delay:
2655 01:36:55.506080 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2656 01:36:55.509826 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2657 01:36:55.512971 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2658 01:36:55.516026 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2659 01:36:55.516445
2660 01:36:55.516769
2661 01:36:55.522982 [DQSOSCAuto] RK0, (LSB)MR18= 0x202, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
2662 01:36:55.525966 CH0 RK0: MR19=404, MR18=202
2663 01:36:55.532808 CH0_RK0: MR19=0x404, MR18=0x202, DQSOSC=409, MR23=63, INC=39, DEC=26
2664 01:36:55.533366
2665 01:36:55.535791 ----->DramcWriteLeveling(PI) begin...
2666 01:36:55.536229 ==
2667 01:36:55.539554 Dram Type= 6, Freq= 0, CH_0, rank 1
2668 01:36:55.542723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2669 01:36:55.543256 ==
2670 01:36:55.545954 Write leveling (Byte 0): 27 => 27
2671 01:36:55.549484 Write leveling (Byte 1): 25 => 25
2672 01:36:55.552862 DramcWriteLeveling(PI) end<-----
2673 01:36:55.553425
2674 01:36:55.553765 ==
2675 01:36:55.556178 Dram Type= 6, Freq= 0, CH_0, rank 1
2676 01:36:55.559627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2677 01:36:55.562832 ==
2678 01:36:55.563258 [Gating] SW mode calibration
2679 01:36:55.572965 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2680 01:36:55.576612 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2681 01:36:55.579661 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2682 01:36:55.586265 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2683 01:36:55.589532 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2684 01:36:55.593022 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2685 01:36:55.599582 0 11 16 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
2686 01:36:55.602644 0 11 20 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (0 1)
2687 01:36:55.606014 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 01:36:55.612725 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 01:36:55.616064 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 01:36:55.619461 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 01:36:55.625955 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 01:36:55.629519 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 01:36:55.632714 0 12 16 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2694 01:36:55.639641 0 12 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2695 01:36:55.642645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 01:36:55.646194 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 01:36:55.652519 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 01:36:55.655962 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 01:36:55.659432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 01:36:55.665858 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 01:36:55.669742 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2702 01:36:55.672624 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2703 01:36:55.675922 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 01:36:55.682748 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 01:36:55.686027 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 01:36:55.689340 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 01:36:55.696179 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 01:36:55.699491 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 01:36:55.702660 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 01:36:55.709635 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 01:36:55.712491 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 01:36:55.715680 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 01:36:55.722420 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 01:36:55.725768 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 01:36:55.729208 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 01:36:55.735726 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 01:36:55.738916 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 01:36:55.742567 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2719 01:36:55.746123 Total UI for P1: 0, mck2ui 16
2720 01:36:55.749074 best dqsien dly found for B0: ( 0, 15, 18)
2721 01:36:55.752404 Total UI for P1: 0, mck2ui 16
2722 01:36:55.755988 best dqsien dly found for B1: ( 0, 15, 18)
2723 01:36:55.759193 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2724 01:36:55.762412 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2725 01:36:55.762974
2726 01:36:55.766137 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2727 01:36:55.772672 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2728 01:36:55.773233 [Gating] SW calibration Done
2729 01:36:55.776076 ==
2730 01:36:55.776633 Dram Type= 6, Freq= 0, CH_0, rank 1
2731 01:36:55.782323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2732 01:36:55.782799 ==
2733 01:36:55.783159 RX Vref Scan: 0
2734 01:36:55.783498
2735 01:36:55.785515 RX Vref 0 -> 0, step: 1
2736 01:36:55.785975
2737 01:36:55.789464 RX Delay -40 -> 252, step: 8
2738 01:36:55.792833 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2739 01:36:55.795850 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2740 01:36:55.799573 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2741 01:36:55.805828 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2742 01:36:55.808749 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2743 01:36:55.812007 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2744 01:36:55.815663 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2745 01:36:55.818902 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2746 01:36:55.825592 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2747 01:36:55.829269 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2748 01:36:55.832402 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2749 01:36:55.835642 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2750 01:36:55.838773 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2751 01:36:55.845490 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2752 01:36:55.849072 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2753 01:36:55.852270 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2754 01:36:55.852735 ==
2755 01:36:55.855863 Dram Type= 6, Freq= 0, CH_0, rank 1
2756 01:36:55.859118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2757 01:36:55.859682 ==
2758 01:36:55.862033 DQS Delay:
2759 01:36:55.862491 DQS0 = 0, DQS1 = 0
2760 01:36:55.865331 DQM Delay:
2761 01:36:55.865790 DQM0 = 116, DQM1 = 106
2762 01:36:55.866157 DQ Delay:
2763 01:36:55.868681 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2764 01:36:55.875480 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2765 01:36:55.878735 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2766 01:36:55.882205 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2767 01:36:55.882775
2768 01:36:55.883141
2769 01:36:55.883476 ==
2770 01:36:55.885600 Dram Type= 6, Freq= 0, CH_0, rank 1
2771 01:36:55.888906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2772 01:36:55.889507 ==
2773 01:36:55.889879
2774 01:36:55.890215
2775 01:36:55.892441 TX Vref Scan disable
2776 01:36:55.895632 == TX Byte 0 ==
2777 01:36:55.899198 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2778 01:36:55.901987 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2779 01:36:55.905198 == TX Byte 1 ==
2780 01:36:55.908653 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2781 01:36:55.911922 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2782 01:36:55.912381 ==
2783 01:36:55.915321 Dram Type= 6, Freq= 0, CH_0, rank 1
2784 01:36:55.918473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2785 01:36:55.918935 ==
2786 01:36:55.931757 TX Vref=22, minBit 8, minWin=25, winSum=420
2787 01:36:55.934993 TX Vref=24, minBit 8, minWin=25, winSum=424
2788 01:36:55.938628 TX Vref=26, minBit 8, minWin=25, winSum=427
2789 01:36:55.942140 TX Vref=28, minBit 8, minWin=26, winSum=429
2790 01:36:55.945420 TX Vref=30, minBit 8, minWin=26, winSum=433
2791 01:36:55.948919 TX Vref=32, minBit 9, minWin=26, winSum=439
2792 01:36:55.955654 [TxChooseVref] Worse bit 9, Min win 26, Win sum 439, Final Vref 32
2793 01:36:55.956210
2794 01:36:55.958543 Final TX Range 1 Vref 32
2795 01:36:55.959006
2796 01:36:55.959371 ==
2797 01:36:55.961954 Dram Type= 6, Freq= 0, CH_0, rank 1
2798 01:36:55.965233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2799 01:36:55.965727 ==
2800 01:36:55.966094
2801 01:36:55.966429
2802 01:36:55.968455 TX Vref Scan disable
2803 01:36:55.972227 == TX Byte 0 ==
2804 01:36:55.975067 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2805 01:36:55.978429 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2806 01:36:55.981969 == TX Byte 1 ==
2807 01:36:55.985348 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2808 01:36:55.988083 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2809 01:36:55.988501
2810 01:36:55.991637 [DATLAT]
2811 01:36:55.992056 Freq=1200, CH0 RK1
2812 01:36:55.992390
2813 01:36:55.995252 DATLAT Default: 0xc
2814 01:36:55.995763 0, 0xFFFF, sum = 0
2815 01:36:55.998536 1, 0xFFFF, sum = 0
2816 01:36:55.999058 2, 0xFFFF, sum = 0
2817 01:36:56.001637 3, 0xFFFF, sum = 0
2818 01:36:56.002156 4, 0xFFFF, sum = 0
2819 01:36:56.004904 5, 0xFFFF, sum = 0
2820 01:36:56.005387 6, 0xFFFF, sum = 0
2821 01:36:56.008784 7, 0xFFFF, sum = 0
2822 01:36:56.011981 8, 0xFFFF, sum = 0
2823 01:36:56.012505 9, 0xFFFF, sum = 0
2824 01:36:56.015118 10, 0xFFFF, sum = 0
2825 01:36:56.015542 11, 0x0, sum = 1
2826 01:36:56.018154 12, 0x0, sum = 2
2827 01:36:56.018575 13, 0x0, sum = 3
2828 01:36:56.018909 14, 0x0, sum = 4
2829 01:36:56.021395 best_step = 12
2830 01:36:56.021809
2831 01:36:56.022180 ==
2832 01:36:56.024750 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 01:36:56.028363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2834 01:36:56.028881 ==
2835 01:36:56.031874 RX Vref Scan: 0
2836 01:36:56.032594
2837 01:36:56.032971 RX Vref 0 -> 0, step: 1
2838 01:36:56.034569
2839 01:36:56.034983 RX Delay -21 -> 252, step: 4
2840 01:36:56.042506 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2841 01:36:56.045712 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2842 01:36:56.048922 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2843 01:36:56.052515 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2844 01:36:56.055681 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2845 01:36:56.062642 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2846 01:36:56.065396 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2847 01:36:56.068805 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2848 01:36:56.072268 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2849 01:36:56.075397 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2850 01:36:56.082164 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2851 01:36:56.085664 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2852 01:36:56.088782 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2853 01:36:56.092116 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2854 01:36:56.095609 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2855 01:36:56.102362 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2856 01:36:56.102896 ==
2857 01:36:56.105725 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 01:36:56.108934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2859 01:36:56.109491 ==
2860 01:36:56.109831 DQS Delay:
2861 01:36:56.112435 DQS0 = 0, DQS1 = 0
2862 01:36:56.112947 DQM Delay:
2863 01:36:56.116141 DQM0 = 114, DQM1 = 105
2864 01:36:56.116666 DQ Delay:
2865 01:36:56.118852 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2866 01:36:56.122673 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2867 01:36:56.125415 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2868 01:36:56.128947 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2869 01:36:56.129506
2870 01:36:56.129884
2871 01:36:56.139022 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2872 01:36:56.139526 CH0 RK1: MR19=404, MR18=B0B
2873 01:36:56.145429 CH0_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2874 01:36:56.149149 [RxdqsGatingPostProcess] freq 1200
2875 01:36:56.155709 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2876 01:36:56.158851 Pre-setting of DQS Precalculation
2877 01:36:56.162549 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2878 01:36:56.163062 ==
2879 01:36:56.165425 Dram Type= 6, Freq= 0, CH_1, rank 0
2880 01:36:56.172302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2881 01:36:56.172865 ==
2882 01:36:56.175661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2883 01:36:56.182106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2884 01:36:56.190312 [CA 0] Center 37 (7~68) winsize 62
2885 01:36:56.193994 [CA 1] Center 37 (7~68) winsize 62
2886 01:36:56.197270 [CA 2] Center 34 (4~65) winsize 62
2887 01:36:56.200293 [CA 3] Center 33 (3~64) winsize 62
2888 01:36:56.203917 [CA 4] Center 32 (1~63) winsize 63
2889 01:36:56.207067 [CA 5] Center 32 (2~63) winsize 62
2890 01:36:56.207627
2891 01:36:56.210855 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2892 01:36:56.211314
2893 01:36:56.213465 [CATrainingPosCal] consider 1 rank data
2894 01:36:56.216678 u2DelayCellTimex100 = 270/100 ps
2895 01:36:56.220656 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2896 01:36:56.223596 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2897 01:36:56.230316 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2898 01:36:56.233409 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2899 01:36:56.236878 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2900 01:36:56.240101 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2901 01:36:56.240653
2902 01:36:56.243790 CA PerBit enable=1, Macro0, CA PI delay=32
2903 01:36:56.244342
2904 01:36:56.246955 [CBTSetCACLKResult] CA Dly = 32
2905 01:36:56.247512 CS Dly: 6 (0~37)
2906 01:36:56.250218 ==
2907 01:36:56.250790 Dram Type= 6, Freq= 0, CH_1, rank 1
2908 01:36:56.257083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2909 01:36:56.257702 ==
2910 01:36:56.260524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2911 01:36:56.267420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2912 01:36:56.275852 [CA 0] Center 37 (7~68) winsize 62
2913 01:36:56.279015 [CA 1] Center 37 (7~68) winsize 62
2914 01:36:56.282037 [CA 2] Center 34 (3~65) winsize 63
2915 01:36:56.285636 [CA 3] Center 33 (3~64) winsize 62
2916 01:36:56.288976 [CA 4] Center 32 (2~63) winsize 62
2917 01:36:56.292001 [CA 5] Center 32 (1~63) winsize 63
2918 01:36:56.292462
2919 01:36:56.295607 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2920 01:36:56.296166
2921 01:36:56.298952 [CATrainingPosCal] consider 2 rank data
2922 01:36:56.302262 u2DelayCellTimex100 = 270/100 ps
2923 01:36:56.305463 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2924 01:36:56.312128 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2925 01:36:56.315493 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2926 01:36:56.318537 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2927 01:36:56.321994 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2928 01:36:56.325275 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2929 01:36:56.325876
2930 01:36:56.328751 CA PerBit enable=1, Macro0, CA PI delay=32
2931 01:36:56.329352
2932 01:36:56.332230 [CBTSetCACLKResult] CA Dly = 32
2933 01:36:56.332786 CS Dly: 6 (0~38)
2934 01:36:56.335179
2935 01:36:56.338645 ----->DramcWriteLeveling(PI) begin...
2936 01:36:56.339212 ==
2937 01:36:56.341664 Dram Type= 6, Freq= 0, CH_1, rank 0
2938 01:36:56.345272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2939 01:36:56.345877 ==
2940 01:36:56.348708 Write leveling (Byte 0): 23 => 23
2941 01:36:56.351835 Write leveling (Byte 1): 23 => 23
2942 01:36:56.355578 DramcWriteLeveling(PI) end<-----
2943 01:36:56.356132
2944 01:36:56.356497 ==
2945 01:36:56.358217 Dram Type= 6, Freq= 0, CH_1, rank 0
2946 01:36:56.361530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2947 01:36:56.361993 ==
2948 01:36:56.365010 [Gating] SW mode calibration
2949 01:36:56.372101 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2950 01:36:56.378348 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2951 01:36:56.381544 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 01:36:56.385229 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 01:36:56.392017 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 01:36:56.395221 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2955 01:36:56.398003 0 11 16 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 0)
2956 01:36:56.404897 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 01:36:56.408262 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 01:36:56.411491 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 01:36:56.418181 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 01:36:56.421369 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 01:36:56.424857 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 01:36:56.431293 0 12 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2963 01:36:56.434894 0 12 16 | B1->B0 | 2b2b 3f3f | 0 0 | (0 0) (0 0)
2964 01:36:56.437925 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2965 01:36:56.441710 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 01:36:56.448312 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 01:36:56.451393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 01:36:56.454805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 01:36:56.461403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 01:36:56.464857 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2971 01:36:56.468408 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2972 01:36:56.474617 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2973 01:36:56.478056 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 01:36:56.481857 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 01:36:56.488189 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 01:36:56.491167 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 01:36:56.494646 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 01:36:56.501677 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 01:36:56.505063 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 01:36:56.507758 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 01:36:56.514641 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 01:36:56.517859 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 01:36:56.521138 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 01:36:56.527960 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 01:36:56.531250 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 01:36:56.534537 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 01:36:56.541279 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2988 01:36:56.544664 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2989 01:36:56.547840 Total UI for P1: 0, mck2ui 16
2990 01:36:56.551015 best dqsien dly found for B0: ( 0, 15, 16)
2991 01:36:56.554378 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 01:36:56.557691 Total UI for P1: 0, mck2ui 16
2993 01:36:56.561032 best dqsien dly found for B1: ( 0, 15, 20)
2994 01:36:56.564483 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2995 01:36:56.568116 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2996 01:36:56.568629
2997 01:36:56.571249 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2998 01:36:56.577982 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2999 01:36:56.578534 [Gating] SW calibration Done
3000 01:36:56.578883 ==
3001 01:36:56.581330 Dram Type= 6, Freq= 0, CH_1, rank 0
3002 01:36:56.588072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3003 01:36:56.588602 ==
3004 01:36:56.588936 RX Vref Scan: 0
3005 01:36:56.589245
3006 01:36:56.590963 RX Vref 0 -> 0, step: 1
3007 01:36:56.591378
3008 01:36:56.594524 RX Delay -40 -> 252, step: 8
3009 01:36:56.597553 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3010 01:36:56.601014 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3011 01:36:56.604350 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3012 01:36:56.611078 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3013 01:36:56.614217 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3014 01:36:56.617556 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3015 01:36:56.620989 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3016 01:36:56.624448 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3017 01:36:56.627824 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3018 01:36:56.634554 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3019 01:36:56.637532 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3020 01:36:56.640907 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3021 01:36:56.644069 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3022 01:36:56.647585 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3023 01:36:56.654243 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3024 01:36:56.657705 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3025 01:36:56.658268 ==
3026 01:36:56.660962 Dram Type= 6, Freq= 0, CH_1, rank 0
3027 01:36:56.664129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3028 01:36:56.664544 ==
3029 01:36:56.667936 DQS Delay:
3030 01:36:56.668723 DQS0 = 0, DQS1 = 0
3031 01:36:56.669226 DQM Delay:
3032 01:36:56.671009 DQM0 = 116, DQM1 = 109
3033 01:36:56.671422 DQ Delay:
3034 01:36:56.674583 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3035 01:36:56.677644 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3036 01:36:56.681277 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3037 01:36:56.687412 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3038 01:36:56.687831
3039 01:36:56.688156
3040 01:36:56.688460 ==
3041 01:36:56.691155 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 01:36:56.694435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3043 01:36:56.694937 ==
3044 01:36:56.695489
3045 01:36:56.696066
3046 01:36:56.697679 TX Vref Scan disable
3047 01:36:56.698092 == TX Byte 0 ==
3048 01:36:56.704669 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3049 01:36:56.707626 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3050 01:36:56.708312 == TX Byte 1 ==
3051 01:36:56.714314 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3052 01:36:56.717609 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3053 01:36:56.718026 ==
3054 01:36:56.720948 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 01:36:56.724475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3056 01:36:56.725032 ==
3057 01:36:56.736818 TX Vref=22, minBit 8, minWin=25, winSum=413
3058 01:36:56.740085 TX Vref=24, minBit 11, minWin=25, winSum=422
3059 01:36:56.743419 TX Vref=26, minBit 15, minWin=25, winSum=429
3060 01:36:56.746782 TX Vref=28, minBit 8, minWin=26, winSum=432
3061 01:36:56.750224 TX Vref=30, minBit 11, minWin=26, winSum=437
3062 01:36:56.756983 TX Vref=32, minBit 9, minWin=26, winSum=433
3063 01:36:56.760041 [TxChooseVref] Worse bit 11, Min win 26, Win sum 437, Final Vref 30
3064 01:36:56.760605
3065 01:36:56.763416 Final TX Range 1 Vref 30
3066 01:36:56.763975
3067 01:36:56.764337 ==
3068 01:36:56.766506 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 01:36:56.769993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3070 01:36:56.773462 ==
3071 01:36:56.774019
3072 01:36:56.774380
3073 01:36:56.774714 TX Vref Scan disable
3074 01:36:56.776785 == TX Byte 0 ==
3075 01:36:56.780078 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3076 01:36:56.783355 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3077 01:36:56.786577 == TX Byte 1 ==
3078 01:36:56.790046 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3079 01:36:56.796959 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3080 01:36:56.797560
3081 01:36:56.797929 [DATLAT]
3082 01:36:56.798266 Freq=1200, CH1 RK0
3083 01:36:56.798589
3084 01:36:56.799936 DATLAT Default: 0xd
3085 01:36:56.800392 0, 0xFFFF, sum = 0
3086 01:36:56.803090 1, 0xFFFF, sum = 0
3087 01:36:56.803622 2, 0xFFFF, sum = 0
3088 01:36:56.806668 3, 0xFFFF, sum = 0
3089 01:36:56.807152 4, 0xFFFF, sum = 0
3090 01:36:56.809982 5, 0xFFFF, sum = 0
3091 01:36:56.813536 6, 0xFFFF, sum = 0
3092 01:36:56.814089 7, 0xFFFF, sum = 0
3093 01:36:56.816733 8, 0xFFFF, sum = 0
3094 01:36:56.817336 9, 0xFFFF, sum = 0
3095 01:36:56.820101 10, 0xFFFF, sum = 0
3096 01:36:56.820811 11, 0x0, sum = 1
3097 01:36:56.823261 12, 0x0, sum = 2
3098 01:36:56.823724 13, 0x0, sum = 3
3099 01:36:56.824093 14, 0x0, sum = 4
3100 01:36:56.826863 best_step = 12
3101 01:36:56.827322
3102 01:36:56.827676 ==
3103 01:36:56.829882 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 01:36:56.833413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3105 01:36:56.833870 ==
3106 01:36:56.836431 RX Vref Scan: 1
3107 01:36:56.836887
3108 01:36:56.839668 Set Vref Range= 32 -> 127
3109 01:36:56.840284
3110 01:36:56.840713 RX Vref 32 -> 127, step: 1
3111 01:36:56.841060
3112 01:36:56.843311 RX Delay -21 -> 252, step: 4
3113 01:36:56.843876
3114 01:36:56.846337 Set Vref, RX VrefLevel [Byte0]: 32
3115 01:36:56.849897 [Byte1]: 32
3116 01:36:56.853487
3117 01:36:56.854036 Set Vref, RX VrefLevel [Byte0]: 33
3118 01:36:56.856758 [Byte1]: 33
3119 01:36:56.861249
3120 01:36:56.861837 Set Vref, RX VrefLevel [Byte0]: 34
3121 01:36:56.864625 [Byte1]: 34
3122 01:36:56.869328
3123 01:36:56.869890 Set Vref, RX VrefLevel [Byte0]: 35
3124 01:36:56.873050 [Byte1]: 35
3125 01:36:56.876998
3126 01:36:56.877489 Set Vref, RX VrefLevel [Byte0]: 36
3127 01:36:56.880357 [Byte1]: 36
3128 01:36:56.885462
3129 01:36:56.886012 Set Vref, RX VrefLevel [Byte0]: 37
3130 01:36:56.888238 [Byte1]: 37
3131 01:36:56.893111
3132 01:36:56.893843 Set Vref, RX VrefLevel [Byte0]: 38
3133 01:36:56.896282 [Byte1]: 38
3134 01:36:56.901003
3135 01:36:56.901629 Set Vref, RX VrefLevel [Byte0]: 39
3136 01:36:56.904500 [Byte1]: 39
3137 01:36:56.908812
3138 01:36:56.909411 Set Vref, RX VrefLevel [Byte0]: 40
3139 01:36:56.912239 [Byte1]: 40
3140 01:36:56.916633
3141 01:36:56.917088 Set Vref, RX VrefLevel [Byte0]: 41
3142 01:36:56.919811 [Byte1]: 41
3143 01:36:56.924399
3144 01:36:56.924869 Set Vref, RX VrefLevel [Byte0]: 42
3145 01:36:56.928103 [Byte1]: 42
3146 01:36:56.932835
3147 01:36:56.933440 Set Vref, RX VrefLevel [Byte0]: 43
3148 01:36:56.936043 [Byte1]: 43
3149 01:36:56.940405
3150 01:36:56.940979 Set Vref, RX VrefLevel [Byte0]: 44
3151 01:36:56.943632 [Byte1]: 44
3152 01:36:56.948486
3153 01:36:56.949040 Set Vref, RX VrefLevel [Byte0]: 45
3154 01:36:56.951822 [Byte1]: 45
3155 01:36:56.956462
3156 01:36:56.957016 Set Vref, RX VrefLevel [Byte0]: 46
3157 01:36:56.959997 [Byte1]: 46
3158 01:36:56.964310
3159 01:36:56.964861 Set Vref, RX VrefLevel [Byte0]: 47
3160 01:36:56.967871 [Byte1]: 47
3161 01:36:56.972166
3162 01:36:56.972716 Set Vref, RX VrefLevel [Byte0]: 48
3163 01:36:56.975652 [Byte1]: 48
3164 01:36:56.980252
3165 01:36:56.980804 Set Vref, RX VrefLevel [Byte0]: 49
3166 01:36:56.983362 [Byte1]: 49
3167 01:36:56.988011
3168 01:36:56.988566 Set Vref, RX VrefLevel [Byte0]: 50
3169 01:36:56.991643 [Byte1]: 50
3170 01:36:56.996052
3171 01:36:56.996623 Set Vref, RX VrefLevel [Byte0]: 51
3172 01:36:56.999493 [Byte1]: 51
3173 01:36:57.004492
3174 01:36:57.005045 Set Vref, RX VrefLevel [Byte0]: 52
3175 01:36:57.007189 [Byte1]: 52
3176 01:36:57.011895
3177 01:36:57.012353 Set Vref, RX VrefLevel [Byte0]: 53
3178 01:36:57.015252 [Byte1]: 53
3179 01:36:57.019487
3180 01:36:57.019944 Set Vref, RX VrefLevel [Byte0]: 54
3181 01:36:57.022676 [Byte1]: 54
3182 01:36:57.027364
3183 01:36:57.027821 Set Vref, RX VrefLevel [Byte0]: 55
3184 01:36:57.030832 [Byte1]: 55
3185 01:36:57.035306
3186 01:36:57.035763 Set Vref, RX VrefLevel [Byte0]: 56
3187 01:36:57.038702 [Byte1]: 56
3188 01:36:57.043502
3189 01:36:57.044064 Set Vref, RX VrefLevel [Byte0]: 57
3190 01:36:57.046475 [Byte1]: 57
3191 01:36:57.051622
3192 01:36:57.052188 Set Vref, RX VrefLevel [Byte0]: 58
3193 01:36:57.054354 [Byte1]: 58
3194 01:36:57.059259
3195 01:36:57.059813 Set Vref, RX VrefLevel [Byte0]: 59
3196 01:36:57.062723 [Byte1]: 59
3197 01:36:57.066936
3198 01:36:57.067391 Set Vref, RX VrefLevel [Byte0]: 60
3199 01:36:57.070478 [Byte1]: 60
3200 01:36:57.075491
3201 01:36:57.076064 Set Vref, RX VrefLevel [Byte0]: 61
3202 01:36:57.078078 [Byte1]: 61
3203 01:36:57.082921
3204 01:36:57.083474 Set Vref, RX VrefLevel [Byte0]: 62
3205 01:36:57.086376 [Byte1]: 62
3206 01:36:57.091202
3207 01:36:57.091752 Set Vref, RX VrefLevel [Byte0]: 63
3208 01:36:57.094073 [Byte1]: 63
3209 01:36:57.099233
3210 01:36:57.099783 Set Vref, RX VrefLevel [Byte0]: 64
3211 01:36:57.101867 [Byte1]: 64
3212 01:36:57.106995
3213 01:36:57.107549 Set Vref, RX VrefLevel [Byte0]: 65
3214 01:36:57.110056 [Byte1]: 65
3215 01:36:57.114441
3216 01:36:57.114892 Set Vref, RX VrefLevel [Byte0]: 66
3217 01:36:57.118209 [Byte1]: 66
3218 01:36:57.122709
3219 01:36:57.123423 Set Vref, RX VrefLevel [Byte0]: 67
3220 01:36:57.125821 [Byte1]: 67
3221 01:36:57.131181
3222 01:36:57.131794 Final RX Vref Byte 0 = 52 to rank0
3223 01:36:57.134170 Final RX Vref Byte 1 = 48 to rank0
3224 01:36:57.137119 Final RX Vref Byte 0 = 52 to rank1
3225 01:36:57.140327 Final RX Vref Byte 1 = 48 to rank1==
3226 01:36:57.144328 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 01:36:57.150421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3228 01:36:57.150974 ==
3229 01:36:57.151394 DQS Delay:
3230 01:36:57.151732 DQS0 = 0, DQS1 = 0
3231 01:36:57.153560 DQM Delay:
3232 01:36:57.154105 DQM0 = 115, DQM1 = 104
3233 01:36:57.157253 DQ Delay:
3234 01:36:57.160242 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3235 01:36:57.163703 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3236 01:36:57.166838 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3237 01:36:57.170375 DQ12 =112, DQ13 =114, DQ14 =114, DQ15 =112
3238 01:36:57.170993
3239 01:36:57.171364
3240 01:36:57.177469 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3241 01:36:57.180778 CH1 RK0: MR19=404, MR18=1717
3242 01:36:57.187194 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3243 01:36:57.187750
3244 01:36:57.190266 ----->DramcWriteLeveling(PI) begin...
3245 01:36:57.190831 ==
3246 01:36:57.193411 Dram Type= 6, Freq= 0, CH_1, rank 1
3247 01:36:57.196963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3248 01:36:57.200447 ==
3249 01:36:57.200996 Write leveling (Byte 0): 21 => 21
3250 01:36:57.203876 Write leveling (Byte 1): 22 => 22
3251 01:36:57.206687 DramcWriteLeveling(PI) end<-----
3252 01:36:57.207145
3253 01:36:57.207496 ==
3254 01:36:57.210187 Dram Type= 6, Freq= 0, CH_1, rank 1
3255 01:36:57.216788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3256 01:36:57.217383 ==
3257 01:36:57.217755 [Gating] SW mode calibration
3258 01:36:57.226877 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3259 01:36:57.230115 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3260 01:36:57.236673 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3261 01:36:57.240029 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3262 01:36:57.243441 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3263 01:36:57.246859 0 11 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
3264 01:36:57.253470 0 11 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
3265 01:36:57.257065 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3266 01:36:57.260181 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3267 01:36:57.266970 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 01:36:57.270122 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 01:36:57.273350 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 01:36:57.280239 0 12 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
3271 01:36:57.283457 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3272 01:36:57.286649 0 12 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3273 01:36:57.293652 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 01:36:57.296734 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 01:36:57.300058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 01:36:57.306943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 01:36:57.309863 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 01:36:57.313396 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 01:36:57.319897 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3280 01:36:57.323207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3281 01:36:57.326460 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 01:36:57.333399 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 01:36:57.336799 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 01:36:57.340672 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 01:36:57.346580 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 01:36:57.350192 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 01:36:57.353466 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 01:36:57.356650 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 01:36:57.363882 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 01:36:57.366812 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 01:36:57.370369 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 01:36:57.376712 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 01:36:57.379802 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 01:36:57.383265 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 01:36:57.389881 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3296 01:36:57.393222 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3297 01:36:57.396650 Total UI for P1: 0, mck2ui 16
3298 01:36:57.399974 best dqsien dly found for B0: ( 0, 15, 12)
3299 01:36:57.403365 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3300 01:36:57.406609 Total UI for P1: 0, mck2ui 16
3301 01:36:57.409890 best dqsien dly found for B1: ( 0, 15, 14)
3302 01:36:57.413020 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3303 01:36:57.416648 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3304 01:36:57.417089
3305 01:36:57.423169 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3306 01:36:57.426275 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3307 01:36:57.429885 [Gating] SW calibration Done
3308 01:36:57.430304 ==
3309 01:36:57.433099 Dram Type= 6, Freq= 0, CH_1, rank 1
3310 01:36:57.436362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3311 01:36:57.436908 ==
3312 01:36:57.437274 RX Vref Scan: 0
3313 01:36:57.437670
3314 01:36:57.439807 RX Vref 0 -> 0, step: 1
3315 01:36:57.440266
3316 01:36:57.443068 RX Delay -40 -> 252, step: 8
3317 01:36:57.446828 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3318 01:36:57.449681 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3319 01:36:57.456693 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3320 01:36:57.460015 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3321 01:36:57.463412 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3322 01:36:57.466371 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3323 01:36:57.469986 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3324 01:36:57.473743 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3325 01:36:57.479838 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3326 01:36:57.483002 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3327 01:36:57.486442 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3328 01:36:57.489614 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3329 01:36:57.493137 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3330 01:36:57.499862 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3331 01:36:57.503294 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3332 01:36:57.506431 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3333 01:36:57.506886 ==
3334 01:36:57.509960 Dram Type= 6, Freq= 0, CH_1, rank 1
3335 01:36:57.512990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3336 01:36:57.516382 ==
3337 01:36:57.516933 DQS Delay:
3338 01:36:57.517332 DQS0 = 0, DQS1 = 0
3339 01:36:57.519723 DQM Delay:
3340 01:36:57.520319 DQM0 = 116, DQM1 = 105
3341 01:36:57.522969 DQ Delay:
3342 01:36:57.526255 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3343 01:36:57.529472 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3344 01:36:57.532770 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =103
3345 01:36:57.536062 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3346 01:36:57.536615
3347 01:36:57.536977
3348 01:36:57.537363 ==
3349 01:36:57.539554 Dram Type= 6, Freq= 0, CH_1, rank 1
3350 01:36:57.542817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3351 01:36:57.543373 ==
3352 01:36:57.543737
3353 01:36:57.545782
3354 01:36:57.546239 TX Vref Scan disable
3355 01:36:57.549475 == TX Byte 0 ==
3356 01:36:57.552726 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3357 01:36:57.555830 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3358 01:36:57.559536 == TX Byte 1 ==
3359 01:36:57.562793 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3360 01:36:57.565903 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3361 01:36:57.566367 ==
3362 01:36:57.568929 Dram Type= 6, Freq= 0, CH_1, rank 1
3363 01:36:57.576138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3364 01:36:57.576699 ==
3365 01:36:57.586202 TX Vref=22, minBit 9, minWin=25, winSum=423
3366 01:36:57.589730 TX Vref=24, minBit 9, minWin=25, winSum=426
3367 01:36:57.592949 TX Vref=26, minBit 9, minWin=25, winSum=428
3368 01:36:57.596149 TX Vref=28, minBit 3, minWin=26, winSum=430
3369 01:36:57.599590 TX Vref=30, minBit 8, minWin=26, winSum=432
3370 01:36:57.602943 TX Vref=32, minBit 9, minWin=26, winSum=432
3371 01:36:57.609664 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3372 01:36:57.610263
3373 01:36:57.612777 Final TX Range 1 Vref 30
3374 01:36:57.613241
3375 01:36:57.613656 ==
3376 01:36:57.616522 Dram Type= 6, Freq= 0, CH_1, rank 1
3377 01:36:57.619828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3378 01:36:57.620438 ==
3379 01:36:57.620816
3380 01:36:57.623067
3381 01:36:57.623527 TX Vref Scan disable
3382 01:36:57.626439 == TX Byte 0 ==
3383 01:36:57.629857 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3384 01:36:57.633141 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3385 01:36:57.636104 == TX Byte 1 ==
3386 01:36:57.640134 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3387 01:36:57.643149 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3388 01:36:57.643705
3389 01:36:57.646138 [DATLAT]
3390 01:36:57.646598 Freq=1200, CH1 RK1
3391 01:36:57.646968
3392 01:36:57.650202 DATLAT Default: 0xc
3393 01:36:57.650715 0, 0xFFFF, sum = 0
3394 01:36:57.652884 1, 0xFFFF, sum = 0
3395 01:36:57.653387 2, 0xFFFF, sum = 0
3396 01:36:57.656156 3, 0xFFFF, sum = 0
3397 01:36:57.656678 4, 0xFFFF, sum = 0
3398 01:36:57.659971 5, 0xFFFF, sum = 0
3399 01:36:57.660531 6, 0xFFFF, sum = 0
3400 01:36:57.663072 7, 0xFFFF, sum = 0
3401 01:36:57.663541 8, 0xFFFF, sum = 0
3402 01:36:57.666616 9, 0xFFFF, sum = 0
3403 01:36:57.669878 10, 0xFFFF, sum = 0
3404 01:36:57.670440 11, 0x0, sum = 1
3405 01:36:57.670814 12, 0x0, sum = 2
3406 01:36:57.672657 13, 0x0, sum = 3
3407 01:36:57.673123 14, 0x0, sum = 4
3408 01:36:57.676494 best_step = 12
3409 01:36:57.677059
3410 01:36:57.677456 ==
3411 01:36:57.679543 Dram Type= 6, Freq= 0, CH_1, rank 1
3412 01:36:57.682867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3413 01:36:57.683519 ==
3414 01:36:57.686121 RX Vref Scan: 0
3415 01:36:57.686576
3416 01:36:57.686933 RX Vref 0 -> 0, step: 1
3417 01:36:57.687265
3418 01:36:57.689657 RX Delay -29 -> 252, step: 4
3419 01:36:57.696585 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3420 01:36:57.700320 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3421 01:36:57.703643 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3422 01:36:57.706429 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3423 01:36:57.709880 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3424 01:36:57.716513 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3425 01:36:57.719693 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3426 01:36:57.722824 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3427 01:36:57.726134 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3428 01:36:57.729881 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3429 01:36:57.736230 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3430 01:36:57.739849 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3431 01:36:57.743178 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3432 01:36:57.746212 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3433 01:36:57.749538 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3434 01:36:57.755998 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3435 01:36:57.756581 ==
3436 01:36:57.759698 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 01:36:57.763218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3438 01:36:57.763779 ==
3439 01:36:57.764151 DQS Delay:
3440 01:36:57.765994 DQS0 = 0, DQS1 = 0
3441 01:36:57.766456 DQM Delay:
3442 01:36:57.769274 DQM0 = 115, DQM1 = 104
3443 01:36:57.769773 DQ Delay:
3444 01:36:57.772564 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3445 01:36:57.776206 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3446 01:36:57.779595 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3447 01:36:57.782823 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3448 01:36:57.783286
3449 01:36:57.783703
3450 01:36:57.792684 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3451 01:36:57.795827 CH1 RK1: MR19=404, MR18=606
3452 01:36:57.799513 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3453 01:36:57.802841 [RxdqsGatingPostProcess] freq 1200
3454 01:36:57.809319 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3455 01:36:57.812463 Pre-setting of DQS Precalculation
3456 01:36:57.815872 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3457 01:36:57.825811 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3458 01:36:57.832566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3459 01:36:57.833164
3460 01:36:57.833704
3461 01:36:57.835908 [Calibration Summary] 2400 Mbps
3462 01:36:57.836372 CH 0, Rank 0
3463 01:36:57.839220 SW Impedance : PASS
3464 01:36:57.839685 DUTY Scan : NO K
3465 01:36:57.842673 ZQ Calibration : PASS
3466 01:36:57.845971 Jitter Meter : NO K
3467 01:36:57.846434 CBT Training : PASS
3468 01:36:57.849653 Write leveling : PASS
3469 01:36:57.852647 RX DQS gating : PASS
3470 01:36:57.853106 RX DQ/DQS(RDDQC) : PASS
3471 01:36:57.855991 TX DQ/DQS : PASS
3472 01:36:57.859203 RX DATLAT : PASS
3473 01:36:57.859620 RX DQ/DQS(Engine): PASS
3474 01:36:57.862584 TX OE : NO K
3475 01:36:57.863004 All Pass.
3476 01:36:57.863334
3477 01:36:57.865992 CH 0, Rank 1
3478 01:36:57.866408 SW Impedance : PASS
3479 01:36:57.869094 DUTY Scan : NO K
3480 01:36:57.869632 ZQ Calibration : PASS
3481 01:36:57.872605 Jitter Meter : NO K
3482 01:36:57.875854 CBT Training : PASS
3483 01:36:57.876579 Write leveling : PASS
3484 01:36:57.879270 RX DQS gating : PASS
3485 01:36:57.882736 RX DQ/DQS(RDDQC) : PASS
3486 01:36:57.883149 TX DQ/DQS : PASS
3487 01:36:57.885946 RX DATLAT : PASS
3488 01:36:57.889413 RX DQ/DQS(Engine): PASS
3489 01:36:57.889825 TX OE : NO K
3490 01:36:57.893134 All Pass.
3491 01:36:57.894085
3492 01:36:57.894562 CH 1, Rank 0
3493 01:36:57.896173 SW Impedance : PASS
3494 01:36:57.896638 DUTY Scan : NO K
3495 01:36:57.899313 ZQ Calibration : PASS
3496 01:36:57.902642 Jitter Meter : NO K
3497 01:36:57.903099 CBT Training : PASS
3498 01:36:57.905872 Write leveling : PASS
3499 01:36:57.909224 RX DQS gating : PASS
3500 01:36:57.909716 RX DQ/DQS(RDDQC) : PASS
3501 01:36:57.912830 TX DQ/DQS : PASS
3502 01:36:57.913243 RX DATLAT : PASS
3503 01:36:57.915812 RX DQ/DQS(Engine): PASS
3504 01:36:57.919279 TX OE : NO K
3505 01:36:57.919692 All Pass.
3506 01:36:57.920016
3507 01:36:57.920319 CH 1, Rank 1
3508 01:36:57.922568 SW Impedance : PASS
3509 01:36:57.925864 DUTY Scan : NO K
3510 01:36:57.926547 ZQ Calibration : PASS
3511 01:36:57.929153 Jitter Meter : NO K
3512 01:36:57.932430 CBT Training : PASS
3513 01:36:57.932852 Write leveling : PASS
3514 01:36:57.935702 RX DQS gating : PASS
3515 01:36:57.939333 RX DQ/DQS(RDDQC) : PASS
3516 01:36:57.939896 TX DQ/DQS : PASS
3517 01:36:57.942335 RX DATLAT : PASS
3518 01:36:57.945968 RX DQ/DQS(Engine): PASS
3519 01:36:57.946473 TX OE : NO K
3520 01:36:57.949099 All Pass.
3521 01:36:57.949563
3522 01:36:57.949898 DramC Write-DBI off
3523 01:36:57.952621 PER_BANK_REFRESH: Hybrid Mode
3524 01:36:57.953135 TX_TRACKING: ON
3525 01:36:57.962581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3526 01:36:57.965773 [FAST_K] Save calibration result to emmc
3527 01:36:57.969154 dramc_set_vcore_voltage set vcore to 650000
3528 01:36:57.972183 Read voltage for 600, 5
3529 01:36:57.972599 Vio18 = 0
3530 01:36:57.975733 Vcore = 650000
3531 01:36:57.976243 Vdram = 0
3532 01:36:57.976576 Vddq = 0
3533 01:36:57.978914 Vmddr = 0
3534 01:36:57.982354 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3535 01:36:57.989067 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3536 01:36:57.989638 MEM_TYPE=3, freq_sel=19
3537 01:36:57.992665 sv_algorithm_assistance_LP4_1600
3538 01:36:57.995659 ============ PULL DRAM RESETB DOWN ============
3539 01:36:58.002188 ========== PULL DRAM RESETB DOWN end =========
3540 01:36:58.005611 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3541 01:36:58.008752 ===================================
3542 01:36:58.012555 LPDDR4 DRAM CONFIGURATION
3543 01:36:58.015859 ===================================
3544 01:36:58.016370 EX_ROW_EN[0] = 0x0
3545 01:36:58.019092 EX_ROW_EN[1] = 0x0
3546 01:36:58.019608 LP4Y_EN = 0x0
3547 01:36:58.022296 WORK_FSP = 0x0
3548 01:36:58.025477 WL = 0x2
3549 01:36:58.025897 RL = 0x2
3550 01:36:58.028802 BL = 0x2
3551 01:36:58.029220 RPST = 0x0
3552 01:36:58.032262 RD_PRE = 0x0
3553 01:36:58.032772 WR_PRE = 0x1
3554 01:36:58.035510 WR_PST = 0x0
3555 01:36:58.036026 DBI_WR = 0x0
3556 01:36:58.038922 DBI_RD = 0x0
3557 01:36:58.039437 OTF = 0x1
3558 01:36:58.042299 ===================================
3559 01:36:58.045326 ===================================
3560 01:36:58.048830 ANA top config
3561 01:36:58.052047 ===================================
3562 01:36:58.052566 DLL_ASYNC_EN = 0
3563 01:36:58.055512 ALL_SLAVE_EN = 1
3564 01:36:58.058739 NEW_RANK_MODE = 1
3565 01:36:58.062004 DLL_IDLE_MODE = 1
3566 01:36:58.065397 LP45_APHY_COMB_EN = 1
3567 01:36:58.065910 TX_ODT_DIS = 1
3568 01:36:58.068651 NEW_8X_MODE = 1
3569 01:36:58.072000 ===================================
3570 01:36:58.075427 ===================================
3571 01:36:58.078798 data_rate = 1200
3572 01:36:58.081871 CKR = 1
3573 01:36:58.085395 DQ_P2S_RATIO = 8
3574 01:36:58.088296 ===================================
3575 01:36:58.088829 CA_P2S_RATIO = 8
3576 01:36:58.091679 DQ_CA_OPEN = 0
3577 01:36:58.094961 DQ_SEMI_OPEN = 0
3578 01:36:58.098448 CA_SEMI_OPEN = 0
3579 01:36:58.102106 CA_FULL_RATE = 0
3580 01:36:58.104780 DQ_CKDIV4_EN = 1
3581 01:36:58.105204 CA_CKDIV4_EN = 1
3582 01:36:58.108150 CA_PREDIV_EN = 0
3583 01:36:58.111423 PH8_DLY = 0
3584 01:36:58.114670 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3585 01:36:58.118296 DQ_AAMCK_DIV = 4
3586 01:36:58.121159 CA_AAMCK_DIV = 4
3587 01:36:58.121646 CA_ADMCK_DIV = 4
3588 01:36:58.125060 DQ_TRACK_CA_EN = 0
3589 01:36:58.127944 CA_PICK = 600
3590 01:36:58.131414 CA_MCKIO = 600
3591 01:36:58.134321 MCKIO_SEMI = 0
3592 01:36:58.138044 PLL_FREQ = 2288
3593 01:36:58.141492 DQ_UI_PI_RATIO = 32
3594 01:36:58.144286 CA_UI_PI_RATIO = 0
3595 01:36:58.147836 ===================================
3596 01:36:58.151145 ===================================
3597 01:36:58.151705 memory_type:LPDDR4
3598 01:36:58.154421 GP_NUM : 10
3599 01:36:58.157464 SRAM_EN : 1
3600 01:36:58.157930 MD32_EN : 0
3601 01:36:58.160859 ===================================
3602 01:36:58.164296 [ANA_INIT] >>>>>>>>>>>>>>
3603 01:36:58.167588 <<<<<< [CONFIGURE PHASE]: ANA_TX
3604 01:36:58.170921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3605 01:36:58.174070 ===================================
3606 01:36:58.177478 data_rate = 1200,PCW = 0X5800
3607 01:36:58.180957 ===================================
3608 01:36:58.184116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3609 01:36:58.187534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3610 01:36:58.193927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3611 01:36:58.197645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3612 01:36:58.200794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3613 01:36:58.204065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3614 01:36:58.207243 [ANA_INIT] flow start
3615 01:36:58.210608 [ANA_INIT] PLL >>>>>>>>
3616 01:36:58.211076 [ANA_INIT] PLL <<<<<<<<
3617 01:36:58.213601 [ANA_INIT] MIDPI >>>>>>>>
3618 01:36:58.217446 [ANA_INIT] MIDPI <<<<<<<<
3619 01:36:58.220639 [ANA_INIT] DLL >>>>>>>>
3620 01:36:58.221194 [ANA_INIT] flow end
3621 01:36:58.223742 ============ LP4 DIFF to SE enter ============
3622 01:36:58.230253 ============ LP4 DIFF to SE exit ============
3623 01:36:58.230713 [ANA_INIT] <<<<<<<<<<<<<
3624 01:36:58.233626 [Flow] Enable top DCM control >>>>>
3625 01:36:58.237425 [Flow] Enable top DCM control <<<<<
3626 01:36:58.240584 Enable DLL master slave shuffle
3627 01:36:58.246947 ==============================================================
3628 01:36:58.247506 Gating Mode config
3629 01:36:58.253544 ==============================================================
3630 01:36:58.257105 Config description:
3631 01:36:58.267131 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3632 01:36:58.273349 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3633 01:36:58.276760 SELPH_MODE 0: By rank 1: By Phase
3634 01:36:58.283378 ==============================================================
3635 01:36:58.286848 GAT_TRACK_EN = 1
3636 01:36:58.287405 RX_GATING_MODE = 2
3637 01:36:58.290062 RX_GATING_TRACK_MODE = 2
3638 01:36:58.293370 SELPH_MODE = 1
3639 01:36:58.296688 PICG_EARLY_EN = 1
3640 01:36:58.300090 VALID_LAT_VALUE = 1
3641 01:36:58.306649 ==============================================================
3642 01:36:58.309578 Enter into Gating configuration >>>>
3643 01:36:58.313041 Exit from Gating configuration <<<<
3644 01:36:58.316393 Enter into DVFS_PRE_config >>>>>
3645 01:36:58.326274 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3646 01:36:58.329514 Exit from DVFS_PRE_config <<<<<
3647 01:36:58.332694 Enter into PICG configuration >>>>
3648 01:36:58.336338 Exit from PICG configuration <<<<
3649 01:36:58.339910 [RX_INPUT] configuration >>>>>
3650 01:36:58.342981 [RX_INPUT] configuration <<<<<
3651 01:36:58.346076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3652 01:36:58.352794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3653 01:36:58.359432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3654 01:36:58.365622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3655 01:36:58.369231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3656 01:36:58.375966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3657 01:36:58.379473 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3658 01:36:58.385677 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3659 01:36:58.389147 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3660 01:36:58.392497 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3661 01:36:58.395761 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3662 01:36:58.402268 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3663 01:36:58.405823 ===================================
3664 01:36:58.408690 LPDDR4 DRAM CONFIGURATION
3665 01:36:58.412380 ===================================
3666 01:36:58.412859 EX_ROW_EN[0] = 0x0
3667 01:36:58.415975 EX_ROW_EN[1] = 0x0
3668 01:36:58.416431 LP4Y_EN = 0x0
3669 01:36:58.419029 WORK_FSP = 0x0
3670 01:36:58.419482 WL = 0x2
3671 01:36:58.422490 RL = 0x2
3672 01:36:58.423053 BL = 0x2
3673 01:36:58.425855 RPST = 0x0
3674 01:36:58.426405 RD_PRE = 0x0
3675 01:36:58.428860 WR_PRE = 0x1
3676 01:36:58.429402 WR_PST = 0x0
3677 01:36:58.432007 DBI_WR = 0x0
3678 01:36:58.432557 DBI_RD = 0x0
3679 01:36:58.435176 OTF = 0x1
3680 01:36:58.438461 ===================================
3681 01:36:58.441772 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3682 01:36:58.445240 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3683 01:36:58.451999 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3684 01:36:58.455801 ===================================
3685 01:36:58.456353 LPDDR4 DRAM CONFIGURATION
3686 01:36:58.458447 ===================================
3687 01:36:58.461958 EX_ROW_EN[0] = 0x10
3688 01:36:58.464963 EX_ROW_EN[1] = 0x0
3689 01:36:58.465446 LP4Y_EN = 0x0
3690 01:36:58.468331 WORK_FSP = 0x0
3691 01:36:58.468796 WL = 0x2
3692 01:36:58.471968 RL = 0x2
3693 01:36:58.472524 BL = 0x2
3694 01:36:58.475114 RPST = 0x0
3695 01:36:58.475668 RD_PRE = 0x0
3696 01:36:58.478667 WR_PRE = 0x1
3697 01:36:58.479216 WR_PST = 0x0
3698 01:36:58.481572 DBI_WR = 0x0
3699 01:36:58.482024 DBI_RD = 0x0
3700 01:36:58.485006 OTF = 0x1
3701 01:36:58.488551 ===================================
3702 01:36:58.494940 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3703 01:36:58.498307 nWR fixed to 30
3704 01:36:58.502043 [ModeRegInit_LP4] CH0 RK0
3705 01:36:58.502604 [ModeRegInit_LP4] CH0 RK1
3706 01:36:58.504956 [ModeRegInit_LP4] CH1 RK0
3707 01:36:58.508172 [ModeRegInit_LP4] CH1 RK1
3708 01:36:58.508628 match AC timing 16
3709 01:36:58.514755 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3710 01:36:58.518168 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3711 01:36:58.521695 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3712 01:36:58.528206 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3713 01:36:58.531700 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3714 01:36:58.532160 ==
3715 01:36:58.534834 Dram Type= 6, Freq= 0, CH_0, rank 0
3716 01:36:58.537910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3717 01:36:58.538368 ==
3718 01:36:58.544826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3719 01:36:58.551415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3720 01:36:58.554592 [CA 0] Center 35 (5~66) winsize 62
3721 01:36:58.557893 [CA 1] Center 35 (5~66) winsize 62
3722 01:36:58.560979 [CA 2] Center 34 (4~65) winsize 62
3723 01:36:58.564720 [CA 3] Center 34 (4~65) winsize 62
3724 01:36:58.567970 [CA 4] Center 33 (3~64) winsize 62
3725 01:36:58.571322 [CA 5] Center 33 (3~64) winsize 62
3726 01:36:58.571882
3727 01:36:58.574265 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3728 01:36:58.574725
3729 01:36:58.577515 [CATrainingPosCal] consider 1 rank data
3730 01:36:58.580860 u2DelayCellTimex100 = 270/100 ps
3731 01:36:58.584173 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3732 01:36:58.587874 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3733 01:36:58.590945 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3734 01:36:58.594152 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3735 01:36:58.597793 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3736 01:36:58.604497 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3737 01:36:58.605056
3738 01:36:58.607595 CA PerBit enable=1, Macro0, CA PI delay=33
3739 01:36:58.608156
3740 01:36:58.610713 [CBTSetCACLKResult] CA Dly = 33
3741 01:36:58.611189 CS Dly: 5 (0~36)
3742 01:36:58.611550 ==
3743 01:36:58.614104 Dram Type= 6, Freq= 0, CH_0, rank 1
3744 01:36:58.617693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3745 01:36:58.620810 ==
3746 01:36:58.623855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3747 01:36:58.630786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3748 01:36:58.633917 [CA 0] Center 36 (6~66) winsize 61
3749 01:36:58.637679 [CA 1] Center 35 (5~66) winsize 62
3750 01:36:58.641002 [CA 2] Center 34 (4~65) winsize 62
3751 01:36:58.643855 [CA 3] Center 34 (4~65) winsize 62
3752 01:36:58.647407 [CA 4] Center 33 (3~64) winsize 62
3753 01:36:58.650516 [CA 5] Center 33 (3~64) winsize 62
3754 01:36:58.650970
3755 01:36:58.654059 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3756 01:36:58.654516
3757 01:36:58.657395 [CATrainingPosCal] consider 2 rank data
3758 01:36:58.660705 u2DelayCellTimex100 = 270/100 ps
3759 01:36:58.663940 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3760 01:36:58.667587 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3761 01:36:58.670806 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3762 01:36:58.677221 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3763 01:36:58.680645 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3764 01:36:58.683881 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3765 01:36:58.684439
3766 01:36:58.687266 CA PerBit enable=1, Macro0, CA PI delay=33
3767 01:36:58.687818
3768 01:36:58.690318 [CBTSetCACLKResult] CA Dly = 33
3769 01:36:58.690772 CS Dly: 4 (0~35)
3770 01:36:58.691134
3771 01:36:58.693428 ----->DramcWriteLeveling(PI) begin...
3772 01:36:58.693890 ==
3773 01:36:58.696590 Dram Type= 6, Freq= 0, CH_0, rank 0
3774 01:36:58.703729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3775 01:36:58.704283 ==
3776 01:36:58.707088 Write leveling (Byte 0): 29 => 29
3777 01:36:58.709815 Write leveling (Byte 1): 29 => 29
3778 01:36:58.713591 DramcWriteLeveling(PI) end<-----
3779 01:36:58.714147
3780 01:36:58.714506 ==
3781 01:36:58.717096 Dram Type= 6, Freq= 0, CH_0, rank 0
3782 01:36:58.720134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3783 01:36:58.720689 ==
3784 01:36:58.723328 [Gating] SW mode calibration
3785 01:36:58.729903 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3786 01:36:58.733401 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3787 01:36:58.740153 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3788 01:36:58.743136 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3789 01:36:58.746192 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
3790 01:36:58.753242 0 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3791 01:36:58.756822 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 01:36:58.759623 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3793 01:36:58.766341 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 01:36:58.769426 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 01:36:58.773140 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 01:36:58.779568 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 01:36:58.782831 0 6 8 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
3798 01:36:58.786217 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3799 01:36:58.793100 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 01:36:58.795945 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 01:36:58.799794 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 01:36:58.806128 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 01:36:58.809338 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 01:36:58.812593 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 01:36:58.819770 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3806 01:36:58.822780 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3807 01:36:58.825618 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 01:36:58.832264 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 01:36:58.835603 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 01:36:58.839116 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 01:36:58.846014 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 01:36:58.848760 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 01:36:58.852161 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 01:36:58.858574 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 01:36:58.861883 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 01:36:58.865557 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 01:36:58.872532 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 01:36:58.875126 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 01:36:58.878628 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 01:36:58.885222 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 01:36:58.888658 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3822 01:36:58.891856 Total UI for P1: 0, mck2ui 16
3823 01:36:58.895111 best dqsien dly found for B0: ( 0, 9, 6)
3824 01:36:58.898403 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3825 01:36:58.905224 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3826 01:36:58.905816 Total UI for P1: 0, mck2ui 16
3827 01:36:58.911699 best dqsien dly found for B1: ( 0, 9, 10)
3828 01:36:58.914810 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3829 01:36:58.918233 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3830 01:36:58.918791
3831 01:36:58.921750 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3832 01:36:58.925042 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3833 01:36:58.928123 [Gating] SW calibration Done
3834 01:36:58.928578 ==
3835 01:36:58.931388 Dram Type= 6, Freq= 0, CH_0, rank 0
3836 01:36:58.934619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3837 01:36:58.935227 ==
3838 01:36:58.938278 RX Vref Scan: 0
3839 01:36:58.938821
3840 01:36:58.939320 RX Vref 0 -> 0, step: 1
3841 01:36:58.939801
3842 01:36:58.941363 RX Delay -230 -> 252, step: 16
3843 01:36:58.948108 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3844 01:36:58.951028 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3845 01:36:58.954588 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3846 01:36:58.957858 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3847 01:36:58.964639 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3848 01:36:58.967825 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3849 01:36:58.971060 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3850 01:36:58.974165 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3851 01:36:58.977898 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3852 01:36:58.984343 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3853 01:36:58.987967 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3854 01:36:58.990921 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3855 01:36:58.994315 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3856 01:36:59.000843 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3857 01:36:59.004423 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3858 01:36:59.007486 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3859 01:36:59.008165 ==
3860 01:36:59.010738 Dram Type= 6, Freq= 0, CH_0, rank 0
3861 01:36:59.013850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3862 01:36:59.017357 ==
3863 01:36:59.017810 DQS Delay:
3864 01:36:59.018169 DQS0 = 0, DQS1 = 0
3865 01:36:59.020688 DQM Delay:
3866 01:36:59.021236 DQM0 = 38, DQM1 = 33
3867 01:36:59.024019 DQ Delay:
3868 01:36:59.027178 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3869 01:36:59.027891 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3870 01:36:59.030474 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3871 01:36:59.033766 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3872 01:36:59.037382
3873 01:36:59.037835
3874 01:36:59.038189 ==
3875 01:36:59.040434 Dram Type= 6, Freq= 0, CH_0, rank 0
3876 01:36:59.043726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3877 01:36:59.044245 ==
3878 01:36:59.044604
3879 01:36:59.044933
3880 01:36:59.047281 TX Vref Scan disable
3881 01:36:59.047890 == TX Byte 0 ==
3882 01:36:59.053518 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3883 01:36:59.057017 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3884 01:36:59.057657 == TX Byte 1 ==
3885 01:36:59.063521 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3886 01:36:59.066746 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3887 01:36:59.067251 ==
3888 01:36:59.070282 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 01:36:59.073262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3890 01:36:59.073757 ==
3891 01:36:59.074115
3892 01:36:59.074442
3893 01:36:59.076986 TX Vref Scan disable
3894 01:36:59.080169 == TX Byte 0 ==
3895 01:36:59.083354 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3896 01:36:59.089870 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3897 01:36:59.090361 == TX Byte 1 ==
3898 01:36:59.093271 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3899 01:36:59.099774 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3900 01:36:59.100325
3901 01:36:59.100684 [DATLAT]
3902 01:36:59.101017 Freq=600, CH0 RK0
3903 01:36:59.101372
3904 01:36:59.102921 DATLAT Default: 0x9
3905 01:36:59.103377 0, 0xFFFF, sum = 0
3906 01:36:59.106467 1, 0xFFFF, sum = 0
3907 01:36:59.109852 2, 0xFFFF, sum = 0
3908 01:36:59.110312 3, 0xFFFF, sum = 0
3909 01:36:59.113364 4, 0xFFFF, sum = 0
3910 01:36:59.113928 5, 0xFFFF, sum = 0
3911 01:36:59.116169 6, 0xFFFF, sum = 0
3912 01:36:59.116630 7, 0x0, sum = 1
3913 01:36:59.116998 8, 0x0, sum = 2
3914 01:36:59.119718 9, 0x0, sum = 3
3915 01:36:59.120182 10, 0x0, sum = 4
3916 01:36:59.123238 best_step = 8
3917 01:36:59.123690
3918 01:36:59.124047 ==
3919 01:36:59.126234 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 01:36:59.129782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3921 01:36:59.130401 ==
3922 01:36:59.132736 RX Vref Scan: 1
3923 01:36:59.133399
3924 01:36:59.133777 RX Vref 0 -> 0, step: 1
3925 01:36:59.134117
3926 01:36:59.136211 RX Delay -195 -> 252, step: 8
3927 01:36:59.136666
3928 01:36:59.139745 Set Vref, RX VrefLevel [Byte0]: 51
3929 01:36:59.142634 [Byte1]: 48
3930 01:36:59.146878
3931 01:36:59.147332 Final RX Vref Byte 0 = 51 to rank0
3932 01:36:59.150580 Final RX Vref Byte 1 = 48 to rank0
3933 01:36:59.153743 Final RX Vref Byte 0 = 51 to rank1
3934 01:36:59.157116 Final RX Vref Byte 1 = 48 to rank1==
3935 01:36:59.160253 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 01:36:59.166844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3937 01:36:59.167299 ==
3938 01:36:59.167657 DQS Delay:
3939 01:36:59.170090 DQS0 = 0, DQS1 = 0
3940 01:36:59.170559 DQM Delay:
3941 01:36:59.170916 DQM0 = 40, DQM1 = 29
3942 01:36:59.173844 DQ Delay:
3943 01:36:59.176798 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3944 01:36:59.180170 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
3945 01:36:59.183479 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3946 01:36:59.186508 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3947 01:36:59.186941
3948 01:36:59.187365
3949 01:36:59.193248 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3950 01:36:59.196975 CH0 RK0: MR19=808, MR18=4B4B
3951 01:36:59.203341 CH0_RK0: MR19=0x808, MR18=0x4B4B, DQSOSC=395, MR23=63, INC=168, DEC=112
3952 01:36:59.203852
3953 01:36:59.206643 ----->DramcWriteLeveling(PI) begin...
3954 01:36:59.207117 ==
3955 01:36:59.209791 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 01:36:59.213361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3957 01:36:59.213776 ==
3958 01:36:59.216635 Write leveling (Byte 0): 29 => 29
3959 01:36:59.220208 Write leveling (Byte 1): 29 => 29
3960 01:36:59.223196 DramcWriteLeveling(PI) end<-----
3961 01:36:59.223621
3962 01:36:59.223944 ==
3963 01:36:59.226541 Dram Type= 6, Freq= 0, CH_0, rank 1
3964 01:36:59.229811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3965 01:36:59.230228 ==
3966 01:36:59.233131 [Gating] SW mode calibration
3967 01:36:59.239656 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3968 01:36:59.246525 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3969 01:36:59.249725 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 01:36:59.256718 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 01:36:59.259661 0 5 8 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 0)
3972 01:36:59.262823 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3973 01:36:59.269479 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 01:36:59.272799 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 01:36:59.276140 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 01:36:59.282845 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 01:36:59.286215 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 01:36:59.289563 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 01:36:59.296271 0 6 8 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
3980 01:36:59.299743 0 6 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3981 01:36:59.302792 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 01:36:59.309097 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 01:36:59.312427 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 01:36:59.315768 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 01:36:59.322188 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 01:36:59.325624 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 01:36:59.329029 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3988 01:36:59.335665 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 01:36:59.338783 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 01:36:59.342076 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 01:36:59.349127 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 01:36:59.352967 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 01:36:59.355513 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 01:36:59.358876 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 01:36:59.365809 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 01:36:59.368901 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 01:36:59.372161 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 01:36:59.378482 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 01:36:59.381954 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 01:36:59.385481 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 01:36:59.392246 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 01:36:59.395474 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 01:36:59.398690 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4004 01:36:59.401969 Total UI for P1: 0, mck2ui 16
4005 01:36:59.405564 best dqsien dly found for B0: ( 0, 9, 6)
4006 01:36:59.411633 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 01:36:59.414923 Total UI for P1: 0, mck2ui 16
4008 01:36:59.418354 best dqsien dly found for B1: ( 0, 9, 8)
4009 01:36:59.421736 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4010 01:36:59.425022 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4011 01:36:59.425673
4012 01:36:59.428495 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4013 01:36:59.431396 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4014 01:36:59.434848 [Gating] SW calibration Done
4015 01:36:59.435310 ==
4016 01:36:59.438117 Dram Type= 6, Freq= 0, CH_0, rank 1
4017 01:36:59.441414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4018 01:36:59.441875 ==
4019 01:36:59.444951 RX Vref Scan: 0
4020 01:36:59.445440
4021 01:36:59.445821 RX Vref 0 -> 0, step: 1
4022 01:36:59.446166
4023 01:36:59.448153 RX Delay -230 -> 252, step: 16
4024 01:36:59.454671 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4025 01:36:59.458439 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4026 01:36:59.461351 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4027 01:36:59.465231 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4028 01:36:59.468351 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4029 01:36:59.474838 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4030 01:36:59.477976 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4031 01:36:59.481536 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4032 01:36:59.484873 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4033 01:36:59.491305 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4034 01:36:59.494594 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4035 01:36:59.497648 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4036 01:36:59.501508 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4037 01:36:59.507921 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4038 01:36:59.510886 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4039 01:36:59.514243 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4040 01:36:59.514799 ==
4041 01:36:59.518083 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 01:36:59.520838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4043 01:36:59.524377 ==
4044 01:36:59.524939 DQS Delay:
4045 01:36:59.525357 DQS0 = 0, DQS1 = 0
4046 01:36:59.527825 DQM Delay:
4047 01:36:59.528443 DQM0 = 43, DQM1 = 33
4048 01:36:59.530659 DQ Delay:
4049 01:36:59.534087 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4050 01:36:59.534681 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4051 01:36:59.537675 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4052 01:36:59.540698 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4053 01:36:59.544180
4054 01:36:59.544747
4055 01:36:59.545119 ==
4056 01:36:59.547511 Dram Type= 6, Freq= 0, CH_0, rank 1
4057 01:36:59.550609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4058 01:36:59.551074 ==
4059 01:36:59.551437
4060 01:36:59.551771
4061 01:36:59.554016 TX Vref Scan disable
4062 01:36:59.554517 == TX Byte 0 ==
4063 01:36:59.560885 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4064 01:36:59.564009 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4065 01:36:59.564586 == TX Byte 1 ==
4066 01:36:59.570804 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4067 01:36:59.574247 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4068 01:36:59.574748 ==
4069 01:36:59.576855 Dram Type= 6, Freq= 0, CH_0, rank 1
4070 01:36:59.580518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4071 01:36:59.581078 ==
4072 01:36:59.581480
4073 01:36:59.583466
4074 01:36:59.583912 TX Vref Scan disable
4075 01:36:59.586853 == TX Byte 0 ==
4076 01:36:59.590635 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4077 01:36:59.597318 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4078 01:36:59.597882 == TX Byte 1 ==
4079 01:36:59.600356 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4080 01:36:59.607202 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4081 01:36:59.607758
4082 01:36:59.608119 [DATLAT]
4083 01:36:59.608451 Freq=600, CH0 RK1
4084 01:36:59.608774
4085 01:36:59.610105 DATLAT Default: 0x8
4086 01:36:59.610559 0, 0xFFFF, sum = 0
4087 01:36:59.613471 1, 0xFFFF, sum = 0
4088 01:36:59.613934 2, 0xFFFF, sum = 0
4089 01:36:59.616902 3, 0xFFFF, sum = 0
4090 01:36:59.620457 4, 0xFFFF, sum = 0
4091 01:36:59.621030 5, 0xFFFF, sum = 0
4092 01:36:59.623578 6, 0xFFFF, sum = 0
4093 01:36:59.624139 7, 0x0, sum = 1
4094 01:36:59.624502 8, 0x0, sum = 2
4095 01:36:59.626851 9, 0x0, sum = 3
4096 01:36:59.627315 10, 0x0, sum = 4
4097 01:36:59.630059 best_step = 8
4098 01:36:59.630605
4099 01:36:59.630965 ==
4100 01:36:59.633117 Dram Type= 6, Freq= 0, CH_0, rank 1
4101 01:36:59.636525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4102 01:36:59.636982 ==
4103 01:36:59.639802 RX Vref Scan: 0
4104 01:36:59.640253
4105 01:36:59.640611 RX Vref 0 -> 0, step: 1
4106 01:36:59.640947
4107 01:36:59.643203 RX Delay -195 -> 252, step: 8
4108 01:36:59.650503 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4109 01:36:59.654112 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4110 01:36:59.657034 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4111 01:36:59.660703 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4112 01:36:59.667438 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4113 01:36:59.670568 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4114 01:36:59.673928 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4115 01:36:59.677102 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4116 01:36:59.680665 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4117 01:36:59.687461 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4118 01:36:59.690456 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4119 01:36:59.693907 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4120 01:36:59.697101 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4121 01:36:59.703780 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4122 01:36:59.707356 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4123 01:36:59.710589 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4124 01:36:59.711140 ==
4125 01:36:59.713576 Dram Type= 6, Freq= 0, CH_0, rank 1
4126 01:36:59.720365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4127 01:36:59.720921 ==
4128 01:36:59.721284 DQS Delay:
4129 01:36:59.721652 DQS0 = 0, DQS1 = 0
4130 01:36:59.723253 DQM Delay:
4131 01:36:59.723704 DQM0 = 42, DQM1 = 32
4132 01:36:59.726968 DQ Delay:
4133 01:36:59.730373 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4134 01:36:59.730925 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4135 01:36:59.733405 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4136 01:36:59.740194 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4137 01:36:59.740758
4138 01:36:59.741123
4139 01:36:59.746734 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4140 01:36:59.749841 CH0 RK1: MR19=808, MR18=6C6C
4141 01:36:59.756601 CH0_RK1: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4142 01:36:59.759936 [RxdqsGatingPostProcess] freq 600
4143 01:36:59.763521 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4144 01:36:59.766576 Pre-setting of DQS Precalculation
4145 01:36:59.773139 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4146 01:36:59.773844 ==
4147 01:36:59.776450 Dram Type= 6, Freq= 0, CH_1, rank 0
4148 01:36:59.779932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4149 01:36:59.780564 ==
4150 01:36:59.786342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4151 01:36:59.793003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4152 01:36:59.795919 [CA 0] Center 35 (5~66) winsize 62
4153 01:36:59.799513 [CA 1] Center 35 (5~65) winsize 61
4154 01:36:59.802805 [CA 2] Center 33 (3~64) winsize 62
4155 01:36:59.806542 [CA 3] Center 33 (3~64) winsize 62
4156 01:36:59.809738 [CA 4] Center 33 (2~64) winsize 63
4157 01:36:59.810295 [CA 5] Center 33 (2~64) winsize 63
4158 01:36:59.812639
4159 01:36:59.816078 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4160 01:36:59.816638
4161 01:36:59.819590 [CATrainingPosCal] consider 1 rank data
4162 01:36:59.822852 u2DelayCellTimex100 = 270/100 ps
4163 01:36:59.825980 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4164 01:36:59.829032 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4165 01:36:59.832620 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4166 01:36:59.835627 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4167 01:36:59.838851 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4168 01:36:59.842467 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4169 01:36:59.842922
4170 01:36:59.848762 CA PerBit enable=1, Macro0, CA PI delay=33
4171 01:36:59.849216
4172 01:36:59.849624 [CBTSetCACLKResult] CA Dly = 33
4173 01:36:59.852573 CS Dly: 5 (0~36)
4174 01:36:59.853137 ==
4175 01:36:59.855836 Dram Type= 6, Freq= 0, CH_1, rank 1
4176 01:36:59.859064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4177 01:36:59.859623 ==
4178 01:36:59.865396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4179 01:36:59.872090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4180 01:36:59.875383 [CA 0] Center 35 (5~66) winsize 62
4181 01:36:59.878979 [CA 1] Center 34 (4~65) winsize 62
4182 01:36:59.881821 [CA 2] Center 33 (3~64) winsize 62
4183 01:36:59.885456 [CA 3] Center 33 (3~64) winsize 62
4184 01:36:59.888738 [CA 4] Center 32 (2~63) winsize 62
4185 01:36:59.891991 [CA 5] Center 32 (2~63) winsize 62
4186 01:36:59.892549
4187 01:36:59.895442 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4188 01:36:59.895994
4189 01:36:59.898269 [CATrainingPosCal] consider 2 rank data
4190 01:36:59.902131 u2DelayCellTimex100 = 270/100 ps
4191 01:36:59.905143 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4192 01:36:59.908562 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4193 01:36:59.911444 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4194 01:36:59.914893 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4195 01:36:59.918316 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4196 01:36:59.924981 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4197 01:36:59.925549
4198 01:36:59.928208 CA PerBit enable=1, Macro0, CA PI delay=32
4199 01:36:59.928761
4200 01:36:59.931421 [CBTSetCACLKResult] CA Dly = 32
4201 01:36:59.931878 CS Dly: 4 (0~35)
4202 01:36:59.932238
4203 01:36:59.934571 ----->DramcWriteLeveling(PI) begin...
4204 01:36:59.935030 ==
4205 01:36:59.937857 Dram Type= 6, Freq= 0, CH_1, rank 0
4206 01:36:59.944772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4207 01:36:59.945369 ==
4208 01:36:59.947824 Write leveling (Byte 0): 27 => 27
4209 01:36:59.951341 Write leveling (Byte 1): 28 => 28
4210 01:36:59.951921 DramcWriteLeveling(PI) end<-----
4211 01:36:59.952284
4212 01:36:59.954526 ==
4213 01:36:59.957687 Dram Type= 6, Freq= 0, CH_1, rank 0
4214 01:36:59.961484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4215 01:36:59.962086 ==
4216 01:36:59.964626 [Gating] SW mode calibration
4217 01:36:59.971286 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 01:36:59.974120 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4219 01:36:59.981171 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4220 01:36:59.984338 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4221 01:36:59.987453 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4222 01:36:59.994305 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 01:36:59.997631 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 01:37:00.000727 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 01:37:00.007362 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 01:37:00.010699 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 01:37:00.013922 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 01:37:00.020923 0 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4229 01:37:00.024060 0 6 8 | B1->B0 | 3434 3939 | 0 1 | (1 1) (0 0)
4230 01:37:00.027055 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 01:37:00.033713 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 01:37:00.037065 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 01:37:00.040478 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 01:37:00.047246 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 01:37:00.050525 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 01:37:00.053864 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4237 01:37:00.060610 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4238 01:37:00.063844 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 01:37:00.067168 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 01:37:00.073655 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 01:37:00.076847 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 01:37:00.080218 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 01:37:00.086807 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 01:37:00.090268 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 01:37:00.093660 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 01:37:00.100289 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 01:37:00.103643 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 01:37:00.106916 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 01:37:00.113075 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 01:37:00.116551 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 01:37:00.120011 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 01:37:00.126461 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4253 01:37:00.129892 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4254 01:37:00.133178 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4255 01:37:00.136587 Total UI for P1: 0, mck2ui 16
4256 01:37:00.139634 best dqsien dly found for B0: ( 0, 9, 6)
4257 01:37:00.142932 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 01:37:00.146097 Total UI for P1: 0, mck2ui 16
4259 01:37:00.149461 best dqsien dly found for B1: ( 0, 9, 12)
4260 01:37:00.153086 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4261 01:37:00.159551 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
4262 01:37:00.160107
4263 01:37:00.162702 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4264 01:37:00.166245 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
4265 01:37:00.169504 [Gating] SW calibration Done
4266 01:37:00.170060 ==
4267 01:37:00.172819 Dram Type= 6, Freq= 0, CH_1, rank 0
4268 01:37:00.175896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4269 01:37:00.176454 ==
4270 01:37:00.179095 RX Vref Scan: 0
4271 01:37:00.179547
4272 01:37:00.179902 RX Vref 0 -> 0, step: 1
4273 01:37:00.180233
4274 01:37:00.182082 RX Delay -230 -> 252, step: 16
4275 01:37:00.188682 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4276 01:37:00.192435 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4277 01:37:00.195788 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4278 01:37:00.198804 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4279 01:37:00.202189 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4280 01:37:00.208966 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4281 01:37:00.212013 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4282 01:37:00.215199 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4283 01:37:00.218576 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4284 01:37:00.225612 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4285 01:37:00.228719 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4286 01:37:00.232167 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4287 01:37:00.234906 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4288 01:37:00.241800 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4289 01:37:00.244816 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4290 01:37:00.248178 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4291 01:37:00.248636 ==
4292 01:37:00.251755 Dram Type= 6, Freq= 0, CH_1, rank 0
4293 01:37:00.254806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4294 01:37:00.258192 ==
4295 01:37:00.258642 DQS Delay:
4296 01:37:00.258994 DQS0 = 0, DQS1 = 0
4297 01:37:00.261380 DQM Delay:
4298 01:37:00.261833 DQM0 = 38, DQM1 = 33
4299 01:37:00.264900 DQ Delay:
4300 01:37:00.265393 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4301 01:37:00.268021 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4302 01:37:00.271268 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4303 01:37:00.274888 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4304 01:37:00.275345
4305 01:37:00.277916
4306 01:37:00.278361 ==
4307 01:37:00.281420 Dram Type= 6, Freq= 0, CH_1, rank 0
4308 01:37:00.285006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4309 01:37:00.285608 ==
4310 01:37:00.285970
4311 01:37:00.286299
4312 01:37:00.288050 TX Vref Scan disable
4313 01:37:00.288501 == TX Byte 0 ==
4314 01:37:00.294383 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4315 01:37:00.298099 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4316 01:37:00.298647 == TX Byte 1 ==
4317 01:37:00.304601 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4318 01:37:00.307988 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4319 01:37:00.308539 ==
4320 01:37:00.311167 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 01:37:00.314417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4322 01:37:00.314875 ==
4323 01:37:00.315233
4324 01:37:00.315562
4325 01:37:00.317898 TX Vref Scan disable
4326 01:37:00.320845 == TX Byte 0 ==
4327 01:37:00.324452 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4328 01:37:00.327836 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4329 01:37:00.330932 == TX Byte 1 ==
4330 01:37:00.334125 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4331 01:37:00.337791 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4332 01:37:00.340804
4333 01:37:00.341251 [DATLAT]
4334 01:37:00.341820 Freq=600, CH1 RK0
4335 01:37:00.342510
4336 01:37:00.343933 DATLAT Default: 0x9
4337 01:37:00.344443 0, 0xFFFF, sum = 0
4338 01:37:00.347455 1, 0xFFFF, sum = 0
4339 01:37:00.347910 2, 0xFFFF, sum = 0
4340 01:37:00.350697 3, 0xFFFF, sum = 0
4341 01:37:00.353916 4, 0xFFFF, sum = 0
4342 01:37:00.354374 5, 0xFFFF, sum = 0
4343 01:37:00.357409 6, 0xFFFF, sum = 0
4344 01:37:00.358168 7, 0x0, sum = 1
4345 01:37:00.358770 8, 0x0, sum = 2
4346 01:37:00.360618 9, 0x0, sum = 3
4347 01:37:00.361097 10, 0x0, sum = 4
4348 01:37:00.364064 best_step = 8
4349 01:37:00.364520
4350 01:37:00.364877 ==
4351 01:37:00.367149 Dram Type= 6, Freq= 0, CH_1, rank 0
4352 01:37:00.370456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4353 01:37:00.370917 ==
4354 01:37:00.373637 RX Vref Scan: 1
4355 01:37:00.374128
4356 01:37:00.374488 RX Vref 0 -> 0, step: 1
4357 01:37:00.374824
4358 01:37:00.377203 RX Delay -195 -> 252, step: 8
4359 01:37:00.377709
4360 01:37:00.380710 Set Vref, RX VrefLevel [Byte0]: 52
4361 01:37:00.383610 [Byte1]: 48
4362 01:37:00.387621
4363 01:37:00.388079 Final RX Vref Byte 0 = 52 to rank0
4364 01:37:00.391213 Final RX Vref Byte 1 = 48 to rank0
4365 01:37:00.394450 Final RX Vref Byte 0 = 52 to rank1
4366 01:37:00.398007 Final RX Vref Byte 1 = 48 to rank1==
4367 01:37:00.401214 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 01:37:00.407758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4369 01:37:00.408326 ==
4370 01:37:00.408694 DQS Delay:
4371 01:37:00.410807 DQS0 = 0, DQS1 = 0
4372 01:37:00.411337 DQM Delay:
4373 01:37:00.411707 DQM0 = 37, DQM1 = 30
4374 01:37:00.413957 DQ Delay:
4375 01:37:00.417356 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4376 01:37:00.420565 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4377 01:37:00.424106 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =24
4378 01:37:00.427149 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4379 01:37:00.427624
4380 01:37:00.427958
4381 01:37:00.433741 [DQSOSCAuto] RK0, (LSB)MR18= 0x7171, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4382 01:37:00.437129 CH1 RK0: MR19=808, MR18=7171
4383 01:37:00.443919 CH1_RK0: MR19=0x808, MR18=0x7171, DQSOSC=388, MR23=63, INC=174, DEC=116
4384 01:37:00.444332
4385 01:37:00.447222 ----->DramcWriteLeveling(PI) begin...
4386 01:37:00.447643 ==
4387 01:37:00.450339 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 01:37:00.453609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4389 01:37:00.454023 ==
4390 01:37:00.457113 Write leveling (Byte 0): 30 => 30
4391 01:37:00.460690 Write leveling (Byte 1): 29 => 29
4392 01:37:00.463655 DramcWriteLeveling(PI) end<-----
4393 01:37:00.464067
4394 01:37:00.464392 ==
4395 01:37:00.467074 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 01:37:00.470263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4397 01:37:00.473478 ==
4398 01:37:00.473891 [Gating] SW mode calibration
4399 01:37:00.483550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4400 01:37:00.486698 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4401 01:37:00.490266 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4402 01:37:00.496503 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4403 01:37:00.499860 0 5 8 | B1->B0 | 3131 2727 | 1 1 | (1 0) (0 0)
4404 01:37:00.502982 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 01:37:00.510008 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 01:37:00.513015 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 01:37:00.516393 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 01:37:00.523175 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 01:37:00.526361 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 01:37:00.529646 0 6 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
4411 01:37:00.536225 0 6 8 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4412 01:37:00.539604 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 01:37:00.543195 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 01:37:00.549692 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 01:37:00.553268 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 01:37:00.556398 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 01:37:00.562875 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 01:37:00.566675 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4419 01:37:00.569573 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4420 01:37:00.576452 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 01:37:00.579912 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 01:37:00.583284 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 01:37:00.589568 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 01:37:00.593094 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 01:37:00.596139 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 01:37:00.603030 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 01:37:00.606023 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 01:37:00.609449 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 01:37:00.616055 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 01:37:00.619346 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 01:37:00.622305 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 01:37:00.629163 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 01:37:00.632609 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 01:37:00.635767 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4435 01:37:00.639395 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4436 01:37:00.642433 Total UI for P1: 0, mck2ui 16
4437 01:37:00.645660 best dqsien dly found for B0: ( 0, 9, 4)
4438 01:37:00.652687 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 01:37:00.655616 Total UI for P1: 0, mck2ui 16
4440 01:37:00.658977 best dqsien dly found for B1: ( 0, 9, 8)
4441 01:37:00.662028 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4442 01:37:00.665619 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4443 01:37:00.666169
4444 01:37:00.668992 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4445 01:37:00.672180 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4446 01:37:00.675662 [Gating] SW calibration Done
4447 01:37:00.676211 ==
4448 01:37:00.678615 Dram Type= 6, Freq= 0, CH_1, rank 1
4449 01:37:00.681845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4450 01:37:00.682305 ==
4451 01:37:00.685366 RX Vref Scan: 0
4452 01:37:00.685822
4453 01:37:00.688804 RX Vref 0 -> 0, step: 1
4454 01:37:00.689255
4455 01:37:00.689665 RX Delay -230 -> 252, step: 16
4456 01:37:00.695430 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4457 01:37:00.699096 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4458 01:37:00.701803 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4459 01:37:00.705338 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4460 01:37:00.712024 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4461 01:37:00.714989 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4462 01:37:00.718462 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4463 01:37:00.721574 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4464 01:37:00.728398 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4465 01:37:00.731612 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4466 01:37:00.734807 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4467 01:37:00.738250 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4468 01:37:00.741437 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4469 01:37:00.747931 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4470 01:37:00.751522 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4471 01:37:00.754688 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4472 01:37:00.755146 ==
4473 01:37:00.758027 Dram Type= 6, Freq= 0, CH_1, rank 1
4474 01:37:00.765004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4475 01:37:00.765605 ==
4476 01:37:00.765973 DQS Delay:
4477 01:37:00.766307 DQS0 = 0, DQS1 = 0
4478 01:37:00.767873 DQM Delay:
4479 01:37:00.768327 DQM0 = 42, DQM1 = 34
4480 01:37:00.771040 DQ Delay:
4481 01:37:00.774645 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4482 01:37:00.777682 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4483 01:37:00.781184 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4484 01:37:00.784257 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4485 01:37:00.784716
4486 01:37:00.785076
4487 01:37:00.785443 ==
4488 01:37:00.787730 Dram Type= 6, Freq= 0, CH_1, rank 1
4489 01:37:00.790930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4490 01:37:00.791433 ==
4491 01:37:00.791793
4492 01:37:00.792123
4493 01:37:00.794808 TX Vref Scan disable
4494 01:37:00.795363 == TX Byte 0 ==
4495 01:37:00.800919 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4496 01:37:00.804365 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4497 01:37:00.807713 == TX Byte 1 ==
4498 01:37:00.811189 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4499 01:37:00.814039 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4500 01:37:00.814501 ==
4501 01:37:00.817497 Dram Type= 6, Freq= 0, CH_1, rank 1
4502 01:37:00.820954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4503 01:37:00.821546 ==
4504 01:37:00.824348
4505 01:37:00.824904
4506 01:37:00.825267 TX Vref Scan disable
4507 01:37:00.827908 == TX Byte 0 ==
4508 01:37:00.831279 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4509 01:37:00.834337 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4510 01:37:00.837993 == TX Byte 1 ==
4511 01:37:00.841429 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 01:37:00.844714 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 01:37:00.847594
4514 01:37:00.848045 [DATLAT]
4515 01:37:00.848401 Freq=600, CH1 RK1
4516 01:37:00.848732
4517 01:37:00.851027 DATLAT Default: 0x8
4518 01:37:00.851579 0, 0xFFFF, sum = 0
4519 01:37:00.854416 1, 0xFFFF, sum = 0
4520 01:37:00.854977 2, 0xFFFF, sum = 0
4521 01:37:00.857355 3, 0xFFFF, sum = 0
4522 01:37:00.861080 4, 0xFFFF, sum = 0
4523 01:37:00.861707 5, 0xFFFF, sum = 0
4524 01:37:00.864395 6, 0xFFFF, sum = 0
4525 01:37:00.864957 7, 0x0, sum = 1
4526 01:37:00.865358 8, 0x0, sum = 2
4527 01:37:00.867389 9, 0x0, sum = 3
4528 01:37:00.867944 10, 0x0, sum = 4
4529 01:37:00.870967 best_step = 8
4530 01:37:00.871419
4531 01:37:00.871775 ==
4532 01:37:00.873794 Dram Type= 6, Freq= 0, CH_1, rank 1
4533 01:37:00.877509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4534 01:37:00.878071 ==
4535 01:37:00.880658 RX Vref Scan: 0
4536 01:37:00.881111
4537 01:37:00.881504 RX Vref 0 -> 0, step: 1
4538 01:37:00.881843
4539 01:37:00.883818 RX Delay -195 -> 252, step: 8
4540 01:37:00.891150 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4541 01:37:00.894861 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4542 01:37:00.897948 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4543 01:37:00.901399 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4544 01:37:00.907676 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4545 01:37:00.911284 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4546 01:37:00.914643 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4547 01:37:00.917846 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4548 01:37:00.924242 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4549 01:37:00.927716 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4550 01:37:00.931209 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4551 01:37:00.934279 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4552 01:37:00.937754 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4553 01:37:00.944122 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4554 01:37:00.948020 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4555 01:37:00.951024 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4556 01:37:00.951583 ==
4557 01:37:00.954051 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 01:37:00.961268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 01:37:00.961863 ==
4560 01:37:00.962224 DQS Delay:
4561 01:37:00.962556 DQS0 = 0, DQS1 = 0
4562 01:37:00.964162 DQM Delay:
4563 01:37:00.964719 DQM0 = 37, DQM1 = 29
4564 01:37:00.967635 DQ Delay:
4565 01:37:00.970428 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4566 01:37:00.973873 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4567 01:37:00.977188 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4568 01:37:00.980794 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4569 01:37:00.981429
4570 01:37:00.981985
4571 01:37:00.986966 [DQSOSCAuto] RK1, (LSB)MR18= 0x5353, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4572 01:37:00.990502 CH1 RK1: MR19=808, MR18=5353
4573 01:37:00.997585 CH1_RK1: MR19=0x808, MR18=0x5353, DQSOSC=394, MR23=63, INC=168, DEC=112
4574 01:37:01.000316 [RxdqsGatingPostProcess] freq 600
4575 01:37:01.003819 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4576 01:37:01.007132 Pre-setting of DQS Precalculation
4577 01:37:01.013459 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4578 01:37:01.020023 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4579 01:37:01.026413 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4580 01:37:01.026869
4581 01:37:01.027226
4582 01:37:01.029886 [Calibration Summary] 1200 Mbps
4583 01:37:01.030342 CH 0, Rank 0
4584 01:37:01.033447 SW Impedance : PASS
4585 01:37:01.036727 DUTY Scan : NO K
4586 01:37:01.037282 ZQ Calibration : PASS
4587 01:37:01.039776 Jitter Meter : NO K
4588 01:37:01.042996 CBT Training : PASS
4589 01:37:01.043449 Write leveling : PASS
4590 01:37:01.046506 RX DQS gating : PASS
4591 01:37:01.049614 RX DQ/DQS(RDDQC) : PASS
4592 01:37:01.050072 TX DQ/DQS : PASS
4593 01:37:01.053100 RX DATLAT : PASS
4594 01:37:01.056219 RX DQ/DQS(Engine): PASS
4595 01:37:01.056671 TX OE : NO K
4596 01:37:01.059503 All Pass.
4597 01:37:01.059955
4598 01:37:01.060310 CH 0, Rank 1
4599 01:37:01.062975 SW Impedance : PASS
4600 01:37:01.063429 DUTY Scan : NO K
4601 01:37:01.066215 ZQ Calibration : PASS
4602 01:37:01.069785 Jitter Meter : NO K
4603 01:37:01.070337 CBT Training : PASS
4604 01:37:01.072937 Write leveling : PASS
4605 01:37:01.076677 RX DQS gating : PASS
4606 01:37:01.077339 RX DQ/DQS(RDDQC) : PASS
4607 01:37:01.079412 TX DQ/DQS : PASS
4608 01:37:01.082976 RX DATLAT : PASS
4609 01:37:01.083531 RX DQ/DQS(Engine): PASS
4610 01:37:01.086040 TX OE : NO K
4611 01:37:01.086499 All Pass.
4612 01:37:01.086854
4613 01:37:01.089600 CH 1, Rank 0
4614 01:37:01.090051 SW Impedance : PASS
4615 01:37:01.092537 DUTY Scan : NO K
4616 01:37:01.096290 ZQ Calibration : PASS
4617 01:37:01.096843 Jitter Meter : NO K
4618 01:37:01.099498 CBT Training : PASS
4619 01:37:01.100047 Write leveling : PASS
4620 01:37:01.102500 RX DQS gating : PASS
4621 01:37:01.105968 RX DQ/DQS(RDDQC) : PASS
4622 01:37:01.106521 TX DQ/DQS : PASS
4623 01:37:01.109433 RX DATLAT : PASS
4624 01:37:01.112309 RX DQ/DQS(Engine): PASS
4625 01:37:01.112769 TX OE : NO K
4626 01:37:01.115759 All Pass.
4627 01:37:01.116213
4628 01:37:01.116581 CH 1, Rank 1
4629 01:37:01.119363 SW Impedance : PASS
4630 01:37:01.119913 DUTY Scan : NO K
4631 01:37:01.122300 ZQ Calibration : PASS
4632 01:37:01.125882 Jitter Meter : NO K
4633 01:37:01.126439 CBT Training : PASS
4634 01:37:01.128845 Write leveling : PASS
4635 01:37:01.132448 RX DQS gating : PASS
4636 01:37:01.133004 RX DQ/DQS(RDDQC) : PASS
4637 01:37:01.135988 TX DQ/DQS : PASS
4638 01:37:01.139217 RX DATLAT : PASS
4639 01:37:01.139770 RX DQ/DQS(Engine): PASS
4640 01:37:01.142263 TX OE : NO K
4641 01:37:01.142732 All Pass.
4642 01:37:01.143095
4643 01:37:01.145516 DramC Write-DBI off
4644 01:37:01.149112 PER_BANK_REFRESH: Hybrid Mode
4645 01:37:01.149734 TX_TRACKING: ON
4646 01:37:01.158699 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4647 01:37:01.161937 [FAST_K] Save calibration result to emmc
4648 01:37:01.165355 dramc_set_vcore_voltage set vcore to 662500
4649 01:37:01.168903 Read voltage for 933, 3
4650 01:37:01.169527 Vio18 = 0
4651 01:37:01.169904 Vcore = 662500
4652 01:37:01.171757 Vdram = 0
4653 01:37:01.172211 Vddq = 0
4654 01:37:01.172564 Vmddr = 0
4655 01:37:01.178545 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4656 01:37:01.181700 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4657 01:37:01.185246 MEM_TYPE=3, freq_sel=17
4658 01:37:01.188515 sv_algorithm_assistance_LP4_1600
4659 01:37:01.191916 ============ PULL DRAM RESETB DOWN ============
4660 01:37:01.194905 ========== PULL DRAM RESETB DOWN end =========
4661 01:37:01.201877 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4662 01:37:01.205118 ===================================
4663 01:37:01.208314 LPDDR4 DRAM CONFIGURATION
4664 01:37:01.212435 ===================================
4665 01:37:01.212993 EX_ROW_EN[0] = 0x0
4666 01:37:01.215333 EX_ROW_EN[1] = 0x0
4667 01:37:01.215885 LP4Y_EN = 0x0
4668 01:37:01.218227 WORK_FSP = 0x0
4669 01:37:01.218677 WL = 0x3
4670 01:37:01.221868 RL = 0x3
4671 01:37:01.222320 BL = 0x2
4672 01:37:01.224782 RPST = 0x0
4673 01:37:01.225233 RD_PRE = 0x0
4674 01:37:01.228466 WR_PRE = 0x1
4675 01:37:01.229018 WR_PST = 0x0
4676 01:37:01.231706 DBI_WR = 0x0
4677 01:37:01.232256 DBI_RD = 0x0
4678 01:37:01.234957 OTF = 0x1
4679 01:37:01.238043 ===================================
4680 01:37:01.241615 ===================================
4681 01:37:01.242166 ANA top config
4682 01:37:01.244839 ===================================
4683 01:37:01.248466 DLL_ASYNC_EN = 0
4684 01:37:01.251701 ALL_SLAVE_EN = 1
4685 01:37:01.254795 NEW_RANK_MODE = 1
4686 01:37:01.255255 DLL_IDLE_MODE = 1
4687 01:37:01.258520 LP45_APHY_COMB_EN = 1
4688 01:37:01.261765 TX_ODT_DIS = 1
4689 01:37:01.264551 NEW_8X_MODE = 1
4690 01:37:01.268303 ===================================
4691 01:37:01.271578 ===================================
4692 01:37:01.274856 data_rate = 1866
4693 01:37:01.275312 CKR = 1
4694 01:37:01.277848 DQ_P2S_RATIO = 8
4695 01:37:01.281446 ===================================
4696 01:37:01.284832 CA_P2S_RATIO = 8
4697 01:37:01.287930 DQ_CA_OPEN = 0
4698 01:37:01.291707 DQ_SEMI_OPEN = 0
4699 01:37:01.294604 CA_SEMI_OPEN = 0
4700 01:37:01.295174 CA_FULL_RATE = 0
4701 01:37:01.297976 DQ_CKDIV4_EN = 1
4702 01:37:01.301211 CA_CKDIV4_EN = 1
4703 01:37:01.304487 CA_PREDIV_EN = 0
4704 01:37:01.307926 PH8_DLY = 0
4705 01:37:01.311324 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4706 01:37:01.314331 DQ_AAMCK_DIV = 4
4707 01:37:01.314897 CA_AAMCK_DIV = 4
4708 01:37:01.317779 CA_ADMCK_DIV = 4
4709 01:37:01.321200 DQ_TRACK_CA_EN = 0
4710 01:37:01.324512 CA_PICK = 933
4711 01:37:01.327657 CA_MCKIO = 933
4712 01:37:01.330997 MCKIO_SEMI = 0
4713 01:37:01.334151 PLL_FREQ = 3732
4714 01:37:01.334617 DQ_UI_PI_RATIO = 32
4715 01:37:01.337328 CA_UI_PI_RATIO = 0
4716 01:37:01.340760 ===================================
4717 01:37:01.343874 ===================================
4718 01:37:01.347575 memory_type:LPDDR4
4719 01:37:01.350672 GP_NUM : 10
4720 01:37:01.351124 SRAM_EN : 1
4721 01:37:01.353882 MD32_EN : 0
4722 01:37:01.357465 ===================================
4723 01:37:01.358016 [ANA_INIT] >>>>>>>>>>>>>>
4724 01:37:01.360471 <<<<<< [CONFIGURE PHASE]: ANA_TX
4725 01:37:01.363678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4726 01:37:01.367209 ===================================
4727 01:37:01.370287 data_rate = 1866,PCW = 0X8f00
4728 01:37:01.373600 ===================================
4729 01:37:01.376885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4730 01:37:01.384103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4731 01:37:01.390340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4732 01:37:01.393768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4733 01:37:01.396781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4734 01:37:01.400243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4735 01:37:01.403780 [ANA_INIT] flow start
4736 01:37:01.404329 [ANA_INIT] PLL >>>>>>>>
4737 01:37:01.407249 [ANA_INIT] PLL <<<<<<<<
4738 01:37:01.410039 [ANA_INIT] MIDPI >>>>>>>>
4739 01:37:01.413719 [ANA_INIT] MIDPI <<<<<<<<
4740 01:37:01.414171 [ANA_INIT] DLL >>>>>>>>
4741 01:37:01.416907 [ANA_INIT] flow end
4742 01:37:01.420016 ============ LP4 DIFF to SE enter ============
4743 01:37:01.423768 ============ LP4 DIFF to SE exit ============
4744 01:37:01.426489 [ANA_INIT] <<<<<<<<<<<<<
4745 01:37:01.430141 [Flow] Enable top DCM control >>>>>
4746 01:37:01.433175 [Flow] Enable top DCM control <<<<<
4747 01:37:01.436348 Enable DLL master slave shuffle
4748 01:37:01.443203 ==============================================================
4749 01:37:01.443758 Gating Mode config
4750 01:37:01.449701 ==============================================================
4751 01:37:01.450164 Config description:
4752 01:37:01.459375 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4753 01:37:01.466535 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4754 01:37:01.472723 SELPH_MODE 0: By rank 1: By Phase
4755 01:37:01.476489 ==============================================================
4756 01:37:01.479392 GAT_TRACK_EN = 1
4757 01:37:01.483012 RX_GATING_MODE = 2
4758 01:37:01.485995 RX_GATING_TRACK_MODE = 2
4759 01:37:01.489423 SELPH_MODE = 1
4760 01:37:01.492956 PICG_EARLY_EN = 1
4761 01:37:01.496326 VALID_LAT_VALUE = 1
4762 01:37:01.502885 ==============================================================
4763 01:37:01.506013 Enter into Gating configuration >>>>
4764 01:37:01.509457 Exit from Gating configuration <<<<
4765 01:37:01.510018 Enter into DVFS_PRE_config >>>>>
4766 01:37:01.522575 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4767 01:37:01.525741 Exit from DVFS_PRE_config <<<<<
4768 01:37:01.529116 Enter into PICG configuration >>>>
4769 01:37:01.532614 Exit from PICG configuration <<<<
4770 01:37:01.533170 [RX_INPUT] configuration >>>>>
4771 01:37:01.535775 [RX_INPUT] configuration <<<<<
4772 01:37:01.542217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4773 01:37:01.545908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4774 01:37:01.552741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4775 01:37:01.558866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4776 01:37:01.565559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4777 01:37:01.572401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4778 01:37:01.575347 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4779 01:37:01.578704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4780 01:37:01.585281 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4781 01:37:01.589002 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4782 01:37:01.591774 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4783 01:37:01.598582 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4784 01:37:01.602072 ===================================
4785 01:37:01.602668 LPDDR4 DRAM CONFIGURATION
4786 01:37:01.605104 ===================================
4787 01:37:01.608600 EX_ROW_EN[0] = 0x0
4788 01:37:01.609162 EX_ROW_EN[1] = 0x0
4789 01:37:01.612095 LP4Y_EN = 0x0
4790 01:37:01.612662 WORK_FSP = 0x0
4791 01:37:01.615048 WL = 0x3
4792 01:37:01.615508 RL = 0x3
4793 01:37:01.618351 BL = 0x2
4794 01:37:01.621614 RPST = 0x0
4795 01:37:01.622077 RD_PRE = 0x0
4796 01:37:01.624937 WR_PRE = 0x1
4797 01:37:01.625542 WR_PST = 0x0
4798 01:37:01.628291 DBI_WR = 0x0
4799 01:37:01.628746 DBI_RD = 0x0
4800 01:37:01.631881 OTF = 0x1
4801 01:37:01.634839 ===================================
4802 01:37:01.638185 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4803 01:37:01.641438 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4804 01:37:01.644891 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4805 01:37:01.648179 ===================================
4806 01:37:01.651487 LPDDR4 DRAM CONFIGURATION
4807 01:37:01.654646 ===================================
4808 01:37:01.658020 EX_ROW_EN[0] = 0x10
4809 01:37:01.658480 EX_ROW_EN[1] = 0x0
4810 01:37:01.661256 LP4Y_EN = 0x0
4811 01:37:01.661798 WORK_FSP = 0x0
4812 01:37:01.664667 WL = 0x3
4813 01:37:01.665128 RL = 0x3
4814 01:37:01.668467 BL = 0x2
4815 01:37:01.669030 RPST = 0x0
4816 01:37:01.671611 RD_PRE = 0x0
4817 01:37:01.674840 WR_PRE = 0x1
4818 01:37:01.675304 WR_PST = 0x0
4819 01:37:01.678086 DBI_WR = 0x0
4820 01:37:01.678546 DBI_RD = 0x0
4821 01:37:01.681323 OTF = 0x1
4822 01:37:01.684568 ===================================
4823 01:37:01.687855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4824 01:37:01.693419 nWR fixed to 30
4825 01:37:01.696686 [ModeRegInit_LP4] CH0 RK0
4826 01:37:01.697164 [ModeRegInit_LP4] CH0 RK1
4827 01:37:01.699780 [ModeRegInit_LP4] CH1 RK0
4828 01:37:01.703125 [ModeRegInit_LP4] CH1 RK1
4829 01:37:01.703613 match AC timing 8
4830 01:37:01.709724 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4831 01:37:01.712989 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4832 01:37:01.716167 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4833 01:37:01.722959 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4834 01:37:01.726408 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4835 01:37:01.726884 ==
4836 01:37:01.729992 Dram Type= 6, Freq= 0, CH_0, rank 0
4837 01:37:01.733033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4838 01:37:01.733633 ==
4839 01:37:01.739218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4840 01:37:01.745952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4841 01:37:01.749181 [CA 0] Center 38 (8~69) winsize 62
4842 01:37:01.752798 [CA 1] Center 38 (8~69) winsize 62
4843 01:37:01.755625 [CA 2] Center 36 (6~67) winsize 62
4844 01:37:01.759271 [CA 3] Center 36 (5~67) winsize 63
4845 01:37:01.762479 [CA 4] Center 35 (4~66) winsize 63
4846 01:37:01.765628 [CA 5] Center 34 (4~65) winsize 62
4847 01:37:01.766084
4848 01:37:01.768966 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4849 01:37:01.769452
4850 01:37:01.772549 [CATrainingPosCal] consider 1 rank data
4851 01:37:01.775735 u2DelayCellTimex100 = 270/100 ps
4852 01:37:01.779237 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4853 01:37:01.782246 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4854 01:37:01.785653 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4855 01:37:01.792515 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4856 01:37:01.795462 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
4857 01:37:01.799052 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4858 01:37:01.799617
4859 01:37:01.802110 CA PerBit enable=1, Macro0, CA PI delay=34
4860 01:37:01.802605
4861 01:37:01.805486 [CBTSetCACLKResult] CA Dly = 34
4862 01:37:01.805943 CS Dly: 7 (0~38)
4863 01:37:01.806299 ==
4864 01:37:01.808729 Dram Type= 6, Freq= 0, CH_0, rank 1
4865 01:37:01.815728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4866 01:37:01.816289 ==
4867 01:37:01.818848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4868 01:37:01.825704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4869 01:37:01.829056 [CA 0] Center 38 (8~69) winsize 62
4870 01:37:01.832378 [CA 1] Center 38 (7~69) winsize 63
4871 01:37:01.835562 [CA 2] Center 36 (5~67) winsize 63
4872 01:37:01.838861 [CA 3] Center 35 (5~66) winsize 62
4873 01:37:01.842689 [CA 4] Center 34 (4~65) winsize 62
4874 01:37:01.845835 [CA 5] Center 34 (4~65) winsize 62
4875 01:37:01.846392
4876 01:37:01.848744 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4877 01:37:01.849214
4878 01:37:01.852534 [CATrainingPosCal] consider 2 rank data
4879 01:37:01.855368 u2DelayCellTimex100 = 270/100 ps
4880 01:37:01.858456 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4881 01:37:01.861830 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4882 01:37:01.868819 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4883 01:37:01.872335 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4884 01:37:01.875551 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4885 01:37:01.878672 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4886 01:37:01.879229
4887 01:37:01.882215 CA PerBit enable=1, Macro0, CA PI delay=34
4888 01:37:01.882770
4889 01:37:01.885534 [CBTSetCACLKResult] CA Dly = 34
4890 01:37:01.886090 CS Dly: 7 (0~39)
4891 01:37:01.886454
4892 01:37:01.888715 ----->DramcWriteLeveling(PI) begin...
4893 01:37:01.891972 ==
4894 01:37:01.895254 Dram Type= 6, Freq= 0, CH_0, rank 0
4895 01:37:01.898443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4896 01:37:01.899002 ==
4897 01:37:01.901896 Write leveling (Byte 0): 27 => 27
4898 01:37:01.905467 Write leveling (Byte 1): 27 => 27
4899 01:37:01.908429 DramcWriteLeveling(PI) end<-----
4900 01:37:01.908984
4901 01:37:01.909388 ==
4902 01:37:01.911931 Dram Type= 6, Freq= 0, CH_0, rank 0
4903 01:37:01.915249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4904 01:37:01.915810 ==
4905 01:37:01.918317 [Gating] SW mode calibration
4906 01:37:01.925748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4907 01:37:01.931145 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4908 01:37:01.934845 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 01:37:01.938389 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 01:37:01.944631 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 01:37:01.947670 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4912 01:37:01.951060 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4913 01:37:01.957743 0 10 20 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4914 01:37:01.961086 0 10 24 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
4915 01:37:01.964282 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 01:37:01.971087 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 01:37:01.974550 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 01:37:01.977806 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 01:37:01.984318 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 01:37:01.987589 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 01:37:01.990616 0 11 20 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
4922 01:37:01.997479 0 11 24 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
4923 01:37:02.000728 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 01:37:02.004126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 01:37:02.010849 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 01:37:02.014152 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 01:37:02.017487 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 01:37:02.024076 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 01:37:02.027180 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4930 01:37:02.030433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 01:37:02.037010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 01:37:02.040203 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 01:37:02.043676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 01:37:02.050310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 01:37:02.053636 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 01:37:02.056842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 01:37:02.060635 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 01:37:02.066936 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 01:37:02.070029 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 01:37:02.073366 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 01:37:02.080162 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 01:37:02.083385 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 01:37:02.086758 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 01:37:02.093380 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 01:37:02.096594 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4946 01:37:02.099880 Total UI for P1: 0, mck2ui 16
4947 01:37:02.103359 best dqsien dly found for B0: ( 0, 14, 18)
4948 01:37:02.106467 Total UI for P1: 0, mck2ui 16
4949 01:37:02.109772 best dqsien dly found for B1: ( 0, 14, 18)
4950 01:37:02.113163 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
4951 01:37:02.116453 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
4952 01:37:02.116907
4953 01:37:02.119713 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
4954 01:37:02.126238 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
4955 01:37:02.126794 [Gating] SW calibration Done
4956 01:37:02.129553 ==
4957 01:37:02.130109 Dram Type= 6, Freq= 0, CH_0, rank 0
4958 01:37:02.136058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4959 01:37:02.136619 ==
4960 01:37:02.137025 RX Vref Scan: 0
4961 01:37:02.137422
4962 01:37:02.139382 RX Vref 0 -> 0, step: 1
4963 01:37:02.139834
4964 01:37:02.142641 RX Delay -80 -> 252, step: 8
4965 01:37:02.146091 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4966 01:37:02.149191 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4967 01:37:02.152820 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4968 01:37:02.159151 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4969 01:37:02.162264 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4970 01:37:02.165740 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4971 01:37:02.169322 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4972 01:37:02.172921 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4973 01:37:02.175696 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4974 01:37:02.182522 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4975 01:37:02.185936 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4976 01:37:02.188781 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4977 01:37:02.192452 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4978 01:37:02.195636 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4979 01:37:02.202550 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4980 01:37:02.205657 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4981 01:37:02.206223 ==
4982 01:37:02.208927 Dram Type= 6, Freq= 0, CH_0, rank 0
4983 01:37:02.212225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4984 01:37:02.212790 ==
4985 01:37:02.215367 DQS Delay:
4986 01:37:02.215927 DQS0 = 0, DQS1 = 0
4987 01:37:02.216292 DQM Delay:
4988 01:37:02.218441 DQM0 = 96, DQM1 = 84
4989 01:37:02.218896 DQ Delay:
4990 01:37:02.221900 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
4991 01:37:02.225079 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
4992 01:37:02.229175 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
4993 01:37:02.231776 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
4994 01:37:02.232236
4995 01:37:02.232593
4996 01:37:02.232929 ==
4997 01:37:02.235237 Dram Type= 6, Freq= 0, CH_0, rank 0
4998 01:37:02.241748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4999 01:37:02.242314 ==
5000 01:37:02.242679
5001 01:37:02.243016
5002 01:37:02.244991 TX Vref Scan disable
5003 01:37:02.245467 == TX Byte 0 ==
5004 01:37:02.248174 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5005 01:37:02.255714 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5006 01:37:02.256289 == TX Byte 1 ==
5007 01:37:02.258031 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5008 01:37:02.264692 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5009 01:37:02.265253 ==
5010 01:37:02.268094 Dram Type= 6, Freq= 0, CH_0, rank 0
5011 01:37:02.271686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5012 01:37:02.272244 ==
5013 01:37:02.272611
5014 01:37:02.272948
5015 01:37:02.274549 TX Vref Scan disable
5016 01:37:02.277836 == TX Byte 0 ==
5017 01:37:02.281553 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5018 01:37:02.284456 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5019 01:37:02.287826 == TX Byte 1 ==
5020 01:37:02.291219 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5021 01:37:02.294194 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5022 01:37:02.294662
5023 01:37:02.297438 [DATLAT]
5024 01:37:02.297897 Freq=933, CH0 RK0
5025 01:37:02.298262
5026 01:37:02.300861 DATLAT Default: 0xd
5027 01:37:02.301355 0, 0xFFFF, sum = 0
5028 01:37:02.304228 1, 0xFFFF, sum = 0
5029 01:37:02.304794 2, 0xFFFF, sum = 0
5030 01:37:02.307764 3, 0xFFFF, sum = 0
5031 01:37:02.308335 4, 0xFFFF, sum = 0
5032 01:37:02.311301 5, 0xFFFF, sum = 0
5033 01:37:02.311869 6, 0xFFFF, sum = 0
5034 01:37:02.314419 7, 0xFFFF, sum = 0
5035 01:37:02.314881 8, 0xFFFF, sum = 0
5036 01:37:02.317252 9, 0xFFFF, sum = 0
5037 01:37:02.317761 10, 0x0, sum = 1
5038 01:37:02.320928 11, 0x0, sum = 2
5039 01:37:02.321542 12, 0x0, sum = 3
5040 01:37:02.324043 13, 0x0, sum = 4
5041 01:37:02.324606 best_step = 11
5042 01:37:02.324969
5043 01:37:02.325334 ==
5044 01:37:02.327385 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 01:37:02.333858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5046 01:37:02.334408 ==
5047 01:37:02.334770 RX Vref Scan: 1
5048 01:37:02.335105
5049 01:37:02.337244 RX Vref 0 -> 0, step: 1
5050 01:37:02.337892
5051 01:37:02.340463 RX Delay -69 -> 252, step: 4
5052 01:37:02.340922
5053 01:37:02.343970 Set Vref, RX VrefLevel [Byte0]: 51
5054 01:37:02.347153 [Byte1]: 48
5055 01:37:02.347718
5056 01:37:02.350455 Final RX Vref Byte 0 = 51 to rank0
5057 01:37:02.354031 Final RX Vref Byte 1 = 48 to rank0
5058 01:37:02.357400 Final RX Vref Byte 0 = 51 to rank1
5059 01:37:02.360182 Final RX Vref Byte 1 = 48 to rank1==
5060 01:37:02.363799 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 01:37:02.367323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5062 01:37:02.367899 ==
5063 01:37:02.370604 DQS Delay:
5064 01:37:02.371159 DQS0 = 0, DQS1 = 0
5065 01:37:02.373435 DQM Delay:
5066 01:37:02.373895 DQM0 = 96, DQM1 = 87
5067 01:37:02.374330 DQ Delay:
5068 01:37:02.377052 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =94
5069 01:37:02.380410 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =104
5070 01:37:02.383476 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5071 01:37:02.386860 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =96
5072 01:37:02.387413
5073 01:37:02.389916
5074 01:37:02.396521 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5075 01:37:02.400218 CH0 RK0: MR19=505, MR18=1D1D
5076 01:37:02.406561 CH0_RK0: MR19=0x505, MR18=0x1D1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5077 01:37:02.407118
5078 01:37:02.409951 ----->DramcWriteLeveling(PI) begin...
5079 01:37:02.410516 ==
5080 01:37:02.413263 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 01:37:02.416356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5082 01:37:02.416824 ==
5083 01:37:02.419570 Write leveling (Byte 0): 29 => 29
5084 01:37:02.423083 Write leveling (Byte 1): 29 => 29
5085 01:37:02.426311 DramcWriteLeveling(PI) end<-----
5086 01:37:02.426770
5087 01:37:02.427131 ==
5088 01:37:02.429470 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 01:37:02.432881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5090 01:37:02.433386 ==
5091 01:37:02.436426 [Gating] SW mode calibration
5092 01:37:02.442811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5093 01:37:02.449573 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5094 01:37:02.452754 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 01:37:02.456489 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 01:37:02.462752 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 01:37:02.465706 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 01:37:02.469223 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5099 01:37:02.475862 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
5100 01:37:02.479034 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 01:37:02.482536 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 01:37:02.489154 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 01:37:02.492272 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 01:37:02.495407 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 01:37:02.502396 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 01:37:02.505798 0 11 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
5107 01:37:02.508985 0 11 20 | B1->B0 | 2727 2f2f | 1 0 | (0 0) (0 0)
5108 01:37:02.515713 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5109 01:37:02.518847 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 01:37:02.522400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 01:37:02.528634 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 01:37:02.531976 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 01:37:02.535292 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 01:37:02.542091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 01:37:02.545638 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5116 01:37:02.548747 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5117 01:37:02.555206 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 01:37:02.558767 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 01:37:02.561732 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 01:37:02.568502 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 01:37:02.571817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 01:37:02.575329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 01:37:02.581743 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 01:37:02.584829 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 01:37:02.588143 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 01:37:02.595186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 01:37:02.597999 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 01:37:02.601475 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 01:37:02.608023 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 01:37:02.611206 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 01:37:02.614328 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5132 01:37:02.620946 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5133 01:37:02.624484 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 01:37:02.627503 Total UI for P1: 0, mck2ui 16
5135 01:37:02.630803 best dqsien dly found for B0: ( 0, 14, 20)
5136 01:37:02.634252 Total UI for P1: 0, mck2ui 16
5137 01:37:02.637382 best dqsien dly found for B1: ( 0, 14, 22)
5138 01:37:02.640837 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5139 01:37:02.643964 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5140 01:37:02.644426
5141 01:37:02.647520 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5142 01:37:02.653866 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5143 01:37:02.654325 [Gating] SW calibration Done
5144 01:37:02.654689 ==
5145 01:37:02.657669 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 01:37:02.663948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5147 01:37:02.664505 ==
5148 01:37:02.664870 RX Vref Scan: 0
5149 01:37:02.665205
5150 01:37:02.667314 RX Vref 0 -> 0, step: 1
5151 01:37:02.667930
5152 01:37:02.670896 RX Delay -80 -> 252, step: 8
5153 01:37:02.673810 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5154 01:37:02.677446 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5155 01:37:02.680633 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5156 01:37:02.687055 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5157 01:37:02.690142 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5158 01:37:02.693735 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5159 01:37:02.696977 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5160 01:37:02.700531 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5161 01:37:02.704008 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5162 01:37:02.710220 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5163 01:37:02.713632 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5164 01:37:02.717312 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5165 01:37:02.720038 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5166 01:37:02.723218 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5167 01:37:02.730029 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5168 01:37:02.733259 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5169 01:37:02.733839 ==
5170 01:37:02.736330 Dram Type= 6, Freq= 0, CH_0, rank 1
5171 01:37:02.739717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5172 01:37:02.740180 ==
5173 01:37:02.743457 DQS Delay:
5174 01:37:02.744009 DQS0 = 0, DQS1 = 0
5175 01:37:02.744374 DQM Delay:
5176 01:37:02.746423 DQM0 = 95, DQM1 = 85
5177 01:37:02.746883 DQ Delay:
5178 01:37:02.749815 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5179 01:37:02.752955 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5180 01:37:02.756751 DQ8 =71, DQ9 =71, DQ10 =83, DQ11 =79
5181 01:37:02.759628 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5182 01:37:02.760154
5183 01:37:02.760531
5184 01:37:02.760924 ==
5185 01:37:02.763021 Dram Type= 6, Freq= 0, CH_0, rank 1
5186 01:37:02.769352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5187 01:37:02.769847 ==
5188 01:37:02.770215
5189 01:37:02.770552
5190 01:37:02.770868 TX Vref Scan disable
5191 01:37:02.773001 == TX Byte 0 ==
5192 01:37:02.776512 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5193 01:37:02.782909 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5194 01:37:02.783464 == TX Byte 1 ==
5195 01:37:02.786164 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5196 01:37:02.792720 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5197 01:37:02.793193 ==
5198 01:37:02.796085 Dram Type= 6, Freq= 0, CH_0, rank 1
5199 01:37:02.799503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5200 01:37:02.800061 ==
5201 01:37:02.800427
5202 01:37:02.800759
5203 01:37:02.802779 TX Vref Scan disable
5204 01:37:02.803333 == TX Byte 0 ==
5205 01:37:02.809625 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5206 01:37:02.812497 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5207 01:37:02.815968 == TX Byte 1 ==
5208 01:37:02.819051 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5209 01:37:02.822503 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5210 01:37:02.822964
5211 01:37:02.823345 [DATLAT]
5212 01:37:02.825687 Freq=933, CH0 RK1
5213 01:37:02.826143
5214 01:37:02.826499 DATLAT Default: 0xb
5215 01:37:02.829139 0, 0xFFFF, sum = 0
5216 01:37:02.832305 1, 0xFFFF, sum = 0
5217 01:37:02.832769 2, 0xFFFF, sum = 0
5218 01:37:02.835931 3, 0xFFFF, sum = 0
5219 01:37:02.836397 4, 0xFFFF, sum = 0
5220 01:37:02.838911 5, 0xFFFF, sum = 0
5221 01:37:02.839375 6, 0xFFFF, sum = 0
5222 01:37:02.842278 7, 0xFFFF, sum = 0
5223 01:37:02.842749 8, 0xFFFF, sum = 0
5224 01:37:02.845622 9, 0xFFFF, sum = 0
5225 01:37:02.846113 10, 0x0, sum = 1
5226 01:37:02.848690 11, 0x0, sum = 2
5227 01:37:02.849152 12, 0x0, sum = 3
5228 01:37:02.852029 13, 0x0, sum = 4
5229 01:37:02.852835 best_step = 11
5230 01:37:02.853458
5231 01:37:02.853819 ==
5232 01:37:02.855180 Dram Type= 6, Freq= 0, CH_0, rank 1
5233 01:37:02.858491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5234 01:37:02.861860 ==
5235 01:37:02.862447 RX Vref Scan: 0
5236 01:37:02.862817
5237 01:37:02.865041 RX Vref 0 -> 0, step: 1
5238 01:37:02.865636
5239 01:37:02.868216 RX Delay -69 -> 252, step: 4
5240 01:37:02.871780 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5241 01:37:02.875006 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5242 01:37:02.878385 iDelay=203, Bit 2, Center 98 (7 ~ 190) 184
5243 01:37:02.885008 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5244 01:37:02.888532 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5245 01:37:02.891660 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5246 01:37:02.894645 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5247 01:37:02.898262 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5248 01:37:02.904846 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5249 01:37:02.907992 iDelay=203, Bit 9, Center 74 (-13 ~ 162) 176
5250 01:37:02.911483 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5251 01:37:02.914890 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5252 01:37:02.918125 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5253 01:37:02.924316 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5254 01:37:02.927662 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5255 01:37:02.931126 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5256 01:37:02.931588 ==
5257 01:37:02.934301 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 01:37:02.937584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 01:37:02.938062 ==
5260 01:37:02.941094 DQS Delay:
5261 01:37:02.941712 DQS0 = 0, DQS1 = 0
5262 01:37:02.944227 DQM Delay:
5263 01:37:02.944682 DQM0 = 98, DQM1 = 86
5264 01:37:02.945043 DQ Delay:
5265 01:37:02.947878 DQ0 =92, DQ1 =98, DQ2 =98, DQ3 =92
5266 01:37:02.950723 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =108
5267 01:37:02.954070 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =78
5268 01:37:02.957539 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5269 01:37:02.958099
5270 01:37:02.958467
5271 01:37:02.967708 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5272 01:37:02.970976 CH0 RK1: MR19=505, MR18=2F2F
5273 01:37:02.974046 CH0_RK1: MR19=0x505, MR18=0x2F2F, DQSOSC=407, MR23=63, INC=65, DEC=43
5274 01:37:02.977534 [RxdqsGatingPostProcess] freq 933
5275 01:37:02.984299 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5276 01:37:02.987350 Pre-setting of DQS Precalculation
5277 01:37:02.990639 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5278 01:37:02.994400 ==
5279 01:37:02.997615 Dram Type= 6, Freq= 0, CH_1, rank 0
5280 01:37:03.001380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5281 01:37:03.002061 ==
5282 01:37:03.003944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5283 01:37:03.010563 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5284 01:37:03.014375 [CA 0] Center 37 (6~68) winsize 63
5285 01:37:03.017890 [CA 1] Center 37 (6~68) winsize 63
5286 01:37:03.020836 [CA 2] Center 34 (4~65) winsize 62
5287 01:37:03.024343 [CA 3] Center 34 (3~65) winsize 63
5288 01:37:03.027610 [CA 4] Center 33 (2~64) winsize 63
5289 01:37:03.030906 [CA 5] Center 33 (2~64) winsize 63
5290 01:37:03.031465
5291 01:37:03.033897 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5292 01:37:03.034360
5293 01:37:03.037477 [CATrainingPosCal] consider 1 rank data
5294 01:37:03.040740 u2DelayCellTimex100 = 270/100 ps
5295 01:37:03.044110 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5296 01:37:03.050434 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5297 01:37:03.053943 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5298 01:37:03.057220 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5299 01:37:03.060150 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5300 01:37:03.063590 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5301 01:37:03.063902
5302 01:37:03.066878 CA PerBit enable=1, Macro0, CA PI delay=33
5303 01:37:03.067114
5304 01:37:03.070337 [CBTSetCACLKResult] CA Dly = 33
5305 01:37:03.073358 CS Dly: 5 (0~36)
5306 01:37:03.073613 ==
5307 01:37:03.076928 Dram Type= 6, Freq= 0, CH_1, rank 1
5308 01:37:03.080078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5309 01:37:03.080407 ==
5310 01:37:03.087124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5311 01:37:03.090007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5312 01:37:03.093883 [CA 0] Center 37 (6~68) winsize 63
5313 01:37:03.097225 [CA 1] Center 37 (6~68) winsize 63
5314 01:37:03.100764 [CA 2] Center 34 (4~65) winsize 62
5315 01:37:03.103775 [CA 3] Center 34 (4~65) winsize 62
5316 01:37:03.106859 [CA 4] Center 33 (2~64) winsize 63
5317 01:37:03.110365 [CA 5] Center 33 (2~64) winsize 63
5318 01:37:03.110657
5319 01:37:03.113737 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5320 01:37:03.114152
5321 01:37:03.117421 [CATrainingPosCal] consider 2 rank data
5322 01:37:03.121017 u2DelayCellTimex100 = 270/100 ps
5323 01:37:03.124386 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5324 01:37:03.130520 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5325 01:37:03.133593 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5326 01:37:03.136944 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5327 01:37:03.140146 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5328 01:37:03.143313 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5329 01:37:03.143769
5330 01:37:03.146961 CA PerBit enable=1, Macro0, CA PI delay=33
5331 01:37:03.147519
5332 01:37:03.150013 [CBTSetCACLKResult] CA Dly = 33
5333 01:37:03.153669 CS Dly: 5 (0~37)
5334 01:37:03.154131
5335 01:37:03.156604 ----->DramcWriteLeveling(PI) begin...
5336 01:37:03.157066 ==
5337 01:37:03.160108 Dram Type= 6, Freq= 0, CH_1, rank 0
5338 01:37:03.163162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5339 01:37:03.163620 ==
5340 01:37:03.166664 Write leveling (Byte 0): 23 => 23
5341 01:37:03.169951 Write leveling (Byte 1): 23 => 23
5342 01:37:03.173515 DramcWriteLeveling(PI) end<-----
5343 01:37:03.174068
5344 01:37:03.174428 ==
5345 01:37:03.176544 Dram Type= 6, Freq= 0, CH_1, rank 0
5346 01:37:03.179777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5347 01:37:03.180339 ==
5348 01:37:03.183131 [Gating] SW mode calibration
5349 01:37:03.189884 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 01:37:03.196699 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5351 01:37:03.199709 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 01:37:03.202832 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 01:37:03.210023 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 01:37:03.213220 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 01:37:03.216515 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5356 01:37:03.223178 0 10 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
5357 01:37:03.226670 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5358 01:37:03.229918 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 01:37:03.236025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 01:37:03.239377 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 01:37:03.242628 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 01:37:03.249817 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 01:37:03.252855 0 11 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5364 01:37:03.256184 0 11 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
5365 01:37:03.262820 0 11 24 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5366 01:37:03.265932 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 01:37:03.269387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 01:37:03.275985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 01:37:03.279162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 01:37:03.282891 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 01:37:03.289268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 01:37:03.292547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5373 01:37:03.295998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 01:37:03.302507 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 01:37:03.305613 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 01:37:03.309024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 01:37:03.315668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 01:37:03.318799 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 01:37:03.322258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 01:37:03.328551 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 01:37:03.332161 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 01:37:03.335102 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 01:37:03.341658 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 01:37:03.345593 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 01:37:03.348670 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 01:37:03.354901 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 01:37:03.358687 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5388 01:37:03.361937 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5389 01:37:03.368185 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 01:37:03.368660 Total UI for P1: 0, mck2ui 16
5391 01:37:03.374724 best dqsien dly found for B0: ( 0, 14, 18)
5392 01:37:03.375286 Total UI for P1: 0, mck2ui 16
5393 01:37:03.381546 best dqsien dly found for B1: ( 0, 14, 20)
5394 01:37:03.385041 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5395 01:37:03.388383 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5396 01:37:03.388965
5397 01:37:03.391321 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5398 01:37:03.394984 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5399 01:37:03.398029 [Gating] SW calibration Done
5400 01:37:03.398502 ==
5401 01:37:03.401384 Dram Type= 6, Freq= 0, CH_1, rank 0
5402 01:37:03.404860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5403 01:37:03.405491 ==
5404 01:37:03.408420 RX Vref Scan: 0
5405 01:37:03.408994
5406 01:37:03.409552 RX Vref 0 -> 0, step: 1
5407 01:37:03.410001
5408 01:37:03.411389 RX Delay -80 -> 252, step: 8
5409 01:37:03.414786 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5410 01:37:03.421410 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5411 01:37:03.424643 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5412 01:37:03.427645 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5413 01:37:03.430959 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5414 01:37:03.434347 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5415 01:37:03.437869 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5416 01:37:03.444299 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5417 01:37:03.447865 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5418 01:37:03.451113 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5419 01:37:03.454225 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5420 01:37:03.457392 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5421 01:37:03.464340 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5422 01:37:03.467601 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5423 01:37:03.470771 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5424 01:37:03.473949 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5425 01:37:03.474410 ==
5426 01:37:03.477527 Dram Type= 6, Freq= 0, CH_1, rank 0
5427 01:37:03.484350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5428 01:37:03.484915 ==
5429 01:37:03.485283 DQS Delay:
5430 01:37:03.487135 DQS0 = 0, DQS1 = 0
5431 01:37:03.487592 DQM Delay:
5432 01:37:03.487952 DQM0 = 93, DQM1 = 86
5433 01:37:03.490693 DQ Delay:
5434 01:37:03.493709 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5435 01:37:03.497609 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91
5436 01:37:03.500710 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5437 01:37:03.503852 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =91
5438 01:37:03.504413
5439 01:37:03.504776
5440 01:37:03.505110 ==
5441 01:37:03.507394 Dram Type= 6, Freq= 0, CH_1, rank 0
5442 01:37:03.510811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5443 01:37:03.511363 ==
5444 01:37:03.511725
5445 01:37:03.512057
5446 01:37:03.513752 TX Vref Scan disable
5447 01:37:03.514208 == TX Byte 0 ==
5448 01:37:03.520501 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5449 01:37:03.523700 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5450 01:37:03.524257 == TX Byte 1 ==
5451 01:37:03.530352 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5452 01:37:03.533776 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5453 01:37:03.534419 ==
5454 01:37:03.536921 Dram Type= 6, Freq= 0, CH_1, rank 0
5455 01:37:03.540477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5456 01:37:03.541054 ==
5457 01:37:03.543511
5458 01:37:03.544030
5459 01:37:03.544501 TX Vref Scan disable
5460 01:37:03.546860 == TX Byte 0 ==
5461 01:37:03.550232 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5462 01:37:03.556633 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5463 01:37:03.557364 == TX Byte 1 ==
5464 01:37:03.560018 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5465 01:37:03.566478 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5466 01:37:03.567044
5467 01:37:03.567527 [DATLAT]
5468 01:37:03.567976 Freq=933, CH1 RK0
5469 01:37:03.568414
5470 01:37:03.569659 DATLAT Default: 0xd
5471 01:37:03.570132 0, 0xFFFF, sum = 0
5472 01:37:03.573063 1, 0xFFFF, sum = 0
5473 01:37:03.576715 2, 0xFFFF, sum = 0
5474 01:37:03.577331 3, 0xFFFF, sum = 0
5475 01:37:03.579794 4, 0xFFFF, sum = 0
5476 01:37:03.580297 5, 0xFFFF, sum = 0
5477 01:37:03.583019 6, 0xFFFF, sum = 0
5478 01:37:03.583499 7, 0xFFFF, sum = 0
5479 01:37:03.586453 8, 0xFFFF, sum = 0
5480 01:37:03.586930 9, 0xFFFF, sum = 0
5481 01:37:03.589675 10, 0x0, sum = 1
5482 01:37:03.590155 11, 0x0, sum = 2
5483 01:37:03.593663 12, 0x0, sum = 3
5484 01:37:03.594244 13, 0x0, sum = 4
5485 01:37:03.594739 best_step = 11
5486 01:37:03.596604
5487 01:37:03.597177 ==
5488 01:37:03.599829 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 01:37:03.603048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5490 01:37:03.603530 ==
5491 01:37:03.604007 RX Vref Scan: 1
5492 01:37:03.604454
5493 01:37:03.606149 RX Vref 0 -> 0, step: 1
5494 01:37:03.606623
5495 01:37:03.609688 RX Delay -69 -> 252, step: 4
5496 01:37:03.610258
5497 01:37:03.612907 Set Vref, RX VrefLevel [Byte0]: 52
5498 01:37:03.616173 [Byte1]: 48
5499 01:37:03.619425
5500 01:37:03.619959 Final RX Vref Byte 0 = 52 to rank0
5501 01:37:03.622947 Final RX Vref Byte 1 = 48 to rank0
5502 01:37:03.625956 Final RX Vref Byte 0 = 52 to rank1
5503 01:37:03.629633 Final RX Vref Byte 1 = 48 to rank1==
5504 01:37:03.632788 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 01:37:03.639751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5506 01:37:03.640328 ==
5507 01:37:03.640809 DQS Delay:
5508 01:37:03.641255 DQS0 = 0, DQS1 = 0
5509 01:37:03.643422 DQM Delay:
5510 01:37:03.644058 DQM0 = 94, DQM1 = 87
5511 01:37:03.645787 DQ Delay:
5512 01:37:03.649069 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5513 01:37:03.652616 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5514 01:37:03.655620 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5515 01:37:03.659190 DQ12 =94, DQ13 =98, DQ14 =98, DQ15 =98
5516 01:37:03.659663
5517 01:37:03.660135
5518 01:37:03.665918 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5519 01:37:03.668959 CH1 RK0: MR19=505, MR18=3232
5520 01:37:03.675670 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5521 01:37:03.676254
5522 01:37:03.678788 ----->DramcWriteLeveling(PI) begin...
5523 01:37:03.679302 ==
5524 01:37:03.681955 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 01:37:03.685723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 01:37:03.686301 ==
5527 01:37:03.688730 Write leveling (Byte 0): 25 => 25
5528 01:37:03.691946 Write leveling (Byte 1): 26 => 26
5529 01:37:03.695491 DramcWriteLeveling(PI) end<-----
5530 01:37:03.696064
5531 01:37:03.696540 ==
5532 01:37:03.698599 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 01:37:03.701784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5534 01:37:03.705322 ==
5535 01:37:03.705902 [Gating] SW mode calibration
5536 01:37:03.711785 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 01:37:03.718654 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5538 01:37:03.721936 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 01:37:03.728465 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 01:37:03.731816 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 01:37:03.734892 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5542 01:37:03.741900 0 10 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5543 01:37:03.744957 0 10 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5544 01:37:03.748408 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 01:37:03.754831 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 01:37:03.758601 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 01:37:03.761273 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 01:37:03.767997 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 01:37:03.771825 0 11 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5550 01:37:03.774983 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5551 01:37:03.781529 0 11 20 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
5552 01:37:03.784704 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 01:37:03.787851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 01:37:03.794551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 01:37:03.798337 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 01:37:03.801246 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 01:37:03.807812 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 01:37:03.811045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5559 01:37:03.814472 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5560 01:37:03.821217 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 01:37:03.824337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 01:37:03.827418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 01:37:03.834281 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 01:37:03.838249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 01:37:03.840717 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 01:37:03.847387 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 01:37:03.850779 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 01:37:03.853882 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 01:37:03.860607 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 01:37:03.863844 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 01:37:03.867360 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 01:37:03.873453 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 01:37:03.877430 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 01:37:03.880371 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 01:37:03.886686 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5576 01:37:03.887251 Total UI for P1: 0, mck2ui 16
5577 01:37:03.893379 best dqsien dly found for B0: ( 0, 14, 18)
5578 01:37:03.896672 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 01:37:03.899849 Total UI for P1: 0, mck2ui 16
5580 01:37:03.903736 best dqsien dly found for B1: ( 0, 14, 20)
5581 01:37:03.906405 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5582 01:37:03.909885 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5583 01:37:03.910460
5584 01:37:03.913161 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5585 01:37:03.916882 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5586 01:37:03.919903 [Gating] SW calibration Done
5587 01:37:03.920470 ==
5588 01:37:03.923048 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 01:37:03.926390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5590 01:37:03.929887 ==
5591 01:37:03.930435 RX Vref Scan: 0
5592 01:37:03.930797
5593 01:37:03.932855 RX Vref 0 -> 0, step: 1
5594 01:37:03.933340
5595 01:37:03.936234 RX Delay -80 -> 252, step: 8
5596 01:37:03.939699 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5597 01:37:03.942934 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5598 01:37:03.945980 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5599 01:37:03.949748 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5600 01:37:03.952734 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5601 01:37:03.959219 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5602 01:37:03.962821 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5603 01:37:03.965826 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5604 01:37:03.969507 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5605 01:37:03.972770 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5606 01:37:03.978995 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5607 01:37:03.982645 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5608 01:37:03.985697 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5609 01:37:03.989401 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5610 01:37:03.992533 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5611 01:37:03.999017 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5612 01:37:03.999476 ==
5613 01:37:04.002148 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 01:37:04.005856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5615 01:37:04.006317 ==
5616 01:37:04.006680 DQS Delay:
5617 01:37:04.008905 DQS0 = 0, DQS1 = 0
5618 01:37:04.009403 DQM Delay:
5619 01:37:04.012302 DQM0 = 95, DQM1 = 87
5620 01:37:04.012758 DQ Delay:
5621 01:37:04.016061 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5622 01:37:04.019029 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5623 01:37:04.022245 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5624 01:37:04.025611 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5625 01:37:04.026175
5626 01:37:04.026541
5627 01:37:04.026877 ==
5628 01:37:04.028939 Dram Type= 6, Freq= 0, CH_1, rank 1
5629 01:37:04.032026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5630 01:37:04.032490 ==
5631 01:37:04.035182
5632 01:37:04.035636
5633 01:37:04.036077 TX Vref Scan disable
5634 01:37:04.038744 == TX Byte 0 ==
5635 01:37:04.041920 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5636 01:37:04.045518 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5637 01:37:04.048814 == TX Byte 1 ==
5638 01:37:04.052042 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5639 01:37:04.055563 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5640 01:37:04.056026 ==
5641 01:37:04.058507 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 01:37:04.065641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5643 01:37:04.066223 ==
5644 01:37:04.066588
5645 01:37:04.066923
5646 01:37:04.068437 TX Vref Scan disable
5647 01:37:04.068893 == TX Byte 0 ==
5648 01:37:04.075278 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5649 01:37:04.078365 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5650 01:37:04.078826 == TX Byte 1 ==
5651 01:37:04.084934 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5652 01:37:04.088485 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5653 01:37:04.089042
5654 01:37:04.089462 [DATLAT]
5655 01:37:04.091942 Freq=933, CH1 RK1
5656 01:37:04.092498
5657 01:37:04.092863 DATLAT Default: 0xb
5658 01:37:04.095133 0, 0xFFFF, sum = 0
5659 01:37:04.095608 1, 0xFFFF, sum = 0
5660 01:37:04.098428 2, 0xFFFF, sum = 0
5661 01:37:04.098897 3, 0xFFFF, sum = 0
5662 01:37:04.101798 4, 0xFFFF, sum = 0
5663 01:37:04.102362 5, 0xFFFF, sum = 0
5664 01:37:04.104930 6, 0xFFFF, sum = 0
5665 01:37:04.105432 7, 0xFFFF, sum = 0
5666 01:37:04.108305 8, 0xFFFF, sum = 0
5667 01:37:04.108889 9, 0xFFFF, sum = 0
5668 01:37:04.111655 10, 0x0, sum = 1
5669 01:37:04.112273 11, 0x0, sum = 2
5670 01:37:04.115119 12, 0x0, sum = 3
5671 01:37:04.115587 13, 0x0, sum = 4
5672 01:37:04.118174 best_step = 11
5673 01:37:04.118751
5674 01:37:04.119242 ==
5675 01:37:04.121506 Dram Type= 6, Freq= 0, CH_1, rank 1
5676 01:37:04.124989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5677 01:37:04.125602 ==
5678 01:37:04.128047 RX Vref Scan: 0
5679 01:37:04.128503
5680 01:37:04.128862 RX Vref 0 -> 0, step: 1
5681 01:37:04.129200
5682 01:37:04.131398 RX Delay -69 -> 252, step: 4
5683 01:37:04.138496 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5684 01:37:04.141989 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5685 01:37:04.145193 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5686 01:37:04.148720 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5687 01:37:04.152176 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5688 01:37:04.155441 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5689 01:37:04.161792 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5690 01:37:04.165505 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5691 01:37:04.168638 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5692 01:37:04.171798 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5693 01:37:04.175305 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5694 01:37:04.181732 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5695 01:37:04.185127 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5696 01:37:04.188477 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5697 01:37:04.191889 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5698 01:37:04.194848 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5699 01:37:04.195345 ==
5700 01:37:04.198145 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 01:37:04.204713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 01:37:04.205177 ==
5703 01:37:04.205592 DQS Delay:
5704 01:37:04.208104 DQS0 = 0, DQS1 = 0
5705 01:37:04.208561 DQM Delay:
5706 01:37:04.208919 DQM0 = 96, DQM1 = 88
5707 01:37:04.211554 DQ Delay:
5708 01:37:04.215135 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =94
5709 01:37:04.218319 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5710 01:37:04.221547 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =80
5711 01:37:04.224791 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5712 01:37:04.225252
5713 01:37:04.225812
5714 01:37:04.231322 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5715 01:37:04.234667 CH1 RK1: MR19=505, MR18=1C1C
5716 01:37:04.241402 CH1_RK1: MR19=0x505, MR18=0x1C1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5717 01:37:04.244777 [RxdqsGatingPostProcess] freq 933
5718 01:37:04.251228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5719 01:37:04.251789 Pre-setting of DQS Precalculation
5720 01:37:04.257611 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5721 01:37:04.264160 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5722 01:37:04.271076 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5723 01:37:04.271636
5724 01:37:04.272002
5725 01:37:04.274102 [Calibration Summary] 1866 Mbps
5726 01:37:04.277444 CH 0, Rank 0
5727 01:37:04.277903 SW Impedance : PASS
5728 01:37:04.280703 DUTY Scan : NO K
5729 01:37:04.283967 ZQ Calibration : PASS
5730 01:37:04.284425 Jitter Meter : NO K
5731 01:37:04.287481 CBT Training : PASS
5732 01:37:04.290782 Write leveling : PASS
5733 01:37:04.291413 RX DQS gating : PASS
5734 01:37:04.293848 RX DQ/DQS(RDDQC) : PASS
5735 01:37:04.294321 TX DQ/DQS : PASS
5736 01:37:04.297525 RX DATLAT : PASS
5737 01:37:04.300531 RX DQ/DQS(Engine): PASS
5738 01:37:04.300986 TX OE : NO K
5739 01:37:04.303941 All Pass.
5740 01:37:04.304397
5741 01:37:04.304755 CH 0, Rank 1
5742 01:37:04.307559 SW Impedance : PASS
5743 01:37:04.308234 DUTY Scan : NO K
5744 01:37:04.311033 ZQ Calibration : PASS
5745 01:37:04.314173 Jitter Meter : NO K
5746 01:37:04.314633 CBT Training : PASS
5747 01:37:04.317248 Write leveling : PASS
5748 01:37:04.320370 RX DQS gating : PASS
5749 01:37:04.320824 RX DQ/DQS(RDDQC) : PASS
5750 01:37:04.323833 TX DQ/DQS : PASS
5751 01:37:04.327294 RX DATLAT : PASS
5752 01:37:04.327853 RX DQ/DQS(Engine): PASS
5753 01:37:04.330379 TX OE : NO K
5754 01:37:04.330840 All Pass.
5755 01:37:04.331200
5756 01:37:04.333678 CH 1, Rank 0
5757 01:37:04.334155 SW Impedance : PASS
5758 01:37:04.336850 DUTY Scan : NO K
5759 01:37:04.340471 ZQ Calibration : PASS
5760 01:37:04.341025 Jitter Meter : NO K
5761 01:37:04.343581 CBT Training : PASS
5762 01:37:04.346838 Write leveling : PASS
5763 01:37:04.347293 RX DQS gating : PASS
5764 01:37:04.350340 RX DQ/DQS(RDDQC) : PASS
5765 01:37:04.353892 TX DQ/DQS : PASS
5766 01:37:04.354457 RX DATLAT : PASS
5767 01:37:04.356831 RX DQ/DQS(Engine): PASS
5768 01:37:04.357312 TX OE : NO K
5769 01:37:04.360015 All Pass.
5770 01:37:04.360470
5771 01:37:04.360831 CH 1, Rank 1
5772 01:37:04.363511 SW Impedance : PASS
5773 01:37:04.366750 DUTY Scan : NO K
5774 01:37:04.367300 ZQ Calibration : PASS
5775 01:37:04.369997 Jitter Meter : NO K
5776 01:37:04.370461 CBT Training : PASS
5777 01:37:04.373176 Write leveling : PASS
5778 01:37:04.376717 RX DQS gating : PASS
5779 01:37:04.377401 RX DQ/DQS(RDDQC) : PASS
5780 01:37:04.379781 TX DQ/DQS : PASS
5781 01:37:04.383476 RX DATLAT : PASS
5782 01:37:04.384032 RX DQ/DQS(Engine): PASS
5783 01:37:04.386352 TX OE : NO K
5784 01:37:04.386806 All Pass.
5785 01:37:04.387165
5786 01:37:04.389678 DramC Write-DBI off
5787 01:37:04.393323 PER_BANK_REFRESH: Hybrid Mode
5788 01:37:04.393874 TX_TRACKING: ON
5789 01:37:04.403328 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5790 01:37:04.406493 [FAST_K] Save calibration result to emmc
5791 01:37:04.409688 dramc_set_vcore_voltage set vcore to 650000
5792 01:37:04.413075 Read voltage for 400, 6
5793 01:37:04.413659 Vio18 = 0
5794 01:37:04.416401 Vcore = 650000
5795 01:37:04.416955 Vdram = 0
5796 01:37:04.417347 Vddq = 0
5797 01:37:04.417686 Vmddr = 0
5798 01:37:04.422791 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5799 01:37:04.426297 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5800 01:37:04.429338 MEM_TYPE=3, freq_sel=20
5801 01:37:04.432671 sv_algorithm_assistance_LP4_800
5802 01:37:04.436140 ============ PULL DRAM RESETB DOWN ============
5803 01:37:04.442490 ========== PULL DRAM RESETB DOWN end =========
5804 01:37:04.446017 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5805 01:37:04.449553 ===================================
5806 01:37:04.452603 LPDDR4 DRAM CONFIGURATION
5807 01:37:04.455865 ===================================
5808 01:37:04.456422 EX_ROW_EN[0] = 0x0
5809 01:37:04.459015 EX_ROW_EN[1] = 0x0
5810 01:37:04.459466 LP4Y_EN = 0x0
5811 01:37:04.462434 WORK_FSP = 0x0
5812 01:37:04.462983 WL = 0x2
5813 01:37:04.465913 RL = 0x2
5814 01:37:04.466367 BL = 0x2
5815 01:37:04.469037 RPST = 0x0
5816 01:37:04.472202 RD_PRE = 0x0
5817 01:37:04.472653 WR_PRE = 0x1
5818 01:37:04.475510 WR_PST = 0x0
5819 01:37:04.475963 DBI_WR = 0x0
5820 01:37:04.478703 DBI_RD = 0x0
5821 01:37:04.479160 OTF = 0x1
5822 01:37:04.482171 ===================================
5823 01:37:04.485506 ===================================
5824 01:37:04.489166 ANA top config
5825 01:37:04.492021 ===================================
5826 01:37:04.492595 DLL_ASYNC_EN = 0
5827 01:37:04.495240 ALL_SLAVE_EN = 1
5828 01:37:04.498370 NEW_RANK_MODE = 1
5829 01:37:04.501836 DLL_IDLE_MODE = 1
5830 01:37:04.502289 LP45_APHY_COMB_EN = 1
5831 01:37:04.504993 TX_ODT_DIS = 1
5832 01:37:04.508516 NEW_8X_MODE = 1
5833 01:37:04.512004 ===================================
5834 01:37:04.515007 ===================================
5835 01:37:04.518463 data_rate = 800
5836 01:37:04.521745 CKR = 1
5837 01:37:04.524911 DQ_P2S_RATIO = 4
5838 01:37:04.528510 ===================================
5839 01:37:04.529057 CA_P2S_RATIO = 4
5840 01:37:04.531437 DQ_CA_OPEN = 0
5841 01:37:04.534699 DQ_SEMI_OPEN = 1
5842 01:37:04.538097 CA_SEMI_OPEN = 1
5843 01:37:04.541908 CA_FULL_RATE = 0
5844 01:37:04.544937 DQ_CKDIV4_EN = 0
5845 01:37:04.545571 CA_CKDIV4_EN = 1
5846 01:37:04.548218 CA_PREDIV_EN = 0
5847 01:37:04.551517 PH8_DLY = 0
5848 01:37:04.554756 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5849 01:37:04.558125 DQ_AAMCK_DIV = 0
5850 01:37:04.561572 CA_AAMCK_DIV = 0
5851 01:37:04.562080 CA_ADMCK_DIV = 4
5852 01:37:04.564542 DQ_TRACK_CA_EN = 0
5853 01:37:04.567938 CA_PICK = 800
5854 01:37:04.571487 CA_MCKIO = 400
5855 01:37:04.574419 MCKIO_SEMI = 400
5856 01:37:04.577920 PLL_FREQ = 3016
5857 01:37:04.581367 DQ_UI_PI_RATIO = 32
5858 01:37:04.584539 CA_UI_PI_RATIO = 32
5859 01:37:04.587773 ===================================
5860 01:37:04.591147 ===================================
5861 01:37:04.591728 memory_type:LPDDR4
5862 01:37:04.594121 GP_NUM : 10
5863 01:37:04.597332 SRAM_EN : 1
5864 01:37:04.597885 MD32_EN : 0
5865 01:37:04.600912 ===================================
5866 01:37:04.604185 [ANA_INIT] >>>>>>>>>>>>>>
5867 01:37:04.607389 <<<<<< [CONFIGURE PHASE]: ANA_TX
5868 01:37:04.610669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5869 01:37:04.613852 ===================================
5870 01:37:04.617572 data_rate = 800,PCW = 0X7400
5871 01:37:04.621109 ===================================
5872 01:37:04.623922 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5873 01:37:04.627079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5874 01:37:04.640608 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5875 01:37:04.643700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5876 01:37:04.647309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5877 01:37:04.650577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5878 01:37:04.654103 [ANA_INIT] flow start
5879 01:37:04.657197 [ANA_INIT] PLL >>>>>>>>
5880 01:37:04.657792 [ANA_INIT] PLL <<<<<<<<
5881 01:37:04.660379 [ANA_INIT] MIDPI >>>>>>>>
5882 01:37:04.663530 [ANA_INIT] MIDPI <<<<<<<<
5883 01:37:04.663984 [ANA_INIT] DLL >>>>>>>>
5884 01:37:04.666961 [ANA_INIT] flow end
5885 01:37:04.669950 ============ LP4 DIFF to SE enter ============
5886 01:37:04.673659 ============ LP4 DIFF to SE exit ============
5887 01:37:04.676975 [ANA_INIT] <<<<<<<<<<<<<
5888 01:37:04.679969 [Flow] Enable top DCM control >>>>>
5889 01:37:04.683578 [Flow] Enable top DCM control <<<<<
5890 01:37:04.686585 Enable DLL master slave shuffle
5891 01:37:04.693680 ==============================================================
5892 01:37:04.694260 Gating Mode config
5893 01:37:04.700221 ==============================================================
5894 01:37:04.703145 Config description:
5895 01:37:04.710079 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5896 01:37:04.716761 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5897 01:37:04.723242 SELPH_MODE 0: By rank 1: By Phase
5898 01:37:04.729491 ==============================================================
5899 01:37:04.729954 GAT_TRACK_EN = 0
5900 01:37:04.732717 RX_GATING_MODE = 2
5901 01:37:04.736401 RX_GATING_TRACK_MODE = 2
5902 01:37:04.739678 SELPH_MODE = 1
5903 01:37:04.742592 PICG_EARLY_EN = 1
5904 01:37:04.745977 VALID_LAT_VALUE = 1
5905 01:37:04.752731 ==============================================================
5906 01:37:04.755911 Enter into Gating configuration >>>>
5907 01:37:04.759381 Exit from Gating configuration <<<<
5908 01:37:04.762523 Enter into DVFS_PRE_config >>>>>
5909 01:37:04.772662 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5910 01:37:04.775884 Exit from DVFS_PRE_config <<<<<
5911 01:37:04.779038 Enter into PICG configuration >>>>
5912 01:37:04.782629 Exit from PICG configuration <<<<
5913 01:37:04.785828 [RX_INPUT] configuration >>>>>
5914 01:37:04.789234 [RX_INPUT] configuration <<<<<
5915 01:37:04.792712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5916 01:37:04.799217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5917 01:37:04.805489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5918 01:37:04.812186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5919 01:37:04.815386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5920 01:37:04.822319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5921 01:37:04.825703 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5922 01:37:04.832331 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5923 01:37:04.835076 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5924 01:37:04.838518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5925 01:37:04.841629 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5926 01:37:04.848309 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5927 01:37:04.852086 ===================================
5928 01:37:04.855380 LPDDR4 DRAM CONFIGURATION
5929 01:37:04.858315 ===================================
5930 01:37:04.858773 EX_ROW_EN[0] = 0x0
5931 01:37:04.861805 EX_ROW_EN[1] = 0x0
5932 01:37:04.862363 LP4Y_EN = 0x0
5933 01:37:04.864825 WORK_FSP = 0x0
5934 01:37:04.865275 WL = 0x2
5935 01:37:04.868407 RL = 0x2
5936 01:37:04.868965 BL = 0x2
5937 01:37:04.871823 RPST = 0x0
5938 01:37:04.872377 RD_PRE = 0x0
5939 01:37:04.874732 WR_PRE = 0x1
5940 01:37:04.875184 WR_PST = 0x0
5941 01:37:04.878438 DBI_WR = 0x0
5942 01:37:04.878987 DBI_RD = 0x0
5943 01:37:04.881367 OTF = 0x1
5944 01:37:04.884985 ===================================
5945 01:37:04.888287 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5946 01:37:04.891228 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5947 01:37:04.897868 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5948 01:37:04.901191 ===================================
5949 01:37:04.904733 LPDDR4 DRAM CONFIGURATION
5950 01:37:04.905284 ===================================
5951 01:37:04.907641 EX_ROW_EN[0] = 0x10
5952 01:37:04.911300 EX_ROW_EN[1] = 0x0
5953 01:37:04.911864 LP4Y_EN = 0x0
5954 01:37:04.914281 WORK_FSP = 0x0
5955 01:37:04.914737 WL = 0x2
5956 01:37:04.917720 RL = 0x2
5957 01:37:04.918173 BL = 0x2
5958 01:37:04.921420 RPST = 0x0
5959 01:37:04.922009 RD_PRE = 0x0
5960 01:37:04.924604 WR_PRE = 0x1
5961 01:37:04.925154 WR_PST = 0x0
5962 01:37:04.927605 DBI_WR = 0x0
5963 01:37:04.928218 DBI_RD = 0x0
5964 01:37:04.930758 OTF = 0x1
5965 01:37:04.934306 ===================================
5966 01:37:04.940932 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5967 01:37:04.944116 nWR fixed to 30
5968 01:37:04.947352 [ModeRegInit_LP4] CH0 RK0
5969 01:37:04.947807 [ModeRegInit_LP4] CH0 RK1
5970 01:37:04.951008 [ModeRegInit_LP4] CH1 RK0
5971 01:37:04.954033 [ModeRegInit_LP4] CH1 RK1
5972 01:37:04.954589 match AC timing 18
5973 01:37:04.960761 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5974 01:37:04.963919 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5975 01:37:04.967306 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5976 01:37:04.974131 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5977 01:37:04.977558 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5978 01:37:04.978111 ==
5979 01:37:04.980773 Dram Type= 6, Freq= 0, CH_0, rank 0
5980 01:37:04.984569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5981 01:37:04.985133 ==
5982 01:37:04.990767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5983 01:37:04.997119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5984 01:37:05.000750 [CA 0] Center 36 (8~64) winsize 57
5985 01:37:05.003947 [CA 1] Center 36 (8~64) winsize 57
5986 01:37:05.007331 [CA 2] Center 36 (8~64) winsize 57
5987 01:37:05.010521 [CA 3] Center 36 (8~64) winsize 57
5988 01:37:05.010978 [CA 4] Center 36 (8~64) winsize 57
5989 01:37:05.014008 [CA 5] Center 36 (8~64) winsize 57
5990 01:37:05.014640
5991 01:37:05.020526 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5992 01:37:05.021184
5993 01:37:05.023493 [CATrainingPosCal] consider 1 rank data
5994 01:37:05.026895 u2DelayCellTimex100 = 270/100 ps
5995 01:37:05.030055 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 01:37:05.033432 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 01:37:05.037073 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 01:37:05.040206 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 01:37:05.043362 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 01:37:05.046919 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 01:37:05.047373
6002 01:37:05.049952 CA PerBit enable=1, Macro0, CA PI delay=36
6003 01:37:05.050406
6004 01:37:05.053267 [CBTSetCACLKResult] CA Dly = 36
6005 01:37:05.056680 CS Dly: 1 (0~32)
6006 01:37:05.057228 ==
6007 01:37:05.060025 Dram Type= 6, Freq= 0, CH_0, rank 1
6008 01:37:05.063181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6009 01:37:05.063663 ==
6010 01:37:05.069951 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6011 01:37:05.076800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6012 01:37:05.079852 [CA 0] Center 36 (8~64) winsize 57
6013 01:37:05.080311 [CA 1] Center 36 (8~64) winsize 57
6014 01:37:05.082896 [CA 2] Center 36 (8~64) winsize 57
6015 01:37:05.086448 [CA 3] Center 36 (8~64) winsize 57
6016 01:37:05.090026 [CA 4] Center 36 (8~64) winsize 57
6017 01:37:05.093363 [CA 5] Center 36 (8~64) winsize 57
6018 01:37:05.093917
6019 01:37:05.096396 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6020 01:37:05.099708
6021 01:37:05.103213 [CATrainingPosCal] consider 2 rank data
6022 01:37:05.103772 u2DelayCellTimex100 = 270/100 ps
6023 01:37:05.109807 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 01:37:05.112892 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 01:37:05.116035 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 01:37:05.119810 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 01:37:05.122398 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 01:37:05.125929 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 01:37:05.126484
6030 01:37:05.129317 CA PerBit enable=1, Macro0, CA PI delay=36
6031 01:37:05.129792
6032 01:37:05.132692 [CBTSetCACLKResult] CA Dly = 36
6033 01:37:05.135940 CS Dly: 1 (0~32)
6034 01:37:05.136486
6035 01:37:05.138979 ----->DramcWriteLeveling(PI) begin...
6036 01:37:05.139446 ==
6037 01:37:05.142369 Dram Type= 6, Freq= 0, CH_0, rank 0
6038 01:37:05.145716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6039 01:37:05.146192 ==
6040 01:37:05.149247 Write leveling (Byte 0): 32 => 0
6041 01:37:05.152432 Write leveling (Byte 1): 32 => 0
6042 01:37:05.155778 DramcWriteLeveling(PI) end<-----
6043 01:37:05.156343
6044 01:37:05.156709 ==
6045 01:37:05.158970 Dram Type= 6, Freq= 0, CH_0, rank 0
6046 01:37:05.162222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6047 01:37:05.162681 ==
6048 01:37:05.165759 [Gating] SW mode calibration
6049 01:37:05.172427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6050 01:37:05.178675 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6051 01:37:05.182029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6052 01:37:05.185649 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6053 01:37:05.192309 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6054 01:37:05.195883 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6055 01:37:05.198888 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6056 01:37:05.205802 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6057 01:37:05.208803 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6058 01:37:05.212506 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6059 01:37:05.218666 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6060 01:37:05.219222 Total UI for P1: 0, mck2ui 16
6061 01:37:05.225466 best dqsien dly found for B0: ( 0, 10, 16)
6062 01:37:05.226023 Total UI for P1: 0, mck2ui 16
6063 01:37:05.231541 best dqsien dly found for B1: ( 0, 10, 24)
6064 01:37:05.235325 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6065 01:37:05.238447 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6066 01:37:05.238908
6067 01:37:05.241805 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6068 01:37:05.245158 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6069 01:37:05.248290 [Gating] SW calibration Done
6070 01:37:05.248741 ==
6071 01:37:05.251751 Dram Type= 6, Freq= 0, CH_0, rank 0
6072 01:37:05.255153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6073 01:37:05.255713 ==
6074 01:37:05.258320 RX Vref Scan: 0
6075 01:37:05.258880
6076 01:37:05.259240 RX Vref 0 -> 0, step: 1
6077 01:37:05.262253
6078 01:37:05.262803 RX Delay -410 -> 252, step: 16
6079 01:37:05.268362 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6080 01:37:05.271878 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6081 01:37:05.275271 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6082 01:37:05.278158 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6083 01:37:05.285140 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6084 01:37:05.288105 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6085 01:37:05.291628 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6086 01:37:05.294903 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6087 01:37:05.301406 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6088 01:37:05.304968 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6089 01:37:05.307876 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6090 01:37:05.314730 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6091 01:37:05.317860 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6092 01:37:05.321522 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6093 01:37:05.324334 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6094 01:37:05.330865 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6095 01:37:05.331403 ==
6096 01:37:05.334174 Dram Type= 6, Freq= 0, CH_0, rank 0
6097 01:37:05.337705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6098 01:37:05.338276 ==
6099 01:37:05.338669 DQS Delay:
6100 01:37:05.340739 DQS0 = 59, DQS1 = 59
6101 01:37:05.341193 DQM Delay:
6102 01:37:05.344273 DQM0 = 19, DQM1 = 15
6103 01:37:05.344996 DQ Delay:
6104 01:37:05.347687 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6105 01:37:05.350998 DQ4 =24, DQ5 =0, DQ6 =32, DQ7 =32
6106 01:37:05.354192 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6107 01:37:05.357600 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6108 01:37:05.358055
6109 01:37:05.358408
6110 01:37:05.358737 ==
6111 01:37:05.360693 Dram Type= 6, Freq= 0, CH_0, rank 0
6112 01:37:05.364355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6113 01:37:05.364930 ==
6114 01:37:05.365349
6115 01:37:05.365931
6116 01:37:05.367480 TX Vref Scan disable
6117 01:37:05.370588 == TX Byte 0 ==
6118 01:37:05.374023 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6119 01:37:05.377257 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6120 01:37:05.380686 == TX Byte 1 ==
6121 01:37:05.384185 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6122 01:37:05.387454 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6123 01:37:05.387910 ==
6124 01:37:05.390651 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 01:37:05.393885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 01:37:05.397651 ==
6127 01:37:05.398165
6128 01:37:05.398587
6129 01:37:05.398987 TX Vref Scan disable
6130 01:37:05.400324 == TX Byte 0 ==
6131 01:37:05.403623 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6132 01:37:05.407045 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6133 01:37:05.410347 == TX Byte 1 ==
6134 01:37:05.413598 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6135 01:37:05.416902 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6136 01:37:05.417358
6137 01:37:05.420370 [DATLAT]
6138 01:37:05.420845 Freq=400, CH0 RK0
6139 01:37:05.421177
6140 01:37:05.423681 DATLAT Default: 0xf
6141 01:37:05.424089 0, 0xFFFF, sum = 0
6142 01:37:05.426824 1, 0xFFFF, sum = 0
6143 01:37:05.427375 2, 0xFFFF, sum = 0
6144 01:37:05.430276 3, 0xFFFF, sum = 0
6145 01:37:05.430799 4, 0xFFFF, sum = 0
6146 01:37:05.433640 5, 0xFFFF, sum = 0
6147 01:37:05.434268 6, 0xFFFF, sum = 0
6148 01:37:05.436682 7, 0xFFFF, sum = 0
6149 01:37:05.437096 8, 0xFFFF, sum = 0
6150 01:37:05.440271 9, 0xFFFF, sum = 0
6151 01:37:05.443489 10, 0xFFFF, sum = 0
6152 01:37:05.443960 11, 0xFFFF, sum = 0
6153 01:37:05.446879 12, 0x0, sum = 1
6154 01:37:05.447295 13, 0x0, sum = 2
6155 01:37:05.447623 14, 0x0, sum = 3
6156 01:37:05.449932 15, 0x0, sum = 4
6157 01:37:05.450349 best_step = 13
6158 01:37:05.450668
6159 01:37:05.453572 ==
6160 01:37:05.456606 Dram Type= 6, Freq= 0, CH_0, rank 0
6161 01:37:05.459819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6162 01:37:05.460236 ==
6163 01:37:05.460562 RX Vref Scan: 1
6164 01:37:05.460862
6165 01:37:05.463556 RX Vref 0 -> 0, step: 1
6166 01:37:05.464068
6167 01:37:05.466456 RX Delay -359 -> 252, step: 8
6168 01:37:05.466887
6169 01:37:05.469922 Set Vref, RX VrefLevel [Byte0]: 51
6170 01:37:05.473464 [Byte1]: 48
6171 01:37:05.476916
6172 01:37:05.477358 Final RX Vref Byte 0 = 51 to rank0
6173 01:37:05.480257 Final RX Vref Byte 1 = 48 to rank0
6174 01:37:05.483218 Final RX Vref Byte 0 = 51 to rank1
6175 01:37:05.486622 Final RX Vref Byte 1 = 48 to rank1==
6176 01:37:05.489812 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 01:37:05.496586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 01:37:05.497025 ==
6179 01:37:05.497414 DQS Delay:
6180 01:37:05.500158 DQS0 = 52, DQS1 = 68
6181 01:37:05.500685 DQM Delay:
6182 01:37:05.501027 DQM0 = 8, DQM1 = 16
6183 01:37:05.503407 DQ Delay:
6184 01:37:05.506455 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6185 01:37:05.506898 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6186 01:37:05.509878 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6187 01:37:05.512979 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6188 01:37:05.513418
6189 01:37:05.516451
6190 01:37:05.522964 [DQSOSCAuto] RK0, (LSB)MR18= 0x9494, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6191 01:37:05.526161 CH0 RK0: MR19=C0C, MR18=9494
6192 01:37:05.533240 CH0_RK0: MR19=0xC0C, MR18=0x9494, DQSOSC=391, MR23=63, INC=386, DEC=257
6193 01:37:05.533830 ==
6194 01:37:05.536306 Dram Type= 6, Freq= 0, CH_0, rank 1
6195 01:37:05.539473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6196 01:37:05.539938 ==
6197 01:37:05.542783 [Gating] SW mode calibration
6198 01:37:05.549787 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6199 01:37:05.556498 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6200 01:37:05.559600 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6201 01:37:05.563157 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6202 01:37:05.569685 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6203 01:37:05.572755 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6204 01:37:05.576004 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6205 01:37:05.582878 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6206 01:37:05.586217 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6207 01:37:05.589477 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6208 01:37:05.592858 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6209 01:37:05.596085 Total UI for P1: 0, mck2ui 16
6210 01:37:05.599483 best dqsien dly found for B0: ( 0, 10, 16)
6211 01:37:05.602801 Total UI for P1: 0, mck2ui 16
6212 01:37:05.606039 best dqsien dly found for B1: ( 0, 10, 16)
6213 01:37:05.609346 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6214 01:37:05.616016 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6215 01:37:05.616583
6216 01:37:05.619154 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6217 01:37:05.622478 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6218 01:37:05.625850 [Gating] SW calibration Done
6219 01:37:05.626312 ==
6220 01:37:05.628991 Dram Type= 6, Freq= 0, CH_0, rank 1
6221 01:37:05.632537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6222 01:37:05.633108 ==
6223 01:37:05.636083 RX Vref Scan: 0
6224 01:37:05.636648
6225 01:37:05.637015 RX Vref 0 -> 0, step: 1
6226 01:37:05.637392
6227 01:37:05.638975 RX Delay -410 -> 252, step: 16
6228 01:37:05.645767 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6229 01:37:05.648867 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6230 01:37:05.652115 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6231 01:37:05.656071 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6232 01:37:05.662114 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6233 01:37:05.665206 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6234 01:37:05.668665 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6235 01:37:05.672308 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6236 01:37:05.678686 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6237 01:37:05.681839 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6238 01:37:05.685404 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6239 01:37:05.688545 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6240 01:37:05.695781 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6241 01:37:05.698522 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6242 01:37:05.702070 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6243 01:37:05.705201 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6244 01:37:05.708464 ==
6245 01:37:05.711857 Dram Type= 6, Freq= 0, CH_0, rank 1
6246 01:37:05.715256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6247 01:37:05.715825 ==
6248 01:37:05.716198 DQS Delay:
6249 01:37:05.718323 DQS0 = 43, DQS1 = 59
6250 01:37:05.718785 DQM Delay:
6251 01:37:05.721739 DQM0 = 7, DQM1 = 16
6252 01:37:05.722296 DQ Delay:
6253 01:37:05.724783 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6254 01:37:05.728508 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6255 01:37:05.731447 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6256 01:37:05.734647 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6257 01:37:05.735113
6258 01:37:05.735475
6259 01:37:05.735814 ==
6260 01:37:05.737961 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 01:37:05.741619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6262 01:37:05.742186 ==
6263 01:37:05.742553
6264 01:37:05.742889
6265 01:37:05.744790 TX Vref Scan disable
6266 01:37:05.745251 == TX Byte 0 ==
6267 01:37:05.751420 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6268 01:37:05.755061 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6269 01:37:05.755628 == TX Byte 1 ==
6270 01:37:05.761672 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6271 01:37:05.764837 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6272 01:37:05.765440 ==
6273 01:37:05.767927 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 01:37:05.771155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6275 01:37:05.771622 ==
6276 01:37:05.771987
6277 01:37:05.772326
6278 01:37:05.774575 TX Vref Scan disable
6279 01:37:05.775036 == TX Byte 0 ==
6280 01:37:05.781237 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6281 01:37:05.784595 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6282 01:37:05.785064 == TX Byte 1 ==
6283 01:37:05.791250 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6284 01:37:05.794766 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6285 01:37:05.795331
6286 01:37:05.795700 [DATLAT]
6287 01:37:05.797602 Freq=400, CH0 RK1
6288 01:37:05.798072
6289 01:37:05.798573 DATLAT Default: 0xd
6290 01:37:05.801550 0, 0xFFFF, sum = 0
6291 01:37:05.802116 1, 0xFFFF, sum = 0
6292 01:37:05.804299 2, 0xFFFF, sum = 0
6293 01:37:05.804756 3, 0xFFFF, sum = 0
6294 01:37:05.807722 4, 0xFFFF, sum = 0
6295 01:37:05.808179 5, 0xFFFF, sum = 0
6296 01:37:05.810782 6, 0xFFFF, sum = 0
6297 01:37:05.811237 7, 0xFFFF, sum = 0
6298 01:37:05.814459 8, 0xFFFF, sum = 0
6299 01:37:05.814917 9, 0xFFFF, sum = 0
6300 01:37:05.817557 10, 0xFFFF, sum = 0
6301 01:37:05.820724 11, 0xFFFF, sum = 0
6302 01:37:05.821181 12, 0x0, sum = 1
6303 01:37:05.821597 13, 0x0, sum = 2
6304 01:37:05.824243 14, 0x0, sum = 3
6305 01:37:05.824702 15, 0x0, sum = 4
6306 01:37:05.827397 best_step = 13
6307 01:37:05.827848
6308 01:37:05.828196 ==
6309 01:37:05.831092 Dram Type= 6, Freq= 0, CH_0, rank 1
6310 01:37:05.834174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6311 01:37:05.834492 ==
6312 01:37:05.837771 RX Vref Scan: 0
6313 01:37:05.838180
6314 01:37:05.838429 RX Vref 0 -> 0, step: 1
6315 01:37:05.840508
6316 01:37:05.840862 RX Delay -359 -> 252, step: 8
6317 01:37:05.848938 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6318 01:37:05.852642 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6319 01:37:05.855910 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6320 01:37:05.862562 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6321 01:37:05.866168 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6322 01:37:05.869143 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6323 01:37:05.871939 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6324 01:37:05.878641 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6325 01:37:05.882104 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6326 01:37:05.885269 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6327 01:37:05.888720 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6328 01:37:05.895436 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6329 01:37:05.898906 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6330 01:37:05.901704 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6331 01:37:05.905340 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6332 01:37:05.912002 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6333 01:37:05.912420 ==
6334 01:37:05.915629 Dram Type= 6, Freq= 0, CH_0, rank 1
6335 01:37:05.918750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6336 01:37:05.919169 ==
6337 01:37:05.919451 DQS Delay:
6338 01:37:05.921801 DQS0 = 52, DQS1 = 64
6339 01:37:05.922114 DQM Delay:
6340 01:37:05.925074 DQM0 = 10, DQM1 = 14
6341 01:37:05.925545 DQ Delay:
6342 01:37:05.928425 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6343 01:37:05.932063 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6344 01:37:05.935093 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6345 01:37:05.938320 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6346 01:37:05.938641
6347 01:37:05.938891
6348 01:37:05.945117 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6349 01:37:05.948269 CH0 RK1: MR19=C0C, MR18=C1C1
6350 01:37:05.954906 CH0_RK1: MR19=0xC0C, MR18=0xC1C1, DQSOSC=385, MR23=63, INC=398, DEC=265
6351 01:37:05.958453 [RxdqsGatingPostProcess] freq 400
6352 01:37:05.964900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6353 01:37:05.968270 Pre-setting of DQS Precalculation
6354 01:37:05.971713 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6355 01:37:05.972170 ==
6356 01:37:05.974768 Dram Type= 6, Freq= 0, CH_1, rank 0
6357 01:37:05.977945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6358 01:37:05.981512 ==
6359 01:37:05.984606 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6360 01:37:05.991143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6361 01:37:05.994729 [CA 0] Center 36 (8~64) winsize 57
6362 01:37:05.997645 [CA 1] Center 36 (8~64) winsize 57
6363 01:37:06.001274 [CA 2] Center 36 (8~64) winsize 57
6364 01:37:06.004147 [CA 3] Center 36 (8~64) winsize 57
6365 01:37:06.007933 [CA 4] Center 36 (8~64) winsize 57
6366 01:37:06.010791 [CA 5] Center 36 (8~64) winsize 57
6367 01:37:06.011114
6368 01:37:06.014318 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6369 01:37:06.014737
6370 01:37:06.017708 [CATrainingPosCal] consider 1 rank data
6371 01:37:06.021247 u2DelayCellTimex100 = 270/100 ps
6372 01:37:06.024415 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 01:37:06.027762 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 01:37:06.031114 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 01:37:06.034155 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 01:37:06.037702 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 01:37:06.040975 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 01:37:06.041427
6379 01:37:06.047648 CA PerBit enable=1, Macro0, CA PI delay=36
6380 01:37:06.048074
6381 01:37:06.048333 [CBTSetCACLKResult] CA Dly = 36
6382 01:37:06.050552 CS Dly: 1 (0~32)
6383 01:37:06.050870 ==
6384 01:37:06.054177 Dram Type= 6, Freq= 0, CH_1, rank 1
6385 01:37:06.057763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6386 01:37:06.058231 ==
6387 01:37:06.063988 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6388 01:37:06.070735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6389 01:37:06.073720 [CA 0] Center 36 (8~64) winsize 57
6390 01:37:06.077071 [CA 1] Center 36 (8~64) winsize 57
6391 01:37:06.080591 [CA 2] Center 36 (8~64) winsize 57
6392 01:37:06.083843 [CA 3] Center 36 (8~64) winsize 57
6393 01:37:06.084285 [CA 4] Center 36 (8~64) winsize 57
6394 01:37:06.087121 [CA 5] Center 36 (8~64) winsize 57
6395 01:37:06.087439
6396 01:37:06.093586 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6397 01:37:06.094006
6398 01:37:06.096835 [CATrainingPosCal] consider 2 rank data
6399 01:37:06.100443 u2DelayCellTimex100 = 270/100 ps
6400 01:37:06.104076 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 01:37:06.106771 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 01:37:06.110390 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 01:37:06.113474 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 01:37:06.117209 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 01:37:06.120321 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 01:37:06.120741
6407 01:37:06.123453 CA PerBit enable=1, Macro0, CA PI delay=36
6408 01:37:06.123871
6409 01:37:06.126843 [CBTSetCACLKResult] CA Dly = 36
6410 01:37:06.130347 CS Dly: 1 (0~32)
6411 01:37:06.130916
6412 01:37:06.133416 ----->DramcWriteLeveling(PI) begin...
6413 01:37:06.133833 ==
6414 01:37:06.136798 Dram Type= 6, Freq= 0, CH_1, rank 0
6415 01:37:06.139995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 01:37:06.140322 ==
6417 01:37:06.143329 Write leveling (Byte 0): 32 => 0
6418 01:37:06.146526 Write leveling (Byte 1): 32 => 0
6419 01:37:06.150021 DramcWriteLeveling(PI) end<-----
6420 01:37:06.150457
6421 01:37:06.150717 ==
6422 01:37:06.153257 Dram Type= 6, Freq= 0, CH_1, rank 0
6423 01:37:06.156580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6424 01:37:06.157018 ==
6425 01:37:06.159753 [Gating] SW mode calibration
6426 01:37:06.166488 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 01:37:06.173024 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6428 01:37:06.176691 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 01:37:06.179815 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 01:37:06.186221 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 01:37:06.189473 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6432 01:37:06.193052 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 01:37:06.199652 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 01:37:06.203016 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 01:37:06.206059 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6436 01:37:06.212846 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 01:37:06.216237 Total UI for P1: 0, mck2ui 16
6438 01:37:06.219483 best dqsien dly found for B0: ( 0, 10, 16)
6439 01:37:06.223114 Total UI for P1: 0, mck2ui 16
6440 01:37:06.226204 best dqsien dly found for B1: ( 0, 10, 16)
6441 01:37:06.229521 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6442 01:37:06.232601 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6443 01:37:06.233057
6444 01:37:06.235800 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6445 01:37:06.239119 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6446 01:37:06.242673 [Gating] SW calibration Done
6447 01:37:06.243226 ==
6448 01:37:06.245728 Dram Type= 6, Freq= 0, CH_1, rank 0
6449 01:37:06.249407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6450 01:37:06.249969 ==
6451 01:37:06.252527 RX Vref Scan: 0
6452 01:37:06.253073
6453 01:37:06.255589 RX Vref 0 -> 0, step: 1
6454 01:37:06.256042
6455 01:37:06.258776 RX Delay -410 -> 252, step: 16
6456 01:37:06.262167 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6457 01:37:06.265930 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6458 01:37:06.268801 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6459 01:37:06.275694 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6460 01:37:06.279298 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6461 01:37:06.281913 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6462 01:37:06.285395 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6463 01:37:06.292299 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6464 01:37:06.295653 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6465 01:37:06.298704 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6466 01:37:06.301985 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6467 01:37:06.308684 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6468 01:37:06.312004 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6469 01:37:06.315272 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6470 01:37:06.318552 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6471 01:37:06.325367 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6472 01:37:06.325920 ==
6473 01:37:06.328527 Dram Type= 6, Freq= 0, CH_1, rank 0
6474 01:37:06.332031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6475 01:37:06.332588 ==
6476 01:37:06.335044 DQS Delay:
6477 01:37:06.335498 DQS0 = 43, DQS1 = 59
6478 01:37:06.335855 DQM Delay:
6479 01:37:06.338357 DQM0 = 6, DQM1 = 14
6480 01:37:06.338805 DQ Delay:
6481 01:37:06.342046 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6482 01:37:06.345030 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6483 01:37:06.348366 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6484 01:37:06.351664 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6485 01:37:06.352221
6486 01:37:06.352582
6487 01:37:06.352913 ==
6488 01:37:06.354885 Dram Type= 6, Freq= 0, CH_1, rank 0
6489 01:37:06.358409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6490 01:37:06.358968 ==
6491 01:37:06.361633
6492 01:37:06.362186
6493 01:37:06.362544 TX Vref Scan disable
6494 01:37:06.365081 == TX Byte 0 ==
6495 01:37:06.368312 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6496 01:37:06.371291 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6497 01:37:06.374693 == TX Byte 1 ==
6498 01:37:06.378145 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6499 01:37:06.381479 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6500 01:37:06.382110 ==
6501 01:37:06.384745 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 01:37:06.391328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 01:37:06.391888 ==
6504 01:37:06.392287
6505 01:37:06.392629
6506 01:37:06.392946 TX Vref Scan disable
6507 01:37:06.394491 == TX Byte 0 ==
6508 01:37:06.397901 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6509 01:37:06.401188 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6510 01:37:06.405005 == TX Byte 1 ==
6511 01:37:06.407822 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6512 01:37:06.411084 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6513 01:37:06.414676
6514 01:37:06.415235 [DATLAT]
6515 01:37:06.415604 Freq=400, CH1 RK0
6516 01:37:06.415944
6517 01:37:06.417621 DATLAT Default: 0xf
6518 01:37:06.418085 0, 0xFFFF, sum = 0
6519 01:37:06.420927 1, 0xFFFF, sum = 0
6520 01:37:06.421488 2, 0xFFFF, sum = 0
6521 01:37:06.424707 3, 0xFFFF, sum = 0
6522 01:37:06.425436 4, 0xFFFF, sum = 0
6523 01:37:06.427716 5, 0xFFFF, sum = 0
6524 01:37:06.430708 6, 0xFFFF, sum = 0
6525 01:37:06.431181 7, 0xFFFF, sum = 0
6526 01:37:06.434054 8, 0xFFFF, sum = 0
6527 01:37:06.434524 9, 0xFFFF, sum = 0
6528 01:37:06.437687 10, 0xFFFF, sum = 0
6529 01:37:06.438266 11, 0xFFFF, sum = 0
6530 01:37:06.441117 12, 0x0, sum = 1
6531 01:37:06.441745 13, 0x0, sum = 2
6532 01:37:06.444575 14, 0x0, sum = 3
6533 01:37:06.445170 15, 0x0, sum = 4
6534 01:37:06.445599 best_step = 13
6535 01:37:06.447570
6536 01:37:06.448029 ==
6537 01:37:06.450722 Dram Type= 6, Freq= 0, CH_1, rank 0
6538 01:37:06.454204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6539 01:37:06.454772 ==
6540 01:37:06.455137 RX Vref Scan: 1
6541 01:37:06.455476
6542 01:37:06.457221 RX Vref 0 -> 0, step: 1
6543 01:37:06.457706
6544 01:37:06.460570 RX Delay -359 -> 252, step: 8
6545 01:37:06.461033
6546 01:37:06.463981 Set Vref, RX VrefLevel [Byte0]: 52
6547 01:37:06.467143 [Byte1]: 48
6548 01:37:06.471262
6549 01:37:06.471824 Final RX Vref Byte 0 = 52 to rank0
6550 01:37:06.474439 Final RX Vref Byte 1 = 48 to rank0
6551 01:37:06.477744 Final RX Vref Byte 0 = 52 to rank1
6552 01:37:06.481356 Final RX Vref Byte 1 = 48 to rank1==
6553 01:37:06.484639 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 01:37:06.490851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 01:37:06.491406 ==
6556 01:37:06.491775 DQS Delay:
6557 01:37:06.494096 DQS0 = 48, DQS1 = 68
6558 01:37:06.494558 DQM Delay:
6559 01:37:06.494924 DQM0 = 8, DQM1 = 20
6560 01:37:06.497537 DQ Delay:
6561 01:37:06.500885 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6562 01:37:06.501384 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6563 01:37:06.504253 DQ8 =0, DQ9 =12, DQ10 =24, DQ11 =12
6564 01:37:06.507699 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6565 01:37:06.508261
6566 01:37:06.511088
6567 01:37:06.517465 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6568 01:37:06.520757 CH1 RK0: MR19=C0C, MR18=C9C9
6569 01:37:06.527132 CH1_RK0: MR19=0xC0C, MR18=0xC9C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6570 01:37:06.527595 ==
6571 01:37:06.530542 Dram Type= 6, Freq= 0, CH_1, rank 1
6572 01:37:06.533880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6573 01:37:06.534344 ==
6574 01:37:06.537263 [Gating] SW mode calibration
6575 01:37:06.543633 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6576 01:37:06.550511 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6577 01:37:06.553653 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6578 01:37:06.557384 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6579 01:37:06.563714 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6580 01:37:06.566942 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6581 01:37:06.570257 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6582 01:37:06.576943 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6583 01:37:06.580385 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6584 01:37:06.583706 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6585 01:37:06.590364 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6586 01:37:06.591052 Total UI for P1: 0, mck2ui 16
6587 01:37:06.593436 best dqsien dly found for B0: ( 0, 10, 16)
6588 01:37:06.597191 Total UI for P1: 0, mck2ui 16
6589 01:37:06.600083 best dqsien dly found for B1: ( 0, 10, 16)
6590 01:37:06.606770 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6591 01:37:06.609989 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6592 01:37:06.610723
6593 01:37:06.613851 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6594 01:37:06.616648 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6595 01:37:06.619916 [Gating] SW calibration Done
6596 01:37:06.620371 ==
6597 01:37:06.623464 Dram Type= 6, Freq= 0, CH_1, rank 1
6598 01:37:06.626572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6599 01:37:06.626996 ==
6600 01:37:06.629931 RX Vref Scan: 0
6601 01:37:06.630342
6602 01:37:06.630663 RX Vref 0 -> 0, step: 1
6603 01:37:06.630963
6604 01:37:06.633248 RX Delay -410 -> 252, step: 16
6605 01:37:06.639907 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6606 01:37:06.643523 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6607 01:37:06.646392 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6608 01:37:06.649587 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6609 01:37:06.656433 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6610 01:37:06.659356 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6611 01:37:06.662798 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6612 01:37:06.666241 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6613 01:37:06.672793 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6614 01:37:06.675999 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6615 01:37:06.679850 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6616 01:37:06.682896 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6617 01:37:06.689381 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6618 01:37:06.693432 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6619 01:37:06.696414 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6620 01:37:06.702398 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6621 01:37:06.702937 ==
6622 01:37:06.705874 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 01:37:06.709054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6624 01:37:06.709624 ==
6625 01:37:06.709993 DQS Delay:
6626 01:37:06.712292 DQS0 = 43, DQS1 = 59
6627 01:37:06.712743 DQM Delay:
6628 01:37:06.715883 DQM0 = 10, DQM1 = 18
6629 01:37:06.716438 DQ Delay:
6630 01:37:06.718926 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6631 01:37:06.722338 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6632 01:37:06.725786 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6633 01:37:06.728993 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6634 01:37:06.729503
6635 01:37:06.729868
6636 01:37:06.730251 ==
6637 01:37:06.732303 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 01:37:06.735729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6639 01:37:06.736286 ==
6640 01:37:06.736646
6641 01:37:06.737089
6642 01:37:06.738624 TX Vref Scan disable
6643 01:37:06.739076 == TX Byte 0 ==
6644 01:37:06.745382 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6645 01:37:06.748627 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6646 01:37:06.749083 == TX Byte 1 ==
6647 01:37:06.755421 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6648 01:37:06.758701 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6649 01:37:06.759160 ==
6650 01:37:06.761911 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 01:37:06.765639 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6652 01:37:06.766199 ==
6653 01:37:06.766560
6654 01:37:06.766957
6655 01:37:06.768743 TX Vref Scan disable
6656 01:37:06.769334 == TX Byte 0 ==
6657 01:37:06.775323 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6658 01:37:06.778498 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6659 01:37:06.778958 == TX Byte 1 ==
6660 01:37:06.784824 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6661 01:37:06.788155 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6662 01:37:06.788609
6663 01:37:06.788965 [DATLAT]
6664 01:37:06.791576 Freq=400, CH1 RK1
6665 01:37:06.792110
6666 01:37:06.792471 DATLAT Default: 0xd
6667 01:37:06.794956 0, 0xFFFF, sum = 0
6668 01:37:06.795428 1, 0xFFFF, sum = 0
6669 01:37:06.798199 2, 0xFFFF, sum = 0
6670 01:37:06.798659 3, 0xFFFF, sum = 0
6671 01:37:06.801783 4, 0xFFFF, sum = 0
6672 01:37:06.802341 5, 0xFFFF, sum = 0
6673 01:37:06.805159 6, 0xFFFF, sum = 0
6674 01:37:06.808834 7, 0xFFFF, sum = 0
6675 01:37:06.809442 8, 0xFFFF, sum = 0
6676 01:37:06.811553 9, 0xFFFF, sum = 0
6677 01:37:06.812123 10, 0xFFFF, sum = 0
6678 01:37:06.815047 11, 0xFFFF, sum = 0
6679 01:37:06.815609 12, 0x0, sum = 1
6680 01:37:06.818197 13, 0x0, sum = 2
6681 01:37:06.818759 14, 0x0, sum = 3
6682 01:37:06.821494 15, 0x0, sum = 4
6683 01:37:06.822055 best_step = 13
6684 01:37:06.822416
6685 01:37:06.822745 ==
6686 01:37:06.824450 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 01:37:06.828084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6688 01:37:06.828645 ==
6689 01:37:06.831632 RX Vref Scan: 0
6690 01:37:06.832183
6691 01:37:06.834650 RX Vref 0 -> 0, step: 1
6692 01:37:06.835166
6693 01:37:06.835528 RX Delay -359 -> 252, step: 8
6694 01:37:06.843411 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6695 01:37:06.846777 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6696 01:37:06.849940 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6697 01:37:06.853684 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6698 01:37:06.860130 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6699 01:37:06.863399 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6700 01:37:06.866884 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6701 01:37:06.870174 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6702 01:37:06.876642 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6703 01:37:06.880259 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6704 01:37:06.883291 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6705 01:37:06.889676 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6706 01:37:06.893321 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6707 01:37:06.896413 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6708 01:37:06.900148 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6709 01:37:06.906362 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6710 01:37:06.906919 ==
6711 01:37:06.909835 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 01:37:06.913059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6713 01:37:06.913557 ==
6714 01:37:06.913918 DQS Delay:
6715 01:37:06.916139 DQS0 = 48, DQS1 = 64
6716 01:37:06.916595 DQM Delay:
6717 01:37:06.919734 DQM0 = 9, DQM1 = 15
6718 01:37:06.920299 DQ Delay:
6719 01:37:06.922983 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6720 01:37:06.926202 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6721 01:37:06.930088 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6722 01:37:06.932978 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6723 01:37:06.933563
6724 01:37:06.933929
6725 01:37:06.939749 [DQSOSCAuto] RK1, (LSB)MR18= 0x9d9d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6726 01:37:06.942729 CH1 RK1: MR19=C0C, MR18=9D9D
6727 01:37:06.949395 CH1_RK1: MR19=0xC0C, MR18=0x9D9D, DQSOSC=390, MR23=63, INC=388, DEC=258
6728 01:37:06.952800 [RxdqsGatingPostProcess] freq 400
6729 01:37:06.959376 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6730 01:37:06.962769 Pre-setting of DQS Precalculation
6731 01:37:06.965949 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6732 01:37:06.972759 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6733 01:37:06.978927 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6734 01:37:06.982034
6735 01:37:06.982489
6736 01:37:06.982847 [Calibration Summary] 800 Mbps
6737 01:37:06.985480 CH 0, Rank 0
6738 01:37:06.985938 SW Impedance : PASS
6739 01:37:06.988942 DUTY Scan : NO K
6740 01:37:06.992052 ZQ Calibration : PASS
6741 01:37:06.992647 Jitter Meter : NO K
6742 01:37:06.995418 CBT Training : PASS
6743 01:37:06.998842 Write leveling : PASS
6744 01:37:06.999295 RX DQS gating : PASS
6745 01:37:07.001848 RX DQ/DQS(RDDQC) : PASS
6746 01:37:07.005510 TX DQ/DQS : PASS
6747 01:37:07.006059 RX DATLAT : PASS
6748 01:37:07.008629 RX DQ/DQS(Engine): PASS
6749 01:37:07.012164 TX OE : NO K
6750 01:37:07.012727 All Pass.
6751 01:37:07.013088
6752 01:37:07.013458 CH 0, Rank 1
6753 01:37:07.015379 SW Impedance : PASS
6754 01:37:07.018867 DUTY Scan : NO K
6755 01:37:07.019425 ZQ Calibration : PASS
6756 01:37:07.021832 Jitter Meter : NO K
6757 01:37:07.025490 CBT Training : PASS
6758 01:37:07.026041 Write leveling : NO K
6759 01:37:07.028938 RX DQS gating : PASS
6760 01:37:07.029527 RX DQ/DQS(RDDQC) : PASS
6761 01:37:07.032165 TX DQ/DQS : PASS
6762 01:37:07.035403 RX DATLAT : PASS
6763 01:37:07.035955 RX DQ/DQS(Engine): PASS
6764 01:37:07.039133 TX OE : NO K
6765 01:37:07.039694 All Pass.
6766 01:37:07.040059
6767 01:37:07.041860 CH 1, Rank 0
6768 01:37:07.042312 SW Impedance : PASS
6769 01:37:07.045392 DUTY Scan : NO K
6770 01:37:07.048489 ZQ Calibration : PASS
6771 01:37:07.048957 Jitter Meter : NO K
6772 01:37:07.052038 CBT Training : PASS
6773 01:37:07.055155 Write leveling : PASS
6774 01:37:07.055613 RX DQS gating : PASS
6775 01:37:07.058758 RX DQ/DQS(RDDQC) : PASS
6776 01:37:07.061743 TX DQ/DQS : PASS
6777 01:37:07.062298 RX DATLAT : PASS
6778 01:37:07.065660 RX DQ/DQS(Engine): PASS
6779 01:37:07.068717 TX OE : NO K
6780 01:37:07.069269 All Pass.
6781 01:37:07.069660
6782 01:37:07.069989 CH 1, Rank 1
6783 01:37:07.071605 SW Impedance : PASS
6784 01:37:07.075182 DUTY Scan : NO K
6785 01:37:07.075732 ZQ Calibration : PASS
6786 01:37:07.078664 Jitter Meter : NO K
6787 01:37:07.079119 CBT Training : PASS
6788 01:37:07.081704 Write leveling : NO K
6789 01:37:07.085195 RX DQS gating : PASS
6790 01:37:07.085891 RX DQ/DQS(RDDQC) : PASS
6791 01:37:07.088435 TX DQ/DQS : PASS
6792 01:37:07.092190 RX DATLAT : PASS
6793 01:37:07.092743 RX DQ/DQS(Engine): PASS
6794 01:37:07.094854 TX OE : NO K
6795 01:37:07.095309 All Pass.
6796 01:37:07.095663
6797 01:37:07.098514 DramC Write-DBI off
6798 01:37:07.101266 PER_BANK_REFRESH: Hybrid Mode
6799 01:37:07.101770 TX_TRACKING: ON
6800 01:37:07.111440 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6801 01:37:07.114805 [FAST_K] Save calibration result to emmc
6802 01:37:07.118409 dramc_set_vcore_voltage set vcore to 725000
6803 01:37:07.121216 Read voltage for 1600, 0
6804 01:37:07.121812 Vio18 = 0
6805 01:37:07.124948 Vcore = 725000
6806 01:37:07.125550 Vdram = 0
6807 01:37:07.125919 Vddq = 0
6808 01:37:07.126252 Vmddr = 0
6809 01:37:07.131345 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6810 01:37:07.137835 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6811 01:37:07.138389 MEM_TYPE=3, freq_sel=13
6812 01:37:07.141348 sv_algorithm_assistance_LP4_3733
6813 01:37:07.144322 ============ PULL DRAM RESETB DOWN ============
6814 01:37:07.151095 ========== PULL DRAM RESETB DOWN end =========
6815 01:37:07.154356 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6816 01:37:07.157624 ===================================
6817 01:37:07.160602 LPDDR4 DRAM CONFIGURATION
6818 01:37:07.164055 ===================================
6819 01:37:07.164590 EX_ROW_EN[0] = 0x0
6820 01:37:07.167626 EX_ROW_EN[1] = 0x0
6821 01:37:07.168172 LP4Y_EN = 0x0
6822 01:37:07.170518 WORK_FSP = 0x1
6823 01:37:07.174164 WL = 0x5
6824 01:37:07.174718 RL = 0x5
6825 01:37:07.177140 BL = 0x2
6826 01:37:07.177685 RPST = 0x0
6827 01:37:07.180523 RD_PRE = 0x0
6828 01:37:07.181069 WR_PRE = 0x1
6829 01:37:07.183991 WR_PST = 0x1
6830 01:37:07.184444 DBI_WR = 0x0
6831 01:37:07.187323 DBI_RD = 0x0
6832 01:37:07.187868 OTF = 0x1
6833 01:37:07.190289 ===================================
6834 01:37:07.193767 ===================================
6835 01:37:07.197333 ANA top config
6836 01:37:07.200531 ===================================
6837 01:37:07.201085 DLL_ASYNC_EN = 0
6838 01:37:07.203936 ALL_SLAVE_EN = 0
6839 01:37:07.207071 NEW_RANK_MODE = 1
6840 01:37:07.210480 DLL_IDLE_MODE = 1
6841 01:37:07.213742 LP45_APHY_COMB_EN = 1
6842 01:37:07.214198 TX_ODT_DIS = 0
6843 01:37:07.217179 NEW_8X_MODE = 1
6844 01:37:07.220543 ===================================
6845 01:37:07.223660 ===================================
6846 01:37:07.226740 data_rate = 3200
6847 01:37:07.230208 CKR = 1
6848 01:37:07.233262 DQ_P2S_RATIO = 8
6849 01:37:07.236811 ===================================
6850 01:37:07.240163 CA_P2S_RATIO = 8
6851 01:37:07.240715 DQ_CA_OPEN = 0
6852 01:37:07.243447 DQ_SEMI_OPEN = 0
6853 01:37:07.246634 CA_SEMI_OPEN = 0
6854 01:37:07.250036 CA_FULL_RATE = 0
6855 01:37:07.253325 DQ_CKDIV4_EN = 0
6856 01:37:07.256893 CA_CKDIV4_EN = 0
6857 01:37:07.257479 CA_PREDIV_EN = 0
6858 01:37:07.259771 PH8_DLY = 12
6859 01:37:07.263044 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6860 01:37:07.266428 DQ_AAMCK_DIV = 4
6861 01:37:07.270049 CA_AAMCK_DIV = 4
6862 01:37:07.272871 CA_ADMCK_DIV = 4
6863 01:37:07.273379 DQ_TRACK_CA_EN = 0
6864 01:37:07.276203 CA_PICK = 1600
6865 01:37:07.279542 CA_MCKIO = 1600
6866 01:37:07.283144 MCKIO_SEMI = 0
6867 01:37:07.286340 PLL_FREQ = 3068
6868 01:37:07.289889 DQ_UI_PI_RATIO = 32
6869 01:37:07.293217 CA_UI_PI_RATIO = 0
6870 01:37:07.296518 ===================================
6871 01:37:07.299811 ===================================
6872 01:37:07.300371 memory_type:LPDDR4
6873 01:37:07.302913 GP_NUM : 10
6874 01:37:07.306219 SRAM_EN : 1
6875 01:37:07.306781 MD32_EN : 0
6876 01:37:07.309649 ===================================
6877 01:37:07.313015 [ANA_INIT] >>>>>>>>>>>>>>
6878 01:37:07.316048 <<<<<< [CONFIGURE PHASE]: ANA_TX
6879 01:37:07.319745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6880 01:37:07.322991 ===================================
6881 01:37:07.326265 data_rate = 3200,PCW = 0X7600
6882 01:37:07.329538 ===================================
6883 01:37:07.332916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6884 01:37:07.335767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6885 01:37:07.342990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6886 01:37:07.346277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6887 01:37:07.349034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6888 01:37:07.352739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6889 01:37:07.355880 [ANA_INIT] flow start
6890 01:37:07.359038 [ANA_INIT] PLL >>>>>>>>
6891 01:37:07.359603 [ANA_INIT] PLL <<<<<<<<
6892 01:37:07.362621 [ANA_INIT] MIDPI >>>>>>>>
6893 01:37:07.365868 [ANA_INIT] MIDPI <<<<<<<<
6894 01:37:07.369601 [ANA_INIT] DLL >>>>>>>>
6895 01:37:07.370175 [ANA_INIT] DLL <<<<<<<<
6896 01:37:07.372372 [ANA_INIT] flow end
6897 01:37:07.375902 ============ LP4 DIFF to SE enter ============
6898 01:37:07.378898 ============ LP4 DIFF to SE exit ============
6899 01:37:07.382048 [ANA_INIT] <<<<<<<<<<<<<
6900 01:37:07.385393 [Flow] Enable top DCM control >>>>>
6901 01:37:07.389405 [Flow] Enable top DCM control <<<<<
6902 01:37:07.392593 Enable DLL master slave shuffle
6903 01:37:07.398808 ==============================================================
6904 01:37:07.399384 Gating Mode config
6905 01:37:07.405420 ==============================================================
6906 01:37:07.405978 Config description:
6907 01:37:07.415382 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6908 01:37:07.421958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6909 01:37:07.428522 SELPH_MODE 0: By rank 1: By Phase
6910 01:37:07.431825 ==============================================================
6911 01:37:07.434835 GAT_TRACK_EN = 1
6912 01:37:07.438195 RX_GATING_MODE = 2
6913 01:37:07.442015 RX_GATING_TRACK_MODE = 2
6914 01:37:07.444885 SELPH_MODE = 1
6915 01:37:07.448095 PICG_EARLY_EN = 1
6916 01:37:07.451451 VALID_LAT_VALUE = 1
6917 01:37:07.458226 ==============================================================
6918 01:37:07.461747 Enter into Gating configuration >>>>
6919 01:37:07.465265 Exit from Gating configuration <<<<
6920 01:37:07.468238 Enter into DVFS_PRE_config >>>>>
6921 01:37:07.477810 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6922 01:37:07.481277 Exit from DVFS_PRE_config <<<<<
6923 01:37:07.484633 Enter into PICG configuration >>>>
6924 01:37:07.488098 Exit from PICG configuration <<<<
6925 01:37:07.491372 [RX_INPUT] configuration >>>>>
6926 01:37:07.491954 [RX_INPUT] configuration <<<<<
6927 01:37:07.497756 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6928 01:37:07.504498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6929 01:37:07.511168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6930 01:37:07.514463 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6931 01:37:07.521493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6932 01:37:07.527803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6933 01:37:07.530813 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6934 01:37:07.533989 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6935 01:37:07.540981 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6936 01:37:07.543893 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6937 01:37:07.547538 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6938 01:37:07.554115 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6939 01:37:07.557498 ===================================
6940 01:37:07.558064 LPDDR4 DRAM CONFIGURATION
6941 01:37:07.560679 ===================================
6942 01:37:07.564218 EX_ROW_EN[0] = 0x0
6943 01:37:07.567594 EX_ROW_EN[1] = 0x0
6944 01:37:07.568157 LP4Y_EN = 0x0
6945 01:37:07.570692 WORK_FSP = 0x1
6946 01:37:07.571380 WL = 0x5
6947 01:37:07.573626 RL = 0x5
6948 01:37:07.574085 BL = 0x2
6949 01:37:07.577071 RPST = 0x0
6950 01:37:07.577777 RD_PRE = 0x0
6951 01:37:07.580491 WR_PRE = 0x1
6952 01:37:07.580950 WR_PST = 0x1
6953 01:37:07.583837 DBI_WR = 0x0
6954 01:37:07.584405 DBI_RD = 0x0
6955 01:37:07.587125 OTF = 0x1
6956 01:37:07.590697 ===================================
6957 01:37:07.593602 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6958 01:37:07.596918 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6959 01:37:07.604140 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6960 01:37:07.607069 ===================================
6961 01:37:07.607643 LPDDR4 DRAM CONFIGURATION
6962 01:37:07.610645 ===================================
6963 01:37:07.613406 EX_ROW_EN[0] = 0x10
6964 01:37:07.617190 EX_ROW_EN[1] = 0x0
6965 01:37:07.617802 LP4Y_EN = 0x0
6966 01:37:07.620261 WORK_FSP = 0x1
6967 01:37:07.620823 WL = 0x5
6968 01:37:07.623625 RL = 0x5
6969 01:37:07.624188 BL = 0x2
6970 01:37:07.626751 RPST = 0x0
6971 01:37:07.627312 RD_PRE = 0x0
6972 01:37:07.629785 WR_PRE = 0x1
6973 01:37:07.630260 WR_PST = 0x1
6974 01:37:07.633352 DBI_WR = 0x0
6975 01:37:07.633924 DBI_RD = 0x0
6976 01:37:07.636400 OTF = 0x1
6977 01:37:07.639918 ===================================
6978 01:37:07.646838 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6979 01:37:07.647443 ==
6980 01:37:07.649969 Dram Type= 6, Freq= 0, CH_0, rank 0
6981 01:37:07.653381 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6982 01:37:07.653848 ==
6983 01:37:07.656612 [Duty_Offset_Calibration]
6984 01:37:07.657171 B0:0 B1:2 CA:1
6985 01:37:07.657579
6986 01:37:07.659643 [DutyScan_Calibration_Flow] k_type=0
6987 01:37:07.670383
6988 01:37:07.670945 ==CLK 0==
6989 01:37:07.674051 Final CLK duty delay cell = 0
6990 01:37:07.676957 [0] MAX Duty = 5187%(X100), DQS PI = 24
6991 01:37:07.680217 [0] MIN Duty = 4938%(X100), DQS PI = 38
6992 01:37:07.683389 [0] AVG Duty = 5062%(X100)
6993 01:37:07.683866
6994 01:37:07.687041 CH0 CLK Duty spec in!! Max-Min= 249%
6995 01:37:07.690463 [DutyScan_Calibration_Flow] ====Done====
6996 01:37:07.691015
6997 01:37:07.693203 [DutyScan_Calibration_Flow] k_type=1
6998 01:37:07.710392
6999 01:37:07.710948 ==DQS 0 ==
7000 01:37:07.713520 Final DQS duty delay cell = 0
7001 01:37:07.717219 [0] MAX Duty = 5156%(X100), DQS PI = 36
7002 01:37:07.720657 [0] MIN Duty = 5031%(X100), DQS PI = 8
7003 01:37:07.721115 [0] AVG Duty = 5093%(X100)
7004 01:37:07.723709
7005 01:37:07.724160 ==DQS 1 ==
7006 01:37:07.726942 Final DQS duty delay cell = 0
7007 01:37:07.730114 [0] MAX Duty = 5031%(X100), DQS PI = 6
7008 01:37:07.733284 [0] MIN Duty = 4876%(X100), DQS PI = 18
7009 01:37:07.736675 [0] AVG Duty = 4953%(X100)
7010 01:37:07.737367
7011 01:37:07.739779 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7012 01:37:07.740235
7013 01:37:07.743293 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7014 01:37:07.746457 [DutyScan_Calibration_Flow] ====Done====
7015 01:37:07.747036
7016 01:37:07.749768 [DutyScan_Calibration_Flow] k_type=3
7017 01:37:07.767375
7018 01:37:07.768063 ==DQM 0 ==
7019 01:37:07.770855 Final DQM duty delay cell = 0
7020 01:37:07.774224 [0] MAX Duty = 5187%(X100), DQS PI = 22
7021 01:37:07.777400 [0] MIN Duty = 4907%(X100), DQS PI = 58
7022 01:37:07.780462 [0] AVG Duty = 5047%(X100)
7023 01:37:07.781207
7024 01:37:07.781700 ==DQM 1 ==
7025 01:37:07.783960 Final DQM duty delay cell = 0
7026 01:37:07.786914 [0] MAX Duty = 5000%(X100), DQS PI = 4
7027 01:37:07.790600 [0] MIN Duty = 4782%(X100), DQS PI = 14
7028 01:37:07.793849 [0] AVG Duty = 4891%(X100)
7029 01:37:07.794306
7030 01:37:07.797056 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7031 01:37:07.797625
7032 01:37:07.800244 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7033 01:37:07.804110 [DutyScan_Calibration_Flow] ====Done====
7034 01:37:07.804566
7035 01:37:07.807226 [DutyScan_Calibration_Flow] k_type=2
7036 01:37:07.823635
7037 01:37:07.824177 ==DQ 0 ==
7038 01:37:07.827007 Final DQ duty delay cell = 0
7039 01:37:07.830202 [0] MAX Duty = 5218%(X100), DQS PI = 18
7040 01:37:07.833591 [0] MIN Duty = 4938%(X100), DQS PI = 56
7041 01:37:07.834004 [0] AVG Duty = 5078%(X100)
7042 01:37:07.836798
7043 01:37:07.837205 ==DQ 1 ==
7044 01:37:07.840026 Final DQ duty delay cell = -4
7045 01:37:07.843804 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7046 01:37:07.846871 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7047 01:37:07.849916 [-4] AVG Duty = 4953%(X100)
7048 01:37:07.850334
7049 01:37:07.853396 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7050 01:37:07.853763
7051 01:37:07.856850 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7052 01:37:07.860184 [DutyScan_Calibration_Flow] ====Done====
7053 01:37:07.860746 ==
7054 01:37:07.863690 Dram Type= 6, Freq= 0, CH_1, rank 0
7055 01:37:07.867054 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7056 01:37:07.867574 ==
7057 01:37:07.869841 [Duty_Offset_Calibration]
7058 01:37:07.870253 B0:0 B1:4 CA:-5
7059 01:37:07.870579
7060 01:37:07.873212 [DutyScan_Calibration_Flow] k_type=0
7061 01:37:07.884265
7062 01:37:07.884768 ==CLK 0==
7063 01:37:07.887615 Final CLK duty delay cell = 0
7064 01:37:07.890977 [0] MAX Duty = 5156%(X100), DQS PI = 22
7065 01:37:07.894178 [0] MIN Duty = 4906%(X100), DQS PI = 50
7066 01:37:07.897264 [0] AVG Duty = 5031%(X100)
7067 01:37:07.897710
7068 01:37:07.900748 CH1 CLK Duty spec in!! Max-Min= 250%
7069 01:37:07.904205 [DutyScan_Calibration_Flow] ====Done====
7070 01:37:07.904716
7071 01:37:07.907362 [DutyScan_Calibration_Flow] k_type=1
7072 01:37:07.923500
7073 01:37:07.924054 ==DQS 0 ==
7074 01:37:07.926874 Final DQS duty delay cell = 0
7075 01:37:07.929752 [0] MAX Duty = 5187%(X100), DQS PI = 18
7076 01:37:07.933692 [0] MIN Duty = 4876%(X100), DQS PI = 44
7077 01:37:07.936378 [0] AVG Duty = 5031%(X100)
7078 01:37:07.936849
7079 01:37:07.937214 ==DQS 1 ==
7080 01:37:07.939911 Final DQS duty delay cell = -4
7081 01:37:07.942852 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7082 01:37:07.946433 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7083 01:37:07.949480 [-4] AVG Duty = 4922%(X100)
7084 01:37:07.949988
7085 01:37:07.952770 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7086 01:37:07.953230
7087 01:37:07.956386 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7088 01:37:07.959427 [DutyScan_Calibration_Flow] ====Done====
7089 01:37:07.959984
7090 01:37:07.963054 [DutyScan_Calibration_Flow] k_type=3
7091 01:37:07.978899
7092 01:37:07.979464 ==DQM 0 ==
7093 01:37:07.982137 Final DQM duty delay cell = -4
7094 01:37:07.985675 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7095 01:37:07.988880 [-4] MIN Duty = 4751%(X100), DQS PI = 44
7096 01:37:07.992163 [-4] AVG Duty = 4891%(X100)
7097 01:37:07.992736
7098 01:37:07.993103 ==DQM 1 ==
7099 01:37:07.995562 Final DQM duty delay cell = -4
7100 01:37:07.998692 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7101 01:37:08.002200 [-4] MIN Duty = 4875%(X100), DQS PI = 40
7102 01:37:08.005952 [-4] AVG Duty = 4984%(X100)
7103 01:37:08.006511
7104 01:37:08.008962 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7105 01:37:08.009563
7106 01:37:08.012257 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7107 01:37:08.015245 [DutyScan_Calibration_Flow] ====Done====
7108 01:37:08.015704
7109 01:37:08.018806 [DutyScan_Calibration_Flow] k_type=2
7110 01:37:08.036861
7111 01:37:08.037450 ==DQ 0 ==
7112 01:37:08.040385 Final DQ duty delay cell = 0
7113 01:37:08.043146 [0] MAX Duty = 5093%(X100), DQS PI = 34
7114 01:37:08.046321 [0] MIN Duty = 4938%(X100), DQS PI = 48
7115 01:37:08.046798 [0] AVG Duty = 5015%(X100)
7116 01:37:08.049904
7117 01:37:08.050432 ==DQ 1 ==
7118 01:37:08.052962 Final DQ duty delay cell = 0
7119 01:37:08.056663 [0] MAX Duty = 5031%(X100), DQS PI = 2
7120 01:37:08.059855 [0] MIN Duty = 4876%(X100), DQS PI = 28
7121 01:37:08.060314 [0] AVG Duty = 4953%(X100)
7122 01:37:08.062755
7123 01:37:08.066213 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7124 01:37:08.066765
7125 01:37:08.069805 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7126 01:37:08.073134 [DutyScan_Calibration_Flow] ====Done====
7127 01:37:08.076357 nWR fixed to 30
7128 01:37:08.076917 [ModeRegInit_LP4] CH0 RK0
7129 01:37:08.079291 [ModeRegInit_LP4] CH0 RK1
7130 01:37:08.082848 [ModeRegInit_LP4] CH1 RK0
7131 01:37:08.085851 [ModeRegInit_LP4] CH1 RK1
7132 01:37:08.086304 match AC timing 4
7133 01:37:08.092850 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7134 01:37:08.095807 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7135 01:37:08.099162 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7136 01:37:08.106061 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7137 01:37:08.109257 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7138 01:37:08.109862 [MiockJmeterHQA]
7139 01:37:08.110225
7140 01:37:08.112517 [DramcMiockJmeter] u1RxGatingPI = 0
7141 01:37:08.115843 0 : 4253, 4026
7142 01:37:08.116403 4 : 4252, 4026
7143 01:37:08.119122 8 : 4363, 4138
7144 01:37:08.119686 12 : 4253, 4027
7145 01:37:08.120057 16 : 4252, 4027
7146 01:37:08.122357 20 : 4363, 4137
7147 01:37:08.122820 24 : 4363, 4138
7148 01:37:08.125739 28 : 4253, 4027
7149 01:37:08.126301 32 : 4252, 4026
7150 01:37:08.129050 36 : 4250, 4027
7151 01:37:08.129671 40 : 4361, 4137
7152 01:37:08.132342 44 : 4250, 4026
7153 01:37:08.132902 48 : 4360, 4138
7154 01:37:08.135644 52 : 4250, 4026
7155 01:37:08.136206 56 : 4250, 4027
7156 01:37:08.136578 60 : 4250, 4027
7157 01:37:08.138666 64 : 4252, 4029
7158 01:37:08.139129 68 : 4250, 4027
7159 01:37:08.141979 72 : 4250, 4027
7160 01:37:08.142439 76 : 4363, 4140
7161 01:37:08.145153 80 : 4250, 4027
7162 01:37:08.145647 84 : 4252, 4029
7163 01:37:08.148756 88 : 4250, 4026
7164 01:37:08.149362 92 : 4361, 4137
7165 01:37:08.149747 96 : 4250, 4026
7166 01:37:08.151851 100 : 4360, 1720
7167 01:37:08.152314 104 : 4361, 0
7168 01:37:08.155380 108 : 4252, 0
7169 01:37:08.155941 112 : 4250, 0
7170 01:37:08.156309 116 : 4250, 0
7171 01:37:08.158681 120 : 4361, 0
7172 01:37:08.159242 124 : 4250, 0
7173 01:37:08.161755 128 : 4252, 0
7174 01:37:08.162232 132 : 4361, 0
7175 01:37:08.162606 136 : 4250, 0
7176 01:37:08.164966 140 : 4250, 0
7177 01:37:08.165475 144 : 4250, 0
7178 01:37:08.169034 148 : 4250, 0
7179 01:37:08.169635 152 : 4252, 0
7180 01:37:08.170008 156 : 4361, 0
7181 01:37:08.171900 160 : 4250, 0
7182 01:37:08.172457 164 : 4250, 0
7183 01:37:08.175149 168 : 4250, 0
7184 01:37:08.175610 172 : 4361, 0
7185 01:37:08.175975 176 : 4361, 0
7186 01:37:08.178548 180 : 4250, 0
7187 01:37:08.179110 184 : 4361, 0
7188 01:37:08.179479 188 : 4250, 0
7189 01:37:08.181699 192 : 4250, 0
7190 01:37:08.182162 196 : 4250, 0
7191 01:37:08.185026 200 : 4250, 0
7192 01:37:08.185531 204 : 4252, 0
7193 01:37:08.185903 208 : 4361, 0
7194 01:37:08.188811 212 : 4250, 0
7195 01:37:08.189276 216 : 4250, 0
7196 01:37:08.191539 220 : 4250, 696
7197 01:37:08.191999 224 : 4363, 4119
7198 01:37:08.194882 228 : 4249, 4027
7199 01:37:08.195345 232 : 4250, 4026
7200 01:37:08.198116 236 : 4250, 4027
7201 01:37:08.198581 240 : 4252, 4029
7202 01:37:08.198946 244 : 4250, 4027
7203 01:37:08.201801 248 : 4252, 4029
7204 01:37:08.202263 252 : 4250, 4027
7205 01:37:08.204720 256 : 4252, 4030
7206 01:37:08.205136 260 : 4250, 4027
7207 01:37:08.208303 264 : 4360, 4138
7208 01:37:08.208822 268 : 4361, 4137
7209 01:37:08.211494 272 : 4250, 4026
7210 01:37:08.211915 276 : 4363, 4139
7211 01:37:08.214641 280 : 4250, 4027
7212 01:37:08.215060 284 : 4250, 4027
7213 01:37:08.217828 288 : 4250, 4026
7214 01:37:08.218246 292 : 4252, 4030
7215 01:37:08.221433 296 : 4250, 4027
7216 01:37:08.221952 300 : 4250, 4027
7217 01:37:08.224494 304 : 4250, 4027
7218 01:37:08.224911 308 : 4252, 4029
7219 01:37:08.225244 312 : 4250, 4027
7220 01:37:08.227707 316 : 4360, 4138
7221 01:37:08.228124 320 : 4361, 4137
7222 01:37:08.231260 324 : 4250, 4026
7223 01:37:08.231678 328 : 4363, 4139
7224 01:37:08.234331 332 : 4250, 4027
7225 01:37:08.234750 336 : 4250, 3816
7226 01:37:08.237653 340 : 4250, 1866
7227 01:37:08.238073
7228 01:37:08.240999 MIOCK jitter meter ch=0
7229 01:37:08.241448
7230 01:37:08.241778 1T = (340-100) = 240 dly cells
7231 01:37:08.247869 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7232 01:37:08.248282 ==
7233 01:37:08.251081 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 01:37:08.254517 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7235 01:37:08.257401 ==
7236 01:37:08.261348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7237 01:37:08.264571 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7238 01:37:08.271049 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7239 01:37:08.274124 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7240 01:37:08.283746 [CA 0] Center 42 (12~73) winsize 62
7241 01:37:08.287472 [CA 1] Center 42 (12~73) winsize 62
7242 01:37:08.290859 [CA 2] Center 39 (9~69) winsize 61
7243 01:37:08.293874 [CA 3] Center 38 (9~68) winsize 60
7244 01:37:08.297366 [CA 4] Center 36 (6~67) winsize 62
7245 01:37:08.300386 [CA 5] Center 36 (6~66) winsize 61
7246 01:37:08.300803
7247 01:37:08.303621 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7248 01:37:08.304093
7249 01:37:08.307361 [CATrainingPosCal] consider 1 rank data
7250 01:37:08.310376 u2DelayCellTimex100 = 271/100 ps
7251 01:37:08.313934 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7252 01:37:08.320636 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7253 01:37:08.323744 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7254 01:37:08.327021 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7255 01:37:08.330195 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7256 01:37:08.333857 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7257 01:37:08.334365
7258 01:37:08.337010 CA PerBit enable=1, Macro0, CA PI delay=36
7259 01:37:08.337568
7260 01:37:08.340283 [CBTSetCACLKResult] CA Dly = 36
7261 01:37:08.343743 CS Dly: 10 (0~41)
7262 01:37:08.346600 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7263 01:37:08.350029 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7264 01:37:08.350542 ==
7265 01:37:08.353899 Dram Type= 6, Freq= 0, CH_0, rank 1
7266 01:37:08.360605 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7267 01:37:08.361124 ==
7268 01:37:08.363536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7269 01:37:08.367438 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7270 01:37:08.373381 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7271 01:37:08.380021 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7272 01:37:08.386397 [CA 0] Center 42 (12~73) winsize 62
7273 01:37:08.389790 [CA 1] Center 42 (12~73) winsize 62
7274 01:37:08.393411 [CA 2] Center 38 (9~68) winsize 60
7275 01:37:08.396463 [CA 3] Center 38 (8~68) winsize 61
7276 01:37:08.400161 [CA 4] Center 36 (6~66) winsize 61
7277 01:37:08.403760 [CA 5] Center 36 (6~66) winsize 61
7278 01:37:08.404412
7279 01:37:08.406573 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7280 01:37:08.407134
7281 01:37:08.409975 [CATrainingPosCal] consider 2 rank data
7282 01:37:08.413211 u2DelayCellTimex100 = 271/100 ps
7283 01:37:08.416234 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7284 01:37:08.423184 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7285 01:37:08.426573 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7286 01:37:08.429498 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7287 01:37:08.432980 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7288 01:37:08.436720 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7289 01:37:08.437275
7290 01:37:08.439646 CA PerBit enable=1, Macro0, CA PI delay=36
7291 01:37:08.440103
7292 01:37:08.442807 [CBTSetCACLKResult] CA Dly = 36
7293 01:37:08.446169 CS Dly: 10 (0~42)
7294 01:37:08.449351 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7295 01:37:08.452704 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7296 01:37:08.453158
7297 01:37:08.455953 ----->DramcWriteLeveling(PI) begin...
7298 01:37:08.456410 ==
7299 01:37:08.459073 Dram Type= 6, Freq= 0, CH_0, rank 0
7300 01:37:08.465948 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7301 01:37:08.466405 ==
7302 01:37:08.469544 Write leveling (Byte 0): 30 => 30
7303 01:37:08.470093 Write leveling (Byte 1): 26 => 26
7304 01:37:08.472817 DramcWriteLeveling(PI) end<-----
7305 01:37:08.473413
7306 01:37:08.476159 ==
7307 01:37:08.476716 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 01:37:08.482528 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7309 01:37:08.483081 ==
7310 01:37:08.485808 [Gating] SW mode calibration
7311 01:37:08.492410 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7312 01:37:08.495825 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7313 01:37:08.502295 0 12 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7314 01:37:08.505874 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7315 01:37:08.509180 0 12 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7316 01:37:08.515564 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 01:37:08.519238 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7318 01:37:08.522334 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7319 01:37:08.529141 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 01:37:08.532622 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7321 01:37:08.535896 0 13 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
7322 01:37:08.542276 0 13 4 | B1->B0 | 3232 2727 | 1 0 | (1 0) (1 0)
7323 01:37:08.545494 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7324 01:37:08.549060 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7325 01:37:08.555284 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 01:37:08.558860 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 01:37:08.562228 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 01:37:08.568633 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7329 01:37:08.571965 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7330 01:37:08.575238 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7331 01:37:08.581678 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7332 01:37:08.585258 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 01:37:08.588418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7334 01:37:08.595051 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 01:37:08.598247 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7336 01:37:08.601827 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 01:37:08.608454 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 01:37:08.611429 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7339 01:37:08.614814 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7340 01:37:08.621563 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 01:37:08.624660 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 01:37:08.628187 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 01:37:08.634592 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 01:37:08.637964 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 01:37:08.641354 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 01:37:08.647811 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 01:37:08.650991 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 01:37:08.654187 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 01:37:08.661063 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 01:37:08.664456 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 01:37:08.667496 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 01:37:08.674369 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7353 01:37:08.677661 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7354 01:37:08.680711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7355 01:37:08.687644 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7356 01:37:08.688242 Total UI for P1: 0, mck2ui 16
7357 01:37:08.690644 best dqsien dly found for B0: ( 1, 1, 0)
7358 01:37:08.694172 Total UI for P1: 0, mck2ui 16
7359 01:37:08.697447 best dqsien dly found for B1: ( 1, 1, 4)
7360 01:37:08.704058 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7361 01:37:08.707138 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7362 01:37:08.707594
7363 01:37:08.710484 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7364 01:37:08.714231 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7365 01:37:08.717019 [Gating] SW calibration Done
7366 01:37:08.717539 ==
7367 01:37:08.720439 Dram Type= 6, Freq= 0, CH_0, rank 0
7368 01:37:08.724039 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7369 01:37:08.724603 ==
7370 01:37:08.724973 RX Vref Scan: 0
7371 01:37:08.727073
7372 01:37:08.727531 RX Vref 0 -> 0, step: 1
7373 01:37:08.727894
7374 01:37:08.730273 RX Delay 0 -> 252, step: 8
7375 01:37:08.733823 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7376 01:37:08.736968 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7377 01:37:08.743441 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7378 01:37:08.746721 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7379 01:37:08.750226 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7380 01:37:08.753220 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7381 01:37:08.756519 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7382 01:37:08.763487 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7383 01:37:08.766378 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7384 01:37:08.770213 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7385 01:37:08.773233 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7386 01:37:08.776672 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7387 01:37:08.783144 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7388 01:37:08.786361 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7389 01:37:08.789594 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7390 01:37:08.793034 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7391 01:37:08.793632 ==
7392 01:37:08.796484 Dram Type= 6, Freq= 0, CH_0, rank 0
7393 01:37:08.802769 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7394 01:37:08.803407 ==
7395 01:37:08.803791 DQS Delay:
7396 01:37:08.806426 DQS0 = 0, DQS1 = 0
7397 01:37:08.806889 DQM Delay:
7398 01:37:08.809709 DQM0 = 129, DQM1 = 123
7399 01:37:08.810253 DQ Delay:
7400 01:37:08.813166 DQ0 =123, DQ1 =131, DQ2 =123, DQ3 =127
7401 01:37:08.816229 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7402 01:37:08.819661 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7403 01:37:08.823127 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7404 01:37:08.823677
7405 01:37:08.824050
7406 01:37:08.824391 ==
7407 01:37:08.826104 Dram Type= 6, Freq= 0, CH_0, rank 0
7408 01:37:08.832829 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7409 01:37:08.833442 ==
7410 01:37:08.833823
7411 01:37:08.834161
7412 01:37:08.834481 TX Vref Scan disable
7413 01:37:08.836190 == TX Byte 0 ==
7414 01:37:08.839329 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7415 01:37:08.842841 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7416 01:37:08.846074 == TX Byte 1 ==
7417 01:37:08.849570 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7418 01:37:08.855882 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7419 01:37:08.856441 ==
7420 01:37:08.859698 Dram Type= 6, Freq= 0, CH_0, rank 0
7421 01:37:08.862748 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7422 01:37:08.863307 ==
7423 01:37:08.875697
7424 01:37:08.878494 TX Vref early break, caculate TX vref
7425 01:37:08.882099 TX Vref=16, minBit 8, minWin=21, winSum=372
7426 01:37:08.885384 TX Vref=18, minBit 8, minWin=22, winSum=377
7427 01:37:08.889128 TX Vref=20, minBit 8, minWin=23, winSum=388
7428 01:37:08.891834 TX Vref=22, minBit 8, minWin=23, winSum=401
7429 01:37:08.894913 TX Vref=24, minBit 9, minWin=24, winSum=406
7430 01:37:08.901927 TX Vref=26, minBit 10, minWin=24, winSum=414
7431 01:37:08.905079 TX Vref=28, minBit 4, minWin=25, winSum=415
7432 01:37:08.908351 TX Vref=30, minBit 0, minWin=25, winSum=409
7433 01:37:08.911898 TX Vref=32, minBit 6, minWin=24, winSum=402
7434 01:37:08.915265 TX Vref=34, minBit 3, minWin=23, winSum=389
7435 01:37:08.921832 [TxChooseVref] Worse bit 4, Min win 25, Win sum 415, Final Vref 28
7436 01:37:08.922401
7437 01:37:08.924961 Final TX Range 0 Vref 28
7438 01:37:08.925460
7439 01:37:08.925911 ==
7440 01:37:08.928105 Dram Type= 6, Freq= 0, CH_0, rank 0
7441 01:37:08.931478 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7442 01:37:08.931946 ==
7443 01:37:08.932312
7444 01:37:08.932650
7445 01:37:08.934708 TX Vref Scan disable
7446 01:37:08.941590 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7447 01:37:08.942057 == TX Byte 0 ==
7448 01:37:08.944777 u2DelayCellOfst[0]=14 cells (4 PI)
7449 01:37:08.948287 u2DelayCellOfst[1]=18 cells (5 PI)
7450 01:37:08.951297 u2DelayCellOfst[2]=10 cells (3 PI)
7451 01:37:08.954888 u2DelayCellOfst[3]=10 cells (3 PI)
7452 01:37:08.957779 u2DelayCellOfst[4]=10 cells (3 PI)
7453 01:37:08.961098 u2DelayCellOfst[5]=0 cells (0 PI)
7454 01:37:08.964373 u2DelayCellOfst[6]=18 cells (5 PI)
7455 01:37:08.967840 u2DelayCellOfst[7]=18 cells (5 PI)
7456 01:37:08.970963 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7457 01:37:08.974536 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7458 01:37:08.977987 == TX Byte 1 ==
7459 01:37:08.981188 u2DelayCellOfst[8]=0 cells (0 PI)
7460 01:37:08.984408 u2DelayCellOfst[9]=0 cells (0 PI)
7461 01:37:08.985136 u2DelayCellOfst[10]=7 cells (2 PI)
7462 01:37:08.987527 u2DelayCellOfst[11]=3 cells (1 PI)
7463 01:37:08.990966 u2DelayCellOfst[12]=14 cells (4 PI)
7464 01:37:08.994232 u2DelayCellOfst[13]=14 cells (4 PI)
7465 01:37:08.997677 u2DelayCellOfst[14]=14 cells (4 PI)
7466 01:37:09.000924 u2DelayCellOfst[15]=10 cells (3 PI)
7467 01:37:09.007508 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7468 01:37:09.010614 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7469 01:37:09.011095 DramC Write-DBI on
7470 01:37:09.011547 ==
7471 01:37:09.014036 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 01:37:09.021102 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7473 01:37:09.021679 ==
7474 01:37:09.022302
7475 01:37:09.022850
7476 01:37:09.023180 TX Vref Scan disable
7477 01:37:09.024764 == TX Byte 0 ==
7478 01:37:09.028025 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7479 01:37:09.031303 == TX Byte 1 ==
7480 01:37:09.034654 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7481 01:37:09.038353 DramC Write-DBI off
7482 01:37:09.038773
7483 01:37:09.039125 [DATLAT]
7484 01:37:09.039439 Freq=1600, CH0 RK0
7485 01:37:09.039747
7486 01:37:09.041160 DATLAT Default: 0xf
7487 01:37:09.041625 0, 0xFFFF, sum = 0
7488 01:37:09.044496 1, 0xFFFF, sum = 0
7489 01:37:09.048500 2, 0xFFFF, sum = 0
7490 01:37:09.049038 3, 0xFFFF, sum = 0
7491 01:37:09.051669 4, 0xFFFF, sum = 0
7492 01:37:09.052200 5, 0xFFFF, sum = 0
7493 01:37:09.054551 6, 0xFFFF, sum = 0
7494 01:37:09.054980 7, 0xFFFF, sum = 0
7495 01:37:09.058207 8, 0xFFFF, sum = 0
7496 01:37:09.058738 9, 0xFFFF, sum = 0
7497 01:37:09.061449 10, 0xFFFF, sum = 0
7498 01:37:09.061979 11, 0xFFFF, sum = 0
7499 01:37:09.064712 12, 0x8FFF, sum = 0
7500 01:37:09.065239 13, 0x0, sum = 1
7501 01:37:09.068051 14, 0x0, sum = 2
7502 01:37:09.068639 15, 0x0, sum = 3
7503 01:37:09.071020 16, 0x0, sum = 4
7504 01:37:09.071491 best_step = 14
7505 01:37:09.071858
7506 01:37:09.072199 ==
7507 01:37:09.074276 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 01:37:09.077605 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7509 01:37:09.080868 ==
7510 01:37:09.081362 RX Vref Scan: 1
7511 01:37:09.081733
7512 01:37:09.084208 Set Vref Range= 24 -> 127
7513 01:37:09.084671
7514 01:37:09.087723 RX Vref 24 -> 127, step: 1
7515 01:37:09.088185
7516 01:37:09.088551 RX Delay 11 -> 252, step: 4
7517 01:37:09.088896
7518 01:37:09.090790 Set Vref, RX VrefLevel [Byte0]: 24
7519 01:37:09.094414 [Byte1]: 24
7520 01:37:09.098060
7521 01:37:09.098519 Set Vref, RX VrefLevel [Byte0]: 25
7522 01:37:09.101259 [Byte1]: 25
7523 01:37:09.105792
7524 01:37:09.106254 Set Vref, RX VrefLevel [Byte0]: 26
7525 01:37:09.109174 [Byte1]: 26
7526 01:37:09.113265
7527 01:37:09.113775 Set Vref, RX VrefLevel [Byte0]: 27
7528 01:37:09.116664 [Byte1]: 27
7529 01:37:09.120871
7530 01:37:09.121365 Set Vref, RX VrefLevel [Byte0]: 28
7531 01:37:09.124100 [Byte1]: 28
7532 01:37:09.128764
7533 01:37:09.129276 Set Vref, RX VrefLevel [Byte0]: 29
7534 01:37:09.132140 [Byte1]: 29
7535 01:37:09.136062
7536 01:37:09.136482 Set Vref, RX VrefLevel [Byte0]: 30
7537 01:37:09.139391 [Byte1]: 30
7538 01:37:09.143888
7539 01:37:09.144434 Set Vref, RX VrefLevel [Byte0]: 31
7540 01:37:09.146918 [Byte1]: 31
7541 01:37:09.151516
7542 01:37:09.151975 Set Vref, RX VrefLevel [Byte0]: 32
7543 01:37:09.154683 [Byte1]: 32
7544 01:37:09.159455
7545 01:37:09.160021 Set Vref, RX VrefLevel [Byte0]: 33
7546 01:37:09.162424 [Byte1]: 33
7547 01:37:09.166609
7548 01:37:09.167069 Set Vref, RX VrefLevel [Byte0]: 34
7549 01:37:09.169919 [Byte1]: 34
7550 01:37:09.174667
7551 01:37:09.175227 Set Vref, RX VrefLevel [Byte0]: 35
7552 01:37:09.177442 [Byte1]: 35
7553 01:37:09.181697
7554 01:37:09.184765 Set Vref, RX VrefLevel [Byte0]: 36
7555 01:37:09.188454 [Byte1]: 36
7556 01:37:09.188976
7557 01:37:09.192381 Set Vref, RX VrefLevel [Byte0]: 37
7558 01:37:09.195045 [Byte1]: 37
7559 01:37:09.195516
7560 01:37:09.198293 Set Vref, RX VrefLevel [Byte0]: 38
7561 01:37:09.201683 [Byte1]: 38
7562 01:37:09.204945
7563 01:37:09.205546 Set Vref, RX VrefLevel [Byte0]: 39
7564 01:37:09.208006 [Byte1]: 39
7565 01:37:09.212096
7566 01:37:09.212649 Set Vref, RX VrefLevel [Byte0]: 40
7567 01:37:09.215386 [Byte1]: 40
7568 01:37:09.220444
7569 01:37:09.220905 Set Vref, RX VrefLevel [Byte0]: 41
7570 01:37:09.223346 [Byte1]: 41
7571 01:37:09.227622
7572 01:37:09.228205 Set Vref, RX VrefLevel [Byte0]: 42
7573 01:37:09.230807 [Byte1]: 42
7574 01:37:09.235074
7575 01:37:09.235493 Set Vref, RX VrefLevel [Byte0]: 43
7576 01:37:09.238337 [Byte1]: 43
7577 01:37:09.242672
7578 01:37:09.243092 Set Vref, RX VrefLevel [Byte0]: 44
7579 01:37:09.246475 [Byte1]: 44
7580 01:37:09.250246
7581 01:37:09.250716 Set Vref, RX VrefLevel [Byte0]: 45
7582 01:37:09.253888 [Byte1]: 45
7583 01:37:09.257969
7584 01:37:09.258521 Set Vref, RX VrefLevel [Byte0]: 46
7585 01:37:09.261032 [Byte1]: 46
7586 01:37:09.265617
7587 01:37:09.266091 Set Vref, RX VrefLevel [Byte0]: 47
7588 01:37:09.269453 [Byte1]: 47
7589 01:37:09.273463
7590 01:37:09.273974 Set Vref, RX VrefLevel [Byte0]: 48
7591 01:37:09.276492 [Byte1]: 48
7592 01:37:09.281109
7593 01:37:09.281668 Set Vref, RX VrefLevel [Byte0]: 49
7594 01:37:09.283986 [Byte1]: 49
7595 01:37:09.288694
7596 01:37:09.289436 Set Vref, RX VrefLevel [Byte0]: 50
7597 01:37:09.291989 [Byte1]: 50
7598 01:37:09.296188
7599 01:37:09.296714 Set Vref, RX VrefLevel [Byte0]: 51
7600 01:37:09.299394 [Byte1]: 51
7601 01:37:09.303642
7602 01:37:09.304060 Set Vref, RX VrefLevel [Byte0]: 52
7603 01:37:09.306858 [Byte1]: 52
7604 01:37:09.311176
7605 01:37:09.311595 Set Vref, RX VrefLevel [Byte0]: 53
7606 01:37:09.314816 [Byte1]: 53
7607 01:37:09.319218
7608 01:37:09.319742 Set Vref, RX VrefLevel [Byte0]: 54
7609 01:37:09.322232 [Byte1]: 54
7610 01:37:09.326674
7611 01:37:09.327188 Set Vref, RX VrefLevel [Byte0]: 55
7612 01:37:09.329971 [Byte1]: 55
7613 01:37:09.334264
7614 01:37:09.334775 Set Vref, RX VrefLevel [Byte0]: 56
7615 01:37:09.337730 [Byte1]: 56
7616 01:37:09.341657
7617 01:37:09.342077 Set Vref, RX VrefLevel [Byte0]: 57
7618 01:37:09.344953 [Byte1]: 57
7619 01:37:09.349398
7620 01:37:09.349819 Set Vref, RX VrefLevel [Byte0]: 58
7621 01:37:09.352810 [Byte1]: 58
7622 01:37:09.356824
7623 01:37:09.357244 Set Vref, RX VrefLevel [Byte0]: 59
7624 01:37:09.360396 [Byte1]: 59
7625 01:37:09.364761
7626 01:37:09.365276 Set Vref, RX VrefLevel [Byte0]: 60
7627 01:37:09.367828 [Byte1]: 60
7628 01:37:09.372409
7629 01:37:09.372921 Set Vref, RX VrefLevel [Byte0]: 61
7630 01:37:09.375716 [Byte1]: 61
7631 01:37:09.379867
7632 01:37:09.380375 Set Vref, RX VrefLevel [Byte0]: 62
7633 01:37:09.383251 [Byte1]: 62
7634 01:37:09.387563
7635 01:37:09.388071 Set Vref, RX VrefLevel [Byte0]: 63
7636 01:37:09.390666 [Byte1]: 63
7637 01:37:09.395042
7638 01:37:09.395562 Set Vref, RX VrefLevel [Byte0]: 64
7639 01:37:09.398601 [Byte1]: 64
7640 01:37:09.402671
7641 01:37:09.403183 Set Vref, RX VrefLevel [Byte0]: 65
7642 01:37:09.406107 [Byte1]: 65
7643 01:37:09.410498
7644 01:37:09.411009 Set Vref, RX VrefLevel [Byte0]: 66
7645 01:37:09.413826 [Byte1]: 66
7646 01:37:09.417718
7647 01:37:09.418138 Set Vref, RX VrefLevel [Byte0]: 67
7648 01:37:09.421364 [Byte1]: 67
7649 01:37:09.425812
7650 01:37:09.426368 Set Vref, RX VrefLevel [Byte0]: 68
7651 01:37:09.428899 [Byte1]: 68
7652 01:37:09.433221
7653 01:37:09.433669 Set Vref, RX VrefLevel [Byte0]: 69
7654 01:37:09.436229 [Byte1]: 69
7655 01:37:09.440787
7656 01:37:09.441206 Set Vref, RX VrefLevel [Byte0]: 70
7657 01:37:09.443960 [Byte1]: 70
7658 01:37:09.448465
7659 01:37:09.448886 Final RX Vref Byte 0 = 54 to rank0
7660 01:37:09.452562 Final RX Vref Byte 1 = 53 to rank0
7661 01:37:09.454959 Final RX Vref Byte 0 = 54 to rank1
7662 01:37:09.458139 Final RX Vref Byte 1 = 53 to rank1==
7663 01:37:09.461543 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 01:37:09.468398 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7665 01:37:09.468922 ==
7666 01:37:09.469265 DQS Delay:
7667 01:37:09.471482 DQS0 = 0, DQS1 = 0
7668 01:37:09.471902 DQM Delay:
7669 01:37:09.472235 DQM0 = 126, DQM1 = 120
7670 01:37:09.474838 DQ Delay:
7671 01:37:09.478182 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7672 01:37:09.481437 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7673 01:37:09.484617 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7674 01:37:09.487809 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7675 01:37:09.488235
7676 01:37:09.488573
7677 01:37:09.488882
7678 01:37:09.491043 [DramC_TX_OE_Calibration] TA2
7679 01:37:09.495002 Original DQ_B0 (3 6) =30, OEN = 27
7680 01:37:09.497932 Original DQ_B1 (3 6) =30, OEN = 27
7681 01:37:09.501364 24, 0x0, End_B0=24 End_B1=24
7682 01:37:09.501881 25, 0x0, End_B0=25 End_B1=25
7683 01:37:09.504694 26, 0x0, End_B0=26 End_B1=26
7684 01:37:09.507865 27, 0x0, End_B0=27 End_B1=27
7685 01:37:09.511025 28, 0x0, End_B0=28 End_B1=28
7686 01:37:09.514603 29, 0x0, End_B0=29 End_B1=29
7687 01:37:09.515120 30, 0x0, End_B0=30 End_B1=30
7688 01:37:09.517589 31, 0x4141, End_B0=30 End_B1=30
7689 01:37:09.521404 Byte0 end_step=30 best_step=27
7690 01:37:09.524563 Byte1 end_step=30 best_step=27
7691 01:37:09.528086 Byte0 TX OE(2T, 0.5T) = (3, 3)
7692 01:37:09.531261 Byte1 TX OE(2T, 0.5T) = (3, 3)
7693 01:37:09.531775
7694 01:37:09.532112
7695 01:37:09.537372 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7696 01:37:09.540781 CH0 RK0: MR19=303, MR18=1818
7697 01:37:09.547534 CH0_RK0: MR19=0x303, MR18=0x1818, DQSOSC=397, MR23=63, INC=23, DEC=15
7698 01:37:09.548046
7699 01:37:09.550876 ----->DramcWriteLeveling(PI) begin...
7700 01:37:09.551364 ==
7701 01:37:09.553948 Dram Type= 6, Freq= 0, CH_0, rank 1
7702 01:37:09.557381 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7703 01:37:09.557896 ==
7704 01:37:09.560655 Write leveling (Byte 0): 30 => 30
7705 01:37:09.564284 Write leveling (Byte 1): 26 => 26
7706 01:37:09.567431 DramcWriteLeveling(PI) end<-----
7707 01:37:09.567967
7708 01:37:09.568309 ==
7709 01:37:09.570820 Dram Type= 6, Freq= 0, CH_0, rank 1
7710 01:37:09.573888 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7711 01:37:09.574315 ==
7712 01:37:09.577104 [Gating] SW mode calibration
7713 01:37:09.584074 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7714 01:37:09.590238 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7715 01:37:09.594024 0 12 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7716 01:37:09.600636 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7717 01:37:09.604021 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7718 01:37:09.606934 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7719 01:37:09.613425 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7720 01:37:09.617170 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 01:37:09.620327 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 01:37:09.627059 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
7723 01:37:09.630289 0 13 0 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7724 01:37:09.633554 0 13 4 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 0)
7725 01:37:09.640182 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7726 01:37:09.643688 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 01:37:09.646404 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7728 01:37:09.653328 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7729 01:37:09.656418 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 01:37:09.659814 0 13 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7731 01:37:09.666401 0 14 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
7732 01:37:09.669811 0 14 4 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
7733 01:37:09.672944 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 01:37:09.679602 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 01:37:09.682632 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7736 01:37:09.686134 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 01:37:09.692673 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 01:37:09.695917 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7739 01:37:09.699296 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7740 01:37:09.705858 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7741 01:37:09.709097 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7742 01:37:09.713094 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 01:37:09.719028 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 01:37:09.722666 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 01:37:09.725909 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 01:37:09.732451 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 01:37:09.735935 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 01:37:09.739539 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 01:37:09.745919 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 01:37:09.748974 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 01:37:09.752246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 01:37:09.758933 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 01:37:09.762190 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 01:37:09.765397 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 01:37:09.772228 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7756 01:37:09.775389 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7757 01:37:09.778529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 01:37:09.781913 Total UI for P1: 0, mck2ui 16
7759 01:37:09.785360 best dqsien dly found for B0: ( 1, 1, 2)
7760 01:37:09.788402 Total UI for P1: 0, mck2ui 16
7761 01:37:09.792177 best dqsien dly found for B1: ( 1, 1, 4)
7762 01:37:09.795278 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7763 01:37:09.798899 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7764 01:37:09.799466
7765 01:37:09.801859 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7766 01:37:09.808247 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7767 01:37:09.808711 [Gating] SW calibration Done
7768 01:37:09.809079 ==
7769 01:37:09.811901 Dram Type= 6, Freq= 0, CH_0, rank 1
7770 01:37:09.818354 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7771 01:37:09.818919 ==
7772 01:37:09.819490 RX Vref Scan: 0
7773 01:37:09.819872
7774 01:37:09.821422 RX Vref 0 -> 0, step: 1
7775 01:37:09.821882
7776 01:37:09.825015 RX Delay 0 -> 252, step: 8
7777 01:37:09.828125 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7778 01:37:09.831504 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7779 01:37:09.834587 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7780 01:37:09.841524 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7781 01:37:09.844850 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7782 01:37:09.848166 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7783 01:37:09.851733 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7784 01:37:09.854393 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7785 01:37:09.861194 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7786 01:37:09.864550 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7787 01:37:09.867881 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7788 01:37:09.871257 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7789 01:37:09.874390 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7790 01:37:09.881003 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7791 01:37:09.884181 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7792 01:37:09.887521 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7793 01:37:09.888079 ==
7794 01:37:09.890595 Dram Type= 6, Freq= 0, CH_0, rank 1
7795 01:37:09.894632 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7796 01:37:09.897258 ==
7797 01:37:09.897748 DQS Delay:
7798 01:37:09.898109 DQS0 = 0, DQS1 = 0
7799 01:37:09.900828 DQM Delay:
7800 01:37:09.901429 DQM0 = 130, DQM1 = 123
7801 01:37:09.904000 DQ Delay:
7802 01:37:09.907234 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7803 01:37:09.910906 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7804 01:37:09.914154 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7805 01:37:09.917487 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7806 01:37:09.918042
7807 01:37:09.918407
7808 01:37:09.918741 ==
7809 01:37:09.920780 Dram Type= 6, Freq= 0, CH_0, rank 1
7810 01:37:09.924017 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7811 01:37:09.924577 ==
7812 01:37:09.924943
7813 01:37:09.927129
7814 01:37:09.927585 TX Vref Scan disable
7815 01:37:09.930732 == TX Byte 0 ==
7816 01:37:09.933575 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7817 01:37:09.936981 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7818 01:37:09.940175 == TX Byte 1 ==
7819 01:37:09.943575 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7820 01:37:09.946985 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7821 01:37:09.947444 ==
7822 01:37:09.950135 Dram Type= 6, Freq= 0, CH_0, rank 1
7823 01:37:09.956672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7824 01:37:09.957230 ==
7825 01:37:09.969386
7826 01:37:09.972458 TX Vref early break, caculate TX vref
7827 01:37:09.975536 TX Vref=16, minBit 8, minWin=22, winSum=373
7828 01:37:09.978803 TX Vref=18, minBit 9, minWin=22, winSum=375
7829 01:37:09.982117 TX Vref=20, minBit 11, minWin=22, winSum=387
7830 01:37:09.985520 TX Vref=22, minBit 8, minWin=23, winSum=396
7831 01:37:09.988815 TX Vref=24, minBit 9, minWin=24, winSum=406
7832 01:37:09.995705 TX Vref=26, minBit 11, minWin=24, winSum=413
7833 01:37:09.998818 TX Vref=28, minBit 7, minWin=25, winSum=416
7834 01:37:10.002073 TX Vref=30, minBit 0, minWin=24, winSum=406
7835 01:37:10.005105 TX Vref=32, minBit 1, minWin=24, winSum=399
7836 01:37:10.008507 TX Vref=34, minBit 8, minWin=22, winSum=393
7837 01:37:10.015368 [TxChooseVref] Worse bit 7, Min win 25, Win sum 416, Final Vref 28
7838 01:37:10.015935
7839 01:37:10.018726 Final TX Range 0 Vref 28
7840 01:37:10.019191
7841 01:37:10.019554 ==
7842 01:37:10.021871 Dram Type= 6, Freq= 0, CH_0, rank 1
7843 01:37:10.025135 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7844 01:37:10.025635 ==
7845 01:37:10.026005
7846 01:37:10.026347
7847 01:37:10.028582 TX Vref Scan disable
7848 01:37:10.035142 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7849 01:37:10.035615 == TX Byte 0 ==
7850 01:37:10.038650 u2DelayCellOfst[0]=14 cells (4 PI)
7851 01:37:10.041890 u2DelayCellOfst[1]=21 cells (6 PI)
7852 01:37:10.045044 u2DelayCellOfst[2]=14 cells (4 PI)
7853 01:37:10.048295 u2DelayCellOfst[3]=14 cells (4 PI)
7854 01:37:10.052273 u2DelayCellOfst[4]=7 cells (2 PI)
7855 01:37:10.055132 u2DelayCellOfst[5]=0 cells (0 PI)
7856 01:37:10.058281 u2DelayCellOfst[6]=21 cells (6 PI)
7857 01:37:10.061928 u2DelayCellOfst[7]=18 cells (5 PI)
7858 01:37:10.065231 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7859 01:37:10.068171 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7860 01:37:10.071913 == TX Byte 1 ==
7861 01:37:10.072469 u2DelayCellOfst[8]=0 cells (0 PI)
7862 01:37:10.075324 u2DelayCellOfst[9]=0 cells (0 PI)
7863 01:37:10.078306 u2DelayCellOfst[10]=10 cells (3 PI)
7864 01:37:10.081905 u2DelayCellOfst[11]=3 cells (1 PI)
7865 01:37:10.084838 u2DelayCellOfst[12]=14 cells (4 PI)
7866 01:37:10.088368 u2DelayCellOfst[13]=14 cells (4 PI)
7867 01:37:10.091507 u2DelayCellOfst[14]=18 cells (5 PI)
7868 01:37:10.094927 u2DelayCellOfst[15]=14 cells (4 PI)
7869 01:37:10.097941 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7870 01:37:10.105057 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7871 01:37:10.105701 DramC Write-DBI on
7872 01:37:10.106081 ==
7873 01:37:10.107983 Dram Type= 6, Freq= 0, CH_0, rank 1
7874 01:37:10.114741 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7875 01:37:10.115210 ==
7876 01:37:10.115578
7877 01:37:10.115922
7878 01:37:10.116289 TX Vref Scan disable
7879 01:37:10.118801 == TX Byte 0 ==
7880 01:37:10.121964 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7881 01:37:10.125024 == TX Byte 1 ==
7882 01:37:10.129153 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7883 01:37:10.131571 DramC Write-DBI off
7884 01:37:10.132119
7885 01:37:10.132487 [DATLAT]
7886 01:37:10.132831 Freq=1600, CH0 RK1
7887 01:37:10.133158
7888 01:37:10.134900 DATLAT Default: 0xe
7889 01:37:10.137925 0, 0xFFFF, sum = 0
7890 01:37:10.138395 1, 0xFFFF, sum = 0
7891 01:37:10.141565 2, 0xFFFF, sum = 0
7892 01:37:10.141994 3, 0xFFFF, sum = 0
7893 01:37:10.144611 4, 0xFFFF, sum = 0
7894 01:37:10.145034 5, 0xFFFF, sum = 0
7895 01:37:10.148103 6, 0xFFFF, sum = 0
7896 01:37:10.148616 7, 0xFFFF, sum = 0
7897 01:37:10.151510 8, 0xFFFF, sum = 0
7898 01:37:10.152024 9, 0xFFFF, sum = 0
7899 01:37:10.154810 10, 0xFFFF, sum = 0
7900 01:37:10.155338 11, 0xFFFF, sum = 0
7901 01:37:10.157925 12, 0x8FFF, sum = 0
7902 01:37:10.158353 13, 0x0, sum = 1
7903 01:37:10.161395 14, 0x0, sum = 2
7904 01:37:10.161912 15, 0x0, sum = 3
7905 01:37:10.164649 16, 0x0, sum = 4
7906 01:37:10.165167 best_step = 14
7907 01:37:10.165561
7908 01:37:10.165873 ==
7909 01:37:10.167729 Dram Type= 6, Freq= 0, CH_0, rank 1
7910 01:37:10.174613 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7911 01:37:10.175125 ==
7912 01:37:10.175463 RX Vref Scan: 0
7913 01:37:10.175775
7914 01:37:10.177982 RX Vref 0 -> 0, step: 1
7915 01:37:10.178507
7916 01:37:10.180955 RX Delay 11 -> 252, step: 4
7917 01:37:10.184557 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7918 01:37:10.187976 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7919 01:37:10.190777 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7920 01:37:10.197568 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7921 01:37:10.200920 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7922 01:37:10.204215 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7923 01:37:10.207361 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7924 01:37:10.210735 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7925 01:37:10.217441 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7926 01:37:10.220965 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7927 01:37:10.224636 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7928 01:37:10.227090 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7929 01:37:10.233895 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7930 01:37:10.237251 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7931 01:37:10.240704 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7932 01:37:10.243887 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7933 01:37:10.244310 ==
7934 01:37:10.247082 Dram Type= 6, Freq= 0, CH_0, rank 1
7935 01:37:10.250804 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7936 01:37:10.253818 ==
7937 01:37:10.254239 DQS Delay:
7938 01:37:10.254572 DQS0 = 0, DQS1 = 0
7939 01:37:10.257054 DQM Delay:
7940 01:37:10.257513 DQM0 = 128, DQM1 = 120
7941 01:37:10.260713 DQ Delay:
7942 01:37:10.264127 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
7943 01:37:10.267210 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7944 01:37:10.270241 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7945 01:37:10.273833 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7946 01:37:10.274347
7947 01:37:10.274685
7948 01:37:10.274992
7949 01:37:10.277330 [DramC_TX_OE_Calibration] TA2
7950 01:37:10.280461 Original DQ_B0 (3 6) =30, OEN = 27
7951 01:37:10.284011 Original DQ_B1 (3 6) =30, OEN = 27
7952 01:37:10.286960 24, 0x0, End_B0=24 End_B1=24
7953 01:37:10.287392 25, 0x0, End_B0=25 End_B1=25
7954 01:37:10.290226 26, 0x0, End_B0=26 End_B1=26
7955 01:37:10.293479 27, 0x0, End_B0=27 End_B1=27
7956 01:37:10.297038 28, 0x0, End_B0=28 End_B1=28
7957 01:37:10.300057 29, 0x0, End_B0=29 End_B1=29
7958 01:37:10.300574 30, 0x0, End_B0=30 End_B1=30
7959 01:37:10.303062 31, 0x4141, End_B0=30 End_B1=30
7960 01:37:10.306589 Byte0 end_step=30 best_step=27
7961 01:37:10.309755 Byte1 end_step=30 best_step=27
7962 01:37:10.313376 Byte0 TX OE(2T, 0.5T) = (3, 3)
7963 01:37:10.316563 Byte1 TX OE(2T, 0.5T) = (3, 3)
7964 01:37:10.317093
7965 01:37:10.317545
7966 01:37:10.323348 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7967 01:37:10.326332 CH0 RK1: MR19=303, MR18=2121
7968 01:37:10.333095 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7969 01:37:10.336367 [RxdqsGatingPostProcess] freq 1600
7970 01:37:10.339599 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7971 01:37:10.342813 Pre-setting of DQS Precalculation
7972 01:37:10.349440 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7973 01:37:10.349907 ==
7974 01:37:10.352988 Dram Type= 6, Freq= 0, CH_1, rank 0
7975 01:37:10.356216 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7976 01:37:10.356681 ==
7977 01:37:10.362699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7978 01:37:10.366001 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7979 01:37:10.369463 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7980 01:37:10.375629 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7981 01:37:10.384556 [CA 0] Center 41 (11~71) winsize 61
7982 01:37:10.387837 [CA 1] Center 40 (10~71) winsize 62
7983 01:37:10.391010 [CA 2] Center 36 (6~66) winsize 61
7984 01:37:10.394462 [CA 3] Center 35 (5~65) winsize 61
7985 01:37:10.397917 [CA 4] Center 33 (4~63) winsize 60
7986 01:37:10.401091 [CA 5] Center 33 (4~63) winsize 60
7987 01:37:10.401777
7988 01:37:10.404609 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7989 01:37:10.405073
7990 01:37:10.407625 [CATrainingPosCal] consider 1 rank data
7991 01:37:10.410886 u2DelayCellTimex100 = 271/100 ps
7992 01:37:10.417376 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
7993 01:37:10.420832 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
7994 01:37:10.424440 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
7995 01:37:10.427305 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
7996 01:37:10.430613 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
7997 01:37:10.434042 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
7998 01:37:10.434463
7999 01:37:10.437119 CA PerBit enable=1, Macro0, CA PI delay=33
8000 01:37:10.437608
8001 01:37:10.440658 [CBTSetCACLKResult] CA Dly = 33
8002 01:37:10.443882 CS Dly: 9 (0~40)
8003 01:37:10.447279 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8004 01:37:10.450768 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8005 01:37:10.451328 ==
8006 01:37:10.453950 Dram Type= 6, Freq= 0, CH_1, rank 1
8007 01:37:10.460452 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8008 01:37:10.461021 ==
8009 01:37:10.464069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8010 01:37:10.466962 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8011 01:37:10.473658 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8012 01:37:10.480111 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8013 01:37:10.487207 [CA 0] Center 40 (10~70) winsize 61
8014 01:37:10.490250 [CA 1] Center 40 (10~70) winsize 61
8015 01:37:10.493278 [CA 2] Center 35 (6~65) winsize 60
8016 01:37:10.496835 [CA 3] Center 35 (5~65) winsize 61
8017 01:37:10.499937 [CA 4] Center 33 (4~62) winsize 59
8018 01:37:10.503326 [CA 5] Center 33 (3~63) winsize 61
8019 01:37:10.503781
8020 01:37:10.506459 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8021 01:37:10.507207
8022 01:37:10.510184 [CATrainingPosCal] consider 2 rank data
8023 01:37:10.513395 u2DelayCellTimex100 = 271/100 ps
8024 01:37:10.516488 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8025 01:37:10.523550 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8026 01:37:10.526934 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8027 01:37:10.530021 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
8028 01:37:10.533434 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8029 01:37:10.536659 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8030 01:37:10.537219
8031 01:37:10.540057 CA PerBit enable=1, Macro0, CA PI delay=33
8032 01:37:10.540605
8033 01:37:10.543063 [CBTSetCACLKResult] CA Dly = 33
8034 01:37:10.546350 CS Dly: 9 (0~41)
8035 01:37:10.549751 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8036 01:37:10.552802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8037 01:37:10.553260
8038 01:37:10.556488 ----->DramcWriteLeveling(PI) begin...
8039 01:37:10.557051 ==
8040 01:37:10.559475 Dram Type= 6, Freq= 0, CH_1, rank 0
8041 01:37:10.566238 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8042 01:37:10.566806 ==
8043 01:37:10.569651 Write leveling (Byte 0): 21 => 21
8044 01:37:10.572688 Write leveling (Byte 1): 21 => 21
8045 01:37:10.573144 DramcWriteLeveling(PI) end<-----
8046 01:37:10.573539
8047 01:37:10.576098 ==
8048 01:37:10.579433 Dram Type= 6, Freq= 0, CH_1, rank 0
8049 01:37:10.582751 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8050 01:37:10.583314 ==
8051 01:37:10.585949 [Gating] SW mode calibration
8052 01:37:10.592564 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8053 01:37:10.595734 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8054 01:37:10.602491 0 12 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8055 01:37:10.605652 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 01:37:10.608991 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 01:37:10.615815 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 01:37:10.619141 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 01:37:10.622864 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 01:37:10.629174 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 01:37:10.632468 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
8062 01:37:10.635804 0 13 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
8063 01:37:10.642390 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 01:37:10.646040 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 01:37:10.649113 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 01:37:10.655990 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 01:37:10.658829 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 01:37:10.662221 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 01:37:10.669000 0 13 28 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8070 01:37:10.672237 0 14 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8071 01:37:10.675737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 01:37:10.682087 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 01:37:10.685532 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 01:37:10.688601 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 01:37:10.695050 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 01:37:10.698482 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 01:37:10.701864 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8078 01:37:10.708613 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8079 01:37:10.712035 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8080 01:37:10.715070 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 01:37:10.722069 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 01:37:10.724993 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 01:37:10.728250 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 01:37:10.734727 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 01:37:10.738191 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 01:37:10.741646 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 01:37:10.748228 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 01:37:10.751816 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 01:37:10.755260 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 01:37:10.758053 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 01:37:10.764950 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 01:37:10.768126 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 01:37:10.771193 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8094 01:37:10.778241 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 01:37:10.781354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 01:37:10.784626 Total UI for P1: 0, mck2ui 16
8097 01:37:10.787712 best dqsien dly found for B0: ( 1, 0, 30)
8098 01:37:10.791220 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 01:37:10.794503 Total UI for P1: 0, mck2ui 16
8100 01:37:10.797598 best dqsien dly found for B1: ( 1, 1, 4)
8101 01:37:10.801339 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
8102 01:37:10.804398 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8103 01:37:10.807939
8104 01:37:10.811163 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
8105 01:37:10.814290 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8106 01:37:10.817374 [Gating] SW calibration Done
8107 01:37:10.817840 ==
8108 01:37:10.820752 Dram Type= 6, Freq= 0, CH_1, rank 0
8109 01:37:10.824278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8110 01:37:10.824835 ==
8111 01:37:10.825208 RX Vref Scan: 0
8112 01:37:10.827485
8113 01:37:10.828037 RX Vref 0 -> 0, step: 1
8114 01:37:10.828407
8115 01:37:10.830774 RX Delay 0 -> 252, step: 8
8116 01:37:10.834152 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8117 01:37:10.837416 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8118 01:37:10.843716 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8119 01:37:10.847234 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8120 01:37:10.850791 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8121 01:37:10.854072 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8122 01:37:10.857121 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8123 01:37:10.864177 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8124 01:37:10.867318 iDelay=200, Bit 8, Center 107 (56 ~ 159) 104
8125 01:37:10.870457 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8126 01:37:10.873777 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8127 01:37:10.877398 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8128 01:37:10.883934 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8129 01:37:10.886997 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8130 01:37:10.890054 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8131 01:37:10.893883 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8132 01:37:10.894441 ==
8133 01:37:10.897000 Dram Type= 6, Freq= 0, CH_1, rank 0
8134 01:37:10.904131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8135 01:37:10.904729 ==
8136 01:37:10.905220 DQS Delay:
8137 01:37:10.907179 DQS0 = 0, DQS1 = 0
8138 01:37:10.907751 DQM Delay:
8139 01:37:10.908240 DQM0 = 129, DQM1 = 125
8140 01:37:10.910310 DQ Delay:
8141 01:37:10.913574 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8142 01:37:10.917077 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8143 01:37:10.920288 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8144 01:37:10.923767 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8145 01:37:10.924343
8146 01:37:10.924829
8147 01:37:10.925278 ==
8148 01:37:10.927252 Dram Type= 6, Freq= 0, CH_1, rank 0
8149 01:37:10.930300 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8150 01:37:10.933804 ==
8151 01:37:10.934370
8152 01:37:10.934853
8153 01:37:10.935301 TX Vref Scan disable
8154 01:37:10.936898 == TX Byte 0 ==
8155 01:37:10.940361 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8156 01:37:10.943407 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8157 01:37:10.947107 == TX Byte 1 ==
8158 01:37:10.950099 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8159 01:37:10.953476 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8160 01:37:10.957402 ==
8161 01:37:10.960186 Dram Type= 6, Freq= 0, CH_1, rank 0
8162 01:37:10.963328 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8163 01:37:10.963903 ==
8164 01:37:10.975138
8165 01:37:10.978276 TX Vref early break, caculate TX vref
8166 01:37:10.981978 TX Vref=16, minBit 0, minWin=21, winSum=370
8167 01:37:10.984872 TX Vref=18, minBit 3, minWin=21, winSum=380
8168 01:37:10.988206 TX Vref=20, minBit 0, minWin=23, winSum=389
8169 01:37:10.991743 TX Vref=22, minBit 1, minWin=23, winSum=392
8170 01:37:10.994852 TX Vref=24, minBit 1, minWin=24, winSum=407
8171 01:37:11.001368 TX Vref=26, minBit 1, minWin=24, winSum=413
8172 01:37:11.004753 TX Vref=28, minBit 3, minWin=24, winSum=413
8173 01:37:11.008084 TX Vref=30, minBit 3, minWin=23, winSum=405
8174 01:37:11.011299 TX Vref=32, minBit 3, minWin=23, winSum=398
8175 01:37:11.014969 TX Vref=34, minBit 1, minWin=23, winSum=390
8176 01:37:11.021407 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 26
8177 01:37:11.021962
8178 01:37:11.024735 Final TX Range 0 Vref 26
8179 01:37:11.025332
8180 01:37:11.025707 ==
8181 01:37:11.027802 Dram Type= 6, Freq= 0, CH_1, rank 0
8182 01:37:11.031103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8183 01:37:11.031665 ==
8184 01:37:11.032031
8185 01:37:11.032362
8186 01:37:11.034044 TX Vref Scan disable
8187 01:37:11.040809 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8188 01:37:11.041406 == TX Byte 0 ==
8189 01:37:11.044181 u2DelayCellOfst[0]=18 cells (5 PI)
8190 01:37:11.047479 u2DelayCellOfst[1]=10 cells (3 PI)
8191 01:37:11.050786 u2DelayCellOfst[2]=0 cells (0 PI)
8192 01:37:11.054139 u2DelayCellOfst[3]=7 cells (2 PI)
8193 01:37:11.057227 u2DelayCellOfst[4]=7 cells (2 PI)
8194 01:37:11.060597 u2DelayCellOfst[5]=18 cells (5 PI)
8195 01:37:11.064102 u2DelayCellOfst[6]=18 cells (5 PI)
8196 01:37:11.067339 u2DelayCellOfst[7]=7 cells (2 PI)
8197 01:37:11.070758 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8198 01:37:11.073909 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8199 01:37:11.077409 == TX Byte 1 ==
8200 01:37:11.080763 u2DelayCellOfst[8]=0 cells (0 PI)
8201 01:37:11.081352 u2DelayCellOfst[9]=7 cells (2 PI)
8202 01:37:11.083822 u2DelayCellOfst[10]=14 cells (4 PI)
8203 01:37:11.086970 u2DelayCellOfst[11]=3 cells (1 PI)
8204 01:37:11.090774 u2DelayCellOfst[12]=18 cells (5 PI)
8205 01:37:11.093705 u2DelayCellOfst[13]=21 cells (6 PI)
8206 01:37:11.096644 u2DelayCellOfst[14]=21 cells (6 PI)
8207 01:37:11.100249 u2DelayCellOfst[15]=18 cells (5 PI)
8208 01:37:11.107091 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8209 01:37:11.110036 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8210 01:37:11.110719 DramC Write-DBI on
8211 01:37:11.111109 ==
8212 01:37:11.113381 Dram Type= 6, Freq= 0, CH_1, rank 0
8213 01:37:11.120082 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8214 01:37:11.120646 ==
8215 01:37:11.121014
8216 01:37:11.121400
8217 01:37:11.121731 TX Vref Scan disable
8218 01:37:11.123904 == TX Byte 0 ==
8219 01:37:11.127493 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8220 01:37:11.130632 == TX Byte 1 ==
8221 01:37:11.133986 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8222 01:37:11.137452 DramC Write-DBI off
8223 01:37:11.138008
8224 01:37:11.138374 [DATLAT]
8225 01:37:11.138751 Freq=1600, CH1 RK0
8226 01:37:11.139080
8227 01:37:11.140440 DATLAT Default: 0xf
8228 01:37:11.140897 0, 0xFFFF, sum = 0
8229 01:37:11.143752 1, 0xFFFF, sum = 0
8230 01:37:11.146939 2, 0xFFFF, sum = 0
8231 01:37:11.147403 3, 0xFFFF, sum = 0
8232 01:37:11.150626 4, 0xFFFF, sum = 0
8233 01:37:11.151205 5, 0xFFFF, sum = 0
8234 01:37:11.153884 6, 0xFFFF, sum = 0
8235 01:37:11.154349 7, 0xFFFF, sum = 0
8236 01:37:11.157117 8, 0xFFFF, sum = 0
8237 01:37:11.157698 9, 0xFFFF, sum = 0
8238 01:37:11.160356 10, 0xFFFF, sum = 0
8239 01:37:11.160823 11, 0xFFFF, sum = 0
8240 01:37:11.163822 12, 0xF7F, sum = 0
8241 01:37:11.164383 13, 0x0, sum = 1
8242 01:37:11.167438 14, 0x0, sum = 2
8243 01:37:11.168051 15, 0x0, sum = 3
8244 01:37:11.170461 16, 0x0, sum = 4
8245 01:37:11.170925 best_step = 14
8246 01:37:11.171284
8247 01:37:11.171620 ==
8248 01:37:11.173819 Dram Type= 6, Freq= 0, CH_1, rank 0
8249 01:37:11.177129 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8250 01:37:11.180270 ==
8251 01:37:11.180823 RX Vref Scan: 1
8252 01:37:11.181186
8253 01:37:11.183772 Set Vref Range= 24 -> 127
8254 01:37:11.184325
8255 01:37:11.186749 RX Vref 24 -> 127, step: 1
8256 01:37:11.187205
8257 01:37:11.187564 RX Delay 11 -> 252, step: 4
8258 01:37:11.187897
8259 01:37:11.190035 Set Vref, RX VrefLevel [Byte0]: 24
8260 01:37:11.193527 [Byte1]: 24
8261 01:37:11.197167
8262 01:37:11.197730 Set Vref, RX VrefLevel [Byte0]: 25
8263 01:37:11.200528 [Byte1]: 25
8264 01:37:11.205089
8265 01:37:11.205684 Set Vref, RX VrefLevel [Byte0]: 26
8266 01:37:11.208480 [Byte1]: 26
8267 01:37:11.212762
8268 01:37:11.213357 Set Vref, RX VrefLevel [Byte0]: 27
8269 01:37:11.215951 [Byte1]: 27
8270 01:37:11.220514
8271 01:37:11.221092 Set Vref, RX VrefLevel [Byte0]: 28
8272 01:37:11.223594 [Byte1]: 28
8273 01:37:11.228015
8274 01:37:11.228570 Set Vref, RX VrefLevel [Byte0]: 29
8275 01:37:11.230825 [Byte1]: 29
8276 01:37:11.235307
8277 01:37:11.235860 Set Vref, RX VrefLevel [Byte0]: 30
8278 01:37:11.238552 [Byte1]: 30
8279 01:37:11.243099
8280 01:37:11.243653 Set Vref, RX VrefLevel [Byte0]: 31
8281 01:37:11.246123 [Byte1]: 31
8282 01:37:11.250576
8283 01:37:11.251125 Set Vref, RX VrefLevel [Byte0]: 32
8284 01:37:11.253964 [Byte1]: 32
8285 01:37:11.258294
8286 01:37:11.258852 Set Vref, RX VrefLevel [Byte0]: 33
8287 01:37:11.261596 [Byte1]: 33
8288 01:37:11.266034
8289 01:37:11.266591 Set Vref, RX VrefLevel [Byte0]: 34
8290 01:37:11.269021 [Byte1]: 34
8291 01:37:11.273509
8292 01:37:11.274061 Set Vref, RX VrefLevel [Byte0]: 35
8293 01:37:11.276617 [Byte1]: 35
8294 01:37:11.281106
8295 01:37:11.281780 Set Vref, RX VrefLevel [Byte0]: 36
8296 01:37:11.284123 [Byte1]: 36
8297 01:37:11.288793
8298 01:37:11.289245 Set Vref, RX VrefLevel [Byte0]: 37
8299 01:37:11.292313 [Byte1]: 37
8300 01:37:11.296185
8301 01:37:11.296637 Set Vref, RX VrefLevel [Byte0]: 38
8302 01:37:11.299268 [Byte1]: 38
8303 01:37:11.304053
8304 01:37:11.304617 Set Vref, RX VrefLevel [Byte0]: 39
8305 01:37:11.307162 [Byte1]: 39
8306 01:37:11.311253
8307 01:37:11.311896 Set Vref, RX VrefLevel [Byte0]: 40
8308 01:37:11.314569 [Byte1]: 40
8309 01:37:11.319167
8310 01:37:11.319716 Set Vref, RX VrefLevel [Byte0]: 41
8311 01:37:11.322328 [Byte1]: 41
8312 01:37:11.326957
8313 01:37:11.327502 Set Vref, RX VrefLevel [Byte0]: 42
8314 01:37:11.329979 [Byte1]: 42
8315 01:37:11.334368
8316 01:37:11.334926 Set Vref, RX VrefLevel [Byte0]: 43
8317 01:37:11.337401 [Byte1]: 43
8318 01:37:11.342184
8319 01:37:11.342733 Set Vref, RX VrefLevel [Byte0]: 44
8320 01:37:11.345168 [Byte1]: 44
8321 01:37:11.349518
8322 01:37:11.350076 Set Vref, RX VrefLevel [Byte0]: 45
8323 01:37:11.352887 [Byte1]: 45
8324 01:37:11.357260
8325 01:37:11.357852 Set Vref, RX VrefLevel [Byte0]: 46
8326 01:37:11.360582 [Byte1]: 46
8327 01:37:11.364876
8328 01:37:11.365460 Set Vref, RX VrefLevel [Byte0]: 47
8329 01:37:11.368458 [Byte1]: 47
8330 01:37:11.372477
8331 01:37:11.373029 Set Vref, RX VrefLevel [Byte0]: 48
8332 01:37:11.375825 [Byte1]: 48
8333 01:37:11.380115
8334 01:37:11.380665 Set Vref, RX VrefLevel [Byte0]: 49
8335 01:37:11.383404 [Byte1]: 49
8336 01:37:11.387912
8337 01:37:11.388457 Set Vref, RX VrefLevel [Byte0]: 50
8338 01:37:11.391219 [Byte1]: 50
8339 01:37:11.395323
8340 01:37:11.395830 Set Vref, RX VrefLevel [Byte0]: 51
8341 01:37:11.398330 [Byte1]: 51
8342 01:37:11.402985
8343 01:37:11.403434 Set Vref, RX VrefLevel [Byte0]: 52
8344 01:37:11.406037 [Byte1]: 52
8345 01:37:11.410402
8346 01:37:11.410851 Set Vref, RX VrefLevel [Byte0]: 53
8347 01:37:11.413745 [Byte1]: 53
8348 01:37:11.418395
8349 01:37:11.418943 Set Vref, RX VrefLevel [Byte0]: 54
8350 01:37:11.421278 [Byte1]: 54
8351 01:37:11.425916
8352 01:37:11.426502 Set Vref, RX VrefLevel [Byte0]: 55
8353 01:37:11.429217 [Byte1]: 55
8354 01:37:11.433352
8355 01:37:11.433807 Set Vref, RX VrefLevel [Byte0]: 56
8356 01:37:11.436708 [Byte1]: 56
8357 01:37:11.441125
8358 01:37:11.441727 Set Vref, RX VrefLevel [Byte0]: 57
8359 01:37:11.444041 [Byte1]: 57
8360 01:37:11.448672
8361 01:37:11.449317 Set Vref, RX VrefLevel [Byte0]: 58
8362 01:37:11.452066 [Byte1]: 58
8363 01:37:11.456073
8364 01:37:11.456526 Set Vref, RX VrefLevel [Byte0]: 59
8365 01:37:11.459225 [Byte1]: 59
8366 01:37:11.463854
8367 01:37:11.464408 Set Vref, RX VrefLevel [Byte0]: 60
8368 01:37:11.467096 [Byte1]: 60
8369 01:37:11.471389
8370 01:37:11.471943 Set Vref, RX VrefLevel [Byte0]: 61
8371 01:37:11.474548 [Byte1]: 61
8372 01:37:11.479314
8373 01:37:11.479868 Set Vref, RX VrefLevel [Byte0]: 62
8374 01:37:11.482045 [Byte1]: 62
8375 01:37:11.486781
8376 01:37:11.487337 Set Vref, RX VrefLevel [Byte0]: 63
8377 01:37:11.489987 [Byte1]: 63
8378 01:37:11.494431
8379 01:37:11.494988 Set Vref, RX VrefLevel [Byte0]: 64
8380 01:37:11.497683 [Byte1]: 64
8381 01:37:11.501869
8382 01:37:11.502317 Set Vref, RX VrefLevel [Byte0]: 65
8383 01:37:11.505038 [Byte1]: 65
8384 01:37:11.509319
8385 01:37:11.509886 Set Vref, RX VrefLevel [Byte0]: 66
8386 01:37:11.512917 [Byte1]: 66
8387 01:37:11.517193
8388 01:37:11.517783 Set Vref, RX VrefLevel [Byte0]: 67
8389 01:37:11.520639 [Byte1]: 67
8390 01:37:11.524594
8391 01:37:11.525046 Set Vref, RX VrefLevel [Byte0]: 68
8392 01:37:11.527991 [Byte1]: 68
8393 01:37:11.532450
8394 01:37:11.533032 Set Vref, RX VrefLevel [Byte0]: 69
8395 01:37:11.535245 [Byte1]: 69
8396 01:37:11.539756
8397 01:37:11.540286 Set Vref, RX VrefLevel [Byte0]: 70
8398 01:37:11.543091 [Byte1]: 70
8399 01:37:11.547483
8400 01:37:11.548060 Set Vref, RX VrefLevel [Byte0]: 71
8401 01:37:11.550831 [Byte1]: 71
8402 01:37:11.554974
8403 01:37:11.555428 Set Vref, RX VrefLevel [Byte0]: 72
8404 01:37:11.558508 [Byte1]: 72
8405 01:37:11.562694
8406 01:37:11.563147 Set Vref, RX VrefLevel [Byte0]: 73
8407 01:37:11.565994 [Byte1]: 73
8408 01:37:11.570572
8409 01:37:11.571126 Set Vref, RX VrefLevel [Byte0]: 74
8410 01:37:11.573465 [Byte1]: 74
8411 01:37:11.578160
8412 01:37:11.578615 Set Vref, RX VrefLevel [Byte0]: 75
8413 01:37:11.581012 [Byte1]: 75
8414 01:37:11.585452
8415 01:37:11.585912 Set Vref, RX VrefLevel [Byte0]: 76
8416 01:37:11.588604 [Byte1]: 76
8417 01:37:11.593235
8418 01:37:11.593729 Set Vref, RX VrefLevel [Byte0]: 77
8419 01:37:11.596426 [Byte1]: 77
8420 01:37:11.600796
8421 01:37:11.601249 Final RX Vref Byte 0 = 64 to rank0
8422 01:37:11.604144 Final RX Vref Byte 1 = 55 to rank0
8423 01:37:11.607426 Final RX Vref Byte 0 = 64 to rank1
8424 01:37:11.610653 Final RX Vref Byte 1 = 55 to rank1==
8425 01:37:11.613798 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 01:37:11.620631 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8427 01:37:11.621188 ==
8428 01:37:11.621760 DQS Delay:
8429 01:37:11.623888 DQS0 = 0, DQS1 = 0
8430 01:37:11.624360 DQM Delay:
8431 01:37:11.624725 DQM0 = 128, DQM1 = 123
8432 01:37:11.627608 DQ Delay:
8433 01:37:11.630436 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8434 01:37:11.633683 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8435 01:37:11.636894 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =114
8436 01:37:11.640522 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8437 01:37:11.640981
8438 01:37:11.641382
8439 01:37:11.641728
8440 01:37:11.643818 [DramC_TX_OE_Calibration] TA2
8441 01:37:11.646945 Original DQ_B0 (3 6) =30, OEN = 27
8442 01:37:11.650058 Original DQ_B1 (3 6) =30, OEN = 27
8443 01:37:11.653835 24, 0x0, End_B0=24 End_B1=24
8444 01:37:11.654750 25, 0x0, End_B0=25 End_B1=25
8445 01:37:11.656668 26, 0x0, End_B0=26 End_B1=26
8446 01:37:11.660223 27, 0x0, End_B0=27 End_B1=27
8447 01:37:11.663456 28, 0x0, End_B0=28 End_B1=28
8448 01:37:11.666560 29, 0x0, End_B0=29 End_B1=29
8449 01:37:11.667155 30, 0x0, End_B0=30 End_B1=30
8450 01:37:11.670217 31, 0x4141, End_B0=30 End_B1=30
8451 01:37:11.673843 Byte0 end_step=30 best_step=27
8452 01:37:11.676891 Byte1 end_step=30 best_step=27
8453 01:37:11.680157 Byte0 TX OE(2T, 0.5T) = (3, 3)
8454 01:37:11.683504 Byte1 TX OE(2T, 0.5T) = (3, 3)
8455 01:37:11.684228
8456 01:37:11.684607
8457 01:37:11.689924 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8458 01:37:11.693083 CH1 RK0: MR19=303, MR18=2929
8459 01:37:11.699644 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8460 01:37:11.700242
8461 01:37:11.703500 ----->DramcWriteLeveling(PI) begin...
8462 01:37:11.704059 ==
8463 01:37:11.706299 Dram Type= 6, Freq= 0, CH_1, rank 1
8464 01:37:11.710038 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8465 01:37:11.710601 ==
8466 01:37:11.713117 Write leveling (Byte 0): 20 => 20
8467 01:37:11.716545 Write leveling (Byte 1): 19 => 19
8468 01:37:11.719721 DramcWriteLeveling(PI) end<-----
8469 01:37:11.720277
8470 01:37:11.720638 ==
8471 01:37:11.722871 Dram Type= 6, Freq= 0, CH_1, rank 1
8472 01:37:11.726080 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8473 01:37:11.729607 ==
8474 01:37:11.730163 [Gating] SW mode calibration
8475 01:37:11.739320 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8476 01:37:11.743060 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8477 01:37:11.745805 0 12 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8478 01:37:11.752854 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 01:37:11.756211 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 01:37:11.759039 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 01:37:11.765860 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 01:37:11.768923 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 01:37:11.772669 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8484 01:37:11.779084 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8485 01:37:11.782774 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8486 01:37:11.785972 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 01:37:11.792419 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 01:37:11.795478 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 01:37:11.798831 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 01:37:11.805559 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8491 01:37:11.808990 0 13 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8492 01:37:11.812069 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8493 01:37:11.818708 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
8494 01:37:11.822217 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 01:37:11.825450 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 01:37:11.832066 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 01:37:11.835463 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 01:37:11.838256 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 01:37:11.845448 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8500 01:37:11.848650 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8501 01:37:11.851712 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8502 01:37:11.858137 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8503 01:37:11.861543 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 01:37:11.865200 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 01:37:11.872180 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 01:37:11.874938 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 01:37:11.878314 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 01:37:11.884864 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 01:37:11.888478 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 01:37:11.891778 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 01:37:11.897990 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 01:37:11.901660 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 01:37:11.904917 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 01:37:11.911240 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8515 01:37:11.914424 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8516 01:37:11.918171 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8517 01:37:11.921379 Total UI for P1: 0, mck2ui 16
8518 01:37:11.924806 best dqsien dly found for B0: ( 1, 0, 22)
8519 01:37:11.928137 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8520 01:37:11.934878 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8521 01:37:11.937882 Total UI for P1: 0, mck2ui 16
8522 01:37:11.941454 best dqsien dly found for B1: ( 1, 1, 0)
8523 01:37:11.944694 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8524 01:37:11.947957 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8525 01:37:11.948511
8526 01:37:11.951374 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8527 01:37:11.954333 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8528 01:37:11.957576 [Gating] SW calibration Done
8529 01:37:11.958030 ==
8530 01:37:11.960885 Dram Type= 6, Freq= 0, CH_1, rank 1
8531 01:37:11.964366 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8532 01:37:11.964931 ==
8533 01:37:11.967968 RX Vref Scan: 0
8534 01:37:11.968525
8535 01:37:11.971007 RX Vref 0 -> 0, step: 1
8536 01:37:11.971575
8537 01:37:11.971947 RX Delay 0 -> 252, step: 8
8538 01:37:11.977780 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8539 01:37:11.980839 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8540 01:37:11.984267 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8541 01:37:11.987666 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8542 01:37:11.990561 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8543 01:37:11.997210 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8544 01:37:12.000545 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8545 01:37:12.003992 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8546 01:37:12.007211 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8547 01:37:12.010691 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8548 01:37:12.017534 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8549 01:37:12.020754 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8550 01:37:12.023951 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8551 01:37:12.027363 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8552 01:37:12.030531 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8553 01:37:12.037312 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8554 01:37:12.037882 ==
8555 01:37:12.040505 Dram Type= 6, Freq= 0, CH_1, rank 1
8556 01:37:12.043763 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8557 01:37:12.044321 ==
8558 01:37:12.044688 DQS Delay:
8559 01:37:12.046833 DQS0 = 0, DQS1 = 0
8560 01:37:12.047289 DQM Delay:
8561 01:37:12.050029 DQM0 = 130, DQM1 = 124
8562 01:37:12.050486 DQ Delay:
8563 01:37:12.053772 DQ0 =131, DQ1 =131, DQ2 =119, DQ3 =127
8564 01:37:12.056897 DQ4 =123, DQ5 =143, DQ6 =139, DQ7 =127
8565 01:37:12.060250 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8566 01:37:12.067048 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8567 01:37:12.067607
8568 01:37:12.067970
8569 01:37:12.068302 ==
8570 01:37:12.069999 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 01:37:12.073526 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 01:37:12.074108 ==
8573 01:37:12.074475
8574 01:37:12.074812
8575 01:37:12.076616 TX Vref Scan disable
8576 01:37:12.077172 == TX Byte 0 ==
8577 01:37:12.083656 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8578 01:37:12.086456 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8579 01:37:12.086919 == TX Byte 1 ==
8580 01:37:12.093070 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8581 01:37:12.096702 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8582 01:37:12.097155 ==
8583 01:37:12.099833 Dram Type= 6, Freq= 0, CH_1, rank 1
8584 01:37:12.103099 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8585 01:37:12.103560 ==
8586 01:37:12.117734
8587 01:37:12.121272 TX Vref early break, caculate TX vref
8588 01:37:12.124355 TX Vref=16, minBit 3, minWin=22, winSum=383
8589 01:37:12.127719 TX Vref=18, minBit 1, minWin=23, winSum=397
8590 01:37:12.130933 TX Vref=20, minBit 0, minWin=24, winSum=404
8591 01:37:12.134178 TX Vref=22, minBit 0, minWin=24, winSum=409
8592 01:37:12.137682 TX Vref=24, minBit 4, minWin=24, winSum=416
8593 01:37:12.144187 TX Vref=26, minBit 1, minWin=25, winSum=418
8594 01:37:12.147273 TX Vref=28, minBit 0, minWin=26, winSum=427
8595 01:37:12.150396 TX Vref=30, minBit 0, minWin=25, winSum=423
8596 01:37:12.153923 TX Vref=32, minBit 0, minWin=24, winSum=416
8597 01:37:12.157138 TX Vref=34, minBit 0, minWin=24, winSum=406
8598 01:37:12.160231 TX Vref=36, minBit 0, minWin=23, winSum=399
8599 01:37:12.167011 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8600 01:37:12.167572
8601 01:37:12.170415 Final TX Range 0 Vref 28
8602 01:37:12.171018
8603 01:37:12.171391 ==
8604 01:37:12.173858 Dram Type= 6, Freq= 0, CH_1, rank 1
8605 01:37:12.177246 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8606 01:37:12.177868 ==
8607 01:37:12.180346
8608 01:37:12.180913
8609 01:37:12.181417 TX Vref Scan disable
8610 01:37:12.186961 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8611 01:37:12.187520 == TX Byte 0 ==
8612 01:37:12.189997 u2DelayCellOfst[0]=18 cells (5 PI)
8613 01:37:12.193234 u2DelayCellOfst[1]=10 cells (3 PI)
8614 01:37:12.196616 u2DelayCellOfst[2]=0 cells (0 PI)
8615 01:37:12.199994 u2DelayCellOfst[3]=7 cells (2 PI)
8616 01:37:12.203197 u2DelayCellOfst[4]=10 cells (3 PI)
8617 01:37:12.206931 u2DelayCellOfst[5]=14 cells (4 PI)
8618 01:37:12.209687 u2DelayCellOfst[6]=18 cells (5 PI)
8619 01:37:12.213314 u2DelayCellOfst[7]=7 cells (2 PI)
8620 01:37:12.216668 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8621 01:37:12.219614 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8622 01:37:12.223318 == TX Byte 1 ==
8623 01:37:12.226758 u2DelayCellOfst[8]=0 cells (0 PI)
8624 01:37:12.229603 u2DelayCellOfst[9]=7 cells (2 PI)
8625 01:37:12.233040 u2DelayCellOfst[10]=7 cells (2 PI)
8626 01:37:12.236476 u2DelayCellOfst[11]=3 cells (1 PI)
8627 01:37:12.237030 u2DelayCellOfst[12]=14 cells (4 PI)
8628 01:37:12.239938 u2DelayCellOfst[13]=18 cells (5 PI)
8629 01:37:12.243094 u2DelayCellOfst[14]=18 cells (5 PI)
8630 01:37:12.246271 u2DelayCellOfst[15]=18 cells (5 PI)
8631 01:37:12.252778 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8632 01:37:12.256447 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8633 01:37:12.257040 DramC Write-DBI on
8634 01:37:12.259403 ==
8635 01:37:12.262713 Dram Type= 6, Freq= 0, CH_1, rank 1
8636 01:37:12.265961 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8637 01:37:12.266527 ==
8638 01:37:12.266890
8639 01:37:12.267220
8640 01:37:12.269646 TX Vref Scan disable
8641 01:37:12.270205 == TX Byte 0 ==
8642 01:37:12.276078 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8643 01:37:12.276635 == TX Byte 1 ==
8644 01:37:12.279274 Update DQM dly =714 (2 ,6, 10) DQM OEN =(3 ,3)
8645 01:37:12.282382 DramC Write-DBI off
8646 01:37:12.282942
8647 01:37:12.283307 [DATLAT]
8648 01:37:12.285583 Freq=1600, CH1 RK1
8649 01:37:12.286128
8650 01:37:12.286491 DATLAT Default: 0xe
8651 01:37:12.288924 0, 0xFFFF, sum = 0
8652 01:37:12.289435 1, 0xFFFF, sum = 0
8653 01:37:12.292382 2, 0xFFFF, sum = 0
8654 01:37:12.292841 3, 0xFFFF, sum = 0
8655 01:37:12.295680 4, 0xFFFF, sum = 0
8656 01:37:12.296144 5, 0xFFFF, sum = 0
8657 01:37:12.298857 6, 0xFFFF, sum = 0
8658 01:37:12.302251 7, 0xFFFF, sum = 0
8659 01:37:12.302718 8, 0xFFFF, sum = 0
8660 01:37:12.305380 9, 0xFFFF, sum = 0
8661 01:37:12.305846 10, 0xFFFF, sum = 0
8662 01:37:12.308695 11, 0xFFFF, sum = 0
8663 01:37:12.309158 12, 0xF7F, sum = 0
8664 01:37:12.311826 13, 0x0, sum = 1
8665 01:37:12.312287 14, 0x0, sum = 2
8666 01:37:12.315663 15, 0x0, sum = 3
8667 01:37:12.316226 16, 0x0, sum = 4
8668 01:37:12.316597 best_step = 14
8669 01:37:12.318589
8670 01:37:12.319041 ==
8671 01:37:12.322021 Dram Type= 6, Freq= 0, CH_1, rank 1
8672 01:37:12.325420 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8673 01:37:12.325984 ==
8674 01:37:12.326354 RX Vref Scan: 0
8675 01:37:12.326698
8676 01:37:12.328701 RX Vref 0 -> 0, step: 1
8677 01:37:12.329206
8678 01:37:12.331962 RX Delay 3 -> 252, step: 4
8679 01:37:12.334988 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8680 01:37:12.341681 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8681 01:37:12.345243 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8682 01:37:12.348490 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8683 01:37:12.351662 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8684 01:37:12.355197 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8685 01:37:12.361577 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8686 01:37:12.365267 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8687 01:37:12.368295 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8688 01:37:12.371706 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8689 01:37:12.375092 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8690 01:37:12.381924 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8691 01:37:12.385046 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8692 01:37:12.388360 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8693 01:37:12.391354 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8694 01:37:12.394959 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8695 01:37:12.398485 ==
8696 01:37:12.401529 Dram Type= 6, Freq= 0, CH_1, rank 1
8697 01:37:12.404706 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8698 01:37:12.405165 ==
8699 01:37:12.405565 DQS Delay:
8700 01:37:12.408028 DQS0 = 0, DQS1 = 0
8701 01:37:12.408482 DQM Delay:
8702 01:37:12.411616 DQM0 = 127, DQM1 = 122
8703 01:37:12.412177 DQ Delay:
8704 01:37:12.414497 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8705 01:37:12.418354 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =124
8706 01:37:12.421234 DQ8 =104, DQ9 =108, DQ10 =124, DQ11 =114
8707 01:37:12.424336 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8708 01:37:12.424792
8709 01:37:12.425147
8710 01:37:12.425557
8711 01:37:12.428013 [DramC_TX_OE_Calibration] TA2
8712 01:37:12.431096 Original DQ_B0 (3 6) =30, OEN = 27
8713 01:37:12.434265 Original DQ_B1 (3 6) =30, OEN = 27
8714 01:37:12.437865 24, 0x0, End_B0=24 End_B1=24
8715 01:37:12.440951 25, 0x0, End_B0=25 End_B1=25
8716 01:37:12.441465 26, 0x0, End_B0=26 End_B1=26
8717 01:37:12.444659 27, 0x0, End_B0=27 End_B1=27
8718 01:37:12.447509 28, 0x0, End_B0=28 End_B1=28
8719 01:37:12.450653 29, 0x0, End_B0=29 End_B1=29
8720 01:37:12.454058 30, 0x0, End_B0=30 End_B1=30
8721 01:37:12.457201 31, 0x4141, End_B0=30 End_B1=30
8722 01:37:12.457730 Byte0 end_step=30 best_step=27
8723 01:37:12.460831 Byte1 end_step=30 best_step=27
8724 01:37:12.464374 Byte0 TX OE(2T, 0.5T) = (3, 3)
8725 01:37:12.467490 Byte1 TX OE(2T, 0.5T) = (3, 3)
8726 01:37:12.468045
8727 01:37:12.468412
8728 01:37:12.473811 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8729 01:37:12.476972 CH1 RK1: MR19=303, MR18=1A1A
8730 01:37:12.484071 CH1_RK1: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
8731 01:37:12.486929 [RxdqsGatingPostProcess] freq 1600
8732 01:37:12.493906 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8733 01:37:12.497284 Pre-setting of DQS Precalculation
8734 01:37:12.500652 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8735 01:37:12.507065 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8736 01:37:12.517099 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8737 01:37:12.517703
8738 01:37:12.518076
8739 01:37:12.518435 [Calibration Summary] 3200 Mbps
8740 01:37:12.520304 CH 0, Rank 0
8741 01:37:12.520768 SW Impedance : PASS
8742 01:37:12.523531 DUTY Scan : NO K
8743 01:37:12.527009 ZQ Calibration : PASS
8744 01:37:12.527574 Jitter Meter : NO K
8745 01:37:12.530057 CBT Training : PASS
8746 01:37:12.533148 Write leveling : PASS
8747 01:37:12.533650 RX DQS gating : PASS
8748 01:37:12.536539 RX DQ/DQS(RDDQC) : PASS
8749 01:37:12.539934 TX DQ/DQS : PASS
8750 01:37:12.540400 RX DATLAT : PASS
8751 01:37:12.543125 RX DQ/DQS(Engine): PASS
8752 01:37:12.546684 TX OE : PASS
8753 01:37:12.547214 All Pass.
8754 01:37:12.547684
8755 01:37:12.548039 CH 0, Rank 1
8756 01:37:12.549746 SW Impedance : PASS
8757 01:37:12.553218 DUTY Scan : NO K
8758 01:37:12.553713 ZQ Calibration : PASS
8759 01:37:12.556428 Jitter Meter : NO K
8760 01:37:12.559929 CBT Training : PASS
8761 01:37:12.560497 Write leveling : PASS
8762 01:37:12.562968 RX DQS gating : PASS
8763 01:37:12.566389 RX DQ/DQS(RDDQC) : PASS
8764 01:37:12.566854 TX DQ/DQS : PASS
8765 01:37:12.570256 RX DATLAT : PASS
8766 01:37:12.573255 RX DQ/DQS(Engine): PASS
8767 01:37:12.573864 TX OE : PASS
8768 01:37:12.574239 All Pass.
8769 01:37:12.576712
8770 01:37:12.577275 CH 1, Rank 0
8771 01:37:12.579725 SW Impedance : PASS
8772 01:37:12.580287 DUTY Scan : NO K
8773 01:37:12.583021 ZQ Calibration : PASS
8774 01:37:12.586342 Jitter Meter : NO K
8775 01:37:12.586912 CBT Training : PASS
8776 01:37:12.589981 Write leveling : PASS
8777 01:37:12.590546 RX DQS gating : PASS
8778 01:37:12.592686 RX DQ/DQS(RDDQC) : PASS
8779 01:37:12.596645 TX DQ/DQS : PASS
8780 01:37:12.597269 RX DATLAT : PASS
8781 01:37:12.599417 RX DQ/DQS(Engine): PASS
8782 01:37:12.603001 TX OE : PASS
8783 01:37:12.603570 All Pass.
8784 01:37:12.603950
8785 01:37:12.604301 CH 1, Rank 1
8786 01:37:12.606381 SW Impedance : PASS
8787 01:37:12.609875 DUTY Scan : NO K
8788 01:37:12.610441 ZQ Calibration : PASS
8789 01:37:12.612601 Jitter Meter : NO K
8790 01:37:12.616226 CBT Training : PASS
8791 01:37:12.616796 Write leveling : PASS
8792 01:37:12.619444 RX DQS gating : PASS
8793 01:37:12.622725 RX DQ/DQS(RDDQC) : PASS
8794 01:37:12.623294 TX DQ/DQS : PASS
8795 01:37:12.625775 RX DATLAT : PASS
8796 01:37:12.629633 RX DQ/DQS(Engine): PASS
8797 01:37:12.630195 TX OE : PASS
8798 01:37:12.632681 All Pass.
8799 01:37:12.633250
8800 01:37:12.633682 DramC Write-DBI on
8801 01:37:12.636062 PER_BANK_REFRESH: Hybrid Mode
8802 01:37:12.636636 TX_TRACKING: ON
8803 01:37:12.645597 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8804 01:37:12.655914 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8805 01:37:12.661975 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8806 01:37:12.665773 [FAST_K] Save calibration result to emmc
8807 01:37:12.669025 sync common calibartion params.
8808 01:37:12.669637 sync cbt_mode0:0, 1:0
8809 01:37:12.672469 dram_init: ddr_geometry: 0
8810 01:37:12.675645 dram_init: ddr_geometry: 0
8811 01:37:12.676199 dram_init: ddr_geometry: 0
8812 01:37:12.678882 0:dram_rank_size:80000000
8813 01:37:12.682180 1:dram_rank_size:80000000
8814 01:37:12.685474 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8815 01:37:12.688931 DFS_SHUFFLE_HW_MODE: ON
8816 01:37:12.692447 dramc_set_vcore_voltage set vcore to 725000
8817 01:37:12.695534 Read voltage for 1600, 0
8818 01:37:12.696089 Vio18 = 0
8819 01:37:12.698977 Vcore = 725000
8820 01:37:12.699536 Vdram = 0
8821 01:37:12.699907 Vddq = 0
8822 01:37:12.701881 Vmddr = 0
8823 01:37:12.702344 switch to 3200 Mbps bootup
8824 01:37:12.705189 [DramcRunTimeConfig]
8825 01:37:12.706079 PHYPLL
8826 01:37:12.708417 DPM_CONTROL_AFTERK: ON
8827 01:37:12.708874 PER_BANK_REFRESH: ON
8828 01:37:12.711699 REFRESH_OVERHEAD_REDUCTION: ON
8829 01:37:12.714878 CMD_PICG_NEW_MODE: OFF
8830 01:37:12.715339 XRTWTW_NEW_MODE: ON
8831 01:37:12.718128 XRTRTR_NEW_MODE: ON
8832 01:37:12.718588 TX_TRACKING: ON
8833 01:37:12.721516 RDSEL_TRACKING: OFF
8834 01:37:12.724869 DQS Precalculation for DVFS: ON
8835 01:37:12.725686 RX_TRACKING: OFF
8836 01:37:12.728377 HW_GATING DBG: ON
8837 01:37:12.728837 ZQCS_ENABLE_LP4: ON
8838 01:37:12.731842 RX_PICG_NEW_MODE: ON
8839 01:37:12.732398 TX_PICG_NEW_MODE: ON
8840 01:37:12.734716 ENABLE_RX_DCM_DPHY: ON
8841 01:37:12.738044 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8842 01:37:12.741484 DUMMY_READ_FOR_TRACKING: OFF
8843 01:37:12.741945 !!! SPM_CONTROL_AFTERK: OFF
8844 01:37:12.744885 !!! SPM could not control APHY
8845 01:37:12.747948 IMPEDANCE_TRACKING: ON
8846 01:37:12.748470 TEMP_SENSOR: ON
8847 01:37:12.751143 HW_SAVE_FOR_SR: OFF
8848 01:37:12.754564 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8849 01:37:12.757971 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8850 01:37:12.761109 Read ODT Tracking: ON
8851 01:37:12.761627 Refresh Rate DeBounce: ON
8852 01:37:12.764518 DFS_NO_QUEUE_FLUSH: ON
8853 01:37:12.767600 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8854 01:37:12.771599 ENABLE_DFS_RUNTIME_MRW: OFF
8855 01:37:12.772373 DDR_RESERVE_NEW_MODE: ON
8856 01:37:12.774534 MR_CBT_SWITCH_FREQ: ON
8857 01:37:12.777623 =========================
8858 01:37:12.795036 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8859 01:37:12.798155 dram_init: ddr_geometry: 0
8860 01:37:12.816428 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8861 01:37:12.819603 dram_init: dram init end (result: 0)
8862 01:37:12.826133 DRAM-K: Full calibration passed in 23421 msecs
8863 01:37:12.829682 MRC: failed to locate region type 0.
8864 01:37:12.830149 DRAM rank0 size:0x80000000,
8865 01:37:12.832664 DRAM rank1 size=0x80000000
8866 01:37:12.842616 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8867 01:37:12.849184 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8868 01:37:12.856194 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8869 01:37:12.862696 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8870 01:37:12.865884 DRAM rank0 size:0x80000000,
8871 01:37:12.869535 DRAM rank1 size=0x80000000
8872 01:37:12.870003 CBMEM:
8873 01:37:12.872337 IMD: root @ 0xfffff000 254 entries.
8874 01:37:12.875862 IMD: root @ 0xffffec00 62 entries.
8875 01:37:12.879052 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8876 01:37:12.882568 WARNING: RO_VPD is uninitialized or empty.
8877 01:37:12.888953 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8878 01:37:12.895711 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8879 01:37:12.908609 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8880 01:37:12.920250 BS: romstage times (exec / console): total (unknown) / 22963 ms
8881 01:37:12.920961
8882 01:37:12.921386
8883 01:37:12.930226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8884 01:37:12.933610 ARM64: Exception handlers installed.
8885 01:37:12.936417 ARM64: Testing exception
8886 01:37:12.940078 ARM64: Done test exception
8887 01:37:12.940639 Enumerating buses...
8888 01:37:12.943547 Show all devs... Before device enumeration.
8889 01:37:12.946333 Root Device: enabled 1
8890 01:37:12.949748 CPU_CLUSTER: 0: enabled 1
8891 01:37:12.950206 CPU: 00: enabled 1
8892 01:37:12.952929 Compare with tree...
8893 01:37:12.953415 Root Device: enabled 1
8894 01:37:12.956233 CPU_CLUSTER: 0: enabled 1
8895 01:37:12.959871 CPU: 00: enabled 1
8896 01:37:12.960425 Root Device scanning...
8897 01:37:12.962792 scan_static_bus for Root Device
8898 01:37:12.966310 CPU_CLUSTER: 0 enabled
8899 01:37:12.969671 scan_static_bus for Root Device done
8900 01:37:12.972902 scan_bus: bus Root Device finished in 8 msecs
8901 01:37:12.973573 done
8902 01:37:12.979578 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8903 01:37:12.982623 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8904 01:37:12.989469 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8905 01:37:12.992986 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8906 01:37:12.996113 Allocating resources...
8907 01:37:12.999715 Reading resources...
8908 01:37:13.002463 Root Device read_resources bus 0 link: 0
8909 01:37:13.005981 DRAM rank0 size:0x80000000,
8910 01:37:13.006641 DRAM rank1 size=0x80000000
8911 01:37:13.009214 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8912 01:37:13.012690 CPU: 00 missing read_resources
8913 01:37:13.019278 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8914 01:37:13.022332 Root Device read_resources bus 0 link: 0 done
8915 01:37:13.022796 Done reading resources.
8916 01:37:13.029095 Show resources in subtree (Root Device)...After reading.
8917 01:37:13.032593 Root Device child on link 0 CPU_CLUSTER: 0
8918 01:37:13.035720 CPU_CLUSTER: 0 child on link 0 CPU: 00
8919 01:37:13.045742 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8920 01:37:13.046304 CPU: 00
8921 01:37:13.048842 Root Device assign_resources, bus 0 link: 0
8922 01:37:13.052730 CPU_CLUSTER: 0 missing set_resources
8923 01:37:13.058821 Root Device assign_resources, bus 0 link: 0 done
8924 01:37:13.059364 Done setting resources.
8925 01:37:13.065550 Show resources in subtree (Root Device)...After assigning values.
8926 01:37:13.068842 Root Device child on link 0 CPU_CLUSTER: 0
8927 01:37:13.072046 CPU_CLUSTER: 0 child on link 0 CPU: 00
8928 01:37:13.081606 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8929 01:37:13.082160 CPU: 00
8930 01:37:13.085129 Done allocating resources.
8931 01:37:13.091779 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8932 01:37:13.092416 Enabling resources...
8933 01:37:13.092797 done.
8934 01:37:13.098441 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8935 01:37:13.101367 Initializing devices...
8936 01:37:13.101833 Root Device init
8937 01:37:13.104871 init hardware done!
8938 01:37:13.105363 0x00000018: ctrlr->caps
8939 01:37:13.108284 52.000 MHz: ctrlr->f_max
8940 01:37:13.111596 0.400 MHz: ctrlr->f_min
8941 01:37:13.112164 0x40ff8080: ctrlr->voltages
8942 01:37:13.114831 sclk: 390625
8943 01:37:13.115314 Bus Width = 1
8944 01:37:13.115674 sclk: 390625
8945 01:37:13.118215 Bus Width = 1
8946 01:37:13.118679 Early init status = 3
8947 01:37:13.124665 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8948 01:37:13.128280 in-header: 03 fc 00 00 01 00 00 00
8949 01:37:13.131636 in-data: 00
8950 01:37:13.134638 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8951 01:37:13.139058 in-header: 03 fd 00 00 00 00 00 00
8952 01:37:13.142208 in-data:
8953 01:37:13.145482 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8954 01:37:13.150008 in-header: 03 fc 00 00 01 00 00 00
8955 01:37:13.153021 in-data: 00
8956 01:37:13.156786 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8957 01:37:13.162002 in-header: 03 fd 00 00 00 00 00 00
8958 01:37:13.165323 in-data:
8959 01:37:13.168865 [SSUSB] Setting up USB HOST controller...
8960 01:37:13.172025 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8961 01:37:13.175446 [SSUSB] phy power-on done.
8962 01:37:13.178391 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8963 01:37:13.185341 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8964 01:37:13.188543 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8965 01:37:13.195269 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8966 01:37:13.201787 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8967 01:37:13.208475 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8968 01:37:13.214819 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8969 01:37:13.221610 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
8970 01:37:13.224804 SPM: binary array size = 0x9dc
8971 01:37:13.228367 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8972 01:37:13.235179 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8973 01:37:13.241346 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8974 01:37:13.248139 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8975 01:37:13.251296 configure_display: Starting display init
8976 01:37:13.285527 anx7625_power_on_init: Init interface.
8977 01:37:13.288899 anx7625_disable_pd_protocol: Disabled PD feature.
8978 01:37:13.291973 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8979 01:37:13.319935 anx7625_start_dp_work: Secure OCM version=00
8980 01:37:13.323075 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8981 01:37:13.337868 sp_tx_get_edid_block: EDID Block = 1
8982 01:37:13.440282 Extracted contents:
8983 01:37:13.443563 header: 00 ff ff ff ff ff ff 00
8984 01:37:13.447196 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8985 01:37:13.450193 version: 01 04
8986 01:37:13.453655 basic params: 95 1f 11 78 0a
8987 01:37:13.456948 chroma info: 76 90 94 55 54 90 27 21 50 54
8988 01:37:13.460023 established: 00 00 00
8989 01:37:13.466608 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8990 01:37:13.473080 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8991 01:37:13.476823 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8992 01:37:13.483167 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8993 01:37:13.489733 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8994 01:37:13.493061 extensions: 00
8995 01:37:13.493671 checksum: fb
8996 01:37:13.494046
8997 01:37:13.499639 Manufacturer: IVO Model 57d Serial Number 0
8998 01:37:13.500192 Made week 0 of 2020
8999 01:37:13.502864 EDID version: 1.4
9000 01:37:13.503428 Digital display
9001 01:37:13.506244 6 bits per primary color channel
9002 01:37:13.509251 DisplayPort interface
9003 01:37:13.509783 Maximum image size: 31 cm x 17 cm
9004 01:37:13.512753 Gamma: 220%
9005 01:37:13.513361 Check DPMS levels
9006 01:37:13.519286 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9007 01:37:13.522485 First detailed timing is preferred timing
9008 01:37:13.526016 Established timings supported:
9009 01:37:13.526593 Standard timings supported:
9010 01:37:13.529265 Detailed timings
9011 01:37:13.532502 Hex of detail: 383680a07038204018303c0035ae10000019
9012 01:37:13.539219 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9013 01:37:13.542315 0780 0798 07c8 0820 hborder 0
9014 01:37:13.545740 0438 043b 0447 0458 vborder 0
9015 01:37:13.548965 -hsync -vsync
9016 01:37:13.549567 Did detailed timing
9017 01:37:13.555753 Hex of detail: 000000000000000000000000000000000000
9018 01:37:13.558645 Manufacturer-specified data, tag 0
9019 01:37:13.562159 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9020 01:37:13.565449 ASCII string: InfoVision
9021 01:37:13.568754 Hex of detail: 000000fe00523134304e574635205248200a
9022 01:37:13.572013 ASCII string: R140NWF5 RH
9023 01:37:13.572566 Checksum
9024 01:37:13.575960 Checksum: 0xfb (valid)
9025 01:37:13.578635 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9026 01:37:13.582102 DSI data_rate: 832800000 bps
9027 01:37:13.588488 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9028 01:37:13.591905 anx7625_parse_edid: pixelclock(138800).
9029 01:37:13.595049 hactive(1920), hsync(48), hfp(24), hbp(88)
9030 01:37:13.598308 vactive(1080), vsync(12), vfp(3), vbp(17)
9031 01:37:13.601814 anx7625_dsi_config: config dsi.
9032 01:37:13.608312 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9033 01:37:13.622269 anx7625_dsi_config: success to config DSI
9034 01:37:13.625817 anx7625_dp_start: MIPI phy setup OK.
9035 01:37:13.628943 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9036 01:37:13.632060 mtk_ddp_mode_set invalid vrefresh 60
9037 01:37:13.635583 main_disp_path_setup
9038 01:37:13.636137 ovl_layer_smi_id_en
9039 01:37:13.638880 ovl_layer_smi_id_en
9040 01:37:13.639438 ccorr_config
9041 01:37:13.639802 aal_config
9042 01:37:13.641886 gamma_config
9043 01:37:13.642345 postmask_config
9044 01:37:13.645653 dither_config
9045 01:37:13.648890 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9046 01:37:13.655608 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9047 01:37:13.658921 Root Device init finished in 553 msecs
9048 01:37:13.662441 CPU_CLUSTER: 0 init
9049 01:37:13.668783 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9050 01:37:13.675525 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9051 01:37:13.676109 APU_MBOX 0x190000b0 = 0x10001
9052 01:37:13.678696 APU_MBOX 0x190001b0 = 0x10001
9053 01:37:13.681717 APU_MBOX 0x190005b0 = 0x10001
9054 01:37:13.685480 APU_MBOX 0x190006b0 = 0x10001
9055 01:37:13.691842 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9056 01:37:13.701419 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9057 01:37:13.713791 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9058 01:37:13.720558 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9059 01:37:13.731961 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9060 01:37:13.741172 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9061 01:37:13.744478 CPU_CLUSTER: 0 init finished in 81 msecs
9062 01:37:13.747836 Devices initialized
9063 01:37:13.750768 Show all devs... After init.
9064 01:37:13.751231 Root Device: enabled 1
9065 01:37:13.754387 CPU_CLUSTER: 0: enabled 1
9066 01:37:13.757582 CPU: 00: enabled 1
9067 01:37:13.761204 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9068 01:37:13.764297 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9069 01:37:13.767772 ELOG: NV offset 0x57f000 size 0x1000
9070 01:37:13.774284 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9071 01:37:13.781050 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9072 01:37:13.784108 ELOG: Event(17) added with size 13 at 2024-06-05 01:37:13 UTC
9073 01:37:13.787712 out: cmd=0x121: 03 db 21 01 00 00 00 00
9074 01:37:13.792292 in-header: 03 ef 00 00 2c 00 00 00
9075 01:37:13.805476 in-data: 74 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9076 01:37:13.812168 ELOG: Event(A1) added with size 10 at 2024-06-05 01:37:13 UTC
9077 01:37:13.818431 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9078 01:37:13.825212 ELOG: Event(A0) added with size 9 at 2024-06-05 01:37:13 UTC
9079 01:37:13.828506 elog_add_boot_reason: Logged dev mode boot
9080 01:37:13.831831 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9081 01:37:13.835077 Finalize devices...
9082 01:37:13.835667 Devices finalized
9083 01:37:13.841659 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9084 01:37:13.844843 Writing coreboot table at 0xffe64000
9085 01:37:13.848162 0. 000000000010a000-0000000000113fff: RAMSTAGE
9086 01:37:13.851231 1. 0000000040000000-00000000400fffff: RAM
9087 01:37:13.858062 2. 0000000040100000-000000004032afff: RAMSTAGE
9088 01:37:13.861400 3. 000000004032b000-00000000545fffff: RAM
9089 01:37:13.864447 4. 0000000054600000-000000005465ffff: BL31
9090 01:37:13.868157 5. 0000000054660000-00000000ffe63fff: RAM
9091 01:37:13.874520 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9092 01:37:13.877903 7. 0000000100000000-000000013fffffff: RAM
9093 01:37:13.881271 Passing 5 GPIOs to payload:
9094 01:37:13.884673 NAME | PORT | POLARITY | VALUE
9095 01:37:13.887874 EC in RW | 0x000000aa | low | undefined
9096 01:37:13.894485 EC interrupt | 0x00000005 | low | undefined
9097 01:37:13.897752 TPM interrupt | 0x000000ab | high | undefined
9098 01:37:13.904637 SD card detect | 0x00000011 | high | undefined
9099 01:37:13.907795 speaker enable | 0x00000093 | high | undefined
9100 01:37:13.910898 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9101 01:37:13.914545 in-header: 03 f8 00 00 02 00 00 00
9102 01:37:13.915064 in-data: 03 00
9103 01:37:13.917558 ADC[4]: Raw value=669695 ID=5
9104 01:37:13.920876 ADC[3]: Raw value=212549 ID=1
9105 01:37:13.923908 RAM Code: 0x51
9106 01:37:13.924566 ADC[6]: Raw value=74778 ID=0
9107 01:37:13.927289 ADC[5]: Raw value=211444 ID=1
9108 01:37:13.930799 SKU Code: 0x1
9109 01:37:13.933989 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c396
9110 01:37:13.937168 coreboot table: 964 bytes.
9111 01:37:13.940725 IMD ROOT 0. 0xfffff000 0x00001000
9112 01:37:13.943971 IMD SMALL 1. 0xffffe000 0x00001000
9113 01:37:13.947079 RO MCACHE 2. 0xffffc000 0x00001104
9114 01:37:13.950620 CONSOLE 3. 0xfff7c000 0x00080000
9115 01:37:13.953947 FMAP 4. 0xfff7b000 0x00000452
9116 01:37:13.957083 TIME STAMP 5. 0xfff7a000 0x00000910
9117 01:37:13.960582 VBOOT WORK 6. 0xfff66000 0x00014000
9118 01:37:13.963883 RAMOOPS 7. 0xffe66000 0x00100000
9119 01:37:13.966985 COREBOOT 8. 0xffe64000 0x00002000
9120 01:37:13.967463 IMD small region:
9121 01:37:13.970448 IMD ROOT 0. 0xffffec00 0x00000400
9122 01:37:13.973814 VPD 1. 0xffffeb80 0x0000006c
9123 01:37:13.977319 MMC STATUS 2. 0xffffeb60 0x00000004
9124 01:37:13.984108 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9125 01:37:13.987596 Probing TPM: done!
9126 01:37:13.990742 Connected to device vid:did:rid of 1ae0:0028:00
9127 01:37:14.001414 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9128 01:37:14.004082 Initialized TPM device CR50 revision 0
9129 01:37:14.007602 Checking cr50 for pending updates
9130 01:37:14.010977 Reading cr50 TPM mode
9131 01:37:14.019724 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9132 01:37:14.026304 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9133 01:37:14.066702 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9134 01:37:14.069499 Checking segment from ROM address 0x40100000
9135 01:37:14.073067 Checking segment from ROM address 0x4010001c
9136 01:37:14.079634 Loading segment from ROM address 0x40100000
9137 01:37:14.080113 code (compression=0)
9138 01:37:14.089810 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9139 01:37:14.096484 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9140 01:37:14.097052 it's not compressed!
9141 01:37:14.103295 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9142 01:37:14.106640 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9143 01:37:14.126665 Loading segment from ROM address 0x4010001c
9144 01:37:14.127289 Entry Point 0x80000000
9145 01:37:14.129842 Loaded segments
9146 01:37:14.133922 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9147 01:37:14.140152 Jumping to boot code at 0x80000000(0xffe64000)
9148 01:37:14.146596 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9149 01:37:14.153484 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9150 01:37:14.160978 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9151 01:37:14.164520 Checking segment from ROM address 0x40100000
9152 01:37:14.167900 Checking segment from ROM address 0x4010001c
9153 01:37:14.174543 Loading segment from ROM address 0x40100000
9154 01:37:14.175086 code (compression=1)
9155 01:37:14.181361 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9156 01:37:14.190970 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9157 01:37:14.191518 using LZMA
9158 01:37:14.199567 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9159 01:37:14.206150 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9160 01:37:14.209531 Loading segment from ROM address 0x4010001c
9161 01:37:14.210000 Entry Point 0x54601000
9162 01:37:14.212907 Loaded segments
9163 01:37:14.216106 NOTICE: MT8192 bl31_setup
9164 01:37:14.223309 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9165 01:37:14.226294 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9166 01:37:14.229633 WARNING: region 0:
9167 01:37:14.233236 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9168 01:37:14.233732 WARNING: region 1:
9169 01:37:14.239569 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9170 01:37:14.242932 WARNING: region 2:
9171 01:37:14.246152 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9172 01:37:14.249593 WARNING: region 3:
9173 01:37:14.253124 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9174 01:37:14.256903 WARNING: region 4:
9175 01:37:14.262891 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9176 01:37:14.263360 WARNING: region 5:
9177 01:37:14.266352 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9178 01:37:14.269654 WARNING: region 6:
9179 01:37:14.272893 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 01:37:14.276220 WARNING: region 7:
9181 01:37:14.279627 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9182 01:37:14.286108 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9183 01:37:14.289735 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9184 01:37:14.293004 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9185 01:37:14.299957 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9186 01:37:14.302846 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9187 01:37:14.306133 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9188 01:37:14.313268 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9189 01:37:14.315942 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9190 01:37:14.322763 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9191 01:37:14.326102 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9192 01:37:14.329593 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9193 01:37:14.336268 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9194 01:37:14.339721 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9195 01:37:14.343506 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9196 01:37:14.349785 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9197 01:37:14.353204 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9198 01:37:14.359814 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9199 01:37:14.363230 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9200 01:37:14.366082 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9201 01:37:14.373139 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9202 01:37:14.376341 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9203 01:37:14.379835 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9204 01:37:14.386701 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9205 01:37:14.389834 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9206 01:37:14.396273 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9207 01:37:14.399802 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9208 01:37:14.403011 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9209 01:37:14.409869 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9210 01:37:14.413136 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9211 01:37:14.419991 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9212 01:37:14.422990 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9213 01:37:14.426520 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9214 01:37:14.433121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9215 01:37:14.436544 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9216 01:37:14.439824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9217 01:37:14.443018 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9218 01:37:14.449660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9219 01:37:14.452983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9220 01:37:14.456164 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9221 01:37:14.459843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9222 01:37:14.466296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9223 01:37:14.469885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9224 01:37:14.472963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9225 01:37:14.476435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9226 01:37:14.483217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9227 01:37:14.486315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9228 01:37:14.489649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9229 01:37:14.492963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9230 01:37:14.499590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9231 01:37:14.503219 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9232 01:37:14.509900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9233 01:37:14.513352 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9234 01:37:14.516465 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9235 01:37:14.523268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9236 01:37:14.526625 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9237 01:37:14.533173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9238 01:37:14.536396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9239 01:37:14.542890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9240 01:37:14.546410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9241 01:37:14.549648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9242 01:37:14.556083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9243 01:37:14.559704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9244 01:37:14.566255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9245 01:37:14.569976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9246 01:37:14.576276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9247 01:37:14.579689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9248 01:37:14.586205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9249 01:37:14.589630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9250 01:37:14.593005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9251 01:37:14.599950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9252 01:37:14.602830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9253 01:37:14.609414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9254 01:37:14.612975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9255 01:37:14.619374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9256 01:37:14.622644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9257 01:37:14.625828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9258 01:37:14.632689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9259 01:37:14.636089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9260 01:37:14.642524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9261 01:37:14.645785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9262 01:37:14.652618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9263 01:37:14.655914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9264 01:37:14.662311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9265 01:37:14.665943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9266 01:37:14.669355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9267 01:37:14.675834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9268 01:37:14.679468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9269 01:37:14.685968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9270 01:37:14.689112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9271 01:37:14.695871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9272 01:37:14.699144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9273 01:37:14.702382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9274 01:37:14.709202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9275 01:37:14.712517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9276 01:37:14.718968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9277 01:37:14.722164 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9278 01:37:14.728747 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9279 01:37:14.732296 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9280 01:37:14.735647 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9281 01:37:14.739126 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9282 01:37:14.742242 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9283 01:37:14.748902 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9284 01:37:14.752463 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9285 01:37:14.759114 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9286 01:37:14.762196 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9287 01:37:14.765487 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9288 01:37:14.772324 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9289 01:37:14.775665 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9290 01:37:14.782406 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9291 01:37:14.785772 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9292 01:37:14.788726 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9293 01:37:14.795543 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9294 01:37:14.799011 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9295 01:37:14.805838 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9296 01:37:14.808606 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9297 01:37:14.811806 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9298 01:37:14.818728 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9299 01:37:14.822000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9300 01:37:14.825249 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9301 01:37:14.832152 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9302 01:37:14.835589 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9303 01:37:14.838549 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9304 01:37:14.841825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9305 01:37:14.848526 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9306 01:37:14.851915 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9307 01:37:14.855162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9308 01:37:14.861842 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9309 01:37:14.865246 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9310 01:37:14.871800 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9311 01:37:14.875047 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9312 01:37:14.878730 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9313 01:37:14.885456 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9314 01:37:14.888867 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9315 01:37:14.891888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9316 01:37:14.898574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9317 01:37:14.902014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9318 01:37:14.908748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9319 01:37:14.912307 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9320 01:37:14.915545 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9321 01:37:14.921845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9322 01:37:14.925358 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9323 01:37:14.931687 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9324 01:37:14.935032 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9325 01:37:14.938418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9326 01:37:14.945017 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9327 01:37:14.948889 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9328 01:37:14.954967 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9329 01:37:14.958264 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9330 01:37:14.961814 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9331 01:37:14.968410 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9332 01:37:14.971683 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9333 01:37:14.978194 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9334 01:37:14.981335 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9335 01:37:14.984886 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9336 01:37:14.991518 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9337 01:37:14.994707 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9338 01:37:15.001283 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9339 01:37:15.004784 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9340 01:37:15.007779 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9341 01:37:15.014586 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9342 01:37:15.017755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9343 01:37:15.024305 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9344 01:37:15.028193 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9345 01:37:15.030707 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9346 01:37:15.037694 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9347 01:37:15.040778 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9348 01:37:15.047552 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9349 01:37:15.050855 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9350 01:37:15.053967 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9351 01:37:15.060775 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9352 01:37:15.063902 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9353 01:37:15.070413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9354 01:37:15.073861 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9355 01:37:15.077012 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9356 01:37:15.083806 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9357 01:37:15.086728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9358 01:37:15.093490 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9359 01:37:15.097003 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9360 01:37:15.100174 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9361 01:37:15.106735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9362 01:37:15.110195 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9363 01:37:15.116820 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9364 01:37:15.120319 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9365 01:37:15.123316 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9366 01:37:15.129829 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9367 01:37:15.133549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9368 01:37:15.139709 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9369 01:37:15.142795 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9370 01:37:15.146180 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9371 01:37:15.153080 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9372 01:37:15.156178 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9373 01:37:15.162740 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9374 01:37:15.166228 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9375 01:37:15.169369 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9376 01:37:15.176248 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9377 01:37:15.179345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9378 01:37:15.186240 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9379 01:37:15.189509 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9380 01:37:15.195641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9381 01:37:15.199360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9382 01:37:15.202868 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9383 01:37:15.208983 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9384 01:37:15.212645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9385 01:37:15.218888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9386 01:37:15.222055 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9387 01:37:15.228441 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9388 01:37:15.232234 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9389 01:37:15.238565 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9390 01:37:15.241827 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9391 01:37:15.245092 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9392 01:37:15.251889 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9393 01:37:15.255161 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9394 01:37:15.261912 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9395 01:37:15.265010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9396 01:37:15.268354 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9397 01:37:15.275046 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9398 01:37:15.278135 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9399 01:37:15.284975 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9400 01:37:15.288956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9401 01:37:15.295037 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9402 01:37:15.298101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9403 01:37:15.301547 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9404 01:37:15.308319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9405 01:37:15.311587 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9406 01:37:15.318166 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9407 01:37:15.321270 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9408 01:37:15.328127 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9409 01:37:15.331576 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9410 01:37:15.334151 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9411 01:37:15.341023 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9412 01:37:15.344298 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9413 01:37:15.347406 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9414 01:37:15.350725 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9415 01:37:15.354209 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9416 01:37:15.361031 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9417 01:37:15.364176 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9418 01:37:15.370884 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9419 01:37:15.374084 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9420 01:37:15.377470 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9421 01:37:15.383885 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9422 01:37:15.386994 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9423 01:37:15.393570 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9424 01:37:15.396755 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9425 01:37:15.400231 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9426 01:37:15.407006 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9427 01:37:15.410121 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9428 01:37:15.413403 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9429 01:37:15.419929 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9430 01:37:15.423518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9431 01:37:15.429954 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9432 01:37:15.433111 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9433 01:37:15.436370 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9434 01:37:15.442994 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9435 01:37:15.446221 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9436 01:37:15.449615 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9437 01:37:15.456422 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9438 01:37:15.459649 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9439 01:37:15.466279 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9440 01:37:15.469830 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9441 01:37:15.472810 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9442 01:37:15.479463 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9443 01:37:15.483015 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9444 01:37:15.486505 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9445 01:37:15.492608 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9446 01:37:15.495926 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9447 01:37:15.499681 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9448 01:37:15.505996 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9449 01:37:15.509751 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9450 01:37:15.516093 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9451 01:37:15.519003 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9452 01:37:15.522454 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9453 01:37:15.525752 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9454 01:37:15.529188 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9455 01:37:15.535572 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9456 01:37:15.539106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9457 01:37:15.542223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9458 01:37:15.545769 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9459 01:37:15.552471 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9460 01:37:15.556171 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9461 01:37:15.558881 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9462 01:37:15.565747 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9463 01:37:15.569077 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9464 01:37:15.572225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9465 01:37:15.578625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9466 01:37:15.582034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9467 01:37:15.588828 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9468 01:37:15.592075 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9469 01:37:15.595547 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9470 01:37:15.602048 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9471 01:37:15.605228 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9472 01:37:15.611834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9473 01:37:15.615215 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9474 01:37:15.621425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9475 01:37:15.624968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9476 01:37:15.628083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9477 01:37:15.634563 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9478 01:37:15.638057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9479 01:37:15.644670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9480 01:37:15.647972 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9481 01:37:15.650972 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9482 01:37:15.657536 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9483 01:37:15.661027 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9484 01:37:15.667565 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9485 01:37:15.671093 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9486 01:37:15.677619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9487 01:37:15.680460 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9488 01:37:15.683880 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9489 01:37:15.690532 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9490 01:37:15.693828 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9491 01:37:15.700694 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9492 01:37:15.703690 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9493 01:37:15.710556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9494 01:37:15.713586 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9495 01:37:15.717196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9496 01:37:15.723230 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9497 01:37:15.726859 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9498 01:37:15.733736 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9499 01:37:15.736995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9500 01:37:15.740157 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9501 01:37:15.746657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9502 01:37:15.749987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9503 01:37:15.757003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9504 01:37:15.760033 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9505 01:37:15.762982 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9506 01:37:15.769846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9507 01:37:15.773617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9508 01:37:15.779643 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9509 01:37:15.783167 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9510 01:37:15.789570 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9511 01:37:15.792929 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9512 01:37:15.796282 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9513 01:37:15.802888 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9514 01:37:15.806431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9515 01:37:15.812637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9516 01:37:15.816119 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9517 01:37:15.822786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9518 01:37:15.825815 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9519 01:37:15.829462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9520 01:37:15.836020 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9521 01:37:15.838903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9522 01:37:15.845709 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9523 01:37:15.848993 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9524 01:37:15.852106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9525 01:37:15.858659 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9526 01:37:15.862076 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9527 01:37:15.868686 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9528 01:37:15.871774 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9529 01:37:15.875189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9530 01:37:15.881921 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9531 01:37:15.885129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9532 01:37:15.891866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9533 01:37:15.895331 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9534 01:37:15.901643 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9535 01:37:15.904925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9536 01:37:15.908071 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9537 01:37:15.914879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9538 01:37:15.918082 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9539 01:37:15.924744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9540 01:37:15.927965 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9541 01:37:15.935039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9542 01:37:15.937996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9543 01:37:15.941325 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9544 01:37:15.948361 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9545 01:37:15.951407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9546 01:37:15.957738 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9547 01:37:15.961410 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9548 01:37:15.967822 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9549 01:37:15.971106 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9550 01:37:15.977679 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9551 01:37:15.981270 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9552 01:37:15.984401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9553 01:37:15.990925 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9554 01:37:15.994271 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9555 01:37:16.001036 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9556 01:37:16.004017 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9557 01:37:16.010627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9558 01:37:16.014131 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9559 01:37:16.020904 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9560 01:37:16.023709 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9561 01:37:16.027025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9562 01:37:16.033796 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9563 01:37:16.037617 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9564 01:37:16.043629 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9565 01:37:16.047024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9566 01:37:16.053715 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9567 01:37:16.056946 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9568 01:37:16.063676 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9569 01:37:16.067329 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9570 01:37:16.070288 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9571 01:37:16.077224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9572 01:37:16.080175 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9573 01:37:16.086793 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9574 01:37:16.090153 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9575 01:37:16.097052 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9576 01:37:16.100085 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9577 01:37:16.106513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9578 01:37:16.109603 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9579 01:37:16.113156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9580 01:37:16.119684 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9581 01:37:16.122917 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9582 01:37:16.129722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9583 01:37:16.133153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9584 01:37:16.139557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9585 01:37:16.142600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9586 01:37:16.146099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9587 01:37:16.152813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9588 01:37:16.155844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9589 01:37:16.162619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9590 01:37:16.165850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9591 01:37:16.172604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9592 01:37:16.175564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9593 01:37:16.182688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9594 01:37:16.185746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9595 01:37:16.192588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9596 01:37:16.195840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9597 01:37:16.202318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9598 01:37:16.205261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9599 01:37:16.212072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9600 01:37:16.215401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9601 01:37:16.222150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9602 01:37:16.225241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9603 01:37:16.231960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9604 01:37:16.235080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9605 01:37:16.241872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9606 01:37:16.244788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9607 01:37:16.251793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9608 01:37:16.254802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9609 01:37:16.261682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9610 01:37:16.264870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9611 01:37:16.271213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9612 01:37:16.274914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9613 01:37:16.281264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9614 01:37:16.284533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9615 01:37:16.291210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9616 01:37:16.294162 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9617 01:37:16.297552 INFO: [APUAPC] vio 0
9618 01:37:16.300929 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9619 01:37:16.307894 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9620 01:37:16.310855 INFO: [APUAPC] D0_APC_0: 0x400510
9621 01:37:16.314509 INFO: [APUAPC] D0_APC_1: 0x0
9622 01:37:16.317896 INFO: [APUAPC] D0_APC_2: 0x1540
9623 01:37:16.318521 INFO: [APUAPC] D0_APC_3: 0x0
9624 01:37:16.320826 INFO: [APUAPC] D1_APC_0: 0xffffffff
9625 01:37:16.327424 INFO: [APUAPC] D1_APC_1: 0xffffffff
9626 01:37:16.330930 INFO: [APUAPC] D1_APC_2: 0x3fffff
9627 01:37:16.331493 INFO: [APUAPC] D1_APC_3: 0x0
9628 01:37:16.334121 INFO: [APUAPC] D2_APC_0: 0xffffffff
9629 01:37:16.337438 INFO: [APUAPC] D2_APC_1: 0xffffffff
9630 01:37:16.340629 INFO: [APUAPC] D2_APC_2: 0x3fffff
9631 01:37:16.343788 INFO: [APUAPC] D2_APC_3: 0x0
9632 01:37:16.347176 INFO: [APUAPC] D3_APC_0: 0xffffffff
9633 01:37:16.350791 INFO: [APUAPC] D3_APC_1: 0xffffffff
9634 01:37:16.353865 INFO: [APUAPC] D3_APC_2: 0x3fffff
9635 01:37:16.356857 INFO: [APUAPC] D3_APC_3: 0x0
9636 01:37:16.360470 INFO: [APUAPC] D4_APC_0: 0xffffffff
9637 01:37:16.363859 INFO: [APUAPC] D4_APC_1: 0xffffffff
9638 01:37:16.366808 INFO: [APUAPC] D4_APC_2: 0x3fffff
9639 01:37:16.370504 INFO: [APUAPC] D4_APC_3: 0x0
9640 01:37:16.373916 INFO: [APUAPC] D5_APC_0: 0xffffffff
9641 01:37:16.376960 INFO: [APUAPC] D5_APC_1: 0xffffffff
9642 01:37:16.380268 INFO: [APUAPC] D5_APC_2: 0x3fffff
9643 01:37:16.383532 INFO: [APUAPC] D5_APC_3: 0x0
9644 01:37:16.386748 INFO: [APUAPC] D6_APC_0: 0xffffffff
9645 01:37:16.390209 INFO: [APUAPC] D6_APC_1: 0xffffffff
9646 01:37:16.393558 INFO: [APUAPC] D6_APC_2: 0x3fffff
9647 01:37:16.396728 INFO: [APUAPC] D6_APC_3: 0x0
9648 01:37:16.400331 INFO: [APUAPC] D7_APC_0: 0xffffffff
9649 01:37:16.403550 INFO: [APUAPC] D7_APC_1: 0xffffffff
9650 01:37:16.406671 INFO: [APUAPC] D7_APC_2: 0x3fffff
9651 01:37:16.409952 INFO: [APUAPC] D7_APC_3: 0x0
9652 01:37:16.413629 INFO: [APUAPC] D8_APC_0: 0xffffffff
9653 01:37:16.416908 INFO: [APUAPC] D8_APC_1: 0xffffffff
9654 01:37:16.419953 INFO: [APUAPC] D8_APC_2: 0x3fffff
9655 01:37:16.423292 INFO: [APUAPC] D8_APC_3: 0x0
9656 01:37:16.426636 INFO: [APUAPC] D9_APC_0: 0xffffffff
9657 01:37:16.429863 INFO: [APUAPC] D9_APC_1: 0xffffffff
9658 01:37:16.432971 INFO: [APUAPC] D9_APC_2: 0x3fffff
9659 01:37:16.436472 INFO: [APUAPC] D9_APC_3: 0x0
9660 01:37:16.439705 INFO: [APUAPC] D10_APC_0: 0xffffffff
9661 01:37:16.443333 INFO: [APUAPC] D10_APC_1: 0xffffffff
9662 01:37:16.446300 INFO: [APUAPC] D10_APC_2: 0x3fffff
9663 01:37:16.449706 INFO: [APUAPC] D10_APC_3: 0x0
9664 01:37:16.453071 INFO: [APUAPC] D11_APC_0: 0xffffffff
9665 01:37:16.456411 INFO: [APUAPC] D11_APC_1: 0xffffffff
9666 01:37:16.459394 INFO: [APUAPC] D11_APC_2: 0x3fffff
9667 01:37:16.462613 INFO: [APUAPC] D11_APC_3: 0x0
9668 01:37:16.465835 INFO: [APUAPC] D12_APC_0: 0xffffffff
9669 01:37:16.469176 INFO: [APUAPC] D12_APC_1: 0xffffffff
9670 01:37:16.473122 INFO: [APUAPC] D12_APC_2: 0x3fffff
9671 01:37:16.475960 INFO: [APUAPC] D12_APC_3: 0x0
9672 01:37:16.479572 INFO: [APUAPC] D13_APC_0: 0xffffffff
9673 01:37:16.482573 INFO: [APUAPC] D13_APC_1: 0xffffffff
9674 01:37:16.485907 INFO: [APUAPC] D13_APC_2: 0x3fffff
9675 01:37:16.489260 INFO: [APUAPC] D13_APC_3: 0x0
9676 01:37:16.492090 INFO: [APUAPC] D14_APC_0: 0xffffffff
9677 01:37:16.495940 INFO: [APUAPC] D14_APC_1: 0xffffffff
9678 01:37:16.499039 INFO: [APUAPC] D14_APC_2: 0x3fffff
9679 01:37:16.502397 INFO: [APUAPC] D14_APC_3: 0x0
9680 01:37:16.505364 INFO: [APUAPC] D15_APC_0: 0xffffffff
9681 01:37:16.508897 INFO: [APUAPC] D15_APC_1: 0xffffffff
9682 01:37:16.512364 INFO: [APUAPC] D15_APC_2: 0x3fffff
9683 01:37:16.515490 INFO: [APUAPC] D15_APC_3: 0x0
9684 01:37:16.518818 INFO: [APUAPC] APC_CON: 0x4
9685 01:37:16.521815 INFO: [NOCDAPC] D0_APC_0: 0x0
9686 01:37:16.525424 INFO: [NOCDAPC] D0_APC_1: 0x0
9687 01:37:16.528561 INFO: [NOCDAPC] D1_APC_0: 0x0
9688 01:37:16.532105 INFO: [NOCDAPC] D1_APC_1: 0xfff
9689 01:37:16.535634 INFO: [NOCDAPC] D2_APC_0: 0x0
9690 01:37:16.536190 INFO: [NOCDAPC] D2_APC_1: 0xfff
9691 01:37:16.538631 INFO: [NOCDAPC] D3_APC_0: 0x0
9692 01:37:16.541726 INFO: [NOCDAPC] D3_APC_1: 0xfff
9693 01:37:16.545269 INFO: [NOCDAPC] D4_APC_0: 0x0
9694 01:37:16.548298 INFO: [NOCDAPC] D4_APC_1: 0xfff
9695 01:37:16.551606 INFO: [NOCDAPC] D5_APC_0: 0x0
9696 01:37:16.554987 INFO: [NOCDAPC] D5_APC_1: 0xfff
9697 01:37:16.558205 INFO: [NOCDAPC] D6_APC_0: 0x0
9698 01:37:16.561568 INFO: [NOCDAPC] D6_APC_1: 0xfff
9699 01:37:16.565070 INFO: [NOCDAPC] D7_APC_0: 0x0
9700 01:37:16.568257 INFO: [NOCDAPC] D7_APC_1: 0xfff
9701 01:37:16.568718 INFO: [NOCDAPC] D8_APC_0: 0x0
9702 01:37:16.571862 INFO: [NOCDAPC] D8_APC_1: 0xfff
9703 01:37:16.574826 INFO: [NOCDAPC] D9_APC_0: 0x0
9704 01:37:16.578243 INFO: [NOCDAPC] D9_APC_1: 0xfff
9705 01:37:16.581347 INFO: [NOCDAPC] D10_APC_0: 0x0
9706 01:37:16.584973 INFO: [NOCDAPC] D10_APC_1: 0xfff
9707 01:37:16.588311 INFO: [NOCDAPC] D11_APC_0: 0x0
9708 01:37:16.591488 INFO: [NOCDAPC] D11_APC_1: 0xfff
9709 01:37:16.595086 INFO: [NOCDAPC] D12_APC_0: 0x0
9710 01:37:16.598002 INFO: [NOCDAPC] D12_APC_1: 0xfff
9711 01:37:16.601172 INFO: [NOCDAPC] D13_APC_0: 0x0
9712 01:37:16.604344 INFO: [NOCDAPC] D13_APC_1: 0xfff
9713 01:37:16.608110 INFO: [NOCDAPC] D14_APC_0: 0x0
9714 01:37:16.611202 INFO: [NOCDAPC] D14_APC_1: 0xfff
9715 01:37:16.614430 INFO: [NOCDAPC] D15_APC_0: 0x0
9716 01:37:16.614889 INFO: [NOCDAPC] D15_APC_1: 0xfff
9717 01:37:16.618004 INFO: [NOCDAPC] APC_CON: 0x4
9718 01:37:16.621025 INFO: [APUAPC] set_apusys_apc done
9719 01:37:16.624718 INFO: [DEVAPC] devapc_init done
9720 01:37:16.631054 INFO: GICv3 without legacy support detected.
9721 01:37:16.634506 INFO: ARM GICv3 driver initialized in EL3
9722 01:37:16.637866 INFO: Maximum SPI INTID supported: 639
9723 01:37:16.640743 INFO: BL31: Initializing runtime services
9724 01:37:16.647624 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9725 01:37:16.650777 INFO: SPM: enable CPC mode
9726 01:37:16.654344 INFO: mcdi ready for mcusys-off-idle and system suspend
9727 01:37:16.660490 INFO: BL31: Preparing for EL3 exit to normal world
9728 01:37:16.663775 INFO: Entry point address = 0x80000000
9729 01:37:16.664232 INFO: SPSR = 0x8
9730 01:37:16.670958
9731 01:37:16.671407
9732 01:37:16.671764
9733 01:37:16.674449 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9734 01:37:16.674983 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9735 01:37:16.675416 Setting prompt string to ['asurada:']
9736 01:37:16.675836 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9737 01:37:16.676667 Starting depthcharge on Spherion...
9738 01:37:16.677116
9739 01:37:16.677532 Wipe memory regions:
9740 01:37:16.677890
9741 01:37:16.678276 [0x00000040000000, 0x00000054600000)
9742 01:37:16.800140
9743 01:37:16.800690 [0x00000054660000, 0x00000080000000)
9744 01:37:17.060645
9745 01:37:17.061198 [0x000000821a7280, 0x000000ffe64000)
9746 01:37:17.805411
9747 01:37:17.806275 [0x00000100000000, 0x00000140000000)
9748 01:37:18.186157
9749 01:37:18.189718 Initializing XHCI USB controller at 0x11200000.
9750 01:37:19.227490
9751 01:37:19.230468 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9752 01:37:19.231152
9753 01:37:19.231560
9754 01:37:19.232443 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9756 01:37:19.333756 asurada: tftpboot 192.168.201.1 14173528/tftp-deploy-9xqmsftx/kernel/image.itb 14173528/tftp-deploy-9xqmsftx/kernel/cmdline
9757 01:37:19.334412 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9758 01:37:19.334906 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9759 01:37:19.339471 tftpboot 192.168.201.1 14173528/tftp-deploy-9xqmsftx/kernel/image.ittp-deploy-9xqmsftx/kernel/cmdline
9760 01:37:19.339938
9761 01:37:19.340298 Waiting for link
9762 01:37:19.499905
9763 01:37:19.500506 R8152: Initializing
9764 01:37:19.501033
9765 01:37:19.503147 Version 9 (ocp_data = 6010)
9766 01:37:19.503702
9767 01:37:19.506080 R8152: Done initializing
9768 01:37:19.506533
9769 01:37:19.506890 Adding net device
9770 01:37:21.630258
9771 01:37:21.630912 done.
9772 01:37:21.631313
9773 01:37:21.631984 MAC: 00:e0:4c:68:03:bd
9774 01:37:21.632343
9775 01:37:21.633754 Sending DHCP discover... done.
9776 01:37:21.634300
9777 01:37:21.636808 Waiting for reply... done.
9778 01:37:21.636888
9779 01:37:21.639681 Sending DHCP request... done.
9780 01:37:21.639761
9781 01:37:21.643036 Waiting for reply... done.
9782 01:37:21.643121
9783 01:37:21.643188 My ip is 192.168.201.16
9784 01:37:21.643250
9785 01:37:21.646453 The DHCP server ip is 192.168.201.1
9786 01:37:21.646539
9787 01:37:21.653298 TFTP server IP predefined by user: 192.168.201.1
9788 01:37:21.653477
9789 01:37:21.659591 Bootfile predefined by user: 14173528/tftp-deploy-9xqmsftx/kernel/image.itb
9790 01:37:21.659707
9791 01:37:21.662763 Sending tftp read request... done.
9792 01:37:21.662882
9793 01:37:21.666720 Waiting for the transfer...
9794 01:37:21.666852
9795 01:37:22.047529 00000000 ################################################################
9796 01:37:22.048056
9797 01:37:22.365443 00080000 ################################################################
9798 01:37:22.365582
9799 01:37:22.649110 00100000 ################################################################
9800 01:37:22.649245
9801 01:37:22.923498 00180000 ################################################################
9802 01:37:22.923658
9803 01:37:23.174312 00200000 ################################################################
9804 01:37:23.174457
9805 01:37:23.441182 00280000 ################################################################
9806 01:37:23.441350
9807 01:37:23.714402 00300000 ################################################################
9808 01:37:23.714538
9809 01:37:23.965615 00380000 ################################################################
9810 01:37:23.965770
9811 01:37:24.218120 00400000 ################################################################
9812 01:37:24.218276
9813 01:37:24.473493 00480000 ################################################################
9814 01:37:24.473662
9815 01:37:24.724089 00500000 ################################################################
9816 01:37:24.724256
9817 01:37:25.005899 00580000 ################################################################
9818 01:37:25.006035
9819 01:37:25.330029 00600000 ################################################################
9820 01:37:25.330666
9821 01:37:25.717122 00680000 ################################################################
9822 01:37:25.717807
9823 01:37:26.070049 00700000 ################################################################
9824 01:37:26.070203
9825 01:37:26.412012 00780000 ################################################################
9826 01:37:26.412156
9827 01:37:26.710677 00800000 ################################################################
9828 01:37:26.710839
9829 01:37:27.002942 00880000 ################################################################
9830 01:37:27.003083
9831 01:37:27.288041 00900000 ################################################################
9832 01:37:27.288201
9833 01:37:27.548395 00980000 ################################################################
9834 01:37:27.548529
9835 01:37:27.804186 00a00000 ################################################################
9836 01:37:27.804333
9837 01:37:28.148759 00a80000 ################################################################
9838 01:37:28.149353
9839 01:37:28.536670 00b00000 ################################################################
9840 01:37:28.537187
9841 01:37:28.904883 00b80000 ################################################################
9842 01:37:28.905057
9843 01:37:29.203744 00c00000 ################################################################
9844 01:37:29.203879
9845 01:37:29.508242 00c80000 ################################################################
9846 01:37:29.508841
9847 01:37:29.894206 00d00000 ################################################################
9848 01:37:29.894815
9849 01:37:30.198324 00d80000 ################################################################
9850 01:37:30.198460
9851 01:37:30.497274 00e00000 ################################################################
9852 01:37:30.497466
9853 01:37:30.773551 00e80000 ################################################################
9854 01:37:30.773717
9855 01:37:31.074438 00f00000 ################################################################
9856 01:37:31.074601
9857 01:37:31.373457 00f80000 ################################################################
9858 01:37:31.373592
9859 01:37:31.674728 01000000 ################################################################
9860 01:37:31.674868
9861 01:37:31.969120 01080000 ################################################################
9862 01:37:31.969302
9863 01:37:32.266016 01100000 ################################################################
9864 01:37:32.266162
9865 01:37:32.553095 01180000 ################################################################
9866 01:37:32.553247
9867 01:37:32.851410 01200000 ################################################################
9868 01:37:32.851548
9869 01:37:33.140199 01280000 ################################################################
9870 01:37:33.140343
9871 01:37:33.412901 01300000 ################################################################
9872 01:37:33.413169
9873 01:37:33.808801 01380000 ################################################################
9874 01:37:33.809463
9875 01:37:34.225246 01400000 ################################################################
9876 01:37:34.225871
9877 01:37:34.603052 01480000 ################################################################
9878 01:37:34.603199
9879 01:37:34.896147 01500000 ################################################################
9880 01:37:34.896289
9881 01:37:35.197789 01580000 ################################################################
9882 01:37:35.197929
9883 01:37:35.498504 01600000 ################################################################
9884 01:37:35.498637
9885 01:37:35.776292 01680000 ################################################################
9886 01:37:35.776462
9887 01:37:36.026848 01700000 ################################################################
9888 01:37:36.026987
9889 01:37:36.324645 01780000 ################################################################
9890 01:37:36.324789
9891 01:37:36.622377 01800000 ################################################################
9892 01:37:36.622515
9893 01:37:36.915666 01880000 ################################################################
9894 01:37:36.915806
9895 01:37:37.213627 01900000 ################################################################
9896 01:37:37.213766
9897 01:37:37.604654 01980000 ################################################################
9898 01:37:37.605191
9899 01:37:38.001766 01a00000 ################################################################
9900 01:37:38.002309
9901 01:37:38.403726 01a80000 ################################################################
9902 01:37:38.404262
9903 01:37:38.702508 01b00000 ################################################################
9904 01:37:38.702648
9905 01:37:38.991856 01b80000 ################################################################
9906 01:37:38.991990
9907 01:37:39.272950 01c00000 ################################################################
9908 01:37:39.273083
9909 01:37:39.549443 01c80000 ################################################################
9910 01:37:39.549606
9911 01:37:39.847601 01d00000 ################################################################
9912 01:37:39.847762
9913 01:37:40.198053 01d80000 ################################################################
9914 01:37:40.198578
9915 01:37:40.521008 01e00000 ################################################################
9916 01:37:40.521144
9917 01:37:40.800650 01e80000 ################################################################
9918 01:37:40.800824
9919 01:37:41.053649 01f00000 ################################################################
9920 01:37:41.053813
9921 01:37:41.344692 01f80000 ################################################################
9922 01:37:41.344849
9923 01:37:41.643579 02000000 ################################################################
9924 01:37:41.643715
9925 01:37:41.935688 02080000 ################################################################
9926 01:37:41.935856
9927 01:37:42.225436 02100000 ################################################################
9928 01:37:42.225580
9929 01:37:42.514724 02180000 ################################################################
9930 01:37:42.514864
9931 01:37:42.811056 02200000 ################################################################
9932 01:37:42.811198
9933 01:37:43.087515 02280000 ################################################################
9934 01:37:43.087688
9935 01:37:43.336057 02300000 ################################################################
9936 01:37:43.336226
9937 01:37:43.631275 02380000 ################################################################
9938 01:37:43.631415
9939 01:37:44.021559 02400000 ################################################################
9940 01:37:44.022102
9941 01:37:44.394853 02480000 ################################################################
9942 01:37:44.394995
9943 01:37:44.710071 02500000 ################################################################
9944 01:37:44.710210
9945 01:37:45.005672 02580000 ################################################################
9946 01:37:45.005839
9947 01:37:45.305498 02600000 ################################################################
9948 01:37:45.305630
9949 01:37:45.608029 02680000 ################################################################
9950 01:37:45.608172
9951 01:37:45.890726 02700000 ################################################################
9952 01:37:45.890896
9953 01:37:46.170149 02780000 ################################################################
9954 01:37:46.170283
9955 01:37:46.456434 02800000 ################################################################
9956 01:37:46.456567
9957 01:37:46.757878 02880000 ################################################################
9958 01:37:46.758016
9959 01:37:47.052704 02900000 ################################################################
9960 01:37:47.052845
9961 01:37:47.353857 02980000 ################################################################
9962 01:37:47.353991
9963 01:37:47.654631 02a00000 ################################################################
9964 01:37:47.654774
9965 01:37:47.955520 02a80000 ################################################################
9966 01:37:47.955655
9967 01:37:48.249081 02b00000 ################################################################
9968 01:37:48.249256
9969 01:37:48.578151 02b80000 ################################################################
9970 01:37:48.578676
9971 01:37:48.965156 02c00000 ################################################################
9972 01:37:48.965371
9973 01:37:49.246075 02c80000 ################################################################
9974 01:37:49.246209
9975 01:37:49.523777 02d00000 ################################################################
9976 01:37:49.523941
9977 01:37:49.777453 02d80000 ################################################################
9978 01:37:49.777592
9979 01:37:50.027909 02e00000 ################################################################
9980 01:37:50.028074
9981 01:37:50.278597 02e80000 ################################################################
9982 01:37:50.278726
9983 01:37:50.529978 02f00000 ################################################################
9984 01:37:50.530119
9985 01:37:50.814207 02f80000 ################################################################
9986 01:37:50.814355
9987 01:37:51.111153 03000000 ################################################################
9988 01:37:51.111294
9989 01:37:51.408597 03080000 ################################################################
9990 01:37:51.408729
9991 01:37:51.698273 03100000 ################################################################
9992 01:37:51.698422
9993 01:37:51.953565 03180000 ################################################################
9994 01:37:51.953707
9995 01:37:52.221739 03200000 ################################################################
9996 01:37:52.221887
9997 01:37:52.498890 03280000 ################################################################
9998 01:37:52.499025
9999 01:37:52.768920 03300000 ################################################################
10000 01:37:52.769057
10001 01:37:53.058023 03380000 ################################################################
10002 01:37:53.058165
10003 01:37:53.349491 03400000 ################################################################
10004 01:37:53.349634
10005 01:37:53.629292 03480000 ################################################################
10006 01:37:53.629476
10007 01:37:53.909412 03500000 ################################################################
10008 01:37:53.909555
10009 01:37:54.189098 03580000 ################################################################
10010 01:37:54.189262
10011 01:37:54.467828 03600000 ################################################################
10012 01:37:54.467972
10013 01:37:54.749940 03680000 ################################################################
10014 01:37:54.750082
10015 01:37:55.051691 03700000 ################################################################
10016 01:37:55.051837
10017 01:37:55.347666 03780000 ################################################################
10018 01:37:55.347826
10019 01:37:55.637975 03800000 ################################################################
10020 01:37:55.638110
10021 01:37:55.908857 03880000 ################################################################
10022 01:37:55.909024
10023 01:37:56.200358 03900000 ################################################################
10024 01:37:56.200694
10025 01:37:56.600741 03980000 ################################################################
10026 01:37:56.601420
10027 01:37:56.988319 03a00000 ################################################################
10028 01:37:56.988864
10029 01:37:57.356555 03a80000 ################################################################
10030 01:37:57.357100
10031 01:37:57.753354 03b00000 ################################################################
10032 01:37:57.753956
10033 01:37:58.140274 03b80000 ################################################################
10034 01:37:58.140914
10035 01:37:58.512646 03c00000 ################################################################
10036 01:37:58.513168
10037 01:37:58.828942 03c80000 ################################################################
10038 01:37:58.829106
10039 01:37:59.143069 03d00000 ################################################################
10040 01:37:59.143614
10041 01:37:59.520139 03d80000 ################################################################
10042 01:37:59.520301
10043 01:37:59.646951 03e00000 ############################## done.
10044 01:37:59.647082
10045 01:37:59.650097 The bootfile was 65250490 bytes long.
10046 01:37:59.650187
10047 01:37:59.653505 Sending tftp read request... done.
10048 01:37:59.653601
10049 01:37:59.656805 Waiting for the transfer...
10050 01:37:59.656908
10051 01:37:59.656988 00000000 # done.
10052 01:37:59.657066
10053 01:37:59.667100 Command line loaded dynamically from TFTP file: 14173528/tftp-deploy-9xqmsftx/kernel/cmdline
10054 01:37:59.667296
10055 01:37:59.680217 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10056 01:37:59.680455
10057 01:37:59.680586 Loading FIT.
10058 01:37:59.680704
10059 01:37:59.683636 Image ramdisk-1 has 52141278 bytes.
10060 01:37:59.683890
10061 01:37:59.686875 Image fdt-1 has 47258 bytes.
10062 01:37:59.687160
10063 01:37:59.690132 Image kernel-1 has 13059919 bytes.
10064 01:37:59.690433
10065 01:37:59.696963 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10066 01:37:59.697386
10067 01:37:59.717066 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10068 01:37:59.717686
10069 01:37:59.719985 Choosing best match conf-1 for compat google,spherion-rev3.
10070 01:37:59.725133
10071 01:37:59.729650 Connected to device vid:did:rid of 1ae0:0028:00
10072 01:37:59.736909
10073 01:37:59.739935 tpm_get_response: command 0x17b, return code 0x0
10074 01:37:59.740406
10075 01:37:59.743297 ec_init: CrosEC protocol v3 supported (256, 248)
10076 01:37:59.748184
10077 01:37:59.750998 tpm_cleanup: add release locality here.
10078 01:37:59.751469
10079 01:37:59.751869 Shutting down all USB controllers.
10080 01:37:59.754631
10081 01:37:59.755129 Removing current net device
10082 01:37:59.755504
10083 01:37:59.761017 Exiting depthcharge with code 4 at timestamp: 71317517
10084 01:37:59.761606
10085 01:37:59.764298 LZMA decompressing kernel-1 to 0x821a6718
10086 01:37:59.764879
10087 01:37:59.767546 LZMA decompressing kernel-1 to 0x40000000
10088 01:38:01.375872
10089 01:38:01.376428 jumping to kernel
10090 01:38:01.378678 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10091 01:38:01.379214 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10092 01:38:01.379634 Setting prompt string to ['Linux version [0-9]']
10093 01:38:01.380023 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 01:38:01.380406 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10095 01:38:01.426272
10096 01:38:01.429968 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10097 01:38:01.433689 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10098 01:38:01.434288 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10099 01:38:01.434696 Setting prompt string to []
10100 01:38:01.435118 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10101 01:38:01.435524 Using line separator: #'\n'#
10102 01:38:01.435857 No login prompt set.
10103 01:38:01.436188 Parsing kernel messages
10104 01:38:01.436498 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10105 01:38:01.437047 [login-action] Waiting for messages, (timeout 00:03:42)
10106 01:38:01.437450 Waiting using forced prompt support (timeout 00:01:51)
10107 01:38:01.452519 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10108 01:38:01.455638 [ 0.000000] random: crng init done
10109 01:38:01.462192 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10110 01:38:01.465472 [ 0.000000] efi: UEFI not found.
10111 01:38:01.472452 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10112 01:38:01.482313 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10113 01:38:01.492257 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10114 01:38:01.498795 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10115 01:38:01.505431 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10116 01:38:01.511908 [ 0.000000] printk: bootconsole [mtk8250] enabled
10117 01:38:01.518328 [ 0.000000] NUMA: No NUMA configuration found
10118 01:38:01.524888 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10119 01:38:01.531368 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10120 01:38:01.531912 [ 0.000000] Zone ranges:
10121 01:38:01.538145 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10122 01:38:01.541663 [ 0.000000] DMA32 empty
10123 01:38:01.548160 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10124 01:38:01.551637 [ 0.000000] Movable zone start for each node
10125 01:38:01.554959 [ 0.000000] Early memory node ranges
10126 01:38:01.561666 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10127 01:38:01.568046 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10128 01:38:01.574636 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10129 01:38:01.581411 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10130 01:38:01.587615 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10131 01:38:01.594253 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10132 01:38:01.625474 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10133 01:38:01.631895 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10134 01:38:01.638622 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10135 01:38:01.641905 [ 0.000000] psci: probing for conduit method from DT.
10136 01:38:01.648507 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10137 01:38:01.651731 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10138 01:38:01.658466 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10139 01:38:01.661850 [ 0.000000] psci: SMC Calling Convention v1.2
10140 01:38:01.668284 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10141 01:38:01.671722 [ 0.000000] Detected VIPT I-cache on CPU0
10142 01:38:01.678042 [ 0.000000] CPU features: detected: GIC system register CPU interface
10143 01:38:01.684626 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10144 01:38:01.691250 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10145 01:38:01.697975 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10146 01:38:01.708111 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10147 01:38:01.714582 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10148 01:38:01.717406 [ 0.000000] alternatives: applying boot alternatives
10149 01:38:01.724307 [ 0.000000] Fallback order for Node 0: 0
10150 01:38:01.730725 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10151 01:38:01.733857 [ 0.000000] Policy zone: Normal
10152 01:38:01.747179 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10153 01:38:01.757443 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10154 01:38:01.767128 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10155 01:38:01.777043 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10156 01:38:01.783954 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10157 01:38:01.787115 <6>[ 0.000000] software IO TLB: area num 8.
10158 01:38:01.842684 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10159 01:38:01.923885 <6>[ 0.000000] Memory: 3798856K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 359608K reserved, 32768K cma-reserved)
10160 01:38:01.930337 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10161 01:38:01.937032 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10162 01:38:01.940540 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10163 01:38:01.946683 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10164 01:38:01.953358 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10165 01:38:01.956624 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10166 01:38:01.966741 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10167 01:38:01.973266 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10168 01:38:01.980002 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10169 01:38:01.986339 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10170 01:38:01.989771 <6>[ 0.000000] GICv3: 608 SPIs implemented
10171 01:38:01.993103 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10172 01:38:01.999695 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10173 01:38:02.003104 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10174 01:38:02.009405 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10175 01:38:02.022790 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10176 01:38:02.035689 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10177 01:38:02.042464 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10178 01:38:02.050313 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10179 01:38:02.063445 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10180 01:38:02.069928 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10181 01:38:02.077179 <6>[ 0.009223] Console: colour dummy device 80x25
10182 01:38:02.086683 <6>[ 0.013945] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10183 01:38:02.093410 <6>[ 0.024451] pid_max: default: 32768 minimum: 301
10184 01:38:02.096657 <6>[ 0.029323] LSM: Security Framework initializing
10185 01:38:02.103368 <6>[ 0.034267] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10186 01:38:02.113088 <6>[ 0.041873] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10187 01:38:02.119623 <6>[ 0.051093] cblist_init_generic: Setting adjustable number of callback queues.
10188 01:38:02.126537 <6>[ 0.058584] cblist_init_generic: Setting shift to 3 and lim to 1.
10189 01:38:02.136335 <6>[ 0.064919] cblist_init_generic: Setting adjustable number of callback queues.
10190 01:38:02.143330 <6>[ 0.072392] cblist_init_generic: Setting shift to 3 and lim to 1.
10191 01:38:02.146045 <6>[ 0.078831] rcu: Hierarchical SRCU implementation.
10192 01:38:02.152685 <6>[ 0.078833] rcu: Max phase no-delay instances is 1000.
10193 01:38:02.159230 <6>[ 0.078856] printk: bootconsole [mtk8250] printing thread started
10194 01:38:02.165600 <6>[ 0.097184] EFI services will not be available.
10195 01:38:02.168911 <6>[ 0.097384] smp: Bringing up secondary CPUs ...
10196 01:38:02.175580 <6>[ 0.097691] Detected VIPT I-cache on CPU1
10197 01:38:02.182342 <6>[ 0.097758] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10198 01:38:02.188929 <6>[ 0.097787] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10199 01:38:02.198163 <6>[ 0.125636] Detected VIPT I-cache on CPU2
10200 01:38:02.204955 <6>[ 0.125687] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10201 01:38:02.211355 <6>[ 0.125704] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10202 01:38:02.218066 <6>[ 0.125961] Detected VIPT I-cache on CPU3
10203 01:38:02.224981 <6>[ 0.126009] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10204 01:38:02.231615 <6>[ 0.126023] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10205 01:38:02.234440 <6>[ 0.126330] CPU features: detected: Spectre-v4
10206 01:38:02.241143 <6>[ 0.126336] CPU features: detected: Spectre-BHB
10207 01:38:02.244172 <6>[ 0.126341] Detected PIPT I-cache on CPU4
10208 01:38:02.250797 <6>[ 0.126398] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10209 01:38:02.257616 <6>[ 0.126414] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10210 01:38:02.264372 <6>[ 0.126706] Detected PIPT I-cache on CPU5
10211 01:38:02.271099 <6>[ 0.126764] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10212 01:38:02.277219 <6>[ 0.126780] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10213 01:38:02.280691 <6>[ 0.127052] Detected PIPT I-cache on CPU6
10214 01:38:02.287223 <6>[ 0.127113] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10215 01:38:02.298095 <6>[ 0.127129] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10216 01:38:02.301358 <6>[ 0.127419] Detected PIPT I-cache on CPU7
10217 01:38:02.308018 <6>[ 0.127482] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10218 01:38:02.315043 <6>[ 0.127498] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10219 01:38:02.318002 <6>[ 0.127544] smp: Brought up 1 node, 8 CPUs
10220 01:38:02.324579 <6>[ 0.127548] SMP: Total of 8 processors activated.
10221 01:38:02.327934 <6>[ 0.127551] CPU features: detected: 32-bit EL0 Support
10222 01:38:02.337979 <6>[ 0.127554] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10223 01:38:02.344413 <6>[ 0.127556] CPU features: detected: Common not Private translations
10224 01:38:02.350890 <6>[ 0.127558] CPU features: detected: CRC32 instructions
10225 01:38:02.357697 <6>[ 0.127561] CPU features: detected: RCpc load-acquire (LDAPR)
10226 01:38:02.361201 <6>[ 0.127562] CPU features: detected: LSE atomic instructions
10227 01:38:02.367386 <6>[ 0.127564] CPU features: detected: Privileged Access Never
10228 01:38:02.373915 <6>[ 0.127565] CPU features: detected: RAS Extension Support
10229 01:38:02.380761 <6>[ 0.127568] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10230 01:38:02.383894 <6>[ 0.127638] CPU: All CPU(s) started at EL2
10231 01:38:02.390719 <6>[ 0.127640] alternatives: applying system-wide alternatives
10232 01:38:02.393644 <6>[ 0.140049] devtmpfs: initialized
10233 01:38:02.419667 <6>[ 0.351745] printk: console [ttyS0] pri<nting thread started
10234 01:38:02.426154 6>[<6>[ 0.351773] printk: console [ttyS0] enabled
10235 01:38:02.436059 0.145537] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10236 01:38:02.442735 <6>[ 0.145550] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10237 01:38:02.445691 <6>[ 0.146429] pinctrl core: initialized pinctrl subsystem
10238 01:38:02.455241 <6>[ 0.351777] printk: bootconsole [mtk8250] disabled
10239 01:38:02.462199 <6>[ 0.384781] printk: bootconsole [mtk8250] printing thread stopped
10240 01:38:02.465412 <6>[ 0.386183] SuperH (H)SCI(F) driver initialized
10241 01:38:02.471992 <6>[ 0.386657] msm_serial: driver initialized
10242 01:38:02.478256 <6>[ 0.391234] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10243 01:38:02.488537 <6>[ 0.391263] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10244 01:38:02.494974 <6>[ 0.391292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10245 01:38:02.507468 <6>[ 0.391320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10246 01:38:02.512627 <6>[ 0.391342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10247 01:38:02.529962 <6>[ 0.391370] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10248 01:38:02.546031 <6>[ 0.391398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10249 01:38:02.546612 <6>[ 0.391527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10250 01:38:02.552408 <6>[ 0.391556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10251 01:38:02.552985 <6>[ 0.402455] loop: module loaded
10252 01:38:02.559664 <6>[ 0.404987] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10253 01:38:02.564063 <4>[ 0.421684] mtk-pmic-keys: Failed to locate of_node [id: -1]
10254 01:38:02.567853 <6>[ 0.422575] megasas: 07.719.03.00-rc1
10255 01:38:02.574197 <6>[ 0.435040] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10256 01:38:02.580952 <6>[ 0.442757] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10257 01:38:02.587600 <6>[ 0.454233] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10258 01:38:02.597364 <6>[ 0.506112] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10259 01:38:04.530730 <6>[ 2.460811] Freeing initrd memory: 50912K
10260 01:38:04.538827 <6>[ 2.467973] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10261 01:38:04.545387 <6>[ 2.472696] tun: Universal TUN/TAP device driver, 1.6
10262 01:38:04.548778 <6>[ 2.473447] thunder_xcv, ver 1.0
10263 01:38:04.552278 <6>[ 2.473465] thunder_bgx, ver 1.0
10264 01:38:04.555298 <6>[ 2.473481] nicpf, ver 1.0
10265 01:38:04.562266 <6>[ 2.474528] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10266 01:38:04.568710 <6>[ 2.474531] hns3: Copyright (c) 2017 Huawei Corporation.
10267 01:38:04.572179 <6>[ 2.474556] hclge is initializing
10268 01:38:04.575361 <6>[ 2.474569] e1000: Intel(R) PRO/1000 Network Driver
10269 01:38:04.582537 <6>[ 2.474572] e1000: Copyright (c) 1999-2006 Intel Corporation.
10270 01:38:04.589761 <6>[ 2.474591] e1000e: Intel(R) PRO/1000 Network Driver
10271 01:38:04.593197 <6>[ 2.474592] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10272 01:38:04.599847 <6>[ 2.474608] igb: Intel(R) Gigabit Ethernet Network Driver
10273 01:38:04.606513 <6>[ 2.474610] igb: Copyright (c) 2007-2014 Intel Corporation.
10274 01:38:04.613484 <6>[ 2.474623] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10275 01:38:04.620364 <6>[ 2.474625] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10276 01:38:04.623773 <6>[ 2.474913] sky2: driver version 1.30
10277 01:38:04.630332 <6>[ 2.475916] usbcore: registered new device driver r8152-cfgselector
10278 01:38:04.633530 <6>[ 2.475935] usbcore: registered new interface driver r8152
10279 01:38:04.640490 <6>[ 2.476009] VFIO - User Level meta-driver version: 0.3
10280 01:38:04.646836 <6>[ 2.478807] usbcore: registered new interface driver usb-storage
10281 01:38:04.653722 <6>[ 2.478990] usbcore: registered new device driver onboard-usb-hub
10282 01:38:04.657322 <6>[ 2.481776] mt6397-rtc mt6359-rtc: registered as rtc0
10283 01:38:04.666882 <6>[ 2.481925] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T01:38:04 UTC (1717551484)
10284 01:38:04.670213 <6>[ 2.482529] i2c_dev: i2c /dev entries driver
10285 01:38:04.680498 <6>[ 2.489634] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10286 01:38:04.686787 <4>[ 2.490356] cpu cpu0: supply cpu not found, using dummy regulator
10287 01:38:04.693427 <4>[ 2.490426] cpu cpu1: supply cpu not found, using dummy regulator
10288 01:38:04.699962 <4>[ 2.490484] cpu cpu2: supply cpu not found, using dummy regulator
10289 01:38:04.706465 <4>[ 2.490550] cpu cpu3: supply cpu not found, using dummy regulator
10290 01:38:04.710201 <4>[ 2.490598] cpu cpu4: supply cpu not found, using dummy regulator
10291 01:38:04.716880 <4>[ 2.490650] cpu cpu5: supply cpu not found, using dummy regulator
10292 01:38:04.722970 <4>[ 2.490698] cpu cpu6: supply cpu not found, using dummy regulator
10293 01:38:04.729858 <4>[ 2.490750] cpu cpu7: supply cpu not found, using dummy regulator
10294 01:38:04.736162 <6>[ 2.504661] cpu cpu0: EM: created perf domain
10295 01:38:04.739632 <6>[ 2.504968] cpu cpu4: EM: created perf domain
10296 01:38:04.746210 <6>[ 2.506201] sdhci: Secure Digital Host Controller Interface driver
10297 01:38:04.749401 <6>[ 2.506202] sdhci: Copyright(c) Pierre Ossman
10298 01:38:04.756325 <6>[ 2.506517] Synopsys Designware Multimedia Card Interface Driver
10299 01:38:04.762674 <6>[ 2.506840] sdhci-pltfm: SDHCI platform and OF driver helper
10300 01:38:04.769430 <6>[ 2.509615] ledtrig-cpu: registered to indicate activity on CPUs
10301 01:38:04.772694 <6>[ 2.510271] mmc0: CQHCI version 5.10
10302 01:38:04.779355 <6>[ 2.510365] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10303 01:38:04.785599 <6>[ 2.510621] usbcore: registered new interface driver usbhid
10304 01:38:04.789218 <6>[ 2.510622] usbhid: USB HID core driver
10305 01:38:04.795640 <6>[ 2.510726] spi_master spi0: will run message pump with realtime priority
10306 01:38:04.808886 <6>[ 2.549876] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10307 01:38:04.822142 <6>[ 2.552656] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10308 01:38:04.828458 <6>[ 2.553963] cros-ec-spi spi0.0: Chrome EC device registered
10309 01:38:04.838681 <6>[ 2.575048] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10310 01:38:04.841641 <6>[ 2.578008] NET: Registered PF_PACKET protocol family
10311 01:38:04.848684 <6>[ 2.578159] 9pnet: Installing 9P2000 support
10312 01:38:04.851729 <5>[ 2.578212] Key type dns_resolver registered
10313 01:38:04.855066 <6>[ 2.578563] registered taskstats version 1
10314 01:38:04.861759 <5>[ 2.578580] Loading compiled-in X.509 certificates
10315 01:38:04.871627 <4>[ 2.594314] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10316 01:38:04.881152 <4>[ 2.594507] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10317 01:38:04.887927 <6>[ 2.603104] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10318 01:38:04.894468 <6>[ 2.609019] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10319 01:38:04.897873 <6>[ 2.609265] mmc0: Command Queue Engine enabled
10320 01:38:04.904495 <6>[ 2.609279] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10321 01:38:04.910942 <6>[ 2.609657] xhci-mtk 11200000.usb: xHCI Host Controller
10322 01:38:04.917651 <6>[ 2.609689] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10323 01:38:04.923997 <6>[ 2.609925] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10324 01:38:04.934245 <6>[ 2.609971] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10325 01:38:04.940484 <6>[ 2.610073] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10326 01:38:04.943922 <6>[ 2.610210] xhci-mtk 11200000.usb: xHCI Host Controller
10327 01:38:04.950450 <6>[ 2.610221] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10328 01:38:04.960374 <6>[ 2.610230] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10329 01:38:04.963553 <6>[ 2.610738] hub 1-0:1.0: USB hub found
10330 01:38:04.966823 <6>[ 2.610767] hub 1-0:1.0: 1 port detected
10331 01:38:04.976881 <6>[ 2.611045] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10332 01:38:04.980401 <6>[ 2.611377] hub 2-0:1.0: USB hub found
10333 01:38:04.983534 <6>[ 2.611402] hub 2-0:1.0: 1 port detected
10334 01:38:04.990162 <6>[ 2.613298] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10335 01:38:04.996773 <6>[ 2.614778] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10336 01:38:05.000104 <6>[ 2.615370] mtk-msdc 11f70000.mmc: Got CD GPIO
10337 01:38:05.006813 <6>[ 2.615729] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10338 01:38:05.013459 <6>[ 2.616435] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10339 01:38:05.020076 <6>[ 2.630142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10340 01:38:05.026269 <6>[ 2.630151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10341 01:38:05.036530 <4>[ 2.630304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10342 01:38:05.045984 <6>[ 2.630932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10343 01:38:05.052962 <6>[ 2.630935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10344 01:38:05.059454 <6>[ 2.631041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10345 01:38:05.069358 <6>[ 2.631052] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10346 01:38:05.076207 <6>[ 2.631056] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10347 01:38:05.085677 <6>[ 2.631065] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10348 01:38:05.092406 <6>[ 2.632525] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10349 01:38:05.102301 <6>[ 2.632544] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10350 01:38:05.109376 <6>[ 2.632549] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10351 01:38:05.118654 <6>[ 2.632555] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10352 01:38:05.125493 <6>[ 2.632560] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10353 01:38:05.135306 <6>[ 2.632567] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10354 01:38:05.142200 <6>[ 2.632572] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10355 01:38:05.151781 <6>[ 2.632578] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10356 01:38:05.161413 <6>[ 2.632583] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10357 01:38:05.168202 <6>[ 2.632588] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10358 01:38:05.177758 <6>[ 2.632594] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10359 01:38:05.184800 <6>[ 2.632599] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10360 01:38:05.194321 <6>[ 2.632605] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10361 01:38:05.200952 <6>[ 2.632611] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10362 01:38:05.210695 <6>[ 2.632616] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10363 01:38:05.217245 <6>[ 2.633150] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10364 01:38:05.223854 <6>[ 2.633970] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10365 01:38:05.230783 <6>[ 2.634512] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10366 01:38:05.237059 <6>[ 2.635120] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10367 01:38:05.243816 <6>[ 2.635810] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10368 01:38:05.253516 <6>[ 2.636098] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10369 01:38:05.260250 <6>[ 2.636114] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10370 01:38:05.270101 <6>[ 2.636120] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10371 01:38:05.280234 <6>[ 2.636127] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10372 01:38:05.290304 <6>[ 2.636133] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10373 01:38:05.299966 <6>[ 2.636139] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10374 01:38:05.306599 <6>[ 2.636145] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10375 01:38:05.316613 <6>[ 2.636151] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10376 01:38:05.326510 <6>[ 2.636156] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10377 01:38:05.335988 <6>[ 2.636164] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10378 01:38:05.345855 <6>[ 2.636169] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10379 01:38:05.355886 <6>[ 2.637381] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10380 01:38:05.362731 <6>[ 3.031658] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10381 01:38:05.365809 <6>[ 3.183182] hub 1-1:1.0: USB hub found
10382 01:38:05.369146 <6>[ 3.183406] hub 1-1:1.0: 4 ports detected
10383 01:38:05.372715 <6>[ 3.186337] hub 1-1:1.0: USB hub found
10384 01:38:05.379337 <6>[ 3.186593] hub 1-1:1.0: 4 ports detected
10385 01:38:05.385740 <6>[ 3.311810] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10386 01:38:05.406812 <6>[ 3.336889] hub 2-1:1.0: USB hub found
10387 01:38:05.410095 <6>[ 3.337314] hub 2-1:1.0: 3 ports detected
10388 01:38:05.413614 <6>[ 3.340185] hub 2-1:1.0: USB hub found
10389 01:38:05.416634 <6>[ 3.340537] hub 2-1:1.0: 3 ports detected
10390 01:38:05.574372 <6>[ 3.499820] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10391 01:38:05.695382 <6>[ 3.627161] hub 1-1.4:1.0: USB hub found
10392 01:38:05.698037 <6>[ 3.627546] hub 1-1.4:1.0: 2 ports detected
10393 01:38:05.701631 <6>[ 3.630200] hub 1-1.4:1.0: USB hub found
10394 01:38:05.707985 <6>[ 3.630528] hub 1-1.4:1.0: 2 ports detected
10395 01:38:05.777999 <6>[ 3.703956] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10396 01:38:05.882405 <6>[ 3.808371] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10397 01:38:05.921962 <6>[ 3.847675] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10398 01:38:05.951050 <6>[ 3.881090] r8152 2-1.3:1.0 eth0: v1.12.13
10399 01:38:05.994380 <6>[ 3.919809] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10400 01:38:06.178356 <6>[ 4.103771] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10401 01:38:07.546823 <6>[ 5.479297] r8152 2-1.3:1.0 eth0: carrier on
10402 01:38:10.498371 <5>[ 5.499772] Sending DHCP requests .., OK
10403 01:38:10.504763 <6>[ 8.427725] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10404 01:38:10.508138 <6>[ 8.427743] IP-Config: Complete:
10405 01:38:10.521166 <6>[ 8.427745] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10406 01:38:10.527718 <6>[ 8.427755] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10407 01:38:10.534521 <6>[ 8.427760] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10408 01:38:10.541217 <6>[ 8.427765] nameserver0=192.168.201.1
10409 01:38:10.544751 <6>[ 8.428021] clk: Disabling unused clocks
10410 01:38:10.548049 <6>[ 8.429013] ALSA device list:
10411 01:38:10.551338 <6>[ 8.429026] No soundcards found.
10412 01:38:10.558207 <6>[ 8.433514] Freeing unused kernel memory: 8512K
10413 01:38:10.561605 <6>[ 8.433706] Run /init as init process
10414 01:38:10.564858 <6>[ 8.491464] NET: Registered PF_INET6 protocol family
10415 01:38:10.571536 <6>[ 8.493318] Segment Routing with IPv6
10416 01:38:10.574792 <6>[ 8.493345] In-situ OAM (IOAM) with IPv6
10417 01:38:10.580812
10418 01:38:10.613597 Welcome to [1mDebian GNU/Linu<30>[ 8.516912] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10419 01:38:10.620315 <30>[ 8.516926] systemd[1]: Detected architecture arm64.
10420 01:38:10.623979 x 12 (bookworm)[0m!
10421 01:38:10.624542
10422 01:38:10.642448 <30>[ 8.571855] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10423 01:38:10.769792 <30>[ 8.698762] systemd[1]: Queued start job for default target graphical.target.
10424 01:38:10.810919 [[0;32m OK [0m] Created slic<30>[ 8.737415] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10425 01:38:10.814213 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10426 01:38:10.838357 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 8.764687] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10427 01:38:10.841682 m-modpr…lice[0m - Slice /system/modprobe.
10428 01:38:10.867269 [[0;32m OK [0m] Created slic<30>[ 8.793661] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10429 01:38:10.873811 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10430 01:38:10.895407 [[0;32m OK [0m] Created slic<30>[ 8.821860] systemd[1]: Created slice user.slice - User and Session Slice.
10431 01:38:10.898638 e [0;1;39muser.slice[0m - User and Session Slice.
10432 01:38:10.925493 [[0;32m OK [0m] Started [0;<30>[ 8.848648] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10433 01:38:10.929143 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10434 01:38:10.952979 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 8.876028] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10435 01:38:10.956083 -passwo… Requests to Wall Directory Watch.
10436 01:38:10.991204 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 8.904335] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10437 01:38:10.997862 ice[0m - /dev/t<30>[ 8.904506] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10438 01:38:11.001238 tyS0...
10439 01:38:11.021359 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 8.947813] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10440 01:38:11.024803 tsetup.…get[0m - Local Encrypted Volumes.
10441 01:38:11.048664 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 8.971858] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10442 01:38:11.051791 grityse…Local Integrity Protected Volumes.
10443 01:38:11.074236 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 9.000353] systemd[1]: Reached target paths.target - Path Units.
10444 01:38:11.074806 s.target[0m - Path Units.
10445 01:38:11.097847 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 9.024247] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10446 01:38:11.101099 te-fs.target[0m - Remote File Systems.
10447 01:38:11.121284 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 9.047790] systemd[1]: Reached target slices.target - Slice Units.
10448 01:38:11.124500 es.target[0m - Slice Units.
10449 01:38:11.146245 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 9.072266] systemd[1]: Reached target swap.target - Swaps.
10450 01:38:11.146817 .target[0m - Swaps.
10451 01:38:11.169978 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 9.096339] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10452 01:38:11.176617 tysetup… - Local Verity Protected Volumes.
10453 01:38:11.198103 [[0;32m OK [0m] Listening on<30>[ 9.124613] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10454 01:38:11.204889 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10455 01:38:11.227476 [[0;32m OK [0m] Listening on<30>[ 9.153781] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10456 01:38:11.233688 [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10457 01:38:11.257441 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 9.180424] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10458 01:38:11.260692 d-journ…t[0m - Journal Socket (/dev/log).
10459 01:38:11.282050 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 9.208432] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10460 01:38:11.285308 d-journald.socket[0m - Journal Socket.
10461 01:38:11.305945 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 9.232469] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10462 01:38:11.312709 d-netwo… - Network Service Netlink Socket.
10463 01:38:11.334865 [[0;32m OK [0m] Listening on<30>[ 9.261254] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10464 01:38:11.341356 [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10465 01:38:11.362607 [[0;32m OK [0m] Listening on<30>[ 9.288898] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10466 01:38:11.369071 [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10467 01:38:11.413992 Mounting [0;1;39mdev-hugepages.mount[<30>[ 9.340091] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10468 01:38:11.416994 0m - Huge Pages File System...
10469 01:38:11.439588 Mounting [0;1;39mdev-m<30>[ 9.365944] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10470 01:38:11.442627 queue.mount…POSIX Message Queue File System...
10471 01:38:11.465056 Mountin<30>[ 9.394780] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10472 01:38:11.471620 g [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10473 01:38:11.500244 <30>[ 9.420346] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10474 01:38:11.510488 Startin<30>[ 9.425185] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10475 01:38:11.516621 g [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10476 01:38:11.566120 Starting [0;1;39mmodprobe@configfs…m<30>[ 9.492408] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10477 01:38:11.569215 - Load Kernel Module configfs...
10478 01:38:11.597932 Starting [0;1;39mmodprobe@dm_mod.s…[<30>[ 9.524369] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10479 01:38:11.610911 0m - Load Kernel Module dm_mod..<6>[ 9.538012] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10480 01:38:11.611469 .
10481 01:38:11.638738 Starting [0;1;39mmodpr<30>[ 9.565264] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10482 01:38:11.641889 obe@drm.service[0m - Load Kernel Module drm...
10483 01:38:11.670589 Starting [0;1;39mmodpr<30>[ 9.596992] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10484 01:38:11.673733 obe@efi_psto…- Load Kernel Module efi_pstore...
10485 01:38:11.702499 Starting [0;1;39mmodpr<30>[ 9.628887] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10486 01:38:11.705557 obe@loop.ser…e[0m - Load Kernel Module loop...
10487 01:38:11.757964 Starting [0;1;39msystemd-journald.serv<30>[ 9.684203] systemd[1]: Starting systemd-journald.service - Journal Service...
10488 01:38:11.761043 ice[0m - Journal Service...
10489 01:38:11.781208 Startin<30>[ 9.710922] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10490 01:38:11.787547 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10491 01:38:11.818713 Starting [0;1;39msyste<30>[ 9.741567] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10492 01:38:11.821733 md-network-g… units from Kernel command line...
10493 01:38:11.853174 Starting [0;1;39msystemd-remount-f…n<30>[ 9.776383] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10494 01:38:11.856506 t Root and Kernel File Systems...
10495 01:38:11.883423 Starting [0;1;39msyste<30>[ 9.809814] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10496 01:38:11.886372 md-udev-trig…[0m - Coldplug All udev Devices...
10497 01:38:11.913661 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 9.840305] systemd[1]: Started systemd-journald.service - Journal Service.
10498 01:38:11.917074 rnald.service[0m - Journal Service.
10499 01:38:11.937819 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10500 01:38:11.954077 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10501 01:38:11.970309 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10502 01:38:11.987269 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10503 01:38:12.007457 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10504 01:38:12.027445 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10505 01:38:12.047455 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10506 01:38:12.068386 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10507 01:38:12.094738 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10508 01:38:12.112450 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10509 01:38:12.131067 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10510 01:38:12.152302 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10511 01:38:12.158849 See 'systemctl status systemd-remount-fs.service' for details.
10512 01:38:12.168627 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10513 01:38:12.188483 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10514 01:38:12.246823 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10515 01:38:12.275263 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10516 01:38:12.285804 <46>[ 10.215134] systemd-journald[194]: Received client request to flush runtime journal.
10517 01:38:12.299334 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10518 01:38:12.351037 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10519 01:38:12.376105 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10520 01:38:12.404101 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10521 01:38:12.423097 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10522 01:38:12.443333 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10523 01:38:12.463512 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10524 01:38:12.483387 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10525 01:38:12.543277 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10526 01:38:12.564107 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10527 01:38:12.586103 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10528 01:38:12.606049 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10529 01:38:12.658597 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10530 01:38:12.686939 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10531 01:38:12.709928 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10532 01:38:12.746524 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10533 01:38:12.770864 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10534 01:38:12.793235 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10535 01:38:12.863651 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10536 01:38:12.888720 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10537 01:38:12.912389 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10538 01:38:13.000888 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10539 01:38:13.019098 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10540 01:38:13.039974 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10541 01:38:13.059605 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10542 01:38:13.078703 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10543 01:38:13.089457 <3>[ 11.016290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10544 01:38:13.099507 <3>[ 11.016312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10545 01:38:13.106193 <3>[ 11.016315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10546 01:38:13.119291 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<3>[ 11.016396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10547 01:38:13.129121 ocket[…- D-Bu<3>[ 11.016399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10548 01:38:13.138994 s System Message<3>[ 11.016401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10549 01:38:13.145358 <3>[ 11.016405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10550 01:38:13.145822 Bus Socket.
10551 01:38:13.155614 <3>[ 11.016407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10552 01:38:13.162045 <3>[ 11.016431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10553 01:38:13.171803 <3>[ 11.016448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10554 01:38:13.181830 [[0;32m OK [0m] Reached targ<3>[ 11.016450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10555 01:38:13.191801 et [0;1;39msock<3>[ 11.016453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10556 01:38:13.201776 ets.target[0m -<3>[ 11.016468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10557 01:38:13.202344 Socket Units.
10558 01:38:13.211650 <3>[ 11.016470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10559 01:38:13.218305 <3>[ 11.016472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10560 01:38:13.218850
10561 01:38:13.227954 <3>[ 11.016475] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10562 01:38:13.234590 <3>[ 11.016477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10563 01:38:13.241118 <3>[ 11.016488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10564 01:38:13.251132 <6>[ 11.044579] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10565 01:38:13.257510 <6>[ 11.044670] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10566 01:38:13.267521 <6>[ 11.044685] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10567 01:38:13.274702 <6>[ 11.061753] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10568 01:38:13.281804 <6>[ 11.073535] remoteproc remoteproc0: scp is available
10569 01:38:13.284804 <6>[ 11.073772] remoteproc remoteproc0: powering up scp
10570 01:38:13.294613 <6>[ 11.073784] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10571 01:38:13.297840 <6>[ 11.073810] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10572 01:38:13.304442 <6>[ 11.120841] mc: Linux media interface: v0.10
10573 01:38:13.310931 <4>[ 11.137679] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10574 01:38:13.318075 <4>[ 11.148783] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10575 01:38:13.324820 <6>[ 11.173336] videodev: Linux video capture interface: v2.00
10576 01:38:13.332124 <6>[ 11.178308] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10577 01:38:13.338631 <6>[ 11.184421] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10578 01:38:13.345263 <6>[ 11.184450] pci_bus 0000:00: root bus resource [bus 00-ff]
10579 01:38:13.351873 <6>[ 11.184461] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10580 01:38:13.361612 <6>[ 11.184468] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10581 01:38:13.368565 <6>[ 11.184549] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10582 01:38:13.375733 <6>[ 11.184585] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10583 01:38:13.378981 <6>[ 11.184721] pci 0000:00:00.0: supports D1 D2
10584 01:38:13.385808 <6>[ 11.184727] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10585 01:38:13.395946 <6>[ 11.199221] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10586 01:38:13.402720 <6>[ 11.199221] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10587 01:38:13.409246 <6>[ 11.199240] remoteproc remoteproc0: remote processor scp is now up
10588 01:38:13.416300 <4>[ 11.200667] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10589 01:38:13.422825 <4>[ 11.200667] Fallback method does not support PEC.
10590 01:38:13.429631 <6>[ 11.210443] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10591 01:38:13.436306 <6>[ 11.211141] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10592 01:38:13.443213 <6>[ 11.211213] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10593 01:38:13.450105 <6>[ 11.211251] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10594 01:38:13.460607 <6>[ 11.211270] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10595 01:38:13.463929 <6>[ 11.211465] pci 0000:01:00.0: supports D1 D2
10596 01:38:13.470592 <6>[ 11.211472] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10597 01:38:13.480750 <3>[ 11.217021] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10598 01:38:13.488176 <6>[ 11.223020] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10599 01:38:13.494507 <6>[ 11.223060] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10600 01:38:13.501508 <6>[ 11.223066] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10601 01:38:13.511434 <6>[ 11.223079] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10602 01:38:13.517975 <6>[ 11.223095] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10603 01:38:13.525112 <6>[ 11.223111] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10604 01:38:13.531916 <6>[ 11.223127] pci 0000:00:00.0: PCI bridge to [bus 01]
10605 01:38:13.538866 <6>[ 11.223135] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10606 01:38:13.545614 <6>[ 11.223304] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10607 01:38:13.552699 <6>[ 11.224322] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10608 01:38:13.559169 <6>[ 11.224573] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10609 01:38:13.566222 <6>[ 11.233253] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10610 01:38:13.573159 <6>[ 11.234394] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10611 01:38:13.582973 <6>[ 11.255621] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10612 01:38:13.596294 Starting [0;1;39msystemd-networkd.…i<6>[ 11.256044] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10613 01:38:13.606243 <3>[ 11.264532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10614 01:38:13.616180 <6>[ 11.266847] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10615 01:38:13.625891 <3>[ 11.267090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10616 01:38:13.629462 <6>[ 11.300837] Bluetooth: Core ver 2.22
10617 01:38:13.633053 <6>[ 11.300901] NET: Registered PF_BLUETOOTH protocol family
10618 01:38:13.639538 <6>[ 11.300902] Bluetooth: HCI device and connection manager initialized
10619 01:38:13.645923 <6>[ 11.300914] Bluetooth: HCI socket layer initialized
10620 01:38:13.652562 <6>[ 11.300918] Bluetooth: L2CAP socket layer initialized
10621 01:38:13.655836 <6>[ 11.300935] Bluetooth: SCO socket layer initialized
10622 01:38:13.665664 <5>[ 11.309030] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10623 01:38:13.672561 <5>[ 11.322532] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10624 01:38:13.678890 <5>[ 11.323049] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10625 01:38:13.689057 <4>[ 11.323134] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10626 01:38:13.692023 <6>[ 11.323143] cfg80211: failed to load regulatory.db
10627 01:38:13.702139 <3>[ 11.334478] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10628 01:38:13.711877 <3>[ 11.340863] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10629 01:38:13.718905 <6>[ 11.341857] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10630 01:38:13.728429 <6>[ 11.343196] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10631 01:38:13.735272 <6>[ 11.343559] usbcore: registered new interface driver uvcvideo
10632 01:38:13.744972 <3>[ 11.362775] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 01:38:13.751664 <3>[ 11.363523] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10634 01:38:13.758682 <6>[ 11.370340] usbcore: registered new interface driver btusb
10635 01:38:13.767764 <4>[ 11.371175] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10636 01:38:13.774583 <3>[ 11.371219] Bluetooth: hci0: Failed to load firmware file (-2)
10637 01:38:13.781057 <3>[ 11.371224] Bluetooth: hci0: Failed to set up firmware (-2)
10638 01:38:13.791229 <4>[ 11.371231] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10639 01:38:13.800842 <3>[ 11.385231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 01:38:13.807853 <6>[ 11.390713] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10641 01:38:13.814025 <3>[ 11.404847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10642 01:38:13.824954 <3>[ 11.426615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 01:38:13.830502 <6>[ 11.435761] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10644 01:38:13.837403 <6>[ 11.435854] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10645 01:38:13.843619 <6>[ 11.454472] mt7921e 0000:01:00.0: ASIC revision: 79610010
10646 01:38:13.850357 <6>[ 11.549251] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10647 01:38:13.853611 <6>[ 11.549251]
10648 01:38:13.856814 ce[0m - Network Configuration...
10649 01:38:13.875748 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10650 01:38:13.882435 <6>[ 11.809611] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10651 01:38:13.905043 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10652 01:38:13.937170 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10653 01:38:13.956738 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10654 01:38:13.976492 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10655 01:38:14.033609 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10656 01:38:14.059758 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10657 01:38:14.080007 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10658 01:38:14.096169 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10659 01:38:14.116055 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10660 01:38:14.176855 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10661 01:38:14.201143 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10662 01:38:14.223935 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10663 01:38:14.245238 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10664 01:38:14.296614 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10665 01:38:14.317044 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10666 01:38:14.335484 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10667 01:38:14.351184 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10668 01:38:14.371027 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10669 01:38:14.443804 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10670 01:38:14.467794 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10671 01:38:14.490957 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10672 01:38:14.532319 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10673 01:38:14.583542
10674 01:38:14.586844 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10675 01:38:14.587307
10676 01:38:14.590262 debian-bookworm-arm64 login: root (automatic login)
10677 01:38:14.590724
10678 01:38:14.601908 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10679 01:38:14.602425
10680 01:38:14.608792 The programs included with the Debian GNU/Linux system are free software;
10681 01:38:14.615434 the exact distribution terms for each program are described in the
10682 01:38:14.618630 individual files in /usr/share/doc/*/copyright.
10683 01:38:14.619094
10684 01:38:14.625308 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10685 01:38:14.628228 permitted by applicable law.
10686 01:38:14.629756 Matched prompt #10: / #
10688 01:38:14.630753 Setting prompt string to ['/ #']
10689 01:38:14.631181 end: 2.2.5.1 login-action (duration 00:00:13) [common]
10691 01:38:14.632143 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
10692 01:38:14.632567 start: 2.2.6 expect-shell-connection (timeout 00:03:28) [common]
10693 01:38:14.632921 Setting prompt string to ['/ #']
10694 01:38:14.633229 Forcing a shell prompt, looking for ['/ #']
10696 01:38:14.684051 / #
10697 01:38:14.684713 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10698 01:38:14.685124 Waiting using forced prompt support (timeout 00:02:30)
10699 01:38:14.690064
10700 01:38:14.690980 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10701 01:38:14.691504 start: 2.2.7 export-device-env (timeout 00:03:28) [common]
10702 01:38:14.692000 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10703 01:38:14.692465 end: 2.2 depthcharge-retry (duration 00:01:32) [common]
10704 01:38:14.692922 end: 2 depthcharge-action (duration 00:01:32) [common]
10705 01:38:14.693425 start: 3 lava-test-retry (timeout 00:05:00) [common]
10706 01:38:14.693891 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10707 01:38:14.694303 Using namespace: common
10709 01:38:14.795656 / # #
10710 01:38:14.796312 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10711 01:38:14.796904 <6>[ 12.651617] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10712 01:38:14.801823 #
10713 01:38:14.802701 Using /lava-14173528
10715 01:38:14.903824 / # export SHELL=/bin/sh
10716 01:38:14.910401 export SHELL=/bin/sh
10718 01:38:15.012243 / # . /lava-14173528/environment
10719 01:38:15.018614 . /lava-14173528/environment
10721 01:38:15.120607 / # /lava-14173528/bin/lava-test-runner /lava-14173528/0
10722 01:38:15.121263 Test shell timeout: 10s (minimum of the action and connection timeout)
10723 01:38:15.126784 /lava-14173528/bin/lava-test-runner /lava-14173528/0
10724 01:38:15.145059 + export TESTRUN_ID=0_cros-ec
10725 01:38:15.154561 + cd /lava-14173528/0/tests/0_cro<8>[ 13.083984] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14173528_1.5.2.3.1>
10726 01:38:15.155147 s-ec
10727 01:38:15.155813 Received signal: <STARTRUN> 0_cros-ec 14173528_1.5.2.3.1
10728 01:38:15.156204 Starting test lava.0_cros-ec (14173528_1.5.2.3.1)
10729 01:38:15.156632 Skipping test definition patterns.
10730 01:38:15.157650 + cat uuid
10731 01:38:15.158118 + UUID=14173528_1.5.2.3.1
10732 01:38:15.158489 + set +x
10733 01:38:15.164368 + python3 -m cros.runners.lava_runner -v
10734 01:38:15.572840 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
10735 01:38:15.579065 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10736 01:38:15.579147
10737 01:38:15.585792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10738 01:38:15.586148 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10740 01:38:15.595818 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
10741 01:38:15.605975 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10742 01:38:15.606537
10743 01:38:15.612347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
10744 01:38:15.613171 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
10746 01:38:15.622341 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
10747 01:38:15.628886 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10748 01:38:15.629384
10749 01:38:15.635802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10750 01:38:15.636654 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10752 01:38:15.642119 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
10753 01:38:15.649112 Checks the standard ABI for the main Embedded Controller. ... ok
10754 01:38:15.649724
10755 01:38:15.652331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10756 01:38:15.653168 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10758 01:38:15.658580 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
10759 01:38:15.665438 Checks the main Embedded controller character device. ... ok
10760 01:38:15.666000
10761 01:38:15.671971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10762 01:38:15.672827 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10764 01:38:15.678661 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
10765 01:38:15.684876 Checks basic comunication with the main Embedded controller. ... ok
10766 01:38:15.685396
10767 01:38:15.691727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10768 01:38:15.692457 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10770 01:38:15.698307 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
10771 01:38:15.705000 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10772 01:38:15.705636
10773 01:38:15.711626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10774 01:38:15.712476 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10776 01:38:15.717932 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
10777 01:38:15.724409 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10778 01:38:15.724956
10779 01:38:15.731172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10780 01:38:15.731899 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10782 01:38:15.737674 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
10783 01:38:15.744567 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10784 01:38:15.745037
10785 01:38:15.750955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10786 01:38:15.751681 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10788 01:38:15.757487 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
10789 01:38:15.767413 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10790 01:38:15.767881
10791 01:38:15.770584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10792 01:38:15.771309 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10794 01:38:15.777199 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
10795 01:38:15.787615 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10796 01:38:15.788197
10797 01:38:15.793847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10798 01:38:15.794579 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10800 01:38:15.800705 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
10801 01:38:15.806988 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10802 01:38:15.807508
10803 01:38:15.813847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10804 01:38:15.814576 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10806 01:38:15.820442 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
10807 01:38:15.826698 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10808 01:38:15.827162
10809 01:38:15.833452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10810 01:38:15.834300 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10812 01:38:15.843700 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
10813 01:38:15.849902 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10814 01:38:15.850368
10815 01:38:15.856896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10816 01:38:15.857913 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10818 01:38:15.866489 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
10819 01:38:15.869636 Check the cros battery ABI. ... skipped 'No BAT found'
10820 01:38:15.870103
10821 01:38:15.876470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10822 01:38:15.877351 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10824 01:38:15.886367 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
10825 01:38:15.893171 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10826 01:38:15.893797
10827 01:38:15.899502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10828 01:38:15.900355 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10830 01:38:15.909219 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
10831 01:38:15.916105 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10832 01:38:15.916681
10833 01:38:15.922674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10834 01:38:15.923520 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10836 01:38:15.929484 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
10837 01:38:15.936046 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10838 01:38:15.936618
10839 01:38:15.942471 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8
10840 01:38:15.943086 Bad test result: ski<8
10841 01:38:15.949398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8>[ 13.879855] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14173528_1.5.2.3.1>
10842 01:38:15.949986 p>
10843 01:38:15.950356
10844 01:38:15.950968 Received signal: <ENDRUN> 0_cros-ec 14173528_1.5.2.3.1
10845 01:38:15.951389 Ending use of test pattern.
10846 01:38:15.951728 Ending test lava.0_cros-ec (14173528_1.5.2.3.1), duration 0.80
10848 01:38:15.955461 ----------------------------------------------------------------------
10849 01:38:15.958875 Ran 18 tests in 0.339s
10850 01:38:15.959334
10851 01:38:15.959699 OK (skipped=15)
10852 01:38:15.962145 + set +x
10853 01:38:15.962613 <LAVA_TEST_RUNNER EXIT>
10854 01:38:15.963264 ok: lava_test_shell seems to have completed
10855 01:38:15.964195 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10856 01:38:15.964687 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10857 01:38:15.965139 end: 3 lava-test-retry (duration 00:00:01) [common]
10858 01:38:15.965678 start: 4 finalize (timeout 00:08:05) [common]
10859 01:38:15.966263 start: 4.1 power-off (timeout 00:00:30) [common]
10860 01:38:15.967368 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10861 01:38:16.087284 >> Command sent successfully.
10862 01:38:16.091081 Returned 0 in 0 seconds
10863 01:38:16.192007 end: 4.1 power-off (duration 00:00:00) [common]
10865 01:38:16.193796 start: 4.2 read-feedback (timeout 00:08:05) [common]
10866 01:38:16.195094 Listened to connection for namespace 'common' for up to 1s
10867 01:38:17.195753 Finalising connection for namespace 'common'
10868 01:38:17.196443 Disconnecting from shell: Finalise
10869 01:38:17.196851 / #
10870 01:38:17.297954 end: 4.2 read-feedback (duration 00:00:01) [common]
10871 01:38:17.298900 end: 4 finalize (duration 00:00:01) [common]
10872 01:38:17.299543 Cleaning after the job
10873 01:38:17.300066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/ramdisk
10874 01:38:17.326429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/kernel
10875 01:38:17.354223 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/dtb
10876 01:38:17.354511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173528/tftp-deploy-9xqmsftx/modules
10877 01:38:17.361383 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173528
10878 01:38:17.448351 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173528
10879 01:38:17.448537 Job finished correctly