Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
1 01:33:39.616157 lava-dispatcher, installed at version: 2024.03
2 01:33:39.616353 start: 0 validate
3 01:33:39.616483 Start time: 2024-06-05 01:33:39.616475+00:00 (UTC)
4 01:33:39.616603 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:33:39.616730 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:33:39.898270 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:33:39.898994 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:33:40.153350 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:33:40.154633 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:33:40.416884 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:33:40.417630 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:33:40.687872 validate duration: 1.07
14 01:33:40.689264 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:33:40.689948 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:33:40.690512 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:33:40.691161 Not decompressing ramdisk as can be used compressed.
18 01:33:40.691638 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:33:40.691998 saving as /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/ramdisk/rootfs.cpio.gz
20 01:33:40.692355 total size: 47897469 (45 MB)
21 01:33:40.697538 progress 0 % (0 MB)
22 01:33:40.735086 progress 5 % (2 MB)
23 01:33:40.750942 progress 10 % (4 MB)
24 01:33:40.763206 progress 15 % (6 MB)
25 01:33:40.775053 progress 20 % (9 MB)
26 01:33:40.787201 progress 25 % (11 MB)
27 01:33:40.799093 progress 30 % (13 MB)
28 01:33:40.810910 progress 35 % (16 MB)
29 01:33:40.822908 progress 40 % (18 MB)
30 01:33:40.834769 progress 45 % (20 MB)
31 01:33:40.846732 progress 50 % (22 MB)
32 01:33:40.858688 progress 55 % (25 MB)
33 01:33:40.870674 progress 60 % (27 MB)
34 01:33:40.882666 progress 65 % (29 MB)
35 01:33:40.894737 progress 70 % (32 MB)
36 01:33:40.906619 progress 75 % (34 MB)
37 01:33:40.918567 progress 80 % (36 MB)
38 01:33:40.930470 progress 85 % (38 MB)
39 01:33:40.942280 progress 90 % (41 MB)
40 01:33:40.953947 progress 95 % (43 MB)
41 01:33:40.965733 progress 100 % (45 MB)
42 01:33:40.965939 45 MB downloaded in 0.27 s (166.95 MB/s)
43 01:33:40.966088 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:33:40.966326 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:33:40.966410 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:33:40.966492 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:33:40.966624 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:33:40.966692 saving as /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/kernel/Image
50 01:33:40.966752 total size: 54682112 (52 MB)
51 01:33:40.966812 No compression specified
52 01:33:40.967975 progress 0 % (0 MB)
53 01:33:40.981574 progress 5 % (2 MB)
54 01:33:40.995490 progress 10 % (5 MB)
55 01:33:41.009296 progress 15 % (7 MB)
56 01:33:41.022856 progress 20 % (10 MB)
57 01:33:41.036418 progress 25 % (13 MB)
58 01:33:41.049895 progress 30 % (15 MB)
59 01:33:41.063481 progress 35 % (18 MB)
60 01:33:41.077085 progress 40 % (20 MB)
61 01:33:41.090763 progress 45 % (23 MB)
62 01:33:41.104463 progress 50 % (26 MB)
63 01:33:41.118093 progress 55 % (28 MB)
64 01:33:41.131644 progress 60 % (31 MB)
65 01:33:41.144979 progress 65 % (33 MB)
66 01:33:41.158733 progress 70 % (36 MB)
67 01:33:41.172161 progress 75 % (39 MB)
68 01:33:41.186072 progress 80 % (41 MB)
69 01:33:41.199574 progress 85 % (44 MB)
70 01:33:41.213036 progress 90 % (46 MB)
71 01:33:41.226697 progress 95 % (49 MB)
72 01:33:41.239753 progress 100 % (52 MB)
73 01:33:41.239971 52 MB downloaded in 0.27 s (190.87 MB/s)
74 01:33:41.240119 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:33:41.240350 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:33:41.240436 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:33:41.240519 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:33:41.240654 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:33:41.240729 saving as /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/dtb/mt8192-asurada-spherion-r0.dtb
81 01:33:41.240789 total size: 47258 (0 MB)
82 01:33:41.240849 No compression specified
83 01:33:41.242034 progress 69 % (0 MB)
84 01:33:41.242300 progress 100 % (0 MB)
85 01:33:41.242451 0 MB downloaded in 0.00 s (27.15 MB/s)
86 01:33:41.242569 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:33:41.242785 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:33:41.242867 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:33:41.242947 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:33:41.243053 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:33:41.243120 saving as /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/modules/modules.tar
93 01:33:41.243179 total size: 8605984 (8 MB)
94 01:33:41.243239 Using unxz to decompress xz
95 01:33:41.247133 progress 0 % (0 MB)
96 01:33:41.265620 progress 5 % (0 MB)
97 01:33:41.292404 progress 10 % (0 MB)
98 01:33:41.321232 progress 15 % (1 MB)
99 01:33:41.344982 progress 20 % (1 MB)
100 01:33:41.368573 progress 25 % (2 MB)
101 01:33:41.392455 progress 30 % (2 MB)
102 01:33:41.416474 progress 35 % (2 MB)
103 01:33:41.442781 progress 40 % (3 MB)
104 01:33:41.465450 progress 45 % (3 MB)
105 01:33:41.489262 progress 50 % (4 MB)
106 01:33:41.514096 progress 55 % (4 MB)
107 01:33:41.538201 progress 60 % (4 MB)
108 01:33:41.561873 progress 65 % (5 MB)
109 01:33:41.586823 progress 70 % (5 MB)
110 01:33:41.610492 progress 75 % (6 MB)
111 01:33:41.637874 progress 80 % (6 MB)
112 01:33:41.661781 progress 85 % (7 MB)
113 01:33:41.686909 progress 90 % (7 MB)
114 01:33:41.712016 progress 95 % (7 MB)
115 01:33:41.736674 progress 100 % (8 MB)
116 01:33:41.741943 8 MB downloaded in 0.50 s (16.46 MB/s)
117 01:33:41.742177 end: 1.4.1 http-download (duration 00:00:00) [common]
119 01:33:41.742438 end: 1.4 download-retry (duration 00:00:00) [common]
120 01:33:41.742531 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:33:41.742623 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:33:41.742702 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:33:41.742785 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:33:41.743011 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1
125 01:33:41.743142 makedir: /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin
126 01:33:41.743244 makedir: /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/tests
127 01:33:41.743342 makedir: /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/results
128 01:33:41.743455 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-add-keys
129 01:33:41.743597 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-add-sources
130 01:33:41.743723 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-background-process-start
131 01:33:41.743850 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-background-process-stop
132 01:33:41.743972 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-common-functions
133 01:33:41.744093 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-echo-ipv4
134 01:33:41.744213 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-install-packages
135 01:33:41.744333 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-installed-packages
136 01:33:41.744453 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-os-build
137 01:33:41.744574 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-probe-channel
138 01:33:41.744692 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-probe-ip
139 01:33:41.744812 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-target-ip
140 01:33:41.744932 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-target-mac
141 01:33:41.745051 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-target-storage
142 01:33:41.745175 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-case
143 01:33:41.745299 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-event
144 01:33:41.745452 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-feedback
145 01:33:41.745573 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-raise
146 01:33:41.745691 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-reference
147 01:33:41.745811 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-runner
148 01:33:41.745930 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-set
149 01:33:41.746051 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-test-shell
150 01:33:41.746174 Updating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-install-packages (oe)
151 01:33:41.746322 Updating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/bin/lava-installed-packages (oe)
152 01:33:41.746440 Creating /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/environment
153 01:33:41.746536 LAVA metadata
154 01:33:41.746607 - LAVA_JOB_ID=14173500
155 01:33:41.746667 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:33:41.746766 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:33:41.746831 skipped lava-vland-overlay
158 01:33:41.746902 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:33:41.746982 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:33:41.747046 skipped lava-multinode-overlay
161 01:33:41.747116 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:33:41.747214 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:33:41.747287 Loading test definitions
164 01:33:41.747379 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:33:41.747450 Using /lava-14173500 at stage 0
166 01:33:41.747753 uuid=14173500_1.5.2.3.1 testdef=None
167 01:33:41.747840 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:33:41.747921 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:33:41.748422 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:33:41.748641 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:33:41.749245 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:33:41.749506 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:33:41.750085 runner path: /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/0/tests/0_igt-gpu-panfrost test_uuid 14173500_1.5.2.3.1
176 01:33:41.750243 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:33:41.750445 Creating lava-test-runner.conf files
179 01:33:41.750507 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173500/lava-overlay-x2rhunz1/lava-14173500/0 for stage 0
180 01:33:41.750594 - 0_igt-gpu-panfrost
181 01:33:41.750688 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:33:41.750773 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:33:41.757778 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:33:41.757878 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:33:41.757962 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:33:41.758044 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:33:41.758127 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:33:43.470533 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 01:33:43.470904 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 01:33:43.471023 extracting modules file /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173500/extract-overlay-ramdisk-gto6qi6n/ramdisk
191 01:33:43.691086 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:33:43.691258 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 01:33:43.691347 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173500/compress-overlay-i2acfzsk/overlay-1.5.2.4.tar.gz to ramdisk
194 01:33:43.691420 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173500/compress-overlay-i2acfzsk/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173500/extract-overlay-ramdisk-gto6qi6n/ramdisk
195 01:33:43.698039 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:33:43.698161 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 01:33:43.698252 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:33:43.698343 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 01:33:43.698421 Building ramdisk /var/lib/lava/dispatcher/tmp/14173500/extract-overlay-ramdisk-gto6qi6n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173500/extract-overlay-ramdisk-gto6qi6n/ramdisk
200 01:33:44.926017 >> 465931 blocks
201 01:33:51.183416 rename /var/lib/lava/dispatcher/tmp/14173500/extract-overlay-ramdisk-gto6qi6n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/ramdisk/ramdisk.cpio.gz
202 01:33:51.183908 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 01:33:51.184030 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 01:33:51.184129 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 01:33:51.184232 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/kernel/Image']
206 01:34:03.959142 Returned 0 in 12 seconds
207 01:34:04.060150 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/kernel/image.itb
208 01:34:04.936035 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:34:04.936401 output: Created: Wed Jun 5 02:34:04 2024
210 01:34:04.936471 output: Image 0 (kernel-1)
211 01:34:04.936534 output: Description:
212 01:34:04.936593 output: Created: Wed Jun 5 02:34:04 2024
213 01:34:04.936653 output: Type: Kernel Image
214 01:34:04.936714 output: Compression: lzma compressed
215 01:34:04.936773 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
216 01:34:04.936832 output: Architecture: AArch64
217 01:34:04.936888 output: OS: Linux
218 01:34:04.936948 output: Load Address: 0x00000000
219 01:34:04.937007 output: Entry Point: 0x00000000
220 01:34:04.937064 output: Hash algo: crc32
221 01:34:04.937118 output: Hash value: 4c96ec19
222 01:34:04.937175 output: Image 1 (fdt-1)
223 01:34:04.937229 output: Description: mt8192-asurada-spherion-r0
224 01:34:04.937281 output: Created: Wed Jun 5 02:34:04 2024
225 01:34:04.937393 output: Type: Flat Device Tree
226 01:34:04.937445 output: Compression: uncompressed
227 01:34:04.937497 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 01:34:04.937549 output: Architecture: AArch64
229 01:34:04.937600 output: Hash algo: crc32
230 01:34:04.937651 output: Hash value: 0f8e4d2e
231 01:34:04.937703 output: Image 2 (ramdisk-1)
232 01:34:04.937754 output: Description: unavailable
233 01:34:04.937806 output: Created: Wed Jun 5 02:34:04 2024
234 01:34:04.937858 output: Type: RAMDisk Image
235 01:34:04.937910 output: Compression: Unknown Compression
236 01:34:04.937961 output: Data Size: 60988320 Bytes = 59558.91 KiB = 58.16 MiB
237 01:34:04.938013 output: Architecture: AArch64
238 01:34:04.938064 output: OS: Linux
239 01:34:04.938116 output: Load Address: unavailable
240 01:34:04.938168 output: Entry Point: unavailable
241 01:34:04.938219 output: Hash algo: crc32
242 01:34:04.938270 output: Hash value: 4de75184
243 01:34:04.938322 output: Default Configuration: 'conf-1'
244 01:34:04.938373 output: Configuration 0 (conf-1)
245 01:34:04.938425 output: Description: mt8192-asurada-spherion-r0
246 01:34:04.938477 output: Kernel: kernel-1
247 01:34:04.938527 output: Init Ramdisk: ramdisk-1
248 01:34:04.938579 output: FDT: fdt-1
249 01:34:04.938630 output: Loadables: kernel-1
250 01:34:04.938681 output:
251 01:34:04.938875 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:34:04.938962 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:34:04.939071 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 01:34:04.939164 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 01:34:04.939245 No LXC device requested
256 01:34:04.939324 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:34:04.939405 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 01:34:04.939481 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:34:04.939550 Checking files for TFTP limit of 4294967296 bytes.
260 01:34:04.940046 end: 1 tftp-deploy (duration 00:00:24) [common]
261 01:34:04.940146 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:34:04.940236 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:34:04.940355 substitutions:
264 01:34:04.940420 - {DTB}: 14173500/tftp-deploy-70c7jjut/dtb/mt8192-asurada-spherion-r0.dtb
265 01:34:04.940482 - {INITRD}: 14173500/tftp-deploy-70c7jjut/ramdisk/ramdisk.cpio.gz
266 01:34:04.940542 - {KERNEL}: 14173500/tftp-deploy-70c7jjut/kernel/Image
267 01:34:04.940599 - {LAVA_MAC}: None
268 01:34:04.940655 - {PRESEED_CONFIG}: None
269 01:34:04.940710 - {PRESEED_LOCAL}: None
270 01:34:04.940765 - {RAMDISK}: 14173500/tftp-deploy-70c7jjut/ramdisk/ramdisk.cpio.gz
271 01:34:04.940819 - {ROOT_PART}: None
272 01:34:04.940874 - {ROOT}: None
273 01:34:04.940927 - {SERVER_IP}: 192.168.201.1
274 01:34:04.940979 - {TEE}: None
275 01:34:04.941033 Parsed boot commands:
276 01:34:04.941085 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:34:04.941258 Parsed boot commands: tftpboot 192.168.201.1 14173500/tftp-deploy-70c7jjut/kernel/image.itb 14173500/tftp-deploy-70c7jjut/kernel/cmdline
278 01:34:04.941407 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:34:04.941491 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:34:04.941578 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:34:04.941665 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:34:04.941739 Not connected, no need to disconnect.
283 01:34:04.941812 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:34:04.941894 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:34:04.941960 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 01:34:04.945530 Setting prompt string to ['lava-test: # ']
287 01:34:04.945882 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:34:04.945985 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:34:04.946096 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:34:04.946209 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:34:04.946472 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 01:34:10.096703 >> Command sent successfully.
293 01:34:10.107972 Returned 0 in 5 seconds
294 01:34:10.209261 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:34:10.210974 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:34:10.211724 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:34:10.212217 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:34:10.212602 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:34:10.212972 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:34:10.215107 [Enter `^Ec?' for help]
302 01:34:10.381013
303 01:34:10.381660
304 01:34:10.382046 F0: 102B 0000
305 01:34:10.382408
306 01:34:10.382755 F3: 1001 0000 [0200]
307 01:34:10.384110
308 01:34:10.384626 F3: 1001 0000
309 01:34:10.385087
310 01:34:10.385497 F7: 102D 0000
311 01:34:10.385840
312 01:34:10.387405 F1: 0000 0000
313 01:34:10.387868
314 01:34:10.388231 V0: 0000 0000 [0001]
315 01:34:10.388572
316 01:34:10.390945 00: 0007 8000
317 01:34:10.391443
318 01:34:10.391830 01: 0000 0000
319 01:34:10.392210
320 01:34:10.393945 BP: 0C00 0209 [0000]
321 01:34:10.394371
322 01:34:10.394710 G0: 1182 0000
323 01:34:10.395068
324 01:34:10.397843 EC: 0000 0021 [4000]
325 01:34:10.398272
326 01:34:10.398613 S7: 0000 0000 [0000]
327 01:34:10.398932
328 01:34:10.400987 CC: 0000 0000 [0001]
329 01:34:10.401560
330 01:34:10.401902 T0: 0000 0040 [010F]
331 01:34:10.402218
332 01:34:10.402516 Jump to BL
333 01:34:10.404152
334 01:34:10.427956
335 01:34:10.428484
336 01:34:10.435075 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 01:34:10.438539 ARM64: Exception handlers installed.
338 01:34:10.442096 ARM64: Testing exception
339 01:34:10.445361 ARM64: Done test exception
340 01:34:10.451923 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 01:34:10.462231 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 01:34:10.469121 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 01:34:10.478996 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 01:34:10.485713 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 01:34:10.492457 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 01:34:10.504085 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 01:34:10.511138 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 01:34:10.530474 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 01:34:10.533668 WDT: Last reset was cold boot
350 01:34:10.536944 SPI1(PAD0) initialized at 2873684 Hz
351 01:34:10.540715 SPI5(PAD0) initialized at 992727 Hz
352 01:34:10.543943 VBOOT: Loading verstage.
353 01:34:10.550332 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 01:34:10.553462 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 01:34:10.556966 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 01:34:10.560311 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 01:34:10.567955 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 01:34:10.574612 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 01:34:10.585315 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 01:34:10.585552
361 01:34:10.585687
362 01:34:10.595666 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 01:34:10.599101 ARM64: Exception handlers installed.
364 01:34:10.602141 ARM64: Testing exception
365 01:34:10.602432 ARM64: Done test exception
366 01:34:10.609214 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 01:34:10.612398 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 01:34:10.626704 Probing TPM: . done!
369 01:34:10.627263 TPM ready after 0 ms
370 01:34:10.634336 Connected to device vid:did:rid of 1ae0:0028:00
371 01:34:10.640872 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 01:34:10.689691 Initialized TPM device CR50 revision 0
373 01:34:10.704646 tlcl_send_startup: Startup return code is 0
374 01:34:10.705211 TPM: setup succeeded
375 01:34:10.715133 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 01:34:10.724423 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 01:34:10.733490 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 01:34:10.742996 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 01:34:10.746211 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 01:34:10.749663 in-header: 03 07 00 00 08 00 00 00
381 01:34:10.752726 in-data: aa e4 47 04 13 02 00 00
382 01:34:10.756139 Chrome EC: UHEPI supported
383 01:34:10.762400 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 01:34:10.765887 in-header: 03 95 00 00 08 00 00 00
385 01:34:10.769575 in-data: 18 20 20 08 00 00 00 00
386 01:34:10.770045 Phase 1
387 01:34:10.773588 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 01:34:10.780741 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 01:34:10.784242 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 01:34:10.788129 Recovery requested (1009000e)
391 01:34:10.797363 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 01:34:10.803077 tlcl_extend: response is 0
393 01:34:10.812623 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 01:34:10.818408 tlcl_extend: response is 0
395 01:34:10.825019 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 01:34:10.845559 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 01:34:10.853372 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 01:34:10.853937
399 01:34:10.854474
400 01:34:10.860182 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 01:34:10.863949 ARM64: Exception handlers installed.
402 01:34:10.867654 ARM64: Testing exception
403 01:34:10.870965 ARM64: Done test exception
404 01:34:10.890295 pmic_efuse_setting: Set efuses in 11 msecs
405 01:34:10.893844 pmwrap_interface_init: Select PMIF_VLD_RDY
406 01:34:10.900402 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 01:34:10.903975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 01:34:10.910326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 01:34:10.913881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 01:34:10.920463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 01:34:10.924089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 01:34:10.926926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 01:34:10.933735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 01:34:10.936899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 01:34:10.943521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 01:34:10.947002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 01:34:10.950347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 01:34:10.957022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 01:34:10.963732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 01:34:10.967515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 01:34:10.974689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 01:34:10.978119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 01:34:10.985596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 01:34:10.993027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 01:34:10.996485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 01:34:11.003849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 01:34:11.007527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 01:34:11.014994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 01:34:11.018615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 01:34:11.026220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 01:34:11.029597 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 01:34:11.033256 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 01:34:11.040786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 01:34:11.044215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 01:34:11.048068 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 01:34:11.055046 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 01:34:11.058596 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 01:34:11.065810 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 01:34:11.069603 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 01:34:11.073375 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 01:34:11.080873 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 01:34:11.084559 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 01:34:11.087856 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 01:34:11.094961 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 01:34:11.098514 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 01:34:11.101993 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 01:34:11.105565 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 01:34:11.113091 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 01:34:11.116503 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 01:34:11.120348 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 01:34:11.123572 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 01:34:11.127335 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 01:34:11.134261 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 01:34:11.138250 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 01:34:11.141762 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 01:34:11.145220 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 01:34:11.152484 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 01:34:11.163364 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 01:34:11.167184 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 01:34:11.174653 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 01:34:11.181808 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 01:34:11.189116 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 01:34:11.192945 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 01:34:11.195884 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:34:11.203546 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
466 01:34:11.210380 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 01:34:11.214254 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 01:34:11.217657 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 01:34:11.228085 [RTC]rtc_get_frequency_meter,154: input=15, output=763
470 01:34:11.237741 [RTC]rtc_get_frequency_meter,154: input=23, output=948
471 01:34:11.246900 [RTC]rtc_get_frequency_meter,154: input=19, output=856
472 01:34:11.256514 [RTC]rtc_get_frequency_meter,154: input=17, output=809
473 01:34:11.266385 [RTC]rtc_get_frequency_meter,154: input=16, output=786
474 01:34:11.275735 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 01:34:11.285265 [RTC]rtc_get_frequency_meter,154: input=17, output=809
476 01:34:11.288662 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 01:34:11.295623 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 01:34:11.299523 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 01:34:11.303126 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 01:34:11.306486 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 01:34:11.310189 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 01:34:11.314183 ADC[4]: Raw value=670432 ID=5
483 01:34:11.317843 ADC[3]: Raw value=212917 ID=1
484 01:34:11.318442 RAM Code: 0x51
485 01:34:11.321339 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 01:34:11.328512 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 01:34:11.335925 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 01:34:11.339605 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 01:34:11.343164 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 01:34:11.347473 in-header: 03 07 00 00 08 00 00 00
491 01:34:11.351321 in-data: aa e4 47 04 13 02 00 00
492 01:34:11.354622 Chrome EC: UHEPI supported
493 01:34:11.361695 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 01:34:11.365341 in-header: 03 95 00 00 08 00 00 00
495 01:34:11.368766 in-data: 18 20 20 08 00 00 00 00
496 01:34:11.372345 MRC: failed to locate region type 0.
497 01:34:11.376347 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 01:34:11.379523 DRAM-K: Running full calibration
499 01:34:11.386945 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 01:34:11.387496 header.status = 0x0
501 01:34:11.390660 header.version = 0x6 (expected: 0x6)
502 01:34:11.393889 header.size = 0xd00 (expected: 0xd00)
503 01:34:11.397893 header.flags = 0x0
504 01:34:11.401351 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 01:34:11.420743 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 01:34:11.428275 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 01:34:11.431777 dram_init: ddr_geometry: 0
508 01:34:11.432245 [EMI] MDL number = 0
509 01:34:11.435747 [EMI] Get MDL freq = 0
510 01:34:11.436216 dram_init: ddr_type: 0
511 01:34:11.439381 is_discrete_lpddr4: 1
512 01:34:11.443092 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 01:34:11.443684
514 01:34:11.444112
515 01:34:11.444473 [Bian_co] ETT version 0.0.0.1
516 01:34:11.450047 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 01:34:11.450605
518 01:34:11.453796 dramc_set_vcore_voltage set vcore to 650000
519 01:34:11.454368 Read voltage for 800, 4
520 01:34:11.457352 Vio18 = 0
521 01:34:11.457819 Vcore = 650000
522 01:34:11.458235 Vdram = 0
523 01:34:11.461083 Vddq = 0
524 01:34:11.461615 Vmddr = 0
525 01:34:11.462140 dram_init: config_dvfs: 1
526 01:34:11.468520 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 01:34:11.472418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 01:34:11.476003 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 01:34:11.479614 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 01:34:11.483240 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 01:34:11.486853 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 01:34:11.490531 MEM_TYPE=3, freq_sel=18
533 01:34:11.494582 sv_algorithm_assistance_LP4_1600
534 01:34:11.497704 ============ PULL DRAM RESETB DOWN ============
535 01:34:11.501750 ========== PULL DRAM RESETB DOWN end =========
536 01:34:11.505266 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 01:34:11.509283 ===================================
538 01:34:11.512510 LPDDR4 DRAM CONFIGURATION
539 01:34:11.516627 ===================================
540 01:34:11.517193 EX_ROW_EN[0] = 0x0
541 01:34:11.520300 EX_ROW_EN[1] = 0x0
542 01:34:11.520817 LP4Y_EN = 0x0
543 01:34:11.523750 WORK_FSP = 0x0
544 01:34:11.524241 WL = 0x2
545 01:34:11.527590 RL = 0x2
546 01:34:11.528154 BL = 0x2
547 01:34:11.530849 RPST = 0x0
548 01:34:11.531352 RD_PRE = 0x0
549 01:34:11.534321 WR_PRE = 0x1
550 01:34:11.534825 WR_PST = 0x0
551 01:34:11.538455 DBI_WR = 0x0
552 01:34:11.538938 DBI_RD = 0x0
553 01:34:11.539313 OTF = 0x1
554 01:34:11.541980 ===================================
555 01:34:11.545485 ===================================
556 01:34:11.548855 ANA top config
557 01:34:11.552637 ===================================
558 01:34:11.553255 DLL_ASYNC_EN = 0
559 01:34:11.556228 ALL_SLAVE_EN = 1
560 01:34:11.560001 NEW_RANK_MODE = 1
561 01:34:11.560495 DLL_IDLE_MODE = 1
562 01:34:11.563619 LP45_APHY_COMB_EN = 1
563 01:34:11.567304 TX_ODT_DIS = 1
564 01:34:11.570470 NEW_8X_MODE = 1
565 01:34:11.573963 ===================================
566 01:34:11.577395 ===================================
567 01:34:11.577960 data_rate = 1600
568 01:34:11.580729 CKR = 1
569 01:34:11.584063 DQ_P2S_RATIO = 8
570 01:34:11.587205 ===================================
571 01:34:11.590766 CA_P2S_RATIO = 8
572 01:34:11.594665 DQ_CA_OPEN = 0
573 01:34:11.595134 DQ_SEMI_OPEN = 0
574 01:34:11.598144 CA_SEMI_OPEN = 0
575 01:34:11.601964 CA_FULL_RATE = 0
576 01:34:11.605613 DQ_CKDIV4_EN = 1
577 01:34:11.606083 CA_CKDIV4_EN = 1
578 01:34:11.609198 CA_PREDIV_EN = 0
579 01:34:11.612668 PH8_DLY = 0
580 01:34:11.616337 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 01:34:11.619569 DQ_AAMCK_DIV = 4
582 01:34:11.620139 CA_AAMCK_DIV = 4
583 01:34:11.622653 CA_ADMCK_DIV = 4
584 01:34:11.626075 DQ_TRACK_CA_EN = 0
585 01:34:11.630029 CA_PICK = 800
586 01:34:11.633715 CA_MCKIO = 800
587 01:34:11.634278 MCKIO_SEMI = 0
588 01:34:11.637248 PLL_FREQ = 3068
589 01:34:11.640224 DQ_UI_PI_RATIO = 32
590 01:34:11.643511 CA_UI_PI_RATIO = 0
591 01:34:11.646540 ===================================
592 01:34:11.650695 ===================================
593 01:34:11.653951 memory_type:LPDDR4
594 01:34:11.654421 GP_NUM : 10
595 01:34:11.658147 SRAM_EN : 1
596 01:34:11.658703 MD32_EN : 0
597 01:34:11.661472 ===================================
598 01:34:11.665136 [ANA_INIT] >>>>>>>>>>>>>>
599 01:34:11.668832 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 01:34:11.672437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 01:34:11.672909 ===================================
602 01:34:11.675925 data_rate = 1600,PCW = 0X7600
603 01:34:11.680018 ===================================
604 01:34:11.683582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 01:34:11.687119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 01:34:11.694134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:34:11.697605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 01:34:11.703955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 01:34:11.707192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:34:11.707735 [ANA_INIT] flow start
611 01:34:11.710889 [ANA_INIT] PLL >>>>>>>>
612 01:34:11.713719 [ANA_INIT] PLL <<<<<<<<
613 01:34:11.714185 [ANA_INIT] MIDPI >>>>>>>>
614 01:34:11.716871 [ANA_INIT] MIDPI <<<<<<<<
615 01:34:11.720766 [ANA_INIT] DLL >>>>>>>>
616 01:34:11.721361 [ANA_INIT] flow end
617 01:34:11.723873 ============ LP4 DIFF to SE enter ============
618 01:34:11.730608 ============ LP4 DIFF to SE exit ============
619 01:34:11.731177 [ANA_INIT] <<<<<<<<<<<<<
620 01:34:11.733709 [Flow] Enable top DCM control >>>>>
621 01:34:11.737513 [Flow] Enable top DCM control <<<<<
622 01:34:11.740613 Enable DLL master slave shuffle
623 01:34:11.746969 ==============================================================
624 01:34:11.747440 Gating Mode config
625 01:34:11.753975 ==============================================================
626 01:34:11.757229 Config description:
627 01:34:11.767096 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 01:34:11.773787 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 01:34:11.777347 SELPH_MODE 0: By rank 1: By Phase
630 01:34:11.783904 ==============================================================
631 01:34:11.787084 GAT_TRACK_EN = 1
632 01:34:11.787558 RX_GATING_MODE = 2
633 01:34:11.790309 RX_GATING_TRACK_MODE = 2
634 01:34:11.793969 SELPH_MODE = 1
635 01:34:11.797670 PICG_EARLY_EN = 1
636 01:34:11.800703 VALID_LAT_VALUE = 1
637 01:34:11.807207 ==============================================================
638 01:34:11.810549 Enter into Gating configuration >>>>
639 01:34:11.814077 Exit from Gating configuration <<<<
640 01:34:11.817002 Enter into DVFS_PRE_config >>>>>
641 01:34:11.827033 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 01:34:11.830217 Exit from DVFS_PRE_config <<<<<
643 01:34:11.834188 Enter into PICG configuration >>>>
644 01:34:11.837055 Exit from PICG configuration <<<<
645 01:34:11.840571 [RX_INPUT] configuration >>>>>
646 01:34:11.843593 [RX_INPUT] configuration <<<<<
647 01:34:11.847058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 01:34:11.853761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 01:34:11.860690 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 01:34:11.863689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 01:34:11.870325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 01:34:11.876733 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 01:34:11.880299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 01:34:11.883354 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 01:34:11.890096 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 01:34:11.893272 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 01:34:11.897011 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 01:34:11.903649 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 01:34:11.906746 ===================================
660 01:34:11.907218 LPDDR4 DRAM CONFIGURATION
661 01:34:11.910021 ===================================
662 01:34:11.913725 EX_ROW_EN[0] = 0x0
663 01:34:11.916893 EX_ROW_EN[1] = 0x0
664 01:34:11.917512 LP4Y_EN = 0x0
665 01:34:11.920209 WORK_FSP = 0x0
666 01:34:11.920773 WL = 0x2
667 01:34:11.923721 RL = 0x2
668 01:34:11.924311 BL = 0x2
669 01:34:11.926561 RPST = 0x0
670 01:34:11.927196 RD_PRE = 0x0
671 01:34:11.930004 WR_PRE = 0x1
672 01:34:11.930477 WR_PST = 0x0
673 01:34:11.933521 DBI_WR = 0x0
674 01:34:11.934081 DBI_RD = 0x0
675 01:34:11.936598 OTF = 0x1
676 01:34:11.940286 ===================================
677 01:34:11.943335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 01:34:11.946795 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 01:34:11.950326 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 01:34:11.953845 ===================================
681 01:34:11.956835 LPDDR4 DRAM CONFIGURATION
682 01:34:11.960305 ===================================
683 01:34:11.963713 EX_ROW_EN[0] = 0x10
684 01:34:11.964186 EX_ROW_EN[1] = 0x0
685 01:34:11.966627 LP4Y_EN = 0x0
686 01:34:11.967100 WORK_FSP = 0x0
687 01:34:11.970073 WL = 0x2
688 01:34:11.970545 RL = 0x2
689 01:34:11.973403 BL = 0x2
690 01:34:11.973909 RPST = 0x0
691 01:34:11.976963 RD_PRE = 0x0
692 01:34:11.977472 WR_PRE = 0x1
693 01:34:11.980086 WR_PST = 0x0
694 01:34:11.983394 DBI_WR = 0x0
695 01:34:11.983864 DBI_RD = 0x0
696 01:34:11.986949 OTF = 0x1
697 01:34:11.989967 ===================================
698 01:34:11.993260 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 01:34:11.998898 nWR fixed to 40
700 01:34:12.002051 [ModeRegInit_LP4] CH0 RK0
701 01:34:12.002835 [ModeRegInit_LP4] CH0 RK1
702 01:34:12.005525 [ModeRegInit_LP4] CH1 RK0
703 01:34:12.008575 [ModeRegInit_LP4] CH1 RK1
704 01:34:12.009141 match AC timing 12
705 01:34:12.015530 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 01:34:12.018731 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 01:34:12.022191 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 01:34:12.028537 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 01:34:12.031979 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 01:34:12.035040 [EMI DOE] emi_dcm 0
711 01:34:12.038412 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 01:34:12.038976 ==
713 01:34:12.042219 Dram Type= 6, Freq= 0, CH_0, rank 0
714 01:34:12.045114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 01:34:12.045755 ==
716 01:34:12.051933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 01:34:12.058243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 01:34:12.065927 [CA 0] Center 37 (7~68) winsize 62
719 01:34:12.069206 [CA 1] Center 37 (7~68) winsize 62
720 01:34:12.072760 [CA 2] Center 35 (5~66) winsize 62
721 01:34:12.075944 [CA 3] Center 35 (5~66) winsize 62
722 01:34:12.079590 [CA 4] Center 34 (3~65) winsize 63
723 01:34:12.082408 [CA 5] Center 34 (3~65) winsize 63
724 01:34:12.082883
725 01:34:12.085965 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 01:34:12.086433
727 01:34:12.089232 [CATrainingPosCal] consider 1 rank data
728 01:34:12.092310 u2DelayCellTimex100 = 270/100 ps
729 01:34:12.096064 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
730 01:34:12.099548 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 01:34:12.105854 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 01:34:12.109082 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
733 01:34:12.112772 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
734 01:34:12.116017 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
735 01:34:12.116587
736 01:34:12.119216 CA PerBit enable=1, Macro0, CA PI delay=34
737 01:34:12.119781
738 01:34:12.122693 [CBTSetCACLKResult] CA Dly = 34
739 01:34:12.123259 CS Dly: 5 (0~36)
740 01:34:12.125630 ==
741 01:34:12.126101 Dram Type= 6, Freq= 0, CH_0, rank 1
742 01:34:12.132574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 01:34:12.133140 ==
744 01:34:12.135920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 01:34:12.142253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 01:34:12.151942 [CA 0] Center 37 (7~68) winsize 62
747 01:34:12.155262 [CA 1] Center 37 (6~68) winsize 63
748 01:34:12.158452 [CA 2] Center 35 (5~66) winsize 62
749 01:34:12.161733 [CA 3] Center 35 (5~66) winsize 62
750 01:34:12.165110 [CA 4] Center 34 (3~65) winsize 63
751 01:34:12.168204 [CA 5] Center 34 (3~65) winsize 63
752 01:34:12.168679
753 01:34:12.171880 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 01:34:12.172446
755 01:34:12.175206 [CATrainingPosCal] consider 2 rank data
756 01:34:12.178849 u2DelayCellTimex100 = 270/100 ps
757 01:34:12.181514 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
758 01:34:12.185009 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 01:34:12.192147 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 01:34:12.195272 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 01:34:12.198485 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
762 01:34:12.201910 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
763 01:34:12.202478
764 01:34:12.205232 CA PerBit enable=1, Macro0, CA PI delay=34
765 01:34:12.205845
766 01:34:12.208572 [CBTSetCACLKResult] CA Dly = 34
767 01:34:12.209138 CS Dly: 5 (0~37)
768 01:34:12.209558
769 01:34:12.211726 ----->DramcWriteLeveling(PI) begin...
770 01:34:12.214894 ==
771 01:34:12.218421 Dram Type= 6, Freq= 0, CH_0, rank 0
772 01:34:12.221618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 01:34:12.222093 ==
774 01:34:12.224928 Write leveling (Byte 0): 31 => 31
775 01:34:12.228952 Write leveling (Byte 1): 27 => 27
776 01:34:12.229595 DramcWriteLeveling(PI) end<-----
777 01:34:12.232210
778 01:34:12.232677 ==
779 01:34:12.233051 Dram Type= 6, Freq= 0, CH_0, rank 0
780 01:34:12.239556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 01:34:12.240125 ==
782 01:34:12.240502 [Gating] SW mode calibration
783 01:34:12.246883 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 01:34:12.253425 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 01:34:12.257604 0 6 0 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
786 01:34:12.260702 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
787 01:34:12.267832 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 01:34:12.270722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 01:34:12.273924 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:34:12.280940 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:34:12.284440 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:34:12.287640 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:34:12.294089 0 7 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
794 01:34:12.297599 0 7 4 | B1->B0 | 3b3b 4040 | 1 1 | (0 0) (0 0)
795 01:34:12.300731 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 01:34:12.307625 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 01:34:12.310730 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 01:34:12.313918 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 01:34:12.320781 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 01:34:12.324027 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 01:34:12.327348 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 01:34:12.330693 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
803 01:34:12.337372 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 01:34:12.340846 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 01:34:12.343878 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 01:34:12.350715 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 01:34:12.354107 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 01:34:12.357383 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 01:34:12.363729 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 01:34:12.367041 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 01:34:12.370253 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 01:34:12.377122 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 01:34:12.380720 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 01:34:12.383793 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 01:34:12.390594 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 01:34:12.393894 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 01:34:12.397083 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
818 01:34:12.403829 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 01:34:12.407188 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 01:34:12.410476 Total UI for P1: 0, mck2ui 16
821 01:34:12.413888 best dqsien dly found for B0: ( 0, 10, 2)
822 01:34:12.417453 Total UI for P1: 0, mck2ui 16
823 01:34:12.420672 best dqsien dly found for B1: ( 0, 10, 2)
824 01:34:12.424010 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 01:34:12.427151 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
826 01:34:12.427663
827 01:34:12.430425 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 01:34:12.433977 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 01:34:12.436832 [Gating] SW calibration Done
830 01:34:12.437329 ==
831 01:34:12.440477 Dram Type= 6, Freq= 0, CH_0, rank 0
832 01:34:12.443578 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 01:34:12.446870 ==
834 01:34:12.447336 RX Vref Scan: 0
835 01:34:12.447714
836 01:34:12.450555 RX Vref 0 -> 0, step: 1
837 01:34:12.451117
838 01:34:12.453614 RX Delay -130 -> 252, step: 16
839 01:34:12.457117 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 01:34:12.460129 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 01:34:12.463441 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 01:34:12.466948 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 01:34:12.473379 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 01:34:12.476815 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 01:34:12.480351 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 01:34:12.484056 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 01:34:12.487060 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 01:34:12.490640 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 01:34:12.496983 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 01:34:12.500400 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 01:34:12.503572 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 01:34:12.507165 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 01:34:12.513801 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 01:34:12.517251 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 01:34:12.517855 ==
856 01:34:12.520364 Dram Type= 6, Freq= 0, CH_0, rank 0
857 01:34:12.523479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 01:34:12.524046 ==
859 01:34:12.524421 DQS Delay:
860 01:34:12.527061 DQS0 = 0, DQS1 = 0
861 01:34:12.527529 DQM Delay:
862 01:34:12.530171 DQM0 = 84, DQM1 = 74
863 01:34:12.530866 DQ Delay:
864 01:34:12.533601 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
865 01:34:12.536732 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 01:34:12.540332 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 01:34:12.543114 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 01:34:12.543580
869 01:34:12.543951
870 01:34:12.544291 ==
871 01:34:12.546611 Dram Type= 6, Freq= 0, CH_0, rank 0
872 01:34:12.550241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 01:34:12.553691 ==
874 01:34:12.554252
875 01:34:12.554627
876 01:34:12.554969 TX Vref Scan disable
877 01:34:12.556546 == TX Byte 0 ==
878 01:34:12.560132 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
879 01:34:12.563537 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
880 01:34:12.566666 == TX Byte 1 ==
881 01:34:12.570026 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 01:34:12.573347 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 01:34:12.576569 ==
884 01:34:12.579845 Dram Type= 6, Freq= 0, CH_0, rank 0
885 01:34:12.583294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 01:34:12.583862 ==
887 01:34:12.596007 TX Vref=22, minBit 4, minWin=27, winSum=447
888 01:34:12.599620 TX Vref=24, minBit 0, minWin=27, winSum=445
889 01:34:12.602961 TX Vref=26, minBit 2, minWin=28, winSum=454
890 01:34:12.605960 TX Vref=28, minBit 11, minWin=27, winSum=452
891 01:34:12.609425 TX Vref=30, minBit 0, minWin=28, winSum=453
892 01:34:12.616170 TX Vref=32, minBit 11, minWin=27, winSum=451
893 01:34:12.619411 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 26
894 01:34:12.619979
895 01:34:12.622766 Final TX Range 1 Vref 26
896 01:34:12.623332
897 01:34:12.623707 ==
898 01:34:12.626430 Dram Type= 6, Freq= 0, CH_0, rank 0
899 01:34:12.629674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 01:34:12.630310 ==
901 01:34:12.630708
902 01:34:12.631060
903 01:34:12.632942 TX Vref Scan disable
904 01:34:12.636378 == TX Byte 0 ==
905 01:34:12.639931 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
906 01:34:12.643121 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
907 01:34:12.646785 == TX Byte 1 ==
908 01:34:12.649842 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
909 01:34:12.653092 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
910 01:34:12.653585
911 01:34:12.656423 [DATLAT]
912 01:34:12.656893 Freq=800, CH0 RK0
913 01:34:12.657263
914 01:34:12.659717 DATLAT Default: 0xa
915 01:34:12.660185 0, 0xFFFF, sum = 0
916 01:34:12.662977 1, 0xFFFF, sum = 0
917 01:34:12.663453 2, 0xFFFF, sum = 0
918 01:34:12.666391 3, 0xFFFF, sum = 0
919 01:34:12.666869 4, 0xFFFF, sum = 0
920 01:34:12.669626 5, 0xFFFF, sum = 0
921 01:34:12.670098 6, 0xFFFF, sum = 0
922 01:34:12.673213 7, 0xFFFF, sum = 0
923 01:34:12.673728 8, 0x0, sum = 1
924 01:34:12.676605 9, 0x0, sum = 2
925 01:34:12.677080 10, 0x0, sum = 3
926 01:34:12.679805 11, 0x0, sum = 4
927 01:34:12.680279 best_step = 9
928 01:34:12.680648
929 01:34:12.680996 ==
930 01:34:12.683413 Dram Type= 6, Freq= 0, CH_0, rank 0
931 01:34:12.686543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 01:34:12.689722 ==
933 01:34:12.690189 RX Vref Scan: 1
934 01:34:12.690563
935 01:34:12.692946 Set Vref Range= 32 -> 127
936 01:34:12.693458
937 01:34:12.696192 RX Vref 32 -> 127, step: 1
938 01:34:12.696657
939 01:34:12.697030 RX Delay -111 -> 252, step: 8
940 01:34:12.697425
941 01:34:12.699567 Set Vref, RX VrefLevel [Byte0]: 32
942 01:34:12.702851 [Byte1]: 32
943 01:34:12.706978
944 01:34:12.707443 Set Vref, RX VrefLevel [Byte0]: 33
945 01:34:12.710166 [Byte1]: 33
946 01:34:12.714522
947 01:34:12.714984 Set Vref, RX VrefLevel [Byte0]: 34
948 01:34:12.718230 [Byte1]: 34
949 01:34:12.722472
950 01:34:12.723186 Set Vref, RX VrefLevel [Byte0]: 35
951 01:34:12.725731 [Byte1]: 35
952 01:34:12.730072
953 01:34:12.730542 Set Vref, RX VrefLevel [Byte0]: 36
954 01:34:12.733178 [Byte1]: 36
955 01:34:12.737512
956 01:34:12.737992 Set Vref, RX VrefLevel [Byte0]: 37
957 01:34:12.740996 [Byte1]: 37
958 01:34:12.745457
959 01:34:12.745924 Set Vref, RX VrefLevel [Byte0]: 38
960 01:34:12.748516 [Byte1]: 38
961 01:34:12.753220
962 01:34:12.753809 Set Vref, RX VrefLevel [Byte0]: 39
963 01:34:12.756150 [Byte1]: 39
964 01:34:12.760408
965 01:34:12.760873 Set Vref, RX VrefLevel [Byte0]: 40
966 01:34:12.763853 [Byte1]: 40
967 01:34:12.768019
968 01:34:12.768495 Set Vref, RX VrefLevel [Byte0]: 41
969 01:34:12.771612 [Byte1]: 41
970 01:34:12.775804
971 01:34:12.776386 Set Vref, RX VrefLevel [Byte0]: 42
972 01:34:12.779267 [Byte1]: 42
973 01:34:12.783605
974 01:34:12.784166 Set Vref, RX VrefLevel [Byte0]: 43
975 01:34:12.787047 [Byte1]: 43
976 01:34:12.791104
977 01:34:12.791565 Set Vref, RX VrefLevel [Byte0]: 44
978 01:34:12.794446 [Byte1]: 44
979 01:34:12.798762
980 01:34:12.799228 Set Vref, RX VrefLevel [Byte0]: 45
981 01:34:12.805029 [Byte1]: 45
982 01:34:12.806508
983 01:34:12.807281 Set Vref, RX VrefLevel [Byte0]: 46
984 01:34:12.809616 [Byte1]: 46
985 01:34:12.814198
986 01:34:12.814659 Set Vref, RX VrefLevel [Byte0]: 47
987 01:34:12.817198 [Byte1]: 47
988 01:34:12.821553
989 01:34:12.822018 Set Vref, RX VrefLevel [Byte0]: 48
990 01:34:12.825124 [Byte1]: 48
991 01:34:12.829202
992 01:34:12.829712 Set Vref, RX VrefLevel [Byte0]: 49
993 01:34:12.832741 [Byte1]: 49
994 01:34:12.836768
995 01:34:12.837094 Set Vref, RX VrefLevel [Byte0]: 50
996 01:34:12.843363 [Byte1]: 50
997 01:34:12.843618
998 01:34:12.846398 Set Vref, RX VrefLevel [Byte0]: 51
999 01:34:12.849886 [Byte1]: 51
1000 01:34:12.850076
1001 01:34:12.852993 Set Vref, RX VrefLevel [Byte0]: 52
1002 01:34:12.856120 [Byte1]: 52
1003 01:34:12.859588
1004 01:34:12.859777 Set Vref, RX VrefLevel [Byte0]: 53
1005 01:34:12.862919 [Byte1]: 53
1006 01:34:12.867314
1007 01:34:12.867504 Set Vref, RX VrefLevel [Byte0]: 54
1008 01:34:12.870374 [Byte1]: 54
1009 01:34:12.874851
1010 01:34:12.875041 Set Vref, RX VrefLevel [Byte0]: 55
1011 01:34:12.878103 [Byte1]: 55
1012 01:34:12.882506
1013 01:34:12.882696 Set Vref, RX VrefLevel [Byte0]: 56
1014 01:34:12.885782 [Byte1]: 56
1015 01:34:12.890110
1016 01:34:12.890300 Set Vref, RX VrefLevel [Byte0]: 57
1017 01:34:12.893739 [Byte1]: 57
1018 01:34:12.898049
1019 01:34:12.898240 Set Vref, RX VrefLevel [Byte0]: 58
1020 01:34:12.901592 [Byte1]: 58
1021 01:34:12.906142
1022 01:34:12.906335 Set Vref, RX VrefLevel [Byte0]: 59
1023 01:34:12.909514 [Byte1]: 59
1024 01:34:12.913529
1025 01:34:12.913776 Set Vref, RX VrefLevel [Byte0]: 60
1026 01:34:12.916885 [Byte1]: 60
1027 01:34:12.921212
1028 01:34:12.921383 Set Vref, RX VrefLevel [Byte0]: 61
1029 01:34:12.924411 [Byte1]: 61
1030 01:34:12.928565
1031 01:34:12.928708 Set Vref, RX VrefLevel [Byte0]: 62
1032 01:34:12.931771 [Byte1]: 62
1033 01:34:12.935851
1034 01:34:12.935966 Set Vref, RX VrefLevel [Byte0]: 63
1035 01:34:12.942411 [Byte1]: 63
1036 01:34:12.942528
1037 01:34:12.945724 Set Vref, RX VrefLevel [Byte0]: 64
1038 01:34:12.949162 [Byte1]: 64
1039 01:34:12.949278
1040 01:34:12.952572 Set Vref, RX VrefLevel [Byte0]: 65
1041 01:34:12.955873 [Byte1]: 65
1042 01:34:12.959277
1043 01:34:12.959466 Set Vref, RX VrefLevel [Byte0]: 66
1044 01:34:12.962481 [Byte1]: 66
1045 01:34:12.966789
1046 01:34:12.966964 Set Vref, RX VrefLevel [Byte0]: 67
1047 01:34:12.969860 [Byte1]: 67
1048 01:34:12.974404
1049 01:34:12.974611 Set Vref, RX VrefLevel [Byte0]: 68
1050 01:34:12.977825 [Byte1]: 68
1051 01:34:12.981987
1052 01:34:12.982208 Set Vref, RX VrefLevel [Byte0]: 69
1053 01:34:12.985562 [Byte1]: 69
1054 01:34:12.989819
1055 01:34:12.990090 Set Vref, RX VrefLevel [Byte0]: 70
1056 01:34:12.992970 [Byte1]: 70
1057 01:34:12.997565
1058 01:34:12.997872 Set Vref, RX VrefLevel [Byte0]: 71
1059 01:34:13.000736 [Byte1]: 71
1060 01:34:13.005478
1061 01:34:13.005924 Set Vref, RX VrefLevel [Byte0]: 72
1062 01:34:13.008620 [Byte1]: 72
1063 01:34:13.013111
1064 01:34:13.013703 Set Vref, RX VrefLevel [Byte0]: 73
1065 01:34:13.016625 [Byte1]: 73
1066 01:34:13.020535
1067 01:34:13.021082 Final RX Vref Byte 0 = 53 to rank0
1068 01:34:13.024091 Final RX Vref Byte 1 = 56 to rank0
1069 01:34:13.027116 Final RX Vref Byte 0 = 53 to rank1
1070 01:34:13.030632 Final RX Vref Byte 1 = 56 to rank1==
1071 01:34:13.033610 Dram Type= 6, Freq= 0, CH_0, rank 0
1072 01:34:13.040364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1073 01:34:13.040917 ==
1074 01:34:13.041281 DQS Delay:
1075 01:34:13.041659 DQS0 = 0, DQS1 = 0
1076 01:34:13.044189 DQM Delay:
1077 01:34:13.044733 DQM0 = 83, DQM1 = 73
1078 01:34:13.047045 DQ Delay:
1079 01:34:13.050694 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1080 01:34:13.053768 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1081 01:34:13.054369 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1082 01:34:13.060810 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1083 01:34:13.061411
1084 01:34:13.061832
1085 01:34:13.066923 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1086 01:34:13.070225 CH0 RK0: MR19=606, MR18=3535
1087 01:34:13.077010 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1088 01:34:13.077611
1089 01:34:13.080344 ----->DramcWriteLeveling(PI) begin...
1090 01:34:13.080901 ==
1091 01:34:13.083778 Dram Type= 6, Freq= 0, CH_0, rank 1
1092 01:34:13.087147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 01:34:13.087702 ==
1094 01:34:13.090083 Write leveling (Byte 0): 27 => 27
1095 01:34:13.093364 Write leveling (Byte 1): 27 => 27
1096 01:34:13.096649 DramcWriteLeveling(PI) end<-----
1097 01:34:13.097129
1098 01:34:13.097548 ==
1099 01:34:13.100209 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 01:34:13.103524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 01:34:13.104075 ==
1102 01:34:13.106594 [Gating] SW mode calibration
1103 01:34:13.113411 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1104 01:34:13.120366 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1105 01:34:13.123441 0 6 0 | B1->B0 | 3232 3131 | 1 0 | (1 0) (0 1)
1106 01:34:13.126909 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1107 01:34:13.133388 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 01:34:13.136916 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 01:34:13.140191 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 01:34:13.146479 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 01:34:13.150182 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 01:34:13.153475 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 01:34:13.160118 0 7 0 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
1114 01:34:13.163411 0 7 4 | B1->B0 | 3a3a 4444 | 0 0 | (1 1) (0 0)
1115 01:34:13.166586 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 01:34:13.173259 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 01:34:13.176816 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 01:34:13.180391 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 01:34:13.186537 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 01:34:13.189701 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 01:34:13.193248 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1122 01:34:13.200068 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1123 01:34:13.203575 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 01:34:13.206942 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 01:34:13.213701 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 01:34:13.216631 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 01:34:13.220358 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 01:34:13.223508 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 01:34:13.230168 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 01:34:13.233566 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 01:34:13.236773 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 01:34:13.243439 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 01:34:13.247098 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 01:34:13.249982 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 01:34:13.256895 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 01:34:13.260490 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 01:34:13.263649 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1138 01:34:13.269761 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1139 01:34:13.273236 Total UI for P1: 0, mck2ui 16
1140 01:34:13.276619 best dqsien dly found for B0: ( 0, 10, 0)
1141 01:34:13.277213 Total UI for P1: 0, mck2ui 16
1142 01:34:13.283380 best dqsien dly found for B1: ( 0, 10, 0)
1143 01:34:13.286421 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1144 01:34:13.290088 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1145 01:34:13.290629
1146 01:34:13.293389 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1147 01:34:13.296736 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1148 01:34:13.299685 [Gating] SW calibration Done
1149 01:34:13.300137 ==
1150 01:34:13.303182 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 01:34:13.347502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1152 01:34:13.348081 ==
1153 01:34:13.348456 RX Vref Scan: 0
1154 01:34:13.348836
1155 01:34:13.349164 RX Vref 0 -> 0, step: 1
1156 01:34:13.349626
1157 01:34:13.350108 RX Delay -130 -> 252, step: 16
1158 01:34:13.350583 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1159 01:34:13.351427 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1160 01:34:13.351779 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1161 01:34:13.352093 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1162 01:34:13.352398 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1163 01:34:13.352702 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1164 01:34:13.353005 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1165 01:34:13.353352 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1166 01:34:13.353723 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1167 01:34:13.355025 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1168 01:34:13.358240 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1169 01:34:13.361754 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1170 01:34:13.365011 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1171 01:34:13.368313 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1172 01:34:13.375388 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1173 01:34:13.378551 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1174 01:34:13.379013 ==
1175 01:34:13.381951 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 01:34:13.385722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1177 01:34:13.386460 ==
1178 01:34:13.388658 DQS Delay:
1179 01:34:13.389114 DQS0 = 0, DQS1 = 0
1180 01:34:13.389531 DQM Delay:
1181 01:34:13.391618 DQM0 = 81, DQM1 = 72
1182 01:34:13.392069 DQ Delay:
1183 01:34:13.395002 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =69
1184 01:34:13.398790 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
1185 01:34:13.401974 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1186 01:34:13.405284 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1187 01:34:13.405774
1188 01:34:13.406192
1189 01:34:13.406530 ==
1190 01:34:13.408696 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 01:34:13.415410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1192 01:34:13.415957 ==
1193 01:34:13.416319
1194 01:34:13.416650
1195 01:34:13.416970 TX Vref Scan disable
1196 01:34:13.418468 == TX Byte 0 ==
1197 01:34:13.421779 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1198 01:34:13.428380 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1199 01:34:13.428935 == TX Byte 1 ==
1200 01:34:13.431993 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1201 01:34:13.438599 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1202 01:34:13.439153 ==
1203 01:34:13.441930 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 01:34:13.445077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1205 01:34:13.445678 ==
1206 01:34:13.457804 TX Vref=22, minBit 0, minWin=27, winSum=439
1207 01:34:13.460876 TX Vref=24, minBit 6, minWin=27, winSum=445
1208 01:34:13.463931 TX Vref=26, minBit 2, minWin=28, winSum=453
1209 01:34:13.467612 TX Vref=28, minBit 0, minWin=28, winSum=458
1210 01:34:13.470581 TX Vref=30, minBit 2, minWin=28, winSum=458
1211 01:34:13.474253 TX Vref=32, minBit 0, minWin=28, winSum=455
1212 01:34:13.481877 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1213 01:34:13.482504
1214 01:34:13.486275 Final TX Range 1 Vref 28
1215 01:34:13.486989
1216 01:34:13.487365 ==
1217 01:34:13.489411 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 01:34:13.492764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1219 01:34:13.493388 ==
1220 01:34:13.493767
1221 01:34:13.494172
1222 01:34:13.495942 TX Vref Scan disable
1223 01:34:13.496578 == TX Byte 0 ==
1224 01:34:13.503029 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1225 01:34:13.506446 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1226 01:34:13.506900 == TX Byte 1 ==
1227 01:34:13.509959 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1228 01:34:13.516813 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1229 01:34:13.517418
1230 01:34:13.517782 [DATLAT]
1231 01:34:13.519916 Freq=800, CH0 RK1
1232 01:34:13.520367
1233 01:34:13.520866 DATLAT Default: 0x9
1234 01:34:13.522966 0, 0xFFFF, sum = 0
1235 01:34:13.523421 1, 0xFFFF, sum = 0
1236 01:34:13.526678 2, 0xFFFF, sum = 0
1237 01:34:13.527237 3, 0xFFFF, sum = 0
1238 01:34:13.529657 4, 0xFFFF, sum = 0
1239 01:34:13.530115 5, 0xFFFF, sum = 0
1240 01:34:13.532843 6, 0xFFFF, sum = 0
1241 01:34:13.533332 7, 0xFFFF, sum = 0
1242 01:34:13.536374 8, 0x0, sum = 1
1243 01:34:13.536828 9, 0x0, sum = 2
1244 01:34:13.539631 10, 0x0, sum = 3
1245 01:34:13.540088 11, 0x0, sum = 4
1246 01:34:13.540456 best_step = 9
1247 01:34:13.543181
1248 01:34:13.543731 ==
1249 01:34:13.546665 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 01:34:13.549793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1251 01:34:13.550345 ==
1252 01:34:13.550709 RX Vref Scan: 0
1253 01:34:13.551042
1254 01:34:13.553247 RX Vref 0 -> 0, step: 1
1255 01:34:13.553845
1256 01:34:13.556323 RX Delay -111 -> 252, step: 8
1257 01:34:13.559707 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1258 01:34:13.566499 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1259 01:34:13.569670 iDelay=217, Bit 2, Center 84 (-39 ~ 208) 248
1260 01:34:13.572677 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1261 01:34:13.576292 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1262 01:34:13.580149 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1263 01:34:13.586233 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1264 01:34:13.589227 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1265 01:34:13.592889 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1266 01:34:13.596001 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1267 01:34:13.599421 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1268 01:34:13.606193 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1269 01:34:13.609166 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1270 01:34:13.612619 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1271 01:34:13.616443 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1272 01:34:13.622779 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1273 01:34:13.623369 ==
1274 01:34:13.626111 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 01:34:13.629132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1276 01:34:13.629630 ==
1277 01:34:13.629989 DQS Delay:
1278 01:34:13.632746 DQS0 = 0, DQS1 = 0
1279 01:34:13.633488 DQM Delay:
1280 01:34:13.635941 DQM0 = 85, DQM1 = 74
1281 01:34:13.636393 DQ Delay:
1282 01:34:13.639400 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1283 01:34:13.642647 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1284 01:34:13.645820 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1285 01:34:13.649355 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1286 01:34:13.649915
1287 01:34:13.650281
1288 01:34:13.656048 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1289 01:34:13.659235 CH0 RK1: MR19=606, MR18=4343
1290 01:34:13.665956 CH0_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1291 01:34:13.669261 [RxdqsGatingPostProcess] freq 800
1292 01:34:13.676033 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1293 01:34:13.676488 Pre-setting of DQS Precalculation
1294 01:34:13.682576 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1295 01:34:13.683023 ==
1296 01:34:13.685702 Dram Type= 6, Freq= 0, CH_1, rank 0
1297 01:34:13.688960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1298 01:34:13.689451 ==
1299 01:34:13.695771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1300 01:34:13.702401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1301 01:34:13.709899 [CA 0] Center 37 (6~68) winsize 63
1302 01:34:13.713547 [CA 1] Center 37 (6~68) winsize 63
1303 01:34:13.716671 [CA 2] Center 34 (4~65) winsize 62
1304 01:34:13.719953 [CA 3] Center 34 (4~65) winsize 62
1305 01:34:13.723544 [CA 4] Center 33 (3~64) winsize 62
1306 01:34:13.726918 [CA 5] Center 33 (3~64) winsize 62
1307 01:34:13.727344
1308 01:34:13.729992 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1309 01:34:13.730442
1310 01:34:13.733270 [CATrainingPosCal] consider 1 rank data
1311 01:34:13.736916 u2DelayCellTimex100 = 270/100 ps
1312 01:34:13.739732 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1313 01:34:13.743507 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1314 01:34:13.749840 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1315 01:34:13.753534 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 01:34:13.756675 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1317 01:34:13.759681 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1318 01:34:13.760129
1319 01:34:13.763039 CA PerBit enable=1, Macro0, CA PI delay=33
1320 01:34:13.763488
1321 01:34:13.766625 [CBTSetCACLKResult] CA Dly = 33
1322 01:34:13.767170 CS Dly: 4 (0~35)
1323 01:34:13.770240 ==
1324 01:34:13.770791 Dram Type= 6, Freq= 0, CH_1, rank 1
1325 01:34:13.776542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1326 01:34:13.777092 ==
1327 01:34:13.780258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1328 01:34:13.786787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1329 01:34:13.796011 [CA 0] Center 36 (6~67) winsize 62
1330 01:34:13.799289 [CA 1] Center 37 (6~68) winsize 63
1331 01:34:13.802505 [CA 2] Center 34 (4~65) winsize 62
1332 01:34:13.805992 [CA 3] Center 34 (4~65) winsize 62
1333 01:34:13.809018 [CA 4] Center 33 (3~64) winsize 62
1334 01:34:13.812664 [CA 5] Center 33 (3~64) winsize 62
1335 01:34:13.813212
1336 01:34:13.815915 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1337 01:34:13.816470
1338 01:34:13.819387 [CATrainingPosCal] consider 2 rank data
1339 01:34:13.822388 u2DelayCellTimex100 = 270/100 ps
1340 01:34:13.825733 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1341 01:34:13.828996 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1342 01:34:13.835712 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1343 01:34:13.839010 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1344 01:34:13.842287 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1345 01:34:13.845805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1346 01:34:13.846344
1347 01:34:13.848904 CA PerBit enable=1, Macro0, CA PI delay=33
1348 01:34:13.849544
1349 01:34:13.852294 [CBTSetCACLKResult] CA Dly = 33
1350 01:34:13.852745 CS Dly: 4 (0~36)
1351 01:34:13.853119
1352 01:34:13.855700 ----->DramcWriteLeveling(PI) begin...
1353 01:34:13.858804 ==
1354 01:34:13.862147 Dram Type= 6, Freq= 0, CH_1, rank 0
1355 01:34:13.865437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1356 01:34:13.865893 ==
1357 01:34:13.869019 Write leveling (Byte 0): 25 => 25
1358 01:34:13.872376 Write leveling (Byte 1): 25 => 25
1359 01:34:13.875654 DramcWriteLeveling(PI) end<-----
1360 01:34:13.876105
1361 01:34:13.876461 ==
1362 01:34:13.878737 Dram Type= 6, Freq= 0, CH_1, rank 0
1363 01:34:13.882105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1364 01:34:13.882808 ==
1365 01:34:13.885457 [Gating] SW mode calibration
1366 01:34:13.892165 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1367 01:34:13.895667 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1368 01:34:13.902106 0 6 0 | B1->B0 | 3030 2929 | 1 0 | (1 0) (1 1)
1369 01:34:13.905400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1370 01:34:13.908892 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 01:34:13.915514 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 01:34:13.918918 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 01:34:13.922257 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 01:34:13.928669 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 01:34:13.931994 0 6 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1376 01:34:13.935913 0 7 0 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
1377 01:34:13.941948 0 7 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
1378 01:34:13.945470 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1379 01:34:13.948694 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 01:34:13.955424 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 01:34:13.958553 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 01:34:13.962370 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 01:34:13.968898 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 01:34:13.971814 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1385 01:34:13.975150 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 01:34:13.981745 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 01:34:13.985094 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 01:34:13.988505 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 01:34:13.995413 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 01:34:13.998411 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 01:34:14.002125 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 01:34:14.008704 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 01:34:14.011698 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 01:34:14.015276 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 01:34:14.018412 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 01:34:14.025267 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 01:34:14.028465 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 01:34:14.031964 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 01:34:14.038655 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1400 01:34:14.041903 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1401 01:34:14.045222 Total UI for P1: 0, mck2ui 16
1402 01:34:14.048429 best dqsien dly found for B1: ( 0, 9, 28)
1403 01:34:14.051734 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1404 01:34:14.055541 Total UI for P1: 0, mck2ui 16
1405 01:34:14.058400 best dqsien dly found for B0: ( 0, 9, 30)
1406 01:34:14.061762 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1407 01:34:14.065018 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1408 01:34:14.065573
1409 01:34:14.071970 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1410 01:34:14.074979 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1411 01:34:14.078360 [Gating] SW calibration Done
1412 01:34:14.078825 ==
1413 01:34:14.081616 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 01:34:14.085553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1415 01:34:14.086138 ==
1416 01:34:14.086509 RX Vref Scan: 0
1417 01:34:14.086849
1418 01:34:14.088502 RX Vref 0 -> 0, step: 1
1419 01:34:14.088959
1420 01:34:14.091829 RX Delay -130 -> 252, step: 16
1421 01:34:14.095075 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1422 01:34:14.098372 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1423 01:34:14.104805 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1424 01:34:14.107970 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1425 01:34:14.111505 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1426 01:34:14.114896 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1427 01:34:14.118122 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1428 01:34:14.124958 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1429 01:34:14.128531 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1430 01:34:14.131477 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1431 01:34:14.134877 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1432 01:34:14.138262 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1433 01:34:14.142430 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1434 01:34:14.149579 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1435 01:34:14.152986 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1436 01:34:14.156629 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1437 01:34:14.157090 ==
1438 01:34:14.160351 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 01:34:14.164107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1440 01:34:14.164715 ==
1441 01:34:14.165328 DQS Delay:
1442 01:34:14.167702 DQS0 = 0, DQS1 = 0
1443 01:34:14.168154 DQM Delay:
1444 01:34:14.171710 DQM0 = 80, DQM1 = 72
1445 01:34:14.172214 DQ Delay:
1446 01:34:14.175115 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1447 01:34:14.175840 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1448 01:34:14.178478 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1449 01:34:14.181936 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1450 01:34:14.185251
1451 01:34:14.185744
1452 01:34:14.186173 ==
1453 01:34:14.188490 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 01:34:14.191844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1455 01:34:14.192324 ==
1456 01:34:14.192689
1457 01:34:14.193025
1458 01:34:14.195093 TX Vref Scan disable
1459 01:34:14.195546 == TX Byte 0 ==
1460 01:34:14.201814 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1461 01:34:14.205149 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1462 01:34:14.205779 == TX Byte 1 ==
1463 01:34:14.211734 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1464 01:34:14.215146 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1465 01:34:14.215699 ==
1466 01:34:14.218415 Dram Type= 6, Freq= 0, CH_1, rank 0
1467 01:34:14.221407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1468 01:34:14.221872 ==
1469 01:34:14.235014 TX Vref=22, minBit 3, minWin=27, winSum=445
1470 01:34:14.238689 TX Vref=24, minBit 3, minWin=27, winSum=450
1471 01:34:14.242063 TX Vref=26, minBit 3, minWin=27, winSum=450
1472 01:34:14.245453 TX Vref=28, minBit 0, minWin=28, winSum=461
1473 01:34:14.248509 TX Vref=30, minBit 0, minWin=28, winSum=459
1474 01:34:14.251745 TX Vref=32, minBit 9, minWin=27, winSum=457
1475 01:34:14.258541 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 28
1476 01:34:14.259079
1477 01:34:14.261782 Final TX Range 1 Vref 28
1478 01:34:14.262242
1479 01:34:14.262602 ==
1480 01:34:14.265451 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 01:34:14.268532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 01:34:14.268992 ==
1483 01:34:14.269417
1484 01:34:14.271701
1485 01:34:14.272156 TX Vref Scan disable
1486 01:34:14.275408 == TX Byte 0 ==
1487 01:34:14.278200 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1488 01:34:14.281636 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1489 01:34:14.284934 == TX Byte 1 ==
1490 01:34:14.288485 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1491 01:34:14.294814 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1492 01:34:14.295280
1493 01:34:14.295640 [DATLAT]
1494 01:34:14.295977 Freq=800, CH1 RK0
1495 01:34:14.296301
1496 01:34:14.298202 DATLAT Default: 0xa
1497 01:34:14.298660 0, 0xFFFF, sum = 0
1498 01:34:14.301588 1, 0xFFFF, sum = 0
1499 01:34:14.302048 2, 0xFFFF, sum = 0
1500 01:34:14.304996 3, 0xFFFF, sum = 0
1501 01:34:14.308581 4, 0xFFFF, sum = 0
1502 01:34:14.309152 5, 0xFFFF, sum = 0
1503 01:34:14.311596 6, 0xFFFF, sum = 0
1504 01:34:14.312156 7, 0xFFFF, sum = 0
1505 01:34:14.315043 8, 0x0, sum = 1
1506 01:34:14.315602 9, 0x0, sum = 2
1507 01:34:14.315977 10, 0x0, sum = 3
1508 01:34:14.318113 11, 0x0, sum = 4
1509 01:34:14.318576 best_step = 9
1510 01:34:14.318938
1511 01:34:14.319275 ==
1512 01:34:14.321875 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 01:34:14.328247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1514 01:34:14.328798 ==
1515 01:34:14.329214 RX Vref Scan: 1
1516 01:34:14.329624
1517 01:34:14.331265 Set Vref Range= 32 -> 127
1518 01:34:14.331722
1519 01:34:14.334855 RX Vref 32 -> 127, step: 1
1520 01:34:14.335403
1521 01:34:14.338207 RX Delay -111 -> 252, step: 8
1522 01:34:14.338763
1523 01:34:14.341512 Set Vref, RX VrefLevel [Byte0]: 32
1524 01:34:14.344786 [Byte1]: 32
1525 01:34:14.345362
1526 01:34:14.348094 Set Vref, RX VrefLevel [Byte0]: 33
1527 01:34:14.351620 [Byte1]: 33
1528 01:34:14.352079
1529 01:34:14.354913 Set Vref, RX VrefLevel [Byte0]: 34
1530 01:34:14.358131 [Byte1]: 34
1531 01:34:14.361138
1532 01:34:14.361641 Set Vref, RX VrefLevel [Byte0]: 35
1533 01:34:14.364713 [Byte1]: 35
1534 01:34:14.369254
1535 01:34:14.369845 Set Vref, RX VrefLevel [Byte0]: 36
1536 01:34:14.372374 [Byte1]: 36
1537 01:34:14.376668
1538 01:34:14.377518 Set Vref, RX VrefLevel [Byte0]: 37
1539 01:34:14.379769 [Byte1]: 37
1540 01:34:14.384377
1541 01:34:14.384842 Set Vref, RX VrefLevel [Byte0]: 38
1542 01:34:14.387599 [Byte1]: 38
1543 01:34:14.391653
1544 01:34:14.392147 Set Vref, RX VrefLevel [Byte0]: 39
1545 01:34:14.395256 [Byte1]: 39
1546 01:34:14.399742
1547 01:34:14.400301 Set Vref, RX VrefLevel [Byte0]: 40
1548 01:34:14.406123 [Byte1]: 40
1549 01:34:14.406665
1550 01:34:14.409449 Set Vref, RX VrefLevel [Byte0]: 41
1551 01:34:14.412528 [Byte1]: 41
1552 01:34:14.412981
1553 01:34:14.416121 Set Vref, RX VrefLevel [Byte0]: 42
1554 01:34:14.419396 [Byte1]: 42
1555 01:34:14.419852
1556 01:34:14.422862 Set Vref, RX VrefLevel [Byte0]: 43
1557 01:34:14.425997 [Byte1]: 43
1558 01:34:14.430054
1559 01:34:14.430502 Set Vref, RX VrefLevel [Byte0]: 44
1560 01:34:14.434187 [Byte1]: 44
1561 01:34:14.437901
1562 01:34:14.438451 Set Vref, RX VrefLevel [Byte0]: 45
1563 01:34:14.441493 [Byte1]: 45
1564 01:34:14.445534
1565 01:34:14.446135 Set Vref, RX VrefLevel [Byte0]: 46
1566 01:34:14.448772 [Byte1]: 46
1567 01:34:14.453224
1568 01:34:14.453828 Set Vref, RX VrefLevel [Byte0]: 47
1569 01:34:14.456836 [Byte1]: 47
1570 01:34:14.461247
1571 01:34:14.461841 Set Vref, RX VrefLevel [Byte0]: 48
1572 01:34:14.464220 [Byte1]: 48
1573 01:34:14.468569
1574 01:34:14.469120 Set Vref, RX VrefLevel [Byte0]: 49
1575 01:34:14.471710 [Byte1]: 49
1576 01:34:14.475850
1577 01:34:14.476300 Set Vref, RX VrefLevel [Byte0]: 50
1578 01:34:14.479437 [Byte1]: 50
1579 01:34:14.483456
1580 01:34:14.483905 Set Vref, RX VrefLevel [Byte0]: 51
1581 01:34:14.487054 [Byte1]: 51
1582 01:34:14.491685
1583 01:34:14.492361 Set Vref, RX VrefLevel [Byte0]: 52
1584 01:34:14.494958 [Byte1]: 52
1585 01:34:14.499143
1586 01:34:14.499691 Set Vref, RX VrefLevel [Byte0]: 53
1587 01:34:14.502904 [Byte1]: 53
1588 01:34:14.506461
1589 01:34:14.506912 Set Vref, RX VrefLevel [Byte0]: 54
1590 01:34:14.510206 [Byte1]: 54
1591 01:34:14.514136
1592 01:34:14.514586 Set Vref, RX VrefLevel [Byte0]: 55
1593 01:34:14.517505 [Byte1]: 55
1594 01:34:14.521776
1595 01:34:14.522278 Set Vref, RX VrefLevel [Byte0]: 56
1596 01:34:14.525418 [Byte1]: 56
1597 01:34:14.529610
1598 01:34:14.530061 Set Vref, RX VrefLevel [Byte0]: 57
1599 01:34:14.533044 [Byte1]: 57
1600 01:34:14.537031
1601 01:34:14.537527 Set Vref, RX VrefLevel [Byte0]: 58
1602 01:34:14.540729 [Byte1]: 58
1603 01:34:14.544709
1604 01:34:14.545175 Set Vref, RX VrefLevel [Byte0]: 59
1605 01:34:14.548478 [Byte1]: 59
1606 01:34:14.552491
1607 01:34:14.552948 Set Vref, RX VrefLevel [Byte0]: 60
1608 01:34:14.555714 [Byte1]: 60
1609 01:34:14.560315
1610 01:34:14.560865 Set Vref, RX VrefLevel [Byte0]: 61
1611 01:34:14.563548 [Byte1]: 61
1612 01:34:14.568055
1613 01:34:14.568599 Set Vref, RX VrefLevel [Byte0]: 62
1614 01:34:14.570873 [Byte1]: 62
1615 01:34:14.575600
1616 01:34:14.576051 Set Vref, RX VrefLevel [Byte0]: 63
1617 01:34:14.578567 [Byte1]: 63
1618 01:34:14.582954
1619 01:34:14.583402 Set Vref, RX VrefLevel [Byte0]: 64
1620 01:34:14.586195 [Byte1]: 64
1621 01:34:14.590714
1622 01:34:14.591165 Set Vref, RX VrefLevel [Byte0]: 65
1623 01:34:14.593879 [Byte1]: 65
1624 01:34:14.598408
1625 01:34:14.598996 Set Vref, RX VrefLevel [Byte0]: 66
1626 01:34:14.601500 [Byte1]: 66
1627 01:34:14.605875
1628 01:34:14.606323 Set Vref, RX VrefLevel [Byte0]: 67
1629 01:34:14.609598 [Byte1]: 67
1630 01:34:14.613592
1631 01:34:14.614037 Set Vref, RX VrefLevel [Byte0]: 68
1632 01:34:14.617050 [Byte1]: 68
1633 01:34:14.621251
1634 01:34:14.621759 Set Vref, RX VrefLevel [Byte0]: 69
1635 01:34:14.624872 [Byte1]: 69
1636 01:34:14.628935
1637 01:34:14.629429 Set Vref, RX VrefLevel [Byte0]: 70
1638 01:34:14.632209 [Byte1]: 70
1639 01:34:14.636661
1640 01:34:14.637220 Set Vref, RX VrefLevel [Byte0]: 71
1641 01:34:14.639986 [Byte1]: 71
1642 01:34:14.644712
1643 01:34:14.645358 Set Vref, RX VrefLevel [Byte0]: 72
1644 01:34:14.647501 [Byte1]: 72
1645 01:34:14.651961
1646 01:34:14.652507 Set Vref, RX VrefLevel [Byte0]: 73
1647 01:34:14.655380 [Byte1]: 73
1648 01:34:14.659637
1649 01:34:14.660200 Set Vref, RX VrefLevel [Byte0]: 74
1650 01:34:14.663150 [Byte1]: 74
1651 01:34:14.667180
1652 01:34:14.667634 Set Vref, RX VrefLevel [Byte0]: 75
1653 01:34:14.670313 [Byte1]: 75
1654 01:34:14.674651
1655 01:34:14.675182 Set Vref, RX VrefLevel [Byte0]: 76
1656 01:34:14.678069 [Byte1]: 76
1657 01:34:14.682349
1658 01:34:14.682804 Set Vref, RX VrefLevel [Byte0]: 77
1659 01:34:14.685596 [Byte1]: 77
1660 01:34:14.689979
1661 01:34:14.690430 Set Vref, RX VrefLevel [Byte0]: 78
1662 01:34:14.693488 [Byte1]: 78
1663 01:34:14.697884
1664 01:34:14.698433 Set Vref, RX VrefLevel [Byte0]: 79
1665 01:34:14.701416 [Byte1]: 79
1666 01:34:14.705837
1667 01:34:14.706403 Set Vref, RX VrefLevel [Byte0]: 80
1668 01:34:14.708897 [Byte1]: 80
1669 01:34:14.713261
1670 01:34:14.714036 Final RX Vref Byte 0 = 65 to rank0
1671 01:34:14.716768 Final RX Vref Byte 1 = 62 to rank0
1672 01:34:14.720416 Final RX Vref Byte 0 = 65 to rank1
1673 01:34:14.723641 Final RX Vref Byte 1 = 62 to rank1==
1674 01:34:14.726757 Dram Type= 6, Freq= 0, CH_1, rank 0
1675 01:34:14.730135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1676 01:34:14.730614 ==
1677 01:34:14.733607 DQS Delay:
1678 01:34:14.734154 DQS0 = 0, DQS1 = 0
1679 01:34:14.736764 DQM Delay:
1680 01:34:14.737392 DQM0 = 81, DQM1 = 74
1681 01:34:14.737771 DQ Delay:
1682 01:34:14.740415 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1683 01:34:14.743961 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1684 01:34:14.747044 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1685 01:34:14.750307 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1686 01:34:14.750861
1687 01:34:14.751224
1688 01:34:14.760344 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1689 01:34:14.763550 CH1 RK0: MR19=606, MR18=5151
1690 01:34:14.770269 CH1_RK0: MR19=0x606, MR18=0x5151, DQSOSC=389, MR23=63, INC=97, DEC=65
1691 01:34:14.770835
1692 01:34:14.773491 ----->DramcWriteLeveling(PI) begin...
1693 01:34:14.774014 ==
1694 01:34:14.776985 Dram Type= 6, Freq= 0, CH_1, rank 1
1695 01:34:14.780000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1696 01:34:14.780462 ==
1697 01:34:14.783371 Write leveling (Byte 0): 24 => 24
1698 01:34:14.786964 Write leveling (Byte 1): 24 => 24
1699 01:34:14.790015 DramcWriteLeveling(PI) end<-----
1700 01:34:14.790470
1701 01:34:14.790828 ==
1702 01:34:14.793335 Dram Type= 6, Freq= 0, CH_1, rank 1
1703 01:34:14.796975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1704 01:34:14.797576 ==
1705 01:34:14.800282 [Gating] SW mode calibration
1706 01:34:14.806874 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1707 01:34:14.813628 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1708 01:34:14.816765 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1709 01:34:14.819946 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 01:34:14.826839 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 01:34:14.830262 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 01:34:14.833218 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 01:34:14.837029 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 01:34:14.843243 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1715 01:34:14.846889 0 6 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1716 01:34:14.849985 0 7 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1717 01:34:14.856802 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 01:34:14.860559 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 01:34:14.863772 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 01:34:14.869849 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 01:34:14.873631 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 01:34:14.876650 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1723 01:34:14.883479 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1724 01:34:14.887213 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1725 01:34:14.889932 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 01:34:14.897162 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 01:34:14.900313 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 01:34:14.903700 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 01:34:14.910198 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 01:34:14.913630 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 01:34:14.916804 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 01:34:14.923523 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 01:34:14.926899 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 01:34:14.929845 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 01:34:14.936751 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 01:34:14.939931 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 01:34:14.943095 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 01:34:14.946888 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1739 01:34:14.953615 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1740 01:34:14.957023 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1741 01:34:14.960097 Total UI for P1: 0, mck2ui 16
1742 01:34:14.963209 best dqsien dly found for B0: ( 0, 9, 26)
1743 01:34:14.966358 Total UI for P1: 0, mck2ui 16
1744 01:34:14.970056 best dqsien dly found for B1: ( 0, 9, 28)
1745 01:34:14.973457 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1746 01:34:14.976622 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1747 01:34:14.977190
1748 01:34:14.979833 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1749 01:34:14.986493 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1750 01:34:14.986947 [Gating] SW calibration Done
1751 01:34:14.987305 ==
1752 01:34:14.991725 Dram Type= 6, Freq= 0, CH_1, rank 1
1753 01:34:14.996459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1754 01:34:14.996911 ==
1755 01:34:14.997268 RX Vref Scan: 0
1756 01:34:14.997649
1757 01:34:14.999829 RX Vref 0 -> 0, step: 1
1758 01:34:15.000376
1759 01:34:15.003454 RX Delay -130 -> 252, step: 16
1760 01:34:15.006593 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1761 01:34:15.009936 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1762 01:34:15.013279 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1763 01:34:15.019823 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1764 01:34:15.023582 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1765 01:34:15.026731 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1766 01:34:15.030249 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1767 01:34:15.033470 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1768 01:34:15.036924 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1769 01:34:15.043509 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1770 01:34:15.046764 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1771 01:34:15.050176 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1772 01:34:15.053338 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1773 01:34:15.059972 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1774 01:34:15.062967 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1775 01:34:15.066289 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1776 01:34:15.066743 ==
1777 01:34:15.069851 Dram Type= 6, Freq= 0, CH_1, rank 1
1778 01:34:15.073439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1779 01:34:15.074002 ==
1780 01:34:15.076763 DQS Delay:
1781 01:34:15.077359 DQS0 = 0, DQS1 = 0
1782 01:34:15.079725 DQM Delay:
1783 01:34:15.080237 DQM0 = 85, DQM1 = 73
1784 01:34:15.080775 DQ Delay:
1785 01:34:15.083402 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1786 01:34:15.086550 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1787 01:34:15.089656 DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69
1788 01:34:15.093017 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1789 01:34:15.093514
1790 01:34:15.093871
1791 01:34:15.096315 ==
1792 01:34:15.099485 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 01:34:15.103085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1794 01:34:15.103636 ==
1795 01:34:15.103994
1796 01:34:15.104327
1797 01:34:15.106114 TX Vref Scan disable
1798 01:34:15.106564 == TX Byte 0 ==
1799 01:34:15.109411 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1800 01:34:15.116216 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1801 01:34:15.116767 == TX Byte 1 ==
1802 01:34:15.119626 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1803 01:34:15.125991 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1804 01:34:15.126528 ==
1805 01:34:15.129659 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 01:34:15.133123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 01:34:15.133709 ==
1808 01:34:15.145891 TX Vref=22, minBit 0, minWin=27, winSum=448
1809 01:34:15.148966 TX Vref=24, minBit 8, minWin=27, winSum=451
1810 01:34:15.152593 TX Vref=26, minBit 0, minWin=28, winSum=457
1811 01:34:15.155593 TX Vref=28, minBit 0, minWin=28, winSum=456
1812 01:34:15.158941 TX Vref=30, minBit 0, minWin=28, winSum=457
1813 01:34:15.165443 TX Vref=32, minBit 9, minWin=27, winSum=453
1814 01:34:15.169037 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 26
1815 01:34:15.169538
1816 01:34:15.172529 Final TX Range 1 Vref 26
1817 01:34:15.173133
1818 01:34:15.173615 ==
1819 01:34:15.175654 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 01:34:15.178712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1821 01:34:15.179173 ==
1822 01:34:15.182224
1823 01:34:15.182674
1824 01:34:15.183031 TX Vref Scan disable
1825 01:34:15.185461 == TX Byte 0 ==
1826 01:34:15.189221 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1827 01:34:15.195670 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1828 01:34:15.196220 == TX Byte 1 ==
1829 01:34:15.198650 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1830 01:34:15.205395 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1831 01:34:15.205935
1832 01:34:15.206294 [DATLAT]
1833 01:34:15.206624 Freq=800, CH1 RK1
1834 01:34:15.206945
1835 01:34:15.209122 DATLAT Default: 0x9
1836 01:34:15.209712 0, 0xFFFF, sum = 0
1837 01:34:15.212277 1, 0xFFFF, sum = 0
1838 01:34:15.212830 2, 0xFFFF, sum = 0
1839 01:34:15.215309 3, 0xFFFF, sum = 0
1840 01:34:15.218814 4, 0xFFFF, sum = 0
1841 01:34:15.219276 5, 0xFFFF, sum = 0
1842 01:34:15.222135 6, 0xFFFF, sum = 0
1843 01:34:15.222693 7, 0xFFFF, sum = 0
1844 01:34:15.225911 8, 0x0, sum = 1
1845 01:34:15.226467 9, 0x0, sum = 2
1846 01:34:15.226840 10, 0x0, sum = 3
1847 01:34:15.228585 11, 0x0, sum = 4
1848 01:34:15.229141 best_step = 9
1849 01:34:15.229552
1850 01:34:15.231979 ==
1851 01:34:15.232527 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 01:34:15.238561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1853 01:34:15.239111 ==
1854 01:34:15.239474 RX Vref Scan: 0
1855 01:34:15.239811
1856 01:34:15.241817 RX Vref 0 -> 0, step: 1
1857 01:34:15.242273
1858 01:34:15.245327 RX Delay -111 -> 252, step: 8
1859 01:34:15.248441 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1860 01:34:15.255059 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1861 01:34:15.258608 iDelay=209, Bit 2, Center 72 (-39 ~ 184) 224
1862 01:34:15.261521 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1863 01:34:15.265159 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1864 01:34:15.268134 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1865 01:34:15.271681 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1866 01:34:15.278171 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1867 01:34:15.281444 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1868 01:34:15.285101 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1869 01:34:15.288361 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1870 01:34:15.294756 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1871 01:34:15.298553 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1872 01:34:15.301329 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1873 01:34:15.305021 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1874 01:34:15.308226 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1875 01:34:15.308810 ==
1876 01:34:15.311431 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 01:34:15.317990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1878 01:34:15.318449 ==
1879 01:34:15.318857 DQS Delay:
1880 01:34:15.321408 DQS0 = 0, DQS1 = 0
1881 01:34:15.321886 DQM Delay:
1882 01:34:15.324778 DQM0 = 84, DQM1 = 74
1883 01:34:15.325370 DQ Delay:
1884 01:34:15.328551 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =80
1885 01:34:15.331307 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1886 01:34:15.334724 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1887 01:34:15.338362 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1888 01:34:15.338907
1889 01:34:15.339263
1890 01:34:15.344746 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1891 01:34:15.348112 CH1 RK1: MR19=606, MR18=3B3B
1892 01:34:15.354691 CH1_RK1: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1893 01:34:15.358143 [RxdqsGatingPostProcess] freq 800
1894 01:34:15.361490 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1895 01:34:15.364787 Pre-setting of DQS Precalculation
1896 01:34:15.371501 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1897 01:34:15.377998 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1898 01:34:15.384652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1899 01:34:15.385185
1900 01:34:15.385625
1901 01:34:15.388146 [Calibration Summary] 1600 Mbps
1902 01:34:15.388648 CH 0, Rank 0
1903 01:34:15.390997 SW Impedance : PASS
1904 01:34:15.394571 DUTY Scan : NO K
1905 01:34:15.395213 ZQ Calibration : PASS
1906 01:34:15.397943 Jitter Meter : NO K
1907 01:34:15.401104 CBT Training : PASS
1908 01:34:15.401649 Write leveling : PASS
1909 01:34:15.404444 RX DQS gating : PASS
1910 01:34:15.408068 RX DQ/DQS(RDDQC) : PASS
1911 01:34:15.408611 TX DQ/DQS : PASS
1912 01:34:15.411387 RX DATLAT : PASS
1913 01:34:15.411954 RX DQ/DQS(Engine): PASS
1914 01:34:15.414535 TX OE : NO K
1915 01:34:15.414984 All Pass.
1916 01:34:15.415341
1917 01:34:15.417826 CH 0, Rank 1
1918 01:34:15.418279 SW Impedance : PASS
1919 01:34:15.421116 DUTY Scan : NO K
1920 01:34:15.424445 ZQ Calibration : PASS
1921 01:34:15.424894 Jitter Meter : NO K
1922 01:34:15.427858 CBT Training : PASS
1923 01:34:15.431180 Write leveling : PASS
1924 01:34:15.431632 RX DQS gating : PASS
1925 01:34:15.434480 RX DQ/DQS(RDDQC) : PASS
1926 01:34:15.438004 TX DQ/DQS : PASS
1927 01:34:15.438457 RX DATLAT : PASS
1928 01:34:15.441105 RX DQ/DQS(Engine): PASS
1929 01:34:15.444539 TX OE : NO K
1930 01:34:15.444990 All Pass.
1931 01:34:15.445377
1932 01:34:15.445712 CH 1, Rank 0
1933 01:34:15.447838 SW Impedance : PASS
1934 01:34:15.450892 DUTY Scan : NO K
1935 01:34:15.451343 ZQ Calibration : PASS
1936 01:34:15.454701 Jitter Meter : NO K
1937 01:34:15.457613 CBT Training : PASS
1938 01:34:15.458067 Write leveling : PASS
1939 01:34:15.460962 RX DQS gating : PASS
1940 01:34:15.464388 RX DQ/DQS(RDDQC) : PASS
1941 01:34:15.464836 TX DQ/DQS : PASS
1942 01:34:15.467607 RX DATLAT : PASS
1943 01:34:15.468072 RX DQ/DQS(Engine): PASS
1944 01:34:15.471048 TX OE : NO K
1945 01:34:15.471521 All Pass.
1946 01:34:15.471879
1947 01:34:15.474217 CH 1, Rank 1
1948 01:34:15.474672 SW Impedance : PASS
1949 01:34:15.477578 DUTY Scan : NO K
1950 01:34:15.481103 ZQ Calibration : PASS
1951 01:34:15.481700 Jitter Meter : NO K
1952 01:34:15.484196 CBT Training : PASS
1953 01:34:15.487557 Write leveling : PASS
1954 01:34:15.488013 RX DQS gating : PASS
1955 01:34:15.490864 RX DQ/DQS(RDDQC) : PASS
1956 01:34:15.494074 TX DQ/DQS : PASS
1957 01:34:15.494533 RX DATLAT : PASS
1958 01:34:15.497395 RX DQ/DQS(Engine): PASS
1959 01:34:15.501059 TX OE : NO K
1960 01:34:15.501676 All Pass.
1961 01:34:15.502045
1962 01:34:15.502379 DramC Write-DBI off
1963 01:34:15.504149 PER_BANK_REFRESH: Hybrid Mode
1964 01:34:15.507674 TX_TRACKING: ON
1965 01:34:15.510674 [GetDramInforAfterCalByMRR] Vendor 6.
1966 01:34:15.514202 [GetDramInforAfterCalByMRR] Revision 606.
1967 01:34:15.517426 [GetDramInforAfterCalByMRR] Revision 2 0.
1968 01:34:15.517883 MR0 0x3939
1969 01:34:15.520785 MR8 0x1111
1970 01:34:15.524712 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1971 01:34:15.525268
1972 01:34:15.525674 MR0 0x3939
1973 01:34:15.526015 MR8 0x1111
1974 01:34:15.530655 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1975 01:34:15.531114
1976 01:34:15.537398 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1977 01:34:15.541252 [FAST_K] Save calibration result to emmc
1978 01:34:15.544215 [FAST_K] Save calibration result to emmc
1979 01:34:15.547638 dram_init: config_dvfs: 1
1980 01:34:15.551017 dramc_set_vcore_voltage set vcore to 662500
1981 01:34:15.554246 Read voltage for 1200, 2
1982 01:34:15.554701 Vio18 = 0
1983 01:34:15.557622 Vcore = 662500
1984 01:34:15.558175 Vdram = 0
1985 01:34:15.558540 Vddq = 0
1986 01:34:15.558875 Vmddr = 0
1987 01:34:15.564182 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1988 01:34:15.570911 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1989 01:34:15.571457 MEM_TYPE=3, freq_sel=15
1990 01:34:15.574383 sv_algorithm_assistance_LP4_1600
1991 01:34:15.577474 ============ PULL DRAM RESETB DOWN ============
1992 01:34:15.584006 ========== PULL DRAM RESETB DOWN end =========
1993 01:34:15.587756 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1994 01:34:15.591246 ===================================
1995 01:34:15.594253 LPDDR4 DRAM CONFIGURATION
1996 01:34:15.597806 ===================================
1997 01:34:15.598363 EX_ROW_EN[0] = 0x0
1998 01:34:15.601146 EX_ROW_EN[1] = 0x0
1999 01:34:15.601635 LP4Y_EN = 0x0
2000 01:34:15.604550 WORK_FSP = 0x0
2001 01:34:15.605103 WL = 0x4
2002 01:34:15.607859 RL = 0x4
2003 01:34:15.608407 BL = 0x2
2004 01:34:15.611080 RPST = 0x0
2005 01:34:15.611533 RD_PRE = 0x0
2006 01:34:15.614327 WR_PRE = 0x1
2007 01:34:15.614840 WR_PST = 0x0
2008 01:34:15.617919 DBI_WR = 0x0
2009 01:34:15.618372 DBI_RD = 0x0
2010 01:34:15.621492 OTF = 0x1
2011 01:34:15.624468 ===================================
2012 01:34:15.627794 ===================================
2013 01:34:15.628252 ANA top config
2014 01:34:15.631169 ===================================
2015 01:34:15.634384 DLL_ASYNC_EN = 0
2016 01:34:15.637866 ALL_SLAVE_EN = 0
2017 01:34:15.641237 NEW_RANK_MODE = 1
2018 01:34:15.641847 DLL_IDLE_MODE = 1
2019 01:34:15.644392 LP45_APHY_COMB_EN = 1
2020 01:34:15.647589 TX_ODT_DIS = 1
2021 01:34:15.651245 NEW_8X_MODE = 1
2022 01:34:15.654311 ===================================
2023 01:34:15.657643 ===================================
2024 01:34:15.661227 data_rate = 2400
2025 01:34:15.664015 CKR = 1
2026 01:34:15.664471 DQ_P2S_RATIO = 8
2027 01:34:15.667280 ===================================
2028 01:34:15.670848 CA_P2S_RATIO = 8
2029 01:34:15.673985 DQ_CA_OPEN = 0
2030 01:34:15.677697 DQ_SEMI_OPEN = 0
2031 01:34:15.680875 CA_SEMI_OPEN = 0
2032 01:34:15.684002 CA_FULL_RATE = 0
2033 01:34:15.684607 DQ_CKDIV4_EN = 0
2034 01:34:15.687121 CA_CKDIV4_EN = 0
2035 01:34:15.690731 CA_PREDIV_EN = 0
2036 01:34:15.694197 PH8_DLY = 17
2037 01:34:15.697459 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2038 01:34:15.700661 DQ_AAMCK_DIV = 4
2039 01:34:15.701120 CA_AAMCK_DIV = 4
2040 01:34:15.704404 CA_ADMCK_DIV = 4
2041 01:34:15.707431 DQ_TRACK_CA_EN = 0
2042 01:34:15.710974 CA_PICK = 1200
2043 01:34:15.714268 CA_MCKIO = 1200
2044 01:34:15.717354 MCKIO_SEMI = 0
2045 01:34:15.721119 PLL_FREQ = 2366
2046 01:34:15.721762 DQ_UI_PI_RATIO = 32
2047 01:34:15.724002 CA_UI_PI_RATIO = 0
2048 01:34:15.727308 ===================================
2049 01:34:15.730639 ===================================
2050 01:34:15.734074 memory_type:LPDDR4
2051 01:34:15.737962 GP_NUM : 10
2052 01:34:15.738528 SRAM_EN : 1
2053 01:34:15.740745 MD32_EN : 0
2054 01:34:15.744027 ===================================
2055 01:34:15.744505 [ANA_INIT] >>>>>>>>>>>>>>
2056 01:34:15.747530 <<<<<< [CONFIGURE PHASE]: ANA_TX
2057 01:34:15.751133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2058 01:34:15.754152 ===================================
2059 01:34:15.757453 data_rate = 2400,PCW = 0X5b00
2060 01:34:15.760658 ===================================
2061 01:34:15.764095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2062 01:34:15.770492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2063 01:34:15.777242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2064 01:34:15.780430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2065 01:34:15.783911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2066 01:34:15.787557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2067 01:34:15.790659 [ANA_INIT] flow start
2068 01:34:15.791221 [ANA_INIT] PLL >>>>>>>>
2069 01:34:15.793614 [ANA_INIT] PLL <<<<<<<<
2070 01:34:15.797221 [ANA_INIT] MIDPI >>>>>>>>
2071 01:34:15.797830 [ANA_INIT] MIDPI <<<<<<<<
2072 01:34:15.800770 [ANA_INIT] DLL >>>>>>>>
2073 01:34:15.803865 [ANA_INIT] DLL <<<<<<<<
2074 01:34:15.804427 [ANA_INIT] flow end
2075 01:34:15.810427 ============ LP4 DIFF to SE enter ============
2076 01:34:15.813925 ============ LP4 DIFF to SE exit ============
2077 01:34:15.817049 [ANA_INIT] <<<<<<<<<<<<<
2078 01:34:15.817574 [Flow] Enable top DCM control >>>>>
2079 01:34:15.821094 [Flow] Enable top DCM control <<<<<
2080 01:34:15.823761 Enable DLL master slave shuffle
2081 01:34:15.830348 ==============================================================
2082 01:34:15.833947 Gating Mode config
2083 01:34:15.836922 ==============================================================
2084 01:34:15.840511 Config description:
2085 01:34:15.850357 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2086 01:34:15.857457 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2087 01:34:15.860648 SELPH_MODE 0: By rank 1: By Phase
2088 01:34:15.867215 ==============================================================
2089 01:34:15.870511 GAT_TRACK_EN = 1
2090 01:34:15.873654 RX_GATING_MODE = 2
2091 01:34:15.874112 RX_GATING_TRACK_MODE = 2
2092 01:34:15.876824 SELPH_MODE = 1
2093 01:34:15.880613 PICG_EARLY_EN = 1
2094 01:34:15.883586 VALID_LAT_VALUE = 1
2095 01:34:15.890616 ==============================================================
2096 01:34:15.893848 Enter into Gating configuration >>>>
2097 01:34:15.896750 Exit from Gating configuration <<<<
2098 01:34:15.900368 Enter into DVFS_PRE_config >>>>>
2099 01:34:15.910304 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2100 01:34:15.913846 Exit from DVFS_PRE_config <<<<<
2101 01:34:15.916927 Enter into PICG configuration >>>>
2102 01:34:15.920432 Exit from PICG configuration <<<<
2103 01:34:15.923984 [RX_INPUT] configuration >>>>>
2104 01:34:15.927094 [RX_INPUT] configuration <<<<<
2105 01:34:15.930355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2106 01:34:15.936985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2107 01:34:15.943507 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2108 01:34:15.949936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2109 01:34:15.953632 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2110 01:34:15.960459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2111 01:34:15.963334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2112 01:34:15.970313 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2113 01:34:15.973832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2114 01:34:15.976793 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2115 01:34:15.980395 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2116 01:34:15.987068 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 01:34:15.990208 ===================================
2118 01:34:15.990666 LPDDR4 DRAM CONFIGURATION
2119 01:34:15.993757 ===================================
2120 01:34:15.996852 EX_ROW_EN[0] = 0x0
2121 01:34:16.000370 EX_ROW_EN[1] = 0x0
2122 01:34:16.000919 LP4Y_EN = 0x0
2123 01:34:16.003869 WORK_FSP = 0x0
2124 01:34:16.004417 WL = 0x4
2125 01:34:16.007135 RL = 0x4
2126 01:34:16.007688 BL = 0x2
2127 01:34:16.010067 RPST = 0x0
2128 01:34:16.010521 RD_PRE = 0x0
2129 01:34:16.013570 WR_PRE = 0x1
2130 01:34:16.014025 WR_PST = 0x0
2131 01:34:16.017266 DBI_WR = 0x0
2132 01:34:16.017754 DBI_RD = 0x0
2133 01:34:16.020360 OTF = 0x1
2134 01:34:16.023898 ===================================
2135 01:34:16.026971 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2136 01:34:16.030387 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2137 01:34:16.037037 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 01:34:16.040473 ===================================
2139 01:34:16.041022 LPDDR4 DRAM CONFIGURATION
2140 01:34:16.043646 ===================================
2141 01:34:16.047118 EX_ROW_EN[0] = 0x10
2142 01:34:16.047665 EX_ROW_EN[1] = 0x0
2143 01:34:16.050387 LP4Y_EN = 0x0
2144 01:34:16.050942 WORK_FSP = 0x0
2145 01:34:16.053636 WL = 0x4
2146 01:34:16.054202 RL = 0x4
2147 01:34:16.056746 BL = 0x2
2148 01:34:16.060300 RPST = 0x0
2149 01:34:16.060851 RD_PRE = 0x0
2150 01:34:16.063560 WR_PRE = 0x1
2151 01:34:16.064109 WR_PST = 0x0
2152 01:34:16.067110 DBI_WR = 0x0
2153 01:34:16.067712 DBI_RD = 0x0
2154 01:34:16.069922 OTF = 0x1
2155 01:34:16.073366 ===================================
2156 01:34:16.076602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2157 01:34:16.080182 ==
2158 01:34:16.083197 Dram Type= 6, Freq= 0, CH_0, rank 0
2159 01:34:16.086557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2160 01:34:16.087014 ==
2161 01:34:16.089902 [Duty_Offset_Calibration]
2162 01:34:16.090364 B0:0 B1:2 CA:1
2163 01:34:16.090726
2164 01:34:16.093230 [DutyScan_Calibration_Flow] k_type=0
2165 01:34:16.103008
2166 01:34:16.103555 ==CLK 0==
2167 01:34:16.106473 Final CLK duty delay cell = 0
2168 01:34:16.109548 [0] MAX Duty = 5093%(X100), DQS PI = 12
2169 01:34:16.113326 [0] MIN Duty = 4938%(X100), DQS PI = 52
2170 01:34:16.113892 [0] AVG Duty = 5015%(X100)
2171 01:34:16.116385
2172 01:34:16.119544 CH0 CLK Duty spec in!! Max-Min= 155%
2173 01:34:16.122997 [DutyScan_Calibration_Flow] ====Done====
2174 01:34:16.123554
2175 01:34:16.126299 [DutyScan_Calibration_Flow] k_type=1
2176 01:34:16.142162
2177 01:34:16.142731 ==DQS 0 ==
2178 01:34:16.145368 Final DQS duty delay cell = 0
2179 01:34:16.149095 [0] MAX Duty = 5093%(X100), DQS PI = 2
2180 01:34:16.152509 [0] MIN Duty = 5031%(X100), DQS PI = 4
2181 01:34:16.153066 [0] AVG Duty = 5062%(X100)
2182 01:34:16.155218
2183 01:34:16.155672 ==DQS 1 ==
2184 01:34:16.159001 Final DQS duty delay cell = 0
2185 01:34:16.162066 [0] MAX Duty = 5062%(X100), DQS PI = 56
2186 01:34:16.165149 [0] MIN Duty = 4906%(X100), DQS PI = 14
2187 01:34:16.168910 [0] AVG Duty = 4984%(X100)
2188 01:34:16.169501
2189 01:34:16.172021 CH0 DQS 0 Duty spec in!! Max-Min= 62%
2190 01:34:16.172580
2191 01:34:16.175103 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2192 01:34:16.178798 [DutyScan_Calibration_Flow] ====Done====
2193 01:34:16.179354
2194 01:34:16.181704 [DutyScan_Calibration_Flow] k_type=3
2195 01:34:16.199686
2196 01:34:16.200241 ==DQM 0 ==
2197 01:34:16.202794 Final DQM duty delay cell = 0
2198 01:34:16.206159 [0] MAX Duty = 5156%(X100), DQS PI = 22
2199 01:34:16.209461 [0] MIN Duty = 4969%(X100), DQS PI = 40
2200 01:34:16.212715 [0] AVG Duty = 5062%(X100)
2201 01:34:16.213268
2202 01:34:16.213675 ==DQM 1 ==
2203 01:34:16.215872 Final DQM duty delay cell = 4
2204 01:34:16.219838 [4] MAX Duty = 5187%(X100), DQS PI = 54
2205 01:34:16.222592 [4] MIN Duty = 5000%(X100), DQS PI = 20
2206 01:34:16.225876 [4] AVG Duty = 5093%(X100)
2207 01:34:16.226331
2208 01:34:16.229571 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2209 01:34:16.230129
2210 01:34:16.232946 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2211 01:34:16.235965 [DutyScan_Calibration_Flow] ====Done====
2212 01:34:16.236519
2213 01:34:16.239120 [DutyScan_Calibration_Flow] k_type=2
2214 01:34:16.254237
2215 01:34:16.254802 ==DQ 0 ==
2216 01:34:16.258036 Final DQ duty delay cell = -4
2217 01:34:16.261225 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2218 01:34:16.264246 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2219 01:34:16.267664 [-4] AVG Duty = 4937%(X100)
2220 01:34:16.268238
2221 01:34:16.268601 ==DQ 1 ==
2222 01:34:16.270714 Final DQ duty delay cell = -4
2223 01:34:16.274583 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2224 01:34:16.277541 [-4] MIN Duty = 4876%(X100), DQS PI = 38
2225 01:34:16.280895 [-4] AVG Duty = 4969%(X100)
2226 01:34:16.281501
2227 01:34:16.284369 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2228 01:34:16.284928
2229 01:34:16.287334 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2230 01:34:16.290891 [DutyScan_Calibration_Flow] ====Done====
2231 01:34:16.291346 ==
2232 01:34:16.294086 Dram Type= 6, Freq= 0, CH_1, rank 0
2233 01:34:16.297392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2234 01:34:16.297854 ==
2235 01:34:16.300918 [Duty_Offset_Calibration]
2236 01:34:16.301750 B0:0 B1:4 CA:-5
2237 01:34:16.302253
2238 01:34:16.304047 [DutyScan_Calibration_Flow] k_type=0
2239 01:34:16.314992
2240 01:34:16.315535 ==CLK 0==
2241 01:34:16.317982 Final CLK duty delay cell = 0
2242 01:34:16.321551 [0] MAX Duty = 5094%(X100), DQS PI = 24
2243 01:34:16.324977 [0] MIN Duty = 4907%(X100), DQS PI = 42
2244 01:34:16.328304 [0] AVG Duty = 5000%(X100)
2245 01:34:16.328852
2246 01:34:16.331619 CH1 CLK Duty spec in!! Max-Min= 187%
2247 01:34:16.334584 [DutyScan_Calibration_Flow] ====Done====
2248 01:34:16.335041
2249 01:34:16.338053 [DutyScan_Calibration_Flow] k_type=1
2250 01:34:16.353515
2251 01:34:16.354074 ==DQS 0 ==
2252 01:34:16.356762 Final DQS duty delay cell = 0
2253 01:34:16.359960 [0] MAX Duty = 5125%(X100), DQS PI = 16
2254 01:34:16.363516 [0] MIN Duty = 4875%(X100), DQS PI = 40
2255 01:34:16.366441 [0] AVG Duty = 5000%(X100)
2256 01:34:16.366904
2257 01:34:16.367267 ==DQS 1 ==
2258 01:34:16.369852 Final DQS duty delay cell = -4
2259 01:34:16.373803 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2260 01:34:16.376772 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2261 01:34:16.380389 [-4] AVG Duty = 4953%(X100)
2262 01:34:16.380935
2263 01:34:16.383375 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2264 01:34:16.383929
2265 01:34:16.386414 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2266 01:34:16.389845 [DutyScan_Calibration_Flow] ====Done====
2267 01:34:16.390301
2268 01:34:16.393334 [DutyScan_Calibration_Flow] k_type=3
2269 01:34:16.408566
2270 01:34:16.409122 ==DQM 0 ==
2271 01:34:16.411972 Final DQM duty delay cell = -4
2272 01:34:16.415248 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2273 01:34:16.418327 [-4] MIN Duty = 4844%(X100), DQS PI = 42
2274 01:34:16.422066 [-4] AVG Duty = 4953%(X100)
2275 01:34:16.422522
2276 01:34:16.422880 ==DQM 1 ==
2277 01:34:16.425169 Final DQM duty delay cell = -4
2278 01:34:16.428510 [-4] MAX Duty = 5093%(X100), DQS PI = 22
2279 01:34:16.431881 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2280 01:34:16.435309 [-4] AVG Duty = 5000%(X100)
2281 01:34:16.435766
2282 01:34:16.439023 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2283 01:34:16.439580
2284 01:34:16.442000 CH1 DQM 1 Duty spec in!! Max-Min= 186%
2285 01:34:16.445510 [DutyScan_Calibration_Flow] ====Done====
2286 01:34:16.446066
2287 01:34:16.448693 [DutyScan_Calibration_Flow] k_type=2
2288 01:34:16.466119
2289 01:34:16.466672 ==DQ 0 ==
2290 01:34:16.469033 Final DQ duty delay cell = 0
2291 01:34:16.472533 [0] MAX Duty = 5062%(X100), DQS PI = 0
2292 01:34:16.475603 [0] MIN Duty = 4969%(X100), DQS PI = 44
2293 01:34:16.476060 [0] AVG Duty = 5015%(X100)
2294 01:34:16.476475
2295 01:34:16.478773 ==DQ 1 ==
2296 01:34:16.482107 Final DQ duty delay cell = 0
2297 01:34:16.485404 [0] MAX Duty = 5031%(X100), DQS PI = 8
2298 01:34:16.488713 [0] MIN Duty = 4875%(X100), DQS PI = 30
2299 01:34:16.489184 [0] AVG Duty = 4953%(X100)
2300 01:34:16.489743
2301 01:34:16.492166 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2302 01:34:16.492619
2303 01:34:16.495598 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2304 01:34:16.502127 [DutyScan_Calibration_Flow] ====Done====
2305 01:34:16.505788 nWR fixed to 30
2306 01:34:16.506200 [ModeRegInit_LP4] CH0 RK0
2307 01:34:16.509107 [ModeRegInit_LP4] CH0 RK1
2308 01:34:16.512275 [ModeRegInit_LP4] CH1 RK0
2309 01:34:16.512567 [ModeRegInit_LP4] CH1 RK1
2310 01:34:16.515734 match AC timing 6
2311 01:34:16.518852 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2312 01:34:16.522274 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2313 01:34:16.528746 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2314 01:34:16.532518 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2315 01:34:16.538922 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2316 01:34:16.539414 ==
2317 01:34:16.542217 Dram Type= 6, Freq= 0, CH_0, rank 0
2318 01:34:16.545938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2319 01:34:16.546808 ==
2320 01:34:16.552351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2321 01:34:16.555454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2322 01:34:16.565507 [CA 0] Center 39 (9~70) winsize 62
2323 01:34:16.568788 [CA 1] Center 39 (8~70) winsize 63
2324 01:34:16.572067 [CA 2] Center 36 (5~67) winsize 63
2325 01:34:16.575388 [CA 3] Center 35 (4~66) winsize 63
2326 01:34:16.578677 [CA 4] Center 34 (3~65) winsize 63
2327 01:34:16.581837 [CA 5] Center 33 (3~64) winsize 62
2328 01:34:16.582347
2329 01:34:16.585116 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2330 01:34:16.585879
2331 01:34:16.588674 [CATrainingPosCal] consider 1 rank data
2332 01:34:16.591933 u2DelayCellTimex100 = 270/100 ps
2333 01:34:16.595390 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2334 01:34:16.599054 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2335 01:34:16.605163 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2336 01:34:16.608690 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2337 01:34:16.611842 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2338 01:34:16.615188 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2339 01:34:16.615648
2340 01:34:16.618590 CA PerBit enable=1, Macro0, CA PI delay=33
2341 01:34:16.619052
2342 01:34:16.621857 [CBTSetCACLKResult] CA Dly = 33
2343 01:34:16.622311 CS Dly: 7 (0~38)
2344 01:34:16.622670 ==
2345 01:34:16.625475 Dram Type= 6, Freq= 0, CH_0, rank 1
2346 01:34:16.631905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2347 01:34:16.632445 ==
2348 01:34:16.635072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2349 01:34:16.641617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2350 01:34:16.650604 [CA 0] Center 39 (8~70) winsize 63
2351 01:34:16.654151 [CA 1] Center 39 (8~70) winsize 63
2352 01:34:16.657382 [CA 2] Center 36 (5~67) winsize 63
2353 01:34:16.660823 [CA 3] Center 35 (4~66) winsize 63
2354 01:34:16.664005 [CA 4] Center 33 (3~64) winsize 62
2355 01:34:16.667275 [CA 5] Center 34 (3~65) winsize 63
2356 01:34:16.667733
2357 01:34:16.670882 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2358 01:34:16.671354
2359 01:34:16.673884 [CATrainingPosCal] consider 2 rank data
2360 01:34:16.677467 u2DelayCellTimex100 = 270/100 ps
2361 01:34:16.680641 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2362 01:34:16.687267 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2363 01:34:16.690516 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2364 01:34:16.693916 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2365 01:34:16.697241 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2366 01:34:16.700476 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2367 01:34:16.700937
2368 01:34:16.703784 CA PerBit enable=1, Macro0, CA PI delay=33
2369 01:34:16.704238
2370 01:34:16.707443 [CBTSetCACLKResult] CA Dly = 33
2371 01:34:16.707991 CS Dly: 7 (0~39)
2372 01:34:16.708355
2373 01:34:16.710862 ----->DramcWriteLeveling(PI) begin...
2374 01:34:16.714268 ==
2375 01:34:16.717262 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 01:34:16.720807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2377 01:34:16.721404 ==
2378 01:34:16.723737 Write leveling (Byte 0): 29 => 29
2379 01:34:16.727394 Write leveling (Byte 1): 26 => 26
2380 01:34:16.730714 DramcWriteLeveling(PI) end<-----
2381 01:34:16.731258
2382 01:34:16.731621 ==
2383 01:34:16.734252 Dram Type= 6, Freq= 0, CH_0, rank 0
2384 01:34:16.737557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2385 01:34:16.738106 ==
2386 01:34:16.740891 [Gating] SW mode calibration
2387 01:34:16.747165 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2388 01:34:16.753891 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2389 01:34:16.757252 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 01:34:16.760637 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2391 01:34:16.767271 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2392 01:34:16.770692 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2393 01:34:16.773990 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2394 01:34:16.777338 0 11 20 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (1 0)
2395 01:34:16.783918 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 01:34:16.787138 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 01:34:16.790236 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 01:34:16.797258 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 01:34:16.800614 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 01:34:16.803712 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2401 01:34:16.810500 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2402 01:34:16.813772 0 12 20 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
2403 01:34:16.817449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 01:34:16.823678 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 01:34:16.827409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 01:34:16.830371 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 01:34:16.837132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 01:34:16.840670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 01:34:16.844351 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2410 01:34:16.850287 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2411 01:34:16.853857 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2412 01:34:16.856753 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 01:34:16.863632 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 01:34:16.866737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 01:34:16.870186 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 01:34:16.876879 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 01:34:16.880295 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 01:34:16.883625 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 01:34:16.886829 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 01:34:16.893448 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 01:34:16.897389 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 01:34:16.900452 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 01:34:16.906738 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 01:34:16.910095 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 01:34:16.913488 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2426 01:34:16.920288 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2427 01:34:16.923511 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2428 01:34:16.927201 Total UI for P1: 0, mck2ui 16
2429 01:34:16.930149 best dqsien dly found for B0: ( 0, 15, 18)
2430 01:34:16.933368 Total UI for P1: 0, mck2ui 16
2431 01:34:16.936774 best dqsien dly found for B1: ( 0, 15, 18)
2432 01:34:16.940425 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2433 01:34:16.943629 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2434 01:34:16.944177
2435 01:34:16.946921 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2436 01:34:16.950444 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2437 01:34:16.953840 [Gating] SW calibration Done
2438 01:34:16.954386 ==
2439 01:34:16.956875 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 01:34:16.960530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2441 01:34:16.964012 ==
2442 01:34:16.964558 RX Vref Scan: 0
2443 01:34:16.964919
2444 01:34:16.966794 RX Vref 0 -> 0, step: 1
2445 01:34:16.967269
2446 01:34:16.970144 RX Delay -40 -> 252, step: 8
2447 01:34:16.973416 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2448 01:34:16.976910 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2449 01:34:16.979903 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2450 01:34:16.983502 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2451 01:34:16.990129 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2452 01:34:16.993481 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2453 01:34:16.996988 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2454 01:34:17.000151 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2455 01:34:17.003236 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2456 01:34:17.009971 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2457 01:34:17.013183 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2458 01:34:17.016592 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2459 01:34:17.019881 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2460 01:34:17.023200 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2461 01:34:17.029962 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2462 01:34:17.033117 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2463 01:34:17.033618 ==
2464 01:34:17.036935 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 01:34:17.039988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2466 01:34:17.040545 ==
2467 01:34:17.043413 DQS Delay:
2468 01:34:17.043964 DQS0 = 0, DQS1 = 0
2469 01:34:17.044324 DQM Delay:
2470 01:34:17.046713 DQM0 = 115, DQM1 = 106
2471 01:34:17.047163 DQ Delay:
2472 01:34:17.049886 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2473 01:34:17.053542 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2474 01:34:17.056545 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2475 01:34:17.063204 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2476 01:34:17.063758
2477 01:34:17.064121
2478 01:34:17.064454 ==
2479 01:34:17.066800 Dram Type= 6, Freq= 0, CH_0, rank 0
2480 01:34:17.070222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2481 01:34:17.070775 ==
2482 01:34:17.071136
2483 01:34:17.071540
2484 01:34:17.073430 TX Vref Scan disable
2485 01:34:17.073881 == TX Byte 0 ==
2486 01:34:17.079645 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2487 01:34:17.082915 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2488 01:34:17.083374 == TX Byte 1 ==
2489 01:34:17.089718 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2490 01:34:17.092985 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2491 01:34:17.093531 ==
2492 01:34:17.096340 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 01:34:17.099542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2494 01:34:17.099999 ==
2495 01:34:17.112542 TX Vref=22, minBit 12, minWin=24, winSum=411
2496 01:34:17.115874 TX Vref=24, minBit 10, minWin=24, winSum=419
2497 01:34:17.119382 TX Vref=26, minBit 10, minWin=25, winSum=428
2498 01:34:17.122818 TX Vref=28, minBit 8, minWin=25, winSum=429
2499 01:34:17.125726 TX Vref=30, minBit 12, minWin=26, winSum=436
2500 01:34:17.132619 TX Vref=32, minBit 9, minWin=26, winSum=433
2501 01:34:17.136019 [TxChooseVref] Worse bit 12, Min win 26, Win sum 436, Final Vref 30
2502 01:34:17.136630
2503 01:34:17.139044 Final TX Range 1 Vref 30
2504 01:34:17.139498
2505 01:34:17.139855 ==
2506 01:34:17.142669 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 01:34:17.145671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2508 01:34:17.149122 ==
2509 01:34:17.149718
2510 01:34:17.150083
2511 01:34:17.150412 TX Vref Scan disable
2512 01:34:17.152650 == TX Byte 0 ==
2513 01:34:17.156031 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2514 01:34:17.159564 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2515 01:34:17.162662 == TX Byte 1 ==
2516 01:34:17.166063 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2517 01:34:17.172410 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2518 01:34:17.172966
2519 01:34:17.173388 [DATLAT]
2520 01:34:17.173734 Freq=1200, CH0 RK0
2521 01:34:17.174056
2522 01:34:17.175781 DATLAT Default: 0xd
2523 01:34:17.176327 0, 0xFFFF, sum = 0
2524 01:34:17.178989 1, 0xFFFF, sum = 0
2525 01:34:17.179461 2, 0xFFFF, sum = 0
2526 01:34:17.182280 3, 0xFFFF, sum = 0
2527 01:34:17.185892 4, 0xFFFF, sum = 0
2528 01:34:17.186467 5, 0xFFFF, sum = 0
2529 01:34:17.189488 6, 0xFFFF, sum = 0
2530 01:34:17.190053 7, 0xFFFF, sum = 0
2531 01:34:17.192733 8, 0xFFFF, sum = 0
2532 01:34:17.193190 9, 0xFFFF, sum = 0
2533 01:34:17.195812 10, 0xFFFF, sum = 0
2534 01:34:17.196366 11, 0x0, sum = 1
2535 01:34:17.198976 12, 0x0, sum = 2
2536 01:34:17.199439 13, 0x0, sum = 3
2537 01:34:17.202599 14, 0x0, sum = 4
2538 01:34:17.203070 best_step = 12
2539 01:34:17.203430
2540 01:34:17.203760 ==
2541 01:34:17.205707 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 01:34:17.209515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2543 01:34:17.210063 ==
2544 01:34:17.212674 RX Vref Scan: 1
2545 01:34:17.213223
2546 01:34:17.216002 Set Vref Range= 32 -> 127
2547 01:34:17.216581
2548 01:34:17.216941 RX Vref 32 -> 127, step: 1
2549 01:34:17.217273
2550 01:34:17.219128 RX Delay -21 -> 252, step: 4
2551 01:34:17.219685
2552 01:34:17.222553 Set Vref, RX VrefLevel [Byte0]: 32
2553 01:34:17.225775 [Byte1]: 32
2554 01:34:17.229448
2555 01:34:17.229994 Set Vref, RX VrefLevel [Byte0]: 33
2556 01:34:17.232774 [Byte1]: 33
2557 01:34:17.237433
2558 01:34:17.237978 Set Vref, RX VrefLevel [Byte0]: 34
2559 01:34:17.240573 [Byte1]: 34
2560 01:34:17.245283
2561 01:34:17.245896 Set Vref, RX VrefLevel [Byte0]: 35
2562 01:34:17.248349 [Byte1]: 35
2563 01:34:17.253199
2564 01:34:17.253800 Set Vref, RX VrefLevel [Byte0]: 36
2565 01:34:17.256466 [Byte1]: 36
2566 01:34:17.261237
2567 01:34:17.261959 Set Vref, RX VrefLevel [Byte0]: 37
2568 01:34:17.264494 [Byte1]: 37
2569 01:34:17.268954
2570 01:34:17.269548 Set Vref, RX VrefLevel [Byte0]: 38
2571 01:34:17.272118 [Byte1]: 38
2572 01:34:17.277083
2573 01:34:17.277694 Set Vref, RX VrefLevel [Byte0]: 39
2574 01:34:17.280232 [Byte1]: 39
2575 01:34:17.284762
2576 01:34:17.285357 Set Vref, RX VrefLevel [Byte0]: 40
2577 01:34:17.288426 [Byte1]: 40
2578 01:34:17.292568
2579 01:34:17.293027 Set Vref, RX VrefLevel [Byte0]: 41
2580 01:34:17.296077 [Byte1]: 41
2581 01:34:17.300795
2582 01:34:17.301392 Set Vref, RX VrefLevel [Byte0]: 42
2583 01:34:17.304140 [Byte1]: 42
2584 01:34:17.308768
2585 01:34:17.309402 Set Vref, RX VrefLevel [Byte0]: 43
2586 01:34:17.311842 [Byte1]: 43
2587 01:34:17.316540
2588 01:34:17.317117 Set Vref, RX VrefLevel [Byte0]: 44
2589 01:34:17.319986 [Byte1]: 44
2590 01:34:17.324565
2591 01:34:17.325112 Set Vref, RX VrefLevel [Byte0]: 45
2592 01:34:17.328012 [Byte1]: 45
2593 01:34:17.332621
2594 01:34:17.333174 Set Vref, RX VrefLevel [Byte0]: 46
2595 01:34:17.335462 [Byte1]: 46
2596 01:34:17.340424
2597 01:34:17.341002 Set Vref, RX VrefLevel [Byte0]: 47
2598 01:34:17.344031 [Byte1]: 47
2599 01:34:17.348453
2600 01:34:17.349002 Set Vref, RX VrefLevel [Byte0]: 48
2601 01:34:17.351503 [Byte1]: 48
2602 01:34:17.356101
2603 01:34:17.356647 Set Vref, RX VrefLevel [Byte0]: 49
2604 01:34:17.359417 [Byte1]: 49
2605 01:34:17.364118
2606 01:34:17.364671 Set Vref, RX VrefLevel [Byte0]: 50
2607 01:34:17.367507 [Byte1]: 50
2608 01:34:17.372197
2609 01:34:17.372743 Set Vref, RX VrefLevel [Byte0]: 51
2610 01:34:17.375235 [Byte1]: 51
2611 01:34:17.379907
2612 01:34:17.380408 Set Vref, RX VrefLevel [Byte0]: 52
2613 01:34:17.383201 [Byte1]: 52
2614 01:34:17.388190
2615 01:34:17.388742 Set Vref, RX VrefLevel [Byte0]: 53
2616 01:34:17.391162 [Byte1]: 53
2617 01:34:17.396122
2618 01:34:17.396679 Set Vref, RX VrefLevel [Byte0]: 54
2619 01:34:17.398754 [Byte1]: 54
2620 01:34:17.403828
2621 01:34:17.404375 Set Vref, RX VrefLevel [Byte0]: 55
2622 01:34:17.407059 [Byte1]: 55
2623 01:34:17.411753
2624 01:34:17.412319 Set Vref, RX VrefLevel [Byte0]: 56
2625 01:34:17.414882 [Byte1]: 56
2626 01:34:17.419742
2627 01:34:17.420294 Set Vref, RX VrefLevel [Byte0]: 57
2628 01:34:17.422596 [Byte1]: 57
2629 01:34:17.427511
2630 01:34:17.428133 Set Vref, RX VrefLevel [Byte0]: 58
2631 01:34:17.430938 [Byte1]: 58
2632 01:34:17.435637
2633 01:34:17.436183 Set Vref, RX VrefLevel [Byte0]: 59
2634 01:34:17.439051 [Byte1]: 59
2635 01:34:17.443443
2636 01:34:17.443993 Set Vref, RX VrefLevel [Byte0]: 60
2637 01:34:17.446648 [Byte1]: 60
2638 01:34:17.451279
2639 01:34:17.451856 Set Vref, RX VrefLevel [Byte0]: 61
2640 01:34:17.454831 [Byte1]: 61
2641 01:34:17.458853
2642 01:34:17.459305 Set Vref, RX VrefLevel [Byte0]: 62
2643 01:34:17.462535 [Byte1]: 62
2644 01:34:17.466987
2645 01:34:17.467438 Set Vref, RX VrefLevel [Byte0]: 63
2646 01:34:17.470190 [Byte1]: 63
2647 01:34:17.474943
2648 01:34:17.475502 Set Vref, RX VrefLevel [Byte0]: 64
2649 01:34:17.478234 [Byte1]: 64
2650 01:34:17.482787
2651 01:34:17.483332 Set Vref, RX VrefLevel [Byte0]: 65
2652 01:34:17.486210 [Byte1]: 65
2653 01:34:17.491014
2654 01:34:17.491669 Set Vref, RX VrefLevel [Byte0]: 66
2655 01:34:17.493849 [Byte1]: 66
2656 01:34:17.498479
2657 01:34:17.498930 Final RX Vref Byte 0 = 47 to rank0
2658 01:34:17.501996 Final RX Vref Byte 1 = 49 to rank0
2659 01:34:17.505430 Final RX Vref Byte 0 = 47 to rank1
2660 01:34:17.509118 Final RX Vref Byte 1 = 49 to rank1==
2661 01:34:17.511924 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 01:34:17.518595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2663 01:34:17.519141 ==
2664 01:34:17.519510 DQS Delay:
2665 01:34:17.519848 DQS0 = 0, DQS1 = 0
2666 01:34:17.521872 DQM Delay:
2667 01:34:17.522325 DQM0 = 114, DQM1 = 105
2668 01:34:17.525423 DQ Delay:
2669 01:34:17.529057 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2670 01:34:17.532239 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2671 01:34:17.535110 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2672 01:34:17.538404 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2673 01:34:17.538854
2674 01:34:17.539228
2675 01:34:17.545487 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2676 01:34:17.548758 CH0 RK0: MR19=404, MR18=707
2677 01:34:17.555358 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2678 01:34:17.555909
2679 01:34:17.558586 ----->DramcWriteLeveling(PI) begin...
2680 01:34:17.559045 ==
2681 01:34:17.562167 Dram Type= 6, Freq= 0, CH_0, rank 1
2682 01:34:17.565715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2683 01:34:17.566263 ==
2684 01:34:17.568601 Write leveling (Byte 0): 26 => 26
2685 01:34:17.571984 Write leveling (Byte 1): 23 => 23
2686 01:34:17.575270 DramcWriteLeveling(PI) end<-----
2687 01:34:17.575845
2688 01:34:17.576217 ==
2689 01:34:17.578629 Dram Type= 6, Freq= 0, CH_0, rank 1
2690 01:34:17.581942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2691 01:34:17.584980 ==
2692 01:34:17.585474 [Gating] SW mode calibration
2693 01:34:17.595201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2694 01:34:17.598374 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2695 01:34:17.601909 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2696 01:34:17.608499 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2697 01:34:17.611808 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2698 01:34:17.615043 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2699 01:34:17.621672 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2700 01:34:17.625189 0 11 20 | B1->B0 | 3333 2626 | 0 1 | (0 1) (1 0)
2701 01:34:17.628301 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 01:34:17.635156 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 01:34:17.638364 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 01:34:17.641741 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 01:34:17.648464 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 01:34:17.651863 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 01:34:17.655125 0 12 16 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
2708 01:34:17.661956 0 12 20 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
2709 01:34:17.665482 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 01:34:17.668629 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 01:34:17.674872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 01:34:17.678557 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 01:34:17.682130 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 01:34:17.685223 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 01:34:17.691719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2716 01:34:17.695190 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2717 01:34:17.698325 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 01:34:17.704911 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 01:34:17.708267 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 01:34:17.712080 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 01:34:17.718349 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 01:34:17.721840 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 01:34:17.725074 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 01:34:17.731975 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 01:34:17.735022 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 01:34:17.738393 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 01:34:17.744964 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 01:34:17.748219 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 01:34:17.751853 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 01:34:17.758393 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 01:34:17.761806 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2732 01:34:17.765201 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2733 01:34:17.768414 Total UI for P1: 0, mck2ui 16
2734 01:34:17.772035 best dqsien dly found for B0: ( 0, 15, 16)
2735 01:34:17.775088 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2736 01:34:17.778512 Total UI for P1: 0, mck2ui 16
2737 01:34:17.781629 best dqsien dly found for B1: ( 0, 15, 18)
2738 01:34:17.788154 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2739 01:34:17.791488 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2740 01:34:17.792063
2741 01:34:17.794750 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2742 01:34:17.798221 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2743 01:34:17.801689 [Gating] SW calibration Done
2744 01:34:17.802369 ==
2745 01:34:17.805200 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 01:34:17.808354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 01:34:17.808818 ==
2748 01:34:17.811589 RX Vref Scan: 0
2749 01:34:17.811969
2750 01:34:17.812305 RX Vref 0 -> 0, step: 1
2751 01:34:17.812629
2752 01:34:17.815193 RX Delay -40 -> 252, step: 8
2753 01:34:17.818143 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2754 01:34:17.824995 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2755 01:34:17.828244 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2756 01:34:17.831688 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2757 01:34:17.834557 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2758 01:34:17.837971 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2759 01:34:17.844696 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2760 01:34:17.848051 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2761 01:34:17.851498 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2762 01:34:17.855027 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2763 01:34:17.857905 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2764 01:34:17.861169 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2765 01:34:17.868027 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2766 01:34:17.871414 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2767 01:34:17.874367 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2768 01:34:17.877625 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2769 01:34:17.878081 ==
2770 01:34:17.881002 Dram Type= 6, Freq= 0, CH_0, rank 1
2771 01:34:17.887827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2772 01:34:17.888369 ==
2773 01:34:17.888733 DQS Delay:
2774 01:34:17.891191 DQS0 = 0, DQS1 = 0
2775 01:34:17.891794 DQM Delay:
2776 01:34:17.894262 DQM0 = 114, DQM1 = 106
2777 01:34:17.894805 DQ Delay:
2778 01:34:17.897648 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2779 01:34:17.900867 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2780 01:34:17.904235 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2781 01:34:17.907744 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2782 01:34:17.908304
2783 01:34:17.908666
2784 01:34:17.908996 ==
2785 01:34:17.910899 Dram Type= 6, Freq= 0, CH_0, rank 1
2786 01:34:17.914179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2787 01:34:17.918143 ==
2788 01:34:17.918691
2789 01:34:17.919055
2790 01:34:17.919385 TX Vref Scan disable
2791 01:34:17.920903 == TX Byte 0 ==
2792 01:34:17.924358 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2793 01:34:17.927397 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2794 01:34:17.930957 == TX Byte 1 ==
2795 01:34:17.934441 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2796 01:34:17.937587 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2797 01:34:17.940776 ==
2798 01:34:17.943961 Dram Type= 6, Freq= 0, CH_0, rank 1
2799 01:34:17.947464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2800 01:34:17.948031 ==
2801 01:34:17.958774 TX Vref=22, minBit 5, minWin=25, winSum=409
2802 01:34:17.962049 TX Vref=24, minBit 1, minWin=25, winSum=415
2803 01:34:17.965647 TX Vref=26, minBit 8, minWin=25, winSum=420
2804 01:34:17.968802 TX Vref=28, minBit 8, minWin=25, winSum=423
2805 01:34:17.972104 TX Vref=30, minBit 8, minWin=25, winSum=429
2806 01:34:17.978486 TX Vref=32, minBit 8, minWin=25, winSum=428
2807 01:34:17.981783 [TxChooseVref] Worse bit 8, Min win 25, Win sum 429, Final Vref 30
2808 01:34:17.982244
2809 01:34:17.985226 Final TX Range 1 Vref 30
2810 01:34:17.986002
2811 01:34:17.986386 ==
2812 01:34:17.988643 Dram Type= 6, Freq= 0, CH_0, rank 1
2813 01:34:17.991907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2814 01:34:17.992382 ==
2815 01:34:17.995278
2816 01:34:17.995895
2817 01:34:17.996291 TX Vref Scan disable
2818 01:34:17.998250 == TX Byte 0 ==
2819 01:34:18.001744 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2820 01:34:18.005142 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2821 01:34:18.008673 == TX Byte 1 ==
2822 01:34:18.012019 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2823 01:34:18.015099 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2824 01:34:18.018388
2825 01:34:18.018943 [DATLAT]
2826 01:34:18.019310 Freq=1200, CH0 RK1
2827 01:34:18.019652
2828 01:34:18.021780 DATLAT Default: 0xc
2829 01:34:18.022232 0, 0xFFFF, sum = 0
2830 01:34:18.024678 1, 0xFFFF, sum = 0
2831 01:34:18.025141 2, 0xFFFF, sum = 0
2832 01:34:18.028414 3, 0xFFFF, sum = 0
2833 01:34:18.031493 4, 0xFFFF, sum = 0
2834 01:34:18.031962 5, 0xFFFF, sum = 0
2835 01:34:18.034705 6, 0xFFFF, sum = 0
2836 01:34:18.035171 7, 0xFFFF, sum = 0
2837 01:34:18.038210 8, 0xFFFF, sum = 0
2838 01:34:18.038676 9, 0xFFFF, sum = 0
2839 01:34:18.041586 10, 0xFFFF, sum = 0
2840 01:34:18.042070 11, 0x0, sum = 1
2841 01:34:18.045007 12, 0x0, sum = 2
2842 01:34:18.045692 13, 0x0, sum = 3
2843 01:34:18.048119 14, 0x0, sum = 4
2844 01:34:18.048598 best_step = 12
2845 01:34:18.049082
2846 01:34:18.049586 ==
2847 01:34:18.051359 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 01:34:18.055061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 01:34:18.055640 ==
2850 01:34:18.058089 RX Vref Scan: 0
2851 01:34:18.058565
2852 01:34:18.061507 RX Vref 0 -> 0, step: 1
2853 01:34:18.062064
2854 01:34:18.062549 RX Delay -21 -> 252, step: 4
2855 01:34:18.069020 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2856 01:34:18.072670 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2857 01:34:18.075384 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2858 01:34:18.079043 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2859 01:34:18.082071 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2860 01:34:18.089063 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2861 01:34:18.092278 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2862 01:34:18.095669 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2863 01:34:18.099077 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2864 01:34:18.102241 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2865 01:34:18.108866 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2866 01:34:18.112319 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2867 01:34:18.115422 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2868 01:34:18.118676 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2869 01:34:18.121910 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2870 01:34:18.129019 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2871 01:34:18.129640 ==
2872 01:34:18.132054 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 01:34:18.135486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2874 01:34:18.136081 ==
2875 01:34:18.136587 DQS Delay:
2876 01:34:18.138924 DQS0 = 0, DQS1 = 0
2877 01:34:18.139496 DQM Delay:
2878 01:34:18.142046 DQM0 = 114, DQM1 = 106
2879 01:34:18.142523 DQ Delay:
2880 01:34:18.145459 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2881 01:34:18.148623 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2882 01:34:18.152131 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2883 01:34:18.155478 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2884 01:34:18.155980
2885 01:34:18.156349
2886 01:34:18.165196 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2887 01:34:18.168549 CH0 RK1: MR19=404, MR18=C0C
2888 01:34:18.171729 CH0_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2889 01:34:18.175677 [RxdqsGatingPostProcess] freq 1200
2890 01:34:18.181683 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2891 01:34:18.185112 Pre-setting of DQS Precalculation
2892 01:34:18.188216 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2893 01:34:18.191464 ==
2894 01:34:18.195424 Dram Type= 6, Freq= 0, CH_1, rank 0
2895 01:34:18.197968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2896 01:34:18.198428 ==
2897 01:34:18.204433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2898 01:34:18.208062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2899 01:34:18.217151 [CA 0] Center 37 (7~68) winsize 62
2900 01:34:18.220605 [CA 1] Center 37 (7~68) winsize 62
2901 01:34:18.223808 [CA 2] Center 34 (4~65) winsize 62
2902 01:34:18.227074 [CA 3] Center 33 (3~64) winsize 62
2903 01:34:18.230320 [CA 4] Center 32 (2~63) winsize 62
2904 01:34:18.233658 [CA 5] Center 32 (2~63) winsize 62
2905 01:34:18.233990
2906 01:34:18.237019 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2907 01:34:18.237386
2908 01:34:18.240208 [CATrainingPosCal] consider 1 rank data
2909 01:34:18.243800 u2DelayCellTimex100 = 270/100 ps
2910 01:34:18.247176 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2911 01:34:18.250384 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2912 01:34:18.256959 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2913 01:34:18.260405 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2914 01:34:18.263477 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2915 01:34:18.266778 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2916 01:34:18.267026
2917 01:34:18.269981 CA PerBit enable=1, Macro0, CA PI delay=32
2918 01:34:18.270178
2919 01:34:18.273204 [CBTSetCACLKResult] CA Dly = 32
2920 01:34:18.273424 CS Dly: 6 (0~37)
2921 01:34:18.276748 ==
2922 01:34:18.276937 Dram Type= 6, Freq= 0, CH_1, rank 1
2923 01:34:18.283680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2924 01:34:18.283872 ==
2925 01:34:18.286642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2926 01:34:18.293205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2927 01:34:18.302042 [CA 0] Center 37 (6~68) winsize 63
2928 01:34:18.305390 [CA 1] Center 37 (7~68) winsize 62
2929 01:34:18.308787 [CA 2] Center 34 (3~65) winsize 63
2930 01:34:18.312219 [CA 3] Center 33 (3~64) winsize 62
2931 01:34:18.315420 [CA 4] Center 32 (2~63) winsize 62
2932 01:34:18.318707 [CA 5] Center 32 (1~63) winsize 63
2933 01:34:18.318897
2934 01:34:18.322019 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2935 01:34:18.322239
2936 01:34:18.325385 [CATrainingPosCal] consider 2 rank data
2937 01:34:18.328664 u2DelayCellTimex100 = 270/100 ps
2938 01:34:18.332051 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2939 01:34:18.335628 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2940 01:34:18.342258 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2941 01:34:18.345536 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2942 01:34:18.348799 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2943 01:34:18.352117 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2944 01:34:18.352356
2945 01:34:18.355360 CA PerBit enable=1, Macro0, CA PI delay=32
2946 01:34:18.355551
2947 01:34:18.358627 [CBTSetCACLKResult] CA Dly = 32
2948 01:34:18.358801 CS Dly: 6 (0~38)
2949 01:34:18.358926
2950 01:34:18.362092 ----->DramcWriteLeveling(PI) begin...
2951 01:34:18.362251 ==
2952 01:34:18.365573 Dram Type= 6, Freq= 0, CH_1, rank 0
2953 01:34:18.372227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2954 01:34:18.372385 ==
2955 01:34:18.375658 Write leveling (Byte 0): 20 => 20
2956 01:34:18.378983 Write leveling (Byte 1): 21 => 21
2957 01:34:18.379193 DramcWriteLeveling(PI) end<-----
2958 01:34:18.382349
2959 01:34:18.382601 ==
2960 01:34:18.385735 Dram Type= 6, Freq= 0, CH_1, rank 0
2961 01:34:18.388928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2962 01:34:18.389088 ==
2963 01:34:18.392435 [Gating] SW mode calibration
2964 01:34:18.398993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2965 01:34:18.402523 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2966 01:34:18.409325 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 01:34:18.412566 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 01:34:18.415953 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 01:34:18.422576 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2970 01:34:18.425882 0 11 16 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 0)
2971 01:34:18.429495 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2972 01:34:18.436204 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2973 01:34:18.439657 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 01:34:18.442702 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 01:34:18.449383 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 01:34:18.453038 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 01:34:18.456003 0 12 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2978 01:34:18.462627 0 12 16 | B1->B0 | 2a2a 3d3d | 0 1 | (0 0) (0 0)
2979 01:34:18.466192 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 01:34:18.469062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 01:34:18.475868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 01:34:18.478901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 01:34:18.482437 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 01:34:18.488880 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 01:34:18.492898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 01:34:18.496052 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2987 01:34:18.498977 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2988 01:34:18.505587 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 01:34:18.509282 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 01:34:18.512749 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 01:34:18.518801 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 01:34:18.522241 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 01:34:18.525733 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 01:34:18.532889 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 01:34:18.535659 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 01:34:18.539116 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 01:34:18.545659 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 01:34:18.549429 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 01:34:18.552314 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 01:34:18.558818 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 01:34:18.562165 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 01:34:18.565660 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3003 01:34:18.568768 Total UI for P1: 0, mck2ui 16
3004 01:34:18.571905 best dqsien dly found for B0: ( 0, 15, 14)
3005 01:34:18.579130 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3006 01:34:18.581996 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3007 01:34:18.585794 Total UI for P1: 0, mck2ui 16
3008 01:34:18.589068 best dqsien dly found for B1: ( 0, 15, 18)
3009 01:34:18.592498 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3010 01:34:18.595584 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3011 01:34:18.596179
3012 01:34:18.598971 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3013 01:34:18.602174 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3014 01:34:18.605419 [Gating] SW calibration Done
3015 01:34:18.605877 ==
3016 01:34:18.608773 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 01:34:18.611911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 01:34:18.615523 ==
3019 01:34:18.616084 RX Vref Scan: 0
3020 01:34:18.616455
3021 01:34:18.618753 RX Vref 0 -> 0, step: 1
3022 01:34:18.619212
3023 01:34:18.619577 RX Delay -40 -> 252, step: 8
3024 01:34:18.625678 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3025 01:34:18.629168 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3026 01:34:18.632358 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3027 01:34:18.635690 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3028 01:34:18.639115 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3029 01:34:18.645623 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3030 01:34:18.649284 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3031 01:34:18.652230 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3032 01:34:18.655901 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3033 01:34:18.658847 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3034 01:34:18.665805 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3035 01:34:18.668986 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3036 01:34:18.672567 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3037 01:34:18.675333 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3038 01:34:18.679216 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3039 01:34:18.685772 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3040 01:34:18.686357 ==
3041 01:34:18.689092 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 01:34:18.692293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3043 01:34:18.692877 ==
3044 01:34:18.693364 DQS Delay:
3045 01:34:18.695420 DQS0 = 0, DQS1 = 0
3046 01:34:18.695883 DQM Delay:
3047 01:34:18.698923 DQM0 = 116, DQM1 = 108
3048 01:34:18.699384 DQ Delay:
3049 01:34:18.702145 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3050 01:34:18.705549 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3051 01:34:18.709190 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3052 01:34:18.712281 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3053 01:34:18.712835
3054 01:34:18.713201
3055 01:34:18.713612 ==
3056 01:34:18.715306 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 01:34:18.721995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3058 01:34:18.722457 ==
3059 01:34:18.722822
3060 01:34:18.723160
3061 01:34:18.723487 TX Vref Scan disable
3062 01:34:18.725851 == TX Byte 0 ==
3063 01:34:18.729331 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3064 01:34:18.736368 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3065 01:34:18.736935 == TX Byte 1 ==
3066 01:34:18.739469 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3067 01:34:18.746086 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3068 01:34:18.746635 ==
3069 01:34:18.749087 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 01:34:18.752293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3071 01:34:18.752754 ==
3072 01:34:18.763953 TX Vref=22, minBit 3, minWin=24, winSum=409
3073 01:34:18.767359 TX Vref=24, minBit 1, minWin=25, winSum=415
3074 01:34:18.770265 TX Vref=26, minBit 0, minWin=26, winSum=421
3075 01:34:18.773824 TX Vref=28, minBit 1, minWin=26, winSum=426
3076 01:34:18.776996 TX Vref=30, minBit 3, minWin=26, winSum=429
3077 01:34:18.783330 TX Vref=32, minBit 9, minWin=26, winSum=432
3078 01:34:18.786995 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3079 01:34:18.787546
3080 01:34:18.790026 Final TX Range 1 Vref 32
3081 01:34:18.790487
3082 01:34:18.790847 ==
3083 01:34:18.793355 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 01:34:18.796718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3085 01:34:18.797275 ==
3086 01:34:18.800067
3087 01:34:18.800734
3088 01:34:18.801217 TX Vref Scan disable
3089 01:34:18.803517 == TX Byte 0 ==
3090 01:34:18.807127 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3091 01:34:18.810214 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3092 01:34:18.813595 == TX Byte 1 ==
3093 01:34:18.816677 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3094 01:34:18.820168 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3095 01:34:18.823141
3096 01:34:18.823599 [DATLAT]
3097 01:34:18.823962 Freq=1200, CH1 RK0
3098 01:34:18.824304
3099 01:34:18.826572 DATLAT Default: 0xd
3100 01:34:18.827037 0, 0xFFFF, sum = 0
3101 01:34:18.830204 1, 0xFFFF, sum = 0
3102 01:34:18.830758 2, 0xFFFF, sum = 0
3103 01:34:18.833321 3, 0xFFFF, sum = 0
3104 01:34:18.833882 4, 0xFFFF, sum = 0
3105 01:34:18.836560 5, 0xFFFF, sum = 0
3106 01:34:18.839951 6, 0xFFFF, sum = 0
3107 01:34:18.840511 7, 0xFFFF, sum = 0
3108 01:34:18.843330 8, 0xFFFF, sum = 0
3109 01:34:18.843885 9, 0xFFFF, sum = 0
3110 01:34:18.846709 10, 0xFFFF, sum = 0
3111 01:34:18.847288 11, 0x0, sum = 1
3112 01:34:18.849724 12, 0x0, sum = 2
3113 01:34:18.850193 13, 0x0, sum = 3
3114 01:34:18.850562 14, 0x0, sum = 4
3115 01:34:18.853098 best_step = 12
3116 01:34:18.853605
3117 01:34:18.853972 ==
3118 01:34:18.856874 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 01:34:18.859945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 01:34:18.860531 ==
3121 01:34:18.863085 RX Vref Scan: 1
3122 01:34:18.863541
3123 01:34:18.866411 Set Vref Range= 32 -> 127
3124 01:34:18.866872
3125 01:34:18.867238 RX Vref 32 -> 127, step: 1
3126 01:34:18.867580
3127 01:34:18.870199 RX Delay -29 -> 252, step: 4
3128 01:34:18.870751
3129 01:34:18.873282 Set Vref, RX VrefLevel [Byte0]: 32
3130 01:34:18.876578 [Byte1]: 32
3131 01:34:18.880155
3132 01:34:18.880704 Set Vref, RX VrefLevel [Byte0]: 33
3133 01:34:18.883195 [Byte1]: 33
3134 01:34:18.888088
3135 01:34:18.888638 Set Vref, RX VrefLevel [Byte0]: 34
3136 01:34:18.891283 [Byte1]: 34
3137 01:34:18.896049
3138 01:34:18.896603 Set Vref, RX VrefLevel [Byte0]: 35
3139 01:34:18.898983 [Byte1]: 35
3140 01:34:18.903931
3141 01:34:18.904488 Set Vref, RX VrefLevel [Byte0]: 36
3142 01:34:18.907463 [Byte1]: 36
3143 01:34:18.911820
3144 01:34:18.912381 Set Vref, RX VrefLevel [Byte0]: 37
3145 01:34:18.915344 [Byte1]: 37
3146 01:34:18.919882
3147 01:34:18.920442 Set Vref, RX VrefLevel [Byte0]: 38
3148 01:34:18.923055 [Byte1]: 38
3149 01:34:18.927766
3150 01:34:18.928227 Set Vref, RX VrefLevel [Byte0]: 39
3151 01:34:18.931386 [Byte1]: 39
3152 01:34:18.935785
3153 01:34:18.936341 Set Vref, RX VrefLevel [Byte0]: 40
3154 01:34:18.938756 [Byte1]: 40
3155 01:34:18.943888
3156 01:34:18.944447 Set Vref, RX VrefLevel [Byte0]: 41
3157 01:34:18.947077 [Byte1]: 41
3158 01:34:18.951551
3159 01:34:18.952011 Set Vref, RX VrefLevel [Byte0]: 42
3160 01:34:18.954719 [Byte1]: 42
3161 01:34:18.959817
3162 01:34:18.960435 Set Vref, RX VrefLevel [Byte0]: 43
3163 01:34:18.962826 [Byte1]: 43
3164 01:34:18.967490
3165 01:34:18.967946 Set Vref, RX VrefLevel [Byte0]: 44
3166 01:34:18.970749 [Byte1]: 44
3167 01:34:18.975456
3168 01:34:18.975933 Set Vref, RX VrefLevel [Byte0]: 45
3169 01:34:18.978673 [Byte1]: 45
3170 01:34:18.983295
3171 01:34:18.983767 Set Vref, RX VrefLevel [Byte0]: 46
3172 01:34:18.987026 [Byte1]: 46
3173 01:34:18.991437
3174 01:34:18.991911 Set Vref, RX VrefLevel [Byte0]: 47
3175 01:34:18.994715 [Byte1]: 47
3176 01:34:18.999749
3177 01:34:19.000336 Set Vref, RX VrefLevel [Byte0]: 48
3178 01:34:19.002626 [Byte1]: 48
3179 01:34:19.007163
3180 01:34:19.007635 Set Vref, RX VrefLevel [Byte0]: 49
3181 01:34:19.010581 [Byte1]: 49
3182 01:34:19.015405
3183 01:34:19.016057 Set Vref, RX VrefLevel [Byte0]: 50
3184 01:34:19.018365 [Byte1]: 50
3185 01:34:19.023033
3186 01:34:19.026711 Set Vref, RX VrefLevel [Byte0]: 51
3187 01:34:19.029537 [Byte1]: 51
3188 01:34:19.030003
3189 01:34:19.033188 Set Vref, RX VrefLevel [Byte0]: 52
3190 01:34:19.036461 [Byte1]: 52
3191 01:34:19.036924
3192 01:34:19.040048 Set Vref, RX VrefLevel [Byte0]: 53
3193 01:34:19.042749 [Byte1]: 53
3194 01:34:19.047263
3195 01:34:19.047820 Set Vref, RX VrefLevel [Byte0]: 54
3196 01:34:19.050391 [Byte1]: 54
3197 01:34:19.055375
3198 01:34:19.055935 Set Vref, RX VrefLevel [Byte0]: 55
3199 01:34:19.058387 [Byte1]: 55
3200 01:34:19.063117
3201 01:34:19.063673 Set Vref, RX VrefLevel [Byte0]: 56
3202 01:34:19.066317 [Byte1]: 56
3203 01:34:19.070717
3204 01:34:19.071174 Set Vref, RX VrefLevel [Byte0]: 57
3205 01:34:19.074263 [Byte1]: 57
3206 01:34:19.078910
3207 01:34:19.079367 Set Vref, RX VrefLevel [Byte0]: 58
3208 01:34:19.082110 [Byte1]: 58
3209 01:34:19.087106
3210 01:34:19.087660 Set Vref, RX VrefLevel [Byte0]: 59
3211 01:34:19.090497 [Byte1]: 59
3212 01:34:19.094804
3213 01:34:19.095261 Set Vref, RX VrefLevel [Byte0]: 60
3214 01:34:19.098132 [Byte1]: 60
3215 01:34:19.102705
3216 01:34:19.103164 Set Vref, RX VrefLevel [Byte0]: 61
3217 01:34:19.105975 [Byte1]: 61
3218 01:34:19.110858
3219 01:34:19.111410 Set Vref, RX VrefLevel [Byte0]: 62
3220 01:34:19.114130 [Byte1]: 62
3221 01:34:19.118801
3222 01:34:19.119404 Set Vref, RX VrefLevel [Byte0]: 63
3223 01:34:19.122099 [Byte1]: 63
3224 01:34:19.126536
3225 01:34:19.126992 Set Vref, RX VrefLevel [Byte0]: 64
3226 01:34:19.129989 [Byte1]: 64
3227 01:34:19.134759
3228 01:34:19.135217 Set Vref, RX VrefLevel [Byte0]: 65
3229 01:34:19.137912 [Byte1]: 65
3230 01:34:19.142697
3231 01:34:19.143154 Final RX Vref Byte 0 = 57 to rank0
3232 01:34:19.145836 Final RX Vref Byte 1 = 50 to rank0
3233 01:34:19.149196 Final RX Vref Byte 0 = 57 to rank1
3234 01:34:19.152570 Final RX Vref Byte 1 = 50 to rank1==
3235 01:34:19.155791 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 01:34:19.162722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3237 01:34:19.163184 ==
3238 01:34:19.163549 DQS Delay:
3239 01:34:19.163886 DQS0 = 0, DQS1 = 0
3240 01:34:19.165941 DQM Delay:
3241 01:34:19.166356 DQM0 = 115, DQM1 = 106
3242 01:34:19.169269 DQ Delay:
3243 01:34:19.172745 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3244 01:34:19.175688 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3245 01:34:19.179013 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3246 01:34:19.182542 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3247 01:34:19.182962
3248 01:34:19.183295
3249 01:34:19.189114 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3250 01:34:19.192571 CH1 RK0: MR19=404, MR18=1313
3251 01:34:19.199355 CH1_RK0: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
3252 01:34:19.199915
3253 01:34:19.202244 ----->DramcWriteLeveling(PI) begin...
3254 01:34:19.202874 ==
3255 01:34:19.205670 Dram Type= 6, Freq= 0, CH_1, rank 1
3256 01:34:19.209142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3257 01:34:19.212462 ==
3258 01:34:19.213007 Write leveling (Byte 0): 21 => 21
3259 01:34:19.215627 Write leveling (Byte 1): 23 => 23
3260 01:34:19.219169 DramcWriteLeveling(PI) end<-----
3261 01:34:19.219717
3262 01:34:19.220089 ==
3263 01:34:19.222325 Dram Type= 6, Freq= 0, CH_1, rank 1
3264 01:34:19.228960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3265 01:34:19.229631 ==
3266 01:34:19.230012 [Gating] SW mode calibration
3267 01:34:19.238781 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3268 01:34:19.242218 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3269 01:34:19.249244 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3270 01:34:19.252140 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3271 01:34:19.256205 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3272 01:34:19.258902 0 11 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
3273 01:34:19.265574 0 11 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
3274 01:34:19.268847 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3275 01:34:19.272443 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 01:34:19.278806 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 01:34:19.282168 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 01:34:19.285408 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 01:34:19.292356 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3280 01:34:19.295870 0 12 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
3281 01:34:19.298967 0 12 16 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
3282 01:34:19.305349 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 01:34:19.308960 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 01:34:19.312448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 01:34:19.318901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 01:34:19.322040 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 01:34:19.325681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 01:34:19.332267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3289 01:34:19.335658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3290 01:34:19.338691 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 01:34:19.345387 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 01:34:19.348839 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 01:34:19.352022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 01:34:19.358523 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 01:34:19.362026 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 01:34:19.365676 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 01:34:19.371894 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 01:34:19.375237 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 01:34:19.378474 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 01:34:19.382127 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 01:34:19.388706 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 01:34:19.392083 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 01:34:19.395203 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 01:34:19.401950 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3305 01:34:19.405430 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3306 01:34:19.408657 Total UI for P1: 0, mck2ui 16
3307 01:34:19.412144 best dqsien dly found for B0: ( 0, 15, 12)
3308 01:34:19.415515 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3309 01:34:19.422317 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3310 01:34:19.422887 Total UI for P1: 0, mck2ui 16
3311 01:34:19.428712 best dqsien dly found for B1: ( 0, 15, 18)
3312 01:34:19.432315 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3313 01:34:19.435682 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3314 01:34:19.436252
3315 01:34:19.439026 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3316 01:34:19.442274 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3317 01:34:19.445401 [Gating] SW calibration Done
3318 01:34:19.445941 ==
3319 01:34:19.448756 Dram Type= 6, Freq= 0, CH_1, rank 1
3320 01:34:19.451889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3321 01:34:19.452350 ==
3322 01:34:19.455425 RX Vref Scan: 0
3323 01:34:19.455969
3324 01:34:19.456335 RX Vref 0 -> 0, step: 1
3325 01:34:19.456674
3326 01:34:19.458837 RX Delay -40 -> 252, step: 8
3327 01:34:19.461821 iDelay=208, Bit 0, Center 115 (40 ~ 191) 152
3328 01:34:19.468826 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3329 01:34:19.471918 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3330 01:34:19.475278 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3331 01:34:19.478580 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3332 01:34:19.481963 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3333 01:34:19.488511 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3334 01:34:19.491963 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3335 01:34:19.494938 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3336 01:34:19.498367 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3337 01:34:19.501508 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3338 01:34:19.508308 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3339 01:34:19.511661 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3340 01:34:19.515040 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3341 01:34:19.518581 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3342 01:34:19.521976 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3343 01:34:19.525650 ==
3344 01:34:19.528406 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 01:34:19.531880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 01:34:19.532428 ==
3347 01:34:19.532787 DQS Delay:
3348 01:34:19.535119 DQS0 = 0, DQS1 = 0
3349 01:34:19.535658 DQM Delay:
3350 01:34:19.538197 DQM0 = 116, DQM1 = 106
3351 01:34:19.538645 DQ Delay:
3352 01:34:19.541873 DQ0 =115, DQ1 =115, DQ2 =107, DQ3 =115
3353 01:34:19.545127 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3354 01:34:19.548506 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3355 01:34:19.551487 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3356 01:34:19.552105
3357 01:34:19.552476
3358 01:34:19.552814 ==
3359 01:34:19.555026 Dram Type= 6, Freq= 0, CH_1, rank 1
3360 01:34:19.561372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3361 01:34:19.561939 ==
3362 01:34:19.562304
3363 01:34:19.562639
3364 01:34:19.562959 TX Vref Scan disable
3365 01:34:19.564662 == TX Byte 0 ==
3366 01:34:19.568131 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3367 01:34:19.574717 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3368 01:34:19.575265 == TX Byte 1 ==
3369 01:34:19.577980 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3370 01:34:19.584706 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3371 01:34:19.585244 ==
3372 01:34:19.588141 Dram Type= 6, Freq= 0, CH_1, rank 1
3373 01:34:19.591362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3374 01:34:19.591930 ==
3375 01:34:19.602590 TX Vref=22, minBit 1, minWin=26, winSum=423
3376 01:34:19.605863 TX Vref=24, minBit 0, minWin=26, winSum=424
3377 01:34:19.609127 TX Vref=26, minBit 3, minWin=26, winSum=428
3378 01:34:19.612579 TX Vref=28, minBit 8, minWin=26, winSum=431
3379 01:34:19.616298 TX Vref=30, minBit 8, minWin=26, winSum=428
3380 01:34:19.619228 TX Vref=32, minBit 9, minWin=26, winSum=432
3381 01:34:19.625963 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3382 01:34:19.626418
3383 01:34:19.629149 Final TX Range 1 Vref 32
3384 01:34:19.629765
3385 01:34:19.630136 ==
3386 01:34:19.632678 Dram Type= 6, Freq= 0, CH_1, rank 1
3387 01:34:19.636033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3388 01:34:19.636583 ==
3389 01:34:19.639656
3390 01:34:19.640202
3391 01:34:19.640562 TX Vref Scan disable
3392 01:34:19.642652 == TX Byte 0 ==
3393 01:34:19.645958 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3394 01:34:19.649467 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3395 01:34:19.652564 == TX Byte 1 ==
3396 01:34:19.655995 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3397 01:34:19.659335 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3398 01:34:19.662484
3399 01:34:19.663034 [DATLAT]
3400 01:34:19.663400 Freq=1200, CH1 RK1
3401 01:34:19.663741
3402 01:34:19.665919 DATLAT Default: 0xc
3403 01:34:19.666467 0, 0xFFFF, sum = 0
3404 01:34:19.669196 1, 0xFFFF, sum = 0
3405 01:34:19.669785 2, 0xFFFF, sum = 0
3406 01:34:19.672330 3, 0xFFFF, sum = 0
3407 01:34:19.672795 4, 0xFFFF, sum = 0
3408 01:34:19.675862 5, 0xFFFF, sum = 0
3409 01:34:19.679262 6, 0xFFFF, sum = 0
3410 01:34:19.679729 7, 0xFFFF, sum = 0
3411 01:34:19.682699 8, 0xFFFF, sum = 0
3412 01:34:19.683257 9, 0xFFFF, sum = 0
3413 01:34:19.685996 10, 0xFFFF, sum = 0
3414 01:34:19.686462 11, 0x0, sum = 1
3415 01:34:19.686835 12, 0x0, sum = 2
3416 01:34:19.689097 13, 0x0, sum = 3
3417 01:34:19.689616 14, 0x0, sum = 4
3418 01:34:19.692675 best_step = 12
3419 01:34:19.693224
3420 01:34:19.693628 ==
3421 01:34:19.695889 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 01:34:19.699421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3423 01:34:19.699978 ==
3424 01:34:19.702513 RX Vref Scan: 0
3425 01:34:19.702975
3426 01:34:19.703343 RX Vref 0 -> 0, step: 1
3427 01:34:19.703684
3428 01:34:19.705606 RX Delay -29 -> 252, step: 4
3429 01:34:19.712798 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3430 01:34:19.716167 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3431 01:34:19.719401 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3432 01:34:19.722857 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3433 01:34:19.725998 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3434 01:34:19.732948 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3435 01:34:19.736204 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3436 01:34:19.739448 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3437 01:34:19.742929 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3438 01:34:19.745972 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3439 01:34:19.752910 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3440 01:34:19.756382 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3441 01:34:19.759410 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3442 01:34:19.762621 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3443 01:34:19.766280 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3444 01:34:19.773053 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3445 01:34:19.773644 ==
3446 01:34:19.776124 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 01:34:19.779413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3448 01:34:19.779877 ==
3449 01:34:19.780242 DQS Delay:
3450 01:34:19.782596 DQS0 = 0, DQS1 = 0
3451 01:34:19.783056 DQM Delay:
3452 01:34:19.786075 DQM0 = 114, DQM1 = 104
3453 01:34:19.786535 DQ Delay:
3454 01:34:19.789130 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3455 01:34:19.792753 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3456 01:34:19.795958 DQ8 =88, DQ9 =92, DQ10 =106, DQ11 =98
3457 01:34:19.799268 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =110
3458 01:34:19.799819
3459 01:34:19.800187
3460 01:34:19.809637 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3461 01:34:19.812538 CH1 RK1: MR19=404, MR18=B0B
3462 01:34:19.815881 CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3463 01:34:19.819341 [RxdqsGatingPostProcess] freq 1200
3464 01:34:19.825875 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3465 01:34:19.828967 Pre-setting of DQS Precalculation
3466 01:34:19.832397 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3467 01:34:19.842794 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3468 01:34:19.849370 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3469 01:34:19.849931
3470 01:34:19.850358
3471 01:34:19.852464 [Calibration Summary] 2400 Mbps
3472 01:34:19.852992 CH 0, Rank 0
3473 01:34:19.855861 SW Impedance : PASS
3474 01:34:19.856411 DUTY Scan : NO K
3475 01:34:19.859174 ZQ Calibration : PASS
3476 01:34:19.862246 Jitter Meter : NO K
3477 01:34:19.862704 CBT Training : PASS
3478 01:34:19.865662 Write leveling : PASS
3479 01:34:19.869007 RX DQS gating : PASS
3480 01:34:19.869498 RX DQ/DQS(RDDQC) : PASS
3481 01:34:19.872538 TX DQ/DQS : PASS
3482 01:34:19.875745 RX DATLAT : PASS
3483 01:34:19.876202 RX DQ/DQS(Engine): PASS
3484 01:34:19.878859 TX OE : NO K
3485 01:34:19.879318 All Pass.
3486 01:34:19.879684
3487 01:34:19.882189 CH 0, Rank 1
3488 01:34:19.882644 SW Impedance : PASS
3489 01:34:19.885474 DUTY Scan : NO K
3490 01:34:19.889545 ZQ Calibration : PASS
3491 01:34:19.890095 Jitter Meter : NO K
3492 01:34:19.892343 CBT Training : PASS
3493 01:34:19.892876 Write leveling : PASS
3494 01:34:19.895665 RX DQS gating : PASS
3495 01:34:19.899216 RX DQ/DQS(RDDQC) : PASS
3496 01:34:19.899770 TX DQ/DQS : PASS
3497 01:34:19.902283 RX DATLAT : PASS
3498 01:34:19.905696 RX DQ/DQS(Engine): PASS
3499 01:34:19.906364 TX OE : NO K
3500 01:34:19.908878 All Pass.
3501 01:34:19.909393
3502 01:34:19.909765 CH 1, Rank 0
3503 01:34:19.912373 SW Impedance : PASS
3504 01:34:19.912917 DUTY Scan : NO K
3505 01:34:19.915546 ZQ Calibration : PASS
3506 01:34:19.918714 Jitter Meter : NO K
3507 01:34:19.919231 CBT Training : PASS
3508 01:34:19.922092 Write leveling : PASS
3509 01:34:19.925531 RX DQS gating : PASS
3510 01:34:19.926076 RX DQ/DQS(RDDQC) : PASS
3511 01:34:19.929161 TX DQ/DQS : PASS
3512 01:34:19.932625 RX DATLAT : PASS
3513 01:34:19.933206 RX DQ/DQS(Engine): PASS
3514 01:34:19.935413 TX OE : NO K
3515 01:34:19.935963 All Pass.
3516 01:34:19.936332
3517 01:34:19.938881 CH 1, Rank 1
3518 01:34:19.939432 SW Impedance : PASS
3519 01:34:19.941979 DUTY Scan : NO K
3520 01:34:19.942438 ZQ Calibration : PASS
3521 01:34:19.945278 Jitter Meter : NO K
3522 01:34:19.949083 CBT Training : PASS
3523 01:34:19.949669 Write leveling : PASS
3524 01:34:19.951921 RX DQS gating : PASS
3525 01:34:19.955695 RX DQ/DQS(RDDQC) : PASS
3526 01:34:19.956248 TX DQ/DQS : PASS
3527 01:34:19.958838 RX DATLAT : PASS
3528 01:34:19.962052 RX DQ/DQS(Engine): PASS
3529 01:34:19.962659 TX OE : NO K
3530 01:34:19.965138 All Pass.
3531 01:34:19.965646
3532 01:34:19.966015 DramC Write-DBI off
3533 01:34:19.968428 PER_BANK_REFRESH: Hybrid Mode
3534 01:34:19.968886 TX_TRACKING: ON
3535 01:34:19.978694 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3536 01:34:19.981950 [FAST_K] Save calibration result to emmc
3537 01:34:19.985685 dramc_set_vcore_voltage set vcore to 650000
3538 01:34:19.988918 Read voltage for 600, 5
3539 01:34:19.989501 Vio18 = 0
3540 01:34:19.992124 Vcore = 650000
3541 01:34:19.992684 Vdram = 0
3542 01:34:19.993054 Vddq = 0
3543 01:34:19.995258 Vmddr = 0
3544 01:34:19.998680 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3545 01:34:20.005282 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3546 01:34:20.005881 MEM_TYPE=3, freq_sel=19
3547 01:34:20.008332 sv_algorithm_assistance_LP4_1600
3548 01:34:20.015329 ============ PULL DRAM RESETB DOWN ============
3549 01:34:20.018185 ========== PULL DRAM RESETB DOWN end =========
3550 01:34:20.021805 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3551 01:34:20.025096 ===================================
3552 01:34:20.028376 LPDDR4 DRAM CONFIGURATION
3553 01:34:20.031677 ===================================
3554 01:34:20.034912 EX_ROW_EN[0] = 0x0
3555 01:34:20.035460 EX_ROW_EN[1] = 0x0
3556 01:34:20.038042 LP4Y_EN = 0x0
3557 01:34:20.038498 WORK_FSP = 0x0
3558 01:34:20.041468 WL = 0x2
3559 01:34:20.041923 RL = 0x2
3560 01:34:20.044769 BL = 0x2
3561 01:34:20.045352 RPST = 0x0
3562 01:34:20.048188 RD_PRE = 0x0
3563 01:34:20.048735 WR_PRE = 0x1
3564 01:34:20.051221 WR_PST = 0x0
3565 01:34:20.051676 DBI_WR = 0x0
3566 01:34:20.054656 DBI_RD = 0x0
3567 01:34:20.055128 OTF = 0x1
3568 01:34:20.058044 ===================================
3569 01:34:20.061448 ===================================
3570 01:34:20.064848 ANA top config
3571 01:34:20.068008 ===================================
3572 01:34:20.071067 DLL_ASYNC_EN = 0
3573 01:34:20.071614 ALL_SLAVE_EN = 1
3574 01:34:20.074334 NEW_RANK_MODE = 1
3575 01:34:20.077892 DLL_IDLE_MODE = 1
3576 01:34:20.081005 LP45_APHY_COMB_EN = 1
3577 01:34:20.081485 TX_ODT_DIS = 1
3578 01:34:20.084475 NEW_8X_MODE = 1
3579 01:34:20.087906 ===================================
3580 01:34:20.091156 ===================================
3581 01:34:20.094213 data_rate = 1200
3582 01:34:20.097775 CKR = 1
3583 01:34:20.101069 DQ_P2S_RATIO = 8
3584 01:34:20.104318 ===================================
3585 01:34:20.107373 CA_P2S_RATIO = 8
3586 01:34:20.107873 DQ_CA_OPEN = 0
3587 01:34:20.110950 DQ_SEMI_OPEN = 0
3588 01:34:20.114111 CA_SEMI_OPEN = 0
3589 01:34:20.117211 CA_FULL_RATE = 0
3590 01:34:20.120951 DQ_CKDIV4_EN = 1
3591 01:34:20.124123 CA_CKDIV4_EN = 1
3592 01:34:20.124677 CA_PREDIV_EN = 0
3593 01:34:20.127401 PH8_DLY = 0
3594 01:34:20.130995 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3595 01:34:20.134198 DQ_AAMCK_DIV = 4
3596 01:34:20.137632 CA_AAMCK_DIV = 4
3597 01:34:20.140832 CA_ADMCK_DIV = 4
3598 01:34:20.141411 DQ_TRACK_CA_EN = 0
3599 01:34:20.144379 CA_PICK = 600
3600 01:34:20.147470 CA_MCKIO = 600
3601 01:34:20.150934 MCKIO_SEMI = 0
3602 01:34:20.153925 PLL_FREQ = 2288
3603 01:34:20.156986 DQ_UI_PI_RATIO = 32
3604 01:34:20.160445 CA_UI_PI_RATIO = 0
3605 01:34:20.163827 ===================================
3606 01:34:20.167458 ===================================
3607 01:34:20.168012 memory_type:LPDDR4
3608 01:34:20.170296 GP_NUM : 10
3609 01:34:20.173920 SRAM_EN : 1
3610 01:34:20.174468 MD32_EN : 0
3611 01:34:20.177159 ===================================
3612 01:34:20.180364 [ANA_INIT] >>>>>>>>>>>>>>
3613 01:34:20.183905 <<<<<< [CONFIGURE PHASE]: ANA_TX
3614 01:34:20.187019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3615 01:34:20.190597 ===================================
3616 01:34:20.193612 data_rate = 1200,PCW = 0X5800
3617 01:34:20.197026 ===================================
3618 01:34:20.200349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3619 01:34:20.203747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3620 01:34:20.210329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3621 01:34:20.213701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3622 01:34:20.217126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3623 01:34:20.220407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3624 01:34:20.223714 [ANA_INIT] flow start
3625 01:34:20.226736 [ANA_INIT] PLL >>>>>>>>
3626 01:34:20.227198 [ANA_INIT] PLL <<<<<<<<
3627 01:34:20.230366 [ANA_INIT] MIDPI >>>>>>>>
3628 01:34:20.233596 [ANA_INIT] MIDPI <<<<<<<<
3629 01:34:20.236855 [ANA_INIT] DLL >>>>>>>>
3630 01:34:20.237462 [ANA_INIT] flow end
3631 01:34:20.240040 ============ LP4 DIFF to SE enter ============
3632 01:34:20.246890 ============ LP4 DIFF to SE exit ============
3633 01:34:20.247442 [ANA_INIT] <<<<<<<<<<<<<
3634 01:34:20.250015 [Flow] Enable top DCM control >>>>>
3635 01:34:20.253433 [Flow] Enable top DCM control <<<<<
3636 01:34:20.256534 Enable DLL master slave shuffle
3637 01:34:20.263014 ==============================================================
3638 01:34:20.263556 Gating Mode config
3639 01:34:20.269893 ==============================================================
3640 01:34:20.272940 Config description:
3641 01:34:20.282931 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3642 01:34:20.289362 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3643 01:34:20.293003 SELPH_MODE 0: By rank 1: By Phase
3644 01:34:20.299953 ==============================================================
3645 01:34:20.302619 GAT_TRACK_EN = 1
3646 01:34:20.306053 RX_GATING_MODE = 2
3647 01:34:20.306513 RX_GATING_TRACK_MODE = 2
3648 01:34:20.309403 SELPH_MODE = 1
3649 01:34:20.312895 PICG_EARLY_EN = 1
3650 01:34:20.315857 VALID_LAT_VALUE = 1
3651 01:34:20.322905 ==============================================================
3652 01:34:20.325841 Enter into Gating configuration >>>>
3653 01:34:20.329242 Exit from Gating configuration <<<<
3654 01:34:20.332565 Enter into DVFS_PRE_config >>>>>
3655 01:34:20.342515 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3656 01:34:20.345944 Exit from DVFS_PRE_config <<<<<
3657 01:34:20.349185 Enter into PICG configuration >>>>
3658 01:34:20.352296 Exit from PICG configuration <<<<
3659 01:34:20.355583 [RX_INPUT] configuration >>>>>
3660 01:34:20.359232 [RX_INPUT] configuration <<<<<
3661 01:34:20.362574 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3662 01:34:20.369046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3663 01:34:20.375784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3664 01:34:20.382071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3665 01:34:20.388594 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3666 01:34:20.391851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3667 01:34:20.398352 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3668 01:34:20.401547 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3669 01:34:20.404838 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3670 01:34:20.408202 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3671 01:34:20.415243 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3672 01:34:20.418095 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3673 01:34:20.421150 ===================================
3674 01:34:20.424538 LPDDR4 DRAM CONFIGURATION
3675 01:34:20.427685 ===================================
3676 01:34:20.427859 EX_ROW_EN[0] = 0x0
3677 01:34:20.431328 EX_ROW_EN[1] = 0x0
3678 01:34:20.431784 LP4Y_EN = 0x0
3679 01:34:20.434710 WORK_FSP = 0x0
3680 01:34:20.435165 WL = 0x2
3681 01:34:20.438051 RL = 0x2
3682 01:34:20.441220 BL = 0x2
3683 01:34:20.441758 RPST = 0x0
3684 01:34:20.444815 RD_PRE = 0x0
3685 01:34:20.445432 WR_PRE = 0x1
3686 01:34:20.447770 WR_PST = 0x0
3687 01:34:20.448224 DBI_WR = 0x0
3688 01:34:20.451184 DBI_RD = 0x0
3689 01:34:20.451950 OTF = 0x1
3690 01:34:20.454382 ===================================
3691 01:34:20.457584 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3692 01:34:20.464156 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3693 01:34:20.468004 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3694 01:34:20.471075 ===================================
3695 01:34:20.474159 LPDDR4 DRAM CONFIGURATION
3696 01:34:20.477672 ===================================
3697 01:34:20.478270 EX_ROW_EN[0] = 0x10
3698 01:34:20.480686 EX_ROW_EN[1] = 0x0
3699 01:34:20.481488 LP4Y_EN = 0x0
3700 01:34:20.484065 WORK_FSP = 0x0
3701 01:34:20.487489 WL = 0x2
3702 01:34:20.487988 RL = 0x2
3703 01:34:20.490670 BL = 0x2
3704 01:34:20.491124 RPST = 0x0
3705 01:34:20.494076 RD_PRE = 0x0
3706 01:34:20.494779 WR_PRE = 0x1
3707 01:34:20.497167 WR_PST = 0x0
3708 01:34:20.497650 DBI_WR = 0x0
3709 01:34:20.500662 DBI_RD = 0x0
3710 01:34:20.501113 OTF = 0x1
3711 01:34:20.503862 ===================================
3712 01:34:20.510383 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3713 01:34:20.514394 nWR fixed to 30
3714 01:34:20.517940 [ModeRegInit_LP4] CH0 RK0
3715 01:34:20.518395 [ModeRegInit_LP4] CH0 RK1
3716 01:34:20.521014 [ModeRegInit_LP4] CH1 RK0
3717 01:34:20.524418 [ModeRegInit_LP4] CH1 RK1
3718 01:34:20.524870 match AC timing 16
3719 01:34:20.531034 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3720 01:34:20.534401 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3721 01:34:20.537683 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3722 01:34:20.544157 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3723 01:34:20.547385 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3724 01:34:20.547843 ==
3725 01:34:20.551138 Dram Type= 6, Freq= 0, CH_0, rank 0
3726 01:34:20.554152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3727 01:34:20.554616 ==
3728 01:34:20.561157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3729 01:34:20.567658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3730 01:34:20.571023 [CA 0] Center 35 (5~66) winsize 62
3731 01:34:20.574200 [CA 1] Center 35 (5~66) winsize 62
3732 01:34:20.577308 [CA 2] Center 34 (4~65) winsize 62
3733 01:34:20.580833 [CA 3] Center 34 (4~65) winsize 62
3734 01:34:20.584416 [CA 4] Center 33 (3~64) winsize 62
3735 01:34:20.587315 [CA 5] Center 33 (3~64) winsize 62
3736 01:34:20.587778
3737 01:34:20.590536 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3738 01:34:20.590993
3739 01:34:20.593755 [CATrainingPosCal] consider 1 rank data
3740 01:34:20.597370 u2DelayCellTimex100 = 270/100 ps
3741 01:34:20.600770 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3742 01:34:20.603973 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3743 01:34:20.607125 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3744 01:34:20.610276 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3745 01:34:20.613749 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3746 01:34:20.620624 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3747 01:34:20.621182
3748 01:34:20.623746 CA PerBit enable=1, Macro0, CA PI delay=33
3749 01:34:20.624300
3750 01:34:20.627205 [CBTSetCACLKResult] CA Dly = 33
3751 01:34:20.627877 CS Dly: 4 (0~35)
3752 01:34:20.628251 ==
3753 01:34:20.630258 Dram Type= 6, Freq= 0, CH_0, rank 1
3754 01:34:20.637030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3755 01:34:20.637632 ==
3756 01:34:20.640334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3757 01:34:20.646963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3758 01:34:20.650106 [CA 0] Center 35 (5~66) winsize 62
3759 01:34:20.653536 [CA 1] Center 35 (5~66) winsize 62
3760 01:34:20.656865 [CA 2] Center 34 (4~65) winsize 62
3761 01:34:20.660241 [CA 3] Center 34 (4~65) winsize 62
3762 01:34:20.663831 [CA 4] Center 33 (3~64) winsize 62
3763 01:34:20.666755 [CA 5] Center 33 (3~64) winsize 62
3764 01:34:20.667301
3765 01:34:20.670260 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3766 01:34:20.670814
3767 01:34:20.673952 [CATrainingPosCal] consider 2 rank data
3768 01:34:20.676530 u2DelayCellTimex100 = 270/100 ps
3769 01:34:20.680201 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3770 01:34:20.683135 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3771 01:34:20.689907 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3772 01:34:20.693523 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3773 01:34:20.696351 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3774 01:34:20.699572 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3775 01:34:20.700029
3776 01:34:20.702890 CA PerBit enable=1, Macro0, CA PI delay=33
3777 01:34:20.703348
3778 01:34:20.706103 [CBTSetCACLKResult] CA Dly = 33
3779 01:34:20.706556 CS Dly: 4 (0~36)
3780 01:34:20.706921
3781 01:34:20.713278 ----->DramcWriteLeveling(PI) begin...
3782 01:34:20.713809 ==
3783 01:34:20.716180 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 01:34:20.719477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 01:34:20.720077 ==
3786 01:34:20.722743 Write leveling (Byte 0): 31 => 31
3787 01:34:20.725985 Write leveling (Byte 1): 30 => 30
3788 01:34:20.729195 DramcWriteLeveling(PI) end<-----
3789 01:34:20.729705
3790 01:34:20.730076 ==
3791 01:34:20.732775 Dram Type= 6, Freq= 0, CH_0, rank 0
3792 01:34:20.736241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3793 01:34:20.736797 ==
3794 01:34:20.739403 [Gating] SW mode calibration
3795 01:34:20.745985 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3796 01:34:20.752445 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3797 01:34:20.756139 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3798 01:34:20.759420 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3799 01:34:20.765889 0 5 8 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 0)
3800 01:34:20.769370 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3801 01:34:20.772632 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 01:34:20.778794 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 01:34:20.782643 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 01:34:20.785773 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 01:34:20.792408 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 01:34:20.795626 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 01:34:20.798861 0 6 8 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (0 0)
3808 01:34:20.805480 0 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3809 01:34:20.808876 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 01:34:20.811999 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 01:34:20.818901 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 01:34:20.822026 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 01:34:20.825154 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 01:34:20.831642 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 01:34:20.835260 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3816 01:34:20.838471 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3817 01:34:20.845048 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 01:34:20.848356 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 01:34:20.851491 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 01:34:20.858128 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 01:34:20.861493 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 01:34:20.864719 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 01:34:20.871516 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 01:34:20.874841 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 01:34:20.878219 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 01:34:20.881895 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 01:34:20.888385 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 01:34:20.891561 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 01:34:20.894755 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 01:34:20.901436 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 01:34:20.904764 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3832 01:34:20.908121 Total UI for P1: 0, mck2ui 16
3833 01:34:20.911302 best dqsien dly found for B0: ( 0, 9, 6)
3834 01:34:20.914792 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3835 01:34:20.917942 Total UI for P1: 0, mck2ui 16
3836 01:34:20.921785 best dqsien dly found for B1: ( 0, 9, 8)
3837 01:34:20.924831 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3838 01:34:20.928053 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3839 01:34:20.928611
3840 01:34:20.934758 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3841 01:34:20.938467 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3842 01:34:20.939018 [Gating] SW calibration Done
3843 01:34:20.941513 ==
3844 01:34:20.944814 Dram Type= 6, Freq= 0, CH_0, rank 0
3845 01:34:20.947877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3846 01:34:20.948339 ==
3847 01:34:20.948701 RX Vref Scan: 0
3848 01:34:20.949038
3849 01:34:20.951089 RX Vref 0 -> 0, step: 1
3850 01:34:20.951544
3851 01:34:20.954511 RX Delay -230 -> 252, step: 16
3852 01:34:20.957747 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3853 01:34:20.961052 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3854 01:34:20.968030 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3855 01:34:20.971041 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3856 01:34:20.974416 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3857 01:34:20.977662 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3858 01:34:20.984478 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3859 01:34:20.987460 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3860 01:34:20.991067 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3861 01:34:20.994439 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3862 01:34:21.000953 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3863 01:34:21.004141 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3864 01:34:21.007548 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3865 01:34:21.010821 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3866 01:34:21.017182 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3867 01:34:21.020868 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3868 01:34:21.021477 ==
3869 01:34:21.023750 Dram Type= 6, Freq= 0, CH_0, rank 0
3870 01:34:21.027403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3871 01:34:21.027987 ==
3872 01:34:21.030317 DQS Delay:
3873 01:34:21.030773 DQS0 = 0, DQS1 = 0
3874 01:34:21.031134 DQM Delay:
3875 01:34:21.033662 DQM0 = 39, DQM1 = 33
3876 01:34:21.034118 DQ Delay:
3877 01:34:21.036964 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3878 01:34:21.040755 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3879 01:34:21.043627 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3880 01:34:21.046770 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3881 01:34:21.047228
3882 01:34:21.047585
3883 01:34:21.047919 ==
3884 01:34:21.050678 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 01:34:21.057038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 01:34:21.057649 ==
3887 01:34:21.058020
3888 01:34:21.058356
3889 01:34:21.058679 TX Vref Scan disable
3890 01:34:21.060413 == TX Byte 0 ==
3891 01:34:21.063872 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3892 01:34:21.070234 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3893 01:34:21.070780 == TX Byte 1 ==
3894 01:34:21.073781 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3895 01:34:21.080093 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3896 01:34:21.080641 ==
3897 01:34:21.083498 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 01:34:21.086992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3899 01:34:21.087563 ==
3900 01:34:21.087998
3901 01:34:21.088344
3902 01:34:21.090144 TX Vref Scan disable
3903 01:34:21.093746 == TX Byte 0 ==
3904 01:34:21.096858 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3905 01:34:21.100268 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3906 01:34:21.103493 == TX Byte 1 ==
3907 01:34:21.106725 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3908 01:34:21.110230 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3909 01:34:21.110793
3910 01:34:21.111228 [DATLAT]
3911 01:34:21.113189 Freq=600, CH0 RK0
3912 01:34:21.113689
3913 01:34:21.116735 DATLAT Default: 0x9
3914 01:34:21.117324 0, 0xFFFF, sum = 0
3915 01:34:21.119915 1, 0xFFFF, sum = 0
3916 01:34:21.120479 2, 0xFFFF, sum = 0
3917 01:34:21.123040 3, 0xFFFF, sum = 0
3918 01:34:21.123500 4, 0xFFFF, sum = 0
3919 01:34:21.126354 5, 0xFFFF, sum = 0
3920 01:34:21.126816 6, 0xFFFF, sum = 0
3921 01:34:21.129738 7, 0x0, sum = 1
3922 01:34:21.130297 8, 0x0, sum = 2
3923 01:34:21.130666 9, 0x0, sum = 3
3924 01:34:21.133122 10, 0x0, sum = 4
3925 01:34:21.133721 best_step = 8
3926 01:34:21.134085
3927 01:34:21.137191 ==
3928 01:34:21.137800 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 01:34:21.143122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3930 01:34:21.143661 ==
3931 01:34:21.144024 RX Vref Scan: 1
3932 01:34:21.144359
3933 01:34:21.146421 RX Vref 0 -> 0, step: 1
3934 01:34:21.146993
3935 01:34:21.149642 RX Delay -195 -> 252, step: 8
3936 01:34:21.150133
3937 01:34:21.153453 Set Vref, RX VrefLevel [Byte0]: 47
3938 01:34:21.156506 [Byte1]: 49
3939 01:34:21.157086
3940 01:34:21.159890 Final RX Vref Byte 0 = 47 to rank0
3941 01:34:21.163031 Final RX Vref Byte 1 = 49 to rank0
3942 01:34:21.166249 Final RX Vref Byte 0 = 47 to rank1
3943 01:34:21.169551 Final RX Vref Byte 1 = 49 to rank1==
3944 01:34:21.172925 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 01:34:21.176191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 01:34:21.176912 ==
3947 01:34:21.179312 DQS Delay:
3948 01:34:21.179821 DQS0 = 0, DQS1 = 0
3949 01:34:21.182752 DQM Delay:
3950 01:34:21.183209 DQM0 = 40, DQM1 = 29
3951 01:34:21.183569 DQ Delay:
3952 01:34:21.186029 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
3953 01:34:21.189378 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
3954 01:34:21.192654 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3955 01:34:21.196007 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
3956 01:34:21.196482
3957 01:34:21.199162
3958 01:34:21.206071 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3959 01:34:21.209342 CH0 RK0: MR19=808, MR18=4D4D
3960 01:34:21.215787 CH0_RK0: MR19=0x808, MR18=0x4D4D, DQSOSC=395, MR23=63, INC=168, DEC=112
3961 01:34:21.216249
3962 01:34:21.219325 ----->DramcWriteLeveling(PI) begin...
3963 01:34:21.219891 ==
3964 01:34:21.222678 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 01:34:21.225848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3966 01:34:21.226413 ==
3967 01:34:21.229171 Write leveling (Byte 0): 28 => 28
3968 01:34:21.232405 Write leveling (Byte 1): 29 => 29
3969 01:34:21.236019 DramcWriteLeveling(PI) end<-----
3970 01:34:21.236575
3971 01:34:21.236934 ==
3972 01:34:21.239015 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 01:34:21.242122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3974 01:34:21.242582 ==
3975 01:34:21.245670 [Gating] SW mode calibration
3976 01:34:21.252148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 01:34:21.258658 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3978 01:34:21.261725 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 01:34:21.268646 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3980 01:34:21.271949 0 5 8 | B1->B0 | 3434 3232 | 1 1 | (0 0) (0 1)
3981 01:34:21.275015 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
3982 01:34:21.281481 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 01:34:21.284726 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 01:34:21.288253 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 01:34:21.295401 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 01:34:21.298129 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 01:34:21.301356 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 01:34:21.307808 0 6 8 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
3989 01:34:21.311378 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3990 01:34:21.314625 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 01:34:21.321724 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 01:34:21.324681 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 01:34:21.327957 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 01:34:21.334540 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 01:34:21.337816 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 01:34:21.341338 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 01:34:21.347686 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 01:34:21.351078 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 01:34:21.353987 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 01:34:21.360959 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 01:34:21.364286 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 01:34:21.367641 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 01:34:21.373983 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 01:34:21.377562 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 01:34:21.380746 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 01:34:21.387328 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 01:34:21.390603 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 01:34:21.393838 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 01:34:21.397243 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 01:34:21.404195 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 01:34:21.407374 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 01:34:21.410569 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4013 01:34:21.417029 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 01:34:21.420483 Total UI for P1: 0, mck2ui 16
4015 01:34:21.423904 best dqsien dly found for B0: ( 0, 9, 8)
4016 01:34:21.426856 Total UI for P1: 0, mck2ui 16
4017 01:34:21.430239 best dqsien dly found for B1: ( 0, 9, 10)
4018 01:34:21.433610 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4019 01:34:21.437083 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4020 01:34:21.437675
4021 01:34:21.440255 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4022 01:34:21.443885 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4023 01:34:21.447013 [Gating] SW calibration Done
4024 01:34:21.447627 ==
4025 01:34:21.449996 Dram Type= 6, Freq= 0, CH_0, rank 1
4026 01:34:21.453658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4027 01:34:21.454211 ==
4028 01:34:21.456757 RX Vref Scan: 0
4029 01:34:21.457326
4030 01:34:21.460026 RX Vref 0 -> 0, step: 1
4031 01:34:21.460573
4032 01:34:21.460937 RX Delay -230 -> 252, step: 16
4033 01:34:21.466716 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4034 01:34:21.469984 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4035 01:34:21.473398 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4036 01:34:21.476634 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4037 01:34:21.483202 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4038 01:34:21.486325 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4039 01:34:21.489671 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4040 01:34:21.493129 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4041 01:34:21.499881 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4042 01:34:21.503001 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4043 01:34:21.506070 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4044 01:34:21.509405 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4045 01:34:21.516141 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4046 01:34:21.519708 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4047 01:34:21.523194 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4048 01:34:21.526052 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4049 01:34:21.526509 ==
4050 01:34:21.529378 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 01:34:21.536327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4052 01:34:21.536973 ==
4053 01:34:21.537402 DQS Delay:
4054 01:34:21.537753 DQS0 = 0, DQS1 = 0
4055 01:34:21.539341 DQM Delay:
4056 01:34:21.539797 DQM0 = 40, DQM1 = 33
4057 01:34:21.542586 DQ Delay:
4058 01:34:21.546075 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4059 01:34:21.549115 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4060 01:34:21.552441 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4061 01:34:21.555793 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4062 01:34:21.556247
4063 01:34:21.556604
4064 01:34:21.556937 ==
4065 01:34:21.559108 Dram Type= 6, Freq= 0, CH_0, rank 1
4066 01:34:21.562325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4067 01:34:21.562785 ==
4068 01:34:21.563149
4069 01:34:21.563485
4070 01:34:21.565896 TX Vref Scan disable
4071 01:34:21.566347 == TX Byte 0 ==
4072 01:34:21.572670 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4073 01:34:21.575620 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4074 01:34:21.576079 == TX Byte 1 ==
4075 01:34:21.582223 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4076 01:34:21.585675 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4077 01:34:21.586134 ==
4078 01:34:21.588831 Dram Type= 6, Freq= 0, CH_0, rank 1
4079 01:34:21.592152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4080 01:34:21.592626 ==
4081 01:34:21.595457
4082 01:34:21.596008
4083 01:34:21.596370 TX Vref Scan disable
4084 01:34:21.599084 == TX Byte 0 ==
4085 01:34:21.602139 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4086 01:34:21.608758 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4087 01:34:21.609215 == TX Byte 1 ==
4088 01:34:21.612361 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4089 01:34:21.618907 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4090 01:34:21.619450
4091 01:34:21.619839 [DATLAT]
4092 01:34:21.620369 Freq=600, CH0 RK1
4093 01:34:21.620721
4094 01:34:21.622173 DATLAT Default: 0x8
4095 01:34:21.622658 0, 0xFFFF, sum = 0
4096 01:34:21.625346 1, 0xFFFF, sum = 0
4097 01:34:21.628687 2, 0xFFFF, sum = 0
4098 01:34:21.629147 3, 0xFFFF, sum = 0
4099 01:34:21.632111 4, 0xFFFF, sum = 0
4100 01:34:21.632574 5, 0xFFFF, sum = 0
4101 01:34:21.635406 6, 0xFFFF, sum = 0
4102 01:34:21.635871 7, 0x0, sum = 1
4103 01:34:21.636238 8, 0x0, sum = 2
4104 01:34:21.638693 9, 0x0, sum = 3
4105 01:34:21.639307 10, 0x0, sum = 4
4106 01:34:21.641821 best_step = 8
4107 01:34:21.642421
4108 01:34:21.642954 ==
4109 01:34:21.645254 Dram Type= 6, Freq= 0, CH_0, rank 1
4110 01:34:21.648454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4111 01:34:21.648911 ==
4112 01:34:21.652082 RX Vref Scan: 0
4113 01:34:21.652535
4114 01:34:21.652898 RX Vref 0 -> 0, step: 1
4115 01:34:21.653238
4116 01:34:21.655066 RX Delay -195 -> 252, step: 8
4117 01:34:21.662479 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4118 01:34:21.665641 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4119 01:34:21.669033 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4120 01:34:21.672492 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4121 01:34:21.678944 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4122 01:34:21.682132 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4123 01:34:21.685648 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4124 01:34:21.688910 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4125 01:34:21.695477 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4126 01:34:21.698810 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4127 01:34:21.702127 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4128 01:34:21.705536 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4129 01:34:21.712313 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4130 01:34:21.715238 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4131 01:34:21.718394 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4132 01:34:21.722109 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4133 01:34:21.722699 ==
4134 01:34:21.725263 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 01:34:21.731712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4136 01:34:21.732246 ==
4137 01:34:21.732751 DQS Delay:
4138 01:34:21.735377 DQS0 = 0, DQS1 = 0
4139 01:34:21.735922 DQM Delay:
4140 01:34:21.736292 DQM0 = 41, DQM1 = 31
4141 01:34:21.738897 DQ Delay:
4142 01:34:21.741656 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4143 01:34:21.744973 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4144 01:34:21.748250 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4145 01:34:21.751530 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4146 01:34:21.751990
4147 01:34:21.752349
4148 01:34:21.758475 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4149 01:34:21.761664 CH0 RK1: MR19=808, MR18=6161
4150 01:34:21.768453 CH0_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4151 01:34:21.771700 [RxdqsGatingPostProcess] freq 600
4152 01:34:21.775218 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4153 01:34:21.778219 Pre-setting of DQS Precalculation
4154 01:34:21.784947 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4155 01:34:21.785547 ==
4156 01:34:21.787898 Dram Type= 6, Freq= 0, CH_1, rank 0
4157 01:34:21.791156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4158 01:34:21.791639 ==
4159 01:34:21.797892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4160 01:34:21.804425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4161 01:34:21.807461 [CA 0] Center 35 (5~66) winsize 62
4162 01:34:21.810977 [CA 1] Center 35 (4~66) winsize 63
4163 01:34:21.813954 [CA 2] Center 33 (3~64) winsize 62
4164 01:34:21.817342 [CA 3] Center 33 (3~64) winsize 62
4165 01:34:21.820906 [CA 4] Center 33 (2~64) winsize 63
4166 01:34:21.824088 [CA 5] Center 33 (2~64) winsize 63
4167 01:34:21.824637
4168 01:34:21.827409 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4169 01:34:21.827863
4170 01:34:21.830974 [CATrainingPosCal] consider 1 rank data
4171 01:34:21.833924 u2DelayCellTimex100 = 270/100 ps
4172 01:34:21.837485 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4173 01:34:21.840480 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4174 01:34:21.843809 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4175 01:34:21.847430 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4176 01:34:21.850755 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4177 01:34:21.854215 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4178 01:34:21.857089
4179 01:34:21.860475 CA PerBit enable=1, Macro0, CA PI delay=33
4180 01:34:21.861019
4181 01:34:21.863906 [CBTSetCACLKResult] CA Dly = 33
4182 01:34:21.864450 CS Dly: 3 (0~34)
4183 01:34:21.864818 ==
4184 01:34:21.866871 Dram Type= 6, Freq= 0, CH_1, rank 1
4185 01:34:21.870468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4186 01:34:21.873727 ==
4187 01:34:21.877241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4188 01:34:21.883935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4189 01:34:21.886957 [CA 0] Center 35 (5~66) winsize 62
4190 01:34:21.889949 [CA 1] Center 34 (4~65) winsize 62
4191 01:34:21.893401 [CA 2] Center 33 (3~64) winsize 62
4192 01:34:21.897139 [CA 3] Center 33 (3~64) winsize 62
4193 01:34:21.900483 [CA 4] Center 32 (2~63) winsize 62
4194 01:34:21.903577 [CA 5] Center 32 (2~63) winsize 62
4195 01:34:21.904128
4196 01:34:21.906541 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4197 01:34:21.907000
4198 01:34:21.909988 [CATrainingPosCal] consider 2 rank data
4199 01:34:21.913579 u2DelayCellTimex100 = 270/100 ps
4200 01:34:21.916812 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4201 01:34:21.920108 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4202 01:34:21.923470 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4203 01:34:21.929916 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4204 01:34:21.933426 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4205 01:34:21.936597 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4206 01:34:21.937163
4207 01:34:21.939712 CA PerBit enable=1, Macro0, CA PI delay=32
4208 01:34:21.940273
4209 01:34:21.942857 [CBTSetCACLKResult] CA Dly = 32
4210 01:34:21.943318 CS Dly: 4 (0~36)
4211 01:34:21.943681
4212 01:34:21.946102 ----->DramcWriteLeveling(PI) begin...
4213 01:34:21.949635 ==
4214 01:34:21.950207 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 01:34:21.956452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 01:34:21.957011 ==
4217 01:34:21.959513 Write leveling (Byte 0): 28 => 28
4218 01:34:21.962707 Write leveling (Byte 1): 28 => 28
4219 01:34:21.966219 DramcWriteLeveling(PI) end<-----
4220 01:34:21.966842
4221 01:34:21.967210 ==
4222 01:34:21.969572 Dram Type= 6, Freq= 0, CH_1, rank 0
4223 01:34:21.972782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4224 01:34:21.973356 ==
4225 01:34:21.976194 [Gating] SW mode calibration
4226 01:34:21.982634 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 01:34:21.989156 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4228 01:34:21.992407 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 01:34:21.996071 0 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4230 01:34:22.002624 0 5 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (0 0)
4231 01:34:22.005866 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 01:34:22.008859 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 01:34:22.015578 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 01:34:22.018680 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 01:34:22.021836 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 01:34:22.028787 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 01:34:22.032101 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4238 01:34:22.035165 0 6 8 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
4239 01:34:22.041896 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 01:34:22.045363 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 01:34:22.048851 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 01:34:22.054928 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 01:34:22.058416 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 01:34:22.061508 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 01:34:22.068277 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4246 01:34:22.071790 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 01:34:22.075197 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 01:34:22.078435 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 01:34:22.085101 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 01:34:22.088495 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 01:34:22.091561 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 01:34:22.098310 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 01:34:22.101650 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 01:34:22.105176 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 01:34:22.111839 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 01:34:22.115211 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 01:34:22.118118 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 01:34:22.124718 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 01:34:22.128508 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 01:34:22.131726 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 01:34:22.137918 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 01:34:22.141350 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4263 01:34:22.144735 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 01:34:22.148099 Total UI for P1: 0, mck2ui 16
4265 01:34:22.151296 best dqsien dly found for B0: ( 0, 9, 8)
4266 01:34:22.154425 Total UI for P1: 0, mck2ui 16
4267 01:34:22.157775 best dqsien dly found for B1: ( 0, 9, 8)
4268 01:34:22.161318 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4269 01:34:22.164496 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4270 01:34:22.165044
4271 01:34:22.171134 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4272 01:34:22.174204 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4273 01:34:22.174660 [Gating] SW calibration Done
4274 01:34:22.177582 ==
4275 01:34:22.180884 Dram Type= 6, Freq= 0, CH_1, rank 0
4276 01:34:22.184375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4277 01:34:22.184928 ==
4278 01:34:22.185340 RX Vref Scan: 0
4279 01:34:22.185750
4280 01:34:22.187899 RX Vref 0 -> 0, step: 1
4281 01:34:22.188346
4282 01:34:22.190972 RX Delay -230 -> 252, step: 16
4283 01:34:22.194310 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4284 01:34:22.197753 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4285 01:34:22.204521 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4286 01:34:22.207513 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4287 01:34:22.211155 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4288 01:34:22.214129 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4289 01:34:22.220908 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4290 01:34:22.224174 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4291 01:34:22.227628 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4292 01:34:22.230716 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4293 01:34:22.233691 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4294 01:34:22.240512 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4295 01:34:22.243840 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4296 01:34:22.247152 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4297 01:34:22.250355 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4298 01:34:22.257160 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4299 01:34:22.257750 ==
4300 01:34:22.260398 Dram Type= 6, Freq= 0, CH_1, rank 0
4301 01:34:22.263889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4302 01:34:22.264439 ==
4303 01:34:22.264840 DQS Delay:
4304 01:34:22.266976 DQS0 = 0, DQS1 = 0
4305 01:34:22.267520 DQM Delay:
4306 01:34:22.270093 DQM0 = 42, DQM1 = 34
4307 01:34:22.270544 DQ Delay:
4308 01:34:22.273689 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4309 01:34:22.276786 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4310 01:34:22.280069 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4311 01:34:22.283395 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4312 01:34:22.283846
4313 01:34:22.284201
4314 01:34:22.284533 ==
4315 01:34:22.286735 Dram Type= 6, Freq= 0, CH_1, rank 0
4316 01:34:22.289928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4317 01:34:22.293388 ==
4318 01:34:22.294074
4319 01:34:22.294587
4320 01:34:22.295078 TX Vref Scan disable
4321 01:34:22.296520 == TX Byte 0 ==
4322 01:34:22.300077 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4323 01:34:22.306758 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4324 01:34:22.307305 == TX Byte 1 ==
4325 01:34:22.310087 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4326 01:34:22.316893 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4327 01:34:22.317484 ==
4328 01:34:22.319831 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 01:34:22.323385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4330 01:34:22.323939 ==
4331 01:34:22.324297
4332 01:34:22.324623
4333 01:34:22.326816 TX Vref Scan disable
4334 01:34:22.329849 == TX Byte 0 ==
4335 01:34:22.333413 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4336 01:34:22.336522 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4337 01:34:22.339904 == TX Byte 1 ==
4338 01:34:22.343243 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4339 01:34:22.346243 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4340 01:34:22.346692
4341 01:34:22.347047 [DATLAT]
4342 01:34:22.349933 Freq=600, CH1 RK0
4343 01:34:22.350493
4344 01:34:22.350850 DATLAT Default: 0x9
4345 01:34:22.353478 0, 0xFFFF, sum = 0
4346 01:34:22.356466 1, 0xFFFF, sum = 0
4347 01:34:22.357025 2, 0xFFFF, sum = 0
4348 01:34:22.359479 3, 0xFFFF, sum = 0
4349 01:34:22.359936 4, 0xFFFF, sum = 0
4350 01:34:22.362865 5, 0xFFFF, sum = 0
4351 01:34:22.363418 6, 0xFFFF, sum = 0
4352 01:34:22.366430 7, 0x0, sum = 1
4353 01:34:22.366997 8, 0x0, sum = 2
4354 01:34:22.367381 9, 0x0, sum = 3
4355 01:34:22.369539 10, 0x0, sum = 4
4356 01:34:22.369999 best_step = 8
4357 01:34:22.370353
4358 01:34:22.373053 ==
4359 01:34:22.373653 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 01:34:22.379304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4361 01:34:22.379851 ==
4362 01:34:22.380210 RX Vref Scan: 1
4363 01:34:22.380538
4364 01:34:22.382914 RX Vref 0 -> 0, step: 1
4365 01:34:22.383365
4366 01:34:22.386180 RX Delay -195 -> 252, step: 8
4367 01:34:22.386721
4368 01:34:22.389403 Set Vref, RX VrefLevel [Byte0]: 57
4369 01:34:22.392384 [Byte1]: 50
4370 01:34:22.392834
4371 01:34:22.395987 Final RX Vref Byte 0 = 57 to rank0
4372 01:34:22.399172 Final RX Vref Byte 1 = 50 to rank0
4373 01:34:22.402441 Final RX Vref Byte 0 = 57 to rank1
4374 01:34:22.405971 Final RX Vref Byte 1 = 50 to rank1==
4375 01:34:22.409101 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 01:34:22.412520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4377 01:34:22.415798 ==
4378 01:34:22.416341 DQS Delay:
4379 01:34:22.416706 DQS0 = 0, DQS1 = 0
4380 01:34:22.418903 DQM Delay:
4381 01:34:22.419355 DQM0 = 37, DQM1 = 30
4382 01:34:22.422481 DQ Delay:
4383 01:34:22.425422 DQ0 =40, DQ1 =28, DQ2 =28, DQ3 =36
4384 01:34:22.425967 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4385 01:34:22.428944 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4386 01:34:22.432229 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4387 01:34:22.435587
4388 01:34:22.436130
4389 01:34:22.442609 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4390 01:34:22.445282 CH1 RK0: MR19=808, MR18=6E6E
4391 01:34:22.452203 CH1_RK0: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4392 01:34:22.452753
4393 01:34:22.455409 ----->DramcWriteLeveling(PI) begin...
4394 01:34:22.455960 ==
4395 01:34:22.458941 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 01:34:22.462367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4397 01:34:22.462920 ==
4398 01:34:22.465347 Write leveling (Byte 0): 29 => 29
4399 01:34:22.468547 Write leveling (Byte 1): 26 => 26
4400 01:34:22.472052 DramcWriteLeveling(PI) end<-----
4401 01:34:22.472592
4402 01:34:22.472947 ==
4403 01:34:22.475348 Dram Type= 6, Freq= 0, CH_1, rank 1
4404 01:34:22.478857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4405 01:34:22.479411 ==
4406 01:34:22.481959 [Gating] SW mode calibration
4407 01:34:22.488769 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 01:34:22.494996 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4409 01:34:22.498505 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 01:34:22.501581 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4411 01:34:22.508268 0 5 8 | B1->B0 | 3030 2828 | 0 0 | (1 1) (1 1)
4412 01:34:22.511551 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 01:34:22.514859 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 01:34:22.521595 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 01:34:22.524901 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 01:34:22.528411 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 01:34:22.534801 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 01:34:22.538116 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4419 01:34:22.541635 0 6 8 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4420 01:34:22.548694 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 01:34:22.551456 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 01:34:22.554857 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 01:34:22.561464 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 01:34:22.564912 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 01:34:22.567984 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 01:34:22.574441 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4427 01:34:22.578175 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 01:34:22.581623 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 01:34:22.587767 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 01:34:22.591103 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 01:34:22.594315 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 01:34:22.600921 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 01:34:22.604553 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 01:34:22.607690 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 01:34:22.614238 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 01:34:22.617699 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 01:34:22.620686 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 01:34:22.627324 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 01:34:22.630817 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 01:34:22.633982 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 01:34:22.640977 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 01:34:22.644013 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 01:34:22.647539 Total UI for P1: 0, mck2ui 16
4444 01:34:22.650408 best dqsien dly found for B0: ( 0, 9, 2)
4445 01:34:22.653957 Total UI for P1: 0, mck2ui 16
4446 01:34:22.657741 best dqsien dly found for B1: ( 0, 9, 2)
4447 01:34:22.660756 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4448 01:34:22.663919 best DQS1 dly(MCK, UI, PI) = (0, 9, 2)
4449 01:34:22.664376
4450 01:34:22.667512 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4451 01:34:22.670411 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 2)
4452 01:34:22.673817 [Gating] SW calibration Done
4453 01:34:22.674358 ==
4454 01:34:22.677100 Dram Type= 6, Freq= 0, CH_1, rank 1
4455 01:34:22.680293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4456 01:34:22.683623 ==
4457 01:34:22.684075 RX Vref Scan: 0
4458 01:34:22.684431
4459 01:34:22.686901 RX Vref 0 -> 0, step: 1
4460 01:34:22.687299
4461 01:34:22.690056 RX Delay -230 -> 252, step: 16
4462 01:34:22.693622 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4463 01:34:22.697093 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4464 01:34:22.700280 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4465 01:34:22.707174 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4466 01:34:22.710200 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4467 01:34:22.713653 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4468 01:34:22.716856 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4469 01:34:22.719970 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4470 01:34:22.726697 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4471 01:34:22.729892 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4472 01:34:22.733181 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4473 01:34:22.736835 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4474 01:34:22.743264 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4475 01:34:22.746614 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4476 01:34:22.749823 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4477 01:34:22.753137 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4478 01:34:22.753741 ==
4479 01:34:22.756624 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 01:34:22.763255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4481 01:34:22.763813 ==
4482 01:34:22.764174 DQS Delay:
4483 01:34:22.766679 DQS0 = 0, DQS1 = 0
4484 01:34:22.767234 DQM Delay:
4485 01:34:22.767600 DQM0 = 41, DQM1 = 34
4486 01:34:22.769601 DQ Delay:
4487 01:34:22.773157 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4488 01:34:22.776244 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4489 01:34:22.779470 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4490 01:34:22.783101 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4491 01:34:22.783552
4492 01:34:22.783906
4493 01:34:22.784234 ==
4494 01:34:22.786013 Dram Type= 6, Freq= 0, CH_1, rank 1
4495 01:34:22.789426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4496 01:34:22.790013 ==
4497 01:34:22.790691
4498 01:34:22.791268
4499 01:34:22.792770 TX Vref Scan disable
4500 01:34:22.796044 == TX Byte 0 ==
4501 01:34:22.799810 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4502 01:34:22.802728 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4503 01:34:22.805965 == TX Byte 1 ==
4504 01:34:22.809708 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4505 01:34:22.812877 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4506 01:34:22.813651 ==
4507 01:34:22.816103 Dram Type= 6, Freq= 0, CH_1, rank 1
4508 01:34:22.819415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4509 01:34:22.822539 ==
4510 01:34:22.822990
4511 01:34:22.823345
4512 01:34:22.823675 TX Vref Scan disable
4513 01:34:22.826518 == TX Byte 0 ==
4514 01:34:22.829708 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 01:34:22.836630 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 01:34:22.837208 == TX Byte 1 ==
4517 01:34:22.839960 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4518 01:34:22.846310 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4519 01:34:22.846928
4520 01:34:22.847617 [DATLAT]
4521 01:34:22.847991 Freq=600, CH1 RK1
4522 01:34:22.848379
4523 01:34:22.849663 DATLAT Default: 0x8
4524 01:34:22.850067 0, 0xFFFF, sum = 0
4525 01:34:22.852776 1, 0xFFFF, sum = 0
4526 01:34:22.856172 2, 0xFFFF, sum = 0
4527 01:34:22.857011 3, 0xFFFF, sum = 0
4528 01:34:22.859386 4, 0xFFFF, sum = 0
4529 01:34:22.859936 5, 0xFFFF, sum = 0
4530 01:34:22.862925 6, 0xFFFF, sum = 0
4531 01:34:22.863388 7, 0x0, sum = 1
4532 01:34:22.866181 8, 0x0, sum = 2
4533 01:34:22.866637 9, 0x0, sum = 3
4534 01:34:22.867002 10, 0x0, sum = 4
4535 01:34:22.869456 best_step = 8
4536 01:34:22.870223
4537 01:34:22.870712 ==
4538 01:34:22.872546 Dram Type= 6, Freq= 0, CH_1, rank 1
4539 01:34:22.875907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4540 01:34:22.876367 ==
4541 01:34:22.879396 RX Vref Scan: 0
4542 01:34:22.879951
4543 01:34:22.880319 RX Vref 0 -> 0, step: 1
4544 01:34:22.882469
4545 01:34:22.882944 RX Delay -195 -> 252, step: 8
4546 01:34:22.890035 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4547 01:34:22.893334 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4548 01:34:22.896989 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4549 01:34:22.900134 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4550 01:34:22.906572 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4551 01:34:22.909837 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4552 01:34:22.913133 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4553 01:34:22.916493 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4554 01:34:22.922944 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4555 01:34:22.926104 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4556 01:34:22.929543 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4557 01:34:22.932899 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4558 01:34:22.939569 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4559 01:34:22.943212 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4560 01:34:22.946056 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4561 01:34:22.949276 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4562 01:34:22.949773 ==
4563 01:34:22.952611 Dram Type= 6, Freq= 0, CH_1, rank 1
4564 01:34:22.959534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4565 01:34:22.960102 ==
4566 01:34:22.960475 DQS Delay:
4567 01:34:22.962706 DQS0 = 0, DQS1 = 0
4568 01:34:22.963164 DQM Delay:
4569 01:34:22.963531 DQM0 = 37, DQM1 = 28
4570 01:34:22.966008 DQ Delay:
4571 01:34:22.969218 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4572 01:34:22.972767 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4573 01:34:22.976418 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4574 01:34:22.979415 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4575 01:34:22.979995
4576 01:34:22.980489
4577 01:34:22.985683 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
4578 01:34:22.989098 CH1 RK1: MR19=808, MR18=4D4D
4579 01:34:22.995773 CH1_RK1: MR19=0x808, MR18=0x4D4D, DQSOSC=395, MR23=63, INC=168, DEC=112
4580 01:34:22.998956 [RxdqsGatingPostProcess] freq 600
4581 01:34:23.005900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4582 01:34:23.006484 Pre-setting of DQS Precalculation
4583 01:34:23.012403 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4584 01:34:23.018912 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4585 01:34:23.025400 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4586 01:34:23.025886
4587 01:34:23.026365
4588 01:34:23.028499 [Calibration Summary] 1200 Mbps
4589 01:34:23.032066 CH 0, Rank 0
4590 01:34:23.032637 SW Impedance : PASS
4591 01:34:23.035265 DUTY Scan : NO K
4592 01:34:23.035744 ZQ Calibration : PASS
4593 01:34:23.038619 Jitter Meter : NO K
4594 01:34:23.041897 CBT Training : PASS
4595 01:34:23.042376 Write leveling : PASS
4596 01:34:23.044995 RX DQS gating : PASS
4597 01:34:23.048483 RX DQ/DQS(RDDQC) : PASS
4598 01:34:23.049058 TX DQ/DQS : PASS
4599 01:34:23.052018 RX DATLAT : PASS
4600 01:34:23.055337 RX DQ/DQS(Engine): PASS
4601 01:34:23.055916 TX OE : NO K
4602 01:34:23.058546 All Pass.
4603 01:34:23.059018
4604 01:34:23.059507 CH 0, Rank 1
4605 01:34:23.061860 SW Impedance : PASS
4606 01:34:23.062443 DUTY Scan : NO K
4607 01:34:23.065137 ZQ Calibration : PASS
4608 01:34:23.068630 Jitter Meter : NO K
4609 01:34:23.069215 CBT Training : PASS
4610 01:34:23.071754 Write leveling : PASS
4611 01:34:23.075116 RX DQS gating : PASS
4612 01:34:23.075690 RX DQ/DQS(RDDQC) : PASS
4613 01:34:23.078539 TX DQ/DQS : PASS
4614 01:34:23.081663 RX DATLAT : PASS
4615 01:34:23.082210 RX DQ/DQS(Engine): PASS
4616 01:34:23.084753 TX OE : NO K
4617 01:34:23.085150 All Pass.
4618 01:34:23.085526
4619 01:34:23.088227 CH 1, Rank 0
4620 01:34:23.088770 SW Impedance : PASS
4621 01:34:23.091545 DUTY Scan : NO K
4622 01:34:23.095075 ZQ Calibration : PASS
4623 01:34:23.095629 Jitter Meter : NO K
4624 01:34:23.098114 CBT Training : PASS
4625 01:34:23.098795 Write leveling : PASS
4626 01:34:23.101519 RX DQS gating : PASS
4627 01:34:23.104725 RX DQ/DQS(RDDQC) : PASS
4628 01:34:23.105179 TX DQ/DQS : PASS
4629 01:34:23.108027 RX DATLAT : PASS
4630 01:34:23.111322 RX DQ/DQS(Engine): PASS
4631 01:34:23.111871 TX OE : NO K
4632 01:34:23.114583 All Pass.
4633 01:34:23.115039
4634 01:34:23.115396 CH 1, Rank 1
4635 01:34:23.118067 SW Impedance : PASS
4636 01:34:23.118728 DUTY Scan : NO K
4637 01:34:23.121359 ZQ Calibration : PASS
4638 01:34:23.124273 Jitter Meter : NO K
4639 01:34:23.124782 CBT Training : PASS
4640 01:34:23.127737 Write leveling : PASS
4641 01:34:23.131204 RX DQS gating : PASS
4642 01:34:23.131654 RX DQ/DQS(RDDQC) : PASS
4643 01:34:23.134533 TX DQ/DQS : PASS
4644 01:34:23.137669 RX DATLAT : PASS
4645 01:34:23.138117 RX DQ/DQS(Engine): PASS
4646 01:34:23.140979 TX OE : NO K
4647 01:34:23.141463 All Pass.
4648 01:34:23.141829
4649 01:34:23.144226 DramC Write-DBI off
4650 01:34:23.147602 PER_BANK_REFRESH: Hybrid Mode
4651 01:34:23.148052 TX_TRACKING: ON
4652 01:34:23.157768 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4653 01:34:23.161067 [FAST_K] Save calibration result to emmc
4654 01:34:23.164420 dramc_set_vcore_voltage set vcore to 662500
4655 01:34:23.167567 Read voltage for 933, 3
4656 01:34:23.168123 Vio18 = 0
4657 01:34:23.168486 Vcore = 662500
4658 01:34:23.171111 Vdram = 0
4659 01:34:23.171560 Vddq = 0
4660 01:34:23.171920 Vmddr = 0
4661 01:34:23.177948 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4662 01:34:23.181121 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4663 01:34:23.183825 MEM_TYPE=3, freq_sel=17
4664 01:34:23.187315 sv_algorithm_assistance_LP4_1600
4665 01:34:23.190420 ============ PULL DRAM RESETB DOWN ============
4666 01:34:23.193644 ========== PULL DRAM RESETB DOWN end =========
4667 01:34:23.200808 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4668 01:34:23.204311 ===================================
4669 01:34:23.207242 LPDDR4 DRAM CONFIGURATION
4670 01:34:23.210634 ===================================
4671 01:34:23.211183 EX_ROW_EN[0] = 0x0
4672 01:34:23.213732 EX_ROW_EN[1] = 0x0
4673 01:34:23.214280 LP4Y_EN = 0x0
4674 01:34:23.216843 WORK_FSP = 0x0
4675 01:34:23.217445 WL = 0x3
4676 01:34:23.220224 RL = 0x3
4677 01:34:23.220775 BL = 0x2
4678 01:34:23.223443 RPST = 0x0
4679 01:34:23.224075 RD_PRE = 0x0
4680 01:34:23.226686 WR_PRE = 0x1
4681 01:34:23.227167 WR_PST = 0x0
4682 01:34:23.230135 DBI_WR = 0x0
4683 01:34:23.233251 DBI_RD = 0x0
4684 01:34:23.233766 OTF = 0x1
4685 01:34:23.236455 ===================================
4686 01:34:23.240081 ===================================
4687 01:34:23.240633 ANA top config
4688 01:34:23.243462 ===================================
4689 01:34:23.246543 DLL_ASYNC_EN = 0
4690 01:34:23.249863 ALL_SLAVE_EN = 1
4691 01:34:23.253477 NEW_RANK_MODE = 1
4692 01:34:23.256737 DLL_IDLE_MODE = 1
4693 01:34:23.257337 LP45_APHY_COMB_EN = 1
4694 01:34:23.259851 TX_ODT_DIS = 1
4695 01:34:23.263032 NEW_8X_MODE = 1
4696 01:34:23.266305 ===================================
4697 01:34:23.269549 ===================================
4698 01:34:23.272769 data_rate = 1866
4699 01:34:23.276400 CKR = 1
4700 01:34:23.279800 DQ_P2S_RATIO = 8
4701 01:34:23.280364 ===================================
4702 01:34:23.282858 CA_P2S_RATIO = 8
4703 01:34:23.286213 DQ_CA_OPEN = 0
4704 01:34:23.289907 DQ_SEMI_OPEN = 0
4705 01:34:23.292693 CA_SEMI_OPEN = 0
4706 01:34:23.296197 CA_FULL_RATE = 0
4707 01:34:23.296758 DQ_CKDIV4_EN = 1
4708 01:34:23.299260 CA_CKDIV4_EN = 1
4709 01:34:23.302765 CA_PREDIV_EN = 0
4710 01:34:23.306103 PH8_DLY = 0
4711 01:34:23.309093 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4712 01:34:23.312763 DQ_AAMCK_DIV = 4
4713 01:34:23.313371 CA_AAMCK_DIV = 4
4714 01:34:23.315921 CA_ADMCK_DIV = 4
4715 01:34:23.319367 DQ_TRACK_CA_EN = 0
4716 01:34:23.322747 CA_PICK = 933
4717 01:34:23.325709 CA_MCKIO = 933
4718 01:34:23.329359 MCKIO_SEMI = 0
4719 01:34:23.332286 PLL_FREQ = 3732
4720 01:34:23.336076 DQ_UI_PI_RATIO = 32
4721 01:34:23.336632 CA_UI_PI_RATIO = 0
4722 01:34:23.339586 ===================================
4723 01:34:23.342572 ===================================
4724 01:34:23.346118 memory_type:LPDDR4
4725 01:34:23.348853 GP_NUM : 10
4726 01:34:23.349355 SRAM_EN : 1
4727 01:34:23.352362 MD32_EN : 0
4728 01:34:23.355688 ===================================
4729 01:34:23.358936 [ANA_INIT] >>>>>>>>>>>>>>
4730 01:34:23.362753 <<<<<< [CONFIGURE PHASE]: ANA_TX
4731 01:34:23.365650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4732 01:34:23.368883 ===================================
4733 01:34:23.369480 data_rate = 1866,PCW = 0X8f00
4734 01:34:23.372484 ===================================
4735 01:34:23.375799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4736 01:34:23.382077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4737 01:34:23.388824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4738 01:34:23.392063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4739 01:34:23.395223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4740 01:34:23.398315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4741 01:34:23.401983 [ANA_INIT] flow start
4742 01:34:23.405250 [ANA_INIT] PLL >>>>>>>>
4743 01:34:23.405845 [ANA_INIT] PLL <<<<<<<<
4744 01:34:23.408486 [ANA_INIT] MIDPI >>>>>>>>
4745 01:34:23.411643 [ANA_INIT] MIDPI <<<<<<<<
4746 01:34:23.412098 [ANA_INIT] DLL >>>>>>>>
4747 01:34:23.414972 [ANA_INIT] flow end
4748 01:34:23.418358 ============ LP4 DIFF to SE enter ============
4749 01:34:23.421867 ============ LP4 DIFF to SE exit ============
4750 01:34:23.424974 [ANA_INIT] <<<<<<<<<<<<<
4751 01:34:23.428152 [Flow] Enable top DCM control >>>>>
4752 01:34:23.431673 [Flow] Enable top DCM control <<<<<
4753 01:34:23.434671 Enable DLL master slave shuffle
4754 01:34:23.441637 ==============================================================
4755 01:34:23.442091 Gating Mode config
4756 01:34:23.448019 ==============================================================
4757 01:34:23.451272 Config description:
4758 01:34:23.457912 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4759 01:34:23.464466 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4760 01:34:23.471039 SELPH_MODE 0: By rank 1: By Phase
4761 01:34:23.477602 ==============================================================
4762 01:34:23.478153 GAT_TRACK_EN = 1
4763 01:34:23.481161 RX_GATING_MODE = 2
4764 01:34:23.484087 RX_GATING_TRACK_MODE = 2
4765 01:34:23.487741 SELPH_MODE = 1
4766 01:34:23.490843 PICG_EARLY_EN = 1
4767 01:34:23.494085 VALID_LAT_VALUE = 1
4768 01:34:23.500729 ==============================================================
4769 01:34:23.504025 Enter into Gating configuration >>>>
4770 01:34:23.507791 Exit from Gating configuration <<<<
4771 01:34:23.510479 Enter into DVFS_PRE_config >>>>>
4772 01:34:23.520518 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4773 01:34:23.524185 Exit from DVFS_PRE_config <<<<<
4774 01:34:23.527329 Enter into PICG configuration >>>>
4775 01:34:23.530424 Exit from PICG configuration <<<<
4776 01:34:23.533828 [RX_INPUT] configuration >>>>>
4777 01:34:23.537122 [RX_INPUT] configuration <<<<<
4778 01:34:23.540738 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4779 01:34:23.546951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4780 01:34:23.553813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4781 01:34:23.560046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4782 01:34:23.563436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4783 01:34:23.569769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4784 01:34:23.573279 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4785 01:34:23.580011 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4786 01:34:23.583519 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4787 01:34:23.586648 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4788 01:34:23.590191 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4789 01:34:23.596687 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4790 01:34:23.600131 ===================================
4791 01:34:23.600760 LPDDR4 DRAM CONFIGURATION
4792 01:34:23.603203 ===================================
4793 01:34:23.606717 EX_ROW_EN[0] = 0x0
4794 01:34:23.609926 EX_ROW_EN[1] = 0x0
4795 01:34:23.610574 LP4Y_EN = 0x0
4796 01:34:23.612930 WORK_FSP = 0x0
4797 01:34:23.613544 WL = 0x3
4798 01:34:23.616268 RL = 0x3
4799 01:34:23.616743 BL = 0x2
4800 01:34:23.619394 RPST = 0x0
4801 01:34:23.619868 RD_PRE = 0x0
4802 01:34:23.622701 WR_PRE = 0x1
4803 01:34:23.623175 WR_PST = 0x0
4804 01:34:23.626182 DBI_WR = 0x0
4805 01:34:23.626712 DBI_RD = 0x0
4806 01:34:23.629433 OTF = 0x1
4807 01:34:23.632691 ===================================
4808 01:34:23.635994 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4809 01:34:23.639224 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4810 01:34:23.645996 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4811 01:34:23.649162 ===================================
4812 01:34:23.652609 LPDDR4 DRAM CONFIGURATION
4813 01:34:23.655950 ===================================
4814 01:34:23.656528 EX_ROW_EN[0] = 0x10
4815 01:34:23.658927 EX_ROW_EN[1] = 0x0
4816 01:34:23.659403 LP4Y_EN = 0x0
4817 01:34:23.662183 WORK_FSP = 0x0
4818 01:34:23.662657 WL = 0x3
4819 01:34:23.666022 RL = 0x3
4820 01:34:23.666596 BL = 0x2
4821 01:34:23.668955 RPST = 0x0
4822 01:34:23.669462 RD_PRE = 0x0
4823 01:34:23.672228 WR_PRE = 0x1
4824 01:34:23.672702 WR_PST = 0x0
4825 01:34:23.675320 DBI_WR = 0x0
4826 01:34:23.675795 DBI_RD = 0x0
4827 01:34:23.678955 OTF = 0x1
4828 01:34:23.682225 ===================================
4829 01:34:23.688974 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4830 01:34:23.692206 nWR fixed to 30
4831 01:34:23.695544 [ModeRegInit_LP4] CH0 RK0
4832 01:34:23.696120 [ModeRegInit_LP4] CH0 RK1
4833 01:34:23.699335 [ModeRegInit_LP4] CH1 RK0
4834 01:34:23.702355 [ModeRegInit_LP4] CH1 RK1
4835 01:34:23.702930 match AC timing 8
4836 01:34:23.708706 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4837 01:34:23.712519 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4838 01:34:23.715587 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4839 01:34:23.721757 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4840 01:34:23.725274 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4841 01:34:23.725912 ==
4842 01:34:23.728448 Dram Type= 6, Freq= 0, CH_0, rank 0
4843 01:34:23.731824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4844 01:34:23.732287 ==
4845 01:34:23.738212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4846 01:34:23.744949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4847 01:34:23.748502 [CA 0] Center 38 (8~69) winsize 62
4848 01:34:23.751295 [CA 1] Center 38 (8~69) winsize 62
4849 01:34:23.754937 [CA 2] Center 36 (6~67) winsize 62
4850 01:34:23.758446 [CA 3] Center 36 (6~66) winsize 61
4851 01:34:23.761645 [CA 4] Center 35 (5~65) winsize 61
4852 01:34:23.764780 [CA 5] Center 34 (4~65) winsize 62
4853 01:34:23.765367
4854 01:34:23.768120 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4855 01:34:23.768688
4856 01:34:23.771407 [CATrainingPosCal] consider 1 rank data
4857 01:34:23.775503 u2DelayCellTimex100 = 270/100 ps
4858 01:34:23.778132 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4859 01:34:23.781478 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4860 01:34:23.784984 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4861 01:34:23.788217 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4862 01:34:23.794621 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4863 01:34:23.798268 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4864 01:34:23.798828
4865 01:34:23.801426 CA PerBit enable=1, Macro0, CA PI delay=34
4866 01:34:23.801982
4867 01:34:23.804479 [CBTSetCACLKResult] CA Dly = 34
4868 01:34:23.805031 CS Dly: 7 (0~38)
4869 01:34:23.805451 ==
4870 01:34:23.807962 Dram Type= 6, Freq= 0, CH_0, rank 1
4871 01:34:23.814514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4872 01:34:23.815078 ==
4873 01:34:23.817501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4874 01:34:23.824673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4875 01:34:23.827631 [CA 0] Center 38 (8~69) winsize 62
4876 01:34:23.830951 [CA 1] Center 38 (8~69) winsize 62
4877 01:34:23.834190 [CA 2] Center 36 (5~67) winsize 63
4878 01:34:23.837229 [CA 3] Center 35 (5~66) winsize 62
4879 01:34:23.840810 [CA 4] Center 34 (4~65) winsize 62
4880 01:34:23.844381 [CA 5] Center 34 (4~65) winsize 62
4881 01:34:23.844958
4882 01:34:23.847448 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4883 01:34:23.848027
4884 01:34:23.850522 [CATrainingPosCal] consider 2 rank data
4885 01:34:23.854224 u2DelayCellTimex100 = 270/100 ps
4886 01:34:23.857394 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4887 01:34:23.860357 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4888 01:34:23.867400 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4889 01:34:23.870690 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4890 01:34:23.874215 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4891 01:34:23.877137 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4892 01:34:23.877766
4893 01:34:23.880152 CA PerBit enable=1, Macro0, CA PI delay=34
4894 01:34:23.880629
4895 01:34:23.883503 [CBTSetCACLKResult] CA Dly = 34
4896 01:34:23.886872 CS Dly: 7 (0~39)
4897 01:34:23.887447
4898 01:34:23.890591 ----->DramcWriteLeveling(PI) begin...
4899 01:34:23.891171 ==
4900 01:34:23.893799 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 01:34:23.896948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 01:34:23.897476 ==
4903 01:34:23.900193 Write leveling (Byte 0): 26 => 26
4904 01:34:23.903684 Write leveling (Byte 1): 27 => 27
4905 01:34:23.906950 DramcWriteLeveling(PI) end<-----
4906 01:34:23.907521
4907 01:34:23.908012 ==
4908 01:34:23.909988 Dram Type= 6, Freq= 0, CH_0, rank 0
4909 01:34:23.913597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4910 01:34:23.914167 ==
4911 01:34:23.916780 [Gating] SW mode calibration
4912 01:34:23.923422 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4913 01:34:23.929878 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4914 01:34:23.933667 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4915 01:34:23.936830 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4916 01:34:23.943178 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4917 01:34:23.946648 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 01:34:23.949668 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 01:34:23.956626 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4920 01:34:23.959539 0 10 24 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4921 01:34:23.962816 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 01:34:23.970037 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4923 01:34:23.972815 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4924 01:34:23.976326 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 01:34:23.983148 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 01:34:23.986392 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 01:34:23.989671 0 11 20 | B1->B0 | 2828 2f2f | 0 0 | (1 1) (1 1)
4928 01:34:23.996322 0 11 24 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
4929 01:34:23.999698 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 01:34:24.002851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4931 01:34:24.009593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4932 01:34:24.012561 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 01:34:24.015794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 01:34:24.022559 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 01:34:24.025627 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4936 01:34:24.028840 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4937 01:34:24.035483 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 01:34:24.038570 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 01:34:24.041849 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 01:34:24.048748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 01:34:24.051916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 01:34:24.055300 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 01:34:24.061940 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 01:34:24.065419 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 01:34:24.068583 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 01:34:24.075554 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 01:34:24.078307 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 01:34:24.081746 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 01:34:24.088527 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 01:34:24.091739 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 01:34:24.094749 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4952 01:34:24.101719 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4953 01:34:24.102178 Total UI for P1: 0, mck2ui 16
4954 01:34:24.108191 best dqsien dly found for B0: ( 0, 14, 20)
4955 01:34:24.108857 Total UI for P1: 0, mck2ui 16
4956 01:34:24.114498 best dqsien dly found for B1: ( 0, 14, 20)
4957 01:34:24.117914 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4958 01:34:24.121325 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4959 01:34:24.121800
4960 01:34:24.124739 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4961 01:34:24.127824 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4962 01:34:24.131319 [Gating] SW calibration Done
4963 01:34:24.131897 ==
4964 01:34:24.134578 Dram Type= 6, Freq= 0, CH_0, rank 0
4965 01:34:24.137848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4966 01:34:24.138333 ==
4967 01:34:24.141232 RX Vref Scan: 0
4968 01:34:24.141739
4969 01:34:24.142221 RX Vref 0 -> 0, step: 1
4970 01:34:24.144770
4971 01:34:24.145379 RX Delay -80 -> 252, step: 8
4972 01:34:24.150950 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4973 01:34:24.154455 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4974 01:34:24.157443 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4975 01:34:24.161159 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4976 01:34:24.164129 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4977 01:34:24.167400 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4978 01:34:24.174333 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4979 01:34:24.177392 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
4980 01:34:24.180586 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4981 01:34:24.183674 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4982 01:34:24.187388 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4983 01:34:24.190823 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
4984 01:34:24.197401 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4985 01:34:24.200227 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4986 01:34:24.203563 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4987 01:34:24.206853 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4988 01:34:24.207330 ==
4989 01:34:24.210591 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 01:34:24.213505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 01:34:24.217026 ==
4992 01:34:24.217547 DQS Delay:
4993 01:34:24.218033 DQS0 = 0, DQS1 = 0
4994 01:34:24.220318 DQM Delay:
4995 01:34:24.220914 DQM0 = 95, DQM1 = 87
4996 01:34:24.223883 DQ Delay:
4997 01:34:24.227040 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
4998 01:34:24.227614 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =99
4999 01:34:24.230087 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83
5000 01:34:24.233774 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5001 01:34:24.236926
5002 01:34:24.237451
5003 01:34:24.237941 ==
5004 01:34:24.240147 Dram Type= 6, Freq= 0, CH_0, rank 0
5005 01:34:24.243412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5006 01:34:24.243894 ==
5007 01:34:24.244378
5008 01:34:24.244828
5009 01:34:24.246535 TX Vref Scan disable
5010 01:34:24.247007 == TX Byte 0 ==
5011 01:34:24.253174 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5012 01:34:24.256515 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5013 01:34:24.256993 == TX Byte 1 ==
5014 01:34:24.263412 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5015 01:34:24.266355 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5016 01:34:24.266859 ==
5017 01:34:24.269903 Dram Type= 6, Freq= 0, CH_0, rank 0
5018 01:34:24.273376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5019 01:34:24.273858 ==
5020 01:34:24.274336
5021 01:34:24.274785
5022 01:34:24.276342 TX Vref Scan disable
5023 01:34:24.279730 == TX Byte 0 ==
5024 01:34:24.283320 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5025 01:34:24.286286 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5026 01:34:24.289686 == TX Byte 1 ==
5027 01:34:24.292857 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5028 01:34:24.296475 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5029 01:34:24.296941
5030 01:34:24.299709 [DATLAT]
5031 01:34:24.300184 Freq=933, CH0 RK0
5032 01:34:24.300664
5033 01:34:24.303132 DATLAT Default: 0xd
5034 01:34:24.303608 0, 0xFFFF, sum = 0
5035 01:34:24.306115 1, 0xFFFF, sum = 0
5036 01:34:24.306601 2, 0xFFFF, sum = 0
5037 01:34:24.309387 3, 0xFFFF, sum = 0
5038 01:34:24.309827 4, 0xFFFF, sum = 0
5039 01:34:24.312718 5, 0xFFFF, sum = 0
5040 01:34:24.313199 6, 0xFFFF, sum = 0
5041 01:34:24.315886 7, 0xFFFF, sum = 0
5042 01:34:24.319515 8, 0xFFFF, sum = 0
5043 01:34:24.319995 9, 0xFFFF, sum = 0
5044 01:34:24.322810 10, 0x0, sum = 1
5045 01:34:24.323389 11, 0x0, sum = 2
5046 01:34:24.323887 12, 0x0, sum = 3
5047 01:34:24.326541 13, 0x0, sum = 4
5048 01:34:24.327121 best_step = 11
5049 01:34:24.327612
5050 01:34:24.328071 ==
5051 01:34:24.329458 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 01:34:24.335920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5053 01:34:24.336479 ==
5054 01:34:24.336848 RX Vref Scan: 1
5055 01:34:24.337190
5056 01:34:24.339313 RX Vref 0 -> 0, step: 1
5057 01:34:24.339773
5058 01:34:24.342205 RX Delay -69 -> 252, step: 4
5059 01:34:24.342752
5060 01:34:24.345591 Set Vref, RX VrefLevel [Byte0]: 47
5061 01:34:24.348897 [Byte1]: 49
5062 01:34:24.349421
5063 01:34:24.352243 Final RX Vref Byte 0 = 47 to rank0
5064 01:34:24.355774 Final RX Vref Byte 1 = 49 to rank0
5065 01:34:24.359033 Final RX Vref Byte 0 = 47 to rank1
5066 01:34:24.362645 Final RX Vref Byte 1 = 49 to rank1==
5067 01:34:24.365602 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 01:34:24.369266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5069 01:34:24.372105 ==
5070 01:34:24.372580 DQS Delay:
5071 01:34:24.372939 DQS0 = 0, DQS1 = 0
5072 01:34:24.375300 DQM Delay:
5073 01:34:24.375676 DQM0 = 97, DQM1 = 87
5074 01:34:24.378882 DQ Delay:
5075 01:34:24.382195 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5076 01:34:24.385405 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =104
5077 01:34:24.388668 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5078 01:34:24.392189 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5079 01:34:24.392671
5080 01:34:24.393098
5081 01:34:24.398714 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5082 01:34:24.401778 CH0 RK0: MR19=505, MR18=1919
5083 01:34:24.408698 CH0_RK0: MR19=0x505, MR18=0x1919, DQSOSC=413, MR23=63, INC=63, DEC=42
5084 01:34:24.409255
5085 01:34:24.411751 ----->DramcWriteLeveling(PI) begin...
5086 01:34:24.412215 ==
5087 01:34:24.415360 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 01:34:24.418442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5089 01:34:24.418905 ==
5090 01:34:24.421664 Write leveling (Byte 0): 27 => 27
5091 01:34:24.425130 Write leveling (Byte 1): 26 => 26
5092 01:34:24.428830 DramcWriteLeveling(PI) end<-----
5093 01:34:24.429684
5094 01:34:24.430259 ==
5095 01:34:24.431642 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 01:34:24.435060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5097 01:34:24.435624 ==
5098 01:34:24.438497 [Gating] SW mode calibration
5099 01:34:24.444882 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 01:34:24.451535 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5101 01:34:24.454952 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 01:34:24.461407 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 01:34:24.464544 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 01:34:24.467901 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 01:34:24.474423 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 01:34:24.477857 0 10 20 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
5107 01:34:24.481367 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5108 01:34:24.487659 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 01:34:24.491020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 01:34:24.494571 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 01:34:24.500988 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 01:34:24.504301 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 01:34:24.507296 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 01:34:24.514062 0 11 20 | B1->B0 | 3030 3535 | 0 1 | (0 0) (0 0)
5115 01:34:24.517539 0 11 24 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
5116 01:34:24.520979 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 01:34:24.527295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 01:34:24.530456 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 01:34:24.533771 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 01:34:24.540598 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 01:34:24.543900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 01:34:24.547165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5123 01:34:24.553604 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5124 01:34:24.556680 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 01:34:24.560413 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 01:34:24.566787 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 01:34:24.569933 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 01:34:24.573531 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 01:34:24.580181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 01:34:24.583093 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 01:34:24.586637 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 01:34:24.593428 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 01:34:24.596438 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 01:34:24.600061 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 01:34:24.606211 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 01:34:24.610208 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 01:34:24.613237 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 01:34:24.619455 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 01:34:24.622934 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5140 01:34:24.626589 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 01:34:24.629606 Total UI for P1: 0, mck2ui 16
5142 01:34:24.633058 best dqsien dly found for B0: ( 0, 14, 24)
5143 01:34:24.636384 Total UI for P1: 0, mck2ui 16
5144 01:34:24.639401 best dqsien dly found for B1: ( 0, 14, 24)
5145 01:34:24.643040 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
5146 01:34:24.646258 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5147 01:34:24.646845
5148 01:34:24.652977 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
5149 01:34:24.656097 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5150 01:34:24.656712 [Gating] SW calibration Done
5151 01:34:24.659512 ==
5152 01:34:24.662536 Dram Type= 6, Freq= 0, CH_0, rank 1
5153 01:34:24.665944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5154 01:34:24.666403 ==
5155 01:34:24.666806 RX Vref Scan: 0
5156 01:34:24.667149
5157 01:34:24.669045 RX Vref 0 -> 0, step: 1
5158 01:34:24.669534
5159 01:34:24.673095 RX Delay -80 -> 252, step: 8
5160 01:34:24.676008 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5161 01:34:24.679348 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5162 01:34:24.682571 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5163 01:34:24.689348 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5164 01:34:24.692353 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5165 01:34:24.695524 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5166 01:34:24.698978 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5167 01:34:24.702229 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5168 01:34:24.705620 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5169 01:34:24.712424 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5170 01:34:24.715456 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5171 01:34:24.718473 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5172 01:34:24.722357 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5173 01:34:24.725674 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5174 01:34:24.731629 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5175 01:34:24.735208 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5176 01:34:24.735766 ==
5177 01:34:24.738492 Dram Type= 6, Freq= 0, CH_0, rank 1
5178 01:34:24.741916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5179 01:34:24.742478 ==
5180 01:34:24.745162 DQS Delay:
5181 01:34:24.745772 DQS0 = 0, DQS1 = 0
5182 01:34:24.746142 DQM Delay:
5183 01:34:24.748659 DQM0 = 96, DQM1 = 86
5184 01:34:24.749216 DQ Delay:
5185 01:34:24.751672 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5186 01:34:24.755268 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5187 01:34:24.758537 DQ8 =75, DQ9 =71, DQ10 =91, DQ11 =79
5188 01:34:24.761655 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5189 01:34:24.762108
5190 01:34:24.762468
5191 01:34:24.762799 ==
5192 01:34:24.765003 Dram Type= 6, Freq= 0, CH_0, rank 1
5193 01:34:24.771645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5194 01:34:24.772196 ==
5195 01:34:24.772559
5196 01:34:24.772914
5197 01:34:24.773367 TX Vref Scan disable
5198 01:34:24.775327 == TX Byte 0 ==
5199 01:34:24.778363 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5200 01:34:24.785457 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5201 01:34:24.786005 == TX Byte 1 ==
5202 01:34:24.788852 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5203 01:34:24.794840 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5204 01:34:24.795293 ==
5205 01:34:24.798117 Dram Type= 6, Freq= 0, CH_0, rank 1
5206 01:34:24.801542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5207 01:34:24.802092 ==
5208 01:34:24.802456
5209 01:34:24.802788
5210 01:34:24.805111 TX Vref Scan disable
5211 01:34:24.805692 == TX Byte 0 ==
5212 01:34:24.811534 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5213 01:34:24.814795 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5214 01:34:24.815350 == TX Byte 1 ==
5215 01:34:24.821549 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5216 01:34:24.824938 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5217 01:34:24.825520
5218 01:34:24.825884 [DATLAT]
5219 01:34:24.828642 Freq=933, CH0 RK1
5220 01:34:24.829194
5221 01:34:24.829618 DATLAT Default: 0xb
5222 01:34:24.831226 0, 0xFFFF, sum = 0
5223 01:34:24.831740 1, 0xFFFF, sum = 0
5224 01:34:24.834442 2, 0xFFFF, sum = 0
5225 01:34:24.837944 3, 0xFFFF, sum = 0
5226 01:34:24.838479 4, 0xFFFF, sum = 0
5227 01:34:24.841353 5, 0xFFFF, sum = 0
5228 01:34:24.841909 6, 0xFFFF, sum = 0
5229 01:34:24.844746 7, 0xFFFF, sum = 0
5230 01:34:24.845352 8, 0xFFFF, sum = 0
5231 01:34:24.847944 9, 0xFFFF, sum = 0
5232 01:34:24.848495 10, 0x0, sum = 1
5233 01:34:24.850984 11, 0x0, sum = 2
5234 01:34:24.851443 12, 0x0, sum = 3
5235 01:34:24.854752 13, 0x0, sum = 4
5236 01:34:24.855308 best_step = 11
5237 01:34:24.855672
5238 01:34:24.856011 ==
5239 01:34:24.857660 Dram Type= 6, Freq= 0, CH_0, rank 1
5240 01:34:24.861082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5241 01:34:24.861687 ==
5242 01:34:24.864505 RX Vref Scan: 0
5243 01:34:24.865053
5244 01:34:24.868198 RX Vref 0 -> 0, step: 1
5245 01:34:24.868747
5246 01:34:24.869110 RX Delay -69 -> 252, step: 4
5247 01:34:24.875708 iDelay=199, Bit 0, Center 94 (7 ~ 182) 176
5248 01:34:24.878757 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5249 01:34:24.882623 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5250 01:34:24.885585 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5251 01:34:24.888711 iDelay=199, Bit 4, Center 102 (15 ~ 190) 176
5252 01:34:24.892216 iDelay=199, Bit 5, Center 92 (-1 ~ 186) 188
5253 01:34:24.898560 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5254 01:34:24.902191 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5255 01:34:24.905547 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5256 01:34:24.908504 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5257 01:34:24.912395 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5258 01:34:24.918385 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5259 01:34:24.922035 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5260 01:34:24.925336 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5261 01:34:24.928496 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5262 01:34:24.931706 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5263 01:34:24.932169 ==
5264 01:34:24.934991 Dram Type= 6, Freq= 0, CH_0, rank 1
5265 01:34:24.941661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5266 01:34:24.942232 ==
5267 01:34:24.942601 DQS Delay:
5268 01:34:24.944946 DQS0 = 0, DQS1 = 0
5269 01:34:24.945521 DQM Delay:
5270 01:34:24.948363 DQM0 = 98, DQM1 = 86
5271 01:34:24.948913 DQ Delay:
5272 01:34:24.951631 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =94
5273 01:34:24.955330 DQ4 =102, DQ5 =92, DQ6 =104, DQ7 =106
5274 01:34:24.958210 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =80
5275 01:34:24.961741 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =98
5276 01:34:24.962293
5277 01:34:24.962655
5278 01:34:24.968342 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5279 01:34:24.971607 CH0 RK1: MR19=505, MR18=2525
5280 01:34:24.978126 CH0_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5281 01:34:24.981536 [RxdqsGatingPostProcess] freq 933
5282 01:34:24.987929 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5283 01:34:24.988469 Pre-setting of DQS Precalculation
5284 01:34:24.994653 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5285 01:34:24.995189 ==
5286 01:34:24.998057 Dram Type= 6, Freq= 0, CH_1, rank 0
5287 01:34:25.001506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5288 01:34:25.002066 ==
5289 01:34:25.007914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5290 01:34:25.014635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5291 01:34:25.017736 [CA 0] Center 37 (7~68) winsize 62
5292 01:34:25.021248 [CA 1] Center 37 (6~68) winsize 63
5293 01:34:25.024369 [CA 2] Center 34 (4~65) winsize 62
5294 01:34:25.027551 [CA 3] Center 34 (4~65) winsize 62
5295 01:34:25.030856 [CA 4] Center 33 (2~64) winsize 63
5296 01:34:25.034191 [CA 5] Center 33 (3~64) winsize 62
5297 01:34:25.034699
5298 01:34:25.037556 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5299 01:34:25.038008
5300 01:34:25.040863 [CATrainingPosCal] consider 1 rank data
5301 01:34:25.044194 u2DelayCellTimex100 = 270/100 ps
5302 01:34:25.047458 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5303 01:34:25.051141 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5304 01:34:25.054617 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5305 01:34:25.057606 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5306 01:34:25.060719 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5307 01:34:25.064658 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5308 01:34:25.067738
5309 01:34:25.071128 CA PerBit enable=1, Macro0, CA PI delay=33
5310 01:34:25.071677
5311 01:34:25.073931 [CBTSetCACLKResult] CA Dly = 33
5312 01:34:25.074528 CS Dly: 5 (0~36)
5313 01:34:25.075058 ==
5314 01:34:25.077480 Dram Type= 6, Freq= 0, CH_1, rank 1
5315 01:34:25.080438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5316 01:34:25.083933 ==
5317 01:34:25.087382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5318 01:34:25.093842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5319 01:34:25.097116 [CA 0] Center 37 (6~68) winsize 63
5320 01:34:25.100307 [CA 1] Center 37 (6~68) winsize 63
5321 01:34:25.103607 [CA 2] Center 34 (4~65) winsize 62
5322 01:34:25.106998 [CA 3] Center 33 (3~64) winsize 62
5323 01:34:25.109959 [CA 4] Center 33 (3~64) winsize 62
5324 01:34:25.113377 [CA 5] Center 33 (2~64) winsize 63
5325 01:34:25.113832
5326 01:34:25.116994 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5327 01:34:25.117591
5328 01:34:25.120742 [CATrainingPosCal] consider 2 rank data
5329 01:34:25.123364 u2DelayCellTimex100 = 270/100 ps
5330 01:34:25.126891 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5331 01:34:25.130254 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5332 01:34:25.133421 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5333 01:34:25.139743 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5334 01:34:25.143429 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5335 01:34:25.146782 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5336 01:34:25.147331
5337 01:34:25.150094 CA PerBit enable=1, Macro0, CA PI delay=33
5338 01:34:25.150562
5339 01:34:25.153333 [CBTSetCACLKResult] CA Dly = 33
5340 01:34:25.153881 CS Dly: 5 (0~37)
5341 01:34:25.154242
5342 01:34:25.156345 ----->DramcWriteLeveling(PI) begin...
5343 01:34:25.159658 ==
5344 01:34:25.160107 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 01:34:25.166730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 01:34:25.167291 ==
5347 01:34:25.169952 Write leveling (Byte 0): 24 => 24
5348 01:34:25.172861 Write leveling (Byte 1): 24 => 24
5349 01:34:25.176648 DramcWriteLeveling(PI) end<-----
5350 01:34:25.177196
5351 01:34:25.177618 ==
5352 01:34:25.179918 Dram Type= 6, Freq= 0, CH_1, rank 0
5353 01:34:25.183260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5354 01:34:25.183810 ==
5355 01:34:25.186105 [Gating] SW mode calibration
5356 01:34:25.193449 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5357 01:34:25.196474 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5358 01:34:25.203010 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 01:34:25.206297 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 01:34:25.209188 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 01:34:25.216321 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 01:34:25.219696 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5363 01:34:25.222797 0 10 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
5364 01:34:25.229515 0 10 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
5365 01:34:25.232905 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 01:34:25.236050 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 01:34:25.242984 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 01:34:25.246254 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 01:34:25.249384 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 01:34:25.256110 0 11 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5371 01:34:25.259396 0 11 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
5372 01:34:25.262846 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5373 01:34:25.269476 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 01:34:25.272580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 01:34:25.276129 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 01:34:25.282694 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 01:34:25.285922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 01:34:25.289166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5379 01:34:25.295778 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5380 01:34:25.299216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 01:34:25.302541 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 01:34:25.309208 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 01:34:25.312276 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 01:34:25.315910 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 01:34:25.322166 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 01:34:25.325755 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 01:34:25.329397 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 01:34:25.335412 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 01:34:25.338568 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 01:34:25.341853 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 01:34:25.348933 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 01:34:25.351988 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 01:34:25.355260 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 01:34:25.361760 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5395 01:34:25.365231 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 01:34:25.368677 Total UI for P1: 0, mck2ui 16
5397 01:34:25.372090 best dqsien dly found for B0: ( 0, 14, 16)
5398 01:34:25.375130 Total UI for P1: 0, mck2ui 16
5399 01:34:25.378534 best dqsien dly found for B1: ( 0, 14, 18)
5400 01:34:25.382076 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5401 01:34:25.385357 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5402 01:34:25.385914
5403 01:34:25.388278 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5404 01:34:25.391893 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5405 01:34:25.394869 [Gating] SW calibration Done
5406 01:34:25.395475 ==
5407 01:34:25.398335 Dram Type= 6, Freq= 0, CH_1, rank 0
5408 01:34:25.401732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5409 01:34:25.404699 ==
5410 01:34:25.405162 RX Vref Scan: 0
5411 01:34:25.405582
5412 01:34:25.408110 RX Vref 0 -> 0, step: 1
5413 01:34:25.408568
5414 01:34:25.411460 RX Delay -80 -> 252, step: 8
5415 01:34:25.414657 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5416 01:34:25.417991 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5417 01:34:25.421349 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5418 01:34:25.424577 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5419 01:34:25.427784 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5420 01:34:25.434607 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5421 01:34:25.437814 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5422 01:34:25.440951 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5423 01:34:25.444277 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5424 01:34:25.447489 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5425 01:34:25.454269 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5426 01:34:25.457641 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5427 01:34:25.460955 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5428 01:34:25.464156 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5429 01:34:25.467520 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5430 01:34:25.474181 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5431 01:34:25.474640 ==
5432 01:34:25.477523 Dram Type= 6, Freq= 0, CH_1, rank 0
5433 01:34:25.481171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5434 01:34:25.481781 ==
5435 01:34:25.482153 DQS Delay:
5436 01:34:25.484478 DQS0 = 0, DQS1 = 0
5437 01:34:25.485039 DQM Delay:
5438 01:34:25.487312 DQM0 = 95, DQM1 = 88
5439 01:34:25.487770 DQ Delay:
5440 01:34:25.490713 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5441 01:34:25.494156 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5442 01:34:25.497340 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5443 01:34:25.500377 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5444 01:34:25.500837
5445 01:34:25.501202
5446 01:34:25.501666 ==
5447 01:34:25.503812 Dram Type= 6, Freq= 0, CH_1, rank 0
5448 01:34:25.507483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5449 01:34:25.508211 ==
5450 01:34:25.510786
5451 01:34:25.511343
5452 01:34:25.511714 TX Vref Scan disable
5453 01:34:25.513954 == TX Byte 0 ==
5454 01:34:25.517138 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5455 01:34:25.520708 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5456 01:34:25.523803 == TX Byte 1 ==
5457 01:34:25.527276 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5458 01:34:25.530009 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5459 01:34:25.533705 ==
5460 01:34:25.534169 Dram Type= 6, Freq= 0, CH_1, rank 0
5461 01:34:25.540160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5462 01:34:25.540619 ==
5463 01:34:25.540981
5464 01:34:25.541358
5465 01:34:25.543209 TX Vref Scan disable
5466 01:34:25.543697 == TX Byte 0 ==
5467 01:34:25.549946 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5468 01:34:25.553182 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5469 01:34:25.553697 == TX Byte 1 ==
5470 01:34:25.559902 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5471 01:34:25.563102 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5472 01:34:25.563564
5473 01:34:25.563925 [DATLAT]
5474 01:34:25.566424 Freq=933, CH1 RK0
5475 01:34:25.566957
5476 01:34:25.567324 DATLAT Default: 0xd
5477 01:34:25.569512 0, 0xFFFF, sum = 0
5478 01:34:25.569979 1, 0xFFFF, sum = 0
5479 01:34:25.573117 2, 0xFFFF, sum = 0
5480 01:34:25.573611 3, 0xFFFF, sum = 0
5481 01:34:25.576329 4, 0xFFFF, sum = 0
5482 01:34:25.576791 5, 0xFFFF, sum = 0
5483 01:34:25.579672 6, 0xFFFF, sum = 0
5484 01:34:25.580133 7, 0xFFFF, sum = 0
5485 01:34:25.582890 8, 0xFFFF, sum = 0
5486 01:34:25.586152 9, 0xFFFF, sum = 0
5487 01:34:25.586617 10, 0x0, sum = 1
5488 01:34:25.586986 11, 0x0, sum = 2
5489 01:34:25.589367 12, 0x0, sum = 3
5490 01:34:25.589832 13, 0x0, sum = 4
5491 01:34:25.592709 best_step = 11
5492 01:34:25.593162
5493 01:34:25.593569 ==
5494 01:34:25.596320 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 01:34:25.599493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5496 01:34:25.599979 ==
5497 01:34:25.602640 RX Vref Scan: 1
5498 01:34:25.603096
5499 01:34:25.603460 RX Vref 0 -> 0, step: 1
5500 01:34:25.606094
5501 01:34:25.606554 RX Delay -69 -> 252, step: 4
5502 01:34:25.606920
5503 01:34:25.609216 Set Vref, RX VrefLevel [Byte0]: 57
5504 01:34:25.612616 [Byte1]: 50
5505 01:34:25.617515
5506 01:34:25.617972 Final RX Vref Byte 0 = 57 to rank0
5507 01:34:25.620535 Final RX Vref Byte 1 = 50 to rank0
5508 01:34:25.624043 Final RX Vref Byte 0 = 57 to rank1
5509 01:34:25.627271 Final RX Vref Byte 1 = 50 to rank1==
5510 01:34:25.630277 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 01:34:25.636763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5512 01:34:25.637451 ==
5513 01:34:25.637835 DQS Delay:
5514 01:34:25.638175 DQS0 = 0, DQS1 = 0
5515 01:34:25.640501 DQM Delay:
5516 01:34:25.641092 DQM0 = 93, DQM1 = 88
5517 01:34:25.643936 DQ Delay:
5518 01:34:25.647029 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =90
5519 01:34:25.650465 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5520 01:34:25.653568 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5521 01:34:25.657150 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5522 01:34:25.657931
5523 01:34:25.658326
5524 01:34:25.663578 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5525 01:34:25.667043 CH1 RK0: MR19=505, MR18=3434
5526 01:34:25.673567 CH1_RK0: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5527 01:34:25.674129
5528 01:34:25.676542 ----->DramcWriteLeveling(PI) begin...
5529 01:34:25.677005 ==
5530 01:34:25.680287 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 01:34:25.683295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5532 01:34:25.683875 ==
5533 01:34:25.686430 Write leveling (Byte 0): 21 => 21
5534 01:34:25.689752 Write leveling (Byte 1): 24 => 24
5535 01:34:25.693249 DramcWriteLeveling(PI) end<-----
5536 01:34:25.693863
5537 01:34:25.694235 ==
5538 01:34:25.696715 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 01:34:25.699527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5540 01:34:25.703065 ==
5541 01:34:25.703626 [Gating] SW mode calibration
5542 01:34:25.709857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5543 01:34:25.716451 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5544 01:34:25.719800 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 01:34:25.726046 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 01:34:25.729487 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 01:34:25.732998 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5548 01:34:25.739778 0 10 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5549 01:34:25.742890 0 10 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
5550 01:34:25.746128 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 01:34:25.752825 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 01:34:25.756089 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 01:34:25.759093 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 01:34:25.765835 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 01:34:25.769411 0 11 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5556 01:34:25.772367 0 11 16 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
5557 01:34:25.779217 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5558 01:34:25.782574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 01:34:25.785872 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 01:34:25.792524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 01:34:25.795511 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 01:34:25.798899 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 01:34:25.805696 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 01:34:25.809249 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 01:34:25.812508 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5566 01:34:25.819036 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 01:34:25.822498 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 01:34:25.825811 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 01:34:25.832393 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 01:34:25.835526 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 01:34:25.838761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 01:34:25.845634 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 01:34:25.848674 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 01:34:25.852326 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 01:34:25.858548 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 01:34:25.861800 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 01:34:25.865010 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 01:34:25.871709 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 01:34:25.874980 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 01:34:25.878386 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5581 01:34:25.885319 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 01:34:25.885896 Total UI for P1: 0, mck2ui 16
5583 01:34:25.888252 best dqsien dly found for B0: ( 0, 14, 16)
5584 01:34:25.891814 Total UI for P1: 0, mck2ui 16
5585 01:34:25.894794 best dqsien dly found for B1: ( 0, 14, 18)
5586 01:34:25.898197 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5587 01:34:25.905092 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5588 01:34:25.905691
5589 01:34:25.908065 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5590 01:34:25.911309 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5591 01:34:25.914786 [Gating] SW calibration Done
5592 01:34:25.915355 ==
5593 01:34:25.918090 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 01:34:25.921684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5595 01:34:25.922261 ==
5596 01:34:25.924742 RX Vref Scan: 0
5597 01:34:25.925345
5598 01:34:25.925840 RX Vref 0 -> 0, step: 1
5599 01:34:25.926298
5600 01:34:25.928384 RX Delay -80 -> 252, step: 8
5601 01:34:25.931142 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5602 01:34:25.937937 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5603 01:34:25.941017 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5604 01:34:25.944756 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5605 01:34:25.948129 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5606 01:34:25.951170 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5607 01:34:25.954746 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5608 01:34:25.961391 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5609 01:34:25.964343 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5610 01:34:25.967568 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5611 01:34:25.971099 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5612 01:34:25.974489 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5613 01:34:25.981120 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5614 01:34:25.984678 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5615 01:34:25.987752 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5616 01:34:25.991195 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5617 01:34:25.991757 ==
5618 01:34:25.994150 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 01:34:25.998218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5620 01:34:25.998778 ==
5621 01:34:26.000805 DQS Delay:
5622 01:34:26.001280 DQS0 = 0, DQS1 = 0
5623 01:34:26.004403 DQM Delay:
5624 01:34:26.004981 DQM0 = 95, DQM1 = 88
5625 01:34:26.005554 DQ Delay:
5626 01:34:26.007338 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5627 01:34:26.010768 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5628 01:34:26.014031 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5629 01:34:26.017066 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5630 01:34:26.017587
5631 01:34:26.018067
5632 01:34:26.020515 ==
5633 01:34:26.024153 Dram Type= 6, Freq= 0, CH_1, rank 1
5634 01:34:26.027159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5635 01:34:26.027639 ==
5636 01:34:26.028124
5637 01:34:26.028576
5638 01:34:26.030553 TX Vref Scan disable
5639 01:34:26.031026 == TX Byte 0 ==
5640 01:34:26.033732 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5641 01:34:26.040386 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5642 01:34:26.040951 == TX Byte 1 ==
5643 01:34:26.047193 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5644 01:34:26.050302 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5645 01:34:26.050782 ==
5646 01:34:26.053580 Dram Type= 6, Freq= 0, CH_1, rank 1
5647 01:34:26.057124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5648 01:34:26.057767 ==
5649 01:34:26.058259
5650 01:34:26.058710
5651 01:34:26.060218 TX Vref Scan disable
5652 01:34:26.063783 == TX Byte 0 ==
5653 01:34:26.067123 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5654 01:34:26.070128 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5655 01:34:26.073817 == TX Byte 1 ==
5656 01:34:26.076842 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5657 01:34:26.079909 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5658 01:34:26.080385
5659 01:34:26.083475 [DATLAT]
5660 01:34:26.084052 Freq=933, CH1 RK1
5661 01:34:26.084547
5662 01:34:26.086599 DATLAT Default: 0xb
5663 01:34:26.087091 0, 0xFFFF, sum = 0
5664 01:34:26.089863 1, 0xFFFF, sum = 0
5665 01:34:26.090350 2, 0xFFFF, sum = 0
5666 01:34:26.093505 3, 0xFFFF, sum = 0
5667 01:34:26.094088 4, 0xFFFF, sum = 0
5668 01:34:26.096638 5, 0xFFFF, sum = 0
5669 01:34:26.097221 6, 0xFFFF, sum = 0
5670 01:34:26.099894 7, 0xFFFF, sum = 0
5671 01:34:26.100480 8, 0xFFFF, sum = 0
5672 01:34:26.103188 9, 0xFFFF, sum = 0
5673 01:34:26.103775 10, 0x0, sum = 1
5674 01:34:26.106267 11, 0x0, sum = 2
5675 01:34:26.106749 12, 0x0, sum = 3
5676 01:34:26.110012 13, 0x0, sum = 4
5677 01:34:26.110600 best_step = 11
5678 01:34:26.111095
5679 01:34:26.111553 ==
5680 01:34:26.112914 Dram Type= 6, Freq= 0, CH_1, rank 1
5681 01:34:26.119723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5682 01:34:26.120306 ==
5683 01:34:26.120870 RX Vref Scan: 0
5684 01:34:26.121361
5685 01:34:26.122736 RX Vref 0 -> 0, step: 1
5686 01:34:26.123213
5687 01:34:26.126149 RX Delay -69 -> 252, step: 4
5688 01:34:26.130193 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5689 01:34:26.132706 iDelay=203, Bit 1, Center 90 (-5 ~ 186) 192
5690 01:34:26.139572 iDelay=203, Bit 2, Center 86 (-9 ~ 182) 192
5691 01:34:26.142749 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5692 01:34:26.146069 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5693 01:34:26.149477 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5694 01:34:26.152847 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5695 01:34:26.159181 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5696 01:34:26.162748 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5697 01:34:26.165873 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5698 01:34:26.169270 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5699 01:34:26.172776 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5700 01:34:26.179288 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5701 01:34:26.182482 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5702 01:34:26.185863 iDelay=203, Bit 14, Center 98 (3 ~ 194) 192
5703 01:34:26.189246 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5704 01:34:26.189850 ==
5705 01:34:26.192559 Dram Type= 6, Freq= 0, CH_1, rank 1
5706 01:34:26.195667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5707 01:34:26.198950 ==
5708 01:34:26.199505 DQS Delay:
5709 01:34:26.199874 DQS0 = 0, DQS1 = 0
5710 01:34:26.202401 DQM Delay:
5711 01:34:26.202999 DQM0 = 95, DQM1 = 87
5712 01:34:26.205559 DQ Delay:
5713 01:34:26.206112 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5714 01:34:26.209152 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =96
5715 01:34:26.212124 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5716 01:34:26.215386 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =94
5717 01:34:26.219149
5718 01:34:26.219725
5719 01:34:26.225737 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5720 01:34:26.228862 CH1 RK1: MR19=505, MR18=2222
5721 01:34:26.235081 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5722 01:34:26.238669 [RxdqsGatingPostProcess] freq 933
5723 01:34:26.241971 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5724 01:34:26.245412 Pre-setting of DQS Precalculation
5725 01:34:26.251927 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5726 01:34:26.258477 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5727 01:34:26.264985 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5728 01:34:26.265617
5729 01:34:26.265993
5730 01:34:26.268518 [Calibration Summary] 1866 Mbps
5731 01:34:26.269070 CH 0, Rank 0
5732 01:34:26.271762 SW Impedance : PASS
5733 01:34:26.275338 DUTY Scan : NO K
5734 01:34:26.275956 ZQ Calibration : PASS
5735 01:34:26.278220 Jitter Meter : NO K
5736 01:34:26.281671 CBT Training : PASS
5737 01:34:26.282221 Write leveling : PASS
5738 01:34:26.284850 RX DQS gating : PASS
5739 01:34:26.288314 RX DQ/DQS(RDDQC) : PASS
5740 01:34:26.288864 TX DQ/DQS : PASS
5741 01:34:26.291299 RX DATLAT : PASS
5742 01:34:26.294907 RX DQ/DQS(Engine): PASS
5743 01:34:26.295514 TX OE : NO K
5744 01:34:26.295903 All Pass.
5745 01:34:26.298742
5746 01:34:26.299296 CH 0, Rank 1
5747 01:34:26.301466 SW Impedance : PASS
5748 01:34:26.302066 DUTY Scan : NO K
5749 01:34:26.304665 ZQ Calibration : PASS
5750 01:34:26.305119 Jitter Meter : NO K
5751 01:34:26.308157 CBT Training : PASS
5752 01:34:26.311545 Write leveling : PASS
5753 01:34:26.312095 RX DQS gating : PASS
5754 01:34:26.314961 RX DQ/DQS(RDDQC) : PASS
5755 01:34:26.318043 TX DQ/DQS : PASS
5756 01:34:26.318501 RX DATLAT : PASS
5757 01:34:26.321175 RX DQ/DQS(Engine): PASS
5758 01:34:26.324759 TX OE : NO K
5759 01:34:26.325346 All Pass.
5760 01:34:26.325721
5761 01:34:26.326060 CH 1, Rank 0
5762 01:34:26.328103 SW Impedance : PASS
5763 01:34:26.331634 DUTY Scan : NO K
5764 01:34:26.332195 ZQ Calibration : PASS
5765 01:34:26.334606 Jitter Meter : NO K
5766 01:34:26.337758 CBT Training : PASS
5767 01:34:26.338313 Write leveling : PASS
5768 01:34:26.341203 RX DQS gating : PASS
5769 01:34:26.344688 RX DQ/DQS(RDDQC) : PASS
5770 01:34:26.345239 TX DQ/DQS : PASS
5771 01:34:26.347846 RX DATLAT : PASS
5772 01:34:26.351230 RX DQ/DQS(Engine): PASS
5773 01:34:26.351778 TX OE : NO K
5774 01:34:26.352151 All Pass.
5775 01:34:26.354483
5776 01:34:26.355031 CH 1, Rank 1
5777 01:34:26.357688 SW Impedance : PASS
5778 01:34:26.358145 DUTY Scan : NO K
5779 01:34:26.360942 ZQ Calibration : PASS
5780 01:34:26.361442 Jitter Meter : NO K
5781 01:34:26.364466 CBT Training : PASS
5782 01:34:26.367802 Write leveling : PASS
5783 01:34:26.368363 RX DQS gating : PASS
5784 01:34:26.371404 RX DQ/DQS(RDDQC) : PASS
5785 01:34:26.374134 TX DQ/DQS : PASS
5786 01:34:26.374630 RX DATLAT : PASS
5787 01:34:26.377368 RX DQ/DQS(Engine): PASS
5788 01:34:26.381154 TX OE : NO K
5789 01:34:26.381748 All Pass.
5790 01:34:26.382114
5791 01:34:26.384383 DramC Write-DBI off
5792 01:34:26.384928 PER_BANK_REFRESH: Hybrid Mode
5793 01:34:26.387905 TX_TRACKING: ON
5794 01:34:26.394615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5795 01:34:26.401248 [FAST_K] Save calibration result to emmc
5796 01:34:26.403980 dramc_set_vcore_voltage set vcore to 650000
5797 01:34:26.404439 Read voltage for 400, 6
5798 01:34:26.407577 Vio18 = 0
5799 01:34:26.408128 Vcore = 650000
5800 01:34:26.408493 Vdram = 0
5801 01:34:26.410753 Vddq = 0
5802 01:34:26.411298 Vmddr = 0
5803 01:34:26.413969 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5804 01:34:26.420597 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5805 01:34:26.423985 MEM_TYPE=3, freq_sel=20
5806 01:34:26.427432 sv_algorithm_assistance_LP4_800
5807 01:34:26.430632 ============ PULL DRAM RESETB DOWN ============
5808 01:34:26.434181 ========== PULL DRAM RESETB DOWN end =========
5809 01:34:26.440302 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5810 01:34:26.443923 ===================================
5811 01:34:26.444499 LPDDR4 DRAM CONFIGURATION
5812 01:34:26.447250 ===================================
5813 01:34:26.450912 EX_ROW_EN[0] = 0x0
5814 01:34:26.451487 EX_ROW_EN[1] = 0x0
5815 01:34:26.453756 LP4Y_EN = 0x0
5816 01:34:26.454230 WORK_FSP = 0x0
5817 01:34:26.457101 WL = 0x2
5818 01:34:26.460227 RL = 0x2
5819 01:34:26.460704 BL = 0x2
5820 01:34:26.463926 RPST = 0x0
5821 01:34:26.464510 RD_PRE = 0x0
5822 01:34:26.466764 WR_PRE = 0x1
5823 01:34:26.467238 WR_PST = 0x0
5824 01:34:26.470198 DBI_WR = 0x0
5825 01:34:26.470795 DBI_RD = 0x0
5826 01:34:26.473502 OTF = 0x1
5827 01:34:26.476950 ===================================
5828 01:34:26.480520 ===================================
5829 01:34:26.481096 ANA top config
5830 01:34:26.483487 ===================================
5831 01:34:26.487057 DLL_ASYNC_EN = 0
5832 01:34:26.489873 ALL_SLAVE_EN = 1
5833 01:34:26.490375 NEW_RANK_MODE = 1
5834 01:34:26.493400 DLL_IDLE_MODE = 1
5835 01:34:26.496802 LP45_APHY_COMB_EN = 1
5836 01:34:26.499954 TX_ODT_DIS = 1
5837 01:34:26.503441 NEW_8X_MODE = 1
5838 01:34:26.506748 ===================================
5839 01:34:26.509941 ===================================
5840 01:34:26.513012 data_rate = 800
5841 01:34:26.513603 CKR = 1
5842 01:34:26.516493 DQ_P2S_RATIO = 4
5843 01:34:26.519690 ===================================
5844 01:34:26.522884 CA_P2S_RATIO = 4
5845 01:34:26.526488 DQ_CA_OPEN = 0
5846 01:34:26.529986 DQ_SEMI_OPEN = 1
5847 01:34:26.530548 CA_SEMI_OPEN = 1
5848 01:34:26.533131 CA_FULL_RATE = 0
5849 01:34:26.536142 DQ_CKDIV4_EN = 0
5850 01:34:26.539755 CA_CKDIV4_EN = 1
5851 01:34:26.542815 CA_PREDIV_EN = 0
5852 01:34:26.546030 PH8_DLY = 0
5853 01:34:26.549394 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5854 01:34:26.549854 DQ_AAMCK_DIV = 0
5855 01:34:26.552620 CA_AAMCK_DIV = 0
5856 01:34:26.556227 CA_ADMCK_DIV = 4
5857 01:34:26.559461 DQ_TRACK_CA_EN = 0
5858 01:34:26.562432 CA_PICK = 800
5859 01:34:26.565735 CA_MCKIO = 400
5860 01:34:26.569366 MCKIO_SEMI = 400
5861 01:34:26.569940 PLL_FREQ = 3016
5862 01:34:26.572611 DQ_UI_PI_RATIO = 32
5863 01:34:26.575636 CA_UI_PI_RATIO = 32
5864 01:34:26.579173 ===================================
5865 01:34:26.582526 ===================================
5866 01:34:26.585905 memory_type:LPDDR4
5867 01:34:26.589186 GP_NUM : 10
5868 01:34:26.589848 SRAM_EN : 1
5869 01:34:26.592412 MD32_EN : 0
5870 01:34:26.595487 ===================================
5871 01:34:26.596031 [ANA_INIT] >>>>>>>>>>>>>>
5872 01:34:26.598911 <<<<<< [CONFIGURE PHASE]: ANA_TX
5873 01:34:26.602648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5874 01:34:26.605674 ===================================
5875 01:34:26.609137 data_rate = 800,PCW = 0X7400
5876 01:34:26.612371 ===================================
5877 01:34:26.615385 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5878 01:34:26.622038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5879 01:34:26.632343 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5880 01:34:26.638420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5881 01:34:26.641779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5882 01:34:26.645453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5883 01:34:26.646027 [ANA_INIT] flow start
5884 01:34:26.648668 [ANA_INIT] PLL >>>>>>>>
5885 01:34:26.651659 [ANA_INIT] PLL <<<<<<<<
5886 01:34:26.652135 [ANA_INIT] MIDPI >>>>>>>>
5887 01:34:26.655154 [ANA_INIT] MIDPI <<<<<<<<
5888 01:34:26.658581 [ANA_INIT] DLL >>>>>>>>
5889 01:34:26.659056 [ANA_INIT] flow end
5890 01:34:26.665212 ============ LP4 DIFF to SE enter ============
5891 01:34:26.668775 ============ LP4 DIFF to SE exit ============
5892 01:34:26.671674 [ANA_INIT] <<<<<<<<<<<<<
5893 01:34:26.674990 [Flow] Enable top DCM control >>>>>
5894 01:34:26.678393 [Flow] Enable top DCM control <<<<<
5895 01:34:26.678871 Enable DLL master slave shuffle
5896 01:34:26.685000 ==============================================================
5897 01:34:26.688339 Gating Mode config
5898 01:34:26.691612 ==============================================================
5899 01:34:26.695069 Config description:
5900 01:34:26.705019 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5901 01:34:26.711613 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5902 01:34:26.714842 SELPH_MODE 0: By rank 1: By Phase
5903 01:34:26.721238 ==============================================================
5904 01:34:26.725161 GAT_TRACK_EN = 0
5905 01:34:26.728266 RX_GATING_MODE = 2
5906 01:34:26.731532 RX_GATING_TRACK_MODE = 2
5907 01:34:26.734792 SELPH_MODE = 1
5908 01:34:26.738078 PICG_EARLY_EN = 1
5909 01:34:26.738554 VALID_LAT_VALUE = 1
5910 01:34:26.744571 ==============================================================
5911 01:34:26.747687 Enter into Gating configuration >>>>
5912 01:34:26.751206 Exit from Gating configuration <<<<
5913 01:34:26.754386 Enter into DVFS_PRE_config >>>>>
5914 01:34:26.764293 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5915 01:34:26.767637 Exit from DVFS_PRE_config <<<<<
5916 01:34:26.771038 Enter into PICG configuration >>>>
5917 01:34:26.774381 Exit from PICG configuration <<<<
5918 01:34:26.777517 [RX_INPUT] configuration >>>>>
5919 01:34:26.780935 [RX_INPUT] configuration <<<<<
5920 01:34:26.787234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5921 01:34:26.790635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5922 01:34:26.797346 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5923 01:34:26.804157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5924 01:34:26.810551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5925 01:34:26.816852 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5926 01:34:26.820286 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5927 01:34:26.823675 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5928 01:34:26.827016 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5929 01:34:26.833381 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5930 01:34:26.837514 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5931 01:34:26.840766 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5932 01:34:26.843304 ===================================
5933 01:34:26.847107 LPDDR4 DRAM CONFIGURATION
5934 01:34:26.850298 ===================================
5935 01:34:26.853679 EX_ROW_EN[0] = 0x0
5936 01:34:26.854264 EX_ROW_EN[1] = 0x0
5937 01:34:26.856888 LP4Y_EN = 0x0
5938 01:34:26.857499 WORK_FSP = 0x0
5939 01:34:26.860131 WL = 0x2
5940 01:34:26.860712 RL = 0x2
5941 01:34:26.863788 BL = 0x2
5942 01:34:26.864358 RPST = 0x0
5943 01:34:26.866801 RD_PRE = 0x0
5944 01:34:26.867375 WR_PRE = 0x1
5945 01:34:26.870211 WR_PST = 0x0
5946 01:34:26.870791 DBI_WR = 0x0
5947 01:34:26.873545 DBI_RD = 0x0
5948 01:34:26.874117 OTF = 0x1
5949 01:34:26.876517 ===================================
5950 01:34:26.883189 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5951 01:34:26.886372 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5952 01:34:26.889514 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5953 01:34:26.893045 ===================================
5954 01:34:26.896411 LPDDR4 DRAM CONFIGURATION
5955 01:34:26.899509 ===================================
5956 01:34:26.902787 EX_ROW_EN[0] = 0x10
5957 01:34:26.903269 EX_ROW_EN[1] = 0x0
5958 01:34:26.906209 LP4Y_EN = 0x0
5959 01:34:26.906685 WORK_FSP = 0x0
5960 01:34:26.909559 WL = 0x2
5961 01:34:26.910034 RL = 0x2
5962 01:34:26.912652 BL = 0x2
5963 01:34:26.913130 RPST = 0x0
5964 01:34:26.916660 RD_PRE = 0x0
5965 01:34:26.917236 WR_PRE = 0x1
5966 01:34:26.919307 WR_PST = 0x0
5967 01:34:26.919781 DBI_WR = 0x0
5968 01:34:26.922710 DBI_RD = 0x0
5969 01:34:26.923221 OTF = 0x1
5970 01:34:26.925868 ===================================
5971 01:34:26.932529 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5972 01:34:26.937689 nWR fixed to 30
5973 01:34:26.940923 [ModeRegInit_LP4] CH0 RK0
5974 01:34:26.941539 [ModeRegInit_LP4] CH0 RK1
5975 01:34:26.943806 [ModeRegInit_LP4] CH1 RK0
5976 01:34:26.947429 [ModeRegInit_LP4] CH1 RK1
5977 01:34:26.947979 match AC timing 18
5978 01:34:26.953985 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5979 01:34:26.957687 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5980 01:34:26.960804 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5981 01:34:26.967526 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5982 01:34:26.970478 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5983 01:34:26.970947 ==
5984 01:34:26.974016 Dram Type= 6, Freq= 0, CH_0, rank 0
5985 01:34:26.977428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5986 01:34:26.977995 ==
5987 01:34:26.984136 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5988 01:34:26.990380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5989 01:34:26.993734 [CA 0] Center 36 (8~64) winsize 57
5990 01:34:26.997144 [CA 1] Center 36 (8~64) winsize 57
5991 01:34:27.000527 [CA 2] Center 36 (8~64) winsize 57
5992 01:34:27.003516 [CA 3] Center 36 (8~64) winsize 57
5993 01:34:27.006988 [CA 4] Center 36 (8~64) winsize 57
5994 01:34:27.007736 [CA 5] Center 36 (8~64) winsize 57
5995 01:34:27.010411
5996 01:34:27.013223 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5997 01:34:27.013713
5998 01:34:27.016706 [CATrainingPosCal] consider 1 rank data
5999 01:34:27.020264 u2DelayCellTimex100 = 270/100 ps
6000 01:34:27.023136 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 01:34:27.026726 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6002 01:34:27.029965 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6003 01:34:27.032963 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 01:34:27.036634 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 01:34:27.039916 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 01:34:27.040470
6007 01:34:27.042846 CA PerBit enable=1, Macro0, CA PI delay=36
6008 01:34:27.043258
6009 01:34:27.046223 [CBTSetCACLKResult] CA Dly = 36
6010 01:34:27.049682 CS Dly: 1 (0~32)
6011 01:34:27.050266 ==
6012 01:34:27.052984 Dram Type= 6, Freq= 0, CH_0, rank 1
6013 01:34:27.056140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6014 01:34:27.056626 ==
6015 01:34:27.063184 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6016 01:34:27.069625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6017 01:34:27.072838 [CA 0] Center 36 (8~64) winsize 57
6018 01:34:27.076101 [CA 1] Center 36 (8~64) winsize 57
6019 01:34:27.076690 [CA 2] Center 36 (8~64) winsize 57
6020 01:34:27.079302 [CA 3] Center 36 (8~64) winsize 57
6021 01:34:27.082967 [CA 4] Center 36 (8~64) winsize 57
6022 01:34:27.086269 [CA 5] Center 36 (8~64) winsize 57
6023 01:34:27.086836
6024 01:34:27.089719 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6025 01:34:27.090294
6026 01:34:27.096364 [CATrainingPosCal] consider 2 rank data
6027 01:34:27.096935 u2DelayCellTimex100 = 270/100 ps
6028 01:34:27.102803 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 01:34:27.106071 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 01:34:27.109366 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 01:34:27.112476 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 01:34:27.116265 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 01:34:27.119060 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 01:34:27.119538
6035 01:34:27.122553 CA PerBit enable=1, Macro0, CA PI delay=36
6036 01:34:27.123130
6037 01:34:27.125958 [CBTSetCACLKResult] CA Dly = 36
6038 01:34:27.128957 CS Dly: 1 (0~32)
6039 01:34:27.129560
6040 01:34:27.132546 ----->DramcWriteLeveling(PI) begin...
6041 01:34:27.133129 ==
6042 01:34:27.136099 Dram Type= 6, Freq= 0, CH_0, rank 0
6043 01:34:27.139100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6044 01:34:27.139579 ==
6045 01:34:27.142145 Write leveling (Byte 0): 32 => 0
6046 01:34:27.145342 Write leveling (Byte 1): 32 => 0
6047 01:34:27.148877 DramcWriteLeveling(PI) end<-----
6048 01:34:27.149496
6049 01:34:27.149982 ==
6050 01:34:27.151996 Dram Type= 6, Freq= 0, CH_0, rank 0
6051 01:34:27.155415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6052 01:34:27.155891 ==
6053 01:34:27.158768 [Gating] SW mode calibration
6054 01:34:27.165400 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6055 01:34:27.171794 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6056 01:34:27.175247 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6057 01:34:27.178846 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6058 01:34:27.185560 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6059 01:34:27.188601 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6060 01:34:27.191728 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6061 01:34:27.198347 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6062 01:34:27.201918 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6063 01:34:27.205193 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6064 01:34:27.211740 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6065 01:34:27.215243 Total UI for P1: 0, mck2ui 16
6066 01:34:27.218188 best dqsien dly found for B0: ( 0, 10, 16)
6067 01:34:27.218765 Total UI for P1: 0, mck2ui 16
6068 01:34:27.224671 best dqsien dly found for B1: ( 0, 10, 16)
6069 01:34:27.228165 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6070 01:34:27.231543 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6071 01:34:27.232121
6072 01:34:27.235245 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6073 01:34:27.238204 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6074 01:34:27.241527 [Gating] SW calibration Done
6075 01:34:27.242125 ==
6076 01:34:27.244486 Dram Type= 6, Freq= 0, CH_0, rank 0
6077 01:34:27.248298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6078 01:34:27.248855 ==
6079 01:34:27.251458 RX Vref Scan: 0
6080 01:34:27.252012
6081 01:34:27.254429 RX Vref 0 -> 0, step: 1
6082 01:34:27.254933
6083 01:34:27.255364 RX Delay -410 -> 252, step: 16
6084 01:34:27.261478 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6085 01:34:27.264834 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6086 01:34:27.268112 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6087 01:34:27.271416 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6088 01:34:27.277912 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6089 01:34:27.281231 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6090 01:34:27.284529 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6091 01:34:27.287916 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6092 01:34:27.294451 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6093 01:34:27.297603 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6094 01:34:27.301320 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6095 01:34:27.307614 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6096 01:34:27.310908 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6097 01:34:27.314297 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6098 01:34:27.317900 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6099 01:34:27.324337 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6100 01:34:27.324881 ==
6101 01:34:27.327540 Dram Type= 6, Freq= 0, CH_0, rank 0
6102 01:34:27.331127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6103 01:34:27.331683 ==
6104 01:34:27.332054 DQS Delay:
6105 01:34:27.334101 DQS0 = 51, DQS1 = 59
6106 01:34:27.334561 DQM Delay:
6107 01:34:27.337385 DQM0 = 12, DQM1 = 11
6108 01:34:27.337935 DQ Delay:
6109 01:34:27.340913 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6110 01:34:27.344106 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6111 01:34:27.347335 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6112 01:34:27.350741 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6113 01:34:27.351318
6114 01:34:27.351855
6115 01:34:27.352381 ==
6116 01:34:27.353823 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 01:34:27.357095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 01:34:27.357597 ==
6119 01:34:27.358177
6120 01:34:27.358545
6121 01:34:27.360610 TX Vref Scan disable
6122 01:34:27.363973 == TX Byte 0 ==
6123 01:34:27.367473 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6124 01:34:27.370826 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6125 01:34:27.373887 == TX Byte 1 ==
6126 01:34:27.377468 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 01:34:27.380555 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 01:34:27.381119 ==
6129 01:34:27.383839 Dram Type= 6, Freq= 0, CH_0, rank 0
6130 01:34:27.387150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6131 01:34:27.390320 ==
6132 01:34:27.390876
6133 01:34:27.391242
6134 01:34:27.391581 TX Vref Scan disable
6135 01:34:27.393618 == TX Byte 0 ==
6136 01:34:27.396963 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6137 01:34:27.400411 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6138 01:34:27.403558 == TX Byte 1 ==
6139 01:34:27.407073 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6140 01:34:27.410947 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6141 01:34:27.411526
6142 01:34:27.413771 [DATLAT]
6143 01:34:27.414248 Freq=400, CH0 RK0
6144 01:34:27.414738
6145 01:34:27.417286 DATLAT Default: 0xf
6146 01:34:27.417905 0, 0xFFFF, sum = 0
6147 01:34:27.420449 1, 0xFFFF, sum = 0
6148 01:34:27.420932 2, 0xFFFF, sum = 0
6149 01:34:27.423729 3, 0xFFFF, sum = 0
6150 01:34:27.424317 4, 0xFFFF, sum = 0
6151 01:34:27.427119 5, 0xFFFF, sum = 0
6152 01:34:27.427700 6, 0xFFFF, sum = 0
6153 01:34:27.430098 7, 0xFFFF, sum = 0
6154 01:34:27.430576 8, 0xFFFF, sum = 0
6155 01:34:27.433620 9, 0xFFFF, sum = 0
6156 01:34:27.434206 10, 0xFFFF, sum = 0
6157 01:34:27.436991 11, 0xFFFF, sum = 0
6158 01:34:27.437629 12, 0x0, sum = 1
6159 01:34:27.440067 13, 0x0, sum = 2
6160 01:34:27.440650 14, 0x0, sum = 3
6161 01:34:27.443412 15, 0x0, sum = 4
6162 01:34:27.443960 best_step = 13
6163 01:34:27.444439
6164 01:34:27.444907 ==
6165 01:34:27.446898 Dram Type= 6, Freq= 0, CH_0, rank 0
6166 01:34:27.453675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6167 01:34:27.454257 ==
6168 01:34:27.454751 RX Vref Scan: 1
6169 01:34:27.455208
6170 01:34:27.456638 RX Vref 0 -> 0, step: 1
6171 01:34:27.457112
6172 01:34:27.459876 RX Delay -359 -> 252, step: 8
6173 01:34:27.460369
6174 01:34:27.463522 Set Vref, RX VrefLevel [Byte0]: 47
6175 01:34:27.467135 [Byte1]: 49
6176 01:34:27.469854
6177 01:34:27.470332 Final RX Vref Byte 0 = 47 to rank0
6178 01:34:27.473504 Final RX Vref Byte 1 = 49 to rank0
6179 01:34:27.476650 Final RX Vref Byte 0 = 47 to rank1
6180 01:34:27.479914 Final RX Vref Byte 1 = 49 to rank1==
6181 01:34:27.483408 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 01:34:27.489964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 01:34:27.490544 ==
6184 01:34:27.491040 DQS Delay:
6185 01:34:27.493091 DQS0 = 52, DQS1 = 68
6186 01:34:27.493715 DQM Delay:
6187 01:34:27.494215 DQM0 = 9, DQM1 = 16
6188 01:34:27.496349 DQ Delay:
6189 01:34:27.499327 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6190 01:34:27.499820 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6191 01:34:27.502872 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6192 01:34:27.505973 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6193 01:34:27.506450
6194 01:34:27.509462
6195 01:34:27.516371 [DQSOSCAuto] RK0, (LSB)MR18= 0x9696, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6196 01:34:27.519755 CH0 RK0: MR19=C0C, MR18=9696
6197 01:34:27.526358 CH0_RK0: MR19=0xC0C, MR18=0x9696, DQSOSC=391, MR23=63, INC=386, DEC=257
6198 01:34:27.526952 ==
6199 01:34:27.529235 Dram Type= 6, Freq= 0, CH_0, rank 1
6200 01:34:27.532752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6201 01:34:27.533364 ==
6202 01:34:27.535760 [Gating] SW mode calibration
6203 01:34:27.542921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6204 01:34:27.549196 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6205 01:34:27.552502 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6206 01:34:27.555984 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6207 01:34:27.562379 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6208 01:34:27.565742 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6209 01:34:27.569274 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6210 01:34:27.575721 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6211 01:34:27.579049 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6212 01:34:27.582611 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6213 01:34:27.588916 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6214 01:34:27.589530 Total UI for P1: 0, mck2ui 16
6215 01:34:27.592289 best dqsien dly found for B0: ( 0, 10, 16)
6216 01:34:27.595492 Total UI for P1: 0, mck2ui 16
6217 01:34:27.598720 best dqsien dly found for B1: ( 0, 10, 24)
6218 01:34:27.605142 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6219 01:34:27.608815 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6220 01:34:27.609431
6221 01:34:27.612083 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6222 01:34:27.615290 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6223 01:34:27.618513 [Gating] SW calibration Done
6224 01:34:27.619085 ==
6225 01:34:27.621998 Dram Type= 6, Freq= 0, CH_0, rank 1
6226 01:34:27.625460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 01:34:27.626042 ==
6228 01:34:27.628696 RX Vref Scan: 0
6229 01:34:27.629280
6230 01:34:27.629815 RX Vref 0 -> 0, step: 1
6231 01:34:27.630276
6232 01:34:27.632085 RX Delay -410 -> 252, step: 16
6233 01:34:27.638484 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6234 01:34:27.641947 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6235 01:34:27.644806 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6236 01:34:27.648206 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6237 01:34:27.655141 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6238 01:34:27.658073 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6239 01:34:27.661877 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6240 01:34:27.664833 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6241 01:34:27.671655 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6242 01:34:27.674706 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6243 01:34:27.678142 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6244 01:34:27.681439 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6245 01:34:27.688023 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6246 01:34:27.691392 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6247 01:34:27.694779 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6248 01:34:27.701362 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6249 01:34:27.701928 ==
6250 01:34:27.704330 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 01:34:27.707777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6252 01:34:27.708334 ==
6253 01:34:27.708702 DQS Delay:
6254 01:34:27.711047 DQS0 = 43, DQS1 = 59
6255 01:34:27.711510 DQM Delay:
6256 01:34:27.714348 DQM0 = 7, DQM1 = 15
6257 01:34:27.714809 DQ Delay:
6258 01:34:27.717807 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6259 01:34:27.721082 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6260 01:34:27.724544 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6261 01:34:27.727572 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6262 01:34:27.728125
6263 01:34:27.728495
6264 01:34:27.728832 ==
6265 01:34:27.731076 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 01:34:27.734247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 01:34:27.734809 ==
6268 01:34:27.735183
6269 01:34:27.735522
6270 01:34:27.737642 TX Vref Scan disable
6271 01:34:27.738197 == TX Byte 0 ==
6272 01:34:27.744115 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6273 01:34:27.747200 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6274 01:34:27.747685 == TX Byte 1 ==
6275 01:34:27.754179 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6276 01:34:27.757252 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6277 01:34:27.757751 ==
6278 01:34:27.761000 Dram Type= 6, Freq= 0, CH_0, rank 1
6279 01:34:27.763623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6280 01:34:27.764086 ==
6281 01:34:27.764453
6282 01:34:27.764791
6283 01:34:27.767132 TX Vref Scan disable
6284 01:34:27.770350 == TX Byte 0 ==
6285 01:34:27.773696 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6286 01:34:27.777134 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6287 01:34:27.777739 == TX Byte 1 ==
6288 01:34:27.783791 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6289 01:34:27.787015 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6290 01:34:27.787565
6291 01:34:27.787932 [DATLAT]
6292 01:34:27.790224 Freq=400, CH0 RK1
6293 01:34:27.790682
6294 01:34:27.791045 DATLAT Default: 0xd
6295 01:34:27.793539 0, 0xFFFF, sum = 0
6296 01:34:27.794004 1, 0xFFFF, sum = 0
6297 01:34:27.796871 2, 0xFFFF, sum = 0
6298 01:34:27.797370 3, 0xFFFF, sum = 0
6299 01:34:27.799984 4, 0xFFFF, sum = 0
6300 01:34:27.803404 5, 0xFFFF, sum = 0
6301 01:34:27.803871 6, 0xFFFF, sum = 0
6302 01:34:27.806646 7, 0xFFFF, sum = 0
6303 01:34:27.807108 8, 0xFFFF, sum = 0
6304 01:34:27.810072 9, 0xFFFF, sum = 0
6305 01:34:27.810537 10, 0xFFFF, sum = 0
6306 01:34:27.813328 11, 0xFFFF, sum = 0
6307 01:34:27.813796 12, 0x0, sum = 1
6308 01:34:27.816794 13, 0x0, sum = 2
6309 01:34:27.817122 14, 0x0, sum = 3
6310 01:34:27.820326 15, 0x0, sum = 4
6311 01:34:27.820879 best_step = 13
6312 01:34:27.821207
6313 01:34:27.821500 ==
6314 01:34:27.823389 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 01:34:27.826661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6316 01:34:27.827127 ==
6317 01:34:27.830301 RX Vref Scan: 0
6318 01:34:27.830847
6319 01:34:27.833279 RX Vref 0 -> 0, step: 1
6320 01:34:27.833867
6321 01:34:27.836843 RX Delay -359 -> 252, step: 8
6322 01:34:27.842866 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6323 01:34:27.845987 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6324 01:34:27.849406 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6325 01:34:27.852810 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6326 01:34:27.859307 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6327 01:34:27.862839 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6328 01:34:27.865930 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6329 01:34:27.869182 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6330 01:34:27.876005 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6331 01:34:27.879143 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6332 01:34:27.882692 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6333 01:34:27.885933 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6334 01:34:27.892330 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6335 01:34:27.895858 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6336 01:34:27.899158 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6337 01:34:27.902371 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6338 01:34:27.905782 ==
6339 01:34:27.908799 Dram Type= 6, Freq= 0, CH_0, rank 1
6340 01:34:27.912205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6341 01:34:27.912622 ==
6342 01:34:27.912952 DQS Delay:
6343 01:34:27.915470 DQS0 = 52, DQS1 = 60
6344 01:34:27.915884 DQM Delay:
6345 01:34:27.918724 DQM0 = 10, DQM1 = 9
6346 01:34:27.919141 DQ Delay:
6347 01:34:27.922177 DQ0 =4, DQ1 =16, DQ2 =8, DQ3 =4
6348 01:34:27.925256 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6349 01:34:27.928944 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6350 01:34:27.931911 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6351 01:34:27.932326
6352 01:34:27.932654
6353 01:34:27.938653 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6354 01:34:27.941776 CH0 RK1: MR19=C0C, MR18=BABA
6355 01:34:27.948431 CH0_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6356 01:34:27.951939 [RxdqsGatingPostProcess] freq 400
6357 01:34:27.955159 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6358 01:34:27.958160 Pre-setting of DQS Precalculation
6359 01:34:27.964903 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6360 01:34:27.965480 ==
6361 01:34:27.968362 Dram Type= 6, Freq= 0, CH_1, rank 0
6362 01:34:27.971674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6363 01:34:27.972096 ==
6364 01:34:27.978264 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6365 01:34:27.984764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6366 01:34:27.988198 [CA 0] Center 36 (8~64) winsize 57
6367 01:34:27.991498 [CA 1] Center 36 (8~64) winsize 57
6368 01:34:27.994664 [CA 2] Center 36 (8~64) winsize 57
6369 01:34:27.998210 [CA 3] Center 36 (8~64) winsize 57
6370 01:34:27.998720 [CA 4] Center 36 (8~64) winsize 57
6371 01:34:28.001324 [CA 5] Center 36 (8~64) winsize 57
6372 01:34:28.001761
6373 01:34:28.008166 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6374 01:34:28.008587
6375 01:34:28.011166 [CATrainingPosCal] consider 1 rank data
6376 01:34:28.014559 u2DelayCellTimex100 = 270/100 ps
6377 01:34:28.017759 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 01:34:28.021253 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 01:34:28.024488 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6380 01:34:28.028016 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 01:34:28.031339 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 01:34:28.034256 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 01:34:28.034816
6384 01:34:28.037863 CA PerBit enable=1, Macro0, CA PI delay=36
6385 01:34:28.038424
6386 01:34:28.040950 [CBTSetCACLKResult] CA Dly = 36
6387 01:34:28.044318 CS Dly: 1 (0~32)
6388 01:34:28.044915 ==
6389 01:34:28.047780 Dram Type= 6, Freq= 0, CH_1, rank 1
6390 01:34:28.050778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6391 01:34:28.051239 ==
6392 01:34:28.057482 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6393 01:34:28.064321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6394 01:34:28.067387 [CA 0] Center 36 (8~64) winsize 57
6395 01:34:28.068066 [CA 1] Center 36 (8~64) winsize 57
6396 01:34:28.070738 [CA 2] Center 36 (8~64) winsize 57
6397 01:34:28.074002 [CA 3] Center 36 (8~64) winsize 57
6398 01:34:28.077224 [CA 4] Center 36 (8~64) winsize 57
6399 01:34:28.080470 [CA 5] Center 36 (8~64) winsize 57
6400 01:34:28.080929
6401 01:34:28.083735 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6402 01:34:28.084196
6403 01:34:28.090663 [CATrainingPosCal] consider 2 rank data
6404 01:34:28.091338 u2DelayCellTimex100 = 270/100 ps
6405 01:34:28.097282 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 01:34:28.100570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 01:34:28.103986 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 01:34:28.107036 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 01:34:28.110403 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 01:34:28.114067 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 01:34:28.114620
6412 01:34:28.116948 CA PerBit enable=1, Macro0, CA PI delay=36
6413 01:34:28.117729
6414 01:34:28.120074 [CBTSetCACLKResult] CA Dly = 36
6415 01:34:28.123281 CS Dly: 1 (0~32)
6416 01:34:28.123742
6417 01:34:28.126868 ----->DramcWriteLeveling(PI) begin...
6418 01:34:28.127428 ==
6419 01:34:28.130077 Dram Type= 6, Freq= 0, CH_1, rank 0
6420 01:34:28.133500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6421 01:34:28.134200 ==
6422 01:34:28.136793 Write leveling (Byte 0): 32 => 0
6423 01:34:28.140053 Write leveling (Byte 1): 32 => 0
6424 01:34:28.143204 DramcWriteLeveling(PI) end<-----
6425 01:34:28.143663
6426 01:34:28.144026 ==
6427 01:34:28.146423 Dram Type= 6, Freq= 0, CH_1, rank 0
6428 01:34:28.150099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6429 01:34:28.150613 ==
6430 01:34:28.153220 [Gating] SW mode calibration
6431 01:34:28.159974 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 01:34:28.166407 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6433 01:34:28.169853 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 01:34:28.173129 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 01:34:28.179948 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 01:34:28.183025 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6437 01:34:28.186308 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 01:34:28.192686 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 01:34:28.196250 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 01:34:28.199707 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6441 01:34:28.206117 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 01:34:28.206990 Total UI for P1: 0, mck2ui 16
6443 01:34:28.213129 best dqsien dly found for B0: ( 0, 10, 16)
6444 01:34:28.213760 Total UI for P1: 0, mck2ui 16
6445 01:34:28.219269 best dqsien dly found for B1: ( 0, 10, 16)
6446 01:34:28.222408 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6447 01:34:28.225952 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6448 01:34:28.226507
6449 01:34:28.229107 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6450 01:34:28.232328 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6451 01:34:28.236034 [Gating] SW calibration Done
6452 01:34:28.236585 ==
6453 01:34:28.239170 Dram Type= 6, Freq= 0, CH_1, rank 0
6454 01:34:28.242300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6455 01:34:28.242766 ==
6456 01:34:28.245871 RX Vref Scan: 0
6457 01:34:28.246330
6458 01:34:28.249097 RX Vref 0 -> 0, step: 1
6459 01:34:28.249795
6460 01:34:28.250190 RX Delay -410 -> 252, step: 16
6461 01:34:28.255714 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6462 01:34:28.258823 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6463 01:34:28.262148 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6464 01:34:28.269093 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6465 01:34:28.272405 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6466 01:34:28.275728 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6467 01:34:28.278656 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6468 01:34:28.285460 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6469 01:34:28.288853 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6470 01:34:28.292409 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6471 01:34:28.295108 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6472 01:34:28.301763 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6473 01:34:28.304867 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6474 01:34:28.308847 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6475 01:34:28.311722 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6476 01:34:28.318218 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6477 01:34:28.318680 ==
6478 01:34:28.321702 Dram Type= 6, Freq= 0, CH_1, rank 0
6479 01:34:28.324925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6480 01:34:28.325518 ==
6481 01:34:28.325896 DQS Delay:
6482 01:34:28.328366 DQS0 = 43, DQS1 = 59
6483 01:34:28.328912 DQM Delay:
6484 01:34:28.331578 DQM0 = 6, DQM1 = 15
6485 01:34:28.332135 DQ Delay:
6486 01:34:28.335152 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6487 01:34:28.338339 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6488 01:34:28.341411 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6489 01:34:28.344869 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6490 01:34:28.345469
6491 01:34:28.345846
6492 01:34:28.346188 ==
6493 01:34:28.348135 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 01:34:28.351168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 01:34:28.351635 ==
6496 01:34:28.352006
6497 01:34:28.354779
6498 01:34:28.355334 TX Vref Scan disable
6499 01:34:28.358103 == TX Byte 0 ==
6500 01:34:28.361421 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6501 01:34:28.364900 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6502 01:34:28.368073 == TX Byte 1 ==
6503 01:34:28.371082 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 01:34:28.374480 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 01:34:28.375040 ==
6506 01:34:28.378147 Dram Type= 6, Freq= 0, CH_1, rank 0
6507 01:34:28.384626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6508 01:34:28.385187 ==
6509 01:34:28.385617
6510 01:34:28.385956
6511 01:34:28.386282 TX Vref Scan disable
6512 01:34:28.387623 == TX Byte 0 ==
6513 01:34:28.390802 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6514 01:34:28.394181 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6515 01:34:28.397835 == TX Byte 1 ==
6516 01:34:28.400891 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6517 01:34:28.404392 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6518 01:34:28.404957
6519 01:34:28.407786 [DATLAT]
6520 01:34:28.408346 Freq=400, CH1 RK0
6521 01:34:28.408721
6522 01:34:28.411033 DATLAT Default: 0xf
6523 01:34:28.411597 0, 0xFFFF, sum = 0
6524 01:34:28.414184 1, 0xFFFF, sum = 0
6525 01:34:28.414759 2, 0xFFFF, sum = 0
6526 01:34:28.417467 3, 0xFFFF, sum = 0
6527 01:34:28.417935 4, 0xFFFF, sum = 0
6528 01:34:28.420988 5, 0xFFFF, sum = 0
6529 01:34:28.421488 6, 0xFFFF, sum = 0
6530 01:34:28.424203 7, 0xFFFF, sum = 0
6531 01:34:28.424776 8, 0xFFFF, sum = 0
6532 01:34:28.427540 9, 0xFFFF, sum = 0
6533 01:34:28.430606 10, 0xFFFF, sum = 0
6534 01:34:28.431179 11, 0xFFFF, sum = 0
6535 01:34:28.434383 12, 0x0, sum = 1
6536 01:34:28.434956 13, 0x0, sum = 2
6537 01:34:28.437473 14, 0x0, sum = 3
6538 01:34:28.437939 15, 0x0, sum = 4
6539 01:34:28.438315 best_step = 13
6540 01:34:28.438654
6541 01:34:28.440485 ==
6542 01:34:28.443954 Dram Type= 6, Freq= 0, CH_1, rank 0
6543 01:34:28.447299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6544 01:34:28.447761 ==
6545 01:34:28.448133 RX Vref Scan: 1
6546 01:34:28.448474
6547 01:34:28.450213 RX Vref 0 -> 0, step: 1
6548 01:34:28.450677
6549 01:34:28.453440 RX Delay -359 -> 252, step: 8
6550 01:34:28.453901
6551 01:34:28.457085 Set Vref, RX VrefLevel [Byte0]: 57
6552 01:34:28.460144 [Byte1]: 50
6553 01:34:28.464453
6554 01:34:28.465020 Final RX Vref Byte 0 = 57 to rank0
6555 01:34:28.467499 Final RX Vref Byte 1 = 50 to rank0
6556 01:34:28.470915 Final RX Vref Byte 0 = 57 to rank1
6557 01:34:28.474163 Final RX Vref Byte 1 = 50 to rank1==
6558 01:34:28.477723 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 01:34:28.484075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 01:34:28.484625 ==
6561 01:34:28.484996 DQS Delay:
6562 01:34:28.487357 DQS0 = 52, DQS1 = 64
6563 01:34:28.487910 DQM Delay:
6564 01:34:28.488276 DQM0 = 10, DQM1 = 16
6565 01:34:28.490624 DQ Delay:
6566 01:34:28.493829 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6567 01:34:28.497191 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6568 01:34:28.497770 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6569 01:34:28.500642 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =28
6570 01:34:28.503721
6571 01:34:28.504267
6572 01:34:28.510576 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6573 01:34:28.513853 CH1 RK0: MR19=C0C, MR18=D0D0
6574 01:34:28.520845 CH1_RK0: MR19=0xC0C, MR18=0xD0D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6575 01:34:28.521448 ==
6576 01:34:28.523821 Dram Type= 6, Freq= 0, CH_1, rank 1
6577 01:34:28.526862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6578 01:34:28.527326 ==
6579 01:34:28.530106 [Gating] SW mode calibration
6580 01:34:28.536765 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6581 01:34:28.543869 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6582 01:34:28.547207 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6583 01:34:28.550240 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6584 01:34:28.556804 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6585 01:34:28.560723 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6586 01:34:28.563844 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6587 01:34:28.570253 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6588 01:34:28.573637 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6589 01:34:28.576955 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6590 01:34:28.580397 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6591 01:34:28.584016 Total UI for P1: 0, mck2ui 16
6592 01:34:28.586791 best dqsien dly found for B0: ( 0, 10, 16)
6593 01:34:28.590229 Total UI for P1: 0, mck2ui 16
6594 01:34:28.593892 best dqsien dly found for B1: ( 0, 10, 16)
6595 01:34:28.596752 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6596 01:34:28.603538 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6597 01:34:28.604084
6598 01:34:28.606534 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6599 01:34:28.610080 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6600 01:34:28.613462 [Gating] SW calibration Done
6601 01:34:28.614016 ==
6602 01:34:28.616567 Dram Type= 6, Freq= 0, CH_1, rank 1
6603 01:34:28.620054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 01:34:28.620610 ==
6605 01:34:28.623411 RX Vref Scan: 0
6606 01:34:28.623968
6607 01:34:28.624340 RX Vref 0 -> 0, step: 1
6608 01:34:28.624685
6609 01:34:28.626532 RX Delay -410 -> 252, step: 16
6610 01:34:28.633648 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6611 01:34:28.636530 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6612 01:34:28.639722 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6613 01:34:28.643128 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6614 01:34:28.649995 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6615 01:34:28.653055 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6616 01:34:28.656414 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6617 01:34:28.659777 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6618 01:34:28.665947 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6619 01:34:28.669649 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6620 01:34:28.672917 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6621 01:34:28.675953 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6622 01:34:28.682439 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6623 01:34:28.686029 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6624 01:34:28.689362 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6625 01:34:28.692668 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6626 01:34:28.695805 ==
6627 01:34:28.699335 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 01:34:28.702576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6629 01:34:28.703128 ==
6630 01:34:28.703500 DQS Delay:
6631 01:34:28.706082 DQS0 = 43, DQS1 = 59
6632 01:34:28.706637 DQM Delay:
6633 01:34:28.709242 DQM0 = 10, DQM1 = 17
6634 01:34:28.709831 DQ Delay:
6635 01:34:28.712321 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6636 01:34:28.715766 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6637 01:34:28.719057 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6638 01:34:28.722231 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6639 01:34:28.722692
6640 01:34:28.723059
6641 01:34:28.723396 ==
6642 01:34:28.725497 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 01:34:28.728900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 01:34:28.729494 ==
6645 01:34:28.729871
6646 01:34:28.730211
6647 01:34:28.732377 TX Vref Scan disable
6648 01:34:28.732920 == TX Byte 0 ==
6649 01:34:28.738919 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6650 01:34:28.742168 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6651 01:34:28.742630 == TX Byte 1 ==
6652 01:34:28.748658 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6653 01:34:28.752146 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6654 01:34:28.752696 ==
6655 01:34:28.755764 Dram Type= 6, Freq= 0, CH_1, rank 1
6656 01:34:28.758599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6657 01:34:28.759084 ==
6658 01:34:28.759453
6659 01:34:28.759789
6660 01:34:28.761863 TX Vref Scan disable
6661 01:34:28.762320 == TX Byte 0 ==
6662 01:34:28.768717 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6663 01:34:28.771961 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6664 01:34:28.772519 == TX Byte 1 ==
6665 01:34:28.778403 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6666 01:34:28.781868 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6667 01:34:28.782332
6668 01:34:28.782788 [DATLAT]
6669 01:34:28.785443 Freq=400, CH1 RK1
6670 01:34:28.785995
6671 01:34:28.786365 DATLAT Default: 0xd
6672 01:34:28.788651 0, 0xFFFF, sum = 0
6673 01:34:28.789209 1, 0xFFFF, sum = 0
6674 01:34:28.792045 2, 0xFFFF, sum = 0
6675 01:34:28.792605 3, 0xFFFF, sum = 0
6676 01:34:28.795231 4, 0xFFFF, sum = 0
6677 01:34:28.795701 5, 0xFFFF, sum = 0
6678 01:34:28.798435 6, 0xFFFF, sum = 0
6679 01:34:28.798992 7, 0xFFFF, sum = 0
6680 01:34:28.801659 8, 0xFFFF, sum = 0
6681 01:34:28.802129 9, 0xFFFF, sum = 0
6682 01:34:28.805434 10, 0xFFFF, sum = 0
6683 01:34:28.808393 11, 0xFFFF, sum = 0
6684 01:34:28.808860 12, 0x0, sum = 1
6685 01:34:28.809233 13, 0x0, sum = 2
6686 01:34:28.811978 14, 0x0, sum = 3
6687 01:34:28.812544 15, 0x0, sum = 4
6688 01:34:28.814831 best_step = 13
6689 01:34:28.815292
6690 01:34:28.815661 ==
6691 01:34:28.818217 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 01:34:28.821710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6693 01:34:28.822265 ==
6694 01:34:28.825137 RX Vref Scan: 0
6695 01:34:28.825731
6696 01:34:28.826101 RX Vref 0 -> 0, step: 1
6697 01:34:28.828482
6698 01:34:28.829030 RX Delay -359 -> 252, step: 8
6699 01:34:28.836796 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6700 01:34:28.840053 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6701 01:34:28.843336 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6702 01:34:28.846704 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6703 01:34:28.853515 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6704 01:34:28.856409 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6705 01:34:28.859835 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6706 01:34:28.863116 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6707 01:34:28.869921 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6708 01:34:28.873219 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6709 01:34:28.876322 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6710 01:34:28.883220 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6711 01:34:28.886244 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6712 01:34:28.889644 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6713 01:34:28.893065 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6714 01:34:28.899541 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6715 01:34:28.900097 ==
6716 01:34:28.902787 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 01:34:28.906034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6718 01:34:28.906587 ==
6719 01:34:28.906953 DQS Delay:
6720 01:34:28.909190 DQS0 = 48, DQS1 = 64
6721 01:34:28.909680 DQM Delay:
6722 01:34:28.912374 DQM0 = 9, DQM1 = 15
6723 01:34:28.912832 DQ Delay:
6724 01:34:28.915718 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6725 01:34:28.919646 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6726 01:34:28.922459 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6727 01:34:28.925927 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6728 01:34:28.926388
6729 01:34:28.926749
6730 01:34:28.932521 [DQSOSCAuto] RK1, (LSB)MR18= 0x9d9d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6731 01:34:28.935902 CH1 RK1: MR19=C0C, MR18=9D9D
6732 01:34:28.942447 CH1_RK1: MR19=0xC0C, MR18=0x9D9D, DQSOSC=390, MR23=63, INC=388, DEC=258
6733 01:34:28.945959 [RxdqsGatingPostProcess] freq 400
6734 01:34:28.952244 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6735 01:34:28.955458 Pre-setting of DQS Precalculation
6736 01:34:28.958945 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6737 01:34:28.965692 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6738 01:34:28.972313 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6739 01:34:28.972864
6740 01:34:28.975797
6741 01:34:28.976376 [Calibration Summary] 800 Mbps
6742 01:34:28.979231 CH 0, Rank 0
6743 01:34:28.979770 SW Impedance : PASS
6744 01:34:28.982045 DUTY Scan : NO K
6745 01:34:28.985498 ZQ Calibration : PASS
6746 01:34:28.986045 Jitter Meter : NO K
6747 01:34:28.988900 CBT Training : PASS
6748 01:34:28.992160 Write leveling : PASS
6749 01:34:28.992713 RX DQS gating : PASS
6750 01:34:28.995232 RX DQ/DQS(RDDQC) : PASS
6751 01:34:28.998915 TX DQ/DQS : PASS
6752 01:34:28.999474 RX DATLAT : PASS
6753 01:34:29.001905 RX DQ/DQS(Engine): PASS
6754 01:34:29.005576 TX OE : NO K
6755 01:34:29.006129 All Pass.
6756 01:34:29.006500
6757 01:34:29.006837 CH 0, Rank 1
6758 01:34:29.009056 SW Impedance : PASS
6759 01:34:29.009662 DUTY Scan : NO K
6760 01:34:29.012205 ZQ Calibration : PASS
6761 01:34:29.015163 Jitter Meter : NO K
6762 01:34:29.015764 CBT Training : PASS
6763 01:34:29.018838 Write leveling : NO K
6764 01:34:29.021924 RX DQS gating : PASS
6765 01:34:29.022385 RX DQ/DQS(RDDQC) : PASS
6766 01:34:29.025506 TX DQ/DQS : PASS
6767 01:34:29.029118 RX DATLAT : PASS
6768 01:34:29.029705 RX DQ/DQS(Engine): PASS
6769 01:34:29.032285 TX OE : NO K
6770 01:34:29.032841 All Pass.
6771 01:34:29.033205
6772 01:34:29.035352 CH 1, Rank 0
6773 01:34:29.035911 SW Impedance : PASS
6774 01:34:29.038879 DUTY Scan : NO K
6775 01:34:29.042046 ZQ Calibration : PASS
6776 01:34:29.042595 Jitter Meter : NO K
6777 01:34:29.045311 CBT Training : PASS
6778 01:34:29.048537 Write leveling : PASS
6779 01:34:29.049087 RX DQS gating : PASS
6780 01:34:29.052100 RX DQ/DQS(RDDQC) : PASS
6781 01:34:29.055012 TX DQ/DQS : PASS
6782 01:34:29.055551 RX DATLAT : PASS
6783 01:34:29.058322 RX DQ/DQS(Engine): PASS
6784 01:34:29.061641 TX OE : NO K
6785 01:34:29.062199 All Pass.
6786 01:34:29.062570
6787 01:34:29.062914 CH 1, Rank 1
6788 01:34:29.064885 SW Impedance : PASS
6789 01:34:29.065386 DUTY Scan : NO K
6790 01:34:29.068364 ZQ Calibration : PASS
6791 01:34:29.071838 Jitter Meter : NO K
6792 01:34:29.072391 CBT Training : PASS
6793 01:34:29.075030 Write leveling : NO K
6794 01:34:29.078492 RX DQS gating : PASS
6795 01:34:29.079047 RX DQ/DQS(RDDQC) : PASS
6796 01:34:29.081534 TX DQ/DQS : PASS
6797 01:34:29.085039 RX DATLAT : PASS
6798 01:34:29.085644 RX DQ/DQS(Engine): PASS
6799 01:34:29.088327 TX OE : NO K
6800 01:34:29.088973 All Pass.
6801 01:34:29.089410
6802 01:34:29.091217 DramC Write-DBI off
6803 01:34:29.094536 PER_BANK_REFRESH: Hybrid Mode
6804 01:34:29.095038 TX_TRACKING: ON
6805 01:34:29.104702 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6806 01:34:29.108115 [FAST_K] Save calibration result to emmc
6807 01:34:29.111363 dramc_set_vcore_voltage set vcore to 725000
6808 01:34:29.114639 Read voltage for 1600, 0
6809 01:34:29.115187 Vio18 = 0
6810 01:34:29.117958 Vcore = 725000
6811 01:34:29.118548 Vdram = 0
6812 01:34:29.118935 Vddq = 0
6813 01:34:29.119278 Vmddr = 0
6814 01:34:29.124480 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6815 01:34:29.131012 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6816 01:34:29.131561 MEM_TYPE=3, freq_sel=13
6817 01:34:29.134511 sv_algorithm_assistance_LP4_3733
6818 01:34:29.137797 ============ PULL DRAM RESETB DOWN ============
6819 01:34:29.144335 ========== PULL DRAM RESETB DOWN end =========
6820 01:34:29.147547 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6821 01:34:29.151024 ===================================
6822 01:34:29.154116 LPDDR4 DRAM CONFIGURATION
6823 01:34:29.157413 ===================================
6824 01:34:29.157880 EX_ROW_EN[0] = 0x0
6825 01:34:29.161532 EX_ROW_EN[1] = 0x0
6826 01:34:29.162083 LP4Y_EN = 0x0
6827 01:34:29.163920 WORK_FSP = 0x1
6828 01:34:29.164379 WL = 0x5
6829 01:34:29.167117 RL = 0x5
6830 01:34:29.170837 BL = 0x2
6831 01:34:29.171387 RPST = 0x0
6832 01:34:29.173856 RD_PRE = 0x0
6833 01:34:29.174330 WR_PRE = 0x1
6834 01:34:29.177262 WR_PST = 0x1
6835 01:34:29.177776 DBI_WR = 0x0
6836 01:34:29.180740 DBI_RD = 0x0
6837 01:34:29.181330 OTF = 0x1
6838 01:34:29.183873 ===================================
6839 01:34:29.187303 ===================================
6840 01:34:29.190710 ANA top config
6841 01:34:29.193734 ===================================
6842 01:34:29.194201 DLL_ASYNC_EN = 0
6843 01:34:29.197462 ALL_SLAVE_EN = 0
6844 01:34:29.200801 NEW_RANK_MODE = 1
6845 01:34:29.203898 DLL_IDLE_MODE = 1
6846 01:34:29.204364 LP45_APHY_COMB_EN = 1
6847 01:34:29.207273 TX_ODT_DIS = 0
6848 01:34:29.210107 NEW_8X_MODE = 1
6849 01:34:29.213724 ===================================
6850 01:34:29.216948 ===================================
6851 01:34:29.220306 data_rate = 3200
6852 01:34:29.223316 CKR = 1
6853 01:34:29.226956 DQ_P2S_RATIO = 8
6854 01:34:29.230185 ===================================
6855 01:34:29.230779 CA_P2S_RATIO = 8
6856 01:34:29.233650 DQ_CA_OPEN = 0
6857 01:34:29.236913 DQ_SEMI_OPEN = 0
6858 01:34:29.240426 CA_SEMI_OPEN = 0
6859 01:34:29.243277 CA_FULL_RATE = 0
6860 01:34:29.246524 DQ_CKDIV4_EN = 0
6861 01:34:29.247075 CA_CKDIV4_EN = 0
6862 01:34:29.250679 CA_PREDIV_EN = 0
6863 01:34:29.253529 PH8_DLY = 12
6864 01:34:29.256743 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6865 01:34:29.259717 DQ_AAMCK_DIV = 4
6866 01:34:29.263563 CA_AAMCK_DIV = 4
6867 01:34:29.264123 CA_ADMCK_DIV = 4
6868 01:34:29.266350 DQ_TRACK_CA_EN = 0
6869 01:34:29.269964 CA_PICK = 1600
6870 01:34:29.273175 CA_MCKIO = 1600
6871 01:34:29.276405 MCKIO_SEMI = 0
6872 01:34:29.279793 PLL_FREQ = 3068
6873 01:34:29.282837 DQ_UI_PI_RATIO = 32
6874 01:34:29.286233 CA_UI_PI_RATIO = 0
6875 01:34:29.289796 ===================================
6876 01:34:29.290260 ===================================
6877 01:34:29.292808 memory_type:LPDDR4
6878 01:34:29.296215 GP_NUM : 10
6879 01:34:29.296675 SRAM_EN : 1
6880 01:34:29.299814 MD32_EN : 0
6881 01:34:29.302827 ===================================
6882 01:34:29.306314 [ANA_INIT] >>>>>>>>>>>>>>
6883 01:34:29.309495 <<<<<< [CONFIGURE PHASE]: ANA_TX
6884 01:34:29.313226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6885 01:34:29.316456 ===================================
6886 01:34:29.317041 data_rate = 3200,PCW = 0X7600
6887 01:34:29.319447 ===================================
6888 01:34:29.326470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6889 01:34:29.329505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6890 01:34:29.336441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6891 01:34:29.339493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6892 01:34:29.342845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6893 01:34:29.345836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6894 01:34:29.349179 [ANA_INIT] flow start
6895 01:34:29.352880 [ANA_INIT] PLL >>>>>>>>
6896 01:34:29.353484 [ANA_INIT] PLL <<<<<<<<
6897 01:34:29.355956 [ANA_INIT] MIDPI >>>>>>>>
6898 01:34:29.359103 [ANA_INIT] MIDPI <<<<<<<<
6899 01:34:29.359551 [ANA_INIT] DLL >>>>>>>>
6900 01:34:29.362702 [ANA_INIT] DLL <<<<<<<<
6901 01:34:29.365866 [ANA_INIT] flow end
6902 01:34:29.369034 ============ LP4 DIFF to SE enter ============
6903 01:34:29.372807 ============ LP4 DIFF to SE exit ============
6904 01:34:29.376163 [ANA_INIT] <<<<<<<<<<<<<
6905 01:34:29.379112 [Flow] Enable top DCM control >>>>>
6906 01:34:29.382564 [Flow] Enable top DCM control <<<<<
6907 01:34:29.385831 Enable DLL master slave shuffle
6908 01:34:29.389095 ==============================================================
6909 01:34:29.392311 Gating Mode config
6910 01:34:29.399353 ==============================================================
6911 01:34:29.399912 Config description:
6912 01:34:29.409002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6913 01:34:29.415440 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6914 01:34:29.421998 SELPH_MODE 0: By rank 1: By Phase
6915 01:34:29.425696 ==============================================================
6916 01:34:29.428705 GAT_TRACK_EN = 1
6917 01:34:29.431983 RX_GATING_MODE = 2
6918 01:34:29.435166 RX_GATING_TRACK_MODE = 2
6919 01:34:29.438465 SELPH_MODE = 1
6920 01:34:29.442029 PICG_EARLY_EN = 1
6921 01:34:29.445365 VALID_LAT_VALUE = 1
6922 01:34:29.448634 ==============================================================
6923 01:34:29.452013 Enter into Gating configuration >>>>
6924 01:34:29.455302 Exit from Gating configuration <<<<
6925 01:34:29.458455 Enter into DVFS_PRE_config >>>>>
6926 01:34:29.471872 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6927 01:34:29.475224 Exit from DVFS_PRE_config <<<<<
6928 01:34:29.478327 Enter into PICG configuration >>>>
6929 01:34:29.478789 Exit from PICG configuration <<<<
6930 01:34:29.481547 [RX_INPUT] configuration >>>>>
6931 01:34:29.484744 [RX_INPUT] configuration <<<<<
6932 01:34:29.491501 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6933 01:34:29.494666 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6934 01:34:29.501460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6935 01:34:29.508407 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6936 01:34:29.514941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6937 01:34:29.521138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6938 01:34:29.524800 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6939 01:34:29.528001 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6940 01:34:29.534685 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6941 01:34:29.537914 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6942 01:34:29.541464 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6943 01:34:29.544764 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6944 01:34:29.547751 ===================================
6945 01:34:29.551378 LPDDR4 DRAM CONFIGURATION
6946 01:34:29.554491 ===================================
6947 01:34:29.557476 EX_ROW_EN[0] = 0x0
6948 01:34:29.558068 EX_ROW_EN[1] = 0x0
6949 01:34:29.561072 LP4Y_EN = 0x0
6950 01:34:29.561596 WORK_FSP = 0x1
6951 01:34:29.564644 WL = 0x5
6952 01:34:29.565193 RL = 0x5
6953 01:34:29.567808 BL = 0x2
6954 01:34:29.568382 RPST = 0x0
6955 01:34:29.570998 RD_PRE = 0x0
6956 01:34:29.571463 WR_PRE = 0x1
6957 01:34:29.574203 WR_PST = 0x1
6958 01:34:29.577679 DBI_WR = 0x0
6959 01:34:29.578227 DBI_RD = 0x0
6960 01:34:29.580924 OTF = 0x1
6961 01:34:29.584235 ===================================
6962 01:34:29.587354 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6963 01:34:29.590926 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6964 01:34:29.594185 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6965 01:34:29.597482 ===================================
6966 01:34:29.600682 LPDDR4 DRAM CONFIGURATION
6967 01:34:29.603926 ===================================
6968 01:34:29.607323 EX_ROW_EN[0] = 0x10
6969 01:34:29.607878 EX_ROW_EN[1] = 0x0
6970 01:34:29.610444 LP4Y_EN = 0x0
6971 01:34:29.610903 WORK_FSP = 0x1
6972 01:34:29.614072 WL = 0x5
6973 01:34:29.614627 RL = 0x5
6974 01:34:29.617433 BL = 0x2
6975 01:34:29.618000 RPST = 0x0
6976 01:34:29.620545 RD_PRE = 0x0
6977 01:34:29.621006 WR_PRE = 0x1
6978 01:34:29.624122 WR_PST = 0x1
6979 01:34:29.627351 DBI_WR = 0x0
6980 01:34:29.627916 DBI_RD = 0x0
6981 01:34:29.630501 OTF = 0x1
6982 01:34:29.633844 ===================================
6983 01:34:29.637347 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6984 01:34:29.640361 ==
6985 01:34:29.640915 Dram Type= 6, Freq= 0, CH_0, rank 0
6986 01:34:29.646856 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6987 01:34:29.647418 ==
6988 01:34:29.650297 [Duty_Offset_Calibration]
6989 01:34:29.650848 B0:0 B1:2 CA:1
6990 01:34:29.651215
6991 01:34:29.653535 [DutyScan_Calibration_Flow] k_type=0
6992 01:34:29.663664
6993 01:34:29.664212 ==CLK 0==
6994 01:34:29.666707 Final CLK duty delay cell = 0
6995 01:34:29.670222 [0] MAX Duty = 5187%(X100), DQS PI = 24
6996 01:34:29.673336 [0] MIN Duty = 4938%(X100), DQS PI = 52
6997 01:34:29.676739 [0] AVG Duty = 5062%(X100)
6998 01:34:29.677329
6999 01:34:29.679960 CH0 CLK Duty spec in!! Max-Min= 249%
7000 01:34:29.683389 [DutyScan_Calibration_Flow] ====Done====
7001 01:34:29.683852
7002 01:34:29.686576 [DutyScan_Calibration_Flow] k_type=1
7003 01:34:29.703428
7004 01:34:29.703983 ==DQS 0 ==
7005 01:34:29.706718 Final DQS duty delay cell = 0
7006 01:34:29.709929 [0] MAX Duty = 5125%(X100), DQS PI = 2
7007 01:34:29.713002 [0] MIN Duty = 5031%(X100), DQS PI = 10
7008 01:34:29.716743 [0] AVG Duty = 5078%(X100)
7009 01:34:29.717323
7010 01:34:29.717698 ==DQS 1 ==
7011 01:34:29.719737 Final DQS duty delay cell = 0
7012 01:34:29.723450 [0] MAX Duty = 5031%(X100), DQS PI = 6
7013 01:34:29.726507 [0] MIN Duty = 4876%(X100), DQS PI = 16
7014 01:34:29.729786 [0] AVG Duty = 4953%(X100)
7015 01:34:29.730249
7016 01:34:29.733071 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7017 01:34:29.733664
7018 01:34:29.736427 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7019 01:34:29.739630 [DutyScan_Calibration_Flow] ====Done====
7020 01:34:29.740150
7021 01:34:29.742936 [DutyScan_Calibration_Flow] k_type=3
7022 01:34:29.760488
7023 01:34:29.761030 ==DQM 0 ==
7024 01:34:29.763815 Final DQM duty delay cell = 0
7025 01:34:29.767246 [0] MAX Duty = 5187%(X100), DQS PI = 22
7026 01:34:29.770234 [0] MIN Duty = 4907%(X100), DQS PI = 44
7027 01:34:29.773925 [0] AVG Duty = 5047%(X100)
7028 01:34:29.774477
7029 01:34:29.774843 ==DQM 1 ==
7030 01:34:29.777096 Final DQM duty delay cell = 0
7031 01:34:29.780112 [0] MAX Duty = 5031%(X100), DQS PI = 52
7032 01:34:29.783531 [0] MIN Duty = 4782%(X100), DQS PI = 12
7033 01:34:29.786793 [0] AVG Duty = 4906%(X100)
7034 01:34:29.787354
7035 01:34:29.790082 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7036 01:34:29.790639
7037 01:34:29.793528 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7038 01:34:29.796683 [DutyScan_Calibration_Flow] ====Done====
7039 01:34:29.797277
7040 01:34:29.800063 [DutyScan_Calibration_Flow] k_type=2
7041 01:34:29.816989
7042 01:34:29.817673 ==DQ 0 ==
7043 01:34:29.820003 Final DQ duty delay cell = 0
7044 01:34:29.823560 [0] MAX Duty = 5218%(X100), DQS PI = 18
7045 01:34:29.826762 [0] MIN Duty = 4938%(X100), DQS PI = 56
7046 01:34:29.827228 [0] AVG Duty = 5078%(X100)
7047 01:34:29.830119
7048 01:34:29.830664 ==DQ 1 ==
7049 01:34:29.833134 Final DQ duty delay cell = -4
7050 01:34:29.836802 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7051 01:34:29.839779 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7052 01:34:29.843244 [-4] AVG Duty = 4953%(X100)
7053 01:34:29.843792
7054 01:34:29.846764 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7055 01:34:29.847319
7056 01:34:29.849919 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7057 01:34:29.853261 [DutyScan_Calibration_Flow] ====Done====
7058 01:34:29.853846 ==
7059 01:34:29.856576 Dram Type= 6, Freq= 0, CH_1, rank 0
7060 01:34:29.859846 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7061 01:34:29.860317 ==
7062 01:34:29.863290 [Duty_Offset_Calibration]
7063 01:34:29.863749 B0:0 B1:4 CA:-5
7064 01:34:29.864116
7065 01:34:29.866293 [DutyScan_Calibration_Flow] k_type=0
7066 01:34:29.877580
7067 01:34:29.878127 ==CLK 0==
7068 01:34:29.880928 Final CLK duty delay cell = 0
7069 01:34:29.883957 [0] MAX Duty = 5156%(X100), DQS PI = 22
7070 01:34:29.887220 [0] MIN Duty = 4906%(X100), DQS PI = 50
7071 01:34:29.890569 [0] AVG Duty = 5031%(X100)
7072 01:34:29.891119
7073 01:34:29.893902 CH1 CLK Duty spec in!! Max-Min= 250%
7074 01:34:29.897136 [DutyScan_Calibration_Flow] ====Done====
7075 01:34:29.897726
7076 01:34:29.900251 [DutyScan_Calibration_Flow] k_type=1
7077 01:34:29.916586
7078 01:34:29.917150 ==DQS 0 ==
7079 01:34:29.919524 Final DQS duty delay cell = 0
7080 01:34:29.922700 [0] MAX Duty = 5156%(X100), DQS PI = 18
7081 01:34:29.926265 [0] MIN Duty = 4876%(X100), DQS PI = 42
7082 01:34:29.929555 [0] AVG Duty = 5016%(X100)
7083 01:34:29.930112
7084 01:34:29.930476 ==DQS 1 ==
7085 01:34:29.933182 Final DQS duty delay cell = -4
7086 01:34:29.936114 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7087 01:34:29.939454 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7088 01:34:29.942976 [-4] AVG Duty = 4922%(X100)
7089 01:34:29.943534
7090 01:34:29.946255 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7091 01:34:29.946805
7092 01:34:29.949248 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7093 01:34:29.952968 [DutyScan_Calibration_Flow] ====Done====
7094 01:34:29.953563
7095 01:34:29.956035 [DutyScan_Calibration_Flow] k_type=3
7096 01:34:29.972063
7097 01:34:29.972614 ==DQM 0 ==
7098 01:34:29.975494 Final DQM duty delay cell = -4
7099 01:34:29.978464 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7100 01:34:29.982209 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7101 01:34:29.985255 [-4] AVG Duty = 4922%(X100)
7102 01:34:29.985745
7103 01:34:29.986194 ==DQM 1 ==
7104 01:34:29.988714 Final DQM duty delay cell = -4
7105 01:34:29.992182 [-4] MAX Duty = 5093%(X100), DQS PI = 18
7106 01:34:29.995428 [-4] MIN Duty = 4875%(X100), DQS PI = 40
7107 01:34:29.998310 [-4] AVG Duty = 4984%(X100)
7108 01:34:29.998768
7109 01:34:30.001922 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7110 01:34:30.002472
7111 01:34:30.005034 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7112 01:34:30.008493 [DutyScan_Calibration_Flow] ====Done====
7113 01:34:30.009044
7114 01:34:30.011336 [DutyScan_Calibration_Flow] k_type=2
7115 01:34:30.029791
7116 01:34:30.030335 ==DQ 0 ==
7117 01:34:30.033084 Final DQ duty delay cell = 0
7118 01:34:30.036209 [0] MAX Duty = 5093%(X100), DQS PI = 4
7119 01:34:30.039393 [0] MIN Duty = 4938%(X100), DQS PI = 48
7120 01:34:30.039856 [0] AVG Duty = 5015%(X100)
7121 01:34:30.042790
7122 01:34:30.043334 ==DQ 1 ==
7123 01:34:30.046199 Final DQ duty delay cell = 0
7124 01:34:30.049262 [0] MAX Duty = 5031%(X100), DQS PI = 4
7125 01:34:30.052857 [0] MIN Duty = 4876%(X100), DQS PI = 28
7126 01:34:30.053452 [0] AVG Duty = 4953%(X100)
7127 01:34:30.053831
7128 01:34:30.056208 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7129 01:34:30.059118
7130 01:34:30.062626 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7131 01:34:30.065750 [DutyScan_Calibration_Flow] ====Done====
7132 01:34:30.069130 nWR fixed to 30
7133 01:34:30.069629 [ModeRegInit_LP4] CH0 RK0
7134 01:34:30.072932 [ModeRegInit_LP4] CH0 RK1
7135 01:34:30.076340 [ModeRegInit_LP4] CH1 RK0
7136 01:34:30.079059 [ModeRegInit_LP4] CH1 RK1
7137 01:34:30.079518 match AC timing 4
7138 01:34:30.085766 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7139 01:34:30.089064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7140 01:34:30.092468 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7141 01:34:30.098923 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7142 01:34:30.102443 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7143 01:34:30.103005 [MiockJmeterHQA]
7144 01:34:30.103371
7145 01:34:30.105553 [DramcMiockJmeter] u1RxGatingPI = 0
7146 01:34:30.109170 0 : 4363, 4137
7147 01:34:30.109806 4 : 4253, 4027
7148 01:34:30.112270 8 : 4252, 4027
7149 01:34:30.112828 12 : 4252, 4027
7150 01:34:30.113197 16 : 4253, 4026
7151 01:34:30.115792 20 : 4252, 4027
7152 01:34:30.116357 24 : 4362, 4137
7153 01:34:30.118547 28 : 4363, 4137
7154 01:34:30.119044 32 : 4252, 4027
7155 01:34:30.121864 36 : 4253, 4027
7156 01:34:30.122329 40 : 4252, 4027
7157 01:34:30.125460 44 : 4360, 4137
7158 01:34:30.125929 48 : 4253, 4027
7159 01:34:30.126300 52 : 4361, 4138
7160 01:34:30.128454 56 : 4253, 4026
7161 01:34:30.128920 60 : 4249, 4027
7162 01:34:30.132338 64 : 4252, 4027
7163 01:34:30.132947 68 : 4253, 4029
7164 01:34:30.135300 72 : 4250, 4027
7165 01:34:30.135862 76 : 4253, 4026
7166 01:34:30.138543 80 : 4363, 4140
7167 01:34:30.139012 84 : 4252, 4027
7168 01:34:30.139387 88 : 4253, 4029
7169 01:34:30.142193 92 : 4250, 4027
7170 01:34:30.142768 96 : 4360, 4137
7171 01:34:30.145068 100 : 4250, 1289
7172 01:34:30.145571 104 : 4250, 0
7173 01:34:30.148369 108 : 4360, 0
7174 01:34:30.148833 112 : 4252, 0
7175 01:34:30.149208 116 : 4250, 0
7176 01:34:30.151688 120 : 4250, 0
7177 01:34:30.152156 124 : 4250, 0
7178 01:34:30.155186 128 : 4360, 0
7179 01:34:30.155746 132 : 4361, 0
7180 01:34:30.156124 136 : 4250, 0
7181 01:34:30.158336 140 : 4250, 0
7182 01:34:30.158800 144 : 4361, 0
7183 01:34:30.159170 148 : 4250, 0
7184 01:34:30.161597 152 : 4250, 0
7185 01:34:30.162066 156 : 4250, 0
7186 01:34:30.165194 160 : 4253, 0
7187 01:34:30.165705 164 : 4360, 0
7188 01:34:30.166075 168 : 4250, 0
7189 01:34:30.168379 172 : 4250, 0
7190 01:34:30.168847 176 : 4250, 0
7191 01:34:30.171808 180 : 4361, 0
7192 01:34:30.172442 184 : 4361, 0
7193 01:34:30.172825 188 : 4250, 0
7194 01:34:30.175171 192 : 4249, 0
7195 01:34:30.175736 196 : 4250, 0
7196 01:34:30.178687 200 : 4253, 0
7197 01:34:30.179267 204 : 4250, 0
7198 01:34:30.179644 208 : 4250, 0
7199 01:34:30.181491 212 : 4253, 0
7200 01:34:30.181963 216 : 4360, 0
7201 01:34:30.185036 220 : 4250, 544
7202 01:34:30.185608 224 : 4250, 4015
7203 01:34:30.186052 228 : 4250, 4027
7204 01:34:30.188439 232 : 4250, 4027
7205 01:34:30.188995 236 : 4360, 4138
7206 01:34:30.191742 240 : 4360, 4137
7207 01:34:30.192302 244 : 4247, 4025
7208 01:34:30.194924 248 : 4363, 4140
7209 01:34:30.195482 252 : 4250, 4027
7210 01:34:30.198404 256 : 4249, 4027
7211 01:34:30.198957 260 : 4250, 4026
7212 01:34:30.201746 264 : 4253, 4029
7213 01:34:30.202306 268 : 4250, 4027
7214 01:34:30.204852 272 : 4250, 4027
7215 01:34:30.205360 276 : 4250, 4026
7216 01:34:30.208634 280 : 4253, 4029
7217 01:34:30.209237 284 : 4250, 4027
7218 01:34:30.209670 288 : 4360, 4138
7219 01:34:30.211236 292 : 4360, 4137
7220 01:34:30.211706 296 : 4250, 4027
7221 01:34:30.215093 300 : 4363, 4140
7222 01:34:30.215688 304 : 4250, 4026
7223 01:34:30.218304 308 : 4250, 4027
7224 01:34:30.218863 312 : 4250, 4026
7225 01:34:30.221265 316 : 4253, 4029
7226 01:34:30.221783 320 : 4250, 4027
7227 01:34:30.224567 324 : 4249, 4027
7228 01:34:30.225132 328 : 4250, 4026
7229 01:34:30.227989 332 : 4253, 4029
7230 01:34:30.228545 336 : 4250, 3746
7231 01:34:30.230985 340 : 4360, 1640
7232 01:34:30.231452
7233 01:34:30.231817 MIOCK jitter meter ch=0
7234 01:34:30.232158
7235 01:34:30.234693 1T = (340-100) = 240 dly cells
7236 01:34:30.241237 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7237 01:34:30.241830 ==
7238 01:34:30.244369 Dram Type= 6, Freq= 0, CH_0, rank 0
7239 01:34:30.247813 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7240 01:34:30.248372 ==
7241 01:34:30.254428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7242 01:34:30.257599 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7243 01:34:30.264331 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7244 01:34:30.267207 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7245 01:34:30.276976 [CA 0] Center 42 (12~73) winsize 62
7246 01:34:30.280130 [CA 1] Center 42 (12~73) winsize 62
7247 01:34:30.283448 [CA 2] Center 39 (9~69) winsize 61
7248 01:34:30.286606 [CA 3] Center 38 (9~68) winsize 60
7249 01:34:30.290144 [CA 4] Center 37 (7~67) winsize 61
7250 01:34:30.293428 [CA 5] Center 36 (6~66) winsize 61
7251 01:34:30.293985
7252 01:34:30.296774 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7253 01:34:30.297390
7254 01:34:30.300121 [CATrainingPosCal] consider 1 rank data
7255 01:34:30.302957 u2DelayCellTimex100 = 271/100 ps
7256 01:34:30.310137 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7257 01:34:30.313373 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7258 01:34:30.316588 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7259 01:34:30.319894 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7260 01:34:30.323352 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7261 01:34:30.326381 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7262 01:34:30.326955
7263 01:34:30.329542 CA PerBit enable=1, Macro0, CA PI delay=36
7264 01:34:30.330005
7265 01:34:30.333175 [CBTSetCACLKResult] CA Dly = 36
7266 01:34:30.336775 CS Dly: 10 (0~41)
7267 01:34:30.339620 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7268 01:34:30.343493 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7269 01:34:30.344069 ==
7270 01:34:30.346349 Dram Type= 6, Freq= 0, CH_0, rank 1
7271 01:34:30.350456 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7272 01:34:30.352990 ==
7273 01:34:30.356494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7274 01:34:30.359789 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7275 01:34:30.365975 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7276 01:34:30.373040 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7277 01:34:30.379634 [CA 0] Center 42 (12~73) winsize 62
7278 01:34:30.382794 [CA 1] Center 41 (11~72) winsize 62
7279 01:34:30.385885 [CA 2] Center 38 (9~68) winsize 60
7280 01:34:30.389070 [CA 3] Center 37 (7~67) winsize 61
7281 01:34:30.392834 [CA 4] Center 35 (5~65) winsize 61
7282 01:34:30.396194 [CA 5] Center 35 (5~66) winsize 62
7283 01:34:30.396746
7284 01:34:30.399459 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7285 01:34:30.400007
7286 01:34:30.402537 [CATrainingPosCal] consider 2 rank data
7287 01:34:30.406084 u2DelayCellTimex100 = 271/100 ps
7288 01:34:30.412202 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7289 01:34:30.415824 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7290 01:34:30.419050 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7291 01:34:30.422451 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7292 01:34:30.425425 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7293 01:34:30.428902 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7294 01:34:30.429396
7295 01:34:30.432178 CA PerBit enable=1, Macro0, CA PI delay=36
7296 01:34:30.432631
7297 01:34:30.435429 [CBTSetCACLKResult] CA Dly = 36
7298 01:34:30.439024 CS Dly: 11 (0~43)
7299 01:34:30.442366 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7300 01:34:30.445496 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7301 01:34:30.445950
7302 01:34:30.448758 ----->DramcWriteLeveling(PI) begin...
7303 01:34:30.449213 ==
7304 01:34:30.452469 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 01:34:30.458632 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7306 01:34:30.459319 ==
7307 01:34:30.461977 Write leveling (Byte 0): 30 => 30
7308 01:34:30.465565 Write leveling (Byte 1): 26 => 26
7309 01:34:30.466104 DramcWriteLeveling(PI) end<-----
7310 01:34:30.466480
7311 01:34:30.468659 ==
7312 01:34:30.472461 Dram Type= 6, Freq= 0, CH_0, rank 0
7313 01:34:30.475385 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7314 01:34:30.475938 ==
7315 01:34:30.478349 [Gating] SW mode calibration
7316 01:34:30.485239 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7317 01:34:30.488371 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7318 01:34:30.495159 0 12 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7319 01:34:30.498209 0 12 4 | B1->B0 | 2424 3333 | 1 0 | (1 1) (0 0)
7320 01:34:30.501634 0 12 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7321 01:34:30.508323 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 01:34:30.511354 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7323 01:34:30.514886 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7324 01:34:30.521153 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 01:34:30.524519 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7326 01:34:30.528491 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
7327 01:34:30.534688 0 13 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
7328 01:34:30.537983 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7329 01:34:30.541187 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 01:34:30.547650 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7331 01:34:30.551017 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7332 01:34:30.554300 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7333 01:34:30.561076 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 01:34:30.564477 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7335 01:34:30.567913 0 14 4 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7336 01:34:30.574503 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 01:34:30.577867 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 01:34:30.581081 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7339 01:34:30.587474 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 01:34:30.590646 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 01:34:30.594217 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7342 01:34:30.600527 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7343 01:34:30.604247 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7344 01:34:30.607554 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7345 01:34:30.614127 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 01:34:30.617250 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 01:34:30.620455 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 01:34:30.627513 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 01:34:30.630597 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 01:34:30.634130 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 01:34:30.640256 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 01:34:30.643652 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 01:34:30.647049 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 01:34:30.653694 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 01:34:30.656802 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 01:34:30.660180 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 01:34:30.666996 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7358 01:34:30.670074 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7359 01:34:30.673251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7360 01:34:30.676597 Total UI for P1: 0, mck2ui 16
7361 01:34:30.680027 best dqsien dly found for B0: ( 1, 0, 30)
7362 01:34:30.686457 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7363 01:34:30.690097 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7364 01:34:30.693173 Total UI for P1: 0, mck2ui 16
7365 01:34:30.696308 best dqsien dly found for B1: ( 1, 1, 4)
7366 01:34:30.699536 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7367 01:34:30.702834 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7368 01:34:30.703295
7369 01:34:30.706148 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7370 01:34:30.709541 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7371 01:34:30.712522 [Gating] SW calibration Done
7372 01:34:30.712974 ==
7373 01:34:30.716315 Dram Type= 6, Freq= 0, CH_0, rank 0
7374 01:34:30.719616 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7375 01:34:30.722555 ==
7376 01:34:30.723018 RX Vref Scan: 0
7377 01:34:30.723387
7378 01:34:30.726087 RX Vref 0 -> 0, step: 1
7379 01:34:30.726635
7380 01:34:30.729710 RX Delay 0 -> 252, step: 8
7381 01:34:30.732829 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7382 01:34:30.735957 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7383 01:34:30.738954 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7384 01:34:30.742798 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7385 01:34:30.749617 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7386 01:34:30.752278 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7387 01:34:30.755660 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7388 01:34:30.759116 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7389 01:34:30.762189 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7390 01:34:30.769023 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7391 01:34:30.772146 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7392 01:34:30.775209 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7393 01:34:30.778495 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7394 01:34:30.781836 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7395 01:34:30.788976 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7396 01:34:30.792024 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7397 01:34:30.792577 ==
7398 01:34:30.795645 Dram Type= 6, Freq= 0, CH_0, rank 0
7399 01:34:30.798392 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7400 01:34:30.798878 ==
7401 01:34:30.801620 DQS Delay:
7402 01:34:30.802096 DQS0 = 0, DQS1 = 0
7403 01:34:30.805472 DQM Delay:
7404 01:34:30.806179 DQM0 = 130, DQM1 = 125
7405 01:34:30.806671 DQ Delay:
7406 01:34:30.808325 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7407 01:34:30.815208 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7408 01:34:30.818311 DQ8 =115, DQ9 =107, DQ10 =127, DQ11 =115
7409 01:34:30.821706 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7410 01:34:30.822269
7411 01:34:30.822760
7412 01:34:30.823216 ==
7413 01:34:30.825116 Dram Type= 6, Freq= 0, CH_0, rank 0
7414 01:34:30.828296 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7415 01:34:30.828867 ==
7416 01:34:30.829392
7417 01:34:30.829854
7418 01:34:30.831816 TX Vref Scan disable
7419 01:34:30.835045 == TX Byte 0 ==
7420 01:34:30.838087 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7421 01:34:30.841475 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7422 01:34:30.844804 == TX Byte 1 ==
7423 01:34:30.848161 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7424 01:34:30.851074 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7425 01:34:30.851576 ==
7426 01:34:30.854802 Dram Type= 6, Freq= 0, CH_0, rank 0
7427 01:34:30.861051 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7428 01:34:30.861677 ==
7429 01:34:30.874121
7430 01:34:30.877265 TX Vref early break, caculate TX vref
7431 01:34:30.880598 TX Vref=16, minBit 8, minWin=22, winSum=369
7432 01:34:30.883863 TX Vref=18, minBit 9, minWin=21, winSum=375
7433 01:34:30.886979 TX Vref=20, minBit 8, minWin=22, winSum=383
7434 01:34:30.890526 TX Vref=22, minBit 8, minWin=23, winSum=394
7435 01:34:30.893781 TX Vref=24, minBit 8, minWin=24, winSum=403
7436 01:34:30.900521 TX Vref=26, minBit 3, minWin=25, winSum=411
7437 01:34:30.903975 TX Vref=28, minBit 4, minWin=25, winSum=413
7438 01:34:30.907015 TX Vref=30, minBit 8, minWin=24, winSum=408
7439 01:34:30.910235 TX Vref=32, minBit 8, minWin=23, winSum=397
7440 01:34:30.913887 TX Vref=34, minBit 8, minWin=23, winSum=393
7441 01:34:30.917232 TX Vref=36, minBit 3, minWin=23, winSum=383
7442 01:34:30.923748 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 28
7443 01:34:30.924319
7444 01:34:30.927170 Final TX Range 0 Vref 28
7445 01:34:30.927741
7446 01:34:30.928234 ==
7447 01:34:30.930137 Dram Type= 6, Freq= 0, CH_0, rank 0
7448 01:34:30.933703 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7449 01:34:30.934274 ==
7450 01:34:30.934764
7451 01:34:30.935218
7452 01:34:30.936874 TX Vref Scan disable
7453 01:34:30.943737 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7454 01:34:30.944305 == TX Byte 0 ==
7455 01:34:30.947068 u2DelayCellOfst[0]=14 cells (4 PI)
7456 01:34:30.950258 u2DelayCellOfst[1]=18 cells (5 PI)
7457 01:34:30.953792 u2DelayCellOfst[2]=14 cells (4 PI)
7458 01:34:30.956795 u2DelayCellOfst[3]=14 cells (4 PI)
7459 01:34:30.960203 u2DelayCellOfst[4]=7 cells (2 PI)
7460 01:34:30.963248 u2DelayCellOfst[5]=0 cells (0 PI)
7461 01:34:30.966367 u2DelayCellOfst[6]=21 cells (6 PI)
7462 01:34:30.969928 u2DelayCellOfst[7]=18 cells (5 PI)
7463 01:34:30.973431 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7464 01:34:30.976732 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7465 01:34:30.980158 == TX Byte 1 ==
7466 01:34:30.983448 u2DelayCellOfst[8]=0 cells (0 PI)
7467 01:34:30.986363 u2DelayCellOfst[9]=0 cells (0 PI)
7468 01:34:30.990118 u2DelayCellOfst[10]=10 cells (3 PI)
7469 01:34:30.990688 u2DelayCellOfst[11]=3 cells (1 PI)
7470 01:34:30.993016 u2DelayCellOfst[12]=10 cells (3 PI)
7471 01:34:30.996678 u2DelayCellOfst[13]=10 cells (3 PI)
7472 01:34:30.999436 u2DelayCellOfst[14]=14 cells (4 PI)
7473 01:34:31.003113 u2DelayCellOfst[15]=10 cells (3 PI)
7474 01:34:31.009907 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7475 01:34:31.013008 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7476 01:34:31.013635 DramC Write-DBI on
7477 01:34:31.014126 ==
7478 01:34:31.016350 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 01:34:31.023088 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7480 01:34:31.023662 ==
7481 01:34:31.024152
7482 01:34:31.024649
7483 01:34:31.026094 TX Vref Scan disable
7484 01:34:31.026572 == TX Byte 0 ==
7485 01:34:31.032783 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7486 01:34:31.033399 == TX Byte 1 ==
7487 01:34:31.036180 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7488 01:34:31.039123 DramC Write-DBI off
7489 01:34:31.039601
7490 01:34:31.040081 [DATLAT]
7491 01:34:31.042614 Freq=1600, CH0 RK0
7492 01:34:31.043191
7493 01:34:31.043680 DATLAT Default: 0xf
7494 01:34:31.045865 0, 0xFFFF, sum = 0
7495 01:34:31.046350 1, 0xFFFF, sum = 0
7496 01:34:31.049446 2, 0xFFFF, sum = 0
7497 01:34:31.050010 3, 0xFFFF, sum = 0
7498 01:34:31.052506 4, 0xFFFF, sum = 0
7499 01:34:31.052988 5, 0xFFFF, sum = 0
7500 01:34:31.056206 6, 0xFFFF, sum = 0
7501 01:34:31.056778 7, 0xFFFF, sum = 0
7502 01:34:31.059561 8, 0xFFFF, sum = 0
7503 01:34:31.062471 9, 0xFFFF, sum = 0
7504 01:34:31.062956 10, 0xFFFF, sum = 0
7505 01:34:31.065880 11, 0xFFFF, sum = 0
7506 01:34:31.066365 12, 0xFFF, sum = 0
7507 01:34:31.069067 13, 0x0, sum = 1
7508 01:34:31.069689 14, 0x0, sum = 2
7509 01:34:31.072978 15, 0x0, sum = 3
7510 01:34:31.073601 16, 0x0, sum = 4
7511 01:34:31.074094 best_step = 14
7512 01:34:31.075552
7513 01:34:31.076010 ==
7514 01:34:31.078904 Dram Type= 6, Freq= 0, CH_0, rank 0
7515 01:34:31.082187 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7516 01:34:31.082653 ==
7517 01:34:31.083019 RX Vref Scan: 1
7518 01:34:31.083360
7519 01:34:31.085742 Set Vref Range= 24 -> 127
7520 01:34:31.086218
7521 01:34:31.088923 RX Vref 24 -> 127, step: 1
7522 01:34:31.089532
7523 01:34:31.092358 RX Delay 11 -> 252, step: 4
7524 01:34:31.092926
7525 01:34:31.095437 Set Vref, RX VrefLevel [Byte0]: 24
7526 01:34:31.098769 [Byte1]: 24
7527 01:34:31.099374
7528 01:34:31.102031 Set Vref, RX VrefLevel [Byte0]: 25
7529 01:34:31.105243 [Byte1]: 25
7530 01:34:31.105846
7531 01:34:31.108821 Set Vref, RX VrefLevel [Byte0]: 26
7532 01:34:31.111965 [Byte1]: 26
7533 01:34:31.115928
7534 01:34:31.116494 Set Vref, RX VrefLevel [Byte0]: 27
7535 01:34:31.119206 [Byte1]: 27
7536 01:34:31.123526
7537 01:34:31.124091 Set Vref, RX VrefLevel [Byte0]: 28
7538 01:34:31.126392 [Byte1]: 28
7539 01:34:31.131708
7540 01:34:31.132272 Set Vref, RX VrefLevel [Byte0]: 29
7541 01:34:31.134560 [Byte1]: 29
7542 01:34:31.138588
7543 01:34:31.139063 Set Vref, RX VrefLevel [Byte0]: 30
7544 01:34:31.141727 [Byte1]: 30
7545 01:34:31.146316
7546 01:34:31.146898 Set Vref, RX VrefLevel [Byte0]: 31
7547 01:34:31.149454 [Byte1]: 31
7548 01:34:31.153886
7549 01:34:31.154597 Set Vref, RX VrefLevel [Byte0]: 32
7550 01:34:31.157184 [Byte1]: 32
7551 01:34:31.161545
7552 01:34:31.162100 Set Vref, RX VrefLevel [Byte0]: 33
7553 01:34:31.167853 [Byte1]: 33
7554 01:34:31.168422
7555 01:34:31.171130 Set Vref, RX VrefLevel [Byte0]: 34
7556 01:34:31.174239 [Byte1]: 34
7557 01:34:31.174715
7558 01:34:31.177562 Set Vref, RX VrefLevel [Byte0]: 35
7559 01:34:31.180907 [Byte1]: 35
7560 01:34:31.184310
7561 01:34:31.184857 Set Vref, RX VrefLevel [Byte0]: 36
7562 01:34:31.187583 [Byte1]: 36
7563 01:34:31.191826
7564 01:34:31.192373 Set Vref, RX VrefLevel [Byte0]: 37
7565 01:34:31.195210 [Byte1]: 37
7566 01:34:31.199755
7567 01:34:31.200300 Set Vref, RX VrefLevel [Byte0]: 38
7568 01:34:31.202679 [Byte1]: 38
7569 01:34:31.207011
7570 01:34:31.207514 Set Vref, RX VrefLevel [Byte0]: 39
7571 01:34:31.210089 [Byte1]: 39
7572 01:34:31.214602
7573 01:34:31.215052 Set Vref, RX VrefLevel [Byte0]: 40
7574 01:34:31.217914 [Byte1]: 40
7575 01:34:31.222290
7576 01:34:31.222840 Set Vref, RX VrefLevel [Byte0]: 41
7577 01:34:31.225683 [Byte1]: 41
7578 01:34:31.230141
7579 01:34:31.230684 Set Vref, RX VrefLevel [Byte0]: 42
7580 01:34:31.233078 [Byte1]: 42
7581 01:34:31.237633
7582 01:34:31.238184 Set Vref, RX VrefLevel [Byte0]: 43
7583 01:34:31.241088 [Byte1]: 43
7584 01:34:31.245172
7585 01:34:31.245779 Set Vref, RX VrefLevel [Byte0]: 44
7586 01:34:31.248423 [Byte1]: 44
7587 01:34:31.252718
7588 01:34:31.253266 Set Vref, RX VrefLevel [Byte0]: 45
7589 01:34:31.255868 [Byte1]: 45
7590 01:34:31.260350
7591 01:34:31.260898 Set Vref, RX VrefLevel [Byte0]: 46
7592 01:34:31.266550 [Byte1]: 46
7593 01:34:31.267101
7594 01:34:31.270000 Set Vref, RX VrefLevel [Byte0]: 47
7595 01:34:31.273615 [Byte1]: 47
7596 01:34:31.274173
7597 01:34:31.276698 Set Vref, RX VrefLevel [Byte0]: 48
7598 01:34:31.279951 [Byte1]: 48
7599 01:34:31.283377
7600 01:34:31.283926 Set Vref, RX VrefLevel [Byte0]: 49
7601 01:34:31.286631 [Byte1]: 49
7602 01:34:31.290824
7603 01:34:31.291369 Set Vref, RX VrefLevel [Byte0]: 50
7604 01:34:31.294126 [Byte1]: 50
7605 01:34:31.298388
7606 01:34:31.298941 Set Vref, RX VrefLevel [Byte0]: 51
7607 01:34:31.301776 [Byte1]: 51
7608 01:34:31.306237
7609 01:34:31.306836 Set Vref, RX VrefLevel [Byte0]: 52
7610 01:34:31.309372 [Byte1]: 52
7611 01:34:31.313771
7612 01:34:31.314370 Set Vref, RX VrefLevel [Byte0]: 53
7613 01:34:31.317138 [Byte1]: 53
7614 01:34:31.321238
7615 01:34:31.321841 Set Vref, RX VrefLevel [Byte0]: 54
7616 01:34:31.324468 [Byte1]: 54
7617 01:34:31.328908
7618 01:34:31.329490 Set Vref, RX VrefLevel [Byte0]: 55
7619 01:34:31.331990 [Byte1]: 55
7620 01:34:31.336672
7621 01:34:31.337217 Set Vref, RX VrefLevel [Byte0]: 56
7622 01:34:31.340380 [Byte1]: 56
7623 01:34:31.344101
7624 01:34:31.344631 Set Vref, RX VrefLevel [Byte0]: 57
7625 01:34:31.347221 [Byte1]: 57
7626 01:34:31.351834
7627 01:34:31.352388 Set Vref, RX VrefLevel [Byte0]: 58
7628 01:34:31.354756 [Byte1]: 58
7629 01:34:31.359411
7630 01:34:31.359959 Set Vref, RX VrefLevel [Byte0]: 59
7631 01:34:31.362665 [Byte1]: 59
7632 01:34:31.366881
7633 01:34:31.367798 Set Vref, RX VrefLevel [Byte0]: 60
7634 01:34:31.370489 [Byte1]: 60
7635 01:34:31.374286
7636 01:34:31.374792 Set Vref, RX VrefLevel [Byte0]: 61
7637 01:34:31.378061 [Byte1]: 61
7638 01:34:31.382293
7639 01:34:31.382845 Set Vref, RX VrefLevel [Byte0]: 62
7640 01:34:31.385360 [Byte1]: 62
7641 01:34:31.389549
7642 01:34:31.390000 Set Vref, RX VrefLevel [Byte0]: 63
7643 01:34:31.393026 [Byte1]: 63
7644 01:34:31.397442
7645 01:34:31.397994 Set Vref, RX VrefLevel [Byte0]: 64
7646 01:34:31.400549 [Byte1]: 64
7647 01:34:31.405138
7648 01:34:31.405750 Set Vref, RX VrefLevel [Byte0]: 65
7649 01:34:31.408091 [Byte1]: 65
7650 01:34:31.412544
7651 01:34:31.413162 Set Vref, RX VrefLevel [Byte0]: 66
7652 01:34:31.416066 [Byte1]: 66
7653 01:34:31.420340
7654 01:34:31.420894 Set Vref, RX VrefLevel [Byte0]: 67
7655 01:34:31.423448 [Byte1]: 67
7656 01:34:31.427784
7657 01:34:31.428332 Set Vref, RX VrefLevel [Byte0]: 68
7658 01:34:31.431559 [Byte1]: 68
7659 01:34:31.435661
7660 01:34:31.436204 Set Vref, RX VrefLevel [Byte0]: 69
7661 01:34:31.438721 [Byte1]: 69
7662 01:34:31.442911
7663 01:34:31.443459 Set Vref, RX VrefLevel [Byte0]: 70
7664 01:34:31.446244 [Byte1]: 70
7665 01:34:31.450697
7666 01:34:31.451387 Set Vref, RX VrefLevel [Byte0]: 71
7667 01:34:31.453727 [Byte1]: 71
7668 01:34:31.458030
7669 01:34:31.458479 Final RX Vref Byte 0 = 52 to rank0
7670 01:34:31.461390 Final RX Vref Byte 1 = 55 to rank0
7671 01:34:31.464859 Final RX Vref Byte 0 = 52 to rank1
7672 01:34:31.467927 Final RX Vref Byte 1 = 55 to rank1==
7673 01:34:31.471128 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 01:34:31.477980 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7675 01:34:31.478535 ==
7676 01:34:31.478902 DQS Delay:
7677 01:34:31.481244 DQS0 = 0, DQS1 = 0
7678 01:34:31.481731 DQM Delay:
7679 01:34:31.482093 DQM0 = 127, DQM1 = 121
7680 01:34:31.484241 DQ Delay:
7681 01:34:31.487830 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7682 01:34:31.491167 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7683 01:34:31.494571 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7684 01:34:31.497505 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7685 01:34:31.497961
7686 01:34:31.498316
7687 01:34:31.498648
7688 01:34:31.500846 [DramC_TX_OE_Calibration] TA2
7689 01:34:31.504430 Original DQ_B0 (3 6) =30, OEN = 27
7690 01:34:31.507724 Original DQ_B1 (3 6) =30, OEN = 27
7691 01:34:31.511070 24, 0x0, End_B0=24 End_B1=24
7692 01:34:31.514133 25, 0x0, End_B0=25 End_B1=25
7693 01:34:31.514652 26, 0x0, End_B0=26 End_B1=26
7694 01:34:31.517897 27, 0x0, End_B0=27 End_B1=27
7695 01:34:31.520854 28, 0x0, End_B0=28 End_B1=28
7696 01:34:31.524338 29, 0x0, End_B0=29 End_B1=29
7697 01:34:31.524958 30, 0x0, End_B0=30 End_B1=30
7698 01:34:31.527154 31, 0x4141, End_B0=30 End_B1=30
7699 01:34:31.530571 Byte0 end_step=30 best_step=27
7700 01:34:31.533697 Byte1 end_step=30 best_step=27
7701 01:34:31.537199 Byte0 TX OE(2T, 0.5T) = (3, 3)
7702 01:34:31.540496 Byte1 TX OE(2T, 0.5T) = (3, 3)
7703 01:34:31.541048
7704 01:34:31.541446
7705 01:34:31.547021 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7706 01:34:31.550585 CH0 RK0: MR19=303, MR18=1717
7707 01:34:31.556885 CH0_RK0: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
7708 01:34:31.557449
7709 01:34:31.560452 ----->DramcWriteLeveling(PI) begin...
7710 01:34:31.561010 ==
7711 01:34:31.563616 Dram Type= 6, Freq= 0, CH_0, rank 1
7712 01:34:31.566802 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7713 01:34:31.567261 ==
7714 01:34:31.570250 Write leveling (Byte 0): 28 => 28
7715 01:34:31.573912 Write leveling (Byte 1): 25 => 25
7716 01:34:31.576927 DramcWriteLeveling(PI) end<-----
7717 01:34:31.577508
7718 01:34:31.577869 ==
7719 01:34:31.580395 Dram Type= 6, Freq= 0, CH_0, rank 1
7720 01:34:31.586758 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7721 01:34:31.587323 ==
7722 01:34:31.587770 [Gating] SW mode calibration
7723 01:34:31.596638 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7724 01:34:31.599861 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7725 01:34:31.603152 0 12 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7726 01:34:31.610163 0 12 4 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7727 01:34:31.613329 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 01:34:31.616706 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7729 01:34:31.623130 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7730 01:34:31.626448 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7731 01:34:31.629733 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7732 01:34:31.636431 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7733 01:34:31.639596 0 13 0 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
7734 01:34:31.643056 0 13 4 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
7735 01:34:31.649534 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
7736 01:34:31.652851 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7737 01:34:31.656278 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7738 01:34:31.662617 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 01:34:31.666002 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7740 01:34:31.669232 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7741 01:34:31.675749 0 14 0 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
7742 01:34:31.679483 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7743 01:34:31.682184 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 01:34:31.689023 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7745 01:34:31.692385 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7746 01:34:31.695768 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 01:34:31.702399 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7748 01:34:31.705483 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7749 01:34:31.708680 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7750 01:34:31.715128 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7751 01:34:31.718816 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 01:34:31.722116 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 01:34:31.728490 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 01:34:31.731966 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 01:34:31.735402 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 01:34:31.741832 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 01:34:31.745239 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 01:34:31.748874 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 01:34:31.755030 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 01:34:31.758774 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 01:34:31.761832 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 01:34:31.768329 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 01:34:31.771676 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 01:34:31.775181 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7765 01:34:31.781511 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7766 01:34:31.785114 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7767 01:34:31.788201 Total UI for P1: 0, mck2ui 16
7768 01:34:31.791618 best dqsien dly found for B0: ( 1, 0, 30)
7769 01:34:31.795009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7770 01:34:31.798563 Total UI for P1: 0, mck2ui 16
7771 01:34:31.801696 best dqsien dly found for B1: ( 1, 1, 2)
7772 01:34:31.804768 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7773 01:34:31.808360 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7774 01:34:31.808812
7775 01:34:31.811714 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7776 01:34:31.818187 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7777 01:34:31.818715 [Gating] SW calibration Done
7778 01:34:31.819393 ==
7779 01:34:31.821216 Dram Type= 6, Freq= 0, CH_0, rank 1
7780 01:34:31.828267 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7781 01:34:31.829036 ==
7782 01:34:31.829645 RX Vref Scan: 0
7783 01:34:31.830069
7784 01:34:31.831586 RX Vref 0 -> 0, step: 1
7785 01:34:31.832036
7786 01:34:31.834693 RX Delay 0 -> 252, step: 8
7787 01:34:31.837871 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7788 01:34:31.841739 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7789 01:34:31.844988 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7790 01:34:31.851586 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7791 01:34:31.854606 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7792 01:34:31.857965 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7793 01:34:31.861122 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7794 01:34:31.864963 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7795 01:34:31.871173 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7796 01:34:31.874657 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7797 01:34:31.877907 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7798 01:34:31.881240 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7799 01:34:31.884826 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7800 01:34:31.891127 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7801 01:34:31.894461 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7802 01:34:31.897708 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7803 01:34:31.898245 ==
7804 01:34:31.901181 Dram Type= 6, Freq= 0, CH_0, rank 1
7805 01:34:31.904329 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7806 01:34:31.904787 ==
7807 01:34:31.907982 DQS Delay:
7808 01:34:31.908532 DQS0 = 0, DQS1 = 0
7809 01:34:31.911187 DQM Delay:
7810 01:34:31.911765 DQM0 = 131, DQM1 = 124
7811 01:34:31.914196 DQ Delay:
7812 01:34:31.917906 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
7813 01:34:31.920841 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7814 01:34:31.924517 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7815 01:34:31.927695 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7816 01:34:31.928251
7817 01:34:31.928615
7818 01:34:31.928951 ==
7819 01:34:31.930864 Dram Type= 6, Freq= 0, CH_0, rank 1
7820 01:34:31.934146 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7821 01:34:31.934602 ==
7822 01:34:31.934965
7823 01:34:31.935296
7824 01:34:31.937432 TX Vref Scan disable
7825 01:34:31.940862 == TX Byte 0 ==
7826 01:34:31.944473 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7827 01:34:31.947298 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7828 01:34:31.950699 == TX Byte 1 ==
7829 01:34:31.953950 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7830 01:34:31.957638 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7831 01:34:31.958188 ==
7832 01:34:31.960778 Dram Type= 6, Freq= 0, CH_0, rank 1
7833 01:34:31.967329 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7834 01:34:31.967885 ==
7835 01:34:31.978992
7836 01:34:31.982018 TX Vref early break, caculate TX vref
7837 01:34:31.985265 TX Vref=16, minBit 9, minWin=21, winSum=374
7838 01:34:31.988619 TX Vref=18, minBit 1, minWin=23, winSum=381
7839 01:34:31.992179 TX Vref=20, minBit 11, minWin=22, winSum=390
7840 01:34:31.995438 TX Vref=22, minBit 8, minWin=23, winSum=399
7841 01:34:31.998643 TX Vref=24, minBit 1, minWin=24, winSum=401
7842 01:34:32.005326 TX Vref=26, minBit 11, minWin=24, winSum=413
7843 01:34:32.008558 TX Vref=28, minBit 6, minWin=25, winSum=416
7844 01:34:32.011773 TX Vref=30, minBit 8, minWin=24, winSum=410
7845 01:34:32.015203 TX Vref=32, minBit 8, minWin=24, winSum=406
7846 01:34:32.018391 TX Vref=34, minBit 1, minWin=23, winSum=394
7847 01:34:32.025159 [TxChooseVref] Worse bit 6, Min win 25, Win sum 416, Final Vref 28
7848 01:34:32.025755
7849 01:34:32.028417 Final TX Range 0 Vref 28
7850 01:34:32.028878
7851 01:34:32.029240 ==
7852 01:34:32.031475 Dram Type= 6, Freq= 0, CH_0, rank 1
7853 01:34:32.034694 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7854 01:34:32.035153 ==
7855 01:34:32.035514
7856 01:34:32.035849
7857 01:34:32.038177 TX Vref Scan disable
7858 01:34:32.044923 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7859 01:34:32.045610 == TX Byte 0 ==
7860 01:34:32.048213 u2DelayCellOfst[0]=14 cells (4 PI)
7861 01:34:32.051325 u2DelayCellOfst[1]=21 cells (6 PI)
7862 01:34:32.055004 u2DelayCellOfst[2]=14 cells (4 PI)
7863 01:34:32.057983 u2DelayCellOfst[3]=14 cells (4 PI)
7864 01:34:32.061400 u2DelayCellOfst[4]=10 cells (3 PI)
7865 01:34:32.064614 u2DelayCellOfst[5]=0 cells (0 PI)
7866 01:34:32.068076 u2DelayCellOfst[6]=21 cells (6 PI)
7867 01:34:32.071516 u2DelayCellOfst[7]=18 cells (5 PI)
7868 01:34:32.074672 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7869 01:34:32.077727 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7870 01:34:32.081219 == TX Byte 1 ==
7871 01:34:32.084400 u2DelayCellOfst[8]=0 cells (0 PI)
7872 01:34:32.088006 u2DelayCellOfst[9]=0 cells (0 PI)
7873 01:34:32.091190 u2DelayCellOfst[10]=10 cells (3 PI)
7874 01:34:32.091668 u2DelayCellOfst[11]=3 cells (1 PI)
7875 01:34:32.094672 u2DelayCellOfst[12]=14 cells (4 PI)
7876 01:34:32.097920 u2DelayCellOfst[13]=14 cells (4 PI)
7877 01:34:32.101254 u2DelayCellOfst[14]=18 cells (5 PI)
7878 01:34:32.104576 u2DelayCellOfst[15]=14 cells (4 PI)
7879 01:34:32.111071 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7880 01:34:32.114427 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7881 01:34:32.114983 DramC Write-DBI on
7882 01:34:32.115348 ==
7883 01:34:32.117454 Dram Type= 6, Freq= 0, CH_0, rank 1
7884 01:34:32.124399 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7885 01:34:32.124949 ==
7886 01:34:32.125365
7887 01:34:32.125717
7888 01:34:32.127460 TX Vref Scan disable
7889 01:34:32.127912 == TX Byte 0 ==
7890 01:34:32.134072 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7891 01:34:32.134625 == TX Byte 1 ==
7892 01:34:32.137649 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7893 01:34:32.140742 DramC Write-DBI off
7894 01:34:32.141335
7895 01:34:32.141715 [DATLAT]
7896 01:34:32.144092 Freq=1600, CH0 RK1
7897 01:34:32.144644
7898 01:34:32.145009 DATLAT Default: 0xe
7899 01:34:32.147454 0, 0xFFFF, sum = 0
7900 01:34:32.147959 1, 0xFFFF, sum = 0
7901 01:34:32.150814 2, 0xFFFF, sum = 0
7902 01:34:32.151376 3, 0xFFFF, sum = 0
7903 01:34:32.153941 4, 0xFFFF, sum = 0
7904 01:34:32.154497 5, 0xFFFF, sum = 0
7905 01:34:32.157654 6, 0xFFFF, sum = 0
7906 01:34:32.158217 7, 0xFFFF, sum = 0
7907 01:34:32.160811 8, 0xFFFF, sum = 0
7908 01:34:32.161459 9, 0xFFFF, sum = 0
7909 01:34:32.163831 10, 0xFFFF, sum = 0
7910 01:34:32.167675 11, 0xFFFF, sum = 0
7911 01:34:32.168233 12, 0xCFFF, sum = 0
7912 01:34:32.170473 13, 0x0, sum = 1
7913 01:34:32.170951 14, 0x0, sum = 2
7914 01:34:32.173883 15, 0x0, sum = 3
7915 01:34:32.174350 16, 0x0, sum = 4
7916 01:34:32.174721 best_step = 14
7917 01:34:32.175060
7918 01:34:32.177144 ==
7919 01:34:32.180303 Dram Type= 6, Freq= 0, CH_0, rank 1
7920 01:34:32.183912 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7921 01:34:32.184486 ==
7922 01:34:32.184850 RX Vref Scan: 0
7923 01:34:32.185182
7924 01:34:32.186991 RX Vref 0 -> 0, step: 1
7925 01:34:32.187440
7926 01:34:32.190061 RX Delay 11 -> 252, step: 4
7927 01:34:32.193893 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7928 01:34:32.197087 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7929 01:34:32.203654 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7930 01:34:32.206943 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7931 01:34:32.209955 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7932 01:34:32.213526 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7933 01:34:32.220237 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7934 01:34:32.223339 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7935 01:34:32.226792 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7936 01:34:32.230152 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7937 01:34:32.233423 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7938 01:34:32.239996 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7939 01:34:32.243294 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7940 01:34:32.246778 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7941 01:34:32.249973 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7942 01:34:32.252790 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7943 01:34:32.256418 ==
7944 01:34:32.259608 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 01:34:32.262957 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7946 01:34:32.263524 ==
7947 01:34:32.263892 DQS Delay:
7948 01:34:32.266260 DQS0 = 0, DQS1 = 0
7949 01:34:32.266804 DQM Delay:
7950 01:34:32.269754 DQM0 = 128, DQM1 = 120
7951 01:34:32.270321 DQ Delay:
7952 01:34:32.272837 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7953 01:34:32.276436 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
7954 01:34:32.279194 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7955 01:34:32.282504 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7956 01:34:32.283017
7957 01:34:32.283500
7958 01:34:32.283950
7959 01:34:32.285634 [DramC_TX_OE_Calibration] TA2
7960 01:34:32.288987 Original DQ_B0 (3 6) =30, OEN = 27
7961 01:34:32.292222 Original DQ_B1 (3 6) =30, OEN = 27
7962 01:34:32.296099 24, 0x0, End_B0=24 End_B1=24
7963 01:34:32.299155 25, 0x0, End_B0=25 End_B1=25
7964 01:34:32.302035 26, 0x0, End_B0=26 End_B1=26
7965 01:34:32.302649 27, 0x0, End_B0=27 End_B1=27
7966 01:34:32.305619 28, 0x0, End_B0=28 End_B1=28
7967 01:34:32.309141 29, 0x0, End_B0=29 End_B1=29
7968 01:34:32.312537 30, 0x0, End_B0=30 End_B1=30
7969 01:34:32.315785 31, 0x4141, End_B0=30 End_B1=30
7970 01:34:32.316398 Byte0 end_step=30 best_step=27
7971 01:34:32.318950 Byte1 end_step=30 best_step=27
7972 01:34:32.322088 Byte0 TX OE(2T, 0.5T) = (3, 3)
7973 01:34:32.325734 Byte1 TX OE(2T, 0.5T) = (3, 3)
7974 01:34:32.326211
7975 01:34:32.326698
7976 01:34:32.332650 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7977 01:34:32.335498 CH0 RK1: MR19=303, MR18=1F1F
7978 01:34:32.342031 CH0_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7979 01:34:32.345336 [RxdqsGatingPostProcess] freq 1600
7980 01:34:32.351867 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7981 01:34:32.355341 Pre-setting of DQS Precalculation
7982 01:34:32.358631 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7983 01:34:32.359200 ==
7984 01:34:32.361882 Dram Type= 6, Freq= 0, CH_1, rank 0
7985 01:34:32.365025 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7986 01:34:32.368490 ==
7987 01:34:32.371789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7988 01:34:32.375202 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7989 01:34:32.381524 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7990 01:34:32.388302 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7991 01:34:32.394546 [CA 0] Center 41 (11~71) winsize 61
7992 01:34:32.397897 [CA 1] Center 41 (11~72) winsize 62
7993 01:34:32.401250 [CA 2] Center 37 (8~67) winsize 60
7994 01:34:32.404489 [CA 3] Center 36 (7~66) winsize 60
7995 01:34:32.407803 [CA 4] Center 34 (4~64) winsize 61
7996 01:34:32.411099 [CA 5] Center 34 (4~64) winsize 61
7997 01:34:32.411551
7998 01:34:32.414864 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7999 01:34:32.415433
8000 01:34:32.417769 [CATrainingPosCal] consider 1 rank data
8001 01:34:32.421993 u2DelayCellTimex100 = 271/100 ps
8002 01:34:32.424274 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8003 01:34:32.431164 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8004 01:34:32.434384 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8005 01:34:32.437786 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8006 01:34:32.441153 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8007 01:34:32.444109 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8008 01:34:32.444565
8009 01:34:32.447639 CA PerBit enable=1, Macro0, CA PI delay=34
8010 01:34:32.448093
8011 01:34:32.451667 [CBTSetCACLKResult] CA Dly = 34
8012 01:34:32.454246 CS Dly: 8 (0~39)
8013 01:34:32.457807 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8014 01:34:32.460968 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8015 01:34:32.461558 ==
8016 01:34:32.464408 Dram Type= 6, Freq= 0, CH_1, rank 1
8017 01:34:32.467189 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8018 01:34:32.470778 ==
8019 01:34:32.474022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8020 01:34:32.477485 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8021 01:34:32.484353 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8022 01:34:32.490546 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8023 01:34:32.497226 [CA 0] Center 41 (11~71) winsize 61
8024 01:34:32.500381 [CA 1] Center 41 (11~71) winsize 61
8025 01:34:32.504017 [CA 2] Center 36 (7~66) winsize 60
8026 01:34:32.506896 [CA 3] Center 36 (7~65) winsize 59
8027 01:34:32.510147 [CA 4] Center 34 (5~64) winsize 60
8028 01:34:32.513823 [CA 5] Center 34 (5~64) winsize 60
8029 01:34:32.514388
8030 01:34:32.516785 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8031 01:34:32.517260
8032 01:34:32.520479 [CATrainingPosCal] consider 2 rank data
8033 01:34:32.523784 u2DelayCellTimex100 = 271/100 ps
8034 01:34:32.526858 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8035 01:34:32.533767 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8036 01:34:32.536701 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8037 01:34:32.539775 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8038 01:34:32.543644 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8039 01:34:32.546890 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8040 01:34:32.547345
8041 01:34:32.549650 CA PerBit enable=1, Macro0, CA PI delay=34
8042 01:34:32.550116
8043 01:34:32.553267 [CBTSetCACLKResult] CA Dly = 34
8044 01:34:32.556794 CS Dly: 9 (0~41)
8045 01:34:32.559903 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8046 01:34:32.563353 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8047 01:34:32.563906
8048 01:34:32.566467 ----->DramcWriteLeveling(PI) begin...
8049 01:34:32.567025 ==
8050 01:34:32.570208 Dram Type= 6, Freq= 0, CH_1, rank 0
8051 01:34:32.576338 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8052 01:34:32.576835 ==
8053 01:34:32.579389 Write leveling (Byte 0): 23 => 23
8054 01:34:32.583049 Write leveling (Byte 1): 20 => 20
8055 01:34:32.583503 DramcWriteLeveling(PI) end<-----
8056 01:34:32.584050
8057 01:34:32.586145 ==
8058 01:34:32.589492 Dram Type= 6, Freq= 0, CH_1, rank 0
8059 01:34:32.592979 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8060 01:34:32.593478 ==
8061 01:34:32.596462 [Gating] SW mode calibration
8062 01:34:32.602890 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 01:34:32.606180 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8064 01:34:32.613016 0 12 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8065 01:34:32.616150 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 01:34:32.619620 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 01:34:32.625952 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 01:34:32.628947 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 01:34:32.632691 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 01:34:32.639117 0 12 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8071 01:34:32.642875 0 12 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
8072 01:34:32.645794 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (0 1) (1 0)
8073 01:34:32.652212 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 01:34:32.655787 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 01:34:32.659316 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 01:34:32.665800 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 01:34:32.669042 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 01:34:32.672323 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 01:34:32.678658 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8080 01:34:32.681981 0 14 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8081 01:34:32.685155 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 01:34:32.692220 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 01:34:32.695082 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 01:34:32.698457 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 01:34:32.705421 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 01:34:32.708557 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 01:34:32.711603 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 01:34:32.718222 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8089 01:34:32.722031 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 01:34:32.725825 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 01:34:32.732153 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 01:34:32.734888 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 01:34:32.738181 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 01:34:32.744662 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 01:34:32.748198 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 01:34:32.751437 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 01:34:32.758032 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 01:34:32.761112 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 01:34:32.764569 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 01:34:32.771403 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 01:34:32.774219 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 01:34:32.777393 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 01:34:32.784482 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8104 01:34:32.787737 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 01:34:32.790561 Total UI for P1: 0, mck2ui 16
8106 01:34:32.793800 best dqsien dly found for B0: ( 1, 0, 26)
8107 01:34:32.797555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 01:34:32.804038 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 01:34:32.804590 Total UI for P1: 0, mck2ui 16
8110 01:34:32.810511 best dqsien dly found for B1: ( 1, 1, 0)
8111 01:34:32.813879 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8112 01:34:32.817137 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8113 01:34:32.817745
8114 01:34:32.820104 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8115 01:34:32.823925 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8116 01:34:32.826741 [Gating] SW calibration Done
8117 01:34:32.827194 ==
8118 01:34:32.830250 Dram Type= 6, Freq= 0, CH_1, rank 0
8119 01:34:32.833922 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8120 01:34:32.834506 ==
8121 01:34:32.837076 RX Vref Scan: 0
8122 01:34:32.837669
8123 01:34:32.838034 RX Vref 0 -> 0, step: 1
8124 01:34:32.838369
8125 01:34:32.839914 RX Delay 0 -> 252, step: 8
8126 01:34:32.843603 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8127 01:34:32.849991 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8128 01:34:32.853271 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8129 01:34:32.856631 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8130 01:34:32.859960 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8131 01:34:32.863349 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8132 01:34:32.870101 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8133 01:34:32.873382 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8134 01:34:32.876564 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8135 01:34:32.879661 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8136 01:34:32.886010 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8137 01:34:32.889893 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8138 01:34:32.893129 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8139 01:34:32.896300 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8140 01:34:32.899483 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8141 01:34:32.906403 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8142 01:34:32.906959 ==
8143 01:34:32.909552 Dram Type= 6, Freq= 0, CH_1, rank 0
8144 01:34:32.912747 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8145 01:34:32.913335 ==
8146 01:34:32.913711 DQS Delay:
8147 01:34:32.916087 DQS0 = 0, DQS1 = 0
8148 01:34:32.916635 DQM Delay:
8149 01:34:32.919292 DQM0 = 130, DQM1 = 125
8150 01:34:32.919765 DQ Delay:
8151 01:34:32.922448 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8152 01:34:32.925756 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8153 01:34:32.929079 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8154 01:34:32.932594 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8155 01:34:32.935739
8156 01:34:32.936195
8157 01:34:32.936560 ==
8158 01:34:32.939232 Dram Type= 6, Freq= 0, CH_1, rank 0
8159 01:34:32.942489 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8160 01:34:32.943043 ==
8161 01:34:32.943409
8162 01:34:32.943743
8163 01:34:32.945662 TX Vref Scan disable
8164 01:34:32.946119 == TX Byte 0 ==
8165 01:34:32.952346 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8166 01:34:32.955545 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8167 01:34:32.956004 == TX Byte 1 ==
8168 01:34:32.962085 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8169 01:34:32.965325 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8170 01:34:32.965788 ==
8171 01:34:32.968664 Dram Type= 6, Freq= 0, CH_1, rank 0
8172 01:34:32.971833 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8173 01:34:32.972295 ==
8174 01:34:32.985463
8175 01:34:32.988800 TX Vref early break, caculate TX vref
8176 01:34:32.992402 TX Vref=16, minBit 3, minWin=21, winSum=369
8177 01:34:32.995792 TX Vref=18, minBit 3, minWin=21, winSum=376
8178 01:34:32.998765 TX Vref=20, minBit 1, minWin=23, winSum=388
8179 01:34:33.002921 TX Vref=22, minBit 3, minWin=23, winSum=395
8180 01:34:33.005399 TX Vref=24, minBit 0, minWin=24, winSum=406
8181 01:34:33.012015 TX Vref=26, minBit 0, minWin=25, winSum=414
8182 01:34:33.014966 TX Vref=28, minBit 3, minWin=24, winSum=414
8183 01:34:33.018533 TX Vref=30, minBit 3, minWin=23, winSum=404
8184 01:34:33.022252 TX Vref=32, minBit 0, minWin=24, winSum=402
8185 01:34:33.025226 TX Vref=34, minBit 3, minWin=22, winSum=390
8186 01:34:33.031806 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8187 01:34:33.032361
8188 01:34:33.034902 Final TX Range 0 Vref 26
8189 01:34:33.035396
8190 01:34:33.035809 ==
8191 01:34:33.038240 Dram Type= 6, Freq= 0, CH_1, rank 0
8192 01:34:33.041875 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8193 01:34:33.042436 ==
8194 01:34:33.042802
8195 01:34:33.043136
8196 01:34:33.044888 TX Vref Scan disable
8197 01:34:33.051328 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8198 01:34:33.051786 == TX Byte 0 ==
8199 01:34:33.054767 u2DelayCellOfst[0]=14 cells (4 PI)
8200 01:34:33.057980 u2DelayCellOfst[1]=7 cells (2 PI)
8201 01:34:33.061540 u2DelayCellOfst[2]=0 cells (0 PI)
8202 01:34:33.064797 u2DelayCellOfst[3]=3 cells (1 PI)
8203 01:34:33.067929 u2DelayCellOfst[4]=7 cells (2 PI)
8204 01:34:33.071057 u2DelayCellOfst[5]=14 cells (4 PI)
8205 01:34:33.074363 u2DelayCellOfst[6]=14 cells (4 PI)
8206 01:34:33.077936 u2DelayCellOfst[7]=3 cells (1 PI)
8207 01:34:33.080992 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8208 01:34:33.084511 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8209 01:34:33.087628 == TX Byte 1 ==
8210 01:34:33.091088 u2DelayCellOfst[8]=0 cells (0 PI)
8211 01:34:33.091545 u2DelayCellOfst[9]=3 cells (1 PI)
8212 01:34:33.094131 u2DelayCellOfst[10]=10 cells (3 PI)
8213 01:34:33.097552 u2DelayCellOfst[11]=3 cells (1 PI)
8214 01:34:33.101086 u2DelayCellOfst[12]=14 cells (4 PI)
8215 01:34:33.104321 u2DelayCellOfst[13]=14 cells (4 PI)
8216 01:34:33.107396 u2DelayCellOfst[14]=14 cells (4 PI)
8217 01:34:33.111075 u2DelayCellOfst[15]=14 cells (4 PI)
8218 01:34:33.114078 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8219 01:34:33.121391 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8220 01:34:33.121963 DramC Write-DBI on
8221 01:34:33.122367 ==
8222 01:34:33.123977 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 01:34:33.130698 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8224 01:34:33.131171 ==
8225 01:34:33.131637
8226 01:34:33.132293
8227 01:34:33.132704 TX Vref Scan disable
8228 01:34:33.134362 == TX Byte 0 ==
8229 01:34:33.137708 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8230 01:34:33.141146 == TX Byte 1 ==
8231 01:34:33.144687 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8232 01:34:33.147838 DramC Write-DBI off
8233 01:34:33.148299
8234 01:34:33.148820 [DATLAT]
8235 01:34:33.149484 Freq=1600, CH1 RK0
8236 01:34:33.149893
8237 01:34:33.151211 DATLAT Default: 0xf
8238 01:34:33.151679 0, 0xFFFF, sum = 0
8239 01:34:33.154473 1, 0xFFFF, sum = 0
8240 01:34:33.157532 2, 0xFFFF, sum = 0
8241 01:34:33.157969 3, 0xFFFF, sum = 0
8242 01:34:33.160871 4, 0xFFFF, sum = 0
8243 01:34:33.161321 5, 0xFFFF, sum = 0
8244 01:34:33.164501 6, 0xFFFF, sum = 0
8245 01:34:33.165040 7, 0xFFFF, sum = 0
8246 01:34:33.167512 8, 0xFFFF, sum = 0
8247 01:34:33.167938 9, 0xFFFF, sum = 0
8248 01:34:33.170770 10, 0xFFFF, sum = 0
8249 01:34:33.171196 11, 0xFFFF, sum = 0
8250 01:34:33.174327 12, 0xF7F, sum = 0
8251 01:34:33.174854 13, 0x0, sum = 1
8252 01:34:33.177487 14, 0x0, sum = 2
8253 01:34:33.177916 15, 0x0, sum = 3
8254 01:34:33.180684 16, 0x0, sum = 4
8255 01:34:33.181106 best_step = 14
8256 01:34:33.181480
8257 01:34:33.181797 ==
8258 01:34:33.184137 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 01:34:33.187775 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8260 01:34:33.190799 ==
8261 01:34:33.191211 RX Vref Scan: 1
8262 01:34:33.191537
8263 01:34:33.194210 Set Vref Range= 24 -> 127
8264 01:34:33.194624
8265 01:34:33.197208 RX Vref 24 -> 127, step: 1
8266 01:34:33.197710
8267 01:34:33.198042 RX Delay 3 -> 252, step: 4
8268 01:34:33.198348
8269 01:34:33.200403 Set Vref, RX VrefLevel [Byte0]: 24
8270 01:34:33.203722 [Byte1]: 24
8271 01:34:33.207520
8272 01:34:33.208028 Set Vref, RX VrefLevel [Byte0]: 25
8273 01:34:33.211538 [Byte1]: 25
8274 01:34:33.215195
8275 01:34:33.215709 Set Vref, RX VrefLevel [Byte0]: 26
8276 01:34:33.218767 [Byte1]: 26
8277 01:34:33.223449
8278 01:34:33.223962 Set Vref, RX VrefLevel [Byte0]: 27
8279 01:34:33.226387 [Byte1]: 27
8280 01:34:33.230641
8281 01:34:33.231128 Set Vref, RX VrefLevel [Byte0]: 28
8282 01:34:33.233937 [Byte1]: 28
8283 01:34:33.238645
8284 01:34:33.239163 Set Vref, RX VrefLevel [Byte0]: 29
8285 01:34:33.241858 [Byte1]: 29
8286 01:34:33.246454
8287 01:34:33.247143 Set Vref, RX VrefLevel [Byte0]: 30
8288 01:34:33.249351 [Byte1]: 30
8289 01:34:33.253854
8290 01:34:33.254398 Set Vref, RX VrefLevel [Byte0]: 31
8291 01:34:33.256747 [Byte1]: 31
8292 01:34:33.261316
8293 01:34:33.261882 Set Vref, RX VrefLevel [Byte0]: 32
8294 01:34:33.264591 [Byte1]: 32
8295 01:34:33.269198
8296 01:34:33.269741 Set Vref, RX VrefLevel [Byte0]: 33
8297 01:34:33.272150 [Byte1]: 33
8298 01:34:33.276594
8299 01:34:33.277002 Set Vref, RX VrefLevel [Byte0]: 34
8300 01:34:33.279892 [Byte1]: 34
8301 01:34:33.284558
8302 01:34:33.285059 Set Vref, RX VrefLevel [Byte0]: 35
8303 01:34:33.287489 [Byte1]: 35
8304 01:34:33.292071
8305 01:34:33.292576 Set Vref, RX VrefLevel [Byte0]: 36
8306 01:34:33.294983 [Byte1]: 36
8307 01:34:33.299466
8308 01:34:33.299875 Set Vref, RX VrefLevel [Byte0]: 37
8309 01:34:33.302808 [Byte1]: 37
8310 01:34:33.307461
8311 01:34:33.308080 Set Vref, RX VrefLevel [Byte0]: 38
8312 01:34:33.310321 [Byte1]: 38
8313 01:34:33.314791
8314 01:34:33.315197 Set Vref, RX VrefLevel [Byte0]: 39
8315 01:34:33.317997 [Byte1]: 39
8316 01:34:33.322378
8317 01:34:33.322951 Set Vref, RX VrefLevel [Byte0]: 40
8318 01:34:33.325609 [Byte1]: 40
8319 01:34:33.330113
8320 01:34:33.330576 Set Vref, RX VrefLevel [Byte0]: 41
8321 01:34:33.333395 [Byte1]: 41
8322 01:34:33.338213
8323 01:34:33.338729 Set Vref, RX VrefLevel [Byte0]: 42
8324 01:34:33.341731 [Byte1]: 42
8325 01:34:33.345694
8326 01:34:33.346197 Set Vref, RX VrefLevel [Byte0]: 43
8327 01:34:33.349233 [Byte1]: 43
8328 01:34:33.353400
8329 01:34:33.353900 Set Vref, RX VrefLevel [Byte0]: 44
8330 01:34:33.356477 [Byte1]: 44
8331 01:34:33.361328
8332 01:34:33.361833 Set Vref, RX VrefLevel [Byte0]: 45
8333 01:34:33.364492 [Byte1]: 45
8334 01:34:33.368463
8335 01:34:33.368880 Set Vref, RX VrefLevel [Byte0]: 46
8336 01:34:33.372052 [Byte1]: 46
8337 01:34:33.376260
8338 01:34:33.376823 Set Vref, RX VrefLevel [Byte0]: 47
8339 01:34:33.379659 [Byte1]: 47
8340 01:34:33.384082
8341 01:34:33.384626 Set Vref, RX VrefLevel [Byte0]: 48
8342 01:34:33.387113 [Byte1]: 48
8343 01:34:33.391172
8344 01:34:33.391625 Set Vref, RX VrefLevel [Byte0]: 49
8345 01:34:33.394772 [Byte1]: 49
8346 01:34:33.399278
8347 01:34:33.399824 Set Vref, RX VrefLevel [Byte0]: 50
8348 01:34:33.402720 [Byte1]: 50
8349 01:34:33.406809
8350 01:34:33.407353 Set Vref, RX VrefLevel [Byte0]: 51
8351 01:34:33.410020 [Byte1]: 51
8352 01:34:33.414725
8353 01:34:33.415270 Set Vref, RX VrefLevel [Byte0]: 52
8354 01:34:33.417670 [Byte1]: 52
8355 01:34:33.421838
8356 01:34:33.422295 Set Vref, RX VrefLevel [Byte0]: 53
8357 01:34:33.425564 [Byte1]: 53
8358 01:34:33.429650
8359 01:34:33.430109 Set Vref, RX VrefLevel [Byte0]: 54
8360 01:34:33.432880 [Byte1]: 54
8361 01:34:33.437419
8362 01:34:33.438103 Set Vref, RX VrefLevel [Byte0]: 55
8363 01:34:33.440817 [Byte1]: 55
8364 01:34:33.445193
8365 01:34:33.445801 Set Vref, RX VrefLevel [Byte0]: 56
8366 01:34:33.448540 [Byte1]: 56
8367 01:34:33.452685
8368 01:34:33.453260 Set Vref, RX VrefLevel [Byte0]: 57
8369 01:34:33.455985 [Byte1]: 57
8370 01:34:33.460615
8371 01:34:33.461178 Set Vref, RX VrefLevel [Byte0]: 58
8372 01:34:33.463844 [Byte1]: 58
8373 01:34:33.468013
8374 01:34:33.468487 Set Vref, RX VrefLevel [Byte0]: 59
8375 01:34:33.471502 [Byte1]: 59
8376 01:34:33.476003
8377 01:34:33.476570 Set Vref, RX VrefLevel [Byte0]: 60
8378 01:34:33.478736 [Byte1]: 60
8379 01:34:33.483294
8380 01:34:33.483869 Set Vref, RX VrefLevel [Byte0]: 61
8381 01:34:33.486770 [Byte1]: 61
8382 01:34:33.490768
8383 01:34:33.491228 Set Vref, RX VrefLevel [Byte0]: 62
8384 01:34:33.494122 [Byte1]: 62
8385 01:34:33.499007
8386 01:34:33.499556 Set Vref, RX VrefLevel [Byte0]: 63
8387 01:34:33.501828 [Byte1]: 63
8388 01:34:33.506567
8389 01:34:33.507117 Set Vref, RX VrefLevel [Byte0]: 64
8390 01:34:33.509915 [Byte1]: 64
8391 01:34:33.513918
8392 01:34:33.514372 Set Vref, RX VrefLevel [Byte0]: 65
8393 01:34:33.517368 [Byte1]: 65
8394 01:34:33.521746
8395 01:34:33.522299 Set Vref, RX VrefLevel [Byte0]: 66
8396 01:34:33.524713 [Byte1]: 66
8397 01:34:33.529482
8398 01:34:33.530033 Set Vref, RX VrefLevel [Byte0]: 67
8399 01:34:33.532638 [Byte1]: 67
8400 01:34:33.536813
8401 01:34:33.537398 Set Vref, RX VrefLevel [Byte0]: 68
8402 01:34:33.540179 [Byte1]: 68
8403 01:34:33.544915
8404 01:34:33.545506 Set Vref, RX VrefLevel [Byte0]: 69
8405 01:34:33.547799 [Byte1]: 69
8406 01:34:33.552041
8407 01:34:33.552598 Set Vref, RX VrefLevel [Byte0]: 70
8408 01:34:33.555315 [Byte1]: 70
8409 01:34:33.560076
8410 01:34:33.560628 Set Vref, RX VrefLevel [Byte0]: 71
8411 01:34:33.563275 [Byte1]: 71
8412 01:34:33.567515
8413 01:34:33.568077 Set Vref, RX VrefLevel [Byte0]: 72
8414 01:34:33.570743 [Byte1]: 72
8415 01:34:33.574844
8416 01:34:33.575319 Set Vref, RX VrefLevel [Byte0]: 73
8417 01:34:33.578553 [Byte1]: 73
8418 01:34:33.582799
8419 01:34:33.583365 Set Vref, RX VrefLevel [Byte0]: 74
8420 01:34:33.586052 [Byte1]: 74
8421 01:34:33.590461
8422 01:34:33.590949 Set Vref, RX VrefLevel [Byte0]: 75
8423 01:34:33.593474 [Byte1]: 75
8424 01:34:33.598035
8425 01:34:33.598594 Set Vref, RX VrefLevel [Byte0]: 76
8426 01:34:33.601497 [Byte1]: 76
8427 01:34:33.605667
8428 01:34:33.606235 Final RX Vref Byte 0 = 59 to rank0
8429 01:34:33.609234 Final RX Vref Byte 1 = 53 to rank0
8430 01:34:33.612367 Final RX Vref Byte 0 = 59 to rank1
8431 01:34:33.615916 Final RX Vref Byte 1 = 53 to rank1==
8432 01:34:33.618650 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 01:34:33.625374 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8434 01:34:33.625941 ==
8435 01:34:33.626422 DQS Delay:
8436 01:34:33.628643 DQS0 = 0, DQS1 = 0
8437 01:34:33.629114 DQM Delay:
8438 01:34:33.629628 DQM0 = 129, DQM1 = 123
8439 01:34:33.632267 DQ Delay:
8440 01:34:33.635517 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
8441 01:34:33.638643 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8442 01:34:33.642036 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8443 01:34:33.645519 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8444 01:34:33.646082
8445 01:34:33.646568
8446 01:34:33.647019
8447 01:34:33.648475 [DramC_TX_OE_Calibration] TA2
8448 01:34:33.651739 Original DQ_B0 (3 6) =30, OEN = 27
8449 01:34:33.655257 Original DQ_B1 (3 6) =30, OEN = 27
8450 01:34:33.658529 24, 0x0, End_B0=24 End_B1=24
8451 01:34:33.659101 25, 0x0, End_B0=25 End_B1=25
8452 01:34:33.662146 26, 0x0, End_B0=26 End_B1=26
8453 01:34:33.665356 27, 0x0, End_B0=27 End_B1=27
8454 01:34:33.668810 28, 0x0, End_B0=28 End_B1=28
8455 01:34:33.671877 29, 0x0, End_B0=29 End_B1=29
8456 01:34:33.672451 30, 0x0, End_B0=30 End_B1=30
8457 01:34:33.675033 31, 0x4141, End_B0=30 End_B1=30
8458 01:34:33.678482 Byte0 end_step=30 best_step=27
8459 01:34:33.681690 Byte1 end_step=30 best_step=27
8460 01:34:33.685180 Byte0 TX OE(2T, 0.5T) = (3, 3)
8461 01:34:33.688277 Byte1 TX OE(2T, 0.5T) = (3, 3)
8462 01:34:33.688822
8463 01:34:33.689184
8464 01:34:33.694832 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8465 01:34:33.698239 CH1 RK0: MR19=303, MR18=2626
8466 01:34:33.704859 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8467 01:34:33.705458
8468 01:34:33.708507 ----->DramcWriteLeveling(PI) begin...
8469 01:34:33.709064 ==
8470 01:34:33.711689 Dram Type= 6, Freq= 0, CH_1, rank 1
8471 01:34:33.714804 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8472 01:34:33.715363 ==
8473 01:34:33.718192 Write leveling (Byte 0): 23 => 23
8474 01:34:33.721730 Write leveling (Byte 1): 22 => 22
8475 01:34:33.724875 DramcWriteLeveling(PI) end<-----
8476 01:34:33.725667
8477 01:34:33.726054 ==
8478 01:34:33.727773 Dram Type= 6, Freq= 0, CH_1, rank 1
8479 01:34:33.731456 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8480 01:34:33.732015 ==
8481 01:34:33.734785 [Gating] SW mode calibration
8482 01:34:33.741508 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8483 01:34:33.747589 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8484 01:34:33.751222 0 12 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8485 01:34:33.757792 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8486 01:34:33.760811 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8487 01:34:33.764360 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8488 01:34:33.770862 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8489 01:34:33.774241 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8490 01:34:33.777332 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8491 01:34:33.784083 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8492 01:34:33.787488 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8493 01:34:33.790566 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8494 01:34:33.797102 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8495 01:34:33.800648 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8496 01:34:33.803986 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8497 01:34:33.810572 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8498 01:34:33.814131 0 13 24 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8499 01:34:33.817430 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8500 01:34:33.823965 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8501 01:34:33.827290 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8502 01:34:33.830737 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8503 01:34:33.837110 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8504 01:34:33.840470 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8505 01:34:33.843682 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8506 01:34:33.849976 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8507 01:34:33.853554 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8508 01:34:33.856474 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8509 01:34:33.863447 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 01:34:33.866509 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 01:34:33.869768 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 01:34:33.876428 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 01:34:33.879749 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 01:34:33.882941 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 01:34:33.889663 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 01:34:33.892932 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 01:34:33.896639 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 01:34:33.902951 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 01:34:33.906015 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 01:34:33.909491 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 01:34:33.916026 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 01:34:33.919440 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8523 01:34:33.922598 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8524 01:34:33.926165 Total UI for P1: 0, mck2ui 16
8525 01:34:33.929203 best dqsien dly found for B0: ( 1, 0, 24)
8526 01:34:33.935907 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8527 01:34:33.939406 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8528 01:34:33.942430 Total UI for P1: 0, mck2ui 16
8529 01:34:33.946152 best dqsien dly found for B1: ( 1, 1, 0)
8530 01:34:33.949147 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8531 01:34:33.952106 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8532 01:34:33.952569
8533 01:34:33.955813 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8534 01:34:33.959380 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8535 01:34:33.962022 [Gating] SW calibration Done
8536 01:34:33.962484 ==
8537 01:34:33.965670 Dram Type= 6, Freq= 0, CH_1, rank 1
8538 01:34:33.968724 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8539 01:34:33.972272 ==
8540 01:34:33.972822 RX Vref Scan: 0
8541 01:34:33.973187
8542 01:34:33.975461 RX Vref 0 -> 0, step: 1
8543 01:34:33.975940
8544 01:34:33.976305 RX Delay 0 -> 252, step: 8
8545 01:34:33.982243 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8546 01:34:33.985286 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8547 01:34:33.988689 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8548 01:34:33.991921 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8549 01:34:33.995222 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8550 01:34:34.001960 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8551 01:34:34.005426 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8552 01:34:34.008639 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8553 01:34:34.011759 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8554 01:34:34.014962 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8555 01:34:34.021805 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8556 01:34:34.025222 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8557 01:34:34.028554 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8558 01:34:34.031856 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8559 01:34:34.038218 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8560 01:34:34.041490 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8561 01:34:34.042046 ==
8562 01:34:34.044913 Dram Type= 6, Freq= 0, CH_1, rank 1
8563 01:34:34.048333 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8564 01:34:34.048894 ==
8565 01:34:34.051443 DQS Delay:
8566 01:34:34.051994 DQS0 = 0, DQS1 = 0
8567 01:34:34.052361 DQM Delay:
8568 01:34:34.055063 DQM0 = 131, DQM1 = 125
8569 01:34:34.055614 DQ Delay:
8570 01:34:34.057976 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8571 01:34:34.061583 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8572 01:34:34.067969 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8573 01:34:34.071534 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8574 01:34:34.072094
8575 01:34:34.072464
8576 01:34:34.072802 ==
8577 01:34:34.074251 Dram Type= 6, Freq= 0, CH_1, rank 1
8578 01:34:34.077781 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8579 01:34:34.078355 ==
8580 01:34:34.078727
8581 01:34:34.079105
8582 01:34:34.080843 TX Vref Scan disable
8583 01:34:34.084667 == TX Byte 0 ==
8584 01:34:34.087670 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8585 01:34:34.090614 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8586 01:34:34.094028 == TX Byte 1 ==
8587 01:34:34.097344 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8588 01:34:34.100855 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8589 01:34:34.101456 ==
8590 01:34:34.104171 Dram Type= 6, Freq= 0, CH_1, rank 1
8591 01:34:34.107607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8592 01:34:34.110340 ==
8593 01:34:34.122808
8594 01:34:34.125845 TX Vref early break, caculate TX vref
8595 01:34:34.129076 TX Vref=16, minBit 0, minWin=22, winSum=377
8596 01:34:34.132769 TX Vref=18, minBit 0, minWin=22, winSum=382
8597 01:34:34.135858 TX Vref=20, minBit 0, minWin=23, winSum=387
8598 01:34:34.139084 TX Vref=22, minBit 5, minWin=23, winSum=402
8599 01:34:34.142506 TX Vref=24, minBit 3, minWin=24, winSum=409
8600 01:34:34.148788 TX Vref=26, minBit 0, minWin=24, winSum=415
8601 01:34:34.152326 TX Vref=28, minBit 0, minWin=24, winSum=416
8602 01:34:34.155623 TX Vref=30, minBit 0, minWin=24, winSum=412
8603 01:34:34.158967 TX Vref=32, minBit 0, minWin=23, winSum=402
8604 01:34:34.162133 TX Vref=34, minBit 0, minWin=22, winSum=397
8605 01:34:34.165468 TX Vref=36, minBit 0, minWin=21, winSum=387
8606 01:34:34.172123 [TxChooseVref] Worse bit 0, Min win 24, Win sum 416, Final Vref 28
8607 01:34:34.172681
8608 01:34:34.175458 Final TX Range 0 Vref 28
8609 01:34:34.176070
8610 01:34:34.176453 ==
8611 01:34:34.178677 Dram Type= 6, Freq= 0, CH_1, rank 1
8612 01:34:34.181964 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8613 01:34:34.182518 ==
8614 01:34:34.185269
8615 01:34:34.185760
8616 01:34:34.186126 TX Vref Scan disable
8617 01:34:34.192098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8618 01:34:34.192654 == TX Byte 0 ==
8619 01:34:34.195002 u2DelayCellOfst[0]=18 cells (5 PI)
8620 01:34:34.198253 u2DelayCellOfst[1]=10 cells (3 PI)
8621 01:34:34.201889 u2DelayCellOfst[2]=0 cells (0 PI)
8622 01:34:34.205320 u2DelayCellOfst[3]=7 cells (2 PI)
8623 01:34:34.208418 u2DelayCellOfst[4]=7 cells (2 PI)
8624 01:34:34.211828 u2DelayCellOfst[5]=14 cells (4 PI)
8625 01:34:34.214828 u2DelayCellOfst[6]=14 cells (4 PI)
8626 01:34:34.218283 u2DelayCellOfst[7]=3 cells (1 PI)
8627 01:34:34.221689 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8628 01:34:34.225195 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8629 01:34:34.228220 == TX Byte 1 ==
8630 01:34:34.231123 u2DelayCellOfst[8]=0 cells (0 PI)
8631 01:34:34.235047 u2DelayCellOfst[9]=7 cells (2 PI)
8632 01:34:34.238200 u2DelayCellOfst[10]=14 cells (4 PI)
8633 01:34:34.241593 u2DelayCellOfst[11]=7 cells (2 PI)
8634 01:34:34.242147 u2DelayCellOfst[12]=18 cells (5 PI)
8635 01:34:34.244876 u2DelayCellOfst[13]=21 cells (6 PI)
8636 01:34:34.247827 u2DelayCellOfst[14]=21 cells (6 PI)
8637 01:34:34.251089 u2DelayCellOfst[15]=21 cells (6 PI)
8638 01:34:34.257987 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8639 01:34:34.261307 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8640 01:34:34.261825 DramC Write-DBI on
8641 01:34:34.264710 ==
8642 01:34:34.267862 Dram Type= 6, Freq= 0, CH_1, rank 1
8643 01:34:34.271396 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8644 01:34:34.271912 ==
8645 01:34:34.272243
8646 01:34:34.272549
8647 01:34:34.274178 TX Vref Scan disable
8648 01:34:34.274596 == TX Byte 0 ==
8649 01:34:34.281024 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8650 01:34:34.281598 == TX Byte 1 ==
8651 01:34:34.284475 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8652 01:34:34.287584 DramC Write-DBI off
8653 01:34:34.288092
8654 01:34:34.288424 [DATLAT]
8655 01:34:34.291407 Freq=1600, CH1 RK1
8656 01:34:34.291921
8657 01:34:34.292351 DATLAT Default: 0xe
8658 01:34:34.294347 0, 0xFFFF, sum = 0
8659 01:34:34.294773 1, 0xFFFF, sum = 0
8660 01:34:34.297182 2, 0xFFFF, sum = 0
8661 01:34:34.297647 3, 0xFFFF, sum = 0
8662 01:34:34.300761 4, 0xFFFF, sum = 0
8663 01:34:34.301277 5, 0xFFFF, sum = 0
8664 01:34:34.304314 6, 0xFFFF, sum = 0
8665 01:34:34.307774 7, 0xFFFF, sum = 0
8666 01:34:34.308293 8, 0xFFFF, sum = 0
8667 01:34:34.310466 9, 0xFFFF, sum = 0
8668 01:34:34.310892 10, 0xFFFF, sum = 0
8669 01:34:34.314283 11, 0xFFFF, sum = 0
8670 01:34:34.314797 12, 0xF7F, sum = 0
8671 01:34:34.317416 13, 0x0, sum = 1
8672 01:34:34.317842 14, 0x0, sum = 2
8673 01:34:34.320253 15, 0x0, sum = 3
8674 01:34:34.320676 16, 0x0, sum = 4
8675 01:34:34.321010 best_step = 14
8676 01:34:34.323975
8677 01:34:34.324483 ==
8678 01:34:34.327152 Dram Type= 6, Freq= 0, CH_1, rank 1
8679 01:34:34.330524 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8680 01:34:34.330947 ==
8681 01:34:34.331282 RX Vref Scan: 0
8682 01:34:34.331590
8683 01:34:34.334206 RX Vref 0 -> 0, step: 1
8684 01:34:34.334623
8685 01:34:34.337052 RX Delay 3 -> 252, step: 4
8686 01:34:34.340260 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8687 01:34:34.346900 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8688 01:34:34.350477 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8689 01:34:34.353616 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8690 01:34:34.357102 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8691 01:34:34.360240 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8692 01:34:34.363418 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8693 01:34:34.370006 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8694 01:34:34.373417 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8695 01:34:34.376475 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8696 01:34:34.380067 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8697 01:34:34.386633 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8698 01:34:34.390007 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8699 01:34:34.393399 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8700 01:34:34.396522 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8701 01:34:34.399690 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8702 01:34:34.403096 ==
8703 01:34:34.406357 Dram Type= 6, Freq= 0, CH_1, rank 1
8704 01:34:34.409639 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8705 01:34:34.410060 ==
8706 01:34:34.410392 DQS Delay:
8707 01:34:34.412926 DQS0 = 0, DQS1 = 0
8708 01:34:34.413383 DQM Delay:
8709 01:34:34.416430 DQM0 = 126, DQM1 = 122
8710 01:34:34.416847 DQ Delay:
8711 01:34:34.419802 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8712 01:34:34.423000 DQ4 =124, DQ5 =138, DQ6 =134, DQ7 =126
8713 01:34:34.426222 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8714 01:34:34.429800 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8715 01:34:34.430220
8716 01:34:34.430550
8717 01:34:34.430857
8718 01:34:34.432987 [DramC_TX_OE_Calibration] TA2
8719 01:34:34.436139 Original DQ_B0 (3 6) =30, OEN = 27
8720 01:34:34.439424 Original DQ_B1 (3 6) =30, OEN = 27
8721 01:34:34.443302 24, 0x0, End_B0=24 End_B1=24
8722 01:34:34.446187 25, 0x0, End_B0=25 End_B1=25
8723 01:34:34.446611 26, 0x0, End_B0=26 End_B1=26
8724 01:34:34.449541 27, 0x0, End_B0=27 End_B1=27
8725 01:34:34.452948 28, 0x0, End_B0=28 End_B1=28
8726 01:34:34.456010 29, 0x0, End_B0=29 End_B1=29
8727 01:34:34.459573 30, 0x0, End_B0=30 End_B1=30
8728 01:34:34.460085 31, 0x4141, End_B0=30 End_B1=30
8729 01:34:34.462904 Byte0 end_step=30 best_step=27
8730 01:34:34.466364 Byte1 end_step=30 best_step=27
8731 01:34:34.469248 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 01:34:34.472588 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 01:34:34.473006
8734 01:34:34.473377
8735 01:34:34.479694 [DQSOSCAuto] RK1, (LSB)MR18= 0x1818, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
8736 01:34:34.482356 CH1 RK1: MR19=303, MR18=1818
8737 01:34:34.489009 CH1_RK1: MR19=0x303, MR18=0x1818, DQSOSC=397, MR23=63, INC=23, DEC=15
8738 01:34:34.492495 [RxdqsGatingPostProcess] freq 1600
8739 01:34:34.498905 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8740 01:34:34.502514 Pre-setting of DQS Precalculation
8741 01:34:34.505672 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8742 01:34:34.512571 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8743 01:34:34.518930 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8744 01:34:34.519498
8745 01:34:34.521943
8746 01:34:34.522443 [Calibration Summary] 3200 Mbps
8747 01:34:34.525236 CH 0, Rank 0
8748 01:34:34.525726 SW Impedance : PASS
8749 01:34:34.528600 DUTY Scan : NO K
8750 01:34:34.532091 ZQ Calibration : PASS
8751 01:34:34.532506 Jitter Meter : NO K
8752 01:34:34.535348 CBT Training : PASS
8753 01:34:34.538521 Write leveling : PASS
8754 01:34:34.538997 RX DQS gating : PASS
8755 01:34:34.541954 RX DQ/DQS(RDDQC) : PASS
8756 01:34:34.545384 TX DQ/DQS : PASS
8757 01:34:34.545903 RX DATLAT : PASS
8758 01:34:34.548657 RX DQ/DQS(Engine): PASS
8759 01:34:34.552135 TX OE : PASS
8760 01:34:34.552647 All Pass.
8761 01:34:34.552979
8762 01:34:34.553318 CH 0, Rank 1
8763 01:34:34.555087 SW Impedance : PASS
8764 01:34:34.558436 DUTY Scan : NO K
8765 01:34:34.558850 ZQ Calibration : PASS
8766 01:34:34.562203 Jitter Meter : NO K
8767 01:34:34.565268 CBT Training : PASS
8768 01:34:34.565817 Write leveling : PASS
8769 01:34:34.568594 RX DQS gating : PASS
8770 01:34:34.571619 RX DQ/DQS(RDDQC) : PASS
8771 01:34:34.572037 TX DQ/DQS : PASS
8772 01:34:34.574956 RX DATLAT : PASS
8773 01:34:34.575374 RX DQ/DQS(Engine): PASS
8774 01:34:34.578456 TX OE : PASS
8775 01:34:34.578980 All Pass.
8776 01:34:34.579319
8777 01:34:34.581739 CH 1, Rank 0
8778 01:34:34.582272 SW Impedance : PASS
8779 01:34:34.584846 DUTY Scan : NO K
8780 01:34:34.588264 ZQ Calibration : PASS
8781 01:34:34.588681 Jitter Meter : NO K
8782 01:34:34.591833 CBT Training : PASS
8783 01:34:34.594820 Write leveling : PASS
8784 01:34:34.595234 RX DQS gating : PASS
8785 01:34:34.598902 RX DQ/DQS(RDDQC) : PASS
8786 01:34:34.601521 TX DQ/DQS : PASS
8787 01:34:34.601962 RX DATLAT : PASS
8788 01:34:34.605132 RX DQ/DQS(Engine): PASS
8789 01:34:34.608484 TX OE : PASS
8790 01:34:34.609008 All Pass.
8791 01:34:34.609390
8792 01:34:34.609710 CH 1, Rank 1
8793 01:34:34.611287 SW Impedance : PASS
8794 01:34:34.614563 DUTY Scan : NO K
8795 01:34:34.614980 ZQ Calibration : PASS
8796 01:34:34.618122 Jitter Meter : NO K
8797 01:34:34.621127 CBT Training : PASS
8798 01:34:34.621643 Write leveling : PASS
8799 01:34:34.624770 RX DQS gating : PASS
8800 01:34:34.627942 RX DQ/DQS(RDDQC) : PASS
8801 01:34:34.628365 TX DQ/DQS : PASS
8802 01:34:34.631039 RX DATLAT : PASS
8803 01:34:34.631454 RX DQ/DQS(Engine): PASS
8804 01:34:34.634556 TX OE : PASS
8805 01:34:34.635076 All Pass.
8806 01:34:34.635415
8807 01:34:34.637934 DramC Write-DBI on
8808 01:34:34.640983 PER_BANK_REFRESH: Hybrid Mode
8809 01:34:34.641538 TX_TRACKING: ON
8810 01:34:34.651024 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8811 01:34:34.658062 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8812 01:34:34.667635 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8813 01:34:34.670869 [FAST_K] Save calibration result to emmc
8814 01:34:34.674216 sync common calibartion params.
8815 01:34:34.674779 sync cbt_mode0:0, 1:0
8816 01:34:34.677331 dram_init: ddr_geometry: 0
8817 01:34:34.680817 dram_init: ddr_geometry: 0
8818 01:34:34.681423 dram_init: ddr_geometry: 0
8819 01:34:34.684251 0:dram_rank_size:80000000
8820 01:34:34.687386 1:dram_rank_size:80000000
8821 01:34:34.690594 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8822 01:34:34.693975 DFS_SHUFFLE_HW_MODE: ON
8823 01:34:34.697157 dramc_set_vcore_voltage set vcore to 725000
8824 01:34:34.700900 Read voltage for 1600, 0
8825 01:34:34.701639 Vio18 = 0
8826 01:34:34.703978 Vcore = 725000
8827 01:34:34.704536 Vdram = 0
8828 01:34:34.704901 Vddq = 0
8829 01:34:34.705236 Vmddr = 0
8830 01:34:34.707181 switch to 3200 Mbps bootup
8831 01:34:34.710451 [DramcRunTimeConfig]
8832 01:34:34.711011 PHYPLL
8833 01:34:34.713833 DPM_CONTROL_AFTERK: ON
8834 01:34:34.714373 PER_BANK_REFRESH: ON
8835 01:34:34.716891 REFRESH_OVERHEAD_REDUCTION: ON
8836 01:34:34.720213 CMD_PICG_NEW_MODE: OFF
8837 01:34:34.720715 XRTWTW_NEW_MODE: ON
8838 01:34:34.723492 XRTRTR_NEW_MODE: ON
8839 01:34:34.723930 TX_TRACKING: ON
8840 01:34:34.726957 RDSEL_TRACKING: OFF
8841 01:34:34.730073 DQS Precalculation for DVFS: ON
8842 01:34:34.730592 RX_TRACKING: OFF
8843 01:34:34.733475 HW_GATING DBG: ON
8844 01:34:34.733901 ZQCS_ENABLE_LP4: ON
8845 01:34:34.736698 RX_PICG_NEW_MODE: ON
8846 01:34:34.737117 TX_PICG_NEW_MODE: ON
8847 01:34:34.740432 ENABLE_RX_DCM_DPHY: ON
8848 01:34:34.743483 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8849 01:34:34.746861 DUMMY_READ_FOR_TRACKING: OFF
8850 01:34:34.747379 !!! SPM_CONTROL_AFTERK: OFF
8851 01:34:34.749912 !!! SPM could not control APHY
8852 01:34:34.753441 IMPEDANCE_TRACKING: ON
8853 01:34:34.753958 TEMP_SENSOR: ON
8854 01:34:34.756797 HW_SAVE_FOR_SR: OFF
8855 01:34:34.760140 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8856 01:34:34.763146 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8857 01:34:34.763570 Read ODT Tracking: ON
8858 01:34:34.766519 Refresh Rate DeBounce: ON
8859 01:34:34.769881 DFS_NO_QUEUE_FLUSH: ON
8860 01:34:34.773484 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8861 01:34:34.776545 ENABLE_DFS_RUNTIME_MRW: OFF
8862 01:34:34.777077 DDR_RESERVE_NEW_MODE: ON
8863 01:34:34.779752 MR_CBT_SWITCH_FREQ: ON
8864 01:34:34.782909 =========================
8865 01:34:34.799912 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8866 01:34:34.803356 dram_init: ddr_geometry: 0
8867 01:34:34.821453 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8868 01:34:34.824948 dram_init: dram init end (result: 0)
8869 01:34:34.831169 DRAM-K: Full calibration passed in 23439 msecs
8870 01:34:34.834390 MRC: failed to locate region type 0.
8871 01:34:34.834851 DRAM rank0 size:0x80000000,
8872 01:34:34.837902 DRAM rank1 size=0x80000000
8873 01:34:34.847775 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8874 01:34:34.854338 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8875 01:34:34.860905 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8876 01:34:34.867690 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8877 01:34:34.871173 DRAM rank0 size:0x80000000,
8878 01:34:34.874310 DRAM rank1 size=0x80000000
8879 01:34:34.874870 CBMEM:
8880 01:34:34.877658 IMD: root @ 0xfffff000 254 entries.
8881 01:34:34.880882 IMD: root @ 0xffffec00 62 entries.
8882 01:34:34.883896 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8883 01:34:34.887664 WARNING: RO_VPD is uninitialized or empty.
8884 01:34:34.893654 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8885 01:34:34.901038 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8886 01:34:34.913942 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8887 01:34:34.925235 BS: romstage times (exec / console): total (unknown) / 22972 ms
8888 01:34:34.925855
8889 01:34:34.926222
8890 01:34:34.935081 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8891 01:34:34.938271 ARM64: Exception handlers installed.
8892 01:34:34.941535 ARM64: Testing exception
8893 01:34:34.944835 ARM64: Done test exception
8894 01:34:34.945433 Enumerating buses...
8895 01:34:34.948343 Show all devs... Before device enumeration.
8896 01:34:34.951239 Root Device: enabled 1
8897 01:34:34.954520 CPU_CLUSTER: 0: enabled 1
8898 01:34:34.954980 CPU: 00: enabled 1
8899 01:34:34.957842 Compare with tree...
8900 01:34:34.958461 Root Device: enabled 1
8901 01:34:34.961345 CPU_CLUSTER: 0: enabled 1
8902 01:34:34.964490 CPU: 00: enabled 1
8903 01:34:34.964950 Root Device scanning...
8904 01:34:34.968041 scan_static_bus for Root Device
8905 01:34:34.971201 CPU_CLUSTER: 0 enabled
8906 01:34:34.974672 scan_static_bus for Root Device done
8907 01:34:34.977880 scan_bus: bus Root Device finished in 8 msecs
8908 01:34:34.978345 done
8909 01:34:34.984391 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8910 01:34:34.987830 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8911 01:34:34.994133 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8912 01:34:35.000709 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8913 01:34:35.001273 Allocating resources...
8914 01:34:35.004298 Reading resources...
8915 01:34:35.008127 Root Device read_resources bus 0 link: 0
8916 01:34:35.010678 DRAM rank0 size:0x80000000,
8917 01:34:35.011232 DRAM rank1 size=0x80000000
8918 01:34:35.016912 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8919 01:34:35.017398 CPU: 00 missing read_resources
8920 01:34:35.023773 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8921 01:34:35.027547 Root Device read_resources bus 0 link: 0 done
8922 01:34:35.030668 Done reading resources.
8923 01:34:35.033742 Show resources in subtree (Root Device)...After reading.
8924 01:34:35.037017 Root Device child on link 0 CPU_CLUSTER: 0
8925 01:34:35.040434 CPU_CLUSTER: 0 child on link 0 CPU: 00
8926 01:34:35.050207 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8927 01:34:35.050786 CPU: 00
8928 01:34:35.053840 Root Device assign_resources, bus 0 link: 0
8929 01:34:35.056803 CPU_CLUSTER: 0 missing set_resources
8930 01:34:35.063389 Root Device assign_resources, bus 0 link: 0 done
8931 01:34:35.063942 Done setting resources.
8932 01:34:35.069958 Show resources in subtree (Root Device)...After assigning values.
8933 01:34:35.073373 Root Device child on link 0 CPU_CLUSTER: 0
8934 01:34:35.076694 CPU_CLUSTER: 0 child on link 0 CPU: 00
8935 01:34:35.086280 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8936 01:34:35.086843 CPU: 00
8937 01:34:35.089964 Done allocating resources.
8938 01:34:35.096280 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8939 01:34:35.096831 Enabling resources...
8940 01:34:35.099864 done.
8941 01:34:35.102709 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8942 01:34:35.105913 Initializing devices...
8943 01:34:35.106366 Root Device init
8944 01:34:35.109186 init hardware done!
8945 01:34:35.109674 0x00000018: ctrlr->caps
8946 01:34:35.112965 52.000 MHz: ctrlr->f_max
8947 01:34:35.116242 0.400 MHz: ctrlr->f_min
8948 01:34:35.116711 0x40ff8080: ctrlr->voltages
8949 01:34:35.119576 sclk: 390625
8950 01:34:35.120126 Bus Width = 1
8951 01:34:35.122437 sclk: 390625
8952 01:34:35.122893 Bus Width = 1
8953 01:34:35.125963 Early init status = 3
8954 01:34:35.129057 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8955 01:34:35.132969 in-header: 03 fc 00 00 01 00 00 00
8956 01:34:35.136800 in-data: 00
8957 01:34:35.139228 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8958 01:34:35.144989 in-header: 03 fd 00 00 00 00 00 00
8959 01:34:35.148388 in-data:
8960 01:34:35.151469 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8961 01:34:35.156065 in-header: 03 fc 00 00 01 00 00 00
8962 01:34:35.159721 in-data: 00
8963 01:34:35.162209 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8964 01:34:35.168369 in-header: 03 fd 00 00 00 00 00 00
8965 01:34:35.171549 in-data:
8966 01:34:35.174928 [SSUSB] Setting up USB HOST controller...
8967 01:34:35.178417 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8968 01:34:35.181709 [SSUSB] phy power-on done.
8969 01:34:35.184683 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8970 01:34:35.191389 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8971 01:34:35.194588 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8972 01:34:35.201418 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8973 01:34:35.208067 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8974 01:34:35.214586 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8975 01:34:35.221440 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8976 01:34:35.227883 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8977 01:34:35.231234 SPM: binary array size = 0x9dc
8978 01:34:35.234217 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8979 01:34:35.241105 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8980 01:34:35.247616 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8981 01:34:35.254077 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8982 01:34:35.257170 configure_display: Starting display init
8983 01:34:35.291478 anx7625_power_on_init: Init interface.
8984 01:34:35.294814 anx7625_disable_pd_protocol: Disabled PD feature.
8985 01:34:35.298174 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8986 01:34:35.325759 anx7625_start_dp_work: Secure OCM version=00
8987 01:34:35.329127 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8988 01:34:35.344051 sp_tx_get_edid_block: EDID Block = 1
8989 01:34:35.446669 Extracted contents:
8990 01:34:35.449927 header: 00 ff ff ff ff ff ff 00
8991 01:34:35.452995 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8992 01:34:35.456462 version: 01 04
8993 01:34:35.459993 basic params: 95 1f 11 78 0a
8994 01:34:35.463332 chroma info: 76 90 94 55 54 90 27 21 50 54
8995 01:34:35.466179 established: 00 00 00
8996 01:34:35.473179 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8997 01:34:35.479316 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8998 01:34:35.482586 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8999 01:34:35.489670 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9000 01:34:35.496130 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9001 01:34:35.499237 extensions: 00
9002 01:34:35.499706 checksum: fb
9003 01:34:35.500174
9004 01:34:35.505808 Manufacturer: IVO Model 57d Serial Number 0
9005 01:34:35.506279 Made week 0 of 2020
9006 01:34:35.508999 EDID version: 1.4
9007 01:34:35.509530 Digital display
9008 01:34:35.512630 6 bits per primary color channel
9009 01:34:35.513197 DisplayPort interface
9010 01:34:35.515552 Maximum image size: 31 cm x 17 cm
9011 01:34:35.518982 Gamma: 220%
9012 01:34:35.519436 Check DPMS levels
9013 01:34:35.522420 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9014 01:34:35.529350 First detailed timing is preferred timing
9015 01:34:35.529922 Established timings supported:
9016 01:34:35.532141 Standard timings supported:
9017 01:34:35.535640 Detailed timings
9018 01:34:35.538693 Hex of detail: 383680a07038204018303c0035ae10000019
9019 01:34:35.545387 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9020 01:34:35.548634 0780 0798 07c8 0820 hborder 0
9021 01:34:35.552218 0438 043b 0447 0458 vborder 0
9022 01:34:35.555366 -hsync -vsync
9023 01:34:35.555828 Did detailed timing
9024 01:34:35.561903 Hex of detail: 000000000000000000000000000000000000
9025 01:34:35.565235 Manufacturer-specified data, tag 0
9026 01:34:35.568868 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9027 01:34:35.571626 ASCII string: InfoVision
9028 01:34:35.575094 Hex of detail: 000000fe00523134304e574635205248200a
9029 01:34:35.578482 ASCII string: R140NWF5 RH
9030 01:34:35.578939 Checksum
9031 01:34:35.581802 Checksum: 0xfb (valid)
9032 01:34:35.584912 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9033 01:34:35.588329 DSI data_rate: 832800000 bps
9034 01:34:35.594863 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9035 01:34:35.598104 anx7625_parse_edid: pixelclock(138800).
9036 01:34:35.601323 hactive(1920), hsync(48), hfp(24), hbp(88)
9037 01:34:35.604713 vactive(1080), vsync(12), vfp(3), vbp(17)
9038 01:34:35.608043 anx7625_dsi_config: config dsi.
9039 01:34:35.614317 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9040 01:34:35.628545 anx7625_dsi_config: success to config DSI
9041 01:34:35.631732 anx7625_dp_start: MIPI phy setup OK.
9042 01:34:35.635036 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9043 01:34:35.638341 mtk_ddp_mode_set invalid vrefresh 60
9044 01:34:35.641473 main_disp_path_setup
9045 01:34:35.641888 ovl_layer_smi_id_en
9046 01:34:35.644740 ovl_layer_smi_id_en
9047 01:34:35.645152 ccorr_config
9048 01:34:35.645519 aal_config
9049 01:34:35.648557 gamma_config
9050 01:34:35.649076 postmask_config
9051 01:34:35.651424 dither_config
9052 01:34:35.654883 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9053 01:34:35.661358 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9054 01:34:35.664801 Root Device init finished in 554 msecs
9055 01:34:35.668616 CPU_CLUSTER: 0 init
9056 01:34:35.674966 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9057 01:34:35.681392 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9058 01:34:35.681840 APU_MBOX 0x190000b0 = 0x10001
9059 01:34:35.684698 APU_MBOX 0x190001b0 = 0x10001
9060 01:34:35.688215 APU_MBOX 0x190005b0 = 0x10001
9061 01:34:35.691330 APU_MBOX 0x190006b0 = 0x10001
9062 01:34:35.697665 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9063 01:34:35.707534 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9064 01:34:35.719819 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9065 01:34:35.726534 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9066 01:34:35.738187 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9067 01:34:35.747461 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9068 01:34:35.750394 CPU_CLUSTER: 0 init finished in 81 msecs
9069 01:34:35.753858 Devices initialized
9070 01:34:35.757045 Show all devs... After init.
9071 01:34:35.757691 Root Device: enabled 1
9072 01:34:35.760520 CPU_CLUSTER: 0: enabled 1
9073 01:34:35.763877 CPU: 00: enabled 1
9074 01:34:35.766761 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9075 01:34:35.770257 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9076 01:34:35.773555 ELOG: NV offset 0x57f000 size 0x1000
9077 01:34:35.780217 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9078 01:34:35.787076 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9079 01:34:35.790342 ELOG: Event(17) added with size 13 at 2024-06-05 01:34:35 UTC
9080 01:34:35.793759 out: cmd=0x121: 03 db 21 01 00 00 00 00
9081 01:34:35.798518 in-header: 03 da 00 00 2c 00 00 00
9082 01:34:35.811718 in-data: 89 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9083 01:34:35.818096 ELOG: Event(A1) added with size 10 at 2024-06-05 01:34:35 UTC
9084 01:34:35.824643 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9085 01:34:35.831522 ELOG: Event(A0) added with size 9 at 2024-06-05 01:34:35 UTC
9086 01:34:35.834781 elog_add_boot_reason: Logged dev mode boot
9087 01:34:35.838272 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9088 01:34:35.841682 Finalize devices...
9089 01:34:35.842278 Devices finalized
9090 01:34:35.848123 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9091 01:34:35.852190 Writing coreboot table at 0xffe64000
9092 01:34:35.854565 0. 000000000010a000-0000000000113fff: RAMSTAGE
9093 01:34:35.858250 1. 0000000040000000-00000000400fffff: RAM
9094 01:34:35.861388 2. 0000000040100000-000000004032afff: RAMSTAGE
9095 01:34:35.868067 3. 000000004032b000-00000000545fffff: RAM
9096 01:34:35.871177 4. 0000000054600000-000000005465ffff: BL31
9097 01:34:35.874758 5. 0000000054660000-00000000ffe63fff: RAM
9098 01:34:35.881330 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9099 01:34:35.884327 7. 0000000100000000-000000013fffffff: RAM
9100 01:34:35.884893 Passing 5 GPIOs to payload:
9101 01:34:35.890735 NAME | PORT | POLARITY | VALUE
9102 01:34:35.894098 EC in RW | 0x000000aa | low | undefined
9103 01:34:35.901279 EC interrupt | 0x00000005 | low | undefined
9104 01:34:35.904231 TPM interrupt | 0x000000ab | high | undefined
9105 01:34:35.910870 SD card detect | 0x00000011 | high | undefined
9106 01:34:35.914182 speaker enable | 0x00000093 | high | undefined
9107 01:34:35.917517 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9108 01:34:35.920830 in-header: 03 f8 00 00 02 00 00 00
9109 01:34:35.921434 in-data: 03 00
9110 01:34:35.924165 ADC[4]: Raw value=668590 ID=5
9111 01:34:35.927483 ADC[3]: Raw value=212917 ID=1
9112 01:34:35.930961 RAM Code: 0x51
9113 01:34:35.931519 ADC[6]: Raw value=74778 ID=0
9114 01:34:35.934177 ADC[5]: Raw value=211812 ID=1
9115 01:34:35.937455 SKU Code: 0x1
9116 01:34:35.940854 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c396
9117 01:34:35.944073 coreboot table: 964 bytes.
9118 01:34:35.947309 IMD ROOT 0. 0xfffff000 0x00001000
9119 01:34:35.950624 IMD SMALL 1. 0xffffe000 0x00001000
9120 01:34:35.953784 RO MCACHE 2. 0xffffc000 0x00001104
9121 01:34:35.957188 CONSOLE 3. 0xfff7c000 0x00080000
9122 01:34:35.960575 FMAP 4. 0xfff7b000 0x00000452
9123 01:34:35.963696 TIME STAMP 5. 0xfff7a000 0x00000910
9124 01:34:35.967061 VBOOT WORK 6. 0xfff66000 0x00014000
9125 01:34:35.970269 RAMOOPS 7. 0xffe66000 0x00100000
9126 01:34:35.973482 COREBOOT 8. 0xffe64000 0x00002000
9127 01:34:35.973942 IMD small region:
9128 01:34:35.976885 IMD ROOT 0. 0xffffec00 0x00000400
9129 01:34:35.980118 VPD 1. 0xffffeb80 0x0000006c
9130 01:34:35.986966 MMC STATUS 2. 0xffffeb60 0x00000004
9131 01:34:35.990198 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9132 01:34:35.993517 Probing TPM: done!
9133 01:34:35.997185 Connected to device vid:did:rid of 1ae0:0028:00
9134 01:34:36.007262 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9135 01:34:36.010240 Initialized TPM device CR50 revision 0
9136 01:34:36.014097 Checking cr50 for pending updates
9137 01:34:36.017668 Reading cr50 TPM mode
9138 01:34:36.026116 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9139 01:34:36.032834 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9140 01:34:36.072856 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9141 01:34:36.076662 Checking segment from ROM address 0x40100000
9142 01:34:36.079501 Checking segment from ROM address 0x4010001c
9143 01:34:36.086485 Loading segment from ROM address 0x40100000
9144 01:34:36.087036 code (compression=0)
9145 01:34:36.096261 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9146 01:34:36.103059 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9147 01:34:36.103640 it's not compressed!
9148 01:34:36.109529 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9149 01:34:36.112955 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9150 01:34:36.133192 Loading segment from ROM address 0x4010001c
9151 01:34:36.133798 Entry Point 0x80000000
9152 01:34:36.136429 Loaded segments
9153 01:34:36.140105 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9154 01:34:36.146748 Jumping to boot code at 0x80000000(0xffe64000)
9155 01:34:36.153347 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9156 01:34:36.160207 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9157 01:34:36.168177 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9158 01:34:36.171185 Checking segment from ROM address 0x40100000
9159 01:34:36.174620 Checking segment from ROM address 0x4010001c
9160 01:34:36.180967 Loading segment from ROM address 0x40100000
9161 01:34:36.181553 code (compression=1)
9162 01:34:36.187793 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9163 01:34:36.197414 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9164 01:34:36.197954 using LZMA
9165 01:34:36.206089 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9166 01:34:36.212932 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9167 01:34:36.216298 Loading segment from ROM address 0x4010001c
9168 01:34:36.216854 Entry Point 0x54601000
9169 01:34:36.219721 Loaded segments
9170 01:34:36.222577 NOTICE: MT8192 bl31_setup
9171 01:34:36.229867 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9172 01:34:36.233205 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9173 01:34:36.236155 WARNING: region 0:
9174 01:34:36.239743 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9175 01:34:36.240297 WARNING: region 1:
9176 01:34:36.246309 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9177 01:34:36.249576 WARNING: region 2:
9178 01:34:36.252919 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9179 01:34:36.256052 WARNING: region 3:
9180 01:34:36.259773 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9181 01:34:36.262586 WARNING: region 4:
9182 01:34:36.269477 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9183 01:34:36.270038 WARNING: region 5:
9184 01:34:36.272762 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9185 01:34:36.276241 WARNING: region 6:
9186 01:34:36.279504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9187 01:34:36.282584 WARNING: region 7:
9188 01:34:36.286043 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 01:34:36.292948 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9190 01:34:36.296290 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9191 01:34:36.299531 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9192 01:34:36.305746 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9193 01:34:36.309449 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9194 01:34:36.312874 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9195 01:34:36.319457 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9196 01:34:36.322937 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9197 01:34:36.329204 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9198 01:34:36.332593 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9199 01:34:36.335995 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9200 01:34:36.342440 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9201 01:34:36.345742 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9202 01:34:36.349463 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9203 01:34:36.356038 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9204 01:34:36.359387 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9205 01:34:36.366047 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9206 01:34:36.369447 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9207 01:34:36.372810 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9208 01:34:36.379536 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9209 01:34:36.382628 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9210 01:34:36.385948 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9211 01:34:36.392802 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9212 01:34:36.395964 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9213 01:34:36.402493 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9214 01:34:36.406212 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9215 01:34:36.409215 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9216 01:34:36.415863 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9217 01:34:36.419195 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9218 01:34:36.425962 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9219 01:34:36.429606 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9220 01:34:36.432602 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9221 01:34:36.439422 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9222 01:34:36.442434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9223 01:34:36.445868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9224 01:34:36.449605 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9225 01:34:36.456701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9226 01:34:36.459258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9227 01:34:36.462448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9228 01:34:36.466209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9229 01:34:36.472846 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9230 01:34:36.475884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9231 01:34:36.479538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9232 01:34:36.482627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9233 01:34:36.489450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9234 01:34:36.492845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9235 01:34:36.495632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9236 01:34:36.498912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9237 01:34:36.505742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9238 01:34:36.509110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9239 01:34:36.515644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9240 01:34:36.519173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9241 01:34:36.525597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9242 01:34:36.529244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9243 01:34:36.532429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9244 01:34:36.539009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9245 01:34:36.542389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9246 01:34:36.549191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9247 01:34:36.552473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9248 01:34:36.559656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9249 01:34:36.562577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9250 01:34:36.565675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9251 01:34:36.572652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9252 01:34:36.575853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9253 01:34:36.582608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9254 01:34:36.585918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9255 01:34:36.592580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9256 01:34:36.596023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9257 01:34:36.599223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9258 01:34:36.605821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9259 01:34:36.609430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9260 01:34:36.616081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9261 01:34:36.619414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9262 01:34:36.625961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9263 01:34:36.629266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9264 01:34:36.632910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9265 01:34:36.639129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9266 01:34:36.642501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9267 01:34:36.649374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9268 01:34:36.652422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9269 01:34:36.659060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9270 01:34:36.662410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9271 01:34:36.669227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9272 01:34:36.672101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9273 01:34:36.675561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9274 01:34:36.682301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9275 01:34:36.685508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9276 01:34:36.692531 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9277 01:34:36.695638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9278 01:34:36.702004 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9279 01:34:36.706044 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9280 01:34:36.709031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9281 01:34:36.715656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9282 01:34:36.718830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9283 01:34:36.725339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9284 01:34:36.729177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9285 01:34:36.735476 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9286 01:34:36.738782 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9287 01:34:36.742154 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9288 01:34:36.745470 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9289 01:34:36.748997 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9290 01:34:36.755304 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9291 01:34:36.759020 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9292 01:34:36.765274 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9293 01:34:36.768819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9294 01:34:36.771944 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9295 01:34:36.778572 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9296 01:34:36.782093 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9297 01:34:36.788824 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9298 01:34:36.791843 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9299 01:34:36.795317 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9300 01:34:36.801895 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9301 01:34:36.805274 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9302 01:34:36.811829 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9303 01:34:36.815304 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9304 01:34:36.818527 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9305 01:34:36.825408 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9306 01:34:36.828657 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9307 01:34:36.832488 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9308 01:34:36.839045 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9309 01:34:36.842327 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9310 01:34:36.845427 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9311 01:34:36.848613 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9312 01:34:36.855504 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9313 01:34:36.858971 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9314 01:34:36.861969 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9315 01:34:36.868739 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9316 01:34:36.872096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9317 01:34:36.878632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9318 01:34:36.882067 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9319 01:34:36.885041 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9320 01:34:36.892123 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9321 01:34:36.895264 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9322 01:34:36.898711 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9323 01:34:36.905624 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9324 01:34:36.908588 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9325 01:34:36.915525 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9326 01:34:36.918722 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9327 01:34:36.922054 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9328 01:34:36.928889 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9329 01:34:36.932345 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9330 01:34:36.935787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9331 01:34:36.942379 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9332 01:34:36.945635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9333 01:34:36.952402 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9334 01:34:36.955799 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9335 01:34:36.958731 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9336 01:34:36.965832 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9337 01:34:36.969150 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9338 01:34:36.975795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9339 01:34:36.979058 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9340 01:34:36.982370 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9341 01:34:36.989409 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9342 01:34:36.992485 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9343 01:34:36.995929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9344 01:34:37.002231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9345 01:34:37.005575 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9346 01:34:37.012627 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9347 01:34:37.015689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9348 01:34:37.018768 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9349 01:34:37.025640 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9350 01:34:37.028536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9351 01:34:37.035607 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9352 01:34:37.038741 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9353 01:34:37.042299 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9354 01:34:37.048819 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9355 01:34:37.052031 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9356 01:34:37.058351 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9357 01:34:37.061982 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9358 01:34:37.065342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9359 01:34:37.072020 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9360 01:34:37.075098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9361 01:34:37.078353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9362 01:34:37.085060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9363 01:34:37.088468 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9364 01:34:37.095053 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9365 01:34:37.098095 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9366 01:34:37.104744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9367 01:34:37.108187 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9368 01:34:37.111332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9369 01:34:37.117910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9370 01:34:37.121413 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9371 01:34:37.128328 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9372 01:34:37.131572 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9373 01:34:37.135033 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9374 01:34:37.140901 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9375 01:34:37.144519 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9376 01:34:37.147870 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9377 01:34:37.154345 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9378 01:34:37.157441 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9379 01:34:37.164707 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9380 01:34:37.167649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9381 01:34:37.174112 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9382 01:34:37.177648 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9383 01:34:37.180883 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9384 01:34:37.187659 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9385 01:34:37.190519 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9386 01:34:37.197084 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9387 01:34:37.200861 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9388 01:34:37.207066 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9389 01:34:37.210548 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9390 01:34:37.213805 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9391 01:34:37.220466 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9392 01:34:37.223737 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9393 01:34:37.230318 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9394 01:34:37.233771 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9395 01:34:37.240136 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9396 01:34:37.243820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9397 01:34:37.246881 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9398 01:34:37.253684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9399 01:34:37.256901 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9400 01:34:37.263494 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9401 01:34:37.266985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9402 01:34:37.273726 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9403 01:34:37.276836 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9404 01:34:37.280216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9405 01:34:37.286868 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9406 01:34:37.290007 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9407 01:34:37.296619 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9408 01:34:37.299706 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9409 01:34:37.302990 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9410 01:34:37.309886 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9411 01:34:37.312978 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9412 01:34:37.319767 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9413 01:34:37.323174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9414 01:34:37.329509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9415 01:34:37.333328 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9416 01:34:37.336110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9417 01:34:37.342922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9418 01:34:37.346419 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9419 01:34:37.350018 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9420 01:34:37.353398 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9421 01:34:37.359756 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9422 01:34:37.362684 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9423 01:34:37.365996 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9424 01:34:37.372716 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9425 01:34:37.375852 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9426 01:34:37.382558 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9427 01:34:37.385929 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9428 01:34:37.389365 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9429 01:34:37.395695 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9430 01:34:37.398791 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9431 01:34:37.402300 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9432 01:34:37.408676 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9433 01:34:37.412053 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9434 01:34:37.415703 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9435 01:34:37.422256 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9436 01:34:37.425631 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9437 01:34:37.432135 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9438 01:34:37.435151 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9439 01:34:37.438720 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9440 01:34:37.445449 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9441 01:34:37.448708 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9442 01:34:37.451835 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9443 01:34:37.458371 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9444 01:34:37.461863 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9445 01:34:37.468134 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9446 01:34:37.471549 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9447 01:34:37.474874 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9448 01:34:37.481470 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9449 01:34:37.484958 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9450 01:34:37.488243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9451 01:34:37.494967 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9452 01:34:37.498149 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9453 01:34:37.501457 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9454 01:34:37.508306 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9455 01:34:37.511578 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9456 01:34:37.517691 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9457 01:34:37.521277 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9458 01:34:37.524925 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9459 01:34:37.527918 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9460 01:34:37.534377 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9461 01:34:37.537543 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9462 01:34:37.541026 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9463 01:34:37.544553 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9464 01:34:37.550888 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9465 01:34:37.554494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9466 01:34:37.558017 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9467 01:34:37.560770 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9468 01:34:37.567925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9469 01:34:37.570812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9470 01:34:37.574293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9471 01:34:37.580796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9472 01:34:37.584159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9473 01:34:37.590701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9474 01:34:37.593935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9475 01:34:37.597168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9476 01:34:37.603985 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9477 01:34:37.607562 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9478 01:34:37.613509 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9479 01:34:37.617566 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9480 01:34:37.620549 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9481 01:34:37.626850 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9482 01:34:37.629968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9483 01:34:37.636603 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9484 01:34:37.640118 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9485 01:34:37.646799 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9486 01:34:37.649935 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9487 01:34:37.653363 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9488 01:34:37.660204 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9489 01:34:37.663800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9490 01:34:37.670100 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9491 01:34:37.673408 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9492 01:34:37.676626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9493 01:34:37.683428 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9494 01:34:37.686429 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9495 01:34:37.693131 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9496 01:34:37.696524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9497 01:34:37.703260 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9498 01:34:37.706091 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9499 01:34:37.709705 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9500 01:34:37.716371 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9501 01:34:37.719730 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9502 01:34:37.722787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9503 01:34:37.729393 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9504 01:34:37.732915 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9505 01:34:37.739008 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9506 01:34:37.742680 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9507 01:34:37.749085 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9508 01:34:37.752619 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9509 01:34:37.758736 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9510 01:34:37.762197 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9511 01:34:37.765656 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9512 01:34:37.772292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9513 01:34:37.775593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9514 01:34:37.781992 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9515 01:34:37.785479 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9516 01:34:37.788867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9517 01:34:37.795760 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9518 01:34:37.798518 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9519 01:34:37.805108 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9520 01:34:37.808342 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9521 01:34:37.815083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9522 01:34:37.818502 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9523 01:34:37.821569 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9524 01:34:37.828446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9525 01:34:37.832095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9526 01:34:37.838219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9527 01:34:37.841720 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9528 01:34:37.844972 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9529 01:34:37.851428 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9530 01:34:37.854914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9531 01:34:37.861453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9532 01:34:37.864413 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9533 01:34:37.871281 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9534 01:34:37.874904 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9535 01:34:37.878223 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9536 01:34:37.884272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9537 01:34:37.887702 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9538 01:34:37.894143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9539 01:34:37.897772 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9540 01:34:37.901029 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9541 01:34:37.907288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9542 01:34:37.910789 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9543 01:34:37.917564 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9544 01:34:37.920868 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9545 01:34:37.927441 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9546 01:34:37.930609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9547 01:34:37.934014 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9548 01:34:37.940484 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9549 01:34:37.944135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9550 01:34:37.950473 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9551 01:34:37.953775 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9552 01:34:37.960282 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9553 01:34:37.963525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9554 01:34:37.967184 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9555 01:34:37.974172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9556 01:34:37.977203 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9557 01:34:37.983680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9558 01:34:37.987366 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9559 01:34:37.993687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9560 01:34:37.996871 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9561 01:34:38.003665 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9562 01:34:38.006646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9563 01:34:38.009839 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9564 01:34:38.016567 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9565 01:34:38.020126 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9566 01:34:38.026573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9567 01:34:38.029837 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9568 01:34:38.036503 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9569 01:34:38.039774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9570 01:34:38.046316 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9571 01:34:38.049610 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9572 01:34:38.052771 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9573 01:34:38.059388 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9574 01:34:38.062741 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9575 01:34:38.069395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9576 01:34:38.072588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9577 01:34:38.079323 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9578 01:34:38.082395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9579 01:34:38.089606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9580 01:34:38.092926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9581 01:34:38.096241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9582 01:34:38.102550 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9583 01:34:38.105896 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9584 01:34:38.112524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9585 01:34:38.115597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9586 01:34:38.122205 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9587 01:34:38.125447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9588 01:34:38.132102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9589 01:34:38.135326 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9590 01:34:38.138601 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9591 01:34:38.145454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9592 01:34:38.148590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9593 01:34:38.155392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9594 01:34:38.158614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9595 01:34:38.165123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9596 01:34:38.168335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9597 01:34:38.175173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9598 01:34:38.178407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9599 01:34:38.184875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9600 01:34:38.188423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9601 01:34:38.194833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9602 01:34:38.197940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9603 01:34:38.204747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9604 01:34:38.207949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9605 01:34:38.211145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9606 01:34:38.217965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9607 01:34:38.221489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9608 01:34:38.227979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9609 01:34:38.231130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9610 01:34:38.238448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9611 01:34:38.241156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9612 01:34:38.247843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9613 01:34:38.251270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9614 01:34:38.257825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9615 01:34:38.261064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9616 01:34:38.267795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9617 01:34:38.271206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9618 01:34:38.277929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9619 01:34:38.281076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9620 01:34:38.288439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9621 01:34:38.290928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9622 01:34:38.297823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9623 01:34:38.300626 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9624 01:34:38.304054 INFO: [APUAPC] vio 0
9625 01:34:38.307289 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9626 01:34:38.313866 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9627 01:34:38.317256 INFO: [APUAPC] D0_APC_0: 0x400510
9628 01:34:38.320798 INFO: [APUAPC] D0_APC_1: 0x0
9629 01:34:38.324065 INFO: [APUAPC] D0_APC_2: 0x1540
9630 01:34:38.324568 INFO: [APUAPC] D0_APC_3: 0x0
9631 01:34:38.327125 INFO: [APUAPC] D1_APC_0: 0xffffffff
9632 01:34:38.333817 INFO: [APUAPC] D1_APC_1: 0xffffffff
9633 01:34:38.336949 INFO: [APUAPC] D1_APC_2: 0x3fffff
9634 01:34:38.337450 INFO: [APUAPC] D1_APC_3: 0x0
9635 01:34:38.340525 INFO: [APUAPC] D2_APC_0: 0xffffffff
9636 01:34:38.344461 INFO: [APUAPC] D2_APC_1: 0xffffffff
9637 01:34:38.347259 INFO: [APUAPC] D2_APC_2: 0x3fffff
9638 01:34:38.350274 INFO: [APUAPC] D2_APC_3: 0x0
9639 01:34:38.353918 INFO: [APUAPC] D3_APC_0: 0xffffffff
9640 01:34:38.357085 INFO: [APUAPC] D3_APC_1: 0xffffffff
9641 01:34:38.360419 INFO: [APUAPC] D3_APC_2: 0x3fffff
9642 01:34:38.363981 INFO: [APUAPC] D3_APC_3: 0x0
9643 01:34:38.367059 INFO: [APUAPC] D4_APC_0: 0xffffffff
9644 01:34:38.370775 INFO: [APUAPC] D4_APC_1: 0xffffffff
9645 01:34:38.373632 INFO: [APUAPC] D4_APC_2: 0x3fffff
9646 01:34:38.376939 INFO: [APUAPC] D4_APC_3: 0x0
9647 01:34:38.380548 INFO: [APUAPC] D5_APC_0: 0xffffffff
9648 01:34:38.383536 INFO: [APUAPC] D5_APC_1: 0xffffffff
9649 01:34:38.386984 INFO: [APUAPC] D5_APC_2: 0x3fffff
9650 01:34:38.390730 INFO: [APUAPC] D5_APC_3: 0x0
9651 01:34:38.393837 INFO: [APUAPC] D6_APC_0: 0xffffffff
9652 01:34:38.397198 INFO: [APUAPC] D6_APC_1: 0xffffffff
9653 01:34:38.399986 INFO: [APUAPC] D6_APC_2: 0x3fffff
9654 01:34:38.403491 INFO: [APUAPC] D6_APC_3: 0x0
9655 01:34:38.406477 INFO: [APUAPC] D7_APC_0: 0xffffffff
9656 01:34:38.409844 INFO: [APUAPC] D7_APC_1: 0xffffffff
9657 01:34:38.413359 INFO: [APUAPC] D7_APC_2: 0x3fffff
9658 01:34:38.416491 INFO: [APUAPC] D7_APC_3: 0x0
9659 01:34:38.420216 INFO: [APUAPC] D8_APC_0: 0xffffffff
9660 01:34:38.423668 INFO: [APUAPC] D8_APC_1: 0xffffffff
9661 01:34:38.426546 INFO: [APUAPC] D8_APC_2: 0x3fffff
9662 01:34:38.430011 INFO: [APUAPC] D8_APC_3: 0x0
9663 01:34:38.433622 INFO: [APUAPC] D9_APC_0: 0xffffffff
9664 01:34:38.436862 INFO: [APUAPC] D9_APC_1: 0xffffffff
9665 01:34:38.440274 INFO: [APUAPC] D9_APC_2: 0x3fffff
9666 01:34:38.443369 INFO: [APUAPC] D9_APC_3: 0x0
9667 01:34:38.446718 INFO: [APUAPC] D10_APC_0: 0xffffffff
9668 01:34:38.450082 INFO: [APUAPC] D10_APC_1: 0xffffffff
9669 01:34:38.453233 INFO: [APUAPC] D10_APC_2: 0x3fffff
9670 01:34:38.456389 INFO: [APUAPC] D10_APC_3: 0x0
9671 01:34:38.459926 INFO: [APUAPC] D11_APC_0: 0xffffffff
9672 01:34:38.462965 INFO: [APUAPC] D11_APC_1: 0xffffffff
9673 01:34:38.466267 INFO: [APUAPC] D11_APC_2: 0x3fffff
9674 01:34:38.469730 INFO: [APUAPC] D11_APC_3: 0x0
9675 01:34:38.473267 INFO: [APUAPC] D12_APC_0: 0xffffffff
9676 01:34:38.476549 INFO: [APUAPC] D12_APC_1: 0xffffffff
9677 01:34:38.479777 INFO: [APUAPC] D12_APC_2: 0x3fffff
9678 01:34:38.483168 INFO: [APUAPC] D12_APC_3: 0x0
9679 01:34:38.486195 INFO: [APUAPC] D13_APC_0: 0xffffffff
9680 01:34:38.489668 INFO: [APUAPC] D13_APC_1: 0xffffffff
9681 01:34:38.493161 INFO: [APUAPC] D13_APC_2: 0x3fffff
9682 01:34:38.496509 INFO: [APUAPC] D13_APC_3: 0x0
9683 01:34:38.499794 INFO: [APUAPC] D14_APC_0: 0xffffffff
9684 01:34:38.502631 INFO: [APUAPC] D14_APC_1: 0xffffffff
9685 01:34:38.505963 INFO: [APUAPC] D14_APC_2: 0x3fffff
9686 01:34:38.509340 INFO: [APUAPC] D14_APC_3: 0x0
9687 01:34:38.512478 INFO: [APUAPC] D15_APC_0: 0xffffffff
9688 01:34:38.516058 INFO: [APUAPC] D15_APC_1: 0xffffffff
9689 01:34:38.519258 INFO: [APUAPC] D15_APC_2: 0x3fffff
9690 01:34:38.522346 INFO: [APUAPC] D15_APC_3: 0x0
9691 01:34:38.525883 INFO: [APUAPC] APC_CON: 0x4
9692 01:34:38.529433 INFO: [NOCDAPC] D0_APC_0: 0x0
9693 01:34:38.532180 INFO: [NOCDAPC] D0_APC_1: 0x0
9694 01:34:38.535784 INFO: [NOCDAPC] D1_APC_0: 0x0
9695 01:34:38.536335 INFO: [NOCDAPC] D1_APC_1: 0xfff
9696 01:34:38.539197 INFO: [NOCDAPC] D2_APC_0: 0x0
9697 01:34:38.542767 INFO: [NOCDAPC] D2_APC_1: 0xfff
9698 01:34:38.546012 INFO: [NOCDAPC] D3_APC_0: 0x0
9699 01:34:38.549233 INFO: [NOCDAPC] D3_APC_1: 0xfff
9700 01:34:38.552675 INFO: [NOCDAPC] D4_APC_0: 0x0
9701 01:34:38.556090 INFO: [NOCDAPC] D4_APC_1: 0xfff
9702 01:34:38.558992 INFO: [NOCDAPC] D5_APC_0: 0x0
9703 01:34:38.562264 INFO: [NOCDAPC] D5_APC_1: 0xfff
9704 01:34:38.565794 INFO: [NOCDAPC] D6_APC_0: 0x0
9705 01:34:38.566350 INFO: [NOCDAPC] D6_APC_1: 0xfff
9706 01:34:38.569050 INFO: [NOCDAPC] D7_APC_0: 0x0
9707 01:34:38.572063 INFO: [NOCDAPC] D7_APC_1: 0xfff
9708 01:34:38.575704 INFO: [NOCDAPC] D8_APC_0: 0x0
9709 01:34:38.579109 INFO: [NOCDAPC] D8_APC_1: 0xfff
9710 01:34:38.582090 INFO: [NOCDAPC] D9_APC_0: 0x0
9711 01:34:38.585662 INFO: [NOCDAPC] D9_APC_1: 0xfff
9712 01:34:38.589150 INFO: [NOCDAPC] D10_APC_0: 0x0
9713 01:34:38.592566 INFO: [NOCDAPC] D10_APC_1: 0xfff
9714 01:34:38.596082 INFO: [NOCDAPC] D11_APC_0: 0x0
9715 01:34:38.598945 INFO: [NOCDAPC] D11_APC_1: 0xfff
9716 01:34:38.602263 INFO: [NOCDAPC] D12_APC_0: 0x0
9717 01:34:38.605751 INFO: [NOCDAPC] D12_APC_1: 0xfff
9718 01:34:38.606303 INFO: [NOCDAPC] D13_APC_0: 0x0
9719 01:34:38.609379 INFO: [NOCDAPC] D13_APC_1: 0xfff
9720 01:34:38.612155 INFO: [NOCDAPC] D14_APC_0: 0x0
9721 01:34:38.615339 INFO: [NOCDAPC] D14_APC_1: 0xfff
9722 01:34:38.619036 INFO: [NOCDAPC] D15_APC_0: 0x0
9723 01:34:38.621936 INFO: [NOCDAPC] D15_APC_1: 0xfff
9724 01:34:38.625217 INFO: [NOCDAPC] APC_CON: 0x4
9725 01:34:38.628673 INFO: [APUAPC] set_apusys_apc done
9726 01:34:38.632190 INFO: [DEVAPC] devapc_init done
9727 01:34:38.635494 INFO: GICv3 without legacy support detected.
9728 01:34:38.638583 INFO: ARM GICv3 driver initialized in EL3
9729 01:34:38.645163 INFO: Maximum SPI INTID supported: 639
9730 01:34:38.648651 INFO: BL31: Initializing runtime services
9731 01:34:38.655471 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9732 01:34:38.656025 INFO: SPM: enable CPC mode
9733 01:34:38.662062 INFO: mcdi ready for mcusys-off-idle and system suspend
9734 01:34:38.665462 INFO: BL31: Preparing for EL3 exit to normal world
9735 01:34:38.668861 INFO: Entry point address = 0x80000000
9736 01:34:38.672134 INFO: SPSR = 0x8
9737 01:34:38.677644
9738 01:34:38.678204
9739 01:34:38.678570
9740 01:34:38.680728 Starting depthcharge on Spherion...
9741 01:34:38.681189
9742 01:34:38.681585 Wipe memory regions:
9743 01:34:38.681926
9744 01:34:38.684663 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9745 01:34:38.685216 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9746 01:34:38.685702 Setting prompt string to ['asurada:']
9747 01:34:38.686133 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9748 01:34:38.686845 [0x00000040000000, 0x00000054600000)
9749 01:34:38.806704
9750 01:34:38.807258 [0x00000054660000, 0x00000080000000)
9751 01:34:39.067001
9752 01:34:39.067550 [0x000000821a7280, 0x000000ffe64000)
9753 01:34:39.812154
9754 01:34:39.812712 [0x00000100000000, 0x00000140000000)
9755 01:34:40.193134
9756 01:34:40.196209 Initializing XHCI USB controller at 0x11200000.
9757 01:34:41.235691
9758 01:34:41.238525 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9759 01:34:41.238988
9760 01:34:41.239349
9761 01:34:41.240138 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9763 01:34:41.341490 asurada: tftpboot 192.168.201.1 14173500/tftp-deploy-70c7jjut/kernel/image.itb 14173500/tftp-deploy-70c7jjut/kernel/cmdline
9764 01:34:41.342128 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9765 01:34:41.342605 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9766 01:34:41.347099 tftpboot 192.168.201.1 14173500/tftp-deploy-70c7jjut/kernel/image.itp-deploy-70c7jjut/kernel/cmdline
9767 01:34:41.347593
9768 01:34:41.348074 Waiting for link
9769 01:34:41.507854
9770 01:34:41.508412 R8152: Initializing
9771 01:34:41.508902
9772 01:34:41.510895 Version 9 (ocp_data = 6010)
9773 01:34:41.511458
9774 01:34:41.514143 R8152: Done initializing
9775 01:34:41.514708
9776 01:34:41.515200 Adding net device
9777 01:34:43.397461
9778 01:34:43.398049 done.
9779 01:34:43.398744
9780 01:34:43.399405 MAC: 00:e0:4c:68:03:bd
9781 01:34:43.399961
9782 01:34:43.400649 Sending DHCP discover... done.
9783 01:34:43.401023
9784 01:34:43.403776 Waiting for reply... done.
9785 01:34:43.404353
9786 01:34:43.406885 Sending DHCP request... done.
9787 01:34:43.407337
9788 01:34:43.412820 Waiting for reply... done.
9789 01:34:43.413270
9790 01:34:43.413681 My ip is 192.168.201.16
9791 01:34:43.414018
9792 01:34:43.416061 The DHCP server ip is 192.168.201.1
9793 01:34:43.416515
9794 01:34:43.422647 TFTP server IP predefined by user: 192.168.201.1
9795 01:34:43.423133
9796 01:34:43.429459 Bootfile predefined by user: 14173500/tftp-deploy-70c7jjut/kernel/image.itb
9797 01:34:43.429919
9798 01:34:43.432650 Sending tftp read request... done.
9799 01:34:43.433107
9800 01:34:43.438921 Waiting for the transfer...
9801 01:34:43.439445
9802 01:34:43.796980 00000000 ################################################################
9803 01:34:43.797128
9804 01:34:44.097484 00080000 ################################################################
9805 01:34:44.097625
9806 01:34:44.393167 00100000 ################################################################
9807 01:34:44.393311
9808 01:34:44.676136 00180000 ################################################################
9809 01:34:44.676281
9810 01:34:44.964745 00200000 ################################################################
9811 01:34:44.964887
9812 01:34:45.255592 00280000 ################################################################
9813 01:34:45.255724
9814 01:34:45.533330 00300000 ################################################################
9815 01:34:45.533470
9816 01:34:45.799959 00380000 ################################################################
9817 01:34:45.800158
9818 01:34:46.050477 00400000 ################################################################
9819 01:34:46.050609
9820 01:34:46.301852 00480000 ################################################################
9821 01:34:46.301994
9822 01:34:46.552829 00500000 ################################################################
9823 01:34:46.552963
9824 01:34:46.803757 00580000 ################################################################
9825 01:34:46.803888
9826 01:34:47.075075 00600000 ################################################################
9827 01:34:47.075215
9828 01:34:47.358061 00680000 ################################################################
9829 01:34:47.358203
9830 01:34:47.651652 00700000 ################################################################
9831 01:34:47.651790
9832 01:34:47.947209 00780000 ################################################################
9833 01:34:47.947345
9834 01:34:48.231687 00800000 ################################################################
9835 01:34:48.231823
9836 01:34:48.508732 00880000 ################################################################
9837 01:34:48.508869
9838 01:34:48.769848 00900000 ################################################################
9839 01:34:48.769991
9840 01:34:49.058642 00980000 ################################################################
9841 01:34:49.058779
9842 01:34:49.358482 00a00000 ################################################################
9843 01:34:49.358619
9844 01:34:49.647886 00a80000 ################################################################
9845 01:34:49.648029
9846 01:34:49.949425 00b00000 ################################################################
9847 01:34:49.949562
9848 01:34:50.241296 00b80000 ################################################################
9849 01:34:50.241445
9850 01:34:50.536225 00c00000 ################################################################
9851 01:34:50.536362
9852 01:34:50.824501 00c80000 ################################################################
9853 01:34:50.824665
9854 01:34:51.115884 00d00000 ################################################################
9855 01:34:51.116047
9856 01:34:51.412835 00d80000 ################################################################
9857 01:34:51.412971
9858 01:34:51.712252 00e00000 ################################################################
9859 01:34:51.712392
9860 01:34:52.007275 00e80000 ################################################################
9861 01:34:52.007419
9862 01:34:52.296552 00f00000 ################################################################
9863 01:34:52.296692
9864 01:34:52.597415 00f80000 ################################################################
9865 01:34:52.597553
9866 01:34:52.893342 01000000 ################################################################
9867 01:34:52.893475
9868 01:34:53.184682 01080000 ################################################################
9869 01:34:53.184814
9870 01:34:53.468208 01100000 ################################################################
9871 01:34:53.468368
9872 01:34:53.751101 01180000 ################################################################
9873 01:34:53.751236
9874 01:34:54.017240 01200000 ################################################################
9875 01:34:54.017384
9876 01:34:54.318410 01280000 ################################################################
9877 01:34:54.318546
9878 01:34:54.596964 01300000 ################################################################
9879 01:34:54.597110
9880 01:34:54.874102 01380000 ################################################################
9881 01:34:54.874241
9882 01:34:55.150385 01400000 ################################################################
9883 01:34:55.150514
9884 01:34:55.411029 01480000 ################################################################
9885 01:34:55.411162
9886 01:34:55.692578 01500000 ################################################################
9887 01:34:55.692714
9888 01:34:55.973710 01580000 ################################################################
9889 01:34:55.973849
9890 01:34:56.270465 01600000 ################################################################
9891 01:34:56.270602
9892 01:34:56.557520 01680000 ################################################################
9893 01:34:56.557660
9894 01:34:56.813558 01700000 ################################################################
9895 01:34:56.813692
9896 01:34:57.082994 01780000 ################################################################
9897 01:34:57.083155
9898 01:34:57.366324 01800000 ################################################################
9899 01:34:57.366472
9900 01:34:57.648349 01880000 ################################################################
9901 01:34:57.648483
9902 01:34:57.949166 01900000 ################################################################
9903 01:34:57.949341
9904 01:34:58.246608 01980000 ################################################################
9905 01:34:58.246749
9906 01:34:58.535339 01a00000 ################################################################
9907 01:34:58.535480
9908 01:34:58.830372 01a80000 ################################################################
9909 01:34:58.830507
9910 01:34:59.121434 01b00000 ################################################################
9911 01:34:59.121576
9912 01:34:59.406712 01b80000 ################################################################
9913 01:34:59.406880
9914 01:34:59.702797 01c00000 ################################################################
9915 01:34:59.702938
9916 01:35:00.003568 01c80000 ################################################################
9917 01:35:00.003703
9918 01:35:00.304783 01d00000 ################################################################
9919 01:35:00.304915
9920 01:35:00.605389 01d80000 ################################################################
9921 01:35:00.605524
9922 01:35:00.893434 01e00000 ################################################################
9923 01:35:00.893577
9924 01:35:01.194122 01e80000 ################################################################
9925 01:35:01.194261
9926 01:35:01.483300 01f00000 ################################################################
9927 01:35:01.483438
9928 01:35:01.776246 01f80000 ################################################################
9929 01:35:01.776393
9930 01:35:02.058995 02000000 ################################################################
9931 01:35:02.059137
9932 01:35:02.346601 02080000 ################################################################
9933 01:35:02.346737
9934 01:35:02.641067 02100000 ################################################################
9935 01:35:02.641202
9936 01:35:02.938657 02180000 ################################################################
9937 01:35:02.938791
9938 01:35:03.227809 02200000 ################################################################
9939 01:35:03.227953
9940 01:35:03.525815 02280000 ################################################################
9941 01:35:03.525957
9942 01:35:03.819500 02300000 ################################################################
9943 01:35:03.819637
9944 01:35:04.119455 02380000 ################################################################
9945 01:35:04.119588
9946 01:35:04.417207 02400000 ################################################################
9947 01:35:04.417357
9948 01:35:04.699162 02480000 ################################################################
9949 01:35:04.699300
9950 01:35:04.996411 02500000 ################################################################
9951 01:35:04.996545
9952 01:35:05.289186 02580000 ################################################################
9953 01:35:05.289356
9954 01:35:05.583676 02600000 ################################################################
9955 01:35:05.583808
9956 01:35:05.868369 02680000 ################################################################
9957 01:35:05.868504
9958 01:35:06.160731 02700000 ################################################################
9959 01:35:06.160868
9960 01:35:06.458662 02780000 ################################################################
9961 01:35:06.458793
9962 01:35:06.752973 02800000 ################################################################
9963 01:35:06.753110
9964 01:35:07.018813 02880000 ################################################################
9965 01:35:07.018957
9966 01:35:07.314312 02900000 ################################################################
9967 01:35:07.314451
9968 01:35:07.613095 02980000 ################################################################
9969 01:35:07.613257
9970 01:35:07.913109 02a00000 ################################################################
9971 01:35:07.913247
9972 01:35:08.182501 02a80000 ################################################################
9973 01:35:08.182645
9974 01:35:08.433901 02b00000 ################################################################
9975 01:35:08.434033
9976 01:35:08.693996 02b80000 ################################################################
9977 01:35:08.694127
9978 01:35:08.947797 02c00000 ################################################################
9979 01:35:08.947928
9980 01:35:09.247159 02c80000 ################################################################
9981 01:35:09.247294
9982 01:35:09.536471 02d00000 ################################################################
9983 01:35:09.536612
9984 01:35:09.837279 02d80000 ################################################################
9985 01:35:09.837426
9986 01:35:10.134796 02e00000 ################################################################
9987 01:35:10.134934
9988 01:35:10.436220 02e80000 ################################################################
9989 01:35:10.436380
9990 01:35:10.733224 02f00000 ################################################################
9991 01:35:10.733381
9992 01:35:11.034044 02f80000 ################################################################
9993 01:35:11.034179
9994 01:35:11.335231 03000000 ################################################################
9995 01:35:11.335363
9996 01:35:11.629862 03080000 ################################################################
9997 01:35:11.630022
9998 01:35:11.889713 03100000 ################################################################
9999 01:35:11.889849
10000 01:35:12.183869 03180000 ################################################################
10001 01:35:12.184028
10002 01:35:12.472803 03200000 ################################################################
10003 01:35:12.472961
10004 01:35:12.764255 03280000 ################################################################
10005 01:35:12.764422
10006 01:35:13.046776 03300000 ################################################################
10007 01:35:13.046915
10008 01:35:13.342439 03380000 ################################################################
10009 01:35:13.342579
10010 01:35:13.630296 03400000 ################################################################
10011 01:35:13.630454
10012 01:35:13.929424 03480000 ################################################################
10013 01:35:13.929585
10014 01:35:14.211409 03500000 ################################################################
10015 01:35:14.211548
10016 01:35:14.501240 03580000 ################################################################
10017 01:35:14.501417
10018 01:35:14.798210 03600000 ################################################################
10019 01:35:14.798364
10020 01:35:15.097341 03680000 ################################################################
10021 01:35:15.097473
10022 01:35:15.392502 03700000 ################################################################
10023 01:35:15.392640
10024 01:35:15.683266 03780000 ################################################################
10025 01:35:15.683403
10026 01:35:15.972900 03800000 ################################################################
10027 01:35:15.973060
10028 01:35:16.269224 03880000 ################################################################
10029 01:35:16.269363
10030 01:35:16.563569 03900000 ################################################################
10031 01:35:16.563708
10032 01:35:16.856957 03980000 ################################################################
10033 01:35:16.857095
10034 01:35:17.141030 03a00000 ################################################################
10035 01:35:17.141169
10036 01:35:17.435762 03a80000 ################################################################
10037 01:35:17.435897
10038 01:35:17.733109 03b00000 ################################################################
10039 01:35:17.733267
10040 01:35:18.023308 03b80000 ################################################################
10041 01:35:18.023453
10042 01:35:18.315288 03c00000 ################################################################
10043 01:35:18.315415
10044 01:35:18.611337 03c80000 ################################################################
10045 01:35:18.611474
10046 01:35:18.905668 03d00000 ################################################################
10047 01:35:18.905802
10048 01:35:19.187366 03d80000 ################################################################
10049 01:35:19.187505
10050 01:35:19.447777 03e00000 ################################################################
10051 01:35:19.447913
10052 01:35:19.736327 03e80000 ################################################################
10053 01:35:19.736460
10054 01:35:20.032178 03f00000 ################################################################
10055 01:35:20.032339
10056 01:35:20.330701 03f80000 ################################################################
10057 01:35:20.330890
10058 01:35:20.622981 04000000 ################################################################
10059 01:35:20.623122
10060 01:35:20.924715 04080000 ################################################################
10061 01:35:20.924852
10062 01:35:21.224051 04100000 ################################################################
10063 01:35:21.224218
10064 01:35:21.519873 04180000 ################################################################
10065 01:35:21.520033
10066 01:35:21.811132 04200000 ################################################################
10067 01:35:21.811272
10068 01:35:22.110848 04280000 ################################################################
10069 01:35:22.111005
10070 01:35:22.407849 04300000 ################################################################
10071 01:35:22.408009
10072 01:35:22.702497 04380000 ################################################################
10073 01:35:22.702653
10074 01:35:22.997882 04400000 ################################################################
10075 01:35:22.998020
10076 01:35:23.297445 04480000 ################################################################
10077 01:35:23.297578
10078 01:35:23.598196 04500000 ################################################################
10079 01:35:23.598333
10080 01:35:23.897164 04580000 ################################################################
10081 01:35:23.897342
10082 01:35:24.161003 04600000 ################################################################
10083 01:35:24.161177
10084 01:35:24.244358 04680000 ###################### done.
10085 01:35:24.244480
10086 01:35:24.247505 The bootfile was 74097530 bytes long.
10087 01:35:24.247591
10088 01:35:24.251246 Sending tftp read request... done.
10089 01:35:24.251410
10090 01:35:24.254358 Waiting for the transfer...
10091 01:35:24.254525
10092 01:35:24.254605 00000000 # done.
10093 01:35:24.254682
10094 01:35:24.260753 Command line loaded dynamically from TFTP file: 14173500/tftp-deploy-70c7jjut/kernel/cmdline
10095 01:35:24.260924
10096 01:35:24.277041 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10097 01:35:24.277253
10098 01:35:24.277390 Loading FIT.
10099 01:35:24.277499
10100 01:35:24.280593 Image ramdisk-1 has 60988320 bytes.
10101 01:35:24.280739
10102 01:35:24.284120 Image fdt-1 has 47258 bytes.
10103 01:35:24.284369
10104 01:35:24.287169 Image kernel-1 has 13059919 bytes.
10105 01:35:24.287365
10106 01:35:24.293758 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10107 01:35:24.293986
10108 01:35:24.314182 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10109 01:35:24.314762
10110 01:35:24.317147 Choosing best match conf-1 for compat google,spherion-rev3.
10111 01:35:24.321915
10112 01:35:24.326821 Connected to device vid:did:rid of 1ae0:0028:00
10113 01:35:24.334987
10114 01:35:24.338190 tpm_get_response: command 0x17b, return code 0x0
10115 01:35:24.338651
10116 01:35:24.341412 ec_init: CrosEC protocol v3 supported (256, 248)
10117 01:35:24.345250
10118 01:35:24.348993 tpm_cleanup: add release locality here.
10119 01:35:24.349484
10120 01:35:24.349851 Shutting down all USB controllers.
10121 01:35:24.350191
10122 01:35:24.352305 Removing current net device
10123 01:35:24.352757
10124 01:35:24.358920 Exiting depthcharge with code 4 at timestamp: 73927233
10125 01:35:24.359380
10126 01:35:24.362306 LZMA decompressing kernel-1 to 0x821a6718
10127 01:35:24.362852
10128 01:35:24.365432 LZMA decompressing kernel-1 to 0x40000000
10129 01:35:25.974228
10130 01:35:25.974779 jumping to kernel
10131 01:35:25.976957 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10132 01:35:25.977523 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10133 01:35:25.978123 Setting prompt string to ['Linux version [0-9]']
10134 01:35:25.978538 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 01:35:25.978915 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10136 01:35:26.025754
10137 01:35:26.028937 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10138 01:35:26.032901 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10139 01:35:26.033565 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10140 01:35:26.033971 Setting prompt string to []
10141 01:35:26.034388 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10142 01:35:26.034786 Using line separator: #'\n'#
10143 01:35:26.035118 No login prompt set.
10144 01:35:26.035453 Parsing kernel messages
10145 01:35:26.035761 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10146 01:35:26.036327 [login-action] Waiting for messages, (timeout 00:03:39)
10147 01:35:26.036687 Waiting using forced prompt support (timeout 00:01:49)
10148 01:35:26.052133 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10149 01:35:26.055219 [ 0.000000] random: crng init done
10150 01:35:26.061869 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10151 01:35:26.065355 [ 0.000000] efi: UEFI not found.
10152 01:35:26.071889 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10153 01:35:26.081874 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10154 01:35:26.091432 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10155 01:35:26.098179 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10156 01:35:26.104768 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10157 01:35:26.111033 [ 0.000000] printk: bootconsole [mtk8250] enabled
10158 01:35:26.118421 [ 0.000000] NUMA: No NUMA configuration found
10159 01:35:26.125043 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10160 01:35:26.131411 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10161 01:35:26.131967 [ 0.000000] Zone ranges:
10162 01:35:26.138161 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10163 01:35:26.141171 [ 0.000000] DMA32 empty
10164 01:35:26.148074 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10165 01:35:26.151187 [ 0.000000] Movable zone start for each node
10166 01:35:26.154488 [ 0.000000] Early memory node ranges
10167 01:35:26.161406 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10168 01:35:26.167536 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10169 01:35:26.174195 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10170 01:35:26.181022 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10171 01:35:26.187606 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10172 01:35:26.193964 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10173 01:35:26.224587 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10174 01:35:26.231420 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10175 01:35:26.237704 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10176 01:35:26.241113 [ 0.000000] psci: probing for conduit method from DT.
10177 01:35:26.247723 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10178 01:35:26.250909 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10179 01:35:26.257627 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10180 01:35:26.260974 [ 0.000000] psci: SMC Calling Convention v1.2
10181 01:35:26.267455 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10182 01:35:26.270896 [ 0.000000] Detected VIPT I-cache on CPU0
10183 01:35:26.277573 [ 0.000000] CPU features: detected: GIC system register CPU interface
10184 01:35:26.284087 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10185 01:35:26.290503 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10186 01:35:26.296944 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10187 01:35:26.306750 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10188 01:35:26.313656 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10189 01:35:26.316683 [ 0.000000] alternatives: applying boot alternatives
10190 01:35:26.323201 [ 0.000000] Fallback order for Node 0: 0
10191 01:35:26.329959 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10192 01:35:26.333661 [ 0.000000] Policy zone: Normal
10193 01:35:26.346618 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10194 01:35:26.356422 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10195 01:35:26.367219 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10196 01:35:26.377025 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10197 01:35:26.384010 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10198 01:35:26.386985 <6>[ 0.000000] software IO TLB: area num 8.
10199 01:35:26.442884 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10200 01:35:26.523645 <6>[ 0.000000] Memory: 3790216K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 368248K reserved, 32768K cma-reserved)
10201 01:35:26.529980 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10202 01:35:26.536395 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10203 01:35:26.539937 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10204 01:35:26.546451 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10205 01:35:26.552996 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10206 01:35:26.556455 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10207 01:35:26.566305 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10208 01:35:26.573021 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10209 01:35:26.579221 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10210 01:35:26.586061 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10211 01:35:26.589357 <6>[ 0.000000] GICv3: 608 SPIs implemented
10212 01:35:26.592766 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10213 01:35:26.599003 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10214 01:35:26.602409 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10215 01:35:26.609154 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10216 01:35:26.622233 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10217 01:35:26.635820 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10218 01:35:26.642149 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10219 01:35:26.650111 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10220 01:35:26.663455 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10221 01:35:26.669945 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10222 01:35:26.676440 <6>[ 0.009171] Console: colour dummy device 80x25
10223 01:35:26.686566 <6>[ 0.013916] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10224 01:35:26.692987 <6>[ 0.024358] pid_max: default: 32768 minimum: 301
10225 01:35:26.696137 <6>[ 0.029260] LSM: Security Framework initializing
10226 01:35:26.703047 <6>[ 0.034173] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10227 01:35:26.712513 <6>[ 0.041780] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10228 01:35:26.719175 <6>[ 0.051001] cblist_init_generic: Setting adjustable number of callback queues.
10229 01:35:26.725833 <6>[ 0.058445] cblist_init_generic: Setting shift to 3 and lim to 1.
10230 01:35:26.735785 <6>[ 0.064782] cblist_init_generic: Setting adjustable number of callback queues.
10231 01:35:26.742272 <6>[ 0.072208] cblist_init_generic: Setting shift to 3 and lim to 1.
10232 01:35:26.745367 <6>[ 0.078647] rcu: Hierarchical SRCU implementation.
10233 01:35:26.752247 <6>[ 0.078649] rcu: Max phase no-delay instances is 1000.
10234 01:35:26.758649 <6>[ 0.078672] printk: bootconsole [mtk8250] printing thread started
10235 01:35:26.765811 <6>[ 0.097009] EFI services will not be available.
10236 01:35:26.768625 <6>[ 0.097214] smp: Bringing up secondary CPUs ...
10237 01:35:26.772142 <6>[ 0.097523] Detected VIPT I-cache on CPU1
10238 01:35:26.781826 <6>[ 0.097591] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10239 01:35:26.788291 <6>[ 0.097621] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10240 01:35:26.797720 <6>[ 0.125484] Detected VIPT I-cache on CPU2
10241 01:35:26.804396 <6>[ 0.125537] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10242 01:35:26.810602 <6>[ 0.125555] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10243 01:35:26.817473 <6>[ 0.125813] Detected VIPT I-cache on CPU3
10244 01:35:26.824035 <6>[ 0.125861] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10245 01:35:26.830529 <6>[ 0.125875] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10246 01:35:26.833797 <6>[ 0.126181] CPU features: detected: Spectre-v4
10247 01:35:26.840248 <6>[ 0.126186] CPU features: detected: Spectre-BHB
10248 01:35:26.843504 <6>[ 0.126192] Detected PIPT I-cache on CPU4
10249 01:35:26.850769 <6>[ 0.126250] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10250 01:35:26.857280 <6>[ 0.126265] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10251 01:35:26.863733 <6>[ 0.126554] Detected PIPT I-cache on CPU5
10252 01:35:26.870442 <6>[ 0.126613] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10253 01:35:26.876819 <6>[ 0.126630] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10254 01:35:26.879908 <6>[ 0.126898] Detected PIPT I-cache on CPU6
10255 01:35:26.886942 <6>[ 0.126960] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10256 01:35:26.897677 <6>[ 0.126976] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10257 01:35:26.900742 <6>[ 0.127266] Detected PIPT I-cache on CPU7
10258 01:35:26.907461 <6>[ 0.127331] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10259 01:35:26.913899 <6>[ 0.127347] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10260 01:35:26.917276 <6>[ 0.127393] smp: Brought up 1 node, 8 CPUs
10261 01:35:26.923873 <6>[ 0.127397] SMP: Total of 8 processors activated.
10262 01:35:26.930552 <6>[ 0.127400] CPU features: detected: 32-bit EL0 Support
10263 01:35:26.937078 <6>[ 0.127403] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10264 01:35:26.943670 <6>[ 0.127405] CPU features: detected: Common not Private translations
10265 01:35:26.950353 <6>[ 0.127407] CPU features: detected: CRC32 instructions
10266 01:35:26.957044 <6>[ 0.127410] CPU features: detected: RCpc load-acquire (LDAPR)
10267 01:35:26.960412 <6>[ 0.127411] CPU features: detected: LSE atomic instructions
10268 01:35:26.966854 <6>[ 0.127413] CPU features: detected: Privileged Access Never
10269 01:35:26.973383 <6>[ 0.127414] CPU features: detected: RAS Extension Support
10270 01:35:26.980094 <6>[ 0.127417] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10271 01:35:26.982993 <6>[ 0.127483] CPU: All CPU(s) started at EL2
10272 01:35:26.989872 <6>[ 0.127485] alternatives: applying system-wide alternatives
10273 01:35:26.993252 <6>[ 0.139861] devtmpfs: initialized
10274 01:35:27.002623 <6>[ 0.145354] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10275 01:35:27.029045 <6>[ 0.361542] print<k: console [ttyS0] printing thread started
10276 01:35:27.035665 6<6>[ 0.361572] printk: console [ttyS0] enabled
10277 01:35:27.042254 >[ 0.145368] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10278 01:35:27.045589 <6>[ 0.361576] printk: bootconsole [mtk8250] disabled
10279 01:35:27.051993 <6>[ 0.379047] printk: bootconsole [mtk8250] printing thread stopped
10280 01:35:27.058701 <6>[ 0.380377] SuperH (H)SCI(F) driver initialized
10281 01:35:27.061863 <6>[ 0.380865] msm_serial: driver initialized
10282 01:35:27.072073 <6>[ 0.385504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10283 01:35:27.078454 <6>[ 0.385535] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10284 01:35:27.088421 <6>[ 0.385563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10285 01:35:27.104003 <6>[ 0.385592] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10286 01:35:27.108924 <6>[ 0.385614] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10287 01:35:27.122461 <6>[ 0.385643] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10288 01:35:27.138483 <6>[ 0.385672] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10289 01:35:27.139739 <6>[ 0.385782] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10290 01:35:27.143540 <6>[ 0.385812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10291 01:35:27.146933 <6>[ 0.394799] loop: module loaded
10292 01:35:27.152838 <6>[ 0.397482] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10293 01:35:27.157708 <4>[ 0.414690] mtk-pmic-keys: Failed to locate of_node [id: -1]
10294 01:35:27.161391 <6>[ 0.415719] megasas: 07.719.03.00-rc1
10295 01:35:27.164969 <6>[ 0.434855] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10296 01:35:27.171479 <6>[ 0.435780] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10297 01:35:27.178175 <6>[ 0.446915] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10298 01:35:27.188201 <6>[ 0.499770] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10299 01:35:29.594572 <6>[ 2.926895] Freeing initrd memory: 59552K
10300 01:35:29.602283 <6>[ 2.934358] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10301 01:35:29.609214 <6>[ 2.939040] tun: Universal TUN/TAP device driver, 1.6
10302 01:35:29.612380 <6>[ 2.939808] thunder_xcv, ver 1.0
10303 01:35:29.615960 <6>[ 2.939827] thunder_bgx, ver 1.0
10304 01:35:29.618804 <6>[ 2.939844] nicpf, ver 1.0
10305 01:35:29.625252 <6>[ 2.940896] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10306 01:35:29.631988 <6>[ 2.940899] hns3: Copyright (c) 2017 Huawei Corporation.
10307 01:35:29.635539 <6>[ 2.940924] hclge is initializing
10308 01:35:29.641961 <6>[ 2.940938] e1000: Intel(R) PRO/1000 Network Driver
10309 01:35:29.645375 <6>[ 2.940940] e1000: Copyright (c) 1999-2006 Intel Corporation.
10310 01:35:29.653039 <6>[ 2.940960] e1000e: Intel(R) PRO/1000 Network Driver
10311 01:35:29.656566 <6>[ 2.940962] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10312 01:35:29.663516 <6>[ 2.940977] igb: Intel(R) Gigabit Ethernet Network Driver
10313 01:35:29.670146 <6>[ 2.940979] igb: Copyright (c) 2007-2014 Intel Corporation.
10314 01:35:29.677101 <6>[ 2.940994] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10315 01:35:29.680932 <6>[ 2.940996] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10316 01:35:29.687230 <6>[ 2.941286] sky2: driver version 1.30
10317 01:35:29.694052 <6>[ 2.942281] usbcore: registered new device driver r8152-cfgselector
10318 01:35:29.697159 <6>[ 2.942301] usbcore: registered new interface driver r8152
10319 01:35:29.703877 <6>[ 2.942379] VFIO - User Level meta-driver version: 0.3
10320 01:35:29.710572 <6>[ 2.945173] usbcore: registered new interface driver usb-storage
10321 01:35:29.717342 <6>[ 2.945358] usbcore: registered new device driver onboard-usb-hub
10322 01:35:29.720126 <6>[ 2.948154] mt6397-rtc mt6359-rtc: registered as rtc0
10323 01:35:29.730036 <6>[ 2.948302] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T01:35:29 UTC (1717551329)
10324 01:35:29.733269 <6>[ 2.948916] i2c_dev: i2c /dev entries driver
10325 01:35:29.743205 <6>[ 2.956008] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10326 01:35:29.749972 <4>[ 2.956731] cpu cpu0: supply cpu not found, using dummy regulator
10327 01:35:29.756737 <4>[ 2.956809] cpu cpu1: supply cpu not found, using dummy regulator
10328 01:35:29.763414 <4>[ 2.956867] cpu cpu2: supply cpu not found, using dummy regulator
10329 01:35:29.770156 <4>[ 2.956920] cpu cpu3: supply cpu not found, using dummy regulator
10330 01:35:29.773098 <4>[ 2.956984] cpu cpu4: supply cpu not found, using dummy regulator
10331 01:35:29.779678 <4>[ 2.957040] cpu cpu5: supply cpu not found, using dummy regulator
10332 01:35:29.786428 <4>[ 2.957090] cpu cpu6: supply cpu not found, using dummy regulator
10333 01:35:29.793472 <4>[ 2.957142] cpu cpu7: supply cpu not found, using dummy regulator
10334 01:35:29.799512 <6>[ 2.971413] cpu cpu0: EM: created perf domain
10335 01:35:29.802624 <6>[ 2.971749] cpu cpu4: EM: created perf domain
10336 01:35:29.809655 <6>[ 2.973641] sdhci: Secure Digital Host Controller Interface driver
10337 01:35:29.812782 <6>[ 2.973642] sdhci: Copyright(c) Pierre Ossman
10338 01:35:29.819130 <6>[ 2.973962] Synopsys Designware Multimedia Card Interface Driver
10339 01:35:29.825966 <6>[ 2.974328] sdhci-pltfm: SDHCI platform and OF driver helper
10340 01:35:29.832431 <6>[ 2.978650] ledtrig-cpu: registered to indicate activity on CPUs
10341 01:35:29.835815 <6>[ 2.979398] mmc0: CQHCI version 5.10
10342 01:35:29.842608 <6>[ 2.979432] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10343 01:35:29.849497 <6>[ 2.979711] usbcore: registered new interface driver usbhid
10344 01:35:29.852469 <6>[ 2.979712] usbhid: USB HID core driver
10345 01:35:29.859041 <6>[ 2.979821] spi_master spi0: will run message pump with realtime priority
10346 01:35:29.872273 <6>[ 3.008897] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10347 01:35:29.885368 <6>[ 3.011163] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10348 01:35:29.892236 <6>[ 3.012110] cros-ec-spi spi0.0: Chrome EC device registered
10349 01:35:29.901954 <6>[ 3.025699] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10350 01:35:29.905355 <6>[ 3.026590] NET: Registered PF_PACKET protocol family
10351 01:35:29.911769 <6>[ 3.026659] 9pnet: Installing 9P2000 support
10352 01:35:29.915502 <5>[ 3.026694] Key type dns_resolver registered
10353 01:35:29.918254 <6>[ 3.026964] registered taskstats version 1
10354 01:35:29.925011 <5>[ 3.026980] Loading compiled-in X.509 certificates
10355 01:35:29.934828 <4>[ 3.042576] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10356 01:35:29.945004 <4>[ 3.042783] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10357 01:35:29.951363 <6>[ 3.051495] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10358 01:35:29.957957 <6>[ 3.052011] xhci-mtk 11200000.usb: xHCI Host Controller
10359 01:35:29.964565 <6>[ 3.052027] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10360 01:35:29.974599 <6>[ 3.052232] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10361 01:35:29.981352 <6>[ 3.052267] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10362 01:35:29.984343 <6>[ 3.052328] xhci-mtk 11200000.usb: xHCI Host Controller
10363 01:35:29.994209 <6>[ 3.052330] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10364 01:35:30.000686 <6>[ 3.052334] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10365 01:35:30.004091 <6>[ 3.052628] hub 1-0:1.0: USB hub found
10366 01:35:30.007249 <6>[ 3.052636] hub 1-0:1.0: 1 port detected
10367 01:35:30.017393 <6>[ 3.052722] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10368 01:35:30.020803 <6>[ 3.052831] hub 2-0:1.0: USB hub found
10369 01:35:30.024123 <6>[ 3.052837] hub 2-0:1.0: 1 port detected
10370 01:35:30.030754 <6>[ 3.054932] mtk-msdc 11f70000.mmc: Got CD GPIO
10371 01:35:30.037367 <6>[ 3.068503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10372 01:35:30.046911 <6>[ 3.068507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10373 01:35:30.053522 <4>[ 3.068559] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10374 01:35:30.060051 <6>[ 3.068643] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10375 01:35:30.070208 <6>[ 3.069041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10376 01:35:30.076989 <6>[ 3.069042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10377 01:35:30.083198 <6>[ 3.069174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10378 01:35:30.093199 <6>[ 3.069183] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10379 01:35:30.099926 <6>[ 3.069185] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10380 01:35:30.110164 <6>[ 3.069188] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10381 01:35:30.116561 <6>[ 3.070228] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10382 01:35:30.126069 <6>[ 3.070241] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10383 01:35:30.136189 <6>[ 3.070243] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10384 01:35:30.142774 <6>[ 3.070246] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10385 01:35:30.152648 <6>[ 3.070248] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10386 01:35:30.159074 <6>[ 3.070251] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10387 01:35:30.169235 <6>[ 3.070254] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10388 01:35:30.175632 <6>[ 3.070257] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10389 01:35:30.185972 <6>[ 3.070259] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10390 01:35:30.192410 <6>[ 3.070262] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10391 01:35:30.201819 <6>[ 3.070264] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10392 01:35:30.208896 <6>[ 3.070266] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10393 01:35:30.218411 <6>[ 3.070269] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10394 01:35:30.225186 <6>[ 3.070271] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10395 01:35:30.234869 <6>[ 3.070274] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10396 01:35:30.241558 <6>[ 3.070612] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10397 01:35:30.248358 <6>[ 3.071242] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10398 01:35:30.255215 <6>[ 3.071492] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10399 01:35:30.261488 <6>[ 3.071743] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10400 01:35:30.268200 <6>[ 3.071960] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10401 01:35:30.278004 <6>[ 3.072107] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10402 01:35:30.285240 <6>[ 3.072118] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10403 01:35:30.294722 <6>[ 3.072121] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10404 01:35:30.304351 <6>[ 3.072124] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10405 01:35:30.314329 <6>[ 3.072128] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10406 01:35:30.324157 <6>[ 3.072132] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10407 01:35:30.331369 <6>[ 3.072137] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10408 01:35:30.340842 <6>[ 3.072141] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10409 01:35:30.350880 <6>[ 3.072143] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10410 01:35:30.360512 <6>[ 3.072148] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10411 01:35:30.370916 <6>[ 3.072151] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10412 01:35:30.380242 <6>[ 3.073003] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10413 01:35:30.383908 <6>[ 3.073169] mmc0: Command Queue Engine enabled
10414 01:35:30.390451 <6>[ 3.073189] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10415 01:35:30.397048 <6>[ 3.073826] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10416 01:35:30.400049 <6>[ 3.077303] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10417 01:35:30.406783 <6>[ 3.078204] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10418 01:35:30.413544 <6>[ 3.078744] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10419 01:35:30.419947 <6>[ 3.079275] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10420 01:35:30.426418 <6>[ 3.435795] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10421 01:35:30.429907 <6>[ 3.463104] hub 2-1:1.0: USB hub found
10422 01:35:30.433464 <6>[ 3.463586] hub 2-1:1.0: 3 ports detected
10423 01:35:30.436379 <6>[ 3.466738] hub 2-1:1.0: USB hub found
10424 01:35:30.443645 <6>[ 3.467083] hub 2-1:1.0: 3 ports detected
10425 01:35:30.449912 <6>[ 3.587615] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10426 01:35:30.453150 <6>[ 3.744532] hub 1-1:1.0: USB hub found
10427 01:35:30.456608 <6>[ 3.744926] hub 1-1:1.0: 4 ports detected
10428 01:35:30.460004 <6>[ 3.748658] hub 1-1:1.0: USB hub found
10429 01:35:30.466241 <6>[ 3.749049] hub 1-1:1.0: 4 ports detected
10430 01:35:30.497739 <6>[ 3.823753] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10431 01:35:30.601850 <6>[ 3.928369] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10432 01:35:30.625605 <4>[ 3.955033] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10433 01:35:30.635527 <4>[ 3.955048] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10434 01:35:30.666354 <6>[ 3.997413] r8152 2-1.3:1.0 eth0: v1.12.13
10435 01:35:30.733512 <6>[ 4.059761] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10436 01:35:30.854291 <6>[ 4.186724] hub 1-1.4:1.0: USB hub found
10437 01:35:30.857716 <6>[ 4.187052] hub 1-1.4:1.0: 2 ports detected
10438 01:35:30.861113 <6>[ 4.189269] hub 1-1.4:1.0: USB hub found
10439 01:35:30.867754 <6>[ 4.189593] hub 1-1.4:1.0: 2 ports detected
10440 01:35:31.149679 <6>[ 4.475576] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10441 01:35:31.333506 <6>[ 4.659551] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10442 01:35:32.270142 <6>[ 5.601293] r8152 2-1.3:1.0 eth0: carrier on
10443 01:35:34.822034 <5>[ 5.631671] Sending DHCP requests .., OK
10444 01:35:34.828487 <6>[ 8.151586] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10445 01:35:34.831813 <6>[ 8.151600] IP-Config: Complete:
10446 01:35:34.845275 <6>[ 8.151602] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10447 01:35:34.851701 <6>[ 8.151609] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10448 01:35:34.858237 <6>[ 8.151612] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10449 01:35:34.865055 <6>[ 8.151616] nameserver0=192.168.201.1
10450 01:35:34.868708 <6>[ 8.151850] clk: Disabling unused clocks
10451 01:35:34.871694 <6>[ 8.152738] ALSA device list:
10452 01:35:34.874980 <6>[ 8.152751] No soundcards found.
10453 01:35:34.881822 <6>[ 8.157015] Freeing unused kernel memory: 8512K
10454 01:35:34.884982 <6>[ 8.157195] Run /init as init process
10455 01:35:34.893783 <6>[ 8.223875] NET: Registered PF_INET6 protocol family
10456 01:35:34.897520 <6>[ 8.225150] Segment Routing with IPv6
10457 01:35:34.898068
10458 01:35:34.907256 Welcome to [1mDebian GNU/Linu<6>[ 8.225175] In-situ OAM (IOAM) with IPv6
10459 01:35:34.940091 x 12 (bookworm)<30>[ 8.236938] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10460 01:35:34.946588 <30>[ 8.236958] systemd[1]: Detected architecture arm64.
10461 01:35:34.947278 [0m!
10462 01:35:34.947655
10463 01:35:34.965943 <30>[ 8.295741] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10464 01:35:35.081473 <30>[ 8.410509] systemd[1]: Queued start job for default target graphical.target.
10465 01:35:35.111045 [[0;32m OK [0m] Created slic<30>[ 8.437678] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10466 01:35:35.114266 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10467 01:35:35.137594 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 8.464323] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10468 01:35:35.140933 m-modpr…lice[0m - Slice /system/modprobe.
10469 01:35:35.166395 [[0;32m OK [0m] Created slic<30>[ 8.493212] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10470 01:35:35.172859 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10471 01:35:35.194180 [[0;32m OK [0m] Created slic<30>[ 8.521064] systemd[1]: Created slice user.slice - User and Session Slice.
10472 01:35:35.197360 e [0;1;39muser.slice[0m - User and Session Slice.
10473 01:35:35.225132 [[0;32m OK [0m] Started [0;<30>[ 8.548616] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10474 01:35:35.228203 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10475 01:35:35.251996 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 8.575844] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10476 01:35:35.255230 -passwo… Requests to Wall Directory Watch.
10477 01:35:35.291162 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 8.604220] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10478 01:35:35.297792 <30>[ 8.604384] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10479 01:35:35.300530 ice[0m - /dev/ttyS0...
10480 01:35:35.321161 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 8.648072] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10481 01:35:35.324500 tsetup.…get[0m - Local Encrypted Volumes.
10482 01:35:35.348138 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 8.671825] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10483 01:35:35.351493 grityse…Local Integrity Protected Volumes.
10484 01:35:35.373242 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 8.700236] systemd[1]: Reached target paths.target - Path Units.
10485 01:35:35.373755 s.target[0m - Path Units.
10486 01:35:35.397356 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 8.724073] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10487 01:35:35.400366 te-fs.target[0m - Remote File Systems.
10488 01:35:35.420701 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 8.747748] systemd[1]: Reached target slices.target - Slice Units.
10489 01:35:35.423986 es.target[0m - Slice Units.
10490 01:35:35.445263 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 8.772174] systemd[1]: Reached target swap.target - Swaps.
10491 01:35:35.445909 .target[0m - Swaps.
10492 01:35:35.469362 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 8.796275] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10493 01:35:35.476118 tysetup… - Local Verity Protected Volumes.
10494 01:35:35.498017 [[0;32m OK [0m] Listening on<30>[ 8.824669] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10495 01:35:35.504352 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10496 01:35:35.527108 [[0;32m OK [0m] Listening on<30>[ 8.853683] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10497 01:35:35.533226 [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10498 01:35:35.556782 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.880424] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10499 01:35:35.559915 d-journ…t[0m - Journal Socket (/dev/log).
10500 01:35:35.581743 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.908459] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10501 01:35:35.585115 d-journald.socket[0m - Journal Socket.
10502 01:35:35.605765 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.932427] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10503 01:35:35.612307 d-udevd….socket[0m - udev Control Socket.
10504 01:35:35.634162 [[0;32m OK [0m] Listening on<30>[ 8.960873] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10505 01:35:35.640491 [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10506 01:35:35.697097 Mounting [0;1;39mdev-hugepages.mount[<30>[ 9.024059] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10507 01:35:35.700560 0m - Huge Pages File System...
10508 01:35:35.716858 Mounting [0;1;39mdev-mqueue.mount…P<30>[ 9.043523] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10509 01:35:35.720278 OSIX Message Queue File System...
10510 01:35:35.741386 <30>[ 9.071381] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10511 01:35:35.748103 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10512 01:35:35.775644 <30>[ 9.095981] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10513 01:35:35.785730 Startin<30>[ 9.100756] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10514 01:35:35.792155 g [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10515 01:35:35.837047 Starting [0;1;39mmodprobe@configfs…m<30>[ 9.164094] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10516 01:35:35.840722 - Load Kernel Module configfs...
10517 01:35:35.870229 Starting [0;1;39mmodpr<30>[ 9.197229] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10518 01:35:35.873626 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10519 01:35:35.885444 <6>[ 9.212306] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10520 01:35:35.902730 Starting [0;1;39mmodpr<30>[ 9.229557] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10521 01:35:35.906154 obe@drm.service[0m - Load Kernel Module drm...
10522 01:35:35.934021 Starting [0;1;39mmodpr<30>[ 9.260796] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10523 01:35:35.937075 obe@efi_psto…- Load Kernel Module efi_pstore...
10524 01:35:35.966028 Starting [0;1;39mmodpr<30>[ 9.292962] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10525 01:35:35.969204 obe@loop.ser…e[0m - Load Kernel Module loop...
10526 01:35:36.001685 Starting [0;1;39msystemd-journald.serv<30>[ 9.328618] systemd[1]: Starting systemd-journald.service - Journal Service...
10527 01:35:36.004850 ice[0m - Journal Service...
10528 01:35:36.024195 Startin<30>[ 9.354455] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10529 01:35:36.030949 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10530 01:35:36.060745 Starting [0;1;39msystemd-network-g… <30>[ 9.384384] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10531 01:35:36.064003 units from Kernel command line...
10532 01:35:36.092662 Starting [0;1;39msystemd-remount-f…n<30>[ 9.415961] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10533 01:35:36.095743 t Root and Kernel File Systems...
10534 01:35:36.121886 Starting [0;1;39msystemd-udev-trig…[<30>[ 9.448171] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10535 01:35:36.125124 0m - Coldplug All udev Devices...
10536 01:35:36.153058 [[0;32m OK [<30>[ 9.483305] systemd[1]: Started systemd-journald.service - Journal Service.
10537 01:35:36.159726 0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10538 01:35:36.181096 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10539 01:35:36.198699 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10540 01:35:36.218849 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10541 01:35:36.243249 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10542 01:35:36.264552 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10543 01:35:36.287964 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10544 01:35:36.312881 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10545 01:35:36.336825 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10546 01:35:36.359719 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10547 01:35:36.382775 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10548 01:35:36.406586 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10549 01:35:36.431821 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10550 01:35:36.450011 See 'systemctl status systemd-remount-fs.service' for details.
10551 01:35:36.475114 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10552 01:35:36.499841 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10553 01:35:36.553915 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10554 01:35:36.578000 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10555 01:35:36.596906 <46>[ 9.926851] systemd-journald[197]: Received client request to flush runtime journal.
10556 01:35:36.603384 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10557 01:35:36.630272 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10558 01:35:36.656341 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10559 01:35:36.682440 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10560 01:35:36.701964 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10561 01:35:36.726472 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10562 01:35:36.746935 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10563 01:35:36.766892 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10564 01:35:36.806125 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10565 01:35:36.828529 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10566 01:35:36.845725 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10567 01:35:36.861459 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10568 01:35:36.910069 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10569 01:35:36.935032 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10570 01:35:36.999166 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10571 01:35:37.020606 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10572 01:35:37.092053 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10573 01:35:37.239265 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10574 01:35:37.265441 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10575 01:35:37.310232 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10576 01:35:37.325027 <6>[ 10.655266] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10577 01:35:37.337230 <3>[ 10.666973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10578 01:35:37.343475 <3>[ 10.667035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10579 01:35:37.353656 <3>[ 10.667050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10580 01:35:37.366731 [[0;32m OK [0m] Created slice [0;1;39msyste<3>[ 10.695261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10581 01:35:37.376470 m-syste…- Slic<3>[ 10.695338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10582 01:35:37.383276 <3>[ 10.695351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10583 01:35:37.389843 <3>[ 10.695367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10584 01:35:37.399725 <3>[ 10.695377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10585 01:35:37.403079 <6>[ 10.697670] remoteproc remoteproc0: scp is available
10586 01:35:37.409743 e /system/system<6>[ 10.697864] remoteproc remoteproc0: powering up scp
10587 01:35:37.419472 <6>[ 10.697870] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10588 01:35:37.426740 <6>[ 10.697890] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10589 01:35:37.433707 <3>[ 10.714317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10590 01:35:37.440146 <6>[ 10.714985] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10591 01:35:37.443534 d-backlight.
10592 01:35:37.450234 <6>[ 10.715040] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10593 01:35:37.460213 <6>[ 10.715050] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10594 01:35:37.466704 <3>[ 10.715088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10595 01:35:37.477178 <3>[ 10.715103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10596 01:35:37.484017 <3>[ 10.715113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10597 01:35:37.490735 <6>[ 10.717366] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10598 01:35:37.501060 <3>[ 10.738934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10599 01:35:37.507950 <3>[ 10.738956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10600 01:35:37.514895 <3>[ 10.738959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10601 01:35:37.525012 <3>[ 10.738964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10602 01:35:37.531280 <3>[ 10.738967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10603 01:35:37.541312 <4>[ 10.750910] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10604 01:35:37.544865 <4>[ 10.750910] Fallback method does not support PEC.
10605 01:35:37.555443 [[0;32m OK [<3>[ 10.751575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10606 01:35:37.561856 <4>[ 10.754955] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10607 01:35:37.568679 <4>[ 10.762972] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10608 01:35:37.578874 <3>[ 10.773474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10609 01:35:37.581896 <6>[ 10.794410] mc: Linux media interface: v0.10
10610 01:35:37.592128 <3>[ 10.816480] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 01:35:37.602507 0m] Reached targ<3>[ 10.817253] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10612 01:35:37.609522 <6>[ 10.823326] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10613 01:35:37.619069 et [0;1;39mtime<6>[ 10.823391] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10614 01:35:37.626238 -set.target[0m <6>[ 10.823396] remoteproc remoteproc0: remote processor scp is now up
10615 01:35:37.633042 <6>[ 10.832944] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10616 01:35:37.639375 - System Time Se<6>[ 10.832961] pci_bus 0000:00: root bus resource [bus 00-ff]
10617 01:35:37.646655 <6>[ 10.832973] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10618 01:35:37.656174 <6>[ 10.832980] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10619 01:35:37.656732 t.
10620 01:35:37.663046 <6>[ 10.833026] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10621 01:35:37.669685 <6>[ 10.833040] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10622 01:35:37.676438 <6>[ 10.833123] pci 0000:00:00.0: supports D1 D2
10623 01:35:37.683312 <6>[ 10.833125] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10624 01:35:37.690280 <6>[ 10.841917] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10625 01:35:37.697013 <6>[ 10.842063] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10626 01:35:37.703888 <6>[ 10.842097] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10627 01:35:37.710449 <6>[ 10.842118] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10628 01:35:37.721008 <6>[ 10.842136] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10629 01:35:37.723953 <6>[ 10.842260] pci 0000:01:00.0: supports D1 D2
10630 01:35:37.731233 <6>[ 10.842264] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10631 01:35:37.741060 <3>[ 10.851022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 01:35:37.748242 <6>[ 10.851504] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10633 01:35:37.754950 <6>[ 10.851539] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10634 01:35:37.761532 <6>[ 10.851545] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10635 01:35:37.771724 <6>[ 10.851557] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10636 01:35:37.777964 <6>[ 10.851574] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10637 01:35:37.788197 <6>[ 10.851589] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10638 01:35:37.791779 <6>[ 10.851605] pci 0000:00:00.0: PCI bridge to [bus 01]
10639 01:35:37.801433 <6>[ 10.851613] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10640 01:35:37.807921 <3>[ 10.851808] power_supply sbs-5-000b: driver failed to report `health' property: -6
10641 01:35:37.814311 <6>[ 10.851942] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10642 01:35:37.821273 <6>[ 10.852922] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10643 01:35:37.824314 <6>[ 10.853138] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10644 01:35:37.834185 <6>[ 10.855668] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10645 01:35:37.840818 <6>[ 10.857413] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10646 01:35:37.850891 <6>[ 10.885414] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10647 01:35:37.860511 <6>[ 10.893406] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10648 01:35:37.870644 <6>[ 10.893644] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10649 01:35:37.880710 <3>[ 10.895284] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 01:35:37.887337 <3>[ 10.897807] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10651 01:35:37.893764 <6>[ 10.909149] videodev: Linux video capture interface: v2.00
10652 01:35:37.903610 <5>[ 10.919019] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10653 01:35:37.909995 <3>[ 10.938632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10654 01:35:37.913584 <6>[ 10.941080] Bluetooth: Core ver 2.22
10655 01:35:37.920287 <6>[ 10.941219] NET: Registered PF_BLUETOOTH protocol family
10656 01:35:37.926614 <6>[ 10.941224] Bluetooth: HCI device and connection manager initialized
10657 01:35:37.933238 <6>[ 10.941269] Bluetooth: HCI socket layer initialized
10658 01:35:37.936668 <6>[ 10.941281] Bluetooth: L2CAP socket layer initialized
10659 01:35:37.943106 <6>[ 10.941307] Bluetooth: SCO socket layer initialized
10660 01:35:37.949954 <5>[ 10.943110] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10661 01:35:37.956805 <5>[ 10.943324] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10662 01:35:37.966597 <4>[ 10.943382] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10663 01:35:37.972941 <6>[ 10.943387] cfg80211: failed to load regulatory.db
10664 01:35:37.979372 <3>[ 10.962841] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 01:35:37.986001 <6>[ 10.987224] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10666 01:35:37.999176 <6>[ 10.988325] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10667 01:35:38.005914 <6>[ 10.988481] usbcore: registered new interface driver uvcvideo
10668 01:35:38.015990 <3>[ 11.003676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 01:35:38.019256 <6>[ 11.011999] usbcore: registered new interface driver btusb
10670 01:35:38.032188 <4>[ 11.014677] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10671 01:35:38.035473 <3>[ 11.014705] Bluetooth: hci0: Failed to load firmware file (-2)
10672 01:35:38.042232 <3>[ 11.014708] Bluetooth: hci0: Failed to set up firmware (-2)
10673 01:35:38.052059 <4>[ 11.014712] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10674 01:35:38.058680 <6>[ 11.022574] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10675 01:35:38.068618 <6>[ 11.062904] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10676 01:35:38.071711 <6>[ 11.063000] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10677 01:35:38.078668 <6>[ 11.079604] mt7921e 0000:01:00.0: ASIC revision: 79610010
10678 01:35:38.088392 <6>[ 11.174294] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10679 01:35:38.088953 <6>[ 11.174294]
10680 01:35:38.095494 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10681 01:35:38.104740 <6>[ 11.434494] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10682 01:35:38.114882 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10683 01:35:38.138148 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10684 01:35:38.186742 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10685 01:35:38.207921 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10686 01:35:38.225205 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10687 01:35:38.243520 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10688 01:35:38.259107 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10689 01:35:38.275488 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10690 01:35:38.311201 [[0;32m OK [0m] Reached target [0;1;39msock<46>[ 11.625755] systemd-journald[197]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
10691 01:35:38.327962 <46>[ 11.625781] systemd-journald[197]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
10692 01:35:38.331550 ets.target[0m - Socket Units.
10693 01:35:38.350271 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10694 01:35:38.365762 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10695 01:35:38.423149 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10696 01:35:38.455467 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10697 01:35:38.478933 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10698 01:35:38.501108 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10699 01:35:38.534777 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10700 01:35:38.588008 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10701 01:35:38.608245 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10702 01:35:38.626638 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10703 01:35:38.677832 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10704 01:35:38.694287 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10705 01:35:38.713750 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10706 01:35:38.735276 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10707 01:35:38.752847 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10708 01:35:38.805966 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10709 01:35:38.842681 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10710 01:35:38.900179
10711 01:35:38.902806 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10712 01:35:38.903369
10713 01:35:38.905904 debian-bookworm-arm64 login: root (automatic login)
10714 01:35:38.906367
10715 01:35:38.918507 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10716 01:35:38.918972
10717 01:35:38.925221 The programs included with the Debian GNU/Linux system are free software;
10718 01:35:38.931469 the exact distribution terms for each program are described in the
10719 01:35:38.934743 individual files in /usr/share/doc/*/copyright.
10720 01:35:38.935161
10721 01:35:38.941423 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10722 01:35:38.944833 permitted by applicable law.
10723 01:35:38.946090 Matched prompt #10: / #
10725 01:35:38.947082 Setting prompt string to ['/ #']
10726 01:35:38.947506 end: 2.2.5.1 login-action (duration 00:00:13) [common]
10728 01:35:38.948485 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
10729 01:35:38.948935 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10730 01:35:38.949330 Setting prompt string to ['/ #']
10731 01:35:38.949682 Forcing a shell prompt, looking for ['/ #']
10733 01:35:39.000488 / #
10734 01:35:39.001137 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10735 01:35:39.001599 Waiting using forced prompt support (timeout 00:02:30)
10736 01:35:39.002112 <6>[ 12.288781] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10737 01:35:39.006715
10738 01:35:39.007663 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10739 01:35:39.008196 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10740 01:35:39.008723 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10741 01:35:39.009427 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
10742 01:35:39.009959 end: 2 depthcharge-action (duration 00:01:34) [common]
10743 01:35:39.010642 start: 3 lava-test-retry (timeout 00:08:02) [common]
10744 01:35:39.011148 start: 3.1 lava-test-shell (timeout 00:08:02) [common]
10745 01:35:39.011581 Using namespace: common
10747 01:35:39.112763 / # #
10748 01:35:39.113377 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10749 01:35:39.119046 #
10750 01:35:39.119945 Using /lava-14173500
10752 01:35:39.221191 / # export SHELL=/bin/sh
10753 01:35:39.227817 export SHELL=/bin/sh
10755 01:35:39.329464 / # . /lava-14173500/environment
10756 01:35:39.336091 . /lava-14173500/environment
10758 01:35:39.437790 / # /lava-14173500/bin/lava-test-runner /lava-14173500/0
10759 01:35:39.438412 Test shell timeout: 10s (minimum of the action and connection timeout)
10760 01:35:39.443974 /lava-14173500/bin/lava-test-runner /lava-14173500/0
10761 01:35:39.465183 + export TESTRUN_ID=0_igt-gpu-panfrost
10762 01:35:39.471511 + cd /la<8>[ 12.800443] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14173500_1.5.2.3.1>
10763 01:35:39.472379 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14173500_1.5.2.3.1
10764 01:35:39.472775 Starting test lava.0_igt-gpu-panfrost (14173500_1.5.2.3.1)
10765 01:35:39.473200 Skipping test definition patterns.
10766 01:35:39.475161 va-14173500/0/tests/0_igt-gpu-panfrost
10767 01:35:39.475613 + cat uuid
10768 01:35:39.478066 + UUID=14173500_1.5.2.3.1
10769 01:35:39.478525 + set +x
10770 01:35:39.488127 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
10771 01:35:39.495661 <8>[ 12.827069] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10772 01:35:39.496595 Received signal: <TESTSET> START panfrost_gem_new
10773 01:35:39.497053 Starting test_set panfrost_gem_new
10774 01:35:39.511029 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.841627] [IGT] panfrost_gem_new: executing
10775 01:35:39.517876 <14>[ 12.843828] [IGT] panfrost_gem_new: exiting, ret=77
10776 01:35:39.524322 <8>[ 12.848403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10777 01:35:39.524900 .92-cip22-rt12 aarch64)
10778 01:35:39.525544 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10780 01:35:39.531085 Using I<14>[ 12.862900] [IGT] panfrost_gem_new: executing
10781 01:35:39.537853 <14>[ 12.864705] [IGT] panfrost_gem_new: exiting, ret=77
10782 01:35:39.544067 GT_SRANDOM=17175<8>[ 12.870351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10783 01:35:39.544820 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10785 01:35:39.547267 51339 for randomisation
10786 01:35:39.553935 Test requirement not met in function dr<14>[ 12.885398] [IGT] panfrost_gem_new: executing
10787 01:35:39.561062 <14>[ 12.887475] [IGT] panfrost_gem_new: exiting, ret=77
10788 01:35:39.567431 m_open_driver, f<8>[ 12.891641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10789 01:35:39.568255 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10791 01:35:39.574172 ile ../lib/drmte<8>[ 12.892850] <LAVA_SIGNAL_TESTSET STOP>
10792 01:35:39.575047 Received signal: <TESTSET> STOP
10793 01:35:39.575457 Closing test_set panfrost_gem_new
10794 01:35:39.580655 <8>[ 12.906704] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10795 01:35:39.581215 st.c:694:
10796 01:35:39.581899 Received signal: <TESTSET> START panfrost_get_param
10797 01:35:39.582267 Starting test_set panfrost_get_param
10798 01:35:39.586966 Test <14>[ 12.919373] [IGT] panfrost_get_param: executing
10799 01:35:39.587509 requirement: !(fd<0)
10800 01:35:39.597368 No known gpu found for chi<14>[ 12.925518] [IGT] panfrost_get_param: exiting, ret=77
10801 01:35:39.603696 <8>[ 12.930717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10802 01:35:39.604260 pset flags 0x32 (panfrost)
10803 01:35:39.604899 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10805 01:35:39.610113 Last errno: 2, No such file or directory
10806 01:35:39.613646 [1mSubtes<14>[ 12.946329] [IGT] panfrost_get_param: executing
10807 01:35:39.623508 t gem-new-4096: SKIP (0.000s)[0<14>[ 12.953889] [IGT] panfrost_get_param: exiting, ret=77
10808 01:35:39.630148 <8>[ 12.957882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10809 01:35:39.630706 m
10810 01:35:39.631350 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10812 01:35:39.637043 IGT-Version: 1.28-ga44ebfe (a<14>[ 12.969455] [IGT] panfrost_get_param: executing
10813 01:35:39.643284 <14>[ 12.971231] [IGT] panfrost_get_param: exiting, ret=77
10814 01:35:39.650014 <8>[ 12.976540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10815 01:35:39.651006 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10817 01:35:39.653351 <8>[ 12.978314] <LAVA_SIGNAL_TESTSET STOP>
10818 01:35:39.654238 Received signal: <TESTSET> STOP
10819 01:35:39.654653 Closing test_set panfrost_get_param
10820 01:35:39.663385 arch64) (Linux: 6.1.92-cip22-rt1<8>[ 12.994921] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10821 01:35:39.663939 2 aarch64)
10822 01:35:39.664583 Received signal: <TESTSET> START panfrost_prime
10823 01:35:39.664961 Starting test_set panfrost_prime
10824 01:35:39.666571 Using IGT_SRANDOM=1717551339 for randomisation
10825 01:35:39.673135 Test requirement not<14>[ 13.005888] [IGT] panfrost_prime: executing
10826 01:35:39.682765 met in function drm_open_driver<14>[ 13.013297] [IGT] panfrost_prime: exiting, ret=77
10827 01:35:39.689851 <8>[ 13.018441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10828 01:35:39.690586 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10830 01:35:39.692917 <8>[ 13.020320] <LAVA_SIGNAL_TESTSET STOP>
10831 01:35:39.693667 Received signal: <TESTSET> STOP
10832 01:35:39.694052 Closing test_set panfrost_prime
10833 01:35:39.696175 , file ../lib/drmtest.c:694:
10834 01:35:39.699527 Test requirement: !(fd<0)
10835 01:35:39.705943 No known gpu found for <8>[ 13.037547] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10836 01:35:39.706716 Received signal: <TESTSET> START panfrost_submit
10837 01:35:39.707076 Starting test_set panfrost_submit
10838 01:35:39.709483 chipset flags 0x32 (panfrost)
10839 01:35:39.712837 Last errno: 2, No such file or directory
10840 01:35:39.715915 [1mSub<14>[ 13.048891] [IGT] panfrost_submit: executing
10841 01:35:39.722558 test gem-new-0: <14>[ 13.050707] [IGT] panfrost_submit: exiting, ret=77
10842 01:35:39.729502 <8>[ 13.057237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10843 01:35:39.730303 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10845 01:35:39.732296 SKIP (0.000s)[0m
10846 01:35:39.742594 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <14>[ 13.071508] [IGT] panfrost_submit: executing
10847 01:35:39.745751 <14>[ 13.073594] [IGT] panfrost_submit: exiting, ret=77
10848 01:35:39.752361 <8>[ 13.078940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10849 01:35:39.753147 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10851 01:35:39.755551 6.1.92-cip22-rt12 aarch64)
10852 01:35:39.762301 Usin<14>[ 13.093031] [IGT] panfrost_submit: executing
10853 01:35:39.769010 g IGT_SRANDOM=1717551339 for ran<14>[ 13.100514] [IGT] panfrost_submit: exiting, ret=77
10854 01:35:39.778684 <8>[ 13.105779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10855 01:35:39.779245 domisation
10856 01:35:39.779889 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10858 01:35:39.788536 Test requirement not met in function drm_open_driver<14>[ 13.120654] [IGT] panfrost_submit: executing
10859 01:35:39.792044 , file ../lib/drmtest.c:694:
10860 01:35:39.798978 Test requirement: <14>[ 13.127160] [IGT] panfrost_submit: exiting, ret=77
10861 01:35:39.799539 !(fd<0)
10862 01:35:39.808713 No know<8>[ 13.131332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10863 01:35:39.809554 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10865 01:35:39.811715 n gpu found for chipset flags 0x32 (panfrost)
10866 01:35:39.815100 L<14>[ 13.146543] [IGT] panfrost_submit: executing
10867 01:35:39.822573 ast errno: 2, No<14>[ 13.148317] [IGT] panfrost_submit: exiting, ret=77
10868 01:35:39.831499 <8>[ 13.153362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
10869 01:35:39.832344 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
10871 01:35:39.834807 such file or directory
10872 01:35:39.841484 [1mSubtest gem-new-zer<14>[ 13.170704] [IGT] panfrost_submit: executing
10873 01:35:39.844783 <14>[ 13.172757] [IGT] panfrost_submit: exiting, ret=77
10874 01:35:39.854767 <8>[ 13.177069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
10875 01:35:39.855817 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
10877 01:35:39.861830 oed: SKIP (0.000<14>[ 13.193124] [IGT] panfrost_submit: executing
10878 01:35:39.862399 s)[0m
10879 01:35:39.868035 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10880 01:35:39.871331 Using IGT_SRANDOM=1717551339 for randomisation
10881 01:35:39.877859 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10882 01:35:39.881283 Test requirement: !(fd<0)
10883 01:35:39.884876 No known gpu found for chipset flags 0x32 (panfrost)
10884 01:35:39.887921 Last errno: 2, No such file or directory
10885 01:35:39.891444 [1mSubtest base-params: SKIP (0.000s)[0m
10886 01:35:39.897892 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10887 01:35:39.904539 Using IGT_SRANDOM=1717551339 for randomisation
10888 01:35:39.911503 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10889 01:35:39.912067 Test requirement: !(fd<0)
10890 01:35:39.917820 No known gpu found for chipset flags 0x32 (panfrost)
10891 01:35:39.920974 Last errno: 2, No such file or directory
10892 01:35:39.924405 [1mSubtest get-bad-param: SKIP (0.000s)[0m
10893 01:35:39.931408 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10894 01:35:39.934198 Using IGT_SRANDOM=1717551339 for randomisation
10895 01:35:39.944122 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10896 01:35:39.944684 Test requirement: !(fd<0)
10897 01:35:39.951050 No known gpu found for chipset flags 0x32 (panfrost)
10898 01:35:39.954039 Last errno: 2, No such file or directory
10899 01:35:39.957084 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10900 01:35:39.963716 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10901 01:35:39.966970 Using IGT_SRANDOM=1717551339 for randomisation
10902 01:35:39.973967 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10903 01:35:39.977072 Test requirement: !(fd<0)
10904 01:35:39.984006 No known gpu found for chipset flags 0x32 (panfrost)
10905 01:35:39.987191 Last errno: 2, No such file or directory
10906 01:35:39.990006 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
10907 01:35:39.997145 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10908 01:35:40.000210 Using IGT_SRANDOM=1717551339 for randomisation
10909 01:35:40.006618 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10910 01:35:40.010017 Test requirement: !(fd<0)
10911 01:35:40.013398 No known gpu found for chipset flags 0x32 (panfrost)
10912 01:35:40.020011 Last errno: 2, No such file or directory
10913 01:35:40.023697 [1mSubtest pan-submit: SKIP (0.000s)[0m
10914 01:35:40.030014 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10915 01:35:40.033194 Using IGT_SRANDOM=1717551339 for randomisation
10916 01:35:40.039897 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10917 01:35:40.043230 Test requirement: !(fd<0)
10918 01:35:40.046481 No known gpu found for chipset flags 0x32 (panfrost)
10919 01:35:40.049796 Last errno: 2, No such file or directory
10920 01:35:40.056353 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
10921 01:35:40.062855 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10922 01:35:40.066228 Using IGT_SRANDOM=1717551339 for randomisation
10923 01:35:40.072706 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10924 01:35:40.076006 Test requirement: !(fd<0)
10925 01:35:40.079246 No known gpu found for chipset flags 0x32 (panfrost)
10926 01:35:40.082521 Last errno: 2, No such file or directory
10927 01:35:40.089079 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
10928 01:35:40.096138 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10929 01:35:40.099267 Using IGT_SRANDOM=1717551339 for randomisation
10930 01:35:40.105686 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10931 01:35:40.109361 Test requirement: !(fd<0)
10932 01:35:40.112628 No known gpu found for chipset flags 0x32 (panfrost)
10933 01:35:40.115639 Last errno: 2, No such file or directory
10934 01:35:40.122099 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
10935 01:35:40.129080 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10936 01:35:40.132207 Using IGT_SRANDOM=1717551339 for randomisation
10937 01:35:40.138833 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10938 01:35:40.142184 Test requirement: !(fd<0)
10939 01:35:40.148606 No known gpu found for chipset flags 0x32 (panfrost)
10940 01:35:40.152041 Last errno: 2, No such file or directory
10941 01:35:40.155138 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
10942 01:35:40.161876 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10943 01:35:40.168566 Using IGT_SRANDOM=1717551339 for randomisation
10944 01:35:40.174846 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10945 01:35:40.178142 Test requirement: !(fd<0)
10946 01:35:40.181452 No known gpu found for chipset flags 0x32 (panfrost)
10947 01:35:40.185210 Last errno: 2, No such file or directory
10948 01:35:40.191347 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
10949 01:35:40.198133 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 13.532760] [IGT] panfrost_submit: exiting, ret=77
10950 01:35:40.201866 92-cip22-rt12 aarch64)
10951 01:35:40.207882 Using IG<8>[ 13.539246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
10952 01:35:40.208730 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
10954 01:35:40.211200 T_SRANDOM=1717551339 for randomisation
10955 01:35:40.218033 Test requirement not met<14>[ 13.550982] [IGT] panfrost_submit: executing
10956 01:35:40.228023 in function drm_open_driver, fi<14>[ 13.558806] [IGT] panfrost_submit: exiting, ret=77
10957 01:35:40.237948 le ../lib/drmtes<8>[ 13.563690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
10958 01:35:40.238535 t.c:694:
10959 01:35:40.239185 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
10961 01:35:40.240947 Test requirement: !(fd<0)
10962 01:35:40.247970 No known gpu found for chip<14>[ 13.578398] [IGT] panfrost_submit: executing
10963 01:35:40.254519 set flags 0x32 (<14>[ 13.580470] [IGT] panfrost_submit: exiting, ret=77
10964 01:35:40.255079 panfrost)
10965 01:35:40.261037 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
10967 01:35:40.264346 Last <8>[ 13.589293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
10968 01:35:40.267490 errno: 2, No suc<8>[ 13.593742] <LAVA_SIGNAL_TESTSET STOP>
10969 01:35:40.268319 Received signal: <TESTSET> STOP
10970 01:35:40.268709 Closing test_set panfrost_submit
10971 01:35:40.277831 h file or direct<8>[ 13.607486] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14173500_1.5.2.3.1>
10972 01:35:40.278406 ory
10973 01:35:40.279054 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14173500_1.5.2.3.1
10974 01:35:40.279484 Ending use of test pattern.
10975 01:35:40.279824 Ending test lava.0_igt-gpu-panfrost (14173500_1.5.2.3.1), duration 0.81
10977 01:35:40.281497 [1mSubtest pan-reset: SKIP (0.000s)[0m
10978 01:35:40.287685 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10979 01:35:40.290471 Using IGT_SRANDOM=1717551340 for randomisation
10980 01:35:40.297200 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10981 01:35:40.300535 Test requirement: !(fd<0)
10982 01:35:40.303863 No known gpu found for chipset flags 0x32 (panfrost)
10983 01:35:40.307221 Last errno: 2, No such file or directory
10984 01:35:40.313712 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
10985 01:35:40.320213 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
10986 01:35:40.323613 Using IGT_SRANDOM=1717551340 for randomisation
10987 01:35:40.329997 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10988 01:35:40.333531 Test requirement: !(fd<0)
10989 01:35:40.337004 No known gpu found for chipset flags 0x32 (panfrost)
10990 01:35:40.340213 Last errno: 2, No such file or directory
10991 01:35:40.346571 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
10992 01:35:40.347071 + set +x
10993 01:35:40.349819 <LAVA_TEST_RUNNER EXIT>
10994 01:35:40.350556 ok: lava_test_shell seems to have completed
10995 01:35:40.352124 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
10996 01:35:40.352613 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10997 01:35:40.353044 end: 3 lava-test-retry (duration 00:00:01) [common]
10998 01:35:40.353531 start: 4 finalize (timeout 00:08:00) [common]
10999 01:35:40.353978 start: 4.1 power-off (timeout 00:00:30) [common]
11000 01:35:40.354916 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11001 01:35:40.477469 >> Command sent successfully.
11002 01:35:40.487415 Returned 0 in 0 seconds
11003 01:35:40.588744 end: 4.1 power-off (duration 00:00:00) [common]
11005 01:35:40.590392 start: 4.2 read-feedback (timeout 00:08:00) [common]
11006 01:35:40.591793 Listened to connection for namespace 'common' for up to 1s
11007 01:35:41.592334 Finalising connection for namespace 'common'
11008 01:35:41.592944 Disconnecting from shell: Finalise
11009 01:35:41.593329 / #
11010 01:35:41.694322 end: 4.2 read-feedback (duration 00:00:01) [common]
11011 01:35:41.695057 end: 4 finalize (duration 00:00:01) [common]
11012 01:35:41.695613 Cleaning after the job
11013 01:35:41.696079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/ramdisk
11014 01:35:41.723665 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/kernel
11015 01:35:41.750421 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/dtb
11016 01:35:41.750690 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173500/tftp-deploy-70c7jjut/modules
11017 01:35:41.757478 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173500
11018 01:35:41.865139 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173500
11019 01:35:41.865330 Job finished correctly