Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 00:37:32.075791 lava-dispatcher, installed at version: 2024.03
2 00:37:32.076005 start: 0 validate
3 00:37:32.076148 Start time: 2024-06-05 00:37:32.076140+00:00 (UTC)
4 00:37:32.076273 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:37:32.076401 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:37:32.335430 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:37:32.335626 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:37:59.598123 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:37:59.598289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:37:59.855845 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:37:59.856073 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:38:00.111798 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:38:00.112013 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:38:02.618040 validate duration: 30.54
16 00:38:02.618301 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:38:02.618402 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:38:02.618488 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:38:02.618609 Not decompressing ramdisk as can be used compressed.
20 00:38:02.618693 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:38:02.618759 saving as /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/ramdisk/initrd.cpio.gz
22 00:38:02.618830 total size: 5628169 (5 MB)
23 00:38:02.868454 progress 0 % (0 MB)
24 00:38:02.870071 progress 5 % (0 MB)
25 00:38:02.871726 progress 10 % (0 MB)
26 00:38:02.873211 progress 15 % (0 MB)
27 00:38:02.874827 progress 20 % (1 MB)
28 00:38:02.876273 progress 25 % (1 MB)
29 00:38:02.877899 progress 30 % (1 MB)
30 00:38:02.879477 progress 35 % (1 MB)
31 00:38:02.880883 progress 40 % (2 MB)
32 00:38:02.882473 progress 45 % (2 MB)
33 00:38:02.883891 progress 50 % (2 MB)
34 00:38:02.885476 progress 55 % (2 MB)
35 00:38:02.887052 progress 60 % (3 MB)
36 00:38:02.888484 progress 65 % (3 MB)
37 00:38:02.890100 progress 70 % (3 MB)
38 00:38:02.891550 progress 75 % (4 MB)
39 00:38:02.893121 progress 80 % (4 MB)
40 00:38:02.894541 progress 85 % (4 MB)
41 00:38:02.896130 progress 90 % (4 MB)
42 00:38:02.897730 progress 95 % (5 MB)
43 00:38:02.899188 progress 100 % (5 MB)
44 00:38:02.899404 5 MB downloaded in 0.28 s (19.13 MB/s)
45 00:38:02.899561 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:38:02.899811 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:38:02.899898 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:38:02.899984 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:38:02.900135 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:38:02.900208 saving as /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/kernel/Image
52 00:38:02.900272 total size: 54682112 (52 MB)
53 00:38:02.900336 No compression specified
54 00:38:02.901497 progress 0 % (0 MB)
55 00:38:02.915640 progress 5 % (2 MB)
56 00:38:02.929902 progress 10 % (5 MB)
57 00:38:02.944352 progress 15 % (7 MB)
58 00:38:02.958612 progress 20 % (10 MB)
59 00:38:02.979485 progress 25 % (13 MB)
60 00:38:03.000778 progress 30 % (15 MB)
61 00:38:03.022229 progress 35 % (18 MB)
62 00:38:03.042360 progress 40 % (20 MB)
63 00:38:03.062130 progress 45 % (23 MB)
64 00:38:03.078219 progress 50 % (26 MB)
65 00:38:03.098541 progress 55 % (28 MB)
66 00:38:03.118938 progress 60 % (31 MB)
67 00:38:03.134344 progress 65 % (33 MB)
68 00:38:03.149169 progress 70 % (36 MB)
69 00:38:03.163959 progress 75 % (39 MB)
70 00:38:03.179018 progress 80 % (41 MB)
71 00:38:03.194093 progress 85 % (44 MB)
72 00:38:03.209723 progress 90 % (46 MB)
73 00:38:03.224136 progress 95 % (49 MB)
74 00:38:03.238554 progress 100 % (52 MB)
75 00:38:03.238888 52 MB downloaded in 0.34 s (154.01 MB/s)
76 00:38:03.239120 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:38:03.239522 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:38:03.239656 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:38:03.239786 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:38:03.239972 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:38:03.240078 saving as /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/dtb/mt8192-asurada-spherion-r0.dtb
83 00:38:03.240179 total size: 47258 (0 MB)
84 00:38:03.240282 No compression specified
85 00:38:03.241548 progress 69 % (0 MB)
86 00:38:03.241867 progress 100 % (0 MB)
87 00:38:03.242050 0 MB downloaded in 0.00 s (24.12 MB/s)
88 00:38:03.242237 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:38:03.242618 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:38:03.242746 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:38:03.242874 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:38:03.243041 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:38:03.243142 saving as /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/nfsrootfs/full.rootfs.tar
95 00:38:03.243243 total size: 120894716 (115 MB)
96 00:38:03.243345 Using unxz to decompress xz
97 00:38:03.247984 progress 0 % (0 MB)
98 00:38:03.635804 progress 5 % (5 MB)
99 00:38:04.056962 progress 10 % (11 MB)
100 00:38:04.432132 progress 15 % (17 MB)
101 00:38:04.808454 progress 20 % (23 MB)
102 00:38:05.112753 progress 25 % (28 MB)
103 00:38:05.494776 progress 30 % (34 MB)
104 00:38:05.857603 progress 35 % (40 MB)
105 00:38:06.037605 progress 40 % (46 MB)
106 00:38:06.224892 progress 45 % (51 MB)
107 00:38:06.562498 progress 50 % (57 MB)
108 00:38:06.975059 progress 55 % (63 MB)
109 00:38:07.340312 progress 60 % (69 MB)
110 00:38:07.709673 progress 65 % (74 MB)
111 00:38:08.087445 progress 70 % (80 MB)
112 00:38:08.457631 progress 75 % (86 MB)
113 00:38:08.809106 progress 80 % (92 MB)
114 00:38:09.169996 progress 85 % (98 MB)
115 00:38:09.591410 progress 90 % (103 MB)
116 00:38:09.954602 progress 95 % (109 MB)
117 00:38:10.376871 progress 100 % (115 MB)
118 00:38:10.382686 115 MB downloaded in 7.14 s (16.15 MB/s)
119 00:38:10.383061 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:38:10.383528 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:38:10.383682 start: 1.5 download-retry (timeout 00:09:52) [common]
123 00:38:10.383830 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 00:38:10.384059 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:38:10.384180 saving as /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/modules/modules.tar
126 00:38:10.384291 total size: 8605984 (8 MB)
127 00:38:10.384409 Using unxz to decompress xz
128 00:38:10.389814 progress 0 % (0 MB)
129 00:38:10.409400 progress 5 % (0 MB)
130 00:38:10.438387 progress 10 % (0 MB)
131 00:38:10.470737 progress 15 % (1 MB)
132 00:38:10.496538 progress 20 % (1 MB)
133 00:38:10.522263 progress 25 % (2 MB)
134 00:38:10.547659 progress 30 % (2 MB)
135 00:38:10.574124 progress 35 % (2 MB)
136 00:38:10.602592 progress 40 % (3 MB)
137 00:38:10.626549 progress 45 % (3 MB)
138 00:38:10.656863 progress 50 % (4 MB)
139 00:38:10.683052 progress 55 % (4 MB)
140 00:38:10.708476 progress 60 % (4 MB)
141 00:38:10.732837 progress 65 % (5 MB)
142 00:38:10.758241 progress 70 % (5 MB)
143 00:38:10.783283 progress 75 % (6 MB)
144 00:38:10.812148 progress 80 % (6 MB)
145 00:38:10.837171 progress 85 % (7 MB)
146 00:38:10.862743 progress 90 % (7 MB)
147 00:38:10.888715 progress 95 % (7 MB)
148 00:38:10.914771 progress 100 % (8 MB)
149 00:38:10.920274 8 MB downloaded in 0.54 s (15.31 MB/s)
150 00:38:10.920642 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:38:10.921114 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:38:10.921288 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:38:10.921469 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:38:15.243563 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8
156 00:38:15.243784 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:38:15.243889 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 00:38:15.244071 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr
159 00:38:15.244237 makedir: /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin
160 00:38:15.244388 makedir: /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/tests
161 00:38:15.244521 makedir: /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/results
162 00:38:15.244670 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-add-keys
163 00:38:15.244867 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-add-sources
164 00:38:15.245039 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-background-process-start
165 00:38:15.245183 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-background-process-stop
166 00:38:15.245325 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-common-functions
167 00:38:15.245455 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-echo-ipv4
168 00:38:15.245621 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-install-packages
169 00:38:15.245779 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-installed-packages
170 00:38:15.245943 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-os-build
171 00:38:15.246112 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-probe-channel
172 00:38:15.246285 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-probe-ip
173 00:38:15.246414 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-target-ip
174 00:38:15.246559 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-target-mac
175 00:38:15.246694 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-target-storage
176 00:38:15.246827 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-case
177 00:38:15.246956 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-event
178 00:38:15.247082 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-feedback
179 00:38:15.247223 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-raise
180 00:38:15.247388 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-reference
181 00:38:15.247553 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-runner
182 00:38:15.247719 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-set
183 00:38:15.247884 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-test-shell
184 00:38:15.248057 Updating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-add-keys (debian)
185 00:38:15.317564 Updating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-add-sources (debian)
186 00:38:15.317903 Updating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-install-packages (debian)
187 00:38:15.318143 Updating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-installed-packages (debian)
188 00:38:15.318366 Updating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/bin/lava-os-build (debian)
189 00:38:15.318568 Creating /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/environment
190 00:38:15.318728 LAVA metadata
191 00:38:15.318852 - LAVA_JOB_ID=14173454
192 00:38:15.318973 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:38:15.319169 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 00:38:15.319296 skipped lava-vland-overlay
195 00:38:15.319431 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:38:15.319575 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 00:38:15.319691 skipped lava-multinode-overlay
198 00:38:15.319827 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:38:15.319977 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 00:38:15.320119 Loading test definitions
201 00:38:15.320278 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 00:38:15.320417 Using /lava-14173454 at stage 0
203 00:38:15.320933 uuid=14173454_1.6.2.3.1 testdef=None
204 00:38:15.321087 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:38:15.321236 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 00:38:15.322007 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:38:15.322426 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 00:38:15.323381 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:38:15.323833 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 00:38:15.397063 runner path: /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/0/tests/0_timesync-off test_uuid 14173454_1.6.2.3.1
213 00:38:15.397375 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:38:15.397765 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 00:38:15.397883 Using /lava-14173454 at stage 0
217 00:38:15.398042 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:38:15.398176 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/0/tests/1_kselftest-alsa'
219 00:38:18.368276 Running '/usr/bin/git checkout kernelci.org
220 00:38:18.530206 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 00:38:18.530973 uuid=14173454_1.6.2.3.5 testdef=None
222 00:38:18.531139 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:38:18.531421 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 00:38:18.532261 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:38:18.532504 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 00:38:18.533621 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:38:18.533870 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 00:38:18.534818 runner path: /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/0/tests/1_kselftest-alsa test_uuid 14173454_1.6.2.3.5
232 00:38:18.534913 BOARD='mt8192-asurada-spherion-r0'
233 00:38:18.535006 BRANCH='cip-gitlab'
234 00:38:18.535094 SKIPFILE='/dev/null'
235 00:38:18.535153 SKIP_INSTALL='True'
236 00:38:18.535211 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:38:18.535270 TST_CASENAME=''
238 00:38:18.535326 TST_CMDFILES='alsa'
239 00:38:18.535473 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:38:18.535684 Creating lava-test-runner.conf files
242 00:38:18.535750 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173454/lava-overlay-5j6aevwr/lava-14173454/0 for stage 0
243 00:38:18.535844 - 0_timesync-off
244 00:38:18.535915 - 1_kselftest-alsa
245 00:38:18.536012 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:38:18.536104 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 00:38:26.463606 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:38:26.463776 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 00:38:26.463875 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:38:26.463977 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 00:38:26.464068 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 00:38:26.642746 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:38:26.643146 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 00:38:26.643267 extracting modules file /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8
255 00:38:26.861054 extracting modules file /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173454/extract-overlay-ramdisk-3wx7p3v9/ramdisk
256 00:38:27.084903 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:38:27.085072 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 00:38:27.085187 [common] Applying overlay to NFS
259 00:38:27.085258 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173454/compress-overlay-_iqe0ul9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8
260 00:38:28.050256 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:38:28.050448 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 00:38:28.050544 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:38:28.050633 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 00:38:28.050715 Building ramdisk /var/lib/lava/dispatcher/tmp/14173454/extract-overlay-ramdisk-3wx7p3v9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173454/extract-overlay-ramdisk-3wx7p3v9/ramdisk
265 00:38:28.405777 >> 130348 blocks
266 00:38:30.564985 rename /var/lib/lava/dispatcher/tmp/14173454/extract-overlay-ramdisk-3wx7p3v9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/ramdisk/ramdisk.cpio.gz
267 00:38:30.565430 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 00:38:30.565555 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 00:38:30.565655 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 00:38:30.565757 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/kernel/Image']
271 00:38:45.760704 Returned 0 in 15 seconds
272 00:38:45.861376 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/kernel/image.itb
273 00:38:46.225315 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:38:46.225715 output: Created: Wed Jun 5 01:38:46 2024
275 00:38:46.225822 output: Image 0 (kernel-1)
276 00:38:46.225923 output: Description:
277 00:38:46.226027 output: Created: Wed Jun 5 01:38:46 2024
278 00:38:46.226129 output: Type: Kernel Image
279 00:38:46.226236 output: Compression: lzma compressed
280 00:38:46.226341 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
281 00:38:46.226448 output: Architecture: AArch64
282 00:38:46.226547 output: OS: Linux
283 00:38:46.226640 output: Load Address: 0x00000000
284 00:38:46.226736 output: Entry Point: 0x00000000
285 00:38:46.226829 output: Hash algo: crc32
286 00:38:46.226924 output: Hash value: 4c96ec19
287 00:38:46.227026 output: Image 1 (fdt-1)
288 00:38:46.227121 output: Description: mt8192-asurada-spherion-r0
289 00:38:46.227237 output: Created: Wed Jun 5 01:38:46 2024
290 00:38:46.227334 output: Type: Flat Device Tree
291 00:38:46.227460 output: Compression: uncompressed
292 00:38:46.227556 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:38:46.227650 output: Architecture: AArch64
294 00:38:46.227749 output: Hash algo: crc32
295 00:38:46.227857 output: Hash value: 0f8e4d2e
296 00:38:46.227957 output: Image 2 (ramdisk-1)
297 00:38:46.228051 output: Description: unavailable
298 00:38:46.228143 output: Created: Wed Jun 5 01:38:46 2024
299 00:38:46.228236 output: Type: RAMDisk Image
300 00:38:46.228327 output: Compression: Unknown Compression
301 00:38:46.228419 output: Data Size: 18732751 Bytes = 18293.70 KiB = 17.86 MiB
302 00:38:46.228517 output: Architecture: AArch64
303 00:38:46.228619 output: OS: Linux
304 00:38:46.228711 output: Load Address: unavailable
305 00:38:46.228803 output: Entry Point: unavailable
306 00:38:46.228895 output: Hash algo: crc32
307 00:38:46.228993 output: Hash value: 7512fe8c
308 00:38:46.229084 output: Default Configuration: 'conf-1'
309 00:38:46.229176 output: Configuration 0 (conf-1)
310 00:38:46.229287 output: Description: mt8192-asurada-spherion-r0
311 00:38:46.229407 output: Kernel: kernel-1
312 00:38:46.229508 output: Init Ramdisk: ramdisk-1
313 00:38:46.229601 output: FDT: fdt-1
314 00:38:46.229693 output: Loadables: kernel-1
315 00:38:46.229785 output:
316 00:38:46.230050 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 00:38:46.230192 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 00:38:46.230352 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 00:38:46.230491 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 00:38:46.230612 No LXC device requested
321 00:38:46.230735 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:38:46.230881 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 00:38:46.231028 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:38:46.231135 Checking files for TFTP limit of 4294967296 bytes.
325 00:38:46.231834 end: 1 tftp-deploy (duration 00:00:44) [common]
326 00:38:46.231987 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:38:46.232128 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:38:46.232311 substitutions:
329 00:38:46.232411 - {DTB}: 14173454/tftp-deploy-7kc_004t/dtb/mt8192-asurada-spherion-r0.dtb
330 00:38:46.232515 - {INITRD}: 14173454/tftp-deploy-7kc_004t/ramdisk/ramdisk.cpio.gz
331 00:38:46.232629 - {KERNEL}: 14173454/tftp-deploy-7kc_004t/kernel/Image
332 00:38:46.232727 - {LAVA_MAC}: None
333 00:38:46.232830 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8
334 00:38:46.232930 - {NFS_SERVER_IP}: 192.168.201.1
335 00:38:46.233026 - {PRESEED_CONFIG}: None
336 00:38:46.233142 - {PRESEED_LOCAL}: None
337 00:38:46.233239 - {RAMDISK}: 14173454/tftp-deploy-7kc_004t/ramdisk/ramdisk.cpio.gz
338 00:38:46.233335 - {ROOT_PART}: None
339 00:38:46.233432 - {ROOT}: None
340 00:38:46.233527 - {SERVER_IP}: 192.168.201.1
341 00:38:46.233628 - {TEE}: None
342 00:38:46.233722 Parsed boot commands:
343 00:38:46.233816 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:38:46.234066 Parsed boot commands: tftpboot 192.168.201.1 14173454/tftp-deploy-7kc_004t/kernel/image.itb 14173454/tftp-deploy-7kc_004t/kernel/cmdline
345 00:38:46.234199 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:38:46.234331 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:38:46.234483 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:38:46.234636 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:38:46.234761 Not connected, no need to disconnect.
350 00:38:46.234878 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:38:46.235019 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:38:46.235134 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 00:38:46.239520 Setting prompt string to ['lava-test: # ']
354 00:38:46.239982 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:38:46.240138 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:38:46.240296 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:38:46.240452 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:38:46.240696 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
359 00:38:51.376785 >> Command sent successfully.
360 00:38:51.379680 Returned 0 in 5 seconds
361 00:38:51.480085 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 00:38:51.480413 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 00:38:51.480516 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 00:38:51.480627 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:38:51.480700 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:38:51.480773 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:38:51.481211 [Enter `^Ec?' for help]
369 00:38:51.652381
370 00:38:51.652610
371 00:38:51.652711 F0: 102B 0000
372 00:38:51.652777
373 00:38:51.652866 F3: 1001 0000 [0200]
374 00:38:51.652968
375 00:38:51.655857 F3: 1001 0000
376 00:38:51.655981
377 00:38:51.656141 F7: 102D 0000
378 00:38:51.656241
379 00:38:51.656372 F1: 0000 0000
380 00:38:51.659271
381 00:38:51.659373 V0: 0000 0000 [0001]
382 00:38:51.659500
383 00:38:51.659596 00: 0007 8000
384 00:38:51.662544
385 00:38:51.662647 01: 0000 0000
386 00:38:51.662748
387 00:38:51.662845 BP: 0C00 0209 [0000]
388 00:38:51.662940
389 00:38:51.665853 G0: 1182 0000
390 00:38:51.665972
391 00:38:51.666072 EC: 0000 0021 [4000]
392 00:38:51.666169
393 00:38:51.669276 S7: 0000 0000 [0000]
394 00:38:51.669362
395 00:38:51.669447 CC: 0000 0000 [0001]
396 00:38:51.672603
397 00:38:51.672714 T0: 0000 0040 [010F]
398 00:38:51.672817
399 00:38:51.672916 Jump to BL
400 00:38:51.673013
401 00:38:51.699244
402 00:38:51.699343
403 00:38:51.706269 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 00:38:51.710104 ARM64: Exception handlers installed.
405 00:38:51.713412 ARM64: Testing exception
406 00:38:51.716384 ARM64: Done test exception
407 00:38:51.723330 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 00:38:51.733798 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 00:38:51.740401 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 00:38:51.750556 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 00:38:51.757419 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 00:38:51.763939 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 00:38:51.775494 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 00:38:51.782257 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 00:38:51.801839 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 00:38:51.804895 WDT: Last reset was cold boot
417 00:38:51.807877 SPI1(PAD0) initialized at 2873684 Hz
418 00:38:51.811278 SPI5(PAD0) initialized at 992727 Hz
419 00:38:51.814761 VBOOT: Loading verstage.
420 00:38:51.821726 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 00:38:51.825133 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 00:38:51.828167 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 00:38:51.831650 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 00:38:51.839300 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 00:38:51.845560 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 00:38:51.856475 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
427 00:38:51.856643
428 00:38:51.856762
429 00:38:51.866576 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 00:38:51.869736 ARM64: Exception handlers installed.
431 00:38:51.873143 ARM64: Testing exception
432 00:38:51.873273 ARM64: Done test exception
433 00:38:51.879953 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 00:38:51.883484 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 00:38:51.897826 Probing TPM: . done!
436 00:38:51.897920 TPM ready after 0 ms
437 00:38:51.904355 Connected to device vid:did:rid of 1ae0:0028:00
438 00:38:51.911243 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 00:38:51.952265 Initialized TPM device CR50 revision 0
440 00:38:51.964706 tlcl_send_startup: Startup return code is 0
441 00:38:51.964836 TPM: setup succeeded
442 00:38:51.975580 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 00:38:51.984598 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 00:38:51.996901 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 00:38:52.007532 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 00:38:52.007666 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 00:38:52.011410 in-header: 03 07 00 00 08 00 00 00
448 00:38:52.015084 in-data: aa e4 47 04 13 02 00 00
449 00:38:52.018891 Chrome EC: UHEPI supported
450 00:38:52.025983 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 00:38:52.029246 in-header: 03 9d 00 00 08 00 00 00
452 00:38:52.032665 in-data: 10 20 20 08 00 00 00 00
453 00:38:52.032764 Phase 1
454 00:38:52.036515 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 00:38:52.043593 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 00:38:52.051283 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 00:38:52.051407 Recovery requested (1009000e)
458 00:38:52.059477 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:38:52.065293 tlcl_extend: response is 0
460 00:38:52.072962 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:38:52.079032 tlcl_extend: response is 0
462 00:38:52.085573 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:38:52.106856 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
464 00:38:52.113857 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:38:52.113990
466 00:38:52.114089
467 00:38:52.121272 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:38:52.125085 ARM64: Exception handlers installed.
469 00:38:52.128513 ARM64: Testing exception
470 00:38:52.131573 ARM64: Done test exception
471 00:38:52.148496 pmic_efuse_setting: Set efuses in 11 msecs
472 00:38:52.157636 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:38:52.161276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:38:52.164845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:38:52.172164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:38:52.175544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:38:52.179921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:38:52.183309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:38:52.190658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:38:52.194171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:38:52.197579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:38:52.204298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:38:52.207760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:38:52.214055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:38:52.217564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:38:52.224042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:38:52.231180 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:38:52.234005 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:38:52.240963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:38:52.247569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:38:52.251426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:38:52.258570 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:38:52.262269 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:38:52.269358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:38:52.276035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:38:52.279604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:38:52.286618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:38:52.289761 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:38:52.297056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:38:52.300534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:38:52.304290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:38:52.310876 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:38:52.314227 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:38:52.321925 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:38:52.325589 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:38:52.329592 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:38:52.336329 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:38:52.340236 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:38:52.347004 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:38:52.349974 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:38:52.353627 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:38:52.360018 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:38:52.363204 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:38:52.366773 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:38:52.373114 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:38:52.376424 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:38:52.380096 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:38:52.386591 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:38:52.390135 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:38:52.393203 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:38:52.396553 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:38:52.403315 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:38:52.406858 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:38:52.413310 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 00:38:52.423553 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:38:52.426691 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:38:52.436590 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:38:52.443259 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:38:52.450055 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:38:52.453343 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:38:52.456321 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:38:52.463725 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x7
533 00:38:52.470516 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:38:52.473972 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
535 00:38:52.477407 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:38:52.488914 [RTC]rtc_get_frequency_meter,154: input=15, output=793
537 00:38:52.491902 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
538 00:38:52.498288 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
539 00:38:52.502053 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
540 00:38:52.505257 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
541 00:38:52.508285 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
542 00:38:52.511808 ADC[4]: Raw value=897780 ID=7
543 00:38:52.515174 ADC[3]: Raw value=212700 ID=1
544 00:38:52.518704 RAM Code: 0x71
545 00:38:52.522224 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
546 00:38:52.525236 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
547 00:38:52.535545 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
548 00:38:52.542682 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
549 00:38:52.545887 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
550 00:38:52.549298 in-header: 03 07 00 00 08 00 00 00
551 00:38:52.552521 in-data: aa e4 47 04 13 02 00 00
552 00:38:52.555970 Chrome EC: UHEPI supported
553 00:38:52.562752 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
554 00:38:52.566371 in-header: 03 15 00 00 08 00 00 00
555 00:38:52.566449 in-data: 98 20 20 08 00 00 00 00
556 00:38:52.570318 MRC: failed to locate region type 0.
557 00:38:52.577509 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
558 00:38:52.581134 DRAM-K: Running full calibration
559 00:38:52.587833 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
560 00:38:52.587915 header.status = 0x0
561 00:38:52.591441 header.version = 0x6 (expected: 0x6)
562 00:38:52.594399 header.size = 0xd00 (expected: 0xd00)
563 00:38:52.598514 header.flags = 0x0
564 00:38:52.601978 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
565 00:38:52.620922 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
566 00:38:52.627282 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
567 00:38:52.630532 dram_init: ddr_geometry: 2
568 00:38:52.634117 [EMI] MDL number = 2
569 00:38:52.634243 [EMI] Get MDL freq = 0
570 00:38:52.637998 dram_init: ddr_type: 0
571 00:38:52.638127 is_discrete_lpddr4: 1
572 00:38:52.641565 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
573 00:38:52.641693
574 00:38:52.641809
575 00:38:52.645408 [Bian_co] ETT version 0.0.0.1
576 00:38:52.649220 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
577 00:38:52.649382
578 00:38:52.652748 dramc_set_vcore_voltage set vcore to 650000
579 00:38:52.656957 Read voltage for 800, 4
580 00:38:52.657085 Vio18 = 0
581 00:38:52.657200 Vcore = 650000
582 00:38:52.660418 Vdram = 0
583 00:38:52.660526 Vddq = 0
584 00:38:52.660626 Vmddr = 0
585 00:38:52.663847 dram_init: config_dvfs: 1
586 00:38:52.667837 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
587 00:38:52.674906 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
588 00:38:52.678437 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
589 00:38:52.682350 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
590 00:38:52.686228 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
591 00:38:52.689949 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
592 00:38:52.690080 MEM_TYPE=3, freq_sel=18
593 00:38:52.693520 sv_algorithm_assistance_LP4_1600
594 00:38:52.696975 ============ PULL DRAM RESETB DOWN ============
595 00:38:52.701072 ========== PULL DRAM RESETB DOWN end =========
596 00:38:52.708205 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
597 00:38:52.712180 ===================================
598 00:38:52.712310 LPDDR4 DRAM CONFIGURATION
599 00:38:52.715322 ===================================
600 00:38:52.719243 EX_ROW_EN[0] = 0x0
601 00:38:52.719370 EX_ROW_EN[1] = 0x0
602 00:38:52.722246 LP4Y_EN = 0x0
603 00:38:52.722372 WORK_FSP = 0x0
604 00:38:52.725678 WL = 0x2
605 00:38:52.725804 RL = 0x2
606 00:38:52.729072 BL = 0x2
607 00:38:52.729192 RPST = 0x0
608 00:38:52.732422 RD_PRE = 0x0
609 00:38:52.732549 WR_PRE = 0x1
610 00:38:52.735895 WR_PST = 0x0
611 00:38:52.736031 DBI_WR = 0x0
612 00:38:52.738780 DBI_RD = 0x0
613 00:38:52.738910 OTF = 0x1
614 00:38:52.742280 ===================================
615 00:38:52.745667 ===================================
616 00:38:52.749132 ANA top config
617 00:38:52.752149 ===================================
618 00:38:52.755390 DLL_ASYNC_EN = 0
619 00:38:52.755524 ALL_SLAVE_EN = 1
620 00:38:52.759070 NEW_RANK_MODE = 1
621 00:38:52.762514 DLL_IDLE_MODE = 1
622 00:38:52.765905 LP45_APHY_COMB_EN = 1
623 00:38:52.766032 TX_ODT_DIS = 1
624 00:38:52.769132 NEW_8X_MODE = 1
625 00:38:52.772337 ===================================
626 00:38:52.775938 ===================================
627 00:38:52.778904 data_rate = 1600
628 00:38:52.782420 CKR = 1
629 00:38:52.785681 DQ_P2S_RATIO = 8
630 00:38:52.789343 ===================================
631 00:38:52.792134 CA_P2S_RATIO = 8
632 00:38:52.792262 DQ_CA_OPEN = 0
633 00:38:52.795349 DQ_SEMI_OPEN = 0
634 00:38:52.798701 CA_SEMI_OPEN = 0
635 00:38:52.802125 CA_FULL_RATE = 0
636 00:38:52.805704 DQ_CKDIV4_EN = 1
637 00:38:52.805831 CA_CKDIV4_EN = 1
638 00:38:52.808724 CA_PREDIV_EN = 0
639 00:38:52.812197 PH8_DLY = 0
640 00:38:52.815692 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
641 00:38:52.818616 DQ_AAMCK_DIV = 4
642 00:38:52.822073 CA_AAMCK_DIV = 4
643 00:38:52.822162 CA_ADMCK_DIV = 4
644 00:38:52.825652 DQ_TRACK_CA_EN = 0
645 00:38:52.828714 CA_PICK = 800
646 00:38:52.831999 CA_MCKIO = 800
647 00:38:52.835593 MCKIO_SEMI = 0
648 00:38:52.839061 PLL_FREQ = 3068
649 00:38:52.842521 DQ_UI_PI_RATIO = 32
650 00:38:52.842659 CA_UI_PI_RATIO = 0
651 00:38:52.845618 ===================================
652 00:38:52.849221 ===================================
653 00:38:52.852341 memory_type:LPDDR4
654 00:38:52.855906 GP_NUM : 10
655 00:38:52.856018 SRAM_EN : 1
656 00:38:52.858749 MD32_EN : 0
657 00:38:52.862498 ===================================
658 00:38:52.865487 [ANA_INIT] >>>>>>>>>>>>>>
659 00:38:52.869055 <<<<<< [CONFIGURE PHASE]: ANA_TX
660 00:38:52.872208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
661 00:38:52.875553 ===================================
662 00:38:52.875652 data_rate = 1600,PCW = 0X7600
663 00:38:52.878635 ===================================
664 00:38:52.882218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
665 00:38:52.888995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
666 00:38:52.895280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 00:38:52.898804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
668 00:38:52.902093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
669 00:38:52.905821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
670 00:38:52.909594 [ANA_INIT] flow start
671 00:38:52.909680 [ANA_INIT] PLL >>>>>>>>
672 00:38:52.913170 [ANA_INIT] PLL <<<<<<<<
673 00:38:52.916552 [ANA_INIT] MIDPI >>>>>>>>
674 00:38:52.916641 [ANA_INIT] MIDPI <<<<<<<<
675 00:38:52.920274 [ANA_INIT] DLL >>>>>>>>
676 00:38:52.920351 [ANA_INIT] flow end
677 00:38:52.924255 ============ LP4 DIFF to SE enter ============
678 00:38:52.931469 ============ LP4 DIFF to SE exit ============
679 00:38:52.931551 [ANA_INIT] <<<<<<<<<<<<<
680 00:38:52.935171 [Flow] Enable top DCM control >>>>>
681 00:38:52.938831 [Flow] Enable top DCM control <<<<<
682 00:38:52.942862 Enable DLL master slave shuffle
683 00:38:52.946361 ==============================================================
684 00:38:52.950339 Gating Mode config
685 00:38:52.953259 ==============================================================
686 00:38:52.956971 Config description:
687 00:38:52.966630 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
688 00:38:52.973464 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
689 00:38:52.976733 SELPH_MODE 0: By rank 1: By Phase
690 00:38:52.983603 ==============================================================
691 00:38:52.986457 GAT_TRACK_EN = 1
692 00:38:52.989993 RX_GATING_MODE = 2
693 00:38:52.993264 RX_GATING_TRACK_MODE = 2
694 00:38:52.993351 SELPH_MODE = 1
695 00:38:52.996713 PICG_EARLY_EN = 1
696 00:38:53.000122 VALID_LAT_VALUE = 1
697 00:38:53.006537 ==============================================================
698 00:38:53.010064 Enter into Gating configuration >>>>
699 00:38:53.013190 Exit from Gating configuration <<<<
700 00:38:53.016928 Enter into DVFS_PRE_config >>>>>
701 00:38:53.026514 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
702 00:38:53.029954 Exit from DVFS_PRE_config <<<<<
703 00:38:53.033514 Enter into PICG configuration >>>>
704 00:38:53.037121 Exit from PICG configuration <<<<
705 00:38:53.039938 [RX_INPUT] configuration >>>>>
706 00:38:53.043318 [RX_INPUT] configuration <<<<<
707 00:38:53.046726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
708 00:38:53.053403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
709 00:38:53.060194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
710 00:38:53.067251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
711 00:38:53.070232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
712 00:38:53.077061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
713 00:38:53.080100 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
714 00:38:53.087134 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
715 00:38:53.090043 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
716 00:38:53.093717 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
717 00:38:53.097021 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
718 00:38:53.103696 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
719 00:38:53.107236 ===================================
720 00:38:53.107345 LPDDR4 DRAM CONFIGURATION
721 00:38:53.110320 ===================================
722 00:38:53.113795 EX_ROW_EN[0] = 0x0
723 00:38:53.116996 EX_ROW_EN[1] = 0x0
724 00:38:53.117109 LP4Y_EN = 0x0
725 00:38:53.120438 WORK_FSP = 0x0
726 00:38:53.120526 WL = 0x2
727 00:38:53.123930 RL = 0x2
728 00:38:53.124030 BL = 0x2
729 00:38:53.126719 RPST = 0x0
730 00:38:53.126804 RD_PRE = 0x0
731 00:38:53.130267 WR_PRE = 0x1
732 00:38:53.130377 WR_PST = 0x0
733 00:38:53.133811 DBI_WR = 0x0
734 00:38:53.133923 DBI_RD = 0x0
735 00:38:53.136745 OTF = 0x1
736 00:38:53.140261 ===================================
737 00:38:53.143965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
738 00:38:53.147552 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
739 00:38:53.153859 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
740 00:38:53.156909 ===================================
741 00:38:53.156996 LPDDR4 DRAM CONFIGURATION
742 00:38:53.160098 ===================================
743 00:38:53.163868 EX_ROW_EN[0] = 0x10
744 00:38:53.163981 EX_ROW_EN[1] = 0x0
745 00:38:53.167131 LP4Y_EN = 0x0
746 00:38:53.167243 WORK_FSP = 0x0
747 00:38:53.170633 WL = 0x2
748 00:38:53.170719 RL = 0x2
749 00:38:53.173928 BL = 0x2
750 00:38:53.176899 RPST = 0x0
751 00:38:53.177011 RD_PRE = 0x0
752 00:38:53.177107 WR_PRE = 0x1
753 00:38:53.180254 WR_PST = 0x0
754 00:38:53.183733 DBI_WR = 0x0
755 00:38:53.183853 DBI_RD = 0x0
756 00:38:53.187227 OTF = 0x1
757 00:38:53.190800 ===================================
758 00:38:53.193616 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
759 00:38:53.198918 nWR fixed to 40
760 00:38:53.202364 [ModeRegInit_LP4] CH0 RK0
761 00:38:53.202492 [ModeRegInit_LP4] CH0 RK1
762 00:38:53.205936 [ModeRegInit_LP4] CH1 RK0
763 00:38:53.208960 [ModeRegInit_LP4] CH1 RK1
764 00:38:53.209072 match AC timing 13
765 00:38:53.215936 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
766 00:38:53.219405 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
767 00:38:53.223054 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
768 00:38:53.226974 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
769 00:38:53.230560 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
770 00:38:53.233946 [EMI DOE] emi_dcm 0
771 00:38:53.237719 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
772 00:38:53.237856 ==
773 00:38:53.241020 Dram Type= 6, Freq= 0, CH_0, rank 0
774 00:38:53.244481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 00:38:53.244616 ==
776 00:38:53.252400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
777 00:38:53.255814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
778 00:38:53.266747 [CA 0] Center 38 (7~69) winsize 63
779 00:38:53.270224 [CA 1] Center 37 (7~68) winsize 62
780 00:38:53.274128 [CA 2] Center 35 (5~66) winsize 62
781 00:38:53.277494 [CA 3] Center 35 (5~66) winsize 62
782 00:38:53.281419 [CA 4] Center 34 (4~65) winsize 62
783 00:38:53.284741 [CA 5] Center 34 (3~65) winsize 63
784 00:38:53.284832
785 00:38:53.288880 [CmdBusTrainingLP45] Vref(ca) range 1: 34
786 00:38:53.288962
787 00:38:53.292253 [CATrainingPosCal] consider 1 rank data
788 00:38:53.295853 u2DelayCellTimex100 = 270/100 ps
789 00:38:53.299332 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
790 00:38:53.303430 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
791 00:38:53.306988 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
792 00:38:53.310369 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
793 00:38:53.314005 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
794 00:38:53.317474 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
795 00:38:53.317583
796 00:38:53.321478 CA PerBit enable=1, Macro0, CA PI delay=34
797 00:38:53.321586
798 00:38:53.321680 [CBTSetCACLKResult] CA Dly = 34
799 00:38:53.325037 CS Dly: 6 (0~37)
800 00:38:53.325136 ==
801 00:38:53.328682 Dram Type= 6, Freq= 0, CH_0, rank 1
802 00:38:53.332490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 00:38:53.332606 ==
804 00:38:53.335909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
805 00:38:53.343271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
806 00:38:53.352989 [CA 0] Center 38 (7~69) winsize 63
807 00:38:53.357153 [CA 1] Center 37 (7~68) winsize 62
808 00:38:53.360602 [CA 2] Center 35 (5~66) winsize 62
809 00:38:53.364150 [CA 3] Center 35 (5~66) winsize 62
810 00:38:53.368145 [CA 4] Center 34 (4~65) winsize 62
811 00:38:53.371632 [CA 5] Center 34 (4~65) winsize 62
812 00:38:53.371713
813 00:38:53.375296 [CmdBusTrainingLP45] Vref(ca) range 1: 30
814 00:38:53.375409
815 00:38:53.378790 [CATrainingPosCal] consider 2 rank data
816 00:38:53.378874 u2DelayCellTimex100 = 270/100 ps
817 00:38:53.382629 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
818 00:38:53.386226 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
819 00:38:53.390183 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
820 00:38:53.394465 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
821 00:38:53.397988 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
822 00:38:53.401460 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
823 00:38:53.401572
824 00:38:53.405535 CA PerBit enable=1, Macro0, CA PI delay=34
825 00:38:53.405644
826 00:38:53.409823 [CBTSetCACLKResult] CA Dly = 34
827 00:38:53.409906 CS Dly: 6 (0~37)
828 00:38:53.409973
829 00:38:53.413285 ----->DramcWriteLeveling(PI) begin...
830 00:38:53.413375 ==
831 00:38:53.416934 Dram Type= 6, Freq= 0, CH_0, rank 0
832 00:38:53.420361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
833 00:38:53.423861 ==
834 00:38:53.423972 Write leveling (Byte 0): 32 => 32
835 00:38:53.427942 Write leveling (Byte 1): 30 => 30
836 00:38:53.431465 DramcWriteLeveling(PI) end<-----
837 00:38:53.431573
838 00:38:53.431668 ==
839 00:38:53.434845 Dram Type= 6, Freq= 0, CH_0, rank 0
840 00:38:53.438927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 00:38:53.439051 ==
842 00:38:53.442606 [Gating] SW mode calibration
843 00:38:53.450411 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
844 00:38:53.454093 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
845 00:38:53.458021 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
846 00:38:53.461540 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
847 00:38:53.468915 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
848 00:38:53.472851 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
849 00:38:53.476679 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 00:38:53.480545 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 00:38:53.484258 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 00:38:53.491112 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:38:53.495014 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:38:53.498771 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:38:53.502522 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:38:53.505706 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:38:53.509809 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:38:53.517409 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:38:53.521061 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:38:53.524408 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:38:53.528403 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:38:53.532273 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
863 00:38:53.539771 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 00:38:53.543076 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
865 00:38:53.546356 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:38:53.549429 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:38:53.556430 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:38:53.559590 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:38:53.563212 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:38:53.569353 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:38:53.572899 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
872 00:38:53.576312 0 9 12 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
873 00:38:53.582807 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
874 00:38:53.586312 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 00:38:53.589447 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 00:38:53.596265 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 00:38:53.599381 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 00:38:53.602858 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 00:38:53.609544 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
880 00:38:53.613160 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
881 00:38:53.616431 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
882 00:38:53.619481 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 00:38:53.626414 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 00:38:53.629841 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 00:38:53.633252 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 00:38:53.639654 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:38:53.643146 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
888 00:38:53.646302 0 11 12 | B1->B0 | 3535 4141 | 0 0 | (0 0) (0 0)
889 00:38:53.652953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 00:38:53.656137 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 00:38:53.659363 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 00:38:53.666277 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 00:38:53.669822 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 00:38:53.673164 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:38:53.680010 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
896 00:38:53.683005 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
897 00:38:53.686507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 00:38:53.692981 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 00:38:53.696220 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 00:38:53.699592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:38:53.702895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:38:53.709788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:38:53.713132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:38:53.716427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:38:53.723332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:38:53.726203 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:38:53.729498 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:38:53.736472 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:38:53.739609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:38:53.743152 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:38:53.749704 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
912 00:38:53.753112 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
913 00:38:53.756563 Total UI for P1: 0, mck2ui 16
914 00:38:53.759473 best dqsien dly found for B0: ( 0, 14, 8)
915 00:38:53.762725 Total UI for P1: 0, mck2ui 16
916 00:38:53.766428 best dqsien dly found for B1: ( 0, 14, 8)
917 00:38:53.769530 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
918 00:38:53.773049 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
919 00:38:53.773130
920 00:38:53.776361 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
921 00:38:53.779386 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
922 00:38:53.782753 [Gating] SW calibration Done
923 00:38:53.782862 ==
924 00:38:53.786438 Dram Type= 6, Freq= 0, CH_0, rank 0
925 00:38:53.789318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 00:38:53.789396 ==
927 00:38:53.792907 RX Vref Scan: 0
928 00:38:53.792982
929 00:38:53.796244 RX Vref 0 -> 0, step: 1
930 00:38:53.796320
931 00:38:53.796382 RX Delay -130 -> 252, step: 16
932 00:38:53.803004 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
933 00:38:53.806224 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
934 00:38:53.809455 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
935 00:38:53.813210 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
936 00:38:53.816023 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
937 00:38:53.823183 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
938 00:38:53.826109 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
939 00:38:53.829580 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
940 00:38:53.832901 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
941 00:38:53.836436 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
942 00:38:53.842942 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
943 00:38:53.846206 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
944 00:38:53.849877 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
945 00:38:53.852774 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
946 00:38:53.856228 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
947 00:38:53.863057 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
948 00:38:53.863169 ==
949 00:38:53.866086 Dram Type= 6, Freq= 0, CH_0, rank 0
950 00:38:53.869382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 00:38:53.869461 ==
952 00:38:53.869526 DQS Delay:
953 00:38:53.872567 DQS0 = 0, DQS1 = 0
954 00:38:53.872642 DQM Delay:
955 00:38:53.876289 DQM0 = 79, DQM1 = 70
956 00:38:53.876393 DQ Delay:
957 00:38:53.879200 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
958 00:38:53.882743 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
959 00:38:53.886230 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
960 00:38:53.889855 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
961 00:38:53.889939
962 00:38:53.890005
963 00:38:53.890073 ==
964 00:38:53.892610 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:38:53.896067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 00:38:53.899476 ==
967 00:38:53.899555
968 00:38:53.899619
969 00:38:53.899679 TX Vref Scan disable
970 00:38:53.902937 == TX Byte 0 ==
971 00:38:53.906524 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
972 00:38:53.909824 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
973 00:38:53.913094 == TX Byte 1 ==
974 00:38:53.916629 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
975 00:38:53.919947 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
976 00:38:53.920073 ==
977 00:38:53.923136 Dram Type= 6, Freq= 0, CH_0, rank 0
978 00:38:53.930054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
979 00:38:53.930180 ==
980 00:38:53.942049 TX Vref=22, minBit 1, minWin=26, winSum=430
981 00:38:53.945395 TX Vref=24, minBit 11, minWin=26, winSum=438
982 00:38:53.948275 TX Vref=26, minBit 14, minWin=26, winSum=441
983 00:38:53.951718 TX Vref=28, minBit 5, minWin=27, winSum=442
984 00:38:53.954830 TX Vref=30, minBit 5, minWin=27, winSum=442
985 00:38:53.958678 TX Vref=32, minBit 0, minWin=27, winSum=437
986 00:38:53.965229 [TxChooseVref] Worse bit 5, Min win 27, Win sum 442, Final Vref 28
987 00:38:53.965338
988 00:38:53.968254 Final TX Range 1 Vref 28
989 00:38:53.968379
990 00:38:53.968469 ==
991 00:38:53.971766 Dram Type= 6, Freq= 0, CH_0, rank 0
992 00:38:53.975221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
993 00:38:53.975305 ==
994 00:38:53.978159
995 00:38:53.978261
996 00:38:53.978338 TX Vref Scan disable
997 00:38:53.981520 == TX Byte 0 ==
998 00:38:53.984742 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
999 00:38:53.991783 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1000 00:38:53.991914 == TX Byte 1 ==
1001 00:38:53.995099 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1002 00:38:54.001548 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1003 00:38:54.001670
1004 00:38:54.001783 [DATLAT]
1005 00:38:54.001892 Freq=800, CH0 RK0
1006 00:38:54.002004
1007 00:38:54.004983 DATLAT Default: 0xa
1008 00:38:54.005068 0, 0xFFFF, sum = 0
1009 00:38:54.007941 1, 0xFFFF, sum = 0
1010 00:38:54.008026 2, 0xFFFF, sum = 0
1011 00:38:54.011959 3, 0xFFFF, sum = 0
1012 00:38:54.012044 4, 0xFFFF, sum = 0
1013 00:38:54.014767 5, 0xFFFF, sum = 0
1014 00:38:54.018119 6, 0xFFFF, sum = 0
1015 00:38:54.018202 7, 0xFFFF, sum = 0
1016 00:38:54.021499 8, 0xFFFF, sum = 0
1017 00:38:54.021583 9, 0x0, sum = 1
1018 00:38:54.021648 10, 0x0, sum = 2
1019 00:38:54.025271 11, 0x0, sum = 3
1020 00:38:54.025384 12, 0x0, sum = 4
1021 00:38:54.028316 best_step = 10
1022 00:38:54.028424
1023 00:38:54.028516 ==
1024 00:38:54.031612 Dram Type= 6, Freq= 0, CH_0, rank 0
1025 00:38:54.035091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1026 00:38:54.035195 ==
1027 00:38:54.038090 RX Vref Scan: 1
1028 00:38:54.038186
1029 00:38:54.041447 Set Vref Range= 32 -> 127
1030 00:38:54.041547
1031 00:38:54.041638 RX Vref 32 -> 127, step: 1
1032 00:38:54.041724
1033 00:38:54.045017 RX Delay -111 -> 252, step: 8
1034 00:38:54.045098
1035 00:38:54.048319 Set Vref, RX VrefLevel [Byte0]: 32
1036 00:38:54.051313 [Byte1]: 32
1037 00:38:54.051394
1038 00:38:54.054648 Set Vref, RX VrefLevel [Byte0]: 33
1039 00:38:54.058484 [Byte1]: 33
1040 00:38:54.062207
1041 00:38:54.062329 Set Vref, RX VrefLevel [Byte0]: 34
1042 00:38:54.065641 [Byte1]: 34
1043 00:38:54.069876
1044 00:38:54.069977 Set Vref, RX VrefLevel [Byte0]: 35
1045 00:38:54.073430 [Byte1]: 35
1046 00:38:54.077316
1047 00:38:54.077397 Set Vref, RX VrefLevel [Byte0]: 36
1048 00:38:54.080836 [Byte1]: 36
1049 00:38:54.085122
1050 00:38:54.085203 Set Vref, RX VrefLevel [Byte0]: 37
1051 00:38:54.088265 [Byte1]: 37
1052 00:38:54.092647
1053 00:38:54.092774 Set Vref, RX VrefLevel [Byte0]: 38
1054 00:38:54.096110 [Byte1]: 38
1055 00:38:54.100368
1056 00:38:54.100488 Set Vref, RX VrefLevel [Byte0]: 39
1057 00:38:54.106758 [Byte1]: 39
1058 00:38:54.106881
1059 00:38:54.109915 Set Vref, RX VrefLevel [Byte0]: 40
1060 00:38:54.113394 [Byte1]: 40
1061 00:38:54.113515
1062 00:38:54.116490 Set Vref, RX VrefLevel [Byte0]: 41
1063 00:38:54.119976 [Byte1]: 41
1064 00:38:54.123292
1065 00:38:54.123412 Set Vref, RX VrefLevel [Byte0]: 42
1066 00:38:54.126707 [Byte1]: 42
1067 00:38:54.131253
1068 00:38:54.131374 Set Vref, RX VrefLevel [Byte0]: 43
1069 00:38:54.134396 [Byte1]: 43
1070 00:38:54.138517
1071 00:38:54.138643 Set Vref, RX VrefLevel [Byte0]: 44
1072 00:38:54.142193 [Byte1]: 44
1073 00:38:54.146339
1074 00:38:54.146435 Set Vref, RX VrefLevel [Byte0]: 45
1075 00:38:54.149292 [Byte1]: 45
1076 00:38:54.154069
1077 00:38:54.154194 Set Vref, RX VrefLevel [Byte0]: 46
1078 00:38:54.157458 [Byte1]: 46
1079 00:38:54.161913
1080 00:38:54.162011 Set Vref, RX VrefLevel [Byte0]: 47
1081 00:38:54.165398 [Byte1]: 47
1082 00:38:54.169585
1083 00:38:54.169669 Set Vref, RX VrefLevel [Byte0]: 48
1084 00:38:54.173103 [Byte1]: 48
1085 00:38:54.176341
1086 00:38:54.180288 Set Vref, RX VrefLevel [Byte0]: 49
1087 00:38:54.180374 [Byte1]: 49
1088 00:38:54.185028
1089 00:38:54.185115 Set Vref, RX VrefLevel [Byte0]: 50
1090 00:38:54.188552 [Byte1]: 50
1091 00:38:54.191901
1092 00:38:54.191979 Set Vref, RX VrefLevel [Byte0]: 51
1093 00:38:54.195274 [Byte1]: 51
1094 00:38:54.199835
1095 00:38:54.199919 Set Vref, RX VrefLevel [Byte0]: 52
1096 00:38:54.206056 [Byte1]: 52
1097 00:38:54.206141
1098 00:38:54.209933 Set Vref, RX VrefLevel [Byte0]: 53
1099 00:38:54.213185 [Byte1]: 53
1100 00:38:54.213271
1101 00:38:54.216021 Set Vref, RX VrefLevel [Byte0]: 54
1102 00:38:54.219575 [Byte1]: 54
1103 00:38:54.219660
1104 00:38:54.222635 Set Vref, RX VrefLevel [Byte0]: 55
1105 00:38:54.225979 [Byte1]: 55
1106 00:38:54.230483
1107 00:38:54.230581 Set Vref, RX VrefLevel [Byte0]: 56
1108 00:38:54.233837 [Byte1]: 56
1109 00:38:54.238061
1110 00:38:54.238173 Set Vref, RX VrefLevel [Byte0]: 57
1111 00:38:54.241363 [Byte1]: 57
1112 00:38:54.245639
1113 00:38:54.245723 Set Vref, RX VrefLevel [Byte0]: 58
1114 00:38:54.248950 [Byte1]: 58
1115 00:38:54.253572
1116 00:38:54.253655 Set Vref, RX VrefLevel [Byte0]: 59
1117 00:38:54.256415 [Byte1]: 59
1118 00:38:54.261143
1119 00:38:54.261228 Set Vref, RX VrefLevel [Byte0]: 60
1120 00:38:54.264409 [Byte1]: 60
1121 00:38:54.268486
1122 00:38:54.268579 Set Vref, RX VrefLevel [Byte0]: 61
1123 00:38:54.271938 [Byte1]: 61
1124 00:38:54.276539
1125 00:38:54.276634 Set Vref, RX VrefLevel [Byte0]: 62
1126 00:38:54.279253 [Byte1]: 62
1127 00:38:54.283601
1128 00:38:54.283685 Set Vref, RX VrefLevel [Byte0]: 63
1129 00:38:54.286981 [Byte1]: 63
1130 00:38:54.291421
1131 00:38:54.291505 Set Vref, RX VrefLevel [Byte0]: 64
1132 00:38:54.294989 [Byte1]: 64
1133 00:38:54.298885
1134 00:38:54.298971 Set Vref, RX VrefLevel [Byte0]: 65
1135 00:38:54.302390 [Byte1]: 65
1136 00:38:54.306741
1137 00:38:54.306835 Set Vref, RX VrefLevel [Byte0]: 66
1138 00:38:54.310121 [Byte1]: 66
1139 00:38:54.314248
1140 00:38:54.314323 Set Vref, RX VrefLevel [Byte0]: 67
1141 00:38:54.317603 [Byte1]: 67
1142 00:38:54.322074
1143 00:38:54.322162 Set Vref, RX VrefLevel [Byte0]: 68
1144 00:38:54.325622 [Byte1]: 68
1145 00:38:54.329626
1146 00:38:54.329738 Set Vref, RX VrefLevel [Byte0]: 69
1147 00:38:54.332992 [Byte1]: 69
1148 00:38:54.337294
1149 00:38:54.337377 Set Vref, RX VrefLevel [Byte0]: 70
1150 00:38:54.340527 [Byte1]: 70
1151 00:38:54.345196
1152 00:38:54.345278 Set Vref, RX VrefLevel [Byte0]: 71
1153 00:38:54.348248 [Byte1]: 71
1154 00:38:54.352629
1155 00:38:54.352712 Set Vref, RX VrefLevel [Byte0]: 72
1156 00:38:54.356306 [Byte1]: 72
1157 00:38:54.360505
1158 00:38:54.360639 Set Vref, RX VrefLevel [Byte0]: 73
1159 00:38:54.363263 [Byte1]: 73
1160 00:38:54.367887
1161 00:38:54.367969 Set Vref, RX VrefLevel [Byte0]: 74
1162 00:38:54.371368 [Byte1]: 74
1163 00:38:54.375465
1164 00:38:54.375575 Set Vref, RX VrefLevel [Byte0]: 75
1165 00:38:54.378878 [Byte1]: 75
1166 00:38:54.383314
1167 00:38:54.383425 Set Vref, RX VrefLevel [Byte0]: 76
1168 00:38:54.386807 [Byte1]: 76
1169 00:38:54.391229
1170 00:38:54.391340 Set Vref, RX VrefLevel [Byte0]: 77
1171 00:38:54.394125 [Byte1]: 77
1172 00:38:54.398590
1173 00:38:54.398695 Set Vref, RX VrefLevel [Byte0]: 78
1174 00:38:54.402024 [Byte1]: 78
1175 00:38:54.405938
1176 00:38:54.406012 Set Vref, RX VrefLevel [Byte0]: 79
1177 00:38:54.409630 [Byte1]: 79
1178 00:38:54.413684
1179 00:38:54.413882 Final RX Vref Byte 0 = 58 to rank0
1180 00:38:54.417106 Final RX Vref Byte 1 = 59 to rank0
1181 00:38:54.420253 Final RX Vref Byte 0 = 58 to rank1
1182 00:38:54.424076 Final RX Vref Byte 1 = 59 to rank1==
1183 00:38:54.427510 Dram Type= 6, Freq= 0, CH_0, rank 0
1184 00:38:54.433575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 00:38:54.433660 ==
1186 00:38:54.433726 DQS Delay:
1187 00:38:54.433786 DQS0 = 0, DQS1 = 0
1188 00:38:54.437043 DQM Delay:
1189 00:38:54.437126 DQM0 = 82, DQM1 = 68
1190 00:38:54.440271 DQ Delay:
1191 00:38:54.443900 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1192 00:38:54.447079 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1193 00:38:54.450458 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1194 00:38:54.453672 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1195 00:38:54.453756
1196 00:38:54.453820
1197 00:38:54.460234 [DQSOSCAuto] RK0, (LSB)MR18= 0x2524, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1198 00:38:54.463919 CH0 RK0: MR19=606, MR18=2524
1199 00:38:54.470239 CH0_RK0: MR19=0x606, MR18=0x2524, DQSOSC=400, MR23=63, INC=92, DEC=61
1200 00:38:54.470324
1201 00:38:54.473353 ----->DramcWriteLeveling(PI) begin...
1202 00:38:54.473453 ==
1203 00:38:54.477012 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 00:38:54.480352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 00:38:54.480436 ==
1206 00:38:54.483695 Write leveling (Byte 0): 34 => 34
1207 00:38:54.487170 Write leveling (Byte 1): 29 => 29
1208 00:38:54.490005 DramcWriteLeveling(PI) end<-----
1209 00:38:54.490089
1210 00:38:54.490155 ==
1211 00:38:54.493336 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 00:38:54.497082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 00:38:54.497166 ==
1214 00:38:54.500042 [Gating] SW mode calibration
1215 00:38:54.506861 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1216 00:38:54.513765 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1217 00:38:54.516960 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 00:38:54.520212 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1219 00:38:54.526794 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1220 00:38:54.530069 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:38:54.533506 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:38:54.540158 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:38:54.543444 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:38:54.546920 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:38:54.553343 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:38:54.556521 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:38:54.560035 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:38:54.567198 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:38:54.570153 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:38:54.573523 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:38:54.620800 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:38:54.620890 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:38:54.621353 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:38:54.621610 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1235 00:38:54.621865 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:38:54.621934 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1237 00:38:54.622009 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:38:54.622587 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:38:54.622851 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:38:54.622931 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:38:54.622994 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:38:54.654138 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:38:54.654806 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1244 00:38:54.655094 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1245 00:38:54.655209 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 00:38:54.655304 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 00:38:54.655407 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 00:38:54.655506 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 00:38:54.658703 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 00:38:54.662050 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
1251 00:38:54.665489 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (1 1)
1252 00:38:54.672058 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:38:54.675061 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:38:54.678446 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 00:38:54.685338 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 00:38:54.688700 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 00:38:54.691736 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 00:38:54.698394 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1259 00:38:54.701675 0 11 8 | B1->B0 | 2929 3535 | 1 1 | (0 0) (0 0)
1260 00:38:54.705089 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1261 00:38:54.711732 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 00:38:54.715104 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 00:38:54.718407 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 00:38:54.725216 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 00:38:54.728517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 00:38:54.732192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 00:38:54.735601 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1268 00:38:54.742509 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:38:54.746482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:38:54.749783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:38:54.753494 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:38:54.760254 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:38:54.763549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:38:54.766877 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:38:54.770354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:38:54.776999 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:38:54.780522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:38:54.783948 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 00:38:54.790255 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:38:54.793685 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:38:54.797106 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:38:54.803640 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:38:54.807237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 00:38:54.810409 Total UI for P1: 0, mck2ui 16
1285 00:38:54.814159 best dqsien dly found for B0: ( 0, 14, 6)
1286 00:38:54.817424 Total UI for P1: 0, mck2ui 16
1287 00:38:54.820758 best dqsien dly found for B1: ( 0, 14, 6)
1288 00:38:54.824213 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1289 00:38:54.827063 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1290 00:38:54.827147
1291 00:38:54.830393 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 00:38:54.833778 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1293 00:38:54.837334 [Gating] SW calibration Done
1294 00:38:54.837418 ==
1295 00:38:54.840488 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 00:38:54.843718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 00:38:54.843803 ==
1298 00:38:54.847200 RX Vref Scan: 0
1299 00:38:54.847284
1300 00:38:54.850165 RX Vref 0 -> 0, step: 1
1301 00:38:54.850248
1302 00:38:54.850314 RX Delay -130 -> 252, step: 16
1303 00:38:54.857220 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1304 00:38:54.860525 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1305 00:38:54.863633 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1306 00:38:54.867166 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1307 00:38:54.870520 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1308 00:38:54.877177 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1309 00:38:54.880129 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1310 00:38:54.883544 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1311 00:38:54.887179 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1312 00:38:54.890539 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1313 00:38:54.897358 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1314 00:38:54.900267 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1315 00:38:54.903579 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1316 00:38:54.907091 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1317 00:38:54.913481 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1318 00:38:54.916751 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1319 00:38:54.916834 ==
1320 00:38:54.920081 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 00:38:54.923722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 00:38:54.923805 ==
1323 00:38:54.923869 DQS Delay:
1324 00:38:54.926905 DQS0 = 0, DQS1 = 0
1325 00:38:54.926987 DQM Delay:
1326 00:38:54.930216 DQM0 = 76, DQM1 = 71
1327 00:38:54.930298 DQ Delay:
1328 00:38:54.933653 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1329 00:38:54.936687 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =85
1330 00:38:54.940470 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1331 00:38:54.943559 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1332 00:38:54.943642
1333 00:38:54.943705
1334 00:38:54.943764 ==
1335 00:38:54.946896 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 00:38:54.950260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 00:38:54.950343 ==
1338 00:38:54.953487
1339 00:38:54.953568
1340 00:38:54.953632 TX Vref Scan disable
1341 00:38:54.957072 == TX Byte 0 ==
1342 00:38:54.960593 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1343 00:38:54.963850 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1344 00:38:54.966957 == TX Byte 1 ==
1345 00:38:54.970238 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1346 00:38:54.973657 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1347 00:38:54.973799 ==
1348 00:38:54.977218 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 00:38:54.983688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 00:38:54.983813 ==
1351 00:38:54.996104 TX Vref=22, minBit 2, minWin=26, winSum=433
1352 00:38:54.999317 TX Vref=24, minBit 1, minWin=27, winSum=440
1353 00:38:55.002880 TX Vref=26, minBit 1, minWin=27, winSum=439
1354 00:38:55.006284 TX Vref=28, minBit 2, minWin=27, winSum=444
1355 00:38:55.009164 TX Vref=30, minBit 1, minWin=27, winSum=444
1356 00:38:55.016138 TX Vref=32, minBit 11, minWin=26, winSum=444
1357 00:38:55.019460 [TxChooseVref] Worse bit 2, Min win 27, Win sum 444, Final Vref 28
1358 00:38:55.019584
1359 00:38:55.022748 Final TX Range 1 Vref 28
1360 00:38:55.022869
1361 00:38:55.023007 ==
1362 00:38:55.025805 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 00:38:55.029091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 00:38:55.029212 ==
1365 00:38:55.032346
1366 00:38:55.032463
1367 00:38:55.032596 TX Vref Scan disable
1368 00:38:55.036135 == TX Byte 0 ==
1369 00:38:55.039440 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1370 00:38:55.042959 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1371 00:38:55.046431 == TX Byte 1 ==
1372 00:38:55.049671 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1373 00:38:55.053133 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1374 00:38:55.056047
1375 00:38:55.056167 [DATLAT]
1376 00:38:55.056278 Freq=800, CH0 RK1
1377 00:38:55.056389
1378 00:38:55.059479 DATLAT Default: 0xa
1379 00:38:55.059603 0, 0xFFFF, sum = 0
1380 00:38:55.062786 1, 0xFFFF, sum = 0
1381 00:38:55.062912 2, 0xFFFF, sum = 0
1382 00:38:55.066180 3, 0xFFFF, sum = 0
1383 00:38:55.066305 4, 0xFFFF, sum = 0
1384 00:38:55.069547 5, 0xFFFF, sum = 0
1385 00:38:55.073046 6, 0xFFFF, sum = 0
1386 00:38:55.073172 7, 0xFFFF, sum = 0
1387 00:38:55.076185 8, 0xFFFF, sum = 0
1388 00:38:55.076293 9, 0x0, sum = 1
1389 00:38:55.076389 10, 0x0, sum = 2
1390 00:38:55.079516 11, 0x0, sum = 3
1391 00:38:55.079618 12, 0x0, sum = 4
1392 00:38:55.082873 best_step = 10
1393 00:38:55.082974
1394 00:38:55.083071 ==
1395 00:38:55.086174 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 00:38:55.089284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 00:38:55.089412 ==
1398 00:38:55.093109 RX Vref Scan: 0
1399 00:38:55.093236
1400 00:38:55.093351 RX Vref 0 -> 0, step: 1
1401 00:38:55.093461
1402 00:38:55.096023 RX Delay -111 -> 252, step: 8
1403 00:38:55.102988 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1404 00:38:55.106376 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1405 00:38:55.109733 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1406 00:38:55.113225 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1407 00:38:55.116148 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1408 00:38:55.123104 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1409 00:38:55.126558 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1410 00:38:55.129664 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1411 00:38:55.132781 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1412 00:38:55.136257 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1413 00:38:55.143019 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1414 00:38:55.146606 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1415 00:38:55.149483 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1416 00:38:55.152839 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1417 00:38:55.156426 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1418 00:38:55.162677 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1419 00:38:55.162784 ==
1420 00:38:55.166063 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 00:38:55.169897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 00:38:55.170027 ==
1423 00:38:55.170142 DQS Delay:
1424 00:38:55.172880 DQS0 = 0, DQS1 = 0
1425 00:38:55.173003 DQM Delay:
1426 00:38:55.176348 DQM0 = 79, DQM1 = 70
1427 00:38:55.176471 DQ Delay:
1428 00:38:55.179460 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1429 00:38:55.183011 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1430 00:38:55.186220 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1431 00:38:55.189736 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1432 00:38:55.189850
1433 00:38:55.189951
1434 00:38:55.196388 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1435 00:38:55.199321 CH0 RK1: MR19=606, MR18=4A26
1436 00:38:55.206231 CH0_RK1: MR19=0x606, MR18=0x4A26, DQSOSC=391, MR23=63, INC=96, DEC=64
1437 00:38:55.209337 [RxdqsGatingPostProcess] freq 800
1438 00:38:55.215998 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 00:38:55.219467 Pre-setting of DQS Precalculation
1440 00:38:55.222937 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 00:38:55.223048 ==
1442 00:38:55.226283 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 00:38:55.229695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 00:38:55.229778 ==
1445 00:38:55.236410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 00:38:55.242819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 00:38:55.251315 [CA 0] Center 36 (6~66) winsize 61
1448 00:38:55.254515 [CA 1] Center 36 (6~67) winsize 62
1449 00:38:55.258089 [CA 2] Center 35 (5~65) winsize 61
1450 00:38:55.261086 [CA 3] Center 34 (4~65) winsize 62
1451 00:38:55.264595 [CA 4] Center 35 (5~65) winsize 61
1452 00:38:55.267978 [CA 5] Center 33 (3~64) winsize 62
1453 00:38:55.268097
1454 00:38:55.271149 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 00:38:55.271273
1456 00:38:55.274294 [CATrainingPosCal] consider 1 rank data
1457 00:38:55.277773 u2DelayCellTimex100 = 270/100 ps
1458 00:38:55.281159 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1459 00:38:55.284486 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1460 00:38:55.291222 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1461 00:38:55.294226 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 00:38:55.297970 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1463 00:38:55.301462 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 00:38:55.301584
1465 00:38:55.304364 CA PerBit enable=1, Macro0, CA PI delay=33
1466 00:38:55.304486
1467 00:38:55.307735 [CBTSetCACLKResult] CA Dly = 33
1468 00:38:55.307817 CS Dly: 5 (0~36)
1469 00:38:55.311116 ==
1470 00:38:55.311224 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 00:38:55.318034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 00:38:55.318172 ==
1473 00:38:55.321435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 00:38:55.327931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 00:38:55.337407 [CA 0] Center 36 (6~67) winsize 62
1476 00:38:55.340911 [CA 1] Center 37 (6~68) winsize 63
1477 00:38:55.344374 [CA 2] Center 34 (4~65) winsize 62
1478 00:38:55.347455 [CA 3] Center 34 (4~64) winsize 61
1479 00:38:55.350908 [CA 4] Center 34 (4~65) winsize 62
1480 00:38:55.354206 [CA 5] Center 33 (3~64) winsize 62
1481 00:38:55.354332
1482 00:38:55.357623 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 00:38:55.357743
1484 00:38:55.360555 [CATrainingPosCal] consider 2 rank data
1485 00:38:55.364364 u2DelayCellTimex100 = 270/100 ps
1486 00:38:55.367603 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1487 00:38:55.374135 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1488 00:38:55.377273 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1489 00:38:55.381119 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1490 00:38:55.384059 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1491 00:38:55.387661 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 00:38:55.387742
1493 00:38:55.390472 CA PerBit enable=1, Macro0, CA PI delay=33
1494 00:38:55.390574
1495 00:38:55.394454 [CBTSetCACLKResult] CA Dly = 33
1496 00:38:55.394538 CS Dly: 6 (0~38)
1497 00:38:55.394605
1498 00:38:55.398005 ----->DramcWriteLeveling(PI) begin...
1499 00:38:55.398138 ==
1500 00:38:55.401216 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 00:38:55.408332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 00:38:55.408461 ==
1503 00:38:55.411758 Write leveling (Byte 0): 29 => 29
1504 00:38:55.411843 Write leveling (Byte 1): 30 => 30
1505 00:38:55.415718 DramcWriteLeveling(PI) end<-----
1506 00:38:55.415819
1507 00:38:55.415886 ==
1508 00:38:55.419215 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 00:38:55.423294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 00:38:55.423407 ==
1511 00:38:55.426699 [Gating] SW mode calibration
1512 00:38:55.434017 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 00:38:55.440535 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 00:38:55.444154 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 00:38:55.447106 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1516 00:38:55.453863 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1517 00:38:55.457358 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:38:55.460703 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:38:55.464188 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:38:55.470429 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:38:55.473841 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:38:55.477075 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:38:55.483610 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:38:55.487033 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:38:55.490220 0 7 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1526 00:38:55.496923 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:38:55.500341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:38:55.503831 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:38:55.510300 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:38:55.513469 0 8 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1531 00:38:55.517044 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1532 00:38:55.523872 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1533 00:38:55.526813 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:38:55.530327 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:38:55.536800 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:38:55.540663 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:38:55.544219 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:38:55.550753 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:38:55.553692 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:38:55.557068 0 9 8 | B1->B0 | 2726 2b2b | 1 0 | (1 1) (0 0)
1541 00:38:55.560500 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 00:38:55.566911 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 00:38:55.570670 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 00:38:55.573500 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 00:38:55.580288 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 00:38:55.583705 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 00:38:55.587121 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1548 00:38:55.593539 0 10 8 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
1549 00:38:55.597170 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:38:55.600394 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:38:55.607088 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:38:55.610628 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:38:55.613581 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 00:38:55.620688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 00:38:55.624052 0 11 4 | B1->B0 | 2626 2828 | 0 1 | (0 0) (0 0)
1556 00:38:55.627461 0 11 8 | B1->B0 | 3838 3737 | 1 1 | (0 0) (0 0)
1557 00:38:55.633753 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 00:38:55.637232 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 00:38:55.640468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 00:38:55.646814 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 00:38:55.650184 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 00:38:55.653561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 00:38:55.660352 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 00:38:55.663702 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1565 00:38:55.667152 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:38:55.670514 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:38:55.677115 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:38:55.680183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:38:55.683584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:38:55.690489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:38:55.693544 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:38:55.697014 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:38:55.703920 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:38:55.707248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:38:55.710588 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:38:55.717218 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 00:38:55.720149 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:38:55.723895 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:38:55.729933 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1580 00:38:55.733550 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 00:38:55.736972 Total UI for P1: 0, mck2ui 16
1582 00:38:55.740335 best dqsien dly found for B0: ( 0, 14, 4)
1583 00:38:55.743856 Total UI for P1: 0, mck2ui 16
1584 00:38:55.746994 best dqsien dly found for B1: ( 0, 14, 6)
1585 00:38:55.750406 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1586 00:38:55.753326 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1587 00:38:55.753407
1588 00:38:55.756843 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 00:38:55.760256 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 00:38:55.763826 [Gating] SW calibration Done
1591 00:38:55.763901 ==
1592 00:38:55.766727 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 00:38:55.770091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 00:38:55.770176 ==
1595 00:38:55.773400 RX Vref Scan: 0
1596 00:38:55.773483
1597 00:38:55.777150 RX Vref 0 -> 0, step: 1
1598 00:38:55.777233
1599 00:38:55.777298 RX Delay -130 -> 252, step: 16
1600 00:38:55.783476 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1601 00:38:55.786864 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1602 00:38:55.789862 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1603 00:38:55.793207 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1604 00:38:55.796990 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1605 00:38:55.803435 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1606 00:38:55.806934 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1607 00:38:55.809796 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1608 00:38:55.813034 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1609 00:38:55.816385 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1610 00:38:55.823277 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1611 00:38:55.826693 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1612 00:38:55.829960 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1613 00:38:55.833438 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1614 00:38:55.839978 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1615 00:38:55.843538 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1616 00:38:55.843614 ==
1617 00:38:55.846939 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 00:38:55.849813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 00:38:55.849893 ==
1620 00:38:55.849956 DQS Delay:
1621 00:38:55.853363 DQS0 = 0, DQS1 = 0
1622 00:38:55.853439 DQM Delay:
1623 00:38:55.856531 DQM0 = 81, DQM1 = 70
1624 00:38:55.856619 DQ Delay:
1625 00:38:55.860075 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1626 00:38:55.863462 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1627 00:38:55.866368 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1628 00:38:55.869924 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1629 00:38:55.870008
1630 00:38:55.870072
1631 00:38:55.870131 ==
1632 00:38:55.873219 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 00:38:55.876727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 00:38:55.879996 ==
1635 00:38:55.880104
1636 00:38:55.880210
1637 00:38:55.880300 TX Vref Scan disable
1638 00:38:55.883522 == TX Byte 0 ==
1639 00:38:55.886823 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1640 00:38:55.890068 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1641 00:38:55.893452 == TX Byte 1 ==
1642 00:38:55.896634 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1643 00:38:55.899816 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1644 00:38:55.899893 ==
1645 00:38:55.903406 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 00:38:55.909787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 00:38:55.909868 ==
1648 00:38:55.921946 TX Vref=22, minBit 1, minWin=26, winSum=438
1649 00:38:55.925363 TX Vref=24, minBit 1, minWin=27, winSum=442
1650 00:38:55.928893 TX Vref=26, minBit 4, minWin=27, winSum=444
1651 00:38:55.931739 TX Vref=28, minBit 5, minWin=27, winSum=447
1652 00:38:55.935414 TX Vref=30, minBit 0, minWin=27, winSum=447
1653 00:38:55.938940 TX Vref=32, minBit 4, minWin=27, winSum=448
1654 00:38:55.945292 [TxChooseVref] Worse bit 4, Min win 27, Win sum 448, Final Vref 32
1655 00:38:55.945376
1656 00:38:55.948510 Final TX Range 1 Vref 32
1657 00:38:55.948612
1658 00:38:55.948676 ==
1659 00:38:55.951970 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 00:38:55.955436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 00:38:55.955519 ==
1662 00:38:55.955583
1663 00:38:55.958878
1664 00:38:55.958984 TX Vref Scan disable
1665 00:38:55.962105 == TX Byte 0 ==
1666 00:38:55.964929 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1667 00:38:55.968296 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1668 00:38:55.972192 == TX Byte 1 ==
1669 00:38:55.975750 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1670 00:38:55.979412 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1671 00:38:55.979492
1672 00:38:55.982729 [DATLAT]
1673 00:38:55.982842 Freq=800, CH1 RK0
1674 00:38:55.982935
1675 00:38:55.986061 DATLAT Default: 0xa
1676 00:38:55.986140 0, 0xFFFF, sum = 0
1677 00:38:55.989439 1, 0xFFFF, sum = 0
1678 00:38:55.989516 2, 0xFFFF, sum = 0
1679 00:38:55.992770 3, 0xFFFF, sum = 0
1680 00:38:55.992884 4, 0xFFFF, sum = 0
1681 00:38:55.996273 5, 0xFFFF, sum = 0
1682 00:38:55.996374 6, 0xFFFF, sum = 0
1683 00:38:55.999300 7, 0xFFFF, sum = 0
1684 00:38:55.999384 8, 0xFFFF, sum = 0
1685 00:38:56.002608 9, 0x0, sum = 1
1686 00:38:56.002692 10, 0x0, sum = 2
1687 00:38:56.006133 11, 0x0, sum = 3
1688 00:38:56.006218 12, 0x0, sum = 4
1689 00:38:56.009380 best_step = 10
1690 00:38:56.009463
1691 00:38:56.009526 ==
1692 00:38:56.012472 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 00:38:56.016026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 00:38:56.016132 ==
1695 00:38:56.016243 RX Vref Scan: 1
1696 00:38:56.016337
1697 00:38:56.019198 Set Vref Range= 32 -> 127
1698 00:38:56.019297
1699 00:38:56.022839 RX Vref 32 -> 127, step: 1
1700 00:38:56.022915
1701 00:38:56.026381 RX Delay -111 -> 252, step: 8
1702 00:38:56.026458
1703 00:38:56.029643 Set Vref, RX VrefLevel [Byte0]: 32
1704 00:38:56.032487 [Byte1]: 32
1705 00:38:56.032567
1706 00:38:56.036025 Set Vref, RX VrefLevel [Byte0]: 33
1707 00:38:56.039393 [Byte1]: 33
1708 00:38:56.039470
1709 00:38:56.042700 Set Vref, RX VrefLevel [Byte0]: 34
1710 00:38:56.046140 [Byte1]: 34
1711 00:38:56.050245
1712 00:38:56.050346 Set Vref, RX VrefLevel [Byte0]: 35
1713 00:38:56.053069 [Byte1]: 35
1714 00:38:56.057778
1715 00:38:56.057855 Set Vref, RX VrefLevel [Byte0]: 36
1716 00:38:56.061218 [Byte1]: 36
1717 00:38:56.065186
1718 00:38:56.065262 Set Vref, RX VrefLevel [Byte0]: 37
1719 00:38:56.068496 [Byte1]: 37
1720 00:38:56.073043
1721 00:38:56.073117 Set Vref, RX VrefLevel [Byte0]: 38
1722 00:38:56.076195 [Byte1]: 38
1723 00:38:56.080824
1724 00:38:56.080906 Set Vref, RX VrefLevel [Byte0]: 39
1725 00:38:56.083819 [Byte1]: 39
1726 00:38:56.088414
1727 00:38:56.088487 Set Vref, RX VrefLevel [Byte0]: 40
1728 00:38:56.091657 [Byte1]: 40
1729 00:38:56.095576
1730 00:38:56.095660 Set Vref, RX VrefLevel [Byte0]: 41
1731 00:38:56.099064 [Byte1]: 41
1732 00:38:56.103650
1733 00:38:56.103732 Set Vref, RX VrefLevel [Byte0]: 42
1734 00:38:56.106966 [Byte1]: 42
1735 00:38:56.111014
1736 00:38:56.111097 Set Vref, RX VrefLevel [Byte0]: 43
1737 00:38:56.114728 [Byte1]: 43
1738 00:38:56.118550
1739 00:38:56.118628 Set Vref, RX VrefLevel [Byte0]: 44
1740 00:38:56.121960 [Byte1]: 44
1741 00:38:56.126135
1742 00:38:56.126215 Set Vref, RX VrefLevel [Byte0]: 45
1743 00:38:56.129693 [Byte1]: 45
1744 00:38:56.133945
1745 00:38:56.134055 Set Vref, RX VrefLevel [Byte0]: 46
1746 00:38:56.137213 [Byte1]: 46
1747 00:38:56.141468
1748 00:38:56.141551 Set Vref, RX VrefLevel [Byte0]: 47
1749 00:38:56.144952 [Byte1]: 47
1750 00:38:56.149485
1751 00:38:56.149579 Set Vref, RX VrefLevel [Byte0]: 48
1752 00:38:56.152419 [Byte1]: 48
1753 00:38:56.157021
1754 00:38:56.157101 Set Vref, RX VrefLevel [Byte0]: 49
1755 00:38:56.160300 [Byte1]: 49
1756 00:38:56.164478
1757 00:38:56.164563 Set Vref, RX VrefLevel [Byte0]: 50
1758 00:38:56.167914 [Byte1]: 50
1759 00:38:56.172416
1760 00:38:56.172493 Set Vref, RX VrefLevel [Byte0]: 51
1761 00:38:56.175440 [Byte1]: 51
1762 00:38:56.180049
1763 00:38:56.180128 Set Vref, RX VrefLevel [Byte0]: 52
1764 00:38:56.183298 [Byte1]: 52
1765 00:38:56.187746
1766 00:38:56.187833 Set Vref, RX VrefLevel [Byte0]: 53
1767 00:38:56.191074 [Byte1]: 53
1768 00:38:56.195171
1769 00:38:56.195252 Set Vref, RX VrefLevel [Byte0]: 54
1770 00:38:56.198493 [Byte1]: 54
1771 00:38:56.202979
1772 00:38:56.203098 Set Vref, RX VrefLevel [Byte0]: 55
1773 00:38:56.206057 [Byte1]: 55
1774 00:38:56.210684
1775 00:38:56.210759 Set Vref, RX VrefLevel [Byte0]: 56
1776 00:38:56.213568 [Byte1]: 56
1777 00:38:56.218098
1778 00:38:56.218173 Set Vref, RX VrefLevel [Byte0]: 57
1779 00:38:56.221663 [Byte1]: 57
1780 00:38:56.225509
1781 00:38:56.225610 Set Vref, RX VrefLevel [Byte0]: 58
1782 00:38:56.228998 [Byte1]: 58
1783 00:38:56.233354
1784 00:38:56.233455 Set Vref, RX VrefLevel [Byte0]: 59
1785 00:38:56.236539 [Byte1]: 59
1786 00:38:56.241083
1787 00:38:56.241159 Set Vref, RX VrefLevel [Byte0]: 60
1788 00:38:56.244355 [Byte1]: 60
1789 00:38:56.248485
1790 00:38:56.248624 Set Vref, RX VrefLevel [Byte0]: 61
1791 00:38:56.252407 [Byte1]: 61
1792 00:38:56.256233
1793 00:38:56.256362 Set Vref, RX VrefLevel [Byte0]: 62
1794 00:38:56.259708 [Byte1]: 62
1795 00:38:56.264291
1796 00:38:56.264411 Set Vref, RX VrefLevel [Byte0]: 63
1797 00:38:56.267430 [Byte1]: 63
1798 00:38:56.271422
1799 00:38:56.271551 Set Vref, RX VrefLevel [Byte0]: 64
1800 00:38:56.274935 [Byte1]: 64
1801 00:38:56.279063
1802 00:38:56.279181 Set Vref, RX VrefLevel [Byte0]: 65
1803 00:38:56.282429 [Byte1]: 65
1804 00:38:56.287045
1805 00:38:56.287168 Set Vref, RX VrefLevel [Byte0]: 66
1806 00:38:56.290325 [Byte1]: 66
1807 00:38:56.294368
1808 00:38:56.294493 Set Vref, RX VrefLevel [Byte0]: 67
1809 00:38:56.297756 [Byte1]: 67
1810 00:38:56.302532
1811 00:38:56.302655 Set Vref, RX VrefLevel [Byte0]: 68
1812 00:38:56.305378 [Byte1]: 68
1813 00:38:56.310083
1814 00:38:56.310207 Set Vref, RX VrefLevel [Byte0]: 69
1815 00:38:56.313230 [Byte1]: 69
1816 00:38:56.317256
1817 00:38:56.317381 Set Vref, RX VrefLevel [Byte0]: 70
1818 00:38:56.320702 [Byte1]: 70
1819 00:38:56.325217
1820 00:38:56.325357 Set Vref, RX VrefLevel [Byte0]: 71
1821 00:38:56.328763 [Byte1]: 71
1822 00:38:56.332595
1823 00:38:56.332680 Set Vref, RX VrefLevel [Byte0]: 72
1824 00:38:56.336060 [Byte1]: 72
1825 00:38:56.340394
1826 00:38:56.340522 Set Vref, RX VrefLevel [Byte0]: 73
1827 00:38:56.343839 [Byte1]: 73
1828 00:38:56.348254
1829 00:38:56.348342 Set Vref, RX VrefLevel [Byte0]: 74
1830 00:38:56.351526 [Byte1]: 74
1831 00:38:56.355697
1832 00:38:56.355805 Set Vref, RX VrefLevel [Byte0]: 75
1833 00:38:56.358961 [Byte1]: 75
1834 00:38:56.363364
1835 00:38:56.363478 Final RX Vref Byte 0 = 59 to rank0
1836 00:38:56.366923 Final RX Vref Byte 1 = 57 to rank0
1837 00:38:56.370225 Final RX Vref Byte 0 = 59 to rank1
1838 00:38:56.373683 Final RX Vref Byte 1 = 57 to rank1==
1839 00:38:56.376582 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 00:38:56.379986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 00:38:56.383471 ==
1842 00:38:56.383610 DQS Delay:
1843 00:38:56.383717 DQS0 = 0, DQS1 = 0
1844 00:38:56.386714 DQM Delay:
1845 00:38:56.386828 DQM0 = 81, DQM1 = 71
1846 00:38:56.390160 DQ Delay:
1847 00:38:56.393496 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1848 00:38:56.393602 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1849 00:38:56.396880 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1850 00:38:56.400323 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1851 00:38:56.403278
1852 00:38:56.403378
1853 00:38:56.410052 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1854 00:38:56.413450 CH1 RK0: MR19=606, MR18=F19
1855 00:38:56.419851 CH1_RK0: MR19=0x606, MR18=0xF19, DQSOSC=403, MR23=63, INC=90, DEC=60
1856 00:38:56.419958
1857 00:38:56.423583 ----->DramcWriteLeveling(PI) begin...
1858 00:38:56.423687 ==
1859 00:38:56.426732 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 00:38:56.430010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 00:38:56.430094 ==
1862 00:38:56.433340 Write leveling (Byte 0): 28 => 28
1863 00:38:56.437072 Write leveling (Byte 1): 29 => 29
1864 00:38:56.440185 DramcWriteLeveling(PI) end<-----
1865 00:38:56.440290
1866 00:38:56.440382 ==
1867 00:38:56.443278 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 00:38:56.446561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 00:38:56.446665 ==
1870 00:38:56.450070 [Gating] SW mode calibration
1871 00:38:56.456940 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 00:38:56.463463 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 00:38:56.466933 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 00:38:56.470068 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1875 00:38:56.476483 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:38:56.480065 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:38:56.483487 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:38:56.490001 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 00:38:56.493477 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 00:38:56.496499 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:38:56.499927 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:38:56.506719 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:38:56.510223 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:38:56.513255 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:38:56.520157 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:38:56.523562 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:38:56.526579 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:38:56.533264 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:38:56.536595 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1890 00:38:56.540064 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1891 00:38:56.546415 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1892 00:38:56.549816 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:38:56.553203 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:38:56.559880 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:38:56.563524 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:38:56.566825 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:38:56.573514 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:38:56.576398 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1899 00:38:56.580099 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1900 00:38:56.586672 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 00:38:56.589929 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 00:38:56.593339 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 00:38:56.596935 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 00:38:56.603169 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 00:38:56.606750 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 00:38:56.610247 0 10 4 | B1->B0 | 3232 2d2d | 1 1 | (0 0) (1 0)
1907 00:38:56.616488 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1908 00:38:56.620083 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:38:56.623540 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 00:38:56.629990 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 00:38:56.633715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 00:38:56.637107 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 00:38:56.643221 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1914 00:38:56.646597 0 11 4 | B1->B0 | 2727 3636 | 0 1 | (0 0) (0 0)
1915 00:38:56.649993 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1916 00:38:56.657068 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 00:38:56.659841 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 00:38:56.663339 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 00:38:56.670224 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 00:38:56.673524 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 00:38:56.676902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 00:38:56.683468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1923 00:38:56.686725 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 00:38:56.689724 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 00:38:56.696410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 00:38:56.699854 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 00:38:56.703216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 00:38:56.709636 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 00:38:56.712862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 00:38:56.716550 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:38:56.719568 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:38:56.726373 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:38:56.729825 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:38:56.736210 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:38:56.739668 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:38:56.742937 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:38:56.746147 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:38:56.753254 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:38:56.756068 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1940 00:38:56.759567 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 00:38:56.763023 Total UI for P1: 0, mck2ui 16
1942 00:38:56.766328 best dqsien dly found for B0: ( 0, 14, 8)
1943 00:38:56.769731 Total UI for P1: 0, mck2ui 16
1944 00:38:56.773020 best dqsien dly found for B1: ( 0, 14, 8)
1945 00:38:56.776016 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1946 00:38:56.779335 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1947 00:38:56.779442
1948 00:38:56.786074 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1949 00:38:56.789557 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1950 00:38:56.789644 [Gating] SW calibration Done
1951 00:38:56.793096 ==
1952 00:38:56.793180 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 00:38:56.799309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 00:38:56.799391 ==
1955 00:38:56.799473 RX Vref Scan: 0
1956 00:38:56.799550
1957 00:38:56.803252 RX Vref 0 -> 0, step: 1
1958 00:38:56.803345
1959 00:38:56.806439 RX Delay -130 -> 252, step: 16
1960 00:38:56.809692 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1961 00:38:56.813317 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1962 00:38:56.816505 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1963 00:38:56.822903 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1964 00:38:56.826163 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1965 00:38:56.829734 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1966 00:38:56.832785 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1967 00:38:56.836061 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1968 00:38:56.843311 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1969 00:38:56.846142 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1970 00:38:56.849441 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1971 00:38:56.852953 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1972 00:38:56.856512 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1973 00:38:56.862755 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1974 00:38:56.866174 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1975 00:38:56.869641 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1976 00:38:56.869720 ==
1977 00:38:56.873115 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 00:38:56.876452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 00:38:56.876567 ==
1980 00:38:56.879838 DQS Delay:
1981 00:38:56.879914 DQS0 = 0, DQS1 = 0
1982 00:38:56.882834 DQM Delay:
1983 00:38:56.882921 DQM0 = 78, DQM1 = 74
1984 00:38:56.883067 DQ Delay:
1985 00:38:56.886217 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1986 00:38:56.889470 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1987 00:38:56.892708 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1988 00:38:56.896138 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1989 00:38:56.896243
1990 00:38:56.896327
1991 00:38:56.899785 ==
1992 00:38:56.903062 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 00:38:56.906350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 00:38:56.906429 ==
1995 00:38:56.906492
1996 00:38:56.906552
1997 00:38:56.909342 TX Vref Scan disable
1998 00:38:56.909417 == TX Byte 0 ==
1999 00:38:56.912750 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 00:38:56.919694 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 00:38:56.919799 == TX Byte 1 ==
2002 00:38:56.922936 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2003 00:38:56.929935 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2004 00:38:56.930019 ==
2005 00:38:56.932803 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 00:38:56.936149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 00:38:56.936228 ==
2008 00:38:56.949548 TX Vref=22, minBit 9, minWin=27, winSum=449
2009 00:38:56.952481 TX Vref=24, minBit 5, minWin=27, winSum=451
2010 00:38:56.956004 TX Vref=26, minBit 0, minWin=28, winSum=455
2011 00:38:56.959234 TX Vref=28, minBit 0, minWin=28, winSum=456
2012 00:38:56.962756 TX Vref=30, minBit 5, minWin=27, winSum=460
2013 00:38:56.965623 TX Vref=32, minBit 1, minWin=27, winSum=456
2014 00:38:56.972458 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
2015 00:38:56.972573
2016 00:38:56.975988 Final TX Range 1 Vref 28
2017 00:38:56.976099
2018 00:38:56.976197 ==
2019 00:38:56.979359 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 00:38:56.982786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 00:38:56.982892 ==
2022 00:38:56.982983
2023 00:38:56.985650
2024 00:38:56.985754 TX Vref Scan disable
2025 00:38:56.989144 == TX Byte 0 ==
2026 00:38:56.992609 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2027 00:38:56.995913 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2028 00:38:56.999308 == TX Byte 1 ==
2029 00:38:57.002784 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2030 00:38:57.006078 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2031 00:38:57.009406
2032 00:38:57.009494 [DATLAT]
2033 00:38:57.009561 Freq=800, CH1 RK1
2034 00:38:57.009621
2035 00:38:57.012504 DATLAT Default: 0xa
2036 00:38:57.012617 0, 0xFFFF, sum = 0
2037 00:38:57.016034 1, 0xFFFF, sum = 0
2038 00:38:57.016138 2, 0xFFFF, sum = 0
2039 00:38:57.019467 3, 0xFFFF, sum = 0
2040 00:38:57.019583 4, 0xFFFF, sum = 0
2041 00:38:57.022836 5, 0xFFFF, sum = 0
2042 00:38:57.022941 6, 0xFFFF, sum = 0
2043 00:38:57.026120 7, 0xFFFF, sum = 0
2044 00:38:57.029344 8, 0xFFFF, sum = 0
2045 00:38:57.029425 9, 0x0, sum = 1
2046 00:38:57.029492 10, 0x0, sum = 2
2047 00:38:57.032810 11, 0x0, sum = 3
2048 00:38:57.032917 12, 0x0, sum = 4
2049 00:38:57.035728 best_step = 10
2050 00:38:57.035812
2051 00:38:57.035877 ==
2052 00:38:57.039063 Dram Type= 6, Freq= 0, CH_1, rank 1
2053 00:38:57.042330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2054 00:38:57.042415 ==
2055 00:38:57.045990 RX Vref Scan: 0
2056 00:38:57.046073
2057 00:38:57.046139 RX Vref 0 -> 0, step: 1
2058 00:38:57.046200
2059 00:38:57.048928 RX Delay -95 -> 252, step: 8
2060 00:38:57.055699 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2061 00:38:57.059047 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2062 00:38:57.062204 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2063 00:38:57.065648 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2064 00:38:57.068886 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2065 00:38:57.075922 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2066 00:38:57.079174 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2067 00:38:57.082623 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2068 00:38:57.086139 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2069 00:38:57.089415 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2070 00:38:57.095640 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2071 00:38:57.099468 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2072 00:38:57.102387 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2073 00:38:57.105832 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2074 00:38:57.109273 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2075 00:38:57.115889 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2076 00:38:57.115969 ==
2077 00:38:57.119425 Dram Type= 6, Freq= 0, CH_1, rank 1
2078 00:38:57.122202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2079 00:38:57.122276 ==
2080 00:38:57.122338 DQS Delay:
2081 00:38:57.125724 DQS0 = 0, DQS1 = 0
2082 00:38:57.125799 DQM Delay:
2083 00:38:57.129132 DQM0 = 77, DQM1 = 73
2084 00:38:57.129214 DQ Delay:
2085 00:38:57.132372 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2086 00:38:57.135749 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2087 00:38:57.139293 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2088 00:38:57.142665 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2089 00:38:57.142756
2090 00:38:57.142821
2091 00:38:57.148963 [DQSOSCAuto] RK1, (LSB)MR18= 0x263d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2092 00:38:57.152214 CH1 RK1: MR19=606, MR18=263D
2093 00:38:57.158924 CH1_RK1: MR19=0x606, MR18=0x263D, DQSOSC=394, MR23=63, INC=95, DEC=63
2094 00:38:57.161953 [RxdqsGatingPostProcess] freq 800
2095 00:38:57.168630 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2096 00:38:57.172726 Pre-setting of DQS Precalculation
2097 00:38:57.175795 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2098 00:38:57.182542 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2099 00:38:57.188677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2100 00:38:57.192248
2101 00:38:57.192358
2102 00:38:57.192454 [Calibration Summary] 1600 Mbps
2103 00:38:57.195335 CH 0, Rank 0
2104 00:38:57.195441 SW Impedance : PASS
2105 00:38:57.198671 DUTY Scan : NO K
2106 00:38:57.201941 ZQ Calibration : PASS
2107 00:38:57.202051 Jitter Meter : NO K
2108 00:38:57.205247 CBT Training : PASS
2109 00:38:57.208686 Write leveling : PASS
2110 00:38:57.208787 RX DQS gating : PASS
2111 00:38:57.212231 RX DQ/DQS(RDDQC) : PASS
2112 00:38:57.215406 TX DQ/DQS : PASS
2113 00:38:57.215509 RX DATLAT : PASS
2114 00:38:57.218745 RX DQ/DQS(Engine): PASS
2115 00:38:57.222293 TX OE : NO K
2116 00:38:57.222401 All Pass.
2117 00:38:57.222496
2118 00:38:57.222584 CH 0, Rank 1
2119 00:38:57.225249 SW Impedance : PASS
2120 00:38:57.228642 DUTY Scan : NO K
2121 00:38:57.228724 ZQ Calibration : PASS
2122 00:38:57.232094 Jitter Meter : NO K
2123 00:38:57.232202 CBT Training : PASS
2124 00:38:57.235452 Write leveling : PASS
2125 00:38:57.238670 RX DQS gating : PASS
2126 00:38:57.238772 RX DQ/DQS(RDDQC) : PASS
2127 00:38:57.242032 TX DQ/DQS : PASS
2128 00:38:57.245611 RX DATLAT : PASS
2129 00:38:57.245715 RX DQ/DQS(Engine): PASS
2130 00:38:57.248536 TX OE : NO K
2131 00:38:57.248619 All Pass.
2132 00:38:57.248681
2133 00:38:57.252064 CH 1, Rank 0
2134 00:38:57.252166 SW Impedance : PASS
2135 00:38:57.255516 DUTY Scan : NO K
2136 00:38:57.258861 ZQ Calibration : PASS
2137 00:38:57.258966 Jitter Meter : NO K
2138 00:38:57.261747 CBT Training : PASS
2139 00:38:57.265038 Write leveling : PASS
2140 00:38:57.265140 RX DQS gating : PASS
2141 00:38:57.268743 RX DQ/DQS(RDDQC) : PASS
2142 00:38:57.271868 TX DQ/DQS : PASS
2143 00:38:57.271977 RX DATLAT : PASS
2144 00:38:57.275040 RX DQ/DQS(Engine): PASS
2145 00:38:57.278318 TX OE : NO K
2146 00:38:57.278422 All Pass.
2147 00:38:57.278515
2148 00:38:57.278606 CH 1, Rank 1
2149 00:38:57.281649 SW Impedance : PASS
2150 00:38:57.284943 DUTY Scan : NO K
2151 00:38:57.285044 ZQ Calibration : PASS
2152 00:38:57.288486 Jitter Meter : NO K
2153 00:38:57.288593 CBT Training : PASS
2154 00:38:57.291787 Write leveling : PASS
2155 00:38:57.295214 RX DQS gating : PASS
2156 00:38:57.295317 RX DQ/DQS(RDDQC) : PASS
2157 00:38:57.298632 TX DQ/DQS : PASS
2158 00:38:57.301903 RX DATLAT : PASS
2159 00:38:57.302007 RX DQ/DQS(Engine): PASS
2160 00:38:57.305041 TX OE : NO K
2161 00:38:57.305144 All Pass.
2162 00:38:57.305237
2163 00:38:57.309025 DramC Write-DBI off
2164 00:38:57.311923 PER_BANK_REFRESH: Hybrid Mode
2165 00:38:57.312026 TX_TRACKING: ON
2166 00:38:57.315113 [GetDramInforAfterCalByMRR] Vendor 6.
2167 00:38:57.318767 [GetDramInforAfterCalByMRR] Revision 606.
2168 00:38:57.321931 [GetDramInforAfterCalByMRR] Revision 2 0.
2169 00:38:57.325363 MR0 0x3b3b
2170 00:38:57.325468 MR8 0x5151
2171 00:38:57.328630 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 00:38:57.328731
2173 00:38:57.328821 MR0 0x3b3b
2174 00:38:57.331984 MR8 0x5151
2175 00:38:57.334932 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 00:38:57.335036
2177 00:38:57.345615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2178 00:38:57.348484 [FAST_K] Save calibration result to emmc
2179 00:38:57.351552 [FAST_K] Save calibration result to emmc
2180 00:38:57.351655 dram_init: config_dvfs: 1
2181 00:38:57.358337 dramc_set_vcore_voltage set vcore to 662500
2182 00:38:57.358441 Read voltage for 1200, 2
2183 00:38:57.361846 Vio18 = 0
2184 00:38:57.361934 Vcore = 662500
2185 00:38:57.362026 Vdram = 0
2186 00:38:57.365394 Vddq = 0
2187 00:38:57.365473 Vmddr = 0
2188 00:38:57.368363 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2189 00:38:57.375275 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2190 00:38:57.378569 MEM_TYPE=3, freq_sel=15
2191 00:38:57.381409 sv_algorithm_assistance_LP4_1600
2192 00:38:57.384983 ============ PULL DRAM RESETB DOWN ============
2193 00:38:57.388239 ========== PULL DRAM RESETB DOWN end =========
2194 00:38:57.391571 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2195 00:38:57.394734 ===================================
2196 00:38:57.398032 LPDDR4 DRAM CONFIGURATION
2197 00:38:57.401287 ===================================
2198 00:38:57.404925 EX_ROW_EN[0] = 0x0
2199 00:38:57.405002 EX_ROW_EN[1] = 0x0
2200 00:38:57.408317 LP4Y_EN = 0x0
2201 00:38:57.408417 WORK_FSP = 0x0
2202 00:38:57.411753 WL = 0x4
2203 00:38:57.411855 RL = 0x4
2204 00:38:57.415116 BL = 0x2
2205 00:38:57.415187 RPST = 0x0
2206 00:38:57.418473 RD_PRE = 0x0
2207 00:38:57.418576 WR_PRE = 0x1
2208 00:38:57.421736 WR_PST = 0x0
2209 00:38:57.421819 DBI_WR = 0x0
2210 00:38:57.424833 DBI_RD = 0x0
2211 00:38:57.428272 OTF = 0x1
2212 00:38:57.428364 ===================================
2213 00:38:57.431464 ===================================
2214 00:38:57.435540 ANA top config
2215 00:38:57.438340 ===================================
2216 00:38:57.441339 DLL_ASYNC_EN = 0
2217 00:38:57.441450 ALL_SLAVE_EN = 0
2218 00:38:57.445140 NEW_RANK_MODE = 1
2219 00:38:57.448075 DLL_IDLE_MODE = 1
2220 00:38:57.451586 LP45_APHY_COMB_EN = 1
2221 00:38:57.454965 TX_ODT_DIS = 1
2222 00:38:57.455070 NEW_8X_MODE = 1
2223 00:38:57.457788 ===================================
2224 00:38:57.461264 ===================================
2225 00:38:57.464649 data_rate = 2400
2226 00:38:57.468132 CKR = 1
2227 00:38:57.471119 DQ_P2S_RATIO = 8
2228 00:38:57.474526 ===================================
2229 00:38:57.478149 CA_P2S_RATIO = 8
2230 00:38:57.481449 DQ_CA_OPEN = 0
2231 00:38:57.481552 DQ_SEMI_OPEN = 0
2232 00:38:57.484707 CA_SEMI_OPEN = 0
2233 00:38:57.488093 CA_FULL_RATE = 0
2234 00:38:57.491317 DQ_CKDIV4_EN = 0
2235 00:38:57.494484 CA_CKDIV4_EN = 0
2236 00:38:57.494593 CA_PREDIV_EN = 0
2237 00:38:57.498062 PH8_DLY = 17
2238 00:38:57.501498 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2239 00:38:57.504549 DQ_AAMCK_DIV = 4
2240 00:38:57.508125 CA_AAMCK_DIV = 4
2241 00:38:57.511511 CA_ADMCK_DIV = 4
2242 00:38:57.511618 DQ_TRACK_CA_EN = 0
2243 00:38:57.514455 CA_PICK = 1200
2244 00:38:57.517984 CA_MCKIO = 1200
2245 00:38:57.521368 MCKIO_SEMI = 0
2246 00:38:57.524648 PLL_FREQ = 2366
2247 00:38:57.528082 DQ_UI_PI_RATIO = 32
2248 00:38:57.531429 CA_UI_PI_RATIO = 0
2249 00:38:57.534800 ===================================
2250 00:38:57.538265 ===================================
2251 00:38:57.538367 memory_type:LPDDR4
2252 00:38:57.541544 GP_NUM : 10
2253 00:38:57.544758 SRAM_EN : 1
2254 00:38:57.544861 MD32_EN : 0
2255 00:38:57.547844 ===================================
2256 00:38:57.551261 [ANA_INIT] >>>>>>>>>>>>>>
2257 00:38:57.554520 <<<<<< [CONFIGURE PHASE]: ANA_TX
2258 00:38:57.557858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2259 00:38:57.561226 ===================================
2260 00:38:57.564698 data_rate = 2400,PCW = 0X5b00
2261 00:38:57.568137 ===================================
2262 00:38:57.570953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2263 00:38:57.574533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 00:38:57.581366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 00:38:57.584730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2266 00:38:57.588152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2267 00:38:57.591102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2268 00:38:57.594401 [ANA_INIT] flow start
2269 00:38:57.597743 [ANA_INIT] PLL >>>>>>>>
2270 00:38:57.597849 [ANA_INIT] PLL <<<<<<<<
2271 00:38:57.600958 [ANA_INIT] MIDPI >>>>>>>>
2272 00:38:57.604405 [ANA_INIT] MIDPI <<<<<<<<
2273 00:38:57.604513 [ANA_INIT] DLL >>>>>>>>
2274 00:38:57.608035 [ANA_INIT] DLL <<<<<<<<
2275 00:38:57.611162 [ANA_INIT] flow end
2276 00:38:57.614679 ============ LP4 DIFF to SE enter ============
2277 00:38:57.618185 ============ LP4 DIFF to SE exit ============
2278 00:38:57.621330 [ANA_INIT] <<<<<<<<<<<<<
2279 00:38:57.624830 [Flow] Enable top DCM control >>>>>
2280 00:38:57.628113 [Flow] Enable top DCM control <<<<<
2281 00:38:57.630936 Enable DLL master slave shuffle
2282 00:38:57.634371 ==============================================================
2283 00:38:57.637702 Gating Mode config
2284 00:38:57.644510 ==============================================================
2285 00:38:57.644649 Config description:
2286 00:38:57.654045 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2287 00:38:57.660896 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2288 00:38:57.668012 SELPH_MODE 0: By rank 1: By Phase
2289 00:38:57.671019 ==============================================================
2290 00:38:57.674177 GAT_TRACK_EN = 1
2291 00:38:57.677275 RX_GATING_MODE = 2
2292 00:38:57.680841 RX_GATING_TRACK_MODE = 2
2293 00:38:57.684233 SELPH_MODE = 1
2294 00:38:57.687205 PICG_EARLY_EN = 1
2295 00:38:57.690705 VALID_LAT_VALUE = 1
2296 00:38:57.694151 ==============================================================
2297 00:38:57.697598 Enter into Gating configuration >>>>
2298 00:38:57.700544 Exit from Gating configuration <<<<
2299 00:38:57.703995 Enter into DVFS_PRE_config >>>>>
2300 00:38:57.716939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2301 00:38:57.720568 Exit from DVFS_PRE_config <<<<<
2302 00:38:57.724177 Enter into PICG configuration >>>>
2303 00:38:57.727155 Exit from PICG configuration <<<<
2304 00:38:57.727270 [RX_INPUT] configuration >>>>>
2305 00:38:57.730628 [RX_INPUT] configuration <<<<<
2306 00:38:57.737591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2307 00:38:57.740744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2308 00:38:57.747591 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 00:38:57.753966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 00:38:57.760620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 00:38:57.766921 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 00:38:57.770243 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2313 00:38:57.773690 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2314 00:38:57.776859 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2315 00:38:57.784064 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2316 00:38:57.787111 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2317 00:38:57.790535 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 00:38:57.793910 ===================================
2319 00:38:57.796869 LPDDR4 DRAM CONFIGURATION
2320 00:38:57.800316 ===================================
2321 00:38:57.803878 EX_ROW_EN[0] = 0x0
2322 00:38:57.803954 EX_ROW_EN[1] = 0x0
2323 00:38:57.807235 LP4Y_EN = 0x0
2324 00:38:57.807309 WORK_FSP = 0x0
2325 00:38:57.810664 WL = 0x4
2326 00:38:57.810793 RL = 0x4
2327 00:38:57.813621 BL = 0x2
2328 00:38:57.813753 RPST = 0x0
2329 00:38:57.816932 RD_PRE = 0x0
2330 00:38:57.817062 WR_PRE = 0x1
2331 00:38:57.820320 WR_PST = 0x0
2332 00:38:57.820442 DBI_WR = 0x0
2333 00:38:57.824077 DBI_RD = 0x0
2334 00:38:57.824206 OTF = 0x1
2335 00:38:57.827251 ===================================
2336 00:38:57.830551 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2337 00:38:57.837155 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2338 00:38:57.840105 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2339 00:38:57.843775 ===================================
2340 00:38:57.846912 LPDDR4 DRAM CONFIGURATION
2341 00:38:57.850531 ===================================
2342 00:38:57.850666 EX_ROW_EN[0] = 0x10
2343 00:38:57.853936 EX_ROW_EN[1] = 0x0
2344 00:38:57.857126 LP4Y_EN = 0x0
2345 00:38:57.857234 WORK_FSP = 0x0
2346 00:38:57.860172 WL = 0x4
2347 00:38:57.860333 RL = 0x4
2348 00:38:57.863901 BL = 0x2
2349 00:38:57.864035 RPST = 0x0
2350 00:38:57.866873 RD_PRE = 0x0
2351 00:38:57.867004 WR_PRE = 0x1
2352 00:38:57.870309 WR_PST = 0x0
2353 00:38:57.870439 DBI_WR = 0x0
2354 00:38:57.873677 DBI_RD = 0x0
2355 00:38:57.873786 OTF = 0x1
2356 00:38:57.877249 ===================================
2357 00:38:57.883870 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2358 00:38:57.883971 ==
2359 00:38:57.887312 Dram Type= 6, Freq= 0, CH_0, rank 0
2360 00:38:57.890610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 00:38:57.890726 ==
2362 00:38:57.893839 [Duty_Offset_Calibration]
2363 00:38:57.897094 B0:2 B1:0 CA:3
2364 00:38:57.897178
2365 00:38:57.900208 [DutyScan_Calibration_Flow] k_type=0
2366 00:38:57.908214
2367 00:38:57.908353 ==CLK 0==
2368 00:38:57.911709 Final CLK duty delay cell = 0
2369 00:38:57.915290 [0] MAX Duty = 5031%(X100), DQS PI = 12
2370 00:38:57.918717 [0] MIN Duty = 4906%(X100), DQS PI = 54
2371 00:38:57.921493 [0] AVG Duty = 4968%(X100)
2372 00:38:57.921617
2373 00:38:57.924909 CH0 CLK Duty spec in!! Max-Min= 125%
2374 00:38:57.928391 [DutyScan_Calibration_Flow] ====Done====
2375 00:38:57.928493
2376 00:38:57.931461 [DutyScan_Calibration_Flow] k_type=1
2377 00:38:57.947301
2378 00:38:57.947415 ==DQS 0 ==
2379 00:38:57.950282 Final DQS duty delay cell = 0
2380 00:38:57.953623 [0] MAX Duty = 5062%(X100), DQS PI = 12
2381 00:38:57.957112 [0] MIN Duty = 4907%(X100), DQS PI = 2
2382 00:38:57.957193 [0] AVG Duty = 4984%(X100)
2383 00:38:57.960252
2384 00:38:57.960333 ==DQS 1 ==
2385 00:38:57.963889 Final DQS duty delay cell = -4
2386 00:38:57.966880 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2387 00:38:57.970586 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2388 00:38:57.973535 [-4] AVG Duty = 4922%(X100)
2389 00:38:57.973612
2390 00:38:57.977058 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2391 00:38:57.977135
2392 00:38:57.980305 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2393 00:38:57.983757 [DutyScan_Calibration_Flow] ====Done====
2394 00:38:57.983831
2395 00:38:57.987125 [DutyScan_Calibration_Flow] k_type=3
2396 00:38:58.004517
2397 00:38:58.004656 ==DQM 0 ==
2398 00:38:58.007678 Final DQM duty delay cell = 0
2399 00:38:58.011175 [0] MAX Duty = 5124%(X100), DQS PI = 28
2400 00:38:58.014816 [0] MIN Duty = 4876%(X100), DQS PI = 0
2401 00:38:58.014958 [0] AVG Duty = 5000%(X100)
2402 00:38:58.017542
2403 00:38:58.017638 ==DQM 1 ==
2404 00:38:58.021141 Final DQM duty delay cell = 4
2405 00:38:58.024680 [4] MAX Duty = 5124%(X100), DQS PI = 50
2406 00:38:58.027650 [4] MIN Duty = 5000%(X100), DQS PI = 14
2407 00:38:58.027781 [4] AVG Duty = 5062%(X100)
2408 00:38:58.031002
2409 00:38:58.034405 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2410 00:38:58.034510
2411 00:38:58.037697 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2412 00:38:58.041135 [DutyScan_Calibration_Flow] ====Done====
2413 00:38:58.041239
2414 00:38:58.044447 [DutyScan_Calibration_Flow] k_type=2
2415 00:38:58.059229
2416 00:38:58.059387 ==DQ 0 ==
2417 00:38:58.062963 Final DQ duty delay cell = -4
2418 00:38:58.066031 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2419 00:38:58.069527 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2420 00:38:58.072672 [-4] AVG Duty = 4969%(X100)
2421 00:38:58.072783
2422 00:38:58.072876 ==DQ 1 ==
2423 00:38:58.075946 Final DQ duty delay cell = -4
2424 00:38:58.079123 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2425 00:38:58.082819 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2426 00:38:58.086116 [-4] AVG Duty = 4938%(X100)
2427 00:38:58.086220
2428 00:38:58.089462 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2429 00:38:58.089554
2430 00:38:58.092990 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2431 00:38:58.095838 [DutyScan_Calibration_Flow] ====Done====
2432 00:38:58.095935 ==
2433 00:38:58.099166 Dram Type= 6, Freq= 0, CH_1, rank 0
2434 00:38:58.102842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2435 00:38:58.102979 ==
2436 00:38:58.106204 [Duty_Offset_Calibration]
2437 00:38:58.106286 B0:1 B1:-2 CA:0
2438 00:38:58.106353
2439 00:38:58.109040 [DutyScan_Calibration_Flow] k_type=0
2440 00:38:58.119731
2441 00:38:58.119848 ==CLK 0==
2442 00:38:58.123345 Final CLK duty delay cell = 0
2443 00:38:58.126441 [0] MAX Duty = 5031%(X100), DQS PI = 16
2444 00:38:58.129707 [0] MIN Duty = 4844%(X100), DQS PI = 58
2445 00:38:58.129844 [0] AVG Duty = 4937%(X100)
2446 00:38:58.133245
2447 00:38:58.136645 CH1 CLK Duty spec in!! Max-Min= 187%
2448 00:38:58.140110 [DutyScan_Calibration_Flow] ====Done====
2449 00:38:58.140217
2450 00:38:58.143434 [DutyScan_Calibration_Flow] k_type=1
2451 00:38:58.158280
2452 00:38:58.158451 ==DQS 0 ==
2453 00:38:58.161728 Final DQS duty delay cell = -4
2454 00:38:58.165207 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2455 00:38:58.168541 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2456 00:38:58.171822 [-4] AVG Duty = 4969%(X100)
2457 00:38:58.171944
2458 00:38:58.172054 ==DQS 1 ==
2459 00:38:58.175351 Final DQS duty delay cell = 0
2460 00:38:58.178675 [0] MAX Duty = 5093%(X100), DQS PI = 0
2461 00:38:58.181987 [0] MIN Duty = 4875%(X100), DQS PI = 26
2462 00:38:58.182118 [0] AVG Duty = 4984%(X100)
2463 00:38:58.185228
2464 00:38:58.188935 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2465 00:38:58.189023
2466 00:38:58.192052 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2467 00:38:58.195147 [DutyScan_Calibration_Flow] ====Done====
2468 00:38:58.195294
2469 00:38:58.198649 [DutyScan_Calibration_Flow] k_type=3
2470 00:38:58.215208
2471 00:38:58.215442 ==DQM 0 ==
2472 00:38:58.218113 Final DQM duty delay cell = 0
2473 00:38:58.221574 [0] MAX Duty = 5000%(X100), DQS PI = 24
2474 00:38:58.224951 [0] MIN Duty = 4876%(X100), DQS PI = 52
2475 00:38:58.228234 [0] AVG Duty = 4938%(X100)
2476 00:38:58.228344
2477 00:38:58.228438 ==DQM 1 ==
2478 00:38:58.231593 Final DQM duty delay cell = 0
2479 00:38:58.235083 [0] MAX Duty = 5031%(X100), DQS PI = 36
2480 00:38:58.237952 [0] MIN Duty = 4907%(X100), DQS PI = 0
2481 00:38:58.241942 [0] AVG Duty = 4969%(X100)
2482 00:38:58.242053
2483 00:38:58.244929 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2484 00:38:58.245013
2485 00:38:58.248096 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2486 00:38:58.251276 [DutyScan_Calibration_Flow] ====Done====
2487 00:38:58.251387
2488 00:38:58.254522 [DutyScan_Calibration_Flow] k_type=2
2489 00:38:58.271700
2490 00:38:58.271858 ==DQ 0 ==
2491 00:38:58.275051 Final DQ duty delay cell = 0
2492 00:38:58.277980 [0] MAX Duty = 5062%(X100), DQS PI = 12
2493 00:38:58.281856 [0] MIN Duty = 4938%(X100), DQS PI = 54
2494 00:38:58.281943 [0] AVG Duty = 5000%(X100)
2495 00:38:58.282008
2496 00:38:58.284667 ==DQ 1 ==
2497 00:38:58.288074 Final DQ duty delay cell = 0
2498 00:38:58.291300 [0] MAX Duty = 5125%(X100), DQS PI = 36
2499 00:38:58.294787 [0] MIN Duty = 4969%(X100), DQS PI = 26
2500 00:38:58.294881 [0] AVG Duty = 5047%(X100)
2501 00:38:58.294948
2502 00:38:58.297956 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2503 00:38:58.301189
2504 00:38:58.304985 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2505 00:38:58.307909 [DutyScan_Calibration_Flow] ====Done====
2506 00:38:58.311274 nWR fixed to 30
2507 00:38:58.311378 [ModeRegInit_LP4] CH0 RK0
2508 00:38:58.314723 [ModeRegInit_LP4] CH0 RK1
2509 00:38:58.318117 [ModeRegInit_LP4] CH1 RK0
2510 00:38:58.318218 [ModeRegInit_LP4] CH1 RK1
2511 00:38:58.321555 match AC timing 7
2512 00:38:58.325019 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2513 00:38:58.328570 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2514 00:38:58.334515 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2515 00:38:58.337905 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2516 00:38:58.344662 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2517 00:38:58.344772 ==
2518 00:38:58.348570 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 00:38:58.351633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 00:38:58.351735 ==
2521 00:38:58.358171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 00:38:58.361589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2523 00:38:58.371283 [CA 0] Center 40 (10~71) winsize 62
2524 00:38:58.374849 [CA 1] Center 40 (10~70) winsize 61
2525 00:38:58.378174 [CA 2] Center 36 (6~66) winsize 61
2526 00:38:58.381688 [CA 3] Center 35 (5~66) winsize 62
2527 00:38:58.385213 [CA 4] Center 34 (4~65) winsize 62
2528 00:38:58.387922 [CA 5] Center 33 (3~64) winsize 62
2529 00:38:58.388037
2530 00:38:58.391385 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2531 00:38:58.391486
2532 00:38:58.394727 [CATrainingPosCal] consider 1 rank data
2533 00:38:58.398296 u2DelayCellTimex100 = 270/100 ps
2534 00:38:58.401867 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2535 00:38:58.408304 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2536 00:38:58.411624 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2537 00:38:58.414796 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 00:38:58.418220 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2539 00:38:58.421774 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2540 00:38:58.421878
2541 00:38:58.424754 CA PerBit enable=1, Macro0, CA PI delay=33
2542 00:38:58.424871
2543 00:38:58.428165 [CBTSetCACLKResult] CA Dly = 33
2544 00:38:58.431647 CS Dly: 7 (0~38)
2545 00:38:58.431754 ==
2546 00:38:58.434680 Dram Type= 6, Freq= 0, CH_0, rank 1
2547 00:38:58.437985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 00:38:58.438097 ==
2549 00:38:58.444955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2550 00:38:58.447777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2551 00:38:58.458001 [CA 0] Center 40 (10~70) winsize 61
2552 00:38:58.460875 [CA 1] Center 40 (10~70) winsize 61
2553 00:38:58.464425 [CA 2] Center 35 (5~66) winsize 62
2554 00:38:58.467750 [CA 3] Center 35 (5~66) winsize 62
2555 00:38:58.471177 [CA 4] Center 34 (3~65) winsize 63
2556 00:38:58.474644 [CA 5] Center 33 (3~64) winsize 62
2557 00:38:58.474747
2558 00:38:58.477722 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2559 00:38:58.477828
2560 00:38:58.480995 [CATrainingPosCal] consider 2 rank data
2561 00:38:58.484267 u2DelayCellTimex100 = 270/100 ps
2562 00:38:58.487833 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2563 00:38:58.494228 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2564 00:38:58.497744 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2565 00:38:58.501265 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 00:38:58.504155 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2567 00:38:58.507608 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2568 00:38:58.507686
2569 00:38:58.511031 CA PerBit enable=1, Macro0, CA PI delay=33
2570 00:38:58.511136
2571 00:38:58.514432 [CBTSetCACLKResult] CA Dly = 33
2572 00:38:58.517604 CS Dly: 8 (0~40)
2573 00:38:58.517708
2574 00:38:58.521069 ----->DramcWriteLeveling(PI) begin...
2575 00:38:58.521172 ==
2576 00:38:58.524247 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 00:38:58.527681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 00:38:58.527786 ==
2579 00:38:58.531115 Write leveling (Byte 0): 34 => 34
2580 00:38:58.534515 Write leveling (Byte 1): 31 => 31
2581 00:38:58.537550 DramcWriteLeveling(PI) end<-----
2582 00:38:58.537654
2583 00:38:58.537745 ==
2584 00:38:58.540969 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 00:38:58.544488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 00:38:58.544618 ==
2587 00:38:58.547846 [Gating] SW mode calibration
2588 00:38:58.554345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2589 00:38:58.561113 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2590 00:38:58.564597 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 00:38:58.567808 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2592 00:38:58.574475 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 00:38:58.577885 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 00:38:58.580764 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 00:38:58.587548 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 00:38:58.591116 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 00:38:58.594417 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 00:38:58.597867 1 0 0 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
2599 00:38:58.604472 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2600 00:38:58.607680 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 00:38:58.611012 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 00:38:58.617641 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 00:38:58.621092 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 00:38:58.624378 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 00:38:58.631111 1 0 28 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
2606 00:38:58.634336 1 1 0 | B1->B0 | 2828 3030 | 0 1 | (0 0) (0 0)
2607 00:38:58.637952 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 00:38:58.644290 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 00:38:58.647859 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 00:38:58.650814 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 00:38:58.657569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 00:38:58.661131 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 00:38:58.664045 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2614 00:38:58.670780 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 00:38:58.674345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 00:38:58.677155 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 00:38:58.684142 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 00:38:58.687096 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 00:38:58.690481 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 00:38:58.697440 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 00:38:58.700215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 00:38:58.703612 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 00:38:58.710262 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:38:58.713564 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:38:58.716991 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:38:58.723288 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:38:58.727113 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:38:58.730079 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:38:58.737001 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:38:58.740435 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2631 00:38:58.743359 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2632 00:38:58.747104 Total UI for P1: 0, mck2ui 16
2633 00:38:58.750176 best dqsien dly found for B0: ( 1, 4, 0)
2634 00:38:58.753291 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 00:38:58.756741 Total UI for P1: 0, mck2ui 16
2636 00:38:58.760302 best dqsien dly found for B1: ( 1, 4, 4)
2637 00:38:58.763551 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2638 00:38:58.767020 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2639 00:38:58.770210
2640 00:38:58.773639 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2641 00:38:58.776478 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2642 00:38:58.780038 [Gating] SW calibration Done
2643 00:38:58.780162 ==
2644 00:38:58.783467 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 00:38:58.786835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 00:38:58.786963 ==
2647 00:38:58.787080 RX Vref Scan: 0
2648 00:38:58.787192
2649 00:38:58.790173 RX Vref 0 -> 0, step: 1
2650 00:38:58.790296
2651 00:38:58.793652 RX Delay -40 -> 252, step: 8
2652 00:38:58.796617 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2653 00:38:58.799955 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2654 00:38:58.807047 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2655 00:38:58.810238 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2656 00:38:58.813519 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2657 00:38:58.817214 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2658 00:38:58.819974 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2659 00:38:58.823535 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2660 00:38:58.830315 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2661 00:38:58.833805 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2662 00:38:58.836927 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2663 00:38:58.840380 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2664 00:38:58.843807 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2665 00:38:58.850263 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2666 00:38:58.853695 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2667 00:38:58.856628 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2668 00:38:58.856709 ==
2669 00:38:58.859902 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 00:38:58.863145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 00:38:58.863232 ==
2672 00:38:58.866596 DQS Delay:
2673 00:38:58.866679 DQS0 = 0, DQS1 = 0
2674 00:38:58.870012 DQM Delay:
2675 00:38:58.870096 DQM0 = 112, DQM1 = 102
2676 00:38:58.870160 DQ Delay:
2677 00:38:58.876705 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2678 00:38:58.880085 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2679 00:38:58.883368 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2680 00:38:58.886668 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2681 00:38:58.886749
2682 00:38:58.886813
2683 00:38:58.886877 ==
2684 00:38:58.890265 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 00:38:58.893345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 00:38:58.893424 ==
2687 00:38:58.893488
2688 00:38:58.893552
2689 00:38:58.896827 TX Vref Scan disable
2690 00:38:58.896911 == TX Byte 0 ==
2691 00:38:58.903288 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2692 00:38:58.906776 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2693 00:38:58.906860 == TX Byte 1 ==
2694 00:38:58.913711 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2695 00:38:58.917075 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2696 00:38:58.917159 ==
2697 00:38:58.920325 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 00:38:58.923126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 00:38:58.923211 ==
2700 00:38:58.936381 TX Vref=22, minBit 0, minWin=25, winSum=414
2701 00:38:58.939684 TX Vref=24, minBit 7, minWin=25, winSum=423
2702 00:38:58.943349 TX Vref=26, minBit 1, minWin=26, winSum=429
2703 00:38:58.946671 TX Vref=28, minBit 10, minWin=26, winSum=429
2704 00:38:58.950049 TX Vref=30, minBit 3, minWin=26, winSum=428
2705 00:38:58.953566 TX Vref=32, minBit 5, minWin=26, winSum=428
2706 00:38:58.959935 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 26
2707 00:38:58.960017
2708 00:38:58.963142 Final TX Range 1 Vref 26
2709 00:38:58.963257
2710 00:38:58.963326 ==
2711 00:38:58.966710 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 00:38:58.969716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 00:38:58.969795 ==
2714 00:38:58.969863
2715 00:38:58.973260
2716 00:38:58.973372 TX Vref Scan disable
2717 00:38:58.976663 == TX Byte 0 ==
2718 00:38:58.979992 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2719 00:38:58.983525 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2720 00:38:58.986885 == TX Byte 1 ==
2721 00:38:58.990038 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2722 00:38:58.993359 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2723 00:38:58.993442
2724 00:38:58.996538 [DATLAT]
2725 00:38:58.996627 Freq=1200, CH0 RK0
2726 00:38:58.996692
2727 00:38:58.999773 DATLAT Default: 0xd
2728 00:38:58.999854 0, 0xFFFF, sum = 0
2729 00:38:59.003335 1, 0xFFFF, sum = 0
2730 00:38:59.003416 2, 0xFFFF, sum = 0
2731 00:38:59.006612 3, 0xFFFF, sum = 0
2732 00:38:59.006691 4, 0xFFFF, sum = 0
2733 00:38:59.010157 5, 0xFFFF, sum = 0
2734 00:38:59.010272 6, 0xFFFF, sum = 0
2735 00:38:59.014289 7, 0xFFFF, sum = 0
2736 00:38:59.014382 8, 0xFFFF, sum = 0
2737 00:38:59.016825 9, 0xFFFF, sum = 0
2738 00:38:59.016917 10, 0xFFFF, sum = 0
2739 00:38:59.020048 11, 0xFFFF, sum = 0
2740 00:38:59.020196 12, 0x0, sum = 1
2741 00:38:59.023481 13, 0x0, sum = 2
2742 00:38:59.023566 14, 0x0, sum = 3
2743 00:38:59.026983 15, 0x0, sum = 4
2744 00:38:59.027099 best_step = 13
2745 00:38:59.027192
2746 00:38:59.027295 ==
2747 00:38:59.030328 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 00:38:59.036965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 00:38:59.037096 ==
2750 00:38:59.037222 RX Vref Scan: 1
2751 00:38:59.037337
2752 00:38:59.040438 Set Vref Range= 32 -> 127
2753 00:38:59.040569
2754 00:38:59.043397 RX Vref 32 -> 127, step: 1
2755 00:38:59.043525
2756 00:38:59.046794 RX Delay -37 -> 252, step: 4
2757 00:38:59.046904
2758 00:38:59.046998 Set Vref, RX VrefLevel [Byte0]: 32
2759 00:38:59.050345 [Byte1]: 32
2760 00:38:59.054943
2761 00:38:59.055017 Set Vref, RX VrefLevel [Byte0]: 33
2762 00:38:59.058455 [Byte1]: 33
2763 00:38:59.062983
2764 00:38:59.063063 Set Vref, RX VrefLevel [Byte0]: 34
2765 00:38:59.066050 [Byte1]: 34
2766 00:38:59.070749
2767 00:38:59.070828 Set Vref, RX VrefLevel [Byte0]: 35
2768 00:38:59.074231 [Byte1]: 35
2769 00:38:59.079023
2770 00:38:59.079160 Set Vref, RX VrefLevel [Byte0]: 36
2771 00:38:59.082505 [Byte1]: 36
2772 00:38:59.086988
2773 00:38:59.087072 Set Vref, RX VrefLevel [Byte0]: 37
2774 00:38:59.090421 [Byte1]: 37
2775 00:38:59.095065
2776 00:38:59.095151 Set Vref, RX VrefLevel [Byte0]: 38
2777 00:38:59.098204 [Byte1]: 38
2778 00:38:59.102828
2779 00:38:59.102913 Set Vref, RX VrefLevel [Byte0]: 39
2780 00:38:59.106371 [Byte1]: 39
2781 00:38:59.111029
2782 00:38:59.111120 Set Vref, RX VrefLevel [Byte0]: 40
2783 00:38:59.114332 [Byte1]: 40
2784 00:38:59.118966
2785 00:38:59.119045 Set Vref, RX VrefLevel [Byte0]: 41
2786 00:38:59.122377 [Byte1]: 41
2787 00:38:59.127050
2788 00:38:59.127164 Set Vref, RX VrefLevel [Byte0]: 42
2789 00:38:59.130177 [Byte1]: 42
2790 00:38:59.135010
2791 00:38:59.135089 Set Vref, RX VrefLevel [Byte0]: 43
2792 00:38:59.138197 [Byte1]: 43
2793 00:38:59.142972
2794 00:38:59.143049 Set Vref, RX VrefLevel [Byte0]: 44
2795 00:38:59.146423 [Byte1]: 44
2796 00:38:59.150971
2797 00:38:59.151058 Set Vref, RX VrefLevel [Byte0]: 45
2798 00:38:59.154230 [Byte1]: 45
2799 00:38:59.158951
2800 00:38:59.159031 Set Vref, RX VrefLevel [Byte0]: 46
2801 00:38:59.162340 [Byte1]: 46
2802 00:38:59.166978
2803 00:38:59.167092 Set Vref, RX VrefLevel [Byte0]: 47
2804 00:38:59.170483 [Byte1]: 47
2805 00:38:59.175136
2806 00:38:59.175272 Set Vref, RX VrefLevel [Byte0]: 48
2807 00:38:59.178000 [Byte1]: 48
2808 00:38:59.182840
2809 00:38:59.182972 Set Vref, RX VrefLevel [Byte0]: 49
2810 00:38:59.186366 [Byte1]: 49
2811 00:38:59.190940
2812 00:38:59.191074 Set Vref, RX VrefLevel [Byte0]: 50
2813 00:38:59.194293 [Byte1]: 50
2814 00:38:59.198820
2815 00:38:59.198943 Set Vref, RX VrefLevel [Byte0]: 51
2816 00:38:59.202336 [Byte1]: 51
2817 00:38:59.207158
2818 00:38:59.207290 Set Vref, RX VrefLevel [Byte0]: 52
2819 00:38:59.210120 [Byte1]: 52
2820 00:38:59.214707
2821 00:38:59.214787 Set Vref, RX VrefLevel [Byte0]: 53
2822 00:38:59.218357 [Byte1]: 53
2823 00:38:59.222643
2824 00:38:59.222757 Set Vref, RX VrefLevel [Byte0]: 54
2825 00:38:59.226381 [Byte1]: 54
2826 00:38:59.230759
2827 00:38:59.230886 Set Vref, RX VrefLevel [Byte0]: 55
2828 00:38:59.233972 [Byte1]: 55
2829 00:38:59.238839
2830 00:38:59.238938 Set Vref, RX VrefLevel [Byte0]: 56
2831 00:38:59.242339 [Byte1]: 56
2832 00:38:59.246694
2833 00:38:59.246774 Set Vref, RX VrefLevel [Byte0]: 57
2834 00:38:59.250287 [Byte1]: 57
2835 00:38:59.254756
2836 00:38:59.254836 Set Vref, RX VrefLevel [Byte0]: 58
2837 00:38:59.258579 [Byte1]: 58
2838 00:38:59.263182
2839 00:38:59.263274 Set Vref, RX VrefLevel [Byte0]: 59
2840 00:38:59.266046 [Byte1]: 59
2841 00:38:59.271158
2842 00:38:59.271248 Set Vref, RX VrefLevel [Byte0]: 60
2843 00:38:59.274654 [Byte1]: 60
2844 00:38:59.278885
2845 00:38:59.278970 Set Vref, RX VrefLevel [Byte0]: 61
2846 00:38:59.282519 [Byte1]: 61
2847 00:38:59.287095
2848 00:38:59.287180 Set Vref, RX VrefLevel [Byte0]: 62
2849 00:38:59.290469 [Byte1]: 62
2850 00:38:59.295140
2851 00:38:59.295232 Set Vref, RX VrefLevel [Byte0]: 63
2852 00:38:59.298235 [Byte1]: 63
2853 00:38:59.302679
2854 00:38:59.302765 Set Vref, RX VrefLevel [Byte0]: 64
2855 00:38:59.306195 [Byte1]: 64
2856 00:38:59.311252
2857 00:38:59.311340 Set Vref, RX VrefLevel [Byte0]: 65
2858 00:38:59.313987 [Byte1]: 65
2859 00:38:59.319036
2860 00:38:59.319125 Set Vref, RX VrefLevel [Byte0]: 66
2861 00:38:59.322614 [Byte1]: 66
2862 00:38:59.326926
2863 00:38:59.327008 Set Vref, RX VrefLevel [Byte0]: 67
2864 00:38:59.330293 [Byte1]: 67
2865 00:38:59.335171
2866 00:38:59.335250 Set Vref, RX VrefLevel [Byte0]: 68
2867 00:38:59.338316 [Byte1]: 68
2868 00:38:59.342830
2869 00:38:59.342920 Set Vref, RX VrefLevel [Byte0]: 69
2870 00:38:59.346433 [Byte1]: 69
2871 00:38:59.350752
2872 00:38:59.350833 Set Vref, RX VrefLevel [Byte0]: 70
2873 00:38:59.354145 [Byte1]: 70
2874 00:38:59.358984
2875 00:38:59.359063 Set Vref, RX VrefLevel [Byte0]: 71
2876 00:38:59.362374 [Byte1]: 71
2877 00:38:59.366988
2878 00:38:59.367073 Set Vref, RX VrefLevel [Byte0]: 72
2879 00:38:59.370311 [Byte1]: 72
2880 00:38:59.374880
2881 00:38:59.374960 Set Vref, RX VrefLevel [Byte0]: 73
2882 00:38:59.378551 [Byte1]: 73
2883 00:38:59.382945
2884 00:38:59.383055 Final RX Vref Byte 0 = 60 to rank0
2885 00:38:59.386101 Final RX Vref Byte 1 = 55 to rank0
2886 00:38:59.389785 Final RX Vref Byte 0 = 60 to rank1
2887 00:38:59.392918 Final RX Vref Byte 1 = 55 to rank1==
2888 00:38:59.396370 Dram Type= 6, Freq= 0, CH_0, rank 0
2889 00:38:59.403236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 00:38:59.403342 ==
2891 00:38:59.403439 DQS Delay:
2892 00:38:59.403537 DQS0 = 0, DQS1 = 0
2893 00:38:59.406558 DQM Delay:
2894 00:38:59.406632 DQM0 = 111, DQM1 = 101
2895 00:38:59.409437 DQ Delay:
2896 00:38:59.412908 DQ0 =110, DQ1 =110, DQ2 =112, DQ3 =108
2897 00:38:59.416364 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2898 00:38:59.419777 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2899 00:38:59.423001 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =108
2900 00:38:59.423108
2901 00:38:59.423200
2902 00:38:59.429337 [DQSOSCAuto] RK0, (LSB)MR18= 0xfaf9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2903 00:38:59.432887 CH0 RK0: MR19=303, MR18=FAF9
2904 00:38:59.439547 CH0_RK0: MR19=0x303, MR18=0xFAF9, DQSOSC=412, MR23=63, INC=38, DEC=25
2905 00:38:59.439637
2906 00:38:59.443024 ----->DramcWriteLeveling(PI) begin...
2907 00:38:59.443105 ==
2908 00:38:59.446220 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 00:38:59.449387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 00:38:59.452471 ==
2911 00:38:59.452584 Write leveling (Byte 0): 32 => 32
2912 00:38:59.456190 Write leveling (Byte 1): 30 => 30
2913 00:38:59.459577 DramcWriteLeveling(PI) end<-----
2914 00:38:59.459688
2915 00:38:59.459780 ==
2916 00:38:59.463010 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 00:38:59.469324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 00:38:59.469409 ==
2919 00:38:59.469475 [Gating] SW mode calibration
2920 00:38:59.479409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2921 00:38:59.482595 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2922 00:38:59.485952 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2923 00:38:59.492841 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 00:38:59.496223 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 00:38:59.499448 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 00:38:59.506029 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 00:38:59.509415 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 00:38:59.512821 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2929 00:38:59.519139 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2930 00:38:59.522588 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2931 00:38:59.525994 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 00:38:59.532595 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 00:38:59.535706 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 00:38:59.539384 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 00:38:59.545546 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 00:38:59.548960 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2937 00:38:59.552394 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
2938 00:38:59.559125 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2939 00:38:59.562743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 00:38:59.565835 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 00:38:59.572511 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 00:38:59.576090 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 00:38:59.578986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 00:38:59.585657 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 00:38:59.588889 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2946 00:38:59.592236 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2947 00:38:59.599118 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:38:59.602464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:38:59.605840 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:38:59.609303 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:38:59.616144 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:38:59.619418 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:38:59.622257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:38:59.629237 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:38:59.632655 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:38:59.636169 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:38:59.642268 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 00:38:59.645656 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 00:38:59.649304 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 00:38:59.655991 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 00:38:59.659332 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2962 00:38:59.662416 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2963 00:38:59.665870 Total UI for P1: 0, mck2ui 16
2964 00:38:59.669184 best dqsien dly found for B0: ( 1, 3, 28)
2965 00:38:59.675910 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 00:38:59.676017 Total UI for P1: 0, mck2ui 16
2967 00:38:59.679135 best dqsien dly found for B1: ( 1, 4, 0)
2968 00:38:59.685560 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2969 00:38:59.689004 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2970 00:38:59.689081
2971 00:38:59.692152 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2972 00:38:59.695858 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2973 00:38:59.699198 [Gating] SW calibration Done
2974 00:38:59.699275 ==
2975 00:38:59.702599 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 00:38:59.706020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 00:38:59.706102 ==
2978 00:38:59.708972 RX Vref Scan: 0
2979 00:38:59.709046
2980 00:38:59.709107 RX Vref 0 -> 0, step: 1
2981 00:38:59.709164
2982 00:38:59.712351 RX Delay -40 -> 252, step: 8
2983 00:38:59.715463 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2984 00:38:59.718907 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2985 00:38:59.725427 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2986 00:38:59.728886 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2987 00:38:59.732315 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2988 00:38:59.735849 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2989 00:38:59.739240 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2990 00:38:59.745537 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2991 00:38:59.748999 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2992 00:38:59.752145 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2993 00:38:59.755753 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2994 00:38:59.759164 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2995 00:38:59.765648 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2996 00:38:59.769230 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2997 00:38:59.772606 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2998 00:38:59.775576 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2999 00:38:59.775667 ==
3000 00:38:59.778827 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 00:38:59.782747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 00:38:59.785601 ==
3003 00:38:59.785686 DQS Delay:
3004 00:38:59.785753 DQS0 = 0, DQS1 = 0
3005 00:38:59.789077 DQM Delay:
3006 00:38:59.789212 DQM0 = 112, DQM1 = 102
3007 00:38:59.792426 DQ Delay:
3008 00:38:59.795570 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3009 00:38:59.799034 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3010 00:38:59.802271 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
3011 00:38:59.805934 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3012 00:38:59.806019
3013 00:38:59.806084
3014 00:38:59.806145 ==
3015 00:38:59.809008 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 00:38:59.812520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 00:38:59.812614 ==
3018 00:38:59.812680
3019 00:38:59.812741
3020 00:38:59.815874 TX Vref Scan disable
3021 00:38:59.818939 == TX Byte 0 ==
3022 00:38:59.822329 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3023 00:38:59.825696 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3024 00:38:59.829224 == TX Byte 1 ==
3025 00:38:59.832190 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3026 00:38:59.835516 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3027 00:38:59.835619 ==
3028 00:38:59.838719 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 00:38:59.845639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 00:38:59.845743 ==
3031 00:38:59.856121 TX Vref=22, minBit 1, minWin=26, winSum=429
3032 00:38:59.859483 TX Vref=24, minBit 8, minWin=26, winSum=432
3033 00:38:59.862735 TX Vref=26, minBit 8, minWin=26, winSum=436
3034 00:38:59.865793 TX Vref=28, minBit 8, minWin=26, winSum=440
3035 00:38:59.869337 TX Vref=30, minBit 5, minWin=27, winSum=445
3036 00:38:59.872624 TX Vref=32, minBit 1, minWin=27, winSum=442
3037 00:38:59.879464 [TxChooseVref] Worse bit 5, Min win 27, Win sum 445, Final Vref 30
3038 00:38:59.879590
3039 00:38:59.883069 Final TX Range 1 Vref 30
3040 00:38:59.883195
3041 00:38:59.883310 ==
3042 00:38:59.886398 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 00:38:59.889733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 00:38:59.889856 ==
3045 00:38:59.889968
3046 00:38:59.890077
3047 00:38:59.892869 TX Vref Scan disable
3048 00:38:59.896448 == TX Byte 0 ==
3049 00:38:59.899675 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3050 00:38:59.902790 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3051 00:38:59.906443 == TX Byte 1 ==
3052 00:38:59.909765 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3053 00:38:59.912836 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3054 00:38:59.912962
3055 00:38:59.916167 [DATLAT]
3056 00:38:59.916290 Freq=1200, CH0 RK1
3057 00:38:59.916398
3058 00:38:59.919816 DATLAT Default: 0xd
3059 00:38:59.919924 0, 0xFFFF, sum = 0
3060 00:38:59.922580 1, 0xFFFF, sum = 0
3061 00:38:59.922657 2, 0xFFFF, sum = 0
3062 00:38:59.926334 3, 0xFFFF, sum = 0
3063 00:38:59.926429 4, 0xFFFF, sum = 0
3064 00:38:59.929134 5, 0xFFFF, sum = 0
3065 00:38:59.929213 6, 0xFFFF, sum = 0
3066 00:38:59.932554 7, 0xFFFF, sum = 0
3067 00:38:59.932643 8, 0xFFFF, sum = 0
3068 00:38:59.935995 9, 0xFFFF, sum = 0
3069 00:38:59.939610 10, 0xFFFF, sum = 0
3070 00:38:59.939699 11, 0xFFFF, sum = 0
3071 00:38:59.942502 12, 0x0, sum = 1
3072 00:38:59.942576 13, 0x0, sum = 2
3073 00:38:59.942643 14, 0x0, sum = 3
3074 00:38:59.945960 15, 0x0, sum = 4
3075 00:38:59.946052 best_step = 13
3076 00:38:59.946114
3077 00:38:59.949694 ==
3078 00:38:59.949783 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 00:38:59.955952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 00:38:59.956049 ==
3081 00:38:59.956115 RX Vref Scan: 0
3082 00:38:59.956175
3083 00:38:59.959449 RX Vref 0 -> 0, step: 1
3084 00:38:59.959523
3085 00:38:59.962366 RX Delay -29 -> 252, step: 4
3086 00:38:59.965724 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3087 00:38:59.969581 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3088 00:38:59.975813 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3089 00:38:59.979468 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3090 00:38:59.982506 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3091 00:38:59.985903 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3092 00:38:59.989336 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3093 00:38:59.996308 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3094 00:38:59.999099 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3095 00:39:00.002857 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3096 00:39:00.005940 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3097 00:39:00.009219 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3098 00:39:00.016066 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3099 00:39:00.019184 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3100 00:39:00.022577 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3101 00:39:00.026050 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3102 00:39:00.026130 ==
3103 00:39:00.029107 Dram Type= 6, Freq= 0, CH_0, rank 1
3104 00:39:00.035915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 00:39:00.036027 ==
3106 00:39:00.036130 DQS Delay:
3107 00:39:00.036220 DQS0 = 0, DQS1 = 0
3108 00:39:00.039327 DQM Delay:
3109 00:39:00.039411 DQM0 = 110, DQM1 = 102
3110 00:39:00.042864 DQ Delay:
3111 00:39:00.045578 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3112 00:39:00.049145 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3113 00:39:00.052603 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3114 00:39:00.055464 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3115 00:39:00.055544
3116 00:39:00.055636
3117 00:39:00.062347 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3118 00:39:00.065653 CH0 RK1: MR19=403, MR18=15FC
3119 00:39:00.072108 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3120 00:39:00.075475 [RxdqsGatingPostProcess] freq 1200
3121 00:39:00.082360 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3122 00:39:00.086269 best DQS0 dly(2T, 0.5T) = (0, 12)
3123 00:39:00.088819 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 00:39:00.088952 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3125 00:39:00.092463 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 00:39:00.095623 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 00:39:00.099009 best DQS1 dly(2T, 0.5T) = (0, 12)
3128 00:39:00.102078 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 00:39:00.105975 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3130 00:39:00.108836 Pre-setting of DQS Precalculation
3131 00:39:00.115746 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3132 00:39:00.115848 ==
3133 00:39:00.119108 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 00:39:00.122066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 00:39:00.122150 ==
3136 00:39:00.129098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 00:39:00.132439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 00:39:00.141950 [CA 0] Center 37 (7~67) winsize 61
3139 00:39:00.145428 [CA 1] Center 37 (7~68) winsize 62
3140 00:39:00.148249 [CA 2] Center 34 (4~64) winsize 61
3141 00:39:00.151903 [CA 3] Center 34 (4~64) winsize 61
3142 00:39:00.155282 [CA 4] Center 34 (4~64) winsize 61
3143 00:39:00.158729 [CA 5] Center 33 (3~63) winsize 61
3144 00:39:00.158807
3145 00:39:00.161489 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3146 00:39:00.161601
3147 00:39:00.164897 [CATrainingPosCal] consider 1 rank data
3148 00:39:00.168438 u2DelayCellTimex100 = 270/100 ps
3149 00:39:00.171944 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3150 00:39:00.175229 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 00:39:00.182060 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 00:39:00.184998 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 00:39:00.188394 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 00:39:00.191713 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3155 00:39:00.191841
3156 00:39:00.195133 CA PerBit enable=1, Macro0, CA PI delay=33
3157 00:39:00.195259
3158 00:39:00.198536 [CBTSetCACLKResult] CA Dly = 33
3159 00:39:00.198659 CS Dly: 6 (0~37)
3160 00:39:00.198773 ==
3161 00:39:00.201931 Dram Type= 6, Freq= 0, CH_1, rank 1
3162 00:39:00.208493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 00:39:00.208632 ==
3164 00:39:00.211990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3165 00:39:00.218391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3166 00:39:00.227410 [CA 0] Center 37 (7~68) winsize 62
3167 00:39:00.230806 [CA 1] Center 37 (7~68) winsize 62
3168 00:39:00.233943 [CA 2] Center 34 (4~65) winsize 62
3169 00:39:00.237330 [CA 3] Center 33 (3~64) winsize 62
3170 00:39:00.240831 [CA 4] Center 34 (4~64) winsize 61
3171 00:39:00.244397 [CA 5] Center 33 (3~64) winsize 62
3172 00:39:00.244496
3173 00:39:00.247140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3174 00:39:00.247263
3175 00:39:00.250646 [CATrainingPosCal] consider 2 rank data
3176 00:39:00.254194 u2DelayCellTimex100 = 270/100 ps
3177 00:39:00.257502 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3178 00:39:00.261114 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3179 00:39:00.267394 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3180 00:39:00.270683 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 00:39:00.274063 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 00:39:00.277629 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3183 00:39:00.277731
3184 00:39:00.280485 CA PerBit enable=1, Macro0, CA PI delay=33
3185 00:39:00.280631
3186 00:39:00.283851 [CBTSetCACLKResult] CA Dly = 33
3187 00:39:00.283948 CS Dly: 7 (0~40)
3188 00:39:00.284088
3189 00:39:00.287670 ----->DramcWriteLeveling(PI) begin...
3190 00:39:00.290873 ==
3191 00:39:00.290979 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 00:39:00.297249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 00:39:00.297437 ==
3194 00:39:00.300663 Write leveling (Byte 0): 28 => 28
3195 00:39:00.304201 Write leveling (Byte 1): 28 => 28
3196 00:39:00.307551 DramcWriteLeveling(PI) end<-----
3197 00:39:00.307647
3198 00:39:00.307741 ==
3199 00:39:00.310536 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 00:39:00.313809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 00:39:00.313903 ==
3202 00:39:00.317214 [Gating] SW mode calibration
3203 00:39:00.324763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3204 00:39:00.330501 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3205 00:39:00.333669 0 15 0 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
3206 00:39:00.337167 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 00:39:00.340619 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 00:39:00.347520 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 00:39:00.350605 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 00:39:00.353855 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 00:39:00.360615 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 00:39:00.364077 0 15 28 | B1->B0 | 2727 2b2b | 1 1 | (1 1) (1 0)
3213 00:39:00.366779 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3214 00:39:00.373799 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 00:39:00.377173 1 0 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3216 00:39:00.380479 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 00:39:00.387026 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 00:39:00.390406 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 00:39:00.393252 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3220 00:39:00.399945 1 0 28 | B1->B0 | 3d3d 4242 | 0 0 | (0 0) (0 0)
3221 00:39:00.403568 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3222 00:39:00.406658 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 00:39:00.413532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 00:39:00.417019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 00:39:00.420263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 00:39:00.427141 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 00:39:00.430578 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 00:39:00.433811 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3229 00:39:00.440169 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3230 00:39:00.443765 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:39:00.447013 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:39:00.453699 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:39:00.457052 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:39:00.460399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:39:00.463376 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:39:00.470519 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:39:00.473513 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:39:00.476945 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:39:00.483999 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 00:39:00.486732 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 00:39:00.490091 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 00:39:00.497154 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 00:39:00.500025 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3244 00:39:00.503526 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3245 00:39:00.509970 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3246 00:39:00.510084 Total UI for P1: 0, mck2ui 16
3247 00:39:00.516781 best dqsien dly found for B1: ( 1, 3, 30)
3248 00:39:00.520253 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 00:39:00.523387 Total UI for P1: 0, mck2ui 16
3250 00:39:00.526672 best dqsien dly found for B0: ( 1, 3, 30)
3251 00:39:00.530157 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3252 00:39:00.533384 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3253 00:39:00.533494
3254 00:39:00.536845 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3255 00:39:00.540085 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3256 00:39:00.543351 [Gating] SW calibration Done
3257 00:39:00.543435 ==
3258 00:39:00.546488 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 00:39:00.550341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 00:39:00.553532 ==
3261 00:39:00.553623 RX Vref Scan: 0
3262 00:39:00.553703
3263 00:39:00.556510 RX Vref 0 -> 0, step: 1
3264 00:39:00.556604
3265 00:39:00.556670 RX Delay -40 -> 252, step: 8
3266 00:39:00.563373 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3267 00:39:00.567209 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3268 00:39:00.570525 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3269 00:39:00.573600 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3270 00:39:00.577149 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3271 00:39:00.584033 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3272 00:39:00.586794 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3273 00:39:00.590305 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3274 00:39:00.593766 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3275 00:39:00.597241 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3276 00:39:00.603577 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3277 00:39:00.607068 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3278 00:39:00.610411 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3279 00:39:00.613708 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3280 00:39:00.617200 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3281 00:39:00.623655 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3282 00:39:00.623766 ==
3283 00:39:00.626894 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 00:39:00.630076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 00:39:00.630200 ==
3286 00:39:00.630314 DQS Delay:
3287 00:39:00.633844 DQS0 = 0, DQS1 = 0
3288 00:39:00.633969 DQM Delay:
3289 00:39:00.636892 DQM0 = 113, DQM1 = 105
3290 00:39:00.637020 DQ Delay:
3291 00:39:00.640121 DQ0 =123, DQ1 =107, DQ2 =99, DQ3 =111
3292 00:39:00.643491 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3293 00:39:00.647005 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3294 00:39:00.650231 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3295 00:39:00.650340
3296 00:39:00.650436
3297 00:39:00.650525 ==
3298 00:39:00.653477 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 00:39:00.660512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 00:39:00.660608 ==
3301 00:39:00.660675
3302 00:39:00.660735
3303 00:39:00.660794 TX Vref Scan disable
3304 00:39:00.664030 == TX Byte 0 ==
3305 00:39:00.667134 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3306 00:39:00.674139 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3307 00:39:00.674229 == TX Byte 1 ==
3308 00:39:00.677422 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3309 00:39:00.680762 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3310 00:39:00.683861 ==
3311 00:39:00.686978 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 00:39:00.690203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 00:39:00.690285 ==
3314 00:39:00.701917 TX Vref=22, minBit 8, minWin=24, winSum=408
3315 00:39:00.705461 TX Vref=24, minBit 8, minWin=25, winSum=413
3316 00:39:00.708365 TX Vref=26, minBit 9, minWin=25, winSum=420
3317 00:39:00.711786 TX Vref=28, minBit 9, minWin=25, winSum=424
3318 00:39:00.715409 TX Vref=30, minBit 9, minWin=25, winSum=424
3319 00:39:00.718691 TX Vref=32, minBit 9, minWin=25, winSum=423
3320 00:39:00.724857 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
3321 00:39:00.724980
3322 00:39:00.728262 Final TX Range 1 Vref 28
3323 00:39:00.728340
3324 00:39:00.728403 ==
3325 00:39:00.731711 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 00:39:00.735380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 00:39:00.735465 ==
3328 00:39:00.735529
3329 00:39:00.738139
3330 00:39:00.738222 TX Vref Scan disable
3331 00:39:00.741455 == TX Byte 0 ==
3332 00:39:00.744946 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3333 00:39:00.748286 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3334 00:39:00.751610 == TX Byte 1 ==
3335 00:39:00.755212 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3336 00:39:00.758419 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3337 00:39:00.758503
3338 00:39:00.761582 [DATLAT]
3339 00:39:00.761705 Freq=1200, CH1 RK0
3340 00:39:00.761801
3341 00:39:00.764908 DATLAT Default: 0xd
3342 00:39:00.764987 0, 0xFFFF, sum = 0
3343 00:39:00.768485 1, 0xFFFF, sum = 0
3344 00:39:00.768607 2, 0xFFFF, sum = 0
3345 00:39:00.771393 3, 0xFFFF, sum = 0
3346 00:39:00.771478 4, 0xFFFF, sum = 0
3347 00:39:00.774956 5, 0xFFFF, sum = 0
3348 00:39:00.775042 6, 0xFFFF, sum = 0
3349 00:39:00.778583 7, 0xFFFF, sum = 0
3350 00:39:00.778669 8, 0xFFFF, sum = 0
3351 00:39:00.782028 9, 0xFFFF, sum = 0
3352 00:39:00.785012 10, 0xFFFF, sum = 0
3353 00:39:00.785094 11, 0xFFFF, sum = 0
3354 00:39:00.788193 12, 0x0, sum = 1
3355 00:39:00.788271 13, 0x0, sum = 2
3356 00:39:00.788354 14, 0x0, sum = 3
3357 00:39:00.791518 15, 0x0, sum = 4
3358 00:39:00.791632 best_step = 13
3359 00:39:00.791726
3360 00:39:00.795127 ==
3361 00:39:00.795234 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 00:39:00.801623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 00:39:00.801714 ==
3364 00:39:00.801794 RX Vref Scan: 1
3365 00:39:00.801861
3366 00:39:00.805186 Set Vref Range= 32 -> 127
3367 00:39:00.805265
3368 00:39:00.808511 RX Vref 32 -> 127, step: 1
3369 00:39:00.808620
3370 00:39:00.812099 RX Delay -21 -> 252, step: 4
3371 00:39:00.812176
3372 00:39:00.815470 Set Vref, RX VrefLevel [Byte0]: 32
3373 00:39:00.818318 [Byte1]: 32
3374 00:39:00.818425
3375 00:39:00.821593 Set Vref, RX VrefLevel [Byte0]: 33
3376 00:39:00.825017 [Byte1]: 33
3377 00:39:00.825098
3378 00:39:00.828405 Set Vref, RX VrefLevel [Byte0]: 34
3379 00:39:00.831939 [Byte1]: 34
3380 00:39:00.835959
3381 00:39:00.836085 Set Vref, RX VrefLevel [Byte0]: 35
3382 00:39:00.838853 [Byte1]: 35
3383 00:39:00.843461
3384 00:39:00.843552 Set Vref, RX VrefLevel [Byte0]: 36
3385 00:39:00.847005 [Byte1]: 36
3386 00:39:00.851670
3387 00:39:00.851777 Set Vref, RX VrefLevel [Byte0]: 37
3388 00:39:00.854982 [Byte1]: 37
3389 00:39:00.859648
3390 00:39:00.859752 Set Vref, RX VrefLevel [Byte0]: 38
3391 00:39:00.862629 [Byte1]: 38
3392 00:39:00.867500
3393 00:39:00.867615 Set Vref, RX VrefLevel [Byte0]: 39
3394 00:39:00.870902 [Byte1]: 39
3395 00:39:00.875414
3396 00:39:00.875523 Set Vref, RX VrefLevel [Byte0]: 40
3397 00:39:00.878520 [Byte1]: 40
3398 00:39:00.883172
3399 00:39:00.883250 Set Vref, RX VrefLevel [Byte0]: 41
3400 00:39:00.886567 [Byte1]: 41
3401 00:39:00.891152
3402 00:39:00.891262 Set Vref, RX VrefLevel [Byte0]: 42
3403 00:39:00.894574 [Byte1]: 42
3404 00:39:00.899082
3405 00:39:00.899166 Set Vref, RX VrefLevel [Byte0]: 43
3406 00:39:00.902249 [Byte1]: 43
3407 00:39:00.906986
3408 00:39:00.907069 Set Vref, RX VrefLevel [Byte0]: 44
3409 00:39:00.910241 [Byte1]: 44
3410 00:39:00.915436
3411 00:39:00.915534 Set Vref, RX VrefLevel [Byte0]: 45
3412 00:39:00.918154 [Byte1]: 45
3413 00:39:00.922960
3414 00:39:00.923039 Set Vref, RX VrefLevel [Byte0]: 46
3415 00:39:00.926095 [Byte1]: 46
3416 00:39:00.930663
3417 00:39:00.930762 Set Vref, RX VrefLevel [Byte0]: 47
3418 00:39:00.934084 [Byte1]: 47
3419 00:39:00.938859
3420 00:39:00.938944 Set Vref, RX VrefLevel [Byte0]: 48
3421 00:39:00.942180 [Byte1]: 48
3422 00:39:00.946853
3423 00:39:00.946936 Set Vref, RX VrefLevel [Byte0]: 49
3424 00:39:00.950162 [Byte1]: 49
3425 00:39:00.954936
3426 00:39:00.955019 Set Vref, RX VrefLevel [Byte0]: 50
3427 00:39:00.957753 [Byte1]: 50
3428 00:39:00.962423
3429 00:39:00.962535 Set Vref, RX VrefLevel [Byte0]: 51
3430 00:39:00.965943 [Byte1]: 51
3431 00:39:00.970216
3432 00:39:00.970306 Set Vref, RX VrefLevel [Byte0]: 52
3433 00:39:00.973768 [Byte1]: 52
3434 00:39:00.978037
3435 00:39:00.978121 Set Vref, RX VrefLevel [Byte0]: 53
3436 00:39:00.981478 [Byte1]: 53
3437 00:39:00.986404
3438 00:39:00.986515 Set Vref, RX VrefLevel [Byte0]: 54
3439 00:39:00.989731 [Byte1]: 54
3440 00:39:00.994080
3441 00:39:00.994187 Set Vref, RX VrefLevel [Byte0]: 55
3442 00:39:00.997552 [Byte1]: 55
3443 00:39:01.002261
3444 00:39:01.002343 Set Vref, RX VrefLevel [Byte0]: 56
3445 00:39:01.005077 [Byte1]: 56
3446 00:39:01.010101
3447 00:39:01.010182 Set Vref, RX VrefLevel [Byte0]: 57
3448 00:39:01.013221 [Byte1]: 57
3449 00:39:01.017930
3450 00:39:01.018013 Set Vref, RX VrefLevel [Byte0]: 58
3451 00:39:01.021143 [Byte1]: 58
3452 00:39:01.025694
3453 00:39:01.025773 Set Vref, RX VrefLevel [Byte0]: 59
3454 00:39:01.029020 [Byte1]: 59
3455 00:39:01.033582
3456 00:39:01.033661 Set Vref, RX VrefLevel [Byte0]: 60
3457 00:39:01.037081 [Byte1]: 60
3458 00:39:01.041480
3459 00:39:01.041568 Set Vref, RX VrefLevel [Byte0]: 61
3460 00:39:01.044921 [Byte1]: 61
3461 00:39:01.049607
3462 00:39:01.049684 Set Vref, RX VrefLevel [Byte0]: 62
3463 00:39:01.053049 [Byte1]: 62
3464 00:39:01.057656
3465 00:39:01.057732 Set Vref, RX VrefLevel [Byte0]: 63
3466 00:39:01.061055 [Byte1]: 63
3467 00:39:01.065652
3468 00:39:01.065733 Set Vref, RX VrefLevel [Byte0]: 64
3469 00:39:01.068509 [Byte1]: 64
3470 00:39:01.073452
3471 00:39:01.073533 Set Vref, RX VrefLevel [Byte0]: 65
3472 00:39:01.076882 [Byte1]: 65
3473 00:39:01.081552
3474 00:39:01.081643 Set Vref, RX VrefLevel [Byte0]: 66
3475 00:39:01.084325 [Byte1]: 66
3476 00:39:01.089289
3477 00:39:01.089369 Set Vref, RX VrefLevel [Byte0]: 67
3478 00:39:01.092283 [Byte1]: 67
3479 00:39:01.096937
3480 00:39:01.097023 Set Vref, RX VrefLevel [Byte0]: 68
3481 00:39:01.100457 [Byte1]: 68
3482 00:39:01.104868
3483 00:39:01.104952 Set Vref, RX VrefLevel [Byte0]: 69
3484 00:39:01.108250 [Byte1]: 69
3485 00:39:01.113202
3486 00:39:01.113280 Set Vref, RX VrefLevel [Byte0]: 70
3487 00:39:01.116435 [Byte1]: 70
3488 00:39:01.121031
3489 00:39:01.121109 Final RX Vref Byte 0 = 56 to rank0
3490 00:39:01.124210 Final RX Vref Byte 1 = 52 to rank0
3491 00:39:01.127707 Final RX Vref Byte 0 = 56 to rank1
3492 00:39:01.130764 Final RX Vref Byte 1 = 52 to rank1==
3493 00:39:01.134143 Dram Type= 6, Freq= 0, CH_1, rank 0
3494 00:39:01.140891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 00:39:01.140978 ==
3496 00:39:01.141043 DQS Delay:
3497 00:39:01.141102 DQS0 = 0, DQS1 = 0
3498 00:39:01.144114 DQM Delay:
3499 00:39:01.144225 DQM0 = 114, DQM1 = 105
3500 00:39:01.147373 DQ Delay:
3501 00:39:01.150836 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3502 00:39:01.154314 DQ4 =112, DQ5 =120, DQ6 =128, DQ7 =112
3503 00:39:01.157708 DQ8 =94, DQ9 =96, DQ10 =104, DQ11 =100
3504 00:39:01.160661 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =112
3505 00:39:01.160744
3506 00:39:01.160809
3507 00:39:01.167574 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3508 00:39:01.171299 CH1 RK0: MR19=303, MR18=EEF5
3509 00:39:01.177768 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3510 00:39:01.177851
3511 00:39:01.180553 ----->DramcWriteLeveling(PI) begin...
3512 00:39:01.180638 ==
3513 00:39:01.184274 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 00:39:01.187682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 00:39:01.190647 ==
3516 00:39:01.190757 Write leveling (Byte 0): 23 => 23
3517 00:39:01.194012 Write leveling (Byte 1): 27 => 27
3518 00:39:01.197773 DramcWriteLeveling(PI) end<-----
3519 00:39:01.197877
3520 00:39:01.197971 ==
3521 00:39:01.201030 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 00:39:01.207386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 00:39:01.207471 ==
3524 00:39:01.207536 [Gating] SW mode calibration
3525 00:39:01.217719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3526 00:39:01.221021 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3527 00:39:01.224548 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3528 00:39:01.231011 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 00:39:01.234273 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 00:39:01.237556 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 00:39:01.244473 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 00:39:01.247608 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3533 00:39:01.251060 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
3534 00:39:01.257486 0 15 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
3535 00:39:01.260659 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 00:39:01.264180 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 00:39:01.270679 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 00:39:01.274013 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 00:39:01.277576 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 00:39:01.284230 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3541 00:39:01.287136 1 0 24 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
3542 00:39:01.290586 1 0 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3543 00:39:01.297041 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 00:39:01.300333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 00:39:01.303763 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 00:39:01.310719 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 00:39:01.313975 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 00:39:01.316929 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3549 00:39:01.324257 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3550 00:39:01.327066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3551 00:39:01.330491 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 00:39:01.337078 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 00:39:01.340234 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 00:39:01.343623 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 00:39:01.347215 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 00:39:01.354110 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 00:39:01.357013 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 00:39:01.360257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 00:39:01.366904 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 00:39:01.370179 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 00:39:01.373789 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 00:39:01.379941 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 00:39:01.383446 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 00:39:01.386656 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 00:39:01.393167 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3566 00:39:01.396498 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 00:39:01.400127 Total UI for P1: 0, mck2ui 16
3568 00:39:01.403501 best dqsien dly found for B0: ( 1, 3, 24)
3569 00:39:01.406858 Total UI for P1: 0, mck2ui 16
3570 00:39:01.410224 best dqsien dly found for B1: ( 1, 3, 24)
3571 00:39:01.413484 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3572 00:39:01.417040 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3573 00:39:01.417123
3574 00:39:01.419876 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3575 00:39:01.423381 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3576 00:39:01.426897 [Gating] SW calibration Done
3577 00:39:01.426980 ==
3578 00:39:01.430127 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 00:39:01.436244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 00:39:01.436330 ==
3581 00:39:01.436395 RX Vref Scan: 0
3582 00:39:01.436456
3583 00:39:01.439602 RX Vref 0 -> 0, step: 1
3584 00:39:01.439685
3585 00:39:01.443058 RX Delay -40 -> 252, step: 8
3586 00:39:01.446245 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3587 00:39:01.449972 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3588 00:39:01.452908 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3589 00:39:01.456444 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3590 00:39:01.463188 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3591 00:39:01.466663 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3592 00:39:01.469410 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3593 00:39:01.472712 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3594 00:39:01.476103 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3595 00:39:01.483036 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3596 00:39:01.486072 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3597 00:39:01.489697 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3598 00:39:01.492738 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3599 00:39:01.496273 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3600 00:39:01.503094 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3601 00:39:01.506422 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3602 00:39:01.506547 ==
3603 00:39:01.509565 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 00:39:01.512947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 00:39:01.513075 ==
3606 00:39:01.516386 DQS Delay:
3607 00:39:01.516514 DQS0 = 0, DQS1 = 0
3608 00:39:01.516632 DQM Delay:
3609 00:39:01.519188 DQM0 = 110, DQM1 = 108
3610 00:39:01.519315 DQ Delay:
3611 00:39:01.522596 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3612 00:39:01.525965 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3613 00:39:01.529355 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3614 00:39:01.535641 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =115
3615 00:39:01.535749
3616 00:39:01.535823
3617 00:39:01.535885 ==
3618 00:39:01.539013 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 00:39:01.542471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 00:39:01.542576 ==
3621 00:39:01.542669
3622 00:39:01.542760
3623 00:39:01.545910 TX Vref Scan disable
3624 00:39:01.546010 == TX Byte 0 ==
3625 00:39:01.552127 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3626 00:39:01.555655 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3627 00:39:01.555755 == TX Byte 1 ==
3628 00:39:01.562353 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3629 00:39:01.565396 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3630 00:39:01.565499 ==
3631 00:39:01.568641 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 00:39:01.571969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 00:39:01.572079 ==
3634 00:39:01.585608 TX Vref=22, minBit 0, minWin=25, winSum=418
3635 00:39:01.588900 TX Vref=24, minBit 3, minWin=25, winSum=422
3636 00:39:01.591909 TX Vref=26, minBit 0, minWin=25, winSum=426
3637 00:39:01.595310 TX Vref=28, minBit 8, minWin=26, winSum=433
3638 00:39:01.598942 TX Vref=30, minBit 1, minWin=26, winSum=431
3639 00:39:01.602491 TX Vref=32, minBit 8, minWin=26, winSum=430
3640 00:39:01.608665 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
3641 00:39:01.608798
3642 00:39:01.612283 Final TX Range 1 Vref 28
3643 00:39:01.612412
3644 00:39:01.612528 ==
3645 00:39:01.615377 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 00:39:01.618878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 00:39:01.619003 ==
3648 00:39:01.619117
3649 00:39:01.622222
3650 00:39:01.622347 TX Vref Scan disable
3651 00:39:01.625571 == TX Byte 0 ==
3652 00:39:01.628843 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3653 00:39:01.632297 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3654 00:39:01.635161 == TX Byte 1 ==
3655 00:39:01.639094 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3656 00:39:01.641972 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3657 00:39:01.642101
3658 00:39:01.645287 [DATLAT]
3659 00:39:01.645410 Freq=1200, CH1 RK1
3660 00:39:01.645525
3661 00:39:01.648650 DATLAT Default: 0xd
3662 00:39:01.648773 0, 0xFFFF, sum = 0
3663 00:39:01.652195 1, 0xFFFF, sum = 0
3664 00:39:01.652322 2, 0xFFFF, sum = 0
3665 00:39:01.655434 3, 0xFFFF, sum = 0
3666 00:39:01.655557 4, 0xFFFF, sum = 0
3667 00:39:01.659062 5, 0xFFFF, sum = 0
3668 00:39:01.659192 6, 0xFFFF, sum = 0
3669 00:39:01.662408 7, 0xFFFF, sum = 0
3670 00:39:01.665444 8, 0xFFFF, sum = 0
3671 00:39:01.665552 9, 0xFFFF, sum = 0
3672 00:39:01.668846 10, 0xFFFF, sum = 0
3673 00:39:01.668929 11, 0xFFFF, sum = 0
3674 00:39:01.671765 12, 0x0, sum = 1
3675 00:39:01.671895 13, 0x0, sum = 2
3676 00:39:01.675114 14, 0x0, sum = 3
3677 00:39:01.675236 15, 0x0, sum = 4
3678 00:39:01.675355 best_step = 13
3679 00:39:01.678485
3680 00:39:01.678606 ==
3681 00:39:01.682005 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 00:39:01.685022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 00:39:01.685144 ==
3684 00:39:01.685259 RX Vref Scan: 0
3685 00:39:01.685372
3686 00:39:01.688304 RX Vref 0 -> 0, step: 1
3687 00:39:01.688425
3688 00:39:01.691829 RX Delay -21 -> 252, step: 4
3689 00:39:01.695471 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3690 00:39:01.701838 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3691 00:39:01.704869 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3692 00:39:01.708319 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3693 00:39:01.711883 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3694 00:39:01.714880 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3695 00:39:01.721528 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3696 00:39:01.724791 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3697 00:39:01.728250 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3698 00:39:01.731516 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3699 00:39:01.734951 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3700 00:39:01.741372 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3701 00:39:01.744751 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3702 00:39:01.748024 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3703 00:39:01.751428 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3704 00:39:01.758289 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3705 00:39:01.758417 ==
3706 00:39:01.761169 Dram Type= 6, Freq= 0, CH_1, rank 1
3707 00:39:01.764572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3708 00:39:01.764696 ==
3709 00:39:01.764811 DQS Delay:
3710 00:39:01.768153 DQS0 = 0, DQS1 = 0
3711 00:39:01.768257 DQM Delay:
3712 00:39:01.771161 DQM0 = 111, DQM1 = 109
3713 00:39:01.771289 DQ Delay:
3714 00:39:01.774370 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3715 00:39:01.777688 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3716 00:39:01.781267 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3717 00:39:01.784469 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3718 00:39:01.784548
3719 00:39:01.784660
3720 00:39:01.794788 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3721 00:39:01.797672 CH1 RK1: MR19=304, MR18=F808
3722 00:39:01.801157 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3723 00:39:01.804603 [RxdqsGatingPostProcess] freq 1200
3724 00:39:01.811013 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3725 00:39:01.814082 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 00:39:01.817548 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 00:39:01.820831 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 00:39:01.823988 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 00:39:01.827534 best DQS0 dly(2T, 0.5T) = (0, 11)
3730 00:39:01.830911 best DQS1 dly(2T, 0.5T) = (0, 11)
3731 00:39:01.834036 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3732 00:39:01.837452 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3733 00:39:01.840703 Pre-setting of DQS Precalculation
3734 00:39:01.843981 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3735 00:39:01.850481 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3736 00:39:01.857722 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3737 00:39:01.860495
3738 00:39:01.860632
3739 00:39:01.860749 [Calibration Summary] 2400 Mbps
3740 00:39:01.863922 CH 0, Rank 0
3741 00:39:01.864040 SW Impedance : PASS
3742 00:39:01.867464 DUTY Scan : NO K
3743 00:39:01.870393 ZQ Calibration : PASS
3744 00:39:01.870524 Jitter Meter : NO K
3745 00:39:01.873892 CBT Training : PASS
3746 00:39:01.877358 Write leveling : PASS
3747 00:39:01.877484 RX DQS gating : PASS
3748 00:39:01.880477 RX DQ/DQS(RDDQC) : PASS
3749 00:39:01.883551 TX DQ/DQS : PASS
3750 00:39:01.883679 RX DATLAT : PASS
3751 00:39:01.887103 RX DQ/DQS(Engine): PASS
3752 00:39:01.890591 TX OE : NO K
3753 00:39:01.890692 All Pass.
3754 00:39:01.890784
3755 00:39:01.890875 CH 0, Rank 1
3756 00:39:01.893913 SW Impedance : PASS
3757 00:39:01.896703 DUTY Scan : NO K
3758 00:39:01.896790 ZQ Calibration : PASS
3759 00:39:01.900146 Jitter Meter : NO K
3760 00:39:01.903693 CBT Training : PASS
3761 00:39:01.903785 Write leveling : PASS
3762 00:39:01.907317 RX DQS gating : PASS
3763 00:39:01.910211 RX DQ/DQS(RDDQC) : PASS
3764 00:39:01.910291 TX DQ/DQS : PASS
3765 00:39:01.913683 RX DATLAT : PASS
3766 00:39:01.913762 RX DQ/DQS(Engine): PASS
3767 00:39:01.917160 TX OE : NO K
3768 00:39:01.917241 All Pass.
3769 00:39:01.917329
3770 00:39:01.919909 CH 1, Rank 0
3771 00:39:01.919989 SW Impedance : PASS
3772 00:39:01.923766 DUTY Scan : NO K
3773 00:39:01.926964 ZQ Calibration : PASS
3774 00:39:01.927043 Jitter Meter : NO K
3775 00:39:01.930217 CBT Training : PASS
3776 00:39:01.933575 Write leveling : PASS
3777 00:39:01.933665 RX DQS gating : PASS
3778 00:39:01.936656 RX DQ/DQS(RDDQC) : PASS
3779 00:39:01.940354 TX DQ/DQS : PASS
3780 00:39:01.940437 RX DATLAT : PASS
3781 00:39:01.943432 RX DQ/DQS(Engine): PASS
3782 00:39:01.946688 TX OE : NO K
3783 00:39:01.946771 All Pass.
3784 00:39:01.946854
3785 00:39:01.946935 CH 1, Rank 1
3786 00:39:01.949890 SW Impedance : PASS
3787 00:39:01.953432 DUTY Scan : NO K
3788 00:39:01.953514 ZQ Calibration : PASS
3789 00:39:01.956801 Jitter Meter : NO K
3790 00:39:01.960147 CBT Training : PASS
3791 00:39:01.960257 Write leveling : PASS
3792 00:39:01.963436 RX DQS gating : PASS
3793 00:39:01.966483 RX DQ/DQS(RDDQC) : PASS
3794 00:39:01.966568 TX DQ/DQS : PASS
3795 00:39:01.969983 RX DATLAT : PASS
3796 00:39:01.970068 RX DQ/DQS(Engine): PASS
3797 00:39:01.973401 TX OE : NO K
3798 00:39:01.973480 All Pass.
3799 00:39:01.973568
3800 00:39:01.976881 DramC Write-DBI off
3801 00:39:01.980247 PER_BANK_REFRESH: Hybrid Mode
3802 00:39:01.980322 TX_TRACKING: ON
3803 00:39:01.990272 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3804 00:39:01.993435 [FAST_K] Save calibration result to emmc
3805 00:39:01.996762 dramc_set_vcore_voltage set vcore to 650000
3806 00:39:02.000246 Read voltage for 600, 5
3807 00:39:02.000325 Vio18 = 0
3808 00:39:02.000390 Vcore = 650000
3809 00:39:02.003145 Vdram = 0
3810 00:39:02.003223 Vddq = 0
3811 00:39:02.003292 Vmddr = 0
3812 00:39:02.010037 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3813 00:39:02.012897 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3814 00:39:02.016354 MEM_TYPE=3, freq_sel=19
3815 00:39:02.019956 sv_algorithm_assistance_LP4_1600
3816 00:39:02.022819 ============ PULL DRAM RESETB DOWN ============
3817 00:39:02.029751 ========== PULL DRAM RESETB DOWN end =========
3818 00:39:02.033004 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3819 00:39:02.036225 ===================================
3820 00:39:02.039494 LPDDR4 DRAM CONFIGURATION
3821 00:39:02.042872 ===================================
3822 00:39:02.042951 EX_ROW_EN[0] = 0x0
3823 00:39:02.046370 EX_ROW_EN[1] = 0x0
3824 00:39:02.046456 LP4Y_EN = 0x0
3825 00:39:02.049419 WORK_FSP = 0x0
3826 00:39:02.049501 WL = 0x2
3827 00:39:02.052730 RL = 0x2
3828 00:39:02.052809 BL = 0x2
3829 00:39:02.055867 RPST = 0x0
3830 00:39:02.059571 RD_PRE = 0x0
3831 00:39:02.059661 WR_PRE = 0x1
3832 00:39:02.062774 WR_PST = 0x0
3833 00:39:02.062888 DBI_WR = 0x0
3834 00:39:02.065976 DBI_RD = 0x0
3835 00:39:02.066054 OTF = 0x1
3836 00:39:02.069261 ===================================
3837 00:39:02.073085 ===================================
3838 00:39:02.073171 ANA top config
3839 00:39:02.076039 ===================================
3840 00:39:02.079446 DLL_ASYNC_EN = 0
3841 00:39:02.082857 ALL_SLAVE_EN = 1
3842 00:39:02.085784 NEW_RANK_MODE = 1
3843 00:39:02.089207 DLL_IDLE_MODE = 1
3844 00:39:02.089314 LP45_APHY_COMB_EN = 1
3845 00:39:02.092708 TX_ODT_DIS = 1
3846 00:39:02.095941 NEW_8X_MODE = 1
3847 00:39:02.099426 ===================================
3848 00:39:02.102554 ===================================
3849 00:39:02.105783 data_rate = 1200
3850 00:39:02.109289 CKR = 1
3851 00:39:02.112354 DQ_P2S_RATIO = 8
3852 00:39:02.115780 ===================================
3853 00:39:02.115860 CA_P2S_RATIO = 8
3854 00:39:02.119176 DQ_CA_OPEN = 0
3855 00:39:02.122703 DQ_SEMI_OPEN = 0
3856 00:39:02.126033 CA_SEMI_OPEN = 0
3857 00:39:02.129101 CA_FULL_RATE = 0
3858 00:39:02.129215 DQ_CKDIV4_EN = 1
3859 00:39:02.132383 CA_CKDIV4_EN = 1
3860 00:39:02.135853 CA_PREDIV_EN = 0
3861 00:39:02.139243 PH8_DLY = 0
3862 00:39:02.142105 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3863 00:39:02.145429 DQ_AAMCK_DIV = 4
3864 00:39:02.145511 CA_AAMCK_DIV = 4
3865 00:39:02.148986 CA_ADMCK_DIV = 4
3866 00:39:02.152174 DQ_TRACK_CA_EN = 0
3867 00:39:02.155175 CA_PICK = 600
3868 00:39:02.158641 CA_MCKIO = 600
3869 00:39:02.162052 MCKIO_SEMI = 0
3870 00:39:02.165241 PLL_FREQ = 2288
3871 00:39:02.168578 DQ_UI_PI_RATIO = 32
3872 00:39:02.168689 CA_UI_PI_RATIO = 0
3873 00:39:02.172307 ===================================
3874 00:39:02.175594 ===================================
3875 00:39:02.178634 memory_type:LPDDR4
3876 00:39:02.182191 GP_NUM : 10
3877 00:39:02.182277 SRAM_EN : 1
3878 00:39:02.185567 MD32_EN : 0
3879 00:39:02.188378 ===================================
3880 00:39:02.191832 [ANA_INIT] >>>>>>>>>>>>>>
3881 00:39:02.191911 <<<<<< [CONFIGURE PHASE]: ANA_TX
3882 00:39:02.198803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3883 00:39:02.202224 ===================================
3884 00:39:02.202344 data_rate = 1200,PCW = 0X5800
3885 00:39:02.205415 ===================================
3886 00:39:02.208442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3887 00:39:02.214952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3888 00:39:02.222030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3889 00:39:02.224876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3890 00:39:02.228495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3891 00:39:02.231820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3892 00:39:02.234789 [ANA_INIT] flow start
3893 00:39:02.234867 [ANA_INIT] PLL >>>>>>>>
3894 00:39:02.238347 [ANA_INIT] PLL <<<<<<<<
3895 00:39:02.241731 [ANA_INIT] MIDPI >>>>>>>>
3896 00:39:02.245138 [ANA_INIT] MIDPI <<<<<<<<
3897 00:39:02.245212 [ANA_INIT] DLL >>>>>>>>
3898 00:39:02.248554 [ANA_INIT] flow end
3899 00:39:02.251378 ============ LP4 DIFF to SE enter ============
3900 00:39:02.255182 ============ LP4 DIFF to SE exit ============
3901 00:39:02.258538 [ANA_INIT] <<<<<<<<<<<<<
3902 00:39:02.261750 [Flow] Enable top DCM control >>>>>
3903 00:39:02.264842 [Flow] Enable top DCM control <<<<<
3904 00:39:02.268323 Enable DLL master slave shuffle
3905 00:39:02.275109 ==============================================================
3906 00:39:02.275223 Gating Mode config
3907 00:39:02.281699 ==============================================================
3908 00:39:02.281785 Config description:
3909 00:39:02.291417 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3910 00:39:02.297719 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3911 00:39:02.304691 SELPH_MODE 0: By rank 1: By Phase
3912 00:39:02.307697 ==============================================================
3913 00:39:02.310927 GAT_TRACK_EN = 1
3914 00:39:02.314431 RX_GATING_MODE = 2
3915 00:39:02.318054 RX_GATING_TRACK_MODE = 2
3916 00:39:02.321165 SELPH_MODE = 1
3917 00:39:02.324573 PICG_EARLY_EN = 1
3918 00:39:02.328067 VALID_LAT_VALUE = 1
3919 00:39:02.334565 ==============================================================
3920 00:39:02.337944 Enter into Gating configuration >>>>
3921 00:39:02.340890 Exit from Gating configuration <<<<
3922 00:39:02.340971 Enter into DVFS_PRE_config >>>>>
3923 00:39:02.354332 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3924 00:39:02.357642 Exit from DVFS_PRE_config <<<<<
3925 00:39:02.360950 Enter into PICG configuration >>>>
3926 00:39:02.364387 Exit from PICG configuration <<<<
3927 00:39:02.364505 [RX_INPUT] configuration >>>>>
3928 00:39:02.367408 [RX_INPUT] configuration <<<<<
3929 00:39:02.374083 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3930 00:39:02.380468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3931 00:39:02.384117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 00:39:02.390874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 00:39:02.397636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3934 00:39:02.403547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3935 00:39:02.407409 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3936 00:39:02.410454 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3937 00:39:02.416753 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3938 00:39:02.420476 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3939 00:39:02.423600 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3940 00:39:02.430022 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3941 00:39:02.433542 ===================================
3942 00:39:02.433674 LPDDR4 DRAM CONFIGURATION
3943 00:39:02.436814 ===================================
3944 00:39:02.440255 EX_ROW_EN[0] = 0x0
3945 00:39:02.440377 EX_ROW_EN[1] = 0x0
3946 00:39:02.443122 LP4Y_EN = 0x0
3947 00:39:02.446596 WORK_FSP = 0x0
3948 00:39:02.446719 WL = 0x2
3949 00:39:02.449936 RL = 0x2
3950 00:39:02.450062 BL = 0x2
3951 00:39:02.453460 RPST = 0x0
3952 00:39:02.453590 RD_PRE = 0x0
3953 00:39:02.456804 WR_PRE = 0x1
3954 00:39:02.456929 WR_PST = 0x0
3955 00:39:02.460222 DBI_WR = 0x0
3956 00:39:02.460349 DBI_RD = 0x0
3957 00:39:02.463021 OTF = 0x1
3958 00:39:02.466793 ===================================
3959 00:39:02.469970 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3960 00:39:02.473159 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3961 00:39:02.479592 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 00:39:02.482952 ===================================
3963 00:39:02.483076 LPDDR4 DRAM CONFIGURATION
3964 00:39:02.486642 ===================================
3965 00:39:02.490191 EX_ROW_EN[0] = 0x10
3966 00:39:02.490321 EX_ROW_EN[1] = 0x0
3967 00:39:02.493131 LP4Y_EN = 0x0
3968 00:39:02.493264 WORK_FSP = 0x0
3969 00:39:02.496270 WL = 0x2
3970 00:39:02.496399 RL = 0x2
3971 00:39:02.499622 BL = 0x2
3972 00:39:02.503140 RPST = 0x0
3973 00:39:02.503272 RD_PRE = 0x0
3974 00:39:02.506553 WR_PRE = 0x1
3975 00:39:02.506675 WR_PST = 0x0
3976 00:39:02.509922 DBI_WR = 0x0
3977 00:39:02.510028 DBI_RD = 0x0
3978 00:39:02.513263 OTF = 0x1
3979 00:39:02.516664 ===================================
3980 00:39:02.519501 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3981 00:39:02.525195 nWR fixed to 30
3982 00:39:02.528432 [ModeRegInit_LP4] CH0 RK0
3983 00:39:02.528535 [ModeRegInit_LP4] CH0 RK1
3984 00:39:02.531507 [ModeRegInit_LP4] CH1 RK0
3985 00:39:02.535463 [ModeRegInit_LP4] CH1 RK1
3986 00:39:02.535541 match AC timing 17
3987 00:39:02.541613 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3988 00:39:02.545033 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3989 00:39:02.548371 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3990 00:39:02.554831 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3991 00:39:02.558346 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3992 00:39:02.558425 ==
3993 00:39:02.561250 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 00:39:02.564878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 00:39:02.564964 ==
3996 00:39:02.571452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 00:39:02.577831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3998 00:39:02.581316 [CA 0] Center 37 (7~67) winsize 61
3999 00:39:02.584804 [CA 1] Center 36 (6~66) winsize 61
4000 00:39:02.587679 [CA 2] Center 35 (5~65) winsize 61
4001 00:39:02.591428 [CA 3] Center 35 (5~65) winsize 61
4002 00:39:02.594290 [CA 4] Center 34 (4~65) winsize 62
4003 00:39:02.598104 [CA 5] Center 34 (4~65) winsize 62
4004 00:39:02.598184
4005 00:39:02.601081 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4006 00:39:02.601197
4007 00:39:02.604501 [CATrainingPosCal] consider 1 rank data
4008 00:39:02.608090 u2DelayCellTimex100 = 270/100 ps
4009 00:39:02.610956 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4010 00:39:02.614286 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4011 00:39:02.617715 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4012 00:39:02.621058 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4013 00:39:02.628020 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4014 00:39:02.631122 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4015 00:39:02.631203
4016 00:39:02.634401 CA PerBit enable=1, Macro0, CA PI delay=34
4017 00:39:02.634499
4018 00:39:02.637477 [CBTSetCACLKResult] CA Dly = 34
4019 00:39:02.637594 CS Dly: 7 (0~38)
4020 00:39:02.637696 ==
4021 00:39:02.641005 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 00:39:02.648001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 00:39:02.648132 ==
4024 00:39:02.650704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4025 00:39:02.657644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4026 00:39:02.660546 [CA 0] Center 37 (7~67) winsize 61
4027 00:39:02.664070 [CA 1] Center 37 (7~67) winsize 61
4028 00:39:02.667482 [CA 2] Center 35 (5~65) winsize 61
4029 00:39:02.670380 [CA 3] Center 35 (5~65) winsize 61
4030 00:39:02.674255 [CA 4] Center 34 (4~65) winsize 62
4031 00:39:02.677108 [CA 5] Center 33 (3~64) winsize 62
4032 00:39:02.677194
4033 00:39:02.680441 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4034 00:39:02.680522
4035 00:39:02.684046 [CATrainingPosCal] consider 2 rank data
4036 00:39:02.687582 u2DelayCellTimex100 = 270/100 ps
4037 00:39:02.690455 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4038 00:39:02.693771 CA1 delay=36 (7~66),Diff = 2 PI (19 cell)
4039 00:39:02.700453 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4040 00:39:02.703945 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4041 00:39:02.706896 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4042 00:39:02.710597 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4043 00:39:02.710684
4044 00:39:02.713638 CA PerBit enable=1, Macro0, CA PI delay=34
4045 00:39:02.713722
4046 00:39:02.717297 [CBTSetCACLKResult] CA Dly = 34
4047 00:39:02.717384 CS Dly: 6 (0~36)
4048 00:39:02.717449
4049 00:39:02.720300 ----->DramcWriteLeveling(PI) begin...
4050 00:39:02.723722 ==
4051 00:39:02.727171 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 00:39:02.730507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 00:39:02.730594 ==
4054 00:39:02.733666 Write leveling (Byte 0): 32 => 32
4055 00:39:02.737323 Write leveling (Byte 1): 32 => 32
4056 00:39:02.740219 DramcWriteLeveling(PI) end<-----
4057 00:39:02.740335
4058 00:39:02.740438 ==
4059 00:39:02.743743 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 00:39:02.746722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 00:39:02.746805 ==
4062 00:39:02.750153 [Gating] SW mode calibration
4063 00:39:02.756615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4064 00:39:02.763515 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4065 00:39:02.766971 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 00:39:02.769977 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 00:39:02.776664 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 00:39:02.779999 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4069 00:39:02.783513 0 9 16 | B1->B0 | 3131 2a2a | 1 1 | (1 1) (1 0)
4070 00:39:02.786480 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 00:39:02.793422 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 00:39:02.796908 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 00:39:02.799698 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 00:39:02.806541 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 00:39:02.810154 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 00:39:02.813013 0 10 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4077 00:39:02.820041 0 10 16 | B1->B0 | 3333 3d3d | 0 1 | (1 1) (0 0)
4078 00:39:02.823167 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 00:39:02.826257 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 00:39:02.833011 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 00:39:02.836413 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 00:39:02.839911 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 00:39:02.846346 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 00:39:02.849677 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4085 00:39:02.852905 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4086 00:39:02.859383 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 00:39:02.862468 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 00:39:02.866055 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 00:39:02.872859 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 00:39:02.875857 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 00:39:02.879180 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 00:39:02.885981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 00:39:02.889399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 00:39:02.892262 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 00:39:02.899129 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 00:39:02.902526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 00:39:02.905770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 00:39:02.912568 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 00:39:02.915464 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 00:39:02.918921 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4101 00:39:02.922279 Total UI for P1: 0, mck2ui 16
4102 00:39:02.925717 best dqsien dly found for B0: ( 0, 13, 10)
4103 00:39:02.932409 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4104 00:39:02.935426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 00:39:02.938980 Total UI for P1: 0, mck2ui 16
4106 00:39:02.942135 best dqsien dly found for B1: ( 0, 13, 18)
4107 00:39:02.945687 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4108 00:39:02.949096 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4109 00:39:02.949222
4110 00:39:02.952285 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4111 00:39:02.955535 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4112 00:39:02.958826 [Gating] SW calibration Done
4113 00:39:02.958910 ==
4114 00:39:02.962269 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 00:39:02.965548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 00:39:02.968944 ==
4117 00:39:02.969054 RX Vref Scan: 0
4118 00:39:02.969147
4119 00:39:02.972095 RX Vref 0 -> 0, step: 1
4120 00:39:02.972180
4121 00:39:02.975320 RX Delay -230 -> 252, step: 16
4122 00:39:02.978465 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4123 00:39:02.982151 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4124 00:39:02.985296 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4125 00:39:02.992130 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4126 00:39:02.995036 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4127 00:39:02.998402 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4128 00:39:03.001992 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4129 00:39:03.005245 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4130 00:39:03.011856 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4131 00:39:03.015295 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4132 00:39:03.018222 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4133 00:39:03.021464 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4134 00:39:03.028446 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4135 00:39:03.031839 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4136 00:39:03.035229 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4137 00:39:03.038089 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4138 00:39:03.038214 ==
4139 00:39:03.041517 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 00:39:03.048014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 00:39:03.048139 ==
4142 00:39:03.048255 DQS Delay:
4143 00:39:03.051631 DQS0 = 0, DQS1 = 0
4144 00:39:03.051758 DQM Delay:
4145 00:39:03.055003 DQM0 = 38, DQM1 = 30
4146 00:39:03.055111 DQ Delay:
4147 00:39:03.058409 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =41
4148 00:39:03.061383 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4149 00:39:03.064586 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4150 00:39:03.068373 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4151 00:39:03.068486
4152 00:39:03.068585
4153 00:39:03.068649 ==
4154 00:39:03.071594 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 00:39:03.074473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 00:39:03.074607 ==
4157 00:39:03.074723
4158 00:39:03.074833
4159 00:39:03.077924 TX Vref Scan disable
4160 00:39:03.081286 == TX Byte 0 ==
4161 00:39:03.085237 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4162 00:39:03.088115 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4163 00:39:03.091095 == TX Byte 1 ==
4164 00:39:03.094595 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4165 00:39:03.097780 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4166 00:39:03.097911 ==
4167 00:39:03.101077 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 00:39:03.104515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 00:39:03.107901 ==
4170 00:39:03.108024
4171 00:39:03.108136
4172 00:39:03.108246 TX Vref Scan disable
4173 00:39:03.111799 == TX Byte 0 ==
4174 00:39:03.115070 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4175 00:39:03.121998 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4176 00:39:03.122125 == TX Byte 1 ==
4177 00:39:03.124815 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4178 00:39:03.132229 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4179 00:39:03.132362
4180 00:39:03.132473 [DATLAT]
4181 00:39:03.132588 Freq=600, CH0 RK0
4182 00:39:03.132699
4183 00:39:03.135207 DATLAT Default: 0x9
4184 00:39:03.135330 0, 0xFFFF, sum = 0
4185 00:39:03.138544 1, 0xFFFF, sum = 0
4186 00:39:03.138669 2, 0xFFFF, sum = 0
4187 00:39:03.142029 3, 0xFFFF, sum = 0
4188 00:39:03.142144 4, 0xFFFF, sum = 0
4189 00:39:03.144919 5, 0xFFFF, sum = 0
4190 00:39:03.148473 6, 0xFFFF, sum = 0
4191 00:39:03.148580 7, 0xFFFF, sum = 0
4192 00:39:03.148657 8, 0x0, sum = 1
4193 00:39:03.151726 9, 0x0, sum = 2
4194 00:39:03.151835 10, 0x0, sum = 3
4195 00:39:03.154760 11, 0x0, sum = 4
4196 00:39:03.154834 best_step = 9
4197 00:39:03.154896
4198 00:39:03.154954 ==
4199 00:39:03.158391 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 00:39:03.164727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 00:39:03.164857 ==
4202 00:39:03.164970 RX Vref Scan: 1
4203 00:39:03.165084
4204 00:39:03.168049 RX Vref 0 -> 0, step: 1
4205 00:39:03.168155
4206 00:39:03.171480 RX Delay -195 -> 252, step: 8
4207 00:39:03.171580
4208 00:39:03.175207 Set Vref, RX VrefLevel [Byte0]: 60
4209 00:39:03.178235 [Byte1]: 55
4210 00:39:03.178338
4211 00:39:03.181184 Final RX Vref Byte 0 = 60 to rank0
4212 00:39:03.184568 Final RX Vref Byte 1 = 55 to rank0
4213 00:39:03.188159 Final RX Vref Byte 0 = 60 to rank1
4214 00:39:03.191592 Final RX Vref Byte 1 = 55 to rank1==
4215 00:39:03.194769 Dram Type= 6, Freq= 0, CH_0, rank 0
4216 00:39:03.197995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 00:39:03.198118 ==
4218 00:39:03.201302 DQS Delay:
4219 00:39:03.201419 DQS0 = 0, DQS1 = 0
4220 00:39:03.204665 DQM Delay:
4221 00:39:03.204746 DQM0 = 34, DQM1 = 29
4222 00:39:03.204839 DQ Delay:
4223 00:39:03.207992 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4224 00:39:03.211570 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4225 00:39:03.214969 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4226 00:39:03.218200 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4227 00:39:03.218279
4228 00:39:03.218344
4229 00:39:03.227861 [DQSOSCAuto] RK0, (LSB)MR18= 0x403e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4230 00:39:03.231389 CH0 RK0: MR19=808, MR18=403E
4231 00:39:03.237724 CH0_RK0: MR19=0x808, MR18=0x403E, DQSOSC=397, MR23=63, INC=166, DEC=110
4232 00:39:03.237805
4233 00:39:03.241113 ----->DramcWriteLeveling(PI) begin...
4234 00:39:03.241220 ==
4235 00:39:03.244480 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 00:39:03.247485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 00:39:03.247582 ==
4238 00:39:03.250980 Write leveling (Byte 0): 33 => 33
4239 00:39:03.254372 Write leveling (Byte 1): 30 => 30
4240 00:39:03.257796 DramcWriteLeveling(PI) end<-----
4241 00:39:03.257901
4242 00:39:03.258000 ==
4243 00:39:03.261143 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 00:39:03.264240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 00:39:03.264321 ==
4246 00:39:03.267797 [Gating] SW mode calibration
4247 00:39:03.274368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4248 00:39:03.280690 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4249 00:39:03.284492 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 00:39:03.287410 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 00:39:03.294298 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 00:39:03.297121 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4253 00:39:03.300438 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
4254 00:39:03.307250 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 00:39:03.310578 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 00:39:03.313790 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 00:39:03.320473 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 00:39:03.324037 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 00:39:03.327097 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 00:39:03.333907 0 10 12 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
4261 00:39:03.337197 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
4262 00:39:03.340767 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 00:39:03.347046 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 00:39:03.350470 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 00:39:03.353507 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 00:39:03.360527 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 00:39:03.363318 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 00:39:03.366730 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4269 00:39:03.373467 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 00:39:03.376473 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 00:39:03.379720 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 00:39:03.386848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 00:39:03.389873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 00:39:03.393221 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 00:39:03.399496 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 00:39:03.402884 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 00:39:03.406269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 00:39:03.412841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 00:39:03.416305 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 00:39:03.419777 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 00:39:03.426233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 00:39:03.429361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 00:39:03.432608 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 00:39:03.439580 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4285 00:39:03.439678 Total UI for P1: 0, mck2ui 16
4286 00:39:03.442964 best dqsien dly found for B0: ( 0, 13, 10)
4287 00:39:03.449279 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4288 00:39:03.452847 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 00:39:03.455932 Total UI for P1: 0, mck2ui 16
4290 00:39:03.459316 best dqsien dly found for B1: ( 0, 13, 14)
4291 00:39:03.462783 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4292 00:39:03.466194 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4293 00:39:03.466304
4294 00:39:03.469572 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4295 00:39:03.476061 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4296 00:39:03.476169 [Gating] SW calibration Done
4297 00:39:03.476238 ==
4298 00:39:03.479299 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 00:39:03.486062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 00:39:03.486186 ==
4301 00:39:03.486317 RX Vref Scan: 0
4302 00:39:03.486429
4303 00:39:03.489102 RX Vref 0 -> 0, step: 1
4304 00:39:03.489236
4305 00:39:03.492485 RX Delay -230 -> 252, step: 16
4306 00:39:03.495593 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4307 00:39:03.499493 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4308 00:39:03.505831 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4309 00:39:03.508828 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4310 00:39:03.512194 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4311 00:39:03.516132 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4312 00:39:03.518990 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4313 00:39:03.525862 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4314 00:39:03.529201 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4315 00:39:03.532160 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4316 00:39:03.535789 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4317 00:39:03.542481 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4318 00:39:03.545703 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4319 00:39:03.548844 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4320 00:39:03.552413 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4321 00:39:03.558674 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4322 00:39:03.558759 ==
4323 00:39:03.562289 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 00:39:03.565698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 00:39:03.565783 ==
4326 00:39:03.565850 DQS Delay:
4327 00:39:03.568693 DQS0 = 0, DQS1 = 0
4328 00:39:03.568778 DQM Delay:
4329 00:39:03.572138 DQM0 = 36, DQM1 = 30
4330 00:39:03.572215 DQ Delay:
4331 00:39:03.575526 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4332 00:39:03.578382 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4333 00:39:03.581795 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4334 00:39:03.585266 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4335 00:39:03.585347
4336 00:39:03.585411
4337 00:39:03.585470 ==
4338 00:39:03.588612 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 00:39:03.591958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 00:39:03.592043 ==
4341 00:39:03.595057
4342 00:39:03.595133
4343 00:39:03.595208 TX Vref Scan disable
4344 00:39:03.598302 == TX Byte 0 ==
4345 00:39:03.601742 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4346 00:39:03.605297 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4347 00:39:03.608291 == TX Byte 1 ==
4348 00:39:03.611661 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4349 00:39:03.615206 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4350 00:39:03.618287 ==
4351 00:39:03.618406 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 00:39:03.624651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 00:39:03.624785 ==
4354 00:39:03.624914
4355 00:39:03.625021
4356 00:39:03.628048 TX Vref Scan disable
4357 00:39:03.628175 == TX Byte 0 ==
4358 00:39:03.634933 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4359 00:39:03.638384 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4360 00:39:03.638521 == TX Byte 1 ==
4361 00:39:03.644998 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4362 00:39:03.648042 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4363 00:39:03.648169
4364 00:39:03.648281 [DATLAT]
4365 00:39:03.651662 Freq=600, CH0 RK1
4366 00:39:03.651788
4367 00:39:03.651899 DATLAT Default: 0x9
4368 00:39:03.654982 0, 0xFFFF, sum = 0
4369 00:39:03.655117 1, 0xFFFF, sum = 0
4370 00:39:03.658005 2, 0xFFFF, sum = 0
4371 00:39:03.658132 3, 0xFFFF, sum = 0
4372 00:39:03.661278 4, 0xFFFF, sum = 0
4373 00:39:03.661408 5, 0xFFFF, sum = 0
4374 00:39:03.664795 6, 0xFFFF, sum = 0
4375 00:39:03.668262 7, 0xFFFF, sum = 0
4376 00:39:03.668347 8, 0x0, sum = 1
4377 00:39:03.668436 9, 0x0, sum = 2
4378 00:39:03.671561 10, 0x0, sum = 3
4379 00:39:03.671648 11, 0x0, sum = 4
4380 00:39:03.674539 best_step = 9
4381 00:39:03.674661
4382 00:39:03.674753 ==
4383 00:39:03.678118 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 00:39:03.681471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 00:39:03.681559 ==
4386 00:39:03.684379 RX Vref Scan: 0
4387 00:39:03.684497
4388 00:39:03.684624 RX Vref 0 -> 0, step: 1
4389 00:39:03.684745
4390 00:39:03.687917 RX Delay -195 -> 252, step: 8
4391 00:39:03.695287 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4392 00:39:03.698665 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4393 00:39:03.701960 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4394 00:39:03.705152 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4395 00:39:03.711928 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4396 00:39:03.715216 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4397 00:39:03.718341 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4398 00:39:03.721713 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4399 00:39:03.724838 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4400 00:39:03.731809 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4401 00:39:03.735077 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4402 00:39:03.738330 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4403 00:39:03.741708 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4404 00:39:03.748034 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4405 00:39:03.751424 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4406 00:39:03.754692 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4407 00:39:03.754776 ==
4408 00:39:03.758023 Dram Type= 6, Freq= 0, CH_0, rank 1
4409 00:39:03.764456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 00:39:03.764538 ==
4411 00:39:03.764611 DQS Delay:
4412 00:39:03.767756 DQS0 = 0, DQS1 = 0
4413 00:39:03.767834 DQM Delay:
4414 00:39:03.767897 DQM0 = 33, DQM1 = 28
4415 00:39:03.771181 DQ Delay:
4416 00:39:03.774546 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4417 00:39:03.778134 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4418 00:39:03.781013 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4419 00:39:03.784375 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4420 00:39:03.784484
4421 00:39:03.784581
4422 00:39:03.791311 [DQSOSCAuto] RK1, (LSB)MR18= 0x6838, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4423 00:39:03.794860 CH0 RK1: MR19=808, MR18=6838
4424 00:39:03.801179 CH0_RK1: MR19=0x808, MR18=0x6838, DQSOSC=390, MR23=63, INC=172, DEC=114
4425 00:39:03.804517 [RxdqsGatingPostProcess] freq 600
4426 00:39:03.807977 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4427 00:39:03.810784 Pre-setting of DQS Precalculation
4428 00:39:03.817517 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4429 00:39:03.817603 ==
4430 00:39:03.821126 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 00:39:03.824812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 00:39:03.824897 ==
4433 00:39:03.831353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4434 00:39:03.834286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4435 00:39:03.838979 [CA 0] Center 36 (6~66) winsize 61
4436 00:39:03.841971 [CA 1] Center 35 (5~66) winsize 62
4437 00:39:03.845740 [CA 2] Center 34 (4~65) winsize 62
4438 00:39:03.848575 [CA 3] Center 34 (4~65) winsize 62
4439 00:39:03.852257 [CA 4] Center 34 (4~65) winsize 62
4440 00:39:03.855646 [CA 5] Center 33 (3~64) winsize 62
4441 00:39:03.855730
4442 00:39:03.858526 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4443 00:39:03.858610
4444 00:39:03.862090 [CATrainingPosCal] consider 1 rank data
4445 00:39:03.865395 u2DelayCellTimex100 = 270/100 ps
4446 00:39:03.868631 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4447 00:39:03.875270 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4448 00:39:03.878767 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 00:39:03.881714 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 00:39:03.885116 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 00:39:03.888222 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4452 00:39:03.888335
4453 00:39:03.891650 CA PerBit enable=1, Macro0, CA PI delay=33
4454 00:39:03.891728
4455 00:39:03.895058 [CBTSetCACLKResult] CA Dly = 33
4456 00:39:03.895185 CS Dly: 4 (0~35)
4457 00:39:03.898550 ==
4458 00:39:03.901910 Dram Type= 6, Freq= 0, CH_1, rank 1
4459 00:39:03.904932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 00:39:03.905056 ==
4461 00:39:03.908259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4462 00:39:03.915134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4463 00:39:03.919210 [CA 0] Center 36 (6~66) winsize 61
4464 00:39:03.922319 [CA 1] Center 36 (6~66) winsize 61
4465 00:39:03.925529 [CA 2] Center 34 (4~65) winsize 62
4466 00:39:03.928977 [CA 3] Center 34 (3~65) winsize 63
4467 00:39:03.932186 [CA 4] Center 34 (4~65) winsize 62
4468 00:39:03.935557 [CA 5] Center 33 (3~64) winsize 62
4469 00:39:03.935646
4470 00:39:03.938606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4471 00:39:03.938691
4472 00:39:03.941994 [CATrainingPosCal] consider 2 rank data
4473 00:39:03.945182 u2DelayCellTimex100 = 270/100 ps
4474 00:39:03.948866 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4475 00:39:03.955624 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4476 00:39:03.958995 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4477 00:39:03.961990 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4478 00:39:03.965314 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4479 00:39:03.968753 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4480 00:39:03.968882
4481 00:39:03.971716 CA PerBit enable=1, Macro0, CA PI delay=33
4482 00:39:03.971816
4483 00:39:03.975297 [CBTSetCACLKResult] CA Dly = 33
4484 00:39:03.975404 CS Dly: 4 (0~36)
4485 00:39:03.978402
4486 00:39:03.981686 ----->DramcWriteLeveling(PI) begin...
4487 00:39:03.981793 ==
4488 00:39:03.985129 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 00:39:03.988448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 00:39:03.988572 ==
4491 00:39:03.992004 Write leveling (Byte 0): 29 => 29
4492 00:39:03.995450 Write leveling (Byte 1): 30 => 30
4493 00:39:03.998515 DramcWriteLeveling(PI) end<-----
4494 00:39:03.998647
4495 00:39:03.998737 ==
4496 00:39:04.001926 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 00:39:04.004815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 00:39:04.004898 ==
4499 00:39:04.008224 [Gating] SW mode calibration
4500 00:39:04.015068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4501 00:39:04.021399 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4502 00:39:04.024879 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 00:39:04.028366 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4504 00:39:04.034536 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4505 00:39:04.038031 0 9 12 | B1->B0 | 3131 3131 | 0 0 | (1 0) (1 0)
4506 00:39:04.041497 0 9 16 | B1->B0 | 2626 2828 | 0 0 | (1 1) (1 1)
4507 00:39:04.048000 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 00:39:04.051287 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 00:39:04.054909 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 00:39:04.061217 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 00:39:04.064788 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 00:39:04.068036 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 00:39:04.074863 0 10 12 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (0 0)
4514 00:39:04.077677 0 10 16 | B1->B0 | 4343 4040 | 0 0 | (0 0) (0 0)
4515 00:39:04.081431 0 10 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
4516 00:39:04.084313 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 00:39:04.090959 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 00:39:04.094372 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 00:39:04.097889 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 00:39:04.104230 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 00:39:04.107682 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4522 00:39:04.111170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4523 00:39:04.117971 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 00:39:04.120862 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 00:39:04.124285 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 00:39:04.131160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 00:39:04.134184 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 00:39:04.137545 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 00:39:04.144254 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 00:39:04.147312 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 00:39:04.150897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 00:39:04.157321 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 00:39:04.160652 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 00:39:04.164528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 00:39:04.170800 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 00:39:04.174335 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 00:39:04.177610 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4538 00:39:04.181114 Total UI for P1: 0, mck2ui 16
4539 00:39:04.184035 best dqsien dly found for B1: ( 0, 13, 10)
4540 00:39:04.190546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4541 00:39:04.193920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 00:39:04.197073 Total UI for P1: 0, mck2ui 16
4543 00:39:04.200438 best dqsien dly found for B0: ( 0, 13, 14)
4544 00:39:04.203739 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4545 00:39:04.207191 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4546 00:39:04.207272
4547 00:39:04.210527 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4548 00:39:04.214027 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4549 00:39:04.217265 [Gating] SW calibration Done
4550 00:39:04.217374 ==
4551 00:39:04.220134 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 00:39:04.227056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 00:39:04.227136 ==
4554 00:39:04.227205 RX Vref Scan: 0
4555 00:39:04.227269
4556 00:39:04.229955 RX Vref 0 -> 0, step: 1
4557 00:39:04.230032
4558 00:39:04.233432 RX Delay -230 -> 252, step: 16
4559 00:39:04.236861 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4560 00:39:04.240306 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4561 00:39:04.243791 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4562 00:39:04.250043 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4563 00:39:04.253106 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4564 00:39:04.256890 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4565 00:39:04.259935 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4566 00:39:04.266235 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4567 00:39:04.270027 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4568 00:39:04.272946 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4569 00:39:04.276197 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4570 00:39:04.280000 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4571 00:39:04.286092 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4572 00:39:04.289449 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4573 00:39:04.292955 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4574 00:39:04.299470 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4575 00:39:04.299558 ==
4576 00:39:04.303061 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 00:39:04.306246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 00:39:04.306334 ==
4579 00:39:04.306420 DQS Delay:
4580 00:39:04.309497 DQS0 = 0, DQS1 = 0
4581 00:39:04.309582 DQM Delay:
4582 00:39:04.312799 DQM0 = 40, DQM1 = 28
4583 00:39:04.312882 DQ Delay:
4584 00:39:04.316094 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4585 00:39:04.319584 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4586 00:39:04.322479 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4587 00:39:04.325963 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4588 00:39:04.326044
4589 00:39:04.326128
4590 00:39:04.326206 ==
4591 00:39:04.329421 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 00:39:04.332836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 00:39:04.332917 ==
4594 00:39:04.333004
4595 00:39:04.333082
4596 00:39:04.335740 TX Vref Scan disable
4597 00:39:04.339089 == TX Byte 0 ==
4598 00:39:04.342490 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4599 00:39:04.345908 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4600 00:39:04.349084 == TX Byte 1 ==
4601 00:39:04.352466 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4602 00:39:04.355884 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4603 00:39:04.355963 ==
4604 00:39:04.359076 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 00:39:04.365586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 00:39:04.365668 ==
4607 00:39:04.365733
4608 00:39:04.365805
4609 00:39:04.365864 TX Vref Scan disable
4610 00:39:04.370218 == TX Byte 0 ==
4611 00:39:04.373385 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4612 00:39:04.380026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4613 00:39:04.380118 == TX Byte 1 ==
4614 00:39:04.383424 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4615 00:39:04.390263 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4616 00:39:04.390347
4617 00:39:04.390434 [DATLAT]
4618 00:39:04.390513 Freq=600, CH1 RK0
4619 00:39:04.390591
4620 00:39:04.393260 DATLAT Default: 0x9
4621 00:39:04.393336 0, 0xFFFF, sum = 0
4622 00:39:04.396525 1, 0xFFFF, sum = 0
4623 00:39:04.399867 2, 0xFFFF, sum = 0
4624 00:39:04.399952 3, 0xFFFF, sum = 0
4625 00:39:04.403440 4, 0xFFFF, sum = 0
4626 00:39:04.403521 5, 0xFFFF, sum = 0
4627 00:39:04.406847 6, 0xFFFF, sum = 0
4628 00:39:04.406930 7, 0xFFFF, sum = 0
4629 00:39:04.409919 8, 0x0, sum = 1
4630 00:39:04.410001 9, 0x0, sum = 2
4631 00:39:04.410086 10, 0x0, sum = 3
4632 00:39:04.412977 11, 0x0, sum = 4
4633 00:39:04.413057 best_step = 9
4634 00:39:04.413162
4635 00:39:04.413242 ==
4636 00:39:04.416392 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 00:39:04.423301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 00:39:04.423412 ==
4639 00:39:04.423486 RX Vref Scan: 1
4640 00:39:04.423547
4641 00:39:04.426666 RX Vref 0 -> 0, step: 1
4642 00:39:04.426742
4643 00:39:04.429640 RX Delay -195 -> 252, step: 8
4644 00:39:04.429723
4645 00:39:04.433010 Set Vref, RX VrefLevel [Byte0]: 56
4646 00:39:04.436371 [Byte1]: 52
4647 00:39:04.436454
4648 00:39:04.439953 Final RX Vref Byte 0 = 56 to rank0
4649 00:39:04.442877 Final RX Vref Byte 1 = 52 to rank0
4650 00:39:04.446184 Final RX Vref Byte 0 = 56 to rank1
4651 00:39:04.449641 Final RX Vref Byte 1 = 52 to rank1==
4652 00:39:04.452940 Dram Type= 6, Freq= 0, CH_1, rank 0
4653 00:39:04.456307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 00:39:04.456391 ==
4655 00:39:04.459631 DQS Delay:
4656 00:39:04.459713 DQS0 = 0, DQS1 = 0
4657 00:39:04.463011 DQM Delay:
4658 00:39:04.463125 DQM0 = 39, DQM1 = 28
4659 00:39:04.463228 DQ Delay:
4660 00:39:04.466373 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4661 00:39:04.469703 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =32
4662 00:39:04.472977 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4663 00:39:04.476101 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4664 00:39:04.476197
4665 00:39:04.476267
4666 00:39:04.485748 [DQSOSCAuto] RK0, (LSB)MR18= 0x2532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4667 00:39:04.489075 CH1 RK0: MR19=808, MR18=2532
4668 00:39:04.496038 CH1_RK0: MR19=0x808, MR18=0x2532, DQSOSC=400, MR23=63, INC=163, DEC=109
4669 00:39:04.496122
4670 00:39:04.499114 ----->DramcWriteLeveling(PI) begin...
4671 00:39:04.499229 ==
4672 00:39:04.502682 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 00:39:04.505961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 00:39:04.506045 ==
4675 00:39:04.509175 Write leveling (Byte 0): 28 => 28
4676 00:39:04.512674 Write leveling (Byte 1): 28 => 28
4677 00:39:04.516089 DramcWriteLeveling(PI) end<-----
4678 00:39:04.516216
4679 00:39:04.516299 ==
4680 00:39:04.519221 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 00:39:04.522258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 00:39:04.522341 ==
4683 00:39:04.525939 [Gating] SW mode calibration
4684 00:39:04.532220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4685 00:39:04.539003 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4686 00:39:04.542517 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4687 00:39:04.545828 0 9 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
4688 00:39:04.552151 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4689 00:39:04.555590 0 9 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4690 00:39:04.558956 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4691 00:39:04.565649 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 00:39:04.569037 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 00:39:04.571848 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 00:39:04.578592 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 00:39:04.581886 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 00:39:04.585156 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4697 00:39:04.591671 0 10 12 | B1->B0 | 2e2e 3838 | 0 0 | (1 1) (1 1)
4698 00:39:04.595010 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4699 00:39:04.598452 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 00:39:04.605309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 00:39:04.608528 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 00:39:04.611997 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 00:39:04.618341 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 00:39:04.621648 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 00:39:04.625160 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4706 00:39:04.631772 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 00:39:04.635198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 00:39:04.638327 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 00:39:04.645163 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 00:39:04.648027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 00:39:04.651532 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 00:39:04.657979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 00:39:04.661402 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 00:39:04.664817 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 00:39:04.671460 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 00:39:04.674965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 00:39:04.677941 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 00:39:04.684594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 00:39:04.688014 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 00:39:04.691298 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 00:39:04.697866 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4722 00:39:04.701340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 00:39:04.704124 Total UI for P1: 0, mck2ui 16
4724 00:39:04.707527 best dqsien dly found for B0: ( 0, 13, 12)
4725 00:39:04.710991 Total UI for P1: 0, mck2ui 16
4726 00:39:04.714523 best dqsien dly found for B1: ( 0, 13, 12)
4727 00:39:04.717806 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4728 00:39:04.720922 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4729 00:39:04.720999
4730 00:39:04.724440 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4731 00:39:04.727671 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4732 00:39:04.730954 [Gating] SW calibration Done
4733 00:39:04.731041 ==
4734 00:39:04.734285 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 00:39:04.737738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 00:39:04.737817 ==
4737 00:39:04.740907 RX Vref Scan: 0
4738 00:39:04.740983
4739 00:39:04.744158 RX Vref 0 -> 0, step: 1
4740 00:39:04.744234
4741 00:39:04.747660 RX Delay -230 -> 252, step: 16
4742 00:39:04.750712 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4743 00:39:04.754137 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4744 00:39:04.757328 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4745 00:39:04.760850 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4746 00:39:04.767195 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4747 00:39:04.770679 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4748 00:39:04.773962 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4749 00:39:04.777326 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4750 00:39:04.784113 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4751 00:39:04.787472 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4752 00:39:04.790848 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4753 00:39:04.793674 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4754 00:39:04.800365 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4755 00:39:04.803550 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4756 00:39:04.806949 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4757 00:39:04.810484 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4758 00:39:04.810572 ==
4759 00:39:04.813781 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 00:39:04.820163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 00:39:04.820246 ==
4762 00:39:04.820355 DQS Delay:
4763 00:39:04.823531 DQS0 = 0, DQS1 = 0
4764 00:39:04.823611 DQM Delay:
4765 00:39:04.823693 DQM0 = 35, DQM1 = 29
4766 00:39:04.826972 DQ Delay:
4767 00:39:04.830122 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4768 00:39:04.833689 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4769 00:39:04.837065 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4770 00:39:04.839986 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4771 00:39:04.840063
4772 00:39:04.840129
4773 00:39:04.840214 ==
4774 00:39:04.843462 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 00:39:04.846788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 00:39:04.846873 ==
4777 00:39:04.846961
4778 00:39:04.847033
4779 00:39:04.850231 TX Vref Scan disable
4780 00:39:04.853370 == TX Byte 0 ==
4781 00:39:04.856746 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4782 00:39:04.860188 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4783 00:39:04.863568 == TX Byte 1 ==
4784 00:39:04.866919 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4785 00:39:04.869792 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4786 00:39:04.869906 ==
4787 00:39:04.873214 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 00:39:04.876622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 00:39:04.880061 ==
4790 00:39:04.880147
4791 00:39:04.880235
4792 00:39:04.880336 TX Vref Scan disable
4793 00:39:04.883501 == TX Byte 0 ==
4794 00:39:04.886988 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4795 00:39:04.890333 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4796 00:39:04.893787 == TX Byte 1 ==
4797 00:39:04.897028 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4798 00:39:04.903270 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4799 00:39:04.903364
4800 00:39:04.903433 [DATLAT]
4801 00:39:04.903494 Freq=600, CH1 RK1
4802 00:39:04.903554
4803 00:39:04.907076 DATLAT Default: 0x9
4804 00:39:04.907168 0, 0xFFFF, sum = 0
4805 00:39:04.909813 1, 0xFFFF, sum = 0
4806 00:39:04.913554 2, 0xFFFF, sum = 0
4807 00:39:04.913639 3, 0xFFFF, sum = 0
4808 00:39:04.916960 4, 0xFFFF, sum = 0
4809 00:39:04.917067 5, 0xFFFF, sum = 0
4810 00:39:04.919936 6, 0xFFFF, sum = 0
4811 00:39:04.920016 7, 0xFFFF, sum = 0
4812 00:39:04.923312 8, 0x0, sum = 1
4813 00:39:04.923390 9, 0x0, sum = 2
4814 00:39:04.923459 10, 0x0, sum = 3
4815 00:39:04.926678 11, 0x0, sum = 4
4816 00:39:04.926765 best_step = 9
4817 00:39:04.926836
4818 00:39:04.926896 ==
4819 00:39:04.930271 Dram Type= 6, Freq= 0, CH_1, rank 1
4820 00:39:04.936517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4821 00:39:04.936618 ==
4822 00:39:04.936693 RX Vref Scan: 0
4823 00:39:04.936753
4824 00:39:04.940317 RX Vref 0 -> 0, step: 1
4825 00:39:04.940394
4826 00:39:04.943410 RX Delay -195 -> 252, step: 8
4827 00:39:04.946437 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4828 00:39:04.953231 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4829 00:39:04.956488 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4830 00:39:04.959950 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4831 00:39:04.963351 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4832 00:39:04.969606 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4833 00:39:04.972896 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4834 00:39:04.976136 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4835 00:39:04.979577 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4836 00:39:04.982875 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4837 00:39:04.989838 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4838 00:39:04.992684 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4839 00:39:04.995877 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4840 00:39:04.999261 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4841 00:39:05.006085 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4842 00:39:05.009356 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4843 00:39:05.009456 ==
4844 00:39:05.012786 Dram Type= 6, Freq= 0, CH_1, rank 1
4845 00:39:05.015840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4846 00:39:05.015943 ==
4847 00:39:05.019225 DQS Delay:
4848 00:39:05.019363 DQS0 = 0, DQS1 = 0
4849 00:39:05.022573 DQM Delay:
4850 00:39:05.022676 DQM0 = 36, DQM1 = 30
4851 00:39:05.022787 DQ Delay:
4852 00:39:05.026066 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4853 00:39:05.029120 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4854 00:39:05.032642 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4855 00:39:05.035963 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4856 00:39:05.036045
4857 00:39:05.036110
4858 00:39:05.045822 [DQSOSCAuto] RK1, (LSB)MR18= 0x3453, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4859 00:39:05.049235 CH1 RK1: MR19=808, MR18=3453
4860 00:39:05.055987 CH1_RK1: MR19=0x808, MR18=0x3453, DQSOSC=394, MR23=63, INC=168, DEC=112
4861 00:39:05.056116 [RxdqsGatingPostProcess] freq 600
4862 00:39:05.062284 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4863 00:39:05.065755 Pre-setting of DQS Precalculation
4864 00:39:05.069291 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4865 00:39:05.079085 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4866 00:39:05.085471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4867 00:39:05.085568
4868 00:39:05.085668
4869 00:39:05.089130 [Calibration Summary] 1200 Mbps
4870 00:39:05.089219 CH 0, Rank 0
4871 00:39:05.091915 SW Impedance : PASS
4872 00:39:05.092010 DUTY Scan : NO K
4873 00:39:05.095369 ZQ Calibration : PASS
4874 00:39:05.098874 Jitter Meter : NO K
4875 00:39:05.098997 CBT Training : PASS
4876 00:39:05.102070 Write leveling : PASS
4877 00:39:05.105570 RX DQS gating : PASS
4878 00:39:05.105659 RX DQ/DQS(RDDQC) : PASS
4879 00:39:05.108952 TX DQ/DQS : PASS
4880 00:39:05.111929 RX DATLAT : PASS
4881 00:39:05.112012 RX DQ/DQS(Engine): PASS
4882 00:39:05.115170 TX OE : NO K
4883 00:39:05.115267 All Pass.
4884 00:39:05.115352
4885 00:39:05.118463 CH 0, Rank 1
4886 00:39:05.118547 SW Impedance : PASS
4887 00:39:05.121973 DUTY Scan : NO K
4888 00:39:05.125217 ZQ Calibration : PASS
4889 00:39:05.125301 Jitter Meter : NO K
4890 00:39:05.128792 CBT Training : PASS
4891 00:39:05.131588 Write leveling : PASS
4892 00:39:05.131667 RX DQS gating : PASS
4893 00:39:05.135104 RX DQ/DQS(RDDQC) : PASS
4894 00:39:05.135179 TX DQ/DQS : PASS
4895 00:39:05.138491 RX DATLAT : PASS
4896 00:39:05.141917 RX DQ/DQS(Engine): PASS
4897 00:39:05.142001 TX OE : NO K
4898 00:39:05.145359 All Pass.
4899 00:39:05.145445
4900 00:39:05.145510 CH 1, Rank 0
4901 00:39:05.148706 SW Impedance : PASS
4902 00:39:05.148815 DUTY Scan : NO K
4903 00:39:05.151626 ZQ Calibration : PASS
4904 00:39:05.155190 Jitter Meter : NO K
4905 00:39:05.155279 CBT Training : PASS
4906 00:39:05.158509 Write leveling : PASS
4907 00:39:05.161691 RX DQS gating : PASS
4908 00:39:05.161775 RX DQ/DQS(RDDQC) : PASS
4909 00:39:05.164808 TX DQ/DQS : PASS
4910 00:39:05.168399 RX DATLAT : PASS
4911 00:39:05.168512 RX DQ/DQS(Engine): PASS
4912 00:39:05.171520 TX OE : NO K
4913 00:39:05.171602 All Pass.
4914 00:39:05.171692
4915 00:39:05.175082 CH 1, Rank 1
4916 00:39:05.175164 SW Impedance : PASS
4917 00:39:05.178446 DUTY Scan : NO K
4918 00:39:05.181600 ZQ Calibration : PASS
4919 00:39:05.181686 Jitter Meter : NO K
4920 00:39:05.184859 CBT Training : PASS
4921 00:39:05.188234 Write leveling : PASS
4922 00:39:05.188352 RX DQS gating : PASS
4923 00:39:05.191541 RX DQ/DQS(RDDQC) : PASS
4924 00:39:05.194687 TX DQ/DQS : PASS
4925 00:39:05.194772 RX DATLAT : PASS
4926 00:39:05.198354 RX DQ/DQS(Engine): PASS
4927 00:39:05.198483 TX OE : NO K
4928 00:39:05.201329 All Pass.
4929 00:39:05.201449
4930 00:39:05.201562 DramC Write-DBI off
4931 00:39:05.204572 PER_BANK_REFRESH: Hybrid Mode
4932 00:39:05.207946 TX_TRACKING: ON
4933 00:39:05.214441 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4934 00:39:05.217646 [FAST_K] Save calibration result to emmc
4935 00:39:05.224392 dramc_set_vcore_voltage set vcore to 662500
4936 00:39:05.224498 Read voltage for 933, 3
4937 00:39:05.224600 Vio18 = 0
4938 00:39:05.227714 Vcore = 662500
4939 00:39:05.227821 Vdram = 0
4940 00:39:05.227913 Vddq = 0
4941 00:39:05.231003 Vmddr = 0
4942 00:39:05.234487 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4943 00:39:05.240766 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4944 00:39:05.244174 MEM_TYPE=3, freq_sel=17
4945 00:39:05.244303 sv_algorithm_assistance_LP4_1600
4946 00:39:05.251082 ============ PULL DRAM RESETB DOWN ============
4947 00:39:05.253978 ========== PULL DRAM RESETB DOWN end =========
4948 00:39:05.257461 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4949 00:39:05.260867 ===================================
4950 00:39:05.264389 LPDDR4 DRAM CONFIGURATION
4951 00:39:05.267847 ===================================
4952 00:39:05.270900 EX_ROW_EN[0] = 0x0
4953 00:39:05.270983 EX_ROW_EN[1] = 0x0
4954 00:39:05.274104 LP4Y_EN = 0x0
4955 00:39:05.274187 WORK_FSP = 0x0
4956 00:39:05.277152 WL = 0x3
4957 00:39:05.277268 RL = 0x3
4958 00:39:05.280983 BL = 0x2
4959 00:39:05.281067 RPST = 0x0
4960 00:39:05.284277 RD_PRE = 0x0
4961 00:39:05.284360 WR_PRE = 0x1
4962 00:39:05.287192 WR_PST = 0x0
4963 00:39:05.287275 DBI_WR = 0x0
4964 00:39:05.290675 DBI_RD = 0x0
4965 00:39:05.294324 OTF = 0x1
4966 00:39:05.297580 ===================================
4967 00:39:05.297664 ===================================
4968 00:39:05.300625 ANA top config
4969 00:39:05.303756 ===================================
4970 00:39:05.307591 DLL_ASYNC_EN = 0
4971 00:39:05.307719 ALL_SLAVE_EN = 1
4972 00:39:05.310560 NEW_RANK_MODE = 1
4973 00:39:05.313925 DLL_IDLE_MODE = 1
4974 00:39:05.317426 LP45_APHY_COMB_EN = 1
4975 00:39:05.320645 TX_ODT_DIS = 1
4976 00:39:05.320771 NEW_8X_MODE = 1
4977 00:39:05.324042 ===================================
4978 00:39:05.326911 ===================================
4979 00:39:05.330237 data_rate = 1866
4980 00:39:05.333592 CKR = 1
4981 00:39:05.337127 DQ_P2S_RATIO = 8
4982 00:39:05.340535 ===================================
4983 00:39:05.343908 CA_P2S_RATIO = 8
4984 00:39:05.346820 DQ_CA_OPEN = 0
4985 00:39:05.346947 DQ_SEMI_OPEN = 0
4986 00:39:05.350200 CA_SEMI_OPEN = 0
4987 00:39:05.353623 CA_FULL_RATE = 0
4988 00:39:05.357213 DQ_CKDIV4_EN = 1
4989 00:39:05.360023 CA_CKDIV4_EN = 1
4990 00:39:05.363445 CA_PREDIV_EN = 0
4991 00:39:05.363556 PH8_DLY = 0
4992 00:39:05.366907 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4993 00:39:05.370348 DQ_AAMCK_DIV = 4
4994 00:39:05.373829 CA_AAMCK_DIV = 4
4995 00:39:05.376930 CA_ADMCK_DIV = 4
4996 00:39:05.380287 DQ_TRACK_CA_EN = 0
4997 00:39:05.380415 CA_PICK = 933
4998 00:39:05.383487 CA_MCKIO = 933
4999 00:39:05.386897 MCKIO_SEMI = 0
5000 00:39:05.390454 PLL_FREQ = 3732
5001 00:39:05.393118 DQ_UI_PI_RATIO = 32
5002 00:39:05.396874 CA_UI_PI_RATIO = 0
5003 00:39:05.399923 ===================================
5004 00:39:05.403417 ===================================
5005 00:39:05.403542 memory_type:LPDDR4
5006 00:39:05.406874 GP_NUM : 10
5007 00:39:05.410098 SRAM_EN : 1
5008 00:39:05.410223 MD32_EN : 0
5009 00:39:05.413325 ===================================
5010 00:39:05.416467 [ANA_INIT] >>>>>>>>>>>>>>
5011 00:39:05.419974 <<<<<< [CONFIGURE PHASE]: ANA_TX
5012 00:39:05.423222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5013 00:39:05.426560 ===================================
5014 00:39:05.429821 data_rate = 1866,PCW = 0X8f00
5015 00:39:05.433165 ===================================
5016 00:39:05.436487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5017 00:39:05.440098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5018 00:39:05.446216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5019 00:39:05.449639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5020 00:39:05.453079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5021 00:39:05.459393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5022 00:39:05.459478 [ANA_INIT] flow start
5023 00:39:05.462953 [ANA_INIT] PLL >>>>>>>>
5024 00:39:05.466249 [ANA_INIT] PLL <<<<<<<<
5025 00:39:05.466331 [ANA_INIT] MIDPI >>>>>>>>
5026 00:39:05.469767 [ANA_INIT] MIDPI <<<<<<<<
5027 00:39:05.472712 [ANA_INIT] DLL >>>>>>>>
5028 00:39:05.472800 [ANA_INIT] flow end
5029 00:39:05.479491 ============ LP4 DIFF to SE enter ============
5030 00:39:05.482538 ============ LP4 DIFF to SE exit ============
5031 00:39:05.482623 [ANA_INIT] <<<<<<<<<<<<<
5032 00:39:05.486139 [Flow] Enable top DCM control >>>>>
5033 00:39:05.489336 [Flow] Enable top DCM control <<<<<
5034 00:39:05.492964 Enable DLL master slave shuffle
5035 00:39:05.499116 ==============================================================
5036 00:39:05.502537 Gating Mode config
5037 00:39:05.505792 ==============================================================
5038 00:39:05.509103 Config description:
5039 00:39:05.519484 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5040 00:39:05.526090 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5041 00:39:05.529346 SELPH_MODE 0: By rank 1: By Phase
5042 00:39:05.535861 ==============================================================
5043 00:39:05.539521 GAT_TRACK_EN = 1
5044 00:39:05.542232 RX_GATING_MODE = 2
5045 00:39:05.542318 RX_GATING_TRACK_MODE = 2
5046 00:39:05.545715 SELPH_MODE = 1
5047 00:39:05.549101 PICG_EARLY_EN = 1
5048 00:39:05.552457 VALID_LAT_VALUE = 1
5049 00:39:05.559284 ==============================================================
5050 00:39:05.562119 Enter into Gating configuration >>>>
5051 00:39:05.565435 Exit from Gating configuration <<<<
5052 00:39:05.569124 Enter into DVFS_PRE_config >>>>>
5053 00:39:05.578869 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5054 00:39:05.582491 Exit from DVFS_PRE_config <<<<<
5055 00:39:05.585390 Enter into PICG configuration >>>>
5056 00:39:05.588641 Exit from PICG configuration <<<<
5057 00:39:05.592272 [RX_INPUT] configuration >>>>>
5058 00:39:05.595263 [RX_INPUT] configuration <<<<<
5059 00:39:05.598436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5060 00:39:05.605387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5061 00:39:05.612114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5062 00:39:05.618507 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5063 00:39:05.625366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5064 00:39:05.628809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5065 00:39:05.634947 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5066 00:39:05.638345 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5067 00:39:05.641730 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5068 00:39:05.644890 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5069 00:39:05.648426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5070 00:39:05.654790 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 00:39:05.658283 ===================================
5072 00:39:05.661518 LPDDR4 DRAM CONFIGURATION
5073 00:39:05.665077 ===================================
5074 00:39:05.665192 EX_ROW_EN[0] = 0x0
5075 00:39:05.668394 EX_ROW_EN[1] = 0x0
5076 00:39:05.668525 LP4Y_EN = 0x0
5077 00:39:05.671281 WORK_FSP = 0x0
5078 00:39:05.671408 WL = 0x3
5079 00:39:05.674649 RL = 0x3
5080 00:39:05.674783 BL = 0x2
5081 00:39:05.678089 RPST = 0x0
5082 00:39:05.678217 RD_PRE = 0x0
5083 00:39:05.681591 WR_PRE = 0x1
5084 00:39:05.681721 WR_PST = 0x0
5085 00:39:05.684581 DBI_WR = 0x0
5086 00:39:05.688031 DBI_RD = 0x0
5087 00:39:05.688110 OTF = 0x1
5088 00:39:05.691465 ===================================
5089 00:39:05.694985 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5090 00:39:05.698110 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5091 00:39:05.704821 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5092 00:39:05.707676 ===================================
5093 00:39:05.711049 LPDDR4 DRAM CONFIGURATION
5094 00:39:05.714455 ===================================
5095 00:39:05.714544 EX_ROW_EN[0] = 0x10
5096 00:39:05.717928 EX_ROW_EN[1] = 0x0
5097 00:39:05.718009 LP4Y_EN = 0x0
5098 00:39:05.720941 WORK_FSP = 0x0
5099 00:39:05.721023 WL = 0x3
5100 00:39:05.724321 RL = 0x3
5101 00:39:05.724396 BL = 0x2
5102 00:39:05.727563 RPST = 0x0
5103 00:39:05.727638 RD_PRE = 0x0
5104 00:39:05.731236 WR_PRE = 0x1
5105 00:39:05.731339 WR_PST = 0x0
5106 00:39:05.734757 DBI_WR = 0x0
5107 00:39:05.734843 DBI_RD = 0x0
5108 00:39:05.737528 OTF = 0x1
5109 00:39:05.741401 ===================================
5110 00:39:05.747577 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5111 00:39:05.750955 nWR fixed to 30
5112 00:39:05.754220 [ModeRegInit_LP4] CH0 RK0
5113 00:39:05.754340 [ModeRegInit_LP4] CH0 RK1
5114 00:39:05.757382 [ModeRegInit_LP4] CH1 RK0
5115 00:39:05.760893 [ModeRegInit_LP4] CH1 RK1
5116 00:39:05.760987 match AC timing 9
5117 00:39:05.767813 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5118 00:39:05.770653 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5119 00:39:05.774135 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5120 00:39:05.781112 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5121 00:39:05.784617 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5122 00:39:05.784755 ==
5123 00:39:05.787554 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 00:39:05.790958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 00:39:05.791099 ==
5126 00:39:05.797667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 00:39:05.804390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5128 00:39:05.807584 [CA 0] Center 38 (8~69) winsize 62
5129 00:39:05.810617 [CA 1] Center 38 (8~68) winsize 61
5130 00:39:05.813865 [CA 2] Center 35 (5~65) winsize 61
5131 00:39:05.817646 [CA 3] Center 35 (5~65) winsize 61
5132 00:39:05.820534 [CA 4] Center 34 (4~65) winsize 62
5133 00:39:05.823904 [CA 5] Center 33 (3~64) winsize 62
5134 00:39:05.824043
5135 00:39:05.827155 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5136 00:39:05.827286
5137 00:39:05.830586 [CATrainingPosCal] consider 1 rank data
5138 00:39:05.833920 u2DelayCellTimex100 = 270/100 ps
5139 00:39:05.837237 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5140 00:39:05.840381 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5141 00:39:05.844040 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5142 00:39:05.847663 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5143 00:39:05.850857 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5144 00:39:05.857362 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5145 00:39:05.857505
5146 00:39:05.860762 CA PerBit enable=1, Macro0, CA PI delay=33
5147 00:39:05.860889
5148 00:39:05.863567 [CBTSetCACLKResult] CA Dly = 33
5149 00:39:05.863711 CS Dly: 7 (0~38)
5150 00:39:05.863775 ==
5151 00:39:05.867017 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 00:39:05.870639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 00:39:05.873852 ==
5154 00:39:05.876905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5155 00:39:05.883815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5156 00:39:05.887207 [CA 0] Center 38 (8~69) winsize 62
5157 00:39:05.890052 [CA 1] Center 38 (8~69) winsize 62
5158 00:39:05.893433 [CA 2] Center 35 (5~66) winsize 62
5159 00:39:05.896908 [CA 3] Center 35 (5~66) winsize 62
5160 00:39:05.900320 [CA 4] Center 34 (4~65) winsize 62
5161 00:39:05.903817 [CA 5] Center 33 (3~64) winsize 62
5162 00:39:05.903958
5163 00:39:05.907191 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5164 00:39:05.907314
5165 00:39:05.910218 [CATrainingPosCal] consider 2 rank data
5166 00:39:05.913444 u2DelayCellTimex100 = 270/100 ps
5167 00:39:05.916899 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5168 00:39:05.920288 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5169 00:39:05.923550 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5170 00:39:05.930205 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5171 00:39:05.933385 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5172 00:39:05.936812 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5173 00:39:05.936945
5174 00:39:05.939591 CA PerBit enable=1, Macro0, CA PI delay=33
5175 00:39:05.939725
5176 00:39:05.943095 [CBTSetCACLKResult] CA Dly = 33
5177 00:39:05.943236 CS Dly: 7 (0~39)
5178 00:39:05.943359
5179 00:39:05.946526 ----->DramcWriteLeveling(PI) begin...
5180 00:39:05.949861 ==
5181 00:39:05.952919 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 00:39:05.956677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 00:39:05.956802 ==
5184 00:39:05.960023 Write leveling (Byte 0): 33 => 33
5185 00:39:05.962869 Write leveling (Byte 1): 29 => 29
5186 00:39:05.966322 DramcWriteLeveling(PI) end<-----
5187 00:39:05.966457
5188 00:39:05.966570 ==
5189 00:39:05.969859 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 00:39:05.973244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 00:39:05.973378 ==
5192 00:39:05.975996 [Gating] SW mode calibration
5193 00:39:05.982980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5194 00:39:05.989594 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5195 00:39:05.992656 0 14 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5196 00:39:05.996458 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5197 00:39:06.002801 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 00:39:06.006390 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 00:39:06.009172 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 00:39:06.016104 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 00:39:06.019008 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 00:39:06.022583 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5203 00:39:06.028970 0 15 0 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
5204 00:39:06.032589 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5205 00:39:06.035527 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 00:39:06.042408 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 00:39:06.045280 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 00:39:06.048635 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 00:39:06.055493 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 00:39:06.058907 0 15 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5211 00:39:06.061993 1 0 0 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)
5212 00:39:06.065358 1 0 4 | B1->B0 | 4443 4646 | 1 0 | (0 0) (0 0)
5213 00:39:06.072202 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 00:39:06.075450 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 00:39:06.078897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 00:39:06.085491 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 00:39:06.088452 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 00:39:06.091745 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5219 00:39:06.098545 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5220 00:39:06.101984 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5221 00:39:06.105371 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 00:39:06.111638 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 00:39:06.115032 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 00:39:06.118414 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 00:39:06.124898 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 00:39:06.128434 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 00:39:06.131892 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 00:39:06.138199 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 00:39:06.141616 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 00:39:06.144602 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 00:39:06.151339 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 00:39:06.154411 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 00:39:06.157754 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 00:39:06.164580 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5235 00:39:06.167831 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5236 00:39:06.171156 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 00:39:06.174440 Total UI for P1: 0, mck2ui 16
5238 00:39:06.177899 best dqsien dly found for B0: ( 1, 2, 30)
5239 00:39:06.180882 Total UI for P1: 0, mck2ui 16
5240 00:39:06.184178 best dqsien dly found for B1: ( 1, 3, 2)
5241 00:39:06.187682 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5242 00:39:06.191108 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5243 00:39:06.191186
5244 00:39:06.197636 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5245 00:39:06.200944 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5246 00:39:06.201049 [Gating] SW calibration Done
5247 00:39:06.204578 ==
5248 00:39:06.207932 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 00:39:06.210845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 00:39:06.210948 ==
5251 00:39:06.211048 RX Vref Scan: 0
5252 00:39:06.211144
5253 00:39:06.214382 RX Vref 0 -> 0, step: 1
5254 00:39:06.214463
5255 00:39:06.217504 RX Delay -80 -> 252, step: 8
5256 00:39:06.220835 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5257 00:39:06.224144 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5258 00:39:06.227588 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5259 00:39:06.234544 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5260 00:39:06.237968 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5261 00:39:06.240751 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5262 00:39:06.244093 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5263 00:39:06.247375 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5264 00:39:06.251043 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5265 00:39:06.257351 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5266 00:39:06.260998 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5267 00:39:06.264082 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5268 00:39:06.267865 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5269 00:39:06.270528 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5270 00:39:06.277226 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5271 00:39:06.280962 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5272 00:39:06.281087 ==
5273 00:39:06.283827 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 00:39:06.287263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 00:39:06.287353 ==
5276 00:39:06.290809 DQS Delay:
5277 00:39:06.290905 DQS0 = 0, DQS1 = 0
5278 00:39:06.290971 DQM Delay:
5279 00:39:06.293869 DQM0 = 94, DQM1 = 83
5280 00:39:06.293947 DQ Delay:
5281 00:39:06.297159 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5282 00:39:06.300482 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5283 00:39:06.303879 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5284 00:39:06.307175 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5285 00:39:06.307295
5286 00:39:06.307389
5287 00:39:06.307481 ==
5288 00:39:06.310458 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 00:39:06.317398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 00:39:06.317490 ==
5291 00:39:06.317562
5292 00:39:06.317626
5293 00:39:06.317716 TX Vref Scan disable
5294 00:39:06.320863 == TX Byte 0 ==
5295 00:39:06.324192 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5296 00:39:06.330493 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5297 00:39:06.330583 == TX Byte 1 ==
5298 00:39:06.334242 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5299 00:39:06.340522 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5300 00:39:06.340629 ==
5301 00:39:06.343903 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 00:39:06.347334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 00:39:06.347440 ==
5304 00:39:06.347550
5305 00:39:06.347645
5306 00:39:06.350602 TX Vref Scan disable
5307 00:39:06.350680 == TX Byte 0 ==
5308 00:39:06.357334 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5309 00:39:06.360159 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5310 00:39:06.360245 == TX Byte 1 ==
5311 00:39:06.367153 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5312 00:39:06.370406 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5313 00:39:06.370492
5314 00:39:06.370561 [DATLAT]
5315 00:39:06.373572 Freq=933, CH0 RK0
5316 00:39:06.373656
5317 00:39:06.373720 DATLAT Default: 0xd
5318 00:39:06.377123 0, 0xFFFF, sum = 0
5319 00:39:06.377209 1, 0xFFFF, sum = 0
5320 00:39:06.380425 2, 0xFFFF, sum = 0
5321 00:39:06.380519 3, 0xFFFF, sum = 0
5322 00:39:06.383879 4, 0xFFFF, sum = 0
5323 00:39:06.387181 5, 0xFFFF, sum = 0
5324 00:39:06.387294 6, 0xFFFF, sum = 0
5325 00:39:06.390397 7, 0xFFFF, sum = 0
5326 00:39:06.390485 8, 0xFFFF, sum = 0
5327 00:39:06.393897 9, 0xFFFF, sum = 0
5328 00:39:06.393983 10, 0x0, sum = 1
5329 00:39:06.396806 11, 0x0, sum = 2
5330 00:39:06.396893 12, 0x0, sum = 3
5331 00:39:06.396962 13, 0x0, sum = 4
5332 00:39:06.400166 best_step = 11
5333 00:39:06.400248
5334 00:39:06.400317 ==
5335 00:39:06.403631 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 00:39:06.406535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 00:39:06.406635 ==
5338 00:39:06.409893 RX Vref Scan: 1
5339 00:39:06.409967
5340 00:39:06.413596 RX Vref 0 -> 0, step: 1
5341 00:39:06.413681
5342 00:39:06.413745 RX Delay -69 -> 252, step: 4
5343 00:39:06.413839
5344 00:39:06.416903 Set Vref, RX VrefLevel [Byte0]: 60
5345 00:39:06.419836 [Byte1]: 55
5346 00:39:06.424960
5347 00:39:06.425037 Final RX Vref Byte 0 = 60 to rank0
5348 00:39:06.427904 Final RX Vref Byte 1 = 55 to rank0
5349 00:39:06.431506 Final RX Vref Byte 0 = 60 to rank1
5350 00:39:06.434938 Final RX Vref Byte 1 = 55 to rank1==
5351 00:39:06.438136 Dram Type= 6, Freq= 0, CH_0, rank 0
5352 00:39:06.445217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 00:39:06.445305 ==
5354 00:39:06.445370 DQS Delay:
5355 00:39:06.445430 DQS0 = 0, DQS1 = 0
5356 00:39:06.448008 DQM Delay:
5357 00:39:06.448083 DQM0 = 95, DQM1 = 84
5358 00:39:06.451382 DQ Delay:
5359 00:39:06.454642 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5360 00:39:06.458005 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5361 00:39:06.461224 DQ8 =78, DQ9 =72, DQ10 =82, DQ11 =80
5362 00:39:06.464482 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5363 00:39:06.464567
5364 00:39:06.464644
5365 00:39:06.471244 [DQSOSCAuto] RK0, (LSB)MR18= 0x1817, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5366 00:39:06.474616 CH0 RK0: MR19=505, MR18=1817
5367 00:39:06.481342 CH0_RK0: MR19=0x505, MR18=0x1817, DQSOSC=414, MR23=63, INC=63, DEC=42
5368 00:39:06.481433
5369 00:39:06.484879 ----->DramcWriteLeveling(PI) begin...
5370 00:39:06.484977 ==
5371 00:39:06.487980 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 00:39:06.491370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 00:39:06.491485 ==
5374 00:39:06.494572 Write leveling (Byte 0): 33 => 33
5375 00:39:06.497977 Write leveling (Byte 1): 29 => 29
5376 00:39:06.501401 DramcWriteLeveling(PI) end<-----
5377 00:39:06.501490
5378 00:39:06.501584 ==
5379 00:39:06.504396 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 00:39:06.507758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 00:39:06.507869 ==
5382 00:39:06.511224 [Gating] SW mode calibration
5383 00:39:06.517855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5384 00:39:06.524305 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5385 00:39:06.527767 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5386 00:39:06.534183 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 00:39:06.537529 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 00:39:06.540886 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 00:39:06.547930 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 00:39:06.551119 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 00:39:06.554317 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5392 00:39:06.557450 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5393 00:39:06.563822 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5394 00:39:06.567524 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 00:39:06.574264 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 00:39:06.576969 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 00:39:06.580456 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 00:39:06.583904 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 00:39:06.590463 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5400 00:39:06.593757 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5401 00:39:06.600004 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5402 00:39:06.603652 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 00:39:06.607050 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 00:39:06.610067 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 00:39:06.616904 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 00:39:06.620207 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 00:39:06.623760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 00:39:06.630311 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5409 00:39:06.633733 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5410 00:39:06.636578 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5411 00:39:06.643607 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 00:39:06.646883 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 00:39:06.649849 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 00:39:06.656700 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 00:39:06.660252 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 00:39:06.663424 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 00:39:06.669799 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 00:39:06.673428 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 00:39:06.676421 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 00:39:06.683242 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 00:39:06.686560 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 00:39:06.690059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 00:39:06.696411 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 00:39:06.699811 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5425 00:39:06.702907 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5426 00:39:06.706490 Total UI for P1: 0, mck2ui 16
5427 00:39:06.709340 best dqsien dly found for B0: ( 1, 2, 28)
5428 00:39:06.716232 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 00:39:06.716321 Total UI for P1: 0, mck2ui 16
5430 00:39:06.723122 best dqsien dly found for B1: ( 1, 3, 0)
5431 00:39:06.725961 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5432 00:39:06.729358 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5433 00:39:06.729445
5434 00:39:06.732885 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5435 00:39:06.736024 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5436 00:39:06.739169 [Gating] SW calibration Done
5437 00:39:06.739279 ==
5438 00:39:06.742705 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 00:39:06.746204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 00:39:06.746314 ==
5441 00:39:06.749488 RX Vref Scan: 0
5442 00:39:06.749568
5443 00:39:06.749637 RX Vref 0 -> 0, step: 1
5444 00:39:06.749698
5445 00:39:06.752510 RX Delay -80 -> 252, step: 8
5446 00:39:06.755875 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5447 00:39:06.762840 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5448 00:39:06.765728 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5449 00:39:06.769081 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5450 00:39:06.772623 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5451 00:39:06.775835 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5452 00:39:06.779285 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5453 00:39:06.785879 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5454 00:39:06.789042 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5455 00:39:06.792233 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5456 00:39:06.795649 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5457 00:39:06.799142 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5458 00:39:06.805519 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5459 00:39:06.808934 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5460 00:39:06.812383 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5461 00:39:06.815666 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5462 00:39:06.815747 ==
5463 00:39:06.818952 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 00:39:06.825424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 00:39:06.825531 ==
5466 00:39:06.825628 DQS Delay:
5467 00:39:06.828929 DQS0 = 0, DQS1 = 0
5468 00:39:06.829009 DQM Delay:
5469 00:39:06.829078 DQM0 = 91, DQM1 = 82
5470 00:39:06.832161 DQ Delay:
5471 00:39:06.835495 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5472 00:39:06.838496 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5473 00:39:06.841885 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5474 00:39:06.845240 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5475 00:39:06.845322
5476 00:39:06.845418
5477 00:39:06.845498 ==
5478 00:39:06.848523 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 00:39:06.851927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 00:39:06.852016 ==
5481 00:39:06.852120
5482 00:39:06.852230
5483 00:39:06.855022 TX Vref Scan disable
5484 00:39:06.858478 == TX Byte 0 ==
5485 00:39:06.861887 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5486 00:39:06.865400 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5487 00:39:06.868288 == TX Byte 1 ==
5488 00:39:06.871776 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5489 00:39:06.874788 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5490 00:39:06.874925 ==
5491 00:39:06.878212 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 00:39:06.881679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 00:39:06.885155 ==
5494 00:39:06.885298
5495 00:39:06.885414
5496 00:39:06.885532 TX Vref Scan disable
5497 00:39:06.888478 == TX Byte 0 ==
5498 00:39:06.892006 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5499 00:39:06.898352 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5500 00:39:06.898485 == TX Byte 1 ==
5501 00:39:06.901858 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5502 00:39:06.908695 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5503 00:39:06.908819
5504 00:39:06.908905 [DATLAT]
5505 00:39:06.908984 Freq=933, CH0 RK1
5506 00:39:06.909086
5507 00:39:06.911749 DATLAT Default: 0xb
5508 00:39:06.911859 0, 0xFFFF, sum = 0
5509 00:39:06.915099 1, 0xFFFF, sum = 0
5510 00:39:06.915244 2, 0xFFFF, sum = 0
5511 00:39:06.918363 3, 0xFFFF, sum = 0
5512 00:39:06.921629 4, 0xFFFF, sum = 0
5513 00:39:06.921759 5, 0xFFFF, sum = 0
5514 00:39:06.925319 6, 0xFFFF, sum = 0
5515 00:39:06.925447 7, 0xFFFF, sum = 0
5516 00:39:06.928563 8, 0xFFFF, sum = 0
5517 00:39:06.928707 9, 0xFFFF, sum = 0
5518 00:39:06.931755 10, 0x0, sum = 1
5519 00:39:06.931882 11, 0x0, sum = 2
5520 00:39:06.934852 12, 0x0, sum = 3
5521 00:39:06.934969 13, 0x0, sum = 4
5522 00:39:06.935065 best_step = 11
5523 00:39:06.935164
5524 00:39:06.938138 ==
5525 00:39:06.941661 Dram Type= 6, Freq= 0, CH_0, rank 1
5526 00:39:06.944803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 00:39:06.944890 ==
5528 00:39:06.944954 RX Vref Scan: 0
5529 00:39:06.945042
5530 00:39:06.948280 RX Vref 0 -> 0, step: 1
5531 00:39:06.948409
5532 00:39:06.951615 RX Delay -69 -> 252, step: 4
5533 00:39:06.954959 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5534 00:39:06.961407 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5535 00:39:06.964833 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5536 00:39:06.967820 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5537 00:39:06.971274 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5538 00:39:06.974860 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5539 00:39:06.981541 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5540 00:39:06.984888 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5541 00:39:06.988233 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5542 00:39:06.991012 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5543 00:39:06.994405 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5544 00:39:07.001062 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5545 00:39:07.004531 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5546 00:39:07.007638 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5547 00:39:07.011004 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5548 00:39:07.014481 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5549 00:39:07.014574 ==
5550 00:39:07.017895 Dram Type= 6, Freq= 0, CH_0, rank 1
5551 00:39:07.024260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 00:39:07.024349 ==
5553 00:39:07.024414 DQS Delay:
5554 00:39:07.027955 DQS0 = 0, DQS1 = 0
5555 00:39:07.028041 DQM Delay:
5556 00:39:07.028105 DQM0 = 92, DQM1 = 84
5557 00:39:07.030861 DQ Delay:
5558 00:39:07.034335 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5559 00:39:07.037748 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5560 00:39:07.041107 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =78
5561 00:39:07.044238 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =92
5562 00:39:07.044339
5563 00:39:07.044402
5564 00:39:07.050918 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5565 00:39:07.054534 CH0 RK1: MR19=505, MR18=2B0D
5566 00:39:07.060892 CH0_RK1: MR19=0x505, MR18=0x2B0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5567 00:39:07.064027 [RxdqsGatingPostProcess] freq 933
5568 00:39:07.067393 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5569 00:39:07.070780 best DQS0 dly(2T, 0.5T) = (0, 10)
5570 00:39:07.074349 best DQS1 dly(2T, 0.5T) = (0, 11)
5571 00:39:07.077755 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5572 00:39:07.080661 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5573 00:39:07.084148 best DQS0 dly(2T, 0.5T) = (0, 10)
5574 00:39:07.087630 best DQS1 dly(2T, 0.5T) = (0, 11)
5575 00:39:07.090501 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5576 00:39:07.094019 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5577 00:39:07.097311 Pre-setting of DQS Precalculation
5578 00:39:07.100780 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5579 00:39:07.104006 ==
5580 00:39:07.104118 Dram Type= 6, Freq= 0, CH_1, rank 0
5581 00:39:07.110955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5582 00:39:07.111039 ==
5583 00:39:07.113919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5584 00:39:07.120752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5585 00:39:07.124257 [CA 0] Center 37 (7~68) winsize 62
5586 00:39:07.127767 [CA 1] Center 37 (7~68) winsize 62
5587 00:39:07.130516 [CA 2] Center 34 (5~64) winsize 60
5588 00:39:07.134043 [CA 3] Center 34 (5~64) winsize 60
5589 00:39:07.137140 [CA 4] Center 34 (5~64) winsize 60
5590 00:39:07.140785 [CA 5] Center 34 (4~64) winsize 61
5591 00:39:07.140863
5592 00:39:07.143788 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5593 00:39:07.143866
5594 00:39:07.147506 [CATrainingPosCal] consider 1 rank data
5595 00:39:07.150787 u2DelayCellTimex100 = 270/100 ps
5596 00:39:07.153761 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5597 00:39:07.160763 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5598 00:39:07.163734 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5599 00:39:07.167156 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5600 00:39:07.170699 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5601 00:39:07.173800 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5602 00:39:07.173888
5603 00:39:07.176905 CA PerBit enable=1, Macro0, CA PI delay=34
5604 00:39:07.177044
5605 00:39:07.180801 [CBTSetCACLKResult] CA Dly = 34
5606 00:39:07.180901 CS Dly: 5 (0~36)
5607 00:39:07.183663 ==
5608 00:39:07.187091 Dram Type= 6, Freq= 0, CH_1, rank 1
5609 00:39:07.190644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 00:39:07.190749 ==
5611 00:39:07.194087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5612 00:39:07.200316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5613 00:39:07.204194 [CA 0] Center 37 (8~67) winsize 60
5614 00:39:07.207258 [CA 1] Center 37 (7~68) winsize 62
5615 00:39:07.210557 [CA 2] Center 35 (5~65) winsize 61
5616 00:39:07.213957 [CA 3] Center 34 (4~64) winsize 61
5617 00:39:07.217427 [CA 4] Center 34 (5~64) winsize 60
5618 00:39:07.220846 [CA 5] Center 34 (4~64) winsize 61
5619 00:39:07.220973
5620 00:39:07.224217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5621 00:39:07.224322
5622 00:39:07.227154 [CATrainingPosCal] consider 2 rank data
5623 00:39:07.230578 u2DelayCellTimex100 = 270/100 ps
5624 00:39:07.234055 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5625 00:39:07.240522 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5626 00:39:07.243997 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5627 00:39:07.246902 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5628 00:39:07.250251 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5629 00:39:07.253934 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5630 00:39:07.254055
5631 00:39:07.256979 CA PerBit enable=1, Macro0, CA PI delay=34
5632 00:39:07.257099
5633 00:39:07.260260 [CBTSetCACLKResult] CA Dly = 34
5634 00:39:07.263987 CS Dly: 6 (0~39)
5635 00:39:07.264107
5636 00:39:07.267015 ----->DramcWriteLeveling(PI) begin...
5637 00:39:07.267181 ==
5638 00:39:07.270677 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 00:39:07.273465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 00:39:07.273621 ==
5641 00:39:07.276972 Write leveling (Byte 0): 23 => 23
5642 00:39:07.280470 Write leveling (Byte 1): 29 => 29
5643 00:39:07.283452 DramcWriteLeveling(PI) end<-----
5644 00:39:07.283577
5645 00:39:07.283690 ==
5646 00:39:07.286786 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 00:39:07.290552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 00:39:07.290673 ==
5649 00:39:07.293843 [Gating] SW mode calibration
5650 00:39:07.300135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5651 00:39:07.307147 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5652 00:39:07.310502 0 14 0 | B1->B0 | 302f 3131 | 1 1 | (0 0) (0 0)
5653 00:39:07.313356 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 00:39:07.320416 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 00:39:07.323333 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 00:39:07.326851 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 00:39:07.333468 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 00:39:07.337113 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 00:39:07.339934 0 14 28 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 1)
5660 00:39:07.346802 0 15 0 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
5661 00:39:07.350155 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 00:39:07.353578 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 00:39:07.359899 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 00:39:07.363390 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 00:39:07.366561 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 00:39:07.370031 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 00:39:07.376277 0 15 28 | B1->B0 | 3232 3131 | 0 0 | (1 1) (0 0)
5668 00:39:07.380219 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 00:39:07.383379 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 00:39:07.389493 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 00:39:07.393076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 00:39:07.396095 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 00:39:07.403108 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 00:39:07.406447 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5675 00:39:07.409850 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5676 00:39:07.416067 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5677 00:39:07.419467 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 00:39:07.422854 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 00:39:07.429200 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 00:39:07.432796 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 00:39:07.436319 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 00:39:07.442486 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 00:39:07.445928 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 00:39:07.449272 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 00:39:07.456273 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 00:39:07.459154 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 00:39:07.462546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 00:39:07.469041 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 00:39:07.472447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 00:39:07.475836 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5691 00:39:07.482418 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5692 00:39:07.486269 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5693 00:39:07.489289 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 00:39:07.492624 Total UI for P1: 0, mck2ui 16
5695 00:39:07.495745 best dqsien dly found for B0: ( 1, 2, 30)
5696 00:39:07.498939 Total UI for P1: 0, mck2ui 16
5697 00:39:07.502038 best dqsien dly found for B1: ( 1, 2, 28)
5698 00:39:07.505539 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5699 00:39:07.508677 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5700 00:39:07.508758
5701 00:39:07.515288 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5702 00:39:07.519187 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5703 00:39:07.519277 [Gating] SW calibration Done
5704 00:39:07.522068 ==
5705 00:39:07.525416 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 00:39:07.528766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 00:39:07.528854 ==
5708 00:39:07.528921 RX Vref Scan: 0
5709 00:39:07.528982
5710 00:39:07.532057 RX Vref 0 -> 0, step: 1
5711 00:39:07.532134
5712 00:39:07.535680 RX Delay -80 -> 252, step: 8
5713 00:39:07.538933 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5714 00:39:07.542174 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5715 00:39:07.545511 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5716 00:39:07.551946 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5717 00:39:07.555358 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5718 00:39:07.558980 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5719 00:39:07.561831 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5720 00:39:07.565349 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5721 00:39:07.568831 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5722 00:39:07.575142 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5723 00:39:07.578274 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5724 00:39:07.581667 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5725 00:39:07.585123 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5726 00:39:07.588426 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5727 00:39:07.594957 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5728 00:39:07.598436 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5729 00:39:07.598546 ==
5730 00:39:07.601975 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 00:39:07.605028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:39:07.605112 ==
5733 00:39:07.608542 DQS Delay:
5734 00:39:07.608631 DQS0 = 0, DQS1 = 0
5735 00:39:07.608698 DQM Delay:
5736 00:39:07.611549 DQM0 = 96, DQM1 = 87
5737 00:39:07.611654 DQ Delay:
5738 00:39:07.614704 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5739 00:39:07.617887 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5740 00:39:07.621419 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5741 00:39:07.624610 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5742 00:39:07.624714
5743 00:39:07.624809
5744 00:39:07.624899 ==
5745 00:39:07.628163 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 00:39:07.634879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 00:39:07.634992 ==
5748 00:39:07.635089
5749 00:39:07.635179
5750 00:39:07.635267 TX Vref Scan disable
5751 00:39:07.638322 == TX Byte 0 ==
5752 00:39:07.641554 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5753 00:39:07.644842 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5754 00:39:07.648159 == TX Byte 1 ==
5755 00:39:07.651654 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5756 00:39:07.658621 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5757 00:39:07.658726 ==
5758 00:39:07.661402 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 00:39:07.665023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 00:39:07.665131 ==
5761 00:39:07.665225
5762 00:39:07.665313
5763 00:39:07.668372 TX Vref Scan disable
5764 00:39:07.668469 == TX Byte 0 ==
5765 00:39:07.674830 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5766 00:39:07.678163 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5767 00:39:07.678269 == TX Byte 1 ==
5768 00:39:07.684479 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5769 00:39:07.687970 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5770 00:39:07.688077
5771 00:39:07.688171 [DATLAT]
5772 00:39:07.691379 Freq=933, CH1 RK0
5773 00:39:07.691484
5774 00:39:07.691577 DATLAT Default: 0xd
5775 00:39:07.694672 0, 0xFFFF, sum = 0
5776 00:39:07.694779 1, 0xFFFF, sum = 0
5777 00:39:07.698228 2, 0xFFFF, sum = 0
5778 00:39:07.701649 3, 0xFFFF, sum = 0
5779 00:39:07.701756 4, 0xFFFF, sum = 0
5780 00:39:07.704715 5, 0xFFFF, sum = 0
5781 00:39:07.704821 6, 0xFFFF, sum = 0
5782 00:39:07.707839 7, 0xFFFF, sum = 0
5783 00:39:07.707928 8, 0xFFFF, sum = 0
5784 00:39:07.711395 9, 0xFFFF, sum = 0
5785 00:39:07.711475 10, 0x0, sum = 1
5786 00:39:07.714650 11, 0x0, sum = 2
5787 00:39:07.714745 12, 0x0, sum = 3
5788 00:39:07.714812 13, 0x0, sum = 4
5789 00:39:07.718055 best_step = 11
5790 00:39:07.718135
5791 00:39:07.718199 ==
5792 00:39:07.721226 Dram Type= 6, Freq= 0, CH_1, rank 0
5793 00:39:07.724554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 00:39:07.724678 ==
5795 00:39:07.728049 RX Vref Scan: 1
5796 00:39:07.728157
5797 00:39:07.728251 RX Vref 0 -> 0, step: 1
5798 00:39:07.731465
5799 00:39:07.731544 RX Delay -69 -> 252, step: 4
5800 00:39:07.731615
5801 00:39:07.734454 Set Vref, RX VrefLevel [Byte0]: 56
5802 00:39:07.738227 [Byte1]: 52
5803 00:39:07.742517
5804 00:39:07.742598 Final RX Vref Byte 0 = 56 to rank0
5805 00:39:07.745796 Final RX Vref Byte 1 = 52 to rank0
5806 00:39:07.749030 Final RX Vref Byte 0 = 56 to rank1
5807 00:39:07.752581 Final RX Vref Byte 1 = 52 to rank1==
5808 00:39:07.755782 Dram Type= 6, Freq= 0, CH_1, rank 0
5809 00:39:07.762201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 00:39:07.762288 ==
5811 00:39:07.762374 DQS Delay:
5812 00:39:07.765269 DQS0 = 0, DQS1 = 0
5813 00:39:07.765348 DQM Delay:
5814 00:39:07.765431 DQM0 = 97, DQM1 = 88
5815 00:39:07.768628 DQ Delay:
5816 00:39:07.772163 DQ0 =104, DQ1 =94, DQ2 =84, DQ3 =92
5817 00:39:07.775663 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5818 00:39:07.778521 DQ8 =76, DQ9 =82, DQ10 =86, DQ11 =82
5819 00:39:07.781791 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5820 00:39:07.781872
5821 00:39:07.781936
5822 00:39:07.788661 [DQSOSCAuto] RK0, (LSB)MR18= 0x40d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5823 00:39:07.792223 CH1 RK0: MR19=505, MR18=40D
5824 00:39:07.798410 CH1_RK0: MR19=0x505, MR18=0x40D, DQSOSC=417, MR23=63, INC=62, DEC=41
5825 00:39:07.798487
5826 00:39:07.801818 ----->DramcWriteLeveling(PI) begin...
5827 00:39:07.801919 ==
5828 00:39:07.805440 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 00:39:07.808871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 00:39:07.808957 ==
5831 00:39:07.811915 Write leveling (Byte 0): 27 => 27
5832 00:39:07.815131 Write leveling (Byte 1): 28 => 28
5833 00:39:07.818684 DramcWriteLeveling(PI) end<-----
5834 00:39:07.818763
5835 00:39:07.818825 ==
5836 00:39:07.821966 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 00:39:07.825000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 00:39:07.825084 ==
5839 00:39:07.828467 [Gating] SW mode calibration
5840 00:39:07.834685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5841 00:39:07.841806 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5842 00:39:07.845024 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5843 00:39:07.851581 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 00:39:07.854902 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 00:39:07.857861 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 00:39:07.864840 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 00:39:07.868224 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 00:39:07.871589 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5849 00:39:07.878105 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5850 00:39:07.881489 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 00:39:07.884505 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 00:39:07.887909 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 00:39:07.894685 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 00:39:07.898122 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 00:39:07.901145 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 00:39:07.908015 0 15 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5857 00:39:07.911651 0 15 28 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
5858 00:39:07.914996 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 00:39:07.921388 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 00:39:07.924893 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 00:39:07.927724 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 00:39:07.934462 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 00:39:07.937918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 00:39:07.940832 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5865 00:39:07.947703 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5866 00:39:07.951091 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 00:39:07.954248 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 00:39:07.961199 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 00:39:07.964412 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 00:39:07.967837 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 00:39:07.974630 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 00:39:07.977681 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 00:39:07.981015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 00:39:07.987281 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 00:39:07.990834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 00:39:07.994305 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 00:39:08.000511 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 00:39:08.004083 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 00:39:08.007339 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 00:39:08.013677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5881 00:39:08.017201 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 00:39:08.020659 Total UI for P1: 0, mck2ui 16
5883 00:39:08.024026 best dqsien dly found for B0: ( 1, 2, 24)
5884 00:39:08.027047 Total UI for P1: 0, mck2ui 16
5885 00:39:08.030554 best dqsien dly found for B1: ( 1, 2, 26)
5886 00:39:08.033948 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5887 00:39:08.037421 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5888 00:39:08.037506
5889 00:39:08.040263 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5890 00:39:08.043708 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5891 00:39:08.046971 [Gating] SW calibration Done
5892 00:39:08.047046 ==
5893 00:39:08.050473 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 00:39:08.053981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 00:39:08.057154 ==
5896 00:39:08.057233 RX Vref Scan: 0
5897 00:39:08.057296
5898 00:39:08.060538 RX Vref 0 -> 0, step: 1
5899 00:39:08.060659
5900 00:39:08.063875 RX Delay -80 -> 252, step: 8
5901 00:39:08.067172 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5902 00:39:08.070442 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5903 00:39:08.073879 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5904 00:39:08.076917 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5905 00:39:08.080067 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5906 00:39:08.086684 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5907 00:39:08.090147 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5908 00:39:08.093512 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5909 00:39:08.097005 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5910 00:39:08.100424 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5911 00:39:08.106666 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5912 00:39:08.110090 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5913 00:39:08.113488 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5914 00:39:08.116979 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5915 00:39:08.119774 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5916 00:39:08.126664 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5917 00:39:08.126797 ==
5918 00:39:08.129979 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 00:39:08.133088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 00:39:08.133217 ==
5921 00:39:08.133331 DQS Delay:
5922 00:39:08.136376 DQS0 = 0, DQS1 = 0
5923 00:39:08.136500 DQM Delay:
5924 00:39:08.139920 DQM0 = 93, DQM1 = 87
5925 00:39:08.140046 DQ Delay:
5926 00:39:08.143326 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5927 00:39:08.146640 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5928 00:39:08.149463 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5929 00:39:08.152912 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5930 00:39:08.153036
5931 00:39:08.153151
5932 00:39:08.153257 ==
5933 00:39:08.156364 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 00:39:08.159649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 00:39:08.159774 ==
5936 00:39:08.162954
5937 00:39:08.163084
5938 00:39:08.163196 TX Vref Scan disable
5939 00:39:08.166418 == TX Byte 0 ==
5940 00:39:08.169802 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5941 00:39:08.173038 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5942 00:39:08.176310 == TX Byte 1 ==
5943 00:39:08.179792 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5944 00:39:08.183054 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5945 00:39:08.183189 ==
5946 00:39:08.186167 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 00:39:08.193114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 00:39:08.193209 ==
5949 00:39:08.193277
5950 00:39:08.193338
5951 00:39:08.193402 TX Vref Scan disable
5952 00:39:08.197355 == TX Byte 0 ==
5953 00:39:08.200175 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5954 00:39:08.207047 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5955 00:39:08.207184 == TX Byte 1 ==
5956 00:39:08.209972 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5957 00:39:08.216796 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5958 00:39:08.216916
5959 00:39:08.217031 [DATLAT]
5960 00:39:08.217144 Freq=933, CH1 RK1
5961 00:39:08.217266
5962 00:39:08.220115 DATLAT Default: 0xb
5963 00:39:08.223026 0, 0xFFFF, sum = 0
5964 00:39:08.223152 1, 0xFFFF, sum = 0
5965 00:39:08.226894 2, 0xFFFF, sum = 0
5966 00:39:08.227019 3, 0xFFFF, sum = 0
5967 00:39:08.230260 4, 0xFFFF, sum = 0
5968 00:39:08.230388 5, 0xFFFF, sum = 0
5969 00:39:08.233033 6, 0xFFFF, sum = 0
5970 00:39:08.233156 7, 0xFFFF, sum = 0
5971 00:39:08.236941 8, 0xFFFF, sum = 0
5972 00:39:08.237080 9, 0xFFFF, sum = 0
5973 00:39:08.239895 10, 0x0, sum = 1
5974 00:39:08.240012 11, 0x0, sum = 2
5975 00:39:08.243415 12, 0x0, sum = 3
5976 00:39:08.243540 13, 0x0, sum = 4
5977 00:39:08.243660 best_step = 11
5978 00:39:08.246821
5979 00:39:08.246936 ==
5980 00:39:08.250082 Dram Type= 6, Freq= 0, CH_1, rank 1
5981 00:39:08.252954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5982 00:39:08.253083 ==
5983 00:39:08.253195 RX Vref Scan: 0
5984 00:39:08.253307
5985 00:39:08.256426 RX Vref 0 -> 0, step: 1
5986 00:39:08.256552
5987 00:39:08.259835 RX Delay -69 -> 252, step: 4
5988 00:39:08.266372 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5989 00:39:08.269987 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5990 00:39:08.272915 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5991 00:39:08.276279 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5992 00:39:08.279764 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5993 00:39:08.283111 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5994 00:39:08.289684 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5995 00:39:08.292923 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5996 00:39:08.296007 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5997 00:39:08.299267 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5998 00:39:08.302553 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5999 00:39:08.309223 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6000 00:39:08.313009 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
6001 00:39:08.316201 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
6002 00:39:08.319625 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
6003 00:39:08.322585 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
6004 00:39:08.322695 ==
6005 00:39:08.326004 Dram Type= 6, Freq= 0, CH_1, rank 1
6006 00:39:08.332777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6007 00:39:08.332856 ==
6008 00:39:08.332919 DQS Delay:
6009 00:39:08.332977 DQS0 = 0, DQS1 = 0
6010 00:39:08.335803 DQM Delay:
6011 00:39:08.335876 DQM0 = 91, DQM1 = 91
6012 00:39:08.339185 DQ Delay:
6013 00:39:08.342472 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
6014 00:39:08.345711 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =88
6015 00:39:08.349221 DQ8 =78, DQ9 =84, DQ10 =90, DQ11 =84
6016 00:39:08.352436 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
6017 00:39:08.352546
6018 00:39:08.352643
6019 00:39:08.359266 [DQSOSCAuto] RK1, (LSB)MR18= 0x1325, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
6020 00:39:08.362174 CH1 RK1: MR19=505, MR18=1325
6021 00:39:08.369244 CH1_RK1: MR19=0x505, MR18=0x1325, DQSOSC=410, MR23=63, INC=64, DEC=42
6022 00:39:08.372506 [RxdqsGatingPostProcess] freq 933
6023 00:39:08.375510 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6024 00:39:08.379063 best DQS0 dly(2T, 0.5T) = (0, 10)
6025 00:39:08.382099 best DQS1 dly(2T, 0.5T) = (0, 10)
6026 00:39:08.385465 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6027 00:39:08.388802 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6028 00:39:08.391965 best DQS0 dly(2T, 0.5T) = (0, 10)
6029 00:39:08.395492 best DQS1 dly(2T, 0.5T) = (0, 10)
6030 00:39:08.398927 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6031 00:39:08.402275 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6032 00:39:08.405504 Pre-setting of DQS Precalculation
6033 00:39:08.409050 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6034 00:39:08.418974 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6035 00:39:08.425259 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6036 00:39:08.425343
6037 00:39:08.425408
6038 00:39:08.428984 [Calibration Summary] 1866 Mbps
6039 00:39:08.429066 CH 0, Rank 0
6040 00:39:08.431914 SW Impedance : PASS
6041 00:39:08.431987 DUTY Scan : NO K
6042 00:39:08.435304 ZQ Calibration : PASS
6043 00:39:08.438761 Jitter Meter : NO K
6044 00:39:08.438837 CBT Training : PASS
6045 00:39:08.441640 Write leveling : PASS
6046 00:39:08.445269 RX DQS gating : PASS
6047 00:39:08.445374 RX DQ/DQS(RDDQC) : PASS
6048 00:39:08.448524 TX DQ/DQS : PASS
6049 00:39:08.451548 RX DATLAT : PASS
6050 00:39:08.451662 RX DQ/DQS(Engine): PASS
6051 00:39:08.454823 TX OE : NO K
6052 00:39:08.454901 All Pass.
6053 00:39:08.454970
6054 00:39:08.458359 CH 0, Rank 1
6055 00:39:08.458434 SW Impedance : PASS
6056 00:39:08.461659 DUTY Scan : NO K
6057 00:39:08.465174 ZQ Calibration : PASS
6058 00:39:08.465254 Jitter Meter : NO K
6059 00:39:08.468056 CBT Training : PASS
6060 00:39:08.471520 Write leveling : PASS
6061 00:39:08.471623 RX DQS gating : PASS
6062 00:39:08.475012 RX DQ/DQS(RDDQC) : PASS
6063 00:39:08.475095 TX DQ/DQS : PASS
6064 00:39:08.478317 RX DATLAT : PASS
6065 00:39:08.481308 RX DQ/DQS(Engine): PASS
6066 00:39:08.481412 TX OE : NO K
6067 00:39:08.484707 All Pass.
6068 00:39:08.484793
6069 00:39:08.484858 CH 1, Rank 0
6070 00:39:08.488324 SW Impedance : PASS
6071 00:39:08.488441 DUTY Scan : NO K
6072 00:39:08.491319 ZQ Calibration : PASS
6073 00:39:08.494869 Jitter Meter : NO K
6074 00:39:08.494982 CBT Training : PASS
6075 00:39:08.498343 Write leveling : PASS
6076 00:39:08.501751 RX DQS gating : PASS
6077 00:39:08.501833 RX DQ/DQS(RDDQC) : PASS
6078 00:39:08.505278 TX DQ/DQS : PASS
6079 00:39:08.507928 RX DATLAT : PASS
6080 00:39:08.508030 RX DQ/DQS(Engine): PASS
6081 00:39:08.511693 TX OE : NO K
6082 00:39:08.511765 All Pass.
6083 00:39:08.511825
6084 00:39:08.514510 CH 1, Rank 1
6085 00:39:08.514592 SW Impedance : PASS
6086 00:39:08.517844 DUTY Scan : NO K
6087 00:39:08.521359 ZQ Calibration : PASS
6088 00:39:08.521438 Jitter Meter : NO K
6089 00:39:08.524750 CBT Training : PASS
6090 00:39:08.524844 Write leveling : PASS
6091 00:39:08.528106 RX DQS gating : PASS
6092 00:39:08.531514 RX DQ/DQS(RDDQC) : PASS
6093 00:39:08.531596 TX DQ/DQS : PASS
6094 00:39:08.534696 RX DATLAT : PASS
6095 00:39:08.538304 RX DQ/DQS(Engine): PASS
6096 00:39:08.538431 TX OE : NO K
6097 00:39:08.541705 All Pass.
6098 00:39:08.541842
6099 00:39:08.541953 DramC Write-DBI off
6100 00:39:08.545286 PER_BANK_REFRESH: Hybrid Mode
6101 00:39:08.545409 TX_TRACKING: ON
6102 00:39:08.554821 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6103 00:39:08.557963 [FAST_K] Save calibration result to emmc
6104 00:39:08.561132 dramc_set_vcore_voltage set vcore to 650000
6105 00:39:08.565149 Read voltage for 400, 6
6106 00:39:08.565278 Vio18 = 0
6107 00:39:08.567951 Vcore = 650000
6108 00:39:08.568075 Vdram = 0
6109 00:39:08.568186 Vddq = 0
6110 00:39:08.571473 Vmddr = 0
6111 00:39:08.575021 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6112 00:39:08.581272 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6113 00:39:08.581359 MEM_TYPE=3, freq_sel=20
6114 00:39:08.584963 sv_algorithm_assistance_LP4_800
6115 00:39:08.591163 ============ PULL DRAM RESETB DOWN ============
6116 00:39:08.594570 ========== PULL DRAM RESETB DOWN end =========
6117 00:39:08.597853 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6118 00:39:08.600904 ===================================
6119 00:39:08.604387 LPDDR4 DRAM CONFIGURATION
6120 00:39:08.607701 ===================================
6121 00:39:08.607842 EX_ROW_EN[0] = 0x0
6122 00:39:08.610996 EX_ROW_EN[1] = 0x0
6123 00:39:08.614787 LP4Y_EN = 0x0
6124 00:39:08.614918 WORK_FSP = 0x0
6125 00:39:08.617862 WL = 0x2
6126 00:39:08.617972 RL = 0x2
6127 00:39:08.620778 BL = 0x2
6128 00:39:08.620883 RPST = 0x0
6129 00:39:08.624435 RD_PRE = 0x0
6130 00:39:08.624542 WR_PRE = 0x1
6131 00:39:08.627789 WR_PST = 0x0
6132 00:39:08.627891 DBI_WR = 0x0
6133 00:39:08.631248 DBI_RD = 0x0
6134 00:39:08.631347 OTF = 0x1
6135 00:39:08.634659 ===================================
6136 00:39:08.637594 ===================================
6137 00:39:08.640873 ANA top config
6138 00:39:08.644674 ===================================
6139 00:39:08.644803 DLL_ASYNC_EN = 0
6140 00:39:08.647608 ALL_SLAVE_EN = 1
6141 00:39:08.650960 NEW_RANK_MODE = 1
6142 00:39:08.654546 DLL_IDLE_MODE = 1
6143 00:39:08.658003 LP45_APHY_COMB_EN = 1
6144 00:39:08.658119 TX_ODT_DIS = 1
6145 00:39:08.660781 NEW_8X_MODE = 1
6146 00:39:08.664351 ===================================
6147 00:39:08.667439 ===================================
6148 00:39:08.670878 data_rate = 800
6149 00:39:08.674403 CKR = 1
6150 00:39:08.677906 DQ_P2S_RATIO = 4
6151 00:39:08.681384 ===================================
6152 00:39:08.681490 CA_P2S_RATIO = 4
6153 00:39:08.684154 DQ_CA_OPEN = 0
6154 00:39:08.687638 DQ_SEMI_OPEN = 1
6155 00:39:08.691310 CA_SEMI_OPEN = 1
6156 00:39:08.694061 CA_FULL_RATE = 0
6157 00:39:08.697573 DQ_CKDIV4_EN = 0
6158 00:39:08.697681 CA_CKDIV4_EN = 1
6159 00:39:08.701028 CA_PREDIV_EN = 0
6160 00:39:08.704436 PH8_DLY = 0
6161 00:39:08.707462 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6162 00:39:08.710803 DQ_AAMCK_DIV = 0
6163 00:39:08.714052 CA_AAMCK_DIV = 0
6164 00:39:08.714142 CA_ADMCK_DIV = 4
6165 00:39:08.717508 DQ_TRACK_CA_EN = 0
6166 00:39:08.720998 CA_PICK = 800
6167 00:39:08.724040 CA_MCKIO = 400
6168 00:39:08.727236 MCKIO_SEMI = 400
6169 00:39:08.730418 PLL_FREQ = 3016
6170 00:39:08.734160 DQ_UI_PI_RATIO = 32
6171 00:39:08.737042 CA_UI_PI_RATIO = 32
6172 00:39:08.740875 ===================================
6173 00:39:08.740969 ===================================
6174 00:39:08.743936 memory_type:LPDDR4
6175 00:39:08.747251 GP_NUM : 10
6176 00:39:08.747346 SRAM_EN : 1
6177 00:39:08.750749 MD32_EN : 0
6178 00:39:08.753966 ===================================
6179 00:39:08.756973 [ANA_INIT] >>>>>>>>>>>>>>
6180 00:39:08.760497 <<<<<< [CONFIGURE PHASE]: ANA_TX
6181 00:39:08.763803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6182 00:39:08.767178 ===================================
6183 00:39:08.767299 data_rate = 800,PCW = 0X7400
6184 00:39:08.770444 ===================================
6185 00:39:08.773780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6186 00:39:08.780700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6187 00:39:08.793736 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6188 00:39:08.797228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6189 00:39:08.800649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6190 00:39:08.804078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6191 00:39:08.806956 [ANA_INIT] flow start
6192 00:39:08.807086 [ANA_INIT] PLL >>>>>>>>
6193 00:39:08.810490 [ANA_INIT] PLL <<<<<<<<
6194 00:39:08.813786 [ANA_INIT] MIDPI >>>>>>>>
6195 00:39:08.813868 [ANA_INIT] MIDPI <<<<<<<<
6196 00:39:08.817309 [ANA_INIT] DLL >>>>>>>>
6197 00:39:08.820145 [ANA_INIT] flow end
6198 00:39:08.823629 ============ LP4 DIFF to SE enter ============
6199 00:39:08.827047 ============ LP4 DIFF to SE exit ============
6200 00:39:08.830253 [ANA_INIT] <<<<<<<<<<<<<
6201 00:39:08.833290 [Flow] Enable top DCM control >>>>>
6202 00:39:08.836899 [Flow] Enable top DCM control <<<<<
6203 00:39:08.839936 Enable DLL master slave shuffle
6204 00:39:08.846570 ==============================================================
6205 00:39:08.846708 Gating Mode config
6206 00:39:08.852974 ==============================================================
6207 00:39:08.853099 Config description:
6208 00:39:08.862792 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6209 00:39:08.869928 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6210 00:39:08.876476 SELPH_MODE 0: By rank 1: By Phase
6211 00:39:08.879784 ==============================================================
6212 00:39:08.882628 GAT_TRACK_EN = 0
6213 00:39:08.886034 RX_GATING_MODE = 2
6214 00:39:08.889467 RX_GATING_TRACK_MODE = 2
6215 00:39:08.892961 SELPH_MODE = 1
6216 00:39:08.896183 PICG_EARLY_EN = 1
6217 00:39:08.899687 VALID_LAT_VALUE = 1
6218 00:39:08.906246 ==============================================================
6219 00:39:08.909106 Enter into Gating configuration >>>>
6220 00:39:08.912610 Exit from Gating configuration <<<<
6221 00:39:08.916070 Enter into DVFS_PRE_config >>>>>
6222 00:39:08.925917 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6223 00:39:08.929322 Exit from DVFS_PRE_config <<<<<
6224 00:39:08.932684 Enter into PICG configuration >>>>
6225 00:39:08.936033 Exit from PICG configuration <<<<
6226 00:39:08.936136 [RX_INPUT] configuration >>>>>
6227 00:39:08.939275 [RX_INPUT] configuration <<<<<
6228 00:39:08.945564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6229 00:39:08.952292 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6230 00:39:08.955406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6231 00:39:08.962252 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6232 00:39:08.968690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6233 00:39:08.975379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6234 00:39:08.978926 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6235 00:39:08.981783 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6236 00:39:08.988619 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6237 00:39:08.992073 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6238 00:39:08.995195 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6239 00:39:09.002018 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 00:39:09.005011 ===================================
6241 00:39:09.005140 LPDDR4 DRAM CONFIGURATION
6242 00:39:09.008542 ===================================
6243 00:39:09.011811 EX_ROW_EN[0] = 0x0
6244 00:39:09.011938 EX_ROW_EN[1] = 0x0
6245 00:39:09.015254 LP4Y_EN = 0x0
6246 00:39:09.015380 WORK_FSP = 0x0
6247 00:39:09.018707 WL = 0x2
6248 00:39:09.021515 RL = 0x2
6249 00:39:09.021640 BL = 0x2
6250 00:39:09.025212 RPST = 0x0
6251 00:39:09.025298 RD_PRE = 0x0
6252 00:39:09.028463 WR_PRE = 0x1
6253 00:39:09.028578 WR_PST = 0x0
6254 00:39:09.031963 DBI_WR = 0x0
6255 00:39:09.032040 DBI_RD = 0x0
6256 00:39:09.034984 OTF = 0x1
6257 00:39:09.038266 ===================================
6258 00:39:09.041588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6259 00:39:09.044887 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6260 00:39:09.051762 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6261 00:39:09.051849 ===================================
6262 00:39:09.054667 LPDDR4 DRAM CONFIGURATION
6263 00:39:09.057984 ===================================
6264 00:39:09.061429 EX_ROW_EN[0] = 0x10
6265 00:39:09.061506 EX_ROW_EN[1] = 0x0
6266 00:39:09.064499 LP4Y_EN = 0x0
6267 00:39:09.064609 WORK_FSP = 0x0
6268 00:39:09.068227 WL = 0x2
6269 00:39:09.068333 RL = 0x2
6270 00:39:09.071339 BL = 0x2
6271 00:39:09.074663 RPST = 0x0
6272 00:39:09.074741 RD_PRE = 0x0
6273 00:39:09.078239 WR_PRE = 0x1
6274 00:39:09.078315 WR_PST = 0x0
6275 00:39:09.081329 DBI_WR = 0x0
6276 00:39:09.081434 DBI_RD = 0x0
6277 00:39:09.084676 OTF = 0x1
6278 00:39:09.088133 ===================================
6279 00:39:09.094202 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6280 00:39:09.097678 nWR fixed to 30
6281 00:39:09.097787 [ModeRegInit_LP4] CH0 RK0
6282 00:39:09.100918 [ModeRegInit_LP4] CH0 RK1
6283 00:39:09.104256 [ModeRegInit_LP4] CH1 RK0
6284 00:39:09.104379 [ModeRegInit_LP4] CH1 RK1
6285 00:39:09.107821 match AC timing 19
6286 00:39:09.110905 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6287 00:39:09.114342 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6288 00:39:09.121400 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6289 00:39:09.124235 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6290 00:39:09.131148 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6291 00:39:09.131233 ==
6292 00:39:09.134480 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 00:39:09.137539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 00:39:09.137627 ==
6295 00:39:09.144375 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6296 00:39:09.147673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6297 00:39:09.150854 [CA 0] Center 36 (8~64) winsize 57
6298 00:39:09.154187 [CA 1] Center 36 (8~64) winsize 57
6299 00:39:09.157607 [CA 2] Center 36 (8~64) winsize 57
6300 00:39:09.161123 [CA 3] Center 36 (8~64) winsize 57
6301 00:39:09.163980 [CA 4] Center 36 (8~64) winsize 57
6302 00:39:09.167309 [CA 5] Center 36 (8~64) winsize 57
6303 00:39:09.167408
6304 00:39:09.170642 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6305 00:39:09.170721
6306 00:39:09.174074 [CATrainingPosCal] consider 1 rank data
6307 00:39:09.177573 u2DelayCellTimex100 = 270/100 ps
6308 00:39:09.180796 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 00:39:09.183802 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 00:39:09.190331 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 00:39:09.193749 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 00:39:09.197087 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 00:39:09.200486 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 00:39:09.200596
6315 00:39:09.204006 CA PerBit enable=1, Macro0, CA PI delay=36
6316 00:39:09.204126
6317 00:39:09.207364 [CBTSetCACLKResult] CA Dly = 36
6318 00:39:09.207448 CS Dly: 1 (0~32)
6319 00:39:09.210404 ==
6320 00:39:09.210498 Dram Type= 6, Freq= 0, CH_0, rank 1
6321 00:39:09.216947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 00:39:09.217034 ==
6323 00:39:09.220575 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6324 00:39:09.226895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6325 00:39:09.230055 [CA 0] Center 36 (8~64) winsize 57
6326 00:39:09.233554 [CA 1] Center 36 (8~64) winsize 57
6327 00:39:09.237088 [CA 2] Center 36 (8~64) winsize 57
6328 00:39:09.240402 [CA 3] Center 36 (8~64) winsize 57
6329 00:39:09.243856 [CA 4] Center 36 (8~64) winsize 57
6330 00:39:09.246702 [CA 5] Center 36 (8~64) winsize 57
6331 00:39:09.246787
6332 00:39:09.250056 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6333 00:39:09.250142
6334 00:39:09.253530 [CATrainingPosCal] consider 2 rank data
6335 00:39:09.256704 u2DelayCellTimex100 = 270/100 ps
6336 00:39:09.260054 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 00:39:09.263485 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 00:39:09.266457 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 00:39:09.269949 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 00:39:09.276498 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 00:39:09.279969 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 00:39:09.280057
6343 00:39:09.283447 CA PerBit enable=1, Macro0, CA PI delay=36
6344 00:39:09.283561
6345 00:39:09.286930 [CBTSetCACLKResult] CA Dly = 36
6346 00:39:09.287015 CS Dly: 1 (0~32)
6347 00:39:09.287079
6348 00:39:09.290099 ----->DramcWriteLeveling(PI) begin...
6349 00:39:09.290177 ==
6350 00:39:09.293353 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 00:39:09.299749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 00:39:09.299836 ==
6353 00:39:09.303442 Write leveling (Byte 0): 40 => 8
6354 00:39:09.303552 Write leveling (Byte 1): 40 => 8
6355 00:39:09.306637 DramcWriteLeveling(PI) end<-----
6356 00:39:09.306721
6357 00:39:09.306788 ==
6358 00:39:09.310169 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 00:39:09.316889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 00:39:09.317011 ==
6361 00:39:09.320070 [Gating] SW mode calibration
6362 00:39:09.326265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6363 00:39:09.329823 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6364 00:39:09.336174 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6365 00:39:09.339660 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6366 00:39:09.342800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 00:39:09.349628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6368 00:39:09.353120 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 00:39:09.355929 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 00:39:09.363100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 00:39:09.365931 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 00:39:09.369326 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6373 00:39:09.372823 Total UI for P1: 0, mck2ui 16
6374 00:39:09.376072 best dqsien dly found for B0: ( 0, 14, 24)
6375 00:39:09.379413 Total UI for P1: 0, mck2ui 16
6376 00:39:09.382914 best dqsien dly found for B1: ( 0, 14, 24)
6377 00:39:09.385772 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6378 00:39:09.389266 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6379 00:39:09.389351
6380 00:39:09.396135 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6381 00:39:09.399042 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6382 00:39:09.399126 [Gating] SW calibration Done
6383 00:39:09.402408 ==
6384 00:39:09.405810 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 00:39:09.409317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 00:39:09.409402 ==
6387 00:39:09.409467 RX Vref Scan: 0
6388 00:39:09.409527
6389 00:39:09.412222 RX Vref 0 -> 0, step: 1
6390 00:39:09.412305
6391 00:39:09.415644 RX Delay -410 -> 252, step: 16
6392 00:39:09.419065 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6393 00:39:09.422524 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6394 00:39:09.428809 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6395 00:39:09.432350 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6396 00:39:09.435611 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6397 00:39:09.438943 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6398 00:39:09.445610 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6399 00:39:09.448671 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6400 00:39:09.452146 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6401 00:39:09.455399 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6402 00:39:09.462281 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6403 00:39:09.465609 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6404 00:39:09.469093 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6405 00:39:09.475326 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6406 00:39:09.478804 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6407 00:39:09.482002 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6408 00:39:09.482117 ==
6409 00:39:09.485500 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 00:39:09.488465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 00:39:09.491899 ==
6412 00:39:09.492016 DQS Delay:
6413 00:39:09.492110 DQS0 = 59, DQS1 = 59
6414 00:39:09.495320 DQM Delay:
6415 00:39:09.495436 DQM0 = 18, DQM1 = 10
6416 00:39:09.498931 DQ Delay:
6417 00:39:09.499037 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6418 00:39:09.501656 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6419 00:39:09.505205 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6420 00:39:09.508766 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6421 00:39:09.508848
6422 00:39:09.508911
6423 00:39:09.512143 ==
6424 00:39:09.515048 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 00:39:09.518360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 00:39:09.518449 ==
6427 00:39:09.518516
6428 00:39:09.518575
6429 00:39:09.521665 TX Vref Scan disable
6430 00:39:09.521767 == TX Byte 0 ==
6431 00:39:09.524970 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 00:39:09.531619 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 00:39:09.531718 == TX Byte 1 ==
6434 00:39:09.534768 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 00:39:09.541428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 00:39:09.541518 ==
6437 00:39:09.545165 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 00:39:09.548333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 00:39:09.548443 ==
6440 00:39:09.548536
6441 00:39:09.548620
6442 00:39:09.551729 TX Vref Scan disable
6443 00:39:09.551825 == TX Byte 0 ==
6444 00:39:09.554923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6445 00:39:09.561824 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6446 00:39:09.561903 == TX Byte 1 ==
6447 00:39:09.564677 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6448 00:39:09.571587 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6449 00:39:09.571697
6450 00:39:09.571801 [DATLAT]
6451 00:39:09.571890 Freq=400, CH0 RK0
6452 00:39:09.571978
6453 00:39:09.574414 DATLAT Default: 0xf
6454 00:39:09.578035 0, 0xFFFF, sum = 0
6455 00:39:09.578108 1, 0xFFFF, sum = 0
6456 00:39:09.581418 2, 0xFFFF, sum = 0
6457 00:39:09.581490 3, 0xFFFF, sum = 0
6458 00:39:09.584901 4, 0xFFFF, sum = 0
6459 00:39:09.584995 5, 0xFFFF, sum = 0
6460 00:39:09.588283 6, 0xFFFF, sum = 0
6461 00:39:09.588388 7, 0xFFFF, sum = 0
6462 00:39:09.591261 8, 0xFFFF, sum = 0
6463 00:39:09.591374 9, 0xFFFF, sum = 0
6464 00:39:09.594812 10, 0xFFFF, sum = 0
6465 00:39:09.594925 11, 0xFFFF, sum = 0
6466 00:39:09.598152 12, 0xFFFF, sum = 0
6467 00:39:09.598259 13, 0x0, sum = 1
6468 00:39:09.601501 14, 0x0, sum = 2
6469 00:39:09.601608 15, 0x0, sum = 3
6470 00:39:09.604427 16, 0x0, sum = 4
6471 00:39:09.604534 best_step = 14
6472 00:39:09.604648
6473 00:39:09.604730 ==
6474 00:39:09.607953 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 00:39:09.614709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 00:39:09.614826 ==
6477 00:39:09.614933 RX Vref Scan: 1
6478 00:39:09.615025
6479 00:39:09.617660 RX Vref 0 -> 0, step: 1
6480 00:39:09.617769
6481 00:39:09.621067 RX Delay -359 -> 252, step: 8
6482 00:39:09.621146
6483 00:39:09.624339 Set Vref, RX VrefLevel [Byte0]: 60
6484 00:39:09.627647 [Byte1]: 55
6485 00:39:09.627758
6486 00:39:09.631266 Final RX Vref Byte 0 = 60 to rank0
6487 00:39:09.634072 Final RX Vref Byte 1 = 55 to rank0
6488 00:39:09.637859 Final RX Vref Byte 0 = 60 to rank1
6489 00:39:09.641022 Final RX Vref Byte 1 = 55 to rank1==
6490 00:39:09.644296 Dram Type= 6, Freq= 0, CH_0, rank 0
6491 00:39:09.647550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 00:39:09.650781 ==
6493 00:39:09.650865 DQS Delay:
6494 00:39:09.650939 DQS0 = 60, DQS1 = 68
6495 00:39:09.654395 DQM Delay:
6496 00:39:09.654507 DQM0 = 14, DQM1 = 13
6497 00:39:09.657513 DQ Delay:
6498 00:39:09.660523 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6499 00:39:09.660641 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6500 00:39:09.663861 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6501 00:39:09.667477 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6502 00:39:09.667558
6503 00:39:09.670756
6504 00:39:09.677128 [DQSOSCAuto] RK0, (LSB)MR18= 0x8582, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6505 00:39:09.680735 CH0 RK0: MR19=C0C, MR18=8582
6506 00:39:09.687101 CH0_RK0: MR19=0xC0C, MR18=0x8582, DQSOSC=393, MR23=63, INC=382, DEC=254
6507 00:39:09.687191 ==
6508 00:39:09.690596 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 00:39:09.693613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 00:39:09.693695 ==
6511 00:39:09.697165 [Gating] SW mode calibration
6512 00:39:09.704188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6513 00:39:09.707096 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6514 00:39:09.713664 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6515 00:39:09.717196 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6516 00:39:09.720781 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 00:39:09.727012 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 00:39:09.730392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 00:39:09.733803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 00:39:09.740248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 00:39:09.743717 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 00:39:09.747024 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6523 00:39:09.750645 Total UI for P1: 0, mck2ui 16
6524 00:39:09.753653 best dqsien dly found for B0: ( 0, 14, 24)
6525 00:39:09.757120 Total UI for P1: 0, mck2ui 16
6526 00:39:09.760596 best dqsien dly found for B1: ( 0, 14, 24)
6527 00:39:09.763681 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6528 00:39:09.767102 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6529 00:39:09.770476
6530 00:39:09.773611 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6531 00:39:09.776749 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6532 00:39:09.779899 [Gating] SW calibration Done
6533 00:39:09.779979 ==
6534 00:39:09.783407 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 00:39:09.786532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 00:39:09.786643 ==
6537 00:39:09.786749 RX Vref Scan: 0
6538 00:39:09.790116
6539 00:39:09.790222 RX Vref 0 -> 0, step: 1
6540 00:39:09.790320
6541 00:39:09.793370 RX Delay -410 -> 252, step: 16
6542 00:39:09.796581 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6543 00:39:09.803374 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6544 00:39:09.806969 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6545 00:39:09.809763 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6546 00:39:09.813349 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6547 00:39:09.820192 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6548 00:39:09.823061 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6549 00:39:09.826518 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6550 00:39:09.829447 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6551 00:39:09.836209 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6552 00:39:09.839590 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6553 00:39:09.843165 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6554 00:39:09.849329 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6555 00:39:09.852929 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6556 00:39:09.856173 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6557 00:39:09.859574 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6558 00:39:09.859680 ==
6559 00:39:09.862414 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 00:39:09.869314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 00:39:09.869424 ==
6562 00:39:09.869518 DQS Delay:
6563 00:39:09.872805 DQS0 = 59, DQS1 = 59
6564 00:39:09.872937 DQM Delay:
6565 00:39:09.875982 DQM0 = 16, DQM1 = 10
6566 00:39:09.876105 DQ Delay:
6567 00:39:09.879471 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6568 00:39:09.882378 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6569 00:39:09.885565 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6570 00:39:09.889514 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6571 00:39:09.889627
6572 00:39:09.889737
6573 00:39:09.889838 ==
6574 00:39:09.892263 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 00:39:09.895577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 00:39:09.895658 ==
6577 00:39:09.895728
6578 00:39:09.895791
6579 00:39:09.899066 TX Vref Scan disable
6580 00:39:09.899142 == TX Byte 0 ==
6581 00:39:09.905252 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6582 00:39:09.908967 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6583 00:39:09.909048 == TX Byte 1 ==
6584 00:39:09.915122 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6585 00:39:09.918565 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6586 00:39:09.918644 ==
6587 00:39:09.922051 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 00:39:09.925376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 00:39:09.925453 ==
6590 00:39:09.925528
6591 00:39:09.925587
6592 00:39:09.928885 TX Vref Scan disable
6593 00:39:09.928958 == TX Byte 0 ==
6594 00:39:09.935137 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6595 00:39:09.938588 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6596 00:39:09.938668 == TX Byte 1 ==
6597 00:39:09.945472 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6598 00:39:09.948757 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6599 00:39:09.948835
6600 00:39:09.948904 [DATLAT]
6601 00:39:09.951606 Freq=400, CH0 RK1
6602 00:39:09.951678
6603 00:39:09.951738 DATLAT Default: 0xe
6604 00:39:09.955633 0, 0xFFFF, sum = 0
6605 00:39:09.955708 1, 0xFFFF, sum = 0
6606 00:39:09.958389 2, 0xFFFF, sum = 0
6607 00:39:09.958463 3, 0xFFFF, sum = 0
6608 00:39:09.961794 4, 0xFFFF, sum = 0
6609 00:39:09.961899 5, 0xFFFF, sum = 0
6610 00:39:09.965281 6, 0xFFFF, sum = 0
6611 00:39:09.965355 7, 0xFFFF, sum = 0
6612 00:39:09.968462 8, 0xFFFF, sum = 0
6613 00:39:09.971460 9, 0xFFFF, sum = 0
6614 00:39:09.971535 10, 0xFFFF, sum = 0
6615 00:39:09.974816 11, 0xFFFF, sum = 0
6616 00:39:09.974892 12, 0xFFFF, sum = 0
6617 00:39:09.978501 13, 0x0, sum = 1
6618 00:39:09.978579 14, 0x0, sum = 2
6619 00:39:09.981767 15, 0x0, sum = 3
6620 00:39:09.981840 16, 0x0, sum = 4
6621 00:39:09.981901 best_step = 14
6622 00:39:09.985310
6623 00:39:09.985388 ==
6624 00:39:09.988129 Dram Type= 6, Freq= 0, CH_0, rank 1
6625 00:39:09.991366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 00:39:09.991471 ==
6627 00:39:09.991567 RX Vref Scan: 0
6628 00:39:09.991655
6629 00:39:09.994850 RX Vref 0 -> 0, step: 1
6630 00:39:09.994924
6631 00:39:09.998083 RX Delay -359 -> 252, step: 8
6632 00:39:10.005447 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6633 00:39:10.008769 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6634 00:39:10.011921 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6635 00:39:10.015179 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6636 00:39:10.022399 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6637 00:39:10.025115 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6638 00:39:10.028604 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6639 00:39:10.032017 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6640 00:39:10.038246 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6641 00:39:10.041811 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6642 00:39:10.045231 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6643 00:39:10.052103 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6644 00:39:10.054920 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6645 00:39:10.058265 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6646 00:39:10.061751 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6647 00:39:10.068626 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6648 00:39:10.068732 ==
6649 00:39:10.071569 Dram Type= 6, Freq= 0, CH_0, rank 1
6650 00:39:10.074918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 00:39:10.074999 ==
6652 00:39:10.075061 DQS Delay:
6653 00:39:10.078352 DQS0 = 60, DQS1 = 72
6654 00:39:10.078425 DQM Delay:
6655 00:39:10.081850 DQM0 = 11, DQM1 = 18
6656 00:39:10.081922 DQ Delay:
6657 00:39:10.084743 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6658 00:39:10.088488 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6659 00:39:10.091577 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6660 00:39:10.094965 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6661 00:39:10.095040
6662 00:39:10.095104
6663 00:39:10.101506 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6664 00:39:10.105113 CH0 RK1: MR19=C0C, MR18=C87E
6665 00:39:10.111744 CH0_RK1: MR19=0xC0C, MR18=0xC87E, DQSOSC=385, MR23=63, INC=398, DEC=265
6666 00:39:10.114887 [RxdqsGatingPostProcess] freq 400
6667 00:39:10.121304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6668 00:39:10.124930 best DQS0 dly(2T, 0.5T) = (0, 10)
6669 00:39:10.125019 best DQS1 dly(2T, 0.5T) = (0, 10)
6670 00:39:10.127919 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6671 00:39:10.131169 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6672 00:39:10.134768 best DQS0 dly(2T, 0.5T) = (0, 10)
6673 00:39:10.137997 best DQS1 dly(2T, 0.5T) = (0, 10)
6674 00:39:10.141367 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6675 00:39:10.144896 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6676 00:39:10.148239 Pre-setting of DQS Precalculation
6677 00:39:10.154413 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6678 00:39:10.154526 ==
6679 00:39:10.157945 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 00:39:10.161493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 00:39:10.161575 ==
6682 00:39:10.167808 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6683 00:39:10.171157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6684 00:39:10.174588 [CA 0] Center 36 (8~64) winsize 57
6685 00:39:10.178059 [CA 1] Center 36 (8~64) winsize 57
6686 00:39:10.180872 [CA 2] Center 36 (8~64) winsize 57
6687 00:39:10.184273 [CA 3] Center 36 (8~64) winsize 57
6688 00:39:10.187693 [CA 4] Center 36 (8~64) winsize 57
6689 00:39:10.191126 [CA 5] Center 36 (8~64) winsize 57
6690 00:39:10.191238
6691 00:39:10.194386 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6692 00:39:10.194487
6693 00:39:10.197871 [CATrainingPosCal] consider 1 rank data
6694 00:39:10.201230 u2DelayCellTimex100 = 270/100 ps
6695 00:39:10.204472 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 00:39:10.207904 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 00:39:10.213895 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 00:39:10.217380 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 00:39:10.220707 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 00:39:10.224212 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 00:39:10.224297
6702 00:39:10.227480 CA PerBit enable=1, Macro0, CA PI delay=36
6703 00:39:10.227566
6704 00:39:10.230875 [CBTSetCACLKResult] CA Dly = 36
6705 00:39:10.230961 CS Dly: 1 (0~32)
6706 00:39:10.233657 ==
6707 00:39:10.236953 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 00:39:10.240397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 00:39:10.240482 ==
6710 00:39:10.243939 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6711 00:39:10.250719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6712 00:39:10.254368 [CA 0] Center 36 (8~64) winsize 57
6713 00:39:10.257552 [CA 1] Center 36 (8~64) winsize 57
6714 00:39:10.260577 [CA 2] Center 36 (8~64) winsize 57
6715 00:39:10.263539 [CA 3] Center 36 (8~64) winsize 57
6716 00:39:10.266908 [CA 4] Center 36 (8~64) winsize 57
6717 00:39:10.270370 [CA 5] Center 36 (8~64) winsize 57
6718 00:39:10.270449
6719 00:39:10.273730 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6720 00:39:10.273834
6721 00:39:10.277158 [CATrainingPosCal] consider 2 rank data
6722 00:39:10.280150 u2DelayCellTimex100 = 270/100 ps
6723 00:39:10.284070 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 00:39:10.286952 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 00:39:10.290403 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 00:39:10.293831 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 00:39:10.297281 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 00:39:10.303436 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 00:39:10.303516
6730 00:39:10.306729 CA PerBit enable=1, Macro0, CA PI delay=36
6731 00:39:10.306845
6732 00:39:10.310309 [CBTSetCACLKResult] CA Dly = 36
6733 00:39:10.310434 CS Dly: 1 (0~32)
6734 00:39:10.310549
6735 00:39:10.313423 ----->DramcWriteLeveling(PI) begin...
6736 00:39:10.313556 ==
6737 00:39:10.316886 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 00:39:10.323258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 00:39:10.323391 ==
6740 00:39:10.326562 Write leveling (Byte 0): 40 => 8
6741 00:39:10.326695 Write leveling (Byte 1): 40 => 8
6742 00:39:10.329810 DramcWriteLeveling(PI) end<-----
6743 00:39:10.329945
6744 00:39:10.330062 ==
6745 00:39:10.333184 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 00:39:10.340142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 00:39:10.340255 ==
6748 00:39:10.342925 [Gating] SW mode calibration
6749 00:39:10.350155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6750 00:39:10.353139 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6751 00:39:10.359867 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6752 00:39:10.363002 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6753 00:39:10.366492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 00:39:10.373137 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6755 00:39:10.376469 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 00:39:10.379407 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 00:39:10.386217 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 00:39:10.389581 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 00:39:10.392962 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6760 00:39:10.396400 Total UI for P1: 0, mck2ui 16
6761 00:39:10.399307 best dqsien dly found for B0: ( 0, 14, 24)
6762 00:39:10.402670 Total UI for P1: 0, mck2ui 16
6763 00:39:10.406188 best dqsien dly found for B1: ( 0, 14, 24)
6764 00:39:10.409784 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6765 00:39:10.412734 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6766 00:39:10.412818
6767 00:39:10.419171 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6768 00:39:10.422393 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6769 00:39:10.422502 [Gating] SW calibration Done
6770 00:39:10.425919 ==
6771 00:39:10.429073 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 00:39:10.432618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 00:39:10.432694 ==
6774 00:39:10.432773 RX Vref Scan: 0
6775 00:39:10.432833
6776 00:39:10.435787 RX Vref 0 -> 0, step: 1
6777 00:39:10.435863
6778 00:39:10.438949 RX Delay -410 -> 252, step: 16
6779 00:39:10.442354 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6780 00:39:10.449175 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6781 00:39:10.452524 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6782 00:39:10.455853 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6783 00:39:10.459049 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6784 00:39:10.465925 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6785 00:39:10.468984 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6786 00:39:10.472171 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6787 00:39:10.475517 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6788 00:39:10.482348 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6789 00:39:10.485341 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6790 00:39:10.488789 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6791 00:39:10.492117 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6792 00:39:10.498829 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6793 00:39:10.502167 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6794 00:39:10.505747 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6795 00:39:10.505864 ==
6796 00:39:10.508538 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 00:39:10.512072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 00:39:10.515598 ==
6799 00:39:10.515681 DQS Delay:
6800 00:39:10.515745 DQS0 = 51, DQS1 = 67
6801 00:39:10.518391 DQM Delay:
6802 00:39:10.518473 DQM0 = 13, DQM1 = 18
6803 00:39:10.522255 DQ Delay:
6804 00:39:10.525118 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6805 00:39:10.525201 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6806 00:39:10.528492 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6807 00:39:10.531891 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6808 00:39:10.531973
6809 00:39:10.532036
6810 00:39:10.535357 ==
6811 00:39:10.538322 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 00:39:10.541514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 00:39:10.541597 ==
6814 00:39:10.541662
6815 00:39:10.541720
6816 00:39:10.545247 TX Vref Scan disable
6817 00:39:10.545331 == TX Byte 0 ==
6818 00:39:10.548473 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 00:39:10.555234 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 00:39:10.555346 == TX Byte 1 ==
6821 00:39:10.558310 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 00:39:10.564995 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 00:39:10.565078 ==
6824 00:39:10.568186 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 00:39:10.571800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 00:39:10.571910 ==
6827 00:39:10.572006
6828 00:39:10.572091
6829 00:39:10.574619 TX Vref Scan disable
6830 00:39:10.574704 == TX Byte 0 ==
6831 00:39:10.578268 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6832 00:39:10.584427 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6833 00:39:10.584510 == TX Byte 1 ==
6834 00:39:10.587894 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6835 00:39:10.594380 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6836 00:39:10.594465
6837 00:39:10.594531 [DATLAT]
6838 00:39:10.598160 Freq=400, CH1 RK0
6839 00:39:10.598244
6840 00:39:10.598308 DATLAT Default: 0xf
6841 00:39:10.601219 0, 0xFFFF, sum = 0
6842 00:39:10.601303 1, 0xFFFF, sum = 0
6843 00:39:10.604834 2, 0xFFFF, sum = 0
6844 00:39:10.604917 3, 0xFFFF, sum = 0
6845 00:39:10.607776 4, 0xFFFF, sum = 0
6846 00:39:10.607860 5, 0xFFFF, sum = 0
6847 00:39:10.611231 6, 0xFFFF, sum = 0
6848 00:39:10.611314 7, 0xFFFF, sum = 0
6849 00:39:10.614705 8, 0xFFFF, sum = 0
6850 00:39:10.614789 9, 0xFFFF, sum = 0
6851 00:39:10.617521 10, 0xFFFF, sum = 0
6852 00:39:10.617604 11, 0xFFFF, sum = 0
6853 00:39:10.621018 12, 0xFFFF, sum = 0
6854 00:39:10.621101 13, 0x0, sum = 1
6855 00:39:10.624273 14, 0x0, sum = 2
6856 00:39:10.624383 15, 0x0, sum = 3
6857 00:39:10.627655 16, 0x0, sum = 4
6858 00:39:10.627739 best_step = 14
6859 00:39:10.627803
6860 00:39:10.627862 ==
6861 00:39:10.631077 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 00:39:10.637373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 00:39:10.637456 ==
6864 00:39:10.637520 RX Vref Scan: 1
6865 00:39:10.637580
6866 00:39:10.641050 RX Vref 0 -> 0, step: 1
6867 00:39:10.641132
6868 00:39:10.644197 RX Delay -375 -> 252, step: 8
6869 00:39:10.644280
6870 00:39:10.647451 Set Vref, RX VrefLevel [Byte0]: 56
6871 00:39:10.650800 [Byte1]: 52
6872 00:39:10.650886
6873 00:39:10.654162 Final RX Vref Byte 0 = 56 to rank0
6874 00:39:10.657457 Final RX Vref Byte 1 = 52 to rank0
6875 00:39:10.660824 Final RX Vref Byte 0 = 56 to rank1
6876 00:39:10.664284 Final RX Vref Byte 1 = 52 to rank1==
6877 00:39:10.667761 Dram Type= 6, Freq= 0, CH_1, rank 0
6878 00:39:10.673958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 00:39:10.674046 ==
6880 00:39:10.674110 DQS Delay:
6881 00:39:10.674169 DQS0 = 56, DQS1 = 64
6882 00:39:10.677198 DQM Delay:
6883 00:39:10.677284 DQM0 = 13, DQM1 = 10
6884 00:39:10.680679 DQ Delay:
6885 00:39:10.683998 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6886 00:39:10.684084 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6887 00:39:10.687415 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6888 00:39:10.690264 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6889 00:39:10.690347
6890 00:39:10.693716
6891 00:39:10.700482 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6892 00:39:10.703972 CH1 RK0: MR19=C0C, MR18=5D71
6893 00:39:10.710496 CH1_RK0: MR19=0xC0C, MR18=0x5D71, DQSOSC=395, MR23=63, INC=378, DEC=252
6894 00:39:10.710601 ==
6895 00:39:10.713571 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 00:39:10.717129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 00:39:10.717235 ==
6898 00:39:10.720495 [Gating] SW mode calibration
6899 00:39:10.726826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6900 00:39:10.733515 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6901 00:39:10.736865 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6902 00:39:10.740340 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6903 00:39:10.746552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 00:39:10.749832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6905 00:39:10.753299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 00:39:10.760312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 00:39:10.763495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 00:39:10.766849 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 00:39:10.773118 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6910 00:39:10.773205 Total UI for P1: 0, mck2ui 16
6911 00:39:10.776564 best dqsien dly found for B0: ( 0, 14, 24)
6912 00:39:10.780046 Total UI for P1: 0, mck2ui 16
6913 00:39:10.783291 best dqsien dly found for B1: ( 0, 14, 24)
6914 00:39:10.789611 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6915 00:39:10.793508 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6916 00:39:10.793596
6917 00:39:10.796228 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6918 00:39:10.799657 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6919 00:39:10.803024 [Gating] SW calibration Done
6920 00:39:10.803097 ==
6921 00:39:10.806523 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 00:39:10.809911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 00:39:10.810015 ==
6924 00:39:10.812917 RX Vref Scan: 0
6925 00:39:10.812989
6926 00:39:10.813057 RX Vref 0 -> 0, step: 1
6927 00:39:10.813122
6928 00:39:10.816182 RX Delay -410 -> 252, step: 16
6929 00:39:10.819656 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6930 00:39:10.826497 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6931 00:39:10.829497 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6932 00:39:10.833158 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6933 00:39:10.836621 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6934 00:39:10.843029 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6935 00:39:10.845913 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6936 00:39:10.849171 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6937 00:39:10.855914 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6938 00:39:10.859430 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6939 00:39:10.862894 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6940 00:39:10.866349 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6941 00:39:10.872907 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6942 00:39:10.875658 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6943 00:39:10.879146 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6944 00:39:10.882520 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6945 00:39:10.885981 ==
6946 00:39:10.886112 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 00:39:10.892205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 00:39:10.892343 ==
6949 00:39:10.892459 DQS Delay:
6950 00:39:10.895593 DQS0 = 59, DQS1 = 59
6951 00:39:10.895720 DQM Delay:
6952 00:39:10.899148 DQM0 = 19, DQM1 = 13
6953 00:39:10.899272 DQ Delay:
6954 00:39:10.902749 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6955 00:39:10.906100 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6956 00:39:10.908935 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6957 00:39:10.912529 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6958 00:39:10.912667
6959 00:39:10.912787
6960 00:39:10.912902 ==
6961 00:39:10.915827 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 00:39:10.918748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 00:39:10.918871 ==
6964 00:39:10.918982
6965 00:39:10.919086
6966 00:39:10.922246 TX Vref Scan disable
6967 00:39:10.922375 == TX Byte 0 ==
6968 00:39:10.929159 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6969 00:39:10.932317 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6970 00:39:10.932451 == TX Byte 1 ==
6971 00:39:10.938658 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6972 00:39:10.942161 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6973 00:39:10.942292 ==
6974 00:39:10.945359 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 00:39:10.948814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 00:39:10.948942 ==
6977 00:39:10.949035
6978 00:39:10.949134
6979 00:39:10.952078 TX Vref Scan disable
6980 00:39:10.952181 == TX Byte 0 ==
6981 00:39:10.958818 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6982 00:39:10.961993 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6983 00:39:10.962099 == TX Byte 1 ==
6984 00:39:10.968572 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6985 00:39:10.971847 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6986 00:39:10.971932
6987 00:39:10.971998 [DATLAT]
6988 00:39:10.975156 Freq=400, CH1 RK1
6989 00:39:10.975233
6990 00:39:10.975303 DATLAT Default: 0xe
6991 00:39:10.978379 0, 0xFFFF, sum = 0
6992 00:39:10.978457 1, 0xFFFF, sum = 0
6993 00:39:10.982005 2, 0xFFFF, sum = 0
6994 00:39:10.982123 3, 0xFFFF, sum = 0
6995 00:39:10.985375 4, 0xFFFF, sum = 0
6996 00:39:10.985480 5, 0xFFFF, sum = 0
6997 00:39:10.988856 6, 0xFFFF, sum = 0
6998 00:39:10.988937 7, 0xFFFF, sum = 0
6999 00:39:10.991884 8, 0xFFFF, sum = 0
7000 00:39:10.991957 9, 0xFFFF, sum = 0
7001 00:39:10.995261 10, 0xFFFF, sum = 0
7002 00:39:10.998899 11, 0xFFFF, sum = 0
7003 00:39:10.999004 12, 0xFFFF, sum = 0
7004 00:39:11.001992 13, 0x0, sum = 1
7005 00:39:11.002096 14, 0x0, sum = 2
7006 00:39:11.005277 15, 0x0, sum = 3
7007 00:39:11.005353 16, 0x0, sum = 4
7008 00:39:11.005423 best_step = 14
7009 00:39:11.005517
7010 00:39:11.008469 ==
7011 00:39:11.011931 Dram Type= 6, Freq= 0, CH_1, rank 1
7012 00:39:11.015164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7013 00:39:11.015295 ==
7014 00:39:11.015412 RX Vref Scan: 0
7015 00:39:11.015524
7016 00:39:11.018648 RX Vref 0 -> 0, step: 1
7017 00:39:11.018771
7018 00:39:11.021400 RX Delay -359 -> 252, step: 8
7019 00:39:11.028928 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7020 00:39:11.032347 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7021 00:39:11.035206 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7022 00:39:11.038832 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7023 00:39:11.045515 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7024 00:39:11.048885 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7025 00:39:11.052220 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7026 00:39:11.055102 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7027 00:39:11.062039 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7028 00:39:11.065299 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7029 00:39:11.068685 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7030 00:39:11.075310 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7031 00:39:11.078557 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7032 00:39:11.081992 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7033 00:39:11.085318 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7034 00:39:11.091658 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7035 00:39:11.091741 ==
7036 00:39:11.095017 Dram Type= 6, Freq= 0, CH_1, rank 1
7037 00:39:11.098464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7038 00:39:11.098570 ==
7039 00:39:11.098664 DQS Delay:
7040 00:39:11.101942 DQS0 = 60, DQS1 = 64
7041 00:39:11.102047 DQM Delay:
7042 00:39:11.104917 DQM0 = 13, DQM1 = 10
7043 00:39:11.104993 DQ Delay:
7044 00:39:11.108223 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7045 00:39:11.111552 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7046 00:39:11.114901 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7047 00:39:11.118589 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7048 00:39:11.118668
7049 00:39:11.118729
7050 00:39:11.124816 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7051 00:39:11.128180 CH1 RK1: MR19=C0C, MR18=77A7
7052 00:39:11.135156 CH1_RK1: MR19=0xC0C, MR18=0x77A7, DQSOSC=389, MR23=63, INC=390, DEC=260
7053 00:39:11.138079 [RxdqsGatingPostProcess] freq 400
7054 00:39:11.145033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7055 00:39:11.148368 best DQS0 dly(2T, 0.5T) = (0, 10)
7056 00:39:11.148443 best DQS1 dly(2T, 0.5T) = (0, 10)
7057 00:39:11.151225 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7058 00:39:11.154600 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7059 00:39:11.158072 best DQS0 dly(2T, 0.5T) = (0, 10)
7060 00:39:11.161507 best DQS1 dly(2T, 0.5T) = (0, 10)
7061 00:39:11.164714 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7062 00:39:11.168056 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7063 00:39:11.171434 Pre-setting of DQS Precalculation
7064 00:39:11.178191 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7065 00:39:11.184479 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7066 00:39:11.191195 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7067 00:39:11.191314
7068 00:39:11.191410
7069 00:39:11.194678 [Calibration Summary] 800 Mbps
7070 00:39:11.194808 CH 0, Rank 0
7071 00:39:11.197838 SW Impedance : PASS
7072 00:39:11.201114 DUTY Scan : NO K
7073 00:39:11.201240 ZQ Calibration : PASS
7074 00:39:11.204672 Jitter Meter : NO K
7075 00:39:11.207513 CBT Training : PASS
7076 00:39:11.207641 Write leveling : PASS
7077 00:39:11.210986 RX DQS gating : PASS
7078 00:39:11.211113 RX DQ/DQS(RDDQC) : PASS
7079 00:39:11.214516 TX DQ/DQS : PASS
7080 00:39:11.217345 RX DATLAT : PASS
7081 00:39:11.217469 RX DQ/DQS(Engine): PASS
7082 00:39:11.220799 TX OE : NO K
7083 00:39:11.220921 All Pass.
7084 00:39:11.221035
7085 00:39:11.224127 CH 0, Rank 1
7086 00:39:11.224252 SW Impedance : PASS
7087 00:39:11.227710 DUTY Scan : NO K
7088 00:39:11.230866 ZQ Calibration : PASS
7089 00:39:11.230994 Jitter Meter : NO K
7090 00:39:11.234028 CBT Training : PASS
7091 00:39:11.237437 Write leveling : NO K
7092 00:39:11.237562 RX DQS gating : PASS
7093 00:39:11.240516 RX DQ/DQS(RDDQC) : PASS
7094 00:39:11.243879 TX DQ/DQS : PASS
7095 00:39:11.244011 RX DATLAT : PASS
7096 00:39:11.247301 RX DQ/DQS(Engine): PASS
7097 00:39:11.250881 TX OE : NO K
7098 00:39:11.250985 All Pass.
7099 00:39:11.251078
7100 00:39:11.251167 CH 1, Rank 0
7101 00:39:11.254360 SW Impedance : PASS
7102 00:39:11.257282 DUTY Scan : NO K
7103 00:39:11.257364 ZQ Calibration : PASS
7104 00:39:11.260655 Jitter Meter : NO K
7105 00:39:11.264117 CBT Training : PASS
7106 00:39:11.264243 Write leveling : PASS
7107 00:39:11.267322 RX DQS gating : PASS
7108 00:39:11.267450 RX DQ/DQS(RDDQC) : PASS
7109 00:39:11.270630 TX DQ/DQS : PASS
7110 00:39:11.274019 RX DATLAT : PASS
7111 00:39:11.274147 RX DQ/DQS(Engine): PASS
7112 00:39:11.277527 TX OE : NO K
7113 00:39:11.277655 All Pass.
7114 00:39:11.277769
7115 00:39:11.280838 CH 1, Rank 1
7116 00:39:11.280958 SW Impedance : PASS
7117 00:39:11.284285 DUTY Scan : NO K
7118 00:39:11.287091 ZQ Calibration : PASS
7119 00:39:11.287221 Jitter Meter : NO K
7120 00:39:11.290341 CBT Training : PASS
7121 00:39:11.293679 Write leveling : NO K
7122 00:39:11.293801 RX DQS gating : PASS
7123 00:39:11.297056 RX DQ/DQS(RDDQC) : PASS
7124 00:39:11.300150 TX DQ/DQS : PASS
7125 00:39:11.300267 RX DATLAT : PASS
7126 00:39:11.303933 RX DQ/DQS(Engine): PASS
7127 00:39:11.306806 TX OE : NO K
7128 00:39:11.306932 All Pass.
7129 00:39:11.307050
7130 00:39:11.307162 DramC Write-DBI off
7131 00:39:11.310495 PER_BANK_REFRESH: Hybrid Mode
7132 00:39:11.313656 TX_TRACKING: ON
7133 00:39:11.320295 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7134 00:39:11.323457 [FAST_K] Save calibration result to emmc
7135 00:39:11.329998 dramc_set_vcore_voltage set vcore to 725000
7136 00:39:11.330136 Read voltage for 1600, 0
7137 00:39:11.333658 Vio18 = 0
7138 00:39:11.333778 Vcore = 725000
7139 00:39:11.333896 Vdram = 0
7140 00:39:11.337184 Vddq = 0
7141 00:39:11.337308 Vmddr = 0
7142 00:39:11.339974 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7143 00:39:11.346920 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7144 00:39:11.349839 MEM_TYPE=3, freq_sel=13
7145 00:39:11.353401 sv_algorithm_assistance_LP4_3733
7146 00:39:11.356731 ============ PULL DRAM RESETB DOWN ============
7147 00:39:11.360163 ========== PULL DRAM RESETB DOWN end =========
7148 00:39:11.366486 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7149 00:39:11.366615 ===================================
7150 00:39:11.369985 LPDDR4 DRAM CONFIGURATION
7151 00:39:11.373241 ===================================
7152 00:39:11.376648 EX_ROW_EN[0] = 0x0
7153 00:39:11.376773 EX_ROW_EN[1] = 0x0
7154 00:39:11.379909 LP4Y_EN = 0x0
7155 00:39:11.380042 WORK_FSP = 0x1
7156 00:39:11.383322 WL = 0x5
7157 00:39:11.383450 RL = 0x5
7158 00:39:11.386528 BL = 0x2
7159 00:39:11.389994 RPST = 0x0
7160 00:39:11.390123 RD_PRE = 0x0
7161 00:39:11.393424 WR_PRE = 0x1
7162 00:39:11.393547 WR_PST = 0x1
7163 00:39:11.396906 DBI_WR = 0x0
7164 00:39:11.397032 DBI_RD = 0x0
7165 00:39:11.399739 OTF = 0x1
7166 00:39:11.403157 ===================================
7167 00:39:11.406578 ===================================
7168 00:39:11.406699 ANA top config
7169 00:39:11.409503 ===================================
7170 00:39:11.412999 DLL_ASYNC_EN = 0
7171 00:39:11.416336 ALL_SLAVE_EN = 0
7172 00:39:11.416465 NEW_RANK_MODE = 1
7173 00:39:11.419805 DLL_IDLE_MODE = 1
7174 00:39:11.423048 LP45_APHY_COMB_EN = 1
7175 00:39:11.426344 TX_ODT_DIS = 0
7176 00:39:11.426472 NEW_8X_MODE = 1
7177 00:39:11.430018 ===================================
7178 00:39:11.433202 ===================================
7179 00:39:11.436480 data_rate = 3200
7180 00:39:11.439783 CKR = 1
7181 00:39:11.443079 DQ_P2S_RATIO = 8
7182 00:39:11.446316 ===================================
7183 00:39:11.449449 CA_P2S_RATIO = 8
7184 00:39:11.452935 DQ_CA_OPEN = 0
7185 00:39:11.453059 DQ_SEMI_OPEN = 0
7186 00:39:11.456189 CA_SEMI_OPEN = 0
7187 00:39:11.459531 CA_FULL_RATE = 0
7188 00:39:11.462727 DQ_CKDIV4_EN = 0
7189 00:39:11.466022 CA_CKDIV4_EN = 0
7190 00:39:11.469360 CA_PREDIV_EN = 0
7191 00:39:11.469489 PH8_DLY = 12
7192 00:39:11.472986 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7193 00:39:11.476266 DQ_AAMCK_DIV = 4
7194 00:39:11.479705 CA_AAMCK_DIV = 4
7195 00:39:11.482682 CA_ADMCK_DIV = 4
7196 00:39:11.486131 DQ_TRACK_CA_EN = 0
7197 00:39:11.489450 CA_PICK = 1600
7198 00:39:11.489573 CA_MCKIO = 1600
7199 00:39:11.492828 MCKIO_SEMI = 0
7200 00:39:11.496156 PLL_FREQ = 3068
7201 00:39:11.499568 DQ_UI_PI_RATIO = 32
7202 00:39:11.502366 CA_UI_PI_RATIO = 0
7203 00:39:11.505960 ===================================
7204 00:39:11.509459 ===================================
7205 00:39:11.512441 memory_type:LPDDR4
7206 00:39:11.512570 GP_NUM : 10
7207 00:39:11.515717 SRAM_EN : 1
7208 00:39:11.515837 MD32_EN : 0
7209 00:39:11.519338 ===================================
7210 00:39:11.522749 [ANA_INIT] >>>>>>>>>>>>>>
7211 00:39:11.525625 <<<<<< [CONFIGURE PHASE]: ANA_TX
7212 00:39:11.529156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7213 00:39:11.532282 ===================================
7214 00:39:11.535838 data_rate = 3200,PCW = 0X7600
7215 00:39:11.539126 ===================================
7216 00:39:11.542011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7217 00:39:11.548894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7218 00:39:11.552349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7219 00:39:11.559055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7220 00:39:11.562234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7221 00:39:11.565584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7222 00:39:11.565713 [ANA_INIT] flow start
7223 00:39:11.568828 [ANA_INIT] PLL >>>>>>>>
7224 00:39:11.571982 [ANA_INIT] PLL <<<<<<<<
7225 00:39:11.572106 [ANA_INIT] MIDPI >>>>>>>>
7226 00:39:11.575041 [ANA_INIT] MIDPI <<<<<<<<
7227 00:39:11.578479 [ANA_INIT] DLL >>>>>>>>
7228 00:39:11.581844 [ANA_INIT] DLL <<<<<<<<
7229 00:39:11.581967 [ANA_INIT] flow end
7230 00:39:11.585372 ============ LP4 DIFF to SE enter ============
7231 00:39:11.592274 ============ LP4 DIFF to SE exit ============
7232 00:39:11.592383 [ANA_INIT] <<<<<<<<<<<<<
7233 00:39:11.595280 [Flow] Enable top DCM control >>>>>
7234 00:39:11.598615 [Flow] Enable top DCM control <<<<<
7235 00:39:11.601659 Enable DLL master slave shuffle
7236 00:39:11.608531 ==============================================================
7237 00:39:11.608623 Gating Mode config
7238 00:39:11.614733 ==============================================================
7239 00:39:11.618390 Config description:
7240 00:39:11.628650 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7241 00:39:11.634896 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7242 00:39:11.638140 SELPH_MODE 0: By rank 1: By Phase
7243 00:39:11.645006 ==============================================================
7244 00:39:11.648408 GAT_TRACK_EN = 1
7245 00:39:11.648538 RX_GATING_MODE = 2
7246 00:39:11.651236 RX_GATING_TRACK_MODE = 2
7247 00:39:11.654679 SELPH_MODE = 1
7248 00:39:11.658210 PICG_EARLY_EN = 1
7249 00:39:11.661687 VALID_LAT_VALUE = 1
7250 00:39:11.667831 ==============================================================
7251 00:39:11.671571 Enter into Gating configuration >>>>
7252 00:39:11.674569 Exit from Gating configuration <<<<
7253 00:39:11.678064 Enter into DVFS_PRE_config >>>>>
7254 00:39:11.687870 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7255 00:39:11.691293 Exit from DVFS_PRE_config <<<<<
7256 00:39:11.694848 Enter into PICG configuration >>>>
7257 00:39:11.697655 Exit from PICG configuration <<<<
7258 00:39:11.701254 [RX_INPUT] configuration >>>>>
7259 00:39:11.704258 [RX_INPUT] configuration <<<<<
7260 00:39:11.707699 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7261 00:39:11.714322 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7262 00:39:11.720974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7263 00:39:11.727558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7264 00:39:11.731046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7265 00:39:11.737904 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7266 00:39:11.740863 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7267 00:39:11.747389 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7268 00:39:11.750910 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7269 00:39:11.754226 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7270 00:39:11.757625 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7271 00:39:11.763991 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 00:39:11.767368 ===================================
7273 00:39:11.771123 LPDDR4 DRAM CONFIGURATION
7274 00:39:11.774138 ===================================
7275 00:39:11.774223 EX_ROW_EN[0] = 0x0
7276 00:39:11.777262 EX_ROW_EN[1] = 0x0
7277 00:39:11.777347 LP4Y_EN = 0x0
7278 00:39:11.780307 WORK_FSP = 0x1
7279 00:39:11.780428 WL = 0x5
7280 00:39:11.783713 RL = 0x5
7281 00:39:11.783798 BL = 0x2
7282 00:39:11.787091 RPST = 0x0
7283 00:39:11.787172 RD_PRE = 0x0
7284 00:39:11.790576 WR_PRE = 0x1
7285 00:39:11.790684 WR_PST = 0x1
7286 00:39:11.794130 DBI_WR = 0x0
7287 00:39:11.794229 DBI_RD = 0x0
7288 00:39:11.797014 OTF = 0x1
7289 00:39:11.800353 ===================================
7290 00:39:11.803954 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7291 00:39:11.807330 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7292 00:39:11.813784 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7293 00:39:11.816824 ===================================
7294 00:39:11.816898 LPDDR4 DRAM CONFIGURATION
7295 00:39:11.820469 ===================================
7296 00:39:11.823573 EX_ROW_EN[0] = 0x10
7297 00:39:11.826927 EX_ROW_EN[1] = 0x0
7298 00:39:11.827002 LP4Y_EN = 0x0
7299 00:39:11.830129 WORK_FSP = 0x1
7300 00:39:11.830202 WL = 0x5
7301 00:39:11.833850 RL = 0x5
7302 00:39:11.833922 BL = 0x2
7303 00:39:11.836679 RPST = 0x0
7304 00:39:11.836777 RD_PRE = 0x0
7305 00:39:11.840425 WR_PRE = 0x1
7306 00:39:11.840562 WR_PST = 0x1
7307 00:39:11.843613 DBI_WR = 0x0
7308 00:39:11.843737 DBI_RD = 0x0
7309 00:39:11.847142 OTF = 0x1
7310 00:39:11.850155 ===================================
7311 00:39:11.856592 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7312 00:39:11.856730 ==
7313 00:39:11.859875 Dram Type= 6, Freq= 0, CH_0, rank 0
7314 00:39:11.863130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7315 00:39:11.863271 ==
7316 00:39:11.866571 [Duty_Offset_Calibration]
7317 00:39:11.866721 B0:2 B1:0 CA:3
7318 00:39:11.866832
7319 00:39:11.870109 [DutyScan_Calibration_Flow] k_type=0
7320 00:39:11.880800
7321 00:39:11.880925 ==CLK 0==
7322 00:39:11.884092 Final CLK duty delay cell = 0
7323 00:39:11.887284 [0] MAX Duty = 5031%(X100), DQS PI = 12
7324 00:39:11.890620 [0] MIN Duty = 4907%(X100), DQS PI = 6
7325 00:39:11.890727 [0] AVG Duty = 4969%(X100)
7326 00:39:11.893958
7327 00:39:11.897418 CH0 CLK Duty spec in!! Max-Min= 124%
7328 00:39:11.900910 [DutyScan_Calibration_Flow] ====Done====
7329 00:39:11.900991
7330 00:39:11.903597 [DutyScan_Calibration_Flow] k_type=1
7331 00:39:11.920554
7332 00:39:11.920638 ==DQS 0 ==
7333 00:39:11.923849 Final DQS duty delay cell = 0
7334 00:39:11.927097 [0] MAX Duty = 5094%(X100), DQS PI = 14
7335 00:39:11.930390 [0] MIN Duty = 4875%(X100), DQS PI = 48
7336 00:39:11.933860 [0] AVG Duty = 4984%(X100)
7337 00:39:11.933949
7338 00:39:11.934011 ==DQS 1 ==
7339 00:39:11.937259 Final DQS duty delay cell = 0
7340 00:39:11.940592 [0] MAX Duty = 5156%(X100), DQS PI = 32
7341 00:39:11.943763 [0] MIN Duty = 5031%(X100), DQS PI = 12
7342 00:39:11.947221 [0] AVG Duty = 5093%(X100)
7343 00:39:11.947349
7344 00:39:11.950853 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7345 00:39:11.950977
7346 00:39:11.953557 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7347 00:39:11.956985 [DutyScan_Calibration_Flow] ====Done====
7348 00:39:11.957112
7349 00:39:11.960326 [DutyScan_Calibration_Flow] k_type=3
7350 00:39:11.978360
7351 00:39:11.978486 ==DQM 0 ==
7352 00:39:11.981625 Final DQM duty delay cell = 0
7353 00:39:11.985046 [0] MAX Duty = 5156%(X100), DQS PI = 12
7354 00:39:11.988409 [0] MIN Duty = 4875%(X100), DQS PI = 0
7355 00:39:11.991865 [0] AVG Duty = 5015%(X100)
7356 00:39:11.991950
7357 00:39:11.992016 ==DQM 1 ==
7358 00:39:11.995000 Final DQM duty delay cell = 4
7359 00:39:11.998305 [4] MAX Duty = 5187%(X100), DQS PI = 60
7360 00:39:12.001770 [4] MIN Duty = 5000%(X100), DQS PI = 14
7361 00:39:12.004836 [4] AVG Duty = 5093%(X100)
7362 00:39:12.004929
7363 00:39:12.008197 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7364 00:39:12.008308
7365 00:39:12.011213 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7366 00:39:12.014463 [DutyScan_Calibration_Flow] ====Done====
7367 00:39:12.014560
7368 00:39:12.018108 [DutyScan_Calibration_Flow] k_type=2
7369 00:39:12.034595
7370 00:39:12.034738 ==DQ 0 ==
7371 00:39:12.037846 Final DQ duty delay cell = -4
7372 00:39:12.041001 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7373 00:39:12.044944 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7374 00:39:12.047764 [-4] AVG Duty = 4953%(X100)
7375 00:39:12.047890
7376 00:39:12.047998 ==DQ 1 ==
7377 00:39:12.051339 Final DQ duty delay cell = 0
7378 00:39:12.054321 [0] MAX Duty = 5156%(X100), DQS PI = 58
7379 00:39:12.057945 [0] MIN Duty = 5000%(X100), DQS PI = 14
7380 00:39:12.061123 [0] AVG Duty = 5078%(X100)
7381 00:39:12.061200
7382 00:39:12.064118 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7383 00:39:12.064224
7384 00:39:12.067834 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7385 00:39:12.071243 [DutyScan_Calibration_Flow] ====Done====
7386 00:39:12.071320 ==
7387 00:39:12.074267 Dram Type= 6, Freq= 0, CH_1, rank 0
7388 00:39:12.077349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7389 00:39:12.077432 ==
7390 00:39:12.080948 [Duty_Offset_Calibration]
7391 00:39:12.081076 B0:1 B1:-2 CA:1
7392 00:39:12.081187
7393 00:39:12.083955 [DutyScan_Calibration_Flow] k_type=0
7394 00:39:12.095244
7395 00:39:12.095380 ==CLK 0==
7396 00:39:12.098285 Final CLK duty delay cell = 0
7397 00:39:12.101938 [0] MAX Duty = 5062%(X100), DQS PI = 20
7398 00:39:12.105280 [0] MIN Duty = 4844%(X100), DQS PI = 58
7399 00:39:12.108282 [0] AVG Duty = 4953%(X100)
7400 00:39:12.108411
7401 00:39:12.111391 CH1 CLK Duty spec in!! Max-Min= 218%
7402 00:39:12.114770 [DutyScan_Calibration_Flow] ====Done====
7403 00:39:12.114852
7404 00:39:12.118348 [DutyScan_Calibration_Flow] k_type=1
7405 00:39:12.134266
7406 00:39:12.134384 ==DQS 0 ==
7407 00:39:12.137049 Final DQS duty delay cell = -4
7408 00:39:12.140330 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7409 00:39:12.143692 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7410 00:39:12.147183 [-4] AVG Duty = 4906%(X100)
7411 00:39:12.147268
7412 00:39:12.147333 ==DQS 1 ==
7413 00:39:12.150509 Final DQS duty delay cell = 0
7414 00:39:12.153609 [0] MAX Duty = 5093%(X100), DQS PI = 58
7415 00:39:12.157172 [0] MIN Duty = 4844%(X100), DQS PI = 24
7416 00:39:12.160470 [0] AVG Duty = 4968%(X100)
7417 00:39:12.160588
7418 00:39:12.163405 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7419 00:39:12.163488
7420 00:39:12.166879 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7421 00:39:12.170554 [DutyScan_Calibration_Flow] ====Done====
7422 00:39:12.170638
7423 00:39:12.173445 [DutyScan_Calibration_Flow] k_type=3
7424 00:39:12.191230
7425 00:39:12.191349 ==DQM 0 ==
7426 00:39:12.194117 Final DQM duty delay cell = 0
7427 00:39:12.197833 [0] MAX Duty = 5031%(X100), DQS PI = 26
7428 00:39:12.201156 [0] MIN Duty = 4813%(X100), DQS PI = 56
7429 00:39:12.204322 [0] AVG Duty = 4922%(X100)
7430 00:39:12.204406
7431 00:39:12.204470 ==DQM 1 ==
7432 00:39:12.207830 Final DQM duty delay cell = 0
7433 00:39:12.210812 [0] MAX Duty = 5062%(X100), DQS PI = 34
7434 00:39:12.214068 [0] MIN Duty = 4875%(X100), DQS PI = 24
7435 00:39:12.217517 [0] AVG Duty = 4968%(X100)
7436 00:39:12.217600
7437 00:39:12.220491 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7438 00:39:12.220583
7439 00:39:12.224203 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7440 00:39:12.227666 [DutyScan_Calibration_Flow] ====Done====
7441 00:39:12.227749
7442 00:39:12.230704 [DutyScan_Calibration_Flow] k_type=2
7443 00:39:12.247646
7444 00:39:12.247739 ==DQ 0 ==
7445 00:39:12.251093 Final DQ duty delay cell = 0
7446 00:39:12.254376 [0] MAX Duty = 5093%(X100), DQS PI = 22
7447 00:39:12.257798 [0] MIN Duty = 4907%(X100), DQS PI = 62
7448 00:39:12.257876 [0] AVG Duty = 5000%(X100)
7449 00:39:12.261355
7450 00:39:12.261437 ==DQ 1 ==
7451 00:39:12.264394 Final DQ duty delay cell = 0
7452 00:39:12.267828 [0] MAX Duty = 5125%(X100), DQS PI = 34
7453 00:39:12.271386 [0] MIN Duty = 4969%(X100), DQS PI = 24
7454 00:39:12.271475 [0] AVG Duty = 5047%(X100)
7455 00:39:12.271561
7456 00:39:12.277435 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7457 00:39:12.277521
7458 00:39:12.280995 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7459 00:39:12.284547 [DutyScan_Calibration_Flow] ====Done====
7460 00:39:12.287524 nWR fixed to 30
7461 00:39:12.287635 [ModeRegInit_LP4] CH0 RK0
7462 00:39:12.291031 [ModeRegInit_LP4] CH0 RK1
7463 00:39:12.294231 [ModeRegInit_LP4] CH1 RK0
7464 00:39:12.297610 [ModeRegInit_LP4] CH1 RK1
7465 00:39:12.297690 match AC timing 5
7466 00:39:12.304099 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7467 00:39:12.307514 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7468 00:39:12.310540 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7469 00:39:12.317407 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7470 00:39:12.320780 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7471 00:39:12.320878 [MiockJmeterHQA]
7472 00:39:12.320944
7473 00:39:12.324155 [DramcMiockJmeter] u1RxGatingPI = 0
7474 00:39:12.327104 0 : 4257, 4029
7475 00:39:12.327217 4 : 4257, 4032
7476 00:39:12.330485 8 : 4371, 4143
7477 00:39:12.330590 12 : 4255, 4030
7478 00:39:12.330683 16 : 4368, 4142
7479 00:39:12.334015 20 : 4255, 4030
7480 00:39:12.334120 24 : 4257, 4032
7481 00:39:12.337255 28 : 4257, 4029
7482 00:39:12.337331 32 : 4366, 4140
7483 00:39:12.340373 36 : 4257, 4029
7484 00:39:12.340450 40 : 4255, 4029
7485 00:39:12.343664 44 : 4368, 4140
7486 00:39:12.343748 48 : 4255, 4029
7487 00:39:12.343815 52 : 4257, 4030
7488 00:39:12.347409 56 : 4260, 4031
7489 00:39:12.347485 60 : 4363, 4140
7490 00:39:12.350648 64 : 4253, 4029
7491 00:39:12.350749 68 : 4366, 4140
7492 00:39:12.353734 72 : 4366, 4140
7493 00:39:12.353813 76 : 4252, 4029
7494 00:39:12.357115 80 : 4252, 4027
7495 00:39:12.357192 84 : 4252, 4030
7496 00:39:12.357256 88 : 4257, 4031
7497 00:39:12.360442 92 : 4365, 4140
7498 00:39:12.360515 96 : 4252, 4029
7499 00:39:12.363868 100 : 4253, 4029
7500 00:39:12.363953 104 : 4252, 3412
7501 00:39:12.367233 108 : 4363, 0
7502 00:39:12.367318 112 : 4364, 0
7503 00:39:12.367384 116 : 4368, 0
7504 00:39:12.370362 120 : 4255, 0
7505 00:39:12.370446 124 : 4252, 0
7506 00:39:12.373668 128 : 4255, 0
7507 00:39:12.373753 132 : 4363, 0
7508 00:39:12.373819 136 : 4252, 0
7509 00:39:12.376812 140 : 4252, 0
7510 00:39:12.376932 144 : 4253, 0
7511 00:39:12.380050 148 : 4252, 0
7512 00:39:12.380175 152 : 4253, 0
7513 00:39:12.380290 156 : 4257, 0
7514 00:39:12.383770 160 : 4363, 0
7515 00:39:12.383895 164 : 4254, 0
7516 00:39:12.383993 168 : 4366, 0
7517 00:39:12.386957 172 : 4253, 0
7518 00:39:12.387081 176 : 4250, 0
7519 00:39:12.389975 180 : 4368, 0
7520 00:39:12.390111 184 : 4363, 0
7521 00:39:12.390223 188 : 4363, 0
7522 00:39:12.393531 192 : 4368, 0
7523 00:39:12.393616 196 : 4252, 0
7524 00:39:12.396962 200 : 4252, 0
7525 00:39:12.397077 204 : 4253, 0
7526 00:39:12.397164 208 : 4257, 0
7527 00:39:12.399872 212 : 4363, 0
7528 00:39:12.399949 216 : 4255, 0
7529 00:39:12.403599 220 : 4252, 0
7530 00:39:12.403691 224 : 4252, 0
7531 00:39:12.403780 228 : 4254, 0
7532 00:39:12.406602 232 : 4257, 0
7533 00:39:12.406689 236 : 4363, 967
7534 00:39:12.410005 240 : 4253, 4029
7535 00:39:12.410094 244 : 4253, 4029
7536 00:39:12.413477 248 : 4252, 4030
7537 00:39:12.413563 252 : 4252, 4029
7538 00:39:12.416451 256 : 4257, 4031
7539 00:39:12.416578 260 : 4255, 4030
7540 00:39:12.416649 264 : 4363, 4139
7541 00:39:12.419949 268 : 4255, 4029
7542 00:39:12.420035 272 : 4363, 4140
7543 00:39:12.423028 276 : 4254, 4030
7544 00:39:12.423125 280 : 4252, 4029
7545 00:39:12.426746 284 : 4255, 4029
7546 00:39:12.426864 288 : 4257, 4032
7547 00:39:12.429536 292 : 4252, 4029
7548 00:39:12.429622 296 : 4253, 4029
7549 00:39:12.433217 300 : 4363, 4140
7550 00:39:12.433340 304 : 4252, 4029
7551 00:39:12.436834 308 : 4255, 4029
7552 00:39:12.436919 312 : 4250, 4027
7553 00:39:12.439928 316 : 4252, 4030
7554 00:39:12.440013 320 : 4255, 4029
7555 00:39:12.442764 324 : 4363, 4140
7556 00:39:12.442866 328 : 4252, 4029
7557 00:39:12.442935 332 : 4252, 4029
7558 00:39:12.446195 336 : 4252, 4029
7559 00:39:12.446281 340 : 4255, 4029
7560 00:39:12.449969 344 : 4257, 4032
7561 00:39:12.450086 348 : 4254, 4030
7562 00:39:12.453388 352 : 4363, 4128
7563 00:39:12.453467 356 : 4255, 2738
7564 00:39:12.456138 360 : 4255, 1
7565 00:39:12.456212
7566 00:39:12.456274 MIOCK jitter meter ch=0
7567 00:39:12.456343
7568 00:39:12.459848 1T = (360-108) = 252 dly cells
7569 00:39:12.466492 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7570 00:39:12.466573 ==
7571 00:39:12.469359 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 00:39:12.472755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 00:39:12.472842 ==
7574 00:39:12.479323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 00:39:12.482903 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 00:39:12.485870 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 00:39:12.492814 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 00:39:12.502456 [CA 0] Center 43 (13~74) winsize 62
7579 00:39:12.505905 [CA 1] Center 43 (13~74) winsize 62
7580 00:39:12.509406 [CA 2] Center 39 (10~68) winsize 59
7581 00:39:12.512368 [CA 3] Center 39 (10~68) winsize 59
7582 00:39:12.515814 [CA 4] Center 36 (7~66) winsize 60
7583 00:39:12.519365 [CA 5] Center 36 (7~66) winsize 60
7584 00:39:12.519446
7585 00:39:12.522307 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 00:39:12.522423
7587 00:39:12.529317 [CATrainingPosCal] consider 1 rank data
7588 00:39:12.529402 u2DelayCellTimex100 = 258/100 ps
7589 00:39:12.535979 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7590 00:39:12.539280 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7591 00:39:12.542288 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7592 00:39:12.545970 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7593 00:39:12.549025 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7594 00:39:12.552640 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7595 00:39:12.552720
7596 00:39:12.555617 CA PerBit enable=1, Macro0, CA PI delay=36
7597 00:39:12.555696
7598 00:39:12.559150 [CBTSetCACLKResult] CA Dly = 36
7599 00:39:12.562100 CS Dly: 11 (0~42)
7600 00:39:12.565410 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 00:39:12.568806 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 00:39:12.568887 ==
7603 00:39:12.572529 Dram Type= 6, Freq= 0, CH_0, rank 1
7604 00:39:12.579070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 00:39:12.579163 ==
7606 00:39:12.582283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7607 00:39:12.588616 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7608 00:39:12.592166 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7609 00:39:12.598852 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7610 00:39:12.606498 [CA 0] Center 43 (13~74) winsize 62
7611 00:39:12.610145 [CA 1] Center 43 (13~74) winsize 62
7612 00:39:12.613404 [CA 2] Center 39 (10~68) winsize 59
7613 00:39:12.616317 [CA 3] Center 39 (10~68) winsize 59
7614 00:39:12.619866 [CA 4] Center 36 (6~66) winsize 61
7615 00:39:12.623242 [CA 5] Center 36 (6~66) winsize 61
7616 00:39:12.623429
7617 00:39:12.626380 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7618 00:39:12.626499
7619 00:39:12.633279 [CATrainingPosCal] consider 2 rank data
7620 00:39:12.633394 u2DelayCellTimex100 = 258/100 ps
7621 00:39:12.639650 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7622 00:39:12.643193 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7623 00:39:12.646188 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7624 00:39:12.649854 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7625 00:39:12.652739 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7626 00:39:12.656339 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7627 00:39:12.656471
7628 00:39:12.659307 CA PerBit enable=1, Macro0, CA PI delay=36
7629 00:39:12.659420
7630 00:39:12.662944 [CBTSetCACLKResult] CA Dly = 36
7631 00:39:12.666142 CS Dly: 11 (0~43)
7632 00:39:12.669317 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7633 00:39:12.672965 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7634 00:39:12.673048
7635 00:39:12.675942 ----->DramcWriteLeveling(PI) begin...
7636 00:39:12.676046 ==
7637 00:39:12.679397 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 00:39:12.686035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 00:39:12.686129 ==
7640 00:39:12.689526 Write leveling (Byte 0): 35 => 35
7641 00:39:12.693061 Write leveling (Byte 1): 29 => 29
7642 00:39:12.695964 DramcWriteLeveling(PI) end<-----
7643 00:39:12.696055
7644 00:39:12.696150 ==
7645 00:39:12.699670 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 00:39:12.702546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 00:39:12.702656 ==
7648 00:39:12.706073 [Gating] SW mode calibration
7649 00:39:12.712359 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7650 00:39:12.719063 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7651 00:39:12.722316 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 00:39:12.725539 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 00:39:12.729055 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 00:39:12.735912 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 00:39:12.738860 1 4 16 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7656 00:39:12.742434 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7657 00:39:12.748774 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 00:39:12.752113 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 00:39:12.755783 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 00:39:12.762196 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 00:39:12.765657 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 00:39:12.768686 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7663 00:39:12.775130 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7664 00:39:12.778607 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7665 00:39:12.782032 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7666 00:39:12.788780 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 00:39:12.792272 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 00:39:12.794955 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 00:39:12.801753 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 00:39:12.805288 1 6 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7671 00:39:12.808418 1 6 16 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7672 00:39:12.814953 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7673 00:39:12.818524 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7674 00:39:12.821514 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 00:39:12.828624 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 00:39:12.831507 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 00:39:12.834905 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 00:39:12.841684 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7679 00:39:12.845135 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7680 00:39:12.848434 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7681 00:39:12.855139 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7682 00:39:12.857856 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7683 00:39:12.861218 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 00:39:12.867933 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 00:39:12.871490 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 00:39:12.874616 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 00:39:12.881230 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 00:39:12.884784 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 00:39:12.887781 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 00:39:12.894313 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 00:39:12.897727 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 00:39:12.901046 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 00:39:12.907592 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7694 00:39:12.911167 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 00:39:12.914161 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7696 00:39:12.920806 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7697 00:39:12.924342 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7698 00:39:12.927389 Total UI for P1: 0, mck2ui 16
7699 00:39:12.930791 best dqsien dly found for B0: ( 1, 9, 18)
7700 00:39:12.934247 Total UI for P1: 0, mck2ui 16
7701 00:39:12.937349 best dqsien dly found for B1: ( 1, 9, 22)
7702 00:39:12.940580 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7703 00:39:12.944109 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7704 00:39:12.944183
7705 00:39:12.947243 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7706 00:39:12.950577 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7707 00:39:12.954031 [Gating] SW calibration Done
7708 00:39:12.954103 ==
7709 00:39:12.957272 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 00:39:12.963383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 00:39:12.963495 ==
7712 00:39:12.963601 RX Vref Scan: 0
7713 00:39:12.963693
7714 00:39:12.966860 RX Vref 0 -> 0, step: 1
7715 00:39:12.966971
7716 00:39:12.970427 RX Delay 0 -> 252, step: 8
7717 00:39:12.973302 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7718 00:39:12.976720 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7719 00:39:12.980078 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7720 00:39:12.983460 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7721 00:39:12.990038 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7722 00:39:12.993642 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7723 00:39:12.996851 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7724 00:39:13.000262 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7725 00:39:13.003344 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7726 00:39:13.009739 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7727 00:39:13.013561 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7728 00:39:13.016763 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7729 00:39:13.019900 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7730 00:39:13.023293 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7731 00:39:13.029862 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7732 00:39:13.033329 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7733 00:39:13.033440 ==
7734 00:39:13.036317 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 00:39:13.039885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 00:39:13.039974 ==
7737 00:39:13.043066 DQS Delay:
7738 00:39:13.043145 DQS0 = 0, DQS1 = 0
7739 00:39:13.043218 DQM Delay:
7740 00:39:13.046403 DQM0 = 128, DQM1 = 123
7741 00:39:13.046482 DQ Delay:
7742 00:39:13.049677 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7743 00:39:13.052980 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7744 00:39:13.059904 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7745 00:39:13.063204 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7746 00:39:13.063312
7747 00:39:13.063404
7748 00:39:13.063491 ==
7749 00:39:13.066368 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 00:39:13.070032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 00:39:13.070110 ==
7752 00:39:13.070189
7753 00:39:13.070257
7754 00:39:13.073300 TX Vref Scan disable
7755 00:39:13.073372 == TX Byte 0 ==
7756 00:39:13.080244 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7757 00:39:13.082949 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7758 00:39:13.083034 == TX Byte 1 ==
7759 00:39:13.089896 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7760 00:39:13.093120 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7761 00:39:13.093194 ==
7762 00:39:13.096255 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 00:39:13.099392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 00:39:13.099475 ==
7765 00:39:13.114335
7766 00:39:13.117512 TX Vref early break, caculate TX vref
7767 00:39:13.121195 TX Vref=16, minBit 8, minWin=21, winSum=360
7768 00:39:13.124172 TX Vref=18, minBit 8, minWin=22, winSum=367
7769 00:39:13.127753 TX Vref=20, minBit 1, minWin=23, winSum=381
7770 00:39:13.131093 TX Vref=22, minBit 8, minWin=23, winSum=387
7771 00:39:13.133895 TX Vref=24, minBit 0, minWin=24, winSum=401
7772 00:39:13.141013 TX Vref=26, minBit 4, minWin=24, winSum=405
7773 00:39:13.143878 TX Vref=28, minBit 0, minWin=25, winSum=411
7774 00:39:13.147134 TX Vref=30, minBit 0, minWin=24, winSum=400
7775 00:39:13.150879 TX Vref=32, minBit 0, minWin=24, winSum=394
7776 00:39:13.153936 TX Vref=34, minBit 9, minWin=22, winSum=380
7777 00:39:13.160473 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
7778 00:39:13.160598
7779 00:39:13.163872 Final TX Range 0 Vref 28
7780 00:39:13.164005
7781 00:39:13.164119 ==
7782 00:39:13.167446 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 00:39:13.170794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 00:39:13.170916 ==
7785 00:39:13.171024
7786 00:39:13.171197
7787 00:39:13.174037 TX Vref Scan disable
7788 00:39:13.180416 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7789 00:39:13.180528 == TX Byte 0 ==
7790 00:39:13.183830 u2DelayCellOfst[0]=15 cells (4 PI)
7791 00:39:13.187345 u2DelayCellOfst[1]=18 cells (5 PI)
7792 00:39:13.190222 u2DelayCellOfst[2]=15 cells (4 PI)
7793 00:39:13.193598 u2DelayCellOfst[3]=15 cells (4 PI)
7794 00:39:13.196965 u2DelayCellOfst[4]=11 cells (3 PI)
7795 00:39:13.200145 u2DelayCellOfst[5]=0 cells (0 PI)
7796 00:39:13.203596 u2DelayCellOfst[6]=22 cells (6 PI)
7797 00:39:13.207070 u2DelayCellOfst[7]=18 cells (5 PI)
7798 00:39:13.209963 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7799 00:39:13.213329 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7800 00:39:13.216979 == TX Byte 1 ==
7801 00:39:13.220149 u2DelayCellOfst[8]=0 cells (0 PI)
7802 00:39:13.223445 u2DelayCellOfst[9]=3 cells (1 PI)
7803 00:39:13.223557 u2DelayCellOfst[10]=7 cells (2 PI)
7804 00:39:13.226874 u2DelayCellOfst[11]=3 cells (1 PI)
7805 00:39:13.230190 u2DelayCellOfst[12]=11 cells (3 PI)
7806 00:39:13.233194 u2DelayCellOfst[13]=11 cells (3 PI)
7807 00:39:13.236971 u2DelayCellOfst[14]=15 cells (4 PI)
7808 00:39:13.239940 u2DelayCellOfst[15]=11 cells (3 PI)
7809 00:39:13.246756 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7810 00:39:13.250275 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7811 00:39:13.250350 DramC Write-DBI on
7812 00:39:13.250411 ==
7813 00:39:13.253068 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 00:39:13.260085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 00:39:13.260169 ==
7816 00:39:13.260237
7817 00:39:13.260297
7818 00:39:13.260353 TX Vref Scan disable
7819 00:39:13.264230 == TX Byte 0 ==
7820 00:39:13.267030 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7821 00:39:13.270477 == TX Byte 1 ==
7822 00:39:13.273825 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7823 00:39:13.277215 DramC Write-DBI off
7824 00:39:13.277288
7825 00:39:13.277367 [DATLAT]
7826 00:39:13.277428 Freq=1600, CH0 RK0
7827 00:39:13.277484
7828 00:39:13.280565 DATLAT Default: 0xf
7829 00:39:13.280652 0, 0xFFFF, sum = 0
7830 00:39:13.283659 1, 0xFFFF, sum = 0
7831 00:39:13.283749 2, 0xFFFF, sum = 0
7832 00:39:13.287294 3, 0xFFFF, sum = 0
7833 00:39:13.290492 4, 0xFFFF, sum = 0
7834 00:39:13.290574 5, 0xFFFF, sum = 0
7835 00:39:13.293826 6, 0xFFFF, sum = 0
7836 00:39:13.293902 7, 0xFFFF, sum = 0
7837 00:39:13.296751 8, 0xFFFF, sum = 0
7838 00:39:13.296830 9, 0xFFFF, sum = 0
7839 00:39:13.300101 10, 0xFFFF, sum = 0
7840 00:39:13.300175 11, 0xFFFF, sum = 0
7841 00:39:13.303369 12, 0xFFFF, sum = 0
7842 00:39:13.303454 13, 0xCFFF, sum = 0
7843 00:39:13.306697 14, 0x0, sum = 1
7844 00:39:13.306779 15, 0x0, sum = 2
7845 00:39:13.310277 16, 0x0, sum = 3
7846 00:39:13.310347 17, 0x0, sum = 4
7847 00:39:13.313688 best_step = 15
7848 00:39:13.313755
7849 00:39:13.313812 ==
7850 00:39:13.317112 Dram Type= 6, Freq= 0, CH_0, rank 0
7851 00:39:13.320214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7852 00:39:13.320281 ==
7853 00:39:13.323596 RX Vref Scan: 1
7854 00:39:13.323667
7855 00:39:13.323727 Set Vref Range= 24 -> 127
7856 00:39:13.323782
7857 00:39:13.326993 RX Vref 24 -> 127, step: 1
7858 00:39:13.327078
7859 00:39:13.330420 RX Delay 11 -> 252, step: 4
7860 00:39:13.330499
7861 00:39:13.333792 Set Vref, RX VrefLevel [Byte0]: 24
7862 00:39:13.336917 [Byte1]: 24
7863 00:39:13.336999
7864 00:39:13.340200 Set Vref, RX VrefLevel [Byte0]: 25
7865 00:39:13.343399 [Byte1]: 25
7866 00:39:13.346973
7867 00:39:13.347110 Set Vref, RX VrefLevel [Byte0]: 26
7868 00:39:13.350088 [Byte1]: 26
7869 00:39:13.354347
7870 00:39:13.354425 Set Vref, RX VrefLevel [Byte0]: 27
7871 00:39:13.357755 [Byte1]: 27
7872 00:39:13.362249
7873 00:39:13.362337 Set Vref, RX VrefLevel [Byte0]: 28
7874 00:39:13.365034 [Byte1]: 28
7875 00:39:13.369687
7876 00:39:13.369815 Set Vref, RX VrefLevel [Byte0]: 29
7877 00:39:13.373112 [Byte1]: 29
7878 00:39:13.376988
7879 00:39:13.377104 Set Vref, RX VrefLevel [Byte0]: 30
7880 00:39:13.380458 [Byte1]: 30
7881 00:39:13.385097
7882 00:39:13.385195 Set Vref, RX VrefLevel [Byte0]: 31
7883 00:39:13.387900 [Byte1]: 31
7884 00:39:13.392102
7885 00:39:13.395597 Set Vref, RX VrefLevel [Byte0]: 32
7886 00:39:13.398702 [Byte1]: 32
7887 00:39:13.398792
7888 00:39:13.402131 Set Vref, RX VrefLevel [Byte0]: 33
7889 00:39:13.405542 [Byte1]: 33
7890 00:39:13.405627
7891 00:39:13.408682 Set Vref, RX VrefLevel [Byte0]: 34
7892 00:39:13.412137 [Byte1]: 34
7893 00:39:13.415539
7894 00:39:13.415625 Set Vref, RX VrefLevel [Byte0]: 35
7895 00:39:13.418834 [Byte1]: 35
7896 00:39:13.422880
7897 00:39:13.422964 Set Vref, RX VrefLevel [Byte0]: 36
7898 00:39:13.426504 [Byte1]: 36
7899 00:39:13.430259
7900 00:39:13.430342 Set Vref, RX VrefLevel [Byte0]: 37
7901 00:39:13.433735 [Byte1]: 37
7902 00:39:13.438206
7903 00:39:13.438289 Set Vref, RX VrefLevel [Byte0]: 38
7904 00:39:13.441596 [Byte1]: 38
7905 00:39:13.445687
7906 00:39:13.445806 Set Vref, RX VrefLevel [Byte0]: 39
7907 00:39:13.452616 [Byte1]: 39
7908 00:39:13.453453
7909 00:39:13.453544 Set Vref, RX VrefLevel [Byte0]: 40
7910 00:39:13.456553 [Byte1]: 40
7911 00:39:13.460987
7912 00:39:13.461093 Set Vref, RX VrefLevel [Byte0]: 41
7913 00:39:13.464537 [Byte1]: 41
7914 00:39:13.468245
7915 00:39:13.468355 Set Vref, RX VrefLevel [Byte0]: 42
7916 00:39:13.471777 [Byte1]: 42
7917 00:39:13.475976
7918 00:39:13.476055 Set Vref, RX VrefLevel [Byte0]: 43
7919 00:39:13.479139 [Byte1]: 43
7920 00:39:13.483869
7921 00:39:13.483950 Set Vref, RX VrefLevel [Byte0]: 44
7922 00:39:13.487004 [Byte1]: 44
7923 00:39:13.491173
7924 00:39:13.491281 Set Vref, RX VrefLevel [Byte0]: 45
7925 00:39:13.494848 [Byte1]: 45
7926 00:39:13.498816
7927 00:39:13.498931 Set Vref, RX VrefLevel [Byte0]: 46
7928 00:39:13.502052 [Byte1]: 46
7929 00:39:13.506389
7930 00:39:13.506503 Set Vref, RX VrefLevel [Byte0]: 47
7931 00:39:13.509949 [Byte1]: 47
7932 00:39:13.513919
7933 00:39:13.514027 Set Vref, RX VrefLevel [Byte0]: 48
7934 00:39:13.517617 [Byte1]: 48
7935 00:39:13.521691
7936 00:39:13.521778 Set Vref, RX VrefLevel [Byte0]: 49
7937 00:39:13.525282 [Byte1]: 49
7938 00:39:13.529545
7939 00:39:13.529655 Set Vref, RX VrefLevel [Byte0]: 50
7940 00:39:13.533082 [Byte1]: 50
7941 00:39:13.536879
7942 00:39:13.536954 Set Vref, RX VrefLevel [Byte0]: 51
7943 00:39:13.540502 [Byte1]: 51
7944 00:39:13.544620
7945 00:39:13.544747 Set Vref, RX VrefLevel [Byte0]: 52
7946 00:39:13.548264 [Byte1]: 52
7947 00:39:13.552308
7948 00:39:13.552430 Set Vref, RX VrefLevel [Byte0]: 53
7949 00:39:13.555370 [Byte1]: 53
7950 00:39:13.559916
7951 00:39:13.560002 Set Vref, RX VrefLevel [Byte0]: 54
7952 00:39:13.562912 [Byte1]: 54
7953 00:39:13.567226
7954 00:39:13.567307 Set Vref, RX VrefLevel [Byte0]: 55
7955 00:39:13.570752 [Byte1]: 55
7956 00:39:13.575106
7957 00:39:13.575183 Set Vref, RX VrefLevel [Byte0]: 56
7958 00:39:13.578434 [Byte1]: 56
7959 00:39:13.582808
7960 00:39:13.582890 Set Vref, RX VrefLevel [Byte0]: 57
7961 00:39:13.585968 [Byte1]: 57
7962 00:39:13.590280
7963 00:39:13.590411 Set Vref, RX VrefLevel [Byte0]: 58
7964 00:39:13.593773 [Byte1]: 58
7965 00:39:13.597801
7966 00:39:13.597921 Set Vref, RX VrefLevel [Byte0]: 59
7967 00:39:13.601487 [Byte1]: 59
7968 00:39:13.605749
7969 00:39:13.605837 Set Vref, RX VrefLevel [Byte0]: 60
7970 00:39:13.608899 [Byte1]: 60
7971 00:39:13.613145
7972 00:39:13.613236 Set Vref, RX VrefLevel [Byte0]: 61
7973 00:39:13.616376 [Byte1]: 61
7974 00:39:13.620906
7975 00:39:13.621040 Set Vref, RX VrefLevel [Byte0]: 62
7976 00:39:13.623900 [Byte1]: 62
7977 00:39:13.628214
7978 00:39:13.628360 Set Vref, RX VrefLevel [Byte0]: 63
7979 00:39:13.631822 [Byte1]: 63
7980 00:39:13.635736
7981 00:39:13.635859 Set Vref, RX VrefLevel [Byte0]: 64
7982 00:39:13.639540 [Byte1]: 64
7983 00:39:13.643684
7984 00:39:13.643808 Set Vref, RX VrefLevel [Byte0]: 65
7985 00:39:13.647077 [Byte1]: 65
7986 00:39:13.651096
7987 00:39:13.651220 Set Vref, RX VrefLevel [Byte0]: 66
7988 00:39:13.654715 [Byte1]: 66
7989 00:39:13.659088
7990 00:39:13.659213 Set Vref, RX VrefLevel [Byte0]: 67
7991 00:39:13.661887 [Byte1]: 67
7992 00:39:13.666598
7993 00:39:13.666724 Set Vref, RX VrefLevel [Byte0]: 68
7994 00:39:13.669828 [Byte1]: 68
7995 00:39:13.673934
7996 00:39:13.674057 Set Vref, RX VrefLevel [Byte0]: 69
7997 00:39:13.677218 [Byte1]: 69
7998 00:39:13.681792
7999 00:39:13.681915 Set Vref, RX VrefLevel [Byte0]: 70
8000 00:39:13.685004 [Byte1]: 70
8001 00:39:13.689494
8002 00:39:13.689616 Set Vref, RX VrefLevel [Byte0]: 71
8003 00:39:13.692823 [Byte1]: 71
8004 00:39:13.697006
8005 00:39:13.697138 Set Vref, RX VrefLevel [Byte0]: 72
8006 00:39:13.700306 [Byte1]: 72
8007 00:39:13.704639
8008 00:39:13.704724 Set Vref, RX VrefLevel [Byte0]: 73
8009 00:39:13.707623 [Byte1]: 73
8010 00:39:13.712138
8011 00:39:13.712262 Set Vref, RX VrefLevel [Byte0]: 74
8012 00:39:13.715396 [Byte1]: 74
8013 00:39:13.719804
8014 00:39:13.719924 Set Vref, RX VrefLevel [Byte0]: 75
8015 00:39:13.722838 [Byte1]: 75
8016 00:39:13.727560
8017 00:39:13.727684 Set Vref, RX VrefLevel [Byte0]: 76
8018 00:39:13.730590 [Byte1]: 76
8019 00:39:13.734824
8020 00:39:13.734943 Set Vref, RX VrefLevel [Byte0]: 77
8021 00:39:13.738146 [Byte1]: 77
8022 00:39:13.742974
8023 00:39:13.743064 Set Vref, RX VrefLevel [Byte0]: 78
8024 00:39:13.745831 [Byte1]: 78
8025 00:39:13.750110
8026 00:39:13.750193 Set Vref, RX VrefLevel [Byte0]: 79
8027 00:39:13.753527 [Byte1]: 79
8028 00:39:13.757668
8029 00:39:13.757752 Final RX Vref Byte 0 = 64 to rank0
8030 00:39:13.761336 Final RX Vref Byte 1 = 59 to rank0
8031 00:39:13.764194 Final RX Vref Byte 0 = 64 to rank1
8032 00:39:13.767850 Final RX Vref Byte 1 = 59 to rank1==
8033 00:39:13.770889 Dram Type= 6, Freq= 0, CH_0, rank 0
8034 00:39:13.778029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 00:39:13.778115 ==
8036 00:39:13.778181 DQS Delay:
8037 00:39:13.778243 DQS0 = 0, DQS1 = 0
8038 00:39:13.780893 DQM Delay:
8039 00:39:13.780982 DQM0 = 126, DQM1 = 119
8040 00:39:13.784500 DQ Delay:
8041 00:39:13.787571 DQ0 =126, DQ1 =128, DQ2 =124, DQ3 =122
8042 00:39:13.791176 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
8043 00:39:13.794022 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8044 00:39:13.797381 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8045 00:39:13.797507
8046 00:39:13.797628
8047 00:39:13.797738
8048 00:39:13.801030 [DramC_TX_OE_Calibration] TA2
8049 00:39:13.804026 Original DQ_B0 (3 6) =30, OEN = 27
8050 00:39:13.807508 Original DQ_B1 (3 6) =30, OEN = 27
8051 00:39:13.810960 24, 0x0, End_B0=24 End_B1=24
8052 00:39:13.811046 25, 0x0, End_B0=25 End_B1=25
8053 00:39:13.814165 26, 0x0, End_B0=26 End_B1=26
8054 00:39:13.817557 27, 0x0, End_B0=27 End_B1=27
8055 00:39:13.821152 28, 0x0, End_B0=28 End_B1=28
8056 00:39:13.824215 29, 0x0, End_B0=29 End_B1=29
8057 00:39:13.824301 30, 0x0, End_B0=30 End_B1=30
8058 00:39:13.827235 31, 0x4141, End_B0=30 End_B1=30
8059 00:39:13.830830 Byte0 end_step=30 best_step=27
8060 00:39:13.834278 Byte1 end_step=30 best_step=27
8061 00:39:13.837417 Byte0 TX OE(2T, 0.5T) = (3, 3)
8062 00:39:13.840798 Byte1 TX OE(2T, 0.5T) = (3, 3)
8063 00:39:13.840927
8064 00:39:13.841041
8065 00:39:13.847379 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8066 00:39:13.850446 CH0 RK0: MR19=303, MR18=1312
8067 00:39:13.857036 CH0_RK0: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8068 00:39:13.857170
8069 00:39:13.860527 ----->DramcWriteLeveling(PI) begin...
8070 00:39:13.860662 ==
8071 00:39:13.863543 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 00:39:13.867015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 00:39:13.867144 ==
8074 00:39:13.870127 Write leveling (Byte 0): 34 => 34
8075 00:39:13.873561 Write leveling (Byte 1): 29 => 29
8076 00:39:13.877238 DramcWriteLeveling(PI) end<-----
8077 00:39:13.877366
8078 00:39:13.877480 ==
8079 00:39:13.880142 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 00:39:13.883724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 00:39:13.883849 ==
8082 00:39:13.887075 [Gating] SW mode calibration
8083 00:39:13.893318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8084 00:39:13.900094 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8085 00:39:13.903299 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 00:39:13.909877 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 00:39:13.913333 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8088 00:39:13.916341 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8089 00:39:13.923437 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8090 00:39:13.926542 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8091 00:39:13.929955 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8092 00:39:13.936783 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 00:39:13.939775 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 00:39:13.943107 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8095 00:39:13.950060 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8096 00:39:13.952752 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8097 00:39:13.956031 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8098 00:39:13.962949 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8099 00:39:13.965886 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 00:39:13.969381 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 00:39:13.976394 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 00:39:13.979415 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 00:39:13.982817 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8104 00:39:13.988977 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8105 00:39:13.992683 1 6 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
8106 00:39:13.996263 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 00:39:14.002690 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 00:39:14.006190 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 00:39:14.009449 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 00:39:14.015512 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 00:39:14.018930 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8112 00:39:14.022559 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8113 00:39:14.028900 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8114 00:39:14.032299 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8115 00:39:14.035724 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 00:39:14.042068 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 00:39:14.045497 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 00:39:14.048948 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 00:39:14.055189 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 00:39:14.058470 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 00:39:14.061998 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 00:39:14.065273 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 00:39:14.071681 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 00:39:14.075139 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 00:39:14.078543 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 00:39:14.084908 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 00:39:14.088894 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8128 00:39:14.091925 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8129 00:39:14.098811 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8130 00:39:14.102007 Total UI for P1: 0, mck2ui 16
8131 00:39:14.105077 best dqsien dly found for B0: ( 1, 9, 10)
8132 00:39:14.108459 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8133 00:39:14.111881 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 00:39:14.115132 Total UI for P1: 0, mck2ui 16
8135 00:39:14.118545 best dqsien dly found for B1: ( 1, 9, 20)
8136 00:39:14.121599 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8137 00:39:14.125049 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8138 00:39:14.125132
8139 00:39:14.131827 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8140 00:39:14.134684 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8141 00:39:14.138137 [Gating] SW calibration Done
8142 00:39:14.138222 ==
8143 00:39:14.141581 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 00:39:14.145046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 00:39:14.145131 ==
8146 00:39:14.145197 RX Vref Scan: 0
8147 00:39:14.145259
8148 00:39:14.148314 RX Vref 0 -> 0, step: 1
8149 00:39:14.148398
8150 00:39:14.151607 RX Delay 0 -> 252, step: 8
8151 00:39:14.155013 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8152 00:39:14.158422 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8153 00:39:14.165128 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8154 00:39:14.168137 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8155 00:39:14.171542 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8156 00:39:14.174942 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8157 00:39:14.178418 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8158 00:39:14.184731 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8159 00:39:14.188147 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8160 00:39:14.191582 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8161 00:39:14.194930 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8162 00:39:14.198276 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8163 00:39:14.204972 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8164 00:39:14.208332 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8165 00:39:14.211200 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8166 00:39:14.214698 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8167 00:39:14.214822 ==
8168 00:39:14.218062 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 00:39:14.224779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 00:39:14.224904 ==
8171 00:39:14.225017 DQS Delay:
8172 00:39:14.225127 DQS0 = 0, DQS1 = 0
8173 00:39:14.227677 DQM Delay:
8174 00:39:14.227794 DQM0 = 127, DQM1 = 121
8175 00:39:14.231107 DQ Delay:
8176 00:39:14.234383 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8177 00:39:14.237998 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8178 00:39:14.241260 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8179 00:39:14.244470 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8180 00:39:14.244605
8181 00:39:14.244715
8182 00:39:14.244821 ==
8183 00:39:14.247762 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 00:39:14.250979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 00:39:14.254353 ==
8186 00:39:14.254492
8187 00:39:14.254591
8188 00:39:14.254651 TX Vref Scan disable
8189 00:39:14.257964 == TX Byte 0 ==
8190 00:39:14.260915 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8191 00:39:14.264263 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8192 00:39:14.267640 == TX Byte 1 ==
8193 00:39:14.270938 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8194 00:39:14.274257 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8195 00:39:14.274368 ==
8196 00:39:14.277521 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 00:39:14.284082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 00:39:14.284189 ==
8199 00:39:14.297700
8200 00:39:14.301305 TX Vref early break, caculate TX vref
8201 00:39:14.304030 TX Vref=16, minBit 0, minWin=22, winSum=367
8202 00:39:14.307510 TX Vref=18, minBit 0, minWin=22, winSum=377
8203 00:39:14.311083 TX Vref=20, minBit 8, minWin=22, winSum=379
8204 00:39:14.314085 TX Vref=22, minBit 8, minWin=23, winSum=391
8205 00:39:14.317605 TX Vref=24, minBit 0, minWin=25, winSum=404
8206 00:39:14.323946 TX Vref=26, minBit 0, minWin=24, winSum=407
8207 00:39:14.327369 TX Vref=28, minBit 0, minWin=24, winSum=407
8208 00:39:14.331050 TX Vref=30, minBit 13, minWin=24, winSum=409
8209 00:39:14.333975 TX Vref=32, minBit 3, minWin=24, winSum=395
8210 00:39:14.337497 TX Vref=34, minBit 8, minWin=22, winSum=391
8211 00:39:14.343961 TX Vref=36, minBit 8, minWin=22, winSum=383
8212 00:39:14.347296 [TxChooseVref] Worse bit 0, Min win 25, Win sum 404, Final Vref 24
8213 00:39:14.347412
8214 00:39:14.350735 Final TX Range 0 Vref 24
8215 00:39:14.350842
8216 00:39:14.350952 ==
8217 00:39:14.354056 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 00:39:14.357360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 00:39:14.357466 ==
8220 00:39:14.360614
8221 00:39:14.360720
8222 00:39:14.360819 TX Vref Scan disable
8223 00:39:14.367000 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8224 00:39:14.367113 == TX Byte 0 ==
8225 00:39:14.370607 u2DelayCellOfst[0]=11 cells (3 PI)
8226 00:39:14.374100 u2DelayCellOfst[1]=18 cells (5 PI)
8227 00:39:14.377377 u2DelayCellOfst[2]=11 cells (3 PI)
8228 00:39:14.380809 u2DelayCellOfst[3]=11 cells (3 PI)
8229 00:39:14.383903 u2DelayCellOfst[4]=7 cells (2 PI)
8230 00:39:14.386870 u2DelayCellOfst[5]=0 cells (0 PI)
8231 00:39:14.390365 u2DelayCellOfst[6]=18 cells (5 PI)
8232 00:39:14.393864 u2DelayCellOfst[7]=18 cells (5 PI)
8233 00:39:14.396913 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8234 00:39:14.400464 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8235 00:39:14.403510 == TX Byte 1 ==
8236 00:39:14.407145 u2DelayCellOfst[8]=0 cells (0 PI)
8237 00:39:14.410574 u2DelayCellOfst[9]=0 cells (0 PI)
8238 00:39:14.413529 u2DelayCellOfst[10]=3 cells (1 PI)
8239 00:39:14.417268 u2DelayCellOfst[11]=3 cells (1 PI)
8240 00:39:14.417383 u2DelayCellOfst[12]=11 cells (3 PI)
8241 00:39:14.420202 u2DelayCellOfst[13]=11 cells (3 PI)
8242 00:39:14.423553 u2DelayCellOfst[14]=15 cells (4 PI)
8243 00:39:14.427064 u2DelayCellOfst[15]=7 cells (2 PI)
8244 00:39:14.433458 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8245 00:39:14.436986 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8246 00:39:14.437065 DramC Write-DBI on
8247 00:39:14.437130 ==
8248 00:39:14.440004 Dram Type= 6, Freq= 0, CH_0, rank 1
8249 00:39:14.446630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 00:39:14.446716 ==
8251 00:39:14.446783
8252 00:39:14.446871
8253 00:39:14.450219 TX Vref Scan disable
8254 00:39:14.450307 == TX Byte 0 ==
8255 00:39:14.456586 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8256 00:39:14.456675 == TX Byte 1 ==
8257 00:39:14.460152 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8258 00:39:14.463329 DramC Write-DBI off
8259 00:39:14.463416
8260 00:39:14.463504 [DATLAT]
8261 00:39:14.466628 Freq=1600, CH0 RK1
8262 00:39:14.466715
8263 00:39:14.466802 DATLAT Default: 0xf
8264 00:39:14.470249 0, 0xFFFF, sum = 0
8265 00:39:14.470338 1, 0xFFFF, sum = 0
8266 00:39:14.473031 2, 0xFFFF, sum = 0
8267 00:39:14.473120 3, 0xFFFF, sum = 0
8268 00:39:14.476638 4, 0xFFFF, sum = 0
8269 00:39:14.476727 5, 0xFFFF, sum = 0
8270 00:39:14.480048 6, 0xFFFF, sum = 0
8271 00:39:14.480136 7, 0xFFFF, sum = 0
8272 00:39:14.483327 8, 0xFFFF, sum = 0
8273 00:39:14.483435 9, 0xFFFF, sum = 0
8274 00:39:14.486458 10, 0xFFFF, sum = 0
8275 00:39:14.489846 11, 0xFFFF, sum = 0
8276 00:39:14.489985 12, 0xFFFF, sum = 0
8277 00:39:14.493242 13, 0xCFFF, sum = 0
8278 00:39:14.493340 14, 0x0, sum = 1
8279 00:39:14.496388 15, 0x0, sum = 2
8280 00:39:14.496492 16, 0x0, sum = 3
8281 00:39:14.499908 17, 0x0, sum = 4
8282 00:39:14.499994 best_step = 15
8283 00:39:14.500063
8284 00:39:14.500124 ==
8285 00:39:14.502830 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 00:39:14.506060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 00:39:14.506141 ==
8288 00:39:14.509765 RX Vref Scan: 0
8289 00:39:14.509860
8290 00:39:14.512656 RX Vref 0 -> 0, step: 1
8291 00:39:14.512743
8292 00:39:14.512808 RX Delay 3 -> 252, step: 4
8293 00:39:14.520055 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8294 00:39:14.523031 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8295 00:39:14.526673 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8296 00:39:14.530093 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8297 00:39:14.533341 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8298 00:39:14.539880 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8299 00:39:14.543394 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8300 00:39:14.546336 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8301 00:39:14.549876 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8302 00:39:14.553349 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8303 00:39:14.559600 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8304 00:39:14.563122 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8305 00:39:14.566135 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8306 00:39:14.569580 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8307 00:39:14.576487 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8308 00:39:14.579404 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8309 00:39:14.579512 ==
8310 00:39:14.583008 Dram Type= 6, Freq= 0, CH_0, rank 1
8311 00:39:14.586554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 00:39:14.586681 ==
8313 00:39:14.586795 DQS Delay:
8314 00:39:14.589361 DQS0 = 0, DQS1 = 0
8315 00:39:14.589479 DQM Delay:
8316 00:39:14.593061 DQM0 = 124, DQM1 = 118
8317 00:39:14.593187 DQ Delay:
8318 00:39:14.595890 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8319 00:39:14.599600 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8320 00:39:14.602586 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8321 00:39:14.609734 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8322 00:39:14.609860
8323 00:39:14.609973
8324 00:39:14.610085
8325 00:39:14.612401 [DramC_TX_OE_Calibration] TA2
8326 00:39:14.615631 Original DQ_B0 (3 6) =30, OEN = 27
8327 00:39:14.615758 Original DQ_B1 (3 6) =30, OEN = 27
8328 00:39:14.619501 24, 0x0, End_B0=24 End_B1=24
8329 00:39:14.622259 25, 0x0, End_B0=25 End_B1=25
8330 00:39:14.625956 26, 0x0, End_B0=26 End_B1=26
8331 00:39:14.629439 27, 0x0, End_B0=27 End_B1=27
8332 00:39:14.629521 28, 0x0, End_B0=28 End_B1=28
8333 00:39:14.632561 29, 0x0, End_B0=29 End_B1=29
8334 00:39:14.635728 30, 0x0, End_B0=30 End_B1=30
8335 00:39:14.639282 31, 0x4545, End_B0=30 End_B1=30
8336 00:39:14.642227 Byte0 end_step=30 best_step=27
8337 00:39:14.642348 Byte1 end_step=30 best_step=27
8338 00:39:14.645811 Byte0 TX OE(2T, 0.5T) = (3, 3)
8339 00:39:14.649307 Byte1 TX OE(2T, 0.5T) = (3, 3)
8340 00:39:14.649426
8341 00:39:14.649522
8342 00:39:14.659111 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8343 00:39:14.659194 CH0 RK1: MR19=303, MR18=2411
8344 00:39:14.665546 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8345 00:39:14.668992 [RxdqsGatingPostProcess] freq 1600
8346 00:39:14.675395 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8347 00:39:14.678675 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 00:39:14.681735 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 00:39:14.685007 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 00:39:14.688361 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 00:39:14.691911 best DQS0 dly(2T, 0.5T) = (1, 1)
8352 00:39:14.691995 best DQS1 dly(2T, 0.5T) = (1, 1)
8353 00:39:14.695160 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8354 00:39:14.698610 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8355 00:39:14.701939 Pre-setting of DQS Precalculation
8356 00:39:14.708432 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8357 00:39:14.708546 ==
8358 00:39:14.711399 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 00:39:14.714804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 00:39:14.714913 ==
8361 00:39:14.721858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8362 00:39:14.724754 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8363 00:39:14.728058 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8364 00:39:14.734973 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8365 00:39:14.744207 [CA 0] Center 41 (12~71) winsize 60
8366 00:39:14.747473 [CA 1] Center 42 (13~72) winsize 60
8367 00:39:14.751082 [CA 2] Center 37 (9~66) winsize 58
8368 00:39:14.754468 [CA 3] Center 36 (7~66) winsize 60
8369 00:39:14.757623 [CA 4] Center 37 (8~66) winsize 59
8370 00:39:14.760788 [CA 5] Center 36 (7~66) winsize 60
8371 00:39:14.760882
8372 00:39:14.764189 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8373 00:39:14.764310
8374 00:39:14.767218 [CATrainingPosCal] consider 1 rank data
8375 00:39:14.770785 u2DelayCellTimex100 = 258/100 ps
8376 00:39:14.774130 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8377 00:39:14.780533 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8378 00:39:14.784171 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8379 00:39:14.787432 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8380 00:39:14.790645 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8381 00:39:14.794004 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8382 00:39:14.794084
8383 00:39:14.797216 CA PerBit enable=1, Macro0, CA PI delay=36
8384 00:39:14.797303
8385 00:39:14.800983 [CBTSetCACLKResult] CA Dly = 36
8386 00:39:14.803586 CS Dly: 10 (0~41)
8387 00:39:14.807172 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8388 00:39:14.810286 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8389 00:39:14.810370 ==
8390 00:39:14.813871 Dram Type= 6, Freq= 0, CH_1, rank 1
8391 00:39:14.816901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 00:39:14.820346 ==
8393 00:39:14.823516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8394 00:39:14.827185 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8395 00:39:14.833548 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8396 00:39:14.840070 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8397 00:39:14.847457 [CA 0] Center 41 (12~71) winsize 60
8398 00:39:14.850913 [CA 1] Center 42 (12~72) winsize 61
8399 00:39:14.854291 [CA 2] Center 37 (8~67) winsize 60
8400 00:39:14.857108 [CA 3] Center 36 (7~66) winsize 60
8401 00:39:14.860660 [CA 4] Center 37 (8~67) winsize 60
8402 00:39:14.863893 [CA 5] Center 36 (6~66) winsize 61
8403 00:39:14.863973
8404 00:39:14.867223 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8405 00:39:14.867302
8406 00:39:14.870789 [CATrainingPosCal] consider 2 rank data
8407 00:39:14.873698 u2DelayCellTimex100 = 258/100 ps
8408 00:39:14.880275 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8409 00:39:14.883557 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8410 00:39:14.887192 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8411 00:39:14.890630 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8412 00:39:14.893513 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8413 00:39:14.896869 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8414 00:39:14.896948
8415 00:39:14.899972 CA PerBit enable=1, Macro0, CA PI delay=36
8416 00:39:14.900047
8417 00:39:14.903450 [CBTSetCACLKResult] CA Dly = 36
8418 00:39:14.906924 CS Dly: 11 (0~43)
8419 00:39:14.910179 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8420 00:39:14.913626 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8421 00:39:14.913704
8422 00:39:14.916537 ----->DramcWriteLeveling(PI) begin...
8423 00:39:14.916625 ==
8424 00:39:14.920032 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 00:39:14.926684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 00:39:14.926780 ==
8427 00:39:14.930113 Write leveling (Byte 0): 23 => 23
8428 00:39:14.933554 Write leveling (Byte 1): 27 => 27
8429 00:39:14.933638 DramcWriteLeveling(PI) end<-----
8430 00:39:14.933705
8431 00:39:14.937140 ==
8432 00:39:14.939997 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 00:39:14.943357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 00:39:14.943435 ==
8435 00:39:14.946654 [Gating] SW mode calibration
8436 00:39:14.952974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8437 00:39:14.956762 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8438 00:39:14.963158 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 00:39:14.966575 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 00:39:14.969566 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 00:39:14.976327 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 00:39:14.979661 1 4 16 | B1->B0 | 302f 3030 | 1 0 | (0 0) (0 0)
8443 00:39:14.982551 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 00:39:14.989225 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 00:39:14.992419 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 00:39:14.995928 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 00:39:15.002466 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 00:39:15.006086 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 00:39:15.009013 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8450 00:39:15.015944 1 5 16 | B1->B0 | 2e2e 2a2a | 0 0 | (0 1) (1 0)
8451 00:39:15.019189 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 00:39:15.022373 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 00:39:15.029009 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 00:39:15.032426 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 00:39:15.035983 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 00:39:15.042380 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 00:39:15.045736 1 6 12 | B1->B0 | 2727 2929 | 0 1 | (0 0) (0 0)
8458 00:39:15.048950 1 6 16 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
8459 00:39:15.055605 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 00:39:15.058938 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 00:39:15.062491 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 00:39:15.069085 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 00:39:15.072513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 00:39:15.075481 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 00:39:15.082425 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8466 00:39:15.085898 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8467 00:39:15.088687 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8468 00:39:15.095502 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 00:39:15.098889 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 00:39:15.101879 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 00:39:15.108673 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 00:39:15.111952 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 00:39:15.115490 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 00:39:15.121761 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 00:39:15.125421 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 00:39:15.128779 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 00:39:15.131861 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 00:39:15.138463 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 00:39:15.141894 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 00:39:15.145352 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 00:39:15.151779 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8482 00:39:15.155202 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8483 00:39:15.158337 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 00:39:15.161797 Total UI for P1: 0, mck2ui 16
8485 00:39:15.165195 best dqsien dly found for B0: ( 1, 9, 14)
8486 00:39:15.168683 Total UI for P1: 0, mck2ui 16
8487 00:39:15.171988 best dqsien dly found for B1: ( 1, 9, 14)
8488 00:39:15.174954 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8489 00:39:15.178181 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8490 00:39:15.181486
8491 00:39:15.185061 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8492 00:39:15.187933 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8493 00:39:15.191921 [Gating] SW calibration Done
8494 00:39:15.192055 ==
8495 00:39:15.194832 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 00:39:15.198286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 00:39:15.198417 ==
8498 00:39:15.201671 RX Vref Scan: 0
8499 00:39:15.201800
8500 00:39:15.201915 RX Vref 0 -> 0, step: 1
8501 00:39:15.202033
8502 00:39:15.204628 RX Delay 0 -> 252, step: 8
8503 00:39:15.208028 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8504 00:39:15.211638 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8505 00:39:15.218054 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8506 00:39:15.221199 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8507 00:39:15.224682 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8508 00:39:15.228098 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8509 00:39:15.231720 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8510 00:39:15.237863 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8511 00:39:15.241438 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8512 00:39:15.244340 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8513 00:39:15.247738 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8514 00:39:15.251342 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8515 00:39:15.257662 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8516 00:39:15.261060 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8517 00:39:15.264416 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8518 00:39:15.267815 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8519 00:39:15.267941 ==
8520 00:39:15.271164 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 00:39:15.277515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 00:39:15.277645 ==
8523 00:39:15.277763 DQS Delay:
8524 00:39:15.280843 DQS0 = 0, DQS1 = 0
8525 00:39:15.280974 DQM Delay:
8526 00:39:15.284051 DQM0 = 132, DQM1 = 125
8527 00:39:15.284181 DQ Delay:
8528 00:39:15.287560 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8529 00:39:15.290635 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8530 00:39:15.294194 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8531 00:39:15.297572 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8532 00:39:15.297699
8533 00:39:15.297814
8534 00:39:15.297925 ==
8535 00:39:15.300945 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 00:39:15.307233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 00:39:15.307359 ==
8538 00:39:15.307474
8539 00:39:15.307594
8540 00:39:15.307705 TX Vref Scan disable
8541 00:39:15.310671 == TX Byte 0 ==
8542 00:39:15.314115 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8543 00:39:15.320890 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8544 00:39:15.321016 == TX Byte 1 ==
8545 00:39:15.323835 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8546 00:39:15.330934 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8547 00:39:15.331061 ==
8548 00:39:15.333773 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 00:39:15.337057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 00:39:15.337184 ==
8551 00:39:15.349659
8552 00:39:15.353229 TX Vref early break, caculate TX vref
8553 00:39:15.356375 TX Vref=16, minBit 1, minWin=21, winSum=354
8554 00:39:15.359786 TX Vref=18, minBit 1, minWin=22, winSum=366
8555 00:39:15.363058 TX Vref=20, minBit 4, minWin=22, winSum=374
8556 00:39:15.366495 TX Vref=22, minBit 0, minWin=24, winSum=395
8557 00:39:15.369508 TX Vref=24, minBit 0, minWin=24, winSum=401
8558 00:39:15.375926 TX Vref=26, minBit 1, minWin=24, winSum=407
8559 00:39:15.379314 TX Vref=28, minBit 1, minWin=23, winSum=413
8560 00:39:15.382916 TX Vref=30, minBit 0, minWin=22, winSum=408
8561 00:39:15.385761 TX Vref=32, minBit 1, minWin=23, winSum=403
8562 00:39:15.389320 TX Vref=34, minBit 1, minWin=21, winSum=389
8563 00:39:15.395755 [TxChooseVref] Worse bit 1, Min win 24, Win sum 407, Final Vref 26
8564 00:39:15.395866
8565 00:39:15.399132 Final TX Range 0 Vref 26
8566 00:39:15.399267
8567 00:39:15.399379 ==
8568 00:39:15.402419 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 00:39:15.405843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 00:39:15.405970 ==
8571 00:39:15.406086
8572 00:39:15.406198
8573 00:39:15.409155 TX Vref Scan disable
8574 00:39:15.415844 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8575 00:39:15.415972 == TX Byte 0 ==
8576 00:39:15.419053 u2DelayCellOfst[0]=18 cells (5 PI)
8577 00:39:15.422487 u2DelayCellOfst[1]=18 cells (5 PI)
8578 00:39:15.425605 u2DelayCellOfst[2]=0 cells (0 PI)
8579 00:39:15.429013 u2DelayCellOfst[3]=3 cells (1 PI)
8580 00:39:15.432581 u2DelayCellOfst[4]=11 cells (3 PI)
8581 00:39:15.435496 u2DelayCellOfst[5]=22 cells (6 PI)
8582 00:39:15.438834 u2DelayCellOfst[6]=22 cells (6 PI)
8583 00:39:15.442112 u2DelayCellOfst[7]=3 cells (1 PI)
8584 00:39:15.445563 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8585 00:39:15.448882 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8586 00:39:15.452420 == TX Byte 1 ==
8587 00:39:15.455474 u2DelayCellOfst[8]=0 cells (0 PI)
8588 00:39:15.455584 u2DelayCellOfst[9]=11 cells (3 PI)
8589 00:39:15.458729 u2DelayCellOfst[10]=15 cells (4 PI)
8590 00:39:15.462485 u2DelayCellOfst[11]=7 cells (2 PI)
8591 00:39:15.465549 u2DelayCellOfst[12]=15 cells (4 PI)
8592 00:39:15.468773 u2DelayCellOfst[13]=22 cells (6 PI)
8593 00:39:15.472129 u2DelayCellOfst[14]=22 cells (6 PI)
8594 00:39:15.475636 u2DelayCellOfst[15]=26 cells (7 PI)
8595 00:39:15.478611 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8596 00:39:15.485194 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8597 00:39:15.485311 DramC Write-DBI on
8598 00:39:15.485404 ==
8599 00:39:15.488677 Dram Type= 6, Freq= 0, CH_1, rank 0
8600 00:39:15.495116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8601 00:39:15.495247 ==
8602 00:39:15.495363
8603 00:39:15.495480
8604 00:39:15.495590 TX Vref Scan disable
8605 00:39:15.499115 == TX Byte 0 ==
8606 00:39:15.502659 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8607 00:39:15.505568 == TX Byte 1 ==
8608 00:39:15.509068 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8609 00:39:15.512535 DramC Write-DBI off
8610 00:39:15.512650
8611 00:39:15.512717 [DATLAT]
8612 00:39:15.512779 Freq=1600, CH1 RK0
8613 00:39:15.512854
8614 00:39:15.515929 DATLAT Default: 0xf
8615 00:39:15.516043 0, 0xFFFF, sum = 0
8616 00:39:15.519080 1, 0xFFFF, sum = 0
8617 00:39:15.522158 2, 0xFFFF, sum = 0
8618 00:39:15.522236 3, 0xFFFF, sum = 0
8619 00:39:15.525749 4, 0xFFFF, sum = 0
8620 00:39:15.525854 5, 0xFFFF, sum = 0
8621 00:39:15.529072 6, 0xFFFF, sum = 0
8622 00:39:15.529169 7, 0xFFFF, sum = 0
8623 00:39:15.532259 8, 0xFFFF, sum = 0
8624 00:39:15.532338 9, 0xFFFF, sum = 0
8625 00:39:15.535284 10, 0xFFFF, sum = 0
8626 00:39:15.535397 11, 0xFFFF, sum = 0
8627 00:39:15.538997 12, 0xFFFF, sum = 0
8628 00:39:15.539081 13, 0x8FFF, sum = 0
8629 00:39:15.542509 14, 0x0, sum = 1
8630 00:39:15.542600 15, 0x0, sum = 2
8631 00:39:15.545201 16, 0x0, sum = 3
8632 00:39:15.545298 17, 0x0, sum = 4
8633 00:39:15.548673 best_step = 15
8634 00:39:15.548747
8635 00:39:15.548809 ==
8636 00:39:15.551869 Dram Type= 6, Freq= 0, CH_1, rank 0
8637 00:39:15.555570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8638 00:39:15.555689 ==
8639 00:39:15.558667 RX Vref Scan: 1
8640 00:39:15.558780
8641 00:39:15.558872 Set Vref Range= 24 -> 127
8642 00:39:15.558960
8643 00:39:15.562145 RX Vref 24 -> 127, step: 1
8644 00:39:15.562254
8645 00:39:15.565112 RX Delay 11 -> 252, step: 4
8646 00:39:15.565193
8647 00:39:15.568356 Set Vref, RX VrefLevel [Byte0]: 24
8648 00:39:15.571704 [Byte1]: 24
8649 00:39:15.571823
8650 00:39:15.575083 Set Vref, RX VrefLevel [Byte0]: 25
8651 00:39:15.578283 [Byte1]: 25
8652 00:39:15.582277
8653 00:39:15.582361 Set Vref, RX VrefLevel [Byte0]: 26
8654 00:39:15.585069 [Byte1]: 26
8655 00:39:15.589635
8656 00:39:15.589720 Set Vref, RX VrefLevel [Byte0]: 27
8657 00:39:15.593139 [Byte1]: 27
8658 00:39:15.597357
8659 00:39:15.597446 Set Vref, RX VrefLevel [Byte0]: 28
8660 00:39:15.600254 [Byte1]: 28
8661 00:39:15.604494
8662 00:39:15.604616 Set Vref, RX VrefLevel [Byte0]: 29
8663 00:39:15.608237 [Byte1]: 29
8664 00:39:15.612347
8665 00:39:15.612459 Set Vref, RX VrefLevel [Byte0]: 30
8666 00:39:15.615386 [Byte1]: 30
8667 00:39:15.619770
8668 00:39:15.619878 Set Vref, RX VrefLevel [Byte0]: 31
8669 00:39:15.622959 [Byte1]: 31
8670 00:39:15.627780
8671 00:39:15.627867 Set Vref, RX VrefLevel [Byte0]: 32
8672 00:39:15.630624 [Byte1]: 32
8673 00:39:15.635550
8674 00:39:15.635653 Set Vref, RX VrefLevel [Byte0]: 33
8675 00:39:15.638596 [Byte1]: 33
8676 00:39:15.642749
8677 00:39:15.642854 Set Vref, RX VrefLevel [Byte0]: 34
8678 00:39:15.645979 [Byte1]: 34
8679 00:39:15.650186
8680 00:39:15.650292 Set Vref, RX VrefLevel [Byte0]: 35
8681 00:39:15.653577 [Byte1]: 35
8682 00:39:15.657746
8683 00:39:15.657873 Set Vref, RX VrefLevel [Byte0]: 36
8684 00:39:15.661378 [Byte1]: 36
8685 00:39:15.665735
8686 00:39:15.665847 Set Vref, RX VrefLevel [Byte0]: 37
8687 00:39:15.668876 [Byte1]: 37
8688 00:39:15.673430
8689 00:39:15.673506 Set Vref, RX VrefLevel [Byte0]: 38
8690 00:39:15.676605 [Byte1]: 38
8691 00:39:15.680779
8692 00:39:15.680874 Set Vref, RX VrefLevel [Byte0]: 39
8693 00:39:15.684285 [Byte1]: 39
8694 00:39:15.688522
8695 00:39:15.688652 Set Vref, RX VrefLevel [Byte0]: 40
8696 00:39:15.691625 [Byte1]: 40
8697 00:39:15.696056
8698 00:39:15.696191 Set Vref, RX VrefLevel [Byte0]: 41
8699 00:39:15.699498 [Byte1]: 41
8700 00:39:15.703611
8701 00:39:15.703722 Set Vref, RX VrefLevel [Byte0]: 42
8702 00:39:15.707159 [Byte1]: 42
8703 00:39:15.711211
8704 00:39:15.711339 Set Vref, RX VrefLevel [Byte0]: 43
8705 00:39:15.714868 [Byte1]: 43
8706 00:39:15.718863
8707 00:39:15.718989 Set Vref, RX VrefLevel [Byte0]: 44
8708 00:39:15.721928 [Byte1]: 44
8709 00:39:15.726395
8710 00:39:15.726522 Set Vref, RX VrefLevel [Byte0]: 45
8711 00:39:15.729987 [Byte1]: 45
8712 00:39:15.734097
8713 00:39:15.734224 Set Vref, RX VrefLevel [Byte0]: 46
8714 00:39:15.737557 [Byte1]: 46
8715 00:39:15.741573
8716 00:39:15.741682 Set Vref, RX VrefLevel [Byte0]: 47
8717 00:39:15.745290 [Byte1]: 47
8718 00:39:15.749103
8719 00:39:15.749230 Set Vref, RX VrefLevel [Byte0]: 48
8720 00:39:15.752500 [Byte1]: 48
8721 00:39:15.756885
8722 00:39:15.756997 Set Vref, RX VrefLevel [Byte0]: 49
8723 00:39:15.759952 [Byte1]: 49
8724 00:39:15.764601
8725 00:39:15.764723 Set Vref, RX VrefLevel [Byte0]: 50
8726 00:39:15.770985 [Byte1]: 50
8727 00:39:15.771113
8728 00:39:15.774246 Set Vref, RX VrefLevel [Byte0]: 51
8729 00:39:15.777658 [Byte1]: 51
8730 00:39:15.777784
8731 00:39:15.781298 Set Vref, RX VrefLevel [Byte0]: 52
8732 00:39:15.784191 [Byte1]: 52
8733 00:39:15.784315
8734 00:39:15.787374 Set Vref, RX VrefLevel [Byte0]: 53
8735 00:39:15.791095 [Byte1]: 53
8736 00:39:15.795571
8737 00:39:15.795680 Set Vref, RX VrefLevel [Byte0]: 54
8738 00:39:15.798406 [Byte1]: 54
8739 00:39:15.803010
8740 00:39:15.803116 Set Vref, RX VrefLevel [Byte0]: 55
8741 00:39:15.805793 [Byte1]: 55
8742 00:39:15.810178
8743 00:39:15.810289 Set Vref, RX VrefLevel [Byte0]: 56
8744 00:39:15.813545 [Byte1]: 56
8745 00:39:15.817665
8746 00:39:15.817792 Set Vref, RX VrefLevel [Byte0]: 57
8747 00:39:15.821067 [Byte1]: 57
8748 00:39:15.825634
8749 00:39:15.825761 Set Vref, RX VrefLevel [Byte0]: 58
8750 00:39:15.828519 [Byte1]: 58
8751 00:39:15.833414
8752 00:39:15.833541 Set Vref, RX VrefLevel [Byte0]: 59
8753 00:39:15.836374 [Byte1]: 59
8754 00:39:15.840881
8755 00:39:15.841002 Set Vref, RX VrefLevel [Byte0]: 60
8756 00:39:15.843771 [Byte1]: 60
8757 00:39:15.848415
8758 00:39:15.848499 Set Vref, RX VrefLevel [Byte0]: 61
8759 00:39:15.851497 [Byte1]: 61
8760 00:39:15.856038
8761 00:39:15.856165 Set Vref, RX VrefLevel [Byte0]: 62
8762 00:39:15.859028 [Byte1]: 62
8763 00:39:15.863734
8764 00:39:15.863856 Set Vref, RX VrefLevel [Byte0]: 63
8765 00:39:15.867072 [Byte1]: 63
8766 00:39:15.871369
8767 00:39:15.871492 Set Vref, RX VrefLevel [Byte0]: 64
8768 00:39:15.874476 [Byte1]: 64
8769 00:39:15.878878
8770 00:39:15.879006 Set Vref, RX VrefLevel [Byte0]: 65
8771 00:39:15.882025 [Byte1]: 65
8772 00:39:15.886644
8773 00:39:15.886770 Set Vref, RX VrefLevel [Byte0]: 66
8774 00:39:15.889430 [Byte1]: 66
8775 00:39:15.894106
8776 00:39:15.894229 Set Vref, RX VrefLevel [Byte0]: 67
8777 00:39:15.897385 [Byte1]: 67
8778 00:39:15.901706
8779 00:39:15.901833 Set Vref, RX VrefLevel [Byte0]: 68
8780 00:39:15.905130 [Byte1]: 68
8781 00:39:15.909132
8782 00:39:15.909256 Set Vref, RX VrefLevel [Byte0]: 69
8783 00:39:15.912407 [Byte1]: 69
8784 00:39:15.916870
8785 00:39:15.916995 Set Vref, RX VrefLevel [Byte0]: 70
8786 00:39:15.920522 [Byte1]: 70
8787 00:39:15.924899
8788 00:39:15.925023 Set Vref, RX VrefLevel [Byte0]: 71
8789 00:39:15.927781 [Byte1]: 71
8790 00:39:15.932479
8791 00:39:15.932604 Set Vref, RX VrefLevel [Byte0]: 72
8792 00:39:15.935677 [Byte1]: 72
8793 00:39:15.939758
8794 00:39:15.939879 Set Vref, RX VrefLevel [Byte0]: 73
8795 00:39:15.943205 [Byte1]: 73
8796 00:39:15.947271
8797 00:39:15.947356 Set Vref, RX VrefLevel [Byte0]: 74
8798 00:39:15.950568 [Byte1]: 74
8799 00:39:15.955228
8800 00:39:15.955311 Final RX Vref Byte 0 = 58 to rank0
8801 00:39:15.958484 Final RX Vref Byte 1 = 51 to rank0
8802 00:39:15.961382 Final RX Vref Byte 0 = 58 to rank1
8803 00:39:15.964513 Final RX Vref Byte 1 = 51 to rank1==
8804 00:39:15.968077 Dram Type= 6, Freq= 0, CH_1, rank 0
8805 00:39:15.975131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 00:39:15.975210 ==
8807 00:39:15.975274 DQS Delay:
8808 00:39:15.977761 DQS0 = 0, DQS1 = 0
8809 00:39:15.977836 DQM Delay:
8810 00:39:15.977897 DQM0 = 131, DQM1 = 122
8811 00:39:15.981139 DQ Delay:
8812 00:39:15.984481 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8813 00:39:15.987821 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8814 00:39:15.991511 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =114
8815 00:39:15.994479 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =130
8816 00:39:15.994558
8817 00:39:15.994625
8818 00:39:15.994725
8819 00:39:15.998074 [DramC_TX_OE_Calibration] TA2
8820 00:39:16.001505 Original DQ_B0 (3 6) =30, OEN = 27
8821 00:39:16.004665 Original DQ_B1 (3 6) =30, OEN = 27
8822 00:39:16.007943 24, 0x0, End_B0=24 End_B1=24
8823 00:39:16.008029 25, 0x0, End_B0=25 End_B1=25
8824 00:39:16.011467 26, 0x0, End_B0=26 End_B1=26
8825 00:39:16.014296 27, 0x0, End_B0=27 End_B1=27
8826 00:39:16.017623 28, 0x0, End_B0=28 End_B1=28
8827 00:39:16.021135 29, 0x0, End_B0=29 End_B1=29
8828 00:39:16.021221 30, 0x0, End_B0=30 End_B1=30
8829 00:39:16.024649 31, 0x4141, End_B0=30 End_B1=30
8830 00:39:16.027499 Byte0 end_step=30 best_step=27
8831 00:39:16.031053 Byte1 end_step=30 best_step=27
8832 00:39:16.034286 Byte0 TX OE(2T, 0.5T) = (3, 3)
8833 00:39:16.037599 Byte1 TX OE(2T, 0.5T) = (3, 3)
8834 00:39:16.037684
8835 00:39:16.037749
8836 00:39:16.044318 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8837 00:39:16.047521 CH1 RK0: MR19=303, MR18=70C
8838 00:39:16.054195 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8839 00:39:16.054280
8840 00:39:16.057909 ----->DramcWriteLeveling(PI) begin...
8841 00:39:16.057994 ==
8842 00:39:16.061018 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 00:39:16.064051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 00:39:16.064136 ==
8845 00:39:16.067476 Write leveling (Byte 0): 22 => 22
8846 00:39:16.070968 Write leveling (Byte 1): 28 => 28
8847 00:39:16.074300 DramcWriteLeveling(PI) end<-----
8848 00:39:16.074384
8849 00:39:16.074448 ==
8850 00:39:16.077132 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 00:39:16.080474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 00:39:16.080565 ==
8853 00:39:16.083915 [Gating] SW mode calibration
8854 00:39:16.090748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8855 00:39:16.097100 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8856 00:39:16.100134 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 00:39:16.107196 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8858 00:39:16.110174 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8859 00:39:16.113768 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8860 00:39:16.120342 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8861 00:39:16.123790 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8862 00:39:16.126821 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8863 00:39:16.133386 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 00:39:16.136955 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8865 00:39:16.139794 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8866 00:39:16.146526 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
8867 00:39:16.149921 1 5 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
8868 00:39:16.153244 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 00:39:16.160006 1 5 20 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8870 00:39:16.163386 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8871 00:39:16.166440 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 00:39:16.172903 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 00:39:16.176245 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 00:39:16.179496 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8875 00:39:16.182816 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8876 00:39:16.189665 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 00:39:16.193170 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 00:39:16.196012 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 00:39:16.202880 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 00:39:16.206223 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 00:39:16.209682 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 00:39:16.216270 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8883 00:39:16.219773 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8884 00:39:16.222604 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 00:39:16.229134 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 00:39:16.232605 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 00:39:16.235875 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 00:39:16.242605 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 00:39:16.246160 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 00:39:16.249615 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 00:39:16.256207 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 00:39:16.259429 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 00:39:16.262304 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 00:39:16.269326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 00:39:16.272579 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 00:39:16.276016 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 00:39:16.282447 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 00:39:16.285688 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8899 00:39:16.289285 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8900 00:39:16.292253 Total UI for P1: 0, mck2ui 16
8901 00:39:16.295665 best dqsien dly found for B0: ( 1, 9, 8)
8902 00:39:16.301999 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8903 00:39:16.302125 Total UI for P1: 0, mck2ui 16
8904 00:39:16.308872 best dqsien dly found for B1: ( 1, 9, 12)
8905 00:39:16.312361 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8906 00:39:16.315576 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8907 00:39:16.315699
8908 00:39:16.319069 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8909 00:39:16.321784 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8910 00:39:16.325221 [Gating] SW calibration Done
8911 00:39:16.325342 ==
8912 00:39:16.328731 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 00:39:16.332012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 00:39:16.332147 ==
8915 00:39:16.335431 RX Vref Scan: 0
8916 00:39:16.335551
8917 00:39:16.335660 RX Vref 0 -> 0, step: 1
8918 00:39:16.335768
8919 00:39:16.339079 RX Delay 0 -> 252, step: 8
8920 00:39:16.341931 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8921 00:39:16.348636 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8922 00:39:16.352093 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8923 00:39:16.355647 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8924 00:39:16.358619 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8925 00:39:16.361989 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8926 00:39:16.368384 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8927 00:39:16.372148 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8928 00:39:16.375005 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8929 00:39:16.378380 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8930 00:39:16.381946 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8931 00:39:16.388273 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8932 00:39:16.391792 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8933 00:39:16.395253 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8934 00:39:16.398231 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8935 00:39:16.401607 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8936 00:39:16.405163 ==
8937 00:39:16.408415 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 00:39:16.411676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 00:39:16.411766 ==
8940 00:39:16.411853 DQS Delay:
8941 00:39:16.414673 DQS0 = 0, DQS1 = 0
8942 00:39:16.414763 DQM Delay:
8943 00:39:16.418517 DQM0 = 131, DQM1 = 127
8944 00:39:16.418605 DQ Delay:
8945 00:39:16.421670 DQ0 =139, DQ1 =127, DQ2 =115, DQ3 =131
8946 00:39:16.424815 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =127
8947 00:39:16.428327 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8948 00:39:16.431888 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8949 00:39:16.431973
8950 00:39:16.432037
8951 00:39:16.432097 ==
8952 00:39:16.434821 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 00:39:16.441305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 00:39:16.441389 ==
8955 00:39:16.441454
8956 00:39:16.441514
8957 00:39:16.441572 TX Vref Scan disable
8958 00:39:16.445487 == TX Byte 0 ==
8959 00:39:16.448462 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8960 00:39:16.452072 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8961 00:39:16.455546 == TX Byte 1 ==
8962 00:39:16.458640 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8963 00:39:16.465072 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8964 00:39:16.465156 ==
8965 00:39:16.468409 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 00:39:16.471595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 00:39:16.471698 ==
8968 00:39:16.484911
8969 00:39:16.487900 TX Vref early break, caculate TX vref
8970 00:39:16.491056 TX Vref=16, minBit 0, minWin=22, winSum=374
8971 00:39:16.494304 TX Vref=18, minBit 0, minWin=22, winSum=382
8972 00:39:16.498124 TX Vref=20, minBit 0, minWin=21, winSum=388
8973 00:39:16.501064 TX Vref=22, minBit 0, minWin=23, winSum=400
8974 00:39:16.504460 TX Vref=24, minBit 0, minWin=23, winSum=402
8975 00:39:16.510902 TX Vref=26, minBit 0, minWin=22, winSum=409
8976 00:39:16.514436 TX Vref=28, minBit 5, minWin=24, winSum=414
8977 00:39:16.517940 TX Vref=30, minBit 1, minWin=24, winSum=410
8978 00:39:16.521100 TX Vref=32, minBit 6, minWin=23, winSum=403
8979 00:39:16.524438 TX Vref=34, minBit 0, minWin=22, winSum=392
8980 00:39:16.531093 [TxChooseVref] Worse bit 5, Min win 24, Win sum 414, Final Vref 28
8981 00:39:16.531222
8982 00:39:16.534178 Final TX Range 0 Vref 28
8983 00:39:16.534302
8984 00:39:16.534414 ==
8985 00:39:16.537774 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 00:39:16.540939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 00:39:16.541065 ==
8988 00:39:16.541184
8989 00:39:16.541293
8990 00:39:16.543960 TX Vref Scan disable
8991 00:39:16.550953 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8992 00:39:16.551079 == TX Byte 0 ==
8993 00:39:16.553944 u2DelayCellOfst[0]=18 cells (5 PI)
8994 00:39:16.557556 u2DelayCellOfst[1]=15 cells (4 PI)
8995 00:39:16.561126 u2DelayCellOfst[2]=0 cells (0 PI)
8996 00:39:16.564003 u2DelayCellOfst[3]=3 cells (1 PI)
8997 00:39:16.567668 u2DelayCellOfst[4]=7 cells (2 PI)
8998 00:39:16.570532 u2DelayCellOfst[5]=22 cells (6 PI)
8999 00:39:16.573931 u2DelayCellOfst[6]=22 cells (6 PI)
9000 00:39:16.577450 u2DelayCellOfst[7]=7 cells (2 PI)
9001 00:39:16.580347 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
9002 00:39:16.583813 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
9003 00:39:16.586888 == TX Byte 1 ==
9004 00:39:16.586992 u2DelayCellOfst[8]=0 cells (0 PI)
9005 00:39:16.590742 u2DelayCellOfst[9]=7 cells (2 PI)
9006 00:39:16.594060 u2DelayCellOfst[10]=15 cells (4 PI)
9007 00:39:16.597015 u2DelayCellOfst[11]=7 cells (2 PI)
9008 00:39:16.600474 u2DelayCellOfst[12]=18 cells (5 PI)
9009 00:39:16.603457 u2DelayCellOfst[13]=18 cells (5 PI)
9010 00:39:16.607249 u2DelayCellOfst[14]=22 cells (6 PI)
9011 00:39:16.610329 u2DelayCellOfst[15]=22 cells (6 PI)
9012 00:39:16.613894 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9013 00:39:16.620085 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9014 00:39:16.620219 DramC Write-DBI on
9015 00:39:16.620334 ==
9016 00:39:16.623964 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 00:39:16.630297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 00:39:16.630422 ==
9019 00:39:16.630540
9020 00:39:16.630648
9021 00:39:16.630760 TX Vref Scan disable
9022 00:39:16.633825 == TX Byte 0 ==
9023 00:39:16.637438 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
9024 00:39:16.640442 == TX Byte 1 ==
9025 00:39:16.643965 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9026 00:39:16.647248 DramC Write-DBI off
9027 00:39:16.647368
9028 00:39:16.647486 [DATLAT]
9029 00:39:16.647595 Freq=1600, CH1 RK1
9030 00:39:16.647701
9031 00:39:16.650349 DATLAT Default: 0xf
9032 00:39:16.650473 0, 0xFFFF, sum = 0
9033 00:39:16.653714 1, 0xFFFF, sum = 0
9034 00:39:16.656851 2, 0xFFFF, sum = 0
9035 00:39:16.656975 3, 0xFFFF, sum = 0
9036 00:39:16.660256 4, 0xFFFF, sum = 0
9037 00:39:16.660377 5, 0xFFFF, sum = 0
9038 00:39:16.663513 6, 0xFFFF, sum = 0
9039 00:39:16.663644 7, 0xFFFF, sum = 0
9040 00:39:16.667144 8, 0xFFFF, sum = 0
9041 00:39:16.667272 9, 0xFFFF, sum = 0
9042 00:39:16.670082 10, 0xFFFF, sum = 0
9043 00:39:16.670207 11, 0xFFFF, sum = 0
9044 00:39:16.673608 12, 0xFFFF, sum = 0
9045 00:39:16.673732 13, 0x8FFF, sum = 0
9046 00:39:16.677065 14, 0x0, sum = 1
9047 00:39:16.677195 15, 0x0, sum = 2
9048 00:39:16.680080 16, 0x0, sum = 3
9049 00:39:16.680201 17, 0x0, sum = 4
9050 00:39:16.683452 best_step = 15
9051 00:39:16.683576
9052 00:39:16.683691 ==
9053 00:39:16.686996 Dram Type= 6, Freq= 0, CH_1, rank 1
9054 00:39:16.690268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9055 00:39:16.690394 ==
9056 00:39:16.693586 RX Vref Scan: 0
9057 00:39:16.693707
9058 00:39:16.693821 RX Vref 0 -> 0, step: 1
9059 00:39:16.693929
9060 00:39:16.696920 RX Delay 11 -> 252, step: 4
9061 00:39:16.703795 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9062 00:39:16.706640 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9063 00:39:16.710183 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9064 00:39:16.713015 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9065 00:39:16.716590 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9066 00:39:16.722958 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9067 00:39:16.726578 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9068 00:39:16.729697 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9069 00:39:16.732976 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
9070 00:39:16.736548 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9071 00:39:16.742991 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
9072 00:39:16.746377 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9073 00:39:16.749846 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9074 00:39:16.752730 iDelay=195, Bit 13, Center 132 (75 ~ 190) 116
9075 00:39:16.756056 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9076 00:39:16.762734 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
9077 00:39:16.762859 ==
9078 00:39:16.766364 Dram Type= 6, Freq= 0, CH_1, rank 1
9079 00:39:16.769489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9080 00:39:16.769619 ==
9081 00:39:16.769733 DQS Delay:
9082 00:39:16.772535 DQS0 = 0, DQS1 = 0
9083 00:39:16.772660 DQM Delay:
9084 00:39:16.776065 DQM0 = 127, DQM1 = 124
9085 00:39:16.776176 DQ Delay:
9086 00:39:16.779620 DQ0 =132, DQ1 =124, DQ2 =114, DQ3 =126
9087 00:39:16.782517 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9088 00:39:16.785984 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =120
9089 00:39:16.789083 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
9090 00:39:16.792851
9091 00:39:16.792935
9092 00:39:16.792999
9093 00:39:16.793058 [DramC_TX_OE_Calibration] TA2
9094 00:39:16.795646 Original DQ_B0 (3 6) =30, OEN = 27
9095 00:39:16.799514 Original DQ_B1 (3 6) =30, OEN = 27
9096 00:39:16.802471 24, 0x0, End_B0=24 End_B1=24
9097 00:39:16.805933 25, 0x0, End_B0=25 End_B1=25
9098 00:39:16.808924 26, 0x0, End_B0=26 End_B1=26
9099 00:39:16.809052 27, 0x0, End_B0=27 End_B1=27
9100 00:39:16.812458 28, 0x0, End_B0=28 End_B1=28
9101 00:39:16.815884 29, 0x0, End_B0=29 End_B1=29
9102 00:39:16.818809 30, 0x0, End_B0=30 End_B1=30
9103 00:39:16.822207 31, 0x4141, End_B0=30 End_B1=30
9104 00:39:16.825580 Byte0 end_step=30 best_step=27
9105 00:39:16.825667 Byte1 end_step=30 best_step=27
9106 00:39:16.829125 Byte0 TX OE(2T, 0.5T) = (3, 3)
9107 00:39:16.832077 Byte1 TX OE(2T, 0.5T) = (3, 3)
9108 00:39:16.832152
9109 00:39:16.832213
9110 00:39:16.842208 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9111 00:39:16.842291 CH1 RK1: MR19=303, MR18=121E
9112 00:39:16.848827 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9113 00:39:16.851867 [RxdqsGatingPostProcess] freq 1600
9114 00:39:16.858402 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9115 00:39:16.861759 best DQS0 dly(2T, 0.5T) = (1, 1)
9116 00:39:16.865419 best DQS1 dly(2T, 0.5T) = (1, 1)
9117 00:39:16.868806 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9118 00:39:16.871744 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9119 00:39:16.871868 best DQS0 dly(2T, 0.5T) = (1, 1)
9120 00:39:16.875241 best DQS1 dly(2T, 0.5T) = (1, 1)
9121 00:39:16.878402 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9122 00:39:16.881922 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9123 00:39:16.885049 Pre-setting of DQS Precalculation
9124 00:39:16.891899 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9125 00:39:16.898487 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9126 00:39:16.905337 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9127 00:39:16.905452
9128 00:39:16.905550
9129 00:39:16.908130 [Calibration Summary] 3200 Mbps
9130 00:39:16.908269 CH 0, Rank 0
9131 00:39:16.911653 SW Impedance : PASS
9132 00:39:16.915328 DUTY Scan : NO K
9133 00:39:16.915453 ZQ Calibration : PASS
9134 00:39:16.918168 Jitter Meter : NO K
9135 00:39:16.921620 CBT Training : PASS
9136 00:39:16.921774 Write leveling : PASS
9137 00:39:16.924594 RX DQS gating : PASS
9138 00:39:16.927924 RX DQ/DQS(RDDQC) : PASS
9139 00:39:16.928029 TX DQ/DQS : PASS
9140 00:39:16.931355 RX DATLAT : PASS
9141 00:39:16.934975 RX DQ/DQS(Engine): PASS
9142 00:39:16.935107 TX OE : PASS
9143 00:39:16.938424 All Pass.
9144 00:39:16.938527
9145 00:39:16.938618 CH 0, Rank 1
9146 00:39:16.941251 SW Impedance : PASS
9147 00:39:16.941351 DUTY Scan : NO K
9148 00:39:16.944806 ZQ Calibration : PASS
9149 00:39:16.944913 Jitter Meter : NO K
9150 00:39:16.948242 CBT Training : PASS
9151 00:39:16.951638 Write leveling : PASS
9152 00:39:16.951734 RX DQS gating : PASS
9153 00:39:16.954575 RX DQ/DQS(RDDQC) : PASS
9154 00:39:16.958104 TX DQ/DQS : PASS
9155 00:39:16.958187 RX DATLAT : PASS
9156 00:39:16.961538 RX DQ/DQS(Engine): PASS
9157 00:39:16.964884 TX OE : PASS
9158 00:39:16.965004 All Pass.
9159 00:39:16.965095
9160 00:39:16.965182 CH 1, Rank 0
9161 00:39:16.968158 SW Impedance : PASS
9162 00:39:16.971204 DUTY Scan : NO K
9163 00:39:16.971304 ZQ Calibration : PASS
9164 00:39:16.974724 Jitter Meter : NO K
9165 00:39:16.977845 CBT Training : PASS
9166 00:39:16.977945 Write leveling : PASS
9167 00:39:16.981206 RX DQS gating : PASS
9168 00:39:16.984311 RX DQ/DQS(RDDQC) : PASS
9169 00:39:16.984391 TX DQ/DQS : PASS
9170 00:39:16.987885 RX DATLAT : PASS
9171 00:39:16.991156 RX DQ/DQS(Engine): PASS
9172 00:39:16.991256 TX OE : PASS
9173 00:39:16.991357 All Pass.
9174 00:39:16.994546
9175 00:39:16.994642 CH 1, Rank 1
9176 00:39:16.997536 SW Impedance : PASS
9177 00:39:16.997628 DUTY Scan : NO K
9178 00:39:17.001128 ZQ Calibration : PASS
9179 00:39:17.001239 Jitter Meter : NO K
9180 00:39:17.004551 CBT Training : PASS
9181 00:39:17.007990 Write leveling : PASS
9182 00:39:17.008092 RX DQS gating : PASS
9183 00:39:17.011439 RX DQ/DQS(RDDQC) : PASS
9184 00:39:17.014292 TX DQ/DQS : PASS
9185 00:39:17.014393 RX DATLAT : PASS
9186 00:39:17.017778 RX DQ/DQS(Engine): PASS
9187 00:39:17.020785 TX OE : PASS
9188 00:39:17.020860 All Pass.
9189 00:39:17.020923
9190 00:39:17.024525 DramC Write-DBI on
9191 00:39:17.024632 PER_BANK_REFRESH: Hybrid Mode
9192 00:39:17.027797 TX_TRACKING: ON
9193 00:39:17.037752 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9194 00:39:17.044093 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9195 00:39:17.051087 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9196 00:39:17.053843 [FAST_K] Save calibration result to emmc
9197 00:39:17.057404 sync common calibartion params.
9198 00:39:17.060861 sync cbt_mode0:1, 1:1
9199 00:39:17.060972 dram_init: ddr_geometry: 2
9200 00:39:17.063795 dram_init: ddr_geometry: 2
9201 00:39:17.067141 dram_init: ddr_geometry: 2
9202 00:39:17.070515 0:dram_rank_size:100000000
9203 00:39:17.070628 1:dram_rank_size:100000000
9204 00:39:17.076918 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9205 00:39:17.080537 DFS_SHUFFLE_HW_MODE: ON
9206 00:39:17.083773 dramc_set_vcore_voltage set vcore to 725000
9207 00:39:17.087078 Read voltage for 1600, 0
9208 00:39:17.087181 Vio18 = 0
9209 00:39:17.087273 Vcore = 725000
9210 00:39:17.090290 Vdram = 0
9211 00:39:17.090393 Vddq = 0
9212 00:39:17.090487 Vmddr = 0
9213 00:39:17.093569 switch to 3200 Mbps bootup
9214 00:39:17.093670 [DramcRunTimeConfig]
9215 00:39:17.096871 PHYPLL
9216 00:39:17.096978 DPM_CONTROL_AFTERK: ON
9217 00:39:17.099903 PER_BANK_REFRESH: ON
9218 00:39:17.103534 REFRESH_OVERHEAD_REDUCTION: ON
9219 00:39:17.103641 CMD_PICG_NEW_MODE: OFF
9220 00:39:17.106640 XRTWTW_NEW_MODE: ON
9221 00:39:17.106752 XRTRTR_NEW_MODE: ON
9222 00:39:17.109763 TX_TRACKING: ON
9223 00:39:17.109871 RDSEL_TRACKING: OFF
9224 00:39:17.113401 DQS Precalculation for DVFS: ON
9225 00:39:17.116569 RX_TRACKING: OFF
9226 00:39:17.116647 HW_GATING DBG: ON
9227 00:39:17.119782 ZQCS_ENABLE_LP4: ON
9228 00:39:17.119867 RX_PICG_NEW_MODE: ON
9229 00:39:17.123316 TX_PICG_NEW_MODE: ON
9230 00:39:17.126388 ENABLE_RX_DCM_DPHY: ON
9231 00:39:17.126505 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9232 00:39:17.129793 DUMMY_READ_FOR_TRACKING: OFF
9233 00:39:17.133256 !!! SPM_CONTROL_AFTERK: OFF
9234 00:39:17.136815 !!! SPM could not control APHY
9235 00:39:17.136925 IMPEDANCE_TRACKING: ON
9236 00:39:17.139575 TEMP_SENSOR: ON
9237 00:39:17.139687 HW_SAVE_FOR_SR: OFF
9238 00:39:17.142996 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9239 00:39:17.149858 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9240 00:39:17.149940 Read ODT Tracking: ON
9241 00:39:17.152850 Refresh Rate DeBounce: ON
9242 00:39:17.152930 DFS_NO_QUEUE_FLUSH: ON
9243 00:39:17.156128 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9244 00:39:17.159926 ENABLE_DFS_RUNTIME_MRW: OFF
9245 00:39:17.162875 DDR_RESERVE_NEW_MODE: ON
9246 00:39:17.162981 MR_CBT_SWITCH_FREQ: ON
9247 00:39:17.166282 =========================
9248 00:39:17.185587 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9249 00:39:17.188648 dram_init: ddr_geometry: 2
9250 00:39:17.206966 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9251 00:39:17.210569 dram_init: dram init end (result: 0)
9252 00:39:17.216632 DRAM-K: Full calibration passed in 24624 msecs
9253 00:39:17.220029 MRC: failed to locate region type 0.
9254 00:39:17.220157 DRAM rank0 size:0x100000000,
9255 00:39:17.223351 DRAM rank1 size=0x100000000
9256 00:39:17.234023 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9257 00:39:17.240264 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9258 00:39:17.246920 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9259 00:39:17.253604 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9260 00:39:17.256538 DRAM rank0 size:0x100000000,
9261 00:39:17.259833 DRAM rank1 size=0x100000000
9262 00:39:17.259961 CBMEM:
9263 00:39:17.263210 IMD: root @ 0xfffff000 254 entries.
9264 00:39:17.266581 IMD: root @ 0xffffec00 62 entries.
9265 00:39:17.270187 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9266 00:39:17.276500 WARNING: RO_VPD is uninitialized or empty.
9267 00:39:17.279859 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9268 00:39:17.287264 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9269 00:39:17.299972 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9270 00:39:17.311277 BS: romstage times (exec / console): total (unknown) / 24079 ms
9271 00:39:17.311364
9272 00:39:17.311430
9273 00:39:17.321186 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9274 00:39:17.324634 ARM64: Exception handlers installed.
9275 00:39:17.327693 ARM64: Testing exception
9276 00:39:17.330979 ARM64: Done test exception
9277 00:39:17.331100 Enumerating buses...
9278 00:39:17.334303 Show all devs... Before device enumeration.
9279 00:39:17.337754 Root Device: enabled 1
9280 00:39:17.341025 CPU_CLUSTER: 0: enabled 1
9281 00:39:17.341146 CPU: 00: enabled 1
9282 00:39:17.344323 Compare with tree...
9283 00:39:17.344443 Root Device: enabled 1
9284 00:39:17.347533 CPU_CLUSTER: 0: enabled 1
9285 00:39:17.350749 CPU: 00: enabled 1
9286 00:39:17.350873 Root Device scanning...
9287 00:39:17.354381 scan_static_bus for Root Device
9288 00:39:17.357498 CPU_CLUSTER: 0 enabled
9289 00:39:17.360783 scan_static_bus for Root Device done
9290 00:39:17.364293 scan_bus: bus Root Device finished in 8 msecs
9291 00:39:17.364416 done
9292 00:39:17.370502 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9293 00:39:17.373936 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9294 00:39:17.380541 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9295 00:39:17.383904 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9296 00:39:17.387271 Allocating resources...
9297 00:39:17.390901 Reading resources...
9298 00:39:17.393710 Root Device read_resources bus 0 link: 0
9299 00:39:17.397097 DRAM rank0 size:0x100000000,
9300 00:39:17.397250 DRAM rank1 size=0x100000000
9301 00:39:17.400524 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9302 00:39:17.404016 CPU: 00 missing read_resources
9303 00:39:17.410234 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9304 00:39:17.413724 Root Device read_resources bus 0 link: 0 done
9305 00:39:17.413801 Done reading resources.
9306 00:39:17.420522 Show resources in subtree (Root Device)...After reading.
9307 00:39:17.423452 Root Device child on link 0 CPU_CLUSTER: 0
9308 00:39:17.426847 CPU_CLUSTER: 0 child on link 0 CPU: 00
9309 00:39:17.436581 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9310 00:39:17.436708 CPU: 00
9311 00:39:17.440293 Root Device assign_resources, bus 0 link: 0
9312 00:39:17.443380 CPU_CLUSTER: 0 missing set_resources
9313 00:39:17.449817 Root Device assign_resources, bus 0 link: 0 done
9314 00:39:17.449941 Done setting resources.
9315 00:39:17.456773 Show resources in subtree (Root Device)...After assigning values.
9316 00:39:17.460120 Root Device child on link 0 CPU_CLUSTER: 0
9317 00:39:17.463112 CPU_CLUSTER: 0 child on link 0 CPU: 00
9318 00:39:17.472957 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9319 00:39:17.473080 CPU: 00
9320 00:39:17.476683 Done allocating resources.
9321 00:39:17.483318 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9322 00:39:17.483444 Enabling resources...
9323 00:39:17.483557 done.
9324 00:39:17.489885 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9325 00:39:17.492905 Initializing devices...
9326 00:39:17.493032 Root Device init
9327 00:39:17.496376 init hardware done!
9328 00:39:17.496498 0x00000018: ctrlr->caps
9329 00:39:17.499801 52.000 MHz: ctrlr->f_max
9330 00:39:17.502850 0.400 MHz: ctrlr->f_min
9331 00:39:17.502979 0x40ff8080: ctrlr->voltages
9332 00:39:17.506133 sclk: 390625
9333 00:39:17.506257 Bus Width = 1
9334 00:39:17.506367 sclk: 390625
9335 00:39:17.509609 Bus Width = 1
9336 00:39:17.509713 Early init status = 3
9337 00:39:17.516444 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9338 00:39:17.519977 in-header: 03 fc 00 00 01 00 00 00
9339 00:39:17.522785 in-data: 00
9340 00:39:17.526191 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9341 00:39:17.530089 in-header: 03 fd 00 00 00 00 00 00
9342 00:39:17.533518 in-data:
9343 00:39:17.536461 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9344 00:39:17.539970 in-header: 03 fc 00 00 01 00 00 00
9345 00:39:17.543246 in-data: 00
9346 00:39:17.546791 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9347 00:39:17.551326 in-header: 03 fd 00 00 00 00 00 00
9348 00:39:17.555100 in-data:
9349 00:39:17.558360 [SSUSB] Setting up USB HOST controller...
9350 00:39:17.561382 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9351 00:39:17.564492 [SSUSB] phy power-on done.
9352 00:39:17.568030 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9353 00:39:17.574513 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9354 00:39:17.577858 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9355 00:39:17.584653 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9356 00:39:17.590963 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9357 00:39:17.597853 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9358 00:39:17.604130 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9359 00:39:17.610974 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9360 00:39:17.614470 SPM: binary array size = 0x9dc
9361 00:39:17.617800 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9362 00:39:17.624005 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9363 00:39:17.630883 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9364 00:39:17.637701 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9365 00:39:17.640579 configure_display: Starting display init
9366 00:39:17.675023 anx7625_power_on_init: Init interface.
9367 00:39:17.677938 anx7625_disable_pd_protocol: Disabled PD feature.
9368 00:39:17.684386 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9369 00:39:17.709208 anx7625_start_dp_work: Secure OCM version=00
9370 00:39:17.712302 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9371 00:39:17.727326 sp_tx_get_edid_block: EDID Block = 1
9372 00:39:17.829859 Extracted contents:
9373 00:39:17.833732 header: 00 ff ff ff ff ff ff 00
9374 00:39:17.836817 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9375 00:39:17.839723 version: 01 04
9376 00:39:17.843208 basic params: 95 1f 11 78 0a
9377 00:39:17.846240 chroma info: 76 90 94 55 54 90 27 21 50 54
9378 00:39:17.849750 established: 00 00 00
9379 00:39:17.856018 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9380 00:39:17.859529 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9381 00:39:17.866099 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 00:39:17.872918 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9383 00:39:17.879033 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9384 00:39:17.882496 extensions: 00
9385 00:39:17.882597 checksum: fb
9386 00:39:17.882687
9387 00:39:17.885894 Manufacturer: IVO Model 57d Serial Number 0
9388 00:39:17.889283 Made week 0 of 2020
9389 00:39:17.892823 EDID version: 1.4
9390 00:39:17.892931 Digital display
9391 00:39:17.896219 6 bits per primary color channel
9392 00:39:17.896306 DisplayPort interface
9393 00:39:17.898989 Maximum image size: 31 cm x 17 cm
9394 00:39:17.902788 Gamma: 220%
9395 00:39:17.902870 Check DPMS levels
9396 00:39:17.905806 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9397 00:39:17.912565 First detailed timing is preferred timing
9398 00:39:17.912670 Established timings supported:
9399 00:39:17.915759 Standard timings supported:
9400 00:39:17.919125 Detailed timings
9401 00:39:17.922139 Hex of detail: 383680a07038204018303c0035ae10000019
9402 00:39:17.928992 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9403 00:39:17.932236 0780 0798 07c8 0820 hborder 0
9404 00:39:17.935727 0438 043b 0447 0458 vborder 0
9405 00:39:17.938910 -hsync -vsync
9406 00:39:17.939029 Did detailed timing
9407 00:39:17.945484 Hex of detail: 000000000000000000000000000000000000
9408 00:39:17.948653 Manufacturer-specified data, tag 0
9409 00:39:17.952141 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9410 00:39:17.955738 ASCII string: InfoVision
9411 00:39:17.958773 Hex of detail: 000000fe00523134304e574635205248200a
9412 00:39:17.962350 ASCII string: R140NWF5 RH
9413 00:39:17.962477 Checksum
9414 00:39:17.965619 Checksum: 0xfb (valid)
9415 00:39:17.968990 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9416 00:39:17.971819 DSI data_rate: 832800000 bps
9417 00:39:17.978583 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9418 00:39:17.981896 anx7625_parse_edid: pixelclock(138800).
9419 00:39:17.985489 hactive(1920), hsync(48), hfp(24), hbp(88)
9420 00:39:17.988703 vactive(1080), vsync(12), vfp(3), vbp(17)
9421 00:39:17.992104 anx7625_dsi_config: config dsi.
9422 00:39:17.998492 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9423 00:39:18.011916 anx7625_dsi_config: success to config DSI
9424 00:39:18.015021 anx7625_dp_start: MIPI phy setup OK.
9425 00:39:18.018384 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9426 00:39:18.022014 mtk_ddp_mode_set invalid vrefresh 60
9427 00:39:18.025050 main_disp_path_setup
9428 00:39:18.025155 ovl_layer_smi_id_en
9429 00:39:18.028347 ovl_layer_smi_id_en
9430 00:39:18.028449 ccorr_config
9431 00:39:18.028538 aal_config
9432 00:39:18.031846 gamma_config
9433 00:39:18.031943 postmask_config
9434 00:39:18.035370 dither_config
9435 00:39:18.038631 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9436 00:39:18.044682 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9437 00:39:18.048323 Root Device init finished in 551 msecs
9438 00:39:18.051368 CPU_CLUSTER: 0 init
9439 00:39:18.058364 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9440 00:39:18.061619 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9441 00:39:18.064624 APU_MBOX 0x190000b0 = 0x10001
9442 00:39:18.068073 APU_MBOX 0x190001b0 = 0x10001
9443 00:39:18.071415 APU_MBOX 0x190005b0 = 0x10001
9444 00:39:18.074478 APU_MBOX 0x190006b0 = 0x10001
9445 00:39:18.081486 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9446 00:39:18.090759 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9447 00:39:18.103259 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9448 00:39:18.109996 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9449 00:39:18.121389 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9450 00:39:18.130746 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9451 00:39:18.133877 CPU_CLUSTER: 0 init finished in 81 msecs
9452 00:39:18.137046 Devices initialized
9453 00:39:18.140423 Show all devs... After init.
9454 00:39:18.140546 Root Device: enabled 1
9455 00:39:18.144009 CPU_CLUSTER: 0: enabled 1
9456 00:39:18.147299 CPU: 00: enabled 1
9457 00:39:18.150713 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9458 00:39:18.154005 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9459 00:39:18.157089 ELOG: NV offset 0x57f000 size 0x1000
9460 00:39:18.163575 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9461 00:39:18.170235 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9462 00:39:18.173706 ELOG: Event(17) added with size 13 at 2024-06-05 00:39:18 UTC
9463 00:39:18.177053 out: cmd=0x121: 03 db 21 01 00 00 00 00
9464 00:39:18.180861 in-header: 03 2d 00 00 2c 00 00 00
9465 00:39:18.194203 in-data: 31 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9466 00:39:18.200521 ELOG: Event(A1) added with size 10 at 2024-06-05 00:39:18 UTC
9467 00:39:18.207471 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9468 00:39:18.213987 ELOG: Event(A0) added with size 9 at 2024-06-05 00:39:18 UTC
9469 00:39:18.217414 elog_add_boot_reason: Logged dev mode boot
9470 00:39:18.220480 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9471 00:39:18.223806 Finalize devices...
9472 00:39:18.223951 Devices finalized
9473 00:39:18.230604 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9474 00:39:18.233961 Writing coreboot table at 0xffe64000
9475 00:39:18.237230 0. 000000000010a000-0000000000113fff: RAMSTAGE
9476 00:39:18.240164 1. 0000000040000000-00000000400fffff: RAM
9477 00:39:18.247004 2. 0000000040100000-000000004032afff: RAMSTAGE
9478 00:39:18.250053 3. 000000004032b000-00000000545fffff: RAM
9479 00:39:18.253486 4. 0000000054600000-000000005465ffff: BL31
9480 00:39:18.257005 5. 0000000054660000-00000000ffe63fff: RAM
9481 00:39:18.263201 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9482 00:39:18.267032 7. 0000000100000000-000000023fffffff: RAM
9483 00:39:18.270152 Passing 5 GPIOs to payload:
9484 00:39:18.273574 NAME | PORT | POLARITY | VALUE
9485 00:39:18.276792 EC in RW | 0x000000aa | low | undefined
9486 00:39:18.283325 EC interrupt | 0x00000005 | low | undefined
9487 00:39:18.286442 TPM interrupt | 0x000000ab | high | undefined
9488 00:39:18.293509 SD card detect | 0x00000011 | high | undefined
9489 00:39:18.296850 speaker enable | 0x00000093 | high | undefined
9490 00:39:18.299814 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9491 00:39:18.303213 in-header: 03 f9 00 00 02 00 00 00
9492 00:39:18.306261 in-data: 02 00
9493 00:39:18.306410 ADC[4]: Raw value=894821 ID=7
9494 00:39:18.309660 ADC[3]: Raw value=213070 ID=1
9495 00:39:18.313138 RAM Code: 0x71
9496 00:39:18.313241 ADC[6]: Raw value=74722 ID=0
9497 00:39:18.316493 ADC[5]: Raw value=211960 ID=1
9498 00:39:18.319886 SKU Code: 0x1
9499 00:39:18.322779 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7b2b
9500 00:39:18.326061 coreboot table: 964 bytes.
9501 00:39:18.329464 IMD ROOT 0. 0xfffff000 0x00001000
9502 00:39:18.333078 IMD SMALL 1. 0xffffe000 0x00001000
9503 00:39:18.335901 RO MCACHE 2. 0xffffc000 0x00001104
9504 00:39:18.339146 CONSOLE 3. 0xfff7c000 0x00080000
9505 00:39:18.342701 FMAP 4. 0xfff7b000 0x00000452
9506 00:39:18.346191 TIME STAMP 5. 0xfff7a000 0x00000910
9507 00:39:18.349432 VBOOT WORK 6. 0xfff66000 0x00014000
9508 00:39:18.352387 RAMOOPS 7. 0xffe66000 0x00100000
9509 00:39:18.355870 COREBOOT 8. 0xffe64000 0x00002000
9510 00:39:18.355975 IMD small region:
9511 00:39:18.363029 IMD ROOT 0. 0xffffec00 0x00000400
9512 00:39:18.365773 VPD 1. 0xffffeb80 0x0000006c
9513 00:39:18.369094 MMC STATUS 2. 0xffffeb60 0x00000004
9514 00:39:18.372210 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9515 00:39:18.376061 Probing TPM: done!
9516 00:39:18.379455 Connected to device vid:did:rid of 1ae0:0028:00
9517 00:39:18.389628 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9518 00:39:18.392827 Initialized TPM device CR50 revision 0
9519 00:39:18.396549 Checking cr50 for pending updates
9520 00:39:18.400334 Reading cr50 TPM mode
9521 00:39:18.408992 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9522 00:39:18.415794 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9523 00:39:18.455999 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9524 00:39:18.459130 Checking segment from ROM address 0x40100000
9525 00:39:18.462591 Checking segment from ROM address 0x4010001c
9526 00:39:18.469296 Loading segment from ROM address 0x40100000
9527 00:39:18.469376 code (compression=0)
9528 00:39:18.475927 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9529 00:39:18.485834 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9530 00:39:18.485968 it's not compressed!
9531 00:39:18.492177 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9532 00:39:18.495446 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9533 00:39:18.516123 Loading segment from ROM address 0x4010001c
9534 00:39:18.516212 Entry Point 0x80000000
9535 00:39:18.519380 Loaded segments
9536 00:39:18.522513 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9537 00:39:18.529448 Jumping to boot code at 0x80000000(0xffe64000)
9538 00:39:18.536292 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9539 00:39:18.542413 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9540 00:39:18.550412 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9541 00:39:18.553975 Checking segment from ROM address 0x40100000
9542 00:39:18.556840 Checking segment from ROM address 0x4010001c
9543 00:39:18.564022 Loading segment from ROM address 0x40100000
9544 00:39:18.564106 code (compression=1)
9545 00:39:18.570497 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9546 00:39:18.580151 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9547 00:39:18.580264 using LZMA
9548 00:39:18.589069 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9549 00:39:18.595282 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9550 00:39:18.598600 Loading segment from ROM address 0x4010001c
9551 00:39:18.598695 Entry Point 0x54601000
9552 00:39:18.601874 Loaded segments
9553 00:39:18.605246 NOTICE: MT8192 bl31_setup
9554 00:39:18.612348 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9555 00:39:18.615547 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9556 00:39:18.619240 WARNING: region 0:
9557 00:39:18.622704 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9558 00:39:18.622830 WARNING: region 1:
9559 00:39:18.629090 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9560 00:39:18.632380 WARNING: region 2:
9561 00:39:18.635866 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9562 00:39:18.639260 WARNING: region 3:
9563 00:39:18.642438 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9564 00:39:18.646101 WARNING: region 4:
9565 00:39:18.652431 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9566 00:39:18.652537 WARNING: region 5:
9567 00:39:18.655878 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9568 00:39:18.659199 WARNING: region 6:
9569 00:39:18.662606 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9570 00:39:18.662691 WARNING: region 7:
9571 00:39:18.669205 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9572 00:39:18.675817 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9573 00:39:18.679069 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9574 00:39:18.682462 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9575 00:39:18.688875 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9576 00:39:18.692757 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9577 00:39:18.695954 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9578 00:39:18.702842 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9579 00:39:18.705943 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9580 00:39:18.709326 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9581 00:39:18.716173 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9582 00:39:18.719087 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9583 00:39:18.725930 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9584 00:39:18.729066 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9585 00:39:18.732417 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9586 00:39:18.739365 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9587 00:39:18.742583 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9588 00:39:18.745767 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9589 00:39:18.752492 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9590 00:39:18.756012 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9591 00:39:18.762164 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9592 00:39:18.765663 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9593 00:39:18.769285 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9594 00:39:18.776037 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9595 00:39:18.779206 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9596 00:39:18.786032 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9597 00:39:18.789418 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9598 00:39:18.792441 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9599 00:39:18.799105 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9600 00:39:18.802302 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9601 00:39:18.809378 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9602 00:39:18.812533 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9603 00:39:18.815914 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9604 00:39:18.819329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9605 00:39:18.826190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9606 00:39:18.829187 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9607 00:39:18.832894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9608 00:39:18.835979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9609 00:39:18.842580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9610 00:39:18.846095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9611 00:39:18.849322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9612 00:39:18.852858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9613 00:39:18.859084 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9614 00:39:18.862340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9615 00:39:18.865933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9616 00:39:18.872247 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9617 00:39:18.875471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9618 00:39:18.879313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9619 00:39:18.882215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9620 00:39:18.889068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9621 00:39:18.892494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9622 00:39:18.899160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9623 00:39:18.902375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9624 00:39:18.905817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9625 00:39:18.912498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9626 00:39:18.915641 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9627 00:39:18.922543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9628 00:39:18.925528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9629 00:39:18.932346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9630 00:39:18.935807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9631 00:39:18.939171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9632 00:39:18.945453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9633 00:39:18.949018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9634 00:39:18.955928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9635 00:39:18.958860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9636 00:39:18.965784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9637 00:39:18.969065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9638 00:39:18.975507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9639 00:39:18.978983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9640 00:39:18.982444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9641 00:39:18.988546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9642 00:39:18.991895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9643 00:39:18.998860 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9644 00:39:19.002336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9645 00:39:19.008881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9646 00:39:19.012091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9647 00:39:19.015383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9648 00:39:19.022248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9649 00:39:19.025353 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9650 00:39:19.032239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9651 00:39:19.035295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9652 00:39:19.042083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9653 00:39:19.045484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9654 00:39:19.048993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9655 00:39:19.055344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9656 00:39:19.058766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9657 00:39:19.065880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9658 00:39:19.068668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9659 00:39:19.075484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9660 00:39:19.078977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9661 00:39:19.082447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9662 00:39:19.088946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9663 00:39:19.092255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9664 00:39:19.098602 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9665 00:39:19.101940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9666 00:39:19.108788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9667 00:39:19.112110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9668 00:39:19.115306 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9669 00:39:19.122323 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9670 00:39:19.125234 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9671 00:39:19.129062 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9672 00:39:19.132074 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9673 00:39:19.138939 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9674 00:39:19.142293 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9675 00:39:19.148737 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9676 00:39:19.152056 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9677 00:39:19.155500 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9678 00:39:19.162481 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9679 00:39:19.165587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9680 00:39:19.169241 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9681 00:39:19.175775 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9682 00:39:19.179177 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9683 00:39:19.185601 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9684 00:39:19.189090 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9685 00:39:19.192496 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9686 00:39:19.198897 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9687 00:39:19.202070 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9688 00:39:19.205780 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9689 00:39:19.212192 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9690 00:39:19.215477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9691 00:39:19.219063 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9692 00:39:19.225792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9693 00:39:19.228792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9694 00:39:19.231984 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9695 00:39:19.235395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9696 00:39:19.242060 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9697 00:39:19.245545 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9698 00:39:19.251949 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9699 00:39:19.255274 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9700 00:39:19.258825 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9701 00:39:19.265693 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9702 00:39:19.269158 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9703 00:39:19.272048 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9704 00:39:19.278661 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9705 00:39:19.282316 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9706 00:39:19.288429 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9707 00:39:19.291996 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9708 00:39:19.295396 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9709 00:39:19.302357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9710 00:39:19.305134 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9711 00:39:19.312079 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9712 00:39:19.315188 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9713 00:39:19.318590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9714 00:39:19.325350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9715 00:39:19.328509 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9716 00:39:19.335373 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9717 00:39:19.338832 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9718 00:39:19.341692 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9719 00:39:19.348503 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9720 00:39:19.352045 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9721 00:39:19.358277 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9722 00:39:19.362169 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9723 00:39:19.365158 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9724 00:39:19.371687 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9725 00:39:19.375185 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9726 00:39:19.378446 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9727 00:39:19.385187 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9728 00:39:19.388336 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9729 00:39:19.395036 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9730 00:39:19.398516 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9731 00:39:19.401854 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9732 00:39:19.408241 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9733 00:39:19.411574 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9734 00:39:19.418280 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9735 00:39:19.421517 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9736 00:39:19.424926 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9737 00:39:19.431589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9738 00:39:19.435064 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9739 00:39:19.441347 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9740 00:39:19.444746 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9741 00:39:19.447887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9742 00:39:19.454525 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9743 00:39:19.458138 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9744 00:39:19.464553 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9745 00:39:19.467605 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9746 00:39:19.471302 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9747 00:39:19.477478 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9748 00:39:19.480935 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9749 00:39:19.487871 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9750 00:39:19.490931 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9751 00:39:19.494228 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9752 00:39:19.500751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9753 00:39:19.504250 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9754 00:39:19.510560 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9755 00:39:19.514096 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9756 00:39:19.517159 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9757 00:39:19.524144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9758 00:39:19.527585 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9759 00:39:19.530509 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9760 00:39:19.537042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9761 00:39:19.540824 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9762 00:39:19.546952 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9763 00:39:19.550303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9764 00:39:19.556913 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9765 00:39:19.560266 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9766 00:39:19.563777 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9767 00:39:19.570451 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9768 00:39:19.573564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9769 00:39:19.580330 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9770 00:39:19.583659 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9771 00:39:19.590457 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9772 00:39:19.593642 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9773 00:39:19.597047 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9774 00:39:19.603337 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9775 00:39:19.606655 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9776 00:39:19.613433 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9777 00:39:19.616808 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9778 00:39:19.623048 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9779 00:39:19.626920 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9780 00:39:19.629825 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9781 00:39:19.636684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9782 00:39:19.639885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9783 00:39:19.646629 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9784 00:39:19.649873 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9785 00:39:19.653276 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9786 00:39:19.659934 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9787 00:39:19.663197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9788 00:39:19.670171 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9789 00:39:19.672995 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9790 00:39:19.679787 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9791 00:39:19.683045 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9792 00:39:19.686368 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9793 00:39:19.692944 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9794 00:39:19.696409 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9795 00:39:19.702823 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9796 00:39:19.706212 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9797 00:39:19.709377 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9798 00:39:19.716145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9799 00:39:19.719270 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9800 00:39:19.726131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9801 00:39:19.729451 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9802 00:39:19.732505 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9803 00:39:19.736119 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9804 00:39:19.742668 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9805 00:39:19.746166 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9806 00:39:19.749065 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9807 00:39:19.755673 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9808 00:39:19.758904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9809 00:39:19.762326 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9810 00:39:19.768958 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9811 00:39:19.772409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9812 00:39:19.775861 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9813 00:39:19.782736 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9814 00:39:19.785853 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9815 00:39:19.789405 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9816 00:39:19.795615 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9817 00:39:19.799220 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9818 00:39:19.805900 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9819 00:39:19.808681 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9820 00:39:19.812183 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9821 00:39:19.818616 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9822 00:39:19.822317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9823 00:39:19.828588 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9824 00:39:19.832105 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9825 00:39:19.835455 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9826 00:39:19.841881 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9827 00:39:19.845383 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9828 00:39:19.848552 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9829 00:39:19.855411 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9830 00:39:19.858903 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9831 00:39:19.862044 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9832 00:39:19.868780 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9833 00:39:19.872050 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9834 00:39:19.878858 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9835 00:39:19.882155 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9836 00:39:19.885506 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9837 00:39:19.892414 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9838 00:39:19.895595 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9839 00:39:19.899012 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9840 00:39:19.905235 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9841 00:39:19.908547 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9842 00:39:19.911959 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9843 00:39:19.915396 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9844 00:39:19.918928 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9845 00:39:19.925035 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9846 00:39:19.928462 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9847 00:39:19.931931 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9848 00:39:19.935601 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9849 00:39:19.941909 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9850 00:39:19.945062 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9851 00:39:19.948263 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9852 00:39:19.954966 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9853 00:39:19.958277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9854 00:39:19.961840 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9855 00:39:19.968262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9856 00:39:19.971419 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9857 00:39:19.978384 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9858 00:39:19.981378 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9859 00:39:19.984912 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9860 00:39:19.991357 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9861 00:39:19.994519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9862 00:39:20.001161 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9863 00:39:20.004875 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9864 00:39:20.007600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9865 00:39:20.014300 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9866 00:39:20.017803 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9867 00:39:20.024261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9868 00:39:20.027648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9869 00:39:20.030991 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9870 00:39:20.037358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9871 00:39:20.040822 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9872 00:39:20.047627 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9873 00:39:20.051105 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9874 00:39:20.057011 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9875 00:39:20.060411 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9876 00:39:20.067368 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9877 00:39:20.070285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9878 00:39:20.073644 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9879 00:39:20.080296 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9880 00:39:20.083804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9881 00:39:20.090386 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9882 00:39:20.093783 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9883 00:39:20.097133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9884 00:39:20.103402 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9885 00:39:20.106752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9886 00:39:20.113509 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9887 00:39:20.116907 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9888 00:39:20.120272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9889 00:39:20.126644 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9890 00:39:20.129730 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9891 00:39:20.136711 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9892 00:39:20.140110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9893 00:39:20.142857 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9894 00:39:20.149845 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9895 00:39:20.152789 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9896 00:39:20.159972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9897 00:39:20.162938 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9898 00:39:20.169867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9899 00:39:20.173276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9900 00:39:20.176085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9901 00:39:20.182985 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9902 00:39:20.186226 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9903 00:39:20.192545 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9904 00:39:20.195775 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9905 00:39:20.202707 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9906 00:39:20.206073 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9907 00:39:20.209135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9908 00:39:20.215818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9909 00:39:20.219314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9910 00:39:20.225908 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9911 00:39:20.229251 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9912 00:39:20.232491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9913 00:39:20.238813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9914 00:39:20.242217 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9915 00:39:20.249195 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9916 00:39:20.252522 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9917 00:39:20.256022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9918 00:39:20.262165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9919 00:39:20.265587 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9920 00:39:20.272005 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9921 00:39:20.275270 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9922 00:39:20.282086 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9923 00:39:20.285607 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9924 00:39:20.288365 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9925 00:39:20.295311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9926 00:39:20.298775 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9927 00:39:20.304917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9928 00:39:20.308073 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9929 00:39:20.314974 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9930 00:39:20.318424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9931 00:39:20.324540 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9932 00:39:20.327895 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9933 00:39:20.331209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9934 00:39:20.338348 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9935 00:39:20.341002 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9936 00:39:20.347809 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9937 00:39:20.351146 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9938 00:39:20.357452 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9939 00:39:20.360946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9940 00:39:20.367467 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9941 00:39:20.370919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9942 00:39:20.374422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9943 00:39:20.380652 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9944 00:39:20.384124 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9945 00:39:20.390587 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9946 00:39:20.393961 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9947 00:39:20.400164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9948 00:39:20.404100 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9949 00:39:20.407051 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9950 00:39:20.413896 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9951 00:39:20.417166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9952 00:39:20.423963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9953 00:39:20.427181 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9954 00:39:20.433508 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9955 00:39:20.436994 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9956 00:39:20.443576 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9957 00:39:20.446797 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9958 00:39:20.449964 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9959 00:39:20.456706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9960 00:39:20.459954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9961 00:39:20.466345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9962 00:39:20.469721 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9963 00:39:20.476421 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9964 00:39:20.480074 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9965 00:39:20.482970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9966 00:39:20.490041 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9967 00:39:20.492836 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9968 00:39:20.499504 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9969 00:39:20.503043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9970 00:39:20.509341 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9971 00:39:20.512887 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9972 00:39:20.519262 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9973 00:39:20.522798 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9974 00:39:20.526194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9975 00:39:20.532857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9976 00:39:20.536206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9977 00:39:20.542430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9978 00:39:20.545889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9979 00:39:20.552447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9980 00:39:20.555794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9981 00:39:20.562486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9982 00:39:20.565710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9983 00:39:20.572506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9984 00:39:20.576045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9985 00:39:20.582394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9986 00:39:20.585785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9987 00:39:20.592229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9988 00:39:20.595531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9989 00:39:20.602001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9990 00:39:20.605197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9991 00:39:20.608671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9992 00:39:20.615623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9993 00:39:20.621812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9994 00:39:20.625038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9995 00:39:20.631680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9996 00:39:20.635319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9997 00:39:20.641944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9998 00:39:20.645003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9999 00:39:20.651637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10000 00:39:20.654719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10001 00:39:20.661372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10002 00:39:20.664454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10003 00:39:20.671163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10004 00:39:20.674695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10005 00:39:20.681322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10006 00:39:20.684486 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10007 00:39:20.687944 INFO: [APUAPC] vio 0
10008 00:39:20.690953 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10009 00:39:20.697501 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10010 00:39:20.701020 INFO: [APUAPC] D0_APC_0: 0x400510
10011 00:39:20.701103 INFO: [APUAPC] D0_APC_1: 0x0
10012 00:39:20.704414 INFO: [APUAPC] D0_APC_2: 0x1540
10013 00:39:20.707989 INFO: [APUAPC] D0_APC_3: 0x0
10014 00:39:20.710890 INFO: [APUAPC] D1_APC_0: 0xffffffff
10015 00:39:20.714311 INFO: [APUAPC] D1_APC_1: 0xffffffff
10016 00:39:20.717750 INFO: [APUAPC] D1_APC_2: 0x3fffff
10017 00:39:20.720533 INFO: [APUAPC] D1_APC_3: 0x0
10018 00:39:20.724298 INFO: [APUAPC] D2_APC_0: 0xffffffff
10019 00:39:20.727676 INFO: [APUAPC] D2_APC_1: 0xffffffff
10020 00:39:20.730632 INFO: [APUAPC] D2_APC_2: 0x3fffff
10021 00:39:20.733881 INFO: [APUAPC] D2_APC_3: 0x0
10022 00:39:20.737597 INFO: [APUAPC] D3_APC_0: 0xffffffff
10023 00:39:20.740643 INFO: [APUAPC] D3_APC_1: 0xffffffff
10024 00:39:20.743745 INFO: [APUAPC] D3_APC_2: 0x3fffff
10025 00:39:20.747608 INFO: [APUAPC] D3_APC_3: 0x0
10026 00:39:20.750393 INFO: [APUAPC] D4_APC_0: 0xffffffff
10027 00:39:20.753857 INFO: [APUAPC] D4_APC_1: 0xffffffff
10028 00:39:20.757295 INFO: [APUAPC] D4_APC_2: 0x3fffff
10029 00:39:20.760805 INFO: [APUAPC] D4_APC_3: 0x0
10030 00:39:20.763923 INFO: [APUAPC] D5_APC_0: 0xffffffff
10031 00:39:20.767173 INFO: [APUAPC] D5_APC_1: 0xffffffff
10032 00:39:20.770368 INFO: [APUAPC] D5_APC_2: 0x3fffff
10033 00:39:20.773881 INFO: [APUAPC] D5_APC_3: 0x0
10034 00:39:20.777358 INFO: [APUAPC] D6_APC_0: 0xffffffff
10035 00:39:20.780707 INFO: [APUAPC] D6_APC_1: 0xffffffff
10036 00:39:20.784188 INFO: [APUAPC] D6_APC_2: 0x3fffff
10037 00:39:20.787002 INFO: [APUAPC] D6_APC_3: 0x0
10038 00:39:20.790517 INFO: [APUAPC] D7_APC_0: 0xffffffff
10039 00:39:20.793909 INFO: [APUAPC] D7_APC_1: 0xffffffff
10040 00:39:20.797053 INFO: [APUAPC] D7_APC_2: 0x3fffff
10041 00:39:20.800281 INFO: [APUAPC] D7_APC_3: 0x0
10042 00:39:20.803680 INFO: [APUAPC] D8_APC_0: 0xffffffff
10043 00:39:20.807187 INFO: [APUAPC] D8_APC_1: 0xffffffff
10044 00:39:20.810257 INFO: [APUAPC] D8_APC_2: 0x3fffff
10045 00:39:20.814011 INFO: [APUAPC] D8_APC_3: 0x0
10046 00:39:20.816916 INFO: [APUAPC] D9_APC_0: 0xffffffff
10047 00:39:20.820290 INFO: [APUAPC] D9_APC_1: 0xffffffff
10048 00:39:20.823760 INFO: [APUAPC] D9_APC_2: 0x3fffff
10049 00:39:20.827015 INFO: [APUAPC] D9_APC_3: 0x0
10050 00:39:20.830248 INFO: [APUAPC] D10_APC_0: 0xffffffff
10051 00:39:20.833529 INFO: [APUAPC] D10_APC_1: 0xffffffff
10052 00:39:20.836802 INFO: [APUAPC] D10_APC_2: 0x3fffff
10053 00:39:20.840327 INFO: [APUAPC] D10_APC_3: 0x0
10054 00:39:20.843461 INFO: [APUAPC] D11_APC_0: 0xffffffff
10055 00:39:20.846676 INFO: [APUAPC] D11_APC_1: 0xffffffff
10056 00:39:20.850372 INFO: [APUAPC] D11_APC_2: 0x3fffff
10057 00:39:20.853835 INFO: [APUAPC] D11_APC_3: 0x0
10058 00:39:20.857074 INFO: [APUAPC] D12_APC_0: 0xffffffff
10059 00:39:20.860066 INFO: [APUAPC] D12_APC_1: 0xffffffff
10060 00:39:20.863521 INFO: [APUAPC] D12_APC_2: 0x3fffff
10061 00:39:20.866805 INFO: [APUAPC] D12_APC_3: 0x0
10062 00:39:20.869903 INFO: [APUAPC] D13_APC_0: 0xffffffff
10063 00:39:20.873614 INFO: [APUAPC] D13_APC_1: 0xffffffff
10064 00:39:20.876562 INFO: [APUAPC] D13_APC_2: 0x3fffff
10065 00:39:20.880062 INFO: [APUAPC] D13_APC_3: 0x0
10066 00:39:20.883628 INFO: [APUAPC] D14_APC_0: 0xffffffff
10067 00:39:20.886621 INFO: [APUAPC] D14_APC_1: 0xffffffff
10068 00:39:20.890189 INFO: [APUAPC] D14_APC_2: 0x3fffff
10069 00:39:20.893484 INFO: [APUAPC] D14_APC_3: 0x0
10070 00:39:20.897044 INFO: [APUAPC] D15_APC_0: 0xffffffff
10071 00:39:20.899933 INFO: [APUAPC] D15_APC_1: 0xffffffff
10072 00:39:20.903098 INFO: [APUAPC] D15_APC_2: 0x3fffff
10073 00:39:20.906385 INFO: [APUAPC] D15_APC_3: 0x0
10074 00:39:20.909931 INFO: [APUAPC] APC_CON: 0x4
10075 00:39:20.910008 INFO: [NOCDAPC] D0_APC_0: 0x0
10076 00:39:20.913306 INFO: [NOCDAPC] D0_APC_1: 0x0
10077 00:39:20.916860 INFO: [NOCDAPC] D1_APC_0: 0x0
10078 00:39:20.919654 INFO: [NOCDAPC] D1_APC_1: 0xfff
10079 00:39:20.923281 INFO: [NOCDAPC] D2_APC_0: 0x0
10080 00:39:20.926419 INFO: [NOCDAPC] D2_APC_1: 0xfff
10081 00:39:20.929568 INFO: [NOCDAPC] D3_APC_0: 0x0
10082 00:39:20.932739 INFO: [NOCDAPC] D3_APC_1: 0xfff
10083 00:39:20.936488 INFO: [NOCDAPC] D4_APC_0: 0x0
10084 00:39:20.939591 INFO: [NOCDAPC] D4_APC_1: 0xfff
10085 00:39:20.939675 INFO: [NOCDAPC] D5_APC_0: 0x0
10086 00:39:20.943076 INFO: [NOCDAPC] D5_APC_1: 0xfff
10087 00:39:20.946451 INFO: [NOCDAPC] D6_APC_0: 0x0
10088 00:39:20.949280 INFO: [NOCDAPC] D6_APC_1: 0xfff
10089 00:39:20.953090 INFO: [NOCDAPC] D7_APC_0: 0x0
10090 00:39:20.956243 INFO: [NOCDAPC] D7_APC_1: 0xfff
10091 00:39:20.959625 INFO: [NOCDAPC] D8_APC_0: 0x0
10092 00:39:20.962880 INFO: [NOCDAPC] D8_APC_1: 0xfff
10093 00:39:20.965951 INFO: [NOCDAPC] D9_APC_0: 0x0
10094 00:39:20.969458 INFO: [NOCDAPC] D9_APC_1: 0xfff
10095 00:39:20.972891 INFO: [NOCDAPC] D10_APC_0: 0x0
10096 00:39:20.976268 INFO: [NOCDAPC] D10_APC_1: 0xfff
10097 00:39:20.976371 INFO: [NOCDAPC] D11_APC_0: 0x0
10098 00:39:20.979622 INFO: [NOCDAPC] D11_APC_1: 0xfff
10099 00:39:20.982860 INFO: [NOCDAPC] D12_APC_0: 0x0
10100 00:39:20.985923 INFO: [NOCDAPC] D12_APC_1: 0xfff
10101 00:39:20.989499 INFO: [NOCDAPC] D13_APC_0: 0x0
10102 00:39:20.993052 INFO: [NOCDAPC] D13_APC_1: 0xfff
10103 00:39:20.995833 INFO: [NOCDAPC] D14_APC_0: 0x0
10104 00:39:20.999339 INFO: [NOCDAPC] D14_APC_1: 0xfff
10105 00:39:21.002931 INFO: [NOCDAPC] D15_APC_0: 0x0
10106 00:39:21.005819 INFO: [NOCDAPC] D15_APC_1: 0xfff
10107 00:39:21.009296 INFO: [NOCDAPC] APC_CON: 0x4
10108 00:39:21.012728 INFO: [APUAPC] set_apusys_apc done
10109 00:39:21.015788 INFO: [DEVAPC] devapc_init done
10110 00:39:21.019335 INFO: GICv3 without legacy support detected.
10111 00:39:21.022201 INFO: ARM GICv3 driver initialized in EL3
10112 00:39:21.025724 INFO: Maximum SPI INTID supported: 639
10113 00:39:21.032107 INFO: BL31: Initializing runtime services
10114 00:39:21.035664 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10115 00:39:21.038768 INFO: SPM: enable CPC mode
10116 00:39:21.045385 INFO: mcdi ready for mcusys-off-idle and system suspend
10117 00:39:21.049032 INFO: BL31: Preparing for EL3 exit to normal world
10118 00:39:21.051996 INFO: Entry point address = 0x80000000
10119 00:39:21.055226 INFO: SPSR = 0x8
10120 00:39:21.060409
10121 00:39:21.060515
10122 00:39:21.060618
10123 00:39:21.063630 Starting depthcharge on Spherion...
10124 00:39:21.063736
10125 00:39:21.063834 Wipe memory regions:
10126 00:39:21.063928
10127 00:39:21.064747 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10128 00:39:21.064886 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10129 00:39:21.064976 Setting prompt string to ['asurada:']
10130 00:39:21.065100 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10131 00:39:21.067125 [0x00000040000000, 0x00000054600000)
10132 00:39:21.189588
10133 00:39:21.189717 [0x00000054660000, 0x00000080000000)
10134 00:39:21.450017
10135 00:39:21.450186 [0x000000821a7280, 0x000000ffe64000)
10136 00:39:22.195141
10137 00:39:22.195312 [0x00000100000000, 0x00000240000000)
10138 00:39:24.085563
10139 00:39:24.088446 Initializing XHCI USB controller at 0x11200000.
10140 00:39:25.127040
10141 00:39:25.129820 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10142 00:39:25.129937
10143 00:39:25.130048
10144 00:39:25.130382 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10146 00:39:25.230778 asurada: tftpboot 192.168.201.1 14173454/tftp-deploy-7kc_004t/kernel/image.itb 14173454/tftp-deploy-7kc_004t/kernel/cmdline
10147 00:39:25.230945 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10148 00:39:25.231046 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10149 00:39:25.235432 tftpboot 192.168.201.1 14173454/tftp-deploy-7kc_004t/kernel/image.itp-deploy-7kc_004t/kernel/cmdline
10150 00:39:25.235597
10151 00:39:25.235706 Waiting for link
10152 00:39:25.395868
10153 00:39:25.396025 R8152: Initializing
10154 00:39:25.396121
10155 00:39:25.399053 Version 6 (ocp_data = 5c30)
10156 00:39:25.399158
10157 00:39:25.402099 R8152: Done initializing
10158 00:39:25.402204
10159 00:39:25.402297 Adding net device
10160 00:39:27.306257
10161 00:39:27.306398 done.
10162 00:39:27.306474
10163 00:39:27.306537 MAC: 00:24:32:30:78:ff
10164 00:39:27.306595
10165 00:39:27.309401 Sending DHCP discover... done.
10166 00:39:27.309486
10167 00:39:27.312765 Waiting for reply... done.
10168 00:39:27.312893
10169 00:39:27.315626 Sending DHCP request... done.
10170 00:39:27.315747
10171 00:39:27.320818 Waiting for reply... done.
10172 00:39:27.320931
10173 00:39:27.321025 My ip is 192.168.201.21
10174 00:39:27.321117
10175 00:39:27.324426 The DHCP server ip is 192.168.201.1
10176 00:39:27.324546
10177 00:39:27.330488 TFTP server IP predefined by user: 192.168.201.1
10178 00:39:27.330580
10179 00:39:27.337106 Bootfile predefined by user: 14173454/tftp-deploy-7kc_004t/kernel/image.itb
10180 00:39:27.337208
10181 00:39:27.340638 Sending tftp read request... done.
10182 00:39:27.340724
10183 00:39:27.344112 Waiting for the transfer...
10184 00:39:27.344195
10185 00:39:27.870647 00000000 ################################################################
10186 00:39:27.870819
10187 00:39:28.396423 00080000 ################################################################
10188 00:39:28.396631
10189 00:39:28.923035 00100000 ################################################################
10190 00:39:28.923178
10191 00:39:29.446797 00180000 ################################################################
10192 00:39:29.446938
10193 00:39:30.050670 00200000 ################################################################
10194 00:39:30.050882
10195 00:39:30.670398 00280000 ################################################################
10196 00:39:30.670565
10197 00:39:31.250446 00300000 ################################################################
10198 00:39:31.250584
10199 00:39:31.784533 00380000 ################################################################
10200 00:39:31.784689
10201 00:39:32.331767 00400000 ################################################################
10202 00:39:32.331943
10203 00:39:32.865735 00480000 ################################################################
10204 00:39:32.865937
10205 00:39:33.399656 00500000 ################################################################
10206 00:39:33.399818
10207 00:39:33.933467 00580000 ################################################################
10208 00:39:33.933645
10209 00:39:34.460783 00600000 ################################################################
10210 00:39:34.460923
10211 00:39:34.997488 00680000 ################################################################
10212 00:39:34.997741
10213 00:39:35.518236 00700000 ################################################################
10214 00:39:35.518379
10215 00:39:36.043002 00780000 ################################################################
10216 00:39:36.043137
10217 00:39:36.593393 00800000 ################################################################
10218 00:39:36.593531
10219 00:39:37.124739 00880000 ################################################################
10220 00:39:37.124938
10221 00:39:37.657241 00900000 ################################################################
10222 00:39:37.657395
10223 00:39:38.196703 00980000 ################################################################
10224 00:39:38.196852
10225 00:39:38.744525 00a00000 ################################################################
10226 00:39:38.744672
10227 00:39:39.277665 00a80000 ################################################################
10228 00:39:39.277853
10229 00:39:39.839378 00b00000 ################################################################
10230 00:39:39.839547
10231 00:39:40.449220 00b80000 ################################################################
10232 00:39:40.449355
10233 00:39:41.021753 00c00000 ################################################################
10234 00:39:41.021952
10235 00:39:41.580345 00c80000 ################################################################
10236 00:39:41.580515
10237 00:39:42.127151 00d00000 ################################################################
10238 00:39:42.127297
10239 00:39:42.669926 00d80000 ################################################################
10240 00:39:42.670066
10241 00:39:43.193158 00e00000 ################################################################
10242 00:39:43.193293
10243 00:39:43.713900 00e80000 ################################################################
10244 00:39:43.714095
10245 00:39:44.231658 00f00000 ################################################################
10246 00:39:44.231809
10247 00:39:44.757144 00f80000 ################################################################
10248 00:39:44.757287
10249 00:39:45.275528 01000000 ################################################################
10250 00:39:45.275696
10251 00:39:45.796659 01080000 ################################################################
10252 00:39:45.796802
10253 00:39:46.329436 01100000 ################################################################
10254 00:39:46.329577
10255 00:39:46.866555 01180000 ################################################################
10256 00:39:46.866756
10257 00:39:47.392107 01200000 ################################################################
10258 00:39:47.392264
10259 00:39:47.909418 01280000 ################################################################
10260 00:39:47.909626
10261 00:39:48.426569 01300000 ################################################################
10262 00:39:48.426750
10263 00:39:48.943670 01380000 ################################################################
10264 00:39:48.943819
10265 00:39:49.464501 01400000 ################################################################
10266 00:39:49.464689
10267 00:39:49.991937 01480000 ################################################################
10268 00:39:49.992130
10269 00:39:50.521280 01500000 ################################################################
10270 00:39:50.521411
10271 00:39:51.045506 01580000 ################################################################
10272 00:39:51.045643
10273 00:39:51.574566 01600000 ################################################################
10274 00:39:51.574704
10275 00:39:52.104137 01680000 ################################################################
10276 00:39:52.104298
10277 00:39:52.630080 01700000 ################################################################
10278 00:39:52.630275
10279 00:39:53.166173 01780000 ################################################################
10280 00:39:53.166367
10281 00:39:53.728106 01800000 ################################################################
10282 00:39:53.728268
10283 00:39:54.259824 01880000 ################################################################
10284 00:39:54.259959
10285 00:39:54.792954 01900000 ################################################################
10286 00:39:54.793091
10287 00:39:55.328028 01980000 ################################################################
10288 00:39:55.328239
10289 00:39:55.891476 01a00000 ################################################################
10290 00:39:55.891623
10291 00:39:56.436998 01a80000 ################################################################
10292 00:39:56.437153
10293 00:39:56.973629 01b00000 ################################################################
10294 00:39:56.973769
10295 00:39:57.524731 01b80000 ################################################################
10296 00:39:57.524864
10297 00:39:58.092464 01c00000 ################################################################
10298 00:39:58.092656
10299 00:39:58.651760 01c80000 ################################################################
10300 00:39:58.651972
10301 00:39:59.210655 01d00000 ################################################################
10302 00:39:59.210789
10303 00:39:59.777585 01d80000 ################################################################
10304 00:39:59.777776
10305 00:40:00.192452 01e00000 ############################################### done.
10306 00:40:00.192624
10307 00:40:00.195721 The bootfile was 31841962 bytes long.
10308 00:40:00.195821
10309 00:40:00.199321 Sending tftp read request... done.
10310 00:40:00.199410
10311 00:40:00.199495 Waiting for the transfer...
10312 00:40:00.199577
10313 00:40:00.202595 00000000 # done.
10314 00:40:00.202701
10315 00:40:00.208903 Command line loaded dynamically from TFTP file: 14173454/tftp-deploy-7kc_004t/kernel/cmdline
10316 00:40:00.208990
10317 00:40:00.232402 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10318 00:40:00.232494
10319 00:40:00.232617 Loading FIT.
10320 00:40:00.232713
10321 00:40:00.235673 Image ramdisk-1 has 18732751 bytes.
10322 00:40:00.235758
10323 00:40:00.238827 Image fdt-1 has 47258 bytes.
10324 00:40:00.238912
10325 00:40:00.242159 Image kernel-1 has 13059919 bytes.
10326 00:40:00.242244
10327 00:40:00.252308 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10328 00:40:00.252394
10329 00:40:00.268612 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10330 00:40:00.268705
10331 00:40:00.275233 Choosing best match conf-1 for compat google,spherion-rev2.
10332 00:40:00.275334
10333 00:40:00.283120 Connected to device vid:did:rid of 1ae0:0028:00
10334 00:40:00.289816
10335 00:40:00.293392 tpm_get_response: command 0x17b, return code 0x0
10336 00:40:00.293478
10337 00:40:00.296811 ec_init: CrosEC protocol v3 supported (256, 248)
10338 00:40:00.300288
10339 00:40:00.303796 tpm_cleanup: add release locality here.
10340 00:40:00.303881
10341 00:40:00.303966 Shutting down all USB controllers.
10342 00:40:00.307061
10343 00:40:00.307146 Removing current net device
10344 00:40:00.307232
10345 00:40:00.314134 Exiting depthcharge with code 4 at timestamp: 68611177
10346 00:40:00.314220
10347 00:40:00.316828 LZMA decompressing kernel-1 to 0x821a6718
10348 00:40:00.316913
10349 00:40:00.320116 LZMA decompressing kernel-1 to 0x40000000
10350 00:40:01.929888
10351 00:40:01.930025 jumping to kernel
10352 00:40:01.930669 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10353 00:40:01.930808 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10354 00:40:01.930921 Setting prompt string to ['Linux version [0-9]']
10355 00:40:01.931029 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10356 00:40:01.931141 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10357 00:40:02.011670
10358 00:40:02.015089 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10359 00:40:02.018508 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10360 00:40:02.018615 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10361 00:40:02.018700 Setting prompt string to []
10362 00:40:02.018831 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10363 00:40:02.018921 Using line separator: #'\n'#
10364 00:40:02.018994 No login prompt set.
10365 00:40:02.019077 Parsing kernel messages
10366 00:40:02.019150 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10367 00:40:02.019331 [login-action] Waiting for messages, (timeout 00:03:44)
10368 00:40:02.019439 Waiting using forced prompt support (timeout 00:01:52)
10369 00:40:02.038342 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10370 00:40:02.041265 [ 0.000000] random: crng init done
10371 00:40:02.048160 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10372 00:40:02.051260 [ 0.000000] efi: UEFI not found.
10373 00:40:02.058354 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10374 00:40:02.067817 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10375 00:40:02.077834 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10376 00:40:02.084682 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10377 00:40:02.091382 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10378 00:40:02.097953 [ 0.000000] printk: bootconsole [mtk8250] enabled
10379 00:40:02.104706 [ 0.000000] NUMA: No NUMA configuration found
10380 00:40:02.111428 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10381 00:40:02.118007 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10382 00:40:02.118093 [ 0.000000] Zone ranges:
10383 00:40:02.124167 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10384 00:40:02.127436 [ 0.000000] DMA32 empty
10385 00:40:02.134230 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10386 00:40:02.137478 [ 0.000000] Movable zone start for each node
10387 00:40:02.141050 [ 0.000000] Early memory node ranges
10388 00:40:02.147349 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10389 00:40:02.154250 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10390 00:40:02.160711 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10391 00:40:02.167489 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10392 00:40:02.173929 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10393 00:40:02.180728 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10394 00:40:02.236843 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10395 00:40:02.243685 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10396 00:40:02.250145 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10397 00:40:02.253947 [ 0.000000] psci: probing for conduit method from DT.
10398 00:40:02.260015 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10399 00:40:02.263406 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10400 00:40:02.270297 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10401 00:40:02.273460 [ 0.000000] psci: SMC Calling Convention v1.2
10402 00:40:02.279805 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10403 00:40:02.283354 [ 0.000000] Detected VIPT I-cache on CPU0
10404 00:40:02.289825 [ 0.000000] CPU features: detected: GIC system register CPU interface
10405 00:40:02.296527 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10406 00:40:02.303657 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10407 00:40:02.309834 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10408 00:40:02.319910 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10409 00:40:02.326477 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10410 00:40:02.329838 [ 0.000000] alternatives: applying boot alternatives
10411 00:40:02.336429 [ 0.000000] Fallback order for Node 0: 0
10412 00:40:02.342774 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10413 00:40:02.345980 [ 0.000000] Policy zone: Normal
10414 00:40:02.369299 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10415 00:40:02.378835 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10416 00:40:02.390137 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10417 00:40:02.400075 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10418 00:40:02.406645 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10419 00:40:02.409778 <6>[ 0.000000] software IO TLB: area num 8.
10420 00:40:02.466629 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10421 00:40:02.615546 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10422 00:40:02.622121 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10423 00:40:02.628842 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10424 00:40:02.632285 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10425 00:40:02.638892 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10426 00:40:02.645400 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10427 00:40:02.648520 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10428 00:40:02.658920 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10429 00:40:02.665529 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10430 00:40:02.671860 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10431 00:40:02.678496 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10432 00:40:02.681898 <6>[ 0.000000] GICv3: 608 SPIs implemented
10433 00:40:02.685074 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10434 00:40:02.691481 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10435 00:40:02.694724 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10436 00:40:02.701455 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10437 00:40:02.714987 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10438 00:40:02.728185 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10439 00:40:02.734453 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10440 00:40:02.742320 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10441 00:40:02.755247 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10442 00:40:02.761898 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10443 00:40:02.768510 <6>[ 0.009142] Console: colour dummy device 80x25
10444 00:40:02.778525 <6>[ 0.013867] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10445 00:40:02.785320 <6>[ 0.024308] pid_max: default: 32768 minimum: 301
10446 00:40:02.788493 <6>[ 0.029211] LSM: Security Framework initializing
10447 00:40:02.795115 <6>[ 0.034180] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 00:40:02.805466 <6>[ 0.041996] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10449 00:40:02.814827 <6>[ 0.051400] cblist_init_generic: Setting adjustable number of callback queues.
10450 00:40:02.818702 <6>[ 0.058844] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 00:40:02.828542 <6>[ 0.065219] cblist_init_generic: Setting adjustable number of callback queues.
10452 00:40:02.834840 <6>[ 0.072646] cblist_init_generic: Setting shift to 3 and lim to 1.
10453 00:40:02.837982 <6>[ 0.079084] rcu: Hierarchical SRCU implementation.
10454 00:40:02.844754 <6>[ 0.079086] rcu: Max phase no-delay instances is 1000.
10455 00:40:02.851446 <6>[ 0.079109] printk: bootconsole [mtk8250] printing thread started
10456 00:40:02.858134 <6>[ 0.097405] EFI services will not be available.
10457 00:40:02.861624 <6>[ 0.097608] smp: Bringing up secondary CPUs ...
10458 00:40:02.864692 <6>[ 0.097914] Detected VIPT I-cache on CPU1
10459 00:40:02.874555 <6>[ 0.097982] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10460 00:40:02.881204 <6>[ 0.098014] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10461 00:40:02.890715 <6>[ 0.125860] Detected VIPT I-cache on CPU2
10462 00:40:02.897293 <6>[ 0.125912] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10463 00:40:02.907152 <6>[ 0.125930] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10464 00:40:02.910611 <6>[ 0.126181] Detected VIPT I-cache on CPU3
10465 00:40:02.917004 <6>[ 0.126225] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10466 00:40:02.923458 <6>[ 0.126239] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10467 00:40:02.926793 <6>[ 0.126529] CPU features: detected: Spectre-v4
10468 00:40:02.933425 <6>[ 0.126534] CPU features: detected: Spectre-BHB
10469 00:40:02.936691 <6>[ 0.126538] Detected PIPT I-cache on CPU4
10470 00:40:02.943058 <6>[ 0.126598] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10471 00:40:02.950198 <6>[ 0.126616] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10472 00:40:02.956711 <6>[ 0.126900] Detected PIPT I-cache on CPU5
10473 00:40:02.963149 <6>[ 0.126959] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10474 00:40:02.969884 <6>[ 0.126975] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10475 00:40:02.973267 <6>[ 0.127254] Detected PIPT I-cache on CPU6
10476 00:40:02.979440 <6>[ 0.127319] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10477 00:40:02.990826 <6>[ 0.127334] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10478 00:40:02.993973 <6>[ 0.127622] Detected PIPT I-cache on CPU7
10479 00:40:03.000781 <6>[ 0.127686] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10480 00:40:03.007176 <6>[ 0.127701] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10481 00:40:03.010066 <6>[ 0.127748] smp: Brought up 1 node, 8 CPUs
10482 00:40:03.016771 <6>[ 0.127753] SMP: Total of 8 processors activated.
10483 00:40:03.023453 <6>[ 0.127755] CPU features: detected: 32-bit EL0 Support
10484 00:40:03.030045 <6>[ 0.127758] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10485 00:40:03.036823 <6>[ 0.127760] CPU features: detected: Common not Private translations
10486 00:40:03.043228 <6>[ 0.127762] CPU features: detected: CRC32 instructions
10487 00:40:03.049692 <6>[ 0.127765] CPU features: detected: RCpc load-acquire (LDAPR)
10488 00:40:03.053117 <6>[ 0.127766] CPU features: detected: LSE atomic instructions
10489 00:40:03.059782 <6>[ 0.127768] CPU features: detected: Privileged Access Never
10490 00:40:03.066194 <6>[ 0.127769] CPU features: detected: RAS Extension Support
10491 00:40:03.072756 <6>[ 0.127772] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10492 00:40:03.076329 <6>[ 0.127837] CPU: All CPU(s) started at EL2
10493 00:40:03.082762 <6>[ 0.127838] alternatives: applying system-wide alternatives
10494 00:40:03.085922 <6>[ 0.141078] devtmpfs: initialized
10495 00:40:03.096009 <6>[ 0.147385] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10496 00:40:03.102167 <6>[ 0.147399] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10497 00:40:03.129164 <6>[ 0.369421] printk: console [tty<S0] printing thread started
10498 00:40:03.135891 6><6>[ 0.369442] printk: console [ttyS0] enabled
10499 00:40:03.139025 [ 0.148263] pinctrl core: initialized pinctrl subsystem
10500 00:40:03.148072 <6>[ 0.369450] printk: bootconsole [mtk8250] disabled
10501 00:40:03.154597 <6>[ 0.385198] printk: bootconsole [mtk8250] printing thread stopped
10502 00:40:03.157905 <6>[ 0.386601] SuperH (H)SCI(F) driver initialized
10503 00:40:03.164482 <6>[ 0.387079] msm_serial: driver initialized
10504 00:40:03.171068 <6>[ 0.391729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10505 00:40:03.181184 <6>[ 0.391761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10506 00:40:03.187789 <6>[ 0.391792] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10507 00:40:03.201580 <6>[ 0.391820] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10508 00:40:03.211786 <6>[ 0.391841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10509 00:40:03.220312 <6>[ 0.391868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10510 00:40:03.224755 <6>[ 0.391896] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10511 00:40:03.237447 <6>[ 0.392030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10512 00:40:03.242669 <6>[ 0.392058] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10513 00:40:03.250435 <6>[ 0.403745] loop: module loaded
10514 00:40:03.255456 <6>[ 0.406275] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10515 00:40:03.258882 <4>[ 0.423029] mtk-pmic-keys: Failed to locate of_node [id: -1]
10516 00:40:03.262230 <6>[ 0.424007] megasas: 07.719.03.00-rc1
10517 00:40:03.265492 <6>[ 0.436167] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10518 00:40:03.272106 <6>[ 0.440025] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10519 00:40:03.278895 <6>[ 0.451651] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10520 00:40:03.288425 <6>[ 0.504161] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10521 00:40:03.788222 <6>[ 1.026339] Freeing initrd memory: 18288K
10522 00:40:03.796161 <6>[ 1.033595] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10523 00:40:03.802819 <6>[ 1.038379] tun: Universal TUN/TAP device driver, 1.6
10524 00:40:03.806100 <6>[ 1.039147] thunder_xcv, ver 1.0
10525 00:40:03.809312 <6>[ 1.039170] thunder_bgx, ver 1.0
10526 00:40:03.812718 <6>[ 1.039183] nicpf, ver 1.0
10527 00:40:03.819447 <6>[ 1.040249] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10528 00:40:03.825872 <6>[ 1.040252] hns3: Copyright (c) 2017 Huawei Corporation.
10529 00:40:03.829368 <6>[ 1.040278] hclge is initializing
10530 00:40:03.835887 <6>[ 1.040293] e1000: Intel(R) PRO/1000 Network Driver
10531 00:40:03.839735 <6>[ 1.040295] e1000: Copyright (c) 1999-2006 Intel Corporation.
10532 00:40:03.846630 <6>[ 1.040314] e1000e: Intel(R) PRO/1000 Network Driver
10533 00:40:03.850485 <6>[ 1.040315] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10534 00:40:03.857540 <6>[ 1.040330] igb: Intel(R) Gigabit Ethernet Network Driver
10535 00:40:03.864038 <6>[ 1.040332] igb: Copyright (c) 2007-2014 Intel Corporation.
10536 00:40:03.870787 <6>[ 1.040348] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10537 00:40:03.874071 <6>[ 1.040350] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10538 00:40:03.881127 <6>[ 1.040647] sky2: driver version 1.30
10539 00:40:03.884888 <6>[ 1.041660] usbcore: registered new device driver r8152-cfgselector
10540 00:40:03.891058 <6>[ 1.041679] usbcore: registered new interface driver r8152
10541 00:40:03.897751 <6>[ 1.041765] VFIO - User Level meta-driver version: 0.3
10542 00:40:03.904785 <6>[ 1.044581] usbcore: registered new interface driver usb-storage
10543 00:40:03.911116 <6>[ 1.044770] usbcore: registered new device driver onboard-usb-hub
10544 00:40:03.914379 <6>[ 1.047549] mt6397-rtc mt6359-rtc: registered as rtc0
10545 00:40:03.924363 <6>[ 1.047698] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T00:40:04 UTC (1717548004)
10546 00:40:03.927515 <6>[ 1.048303] i2c_dev: i2c /dev entries driver
10547 00:40:03.937832 <6>[ 1.055455] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10548 00:40:03.944123 <4>[ 1.056178] cpu cpu0: supply cpu not found, using dummy regulator
10549 00:40:03.950515 <4>[ 1.056255] cpu cpu1: supply cpu not found, using dummy regulator
10550 00:40:03.953879 <4>[ 1.056326] cpu cpu2: supply cpu not found, using dummy regulator
10551 00:40:03.961114 <4>[ 1.056377] cpu cpu3: supply cpu not found, using dummy regulator
10552 00:40:03.967345 <4>[ 1.056430] cpu cpu4: supply cpu not found, using dummy regulator
10553 00:40:03.974491 <4>[ 1.056474] cpu cpu5: supply cpu not found, using dummy regulator
10554 00:40:03.981106 <4>[ 1.056529] cpu cpu6: supply cpu not found, using dummy regulator
10555 00:40:03.987700 <4>[ 1.056577] cpu cpu7: supply cpu not found, using dummy regulator
10556 00:40:03.990981 <6>[ 1.071785] cpu cpu0: EM: created perf domain
10557 00:40:03.997283 <6>[ 1.072111] cpu cpu4: EM: created perf domain
10558 00:40:04.004151 <6>[ 1.074875] sdhci: Secure Digital Host Controller Interface driver
10559 00:40:04.007251 <6>[ 1.074877] sdhci: Copyright(c) Pierre Ossman
10560 00:40:04.014131 <6>[ 1.075235] Synopsys Designware Multimedia Card Interface Driver
10561 00:40:04.020753 <6>[ 1.075616] sdhci-pltfm: SDHCI platform and OF driver helper
10562 00:40:04.027368 <6>[ 1.079973] ledtrig-cpu: registered to indicate activity on CPUs
10563 00:40:04.030643 <6>[ 1.080340] mmc0: CQHCI version 5.10
10564 00:40:04.037159 <6>[ 1.080925] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10565 00:40:04.043726 <6>[ 1.081211] usbcore: registered new interface driver usbhid
10566 00:40:04.047311 <6>[ 1.081212] usbhid: USB HID core driver
10567 00:40:04.053598 <6>[ 1.081321] spi_master spi0: will run message pump with realtime priority
10568 00:40:04.067248 <6>[ 1.115913] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10569 00:40:04.080139 <6>[ 1.117905] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10570 00:40:04.087259 <6>[ 1.118808] cros-ec-spi spi0.0: Chrome EC device registered
10571 00:40:04.093789 <6>[ 1.137535] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10572 00:40:04.100487 <6>[ 1.140809] NET: Registered PF_PACKET protocol family
10573 00:40:04.103458 <6>[ 1.140941] 9pnet: Installing 9P2000 support
10574 00:40:04.110602 <5>[ 1.140982] Key type dns_resolver registered
10575 00:40:04.113269 <6>[ 1.141399] registered taskstats version 1
10576 00:40:04.117195 <5>[ 1.141421] Loading compiled-in X.509 certificates
10577 00:40:04.130031 <4>[ 1.158229] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 00:40:04.140007 <4>[ 1.158494] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 00:40:04.146834 <6>[ 1.169840] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17814
10580 00:40:04.150008 <6>[ 1.171768] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10581 00:40:04.156881 <6>[ 1.172320] xhci-mtk 11200000.usb: xHCI Host Controller
10582 00:40:04.163461 <6>[ 1.172336] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10583 00:40:04.173071 <6>[ 1.172548] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10584 00:40:04.179779 <6>[ 1.172592] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10585 00:40:04.186705 <6>[ 1.172729] xhci-mtk 11200000.usb: xHCI Host Controller
10586 00:40:04.192767 <6>[ 1.172744] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10587 00:40:04.199892 <6>[ 1.172759] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10588 00:40:04.202678 <6>[ 1.173145] hub 1-0:1.0: USB hub found
10589 00:40:04.209906 <6>[ 1.173164] hub 1-0:1.0: 1 port detected
10590 00:40:04.216456 <6>[ 1.173379] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10591 00:40:04.219781 <6>[ 1.173738] hub 2-0:1.0: USB hub found
10592 00:40:04.226544 <6>[ 1.173760] hub 2-0:1.0: 1 port detected
10593 00:40:04.229848 <6>[ 1.174328] mmc0: Command Queue Engine enabled
10594 00:40:04.235997 <6>[ 1.174339] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10595 00:40:04.242779 <6>[ 1.174789] mmcblk0: mmc0:0001 DA4128 116 GiB
10596 00:40:04.246131 <6>[ 1.177463] mtk-msdc 11f70000.mmc: Got CD GPIO
10597 00:40:04.252995 <6>[ 1.178377] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10598 00:40:04.256134 <6>[ 1.179452] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10599 00:40:04.262937 <6>[ 1.180039] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10600 00:40:04.269064 <6>[ 1.180568] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10601 00:40:04.275960 <6>[ 1.194417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 00:40:04.285563 <6>[ 1.194427] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 00:40:04.291963 <4>[ 1.194587] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 00:40:04.301918 <6>[ 1.195221] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 00:40:04.308463 <6>[ 1.195224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 00:40:04.318921 <6>[ 1.195345] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 00:40:04.325557 <6>[ 1.195356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 00:40:04.331859 <6>[ 1.195360] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 00:40:04.341652 <6>[ 1.195369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 00:40:04.351841 <6>[ 1.196896] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 00:40:04.358097 <6>[ 1.196915] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 00:40:04.368032 <6>[ 1.196921] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 00:40:04.375034 <6>[ 1.196926] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 00:40:04.384734 <6>[ 1.196932] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 00:40:04.391120 <6>[ 1.196938] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 00:40:04.400874 <6>[ 1.196943] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 00:40:04.407998 <6>[ 1.196949] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 00:40:04.417754 <6>[ 1.196954] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 00:40:04.424483 <6>[ 1.196960] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 00:40:04.434326 <6>[ 1.196965] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 00:40:04.440452 <6>[ 1.196971] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 00:40:04.450825 <6>[ 1.196976] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 00:40:04.457476 <6>[ 1.196982] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 00:40:04.467027 <6>[ 1.196987] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 00:40:04.473878 <6>[ 1.197503] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 00:40:04.480419 <6>[ 1.198353] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 00:40:04.486927 <6>[ 1.198905] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 00:40:04.493455 <6>[ 1.199527] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 00:40:04.500502 <6>[ 1.200135] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 00:40:04.510510 <6>[ 1.200339] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 00:40:04.517032 <6>[ 1.200355] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 00:40:04.526889 <6>[ 1.200361] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 00:40:04.536665 <6>[ 1.200367] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 00:40:04.546584 <6>[ 1.200374] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 00:40:04.556494 <6>[ 1.200379] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 00:40:04.566646 <6>[ 1.200386] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 00:40:04.573204 <6>[ 1.200391] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 00:40:04.582998 <6>[ 1.200397] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 00:40:04.593386 <6>[ 1.200404] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 00:40:04.602998 <6>[ 1.200409] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 00:40:04.612848 <6>[ 1.201305] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 00:40:04.619312 <6>[ 1.215808] Trying to probe devices needed for running init ...
10643 00:40:04.626043 <6>[ 1.584778] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10644 00:40:04.629173 <6>[ 1.736324] hub 1-1:1.0: USB hub found
10645 00:40:04.632552 <6>[ 1.736546] hub 1-1:1.0: 4 ports detected
10646 00:40:04.636107 <6>[ 1.739724] hub 1-1:1.0: USB hub found
10647 00:40:04.642594 <6>[ 1.740017] hub 1-1:1.0: 4 ports detected
10648 00:40:04.649349 <6>[ 1.861008] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10649 00:40:04.652538 <6>[ 1.885973] hub 2-1:1.0: USB hub found
10650 00:40:04.655634 <6>[ 1.886402] hub 2-1:1.0: 3 ports detected
10651 00:40:04.659232 <6>[ 1.889942] hub 2-1:1.0: USB hub found
10652 00:40:04.665728 <6>[ 1.890366] hub 2-1:1.0: 3 ports detected
10653 00:40:04.819609 <6>[ 2.052907] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10654 00:40:04.939959 <6>[ 2.180314] hub 1-1.4:1.0: USB hub found
10655 00:40:04.943659 <6>[ 2.180755] hub 1-1.4:1.0: 2 ports detected
10656 00:40:04.946722 <6>[ 2.184474] hub 1-1.4:1.0: USB hub found
10657 00:40:04.953403 <6>[ 2.184903] hub 1-1.4:1.0: 2 ports detected
10658 00:40:05.027191 <6>[ 2.261038] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10659 00:40:05.131435 <6>[ 2.365453] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10660 00:40:05.155265 <4>[ 2.392141] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10661 00:40:05.165264 <4>[ 2.392160] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10662 00:40:05.187848 <6>[ 2.425939] r8152 2-1.3:1.0 eth0: v1.12.13
10663 00:40:05.239150 <6>[ 2.472854] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10664 00:40:05.422952 <6>[ 2.656880] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10665 00:40:06.801203 <6>[ 4.039151] r8152 2-1.3:1.0 eth0: carrier on
10666 00:40:08.978743 <5>[ 4.068880] Sending DHCP requests .., OK
10667 00:40:08.985082 <6>[ 6.212789] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10668 00:40:08.991548 Loading, please <6>[ 6.212807] IP-Config: Complete:
10669 00:40:08.991631 wait...
10670 00:40:09.001797 <6>[ 6.212809] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10671 00:40:09.011814 <6>[ 6.212819] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10672 00:40:09.018371 <6>[ 6.212824] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10673 00:40:09.024840 Starting systemd<6>[ 6.212830] nameserver0=192.168.201.1
10674 00:40:09.028501 -udevd version 2<6>[ 6.213107] clk: Disabling unused clocks
10675 00:40:09.031435 52.22-1~deb12u1
10676 00:40:09.034804 <6>[ 6.214183] ALSA device list:
10677 00:40:09.034886
10678 00:40:09.038022 <6>[ 6.214197] No soundcards found.
10679 00:40:09.041064 <6>[ 6.218540] Freeing unused kernel memory: 8512K
10680 00:40:09.047765 <6>[ 6.218738] Run /init as init process
10681 00:40:09.279172 <6>[ 6.515761] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10682 00:40:09.282296 <6>[ 6.519511] remoteproc remoteproc0: scp is available
10683 00:40:09.289240 <6>[ 6.519688] remoteproc remoteproc0: powering up scp
10684 00:40:09.295741 <6>[ 6.519697] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10685 00:40:09.302618 <6>[ 6.519751] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10686 00:40:09.319080 <6>[ 6.553047] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10687 00:40:09.325569 <6>[ 6.553086] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10688 00:40:09.335418 <6>[ 6.553094] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10689 00:40:09.342033 <6>[ 6.577803] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10690 00:40:09.352183 <3>[ 6.577963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 00:40:09.358722 <3>[ 6.577982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 00:40:09.368458 <3>[ 6.577993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 00:40:09.375582 <3>[ 6.578085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 00:40:09.382213 <3>[ 6.578097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 00:40:09.392218 <3>[ 6.578103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 00:40:09.399262 <3>[ 6.578118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 00:40:09.409573 <3>[ 6.578127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 00:40:09.416447 <3>[ 6.578235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 00:40:09.423050 <3>[ 6.578294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 00:40:09.432709 <3>[ 6.578304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 00:40:09.439706 <3>[ 6.578311] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 00:40:09.449547 <3>[ 6.578370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 00:40:09.456028 <3>[ 6.578378] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 00:40:09.465771 <3>[ 6.578385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 00:40:09.472476 <3>[ 6.578392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 00:40:09.478804 <3>[ 6.578398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 00:40:09.488810 <3>[ 6.578496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 00:40:09.495521 <4>[ 6.590559] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10709 00:40:09.502161 <4>[ 6.591630] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10710 00:40:09.511794 <4>[ 6.609196] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10711 00:40:09.515083 <4>[ 6.609196] Fallback method does not support PEC.
10712 00:40:09.522033 <6>[ 6.622590] mc: Linux media interface: v0.10
10713 00:40:09.531594 <3>[ 6.630979] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 00:40:09.538189 <6>[ 6.645048] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10715 00:40:09.545047 <6>[ 6.645053] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10716 00:40:09.551519 <6>[ 6.645068] remoteproc remoteproc0: remote processor scp is now up
10717 00:40:09.561628 <3>[ 6.654685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 00:40:09.568364 <6>[ 6.674025] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10719 00:40:09.574628 <6>[ 6.674038] pci_bus 0000:00: root bus resource [bus 00-ff]
10720 00:40:09.581048 <6>[ 6.674047] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10721 00:40:09.591178 <6>[ 6.674052] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10722 00:40:09.597488 <6>[ 6.674083] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10723 00:40:09.604274 <6>[ 6.674103] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10724 00:40:09.607591 <6>[ 6.674182] pci 0000:00:00.0: supports D1 D2
10725 00:40:09.614134 <6>[ 6.674186] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10726 00:40:09.624085 <6>[ 6.675771] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10727 00:40:09.630688 <6>[ 6.675908] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10728 00:40:09.637160 <6>[ 6.675941] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10729 00:40:09.643981 <6>[ 6.675961] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10730 00:40:09.654244 <6>[ 6.675980] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10731 00:40:09.657510 <6>[ 6.676103] pci 0000:01:00.0: supports D1 D2
10732 00:40:09.663968 <6>[ 6.676106] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10733 00:40:09.670327 <6>[ 6.679321] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10734 00:40:09.680726 <6>[ 6.680427] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10735 00:40:09.687179 <6>[ 6.684693] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10736 00:40:09.693975 <6>[ 6.684744] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10737 00:40:09.703658 <6>[ 6.684751] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10738 00:40:09.710054 <6>[ 6.684765] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10739 00:40:09.720248 <6>[ 6.684782] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10740 00:40:09.727090 <6>[ 6.684798] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10741 00:40:09.733396 <6>[ 6.684814] pci 0000:00:00.0: PCI bridge to [bus 01]
10742 00:40:09.741531 <6>[ 6.684822] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10743 00:40:09.746670 <6>[ 6.684958] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10744 00:40:09.753786 <6>[ 6.685878] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10745 00:40:09.759827 <6>[ 6.686178] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10746 00:40:09.769947 <6>[ 6.703579] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10747 00:40:09.779639 <6>[ 6.721877] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10748 00:40:09.786453 <6>[ 6.722219] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10749 00:40:09.792992 <6>[ 6.735234] videodev: Linux video capture interface: v2.00
10750 00:40:09.799648 <5>[ 6.746466] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10751 00:40:09.805845 <6>[ 6.763746] Bluetooth: Core ver 2.22
10752 00:40:09.809451 <6>[ 6.763908] NET: Registered PF_BLUETOOTH protocol family
10753 00:40:09.815991 <6>[ 6.763913] Bluetooth: HCI device and connection manager initialized
10754 00:40:09.822551 <6>[ 6.763957] Bluetooth: HCI socket layer initialized
10755 00:40:09.825919 <6>[ 6.763966] Bluetooth: L2CAP socket layer initialized
10756 00:40:09.832385 <6>[ 6.763978] Bluetooth: SCO socket layer initialized
10757 00:40:09.838959 <5>[ 6.766275] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10758 00:40:09.849033 <5>[ 6.766512] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10759 00:40:09.855441 <4>[ 6.766574] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10760 00:40:09.862407 <6>[ 6.766580] cfg80211: failed to load regulatory.db
10761 00:40:09.868731 <6>[ 6.809340] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10762 00:40:09.881730 <6>[ 6.810975] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10763 00:40:09.888536 <6>[ 6.811141] usbcore: registered new interface driver uvcvideo
10764 00:40:09.891529 <6>[ 6.837958] usbcore: registered new interface driver btusb
10765 00:40:09.901729 <4>[ 6.838893] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 00:40:09.908176 <3>[ 6.838916] Bluetooth: hci0: Failed to load firmware file (-2)
10767 00:40:09.915146 <3>[ 6.838921] Bluetooth: hci0: Failed to set up firmware (-2)
10768 00:40:09.924766 <4>[ 6.838927] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 00:40:09.931272 <6>[ 6.851246] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10770 00:40:09.937780 <6>[ 6.877905] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10771 00:40:09.944440 <6>[ 6.877993] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10772 00:40:09.951177 <6>[ 6.896731] mt7921e 0000:01:00.0: ASIC revision: 79610010
10773 00:40:09.960861 <6>[ 6.987666] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10774 00:40:09.960946 <6>[ 6.987666]
10775 00:40:09.964331 Begin: Loading essential drivers ... done.
10776 00:40:09.970619 Begin: Running /scripts/init-premount ... done.
10777 00:40:09.977440 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10778 00:40:09.983876 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10779 00:40:09.987813 Device /sys/class/net/eth0 found
10780 00:40:09.987895 done.
10781 00:40:09.997042 Begin: Waiting up to 180 secs for any network device to become available ... done.
10782 00:40:10.010735 <6>[ 7.245776] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10783 00:40:10.040096 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10784 00:40:10.046261 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10785 00:40:10.052884 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10786 00:40:10.059750 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10787 00:40:10.066416 host : mt8192-asurada-spherion-r0-cbg-8
10788 00:40:10.072913 domain : lava-rack
10789 00:40:10.076055 rootserver: 192.168.201.1 rootpath:
10790 00:40:10.076136 filename :
10791 00:40:10.218819 done.
10792 00:40:10.226197 Begin: Running /scripts/nfs-bottom ... done.
10793 00:40:10.243612 Begin: Running /scripts/init-bottom ... done.
10794 00:40:11.587052 <6>[ 8.827657] NET: Registered PF_INET6 protocol family
10795 00:40:11.595566 <6>[ 8.834552] Segment Routing with IPv6
10796 00:40:11.598673 <6>[ 8.834569] In-situ OAM (IOAM) with IPv6
10797 00:40:11.757866 <30>[ 8.969526] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10798 00:40:11.761384
10799 00:40:11.767753 Welcome to [1mDebian GNU/Linux 12 (bookworm)<30>[ 8.969566] systemd[1]: Detected architecture arm64.
10800 00:40:11.767835 [0m!
10801 00:40:11.771268
10802 00:40:11.795058 <30>[ 9.034394] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10803 00:40:12.866519 <30>[ 10.102919] systemd[1]: Queued start job for default target graphical.target.
10804 00:40:12.899562 [[0;32m OK [0m] Created slic<30>[ 10.133940] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10805 00:40:12.903163 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10806 00:40:12.928196 [[0;32m OK [0m] Created slic<30>[ 10.162749] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10807 00:40:12.931712 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10808 00:40:12.956068 [[0;32m OK [0m] Created slic<30>[ 10.190617] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10809 00:40:12.962493 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10810 00:40:12.983306 [[0;32m OK [0m] Created slic<30>[ 10.218274] systemd[1]: Created slice user.slice - User and Session Slice.
10811 00:40:12.987000 e [0;1;39muser.slice[0m - User and Session Slice.
10812 00:40:13.013693 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 10.245217] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10813 00:40:13.017499 -passwo…quests to Console Directory Watch.
10814 00:40:13.041867 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 10.273149] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10815 00:40:13.045140 -passwo… Requests to Wall Directory Watch.
10816 00:40:13.079603 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 10.301061] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10817 00:40:13.086106 <30>[ 10.301193] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10818 00:40:13.089804 ice[0m - /dev/ttyS0...
10819 00:40:13.109870 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 10.344905] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10820 00:40:13.113420 tsetup.…get[0m - Local Encrypted Volumes.
10821 00:40:13.137647 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 10.369032] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10822 00:40:13.140850 grityse…Local Integrity Protected Volumes.
10823 00:40:13.162382 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 10.397008] systemd[1]: Reached target paths.target - Path Units.
10824 00:40:13.162467 s.target[0m - Path Units.
10825 00:40:13.186740 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 10.421377] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10826 00:40:13.189957 te-fs.target[0m - Remote File Systems.
10827 00:40:13.210272 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 10.444925] systemd[1]: Reached target slices.target - Slice Units.
10828 00:40:13.213457 es.target[0m - Slice Units.
10829 00:40:13.234092 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 10.468965] systemd[1]: Reached target swap.target - Swaps.
10830 00:40:13.234178 .target[0m - Swaps.
10831 00:40:13.258205 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 10.493038] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10832 00:40:13.265071 tysetup… - Local Verity Protected Volumes.
10833 00:40:13.289775 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.521353] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10834 00:40:13.292697 d-initc… initctl Compatibility Named Pipe.
10835 00:40:13.316698 [[0;32m OK [<30>[ 10.551524] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10836 00:40:13.323004 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10837 00:40:13.343497 [[0;32m OK [0m] Listening on<30>[ 10.578298] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10838 00:40:13.349902 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10839 00:40:13.371058 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.605529] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10840 00:40:13.373775 d-journald.socket[0m - Journal Socket.
10841 00:40:13.395451 [[0;32m OK [0m] Listening on<30>[ 10.630446] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10842 00:40:13.402421 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10843 00:40:13.421695 [[0;32m OK [<30>[ 10.659773] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10844 00:40:13.431678 0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10845 00:40:13.450642 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.685402] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10846 00:40:13.453902 d-udevd…l.socket[0m - udev Kernel Socket.
10847 00:40:13.510641 Mounting [0;1;39mdev-hugepages.mount[<30>[ 10.745116] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10848 00:40:13.513656 0m - Huge Pages File System...
10849 00:40:13.539405 Mounting [0;1;39mdev-m<30>[ 10.774056] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10850 00:40:13.542386 queue.mount…POSIX Message Queue File System...
10851 00:40:13.572227 Mounting [0;1;39msys-k<30>[ 10.806842] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10852 00:40:13.575443 ernel-debug.…[0m - Kernel Debug File System...
10853 00:40:13.605178 <30>[ 10.833475] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10854 00:40:13.645885 Starting [0;1;39mkmod-static-nodes…a<30>[ 10.877535] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10855 00:40:13.649129 te List of Static Device Nodes...
10856 00:40:13.675468 Starting [0;1;39mmodpr<30>[ 10.910380] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10857 00:40:13.678817 obe@configfs…m - Load Kernel Module configfs...
10858 00:40:13.706205 Starting [0;1;39mmodprobe@dm_mod.s…[<30>[ 10.940692] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10859 00:40:13.709303 0m - Load Kernel Module dm_mod...
10860 00:40:13.735631 Starting [0;1;39mmodpr<30>[ 10.970089] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10861 00:40:13.738652 obe@drm.service[0m - Load Kernel Module drm...
10862 00:40:13.748244 <6>[ 10.983704] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10863 00:40:13.748331
10864 00:40:13.803025 Starting [0;1;39mmodpr<30>[ 11.037800] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10865 00:40:13.806236 obe@efi_psto…- Load Kernel Module efi_pstore...
10866 00:40:13.835420 Starting [0;1;39mmodpr<30>[ 11.070298] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10867 00:40:13.838995 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10868 00:40:13.867125 Starting [0;1;39mmodpr<30>[ 11.101876] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10869 00:40:13.873820 obe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 11.115372] fuse: init (API version 7.37)
10870 00:40:13.873911 .
10871 00:40:13.908026 Starting [0;1;39msyste<30>[ 11.142747] systemd[1]: Starting systemd-journald.service - Journal Service...
10872 00:40:13.911294 md-journald.service[0m - Journal Service...
10873 00:40:13.967471 Starting [0;1;39msyste<30>[ 11.201592] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10874 00:40:13.970928 md-modules-l…rvice[0m - Load Kernel Modules...
10875 00:40:14.002541 Starting [0;1;39msyste<30>[ 11.233765] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10876 00:40:14.005507 md-network-g… units from Kernel command line...
10877 00:40:14.037721 Starting [0;1;39msystemd-remount-f…n<30>[ 11.268563] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10878 00:40:14.041070 t Root and Kernel File Systems...
10879 00:40:14.066386 <3>[ 11.303830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 00:40:14.087089 Starting [0;1;39msystemd-udev-trig…[<30>[ 11.321512] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10881 00:40:14.090000 0m - Coldplug All udev Devices...
10882 00:40:14.110283 <3>[ 11.345260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 00:40:14.127152 [[0;32m OK [0m] Mounted [0;<30>[ 11.362129] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10884 00:40:14.130266 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10885 00:40:14.155258 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.<30>[ 11.389521] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10886 00:40:14.165085 mount[…- POSI<3>[ 11.392560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 00:40:14.168523 X Message Queue File System.
10888 00:40:14.186618 <3>[ 11.424523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 00:40:14.193490 <30>[ 11.425040] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10890 00:40:14.203702 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10891 00:40:14.210052 <3>[ 11.445085] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 00:40:14.225019 [[0;32m OK [<30>[ 11.459368] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10893 00:40:14.235258 0m] Finished [0<3>[ 11.467770] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 00:40:14.238417 ;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10895 00:40:14.254222 <3>[ 11.489685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 00:40:14.261063 <30>[ 11.493551] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10897 00:40:14.274685 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<30>[ 11.493944] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10898 00:40:14.278453 onfigfs…[0m - Load Kernel Module configfs.
10899 00:40:14.288011 <3>[ 11.524564] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 00:40:14.303800 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<30>[ 11.536923] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10901 00:40:14.313519 m_mod.s…e[0m <30>[ 11.538009] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10902 00:40:14.313666 - Load Kernel Module dm_mod.
10903 00:40:14.332713 [[0;32m OK [0m] Finished [0<30>[ 11.570193] systemd[1]: modprobe@drm.service: Deactivated successfully.
10904 00:40:14.342999 ;1;39mmodprobe@d<30>[ 11.570620] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10905 00:40:14.346250 rm.service[0m - Load Kernel Module drm.
10906 00:40:14.366313 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 11.601275] systemd[1]: Started systemd-journald.service - Journal Service.
10907 00:40:14.369812 rnald.service[0m - Journal Service.
10908 00:40:14.393474 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10909 00:40:14.412146 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10910 00:40:14.433010 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10911 00:40:14.452128 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10912 00:40:14.472244 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10913 00:40:14.492278 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10914 00:40:14.513402 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10915 00:40:14.567818 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10916 00:40:14.574123 <4>[ 11.810343] power_supply_show_property: 2 callbacks suppressed
10917 00:40:14.580938 <3>[ 11.810356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 00:40:14.597570 <4>[ 11.810371] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10919 00:40:14.604082 <3>[ 11.810374] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10920 00:40:14.614774 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10921 00:40:14.634210 <3>[ 11.869416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 00:40:14.662574 <3>[ 11.899732] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 00:40:14.669084 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10924 00:40:14.694273 <3>[ 11.929107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 00:40:14.700873 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10926 00:40:14.722474 <3>[ 11.959064] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 00:40:14.744715 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10928 00:40:14.754515 <3>[ 11.991524] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 00:40:14.783207 <3>[ 12.020218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 00:40:14.799987 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10931 00:40:14.814191 <3>[ 12.050086] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 00:40:14.831675 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10933 00:40:14.842853 <3>[ 12.079548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 00:40:14.855521 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10935 00:40:14.874245 <3>[ 12.108981] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 00:40:14.884267 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10937 00:40:14.907989 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10938 00:40:14.926376 <46>[ 12.160936] systemd-journald[304]: Received client request to flush runtime journal.
10939 00:40:14.936294 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10940 00:40:14.952214 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10941 00:40:15.004059 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10942 00:40:16.371784 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10943 00:40:16.424824 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10944 00:40:16.443066 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10945 00:40:16.458624 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10946 00:40:16.498991 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10947 00:40:16.526443 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10948 00:40:16.825339 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10949 00:40:16.899229 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10950 00:40:16.941455 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10951 00:40:17.194837 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10952 00:40:17.268454 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10953 00:40:17.274853 <6>[ 14.513330] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10954 00:40:17.301024 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10955 00:40:17.425879 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10956 00:40:17.446837 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10957 00:40:17.466751 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10958 00:40:17.507046 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10959 00:40:17.527138 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10960 00:40:17.563124 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10961 00:40:17.591550 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10962 00:40:17.621904 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Se<46>[ 14.860256] systemd-journald[304]: Time jumped backwards, rotating.
10963 00:40:17.622073 t.
10964 00:40:17.675892 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10965 00:40:17.702447 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10966 00:40:17.720769 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10967 00:40:17.744600 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10968 00:40:18.406538 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10969 00:40:18.734972 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10970 00:40:18.754668 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10971 00:40:19.103751 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10972 00:40:19.130392 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10973 00:40:19.146637 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10974 00:40:19.166553 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10975 00:40:19.185835 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10976 00:40:19.202363 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10977 00:40:19.208863 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10978 00:40:19.263441 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10979 00:40:19.295338 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10980 00:40:19.389939 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10981 00:40:19.412489 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10982 00:40:19.430832 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10983 00:40:19.617998 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10984 00:40:19.671311 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10985 00:40:19.689699 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10986 00:40:19.714377 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10987 00:40:19.730842 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10988 00:40:19.766584 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10989 00:40:19.792611 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10990 00:40:19.816492 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10991 00:40:19.838635 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10992 00:40:19.891954 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10993 00:40:19.941333 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10994 00:40:20.004936
10995 00:40:20.008205 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10996 00:40:20.008313
10997 00:40:20.011297 debian-bookworm-arm64 login: root (automatic login)
10998 00:40:20.011403
10999 00:40:20.344186 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
11000 00:40:20.344329
11001 00:40:20.351019 The programs included with the Debian GNU/Linux system are free software;
11002 00:40:20.357396 the exact distribution terms for each program are described in the
11003 00:40:20.360594 individual files in /usr/share/doc/*/copyright.
11004 00:40:20.360691
11005 00:40:20.367382 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11006 00:40:20.370540 permitted by applicable law.
11007 00:40:21.478471 Matched prompt #10: / #
11009 00:40:21.478769 Setting prompt string to ['/ #']
11010 00:40:21.478863 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11012 00:40:21.479054 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11013 00:40:21.479213 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
11014 00:40:21.479326 Setting prompt string to ['/ #']
11015 00:40:21.479429 Forcing a shell prompt, looking for ['/ #']
11017 00:40:21.529735 / #
11018 00:40:21.529887 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11019 00:40:21.529978 Waiting using forced prompt support (timeout 00:02:30)
11020 00:40:21.534711
11021 00:40:21.534983 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11022 00:40:21.535076 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
11024 00:40:21.635422 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8'
11025 00:40:21.640310 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173454/extract-nfsrootfs-n055v7n8'
11027 00:40:21.740870 / # export NFS_SERVER_IP='192.168.201.1'
11028 00:40:21.745777 export NFS_SERVER_IP='192.168.201.1'
11029 00:40:21.746061 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 00:40:21.746160 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11031 00:40:21.746246 end: 2 depthcharge-action (duration 00:01:36) [common]
11032 00:40:21.746395 start: 3 lava-test-retry (timeout 00:07:41) [common]
11033 00:40:21.746506 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11034 00:40:21.746581 Using namespace: common
11036 00:40:21.846859 / # #
11037 00:40:21.847050 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11038 00:40:21.852091 #
11039 00:40:21.852410 Using /lava-14173454
11041 00:40:21.952857 / # export SHELL=/bin/bash
11042 00:40:21.957816 export SHELL=/bin/bash
11044 00:40:22.058324 / # . /lava-14173454/environment
11045 00:40:22.063873 . /lava-14173454/environment
11047 00:40:22.170194 / # /lava-14173454/bin/lava-test-runner /lava-14173454/0
11048 00:40:22.170370 Test shell timeout: 10s (minimum of the action and connection timeout)
11049 00:40:22.175046 /lava-14173454/bin/lava-test-runner /lava-14173454/0
11050 00:40:22.456806 + export TESTRUN_ID=0_timesync-off
11051 00:40:22.459269 + TESTRUN_ID=0_timesync-off
11052 00:40:22.462551 + cd /lava-14173454/0/tests/0_timesync-off
11053 00:40:22.465722 ++ cat uuid
11054 00:40:22.471847 + UUID=14173454_1.6.2.3.1
11055 00:40:22.471931 + set +x
11056 00:40:22.478296 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14173454_1.6.2.3.1>
11057 00:40:22.478570 Received signal: <STARTRUN> 0_timesync-off 14173454_1.6.2.3.1
11058 00:40:22.478654 Starting test lava.0_timesync-off (14173454_1.6.2.3.1)
11059 00:40:22.478739 Skipping test definition patterns.
11060 00:40:22.480972 + systemctl stop systemd-timesyncd
11061 00:40:22.554328 + set +x
11062 00:40:22.557774 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14173454_1.6.2.3.1>
11063 00:40:22.558035 Received signal: <ENDRUN> 0_timesync-off 14173454_1.6.2.3.1
11064 00:40:22.558120 Ending use of test pattern.
11065 00:40:22.558181 Ending test lava.0_timesync-off (14173454_1.6.2.3.1), duration 0.08
11067 00:40:22.640693 + export TESTRUN_ID=1_kselftest-alsa
11068 00:40:22.643778 + TESTRUN_ID=1_kselftest-alsa
11069 00:40:22.650260 + cd /lava-14173454/0/tests/1_kselftest-alsa
11070 00:40:22.650347 ++ cat uuid
11071 00:40:22.654040 + UUID=14173454_1.6.2.3.5
11072 00:40:22.654124 + set +x
11073 00:40:22.660716 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14173454_1.6.2.3.5>
11074 00:40:22.660987 Received signal: <STARTRUN> 1_kselftest-alsa 14173454_1.6.2.3.5
11075 00:40:22.661064 Starting test lava.1_kselftest-alsa (14173454_1.6.2.3.5)
11076 00:40:22.661175 Skipping test definition patterns.
11077 00:40:22.664040 + cd ./automated/linux/kselftest/
11078 00:40:22.693747 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11079 00:40:22.735635 INFO: install_deps skipped
11080 00:40:23.250726 --2024-06-05 00:40:23-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11081 00:40:23.257389 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11082 00:40:23.377800 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11083 00:40:23.502550 HTTP request sent, awaiting response... 200 OK
11084 00:40:23.505753 Length: 1648104 (1.6M) [application/octet-stream]
11085 00:40:23.509295 Saving to: 'kselftest_armhf.tar.gz'
11086 00:40:23.509427
11087 00:40:23.509552
11088 00:40:23.752177 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11089 00:40:24.002714 kselftest_armhf.tar 2%[ ] 47.81K 192KB/s
11090 00:40:24.252174 kselftest_armhf.tar 13%[=> ] 219.84K 440KB/s
11091 00:40:24.543710 kselftest_armhf.tar 55%[==========> ] 896.25K 1.17MB/s
11092 00:40:24.550461 kselftest_armhf.tar 96%[==================> ] 1.52M 1.46MB/s
11093 00:40:24.556956 kselftest_armhf.tar 100%[===================>] 1.57M 1.51MB/s in 1.0s
11094 00:40:24.557070
11095 00:40:24.697809 2024-06-05 00:40:24 (1.51 MB/s) - 'kselftest_armhf.tar.gz' saved [1648104/1648104]
11096 00:40:24.698022
11097 00:40:29.629172 skiplist:
11098 00:40:29.632349 ========================================
11099 00:40:29.635719 ========================================
11100 00:40:29.688154 alsa:mixer-test
11101 00:40:29.709782 ============== Tests to run ===============
11102 00:40:29.713070 alsa:mixer-test
11103 00:40:29.716418 ===========End Tests to run ===============
11104 00:40:29.719761 shardfile-alsa pass
11105 00:40:29.829124 <12>[ 27.072047] kselftest: Running tests in alsa
11106 00:40:29.837697 TAP version 13
11107 00:40:29.852759 1..1
11108 00:40:29.869411 # selftests: alsa: mixer-test
11109 00:40:30.384880 # TAP version 13
11110 00:40:30.385030 # 1..0
11111 00:40:30.391383 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11112 00:40:30.394950 ok 1 selftests: alsa: mixer-test
11113 00:40:31.904231 alsa_mixer-test pass
11114 00:40:31.982019 + ../../utils/send-to-lava.sh ./output/result.txt
11115 00:40:32.057835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11116 00:40:32.058152 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11118 00:40:32.115178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11119 00:40:32.115287 + set +x
11120 00:40:32.115529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11122 00:40:32.121825 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14173454_1.6.2.3.5>
11123 00:40:32.122079 Received signal: <ENDRUN> 1_kselftest-alsa 14173454_1.6.2.3.5
11124 00:40:32.122153 Ending use of test pattern.
11125 00:40:32.122215 Ending test lava.1_kselftest-alsa (14173454_1.6.2.3.5), duration 9.46
11127 00:40:32.125044 <LAVA_TEST_RUNNER EXIT>
11128 00:40:32.125297 ok: lava_test_shell seems to have completed
11129 00:40:32.125399 alsa_mixer-test: pass
shardfile-alsa: pass
11130 00:40:32.125488 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11131 00:40:32.125570 end: 3 lava-test-retry (duration 00:00:10) [common]
11132 00:40:32.125657 start: 4 finalize (timeout 00:07:30) [common]
11133 00:40:32.125745 start: 4.1 power-off (timeout 00:00:30) [common]
11134 00:40:32.125900 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11135 00:40:32.202307 >> Command sent successfully.
11136 00:40:32.204873 Returned 0 in 0 seconds
11137 00:40:32.305308 end: 4.1 power-off (duration 00:00:00) [common]
11139 00:40:32.305788 start: 4.2 read-feedback (timeout 00:07:30) [common]
11140 00:40:32.306158 Listened to connection for namespace 'common' for up to 1s
11141 00:40:33.307062 Finalising connection for namespace 'common'
11142 00:40:33.307315 Disconnecting from shell: Finalise
11143 00:40:33.307451 / #
11144 00:40:33.407843 end: 4.2 read-feedback (duration 00:00:01) [common]
11145 00:40:33.408097 end: 4 finalize (duration 00:00:01) [common]
11146 00:40:33.408277 Cleaning after the job
11147 00:40:33.408448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/ramdisk
11148 00:40:33.411499 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/kernel
11149 00:40:33.426675 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/dtb
11150 00:40:33.427003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/nfsrootfs
11151 00:40:33.498914 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173454/tftp-deploy-7kc_004t/modules
11152 00:40:33.505396 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173454
11153 00:40:34.110457 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173454
11154 00:40:34.110653 Job finished correctly