Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 44
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 00:37:47.837660 lava-dispatcher, installed at version: 2024.03
2 00:37:47.837880 start: 0 validate
3 00:37:47.838020 Start time: 2024-06-05 00:37:47.838010+00:00 (UTC)
4 00:37:47.838143 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:37:47.838315 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:37:48.097798 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:37:48.097987 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:37:48.356472 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:37:48.357171 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:38:03.492492 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:38:03.493173 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:38:04.007198 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:38:04.008233 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:38:04.280035 validate duration: 16.44
16 00:38:04.281356 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:38:04.281926 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:38:04.282458 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:38:04.283083 Not decompressing ramdisk as can be used compressed.
20 00:38:04.283566 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:38:04.283950 saving as /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/ramdisk/initrd.cpio.gz
22 00:38:04.284321 total size: 5628169 (5 MB)
23 00:38:06.955763 progress 0 % (0 MB)
24 00:38:06.965701 progress 5 % (0 MB)
25 00:38:06.974965 progress 10 % (0 MB)
26 00:38:06.982801 progress 15 % (0 MB)
27 00:38:06.988115 progress 20 % (1 MB)
28 00:38:06.992026 progress 25 % (1 MB)
29 00:38:06.995480 progress 30 % (1 MB)
30 00:38:06.998523 progress 35 % (1 MB)
31 00:38:07.001033 progress 40 % (2 MB)
32 00:38:07.003663 progress 45 % (2 MB)
33 00:38:07.005827 progress 50 % (2 MB)
34 00:38:07.008031 progress 55 % (2 MB)
35 00:38:07.010146 progress 60 % (3 MB)
36 00:38:07.011984 progress 65 % (3 MB)
37 00:38:07.013877 progress 70 % (3 MB)
38 00:38:07.015573 progress 75 % (4 MB)
39 00:38:07.017369 progress 80 % (4 MB)
40 00:38:07.018894 progress 85 % (4 MB)
41 00:38:07.020601 progress 90 % (4 MB)
42 00:38:07.022248 progress 95 % (5 MB)
43 00:38:07.023663 progress 100 % (5 MB)
44 00:38:07.023874 5 MB downloaded in 2.74 s (1.96 MB/s)
45 00:38:07.024028 end: 1.1.1 http-download (duration 00:00:03) [common]
47 00:38:07.024276 end: 1.1 download-retry (duration 00:00:03) [common]
48 00:38:07.024365 start: 1.2 download-retry (timeout 00:09:57) [common]
49 00:38:07.024452 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 00:38:07.024588 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:38:07.024659 saving as /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/kernel/Image
52 00:38:07.024722 total size: 54682112 (52 MB)
53 00:38:07.024787 No compression specified
54 00:38:07.025933 progress 0 % (0 MB)
55 00:38:07.040026 progress 5 % (2 MB)
56 00:38:07.054147 progress 10 % (5 MB)
57 00:38:07.068267 progress 15 % (7 MB)
58 00:38:07.082750 progress 20 % (10 MB)
59 00:38:07.097068 progress 25 % (13 MB)
60 00:38:07.110851 progress 30 % (15 MB)
61 00:38:07.124779 progress 35 % (18 MB)
62 00:38:07.138789 progress 40 % (20 MB)
63 00:38:07.152950 progress 45 % (23 MB)
64 00:38:07.167146 progress 50 % (26 MB)
65 00:38:07.181000 progress 55 % (28 MB)
66 00:38:07.194974 progress 60 % (31 MB)
67 00:38:07.209214 progress 65 % (33 MB)
68 00:38:07.223220 progress 70 % (36 MB)
69 00:38:07.237146 progress 75 % (39 MB)
70 00:38:07.251174 progress 80 % (41 MB)
71 00:38:07.265222 progress 85 % (44 MB)
72 00:38:07.279124 progress 90 % (46 MB)
73 00:38:07.292913 progress 95 % (49 MB)
74 00:38:07.306614 progress 100 % (52 MB)
75 00:38:07.306872 52 MB downloaded in 0.28 s (184.83 MB/s)
76 00:38:07.307028 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:38:07.307266 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:38:07.307355 start: 1.3 download-retry (timeout 00:09:57) [common]
80 00:38:07.307441 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 00:38:07.307582 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:38:07.307655 saving as /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/dtb/mt8192-asurada-spherion-r0.dtb
83 00:38:07.307718 total size: 47258 (0 MB)
84 00:38:07.307780 No compression specified
85 00:38:07.308914 progress 69 % (0 MB)
86 00:38:07.309207 progress 100 % (0 MB)
87 00:38:07.309365 0 MB downloaded in 0.00 s (27.40 MB/s)
88 00:38:07.309490 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:38:07.309712 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:38:07.309799 start: 1.4 download-retry (timeout 00:09:57) [common]
92 00:38:07.309883 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 00:38:07.309999 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:38:07.310068 saving as /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/nfsrootfs/full.rootfs.tar
95 00:38:07.310130 total size: 120894716 (115 MB)
96 00:38:07.310246 Using unxz to decompress xz
97 00:38:07.314325 progress 0 % (0 MB)
98 00:38:07.668438 progress 5 % (5 MB)
99 00:38:08.039144 progress 10 % (11 MB)
100 00:38:08.392321 progress 15 % (17 MB)
101 00:38:08.719849 progress 20 % (23 MB)
102 00:38:09.013947 progress 25 % (28 MB)
103 00:38:09.376732 progress 30 % (34 MB)
104 00:38:09.717670 progress 35 % (40 MB)
105 00:38:09.890422 progress 40 % (46 MB)
106 00:38:10.073591 progress 45 % (51 MB)
107 00:38:10.389692 progress 50 % (57 MB)
108 00:38:10.771990 progress 55 % (63 MB)
109 00:38:11.118529 progress 60 % (69 MB)
110 00:38:11.460288 progress 65 % (74 MB)
111 00:38:11.808227 progress 70 % (80 MB)
112 00:38:12.167644 progress 75 % (86 MB)
113 00:38:12.512170 progress 80 % (92 MB)
114 00:38:12.857356 progress 85 % (98 MB)
115 00:38:13.218456 progress 90 % (103 MB)
116 00:38:13.555148 progress 95 % (109 MB)
117 00:38:13.922644 progress 100 % (115 MB)
118 00:38:13.928372 115 MB downloaded in 6.62 s (17.42 MB/s)
119 00:38:13.928715 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:38:13.929002 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:38:13.929097 start: 1.5 download-retry (timeout 00:09:50) [common]
123 00:38:13.929184 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 00:38:13.929331 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:38:13.929408 saving as /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/modules/modules.tar
126 00:38:13.929472 total size: 8605984 (8 MB)
127 00:38:13.929537 Using unxz to decompress xz
128 00:38:13.934239 progress 0 % (0 MB)
129 00:38:13.953925 progress 5 % (0 MB)
130 00:38:13.982133 progress 10 % (0 MB)
131 00:38:14.013801 progress 15 % (1 MB)
132 00:38:14.038473 progress 20 % (1 MB)
133 00:38:14.064271 progress 25 % (2 MB)
134 00:38:14.091295 progress 30 % (2 MB)
135 00:38:14.118257 progress 35 % (2 MB)
136 00:38:14.146916 progress 40 % (3 MB)
137 00:38:14.171189 progress 45 % (3 MB)
138 00:38:14.196356 progress 50 % (4 MB)
139 00:38:14.222117 progress 55 % (4 MB)
140 00:38:14.248111 progress 60 % (4 MB)
141 00:38:14.274466 progress 65 % (5 MB)
142 00:38:14.301939 progress 70 % (5 MB)
143 00:38:14.327759 progress 75 % (6 MB)
144 00:38:14.357121 progress 80 % (6 MB)
145 00:38:14.382510 progress 85 % (7 MB)
146 00:38:14.408601 progress 90 % (7 MB)
147 00:38:14.434431 progress 95 % (7 MB)
148 00:38:14.460170 progress 100 % (8 MB)
149 00:38:14.465718 8 MB downloaded in 0.54 s (15.31 MB/s)
150 00:38:14.466021 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:38:14.466359 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:38:14.466467 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 00:38:14.466565 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 00:38:17.895347 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf
156 00:38:17.895560 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:38:17.895660 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 00:38:17.895822 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud
159 00:38:17.895953 makedir: /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin
160 00:38:17.896054 makedir: /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/tests
161 00:38:17.896155 makedir: /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/results
162 00:38:17.896256 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-add-keys
163 00:38:17.896397 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-add-sources
164 00:38:17.896526 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-background-process-start
165 00:38:17.896654 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-background-process-stop
166 00:38:17.896791 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-common-functions
167 00:38:17.896918 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-echo-ipv4
168 00:38:17.897046 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-install-packages
169 00:38:17.897170 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-installed-packages
170 00:38:17.897294 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-os-build
171 00:38:17.897419 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-probe-channel
172 00:38:17.897544 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-probe-ip
173 00:38:17.897668 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-target-ip
174 00:38:17.897793 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-target-mac
175 00:38:17.897917 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-target-storage
176 00:38:17.898045 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-case
177 00:38:17.898194 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-event
178 00:38:17.899140 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-feedback
179 00:38:17.899269 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-raise
180 00:38:17.899393 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-reference
181 00:38:17.899517 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-runner
182 00:38:17.899641 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-set
183 00:38:17.899768 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-test-shell
184 00:38:17.899894 Updating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-add-keys (debian)
185 00:38:17.900087 Updating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-add-sources (debian)
186 00:38:17.900230 Updating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-install-packages (debian)
187 00:38:17.900398 Updating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-installed-packages (debian)
188 00:38:17.900535 Updating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/bin/lava-os-build (debian)
189 00:38:17.900656 Creating /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/environment
190 00:38:17.900754 LAVA metadata
191 00:38:17.900822 - LAVA_JOB_ID=14173479
192 00:38:17.900885 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:38:17.900995 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 00:38:17.901064 skipped lava-vland-overlay
195 00:38:17.901139 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:38:17.901221 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 00:38:17.901282 skipped lava-multinode-overlay
198 00:38:17.901354 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:38:17.901432 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 00:38:17.901507 Loading test definitions
201 00:38:17.901600 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 00:38:17.901671 Using /lava-14173479 at stage 0
203 00:38:17.901957 uuid=14173479_1.6.2.3.1 testdef=None
204 00:38:17.902046 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:38:17.902130 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 00:38:17.902640 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:38:17.902886 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 00:38:17.903449 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:38:17.903682 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 00:38:17.909821 runner path: /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/0/tests/0_timesync-off test_uuid 14173479_1.6.2.3.1
213 00:38:17.910038 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:38:17.910305 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 00:38:17.910383 Using /lava-14173479 at stage 0
217 00:38:17.910485 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:38:17.910575 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/0/tests/1_kselftest-dt'
219 00:38:21.464499 Running '/usr/bin/git checkout kernelci.org
220 00:38:21.613608 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 00:38:21.614398 uuid=14173479_1.6.2.3.5 testdef=None
222 00:38:21.614563 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 00:38:21.614812 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 00:38:21.615567 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:38:21.615800 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 00:38:21.616806 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:38:21.617052 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 00:38:21.618068 runner path: /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/0/tests/1_kselftest-dt test_uuid 14173479_1.6.2.3.5
232 00:38:21.618186 BOARD='mt8192-asurada-spherion-r0'
233 00:38:21.618267 BRANCH='cip-gitlab'
234 00:38:21.618328 SKIPFILE='/dev/null'
235 00:38:21.618387 SKIP_INSTALL='True'
236 00:38:21.618444 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:38:21.618504 TST_CASENAME=''
238 00:38:21.618560 TST_CMDFILES='dt'
239 00:38:21.618702 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:38:21.618912 Creating lava-test-runner.conf files
242 00:38:21.618977 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173479/lava-overlay-av1s4qud/lava-14173479/0 for stage 0
243 00:38:21.619071 - 0_timesync-off
244 00:38:21.619141 - 1_kselftest-dt
245 00:38:21.619237 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 00:38:21.619327 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 00:38:29.113069 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:38:29.113228 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 00:38:29.113319 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:38:29.113414 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 00:38:29.113500 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 00:38:29.278459 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:38:29.278855 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 00:38:29.278973 extracting modules file /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf
255 00:38:29.494732 extracting modules file /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173479/extract-overlay-ramdisk-zs5_2wtr/ramdisk
256 00:38:29.713676 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:38:29.713849 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 00:38:29.713945 [common] Applying overlay to NFS
259 00:38:29.714018 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173479/compress-overlay-c7sfw87b/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf
260 00:38:30.634498 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:38:30.634674 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 00:38:30.634772 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:38:30.634865 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 00:38:30.634990 Building ramdisk /var/lib/lava/dispatcher/tmp/14173479/extract-overlay-ramdisk-zs5_2wtr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173479/extract-overlay-ramdisk-zs5_2wtr/ramdisk
265 00:38:31.088326 >> 130348 blocks
266 00:38:33.109747 rename /var/lib/lava/dispatcher/tmp/14173479/extract-overlay-ramdisk-zs5_2wtr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/ramdisk/ramdisk.cpio.gz
267 00:38:33.110256 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:38:33.110386 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 00:38:33.110486 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 00:38:33.110593 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/kernel/Image']
271 00:38:47.429948 Returned 0 in 14 seconds
272 00:38:47.530661 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/kernel/image.itb
273 00:38:47.889530 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:38:47.889906 output: Created: Wed Jun 5 01:38:47 2024
275 00:38:47.889979 output: Image 0 (kernel-1)
276 00:38:47.890048 output: Description:
277 00:38:47.890117 output: Created: Wed Jun 5 01:38:47 2024
278 00:38:47.890240 output: Type: Kernel Image
279 00:38:47.890305 output: Compression: lzma compressed
280 00:38:47.890366 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
281 00:38:47.890428 output: Architecture: AArch64
282 00:38:47.890501 output: OS: Linux
283 00:38:47.890571 output: Load Address: 0x00000000
284 00:38:47.890652 output: Entry Point: 0x00000000
285 00:38:47.890709 output: Hash algo: crc32
286 00:38:47.890792 output: Hash value: 4c96ec19
287 00:38:47.890856 output: Image 1 (fdt-1)
288 00:38:47.890927 output: Description: mt8192-asurada-spherion-r0
289 00:38:47.891000 output: Created: Wed Jun 5 01:38:47 2024
290 00:38:47.891100 output: Type: Flat Device Tree
291 00:38:47.891154 output: Compression: uncompressed
292 00:38:47.891206 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:38:47.891284 output: Architecture: AArch64
294 00:38:47.891339 output: Hash algo: crc32
295 00:38:47.891393 output: Hash value: 0f8e4d2e
296 00:38:47.891458 output: Image 2 (ramdisk-1)
297 00:38:47.891511 output: Description: unavailable
298 00:38:47.891573 output: Created: Wed Jun 5 01:38:47 2024
299 00:38:47.891628 output: Type: RAMDisk Image
300 00:38:47.891680 output: Compression: Unknown Compression
301 00:38:47.891732 output: Data Size: 18731676 Bytes = 18292.65 KiB = 17.86 MiB
302 00:38:47.891786 output: Architecture: AArch64
303 00:38:47.891838 output: OS: Linux
304 00:38:47.891890 output: Load Address: unavailable
305 00:38:47.891941 output: Entry Point: unavailable
306 00:38:47.891994 output: Hash algo: crc32
307 00:38:47.892045 output: Hash value: defae9b7
308 00:38:47.892097 output: Default Configuration: 'conf-1'
309 00:38:47.892149 output: Configuration 0 (conf-1)
310 00:38:47.892201 output: Description: mt8192-asurada-spherion-r0
311 00:38:47.892253 output: Kernel: kernel-1
312 00:38:47.892304 output: Init Ramdisk: ramdisk-1
313 00:38:47.892355 output: FDT: fdt-1
314 00:38:47.892438 output: Loadables: kernel-1
315 00:38:47.892489 output:
316 00:38:47.892801 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 00:38:47.892950 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 00:38:47.893098 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 00:38:47.893226 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 00:38:47.893310 No LXC device requested
321 00:38:47.893391 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:38:47.893482 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 00:38:47.893564 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:38:47.893640 Checking files for TFTP limit of 4294967296 bytes.
325 00:38:47.894154 end: 1 tftp-deploy (duration 00:00:44) [common]
326 00:38:47.894301 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:38:47.894391 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:38:47.894627 substitutions:
329 00:38:47.894698 - {DTB}: 14173479/tftp-deploy-dv0tiued/dtb/mt8192-asurada-spherion-r0.dtb
330 00:38:47.894770 - {INITRD}: 14173479/tftp-deploy-dv0tiued/ramdisk/ramdisk.cpio.gz
331 00:38:47.894851 - {KERNEL}: 14173479/tftp-deploy-dv0tiued/kernel/Image
332 00:38:47.894945 - {LAVA_MAC}: None
333 00:38:47.895034 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf
334 00:38:47.895202 - {NFS_SERVER_IP}: 192.168.201.1
335 00:38:47.895291 - {PRESEED_CONFIG}: None
336 00:38:47.895377 - {PRESEED_LOCAL}: None
337 00:38:47.895462 - {RAMDISK}: 14173479/tftp-deploy-dv0tiued/ramdisk/ramdisk.cpio.gz
338 00:38:47.895563 - {ROOT_PART}: None
339 00:38:47.895642 - {ROOT}: None
340 00:38:47.895698 - {SERVER_IP}: 192.168.201.1
341 00:38:47.895752 - {TEE}: None
342 00:38:47.895806 Parsed boot commands:
343 00:38:47.895877 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:38:47.896114 Parsed boot commands: tftpboot 192.168.201.1 14173479/tftp-deploy-dv0tiued/kernel/image.itb 14173479/tftp-deploy-dv0tiued/kernel/cmdline
345 00:38:47.896293 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:38:47.896426 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:38:47.896584 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:38:47.896772 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:38:47.896882 Not connected, no need to disconnect.
350 00:38:47.896994 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:38:47.897111 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:38:47.897208 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 00:38:47.902045 Setting prompt string to ['lava-test: # ']
354 00:38:47.902669 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:38:47.902872 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:38:47.903042 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:38:47.903193 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:38:47.903475 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 00:39:01.920214 Returned 0 in 14 seconds
360 00:39:02.021395 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:39:02.022964 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:39:02.023515 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:39:02.023999 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:39:02.024380 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:39:02.024720 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:39:02.026797 [Enter `^Ec?' for help]
368 00:39:02.027238
369 00:39:02.027586 F0: 102B 0000
370 00:39:02.027927
371 00:39:02.028255 F3: 1001 0000 [0200]
372 00:39:02.028566
373 00:39:02.028884 F3: 1001 0000
374 00:39:02.029191
375 00:39:02.029492 F7: 102D 0000
376 00:39:02.029793
377 00:39:02.030079 F1: 0000 0000
378 00:39:02.030448
379 00:39:02.030735 V0: 0000 0000 [0001]
380 00:39:02.031014
381 00:39:02.031291 00: 0007 8000
382 00:39:02.031589
383 00:39:02.031866 01: 0000 0000
384 00:39:02.032151
385 00:39:02.032430 BP: 0C00 0209 [0000]
386 00:39:02.032707
387 00:39:02.033000 G0: 1182 0000
388 00:39:02.033291
389 00:39:02.033568 EC: 0000 0021 [4000]
390 00:39:02.033846
391 00:39:02.034117 S7: 0000 0000 [0000]
392 00:39:02.034436
393 00:39:02.034715 CC: 0000 0000 [0001]
394 00:39:02.034990
395 00:39:02.035263 T0: 0000 0040 [010F]
396 00:39:02.035540
397 00:39:02.035812 Jump to BL
398 00:39:02.036084
399 00:39:02.036354
400 00:39:02.036659
401 00:39:02.036938 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
402 00:39:02.037302 ARM64: Exception handlers installed.
403 00:39:02.037598 ARM64: Testing exception
404 00:39:02.037877 ARM64: Done test exception
405 00:39:02.038329 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
406 00:39:02.038634 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
407 00:39:02.038924 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
408 00:39:02.039206 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
409 00:39:02.039541 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
410 00:39:02.039854 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
411 00:39:02.040147 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
412 00:39:02.040460 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
413 00:39:02.040749 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
414 00:39:02.041033 WDT: Last reset was cold boot
415 00:39:02.041311 SPI1(PAD0) initialized at 2873684 Hz
416 00:39:02.041590 SPI5(PAD0) initialized at 992727 Hz
417 00:39:02.041868 VBOOT: Loading verstage.
418 00:39:02.042146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
419 00:39:02.042506 FMAP: Found "FLASH" version 1.1 at 0x20000.
420 00:39:02.042794 FMAP: base = 0x0 size = 0x800000 #areas = 25
421 00:39:02.043096 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
422 00:39:02.043387 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
423 00:39:02.043672 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
424 00:39:02.043951 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
425 00:39:02.044232
426 00:39:02.044508
427 00:39:02.044783 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
428 00:39:02.045065 ARM64: Exception handlers installed.
429 00:39:02.045343 ARM64: Testing exception
430 00:39:02.045616 ARM64: Done test exception
431 00:39:02.045892 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
432 00:39:02.046194 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
433 00:39:02.046490 Probing TPM: . done!
434 00:39:02.046769 TPM ready after 0 ms
435 00:39:02.047072 Connected to device vid:did:rid of 1ae0:0028:00
436 00:39:02.047351 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
437 00:39:02.047632 Initialized TPM device CR50 revision 0
438 00:39:02.047910 tlcl_send_startup: Startup return code is 0
439 00:39:02.048189 TPM: setup succeeded
440 00:39:02.048467 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
441 00:39:02.048743 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
442 00:39:02.049021 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
443 00:39:02.049302 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 00:39:02.049501 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
445 00:39:02.049701 in-header: 03 07 00 00 08 00 00 00
446 00:39:02.049923 in-data: aa e4 47 04 13 02 00 00
447 00:39:02.050126 Chrome EC: UHEPI supported
448 00:39:02.050388 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
449 00:39:02.050595 in-header: 03 a9 00 00 08 00 00 00
450 00:39:02.050793 in-data: 84 60 60 08 00 00 00 00
451 00:39:02.050990 Phase 1
452 00:39:02.051188 FMAP: area GBB found @ 3f5000 (12032 bytes)
453 00:39:02.051393 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
454 00:39:02.051593 VB2:vb2_check_recovery() Recovery was requested manually
455 00:39:02.051795 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
456 00:39:02.051997 Recovery requested (1009000e)
457 00:39:02.052196 TPM: Extending digest for VBOOT: boot mode into PCR 0
458 00:39:02.052395 tlcl_extend: response is 0
459 00:39:02.052595 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
460 00:39:02.052794 tlcl_extend: response is 0
461 00:39:02.053016 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
462 00:39:02.053217 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
463 00:39:02.053448 BS: bootblock times (exec / console): total (unknown) / 148 ms
464 00:39:02.053659
465 00:39:02.053856
466 00:39:02.054055 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
467 00:39:02.054311 ARM64: Exception handlers installed.
468 00:39:02.054554 ARM64: Testing exception
469 00:39:02.054760 ARM64: Done test exception
470 00:39:02.054916 pmic_efuse_setting: Set efuses in 11 msecs
471 00:39:02.055068 pmwrap_interface_init: Select PMIF_VLD_RDY
472 00:39:02.055219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
473 00:39:02.055645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
474 00:39:02.055978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
475 00:39:02.056315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
476 00:39:02.056635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
477 00:39:02.056877 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
478 00:39:02.057114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
479 00:39:02.057349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
480 00:39:02.057582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
481 00:39:02.057815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
482 00:39:02.058047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
483 00:39:02.058307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
484 00:39:02.058542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
485 00:39:02.058774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
486 00:39:02.059028 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
487 00:39:02.059278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
488 00:39:02.059466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
489 00:39:02.059654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
490 00:39:02.059841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
491 00:39:02.060028 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
492 00:39:02.060215 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
493 00:39:02.060403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
494 00:39:02.060590 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
495 00:39:02.060776 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
496 00:39:02.060963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
497 00:39:02.061150 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
498 00:39:02.061336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
499 00:39:02.061509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
500 00:39:02.061634 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
501 00:39:02.061754 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
502 00:39:02.061875 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
503 00:39:02.061994 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
504 00:39:02.062114 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
505 00:39:02.062254 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
506 00:39:02.062376 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
507 00:39:02.062496 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
508 00:39:02.062617 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
509 00:39:02.062738 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
510 00:39:02.062856 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
511 00:39:02.062975 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
512 00:39:02.063094 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
513 00:39:02.063214 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
514 00:39:02.063332 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
515 00:39:02.063452 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
516 00:39:02.063570 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
517 00:39:02.063689 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
518 00:39:02.063807 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
519 00:39:02.063926 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
520 00:39:02.064046 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
521 00:39:02.064165 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
522 00:39:02.064291 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
523 00:39:02.064393 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
524 00:39:02.064495 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
525 00:39:02.064596 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
526 00:39:02.064696 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
527 00:39:02.064798 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
528 00:39:02.064899 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
529 00:39:02.064998 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
530 00:39:02.065098 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:39:02.065199 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
532 00:39:02.065299 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
533 00:39:02.065399 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
534 00:39:02.065499 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
535 00:39:02.065598 [RTC]rtc_get_frequency_meter,154: input=15, output=835
536 00:39:02.065697 [RTC]rtc_get_frequency_meter,154: input=7, output=709
537 00:39:02.065797 [RTC]rtc_get_frequency_meter,154: input=11, output=773
538 00:39:02.065897 [RTC]rtc_get_frequency_meter,154: input=13, output=804
539 00:39:02.065997 [RTC]rtc_get_frequency_meter,154: input=12, output=788
540 00:39:02.066096 [RTC]rtc_get_frequency_meter,154: input=12, output=788
541 00:39:02.066293 [RTC]rtc_get_frequency_meter,154: input=13, output=804
542 00:39:02.066437 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
543 00:39:02.066780 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
544 00:39:02.066907 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
545 00:39:02.067022 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
546 00:39:02.067134 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
547 00:39:02.067241 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
548 00:39:02.067348 ADC[4]: Raw value=901552 ID=7
549 00:39:02.067454 ADC[3]: Raw value=213652 ID=1
550 00:39:02.067558 RAM Code: 0x71
551 00:39:02.067662 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
552 00:39:02.067767 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
553 00:39:02.067872 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
554 00:39:02.067976 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
555 00:39:02.068079 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
556 00:39:02.068182 in-header: 03 07 00 00 08 00 00 00
557 00:39:02.068284 in-data: aa e4 47 04 13 02 00 00
558 00:39:02.068385 Chrome EC: UHEPI supported
559 00:39:02.068487 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
560 00:39:02.068590 in-header: 03 a9 00 00 08 00 00 00
561 00:39:02.068691 in-data: 84 60 60 08 00 00 00 00
562 00:39:02.068792 MRC: failed to locate region type 0.
563 00:39:02.068893 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
564 00:39:02.068995 DRAM-K: Running full calibration
565 00:39:02.069096 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
566 00:39:02.069199 header.status = 0x0
567 00:39:02.069313 header.version = 0x6 (expected: 0x6)
568 00:39:02.069400 header.size = 0xd00 (expected: 0xd00)
569 00:39:02.069487 header.flags = 0x0
570 00:39:02.069573 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
571 00:39:02.069703 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
572 00:39:02.069796 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
573 00:39:02.069885 dram_init: ddr_geometry: 2
574 00:39:02.069972 [EMI] MDL number = 2
575 00:39:02.070060 [EMI] Get MDL freq = 0
576 00:39:02.070146 dram_init: ddr_type: 0
577 00:39:02.070241 is_discrete_lpddr4: 1
578 00:39:02.070328 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
579 00:39:02.070415
580 00:39:02.070501
581 00:39:02.070587 [Bian_co] ETT version 0.0.0.1
582 00:39:02.070675 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
583 00:39:02.070762
584 00:39:02.070848 dramc_set_vcore_voltage set vcore to 650000
585 00:39:02.070935 Read voltage for 800, 4
586 00:39:02.071022 Vio18 = 0
587 00:39:02.071109 Vcore = 650000
588 00:39:02.071195 Vdram = 0
589 00:39:02.071282 Vddq = 0
590 00:39:02.071368 Vmddr = 0
591 00:39:02.071453 dram_init: config_dvfs: 1
592 00:39:02.071541 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
593 00:39:02.071628 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
594 00:39:02.071716 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
595 00:39:02.071804 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
596 00:39:02.071891 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
597 00:39:02.071979 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
598 00:39:02.072067 MEM_TYPE=3, freq_sel=18
599 00:39:02.072156 sv_algorithm_assistance_LP4_1600
600 00:39:02.072242 ============ PULL DRAM RESETB DOWN ============
601 00:39:02.072330 ========== PULL DRAM RESETB DOWN end =========
602 00:39:02.072417 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
603 00:39:02.072504 ===================================
604 00:39:02.072590 LPDDR4 DRAM CONFIGURATION
605 00:39:02.072677 ===================================
606 00:39:02.072764 EX_ROW_EN[0] = 0x0
607 00:39:02.072850 EX_ROW_EN[1] = 0x0
608 00:39:02.072976 LP4Y_EN = 0x0
609 00:39:02.073067 WORK_FSP = 0x0
610 00:39:02.073154 WL = 0x2
611 00:39:02.073241 RL = 0x2
612 00:39:02.073328 BL = 0x2
613 00:39:02.073415 RPST = 0x0
614 00:39:02.073500 RD_PRE = 0x0
615 00:39:02.073585 WR_PRE = 0x1
616 00:39:02.073672 WR_PST = 0x0
617 00:39:02.073757 DBI_WR = 0x0
618 00:39:02.073842 DBI_RD = 0x0
619 00:39:02.073927 OTF = 0x1
620 00:39:02.074013 ===================================
621 00:39:02.074100 ===================================
622 00:39:02.074200 ANA top config
623 00:39:02.074290 ===================================
624 00:39:02.074381 DLL_ASYNC_EN = 0
625 00:39:02.074457 ALL_SLAVE_EN = 1
626 00:39:02.074532 NEW_RANK_MODE = 1
627 00:39:02.074612 DLL_IDLE_MODE = 1
628 00:39:02.074688 LP45_APHY_COMB_EN = 1
629 00:39:02.074765 TX_ODT_DIS = 1
630 00:39:02.074841 NEW_8X_MODE = 1
631 00:39:02.074917 ===================================
632 00:39:02.074993 ===================================
633 00:39:02.075069 data_rate = 1600
634 00:39:02.075145 CKR = 1
635 00:39:02.075221 DQ_P2S_RATIO = 8
636 00:39:02.075297 ===================================
637 00:39:02.075373 CA_P2S_RATIO = 8
638 00:39:02.075449 DQ_CA_OPEN = 0
639 00:39:02.075525 DQ_SEMI_OPEN = 0
640 00:39:02.075600 CA_SEMI_OPEN = 0
641 00:39:02.075676 CA_FULL_RATE = 0
642 00:39:02.075751 DQ_CKDIV4_EN = 1
643 00:39:02.075827 CA_CKDIV4_EN = 1
644 00:39:02.075902 CA_PREDIV_EN = 0
645 00:39:02.075982 PH8_DLY = 0
646 00:39:02.076082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
647 00:39:02.076159 DQ_AAMCK_DIV = 4
648 00:39:02.076235 CA_AAMCK_DIV = 4
649 00:39:02.076310 CA_ADMCK_DIV = 4
650 00:39:02.076386 DQ_TRACK_CA_EN = 0
651 00:39:02.076461 CA_PICK = 800
652 00:39:02.076536 CA_MCKIO = 800
653 00:39:02.076612 MCKIO_SEMI = 0
654 00:39:02.076687 PLL_FREQ = 3068
655 00:39:02.076762 DQ_UI_PI_RATIO = 32
656 00:39:02.076838 CA_UI_PI_RATIO = 0
657 00:39:02.076913 ===================================
658 00:39:02.076990 ===================================
659 00:39:02.077066 memory_type:LPDDR4
660 00:39:02.077141 GP_NUM : 10
661 00:39:02.077217 SRAM_EN : 1
662 00:39:02.077292 MD32_EN : 0
663 00:39:02.077598 ===================================
664 00:39:02.077685 [ANA_INIT] >>>>>>>>>>>>>>
665 00:39:02.077762 <<<<<< [CONFIGURE PHASE]: ANA_TX
666 00:39:02.077842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
667 00:39:02.077918 ===================================
668 00:39:02.077994 data_rate = 1600,PCW = 0X7600
669 00:39:02.078070 ===================================
670 00:39:02.078146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
671 00:39:02.078235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 00:39:02.078313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:39:02.078390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
674 00:39:02.078467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
675 00:39:02.078542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:39:02.078618 [ANA_INIT] flow start
677 00:39:02.078694 [ANA_INIT] PLL >>>>>>>>
678 00:39:02.078769 [ANA_INIT] PLL <<<<<<<<
679 00:39:02.078844 [ANA_INIT] MIDPI >>>>>>>>
680 00:39:02.078920 [ANA_INIT] MIDPI <<<<<<<<
681 00:39:02.078996 [ANA_INIT] DLL >>>>>>>>
682 00:39:02.079071 [ANA_INIT] flow end
683 00:39:02.079147 ============ LP4 DIFF to SE enter ============
684 00:39:02.079224 ============ LP4 DIFF to SE exit ============
685 00:39:02.079332 [ANA_INIT] <<<<<<<<<<<<<
686 00:39:02.079410 [Flow] Enable top DCM control >>>>>
687 00:39:02.079487 [Flow] Enable top DCM control <<<<<
688 00:39:02.079563 Enable DLL master slave shuffle
689 00:39:02.079639 ==============================================================
690 00:39:02.079716 Gating Mode config
691 00:39:02.079793 ==============================================================
692 00:39:02.079869 Config description:
693 00:39:02.079945 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
694 00:39:02.080023 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
695 00:39:02.080101 SELPH_MODE 0: By rank 1: By Phase
696 00:39:02.080178 ==============================================================
697 00:39:02.080253 GAT_TRACK_EN = 1
698 00:39:02.080329 RX_GATING_MODE = 2
699 00:39:02.080404 RX_GATING_TRACK_MODE = 2
700 00:39:02.080480 SELPH_MODE = 1
701 00:39:02.080554 PICG_EARLY_EN = 1
702 00:39:02.080630 VALID_LAT_VALUE = 1
703 00:39:02.080706 ==============================================================
704 00:39:02.080783 Enter into Gating configuration >>>>
705 00:39:02.080858 Exit from Gating configuration <<<<
706 00:39:02.080933 Enter into DVFS_PRE_config >>>>>
707 00:39:02.081010 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
708 00:39:02.081091 Exit from DVFS_PRE_config <<<<<
709 00:39:02.081168 Enter into PICG configuration >>>>
710 00:39:02.081243 Exit from PICG configuration <<<<
711 00:39:02.081319 [RX_INPUT] configuration >>>>>
712 00:39:02.081395 [RX_INPUT] configuration <<<<<
713 00:39:02.081471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
714 00:39:02.081546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
715 00:39:02.081623 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
716 00:39:02.081699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
717 00:39:02.081775 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
718 00:39:02.081851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
719 00:39:02.081927 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
720 00:39:02.082003 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
721 00:39:02.082079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
722 00:39:02.082154 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
723 00:39:02.082242 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
724 00:39:02.082318 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
725 00:39:02.082394 ===================================
726 00:39:02.082471 LPDDR4 DRAM CONFIGURATION
727 00:39:02.082546 ===================================
728 00:39:02.082622 EX_ROW_EN[0] = 0x0
729 00:39:02.082720 EX_ROW_EN[1] = 0x0
730 00:39:02.082802 LP4Y_EN = 0x0
731 00:39:02.082878 WORK_FSP = 0x0
732 00:39:02.082954 WL = 0x2
733 00:39:02.083030 RL = 0x2
734 00:39:02.083105 BL = 0x2
735 00:39:02.083180 RPST = 0x0
736 00:39:02.083255 RD_PRE = 0x0
737 00:39:02.083330 WR_PRE = 0x1
738 00:39:02.083405 WR_PST = 0x0
739 00:39:02.083479 DBI_WR = 0x0
740 00:39:02.083554 DBI_RD = 0x0
741 00:39:02.083630 OTF = 0x1
742 00:39:02.083706 ===================================
743 00:39:02.083781 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
744 00:39:02.083857 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
745 00:39:02.083933 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
746 00:39:02.084009 ===================================
747 00:39:02.084085 LPDDR4 DRAM CONFIGURATION
748 00:39:02.084161 ===================================
749 00:39:02.084236 EX_ROW_EN[0] = 0x10
750 00:39:02.084311 EX_ROW_EN[1] = 0x0
751 00:39:02.084386 LP4Y_EN = 0x0
752 00:39:02.084462 WORK_FSP = 0x0
753 00:39:02.084538 WL = 0x2
754 00:39:02.084612 RL = 0x2
755 00:39:02.084687 BL = 0x2
756 00:39:02.084762 RPST = 0x0
757 00:39:02.084837 RD_PRE = 0x0
758 00:39:02.084910 WR_PRE = 0x1
759 00:39:02.084985 WR_PST = 0x0
760 00:39:02.085060 DBI_WR = 0x0
761 00:39:02.085135 DBI_RD = 0x0
762 00:39:02.085209 OTF = 0x1
763 00:39:02.085285 ===================================
764 00:39:02.085360 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
765 00:39:02.085436 nWR fixed to 40
766 00:39:02.085512 [ModeRegInit_LP4] CH0 RK0
767 00:39:02.085586 [ModeRegInit_LP4] CH0 RK1
768 00:39:02.085661 [ModeRegInit_LP4] CH1 RK0
769 00:39:02.085736 [ModeRegInit_LP4] CH1 RK1
770 00:39:02.085843 match AC timing 13
771 00:39:02.086132 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
772 00:39:02.086235 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
773 00:39:02.086316 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
774 00:39:02.086395 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
775 00:39:02.086473 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
776 00:39:02.086550 [EMI DOE] emi_dcm 0
777 00:39:02.086627 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
778 00:39:02.086703 ==
779 00:39:02.086781 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:39:02.086856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:39:02.086934 ==
782 00:39:02.087010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 00:39:02.087087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 00:39:02.087165 [CA 0] Center 37 (6~68) winsize 63
785 00:39:02.087241 [CA 1] Center 37 (6~68) winsize 63
786 00:39:02.087318 [CA 2] Center 34 (4~65) winsize 62
787 00:39:02.087394 [CA 3] Center 34 (4~65) winsize 62
788 00:39:02.087471 [CA 4] Center 33 (3~64) winsize 62
789 00:39:02.087547 [CA 5] Center 33 (3~64) winsize 62
790 00:39:02.087623
791 00:39:02.087698 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 00:39:02.087774
793 00:39:02.087850 [CATrainingPosCal] consider 1 rank data
794 00:39:02.087926 u2DelayCellTimex100 = 270/100 ps
795 00:39:02.088001 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
796 00:39:02.088078 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
797 00:39:02.088153 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:39:02.088229 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:39:02.088304 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:39:02.088380 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 00:39:02.088456
802 00:39:02.088531 CA PerBit enable=1, Macro0, CA PI delay=33
803 00:39:02.088606
804 00:39:02.088680 [CBTSetCACLKResult] CA Dly = 33
805 00:39:02.088755 CS Dly: 6 (0~37)
806 00:39:02.088830 ==
807 00:39:02.088905 Dram Type= 6, Freq= 0, CH_0, rank 1
808 00:39:02.088980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
809 00:39:02.089083 ==
810 00:39:02.089160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
811 00:39:02.089236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
812 00:39:02.089312 [CA 0] Center 37 (6~68) winsize 63
813 00:39:02.089417 [CA 1] Center 37 (7~68) winsize 62
814 00:39:02.089498 [CA 2] Center 34 (4~65) winsize 62
815 00:39:02.089575 [CA 3] Center 34 (4~65) winsize 62
816 00:39:02.089651 [CA 4] Center 33 (3~64) winsize 62
817 00:39:02.089727 [CA 5] Center 33 (2~64) winsize 63
818 00:39:02.089802
819 00:39:02.089877 [CmdBusTrainingLP45] Vref(ca) range 1: 32
820 00:39:02.089954
821 00:39:02.090029 [CATrainingPosCal] consider 2 rank data
822 00:39:02.090106 u2DelayCellTimex100 = 270/100 ps
823 00:39:02.090190 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
824 00:39:02.090268 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
825 00:39:02.090344 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
826 00:39:02.090421 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
827 00:39:02.090497 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
828 00:39:02.090572 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
829 00:39:02.090648
830 00:39:02.090728 CA PerBit enable=1, Macro0, CA PI delay=33
831 00:39:02.090870
832 00:39:02.090956 [CBTSetCACLKResult] CA Dly = 33
833 00:39:02.091090 CS Dly: 6 (0~38)
834 00:39:02.091179
835 00:39:02.091257 ----->DramcWriteLeveling(PI) begin...
836 00:39:02.091336 ==
837 00:39:02.091414 Dram Type= 6, Freq= 0, CH_0, rank 0
838 00:39:02.091489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
839 00:39:02.091567 ==
840 00:39:02.091642 Write leveling (Byte 0): 31 => 31
841 00:39:02.091719 Write leveling (Byte 1): 31 => 31
842 00:39:02.091795 DramcWriteLeveling(PI) end<-----
843 00:39:02.091872
844 00:39:02.091946 ==
845 00:39:02.092023 Dram Type= 6, Freq= 0, CH_0, rank 0
846 00:39:02.092098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
847 00:39:02.092175 ==
848 00:39:02.092250 [Gating] SW mode calibration
849 00:39:02.092326 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
850 00:39:02.092402 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
851 00:39:02.092477 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 00:39:02.092553 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 00:39:02.092629 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 00:39:02.092707 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:39:02.092812 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:39:02.092890 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:39:02.092966 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:39:02.093042 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:39:02.093118 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:39:02.093193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:39:02.093269 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:39:02.093345 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:39:02.093421 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:39:02.093496 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:39:02.093571 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:39:02.093646 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:39:02.093721 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 00:39:02.093796 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
869 00:39:02.093871 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
870 00:39:02.093947 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:39:02.094022 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:39:02.094097 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:39:02.094184 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:39:02.094263 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:39:02.094350 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:39:02.094417 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:39:02.094484 0 9 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
878 00:39:02.094551 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
879 00:39:02.094828 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 00:39:02.094908 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:39:02.094978 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:39:02.095046 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:39:02.095114 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:39:02.095181 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
885 00:39:02.095249 0 10 8 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (1 1)
886 00:39:02.095315 0 10 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
887 00:39:02.095383 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:39:02.095450 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:39:02.095518 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:39:02.095584 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:39:02.095652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:39:02.095720 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
893 00:39:02.095787 0 11 8 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (0 0)
894 00:39:02.095854 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
895 00:39:02.095921 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:39:02.095988 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:39:02.096055 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:39:02.096121 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:39:02.096188 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:39:02.096284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 00:39:02.096355 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
902 00:39:02.096423 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 00:39:02.096491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:39:02.096558 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:39:02.096626 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:39:02.096693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:39:02.096760 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:39:02.096827 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:39:02.096895 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:39:02.096962 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:39:02.097029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:39:02.097100 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:39:02.097167 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:39:02.097233 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:39:02.097300 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:39:02.097367 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:39:02.097434 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 00:39:02.097501 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 00:39:02.097568 Total UI for P1: 0, mck2ui 16
920 00:39:02.097635 best dqsien dly found for B0: ( 0, 14, 8)
921 00:39:02.097703 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 00:39:02.097770 Total UI for P1: 0, mck2ui 16
923 00:39:02.097837 best dqsien dly found for B1: ( 0, 14, 12)
924 00:39:02.097904 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
925 00:39:02.097971 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
926 00:39:02.098041
927 00:39:02.098107 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
928 00:39:02.098184 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
929 00:39:02.098254 [Gating] SW calibration Done
930 00:39:02.098321 ==
931 00:39:02.098388 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:39:02.098455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:39:02.098523 ==
934 00:39:02.098589 RX Vref Scan: 0
935 00:39:02.098656
936 00:39:02.098722 RX Vref 0 -> 0, step: 1
937 00:39:02.098789
938 00:39:02.098855 RX Delay -130 -> 252, step: 16
939 00:39:02.098922 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 00:39:02.098989 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
941 00:39:02.099056 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 00:39:02.099123 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 00:39:02.099190 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
944 00:39:02.099270 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 00:39:02.099330 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 00:39:02.099390 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
947 00:39:02.099450 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
948 00:39:02.099528 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
949 00:39:02.099594 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 00:39:02.099655 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 00:39:02.099716 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
952 00:39:02.099777 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
953 00:39:02.099838 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 00:39:02.099898 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
955 00:39:02.099958 ==
956 00:39:02.100019 Dram Type= 6, Freq= 0, CH_0, rank 0
957 00:39:02.100080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 00:39:02.100141 ==
959 00:39:02.100201 DQS Delay:
960 00:39:02.100261 DQS0 = 0, DQS1 = 0
961 00:39:02.100322 DQM Delay:
962 00:39:02.100382 DQM0 = 85, DQM1 = 71
963 00:39:02.100462 DQ Delay:
964 00:39:02.100523 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
965 00:39:02.100584 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
966 00:39:02.100645 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
967 00:39:02.100705 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
968 00:39:02.100765
969 00:39:02.100825
970 00:39:02.100884 ==
971 00:39:02.100944 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:39:02.101005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:39:02.101065 ==
974 00:39:02.101125
975 00:39:02.101185
976 00:39:02.101244 TX Vref Scan disable
977 00:39:02.101304 == TX Byte 0 ==
978 00:39:02.101364 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 00:39:02.101426 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 00:39:02.101485 == TX Byte 1 ==
981 00:39:02.101546 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
982 00:39:02.101605 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
983 00:39:02.101666 ==
984 00:39:02.101726 Dram Type= 6, Freq= 0, CH_0, rank 0
985 00:39:02.101787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 00:39:02.101847 ==
987 00:39:02.102105 TX Vref=22, minBit 5, minWin=27, winSum=445
988 00:39:02.102182 TX Vref=24, minBit 5, minWin=27, winSum=449
989 00:39:02.102247 TX Vref=26, minBit 8, minWin=27, winSum=450
990 00:39:02.102309 TX Vref=28, minBit 10, minWin=27, winSum=449
991 00:39:02.102370 TX Vref=30, minBit 10, minWin=27, winSum=449
992 00:39:02.102434 TX Vref=32, minBit 10, minWin=27, winSum=446
993 00:39:02.102516 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 26
994 00:39:02.102578
995 00:39:02.102640 Final TX Range 1 Vref 26
996 00:39:02.102700
997 00:39:02.102760 ==
998 00:39:02.102821 Dram Type= 6, Freq= 0, CH_0, rank 0
999 00:39:02.102881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 00:39:02.102942 ==
1001 00:39:02.103002
1002 00:39:02.103062
1003 00:39:02.103122 TX Vref Scan disable
1004 00:39:02.103181 == TX Byte 0 ==
1005 00:39:02.103241 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 00:39:02.103302 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 00:39:02.103362 == TX Byte 1 ==
1008 00:39:02.103422 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1009 00:39:02.103482 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1010 00:39:02.103542
1011 00:39:02.103602 [DATLAT]
1012 00:39:02.103663 Freq=800, CH0 RK0
1013 00:39:02.103724
1014 00:39:02.103784 DATLAT Default: 0xa
1015 00:39:02.103844 0, 0xFFFF, sum = 0
1016 00:39:02.103905 1, 0xFFFF, sum = 0
1017 00:39:02.103966 2, 0xFFFF, sum = 0
1018 00:39:02.104027 3, 0xFFFF, sum = 0
1019 00:39:02.104089 4, 0xFFFF, sum = 0
1020 00:39:02.104149 5, 0xFFFF, sum = 0
1021 00:39:02.104211 6, 0xFFFF, sum = 0
1022 00:39:02.104272 7, 0xFFFF, sum = 0
1023 00:39:02.104341 8, 0xFFFF, sum = 0
1024 00:39:02.104397 9, 0x0, sum = 1
1025 00:39:02.104459 10, 0x0, sum = 2
1026 00:39:02.104521 11, 0x0, sum = 3
1027 00:39:02.104578 12, 0x0, sum = 4
1028 00:39:02.104635 best_step = 10
1029 00:39:02.104689
1030 00:39:02.104744 ==
1031 00:39:02.104798 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 00:39:02.104852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 00:39:02.104908 ==
1034 00:39:02.104962 RX Vref Scan: 1
1035 00:39:02.105015
1036 00:39:02.105069 Set Vref Range= 32 -> 127
1037 00:39:02.105123
1038 00:39:02.105178 RX Vref 32 -> 127, step: 1
1039 00:39:02.105232
1040 00:39:02.105285 RX Delay -111 -> 252, step: 8
1041 00:39:02.105339
1042 00:39:02.105394 Set Vref, RX VrefLevel [Byte0]: 32
1043 00:39:02.105450 [Byte1]: 32
1044 00:39:02.105513
1045 00:39:02.105568 Set Vref, RX VrefLevel [Byte0]: 33
1046 00:39:02.105622 [Byte1]: 33
1047 00:39:02.105677
1048 00:39:02.105745 Set Vref, RX VrefLevel [Byte0]: 34
1049 00:39:02.105805 [Byte1]: 34
1050 00:39:02.105860
1051 00:39:02.105914 Set Vref, RX VrefLevel [Byte0]: 35
1052 00:39:02.105969 [Byte1]: 35
1053 00:39:02.106023
1054 00:39:02.106076 Set Vref, RX VrefLevel [Byte0]: 36
1055 00:39:02.106131 [Byte1]: 36
1056 00:39:02.106193
1057 00:39:02.106248 Set Vref, RX VrefLevel [Byte0]: 37
1058 00:39:02.106303 [Byte1]: 37
1059 00:39:02.106357
1060 00:39:02.106410 Set Vref, RX VrefLevel [Byte0]: 38
1061 00:39:02.106463 [Byte1]: 38
1062 00:39:02.106517
1063 00:39:02.106570 Set Vref, RX VrefLevel [Byte0]: 39
1064 00:39:02.106624 [Byte1]: 39
1065 00:39:02.106678
1066 00:39:02.106732 Set Vref, RX VrefLevel [Byte0]: 40
1067 00:39:02.106786 [Byte1]: 40
1068 00:39:02.106839
1069 00:39:02.106893 Set Vref, RX VrefLevel [Byte0]: 41
1070 00:39:02.106947 [Byte1]: 41
1071 00:39:02.107001
1072 00:39:02.107054 Set Vref, RX VrefLevel [Byte0]: 42
1073 00:39:02.107108 [Byte1]: 42
1074 00:39:02.107163
1075 00:39:02.107217 Set Vref, RX VrefLevel [Byte0]: 43
1076 00:39:02.107271 [Byte1]: 43
1077 00:39:02.107325
1078 00:39:02.107379 Set Vref, RX VrefLevel [Byte0]: 44
1079 00:39:02.107433 [Byte1]: 44
1080 00:39:02.107487
1081 00:39:02.107541 Set Vref, RX VrefLevel [Byte0]: 45
1082 00:39:02.107595 [Byte1]: 45
1083 00:39:02.107649
1084 00:39:02.107703 Set Vref, RX VrefLevel [Byte0]: 46
1085 00:39:02.107757 [Byte1]: 46
1086 00:39:02.107811
1087 00:39:02.107865 Set Vref, RX VrefLevel [Byte0]: 47
1088 00:39:02.107919 [Byte1]: 47
1089 00:39:02.107972
1090 00:39:02.108026 Set Vref, RX VrefLevel [Byte0]: 48
1091 00:39:02.108080 [Byte1]: 48
1092 00:39:02.108134
1093 00:39:02.108187 Set Vref, RX VrefLevel [Byte0]: 49
1094 00:39:02.108241 [Byte1]: 49
1095 00:39:02.108295
1096 00:39:02.108349 Set Vref, RX VrefLevel [Byte0]: 50
1097 00:39:02.108403 [Byte1]: 50
1098 00:39:02.108457
1099 00:39:02.108510 Set Vref, RX VrefLevel [Byte0]: 51
1100 00:39:02.108564 [Byte1]: 51
1101 00:39:02.108618
1102 00:39:02.108672 Set Vref, RX VrefLevel [Byte0]: 52
1103 00:39:02.108726 [Byte1]: 52
1104 00:39:02.108795
1105 00:39:02.108854 Set Vref, RX VrefLevel [Byte0]: 53
1106 00:39:02.108909 [Byte1]: 53
1107 00:39:02.108963
1108 00:39:02.109017 Set Vref, RX VrefLevel [Byte0]: 54
1109 00:39:02.109071 [Byte1]: 54
1110 00:39:02.109125
1111 00:39:02.109178 Set Vref, RX VrefLevel [Byte0]: 55
1112 00:39:02.109232 [Byte1]: 55
1113 00:39:02.109300
1114 00:39:02.109352 Set Vref, RX VrefLevel [Byte0]: 56
1115 00:39:02.109405 [Byte1]: 56
1116 00:39:02.109458
1117 00:39:02.109511 Set Vref, RX VrefLevel [Byte0]: 57
1118 00:39:02.109564 [Byte1]: 57
1119 00:39:02.109617
1120 00:39:02.109669 Set Vref, RX VrefLevel [Byte0]: 58
1121 00:39:02.109722 [Byte1]: 58
1122 00:39:02.109776
1123 00:39:02.109829 Set Vref, RX VrefLevel [Byte0]: 59
1124 00:39:02.109881 [Byte1]: 59
1125 00:39:02.109934
1126 00:39:02.109986 Set Vref, RX VrefLevel [Byte0]: 60
1127 00:39:02.110039 [Byte1]: 60
1128 00:39:02.110092
1129 00:39:02.110144 Set Vref, RX VrefLevel [Byte0]: 61
1130 00:39:02.110229 [Byte1]: 61
1131 00:39:02.110296
1132 00:39:02.110349 Set Vref, RX VrefLevel [Byte0]: 62
1133 00:39:02.110402 [Byte1]: 62
1134 00:39:02.110455
1135 00:39:02.110507 Set Vref, RX VrefLevel [Byte0]: 63
1136 00:39:02.110560 [Byte1]: 63
1137 00:39:02.110613
1138 00:39:02.110665 Set Vref, RX VrefLevel [Byte0]: 64
1139 00:39:02.110719 [Byte1]: 64
1140 00:39:02.110772
1141 00:39:02.110824 Set Vref, RX VrefLevel [Byte0]: 65
1142 00:39:02.110876 [Byte1]: 65
1143 00:39:02.110929
1144 00:39:02.110982 Set Vref, RX VrefLevel [Byte0]: 66
1145 00:39:02.111035 [Byte1]: 66
1146 00:39:02.111087
1147 00:39:02.111140 Set Vref, RX VrefLevel [Byte0]: 67
1148 00:39:02.111193 [Byte1]: 67
1149 00:39:02.111246
1150 00:39:02.111298 Set Vref, RX VrefLevel [Byte0]: 68
1151 00:39:02.111350 [Byte1]: 68
1152 00:39:02.111403
1153 00:39:02.111456 Set Vref, RX VrefLevel [Byte0]: 69
1154 00:39:02.111701 [Byte1]: 69
1155 00:39:02.111761
1156 00:39:02.111816 Set Vref, RX VrefLevel [Byte0]: 70
1157 00:39:02.111870 [Byte1]: 70
1158 00:39:02.111923
1159 00:39:02.111975 Set Vref, RX VrefLevel [Byte0]: 71
1160 00:39:02.112028 [Byte1]: 71
1161 00:39:02.112081
1162 00:39:02.112134 Set Vref, RX VrefLevel [Byte0]: 72
1163 00:39:02.112187 [Byte1]: 72
1164 00:39:02.112240
1165 00:39:02.112293 Set Vref, RX VrefLevel [Byte0]: 73
1166 00:39:02.112346 [Byte1]: 73
1167 00:39:02.112399
1168 00:39:02.112451 Set Vref, RX VrefLevel [Byte0]: 74
1169 00:39:02.112523 [Byte1]: 74
1170 00:39:02.112580
1171 00:39:02.112634 Set Vref, RX VrefLevel [Byte0]: 75
1172 00:39:02.112687 [Byte1]: 75
1173 00:39:02.112740
1174 00:39:02.112793 Set Vref, RX VrefLevel [Byte0]: 76
1175 00:39:02.112846 [Byte1]: 76
1176 00:39:02.112899
1177 00:39:02.112952 Set Vref, RX VrefLevel [Byte0]: 77
1178 00:39:02.113006 [Byte1]: 77
1179 00:39:02.113059
1180 00:39:02.113112 Set Vref, RX VrefLevel [Byte0]: 78
1181 00:39:02.113164 [Byte1]: 78
1182 00:39:02.113218
1183 00:39:02.113270 Set Vref, RX VrefLevel [Byte0]: 79
1184 00:39:02.113323 [Byte1]: 79
1185 00:39:02.113376
1186 00:39:02.113428 Set Vref, RX VrefLevel [Byte0]: 80
1187 00:39:02.113481 [Byte1]: 80
1188 00:39:02.113534
1189 00:39:02.113587 Final RX Vref Byte 0 = 65 to rank0
1190 00:39:02.113641 Final RX Vref Byte 1 = 55 to rank0
1191 00:39:02.113695 Final RX Vref Byte 0 = 65 to rank1
1192 00:39:02.113748 Final RX Vref Byte 1 = 55 to rank1==
1193 00:39:02.113818 Dram Type= 6, Freq= 0, CH_0, rank 0
1194 00:39:02.113874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 00:39:02.113928 ==
1196 00:39:02.113981 DQS Delay:
1197 00:39:02.114037 DQS0 = 0, DQS1 = 0
1198 00:39:02.114091 DQM Delay:
1199 00:39:02.114144 DQM0 = 86, DQM1 = 75
1200 00:39:02.114239 DQ Delay:
1201 00:39:02.114293 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1202 00:39:02.114346 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1203 00:39:02.114400 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1204 00:39:02.114453 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1205 00:39:02.114506
1206 00:39:02.114559
1207 00:39:02.114612 [DQSOSCAuto] RK0, (LSB)MR18= 0x4324, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1208 00:39:02.114666 CH0 RK0: MR19=606, MR18=4324
1209 00:39:02.114720 CH0_RK0: MR19=0x606, MR18=0x4324, DQSOSC=393, MR23=63, INC=95, DEC=63
1210 00:39:02.114773
1211 00:39:02.114826 ----->DramcWriteLeveling(PI) begin...
1212 00:39:02.114880 ==
1213 00:39:02.114933 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 00:39:02.114987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 00:39:02.115041 ==
1216 00:39:02.115093 Write leveling (Byte 0): 30 => 30
1217 00:39:02.115147 Write leveling (Byte 1): 29 => 29
1218 00:39:02.115203 DramcWriteLeveling(PI) end<-----
1219 00:39:02.115256
1220 00:39:02.115309 ==
1221 00:39:02.115362 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 00:39:02.115415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1223 00:39:02.115469 ==
1224 00:39:02.115522 [Gating] SW mode calibration
1225 00:39:02.115575 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1226 00:39:02.115635 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1227 00:39:02.115702 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1228 00:39:02.115756 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 00:39:02.115810 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1230 00:39:02.115863 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1231 00:39:02.115916 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:39:02.115970 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:39:02.116023 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:39:02.116076 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:39:02.116130 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:39:02.116183 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:39:02.116236 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:39:02.116289 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:39:02.116343 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:39:02.116396 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:39:02.116449 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:39:02.116502 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:39:02.116555 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:39:02.116608 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1245 00:39:02.116661 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1246 00:39:02.116715 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 00:39:02.116768 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 00:39:02.116821 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:39:02.116874 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:39:02.116927 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:39:02.116981 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:39:02.117034 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:39:02.117087 0 9 8 | B1->B0 | 2525 2e2e | 0 1 | (1 1) (1 1)
1254 00:39:02.117140 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1255 00:39:02.117194 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 00:39:02.117247 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 00:39:02.117300 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 00:39:02.117353 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 00:39:02.117407 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 00:39:02.117460 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
1261 00:39:02.117513 0 10 8 | B1->B0 | 3030 2a2a | 1 0 | (1 0) (1 0)
1262 00:39:02.117566 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1263 00:39:02.117619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 00:39:02.117673 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 00:39:02.117726 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 00:39:02.117779 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 00:39:02.118027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 00:39:02.118090 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1269 00:39:02.118144 0 11 8 | B1->B0 | 3030 3d3d | 0 0 | (1 1) (0 0)
1270 00:39:02.118239 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
1271 00:39:02.118293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 00:39:02.118349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 00:39:02.118403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 00:39:02.118457 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 00:39:02.118511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 00:39:02.118586 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 00:39:02.118642 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1278 00:39:02.118695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 00:39:02.118749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:39:02.118802 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:39:02.118855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:39:02.118908 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:39:02.118961 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:39:02.119014 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:39:02.119068 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:39:02.119121 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:39:02.119175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 00:39:02.119227 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 00:39:02.119280 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 00:39:02.119333 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 00:39:02.119386 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 00:39:02.119439 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1293 00:39:02.119492 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1294 00:39:02.119545 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1295 00:39:02.119598 Total UI for P1: 0, mck2ui 16
1296 00:39:02.119652 best dqsien dly found for B0: ( 0, 14, 6)
1297 00:39:02.119705 Total UI for P1: 0, mck2ui 16
1298 00:39:02.119758 best dqsien dly found for B1: ( 0, 14, 10)
1299 00:39:02.119811 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1300 00:39:02.119863 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1301 00:39:02.119916
1302 00:39:02.119968 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1303 00:39:02.120021 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1304 00:39:02.120074 [Gating] SW calibration Done
1305 00:39:02.120127 ==
1306 00:39:02.120180 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 00:39:02.120233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 00:39:02.120286 ==
1309 00:39:02.120340 RX Vref Scan: 0
1310 00:39:02.120393
1311 00:39:02.120445 RX Vref 0 -> 0, step: 1
1312 00:39:02.120498
1313 00:39:02.120550 RX Delay -130 -> 252, step: 16
1314 00:39:02.120604 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1315 00:39:02.120657 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1316 00:39:02.120710 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1317 00:39:02.120762 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1318 00:39:02.120814 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1319 00:39:02.120867 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1320 00:39:02.120919 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1321 00:39:02.120972 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1322 00:39:02.121025 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1323 00:39:02.121077 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1324 00:39:02.121130 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1325 00:39:02.121183 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1326 00:39:02.121235 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1327 00:39:02.121288 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1328 00:39:02.121341 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1329 00:39:02.121393 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1330 00:39:02.121446 ==
1331 00:39:02.121499 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:39:02.121552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:39:02.121605 ==
1334 00:39:02.121657 DQS Delay:
1335 00:39:02.121710 DQS0 = 0, DQS1 = 0
1336 00:39:02.121763 DQM Delay:
1337 00:39:02.121816 DQM0 = 85, DQM1 = 79
1338 00:39:02.121868 DQ Delay:
1339 00:39:02.121920 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1340 00:39:02.121973 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1341 00:39:02.122026 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1342 00:39:02.122121 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1343 00:39:02.122232
1344 00:39:02.122288
1345 00:39:02.122341 ==
1346 00:39:02.122394 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 00:39:02.122449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 00:39:02.122503 ==
1349 00:39:02.122556
1350 00:39:02.122609
1351 00:39:02.122661 TX Vref Scan disable
1352 00:39:02.122714 == TX Byte 0 ==
1353 00:39:02.122767 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1354 00:39:02.122820 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1355 00:39:02.122874 == TX Byte 1 ==
1356 00:39:02.122927 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1357 00:39:02.122981 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1358 00:39:02.123034 ==
1359 00:39:02.123087 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 00:39:02.123140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 00:39:02.123194 ==
1362 00:39:02.123246 TX Vref=22, minBit 9, minWin=27, winSum=446
1363 00:39:02.123299 TX Vref=24, minBit 8, minWin=27, winSum=445
1364 00:39:02.123352 TX Vref=26, minBit 9, minWin=27, winSum=447
1365 00:39:02.123405 TX Vref=28, minBit 9, minWin=27, winSum=450
1366 00:39:02.123458 TX Vref=30, minBit 9, minWin=27, winSum=448
1367 00:39:02.123511 TX Vref=32, minBit 4, minWin=27, winSum=444
1368 00:39:02.123564 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 28
1369 00:39:02.123617
1370 00:39:02.123670 Final TX Range 1 Vref 28
1371 00:39:02.123723
1372 00:39:02.123775 ==
1373 00:39:02.123827 Dram Type= 6, Freq= 0, CH_0, rank 1
1374 00:39:02.123880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 00:39:02.123932 ==
1376 00:39:02.123985
1377 00:39:02.124036
1378 00:39:02.124089 TX Vref Scan disable
1379 00:39:02.124141 == TX Byte 0 ==
1380 00:39:02.124193 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1381 00:39:02.124245 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1382 00:39:02.124297 == TX Byte 1 ==
1383 00:39:02.124542 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1384 00:39:02.124602 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1385 00:39:02.124655
1386 00:39:02.124707 [DATLAT]
1387 00:39:02.124759 Freq=800, CH0 RK1
1388 00:39:02.124812
1389 00:39:02.124864 DATLAT Default: 0xa
1390 00:39:02.124917 0, 0xFFFF, sum = 0
1391 00:39:02.124971 1, 0xFFFF, sum = 0
1392 00:39:02.125025 2, 0xFFFF, sum = 0
1393 00:39:02.125078 3, 0xFFFF, sum = 0
1394 00:39:02.125131 4, 0xFFFF, sum = 0
1395 00:39:02.125206 5, 0xFFFF, sum = 0
1396 00:39:02.125263 6, 0xFFFF, sum = 0
1397 00:39:02.125316 7, 0xFFFF, sum = 0
1398 00:39:02.125369 8, 0xFFFF, sum = 0
1399 00:39:02.125423 9, 0x0, sum = 1
1400 00:39:02.125476 10, 0x0, sum = 2
1401 00:39:02.125530 11, 0x0, sum = 3
1402 00:39:02.125583 12, 0x0, sum = 4
1403 00:39:02.125637 best_step = 10
1404 00:39:02.125690
1405 00:39:02.125742 ==
1406 00:39:02.125794 Dram Type= 6, Freq= 0, CH_0, rank 1
1407 00:39:02.125847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 00:39:02.125900 ==
1409 00:39:02.125953 RX Vref Scan: 0
1410 00:39:02.126006
1411 00:39:02.126058 RX Vref 0 -> 0, step: 1
1412 00:39:02.126110
1413 00:39:02.126169 RX Delay -95 -> 252, step: 8
1414 00:39:02.126262 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1415 00:39:02.126315 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1416 00:39:02.126367 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1417 00:39:02.126419 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1418 00:39:02.126471 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1419 00:39:02.126523 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1420 00:39:02.126576 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1421 00:39:02.126628 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1422 00:39:02.126681 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1423 00:39:02.126733 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1424 00:39:02.126785 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1425 00:39:02.126837 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1426 00:39:02.126889 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1427 00:39:02.126941 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1428 00:39:02.126993 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1429 00:39:02.127045 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1430 00:39:02.127096 ==
1431 00:39:02.127149 Dram Type= 6, Freq= 0, CH_0, rank 1
1432 00:39:02.127201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 00:39:02.127254 ==
1434 00:39:02.127305 DQS Delay:
1435 00:39:02.127358 DQS0 = 0, DQS1 = 0
1436 00:39:02.127410 DQM Delay:
1437 00:39:02.127462 DQM0 = 86, DQM1 = 76
1438 00:39:02.127514 DQ Delay:
1439 00:39:02.127566 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1440 00:39:02.127618 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1441 00:39:02.127670 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1442 00:39:02.127722 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1443 00:39:02.127775
1444 00:39:02.127827
1445 00:39:02.127879 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f06, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1446 00:39:02.127932 CH0 RK1: MR19=606, MR18=3F06
1447 00:39:02.127984 CH0_RK1: MR19=0x606, MR18=0x3F06, DQSOSC=393, MR23=63, INC=95, DEC=63
1448 00:39:02.128037 [RxdqsGatingPostProcess] freq 800
1449 00:39:02.128089 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1450 00:39:02.128142 Pre-setting of DQS Precalculation
1451 00:39:02.128194 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1452 00:39:02.128247 ==
1453 00:39:02.128299 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 00:39:02.128351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 00:39:02.128404 ==
1456 00:39:02.128455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1457 00:39:02.128508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1458 00:39:02.128561 [CA 0] Center 36 (6~67) winsize 62
1459 00:39:02.128613 [CA 1] Center 36 (6~67) winsize 62
1460 00:39:02.128666 [CA 2] Center 34 (4~65) winsize 62
1461 00:39:02.128718 [CA 3] Center 34 (3~65) winsize 63
1462 00:39:02.128793 [CA 4] Center 34 (4~65) winsize 62
1463 00:39:02.128847 [CA 5] Center 34 (3~65) winsize 63
1464 00:39:02.128900
1465 00:39:02.128952 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1466 00:39:02.129005
1467 00:39:02.129057 [CATrainingPosCal] consider 1 rank data
1468 00:39:02.129109 u2DelayCellTimex100 = 270/100 ps
1469 00:39:02.129162 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1470 00:39:02.129214 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1471 00:39:02.129266 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 00:39:02.129318 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1473 00:39:02.129370 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 00:39:02.129422 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 00:39:02.129474
1476 00:39:02.129525 CA PerBit enable=1, Macro0, CA PI delay=34
1477 00:39:02.129578
1478 00:39:02.129629 [CBTSetCACLKResult] CA Dly = 34
1479 00:39:02.129682 CS Dly: 5 (0~36)
1480 00:39:02.129734 ==
1481 00:39:02.129800 Dram Type= 6, Freq= 0, CH_1, rank 1
1482 00:39:02.129855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 00:39:02.129909 ==
1484 00:39:02.129961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1485 00:39:02.130014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1486 00:39:02.130067 [CA 0] Center 36 (6~67) winsize 62
1487 00:39:02.130119 [CA 1] Center 36 (6~67) winsize 62
1488 00:39:02.130178 [CA 2] Center 34 (4~65) winsize 62
1489 00:39:02.130271 [CA 3] Center 34 (3~65) winsize 63
1490 00:39:02.130324 [CA 4] Center 34 (4~65) winsize 62
1491 00:39:02.130376 [CA 5] Center 34 (3~65) winsize 63
1492 00:39:02.130428
1493 00:39:02.130480 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1494 00:39:02.130532
1495 00:39:02.130584 [CATrainingPosCal] consider 2 rank data
1496 00:39:02.130636 u2DelayCellTimex100 = 270/100 ps
1497 00:39:02.130688 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1498 00:39:02.130741 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1499 00:39:02.130793 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1500 00:39:02.130845 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1501 00:39:02.130898 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 00:39:02.130950 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1503 00:39:02.131002
1504 00:39:02.131054 CA PerBit enable=1, Macro0, CA PI delay=34
1505 00:39:02.131106
1506 00:39:02.131157 [CBTSetCACLKResult] CA Dly = 34
1507 00:39:02.131209 CS Dly: 6 (0~38)
1508 00:39:02.131261
1509 00:39:02.131313 ----->DramcWriteLeveling(PI) begin...
1510 00:39:02.131366 ==
1511 00:39:02.131418 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 00:39:02.131471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 00:39:02.131523 ==
1514 00:39:02.131575 Write leveling (Byte 0): 27 => 27
1515 00:39:02.131628 Write leveling (Byte 1): 28 => 28
1516 00:39:02.131680 DramcWriteLeveling(PI) end<-----
1517 00:39:02.131731
1518 00:39:02.131782 ==
1519 00:39:02.132027 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 00:39:02.132087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1521 00:39:02.132151 ==
1522 00:39:02.132214 [Gating] SW mode calibration
1523 00:39:02.132269 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1524 00:39:02.132322 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1525 00:39:02.132375 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1526 00:39:02.132428 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1527 00:39:02.132481 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1528 00:39:02.132533 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:39:02.132585 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:39:02.132637 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:39:02.132689 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:39:02.132741 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:39:02.132793 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:39:02.132846 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:39:02.132898 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:39:02.132951 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:39:02.133003 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:39:02.133055 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:39:02.133108 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:39:02.133160 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:39:02.133212 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1542 00:39:02.133265 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1543 00:39:02.133317 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:39:02.133369 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 00:39:02.133421 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:39:02.133473 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:39:02.133526 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:39:02.133578 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:39:02.133630 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:39:02.133682 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1551 00:39:02.133734 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1552 00:39:02.133786 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 00:39:02.133838 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 00:39:02.133890 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 00:39:02.133943 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 00:39:02.133996 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 00:39:02.134048 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 00:39:02.134101 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1559 00:39:02.134153 0 10 8 | B1->B0 | 2c2c 2727 | 0 0 | (0 1) (0 0)
1560 00:39:02.134251 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 00:39:02.134304 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 00:39:02.134356 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 00:39:02.134409 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 00:39:02.134461 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 00:39:02.134513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 00:39:02.134565 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1567 00:39:02.134617 0 11 8 | B1->B0 | 3c3c 4141 | 1 0 | (0 0) (0 0)
1568 00:39:02.134669 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 00:39:02.134721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 00:39:02.134773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 00:39:02.134826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 00:39:02.134878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 00:39:02.134930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 00:39:02.134982 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1575 00:39:02.135035 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1576 00:39:02.135087 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 00:39:02.135162 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:39:02.135217 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:39:02.135270 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:39:02.135323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:39:02.135375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:39:02.135427 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:39:02.135480 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:39:02.135532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 00:39:02.135584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 00:39:02.135636 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 00:39:02.135688 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 00:39:02.135741 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 00:39:02.135794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 00:39:02.135847 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1591 00:39:02.135899 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1592 00:39:02.135951 Total UI for P1: 0, mck2ui 16
1593 00:39:02.136005 best dqsien dly found for B0: ( 0, 14, 4)
1594 00:39:02.136057 Total UI for P1: 0, mck2ui 16
1595 00:39:02.136110 best dqsien dly found for B1: ( 0, 14, 4)
1596 00:39:02.136163 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1597 00:39:02.136216 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1598 00:39:02.136268
1599 00:39:02.136320 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1600 00:39:02.136372 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1601 00:39:02.136424 [Gating] SW calibration Done
1602 00:39:02.136476 ==
1603 00:39:02.136528 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 00:39:02.136776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 00:39:02.136839 ==
1606 00:39:02.136892 RX Vref Scan: 0
1607 00:39:02.136945
1608 00:39:02.136998 RX Vref 0 -> 0, step: 1
1609 00:39:02.137050
1610 00:39:02.137102 RX Delay -130 -> 252, step: 16
1611 00:39:02.137155 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1612 00:39:02.137208 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1613 00:39:02.137261 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1614 00:39:02.137313 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1615 00:39:02.137366 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1616 00:39:02.137418 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1617 00:39:02.137471 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1618 00:39:02.137523 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1619 00:39:02.137575 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1620 00:39:02.137627 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1621 00:39:02.137680 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1622 00:39:02.137732 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1623 00:39:02.137784 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1624 00:39:02.137837 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1625 00:39:02.137889 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1626 00:39:02.137941 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1627 00:39:02.137994 ==
1628 00:39:02.138046 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 00:39:02.138098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 00:39:02.138151 ==
1631 00:39:02.138248 DQS Delay:
1632 00:39:02.138300 DQS0 = 0, DQS1 = 0
1633 00:39:02.138352 DQM Delay:
1634 00:39:02.138404 DQM0 = 89, DQM1 = 78
1635 00:39:02.138455 DQ Delay:
1636 00:39:02.138507 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1637 00:39:02.138568 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1638 00:39:02.138631 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1639 00:39:02.138684 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1640 00:39:02.138737
1641 00:39:02.138788
1642 00:39:02.138840 ==
1643 00:39:02.138891 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 00:39:02.138944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 00:39:02.138997 ==
1646 00:39:02.139048
1647 00:39:02.139100
1648 00:39:02.139151 TX Vref Scan disable
1649 00:39:02.139203 == TX Byte 0 ==
1650 00:39:02.139255 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1651 00:39:02.139308 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1652 00:39:02.139360 == TX Byte 1 ==
1653 00:39:02.139412 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1654 00:39:02.139464 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1655 00:39:02.139517 ==
1656 00:39:02.139568 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 00:39:02.139620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 00:39:02.139673 ==
1659 00:39:02.139725 TX Vref=22, minBit 9, minWin=27, winSum=446
1660 00:39:02.139778 TX Vref=24, minBit 8, minWin=27, winSum=446
1661 00:39:02.139830 TX Vref=26, minBit 9, minWin=27, winSum=452
1662 00:39:02.139883 TX Vref=28, minBit 15, minWin=27, winSum=455
1663 00:39:02.139935 TX Vref=30, minBit 10, minWin=27, winSum=449
1664 00:39:02.139988 TX Vref=32, minBit 8, minWin=27, winSum=446
1665 00:39:02.140041 [TxChooseVref] Worse bit 15, Min win 27, Win sum 455, Final Vref 28
1666 00:39:02.140094
1667 00:39:02.140146 Final TX Range 1 Vref 28
1668 00:39:02.140199
1669 00:39:02.140251 ==
1670 00:39:02.140303 Dram Type= 6, Freq= 0, CH_1, rank 0
1671 00:39:02.140355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1672 00:39:02.140408 ==
1673 00:39:02.140459
1674 00:39:02.140511
1675 00:39:02.140563 TX Vref Scan disable
1676 00:39:02.140615 == TX Byte 0 ==
1677 00:39:02.140667 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1678 00:39:02.140719 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1679 00:39:02.140771 == TX Byte 1 ==
1680 00:39:02.140823 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1681 00:39:02.140875 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1682 00:39:02.140927
1683 00:39:02.140979 [DATLAT]
1684 00:39:02.141031 Freq=800, CH1 RK0
1685 00:39:02.141083
1686 00:39:02.141134 DATLAT Default: 0xa
1687 00:39:02.141186 0, 0xFFFF, sum = 0
1688 00:39:02.141240 1, 0xFFFF, sum = 0
1689 00:39:02.141293 2, 0xFFFF, sum = 0
1690 00:39:02.141346 3, 0xFFFF, sum = 0
1691 00:39:02.141399 4, 0xFFFF, sum = 0
1692 00:39:02.141451 5, 0xFFFF, sum = 0
1693 00:39:02.141504 6, 0xFFFF, sum = 0
1694 00:39:02.141557 7, 0xFFFF, sum = 0
1695 00:39:02.141609 8, 0xFFFF, sum = 0
1696 00:39:02.141662 9, 0x0, sum = 1
1697 00:39:02.141715 10, 0x0, sum = 2
1698 00:39:02.141768 11, 0x0, sum = 3
1699 00:39:02.141821 12, 0x0, sum = 4
1700 00:39:02.141873 best_step = 10
1701 00:39:02.141946
1702 00:39:02.142000 ==
1703 00:39:02.142053 Dram Type= 6, Freq= 0, CH_1, rank 0
1704 00:39:02.142106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1705 00:39:02.142163 ==
1706 00:39:02.142220 RX Vref Scan: 1
1707 00:39:02.142273
1708 00:39:02.142325 Set Vref Range= 32 -> 127
1709 00:39:02.142378
1710 00:39:02.142430 RX Vref 32 -> 127, step: 1
1711 00:39:02.142482
1712 00:39:02.142533 RX Delay -95 -> 252, step: 8
1713 00:39:02.142591
1714 00:39:02.142643 Set Vref, RX VrefLevel [Byte0]: 32
1715 00:39:02.142695 [Byte1]: 32
1716 00:39:02.142748
1717 00:39:02.142799 Set Vref, RX VrefLevel [Byte0]: 33
1718 00:39:02.142851 [Byte1]: 33
1719 00:39:02.142903
1720 00:39:02.142955 Set Vref, RX VrefLevel [Byte0]: 34
1721 00:39:02.143007 [Byte1]: 34
1722 00:39:02.143059
1723 00:39:02.143110 Set Vref, RX VrefLevel [Byte0]: 35
1724 00:39:02.143162 [Byte1]: 35
1725 00:39:02.143214
1726 00:39:02.143266 Set Vref, RX VrefLevel [Byte0]: 36
1727 00:39:02.143318 [Byte1]: 36
1728 00:39:02.143369
1729 00:39:02.143421 Set Vref, RX VrefLevel [Byte0]: 37
1730 00:39:02.143472 [Byte1]: 37
1731 00:39:02.143524
1732 00:39:02.143575 Set Vref, RX VrefLevel [Byte0]: 38
1733 00:39:02.143627 [Byte1]: 38
1734 00:39:02.143679
1735 00:39:02.143731 Set Vref, RX VrefLevel [Byte0]: 39
1736 00:39:02.143783 [Byte1]: 39
1737 00:39:02.143835
1738 00:39:02.143886 Set Vref, RX VrefLevel [Byte0]: 40
1739 00:39:02.143938 [Byte1]: 40
1740 00:39:02.143990
1741 00:39:02.144042 Set Vref, RX VrefLevel [Byte0]: 41
1742 00:39:02.144094 [Byte1]: 41
1743 00:39:02.144146
1744 00:39:02.144197 Set Vref, RX VrefLevel [Byte0]: 42
1745 00:39:02.144249 [Byte1]: 42
1746 00:39:02.144300
1747 00:39:02.144352 Set Vref, RX VrefLevel [Byte0]: 43
1748 00:39:02.144404 [Byte1]: 43
1749 00:39:02.144455
1750 00:39:02.144510 Set Vref, RX VrefLevel [Byte0]: 44
1751 00:39:02.144563 [Byte1]: 44
1752 00:39:02.144615
1753 00:39:02.144667 Set Vref, RX VrefLevel [Byte0]: 45
1754 00:39:02.144719 [Byte1]: 45
1755 00:39:02.144772
1756 00:39:02.144823 Set Vref, RX VrefLevel [Byte0]: 46
1757 00:39:02.144875 [Byte1]: 46
1758 00:39:02.144927
1759 00:39:02.144979 Set Vref, RX VrefLevel [Byte0]: 47
1760 00:39:02.145031 [Byte1]: 47
1761 00:39:02.145083
1762 00:39:02.145327 Set Vref, RX VrefLevel [Byte0]: 48
1763 00:39:02.145386 [Byte1]: 48
1764 00:39:02.145456
1765 00:39:02.145514 Set Vref, RX VrefLevel [Byte0]: 49
1766 00:39:02.145568 [Byte1]: 49
1767 00:39:02.145620
1768 00:39:02.145672 Set Vref, RX VrefLevel [Byte0]: 50
1769 00:39:02.145724 [Byte1]: 50
1770 00:39:02.145777
1771 00:39:02.145828 Set Vref, RX VrefLevel [Byte0]: 51
1772 00:39:02.145881 [Byte1]: 51
1773 00:39:02.145933
1774 00:39:02.145985 Set Vref, RX VrefLevel [Byte0]: 52
1775 00:39:02.146038 [Byte1]: 52
1776 00:39:02.146089
1777 00:39:02.146141 Set Vref, RX VrefLevel [Byte0]: 53
1778 00:39:02.146205 [Byte1]: 53
1779 00:39:02.146258
1780 00:39:02.146310 Set Vref, RX VrefLevel [Byte0]: 54
1781 00:39:02.146362 [Byte1]: 54
1782 00:39:02.146415
1783 00:39:02.146466 Set Vref, RX VrefLevel [Byte0]: 55
1784 00:39:02.146518 [Byte1]: 55
1785 00:39:02.146570
1786 00:39:02.146622 Set Vref, RX VrefLevel [Byte0]: 56
1787 00:39:02.146673 [Byte1]: 56
1788 00:39:02.146725
1789 00:39:02.146777 Set Vref, RX VrefLevel [Byte0]: 57
1790 00:39:02.146829 [Byte1]: 57
1791 00:39:02.146882
1792 00:39:02.146934 Set Vref, RX VrefLevel [Byte0]: 58
1793 00:39:02.146986 [Byte1]: 58
1794 00:39:02.147038
1795 00:39:02.147089 Set Vref, RX VrefLevel [Byte0]: 59
1796 00:39:02.147140 [Byte1]: 59
1797 00:39:02.147193
1798 00:39:02.147245 Set Vref, RX VrefLevel [Byte0]: 60
1799 00:39:02.147297 [Byte1]: 60
1800 00:39:02.147348
1801 00:39:02.147399 Set Vref, RX VrefLevel [Byte0]: 61
1802 00:39:02.147451 [Byte1]: 61
1803 00:39:02.147503
1804 00:39:02.147555 Set Vref, RX VrefLevel [Byte0]: 62
1805 00:39:02.147607 [Byte1]: 62
1806 00:39:02.147658
1807 00:39:02.147710 Set Vref, RX VrefLevel [Byte0]: 63
1808 00:39:02.147762 [Byte1]: 63
1809 00:39:02.147813
1810 00:39:02.147865 Set Vref, RX VrefLevel [Byte0]: 64
1811 00:39:02.147917 [Byte1]: 64
1812 00:39:02.147969
1813 00:39:02.148021 Set Vref, RX VrefLevel [Byte0]: 65
1814 00:39:02.148072 [Byte1]: 65
1815 00:39:02.148124
1816 00:39:02.148176 Set Vref, RX VrefLevel [Byte0]: 66
1817 00:39:02.148228 [Byte1]: 66
1818 00:39:02.148279
1819 00:39:02.148330 Set Vref, RX VrefLevel [Byte0]: 67
1820 00:39:02.148382 [Byte1]: 67
1821 00:39:02.148458
1822 00:39:02.148513 Set Vref, RX VrefLevel [Byte0]: 68
1823 00:39:02.148566 [Byte1]: 68
1824 00:39:02.148618
1825 00:39:02.148670 Set Vref, RX VrefLevel [Byte0]: 69
1826 00:39:02.148722 [Byte1]: 69
1827 00:39:02.148775
1828 00:39:02.148827 Set Vref, RX VrefLevel [Byte0]: 70
1829 00:39:02.148880 [Byte1]: 70
1830 00:39:02.148932
1831 00:39:02.148983 Set Vref, RX VrefLevel [Byte0]: 71
1832 00:39:02.149036 [Byte1]: 71
1833 00:39:02.149087
1834 00:39:02.149139 Set Vref, RX VrefLevel [Byte0]: 72
1835 00:39:02.149191 [Byte1]: 72
1836 00:39:02.149243
1837 00:39:02.149296 Set Vref, RX VrefLevel [Byte0]: 73
1838 00:39:02.149347 [Byte1]: 73
1839 00:39:02.149399
1840 00:39:02.149451 Set Vref, RX VrefLevel [Byte0]: 74
1841 00:39:02.149503 [Byte1]: 74
1842 00:39:02.149555
1843 00:39:02.149606 Final RX Vref Byte 0 = 59 to rank0
1844 00:39:02.149659 Final RX Vref Byte 1 = 64 to rank0
1845 00:39:02.149711 Final RX Vref Byte 0 = 59 to rank1
1846 00:39:02.149763 Final RX Vref Byte 1 = 64 to rank1==
1847 00:39:02.149815 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 00:39:02.149867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 00:39:02.149920 ==
1850 00:39:02.149972 DQS Delay:
1851 00:39:02.150024 DQS0 = 0, DQS1 = 0
1852 00:39:02.150076 DQM Delay:
1853 00:39:02.150128 DQM0 = 86, DQM1 = 79
1854 00:39:02.150183 DQ Delay:
1855 00:39:02.150236 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1856 00:39:02.150288 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1857 00:39:02.150340 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1858 00:39:02.150392 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1859 00:39:02.150445
1860 00:39:02.150496
1861 00:39:02.150548 [DQSOSCAuto] RK0, (LSB)MR18= 0x3723, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
1862 00:39:02.150601 CH1 RK0: MR19=606, MR18=3723
1863 00:39:02.150653 CH1_RK0: MR19=0x606, MR18=0x3723, DQSOSC=395, MR23=63, INC=94, DEC=63
1864 00:39:02.150706
1865 00:39:02.150758 ----->DramcWriteLeveling(PI) begin...
1866 00:39:02.150811 ==
1867 00:39:02.150863 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 00:39:02.150916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 00:39:02.150968 ==
1870 00:39:02.151020 Write leveling (Byte 0): 26 => 26
1871 00:39:02.151072 Write leveling (Byte 1): 32 => 32
1872 00:39:02.151124 DramcWriteLeveling(PI) end<-----
1873 00:39:02.151176
1874 00:39:02.151227 ==
1875 00:39:02.151278 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 00:39:02.151330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 00:39:02.151383 ==
1878 00:39:02.151434 [Gating] SW mode calibration
1879 00:39:02.151486 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 00:39:02.151540 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 00:39:02.151593 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 00:39:02.151646 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1883 00:39:02.151698 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:39:02.151750 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:39:02.151803 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:39:02.151855 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:39:02.151908 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:39:02.151960 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:39:02.152035 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:39:02.152091 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:39:02.152144 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:39:02.152196 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:39:02.152249 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:39:02.152301 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:39:02.152353 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:39:02.152406 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:39:02.152458 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:39:02.152714 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1899 00:39:02.152774 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1900 00:39:02.152828 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:39:02.152880 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:39:02.152933 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:39:02.152986 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:39:02.153039 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:39:02.153091 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:39:02.153142 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:39:02.153194 0 9 8 | B1->B0 | 3030 2727 | 1 1 | (1 1) (0 0)
1908 00:39:02.153246 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 00:39:02.153298 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 00:39:02.153350 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 00:39:02.153402 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 00:39:02.153454 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 00:39:02.153508 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 00:39:02.153560 0 10 4 | B1->B0 | 3131 3333 | 0 1 | (0 1) (1 1)
1915 00:39:02.153612 0 10 8 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 1)
1916 00:39:02.153664 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:39:02.153717 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:39:02.153769 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:39:02.153822 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 00:39:02.153874 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 00:39:02.153926 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 00:39:02.153978 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1923 00:39:02.154030 0 11 8 | B1->B0 | 4242 3c3c | 0 0 | (0 0) (1 1)
1924 00:39:02.154082 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 00:39:02.154134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 00:39:02.154220 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 00:39:02.154287 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 00:39:02.154339 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 00:39:02.154391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 00:39:02.154443 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 00:39:02.154496 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:39:02.154548 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:39:02.154600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:39:02.154652 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:39:02.154705 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:39:02.154757 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:39:02.154810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:39:02.154862 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:39:02.154913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:39:02.154965 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:39:02.155016 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:39:02.155068 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:39:02.155142 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:39:02.155198 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:39:02.155251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 00:39:02.155305 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1947 00:39:02.155357 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 00:39:02.155410 Total UI for P1: 0, mck2ui 16
1949 00:39:02.155464 best dqsien dly found for B0: ( 0, 14, 6)
1950 00:39:02.155516 Total UI for P1: 0, mck2ui 16
1951 00:39:02.155569 best dqsien dly found for B1: ( 0, 14, 4)
1952 00:39:02.155622 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1953 00:39:02.155675 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1954 00:39:02.155726
1955 00:39:02.155778 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1956 00:39:02.155830 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1957 00:39:02.155882 [Gating] SW calibration Done
1958 00:39:02.155935 ==
1959 00:39:02.155987 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 00:39:02.156039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 00:39:02.156092 ==
1962 00:39:02.156144 RX Vref Scan: 0
1963 00:39:02.156196
1964 00:39:02.156248 RX Vref 0 -> 0, step: 1
1965 00:39:02.156299
1966 00:39:02.156351 RX Delay -130 -> 252, step: 16
1967 00:39:02.156403 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1968 00:39:02.156455 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1969 00:39:02.156507 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1970 00:39:02.156559 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1971 00:39:02.156612 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1972 00:39:02.156663 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1973 00:39:02.156715 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1974 00:39:02.156767 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1975 00:39:02.156819 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1976 00:39:02.156871 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1977 00:39:02.156923 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1978 00:39:02.156975 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1979 00:39:02.157027 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1980 00:39:02.157078 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1981 00:39:02.157130 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1982 00:39:02.157182 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1983 00:39:02.157235 ==
1984 00:39:02.348661 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 00:39:02.349203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 00:39:02.349571 ==
1987 00:39:02.349906 DQS Delay:
1988 00:39:02.350255 DQS0 = 0, DQS1 = 0
1989 00:39:02.350578 DQM Delay:
1990 00:39:02.350890 DQM0 = 87, DQM1 = 78
1991 00:39:02.351199 DQ Delay:
1992 00:39:02.351502 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1993 00:39:02.351807 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1994 00:39:02.352110 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1995 00:39:02.352859 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1996 00:39:02.353201
1997 00:39:02.353508
1998 00:39:02.353807 ==
1999 00:39:02.354103 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 00:39:02.354488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 00:39:02.354800 ==
2002 00:39:02.355099
2003 00:39:02.355394
2004 00:39:02.355688 TX Vref Scan disable
2005 00:39:02.355991 == TX Byte 0 ==
2006 00:39:02.356307 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2007 00:39:02.356585 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2008 00:39:02.356853 == TX Byte 1 ==
2009 00:39:02.357122 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2010 00:39:02.357395 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2011 00:39:02.357667 ==
2012 00:39:02.357932 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 00:39:02.358223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 00:39:02.358498 ==
2015 00:39:02.358772 TX Vref=22, minBit 1, minWin=27, winSum=447
2016 00:39:02.359045 TX Vref=24, minBit 8, minWin=27, winSum=449
2017 00:39:02.359319 TX Vref=26, minBit 9, minWin=26, winSum=447
2018 00:39:02.359591 TX Vref=28, minBit 8, minWin=27, winSum=450
2019 00:39:02.359862 TX Vref=30, minBit 8, minWin=27, winSum=450
2020 00:39:02.360133 TX Vref=32, minBit 8, minWin=27, winSum=447
2021 00:39:02.360402 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
2022 00:39:02.360676
2023 00:39:02.360944 Final TX Range 1 Vref 28
2024 00:39:02.361217
2025 00:39:02.361484 ==
2026 00:39:02.361750 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 00:39:02.362021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 00:39:02.362316 ==
2029 00:39:02.362584
2030 00:39:02.362850
2031 00:39:02.363116 TX Vref Scan disable
2032 00:39:02.363385 == TX Byte 0 ==
2033 00:39:02.363653 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2034 00:39:02.363921 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2035 00:39:02.364193 == TX Byte 1 ==
2036 00:39:02.364460 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2037 00:39:02.364728 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2038 00:39:02.364993
2039 00:39:02.365258 [DATLAT]
2040 00:39:02.365524 Freq=800, CH1 RK1
2041 00:39:02.365794
2042 00:39:02.366062 DATLAT Default: 0xa
2043 00:39:02.366348 0, 0xFFFF, sum = 0
2044 00:39:02.366627 1, 0xFFFF, sum = 0
2045 00:39:02.366902 2, 0xFFFF, sum = 0
2046 00:39:02.367173 3, 0xFFFF, sum = 0
2047 00:39:02.367445 4, 0xFFFF, sum = 0
2048 00:39:02.367720 5, 0xFFFF, sum = 0
2049 00:39:02.367992 6, 0xFFFF, sum = 0
2050 00:39:02.368266 7, 0xFFFF, sum = 0
2051 00:39:02.368537 8, 0xFFFF, sum = 0
2052 00:39:02.368810 9, 0x0, sum = 1
2053 00:39:02.369086 10, 0x0, sum = 2
2054 00:39:02.369361 11, 0x0, sum = 3
2055 00:39:02.369649 12, 0x0, sum = 4
2056 00:39:02.369925 best_step = 10
2057 00:39:02.370209
2058 00:39:02.370480 ==
2059 00:39:02.370748 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 00:39:02.371020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 00:39:02.371289 ==
2062 00:39:02.371558 RX Vref Scan: 0
2063 00:39:02.371825
2064 00:39:02.372091 RX Vref 0 -> 0, step: 1
2065 00:39:02.372360
2066 00:39:02.372627 RX Delay -95 -> 252, step: 8
2067 00:39:02.372895 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2068 00:39:02.373166 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2069 00:39:02.373435 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2070 00:39:02.373704 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2071 00:39:02.373971 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2072 00:39:02.374275 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2073 00:39:02.374473 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2074 00:39:02.374666 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2075 00:39:02.374859 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2076 00:39:02.375048 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2077 00:39:02.375241 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2078 00:39:02.375434 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2079 00:39:02.375626 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2080 00:39:02.375818 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2081 00:39:02.376011 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2082 00:39:02.376205 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2083 00:39:02.376398 ==
2084 00:39:02.376590 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 00:39:02.376785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 00:39:02.376978 ==
2087 00:39:02.377169 DQS Delay:
2088 00:39:02.377360 DQS0 = 0, DQS1 = 0
2089 00:39:02.377552 DQM Delay:
2090 00:39:02.377742 DQM0 = 87, DQM1 = 79
2091 00:39:02.377935 DQ Delay:
2092 00:39:02.378127 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2093 00:39:02.378335 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2094 00:39:02.378529 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2095 00:39:02.378726 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2096 00:39:02.378921
2097 00:39:02.379113
2098 00:39:02.379307 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2099 00:39:02.379457 CH1 RK1: MR19=606, MR18=1C15
2100 00:39:02.379604 CH1_RK1: MR19=0x606, MR18=0x1C15, DQSOSC=402, MR23=63, INC=91, DEC=60
2101 00:39:02.379752 [RxdqsGatingPostProcess] freq 800
2102 00:39:02.379899 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 00:39:02.380047 Pre-setting of DQS Precalculation
2104 00:39:02.380195 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 00:39:02.380343 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 00:39:02.380491 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 00:39:02.380639
2108 00:39:02.380783
2109 00:39:02.380927 [Calibration Summary] 1600 Mbps
2110 00:39:02.381072 CH 0, Rank 0
2111 00:39:02.381219 SW Impedance : PASS
2112 00:39:02.381365 DUTY Scan : NO K
2113 00:39:02.381513 ZQ Calibration : PASS
2114 00:39:02.381659 Jitter Meter : NO K
2115 00:39:02.381806 CBT Training : PASS
2116 00:39:02.381952 Write leveling : PASS
2117 00:39:02.382097 RX DQS gating : PASS
2118 00:39:02.382255 RX DQ/DQS(RDDQC) : PASS
2119 00:39:02.382402 TX DQ/DQS : PASS
2120 00:39:02.382548 RX DATLAT : PASS
2121 00:39:02.382695 RX DQ/DQS(Engine): PASS
2122 00:39:02.382839 TX OE : NO K
2123 00:39:02.382986 All Pass.
2124 00:39:02.383132
2125 00:39:02.383277 CH 0, Rank 1
2126 00:39:02.383422 SW Impedance : PASS
2127 00:39:02.383568 DUTY Scan : NO K
2128 00:39:02.383713 ZQ Calibration : PASS
2129 00:39:02.383859 Jitter Meter : NO K
2130 00:39:02.384005 CBT Training : PASS
2131 00:39:02.384151 Write leveling : PASS
2132 00:39:02.384308 RX DQS gating : PASS
2133 00:39:02.384425 RX DQ/DQS(RDDQC) : PASS
2134 00:39:02.384542 TX DQ/DQS : PASS
2135 00:39:02.384658 RX DATLAT : PASS
2136 00:39:02.384774 RX DQ/DQS(Engine): PASS
2137 00:39:02.384891 TX OE : NO K
2138 00:39:02.385008 All Pass.
2139 00:39:02.385124
2140 00:39:02.385239 CH 1, Rank 0
2141 00:39:02.385355 SW Impedance : PASS
2142 00:39:02.385472 DUTY Scan : NO K
2143 00:39:02.385588 ZQ Calibration : PASS
2144 00:39:02.385951 Jitter Meter : NO K
2145 00:39:02.386086 CBT Training : PASS
2146 00:39:02.386221 Write leveling : PASS
2147 00:39:02.386341 RX DQS gating : PASS
2148 00:39:02.386459 RX DQ/DQS(RDDQC) : PASS
2149 00:39:02.386577 TX DQ/DQS : PASS
2150 00:39:02.386696 RX DATLAT : PASS
2151 00:39:02.386813 RX DQ/DQS(Engine): PASS
2152 00:39:02.386929 TX OE : NO K
2153 00:39:02.387047 All Pass.
2154 00:39:02.387164
2155 00:39:02.387282 CH 1, Rank 1
2156 00:39:02.387398 SW Impedance : PASS
2157 00:39:02.387516 DUTY Scan : NO K
2158 00:39:02.387632 ZQ Calibration : PASS
2159 00:39:02.387749 Jitter Meter : NO K
2160 00:39:02.387865 CBT Training : PASS
2161 00:39:02.387983 Write leveling : PASS
2162 00:39:02.388101 RX DQS gating : PASS
2163 00:39:02.388219 RX DQ/DQS(RDDQC) : PASS
2164 00:39:02.388335 TX DQ/DQS : PASS
2165 00:39:02.388452 RX DATLAT : PASS
2166 00:39:02.388569 RX DQ/DQS(Engine): PASS
2167 00:39:02.388686 TX OE : NO K
2168 00:39:02.388803 All Pass.
2169 00:39:02.388919
2170 00:39:02.389035 DramC Write-DBI off
2171 00:39:02.389152 PER_BANK_REFRESH: Hybrid Mode
2172 00:39:02.389283 TX_TRACKING: ON
2173 00:39:02.389382 [GetDramInforAfterCalByMRR] Vendor 6.
2174 00:39:02.389480 [GetDramInforAfterCalByMRR] Revision 606.
2175 00:39:02.389579 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 00:39:02.389677 MR0 0x3b3b
2177 00:39:02.389775 MR8 0x5151
2178 00:39:02.389872 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 00:39:02.389971
2180 00:39:02.390069 MR0 0x3b3b
2181 00:39:02.390172 MR8 0x5151
2182 00:39:02.390271 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 00:39:02.390371
2184 00:39:02.390469 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 00:39:02.390570 [FAST_K] Save calibration result to emmc
2186 00:39:02.390668 [FAST_K] Save calibration result to emmc
2187 00:39:02.390767 dram_init: config_dvfs: 1
2188 00:39:02.390865 dramc_set_vcore_voltage set vcore to 662500
2189 00:39:02.390963 Read voltage for 1200, 2
2190 00:39:02.391061 Vio18 = 0
2191 00:39:02.391159 Vcore = 662500
2192 00:39:02.391257 Vdram = 0
2193 00:39:02.391354 Vddq = 0
2194 00:39:02.391451 Vmddr = 0
2195 00:39:02.391548 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 00:39:02.391646 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 00:39:02.391745 MEM_TYPE=3, freq_sel=15
2198 00:39:02.391842 sv_algorithm_assistance_LP4_1600
2199 00:39:02.391986 ============ PULL DRAM RESETB DOWN ============
2200 00:39:02.392151 ========== PULL DRAM RESETB DOWN end =========
2201 00:39:02.392258 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 00:39:02.392359 ===================================
2203 00:39:02.392460 LPDDR4 DRAM CONFIGURATION
2204 00:39:02.392560 ===================================
2205 00:39:02.392660 EX_ROW_EN[0] = 0x0
2206 00:39:02.392759 EX_ROW_EN[1] = 0x0
2207 00:39:02.392857 LP4Y_EN = 0x0
2208 00:39:02.392956 WORK_FSP = 0x0
2209 00:39:02.393054 WL = 0x4
2210 00:39:02.393151 RL = 0x4
2211 00:39:02.393248 BL = 0x2
2212 00:39:02.393345 RPST = 0x0
2213 00:39:02.393443 RD_PRE = 0x0
2214 00:39:02.393539 WR_PRE = 0x1
2215 00:39:02.393636 WR_PST = 0x0
2216 00:39:02.393732 DBI_WR = 0x0
2217 00:39:02.393830 DBI_RD = 0x0
2218 00:39:02.393928 OTF = 0x1
2219 00:39:02.394027 ===================================
2220 00:39:02.394126 ===================================
2221 00:39:02.394242 ANA top config
2222 00:39:02.394347 ===================================
2223 00:39:02.394432 DLL_ASYNC_EN = 0
2224 00:39:02.394516 ALL_SLAVE_EN = 0
2225 00:39:02.394600 NEW_RANK_MODE = 1
2226 00:39:02.394686 DLL_IDLE_MODE = 1
2227 00:39:02.394770 LP45_APHY_COMB_EN = 1
2228 00:39:02.394853 TX_ODT_DIS = 1
2229 00:39:02.394938 NEW_8X_MODE = 1
2230 00:39:02.395023 ===================================
2231 00:39:02.395108 ===================================
2232 00:39:02.395192 data_rate = 2400
2233 00:39:02.395276 CKR = 1
2234 00:39:02.395360 DQ_P2S_RATIO = 8
2235 00:39:02.395444 ===================================
2236 00:39:02.395529 CA_P2S_RATIO = 8
2237 00:39:02.395613 DQ_CA_OPEN = 0
2238 00:39:02.395696 DQ_SEMI_OPEN = 0
2239 00:39:02.395780 CA_SEMI_OPEN = 0
2240 00:39:02.395864 CA_FULL_RATE = 0
2241 00:39:02.395948 DQ_CKDIV4_EN = 0
2242 00:39:02.396033 CA_CKDIV4_EN = 0
2243 00:39:02.396117 CA_PREDIV_EN = 0
2244 00:39:02.396201 PH8_DLY = 17
2245 00:39:02.396286 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 00:39:02.396374 DQ_AAMCK_DIV = 4
2247 00:39:02.396459 CA_AAMCK_DIV = 4
2248 00:39:02.396543 CA_ADMCK_DIV = 4
2249 00:39:02.396626 DQ_TRACK_CA_EN = 0
2250 00:39:02.396711 CA_PICK = 1200
2251 00:39:02.396795 CA_MCKIO = 1200
2252 00:39:02.396878 MCKIO_SEMI = 0
2253 00:39:02.396961 PLL_FREQ = 2366
2254 00:39:02.397045 DQ_UI_PI_RATIO = 32
2255 00:39:02.397130 CA_UI_PI_RATIO = 0
2256 00:39:02.397214 ===================================
2257 00:39:02.397299 ===================================
2258 00:39:02.397384 memory_type:LPDDR4
2259 00:39:02.397468 GP_NUM : 10
2260 00:39:02.397553 SRAM_EN : 1
2261 00:39:02.397636 MD32_EN : 0
2262 00:39:02.397719 ===================================
2263 00:39:02.397804 [ANA_INIT] >>>>>>>>>>>>>>
2264 00:39:02.397889 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 00:39:02.397974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 00:39:02.398059 ===================================
2267 00:39:02.398144 data_rate = 2400,PCW = 0X5b00
2268 00:39:02.398242 ===================================
2269 00:39:02.398327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 00:39:02.398412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 00:39:02.398497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 00:39:02.398582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 00:39:02.398667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 00:39:02.398752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 00:39:02.398838 [ANA_INIT] flow start
2276 00:39:02.398923 [ANA_INIT] PLL >>>>>>>>
2277 00:39:02.399007 [ANA_INIT] PLL <<<<<<<<
2278 00:39:02.399091 [ANA_INIT] MIDPI >>>>>>>>
2279 00:39:02.399174 [ANA_INIT] MIDPI <<<<<<<<
2280 00:39:02.399258 [ANA_INIT] DLL >>>>>>>>
2281 00:39:02.399346 [ANA_INIT] DLL <<<<<<<<
2282 00:39:02.399628 [ANA_INIT] flow end
2283 00:39:02.399713 ============ LP4 DIFF to SE enter ============
2284 00:39:02.399790 ============ LP4 DIFF to SE exit ============
2285 00:39:02.399865 [ANA_INIT] <<<<<<<<<<<<<
2286 00:39:02.399940 [Flow] Enable top DCM control >>>>>
2287 00:39:02.400014 [Flow] Enable top DCM control <<<<<
2288 00:39:02.400089 Enable DLL master slave shuffle
2289 00:39:02.400163 ==============================================================
2290 00:39:02.400238 Gating Mode config
2291 00:39:02.400311 ==============================================================
2292 00:39:02.400386 Config description:
2293 00:39:02.400460 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 00:39:02.400536 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 00:39:02.400639 SELPH_MODE 0: By rank 1: By Phase
2296 00:39:02.400716 ==============================================================
2297 00:39:02.400791 GAT_TRACK_EN = 1
2298 00:39:02.400866 RX_GATING_MODE = 2
2299 00:39:02.400940 RX_GATING_TRACK_MODE = 2
2300 00:39:02.401013 SELPH_MODE = 1
2301 00:39:02.401087 PICG_EARLY_EN = 1
2302 00:39:02.401160 VALID_LAT_VALUE = 1
2303 00:39:02.401234 ==============================================================
2304 00:39:02.401309 Enter into Gating configuration >>>>
2305 00:39:02.401383 Exit from Gating configuration <<<<
2306 00:39:02.401457 Enter into DVFS_PRE_config >>>>>
2307 00:39:02.401530 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 00:39:02.401606 Exit from DVFS_PRE_config <<<<<
2309 00:39:02.401680 Enter into PICG configuration >>>>
2310 00:39:02.401754 Exit from PICG configuration <<<<
2311 00:39:02.401827 [RX_INPUT] configuration >>>>>
2312 00:39:02.401901 [RX_INPUT] configuration <<<<<
2313 00:39:02.401985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 00:39:02.402109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 00:39:02.402223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 00:39:02.402301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 00:39:02.402377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 00:39:02.402452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 00:39:02.402527 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 00:39:02.402602 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 00:39:02.402677 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 00:39:02.402751 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 00:39:02.402826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 00:39:02.402900 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 00:39:02.402975 ===================================
2326 00:39:02.403049 LPDDR4 DRAM CONFIGURATION
2327 00:39:02.403124 ===================================
2328 00:39:02.403198 EX_ROW_EN[0] = 0x0
2329 00:39:02.403272 EX_ROW_EN[1] = 0x0
2330 00:39:02.403346 LP4Y_EN = 0x0
2331 00:39:02.403420 WORK_FSP = 0x0
2332 00:39:02.403493 WL = 0x4
2333 00:39:02.403566 RL = 0x4
2334 00:39:02.403640 BL = 0x2
2335 00:39:02.403714 RPST = 0x0
2336 00:39:02.403788 RD_PRE = 0x0
2337 00:39:02.403862 WR_PRE = 0x1
2338 00:39:02.403936 WR_PST = 0x0
2339 00:39:02.404009 DBI_WR = 0x0
2340 00:39:02.404083 DBI_RD = 0x0
2341 00:39:02.404156 OTF = 0x1
2342 00:39:02.404230 ===================================
2343 00:39:02.404316 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 00:39:02.404383 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 00:39:02.404449 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 00:39:02.404515 ===================================
2347 00:39:02.404581 LPDDR4 DRAM CONFIGURATION
2348 00:39:02.404647 ===================================
2349 00:39:02.404713 EX_ROW_EN[0] = 0x10
2350 00:39:02.404779 EX_ROW_EN[1] = 0x0
2351 00:39:02.404845 LP4Y_EN = 0x0
2352 00:39:02.404910 WORK_FSP = 0x0
2353 00:39:02.404977 WL = 0x4
2354 00:39:02.405042 RL = 0x4
2355 00:39:02.405108 BL = 0x2
2356 00:39:02.405173 RPST = 0x0
2357 00:39:02.405239 RD_PRE = 0x0
2358 00:39:02.405303 WR_PRE = 0x1
2359 00:39:02.405369 WR_PST = 0x0
2360 00:39:02.405434 DBI_WR = 0x0
2361 00:39:02.405500 DBI_RD = 0x0
2362 00:39:02.405565 OTF = 0x1
2363 00:39:02.405630 ===================================
2364 00:39:02.405696 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 00:39:02.405762 ==
2366 00:39:02.405827 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 00:39:02.405892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 00:39:02.405958 ==
2369 00:39:02.406068 [Duty_Offset_Calibration]
2370 00:39:02.406178 B0:1 B1:-1 CA:0
2371 00:39:02.406248
2372 00:39:02.406314 [DutyScan_Calibration_Flow] k_type=0
2373 00:39:02.406380
2374 00:39:02.406446 ==CLK 0==
2375 00:39:02.406511 Final CLK duty delay cell = 0
2376 00:39:02.406577 [0] MAX Duty = 5094%(X100), DQS PI = 16
2377 00:39:02.406644 [0] MIN Duty = 4875%(X100), DQS PI = 8
2378 00:39:02.406709 [0] AVG Duty = 4984%(X100)
2379 00:39:02.406774
2380 00:39:02.406839 CH0 CLK Duty spec in!! Max-Min= 219%
2381 00:39:02.406905 [DutyScan_Calibration_Flow] ====Done====
2382 00:39:02.406970
2383 00:39:02.407034 [DutyScan_Calibration_Flow] k_type=1
2384 00:39:02.407099
2385 00:39:02.407164 ==DQS 0 ==
2386 00:39:02.407229 Final DQS duty delay cell = -4
2387 00:39:02.407295 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2388 00:39:02.407360 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2389 00:39:02.407425 [-4] AVG Duty = 4968%(X100)
2390 00:39:02.407490
2391 00:39:02.407555 ==DQS 1 ==
2392 00:39:02.407620 Final DQS duty delay cell = 0
2393 00:39:02.407685 [0] MAX Duty = 5124%(X100), DQS PI = 6
2394 00:39:02.407751 [0] MIN Duty = 5000%(X100), DQS PI = 22
2395 00:39:02.407817 [0] AVG Duty = 5062%(X100)
2396 00:39:02.407881
2397 00:39:02.407945 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2398 00:39:02.408010
2399 00:39:02.408075 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2400 00:39:02.408140 [DutyScan_Calibration_Flow] ====Done====
2401 00:39:02.408205
2402 00:39:02.408484 [DutyScan_Calibration_Flow] k_type=3
2403 00:39:02.408565
2404 00:39:02.408632 ==DQM 0 ==
2405 00:39:02.408698 Final DQM duty delay cell = 0
2406 00:39:02.408764 [0] MAX Duty = 5062%(X100), DQS PI = 22
2407 00:39:02.408831 [0] MIN Duty = 4844%(X100), DQS PI = 8
2408 00:39:02.408896 [0] AVG Duty = 4953%(X100)
2409 00:39:02.408961
2410 00:39:02.409026 ==DQM 1 ==
2411 00:39:02.409091 Final DQM duty delay cell = 4
2412 00:39:02.409158 [4] MAX Duty = 5156%(X100), DQS PI = 8
2413 00:39:02.409223 [4] MIN Duty = 5000%(X100), DQS PI = 24
2414 00:39:02.409299 [4] AVG Duty = 5078%(X100)
2415 00:39:02.409358
2416 00:39:02.409416 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2417 00:39:02.409475
2418 00:39:02.409533 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2419 00:39:02.409593 [DutyScan_Calibration_Flow] ====Done====
2420 00:39:02.409652
2421 00:39:02.409710 [DutyScan_Calibration_Flow] k_type=2
2422 00:39:02.409768
2423 00:39:02.409827 ==DQ 0 ==
2424 00:39:02.409886 Final DQ duty delay cell = -4
2425 00:39:02.409946 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2426 00:39:02.410004 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2427 00:39:02.410064 [-4] AVG Duty = 4953%(X100)
2428 00:39:02.410122
2429 00:39:02.410190 ==DQ 1 ==
2430 00:39:02.410251 Final DQ duty delay cell = -4
2431 00:39:02.410310 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2432 00:39:02.410370 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2433 00:39:02.410429 [-4] AVG Duty = 4922%(X100)
2434 00:39:02.410488
2435 00:39:02.410547 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2436 00:39:02.410606
2437 00:39:02.410665 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2438 00:39:02.410725 [DutyScan_Calibration_Flow] ====Done====
2439 00:39:02.410783 ==
2440 00:39:02.410842 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 00:39:02.410901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 00:39:02.410961 ==
2443 00:39:02.411020 [Duty_Offset_Calibration]
2444 00:39:02.411078 B0:-1 B1:1 CA:2
2445 00:39:02.411139
2446 00:39:02.411198 [DutyScan_Calibration_Flow] k_type=0
2447 00:39:02.411257
2448 00:39:02.411315 ==CLK 0==
2449 00:39:02.411374 Final CLK duty delay cell = 0
2450 00:39:02.411433 [0] MAX Duty = 5156%(X100), DQS PI = 22
2451 00:39:02.411492 [0] MIN Duty = 4969%(X100), DQS PI = 60
2452 00:39:02.411551 [0] AVG Duty = 5062%(X100)
2453 00:39:02.411610
2454 00:39:02.411669 CH1 CLK Duty spec in!! Max-Min= 187%
2455 00:39:02.411729 [DutyScan_Calibration_Flow] ====Done====
2456 00:39:02.411787
2457 00:39:02.411846 [DutyScan_Calibration_Flow] k_type=1
2458 00:39:02.411905
2459 00:39:02.411964 ==DQS 0 ==
2460 00:39:02.412023 Final DQS duty delay cell = 0
2461 00:39:02.412082 [0] MAX Duty = 5125%(X100), DQS PI = 50
2462 00:39:02.412141 [0] MIN Duty = 4907%(X100), DQS PI = 6
2463 00:39:02.412200 [0] AVG Duty = 5016%(X100)
2464 00:39:02.412260
2465 00:39:02.412317 ==DQS 1 ==
2466 00:39:02.412376 Final DQS duty delay cell = 0
2467 00:39:02.412436 [0] MAX Duty = 5062%(X100), DQS PI = 12
2468 00:39:02.412495 [0] MIN Duty = 4969%(X100), DQS PI = 54
2469 00:39:02.412554 [0] AVG Duty = 5015%(X100)
2470 00:39:02.412611
2471 00:39:02.412670 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2472 00:39:02.412729
2473 00:39:02.412788 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2474 00:39:02.412847 [DutyScan_Calibration_Flow] ====Done====
2475 00:39:02.412906
2476 00:39:02.412964 [DutyScan_Calibration_Flow] k_type=3
2477 00:39:02.413023
2478 00:39:02.413080 ==DQM 0 ==
2479 00:39:02.413139 Final DQM duty delay cell = -4
2480 00:39:02.413198 [-4] MAX Duty = 5031%(X100), DQS PI = 36
2481 00:39:02.413257 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2482 00:39:02.413316 [-4] AVG Duty = 4937%(X100)
2483 00:39:02.413375
2484 00:39:02.413433 ==DQM 1 ==
2485 00:39:02.413492 Final DQM duty delay cell = 0
2486 00:39:02.413551 [0] MAX Duty = 5187%(X100), DQS PI = 6
2487 00:39:02.413609 [0] MIN Duty = 4969%(X100), DQS PI = 28
2488 00:39:02.413669 [0] AVG Duty = 5078%(X100)
2489 00:39:02.413728
2490 00:39:02.413786 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2491 00:39:02.413844
2492 00:39:02.413902 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2493 00:39:02.413961 [DutyScan_Calibration_Flow] ====Done====
2494 00:39:02.414019
2495 00:39:02.414077 [DutyScan_Calibration_Flow] k_type=2
2496 00:39:02.414135
2497 00:39:02.414216 ==DQ 0 ==
2498 00:39:02.414279 Final DQ duty delay cell = 0
2499 00:39:02.414348 [0] MAX Duty = 5156%(X100), DQS PI = 28
2500 00:39:02.414402 [0] MIN Duty = 4907%(X100), DQS PI = 6
2501 00:39:02.414456 [0] AVG Duty = 5031%(X100)
2502 00:39:02.414509
2503 00:39:02.414563 ==DQ 1 ==
2504 00:39:02.414616 Final DQ duty delay cell = 0
2505 00:39:02.414670 [0] MAX Duty = 5124%(X100), DQS PI = 10
2506 00:39:02.414723 [0] MIN Duty = 4969%(X100), DQS PI = 0
2507 00:39:02.414776 [0] AVG Duty = 5046%(X100)
2508 00:39:02.414829
2509 00:39:02.414882 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2510 00:39:02.414935
2511 00:39:02.414989 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2512 00:39:02.415043 [DutyScan_Calibration_Flow] ====Done====
2513 00:39:02.415097 nWR fixed to 30
2514 00:39:02.415151 [ModeRegInit_LP4] CH0 RK0
2515 00:39:02.415205 [ModeRegInit_LP4] CH0 RK1
2516 00:39:02.415258 [ModeRegInit_LP4] CH1 RK0
2517 00:39:02.415311 [ModeRegInit_LP4] CH1 RK1
2518 00:39:02.415364 match AC timing 7
2519 00:39:02.415417 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 00:39:02.415472 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 00:39:02.415525 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 00:39:02.415579 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 00:39:02.415634 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 00:39:02.415687 ==
2525 00:39:02.415740 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 00:39:02.415794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 00:39:02.415849 ==
2528 00:39:02.415902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 00:39:02.415958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2530 00:39:02.416012 [CA 0] Center 39 (9~70) winsize 62
2531 00:39:02.416065 [CA 1] Center 39 (9~70) winsize 62
2532 00:39:02.416119 [CA 2] Center 35 (5~66) winsize 62
2533 00:39:02.416173 [CA 3] Center 35 (5~65) winsize 61
2534 00:39:02.416225 [CA 4] Center 33 (3~64) winsize 62
2535 00:39:02.416279 [CA 5] Center 33 (4~63) winsize 60
2536 00:39:02.416332
2537 00:39:02.416385 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2538 00:39:02.416438
2539 00:39:02.416490 [CATrainingPosCal] consider 1 rank data
2540 00:39:02.416543 u2DelayCellTimex100 = 270/100 ps
2541 00:39:02.416597 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2542 00:39:02.416650 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2543 00:39:02.416704 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 00:39:02.416757 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2545 00:39:02.416811 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2546 00:39:02.416864 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2547 00:39:02.416917
2548 00:39:02.416970 CA PerBit enable=1, Macro0, CA PI delay=33
2549 00:39:02.417024
2550 00:39:02.417078 [CBTSetCACLKResult] CA Dly = 33
2551 00:39:02.417131 CS Dly: 8 (0~39)
2552 00:39:02.417183 ==
2553 00:39:02.417430 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 00:39:02.417491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 00:39:02.417547 ==
2556 00:39:02.417601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 00:39:02.417655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2558 00:39:02.417709 [CA 0] Center 39 (9~70) winsize 62
2559 00:39:02.417762 [CA 1] Center 39 (9~70) winsize 62
2560 00:39:02.417816 [CA 2] Center 35 (5~66) winsize 62
2561 00:39:02.417870 [CA 3] Center 34 (4~65) winsize 62
2562 00:39:02.417922 [CA 4] Center 33 (3~64) winsize 62
2563 00:39:02.417976 [CA 5] Center 33 (3~63) winsize 61
2564 00:39:02.418029
2565 00:39:02.418082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2566 00:39:02.418136
2567 00:39:02.418203 [CATrainingPosCal] consider 2 rank data
2568 00:39:02.418260 u2DelayCellTimex100 = 270/100 ps
2569 00:39:02.418314 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2570 00:39:02.418368 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2571 00:39:02.418422 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2572 00:39:02.418475 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2573 00:39:02.418529 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2574 00:39:02.418583 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2575 00:39:02.418636
2576 00:39:02.418689 CA PerBit enable=1, Macro0, CA PI delay=33
2577 00:39:02.418743
2578 00:39:02.418796 [CBTSetCACLKResult] CA Dly = 33
2579 00:39:02.418850 CS Dly: 9 (0~41)
2580 00:39:02.418903
2581 00:39:02.418957 ----->DramcWriteLeveling(PI) begin...
2582 00:39:02.419011 ==
2583 00:39:02.419065 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 00:39:02.419118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 00:39:02.419172 ==
2586 00:39:02.419225 Write leveling (Byte 0): 31 => 31
2587 00:39:02.419292 Write leveling (Byte 1): 29 => 29
2588 00:39:02.419344 DramcWriteLeveling(PI) end<-----
2589 00:39:02.419396
2590 00:39:02.419448 ==
2591 00:39:02.419500 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 00:39:02.419552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 00:39:02.419605 ==
2594 00:39:02.419657 [Gating] SW mode calibration
2595 00:39:02.419710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 00:39:02.419764 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 00:39:02.419816 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2598 00:39:02.419869 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (1 1) (1 1)
2599 00:39:02.419921 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2600 00:39:02.419974 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 00:39:02.420026 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 00:39:02.420078 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 00:39:02.420131 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2604 00:39:02.420183 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
2605 00:39:02.420235 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
2606 00:39:02.420289 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2607 00:39:02.420342 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 00:39:02.420394 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 00:39:02.420447 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 00:39:02.420499 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 00:39:02.420552 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 00:39:02.420604 1 0 28 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
2613 00:39:02.420656 1 1 0 | B1->B0 | 2828 4545 | 0 0 | (1 1) (0 0)
2614 00:39:02.420708 1 1 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
2615 00:39:02.420761 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 00:39:02.420814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 00:39:02.420866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 00:39:02.420918 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 00:39:02.420971 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2620 00:39:02.421023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 00:39:02.421075 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 00:39:02.421127 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 00:39:02.421180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:39:02.421233 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:39:02.421285 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:39:02.421338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:39:02.421390 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:39:02.421443 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:39:02.421495 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:39:02.421547 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:39:02.421600 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:39:02.421652 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 00:39:02.421705 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 00:39:02.421757 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 00:39:02.421809 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 00:39:02.421861 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 00:39:02.421914 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 00:39:02.421966 Total UI for P1: 0, mck2ui 16
2639 00:39:02.422019 best dqsien dly found for B0: ( 1, 3, 28)
2640 00:39:02.422072 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 00:39:02.422125 Total UI for P1: 0, mck2ui 16
2642 00:39:02.422204 best dqsien dly found for B1: ( 1, 4, 0)
2643 00:39:02.422271 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2644 00:39:02.422324 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2645 00:39:02.422377
2646 00:39:02.422429 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2647 00:39:02.422481 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2648 00:39:02.422533 [Gating] SW calibration Done
2649 00:39:02.422586 ==
2650 00:39:02.422639 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 00:39:02.422691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 00:39:02.422744 ==
2653 00:39:02.422797 RX Vref Scan: 0
2654 00:39:02.422849
2655 00:39:02.422901 RX Vref 0 -> 0, step: 1
2656 00:39:02.422952
2657 00:39:02.423004 RX Delay -40 -> 252, step: 8
2658 00:39:02.423250 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2659 00:39:02.423309 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2660 00:39:02.423364 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2661 00:39:02.423417 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2662 00:39:02.423470 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2663 00:39:02.423522 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2664 00:39:02.423575 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2665 00:39:02.423628 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2666 00:39:02.423680 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2667 00:39:02.423733 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2668 00:39:02.423786 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2669 00:39:02.423838 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2670 00:39:02.423891 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2671 00:39:02.423943 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2672 00:39:02.423995 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2673 00:39:02.424048 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2674 00:39:02.424100 ==
2675 00:39:02.424153 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 00:39:02.424205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 00:39:02.424258 ==
2678 00:39:02.424311 DQS Delay:
2679 00:39:02.424364 DQS0 = 0, DQS1 = 0
2680 00:39:02.424416 DQM Delay:
2681 00:39:02.424468 DQM0 = 119, DQM1 = 106
2682 00:39:02.424520 DQ Delay:
2683 00:39:02.424573 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2684 00:39:02.424625 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2685 00:39:02.424678 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2686 00:39:02.424730 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2687 00:39:02.424782
2688 00:39:02.424834
2689 00:39:02.424885 ==
2690 00:39:02.424938 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 00:39:02.424990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 00:39:02.425043 ==
2693 00:39:02.425095
2694 00:39:02.425148
2695 00:39:02.425200 TX Vref Scan disable
2696 00:39:02.425252 == TX Byte 0 ==
2697 00:39:02.425305 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2698 00:39:02.425357 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2699 00:39:02.425410 == TX Byte 1 ==
2700 00:39:02.425462 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2701 00:39:02.425514 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2702 00:39:02.425566 ==
2703 00:39:02.425618 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 00:39:02.425671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 00:39:02.425723 ==
2706 00:39:02.425775 TX Vref=22, minBit 5, minWin=25, winSum=415
2707 00:39:02.425829 TX Vref=24, minBit 13, minWin=25, winSum=421
2708 00:39:02.425881 TX Vref=26, minBit 13, minWin=25, winSum=424
2709 00:39:02.425934 TX Vref=28, minBit 13, minWin=25, winSum=430
2710 00:39:02.425987 TX Vref=30, minBit 5, minWin=26, winSum=432
2711 00:39:02.426040 TX Vref=32, minBit 4, minWin=26, winSum=431
2712 00:39:02.426093 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2713 00:39:02.426146
2714 00:39:02.426231 Final TX Range 1 Vref 30
2715 00:39:02.426299
2716 00:39:02.426350 ==
2717 00:39:02.426403 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 00:39:02.426456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 00:39:02.426509 ==
2720 00:39:02.426562
2721 00:39:02.426614
2722 00:39:02.426665 TX Vref Scan disable
2723 00:39:02.426717 == TX Byte 0 ==
2724 00:39:02.426769 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2725 00:39:02.426822 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2726 00:39:02.426875 == TX Byte 1 ==
2727 00:39:02.426927 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2728 00:39:02.426980 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2729 00:39:02.427032
2730 00:39:02.427084 [DATLAT]
2731 00:39:02.427136 Freq=1200, CH0 RK0
2732 00:39:02.427188
2733 00:39:02.427240 DATLAT Default: 0xd
2734 00:39:02.427292 0, 0xFFFF, sum = 0
2735 00:39:02.427346 1, 0xFFFF, sum = 0
2736 00:39:02.427398 2, 0xFFFF, sum = 0
2737 00:39:02.427452 3, 0xFFFF, sum = 0
2738 00:39:02.427505 4, 0xFFFF, sum = 0
2739 00:39:02.427557 5, 0xFFFF, sum = 0
2740 00:39:02.427611 6, 0xFFFF, sum = 0
2741 00:39:02.427664 7, 0xFFFF, sum = 0
2742 00:39:02.427718 8, 0xFFFF, sum = 0
2743 00:39:02.427771 9, 0xFFFF, sum = 0
2744 00:39:02.427824 10, 0xFFFF, sum = 0
2745 00:39:02.427878 11, 0xFFFF, sum = 0
2746 00:39:02.427930 12, 0x0, sum = 1
2747 00:39:02.427983 13, 0x0, sum = 2
2748 00:39:02.428036 14, 0x0, sum = 3
2749 00:39:02.428089 15, 0x0, sum = 4
2750 00:39:02.428142 best_step = 13
2751 00:39:02.428194
2752 00:39:02.428246 ==
2753 00:39:02.428299 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 00:39:02.428351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 00:39:02.428404 ==
2756 00:39:02.428457 RX Vref Scan: 1
2757 00:39:02.428509
2758 00:39:02.428561 Set Vref Range= 32 -> 127
2759 00:39:02.428613
2760 00:39:02.428665 RX Vref 32 -> 127, step: 1
2761 00:39:02.428718
2762 00:39:02.428770 RX Delay -21 -> 252, step: 4
2763 00:39:02.428823
2764 00:39:02.428875 Set Vref, RX VrefLevel [Byte0]: 32
2765 00:39:02.428929 [Byte1]: 32
2766 00:39:02.428981
2767 00:39:02.429033 Set Vref, RX VrefLevel [Byte0]: 33
2768 00:39:02.429085 [Byte1]: 33
2769 00:39:02.429137
2770 00:39:02.429189 Set Vref, RX VrefLevel [Byte0]: 34
2771 00:39:02.429242 [Byte1]: 34
2772 00:39:02.429294
2773 00:39:02.429345 Set Vref, RX VrefLevel [Byte0]: 35
2774 00:39:02.429398 [Byte1]: 35
2775 00:39:02.429450
2776 00:39:02.429502 Set Vref, RX VrefLevel [Byte0]: 36
2777 00:39:02.429553 [Byte1]: 36
2778 00:39:02.429605
2779 00:39:02.429657 Set Vref, RX VrefLevel [Byte0]: 37
2780 00:39:02.429709 [Byte1]: 37
2781 00:39:02.429761
2782 00:39:02.429813 Set Vref, RX VrefLevel [Byte0]: 38
2783 00:39:02.429865 [Byte1]: 38
2784 00:39:02.429917
2785 00:39:02.429969 Set Vref, RX VrefLevel [Byte0]: 39
2786 00:39:02.430022 [Byte1]: 39
2787 00:39:02.430074
2788 00:39:02.430125 Set Vref, RX VrefLevel [Byte0]: 40
2789 00:39:02.430182 [Byte1]: 40
2790 00:39:02.430270
2791 00:39:02.430322 Set Vref, RX VrefLevel [Byte0]: 41
2792 00:39:02.430375 [Byte1]: 41
2793 00:39:02.430427
2794 00:39:02.430478 Set Vref, RX VrefLevel [Byte0]: 42
2795 00:39:02.430530 [Byte1]: 42
2796 00:39:02.430582
2797 00:39:02.430634 Set Vref, RX VrefLevel [Byte0]: 43
2798 00:39:02.430686 [Byte1]: 43
2799 00:39:02.430737
2800 00:39:02.430794 Set Vref, RX VrefLevel [Byte0]: 44
2801 00:39:02.430855 [Byte1]: 44
2802 00:39:02.430908
2803 00:39:02.430960 Set Vref, RX VrefLevel [Byte0]: 45
2804 00:39:02.431013 [Byte1]: 45
2805 00:39:02.431065
2806 00:39:02.431118 Set Vref, RX VrefLevel [Byte0]: 46
2807 00:39:02.431171 [Byte1]: 46
2808 00:39:02.431224
2809 00:39:02.431276 Set Vref, RX VrefLevel [Byte0]: 47
2810 00:39:02.431329 [Byte1]: 47
2811 00:39:02.431381
2812 00:39:02.431433 Set Vref, RX VrefLevel [Byte0]: 48
2813 00:39:02.431679 [Byte1]: 48
2814 00:39:02.431741
2815 00:39:02.431795 Set Vref, RX VrefLevel [Byte0]: 49
2816 00:39:02.431848 [Byte1]: 49
2817 00:39:02.431901
2818 00:39:02.431953 Set Vref, RX VrefLevel [Byte0]: 50
2819 00:39:02.432005 [Byte1]: 50
2820 00:39:02.432058
2821 00:39:02.432110 Set Vref, RX VrefLevel [Byte0]: 51
2822 00:39:02.432162 [Byte1]: 51
2823 00:39:02.432214
2824 00:39:02.432266 Set Vref, RX VrefLevel [Byte0]: 52
2825 00:39:02.432319 [Byte1]: 52
2826 00:39:02.432371
2827 00:39:02.432423 Set Vref, RX VrefLevel [Byte0]: 53
2828 00:39:02.432475 [Byte1]: 53
2829 00:39:02.432527
2830 00:39:02.432579 Set Vref, RX VrefLevel [Byte0]: 54
2831 00:39:02.432632 [Byte1]: 54
2832 00:39:02.432684
2833 00:39:02.432736 Set Vref, RX VrefLevel [Byte0]: 55
2834 00:39:02.432788 [Byte1]: 55
2835 00:39:02.432841
2836 00:39:02.432892 Set Vref, RX VrefLevel [Byte0]: 56
2837 00:39:02.432944 [Byte1]: 56
2838 00:39:02.432997
2839 00:39:02.433048 Set Vref, RX VrefLevel [Byte0]: 57
2840 00:39:02.433101 [Byte1]: 57
2841 00:39:02.433153
2842 00:39:02.433205 Set Vref, RX VrefLevel [Byte0]: 58
2843 00:39:02.433257 [Byte1]: 58
2844 00:39:02.433309
2845 00:39:02.433361 Set Vref, RX VrefLevel [Byte0]: 59
2846 00:39:02.433412 [Byte1]: 59
2847 00:39:02.433465
2848 00:39:02.433517 Set Vref, RX VrefLevel [Byte0]: 60
2849 00:39:02.433569 [Byte1]: 60
2850 00:39:02.433621
2851 00:39:02.433673 Set Vref, RX VrefLevel [Byte0]: 61
2852 00:39:02.433725 [Byte1]: 61
2853 00:39:02.433777
2854 00:39:02.433829 Set Vref, RX VrefLevel [Byte0]: 62
2855 00:39:02.433881 [Byte1]: 62
2856 00:39:02.433933
2857 00:39:02.433985 Set Vref, RX VrefLevel [Byte0]: 63
2858 00:39:02.434037 [Byte1]: 63
2859 00:39:02.434089
2860 00:39:02.434141 Set Vref, RX VrefLevel [Byte0]: 64
2861 00:39:02.434230 [Byte1]: 64
2862 00:39:02.434296
2863 00:39:02.434348 Set Vref, RX VrefLevel [Byte0]: 65
2864 00:39:02.434400 [Byte1]: 65
2865 00:39:02.434453
2866 00:39:02.434504 Set Vref, RX VrefLevel [Byte0]: 66
2867 00:39:02.434556 [Byte1]: 66
2868 00:39:02.434608
2869 00:39:02.434660 Set Vref, RX VrefLevel [Byte0]: 67
2870 00:39:02.434712 [Byte1]: 67
2871 00:39:02.434764
2872 00:39:02.434815 Set Vref, RX VrefLevel [Byte0]: 68
2873 00:39:02.434868 [Byte1]: 68
2874 00:39:02.434919
2875 00:39:02.434971 Set Vref, RX VrefLevel [Byte0]: 69
2876 00:39:02.435023 [Byte1]: 69
2877 00:39:02.435075
2878 00:39:02.435127 Set Vref, RX VrefLevel [Byte0]: 70
2879 00:39:02.435179 [Byte1]: 70
2880 00:39:02.435230
2881 00:39:02.435282 Set Vref, RX VrefLevel [Byte0]: 71
2882 00:39:02.435335 [Byte1]: 71
2883 00:39:02.435387
2884 00:39:02.435439 Set Vref, RX VrefLevel [Byte0]: 72
2885 00:39:02.435490 [Byte1]: 72
2886 00:39:02.435542
2887 00:39:02.435594 Set Vref, RX VrefLevel [Byte0]: 73
2888 00:39:02.435646 [Byte1]: 73
2889 00:39:02.435699
2890 00:39:02.435750 Set Vref, RX VrefLevel [Byte0]: 74
2891 00:39:02.435803 [Byte1]: 74
2892 00:39:02.435855
2893 00:39:02.435906 Set Vref, RX VrefLevel [Byte0]: 75
2894 00:39:02.435958 [Byte1]: 75
2895 00:39:02.436010
2896 00:39:02.436061 Set Vref, RX VrefLevel [Byte0]: 76
2897 00:39:02.436113 [Byte1]: 76
2898 00:39:02.436165
2899 00:39:02.436217 Set Vref, RX VrefLevel [Byte0]: 77
2900 00:39:02.436270 [Byte1]: 77
2901 00:39:02.436322
2902 00:39:02.436374 Set Vref, RX VrefLevel [Byte0]: 78
2903 00:39:02.436426 [Byte1]: 78
2904 00:39:02.436478
2905 00:39:02.436530 Final RX Vref Byte 0 = 60 to rank0
2906 00:39:02.436583 Final RX Vref Byte 1 = 50 to rank0
2907 00:39:02.436635 Final RX Vref Byte 0 = 60 to rank1
2908 00:39:02.436688 Final RX Vref Byte 1 = 50 to rank1==
2909 00:39:02.436740 Dram Type= 6, Freq= 0, CH_0, rank 0
2910 00:39:02.436791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 00:39:02.436844 ==
2912 00:39:02.436896 DQS Delay:
2913 00:39:02.436947 DQS0 = 0, DQS1 = 0
2914 00:39:02.436999 DQM Delay:
2915 00:39:02.437051 DQM0 = 118, DQM1 = 107
2916 00:39:02.437103 DQ Delay:
2917 00:39:02.437156 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2918 00:39:02.437209 DQ4 =120, DQ5 =112, DQ6 =124, DQ7 =124
2919 00:39:02.437261 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =100
2920 00:39:02.437313 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2921 00:39:02.437365
2922 00:39:02.437416
2923 00:39:02.437468 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2924 00:39:02.437522 CH0 RK0: MR19=404, MR18=1400
2925 00:39:02.437574 CH0_RK0: MR19=0x404, MR18=0x1400, DQSOSC=402, MR23=63, INC=40, DEC=27
2926 00:39:02.437627
2927 00:39:02.437678 ----->DramcWriteLeveling(PI) begin...
2928 00:39:02.437732 ==
2929 00:39:02.437784 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 00:39:02.437837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 00:39:02.437889 ==
2932 00:39:02.437942 Write leveling (Byte 0): 31 => 31
2933 00:39:02.437995 Write leveling (Byte 1): 29 => 29
2934 00:39:02.438047 DramcWriteLeveling(PI) end<-----
2935 00:39:02.438099
2936 00:39:02.438151 ==
2937 00:39:02.438247 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 00:39:02.438299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 00:39:02.438352 ==
2940 00:39:02.438404 [Gating] SW mode calibration
2941 00:39:02.438456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2942 00:39:02.438510 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2943 00:39:02.438563 0 15 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
2944 00:39:02.438615 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2945 00:39:02.438668 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 00:39:02.438720 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 00:39:02.438772 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 00:39:02.438824 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 00:39:02.438876 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 00:39:02.438929 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2951 00:39:02.438981 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2952 00:39:02.439033 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 00:39:02.439086 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 00:39:02.439330 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 00:39:02.439391 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 00:39:02.439444 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 00:39:02.439498 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 00:39:02.439551 1 0 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2959 00:39:02.439604 1 1 0 | B1->B0 | 3232 4242 | 0 0 | (0 0) (0 0)
2960 00:39:02.439656 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 00:39:02.439709 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 00:39:02.439761 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 00:39:02.439814 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 00:39:02.439866 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 00:39:02.439919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 00:39:02.439971 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2967 00:39:02.440024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2968 00:39:02.440077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 00:39:02.440129 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 00:39:02.440182 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 00:39:02.440234 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 00:39:02.440286 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 00:39:02.440339 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 00:39:02.440391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 00:39:02.440444 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 00:39:02.440496 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 00:39:02.440549 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 00:39:02.440601 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 00:39:02.440654 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 00:39:02.440706 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 00:39:02.440759 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2982 00:39:02.440811 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2983 00:39:02.440863 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2984 00:39:02.440915 Total UI for P1: 0, mck2ui 16
2985 00:39:02.440968 best dqsien dly found for B0: ( 1, 3, 26)
2986 00:39:02.441021 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 00:39:02.441074 Total UI for P1: 0, mck2ui 16
2988 00:39:02.441127 best dqsien dly found for B1: ( 1, 4, 0)
2989 00:39:02.441179 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2990 00:39:02.441232 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2991 00:39:02.441285
2992 00:39:02.441337 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2993 00:39:02.441390 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2994 00:39:02.441442 [Gating] SW calibration Done
2995 00:39:02.441495 ==
2996 00:39:02.441548 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 00:39:02.441600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 00:39:02.441653 ==
2999 00:39:02.441705 RX Vref Scan: 0
3000 00:39:02.441757
3001 00:39:02.441808 RX Vref 0 -> 0, step: 1
3002 00:39:02.441860
3003 00:39:02.441912 RX Delay -40 -> 252, step: 8
3004 00:39:02.707138 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3005 00:39:02.707693 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3006 00:39:02.708033 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3007 00:39:02.708352 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3008 00:39:02.708754 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3009 00:39:02.709097 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3010 00:39:02.709413 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3011 00:39:02.709698 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3012 00:39:02.710069 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3013 00:39:02.710545 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3014 00:39:02.710841 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3015 00:39:02.711127 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3016 00:39:02.711406 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3017 00:39:02.711685 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3018 00:39:02.712081 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3019 00:39:02.712364 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3020 00:39:02.712644 ==
3021 00:39:02.712924 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 00:39:02.713203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 00:39:02.713483 ==
3024 00:39:02.713757 DQS Delay:
3025 00:39:02.714035 DQS0 = 0, DQS1 = 0
3026 00:39:02.714353 DQM Delay:
3027 00:39:02.714688 DQM0 = 116, DQM1 = 108
3028 00:39:02.715050 DQ Delay:
3029 00:39:02.715388 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3030 00:39:02.715674 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3031 00:39:02.715949 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3032 00:39:02.716238 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3033 00:39:02.716515
3034 00:39:02.716787
3035 00:39:02.717058 ==
3036 00:39:02.717474 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 00:39:02.717844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 00:39:02.718133 ==
3039 00:39:02.718562
3040 00:39:02.718849
3041 00:39:02.719126 TX Vref Scan disable
3042 00:39:02.719399 == TX Byte 0 ==
3043 00:39:02.719675 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3044 00:39:02.719953 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3045 00:39:02.720230 == TX Byte 1 ==
3046 00:39:02.720505 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3047 00:39:02.720779 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3048 00:39:02.721052 ==
3049 00:39:02.721395 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 00:39:02.721875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 00:39:02.722199 ==
3052 00:39:02.722543 TX Vref=22, minBit 13, minWin=25, winSum=425
3053 00:39:02.723016 TX Vref=24, minBit 13, minWin=25, winSum=425
3054 00:39:02.723450 TX Vref=26, minBit 0, minWin=26, winSum=426
3055 00:39:02.723881 TX Vref=28, minBit 1, minWin=26, winSum=431
3056 00:39:02.724309 TX Vref=30, minBit 14, minWin=26, winSum=434
3057 00:39:02.724769 TX Vref=32, minBit 4, minWin=26, winSum=427
3058 00:39:02.725259 [TxChooseVref] Worse bit 14, Min win 26, Win sum 434, Final Vref 30
3059 00:39:02.725670
3060 00:39:02.725955 Final TX Range 1 Vref 30
3061 00:39:02.726257
3062 00:39:02.726533 ==
3063 00:39:02.726809 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 00:39:02.727084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 00:39:02.727361 ==
3066 00:39:02.727778
3067 00:39:02.728091
3068 00:39:02.728374 TX Vref Scan disable
3069 00:39:02.728753 == TX Byte 0 ==
3070 00:39:02.729433 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3071 00:39:02.729751 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3072 00:39:02.730038 == TX Byte 1 ==
3073 00:39:02.730375 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3074 00:39:02.730663 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3075 00:39:02.730943
3076 00:39:02.731212 [DATLAT]
3077 00:39:02.731594 Freq=1200, CH0 RK1
3078 00:39:02.731922
3079 00:39:02.732197 DATLAT Default: 0xd
3080 00:39:02.732471 0, 0xFFFF, sum = 0
3081 00:39:02.732753 1, 0xFFFF, sum = 0
3082 00:39:02.733031 2, 0xFFFF, sum = 0
3083 00:39:02.733310 3, 0xFFFF, sum = 0
3084 00:39:02.733586 4, 0xFFFF, sum = 0
3085 00:39:02.733862 5, 0xFFFF, sum = 0
3086 00:39:02.734139 6, 0xFFFF, sum = 0
3087 00:39:02.734458 7, 0xFFFF, sum = 0
3088 00:39:02.734735 8, 0xFFFF, sum = 0
3089 00:39:02.735124 9, 0xFFFF, sum = 0
3090 00:39:02.735385 10, 0xFFFF, sum = 0
3091 00:39:02.735584 11, 0xFFFF, sum = 0
3092 00:39:02.735785 12, 0x0, sum = 1
3093 00:39:02.735984 13, 0x0, sum = 2
3094 00:39:02.736182 14, 0x0, sum = 3
3095 00:39:02.736381 15, 0x0, sum = 4
3096 00:39:02.736576 best_step = 13
3097 00:39:02.736769
3098 00:39:02.736963 ==
3099 00:39:02.737157 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 00:39:02.737351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 00:39:02.737548 ==
3102 00:39:02.737747 RX Vref Scan: 0
3103 00:39:02.737944
3104 00:39:02.738140 RX Vref 0 -> 0, step: 1
3105 00:39:02.738426
3106 00:39:02.738636 RX Delay -21 -> 252, step: 4
3107 00:39:02.738838 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3108 00:39:02.739038 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3109 00:39:02.739233 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3110 00:39:02.739432 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3111 00:39:02.739629 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3112 00:39:02.739826 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3113 00:39:02.740024 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3114 00:39:02.740221 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3115 00:39:02.740398 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3116 00:39:02.740546 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3117 00:39:02.740693 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3118 00:39:02.740841 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3119 00:39:02.740987 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3120 00:39:02.741135 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3121 00:39:02.741282 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3122 00:39:02.741429 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3123 00:39:02.741631 ==
3124 00:39:02.741791 Dram Type= 6, Freq= 0, CH_0, rank 1
3125 00:39:02.741941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 00:39:02.742092 ==
3127 00:39:02.742268 DQS Delay:
3128 00:39:02.742419 DQS0 = 0, DQS1 = 0
3129 00:39:02.742567 DQM Delay:
3130 00:39:02.742714 DQM0 = 116, DQM1 = 107
3131 00:39:02.742862 DQ Delay:
3132 00:39:02.743008 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3133 00:39:02.743155 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3134 00:39:02.743303 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3135 00:39:02.743452 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3136 00:39:02.743599
3137 00:39:02.743744
3138 00:39:02.743892 [DQSOSCAuto] RK1, (LSB)MR18= 0xce7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3139 00:39:02.744043 CH0 RK1: MR19=403, MR18=CE7
3140 00:39:02.744192 CH0_RK1: MR19=0x403, MR18=0xCE7, DQSOSC=405, MR23=63, INC=39, DEC=26
3141 00:39:02.744341 [RxdqsGatingPostProcess] freq 1200
3142 00:39:02.744489 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3143 00:39:02.744640 best DQS0 dly(2T, 0.5T) = (0, 11)
3144 00:39:02.744789 best DQS1 dly(2T, 0.5T) = (0, 12)
3145 00:39:02.744939 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3146 00:39:02.745146 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3147 00:39:02.745309 best DQS0 dly(2T, 0.5T) = (0, 11)
3148 00:39:02.745429 best DQS1 dly(2T, 0.5T) = (0, 12)
3149 00:39:02.745546 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3150 00:39:02.745665 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3151 00:39:02.745782 Pre-setting of DQS Precalculation
3152 00:39:02.745900 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3153 00:39:02.746019 ==
3154 00:39:02.746136 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 00:39:02.746269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 00:39:02.746389 ==
3157 00:39:02.746508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 00:39:02.746626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 00:39:02.746745 [CA 0] Center 38 (8~68) winsize 61
3160 00:39:02.746863 [CA 1] Center 37 (7~68) winsize 62
3161 00:39:02.746981 [CA 2] Center 34 (4~64) winsize 61
3162 00:39:02.747098 [CA 3] Center 33 (3~64) winsize 62
3163 00:39:02.747216 [CA 4] Center 34 (4~64) winsize 61
3164 00:39:02.747334 [CA 5] Center 33 (3~64) winsize 62
3165 00:39:02.747451
3166 00:39:02.747568 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 00:39:02.747687
3168 00:39:02.747822 [CATrainingPosCal] consider 1 rank data
3169 00:39:02.747964 u2DelayCellTimex100 = 270/100 ps
3170 00:39:02.748083 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3171 00:39:02.748204 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 00:39:02.748323 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 00:39:02.748443 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 00:39:02.748560 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 00:39:02.748679 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 00:39:02.748795
3177 00:39:02.748913 CA PerBit enable=1, Macro0, CA PI delay=33
3178 00:39:02.749032
3179 00:39:02.749149 [CBTSetCACLKResult] CA Dly = 33
3180 00:39:02.749269 CS Dly: 6 (0~37)
3181 00:39:02.749386 ==
3182 00:39:02.749506 Dram Type= 6, Freq= 0, CH_1, rank 1
3183 00:39:02.749624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 00:39:02.749744 ==
3185 00:39:02.749863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3186 00:39:02.749981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3187 00:39:02.750100 [CA 0] Center 37 (7~68) winsize 62
3188 00:39:02.750240 [CA 1] Center 38 (8~68) winsize 61
3189 00:39:02.750360 [CA 2] Center 34 (4~65) winsize 62
3190 00:39:02.750459 [CA 3] Center 33 (3~64) winsize 62
3191 00:39:02.750557 [CA 4] Center 34 (4~65) winsize 62
3192 00:39:02.750656 [CA 5] Center 33 (3~64) winsize 62
3193 00:39:02.750755
3194 00:39:02.750853 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3195 00:39:02.750953
3196 00:39:02.751051 [CATrainingPosCal] consider 2 rank data
3197 00:39:02.751150 u2DelayCellTimex100 = 270/100 ps
3198 00:39:02.751251 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3199 00:39:02.751387 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3200 00:39:02.751747 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 00:39:02.751867 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 00:39:02.751969 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 00:39:02.752070 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 00:39:02.752169
3205 00:39:02.752269 CA PerBit enable=1, Macro0, CA PI delay=33
3206 00:39:02.752369
3207 00:39:02.752468 [CBTSetCACLKResult] CA Dly = 33
3208 00:39:02.752567 CS Dly: 7 (0~40)
3209 00:39:02.752666
3210 00:39:02.752765 ----->DramcWriteLeveling(PI) begin...
3211 00:39:02.752865 ==
3212 00:39:02.752965 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 00:39:02.753064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 00:39:02.753165 ==
3215 00:39:02.753263 Write leveling (Byte 0): 25 => 25
3216 00:39:02.753362 Write leveling (Byte 1): 27 => 27
3217 00:39:02.753462 DramcWriteLeveling(PI) end<-----
3218 00:39:02.753560
3219 00:39:02.753657 ==
3220 00:39:02.753755 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 00:39:02.753854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 00:39:02.753953 ==
3223 00:39:02.754052 [Gating] SW mode calibration
3224 00:39:02.754150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3225 00:39:02.754270 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3226 00:39:02.754370 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3227 00:39:02.754471 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 00:39:02.754610 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 00:39:02.754717 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 00:39:02.754819 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 00:39:02.754919 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 00:39:02.755019 0 15 24 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
3233 00:39:02.755119 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
3234 00:39:02.755220 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 00:39:02.755328 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 00:39:02.755413 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 00:39:02.755497 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 00:39:02.755582 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 00:39:02.755667 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 00:39:02.755753 1 0 24 | B1->B0 | 2a2a 3c3c | 0 0 | (0 0) (0 0)
3241 00:39:02.755839 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3242 00:39:02.755923 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3243 00:39:02.756007 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 00:39:02.756092 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 00:39:02.756177 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 00:39:02.756261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 00:39:02.756346 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 00:39:02.756431 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3249 00:39:02.756515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3250 00:39:02.756599 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 00:39:02.756684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 00:39:02.756769 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 00:39:02.756853 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 00:39:02.756938 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 00:39:02.757023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 00:39:02.757107 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 00:39:02.757192 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 00:39:02.757277 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 00:39:02.757362 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 00:39:02.757446 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 00:39:02.757541 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 00:39:02.757646 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 00:39:02.757771 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 00:39:02.757898 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3265 00:39:02.757993 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3266 00:39:02.758079 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 00:39:02.758189 Total UI for P1: 0, mck2ui 16
3268 00:39:02.758321 best dqsien dly found for B0: ( 1, 3, 26)
3269 00:39:02.758410 Total UI for P1: 0, mck2ui 16
3270 00:39:02.758569 best dqsien dly found for B1: ( 1, 3, 28)
3271 00:39:02.758722 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3272 00:39:02.758857 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3273 00:39:02.758988
3274 00:39:02.759131 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3275 00:39:02.759252 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3276 00:39:02.759340 [Gating] SW calibration Done
3277 00:39:02.759428 ==
3278 00:39:02.759513 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 00:39:02.759598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 00:39:02.759684 ==
3281 00:39:02.759768 RX Vref Scan: 0
3282 00:39:02.759853
3283 00:39:02.759937 RX Vref 0 -> 0, step: 1
3284 00:39:02.760021
3285 00:39:02.760105 RX Delay -40 -> 252, step: 8
3286 00:39:02.760189 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3287 00:39:02.760287 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3288 00:39:02.760361 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3289 00:39:02.760434 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3290 00:39:02.760508 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3291 00:39:02.760581 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3292 00:39:02.760655 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3293 00:39:02.760729 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3294 00:39:02.760802 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3295 00:39:02.760876 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3296 00:39:02.760950 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3297 00:39:02.761036 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3298 00:39:02.761125 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3299 00:39:02.761201 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3300 00:39:02.761275 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3301 00:39:02.761562 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3302 00:39:02.761647 ==
3303 00:39:02.761723 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 00:39:02.761799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 00:39:02.761875 ==
3306 00:39:02.761949 DQS Delay:
3307 00:39:02.762023 DQS0 = 0, DQS1 = 0
3308 00:39:02.762098 DQM Delay:
3309 00:39:02.762183 DQM0 = 118, DQM1 = 109
3310 00:39:02.762260 DQ Delay:
3311 00:39:02.762335 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3312 00:39:02.762410 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3313 00:39:02.762484 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3314 00:39:02.762559 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3315 00:39:02.762633
3316 00:39:02.762707
3317 00:39:02.762780 ==
3318 00:39:02.762854 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 00:39:02.762928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 00:39:02.763002 ==
3321 00:39:02.763076
3322 00:39:02.763150
3323 00:39:02.763223 TX Vref Scan disable
3324 00:39:02.763297 == TX Byte 0 ==
3325 00:39:02.763372 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3326 00:39:02.763448 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3327 00:39:02.763523 == TX Byte 1 ==
3328 00:39:02.763597 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3329 00:39:02.763672 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3330 00:39:02.763745 ==
3331 00:39:02.763845 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 00:39:02.763924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 00:39:02.763999 ==
3334 00:39:02.764074 TX Vref=22, minBit 10, minWin=24, winSum=414
3335 00:39:02.764150 TX Vref=24, minBit 10, minWin=25, winSum=418
3336 00:39:02.764224 TX Vref=26, minBit 9, minWin=25, winSum=429
3337 00:39:02.764333 TX Vref=28, minBit 8, minWin=26, winSum=431
3338 00:39:02.764412 TX Vref=30, minBit 9, minWin=25, winSum=428
3339 00:39:02.764487 TX Vref=32, minBit 9, minWin=25, winSum=423
3340 00:39:02.764562 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 28
3341 00:39:02.764637
3342 00:39:02.764711 Final TX Range 1 Vref 28
3343 00:39:02.764786
3344 00:39:02.764860 ==
3345 00:39:02.764935 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 00:39:02.765009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 00:39:02.765084 ==
3348 00:39:02.765157
3349 00:39:02.765230
3350 00:39:02.765314 TX Vref Scan disable
3351 00:39:02.765380 == TX Byte 0 ==
3352 00:39:02.765446 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3353 00:39:02.765512 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3354 00:39:02.765578 == TX Byte 1 ==
3355 00:39:02.765645 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3356 00:39:02.765711 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3357 00:39:02.765776
3358 00:39:02.765841 [DATLAT]
3359 00:39:02.765907 Freq=1200, CH1 RK0
3360 00:39:02.765973
3361 00:39:02.766038 DATLAT Default: 0xd
3362 00:39:02.766104 0, 0xFFFF, sum = 0
3363 00:39:02.766179 1, 0xFFFF, sum = 0
3364 00:39:02.766247 2, 0xFFFF, sum = 0
3365 00:39:02.766313 3, 0xFFFF, sum = 0
3366 00:39:02.766380 4, 0xFFFF, sum = 0
3367 00:39:02.766446 5, 0xFFFF, sum = 0
3368 00:39:02.766512 6, 0xFFFF, sum = 0
3369 00:39:02.766577 7, 0xFFFF, sum = 0
3370 00:39:02.766643 8, 0xFFFF, sum = 0
3371 00:39:02.766710 9, 0xFFFF, sum = 0
3372 00:39:02.766776 10, 0xFFFF, sum = 0
3373 00:39:02.766842 11, 0xFFFF, sum = 0
3374 00:39:02.766908 12, 0x0, sum = 1
3375 00:39:02.766975 13, 0x0, sum = 2
3376 00:39:02.767040 14, 0x0, sum = 3
3377 00:39:02.767106 15, 0x0, sum = 4
3378 00:39:02.767172 best_step = 13
3379 00:39:02.767237
3380 00:39:02.767301 ==
3381 00:39:02.767383 Dram Type= 6, Freq= 0, CH_1, rank 0
3382 00:39:02.767457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3383 00:39:02.767524 ==
3384 00:39:02.767594 RX Vref Scan: 1
3385 00:39:02.767663
3386 00:39:02.767728 Set Vref Range= 32 -> 127
3387 00:39:02.767795
3388 00:39:02.767859 RX Vref 32 -> 127, step: 1
3389 00:39:02.767924
3390 00:39:02.767989 RX Delay -21 -> 252, step: 4
3391 00:39:02.768054
3392 00:39:02.768120 Set Vref, RX VrefLevel [Byte0]: 32
3393 00:39:02.768185 [Byte1]: 32
3394 00:39:02.768250
3395 00:39:02.768314 Set Vref, RX VrefLevel [Byte0]: 33
3396 00:39:02.768380 [Byte1]: 33
3397 00:39:02.768444
3398 00:39:02.768508 Set Vref, RX VrefLevel [Byte0]: 34
3399 00:39:02.768573 [Byte1]: 34
3400 00:39:02.768638
3401 00:39:02.768703 Set Vref, RX VrefLevel [Byte0]: 35
3402 00:39:02.768768 [Byte1]: 35
3403 00:39:02.768834
3404 00:39:02.768899 Set Vref, RX VrefLevel [Byte0]: 36
3405 00:39:02.768964 [Byte1]: 36
3406 00:39:02.769030
3407 00:39:02.769096 Set Vref, RX VrefLevel [Byte0]: 37
3408 00:39:02.769162 [Byte1]: 37
3409 00:39:02.769226
3410 00:39:02.769290 Set Vref, RX VrefLevel [Byte0]: 38
3411 00:39:02.769355 [Byte1]: 38
3412 00:39:02.769421
3413 00:39:02.769486 Set Vref, RX VrefLevel [Byte0]: 39
3414 00:39:02.769551 [Byte1]: 39
3415 00:39:02.769640
3416 00:39:02.769709 Set Vref, RX VrefLevel [Byte0]: 40
3417 00:39:02.769819 [Byte1]: 40
3418 00:39:02.769891
3419 00:39:02.769958 Set Vref, RX VrefLevel [Byte0]: 41
3420 00:39:02.770024 [Byte1]: 41
3421 00:39:02.770090
3422 00:39:02.770155 Set Vref, RX VrefLevel [Byte0]: 42
3423 00:39:02.770227 [Byte1]: 42
3424 00:39:02.770292
3425 00:39:02.770369 Set Vref, RX VrefLevel [Byte0]: 43
3426 00:39:02.770428 [Byte1]: 43
3427 00:39:02.770486
3428 00:39:02.770545 Set Vref, RX VrefLevel [Byte0]: 44
3429 00:39:02.770604 [Byte1]: 44
3430 00:39:02.770662
3431 00:39:02.770721 Set Vref, RX VrefLevel [Byte0]: 45
3432 00:39:02.770780 [Byte1]: 45
3433 00:39:02.770839
3434 00:39:02.770897 Set Vref, RX VrefLevel [Byte0]: 46
3435 00:39:02.770955 [Byte1]: 46
3436 00:39:02.771014
3437 00:39:02.771072 Set Vref, RX VrefLevel [Byte0]: 47
3438 00:39:02.771131 [Byte1]: 47
3439 00:39:02.771189
3440 00:39:02.771248 Set Vref, RX VrefLevel [Byte0]: 48
3441 00:39:02.771307 [Byte1]: 48
3442 00:39:02.771378
3443 00:39:02.771446 Set Vref, RX VrefLevel [Byte0]: 49
3444 00:39:02.771506 [Byte1]: 49
3445 00:39:02.771565
3446 00:39:02.771629 Set Vref, RX VrefLevel [Byte0]: 50
3447 00:39:02.771689 [Byte1]: 50
3448 00:39:02.771748
3449 00:39:02.771807 Set Vref, RX VrefLevel [Byte0]: 51
3450 00:39:02.771865 [Byte1]: 51
3451 00:39:02.771924
3452 00:39:02.771983 Set Vref, RX VrefLevel [Byte0]: 52
3453 00:39:02.772041 [Byte1]: 52
3454 00:39:02.772100
3455 00:39:02.772158 Set Vref, RX VrefLevel [Byte0]: 53
3456 00:39:02.772216 [Byte1]: 53
3457 00:39:02.772275
3458 00:39:02.772333 Set Vref, RX VrefLevel [Byte0]: 54
3459 00:39:02.772392 [Byte1]: 54
3460 00:39:02.772450
3461 00:39:02.772508 Set Vref, RX VrefLevel [Byte0]: 55
3462 00:39:02.772567 [Byte1]: 55
3463 00:39:02.772626
3464 00:39:02.772683 Set Vref, RX VrefLevel [Byte0]: 56
3465 00:39:02.772742 [Byte1]: 56
3466 00:39:02.772800
3467 00:39:02.772858 Set Vref, RX VrefLevel [Byte0]: 57
3468 00:39:02.772917 [Byte1]: 57
3469 00:39:02.773177
3470 00:39:02.773246 Set Vref, RX VrefLevel [Byte0]: 58
3471 00:39:02.773307 [Byte1]: 58
3472 00:39:02.773367
3473 00:39:02.773425 Set Vref, RX VrefLevel [Byte0]: 59
3474 00:39:02.773485 [Byte1]: 59
3475 00:39:02.773544
3476 00:39:02.773607 Set Vref, RX VrefLevel [Byte0]: 60
3477 00:39:02.773667 [Byte1]: 60
3478 00:39:02.773726
3479 00:39:02.773785 Set Vref, RX VrefLevel [Byte0]: 61
3480 00:39:02.773845 [Byte1]: 61
3481 00:39:02.773903
3482 00:39:02.773961 Set Vref, RX VrefLevel [Byte0]: 62
3483 00:39:02.774021 [Byte1]: 62
3484 00:39:02.774079
3485 00:39:02.774138 Set Vref, RX VrefLevel [Byte0]: 63
3486 00:39:02.774211 [Byte1]: 63
3487 00:39:02.774271
3488 00:39:02.774329 Set Vref, RX VrefLevel [Byte0]: 64
3489 00:39:02.774388 [Byte1]: 64
3490 00:39:02.774460
3491 00:39:02.774527 Set Vref, RX VrefLevel [Byte0]: 65
3492 00:39:02.774587 [Byte1]: 65
3493 00:39:02.774646
3494 00:39:02.774704 Set Vref, RX VrefLevel [Byte0]: 66
3495 00:39:02.774763 [Byte1]: 66
3496 00:39:02.774821
3497 00:39:02.774880 Final RX Vref Byte 0 = 48 to rank0
3498 00:39:02.774939 Final RX Vref Byte 1 = 59 to rank0
3499 00:39:02.774997 Final RX Vref Byte 0 = 48 to rank1
3500 00:39:02.775056 Final RX Vref Byte 1 = 59 to rank1==
3501 00:39:02.775115 Dram Type= 6, Freq= 0, CH_1, rank 0
3502 00:39:02.775174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 00:39:02.775233 ==
3504 00:39:02.775302 DQS Delay:
3505 00:39:02.775356 DQS0 = 0, DQS1 = 0
3506 00:39:02.775409 DQM Delay:
3507 00:39:02.775462 DQM0 = 116, DQM1 = 112
3508 00:39:02.775515 DQ Delay:
3509 00:39:02.775568 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3510 00:39:02.775621 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3511 00:39:02.775674 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =100
3512 00:39:02.775727 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =120
3513 00:39:02.775780
3514 00:39:02.775833
3515 00:39:02.775886 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3516 00:39:02.775941 CH1 RK0: MR19=403, MR18=1F5
3517 00:39:02.775995 CH1_RK0: MR19=0x403, MR18=0x1F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3518 00:39:02.776049
3519 00:39:02.776103 ----->DramcWriteLeveling(PI) begin...
3520 00:39:02.776157 ==
3521 00:39:02.776210 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 00:39:02.776264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 00:39:02.776318 ==
3524 00:39:02.776371 Write leveling (Byte 0): 24 => 24
3525 00:39:02.776425 Write leveling (Byte 1): 27 => 27
3526 00:39:02.776478 DramcWriteLeveling(PI) end<-----
3527 00:39:02.776532
3528 00:39:02.776584 ==
3529 00:39:02.776637 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 00:39:02.776691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 00:39:02.776745 ==
3532 00:39:02.776798 [Gating] SW mode calibration
3533 00:39:02.776852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3534 00:39:02.776906 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3535 00:39:02.776960 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 00:39:02.777013 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 00:39:02.777067 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3538 00:39:02.777121 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3539 00:39:02.777174 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 00:39:02.777228 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 00:39:02.777281 0 15 24 | B1->B0 | 2e2e 3333 | 1 1 | (1 0) (1 0)
3542 00:39:02.777334 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
3543 00:39:02.777393 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 00:39:02.777460 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 00:39:02.777514 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3546 00:39:02.777568 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 00:39:02.777655 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 00:39:02.777736 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3549 00:39:02.777810 1 0 24 | B1->B0 | 3939 2727 | 0 0 | (0 0) (0 0)
3550 00:39:02.777865 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 00:39:02.777919 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 00:39:02.777973 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 00:39:02.778027 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 00:39:02.778081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 00:39:02.778134 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 00:39:02.778200 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 00:39:02.778254 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3558 00:39:02.778308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3559 00:39:02.778361 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 00:39:02.778415 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 00:39:02.778468 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 00:39:02.778522 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 00:39:02.778575 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 00:39:02.778628 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 00:39:02.778682 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 00:39:02.778735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 00:39:02.778789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 00:39:02.778842 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 00:39:02.778894 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 00:39:02.778947 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 00:39:02.779001 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 00:39:02.779054 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 00:39:02.779107 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3574 00:39:02.779161 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3575 00:39:02.779214 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 00:39:02.779267 Total UI for P1: 0, mck2ui 16
3577 00:39:02.779321 best dqsien dly found for B0: ( 1, 3, 26)
3578 00:39:02.779375 Total UI for P1: 0, mck2ui 16
3579 00:39:02.779629 best dqsien dly found for B1: ( 1, 3, 26)
3580 00:39:02.779689 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3581 00:39:02.779743 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3582 00:39:02.779797
3583 00:39:02.779849 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3584 00:39:02.779902 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3585 00:39:02.779956 [Gating] SW calibration Done
3586 00:39:02.780010 ==
3587 00:39:02.780064 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 00:39:02.780117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 00:39:02.780171 ==
3590 00:39:02.780224 RX Vref Scan: 0
3591 00:39:02.780290
3592 00:39:02.780341 RX Vref 0 -> 0, step: 1
3593 00:39:02.780393
3594 00:39:02.780445 RX Delay -40 -> 252, step: 8
3595 00:39:02.780498 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3596 00:39:02.780550 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3597 00:39:02.780602 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3598 00:39:02.780655 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3599 00:39:02.780707 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3600 00:39:02.780759 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3601 00:39:02.780811 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3602 00:39:02.780864 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3603 00:39:02.780926 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3604 00:39:02.780989 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3605 00:39:02.781042 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3606 00:39:02.781094 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3607 00:39:02.781147 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3608 00:39:02.781199 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3609 00:39:02.781251 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3610 00:39:02.781304 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3611 00:39:02.781356 ==
3612 00:39:02.781408 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 00:39:02.781460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 00:39:02.781513 ==
3615 00:39:02.781566 DQS Delay:
3616 00:39:02.781617 DQS0 = 0, DQS1 = 0
3617 00:39:02.781669 DQM Delay:
3618 00:39:02.781721 DQM0 = 116, DQM1 = 110
3619 00:39:02.781773 DQ Delay:
3620 00:39:02.781825 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3621 00:39:02.781878 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3622 00:39:02.781930 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3623 00:39:02.781982 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3624 00:39:02.782034
3625 00:39:02.782086
3626 00:39:02.782137 ==
3627 00:39:02.782235 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 00:39:02.782288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 00:39:02.782341 ==
3630 00:39:02.782393
3631 00:39:02.782445
3632 00:39:02.782497 TX Vref Scan disable
3633 00:39:02.782549 == TX Byte 0 ==
3634 00:39:02.782602 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3635 00:39:02.782655 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3636 00:39:02.782707 == TX Byte 1 ==
3637 00:39:02.782759 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 00:39:02.782812 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 00:39:02.782864 ==
3640 00:39:02.782916 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 00:39:02.782968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 00:39:02.783022 ==
3643 00:39:02.783074 TX Vref=22, minBit 8, minWin=26, winSum=431
3644 00:39:02.783127 TX Vref=24, minBit 8, minWin=26, winSum=434
3645 00:39:02.783180 TX Vref=26, minBit 9, minWin=26, winSum=436
3646 00:39:02.783232 TX Vref=28, minBit 4, minWin=26, winSum=431
3647 00:39:02.783284 TX Vref=30, minBit 9, minWin=26, winSum=437
3648 00:39:02.783337 TX Vref=32, minBit 8, minWin=26, winSum=432
3649 00:39:02.783389 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3650 00:39:02.783442
3651 00:39:02.783494 Final TX Range 1 Vref 30
3652 00:39:02.783547
3653 00:39:02.783599 ==
3654 00:39:02.783651 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 00:39:02.783703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 00:39:02.783755 ==
3657 00:39:02.783807
3658 00:39:02.783859
3659 00:39:02.783910 TX Vref Scan disable
3660 00:39:02.783962 == TX Byte 0 ==
3661 00:39:02.784015 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3662 00:39:02.784068 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3663 00:39:02.784120 == TX Byte 1 ==
3664 00:39:02.784173 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3665 00:39:02.784225 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3666 00:39:02.784278
3667 00:39:02.784330 [DATLAT]
3668 00:39:02.784382 Freq=1200, CH1 RK1
3669 00:39:02.784456
3670 00:39:02.784510 DATLAT Default: 0xd
3671 00:39:02.784563 0, 0xFFFF, sum = 0
3672 00:39:02.784616 1, 0xFFFF, sum = 0
3673 00:39:02.784670 2, 0xFFFF, sum = 0
3674 00:39:02.784723 3, 0xFFFF, sum = 0
3675 00:39:02.784776 4, 0xFFFF, sum = 0
3676 00:39:02.784829 5, 0xFFFF, sum = 0
3677 00:39:02.784882 6, 0xFFFF, sum = 0
3678 00:39:02.784935 7, 0xFFFF, sum = 0
3679 00:39:02.784988 8, 0xFFFF, sum = 0
3680 00:39:02.785041 9, 0xFFFF, sum = 0
3681 00:39:02.785094 10, 0xFFFF, sum = 0
3682 00:39:02.785147 11, 0xFFFF, sum = 0
3683 00:39:02.785200 12, 0x0, sum = 1
3684 00:39:02.785254 13, 0x0, sum = 2
3685 00:39:02.785308 14, 0x0, sum = 3
3686 00:39:02.785361 15, 0x0, sum = 4
3687 00:39:02.785414 best_step = 13
3688 00:39:02.785466
3689 00:39:02.785517 ==
3690 00:39:02.785570 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 00:39:02.785623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 00:39:02.785675 ==
3693 00:39:02.785727 RX Vref Scan: 0
3694 00:39:02.785779
3695 00:39:02.785832 RX Vref 0 -> 0, step: 1
3696 00:39:02.785884
3697 00:39:02.785935 RX Delay -21 -> 252, step: 4
3698 00:39:02.785988 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3699 00:39:02.786041 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3700 00:39:02.786093 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3701 00:39:02.786145 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3702 00:39:02.786244 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3703 00:39:02.786297 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3704 00:39:02.786350 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3705 00:39:02.786402 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3706 00:39:02.786454 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3707 00:39:02.786506 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3708 00:39:02.786558 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3709 00:39:02.786610 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3710 00:39:02.786663 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3711 00:39:02.786715 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3712 00:39:02.786767 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3713 00:39:02.786819 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3714 00:39:02.786871 ==
3715 00:39:02.786923 Dram Type= 6, Freq= 0, CH_1, rank 1
3716 00:39:02.786975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3717 00:39:02.787029 ==
3718 00:39:02.787081 DQS Delay:
3719 00:39:02.787133 DQS0 = 0, DQS1 = 0
3720 00:39:02.787186 DQM Delay:
3721 00:39:02.787238 DQM0 = 116, DQM1 = 110
3722 00:39:02.787483 DQ Delay:
3723 00:39:02.787554 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3724 00:39:02.787616 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3725 00:39:02.787670 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3726 00:39:02.787723 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3727 00:39:02.787776
3728 00:39:02.787828
3729 00:39:02.787879 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3730 00:39:02.787933 CH1 RK1: MR19=303, MR18=F6F1
3731 00:39:02.787986 CH1_RK1: MR19=0x303, MR18=0xF6F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3732 00:39:02.788039 [RxdqsGatingPostProcess] freq 1200
3733 00:39:02.788091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3734 00:39:02.788143 best DQS0 dly(2T, 0.5T) = (0, 11)
3735 00:39:02.788196 best DQS1 dly(2T, 0.5T) = (0, 11)
3736 00:39:02.788248 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3737 00:39:02.788301 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3738 00:39:02.788352 best DQS0 dly(2T, 0.5T) = (0, 11)
3739 00:39:02.788404 best DQS1 dly(2T, 0.5T) = (0, 11)
3740 00:39:02.788456 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3741 00:39:02.788508 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3742 00:39:02.788559 Pre-setting of DQS Precalculation
3743 00:39:02.788612 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3744 00:39:02.788664 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3745 00:39:02.788717 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3746 00:39:02.788770
3747 00:39:02.788821
3748 00:39:02.788873 [Calibration Summary] 2400 Mbps
3749 00:39:02.788925 CH 0, Rank 0
3750 00:39:02.788978 SW Impedance : PASS
3751 00:39:02.789029 DUTY Scan : NO K
3752 00:39:02.789082 ZQ Calibration : PASS
3753 00:39:02.789134 Jitter Meter : NO K
3754 00:39:02.789186 CBT Training : PASS
3755 00:39:02.789237 Write leveling : PASS
3756 00:39:02.789289 RX DQS gating : PASS
3757 00:39:02.789341 RX DQ/DQS(RDDQC) : PASS
3758 00:39:02.789393 TX DQ/DQS : PASS
3759 00:39:02.789445 RX DATLAT : PASS
3760 00:39:02.789497 RX DQ/DQS(Engine): PASS
3761 00:39:02.789548 TX OE : NO K
3762 00:39:02.789601 All Pass.
3763 00:39:02.789653
3764 00:39:02.789705 CH 0, Rank 1
3765 00:39:02.789757 SW Impedance : PASS
3766 00:39:02.789809 DUTY Scan : NO K
3767 00:39:02.789862 ZQ Calibration : PASS
3768 00:39:02.789914 Jitter Meter : NO K
3769 00:39:02.789966 CBT Training : PASS
3770 00:39:02.790018 Write leveling : PASS
3771 00:39:02.790070 RX DQS gating : PASS
3772 00:39:02.790122 RX DQ/DQS(RDDQC) : PASS
3773 00:39:02.790206 TX DQ/DQS : PASS
3774 00:39:02.790274 RX DATLAT : PASS
3775 00:39:02.790327 RX DQ/DQS(Engine): PASS
3776 00:39:02.790379 TX OE : NO K
3777 00:39:02.790431 All Pass.
3778 00:39:02.790482
3779 00:39:02.790534 CH 1, Rank 0
3780 00:39:02.790586 SW Impedance : PASS
3781 00:39:02.790638 DUTY Scan : NO K
3782 00:39:02.790690 ZQ Calibration : PASS
3783 00:39:02.790765 Jitter Meter : NO K
3784 00:39:02.790819 CBT Training : PASS
3785 00:39:02.790872 Write leveling : PASS
3786 00:39:02.790925 RX DQS gating : PASS
3787 00:39:02.790977 RX DQ/DQS(RDDQC) : PASS
3788 00:39:02.791029 TX DQ/DQS : PASS
3789 00:39:02.791082 RX DATLAT : PASS
3790 00:39:02.791134 RX DQ/DQS(Engine): PASS
3791 00:39:02.791185 TX OE : NO K
3792 00:39:02.791237 All Pass.
3793 00:39:02.791289
3794 00:39:02.791341 CH 1, Rank 1
3795 00:39:02.791393 SW Impedance : PASS
3796 00:39:02.791445 DUTY Scan : NO K
3797 00:39:02.791497 ZQ Calibration : PASS
3798 00:39:02.791550 Jitter Meter : NO K
3799 00:39:02.791602 CBT Training : PASS
3800 00:39:02.791654 Write leveling : PASS
3801 00:39:02.791706 RX DQS gating : PASS
3802 00:39:02.791758 RX DQ/DQS(RDDQC) : PASS
3803 00:39:02.791809 TX DQ/DQS : PASS
3804 00:39:02.791862 RX DATLAT : PASS
3805 00:39:02.791914 RX DQ/DQS(Engine): PASS
3806 00:39:02.791966 TX OE : NO K
3807 00:39:02.792018 All Pass.
3808 00:39:02.792070
3809 00:39:02.792123 DramC Write-DBI off
3810 00:39:02.792175 PER_BANK_REFRESH: Hybrid Mode
3811 00:39:02.792227 TX_TRACKING: ON
3812 00:39:02.792280 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3813 00:39:02.792334 [FAST_K] Save calibration result to emmc
3814 00:39:02.792386 dramc_set_vcore_voltage set vcore to 650000
3815 00:39:02.792439 Read voltage for 600, 5
3816 00:39:02.792490 Vio18 = 0
3817 00:39:02.792543 Vcore = 650000
3818 00:39:02.792594 Vdram = 0
3819 00:39:02.792646 Vddq = 0
3820 00:39:02.792698 Vmddr = 0
3821 00:39:02.792750 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3822 00:39:02.792803 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3823 00:39:02.792855 MEM_TYPE=3, freq_sel=19
3824 00:39:02.792908 sv_algorithm_assistance_LP4_1600
3825 00:39:02.792960 ============ PULL DRAM RESETB DOWN ============
3826 00:39:02.793012 ========== PULL DRAM RESETB DOWN end =========
3827 00:39:02.793065 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3828 00:39:02.793118 ===================================
3829 00:39:02.793170 LPDDR4 DRAM CONFIGURATION
3830 00:39:02.793222 ===================================
3831 00:39:02.793274 EX_ROW_EN[0] = 0x0
3832 00:39:02.793326 EX_ROW_EN[1] = 0x0
3833 00:39:02.793378 LP4Y_EN = 0x0
3834 00:39:02.793429 WORK_FSP = 0x0
3835 00:39:02.793481 WL = 0x2
3836 00:39:02.793533 RL = 0x2
3837 00:39:02.793588 BL = 0x2
3838 00:39:02.793684 RPST = 0x0
3839 00:39:02.793754 RD_PRE = 0x0
3840 00:39:02.793808 WR_PRE = 0x1
3841 00:39:02.793861 WR_PST = 0x0
3842 00:39:02.793914 DBI_WR = 0x0
3843 00:39:02.793967 DBI_RD = 0x0
3844 00:39:02.794019 OTF = 0x1
3845 00:39:02.794072 ===================================
3846 00:39:02.794126 ===================================
3847 00:39:02.794219 ANA top config
3848 00:39:02.794273 ===================================
3849 00:39:02.794327 DLL_ASYNC_EN = 0
3850 00:39:02.794397 ALL_SLAVE_EN = 1
3851 00:39:02.794458 NEW_RANK_MODE = 1
3852 00:39:02.794512 DLL_IDLE_MODE = 1
3853 00:39:02.794565 LP45_APHY_COMB_EN = 1
3854 00:39:02.794618 TX_ODT_DIS = 1
3855 00:39:02.794671 NEW_8X_MODE = 1
3856 00:39:02.794724 ===================================
3857 00:39:02.794777 ===================================
3858 00:39:02.794830 data_rate = 1200
3859 00:39:02.794882 CKR = 1
3860 00:39:02.794935 DQ_P2S_RATIO = 8
3861 00:39:02.794987 ===================================
3862 00:39:02.795040 CA_P2S_RATIO = 8
3863 00:39:02.795093 DQ_CA_OPEN = 0
3864 00:39:02.795145 DQ_SEMI_OPEN = 0
3865 00:39:02.795391 CA_SEMI_OPEN = 0
3866 00:39:02.795449 CA_FULL_RATE = 0
3867 00:39:02.795503 DQ_CKDIV4_EN = 1
3868 00:39:02.795556 CA_CKDIV4_EN = 1
3869 00:39:02.795609 CA_PREDIV_EN = 0
3870 00:39:02.795661 PH8_DLY = 0
3871 00:39:02.795714 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3872 00:39:02.795767 DQ_AAMCK_DIV = 4
3873 00:39:02.795819 CA_AAMCK_DIV = 4
3874 00:39:02.795872 CA_ADMCK_DIV = 4
3875 00:39:02.795924 DQ_TRACK_CA_EN = 0
3876 00:39:02.795976 CA_PICK = 600
3877 00:39:02.796029 CA_MCKIO = 600
3878 00:39:02.796081 MCKIO_SEMI = 0
3879 00:39:02.796133 PLL_FREQ = 2288
3880 00:39:02.796185 DQ_UI_PI_RATIO = 32
3881 00:39:02.796237 CA_UI_PI_RATIO = 0
3882 00:39:02.796289 ===================================
3883 00:39:02.796342 ===================================
3884 00:39:02.796394 memory_type:LPDDR4
3885 00:39:02.796446 GP_NUM : 10
3886 00:39:02.796499 SRAM_EN : 1
3887 00:39:02.796551 MD32_EN : 0
3888 00:39:02.796602 ===================================
3889 00:39:02.796656 [ANA_INIT] >>>>>>>>>>>>>>
3890 00:39:02.796707 <<<<<< [CONFIGURE PHASE]: ANA_TX
3891 00:39:02.796760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3892 00:39:02.796813 ===================================
3893 00:39:02.796865 data_rate = 1200,PCW = 0X5800
3894 00:39:02.796917 ===================================
3895 00:39:02.796970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3896 00:39:02.797023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3897 00:39:02.797075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3898 00:39:02.797128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3899 00:39:02.797181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3900 00:39:02.797233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3901 00:39:02.797285 [ANA_INIT] flow start
3902 00:39:02.797337 [ANA_INIT] PLL >>>>>>>>
3903 00:39:02.797389 [ANA_INIT] PLL <<<<<<<<
3904 00:39:02.797463 [ANA_INIT] MIDPI >>>>>>>>
3905 00:39:02.797521 [ANA_INIT] MIDPI <<<<<<<<
3906 00:39:02.797574 [ANA_INIT] DLL >>>>>>>>
3907 00:39:02.797626 [ANA_INIT] flow end
3908 00:39:02.797679 ============ LP4 DIFF to SE enter ============
3909 00:39:02.797733 ============ LP4 DIFF to SE exit ============
3910 00:39:02.797786 [ANA_INIT] <<<<<<<<<<<<<
3911 00:39:02.797838 [Flow] Enable top DCM control >>>>>
3912 00:39:02.797891 [Flow] Enable top DCM control <<<<<
3913 00:39:02.797943 Enable DLL master slave shuffle
3914 00:39:02.797996 ==============================================================
3915 00:39:02.798049 Gating Mode config
3916 00:39:02.798101 ==============================================================
3917 00:39:02.798154 Config description:
3918 00:39:02.798262 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3919 00:39:02.798359 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3920 00:39:02.798419 SELPH_MODE 0: By rank 1: By Phase
3921 00:39:02.798473 ==============================================================
3922 00:39:02.798526 GAT_TRACK_EN = 1
3923 00:39:02.798579 RX_GATING_MODE = 2
3924 00:39:02.798631 RX_GATING_TRACK_MODE = 2
3925 00:39:02.798684 SELPH_MODE = 1
3926 00:39:02.798737 PICG_EARLY_EN = 1
3927 00:39:02.798789 VALID_LAT_VALUE = 1
3928 00:39:02.798842 ==============================================================
3929 00:39:02.798895 Enter into Gating configuration >>>>
3930 00:39:02.798948 Exit from Gating configuration <<<<
3931 00:39:02.799000 Enter into DVFS_PRE_config >>>>>
3932 00:39:02.799052 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3933 00:39:02.799106 Exit from DVFS_PRE_config <<<<<
3934 00:39:02.799158 Enter into PICG configuration >>>>
3935 00:39:02.799211 Exit from PICG configuration <<<<
3936 00:39:02.799262 [RX_INPUT] configuration >>>>>
3937 00:39:02.799315 [RX_INPUT] configuration <<<<<
3938 00:39:02.799366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3939 00:39:02.799419 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3940 00:39:02.799471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3941 00:39:02.799525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3942 00:39:02.799577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3943 00:39:02.799630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3944 00:39:02.799683 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3945 00:39:02.799735 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3946 00:39:02.799787 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3947 00:39:02.799840 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3948 00:39:02.799892 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3949 00:39:02.799945 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3950 00:39:02.799997 ===================================
3951 00:39:02.800050 LPDDR4 DRAM CONFIGURATION
3952 00:39:02.800102 ===================================
3953 00:39:02.800154 EX_ROW_EN[0] = 0x0
3954 00:39:02.800207 EX_ROW_EN[1] = 0x0
3955 00:39:02.800259 LP4Y_EN = 0x0
3956 00:39:02.800311 WORK_FSP = 0x0
3957 00:39:02.800363 WL = 0x2
3958 00:39:02.800415 RL = 0x2
3959 00:39:02.800467 BL = 0x2
3960 00:39:02.800538 RPST = 0x0
3961 00:39:02.800616 RD_PRE = 0x0
3962 00:39:02.800685 WR_PRE = 0x1
3963 00:39:02.800742 WR_PST = 0x0
3964 00:39:02.804200 DBI_WR = 0x0
3965 00:39:02.807715 DBI_RD = 0x0
3966 00:39:02.807798 OTF = 0x1
3967 00:39:02.810724 ===================================
3968 00:39:02.813844 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3969 00:39:02.817059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3970 00:39:02.823833 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3971 00:39:02.826993 ===================================
3972 00:39:02.830232 LPDDR4 DRAM CONFIGURATION
3973 00:39:02.833480 ===================================
3974 00:39:02.833565 EX_ROW_EN[0] = 0x10
3975 00:39:02.837128 EX_ROW_EN[1] = 0x0
3976 00:39:02.837210 LP4Y_EN = 0x0
3977 00:39:02.840730 WORK_FSP = 0x0
3978 00:39:02.840811 WL = 0x2
3979 00:39:02.843585 RL = 0x2
3980 00:39:02.843666 BL = 0x2
3981 00:39:02.846946 RPST = 0x0
3982 00:39:02.847027 RD_PRE = 0x0
3983 00:39:02.850439 WR_PRE = 0x1
3984 00:39:02.853768 WR_PST = 0x0
3985 00:39:02.853856 DBI_WR = 0x0
3986 00:39:02.856899 DBI_RD = 0x0
3987 00:39:02.856993 OTF = 0x1
3988 00:39:02.859895 ===================================
3989 00:39:02.866603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3990 00:39:02.870677 nWR fixed to 30
3991 00:39:02.873728 [ModeRegInit_LP4] CH0 RK0
3992 00:39:02.873875 [ModeRegInit_LP4] CH0 RK1
3993 00:39:02.876964 [ModeRegInit_LP4] CH1 RK0
3994 00:39:02.880607 [ModeRegInit_LP4] CH1 RK1
3995 00:39:02.880730 match AC timing 17
3996 00:39:02.886778 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3997 00:39:02.890191 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3998 00:39:02.893627 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3999 00:39:02.900211 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4000 00:39:02.903690 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4001 00:39:03.082158 ==
4002 00:39:03.082635 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 00:39:03.082773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 00:39:03.082891 ==
4005 00:39:03.083004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 00:39:03.083115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4007 00:39:03.083224 [CA 0] Center 36 (6~66) winsize 61
4008 00:39:03.083330 [CA 1] Center 36 (6~66) winsize 61
4009 00:39:03.083435 [CA 2] Center 34 (3~65) winsize 63
4010 00:39:03.083539 [CA 3] Center 34 (3~65) winsize 63
4011 00:39:03.083642 [CA 4] Center 33 (3~64) winsize 62
4012 00:39:03.083745 [CA 5] Center 33 (3~64) winsize 62
4013 00:39:03.083847
4014 00:39:03.083950 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4015 00:39:03.084052
4016 00:39:03.084154 [CATrainingPosCal] consider 1 rank data
4017 00:39:03.084256 u2DelayCellTimex100 = 270/100 ps
4018 00:39:03.084357 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 00:39:03.084460 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4020 00:39:03.084560 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4021 00:39:03.084662 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4022 00:39:03.084763 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 00:39:03.084865 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 00:39:03.084965
4025 00:39:03.085066 CA PerBit enable=1, Macro0, CA PI delay=33
4026 00:39:03.085167
4027 00:39:03.085268 [CBTSetCACLKResult] CA Dly = 33
4028 00:39:03.085369 CS Dly: 5 (0~36)
4029 00:39:03.085455 ==
4030 00:39:03.085542 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 00:39:03.085628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 00:39:03.085715 ==
4033 00:39:03.085801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4034 00:39:03.085888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4035 00:39:03.085975 [CA 0] Center 36 (6~66) winsize 61
4036 00:39:03.086061 [CA 1] Center 36 (6~66) winsize 61
4037 00:39:03.086147 [CA 2] Center 34 (4~65) winsize 62
4038 00:39:03.086243 [CA 3] Center 34 (4~64) winsize 61
4039 00:39:03.086330 [CA 4] Center 33 (2~64) winsize 63
4040 00:39:03.086416 [CA 5] Center 33 (2~64) winsize 63
4041 00:39:03.086503
4042 00:39:03.086588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4043 00:39:03.086675
4044 00:39:03.086760 [CATrainingPosCal] consider 2 rank data
4045 00:39:03.086846 u2DelayCellTimex100 = 270/100 ps
4046 00:39:03.086932 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4047 00:39:03.087018 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4048 00:39:03.087104 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4049 00:39:03.087190 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4050 00:39:03.087276 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4051 00:39:03.087361 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4052 00:39:03.087447
4053 00:39:03.087532 CA PerBit enable=1, Macro0, CA PI delay=33
4054 00:39:03.087619
4055 00:39:03.087703 [CBTSetCACLKResult] CA Dly = 33
4056 00:39:03.087790 CS Dly: 5 (0~36)
4057 00:39:03.087875
4058 00:39:03.087960 ----->DramcWriteLeveling(PI) begin...
4059 00:39:03.088064 ==
4060 00:39:03.088155 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 00:39:03.088243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 00:39:03.088333 ==
4063 00:39:03.088385 Write leveling (Byte 0): 33 => 33
4064 00:39:03.088437 Write leveling (Byte 1): 30 => 30
4065 00:39:03.088505 DramcWriteLeveling(PI) end<-----
4066 00:39:03.088560
4067 00:39:03.088612 ==
4068 00:39:03.088676 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 00:39:03.091705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 00:39:03.091795 ==
4071 00:39:03.094774 [Gating] SW mode calibration
4072 00:39:03.101343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4073 00:39:03.108101 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4074 00:39:03.111496 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4075 00:39:03.114438 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4076 00:39:03.121633 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4077 00:39:03.124568 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4078 00:39:03.127774 0 9 16 | B1->B0 | 3131 2525 | 0 0 | (0 1) (1 1)
4079 00:39:03.134788 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 00:39:03.137907 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 00:39:03.141392 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 00:39:03.148471 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 00:39:03.151490 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 00:39:03.154983 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 00:39:03.161399 0 10 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4086 00:39:03.164305 0 10 16 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
4087 00:39:03.167515 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 00:39:03.174333 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 00:39:03.177491 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 00:39:03.180752 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 00:39:03.187418 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 00:39:03.190761 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 00:39:03.194198 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4094 00:39:03.200592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4095 00:39:03.203888 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 00:39:03.207364 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 00:39:03.213741 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 00:39:03.217155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 00:39:03.220990 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 00:39:03.226836 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 00:39:03.230099 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 00:39:03.233652 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 00:39:03.240006 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 00:39:03.243475 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 00:39:03.246504 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 00:39:03.252999 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 00:39:03.256184 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 00:39:03.259904 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 00:39:03.266491 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4110 00:39:03.269585 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4111 00:39:03.273047 Total UI for P1: 0, mck2ui 16
4112 00:39:03.276380 best dqsien dly found for B1: ( 0, 13, 14)
4113 00:39:03.279756 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 00:39:03.282872 Total UI for P1: 0, mck2ui 16
4115 00:39:03.286258 best dqsien dly found for B0: ( 0, 13, 14)
4116 00:39:03.289438 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4117 00:39:03.295845 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4118 00:39:03.295999
4119 00:39:03.299188 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4120 00:39:03.302535 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4121 00:39:03.305925 [Gating] SW calibration Done
4122 00:39:03.306023 ==
4123 00:39:03.309013 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 00:39:03.312220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 00:39:03.312316 ==
4126 00:39:03.315532 RX Vref Scan: 0
4127 00:39:03.315634
4128 00:39:03.315734 RX Vref 0 -> 0, step: 1
4129 00:39:03.315830
4130 00:39:03.319568 RX Delay -230 -> 252, step: 16
4131 00:39:03.322059 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4132 00:39:03.329083 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4133 00:39:03.332480 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4134 00:39:03.335812 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4135 00:39:03.338597 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4136 00:39:03.345708 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4137 00:39:03.348611 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4138 00:39:03.351854 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4139 00:39:03.355310 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4140 00:39:03.358361 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4141 00:39:03.365074 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4142 00:39:03.368497 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4143 00:39:03.371955 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4144 00:39:03.378883 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4145 00:39:03.382025 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4146 00:39:03.385416 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4147 00:39:03.385845 ==
4148 00:39:03.388705 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 00:39:03.391628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 00:39:03.392062 ==
4151 00:39:03.395011 DQS Delay:
4152 00:39:03.395463 DQS0 = 0, DQS1 = 0
4153 00:39:03.398347 DQM Delay:
4154 00:39:03.398785 DQM0 = 43, DQM1 = 32
4155 00:39:03.399222 DQ Delay:
4156 00:39:03.401737 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4157 00:39:03.405652 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4158 00:39:03.408389 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4159 00:39:03.411951 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4160 00:39:03.412480
4161 00:39:03.412923
4162 00:39:03.415553 ==
4163 00:39:03.415992 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 00:39:03.422271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 00:39:03.422794 ==
4166 00:39:03.423132
4167 00:39:03.423445
4168 00:39:03.424911 TX Vref Scan disable
4169 00:39:03.425338 == TX Byte 0 ==
4170 00:39:03.431502 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4171 00:39:03.435500 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4172 00:39:03.436037 == TX Byte 1 ==
4173 00:39:03.441523 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4174 00:39:03.444354 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4175 00:39:03.444839 ==
4176 00:39:03.448126 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 00:39:03.451320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 00:39:03.451860 ==
4179 00:39:03.452306
4180 00:39:03.452718
4181 00:39:03.454304 TX Vref Scan disable
4182 00:39:03.457825 == TX Byte 0 ==
4183 00:39:03.461660 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4184 00:39:03.464434 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4185 00:39:03.467523 == TX Byte 1 ==
4186 00:39:03.471019 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4187 00:39:03.474334 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4188 00:39:03.477209
4189 00:39:03.477646 [DATLAT]
4190 00:39:03.478080 Freq=600, CH0 RK0
4191 00:39:03.478572
4192 00:39:03.481001 DATLAT Default: 0x9
4193 00:39:03.481426 0, 0xFFFF, sum = 0
4194 00:39:03.484215 1, 0xFFFF, sum = 0
4195 00:39:03.484649 2, 0xFFFF, sum = 0
4196 00:39:03.487453 3, 0xFFFF, sum = 0
4197 00:39:03.490751 4, 0xFFFF, sum = 0
4198 00:39:03.491186 5, 0xFFFF, sum = 0
4199 00:39:03.493748 6, 0xFFFF, sum = 0
4200 00:39:03.494208 7, 0xFFFF, sum = 0
4201 00:39:03.498142 8, 0x0, sum = 1
4202 00:39:03.498718 9, 0x0, sum = 2
4203 00:39:03.499070 10, 0x0, sum = 3
4204 00:39:03.500595 11, 0x0, sum = 4
4205 00:39:03.501099 best_step = 9
4206 00:39:03.501601
4207 00:39:03.501959 ==
4208 00:39:03.503852 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 00:39:03.510702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 00:39:03.511234 ==
4211 00:39:03.511622 RX Vref Scan: 1
4212 00:39:03.511967
4213 00:39:03.513936 RX Vref 0 -> 0, step: 1
4214 00:39:03.514394
4215 00:39:03.517308 RX Delay -195 -> 252, step: 8
4216 00:39:03.517732
4217 00:39:03.520869 Set Vref, RX VrefLevel [Byte0]: 60
4218 00:39:03.523696 [Byte1]: 50
4219 00:39:03.524218
4220 00:39:03.526991 Final RX Vref Byte 0 = 60 to rank0
4221 00:39:03.530108 Final RX Vref Byte 1 = 50 to rank0
4222 00:39:03.533355 Final RX Vref Byte 0 = 60 to rank1
4223 00:39:03.536838 Final RX Vref Byte 1 = 50 to rank1==
4224 00:39:03.540100 Dram Type= 6, Freq= 0, CH_0, rank 0
4225 00:39:03.543490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 00:39:03.546959 ==
4227 00:39:03.547503 DQS Delay:
4228 00:39:03.547951 DQS0 = 0, DQS1 = 0
4229 00:39:03.549911 DQM Delay:
4230 00:39:03.550437 DQM0 = 44, DQM1 = 32
4231 00:39:03.553202 DQ Delay:
4232 00:39:03.553684 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =40
4233 00:39:03.556412 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4234 00:39:03.560399 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4235 00:39:03.563130 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4236 00:39:03.566667
4237 00:39:03.567148
4238 00:39:03.573327 [DQSOSCAuto] RK0, (LSB)MR18= 0x663e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4239 00:39:03.576228 CH0 RK0: MR19=808, MR18=663E
4240 00:39:03.582945 CH0_RK0: MR19=0x808, MR18=0x663E, DQSOSC=390, MR23=63, INC=172, DEC=114
4241 00:39:03.583385
4242 00:39:03.586248 ----->DramcWriteLeveling(PI) begin...
4243 00:39:03.586695 ==
4244 00:39:03.590151 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 00:39:03.592879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 00:39:03.593320 ==
4247 00:39:03.596280 Write leveling (Byte 0): 31 => 31
4248 00:39:03.599425 Write leveling (Byte 1): 31 => 31
4249 00:39:03.602795 DramcWriteLeveling(PI) end<-----
4250 00:39:03.603267
4251 00:39:03.603677 ==
4252 00:39:03.606613 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 00:39:03.609835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 00:39:03.610443 ==
4255 00:39:03.613244 [Gating] SW mode calibration
4256 00:39:03.619594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4257 00:39:03.625955 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4258 00:39:03.629694 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4259 00:39:03.636120 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4260 00:39:03.639250 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4261 00:39:03.642587 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4262 00:39:03.649738 0 9 16 | B1->B0 | 3030 2727 | 1 1 | (1 1) (0 0)
4263 00:39:03.652965 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 00:39:03.655432 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 00:39:03.662021 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 00:39:03.665517 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 00:39:03.668760 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 00:39:03.675076 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 00:39:03.678759 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4270 00:39:03.682208 0 10 16 | B1->B0 | 3c3c 4040 | 0 0 | (0 0) (0 0)
4271 00:39:03.688674 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 00:39:03.691987 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 00:39:03.695399 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 00:39:03.701870 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 00:39:03.705874 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 00:39:03.708072 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 00:39:03.714921 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4278 00:39:03.718150 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4279 00:39:03.721836 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 00:39:03.727790 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 00:39:03.731717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 00:39:03.734396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 00:39:03.741227 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 00:39:03.745129 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 00:39:03.747979 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 00:39:03.754799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 00:39:03.757988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 00:39:03.761589 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 00:39:03.767644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 00:39:03.771150 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 00:39:03.774134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 00:39:03.780645 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 00:39:03.784300 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4294 00:39:03.788163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 00:39:03.790766 Total UI for P1: 0, mck2ui 16
4296 00:39:03.794148 best dqsien dly found for B0: ( 0, 13, 12)
4297 00:39:03.797391 Total UI for P1: 0, mck2ui 16
4298 00:39:03.800513 best dqsien dly found for B1: ( 0, 13, 14)
4299 00:39:03.803677 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4300 00:39:03.807074 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4301 00:39:03.807528
4302 00:39:03.813987 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4303 00:39:03.816857 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4304 00:39:03.817277 [Gating] SW calibration Done
4305 00:39:03.820266 ==
4306 00:39:03.820684 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 00:39:03.826916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 00:39:03.827588 ==
4309 00:39:03.827990 RX Vref Scan: 0
4310 00:39:03.828303
4311 00:39:03.830141 RX Vref 0 -> 0, step: 1
4312 00:39:03.830614
4313 00:39:03.833911 RX Delay -230 -> 252, step: 16
4314 00:39:03.837289 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4315 00:39:03.840419 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4316 00:39:03.847185 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4317 00:39:03.850294 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4318 00:39:03.853548 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4319 00:39:03.857271 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4320 00:39:03.860372 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4321 00:39:03.866869 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4322 00:39:03.870518 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4323 00:39:03.873826 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4324 00:39:03.876766 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4325 00:39:03.883053 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4326 00:39:03.886519 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4327 00:39:03.890152 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4328 00:39:03.893088 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4329 00:39:03.899958 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4330 00:39:03.900404 ==
4331 00:39:03.902925 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 00:39:03.906776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 00:39:03.907209 ==
4334 00:39:03.907543 DQS Delay:
4335 00:39:03.909448 DQS0 = 0, DQS1 = 0
4336 00:39:03.909872 DQM Delay:
4337 00:39:03.912633 DQM0 = 41, DQM1 = 34
4338 00:39:03.913056 DQ Delay:
4339 00:39:03.916031 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4340 00:39:03.919451 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4341 00:39:03.923086 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4342 00:39:03.925926 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4343 00:39:03.926543
4344 00:39:03.927143
4345 00:39:03.927490 ==
4346 00:39:03.929882 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 00:39:03.935768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 00:39:03.936365 ==
4349 00:39:03.936702
4350 00:39:03.937009
4351 00:39:03.937299 TX Vref Scan disable
4352 00:39:03.939161 == TX Byte 0 ==
4353 00:39:03.942870 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4354 00:39:03.945972 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4355 00:39:03.949876 == TX Byte 1 ==
4356 00:39:03.952744 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4357 00:39:03.959273 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4358 00:39:03.959792 ==
4359 00:39:03.962759 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 00:39:03.966280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 00:39:03.966839 ==
4362 00:39:03.967310
4363 00:39:03.967780
4364 00:39:03.969447 TX Vref Scan disable
4365 00:39:03.972604 == TX Byte 0 ==
4366 00:39:03.975982 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4367 00:39:03.979213 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4368 00:39:03.982211 == TX Byte 1 ==
4369 00:39:03.985969 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4370 00:39:03.988613 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4371 00:39:03.988851
4372 00:39:03.989025 [DATLAT]
4373 00:39:03.992285 Freq=600, CH0 RK1
4374 00:39:03.992600
4375 00:39:03.995439 DATLAT Default: 0x9
4376 00:39:03.995665 0, 0xFFFF, sum = 0
4377 00:39:03.998699 1, 0xFFFF, sum = 0
4378 00:39:03.998930 2, 0xFFFF, sum = 0
4379 00:39:04.001875 3, 0xFFFF, sum = 0
4380 00:39:04.002283 4, 0xFFFF, sum = 0
4381 00:39:04.005565 5, 0xFFFF, sum = 0
4382 00:39:04.005800 6, 0xFFFF, sum = 0
4383 00:39:04.008389 7, 0xFFFF, sum = 0
4384 00:39:04.008695 8, 0x0, sum = 1
4385 00:39:04.011956 9, 0x0, sum = 2
4386 00:39:04.012187 10, 0x0, sum = 3
4387 00:39:04.014964 11, 0x0, sum = 4
4388 00:39:04.015195 best_step = 9
4389 00:39:04.015373
4390 00:39:04.015538 ==
4391 00:39:04.018364 Dram Type= 6, Freq= 0, CH_0, rank 1
4392 00:39:04.022024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 00:39:04.022381 ==
4394 00:39:04.024821 RX Vref Scan: 0
4395 00:39:04.025142
4396 00:39:04.028706 RX Vref 0 -> 0, step: 1
4397 00:39:04.028932
4398 00:39:04.029111 RX Delay -195 -> 252, step: 8
4399 00:39:04.036127 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4400 00:39:04.039658 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4401 00:39:04.043276 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4402 00:39:04.046406 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4403 00:39:04.053014 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4404 00:39:04.056546 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4405 00:39:04.059405 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4406 00:39:04.062893 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4407 00:39:04.069522 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4408 00:39:04.072992 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4409 00:39:04.076147 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4410 00:39:04.079056 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4411 00:39:04.086324 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4412 00:39:04.089597 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4413 00:39:04.092473 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4414 00:39:04.096176 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4415 00:39:04.096644 ==
4416 00:39:04.099070 Dram Type= 6, Freq= 0, CH_0, rank 1
4417 00:39:04.105851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 00:39:04.106425 ==
4419 00:39:04.106794 DQS Delay:
4420 00:39:04.108920 DQS0 = 0, DQS1 = 0
4421 00:39:04.109517 DQM Delay:
4422 00:39:04.109887 DQM0 = 41, DQM1 = 37
4423 00:39:04.112431 DQ Delay:
4424 00:39:04.115612 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4425 00:39:04.118671 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4426 00:39:04.121848 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4427 00:39:04.125032 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4428 00:39:04.125506
4429 00:39:04.125878
4430 00:39:04.131736 [DQSOSCAuto] RK1, (LSB)MR18= 0x6115, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4431 00:39:04.135702 CH0 RK1: MR19=808, MR18=6115
4432 00:39:04.141632 CH0_RK1: MR19=0x808, MR18=0x6115, DQSOSC=391, MR23=63, INC=171, DEC=114
4433 00:39:04.144804 [RxdqsGatingPostProcess] freq 600
4434 00:39:04.151560 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4435 00:39:04.152150 Pre-setting of DQS Precalculation
4436 00:39:04.158055 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4437 00:39:04.158636 ==
4438 00:39:04.161654 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 00:39:04.164713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 00:39:04.165191 ==
4441 00:39:04.171667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 00:39:04.177343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4443 00:39:04.181061 [CA 0] Center 35 (5~66) winsize 62
4444 00:39:04.184708 [CA 1] Center 35 (5~66) winsize 62
4445 00:39:04.187541 [CA 2] Center 34 (4~65) winsize 62
4446 00:39:04.191007 [CA 3] Center 33 (3~64) winsize 62
4447 00:39:04.194087 [CA 4] Center 34 (4~64) winsize 61
4448 00:39:04.197446 [CA 5] Center 34 (3~65) winsize 63
4449 00:39:04.197908
4450 00:39:04.201168 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4451 00:39:04.201724
4452 00:39:04.204097 [CATrainingPosCal] consider 1 rank data
4453 00:39:04.207346 u2DelayCellTimex100 = 270/100 ps
4454 00:39:04.210641 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4455 00:39:04.214414 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 00:39:04.217618 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 00:39:04.220903 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4458 00:39:04.227017 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4459 00:39:04.230563 CA5 delay=34 (3~65),Diff = 1 PI (9 cell)
4460 00:39:04.231120
4461 00:39:04.233620 CA PerBit enable=1, Macro0, CA PI delay=33
4462 00:39:04.234084
4463 00:39:04.237569 [CBTSetCACLKResult] CA Dly = 33
4464 00:39:04.238121 CS Dly: 4 (0~35)
4465 00:39:04.238529 ==
4466 00:39:04.240766 Dram Type= 6, Freq= 0, CH_1, rank 1
4467 00:39:04.246736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 00:39:04.247233 ==
4469 00:39:04.250382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4470 00:39:04.256837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4471 00:39:04.260054 [CA 0] Center 35 (5~66) winsize 62
4472 00:39:04.263246 [CA 1] Center 36 (6~66) winsize 61
4473 00:39:04.266489 [CA 2] Center 34 (4~65) winsize 62
4474 00:39:04.270114 [CA 3] Center 34 (3~65) winsize 63
4475 00:39:04.273354 [CA 4] Center 34 (4~65) winsize 62
4476 00:39:04.276848 [CA 5] Center 34 (3~65) winsize 63
4477 00:39:04.277407
4478 00:39:04.279684 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4479 00:39:04.280098
4480 00:39:04.284064 [CATrainingPosCal] consider 2 rank data
4481 00:39:04.286846 u2DelayCellTimex100 = 270/100 ps
4482 00:39:04.290239 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4483 00:39:04.296546 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4484 00:39:04.300136 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4485 00:39:04.302963 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4486 00:39:04.306609 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4487 00:39:04.309867 CA5 delay=34 (3~65),Diff = 1 PI (9 cell)
4488 00:39:04.310350
4489 00:39:04.313036 CA PerBit enable=1, Macro0, CA PI delay=33
4490 00:39:04.313587
4491 00:39:04.316565 [CBTSetCACLKResult] CA Dly = 33
4492 00:39:04.317166 CS Dly: 4 (0~36)
4493 00:39:04.319881
4494 00:39:04.322694 ----->DramcWriteLeveling(PI) begin...
4495 00:39:04.323161 ==
4496 00:39:04.326234 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 00:39:04.329674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 00:39:04.330294 ==
4499 00:39:04.333056 Write leveling (Byte 0): 29 => 29
4500 00:39:04.336246 Write leveling (Byte 1): 30 => 30
4501 00:39:04.339430 DramcWriteLeveling(PI) end<-----
4502 00:39:04.340048
4503 00:39:04.340415 ==
4504 00:39:04.342464 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 00:39:04.346085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 00:39:04.346587 ==
4507 00:39:04.349386 [Gating] SW mode calibration
4508 00:39:04.355548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4509 00:39:04.362198 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4510 00:39:04.365595 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4511 00:39:04.369097 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4512 00:39:04.375626 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4513 00:39:04.379021 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
4514 00:39:04.381944 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 00:39:04.388578 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 00:39:04.392508 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 00:39:04.395507 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 00:39:04.401696 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 00:39:04.405289 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 00:39:04.408506 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 00:39:04.414977 0 10 12 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
4522 00:39:04.418615 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 00:39:04.422033 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 00:39:04.428355 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 00:39:04.431925 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 00:39:04.434890 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 00:39:04.441782 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 00:39:04.445055 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 00:39:04.448370 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4530 00:39:04.454526 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 00:39:04.458253 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 00:39:04.461425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 00:39:04.467788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 00:39:04.471053 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 00:39:04.474820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 00:39:04.481425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 00:39:04.484934 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 00:39:04.488290 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 00:39:04.494038 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 00:39:04.497934 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 00:39:04.501073 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 00:39:04.507250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 00:39:04.511034 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 00:39:04.514244 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 00:39:04.520516 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4546 00:39:04.520987 Total UI for P1: 0, mck2ui 16
4547 00:39:04.526928 best dqsien dly found for B0: ( 0, 13, 10)
4548 00:39:04.530802 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 00:39:04.533845 Total UI for P1: 0, mck2ui 16
4550 00:39:04.536961 best dqsien dly found for B1: ( 0, 13, 12)
4551 00:39:04.540544 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4552 00:39:04.543602 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4553 00:39:04.544027
4554 00:39:04.546591 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4555 00:39:04.553548 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4556 00:39:04.554048 [Gating] SW calibration Done
4557 00:39:04.554409 ==
4558 00:39:04.557377 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 00:39:04.563500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 00:39:04.563923 ==
4561 00:39:04.564260 RX Vref Scan: 0
4562 00:39:04.564570
4563 00:39:04.566722 RX Vref 0 -> 0, step: 1
4564 00:39:04.567153
4565 00:39:04.570510 RX Delay -230 -> 252, step: 16
4566 00:39:04.573670 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4567 00:39:04.576916 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4568 00:39:04.579918 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4569 00:39:04.586738 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4570 00:39:04.590133 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4571 00:39:04.592983 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4572 00:39:04.596488 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4573 00:39:04.603086 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4574 00:39:04.606585 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4575 00:39:04.609828 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4576 00:39:04.613120 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4577 00:39:04.619466 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4578 00:39:04.622882 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4579 00:39:04.626250 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4580 00:39:04.629383 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4581 00:39:04.635850 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4582 00:39:04.636355 ==
4583 00:39:04.639530 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 00:39:04.642657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 00:39:04.643182 ==
4586 00:39:04.643539 DQS Delay:
4587 00:39:04.646123 DQS0 = 0, DQS1 = 0
4588 00:39:04.646679 DQM Delay:
4589 00:39:04.649114 DQM0 = 46, DQM1 = 38
4590 00:39:04.649661 DQ Delay:
4591 00:39:04.652393 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4592 00:39:04.656066 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4593 00:39:04.658998 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4594 00:39:04.662924 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4595 00:39:04.663375
4596 00:39:04.663740
4597 00:39:04.664082 ==
4598 00:39:04.665389 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 00:39:04.669259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 00:39:04.669713 ==
4601 00:39:04.672003
4602 00:39:04.672570
4603 00:39:04.673057 TX Vref Scan disable
4604 00:39:04.675376 == TX Byte 0 ==
4605 00:39:04.679179 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4606 00:39:04.682675 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4607 00:39:04.685265 == TX Byte 1 ==
4608 00:39:04.688643 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4609 00:39:04.691946 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4610 00:39:04.695438 ==
4611 00:39:04.696004 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 00:39:04.701925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 00:39:04.702500 ==
4614 00:39:04.702931
4615 00:39:04.703333
4616 00:39:04.705292 TX Vref Scan disable
4617 00:39:04.705725 == TX Byte 0 ==
4618 00:39:04.711651 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4619 00:39:04.715400 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4620 00:39:04.715828 == TX Byte 1 ==
4621 00:39:04.721784 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4622 00:39:04.724881 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4623 00:39:04.725389
4624 00:39:04.725816 [DATLAT]
4625 00:39:04.728280 Freq=600, CH1 RK0
4626 00:39:04.728708
4627 00:39:04.729136 DATLAT Default: 0x9
4628 00:39:04.731373 0, 0xFFFF, sum = 0
4629 00:39:04.734556 1, 0xFFFF, sum = 0
4630 00:39:04.735018 2, 0xFFFF, sum = 0
4631 00:39:04.738255 3, 0xFFFF, sum = 0
4632 00:39:04.738718 4, 0xFFFF, sum = 0
4633 00:39:04.741336 5, 0xFFFF, sum = 0
4634 00:39:04.741915 6, 0xFFFF, sum = 0
4635 00:39:04.744537 7, 0xFFFF, sum = 0
4636 00:39:04.744982 8, 0x0, sum = 1
4637 00:39:04.748204 9, 0x0, sum = 2
4638 00:39:04.748648 10, 0x0, sum = 3
4639 00:39:04.749013 11, 0x0, sum = 4
4640 00:39:04.751297 best_step = 9
4641 00:39:04.751856
4642 00:39:04.752352 ==
4643 00:39:04.754871 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 00:39:04.757631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 00:39:04.758085 ==
4646 00:39:04.761198 RX Vref Scan: 1
4647 00:39:04.761657
4648 00:39:04.764551 RX Vref 0 -> 0, step: 1
4649 00:39:04.765139
4650 00:39:04.765507 RX Delay -179 -> 252, step: 8
4651 00:39:04.765865
4652 00:39:04.767419 Set Vref, RX VrefLevel [Byte0]: 48
4653 00:39:04.770955 [Byte1]: 59
4654 00:39:04.775529
4655 00:39:04.775963 Final RX Vref Byte 0 = 48 to rank0
4656 00:39:04.778883 Final RX Vref Byte 1 = 59 to rank0
4657 00:39:04.782025 Final RX Vref Byte 0 = 48 to rank1
4658 00:39:04.785372 Final RX Vref Byte 1 = 59 to rank1==
4659 00:39:04.788738 Dram Type= 6, Freq= 0, CH_1, rank 0
4660 00:39:04.795014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 00:39:04.795448 ==
4662 00:39:04.795799 DQS Delay:
4663 00:39:04.798630 DQS0 = 0, DQS1 = 0
4664 00:39:04.799208 DQM Delay:
4665 00:39:04.799704 DQM0 = 49, DQM1 = 38
4666 00:39:04.801846 DQ Delay:
4667 00:39:04.805392 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4668 00:39:04.808580 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4669 00:39:04.811949 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4670 00:39:04.814991 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4671 00:39:04.815428
4672 00:39:04.815780
4673 00:39:04.821896 [DQSOSCAuto] RK0, (LSB)MR18= 0x5237, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4674 00:39:04.825024 CH1 RK0: MR19=808, MR18=5237
4675 00:39:04.831626 CH1_RK0: MR19=0x808, MR18=0x5237, DQSOSC=394, MR23=63, INC=168, DEC=112
4676 00:39:04.832061
4677 00:39:04.834652 ----->DramcWriteLeveling(PI) begin...
4678 00:39:04.835173 ==
4679 00:39:04.838242 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 00:39:04.841213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 00:39:04.841780 ==
4682 00:39:04.844721 Write leveling (Byte 0): 33 => 33
4683 00:39:04.848040 Write leveling (Byte 1): 30 => 30
4684 00:39:04.851371 DramcWriteLeveling(PI) end<-----
4685 00:39:04.851884
4686 00:39:04.852422 ==
4687 00:39:04.854520 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 00:39:04.857736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 00:39:04.861192 ==
4690 00:39:04.861803 [Gating] SW mode calibration
4691 00:39:04.871351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4692 00:39:04.874582 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4693 00:39:04.877924 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4694 00:39:04.884380 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4695 00:39:04.887654 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4696 00:39:04.891363 0 9 12 | B1->B0 | 3232 3232 | 0 0 | (0 0) (1 0)
4697 00:39:04.897874 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 00:39:04.901120 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 00:39:04.904325 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4700 00:39:04.911039 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 00:39:04.913995 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 00:39:04.917530 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 00:39:04.924296 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 00:39:04.927811 0 10 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4705 00:39:04.930734 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4706 00:39:04.937417 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 00:39:04.940547 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 00:39:04.943825 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 00:39:04.950141 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 00:39:04.953847 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 00:39:04.957184 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 00:39:04.963878 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4713 00:39:04.966777 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 00:39:04.970082 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 00:39:04.976633 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 00:39:04.980044 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 00:39:04.983628 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 00:39:04.989967 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 00:39:04.993456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 00:39:04.996654 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 00:39:05.003436 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 00:39:05.006347 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 00:39:05.010427 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 00:39:05.016327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 00:39:05.020058 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 00:39:05.022860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 00:39:05.029954 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 00:39:05.033016 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4729 00:39:05.036111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 00:39:05.039958 Total UI for P1: 0, mck2ui 16
4731 00:39:05.042753 best dqsien dly found for B0: ( 0, 13, 12)
4732 00:39:05.046056 Total UI for P1: 0, mck2ui 16
4733 00:39:05.049614 best dqsien dly found for B1: ( 0, 13, 12)
4734 00:39:05.052561 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4735 00:39:05.056182 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4736 00:39:05.056723
4737 00:39:05.062580 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4738 00:39:05.065739 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4739 00:39:05.068950 [Gating] SW calibration Done
4740 00:39:05.069371 ==
4741 00:39:05.072355 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 00:39:05.075817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 00:39:05.076255 ==
4744 00:39:05.076603 RX Vref Scan: 0
4745 00:39:05.077072
4746 00:39:05.079031 RX Vref 0 -> 0, step: 1
4747 00:39:05.079481
4748 00:39:05.082463 RX Delay -230 -> 252, step: 16
4749 00:39:05.085851 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4750 00:39:05.092276 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4751 00:39:05.095534 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4752 00:39:05.098959 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4753 00:39:05.102220 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4754 00:39:05.105499 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4755 00:39:05.112233 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4756 00:39:05.115323 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4757 00:39:05.118810 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4758 00:39:05.122137 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4759 00:39:05.128989 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4760 00:39:05.131669 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4761 00:39:05.134997 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4762 00:39:05.138634 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4763 00:39:05.144871 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4764 00:39:05.148483 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4765 00:39:05.148928 ==
4766 00:39:05.151627 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 00:39:05.154933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 00:39:05.155382 ==
4769 00:39:05.158346 DQS Delay:
4770 00:39:05.158764 DQS0 = 0, DQS1 = 0
4771 00:39:05.159091 DQM Delay:
4772 00:39:05.161660 DQM0 = 44, DQM1 = 40
4773 00:39:05.162075 DQ Delay:
4774 00:39:05.164622 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4775 00:39:05.168038 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4776 00:39:05.171361 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4777 00:39:05.174675 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4778 00:39:05.175089
4779 00:39:05.175417
4780 00:39:05.175721 ==
4781 00:39:05.178060 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 00:39:05.184280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 00:39:05.184387 ==
4784 00:39:05.184488
4785 00:39:05.184575
4786 00:39:05.184660 TX Vref Scan disable
4787 00:39:05.188517 == TX Byte 0 ==
4788 00:39:05.191613 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4789 00:39:05.198339 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4790 00:39:05.198447 == TX Byte 1 ==
4791 00:39:05.201266 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4792 00:39:05.207874 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4793 00:39:05.207976 ==
4794 00:39:05.211507 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 00:39:05.214828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 00:39:05.214909 ==
4797 00:39:05.214973
4798 00:39:05.215031
4799 00:39:05.218338 TX Vref Scan disable
4800 00:39:05.221389 == TX Byte 0 ==
4801 00:39:05.225077 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4802 00:39:05.227759 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4803 00:39:05.231051 == TX Byte 1 ==
4804 00:39:05.234714 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4805 00:39:05.237604 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4806 00:39:05.237685
4807 00:39:05.237749 [DATLAT]
4808 00:39:05.240942 Freq=600, CH1 RK1
4809 00:39:05.241023
4810 00:39:05.244241 DATLAT Default: 0x9
4811 00:39:05.244322 0, 0xFFFF, sum = 0
4812 00:39:05.247575 1, 0xFFFF, sum = 0
4813 00:39:05.247660 2, 0xFFFF, sum = 0
4814 00:39:05.251188 3, 0xFFFF, sum = 0
4815 00:39:05.251266 4, 0xFFFF, sum = 0
4816 00:39:05.254372 5, 0xFFFF, sum = 0
4817 00:39:05.254515 6, 0xFFFF, sum = 0
4818 00:39:05.257693 7, 0xFFFF, sum = 0
4819 00:39:05.257779 8, 0x0, sum = 1
4820 00:39:05.260683 9, 0x0, sum = 2
4821 00:39:05.260760 10, 0x0, sum = 3
4822 00:39:05.264271 11, 0x0, sum = 4
4823 00:39:05.264349 best_step = 9
4824 00:39:05.264412
4825 00:39:05.264474 ==
4826 00:39:05.267390 Dram Type= 6, Freq= 0, CH_1, rank 1
4827 00:39:05.270763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4828 00:39:05.270844 ==
4829 00:39:05.274398 RX Vref Scan: 0
4830 00:39:05.274478
4831 00:39:05.277279 RX Vref 0 -> 0, step: 1
4832 00:39:05.277352
4833 00:39:05.277414 RX Delay -179 -> 252, step: 8
4834 00:39:05.285353 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4835 00:39:05.288318 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4836 00:39:05.291911 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4837 00:39:05.295263 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4838 00:39:05.301576 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4839 00:39:05.304969 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4840 00:39:05.308010 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4841 00:39:05.311367 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4842 00:39:05.317979 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4843 00:39:05.321359 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4844 00:39:05.324835 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4845 00:39:05.328563 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4846 00:39:05.331195 iDelay=213, Bit 12, Center 52 (-99 ~ 204) 304
4847 00:39:05.337860 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4848 00:39:05.341211 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4849 00:39:05.344369 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4850 00:39:05.344445 ==
4851 00:39:05.348082 Dram Type= 6, Freq= 0, CH_1, rank 1
4852 00:39:05.354323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4853 00:39:05.354399 ==
4854 00:39:05.354461 DQS Delay:
4855 00:39:05.358124 DQS0 = 0, DQS1 = 0
4856 00:39:05.358260 DQM Delay:
4857 00:39:05.358325 DQM0 = 45, DQM1 = 37
4858 00:39:05.360806 DQ Delay:
4859 00:39:05.364538 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4860 00:39:05.367473 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4861 00:39:05.370983 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4862 00:39:05.373944 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4863 00:39:05.374020
4864 00:39:05.374082
4865 00:39:05.380398 [DQSOSCAuto] RK1, (LSB)MR18= 0x3429, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4866 00:39:05.383735 CH1 RK1: MR19=808, MR18=3429
4867 00:39:05.390267 CH1_RK1: MR19=0x808, MR18=0x3429, DQSOSC=400, MR23=63, INC=163, DEC=109
4868 00:39:05.393571 [RxdqsGatingPostProcess] freq 600
4869 00:39:05.397440 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4870 00:39:05.400464 Pre-setting of DQS Precalculation
4871 00:39:05.406799 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4872 00:39:05.413602 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4873 00:39:05.420487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4874 00:39:05.420567
4875 00:39:05.420630
4876 00:39:05.423552 [Calibration Summary] 1200 Mbps
4877 00:39:05.426595 CH 0, Rank 0
4878 00:39:05.426664 SW Impedance : PASS
4879 00:39:05.430082 DUTY Scan : NO K
4880 00:39:05.433153 ZQ Calibration : PASS
4881 00:39:05.433232 Jitter Meter : NO K
4882 00:39:05.436680 CBT Training : PASS
4883 00:39:05.436755 Write leveling : PASS
4884 00:39:05.439835 RX DQS gating : PASS
4885 00:39:05.443121 RX DQ/DQS(RDDQC) : PASS
4886 00:39:05.443248 TX DQ/DQS : PASS
4887 00:39:05.446655 RX DATLAT : PASS
4888 00:39:05.450063 RX DQ/DQS(Engine): PASS
4889 00:39:05.450133 TX OE : NO K
4890 00:39:05.453364 All Pass.
4891 00:39:05.453443
4892 00:39:05.453514 CH 0, Rank 1
4893 00:39:05.456315 SW Impedance : PASS
4894 00:39:05.456395 DUTY Scan : NO K
4895 00:39:05.460273 ZQ Calibration : PASS
4896 00:39:05.463447 Jitter Meter : NO K
4897 00:39:05.463528 CBT Training : PASS
4898 00:39:05.466697 Write leveling : PASS
4899 00:39:05.469577 RX DQS gating : PASS
4900 00:39:05.469657 RX DQ/DQS(RDDQC) : PASS
4901 00:39:05.472803 TX DQ/DQS : PASS
4902 00:39:05.476215 RX DATLAT : PASS
4903 00:39:05.476295 RX DQ/DQS(Engine): PASS
4904 00:39:05.479318 TX OE : NO K
4905 00:39:05.479399 All Pass.
4906 00:39:05.479462
4907 00:39:05.483159 CH 1, Rank 0
4908 00:39:05.483239 SW Impedance : PASS
4909 00:39:05.486099 DUTY Scan : NO K
4910 00:39:05.489586 ZQ Calibration : PASS
4911 00:39:05.489666 Jitter Meter : NO K
4912 00:39:05.492928 CBT Training : PASS
4913 00:39:05.496110 Write leveling : PASS
4914 00:39:05.496191 RX DQS gating : PASS
4915 00:39:05.499478 RX DQ/DQS(RDDQC) : PASS
4916 00:39:05.502309 TX DQ/DQS : PASS
4917 00:39:05.502390 RX DATLAT : PASS
4918 00:39:05.506082 RX DQ/DQS(Engine): PASS
4919 00:39:05.506186 TX OE : NO K
4920 00:39:05.508976 All Pass.
4921 00:39:05.509052
4922 00:39:05.509115 CH 1, Rank 1
4923 00:39:05.512893 SW Impedance : PASS
4924 00:39:05.512972 DUTY Scan : NO K
4925 00:39:05.515740 ZQ Calibration : PASS
4926 00:39:05.518993 Jitter Meter : NO K
4927 00:39:05.519078 CBT Training : PASS
4928 00:39:05.522999 Write leveling : PASS
4929 00:39:05.525501 RX DQS gating : PASS
4930 00:39:05.525581 RX DQ/DQS(RDDQC) : PASS
4931 00:39:05.529144 TX DQ/DQS : PASS
4932 00:39:05.532420 RX DATLAT : PASS
4933 00:39:05.532513 RX DQ/DQS(Engine): PASS
4934 00:39:05.535822 TX OE : NO K
4935 00:39:05.535891 All Pass.
4936 00:39:05.535951
4937 00:39:05.539270 DramC Write-DBI off
4938 00:39:05.542478 PER_BANK_REFRESH: Hybrid Mode
4939 00:39:05.542555 TX_TRACKING: ON
4940 00:39:05.552092 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4941 00:39:05.555608 [FAST_K] Save calibration result to emmc
4942 00:39:05.558605 dramc_set_vcore_voltage set vcore to 662500
4943 00:39:05.562077 Read voltage for 933, 3
4944 00:39:05.562153 Vio18 = 0
4945 00:39:05.562230 Vcore = 662500
4946 00:39:05.565605 Vdram = 0
4947 00:39:05.565681 Vddq = 0
4948 00:39:05.565742 Vmddr = 0
4949 00:39:05.572127 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4950 00:39:05.575681 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4951 00:39:05.578855 MEM_TYPE=3, freq_sel=17
4952 00:39:05.581800 sv_algorithm_assistance_LP4_1600
4953 00:39:05.585271 ============ PULL DRAM RESETB DOWN ============
4954 00:39:05.588588 ========== PULL DRAM RESETB DOWN end =========
4955 00:39:05.595631 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4956 00:39:05.599047 ===================================
4957 00:39:05.601971 LPDDR4 DRAM CONFIGURATION
4958 00:39:05.604897 ===================================
4959 00:39:05.604976 EX_ROW_EN[0] = 0x0
4960 00:39:05.608278 EX_ROW_EN[1] = 0x0
4961 00:39:05.608380 LP4Y_EN = 0x0
4962 00:39:05.611664 WORK_FSP = 0x0
4963 00:39:05.611739 WL = 0x3
4964 00:39:05.615134 RL = 0x3
4965 00:39:05.615208 BL = 0x2
4966 00:39:05.618487 RPST = 0x0
4967 00:39:05.618564 RD_PRE = 0x0
4968 00:39:05.621487 WR_PRE = 0x1
4969 00:39:05.621565 WR_PST = 0x0
4970 00:39:05.624757 DBI_WR = 0x0
4971 00:39:05.628174 DBI_RD = 0x0
4972 00:39:05.628279 OTF = 0x1
4973 00:39:05.631540 ===================================
4974 00:39:05.634967 ===================================
4975 00:39:05.635058 ANA top config
4976 00:39:05.638752 ===================================
4977 00:39:05.641483 DLL_ASYNC_EN = 0
4978 00:39:05.644927 ALL_SLAVE_EN = 1
4979 00:39:05.648044 NEW_RANK_MODE = 1
4980 00:39:05.651142 DLL_IDLE_MODE = 1
4981 00:39:05.651217 LP45_APHY_COMB_EN = 1
4982 00:39:05.655001 TX_ODT_DIS = 1
4983 00:39:05.657947 NEW_8X_MODE = 1
4984 00:39:05.661094 ===================================
4985 00:39:05.664439 ===================================
4986 00:39:05.667669 data_rate = 1866
4987 00:39:05.670924 CKR = 1
4988 00:39:05.670998 DQ_P2S_RATIO = 8
4989 00:39:05.674364 ===================================
4990 00:39:05.677855 CA_P2S_RATIO = 8
4991 00:39:05.681244 DQ_CA_OPEN = 0
4992 00:39:05.684540 DQ_SEMI_OPEN = 0
4993 00:39:05.687479 CA_SEMI_OPEN = 0
4994 00:39:05.690861 CA_FULL_RATE = 0
4995 00:39:05.690965 DQ_CKDIV4_EN = 1
4996 00:39:05.694819 CA_CKDIV4_EN = 1
4997 00:39:05.697941 CA_PREDIV_EN = 0
4998 00:39:05.700684 PH8_DLY = 0
4999 00:39:05.704207 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5000 00:39:05.707326 DQ_AAMCK_DIV = 4
5001 00:39:05.707407 CA_AAMCK_DIV = 4
5002 00:39:05.711139 CA_ADMCK_DIV = 4
5003 00:39:05.714330 DQ_TRACK_CA_EN = 0
5004 00:39:05.717774 CA_PICK = 933
5005 00:39:05.720740 CA_MCKIO = 933
5006 00:39:05.723782 MCKIO_SEMI = 0
5007 00:39:05.727265 PLL_FREQ = 3732
5008 00:39:05.730797 DQ_UI_PI_RATIO = 32
5009 00:39:05.730877 CA_UI_PI_RATIO = 0
5010 00:39:05.733717 ===================================
5011 00:39:05.737332 ===================================
5012 00:39:05.740339 memory_type:LPDDR4
5013 00:39:05.744324 GP_NUM : 10
5014 00:39:05.744430 SRAM_EN : 1
5015 00:39:05.747498 MD32_EN : 0
5016 00:39:05.750508 ===================================
5017 00:39:05.753927 [ANA_INIT] >>>>>>>>>>>>>>
5018 00:39:05.757516 <<<<<< [CONFIGURE PHASE]: ANA_TX
5019 00:39:05.760256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5020 00:39:05.763891 ===================================
5021 00:39:05.763964 data_rate = 1866,PCW = 0X8f00
5022 00:39:05.766782 ===================================
5023 00:39:05.769948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5024 00:39:05.776836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5025 00:39:05.784224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5026 00:39:05.786873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5027 00:39:05.790136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5028 00:39:05.793779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5029 00:39:05.796905 [ANA_INIT] flow start
5030 00:39:05.799839 [ANA_INIT] PLL >>>>>>>>
5031 00:39:05.799910 [ANA_INIT] PLL <<<<<<<<
5032 00:39:05.802958 [ANA_INIT] MIDPI >>>>>>>>
5033 00:39:05.806668 [ANA_INIT] MIDPI <<<<<<<<
5034 00:39:05.806748 [ANA_INIT] DLL >>>>>>>>
5035 00:39:05.809515 [ANA_INIT] flow end
5036 00:39:05.812956 ============ LP4 DIFF to SE enter ============
5037 00:39:05.816324 ============ LP4 DIFF to SE exit ============
5038 00:39:05.819838 [ANA_INIT] <<<<<<<<<<<<<
5039 00:39:05.823097 [Flow] Enable top DCM control >>>>>
5040 00:39:05.826157 [Flow] Enable top DCM control <<<<<
5041 00:39:05.829565 Enable DLL master slave shuffle
5042 00:39:05.836020 ==============================================================
5043 00:39:05.836104 Gating Mode config
5044 00:39:05.843493 ==============================================================
5045 00:39:05.843577 Config description:
5046 00:39:05.852588 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5047 00:39:05.859415 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5048 00:39:05.866130 SELPH_MODE 0: By rank 1: By Phase
5049 00:39:05.872759 ==============================================================
5050 00:39:05.872842 GAT_TRACK_EN = 1
5051 00:39:05.875842 RX_GATING_MODE = 2
5052 00:39:05.878978 RX_GATING_TRACK_MODE = 2
5053 00:39:05.882458 SELPH_MODE = 1
5054 00:39:05.885852 PICG_EARLY_EN = 1
5055 00:39:05.889253 VALID_LAT_VALUE = 1
5056 00:39:05.896014 ==============================================================
5057 00:39:05.899250 Enter into Gating configuration >>>>
5058 00:39:05.902129 Exit from Gating configuration <<<<
5059 00:39:05.905685 Enter into DVFS_PRE_config >>>>>
5060 00:39:05.915496 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5061 00:39:05.918556 Exit from DVFS_PRE_config <<<<<
5062 00:39:05.921829 Enter into PICG configuration >>>>
5063 00:39:05.925240 Exit from PICG configuration <<<<
5064 00:39:05.928828 [RX_INPUT] configuration >>>>>
5065 00:39:05.931728 [RX_INPUT] configuration <<<<<
5066 00:39:05.935128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5067 00:39:05.941905 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5068 00:39:05.948366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5069 00:39:05.954868 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5070 00:39:05.958336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5071 00:39:05.964797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5072 00:39:05.968389 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5073 00:39:05.975174 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5074 00:39:05.978115 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5075 00:39:05.981578 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5076 00:39:05.984697 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5077 00:39:05.991001 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5078 00:39:05.994321 ===================================
5079 00:39:05.997879 LPDDR4 DRAM CONFIGURATION
5080 00:39:06.000998 ===================================
5081 00:39:06.001079 EX_ROW_EN[0] = 0x0
5082 00:39:06.004305 EX_ROW_EN[1] = 0x0
5083 00:39:06.004386 LP4Y_EN = 0x0
5084 00:39:06.007523 WORK_FSP = 0x0
5085 00:39:06.007602 WL = 0x3
5086 00:39:06.011447 RL = 0x3
5087 00:39:06.011527 BL = 0x2
5088 00:39:06.014414 RPST = 0x0
5089 00:39:06.014495 RD_PRE = 0x0
5090 00:39:06.017598 WR_PRE = 0x1
5091 00:39:06.017678 WR_PST = 0x0
5092 00:39:06.021143 DBI_WR = 0x0
5093 00:39:06.021223 DBI_RD = 0x0
5094 00:39:06.023954 OTF = 0x1
5095 00:39:06.027362 ===================================
5096 00:39:06.031056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5097 00:39:06.034786 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5098 00:39:06.040774 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5099 00:39:06.044052 ===================================
5100 00:39:06.047375 LPDDR4 DRAM CONFIGURATION
5101 00:39:06.050354 ===================================
5102 00:39:06.050461 EX_ROW_EN[0] = 0x10
5103 00:39:06.054437 EX_ROW_EN[1] = 0x0
5104 00:39:06.054540 LP4Y_EN = 0x0
5105 00:39:06.057174 WORK_FSP = 0x0
5106 00:39:06.057280 WL = 0x3
5107 00:39:06.060390 RL = 0x3
5108 00:39:06.060470 BL = 0x2
5109 00:39:06.063935 RPST = 0x0
5110 00:39:06.064015 RD_PRE = 0x0
5111 00:39:06.066931 WR_PRE = 0x1
5112 00:39:06.067011 WR_PST = 0x0
5113 00:39:06.070646 DBI_WR = 0x0
5114 00:39:06.073961 DBI_RD = 0x0
5115 00:39:06.074042 OTF = 0x1
5116 00:39:06.076652 ===================================
5117 00:39:06.083206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5118 00:39:06.086884 nWR fixed to 30
5119 00:39:06.090648 [ModeRegInit_LP4] CH0 RK0
5120 00:39:06.090734 [ModeRegInit_LP4] CH0 RK1
5121 00:39:06.093508 [ModeRegInit_LP4] CH1 RK0
5122 00:39:06.096867 [ModeRegInit_LP4] CH1 RK1
5123 00:39:06.096947 match AC timing 9
5124 00:39:06.103454 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5125 00:39:06.106596 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5126 00:39:06.109962 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5127 00:39:06.116834 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5128 00:39:06.120086 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5129 00:39:06.120191 ==
5130 00:39:06.123003 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 00:39:06.126486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 00:39:06.126567 ==
5133 00:39:06.133653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 00:39:06.139626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5135 00:39:06.143465 [CA 0] Center 37 (7~68) winsize 62
5136 00:39:06.146639 [CA 1] Center 37 (7~68) winsize 62
5137 00:39:06.149943 [CA 2] Center 34 (4~65) winsize 62
5138 00:39:06.152937 [CA 3] Center 35 (5~65) winsize 61
5139 00:39:06.156522 [CA 4] Center 33 (3~64) winsize 62
5140 00:39:06.159592 [CA 5] Center 33 (4~63) winsize 60
5141 00:39:06.159673
5142 00:39:06.162641 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5143 00:39:06.162722
5144 00:39:06.165897 [CATrainingPosCal] consider 1 rank data
5145 00:39:06.169540 u2DelayCellTimex100 = 270/100 ps
5146 00:39:06.172585 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5147 00:39:06.176109 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5148 00:39:06.179376 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5149 00:39:06.185876 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5150 00:39:06.189149 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5151 00:39:06.192590 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5152 00:39:06.192671
5153 00:39:06.195681 CA PerBit enable=1, Macro0, CA PI delay=33
5154 00:39:06.195762
5155 00:39:06.198987 [CBTSetCACLKResult] CA Dly = 33
5156 00:39:06.199068 CS Dly: 7 (0~38)
5157 00:39:06.199131 ==
5158 00:39:06.202225 Dram Type= 6, Freq= 0, CH_0, rank 1
5159 00:39:06.209206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 00:39:06.209288 ==
5161 00:39:06.212202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5162 00:39:06.218862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5163 00:39:06.222425 [CA 0] Center 37 (7~68) winsize 62
5164 00:39:06.225667 [CA 1] Center 37 (7~68) winsize 62
5165 00:39:06.228872 [CA 2] Center 34 (4~65) winsize 62
5166 00:39:06.232185 [CA 3] Center 34 (4~65) winsize 62
5167 00:39:06.235272 [CA 4] Center 33 (3~64) winsize 62
5168 00:39:06.238972 [CA 5] Center 32 (2~63) winsize 62
5169 00:39:06.239052
5170 00:39:06.242366 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5171 00:39:06.242447
5172 00:39:06.245549 [CATrainingPosCal] consider 2 rank data
5173 00:39:06.248758 u2DelayCellTimex100 = 270/100 ps
5174 00:39:06.252450 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5175 00:39:06.258777 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5176 00:39:06.261563 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5177 00:39:06.265102 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5178 00:39:06.268594 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5179 00:39:06.271530 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5180 00:39:06.271613
5181 00:39:06.275308 CA PerBit enable=1, Macro0, CA PI delay=33
5182 00:39:06.275390
5183 00:39:06.278059 [CBTSetCACLKResult] CA Dly = 33
5184 00:39:06.281596 CS Dly: 7 (0~39)
5185 00:39:06.281677
5186 00:39:06.285093 ----->DramcWriteLeveling(PI) begin...
5187 00:39:06.285176 ==
5188 00:39:06.288079 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 00:39:06.291301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 00:39:06.291383 ==
5191 00:39:06.295043 Write leveling (Byte 0): 32 => 32
5192 00:39:06.298455 Write leveling (Byte 1): 31 => 31
5193 00:39:06.301589 DramcWriteLeveling(PI) end<-----
5194 00:39:06.301670
5195 00:39:06.301733 ==
5196 00:39:06.304553 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 00:39:06.307937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 00:39:06.308019 ==
5199 00:39:06.311586 [Gating] SW mode calibration
5200 00:39:06.317698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5201 00:39:06.324338 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5202 00:39:06.327623 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5203 00:39:06.331016 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5204 00:39:06.337584 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 00:39:06.341186 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 00:39:06.344238 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5207 00:39:06.350820 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 00:39:06.354250 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5209 00:39:06.357286 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5210 00:39:06.363971 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (1 0)
5211 00:39:06.367136 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 00:39:06.370571 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 00:39:06.377210 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 00:39:06.380468 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 00:39:06.384289 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 00:39:06.390090 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 00:39:06.393726 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
5218 00:39:06.396825 1 0 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
5219 00:39:06.403469 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 00:39:06.407366 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 00:39:06.410244 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 00:39:06.416939 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 00:39:06.420379 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 00:39:06.423675 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5225 00:39:06.430022 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5226 00:39:06.433388 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5227 00:39:06.436729 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5228 00:39:06.443497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 00:39:06.446331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 00:39:06.450011 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 00:39:06.456922 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 00:39:06.459824 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 00:39:06.462832 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 00:39:06.469410 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 00:39:06.472925 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 00:39:06.476215 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 00:39:06.482781 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 00:39:06.485747 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 00:39:06.489678 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 00:39:06.495913 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 00:39:06.499132 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 00:39:06.502451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5243 00:39:06.505400 Total UI for P1: 0, mck2ui 16
5244 00:39:06.508732 best dqsien dly found for B0: ( 1, 2, 30)
5245 00:39:06.515287 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5246 00:39:06.519177 Total UI for P1: 0, mck2ui 16
5247 00:39:06.522325 best dqsien dly found for B1: ( 1, 3, 0)
5248 00:39:06.525727 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5249 00:39:06.528811 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5250 00:39:06.528887
5251 00:39:06.532012 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5252 00:39:06.535519 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5253 00:39:06.538932 [Gating] SW calibration Done
5254 00:39:06.539008 ==
5255 00:39:06.542120 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 00:39:06.545113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 00:39:06.545186 ==
5258 00:39:06.548419 RX Vref Scan: 0
5259 00:39:06.548497
5260 00:39:06.552034 RX Vref 0 -> 0, step: 1
5261 00:39:06.552108
5262 00:39:06.552169 RX Delay -80 -> 252, step: 8
5263 00:39:06.558529 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5264 00:39:06.561786 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5265 00:39:06.565165 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5266 00:39:06.568081 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5267 00:39:06.571562 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5268 00:39:06.574875 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5269 00:39:06.581760 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5270 00:39:06.584976 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5271 00:39:06.587829 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5272 00:39:06.591141 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5273 00:39:06.594863 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5274 00:39:06.601505 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5275 00:39:06.604655 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5276 00:39:06.607600 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5277 00:39:06.611304 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5278 00:39:06.614453 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5279 00:39:06.614534 ==
5280 00:39:06.617584 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 00:39:06.624519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 00:39:06.624600 ==
5283 00:39:06.624663 DQS Delay:
5284 00:39:06.627529 DQS0 = 0, DQS1 = 0
5285 00:39:06.627610 DQM Delay:
5286 00:39:06.630696 DQM0 = 96, DQM1 = 86
5287 00:39:06.630776 DQ Delay:
5288 00:39:06.634617 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5289 00:39:06.637613 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5290 00:39:06.641069 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5291 00:39:06.644367 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5292 00:39:06.644450
5293 00:39:06.644534
5294 00:39:06.644618 ==
5295 00:39:06.647768 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 00:39:06.650652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 00:39:06.650737 ==
5298 00:39:06.650821
5299 00:39:06.650899
5300 00:39:06.654187 TX Vref Scan disable
5301 00:39:06.657490 == TX Byte 0 ==
5302 00:39:06.660896 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5303 00:39:06.663762 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5304 00:39:06.667329 == TX Byte 1 ==
5305 00:39:06.670836 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5306 00:39:06.674260 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5307 00:39:06.674352 ==
5308 00:39:06.677252 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 00:39:06.683611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 00:39:06.683693 ==
5311 00:39:06.683755
5312 00:39:06.683814
5313 00:39:06.683870 TX Vref Scan disable
5314 00:39:06.687550 == TX Byte 0 ==
5315 00:39:06.691175 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5316 00:39:06.694792 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5317 00:39:06.697661 == TX Byte 1 ==
5318 00:39:06.700786 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5319 00:39:06.707356 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5320 00:39:06.707485
5321 00:39:06.707579 [DATLAT]
5322 00:39:06.707683 Freq=933, CH0 RK0
5323 00:39:06.707756
5324 00:39:06.710543 DATLAT Default: 0xd
5325 00:39:06.710643 0, 0xFFFF, sum = 0
5326 00:39:06.713956 1, 0xFFFF, sum = 0
5327 00:39:06.717390 2, 0xFFFF, sum = 0
5328 00:39:06.717515 3, 0xFFFF, sum = 0
5329 00:39:06.720785 4, 0xFFFF, sum = 0
5330 00:39:06.720870 5, 0xFFFF, sum = 0
5331 00:39:06.723690 6, 0xFFFF, sum = 0
5332 00:39:06.723774 7, 0xFFFF, sum = 0
5333 00:39:06.727231 8, 0xFFFF, sum = 0
5334 00:39:06.727312 9, 0xFFFF, sum = 0
5335 00:39:06.730352 10, 0x0, sum = 1
5336 00:39:06.730434 11, 0x0, sum = 2
5337 00:39:06.733939 12, 0x0, sum = 3
5338 00:39:06.734047 13, 0x0, sum = 4
5339 00:39:06.734140 best_step = 11
5340 00:39:06.737003
5341 00:39:06.737111 ==
5342 00:39:06.740521 Dram Type= 6, Freq= 0, CH_0, rank 0
5343 00:39:06.743758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 00:39:06.743842 ==
5345 00:39:06.743906 RX Vref Scan: 1
5346 00:39:06.743966
5347 00:39:06.747162 RX Vref 0 -> 0, step: 1
5348 00:39:06.747250
5349 00:39:06.750352 RX Delay -61 -> 252, step: 4
5350 00:39:06.750467
5351 00:39:06.753997 Set Vref, RX VrefLevel [Byte0]: 60
5352 00:39:06.757186 [Byte1]: 50
5353 00:39:06.760182
5354 00:39:06.760280 Final RX Vref Byte 0 = 60 to rank0
5355 00:39:06.763313 Final RX Vref Byte 1 = 50 to rank0
5356 00:39:06.766835 Final RX Vref Byte 0 = 60 to rank1
5357 00:39:06.770657 Final RX Vref Byte 1 = 50 to rank1==
5358 00:39:06.773419 Dram Type= 6, Freq= 0, CH_0, rank 0
5359 00:39:06.779954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 00:39:06.780037 ==
5361 00:39:06.780102 DQS Delay:
5362 00:39:06.783317 DQS0 = 0, DQS1 = 0
5363 00:39:06.783399 DQM Delay:
5364 00:39:06.783463 DQM0 = 96, DQM1 = 85
5365 00:39:06.786471 DQ Delay:
5366 00:39:06.789682 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5367 00:39:06.793837 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =106
5368 00:39:06.796390 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5369 00:39:06.799945 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =92
5370 00:39:06.800032
5371 00:39:06.800097
5372 00:39:06.806185 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5373 00:39:06.809596 CH0 RK0: MR19=505, MR18=2B12
5374 00:39:06.816272 CH0_RK0: MR19=0x505, MR18=0x2B12, DQSOSC=408, MR23=63, INC=65, DEC=43
5375 00:39:06.816385
5376 00:39:06.819693 ----->DramcWriteLeveling(PI) begin...
5377 00:39:06.819797 ==
5378 00:39:06.823293 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 00:39:06.826138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 00:39:06.826230 ==
5381 00:39:06.829800 Write leveling (Byte 0): 35 => 35
5382 00:39:06.832644 Write leveling (Byte 1): 34 => 34
5383 00:39:06.836114 DramcWriteLeveling(PI) end<-----
5384 00:39:06.836219
5385 00:39:06.836309 ==
5386 00:39:06.839305 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 00:39:06.842602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 00:39:06.845876 ==
5389 00:39:06.845975 [Gating] SW mode calibration
5390 00:39:06.855869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5391 00:39:06.859034 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5392 00:39:06.862086 0 14 0 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
5393 00:39:06.869452 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 00:39:06.872319 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 00:39:06.875859 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 00:39:06.882037 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 00:39:06.885328 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 00:39:06.888545 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 00:39:06.895457 0 14 28 | B1->B0 | 3232 2c2c | 1 1 | (1 1) (1 1)
5400 00:39:06.898546 0 15 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (1 0)
5401 00:39:06.901986 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 00:39:06.909034 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 00:39:06.912166 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 00:39:06.915203 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 00:39:06.922055 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 00:39:06.925613 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 00:39:06.928443 0 15 28 | B1->B0 | 2827 3a3a | 1 1 | (0 0) (0 0)
5408 00:39:06.935003 1 0 0 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
5409 00:39:06.938376 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 00:39:06.941605 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 00:39:06.948425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 00:39:06.951655 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 00:39:06.954674 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 00:39:06.961589 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 00:39:06.964572 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 00:39:06.967679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5417 00:39:06.975118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 00:39:06.977987 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 00:39:06.981392 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 00:39:06.987922 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 00:39:06.991371 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 00:39:06.994055 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 00:39:07.001001 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 00:39:07.004795 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 00:39:07.007885 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 00:39:07.014299 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 00:39:07.017452 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 00:39:07.020550 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 00:39:07.027170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 00:39:07.030365 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 00:39:07.033806 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5432 00:39:07.040333 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 00:39:07.043619 Total UI for P1: 0, mck2ui 16
5434 00:39:07.046688 best dqsien dly found for B0: ( 1, 2, 28)
5435 00:39:07.050579 Total UI for P1: 0, mck2ui 16
5436 00:39:07.053774 best dqsien dly found for B1: ( 1, 2, 28)
5437 00:39:07.056924 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5438 00:39:07.060369 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5439 00:39:07.060486
5440 00:39:07.063669 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5441 00:39:07.067027 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5442 00:39:07.070129 [Gating] SW calibration Done
5443 00:39:07.070264 ==
5444 00:39:07.073666 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 00:39:07.076552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 00:39:07.076648 ==
5447 00:39:07.080030 RX Vref Scan: 0
5448 00:39:07.080137
5449 00:39:07.083232 RX Vref 0 -> 0, step: 1
5450 00:39:07.083332
5451 00:39:07.083430 RX Delay -80 -> 252, step: 8
5452 00:39:07.089748 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5453 00:39:07.092786 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5454 00:39:07.096405 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5455 00:39:07.099748 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5456 00:39:07.103409 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5457 00:39:07.106503 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5458 00:39:07.113508 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5459 00:39:07.116689 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5460 00:39:07.119540 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5461 00:39:07.123107 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5462 00:39:07.126207 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5463 00:39:07.132782 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5464 00:39:07.136246 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5465 00:39:07.139422 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5466 00:39:07.142887 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5467 00:39:07.145925 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5468 00:39:07.146002 ==
5469 00:39:07.149184 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 00:39:07.155744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 00:39:07.155845 ==
5472 00:39:07.155945 DQS Delay:
5473 00:39:07.159058 DQS0 = 0, DQS1 = 0
5474 00:39:07.159126 DQM Delay:
5475 00:39:07.162329 DQM0 = 96, DQM1 = 86
5476 00:39:07.162427 DQ Delay:
5477 00:39:07.165686 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5478 00:39:07.168831 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5479 00:39:07.172206 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =79
5480 00:39:07.175680 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5481 00:39:07.175773
5482 00:39:07.175859
5483 00:39:07.175934 ==
5484 00:39:07.179064 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 00:39:07.182414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 00:39:07.182484 ==
5487 00:39:07.182544
5488 00:39:07.182600
5489 00:39:07.185694 TX Vref Scan disable
5490 00:39:07.188678 == TX Byte 0 ==
5491 00:39:07.192113 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5492 00:39:07.195854 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5493 00:39:07.198525 == TX Byte 1 ==
5494 00:39:07.202088 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5495 00:39:07.205803 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5496 00:39:07.205879 ==
5497 00:39:07.208670 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 00:39:07.212211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 00:39:07.215374 ==
5500 00:39:07.215461
5501 00:39:07.215523
5502 00:39:07.215580 TX Vref Scan disable
5503 00:39:07.219191 == TX Byte 0 ==
5504 00:39:07.222568 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5505 00:39:07.228762 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5506 00:39:07.228862 == TX Byte 1 ==
5507 00:39:07.232300 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5508 00:39:07.239094 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5509 00:39:07.239183
5510 00:39:07.239277 [DATLAT]
5511 00:39:07.239371 Freq=933, CH0 RK1
5512 00:39:07.239460
5513 00:39:07.242354 DATLAT Default: 0xb
5514 00:39:07.245241 0, 0xFFFF, sum = 0
5515 00:39:07.245339 1, 0xFFFF, sum = 0
5516 00:39:07.248754 2, 0xFFFF, sum = 0
5517 00:39:07.248853 3, 0xFFFF, sum = 0
5518 00:39:07.251823 4, 0xFFFF, sum = 0
5519 00:39:07.251894 5, 0xFFFF, sum = 0
5520 00:39:07.255569 6, 0xFFFF, sum = 0
5521 00:39:07.255648 7, 0xFFFF, sum = 0
5522 00:39:07.258782 8, 0xFFFF, sum = 0
5523 00:39:07.258858 9, 0xFFFF, sum = 0
5524 00:39:07.262068 10, 0x0, sum = 1
5525 00:39:07.262175 11, 0x0, sum = 2
5526 00:39:07.265285 12, 0x0, sum = 3
5527 00:39:07.265385 13, 0x0, sum = 4
5528 00:39:07.268404 best_step = 11
5529 00:39:07.268494
5530 00:39:07.268581 ==
5531 00:39:07.271963 Dram Type= 6, Freq= 0, CH_0, rank 1
5532 00:39:07.274760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 00:39:07.274848 ==
5534 00:39:07.274936 RX Vref Scan: 0
5535 00:39:07.278381
5536 00:39:07.278468 RX Vref 0 -> 0, step: 1
5537 00:39:07.278555
5538 00:39:07.281534 RX Delay -69 -> 252, step: 4
5539 00:39:07.288515 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5540 00:39:07.291474 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5541 00:39:07.294894 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5542 00:39:07.297989 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5543 00:39:07.301411 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5544 00:39:07.308487 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5545 00:39:07.311292 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5546 00:39:07.314364 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5547 00:39:07.317945 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5548 00:39:07.321427 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5549 00:39:07.327723 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5550 00:39:07.330945 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5551 00:39:07.334478 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5552 00:39:07.337853 iDelay=203, Bit 13, Center 90 (-5 ~ 186) 192
5553 00:39:07.341540 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5554 00:39:07.347477 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5555 00:39:07.347560 ==
5556 00:39:07.351064 Dram Type= 6, Freq= 0, CH_0, rank 1
5557 00:39:07.354454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 00:39:07.354537 ==
5559 00:39:07.354601 DQS Delay:
5560 00:39:07.357389 DQS0 = 0, DQS1 = 0
5561 00:39:07.357471 DQM Delay:
5562 00:39:07.360537 DQM0 = 94, DQM1 = 85
5563 00:39:07.360619 DQ Delay:
5564 00:39:07.363902 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5565 00:39:07.367030 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5566 00:39:07.370752 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5567 00:39:07.373643 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5568 00:39:07.373725
5569 00:39:07.373789
5570 00:39:07.380363 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5571 00:39:07.383510 CH0 RK1: MR19=504, MR18=25F5
5572 00:39:07.390289 CH0_RK1: MR19=0x504, MR18=0x25F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5573 00:39:07.393620 [RxdqsGatingPostProcess] freq 933
5574 00:39:07.399937 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5575 00:39:07.403493 best DQS0 dly(2T, 0.5T) = (0, 10)
5576 00:39:07.406939 best DQS1 dly(2T, 0.5T) = (0, 11)
5577 00:39:07.410384 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5578 00:39:07.413302 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5579 00:39:07.416770 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 00:39:07.416870 best DQS1 dly(2T, 0.5T) = (0, 10)
5581 00:39:07.420046 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 00:39:07.423086 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5583 00:39:07.426879 Pre-setting of DQS Precalculation
5584 00:39:07.433431 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5585 00:39:07.433530 ==
5586 00:39:07.436696 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 00:39:07.439913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 00:39:07.439992 ==
5589 00:39:07.446297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5590 00:39:07.453325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5591 00:39:07.456361 [CA 0] Center 36 (6~67) winsize 62
5592 00:39:07.459901 [CA 1] Center 37 (6~68) winsize 63
5593 00:39:07.462736 [CA 2] Center 34 (4~65) winsize 62
5594 00:39:07.466051 [CA 3] Center 33 (3~64) winsize 62
5595 00:39:07.469094 [CA 4] Center 34 (4~64) winsize 61
5596 00:39:07.472849 [CA 5] Center 33 (3~64) winsize 62
5597 00:39:07.472963
5598 00:39:07.475962 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5599 00:39:07.476061
5600 00:39:07.479244 [CATrainingPosCal] consider 1 rank data
5601 00:39:07.482670 u2DelayCellTimex100 = 270/100 ps
5602 00:39:07.485816 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5603 00:39:07.489042 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5604 00:39:07.492326 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5605 00:39:07.495735 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5606 00:39:07.498937 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5607 00:39:07.502314 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5608 00:39:07.505366
5609 00:39:07.508861 CA PerBit enable=1, Macro0, CA PI delay=33
5610 00:39:07.508944
5611 00:39:07.512064 [CBTSetCACLKResult] CA Dly = 33
5612 00:39:07.512174 CS Dly: 6 (0~37)
5613 00:39:07.512296 ==
5614 00:39:07.515376 Dram Type= 6, Freq= 0, CH_1, rank 1
5615 00:39:07.518737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 00:39:07.521858 ==
5617 00:39:07.525197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5618 00:39:07.531876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5619 00:39:07.534917 [CA 0] Center 36 (6~67) winsize 62
5620 00:39:07.538567 [CA 1] Center 37 (7~67) winsize 61
5621 00:39:07.541737 [CA 2] Center 34 (4~65) winsize 62
5622 00:39:07.545207 [CA 3] Center 33 (3~64) winsize 62
5623 00:39:07.548372 [CA 4] Center 34 (3~65) winsize 63
5624 00:39:07.551805 [CA 5] Center 33 (3~64) winsize 62
5625 00:39:07.551913
5626 00:39:07.554790 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5627 00:39:07.554890
5628 00:39:07.558000 [CATrainingPosCal] consider 2 rank data
5629 00:39:07.561598 u2DelayCellTimex100 = 270/100 ps
5630 00:39:07.564777 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5631 00:39:07.568049 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5632 00:39:07.571724 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5633 00:39:07.578214 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5634 00:39:07.581179 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5635 00:39:07.584392 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5636 00:39:07.584474
5637 00:39:07.587788 CA PerBit enable=1, Macro0, CA PI delay=33
5638 00:39:07.587871
5639 00:39:07.591147 [CBTSetCACLKResult] CA Dly = 33
5640 00:39:07.591223 CS Dly: 7 (0~39)
5641 00:39:07.591296
5642 00:39:07.594487 ----->DramcWriteLeveling(PI) begin...
5643 00:39:07.597782 ==
5644 00:39:07.600944 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 00:39:07.604399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 00:39:07.604503 ==
5647 00:39:07.607412 Write leveling (Byte 0): 23 => 23
5648 00:39:07.610690 Write leveling (Byte 1): 31 => 31
5649 00:39:07.614053 DramcWriteLeveling(PI) end<-----
5650 00:39:07.614155
5651 00:39:07.614256 ==
5652 00:39:07.617800 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 00:39:07.620646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 00:39:07.620745 ==
5655 00:39:07.624046 [Gating] SW mode calibration
5656 00:39:07.630626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5657 00:39:07.637361 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5658 00:39:07.640312 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5659 00:39:07.643671 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 00:39:07.650441 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 00:39:07.653608 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 00:39:07.656747 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 00:39:07.663818 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 00:39:07.666888 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 0)
5665 00:39:07.669908 0 14 28 | B1->B0 | 2d2d 2a2a | 1 1 | (1 0) (1 0)
5666 00:39:07.676311 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5667 00:39:07.680374 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 00:39:07.683597 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 00:39:07.689716 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 00:39:07.693572 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 00:39:07.696502 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 00:39:07.702968 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5673 00:39:07.706285 0 15 28 | B1->B0 | 3333 3a3a | 0 0 | (0 0) (0 0)
5674 00:39:07.709316 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 00:39:07.716169 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 00:39:07.719417 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 00:39:07.722351 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 00:39:07.729478 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 00:39:07.732501 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 00:39:07.735642 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5681 00:39:07.742463 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 00:39:07.745663 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 00:39:07.748677 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 00:39:07.755739 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 00:39:07.759119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 00:39:07.762050 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 00:39:07.769029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 00:39:07.772155 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 00:39:07.775424 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 00:39:07.782380 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 00:39:07.785197 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 00:39:07.788543 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 00:39:07.794964 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 00:39:07.798720 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 00:39:07.801779 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 00:39:07.808680 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5697 00:39:07.811976 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 00:39:07.815208 Total UI for P1: 0, mck2ui 16
5699 00:39:07.818694 best dqsien dly found for B0: ( 1, 2, 24)
5700 00:39:07.821528 Total UI for P1: 0, mck2ui 16
5701 00:39:07.825337 best dqsien dly found for B1: ( 1, 2, 26)
5702 00:39:07.828202 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5703 00:39:07.831763 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5704 00:39:07.831844
5705 00:39:07.834655 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5706 00:39:07.837839 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5707 00:39:07.841383 [Gating] SW calibration Done
5708 00:39:07.841464 ==
5709 00:39:07.844710 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 00:39:07.851483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 00:39:07.851578 ==
5712 00:39:07.851643 RX Vref Scan: 0
5713 00:39:07.851703
5714 00:39:07.854848 RX Vref 0 -> 0, step: 1
5715 00:39:07.854922
5716 00:39:07.857990 RX Delay -80 -> 252, step: 8
5717 00:39:07.861582 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5718 00:39:07.864383 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5719 00:39:07.867861 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5720 00:39:07.871560 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5721 00:39:07.877758 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5722 00:39:07.880976 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5723 00:39:07.883958 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5724 00:39:07.887780 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5725 00:39:07.890844 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5726 00:39:07.893896 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5727 00:39:07.901230 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5728 00:39:07.903843 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5729 00:39:07.907253 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5730 00:39:07.910844 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5731 00:39:07.914025 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5732 00:39:07.920593 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5733 00:39:07.920675 ==
5734 00:39:07.923917 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 00:39:07.926961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 00:39:07.927043 ==
5737 00:39:07.927106 DQS Delay:
5738 00:39:07.930688 DQS0 = 0, DQS1 = 0
5739 00:39:07.930769 DQM Delay:
5740 00:39:07.933638 DQM0 = 100, DQM1 = 91
5741 00:39:07.933719 DQ Delay:
5742 00:39:07.937136 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5743 00:39:07.940125 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5744 00:39:07.943991 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5745 00:39:07.947153 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5746 00:39:07.947234
5747 00:39:07.947298
5748 00:39:07.947356 ==
5749 00:39:07.950270 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 00:39:07.953697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 00:39:07.957122 ==
5752 00:39:07.957202
5753 00:39:07.957265
5754 00:39:07.957323 TX Vref Scan disable
5755 00:39:07.960144 == TX Byte 0 ==
5756 00:39:07.963364 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5757 00:39:07.967049 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5758 00:39:07.970243 == TX Byte 1 ==
5759 00:39:07.973850 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5760 00:39:07.976740 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5761 00:39:07.979887 ==
5762 00:39:07.983071 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 00:39:07.986462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 00:39:07.986549 ==
5765 00:39:07.986614
5766 00:39:07.986672
5767 00:39:07.989691 TX Vref Scan disable
5768 00:39:07.989798 == TX Byte 0 ==
5769 00:39:07.996351 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5770 00:39:08.000345 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5771 00:39:08.000419 == TX Byte 1 ==
5772 00:39:08.006347 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5773 00:39:08.009898 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5774 00:39:08.009981
5775 00:39:08.010044 [DATLAT]
5776 00:39:08.013089 Freq=933, CH1 RK0
5777 00:39:08.013170
5778 00:39:08.013232 DATLAT Default: 0xd
5779 00:39:08.016316 0, 0xFFFF, sum = 0
5780 00:39:08.016438 1, 0xFFFF, sum = 0
5781 00:39:08.019637 2, 0xFFFF, sum = 0
5782 00:39:08.022938 3, 0xFFFF, sum = 0
5783 00:39:08.023020 4, 0xFFFF, sum = 0
5784 00:39:08.025995 5, 0xFFFF, sum = 0
5785 00:39:08.026076 6, 0xFFFF, sum = 0
5786 00:39:08.029478 7, 0xFFFF, sum = 0
5787 00:39:08.029559 8, 0xFFFF, sum = 0
5788 00:39:08.032843 9, 0xFFFF, sum = 0
5789 00:39:08.032925 10, 0x0, sum = 1
5790 00:39:08.036432 11, 0x0, sum = 2
5791 00:39:08.036514 12, 0x0, sum = 3
5792 00:39:08.039561 13, 0x0, sum = 4
5793 00:39:08.039643 best_step = 11
5794 00:39:08.039705
5795 00:39:08.039763 ==
5796 00:39:08.042979 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 00:39:08.046409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 00:39:08.046490 ==
5799 00:39:08.049398 RX Vref Scan: 1
5800 00:39:08.049478
5801 00:39:08.052856 RX Vref 0 -> 0, step: 1
5802 00:39:08.052935
5803 00:39:08.052999 RX Delay -69 -> 252, step: 4
5804 00:39:08.053057
5805 00:39:08.055810 Set Vref, RX VrefLevel [Byte0]: 48
5806 00:39:08.059317 [Byte1]: 59
5807 00:39:08.063746
5808 00:39:08.063827 Final RX Vref Byte 0 = 48 to rank0
5809 00:39:08.067157 Final RX Vref Byte 1 = 59 to rank0
5810 00:39:08.070857 Final RX Vref Byte 0 = 48 to rank1
5811 00:39:08.073705 Final RX Vref Byte 1 = 59 to rank1==
5812 00:39:08.077429 Dram Type= 6, Freq= 0, CH_1, rank 0
5813 00:39:08.083853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 00:39:08.083962 ==
5815 00:39:08.084057 DQS Delay:
5816 00:39:08.087128 DQS0 = 0, DQS1 = 0
5817 00:39:08.087230 DQM Delay:
5818 00:39:08.087318 DQM0 = 100, DQM1 = 94
5819 00:39:08.090277 DQ Delay:
5820 00:39:08.093812 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5821 00:39:08.097144 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =98
5822 00:39:08.100622 DQ8 =82, DQ9 =84, DQ10 =98, DQ11 =86
5823 00:39:08.103650 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5824 00:39:08.103732
5825 00:39:08.103794
5826 00:39:08.110071 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5827 00:39:08.113472 CH1 RK0: MR19=505, MR18=1E0E
5828 00:39:08.120222 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5829 00:39:08.120303
5830 00:39:08.123442 ----->DramcWriteLeveling(PI) begin...
5831 00:39:08.123524 ==
5832 00:39:08.126523 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 00:39:08.130081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 00:39:08.133538 ==
5835 00:39:08.133620 Write leveling (Byte 0): 28 => 28
5836 00:39:08.136294 Write leveling (Byte 1): 31 => 31
5837 00:39:08.140120 DramcWriteLeveling(PI) end<-----
5838 00:39:08.140203
5839 00:39:08.140268 ==
5840 00:39:08.143253 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 00:39:08.149699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 00:39:08.149781 ==
5843 00:39:08.153135 [Gating] SW mode calibration
5844 00:39:08.159634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5845 00:39:08.162946 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5846 00:39:08.169131 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5847 00:39:08.172398 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 00:39:08.175562 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 00:39:08.182082 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 00:39:08.185819 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 00:39:08.189180 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 00:39:08.195605 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5853 00:39:08.198682 0 14 28 | B1->B0 | 2d2d 2f2f | 1 0 | (1 0) (0 1)
5854 00:39:08.202419 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5855 00:39:08.208753 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 00:39:08.211887 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 00:39:08.215377 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 00:39:08.222103 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 00:39:08.225128 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 00:39:08.228447 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5861 00:39:08.234997 0 15 28 | B1->B0 | 3939 3333 | 0 0 | (0 0) (0 0)
5862 00:39:08.237927 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 00:39:08.241187 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 00:39:08.248203 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 00:39:08.251351 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 00:39:08.254351 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 00:39:08.261284 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 00:39:08.264476 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5869 00:39:08.267746 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5870 00:39:08.274455 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5871 00:39:08.277583 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 00:39:08.280684 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 00:39:08.288059 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 00:39:08.290777 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 00:39:08.294059 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 00:39:08.300632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 00:39:08.303850 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 00:39:08.307000 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 00:39:08.313625 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 00:39:08.317163 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 00:39:08.320335 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 00:39:08.327288 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 00:39:08.329998 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 00:39:08.333644 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 00:39:08.339895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5886 00:39:08.343233 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 00:39:08.346968 Total UI for P1: 0, mck2ui 16
5888 00:39:08.350103 best dqsien dly found for B0: ( 1, 2, 28)
5889 00:39:08.354088 Total UI for P1: 0, mck2ui 16
5890 00:39:08.356702 best dqsien dly found for B1: ( 1, 2, 28)
5891 00:39:08.360193 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5892 00:39:08.363705 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5893 00:39:08.363776
5894 00:39:08.366543 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5895 00:39:08.373453 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5896 00:39:08.373535 [Gating] SW calibration Done
5897 00:39:08.373599 ==
5898 00:39:08.376740 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 00:39:08.383077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 00:39:08.383170 ==
5901 00:39:08.383252 RX Vref Scan: 0
5902 00:39:08.383329
5903 00:39:08.386394 RX Vref 0 -> 0, step: 1
5904 00:39:08.386476
5905 00:39:08.389763 RX Delay -80 -> 252, step: 8
5906 00:39:08.392748 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5907 00:39:08.396336 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5908 00:39:08.399319 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5909 00:39:08.402798 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5910 00:39:08.409594 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5911 00:39:08.412508 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5912 00:39:08.416199 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5913 00:39:08.419256 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5914 00:39:08.422784 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5915 00:39:08.428990 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5916 00:39:08.432837 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5917 00:39:08.436249 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5918 00:39:08.439178 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5919 00:39:08.443137 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5920 00:39:08.448926 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5921 00:39:08.452754 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5922 00:39:08.452840 ==
5923 00:39:08.455873 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 00:39:08.459190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 00:39:08.459276 ==
5926 00:39:08.459363 DQS Delay:
5927 00:39:08.462691 DQS0 = 0, DQS1 = 0
5928 00:39:08.462765 DQM Delay:
5929 00:39:08.465847 DQM0 = 100, DQM1 = 93
5930 00:39:08.465920 DQ Delay:
5931 00:39:08.468909 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5932 00:39:08.472534 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5933 00:39:08.475438 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5934 00:39:08.479102 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5935 00:39:08.479177
5936 00:39:08.479256
5937 00:39:08.479331 ==
5938 00:39:08.482339 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 00:39:08.488554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 00:39:08.488646 ==
5941 00:39:08.488735
5942 00:39:08.488794
5943 00:39:08.488850 TX Vref Scan disable
5944 00:39:08.492151 == TX Byte 0 ==
5945 00:39:08.495471 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5946 00:39:08.501950 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5947 00:39:08.502061 == TX Byte 1 ==
5948 00:39:08.505702 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5949 00:39:08.512453 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5950 00:39:08.512578 ==
5951 00:39:08.515515 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 00:39:08.518740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 00:39:08.518811 ==
5954 00:39:08.518870
5955 00:39:08.518926
5956 00:39:08.521828 TX Vref Scan disable
5957 00:39:08.525612 == TX Byte 0 ==
5958 00:39:08.528640 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5959 00:39:08.531838 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5960 00:39:08.534844 == TX Byte 1 ==
5961 00:39:08.538188 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5962 00:39:08.541763 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5963 00:39:08.541868
5964 00:39:08.541960 [DATLAT]
5965 00:39:08.545107 Freq=933, CH1 RK1
5966 00:39:08.545188
5967 00:39:08.548446 DATLAT Default: 0xb
5968 00:39:08.548526 0, 0xFFFF, sum = 0
5969 00:39:08.551433 1, 0xFFFF, sum = 0
5970 00:39:08.551516 2, 0xFFFF, sum = 0
5971 00:39:08.554981 3, 0xFFFF, sum = 0
5972 00:39:08.555063 4, 0xFFFF, sum = 0
5973 00:39:08.558133 5, 0xFFFF, sum = 0
5974 00:39:08.558228 6, 0xFFFF, sum = 0
5975 00:39:08.561651 7, 0xFFFF, sum = 0
5976 00:39:08.561726 8, 0xFFFF, sum = 0
5977 00:39:08.564671 9, 0xFFFF, sum = 0
5978 00:39:08.564753 10, 0x0, sum = 1
5979 00:39:08.567598 11, 0x0, sum = 2
5980 00:39:08.567680 12, 0x0, sum = 3
5981 00:39:08.571100 13, 0x0, sum = 4
5982 00:39:08.571206 best_step = 11
5983 00:39:08.571321
5984 00:39:08.571412 ==
5985 00:39:08.574871 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 00:39:08.577951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 00:39:08.581172 ==
5988 00:39:08.581266 RX Vref Scan: 0
5989 00:39:08.581329
5990 00:39:08.584438 RX Vref 0 -> 0, step: 1
5991 00:39:08.584519
5992 00:39:08.587566 RX Delay -61 -> 252, step: 4
5993 00:39:08.591481 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5994 00:39:08.594291 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5995 00:39:08.600731 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5996 00:39:08.603977 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5997 00:39:08.607106 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5998 00:39:08.610743 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5999 00:39:08.614110 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6000 00:39:08.617528 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6001 00:39:08.624074 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6002 00:39:08.627365 iDelay=207, Bit 9, Center 82 (-5 ~ 170) 176
6003 00:39:08.630344 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6004 00:39:08.633511 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6005 00:39:08.636857 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6006 00:39:08.643840 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6007 00:39:08.647035 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
6008 00:39:08.650136 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6009 00:39:08.650258 ==
6010 00:39:08.653576 Dram Type= 6, Freq= 0, CH_1, rank 1
6011 00:39:08.656720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6012 00:39:08.659987 ==
6013 00:39:08.660088 DQS Delay:
6014 00:39:08.660178 DQS0 = 0, DQS1 = 0
6015 00:39:08.663620 DQM Delay:
6016 00:39:08.663728 DQM0 = 101, DQM1 = 94
6017 00:39:08.666522 DQ Delay:
6018 00:39:08.669973 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6019 00:39:08.673316 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =98
6020 00:39:08.676477 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =84
6021 00:39:08.680147 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
6022 00:39:08.680229
6023 00:39:08.680294
6024 00:39:08.686811 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6025 00:39:08.690005 CH1 RK1: MR19=505, MR18=801
6026 00:39:08.696236 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
6027 00:39:08.699915 [RxdqsGatingPostProcess] freq 933
6028 00:39:08.702884 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6029 00:39:08.706532 best DQS0 dly(2T, 0.5T) = (0, 10)
6030 00:39:08.709814 best DQS1 dly(2T, 0.5T) = (0, 10)
6031 00:39:08.713114 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6032 00:39:08.716358 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6033 00:39:08.719407 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 00:39:08.723264 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 00:39:08.726101 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 00:39:08.729832 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 00:39:08.732819 Pre-setting of DQS Precalculation
6038 00:39:08.736066 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6039 00:39:08.745791 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6040 00:39:08.752511 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6041 00:39:08.752597
6042 00:39:08.752682
6043 00:39:08.756074 [Calibration Summary] 1866 Mbps
6044 00:39:08.756160 CH 0, Rank 0
6045 00:39:08.759244 SW Impedance : PASS
6046 00:39:08.759329 DUTY Scan : NO K
6047 00:39:08.762514 ZQ Calibration : PASS
6048 00:39:08.765867 Jitter Meter : NO K
6049 00:39:08.765952 CBT Training : PASS
6050 00:39:08.769029 Write leveling : PASS
6051 00:39:08.772417 RX DQS gating : PASS
6052 00:39:08.772503 RX DQ/DQS(RDDQC) : PASS
6053 00:39:08.775601 TX DQ/DQS : PASS
6054 00:39:08.779008 RX DATLAT : PASS
6055 00:39:08.779093 RX DQ/DQS(Engine): PASS
6056 00:39:08.782058 TX OE : NO K
6057 00:39:08.782143 All Pass.
6058 00:39:08.782301
6059 00:39:08.785573 CH 0, Rank 1
6060 00:39:08.785657 SW Impedance : PASS
6061 00:39:08.789013 DUTY Scan : NO K
6062 00:39:08.791987 ZQ Calibration : PASS
6063 00:39:08.792072 Jitter Meter : NO K
6064 00:39:08.795668 CBT Training : PASS
6065 00:39:08.798726 Write leveling : PASS
6066 00:39:08.798810 RX DQS gating : PASS
6067 00:39:08.801982 RX DQ/DQS(RDDQC) : PASS
6068 00:39:08.805352 TX DQ/DQS : PASS
6069 00:39:08.805438 RX DATLAT : PASS
6070 00:39:08.808813 RX DQ/DQS(Engine): PASS
6071 00:39:08.811665 TX OE : NO K
6072 00:39:08.811751 All Pass.
6073 00:39:08.811835
6074 00:39:08.811914 CH 1, Rank 0
6075 00:39:08.815193 SW Impedance : PASS
6076 00:39:08.818804 DUTY Scan : NO K
6077 00:39:08.818889 ZQ Calibration : PASS
6078 00:39:08.821640 Jitter Meter : NO K
6079 00:39:08.824895 CBT Training : PASS
6080 00:39:08.824979 Write leveling : PASS
6081 00:39:08.828202 RX DQS gating : PASS
6082 00:39:08.831674 RX DQ/DQS(RDDQC) : PASS
6083 00:39:08.831759 TX DQ/DQS : PASS
6084 00:39:08.835205 RX DATLAT : PASS
6085 00:39:08.835290 RX DQ/DQS(Engine): PASS
6086 00:39:08.838034 TX OE : NO K
6087 00:39:08.838146 All Pass.
6088 00:39:08.838264
6089 00:39:08.841629 CH 1, Rank 1
6090 00:39:08.841713 SW Impedance : PASS
6091 00:39:08.844681 DUTY Scan : NO K
6092 00:39:08.847916 ZQ Calibration : PASS
6093 00:39:08.848000 Jitter Meter : NO K
6094 00:39:08.851450 CBT Training : PASS
6095 00:39:08.854625 Write leveling : PASS
6096 00:39:08.854710 RX DQS gating : PASS
6097 00:39:08.857869 RX DQ/DQS(RDDQC) : PASS
6098 00:39:08.861426 TX DQ/DQS : PASS
6099 00:39:08.861511 RX DATLAT : PASS
6100 00:39:08.864288 RX DQ/DQS(Engine): PASS
6101 00:39:08.867892 TX OE : NO K
6102 00:39:08.867977 All Pass.
6103 00:39:08.868063
6104 00:39:08.870944 DramC Write-DBI off
6105 00:39:08.871028 PER_BANK_REFRESH: Hybrid Mode
6106 00:39:08.874469 TX_TRACKING: ON
6107 00:39:08.884159 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6108 00:39:08.887750 [FAST_K] Save calibration result to emmc
6109 00:39:08.891145 dramc_set_vcore_voltage set vcore to 650000
6110 00:39:08.891230 Read voltage for 400, 6
6111 00:39:08.894547 Vio18 = 0
6112 00:39:08.894632 Vcore = 650000
6113 00:39:08.894717 Vdram = 0
6114 00:39:08.897393 Vddq = 0
6115 00:39:08.897478 Vmddr = 0
6116 00:39:08.900932 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6117 00:39:08.907588 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6118 00:39:08.910890 MEM_TYPE=3, freq_sel=20
6119 00:39:08.914367 sv_algorithm_assistance_LP4_800
6120 00:39:08.917326 ============ PULL DRAM RESETB DOWN ============
6121 00:39:08.920722 ========== PULL DRAM RESETB DOWN end =========
6122 00:39:08.927141 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6123 00:39:08.930533 ===================================
6124 00:39:08.930619 LPDDR4 DRAM CONFIGURATION
6125 00:39:08.933696 ===================================
6126 00:39:08.937032 EX_ROW_EN[0] = 0x0
6127 00:39:08.940179 EX_ROW_EN[1] = 0x0
6128 00:39:08.940264 LP4Y_EN = 0x0
6129 00:39:08.943536 WORK_FSP = 0x0
6130 00:39:08.943636 WL = 0x2
6131 00:39:08.947611 RL = 0x2
6132 00:39:08.947695 BL = 0x2
6133 00:39:08.950390 RPST = 0x0
6134 00:39:08.950474 RD_PRE = 0x0
6135 00:39:08.953590 WR_PRE = 0x1
6136 00:39:08.953674 WR_PST = 0x0
6137 00:39:08.957081 DBI_WR = 0x0
6138 00:39:08.957166 DBI_RD = 0x0
6139 00:39:08.960341 OTF = 0x1
6140 00:39:08.963839 ===================================
6141 00:39:08.966883 ===================================
6142 00:39:08.966967 ANA top config
6143 00:39:08.969981 ===================================
6144 00:39:08.973696 DLL_ASYNC_EN = 0
6145 00:39:08.976847 ALL_SLAVE_EN = 1
6146 00:39:08.980084 NEW_RANK_MODE = 1
6147 00:39:08.980170 DLL_IDLE_MODE = 1
6148 00:39:08.983085 LP45_APHY_COMB_EN = 1
6149 00:39:08.986460 TX_ODT_DIS = 1
6150 00:39:08.989841 NEW_8X_MODE = 1
6151 00:39:08.993000 ===================================
6152 00:39:08.996315 ===================================
6153 00:39:08.999902 data_rate = 800
6154 00:39:08.999987 CKR = 1
6155 00:39:09.002881 DQ_P2S_RATIO = 4
6156 00:39:09.006592 ===================================
6157 00:39:09.009592 CA_P2S_RATIO = 4
6158 00:39:09.013098 DQ_CA_OPEN = 0
6159 00:39:09.016227 DQ_SEMI_OPEN = 1
6160 00:39:09.019612 CA_SEMI_OPEN = 1
6161 00:39:09.019697 CA_FULL_RATE = 0
6162 00:39:09.022620 DQ_CKDIV4_EN = 0
6163 00:39:09.026193 CA_CKDIV4_EN = 1
6164 00:39:09.029792 CA_PREDIV_EN = 0
6165 00:39:09.032454 PH8_DLY = 0
6166 00:39:09.035768 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6167 00:39:09.035853 DQ_AAMCK_DIV = 0
6168 00:39:09.038964 CA_AAMCK_DIV = 0
6169 00:39:09.042966 CA_ADMCK_DIV = 4
6170 00:39:09.045922 DQ_TRACK_CA_EN = 0
6171 00:39:09.049171 CA_PICK = 800
6172 00:39:09.052404 CA_MCKIO = 400
6173 00:39:09.055763 MCKIO_SEMI = 400
6174 00:39:09.059278 PLL_FREQ = 3016
6175 00:39:09.059402 DQ_UI_PI_RATIO = 32
6176 00:39:09.062813 CA_UI_PI_RATIO = 32
6177 00:39:09.065461 ===================================
6178 00:39:09.068866 ===================================
6179 00:39:09.072392 memory_type:LPDDR4
6180 00:39:09.075484 GP_NUM : 10
6181 00:39:09.075569 SRAM_EN : 1
6182 00:39:09.078874 MD32_EN : 0
6183 00:39:09.082256 ===================================
6184 00:39:09.085511 [ANA_INIT] >>>>>>>>>>>>>>
6185 00:39:09.085595 <<<<<< [CONFIGURE PHASE]: ANA_TX
6186 00:39:09.088972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6187 00:39:09.092496 ===================================
6188 00:39:09.095200 data_rate = 800,PCW = 0X7400
6189 00:39:09.098395 ===================================
6190 00:39:09.101697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6191 00:39:09.109072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6192 00:39:09.118322 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6193 00:39:09.124891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6194 00:39:09.129105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6195 00:39:09.131483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6196 00:39:09.135037 [ANA_INIT] flow start
6197 00:39:09.135122 [ANA_INIT] PLL >>>>>>>>
6198 00:39:09.138561 [ANA_INIT] PLL <<<<<<<<
6199 00:39:09.141891 [ANA_INIT] MIDPI >>>>>>>>
6200 00:39:09.141999 [ANA_INIT] MIDPI <<<<<<<<
6201 00:39:09.144890 [ANA_INIT] DLL >>>>>>>>
6202 00:39:09.148902 [ANA_INIT] flow end
6203 00:39:09.151564 ============ LP4 DIFF to SE enter ============
6204 00:39:09.155124 ============ LP4 DIFF to SE exit ============
6205 00:39:09.158177 [ANA_INIT] <<<<<<<<<<<<<
6206 00:39:09.161294 [Flow] Enable top DCM control >>>>>
6207 00:39:09.164596 [Flow] Enable top DCM control <<<<<
6208 00:39:09.167981 Enable DLL master slave shuffle
6209 00:39:09.171429 ==============================================================
6210 00:39:09.174556 Gating Mode config
6211 00:39:09.181148 ==============================================================
6212 00:39:09.181233 Config description:
6213 00:39:09.191099 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6214 00:39:09.197568 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6215 00:39:09.203974 SELPH_MODE 0: By rank 1: By Phase
6216 00:39:09.207643 ==============================================================
6217 00:39:09.210648 GAT_TRACK_EN = 0
6218 00:39:09.214034 RX_GATING_MODE = 2
6219 00:39:09.217645 RX_GATING_TRACK_MODE = 2
6220 00:39:09.220829 SELPH_MODE = 1
6221 00:39:09.224146 PICG_EARLY_EN = 1
6222 00:39:09.227099 VALID_LAT_VALUE = 1
6223 00:39:09.230537 ==============================================================
6224 00:39:09.234712 Enter into Gating configuration >>>>
6225 00:39:09.237565 Exit from Gating configuration <<<<
6226 00:39:09.240487 Enter into DVFS_PRE_config >>>>>
6227 00:39:09.253641 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6228 00:39:09.256898 Exit from DVFS_PRE_config <<<<<
6229 00:39:09.260213 Enter into PICG configuration >>>>
6230 00:39:09.263325 Exit from PICG configuration <<<<
6231 00:39:09.263410 [RX_INPUT] configuration >>>>>
6232 00:39:09.267102 [RX_INPUT] configuration <<<<<
6233 00:39:09.273623 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6234 00:39:09.276861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6235 00:39:09.283414 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6236 00:39:09.289990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6237 00:39:09.296770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6238 00:39:09.303522 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6239 00:39:09.306726 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6240 00:39:09.309938 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6241 00:39:09.316522 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6242 00:39:09.319746 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6243 00:39:09.323212 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6244 00:39:09.329419 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 00:39:09.332851 ===================================
6246 00:39:09.332934 LPDDR4 DRAM CONFIGURATION
6247 00:39:09.336229 ===================================
6248 00:39:09.339533 EX_ROW_EN[0] = 0x0
6249 00:39:09.339615 EX_ROW_EN[1] = 0x0
6250 00:39:09.342766 LP4Y_EN = 0x0
6251 00:39:09.342848 WORK_FSP = 0x0
6252 00:39:09.346094 WL = 0x2
6253 00:39:09.349182 RL = 0x2
6254 00:39:09.349264 BL = 0x2
6255 00:39:09.352823 RPST = 0x0
6256 00:39:09.352905 RD_PRE = 0x0
6257 00:39:09.356281 WR_PRE = 0x1
6258 00:39:09.356362 WR_PST = 0x0
6259 00:39:09.358914 DBI_WR = 0x0
6260 00:39:09.358996 DBI_RD = 0x0
6261 00:39:09.362441 OTF = 0x1
6262 00:39:09.365675 ===================================
6263 00:39:09.368759 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6264 00:39:09.371929 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6265 00:39:09.378753 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6266 00:39:09.381887 ===================================
6267 00:39:09.381970 LPDDR4 DRAM CONFIGURATION
6268 00:39:09.385277 ===================================
6269 00:39:09.388699 EX_ROW_EN[0] = 0x10
6270 00:39:09.391939 EX_ROW_EN[1] = 0x0
6271 00:39:09.392021 LP4Y_EN = 0x0
6272 00:39:09.395243 WORK_FSP = 0x0
6273 00:39:09.395325 WL = 0x2
6274 00:39:09.398534 RL = 0x2
6275 00:39:09.398615 BL = 0x2
6276 00:39:09.401877 RPST = 0x0
6277 00:39:09.401959 RD_PRE = 0x0
6278 00:39:09.405416 WR_PRE = 0x1
6279 00:39:09.405531 WR_PST = 0x0
6280 00:39:09.408415 DBI_WR = 0x0
6281 00:39:09.408496 DBI_RD = 0x0
6282 00:39:09.411665 OTF = 0x1
6283 00:39:09.415290 ===================================
6284 00:39:09.421522 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6285 00:39:09.424589 nWR fixed to 30
6286 00:39:09.424672 [ModeRegInit_LP4] CH0 RK0
6287 00:39:09.427886 [ModeRegInit_LP4] CH0 RK1
6288 00:39:09.431639 [ModeRegInit_LP4] CH1 RK0
6289 00:39:09.435238 [ModeRegInit_LP4] CH1 RK1
6290 00:39:09.435321 match AC timing 19
6291 00:39:09.441586 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6292 00:39:09.444375 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6293 00:39:09.447822 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6294 00:39:09.454223 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6295 00:39:09.457615 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6296 00:39:09.457698 ==
6297 00:39:09.461102 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 00:39:09.464709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 00:39:09.464791 ==
6300 00:39:09.471214 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6301 00:39:09.477850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6302 00:39:09.480978 [CA 0] Center 36 (8~64) winsize 57
6303 00:39:09.483918 [CA 1] Center 36 (8~64) winsize 57
6304 00:39:09.487260 [CA 2] Center 36 (8~64) winsize 57
6305 00:39:09.487342 [CA 3] Center 36 (8~64) winsize 57
6306 00:39:09.491155 [CA 4] Center 36 (8~64) winsize 57
6307 00:39:09.494052 [CA 5] Center 36 (8~64) winsize 57
6308 00:39:09.494149
6309 00:39:09.500597 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6310 00:39:09.500680
6311 00:39:09.503988 [CATrainingPosCal] consider 1 rank data
6312 00:39:09.506915 u2DelayCellTimex100 = 270/100 ps
6313 00:39:09.510824 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 00:39:09.513996 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 00:39:09.517196 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 00:39:09.520615 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 00:39:09.524158 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 00:39:09.526817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 00:39:09.526900
6320 00:39:09.530329 CA PerBit enable=1, Macro0, CA PI delay=36
6321 00:39:09.530411
6322 00:39:09.533492 [CBTSetCACLKResult] CA Dly = 36
6323 00:39:09.537232 CS Dly: 1 (0~32)
6324 00:39:09.537314 ==
6325 00:39:09.540235 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 00:39:09.543636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 00:39:09.543719 ==
6328 00:39:09.549908 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6329 00:39:09.557137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6330 00:39:09.560137 [CA 0] Center 36 (8~64) winsize 57
6331 00:39:09.560219 [CA 1] Center 36 (8~64) winsize 57
6332 00:39:09.563200 [CA 2] Center 36 (8~64) winsize 57
6333 00:39:09.566422 [CA 3] Center 36 (8~64) winsize 57
6334 00:39:09.570125 [CA 4] Center 36 (8~64) winsize 57
6335 00:39:09.573405 [CA 5] Center 36 (8~64) winsize 57
6336 00:39:09.573490
6337 00:39:09.576746 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6338 00:39:09.576831
6339 00:39:09.583168 [CATrainingPosCal] consider 2 rank data
6340 00:39:09.583253 u2DelayCellTimex100 = 270/100 ps
6341 00:39:09.589640 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 00:39:09.592727 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 00:39:09.596330 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 00:39:09.599421 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 00:39:09.602800 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 00:39:09.605972 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 00:39:09.606057
6348 00:39:09.609650 CA PerBit enable=1, Macro0, CA PI delay=36
6349 00:39:09.609759
6350 00:39:09.612729 [CBTSetCACLKResult] CA Dly = 36
6351 00:39:09.616044 CS Dly: 1 (0~32)
6352 00:39:09.616167
6353 00:39:09.619325 ----->DramcWriteLeveling(PI) begin...
6354 00:39:09.619411 ==
6355 00:39:09.622515 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 00:39:09.625849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 00:39:09.625959 ==
6358 00:39:09.629500 Write leveling (Byte 0): 40 => 8
6359 00:39:09.632714 Write leveling (Byte 1): 32 => 0
6360 00:39:09.635626 DramcWriteLeveling(PI) end<-----
6361 00:39:09.635708
6362 00:39:09.635772 ==
6363 00:39:09.639004 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 00:39:09.642208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 00:39:09.642291 ==
6366 00:39:09.645402 [Gating] SW mode calibration
6367 00:39:09.652202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6368 00:39:09.658964 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6369 00:39:09.661854 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6370 00:39:09.665370 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6371 00:39:09.671999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 00:39:09.675591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6373 00:39:09.678881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 00:39:09.685383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 00:39:09.688660 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6376 00:39:09.691872 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6377 00:39:09.698416 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 00:39:09.701863 Total UI for P1: 0, mck2ui 16
6379 00:39:09.704884 best dqsien dly found for B0: ( 0, 14, 24)
6380 00:39:09.708154 Total UI for P1: 0, mck2ui 16
6381 00:39:09.711690 best dqsien dly found for B1: ( 0, 14, 24)
6382 00:39:09.714986 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6383 00:39:09.718694 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6384 00:39:09.718775
6385 00:39:09.721429 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6386 00:39:09.724739 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6387 00:39:09.727894 [Gating] SW calibration Done
6388 00:39:09.727975 ==
6389 00:39:09.731728 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 00:39:09.734832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 00:39:09.734914 ==
6392 00:39:09.738116 RX Vref Scan: 0
6393 00:39:09.738222
6394 00:39:09.741618 RX Vref 0 -> 0, step: 1
6395 00:39:09.741700
6396 00:39:09.741763 RX Delay -410 -> 252, step: 16
6397 00:39:09.748388 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6398 00:39:09.751337 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6399 00:39:09.754984 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6400 00:39:09.761678 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6401 00:39:09.764950 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6402 00:39:09.768309 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6403 00:39:09.771192 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6404 00:39:09.777962 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6405 00:39:09.781208 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6406 00:39:09.784301 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6407 00:39:09.788125 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6408 00:39:09.794184 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6409 00:39:09.797644 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6410 00:39:09.800922 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6411 00:39:09.804216 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6412 00:39:09.810937 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6413 00:39:09.811021 ==
6414 00:39:09.813986 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 00:39:09.817453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 00:39:09.817536 ==
6417 00:39:09.817601 DQS Delay:
6418 00:39:09.820583 DQS0 = 43, DQS1 = 59
6419 00:39:09.820665 DQM Delay:
6420 00:39:09.823988 DQM0 = 9, DQM1 = 11
6421 00:39:09.824070 DQ Delay:
6422 00:39:09.827200 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6423 00:39:09.831086 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6424 00:39:09.833807 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6425 00:39:09.837243 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6426 00:39:09.837325
6427 00:39:09.837389
6428 00:39:09.837448 ==
6429 00:39:09.840474 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 00:39:09.843827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 00:39:09.843910 ==
6432 00:39:09.843974
6433 00:39:09.847223
6434 00:39:09.847343 TX Vref Scan disable
6435 00:39:09.851092 == TX Byte 0 ==
6436 00:39:09.853580 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 00:39:09.857266 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 00:39:09.860829 == TX Byte 1 ==
6439 00:39:09.863732 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6440 00:39:09.866816 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6441 00:39:09.866899 ==
6442 00:39:09.870515 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 00:39:09.877005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 00:39:09.877087 ==
6445 00:39:09.877152
6446 00:39:09.877211
6447 00:39:09.877268 TX Vref Scan disable
6448 00:39:09.879952 == TX Byte 0 ==
6449 00:39:09.883539 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6450 00:39:09.887063 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6451 00:39:09.890221 == TX Byte 1 ==
6452 00:39:09.893992 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6453 00:39:09.896752 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6454 00:39:09.896834
6455 00:39:09.900103 [DATLAT]
6456 00:39:09.900184 Freq=400, CH0 RK0
6457 00:39:09.900248
6458 00:39:09.903331 DATLAT Default: 0xf
6459 00:39:09.903413 0, 0xFFFF, sum = 0
6460 00:39:09.906716 1, 0xFFFF, sum = 0
6461 00:39:09.906799 2, 0xFFFF, sum = 0
6462 00:39:09.909728 3, 0xFFFF, sum = 0
6463 00:39:09.909812 4, 0xFFFF, sum = 0
6464 00:39:09.913531 5, 0xFFFF, sum = 0
6465 00:39:09.913614 6, 0xFFFF, sum = 0
6466 00:39:09.916337 7, 0xFFFF, sum = 0
6467 00:39:09.916421 8, 0xFFFF, sum = 0
6468 00:39:09.919745 9, 0xFFFF, sum = 0
6469 00:39:09.919829 10, 0xFFFF, sum = 0
6470 00:39:09.923151 11, 0xFFFF, sum = 0
6471 00:39:09.926393 12, 0xFFFF, sum = 0
6472 00:39:09.926476 13, 0x0, sum = 1
6473 00:39:09.929769 14, 0x0, sum = 2
6474 00:39:09.929851 15, 0x0, sum = 3
6475 00:39:09.929917 16, 0x0, sum = 4
6476 00:39:09.932748 best_step = 14
6477 00:39:09.932830
6478 00:39:09.932893 ==
6479 00:39:09.936252 Dram Type= 6, Freq= 0, CH_0, rank 0
6480 00:39:09.939518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 00:39:09.939610 ==
6482 00:39:09.943000 RX Vref Scan: 1
6483 00:39:09.943085
6484 00:39:09.946135 RX Vref 0 -> 0, step: 1
6485 00:39:09.946246
6486 00:39:09.946330 RX Delay -359 -> 252, step: 8
6487 00:39:09.946429
6488 00:39:09.949579 Set Vref, RX VrefLevel [Byte0]: 60
6489 00:39:09.952862 [Byte1]: 50
6490 00:39:09.958524
6491 00:39:09.958605 Final RX Vref Byte 0 = 60 to rank0
6492 00:39:09.961431 Final RX Vref Byte 1 = 50 to rank0
6493 00:39:09.964783 Final RX Vref Byte 0 = 60 to rank1
6494 00:39:09.968241 Final RX Vref Byte 1 = 50 to rank1==
6495 00:39:09.971517 Dram Type= 6, Freq= 0, CH_0, rank 0
6496 00:39:09.978148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 00:39:09.978254 ==
6498 00:39:09.978319 DQS Delay:
6499 00:39:09.981275 DQS0 = 48, DQS1 = 64
6500 00:39:09.981357 DQM Delay:
6501 00:39:09.981422 DQM0 = 11, DQM1 = 14
6502 00:39:09.984841 DQ Delay:
6503 00:39:09.987733 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6504 00:39:09.991071 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6505 00:39:09.991153 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6506 00:39:09.998150 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6507 00:39:09.998288
6508 00:39:09.998377
6509 00:39:10.004539 [DQSOSCAuto] RK0, (LSB)MR18= 0xc487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6510 00:39:10.007572 CH0 RK0: MR19=C0C, MR18=C487
6511 00:39:10.014266 CH0_RK0: MR19=0xC0C, MR18=0xC487, DQSOSC=385, MR23=63, INC=398, DEC=265
6512 00:39:10.014349 ==
6513 00:39:10.017343 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 00:39:10.020852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 00:39:10.020935 ==
6516 00:39:10.023916 [Gating] SW mode calibration
6517 00:39:10.030782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6518 00:39:10.037375 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6519 00:39:10.040687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6520 00:39:10.044002 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6521 00:39:10.050509 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 00:39:10.053742 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6523 00:39:10.056880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 00:39:10.063510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 00:39:10.067023 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6526 00:39:10.070514 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6527 00:39:10.076578 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 00:39:10.079960 Total UI for P1: 0, mck2ui 16
6529 00:39:10.083315 best dqsien dly found for B0: ( 0, 14, 24)
6530 00:39:10.083397 Total UI for P1: 0, mck2ui 16
6531 00:39:10.090169 best dqsien dly found for B1: ( 0, 14, 24)
6532 00:39:10.093435 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6533 00:39:10.096870 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6534 00:39:10.096952
6535 00:39:10.099834 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6536 00:39:10.103312 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6537 00:39:10.106403 [Gating] SW calibration Done
6538 00:39:10.106485 ==
6539 00:39:10.109620 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 00:39:10.112829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 00:39:10.112912 ==
6542 00:39:10.116100 RX Vref Scan: 0
6543 00:39:10.116182
6544 00:39:10.119710 RX Vref 0 -> 0, step: 1
6545 00:39:10.119792
6546 00:39:10.119855 RX Delay -410 -> 252, step: 16
6547 00:39:10.126755 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6548 00:39:10.129409 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6549 00:39:10.132716 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6550 00:39:10.139763 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6551 00:39:10.142996 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6552 00:39:10.145961 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6553 00:39:10.149275 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6554 00:39:10.152667 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6555 00:39:10.159370 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6556 00:39:10.162722 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6557 00:39:10.165906 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6558 00:39:10.172757 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6559 00:39:10.175977 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6560 00:39:10.179134 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6561 00:39:10.182214 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6562 00:39:10.189439 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6563 00:39:10.189521 ==
6564 00:39:10.192724 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 00:39:10.195477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 00:39:10.195563 ==
6567 00:39:10.195648 DQS Delay:
6568 00:39:10.198859 DQS0 = 43, DQS1 = 51
6569 00:39:10.198945 DQM Delay:
6570 00:39:10.202570 DQM0 = 10, DQM1 = 9
6571 00:39:10.202654 DQ Delay:
6572 00:39:10.205512 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6573 00:39:10.209417 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6574 00:39:10.212623 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6575 00:39:10.215310 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6576 00:39:10.215394
6577 00:39:10.215479
6578 00:39:10.215559 ==
6579 00:39:10.219290 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 00:39:10.222039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 00:39:10.222149 ==
6582 00:39:10.222270
6583 00:39:10.222368
6584 00:39:10.225539 TX Vref Scan disable
6585 00:39:10.228784 == TX Byte 0 ==
6586 00:39:10.232041 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6587 00:39:10.235218 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6588 00:39:10.238594 == TX Byte 1 ==
6589 00:39:10.241777 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6590 00:39:10.245525 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6591 00:39:10.245611 ==
6592 00:39:10.248840 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 00:39:10.252004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 00:39:10.252090 ==
6595 00:39:10.255190
6596 00:39:10.255274
6597 00:39:10.255360 TX Vref Scan disable
6598 00:39:10.258540 == TX Byte 0 ==
6599 00:39:10.261583 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6600 00:39:10.265166 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6601 00:39:10.268169 == TX Byte 1 ==
6602 00:39:10.271874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6603 00:39:10.274723 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6604 00:39:10.274808
6605 00:39:10.274893 [DATLAT]
6606 00:39:10.278133 Freq=400, CH0 RK1
6607 00:39:10.278257
6608 00:39:10.281613 DATLAT Default: 0xe
6609 00:39:10.281698 0, 0xFFFF, sum = 0
6610 00:39:10.284565 1, 0xFFFF, sum = 0
6611 00:39:10.284651 2, 0xFFFF, sum = 0
6612 00:39:10.288116 3, 0xFFFF, sum = 0
6613 00:39:10.288202 4, 0xFFFF, sum = 0
6614 00:39:10.291215 5, 0xFFFF, sum = 0
6615 00:39:10.291301 6, 0xFFFF, sum = 0
6616 00:39:10.294669 7, 0xFFFF, sum = 0
6617 00:39:10.294755 8, 0xFFFF, sum = 0
6618 00:39:10.298201 9, 0xFFFF, sum = 0
6619 00:39:10.298287 10, 0xFFFF, sum = 0
6620 00:39:10.301368 11, 0xFFFF, sum = 0
6621 00:39:10.301455 12, 0xFFFF, sum = 0
6622 00:39:10.304711 13, 0x0, sum = 1
6623 00:39:10.304797 14, 0x0, sum = 2
6624 00:39:10.307568 15, 0x0, sum = 3
6625 00:39:10.307654 16, 0x0, sum = 4
6626 00:39:10.311109 best_step = 14
6627 00:39:10.311194
6628 00:39:10.311278 ==
6629 00:39:10.314102 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 00:39:10.317961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 00:39:10.318063 ==
6632 00:39:10.321292 RX Vref Scan: 0
6633 00:39:10.321377
6634 00:39:10.321462 RX Vref 0 -> 0, step: 1
6635 00:39:10.321541
6636 00:39:10.324526 RX Delay -343 -> 252, step: 8
6637 00:39:10.332759 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6638 00:39:10.335420 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6639 00:39:10.339606 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6640 00:39:10.345799 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6641 00:39:10.348856 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6642 00:39:10.352019 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6643 00:39:10.355470 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6644 00:39:10.361870 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6645 00:39:10.364927 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6646 00:39:10.368928 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6647 00:39:10.371688 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6648 00:39:10.378249 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6649 00:39:10.381762 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6650 00:39:10.385001 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6651 00:39:10.387995 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6652 00:39:10.394712 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6653 00:39:10.394794 ==
6654 00:39:10.397985 Dram Type= 6, Freq= 0, CH_0, rank 1
6655 00:39:10.401223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 00:39:10.401307 ==
6657 00:39:10.404319 DQS Delay:
6658 00:39:10.404401 DQS0 = 44, DQS1 = 60
6659 00:39:10.404466 DQM Delay:
6660 00:39:10.407918 DQM0 = 7, DQM1 = 14
6661 00:39:10.408001 DQ Delay:
6662 00:39:10.411365 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6663 00:39:10.414541 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6664 00:39:10.417695 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =4
6665 00:39:10.421144 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6666 00:39:10.421226
6667 00:39:10.421290
6668 00:39:10.428131 [DQSOSCAuto] RK1, (LSB)MR18= 0xb440, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6669 00:39:10.430867 CH0 RK1: MR19=C0C, MR18=B440
6670 00:39:10.437546 CH0_RK1: MR19=0xC0C, MR18=0xB440, DQSOSC=387, MR23=63, INC=394, DEC=262
6671 00:39:10.441379 [RxdqsGatingPostProcess] freq 400
6672 00:39:10.447531 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6673 00:39:10.451205 best DQS0 dly(2T, 0.5T) = (0, 10)
6674 00:39:10.454133 best DQS1 dly(2T, 0.5T) = (0, 10)
6675 00:39:10.457422 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6676 00:39:10.460762 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6677 00:39:10.460835 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 00:39:10.464367 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 00:39:10.467230 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 00:39:10.470712 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 00:39:10.474169 Pre-setting of DQS Precalculation
6682 00:39:10.480630 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6683 00:39:10.480732 ==
6684 00:39:10.483682 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 00:39:10.487730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 00:39:10.487828 ==
6687 00:39:10.494011 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6688 00:39:10.500166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6689 00:39:10.503617 [CA 0] Center 36 (8~64) winsize 57
6690 00:39:10.506617 [CA 1] Center 36 (8~64) winsize 57
6691 00:39:10.510177 [CA 2] Center 36 (8~64) winsize 57
6692 00:39:10.510278 [CA 3] Center 36 (8~64) winsize 57
6693 00:39:10.513434 [CA 4] Center 36 (8~64) winsize 57
6694 00:39:10.516398 [CA 5] Center 36 (8~64) winsize 57
6695 00:39:10.516500
6696 00:39:10.523671 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6697 00:39:10.523776
6698 00:39:10.526468 [CATrainingPosCal] consider 1 rank data
6699 00:39:10.529771 u2DelayCellTimex100 = 270/100 ps
6700 00:39:10.533003 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 00:39:10.536830 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 00:39:10.539748 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 00:39:10.543172 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 00:39:10.546332 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 00:39:10.549944 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 00:39:10.550027
6707 00:39:10.553111 CA PerBit enable=1, Macro0, CA PI delay=36
6708 00:39:10.553210
6709 00:39:10.556050 [CBTSetCACLKResult] CA Dly = 36
6710 00:39:10.559590 CS Dly: 1 (0~32)
6711 00:39:10.559693 ==
6712 00:39:10.562889 Dram Type= 6, Freq= 0, CH_1, rank 1
6713 00:39:10.566278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 00:39:10.566354 ==
6715 00:39:10.572669 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6716 00:39:10.579701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6717 00:39:10.582594 [CA 0] Center 36 (8~64) winsize 57
6718 00:39:10.585628 [CA 1] Center 36 (8~64) winsize 57
6719 00:39:10.585703 [CA 2] Center 36 (8~64) winsize 57
6720 00:39:10.589357 [CA 3] Center 36 (8~64) winsize 57
6721 00:39:10.592393 [CA 4] Center 36 (8~64) winsize 57
6722 00:39:10.595576 [CA 5] Center 36 (8~64) winsize 57
6723 00:39:10.595675
6724 00:39:10.598992 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6725 00:39:10.602504
6726 00:39:10.605500 [CATrainingPosCal] consider 2 rank data
6727 00:39:10.605600 u2DelayCellTimex100 = 270/100 ps
6728 00:39:10.611825 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 00:39:10.615569 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 00:39:10.619102 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 00:39:10.621727 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 00:39:10.625384 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 00:39:10.628414 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 00:39:10.628493
6735 00:39:10.632103 CA PerBit enable=1, Macro0, CA PI delay=36
6736 00:39:10.632177
6737 00:39:10.635091 [CBTSetCACLKResult] CA Dly = 36
6738 00:39:10.638453 CS Dly: 1 (0~32)
6739 00:39:10.638541
6740 00:39:10.642384 ----->DramcWriteLeveling(PI) begin...
6741 00:39:10.642485 ==
6742 00:39:10.645104 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 00:39:10.648287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 00:39:10.648364 ==
6745 00:39:10.651380 Write leveling (Byte 0): 40 => 8
6746 00:39:10.655053 Write leveling (Byte 1): 32 => 0
6747 00:39:10.657949 DramcWriteLeveling(PI) end<-----
6748 00:39:10.658045
6749 00:39:10.658136 ==
6750 00:39:10.661357 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 00:39:10.664759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 00:39:10.664836 ==
6753 00:39:10.668057 [Gating] SW mode calibration
6754 00:39:10.674556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6755 00:39:10.681178 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6756 00:39:10.684752 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6757 00:39:10.691272 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6758 00:39:10.694344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 00:39:10.697583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6760 00:39:10.703893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 00:39:10.707372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 00:39:10.710591 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6763 00:39:10.717163 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6764 00:39:10.720504 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 00:39:10.724220 Total UI for P1: 0, mck2ui 16
6766 00:39:10.727063 best dqsien dly found for B0: ( 0, 14, 24)
6767 00:39:10.730652 Total UI for P1: 0, mck2ui 16
6768 00:39:10.733713 best dqsien dly found for B1: ( 0, 14, 24)
6769 00:39:10.736828 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6770 00:39:10.740534 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6771 00:39:10.740637
6772 00:39:10.743650 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6773 00:39:10.746923 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6774 00:39:10.750302 [Gating] SW calibration Done
6775 00:39:10.750376 ==
6776 00:39:10.753435 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 00:39:10.756808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 00:39:10.760083 ==
6779 00:39:10.760185 RX Vref Scan: 0
6780 00:39:10.760275
6781 00:39:10.763516 RX Vref 0 -> 0, step: 1
6782 00:39:10.763592
6783 00:39:10.766580 RX Delay -410 -> 252, step: 16
6784 00:39:10.770429 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6785 00:39:10.773858 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6786 00:39:10.776698 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6787 00:39:10.783257 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6788 00:39:10.786610 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6789 00:39:10.790392 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6790 00:39:10.793478 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6791 00:39:10.800169 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6792 00:39:10.803516 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6793 00:39:10.806822 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6794 00:39:10.810092 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6795 00:39:10.816522 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6796 00:39:10.819878 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6797 00:39:10.823469 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6798 00:39:10.829781 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6799 00:39:10.833153 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6800 00:39:10.833251 ==
6801 00:39:10.836346 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 00:39:10.839506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 00:39:10.839605 ==
6804 00:39:10.842901 DQS Delay:
6805 00:39:10.842998 DQS0 = 43, DQS1 = 51
6806 00:39:10.843088 DQM Delay:
6807 00:39:10.845934 DQM0 = 12, DQM1 = 14
6808 00:39:10.846029 DQ Delay:
6809 00:39:10.849243 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6810 00:39:10.852646 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6811 00:39:10.856039 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6812 00:39:10.859610 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6813 00:39:10.859712
6814 00:39:10.859802
6815 00:39:10.859890 ==
6816 00:39:10.862890 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 00:39:10.866092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 00:39:10.869512 ==
6819 00:39:10.869587
6820 00:39:10.869677
6821 00:39:10.869764 TX Vref Scan disable
6822 00:39:10.872573 == TX Byte 0 ==
6823 00:39:10.875734 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 00:39:10.879023 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 00:39:10.882648 == TX Byte 1 ==
6826 00:39:10.885606 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6827 00:39:10.889159 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6828 00:39:10.889237 ==
6829 00:39:10.892706 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 00:39:10.899173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 00:39:10.899256 ==
6832 00:39:10.899320
6833 00:39:10.899379
6834 00:39:10.899435 TX Vref Scan disable
6835 00:39:10.902508 == TX Byte 0 ==
6836 00:39:10.905543 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6837 00:39:10.909233 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6838 00:39:10.911946 == TX Byte 1 ==
6839 00:39:10.915407 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6840 00:39:10.922077 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6841 00:39:10.922165
6842 00:39:10.922287 [DATLAT]
6843 00:39:10.922348 Freq=400, CH1 RK0
6844 00:39:10.922406
6845 00:39:10.925367 DATLAT Default: 0xf
6846 00:39:10.925449 0, 0xFFFF, sum = 0
6847 00:39:10.928391 1, 0xFFFF, sum = 0
6848 00:39:10.928475 2, 0xFFFF, sum = 0
6849 00:39:10.931844 3, 0xFFFF, sum = 0
6850 00:39:10.935200 4, 0xFFFF, sum = 0
6851 00:39:10.935283 5, 0xFFFF, sum = 0
6852 00:39:10.938712 6, 0xFFFF, sum = 0
6853 00:39:10.938796 7, 0xFFFF, sum = 0
6854 00:39:10.942017 8, 0xFFFF, sum = 0
6855 00:39:10.942104 9, 0xFFFF, sum = 0
6856 00:39:10.945310 10, 0xFFFF, sum = 0
6857 00:39:10.945397 11, 0xFFFF, sum = 0
6858 00:39:10.948068 12, 0xFFFF, sum = 0
6859 00:39:10.948154 13, 0x0, sum = 1
6860 00:39:10.951499 14, 0x0, sum = 2
6861 00:39:10.951585 15, 0x0, sum = 3
6862 00:39:10.954585 16, 0x0, sum = 4
6863 00:39:10.954671 best_step = 14
6864 00:39:10.954757
6865 00:39:10.954836 ==
6866 00:39:10.957944 Dram Type= 6, Freq= 0, CH_1, rank 0
6867 00:39:10.964884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 00:39:10.964970 ==
6869 00:39:10.965055 RX Vref Scan: 1
6870 00:39:10.965135
6871 00:39:10.967667 RX Vref 0 -> 0, step: 1
6872 00:39:10.967751
6873 00:39:10.971868 RX Delay -343 -> 252, step: 8
6874 00:39:10.971953
6875 00:39:10.974318 Set Vref, RX VrefLevel [Byte0]: 48
6876 00:39:10.977942 [Byte1]: 59
6877 00:39:10.978027
6878 00:39:10.981296 Final RX Vref Byte 0 = 48 to rank0
6879 00:39:10.984301 Final RX Vref Byte 1 = 59 to rank0
6880 00:39:10.987937 Final RX Vref Byte 0 = 48 to rank1
6881 00:39:10.991309 Final RX Vref Byte 1 = 59 to rank1==
6882 00:39:10.994440 Dram Type= 6, Freq= 0, CH_1, rank 0
6883 00:39:10.997879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 00:39:11.000589 ==
6885 00:39:11.000673 DQS Delay:
6886 00:39:11.000759 DQS0 = 44, DQS1 = 56
6887 00:39:11.004011 DQM Delay:
6888 00:39:11.004096 DQM0 = 8, DQM1 = 12
6889 00:39:11.007177 DQ Delay:
6890 00:39:11.010647 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6891 00:39:11.010732 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6892 00:39:11.014061 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6893 00:39:11.017260 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6894 00:39:11.017346
6895 00:39:11.017431
6896 00:39:11.027191 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6897 00:39:11.030443 CH1 RK0: MR19=C0C, MR18=9C72
6898 00:39:11.037038 CH1_RK0: MR19=0xC0C, MR18=0x9C72, DQSOSC=390, MR23=63, INC=388, DEC=258
6899 00:39:11.037123 ==
6900 00:39:11.040200 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 00:39:11.043896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 00:39:11.043981 ==
6903 00:39:11.047035 [Gating] SW mode calibration
6904 00:39:11.053487 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6905 00:39:11.060415 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6906 00:39:11.063348 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6907 00:39:11.067129 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6908 00:39:11.070064 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 00:39:11.076803 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6910 00:39:11.080525 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 00:39:11.083340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 00:39:11.089909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6913 00:39:11.093067 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6914 00:39:11.096961 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 00:39:11.099950 Total UI for P1: 0, mck2ui 16
6916 00:39:11.102993 best dqsien dly found for B0: ( 0, 14, 24)
6917 00:39:11.106724 Total UI for P1: 0, mck2ui 16
6918 00:39:11.109605 best dqsien dly found for B1: ( 0, 14, 24)
6919 00:39:11.116489 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6920 00:39:11.119470 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6921 00:39:11.119552
6922 00:39:11.122924 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6923 00:39:11.126072 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6924 00:39:11.129828 [Gating] SW calibration Done
6925 00:39:11.129925 ==
6926 00:39:11.133100 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 00:39:11.136338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 00:39:11.136422 ==
6929 00:39:11.139322 RX Vref Scan: 0
6930 00:39:11.139429
6931 00:39:11.139530 RX Vref 0 -> 0, step: 1
6932 00:39:11.139608
6933 00:39:11.142835 RX Delay -410 -> 252, step: 16
6934 00:39:11.149479 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6935 00:39:11.153313 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6936 00:39:11.155999 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6937 00:39:11.159377 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6938 00:39:11.165875 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6939 00:39:11.169094 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6940 00:39:11.172445 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6941 00:39:11.175769 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6942 00:39:11.182060 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6943 00:39:11.185861 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6944 00:39:11.188800 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6945 00:39:11.192099 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6946 00:39:11.199129 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6947 00:39:11.202085 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6948 00:39:11.205527 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6949 00:39:11.212172 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6950 00:39:11.212255 ==
6951 00:39:11.215101 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 00:39:11.219159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 00:39:11.219242 ==
6954 00:39:11.219307 DQS Delay:
6955 00:39:11.221846 DQS0 = 51, DQS1 = 59
6956 00:39:11.221928 DQM Delay:
6957 00:39:11.225262 DQM0 = 20, DQM1 = 22
6958 00:39:11.225343 DQ Delay:
6959 00:39:11.228588 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6960 00:39:11.231512 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6961 00:39:11.235338 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6962 00:39:11.238575 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6963 00:39:11.238657
6964 00:39:11.238721
6965 00:39:11.238781 ==
6966 00:39:11.241904 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 00:39:11.245060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 00:39:11.245142 ==
6969 00:39:11.245206
6970 00:39:11.248152
6971 00:39:11.248259 TX Vref Scan disable
6972 00:39:11.251724 == TX Byte 0 ==
6973 00:39:11.255098 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6974 00:39:11.258003 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6975 00:39:11.261361 == TX Byte 1 ==
6976 00:39:11.264564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6977 00:39:11.267868 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6978 00:39:11.267978 ==
6979 00:39:11.271196 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 00:39:11.274627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 00:39:11.277961 ==
6982 00:39:11.278042
6983 00:39:11.278106
6984 00:39:11.278189 TX Vref Scan disable
6985 00:39:11.281296 == TX Byte 0 ==
6986 00:39:11.284257 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6987 00:39:11.287502 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6988 00:39:11.290931 == TX Byte 1 ==
6989 00:39:11.294391 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6990 00:39:11.297427 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6991 00:39:11.297509
6992 00:39:11.301069 [DATLAT]
6993 00:39:11.301151 Freq=400, CH1 RK1
6994 00:39:11.301217
6995 00:39:11.304684 DATLAT Default: 0xe
6996 00:39:11.304766 0, 0xFFFF, sum = 0
6997 00:39:11.307909 1, 0xFFFF, sum = 0
6998 00:39:11.307993 2, 0xFFFF, sum = 0
6999 00:39:11.310969 3, 0xFFFF, sum = 0
7000 00:39:11.311052 4, 0xFFFF, sum = 0
7001 00:39:11.314483 5, 0xFFFF, sum = 0
7002 00:39:11.314566 6, 0xFFFF, sum = 0
7003 00:39:11.317804 7, 0xFFFF, sum = 0
7004 00:39:11.317887 8, 0xFFFF, sum = 0
7005 00:39:11.321268 9, 0xFFFF, sum = 0
7006 00:39:11.321352 10, 0xFFFF, sum = 0
7007 00:39:11.324154 11, 0xFFFF, sum = 0
7008 00:39:11.324237 12, 0xFFFF, sum = 0
7009 00:39:11.327357 13, 0x0, sum = 1
7010 00:39:11.327440 14, 0x0, sum = 2
7011 00:39:11.331041 15, 0x0, sum = 3
7012 00:39:11.331124 16, 0x0, sum = 4
7013 00:39:11.334455 best_step = 14
7014 00:39:11.334536
7015 00:39:11.334600 ==
7016 00:39:11.337789 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 00:39:11.341029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 00:39:11.341111 ==
7019 00:39:11.344190 RX Vref Scan: 0
7020 00:39:11.344271
7021 00:39:11.344335 RX Vref 0 -> 0, step: 1
7022 00:39:11.344394
7023 00:39:11.347099 RX Delay -359 -> 252, step: 8
7024 00:39:11.355444 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7025 00:39:11.358600 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7026 00:39:11.362272 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7027 00:39:11.368936 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7028 00:39:11.371790 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7029 00:39:11.374999 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7030 00:39:11.378611 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7031 00:39:11.384815 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7032 00:39:11.387974 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7033 00:39:11.391426 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7034 00:39:11.394734 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7035 00:39:11.401439 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7036 00:39:11.404695 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7037 00:39:11.408024 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7038 00:39:11.411699 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7039 00:39:11.417926 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7040 00:39:11.418011 ==
7041 00:39:11.421060 Dram Type= 6, Freq= 0, CH_1, rank 1
7042 00:39:11.424566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7043 00:39:11.424652 ==
7044 00:39:11.428200 DQS Delay:
7045 00:39:11.428309 DQS0 = 48, DQS1 = 56
7046 00:39:11.428405 DQM Delay:
7047 00:39:11.430782 DQM0 = 13, DQM1 = 10
7048 00:39:11.430855 DQ Delay:
7049 00:39:11.434351 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7050 00:39:11.437720 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =8
7051 00:39:11.441272 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7052 00:39:11.444089 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7053 00:39:11.444165
7054 00:39:11.444227
7055 00:39:11.454487 [DQSOSCAuto] RK1, (LSB)MR18= 0x6958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7056 00:39:11.454590 CH1 RK1: MR19=C0C, MR18=6958
7057 00:39:11.460966 CH1_RK1: MR19=0xC0C, MR18=0x6958, DQSOSC=396, MR23=63, INC=376, DEC=251
7058 00:39:11.464084 [RxdqsGatingPostProcess] freq 400
7059 00:39:11.470711 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7060 00:39:11.473943 best DQS0 dly(2T, 0.5T) = (0, 10)
7061 00:39:11.477307 best DQS1 dly(2T, 0.5T) = (0, 10)
7062 00:39:11.480926 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7063 00:39:11.484007 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7064 00:39:11.487433 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 00:39:11.490614 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 00:39:11.493740 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 00:39:11.497077 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 00:39:11.497150 Pre-setting of DQS Precalculation
7069 00:39:11.503734 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7070 00:39:11.510306 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7071 00:39:11.516840 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7072 00:39:11.516946
7073 00:39:11.517038
7074 00:39:11.520534 [Calibration Summary] 800 Mbps
7075 00:39:11.523487 CH 0, Rank 0
7076 00:39:11.523586 SW Impedance : PASS
7077 00:39:11.526759 DUTY Scan : NO K
7078 00:39:11.530315 ZQ Calibration : PASS
7079 00:39:11.530389 Jitter Meter : NO K
7080 00:39:11.533284 CBT Training : PASS
7081 00:39:11.537129 Write leveling : PASS
7082 00:39:11.537215 RX DQS gating : PASS
7083 00:39:11.540192 RX DQ/DQS(RDDQC) : PASS
7084 00:39:11.540289 TX DQ/DQS : PASS
7085 00:39:11.543345 RX DATLAT : PASS
7086 00:39:11.546618 RX DQ/DQS(Engine): PASS
7087 00:39:11.546693 TX OE : NO K
7088 00:39:11.550016 All Pass.
7089 00:39:11.550111
7090 00:39:11.550200 CH 0, Rank 1
7091 00:39:11.553225 SW Impedance : PASS
7092 00:39:11.553297 DUTY Scan : NO K
7093 00:39:11.556234 ZQ Calibration : PASS
7094 00:39:11.559559 Jitter Meter : NO K
7095 00:39:11.559659 CBT Training : PASS
7096 00:39:11.563048 Write leveling : NO K
7097 00:39:11.566376 RX DQS gating : PASS
7098 00:39:11.566450 RX DQ/DQS(RDDQC) : PASS
7099 00:39:11.569403 TX DQ/DQS : PASS
7100 00:39:11.572825 RX DATLAT : PASS
7101 00:39:11.572923 RX DQ/DQS(Engine): PASS
7102 00:39:11.576175 TX OE : NO K
7103 00:39:11.576247 All Pass.
7104 00:39:11.576308
7105 00:39:11.579712 CH 1, Rank 0
7106 00:39:11.579807 SW Impedance : PASS
7107 00:39:11.582909 DUTY Scan : NO K
7108 00:39:11.585980 ZQ Calibration : PASS
7109 00:39:11.586077 Jitter Meter : NO K
7110 00:39:11.589259 CBT Training : PASS
7111 00:39:11.592652 Write leveling : PASS
7112 00:39:11.592729 RX DQS gating : PASS
7113 00:39:11.596010 RX DQ/DQS(RDDQC) : PASS
7114 00:39:11.599510 TX DQ/DQS : PASS
7115 00:39:11.599582 RX DATLAT : PASS
7116 00:39:11.602659 RX DQ/DQS(Engine): PASS
7117 00:39:11.606352 TX OE : NO K
7118 00:39:11.606422 All Pass.
7119 00:39:11.606485
7120 00:39:11.606544 CH 1, Rank 1
7121 00:39:11.609500 SW Impedance : PASS
7122 00:39:11.612528 DUTY Scan : NO K
7123 00:39:11.612629 ZQ Calibration : PASS
7124 00:39:11.615844 Jitter Meter : NO K
7125 00:39:11.618836 CBT Training : PASS
7126 00:39:11.618909 Write leveling : NO K
7127 00:39:11.622351 RX DQS gating : PASS
7128 00:39:11.622425 RX DQ/DQS(RDDQC) : PASS
7129 00:39:11.625554 TX DQ/DQS : PASS
7130 00:39:11.629421 RX DATLAT : PASS
7131 00:39:11.629502 RX DQ/DQS(Engine): PASS
7132 00:39:11.632262 TX OE : NO K
7133 00:39:11.632360 All Pass.
7134 00:39:11.632450
7135 00:39:11.635369 DramC Write-DBI off
7136 00:39:11.638826 PER_BANK_REFRESH: Hybrid Mode
7137 00:39:11.638897 TX_TRACKING: ON
7138 00:39:11.648662 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7139 00:39:11.652309 [FAST_K] Save calibration result to emmc
7140 00:39:11.655788 dramc_set_vcore_voltage set vcore to 725000
7141 00:39:11.658639 Read voltage for 1600, 0
7142 00:39:11.658714 Vio18 = 0
7143 00:39:11.662086 Vcore = 725000
7144 00:39:11.662213 Vdram = 0
7145 00:39:11.662288 Vddq = 0
7146 00:39:11.662380 Vmddr = 0
7147 00:39:11.669050 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7148 00:39:11.675115 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7149 00:39:11.675196 MEM_TYPE=3, freq_sel=13
7150 00:39:11.678516 sv_algorithm_assistance_LP4_3733
7151 00:39:11.681605 ============ PULL DRAM RESETB DOWN ============
7152 00:39:11.688380 ========== PULL DRAM RESETB DOWN end =========
7153 00:39:11.691560 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7154 00:39:11.695319 ===================================
7155 00:39:11.698433 LPDDR4 DRAM CONFIGURATION
7156 00:39:11.702075 ===================================
7157 00:39:11.702156 EX_ROW_EN[0] = 0x0
7158 00:39:11.705265 EX_ROW_EN[1] = 0x0
7159 00:39:11.705344 LP4Y_EN = 0x0
7160 00:39:11.708385 WORK_FSP = 0x1
7161 00:39:11.708467 WL = 0x5
7162 00:39:11.711508 RL = 0x5
7163 00:39:11.715167 BL = 0x2
7164 00:39:11.715249 RPST = 0x0
7165 00:39:11.718374 RD_PRE = 0x0
7166 00:39:11.718455 WR_PRE = 0x1
7167 00:39:11.721319 WR_PST = 0x1
7168 00:39:11.721400 DBI_WR = 0x0
7169 00:39:11.724611 DBI_RD = 0x0
7170 00:39:11.724692 OTF = 0x1
7171 00:39:11.728118 ===================================
7172 00:39:11.731587 ===================================
7173 00:39:11.734796 ANA top config
7174 00:39:11.738067 ===================================
7175 00:39:11.738218 DLL_ASYNC_EN = 0
7176 00:39:11.741241 ALL_SLAVE_EN = 0
7177 00:39:11.744632 NEW_RANK_MODE = 1
7178 00:39:11.747704 DLL_IDLE_MODE = 1
7179 00:39:11.747812 LP45_APHY_COMB_EN = 1
7180 00:39:11.751216 TX_ODT_DIS = 0
7181 00:39:11.755010 NEW_8X_MODE = 1
7182 00:39:11.757818 ===================================
7183 00:39:11.761027 ===================================
7184 00:39:11.764438 data_rate = 3200
7185 00:39:11.767643 CKR = 1
7186 00:39:11.770919 DQ_P2S_RATIO = 8
7187 00:39:11.774325 ===================================
7188 00:39:11.774407 CA_P2S_RATIO = 8
7189 00:39:11.777523 DQ_CA_OPEN = 0
7190 00:39:11.780951 DQ_SEMI_OPEN = 0
7191 00:39:11.784247 CA_SEMI_OPEN = 0
7192 00:39:11.787326 CA_FULL_RATE = 0
7193 00:39:11.790949 DQ_CKDIV4_EN = 0
7194 00:39:11.791031 CA_CKDIV4_EN = 0
7195 00:39:11.794086 CA_PREDIV_EN = 0
7196 00:39:11.797611 PH8_DLY = 12
7197 00:39:11.800921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7198 00:39:11.803997 DQ_AAMCK_DIV = 4
7199 00:39:11.807190 CA_AAMCK_DIV = 4
7200 00:39:11.810530 CA_ADMCK_DIV = 4
7201 00:39:11.810615 DQ_TRACK_CA_EN = 0
7202 00:39:11.813887 CA_PICK = 1600
7203 00:39:11.817189 CA_MCKIO = 1600
7204 00:39:11.820321 MCKIO_SEMI = 0
7205 00:39:11.823869 PLL_FREQ = 3068
7206 00:39:11.826874 DQ_UI_PI_RATIO = 32
7207 00:39:11.830362 CA_UI_PI_RATIO = 0
7208 00:39:11.833563 ===================================
7209 00:39:11.836746 ===================================
7210 00:39:11.836828 memory_type:LPDDR4
7211 00:39:11.840291 GP_NUM : 10
7212 00:39:11.843594 SRAM_EN : 1
7213 00:39:11.843676 MD32_EN : 0
7214 00:39:11.846813 ===================================
7215 00:39:11.850082 [ANA_INIT] >>>>>>>>>>>>>>
7216 00:39:11.853343 <<<<<< [CONFIGURE PHASE]: ANA_TX
7217 00:39:11.856850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7218 00:39:11.860116 ===================================
7219 00:39:11.863805 data_rate = 3200,PCW = 0X7600
7220 00:39:11.866446 ===================================
7221 00:39:11.869965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7222 00:39:11.873330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7223 00:39:11.879552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7224 00:39:11.882844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7225 00:39:11.890188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7226 00:39:11.893040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7227 00:39:11.893183 [ANA_INIT] flow start
7228 00:39:11.896383 [ANA_INIT] PLL >>>>>>>>
7229 00:39:11.899336 [ANA_INIT] PLL <<<<<<<<
7230 00:39:11.899470 [ANA_INIT] MIDPI >>>>>>>>
7231 00:39:11.902680 [ANA_INIT] MIDPI <<<<<<<<
7232 00:39:11.906464 [ANA_INIT] DLL >>>>>>>>
7233 00:39:11.906599 [ANA_INIT] DLL <<<<<<<<
7234 00:39:11.909460 [ANA_INIT] flow end
7235 00:39:11.912662 ============ LP4 DIFF to SE enter ============
7236 00:39:11.915872 ============ LP4 DIFF to SE exit ============
7237 00:39:11.919114 [ANA_INIT] <<<<<<<<<<<<<
7238 00:39:11.922389 [Flow] Enable top DCM control >>>>>
7239 00:39:11.926398 [Flow] Enable top DCM control <<<<<
7240 00:39:11.928973 Enable DLL master slave shuffle
7241 00:39:11.935652 ==============================================================
7242 00:39:11.935735 Gating Mode config
7243 00:39:11.942401 ==============================================================
7244 00:39:11.945818 Config description:
7245 00:39:11.952537 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7246 00:39:11.958814 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7247 00:39:11.965423 SELPH_MODE 0: By rank 1: By Phase
7248 00:39:11.972790 ==============================================================
7249 00:39:11.972873 GAT_TRACK_EN = 1
7250 00:39:11.975164 RX_GATING_MODE = 2
7251 00:39:11.978701 RX_GATING_TRACK_MODE = 2
7252 00:39:11.982080 SELPH_MODE = 1
7253 00:39:11.985564 PICG_EARLY_EN = 1
7254 00:39:11.988532 VALID_LAT_VALUE = 1
7255 00:39:11.995092 ==============================================================
7256 00:39:11.998402 Enter into Gating configuration >>>>
7257 00:39:12.002505 Exit from Gating configuration <<<<
7258 00:39:12.004960 Enter into DVFS_PRE_config >>>>>
7259 00:39:12.015377 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7260 00:39:12.018285 Exit from DVFS_PRE_config <<<<<
7261 00:39:12.021581 Enter into PICG configuration >>>>
7262 00:39:12.024860 Exit from PICG configuration <<<<
7263 00:39:12.027961 [RX_INPUT] configuration >>>>>
7264 00:39:12.031776 [RX_INPUT] configuration <<<<<
7265 00:39:12.034596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7266 00:39:12.041191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7267 00:39:12.048108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7268 00:39:12.051456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7269 00:39:12.057778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7270 00:39:12.064409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7271 00:39:12.067878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7272 00:39:12.074399 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7273 00:39:12.077845 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7274 00:39:12.080953 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7275 00:39:12.084832 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7276 00:39:12.090932 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 00:39:12.094252 ===================================
7278 00:39:12.094334 LPDDR4 DRAM CONFIGURATION
7279 00:39:12.097372 ===================================
7280 00:39:12.100578 EX_ROW_EN[0] = 0x0
7281 00:39:12.104010 EX_ROW_EN[1] = 0x0
7282 00:39:12.104086 LP4Y_EN = 0x0
7283 00:39:12.107628 WORK_FSP = 0x1
7284 00:39:12.107709 WL = 0x5
7285 00:39:12.110509 RL = 0x5
7286 00:39:12.110589 BL = 0x2
7287 00:39:12.113865 RPST = 0x0
7288 00:39:12.113971 RD_PRE = 0x0
7289 00:39:12.117455 WR_PRE = 0x1
7290 00:39:12.117535 WR_PST = 0x1
7291 00:39:12.120430 DBI_WR = 0x0
7292 00:39:12.120510 DBI_RD = 0x0
7293 00:39:12.123927 OTF = 0x1
7294 00:39:12.127143 ===================================
7295 00:39:12.130535 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7296 00:39:12.133690 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7297 00:39:12.140479 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7298 00:39:12.143820 ===================================
7299 00:39:12.143909 LPDDR4 DRAM CONFIGURATION
7300 00:39:12.147503 ===================================
7301 00:39:12.150588 EX_ROW_EN[0] = 0x10
7302 00:39:12.153507 EX_ROW_EN[1] = 0x0
7303 00:39:12.153591 LP4Y_EN = 0x0
7304 00:39:12.156836 WORK_FSP = 0x1
7305 00:39:12.156945 WL = 0x5
7306 00:39:12.160009 RL = 0x5
7307 00:39:12.160094 BL = 0x2
7308 00:39:12.163464 RPST = 0x0
7309 00:39:12.163548 RD_PRE = 0x0
7310 00:39:12.166755 WR_PRE = 0x1
7311 00:39:12.166840 WR_PST = 0x1
7312 00:39:12.169996 DBI_WR = 0x0
7313 00:39:12.170105 DBI_RD = 0x0
7314 00:39:12.173947 OTF = 0x1
7315 00:39:12.176412 ===================================
7316 00:39:12.182913 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7317 00:39:12.183006 ==
7318 00:39:12.186291 Dram Type= 6, Freq= 0, CH_0, rank 0
7319 00:39:12.189775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 00:39:12.189860 ==
7321 00:39:12.193109 [Duty_Offset_Calibration]
7322 00:39:12.193228 B0:1 B1:-1 CA:0
7323 00:39:12.196148
7324 00:39:12.199337 [DutyScan_Calibration_Flow] k_type=0
7325 00:39:12.207981
7326 00:39:12.208069 ==CLK 0==
7327 00:39:12.211048 Final CLK duty delay cell = 0
7328 00:39:12.214549 [0] MAX Duty = 5124%(X100), DQS PI = 22
7329 00:39:12.217851 [0] MIN Duty = 4907%(X100), DQS PI = 4
7330 00:39:12.221436 [0] AVG Duty = 5015%(X100)
7331 00:39:12.221518
7332 00:39:12.224192 CH0 CLK Duty spec in!! Max-Min= 217%
7333 00:39:12.227325 [DutyScan_Calibration_Flow] ====Done====
7334 00:39:12.227408
7335 00:39:12.231201 [DutyScan_Calibration_Flow] k_type=1
7336 00:39:12.246626
7337 00:39:12.246707 ==DQS 0 ==
7338 00:39:12.250532 Final DQS duty delay cell = -4
7339 00:39:12.253824 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7340 00:39:12.256625 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7341 00:39:12.259666 [-4] AVG Duty = 4906%(X100)
7342 00:39:12.259742
7343 00:39:12.259805 ==DQS 1 ==
7344 00:39:12.263460 Final DQS duty delay cell = 0
7345 00:39:12.266740 [0] MAX Duty = 5156%(X100), DQS PI = 4
7346 00:39:12.269593 [0] MIN Duty = 5000%(X100), DQS PI = 18
7347 00:39:12.272985 [0] AVG Duty = 5078%(X100)
7348 00:39:12.273067
7349 00:39:12.276559 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7350 00:39:12.276642
7351 00:39:12.279672 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7352 00:39:12.282773 [DutyScan_Calibration_Flow] ====Done====
7353 00:39:12.282854
7354 00:39:12.286699 [DutyScan_Calibration_Flow] k_type=3
7355 00:39:12.304749
7356 00:39:12.304833 ==DQM 0 ==
7357 00:39:12.307460 Final DQM duty delay cell = 0
7358 00:39:12.310869 [0] MAX Duty = 5124%(X100), DQS PI = 22
7359 00:39:12.314062 [0] MIN Duty = 4875%(X100), DQS PI = 10
7360 00:39:12.317782 [0] AVG Duty = 4999%(X100)
7361 00:39:12.317865
7362 00:39:12.317928 ==DQM 1 ==
7363 00:39:12.321118 Final DQM duty delay cell = 0
7364 00:39:12.324047 [0] MAX Duty = 5000%(X100), DQS PI = 4
7365 00:39:12.327413 [0] MIN Duty = 4813%(X100), DQS PI = 18
7366 00:39:12.330775 [0] AVG Duty = 4906%(X100)
7367 00:39:12.330857
7368 00:39:12.333845 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7369 00:39:12.333927
7370 00:39:12.337202 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7371 00:39:12.340406 [DutyScan_Calibration_Flow] ====Done====
7372 00:39:12.340487
7373 00:39:12.343814 [DutyScan_Calibration_Flow] k_type=2
7374 00:39:12.360739
7375 00:39:12.360820 ==DQ 0 ==
7376 00:39:12.363955 Final DQ duty delay cell = -4
7377 00:39:12.367195 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7378 00:39:12.370499 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7379 00:39:12.373801 [-4] AVG Duty = 4953%(X100)
7380 00:39:12.373881
7381 00:39:12.373945 ==DQ 1 ==
7382 00:39:12.377515 Final DQ duty delay cell = 0
7383 00:39:12.380512 [0] MAX Duty = 5125%(X100), DQS PI = 4
7384 00:39:12.383650 [0] MIN Duty = 4969%(X100), DQS PI = 38
7385 00:39:12.386802 [0] AVG Duty = 5047%(X100)
7386 00:39:12.386883
7387 00:39:12.390437 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7388 00:39:12.390518
7389 00:39:12.393888 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7390 00:39:12.397238 [DutyScan_Calibration_Flow] ====Done====
7391 00:39:12.397319 ==
7392 00:39:12.399950 Dram Type= 6, Freq= 0, CH_1, rank 0
7393 00:39:12.403466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7394 00:39:12.403548 ==
7395 00:39:12.406595 [Duty_Offset_Calibration]
7396 00:39:12.406676 B0:-1 B1:1 CA:2
7397 00:39:12.409894
7398 00:39:12.413186 [DutyScan_Calibration_Flow] k_type=0
7399 00:39:12.421213
7400 00:39:12.421292 ==CLK 0==
7401 00:39:12.424923 Final CLK duty delay cell = 0
7402 00:39:12.428115 [0] MAX Duty = 5187%(X100), DQS PI = 22
7403 00:39:12.431368 [0] MIN Duty = 4969%(X100), DQS PI = 0
7404 00:39:12.431449 [0] AVG Duty = 5078%(X100)
7405 00:39:12.434239
7406 00:39:12.437741 CH1 CLK Duty spec in!! Max-Min= 218%
7407 00:39:12.440841 [DutyScan_Calibration_Flow] ====Done====
7408 00:39:12.440921
7409 00:39:12.444248 [DutyScan_Calibration_Flow] k_type=1
7410 00:39:12.461072
7411 00:39:12.461151 ==DQS 0 ==
7412 00:39:12.464107 Final DQS duty delay cell = 0
7413 00:39:12.467331 [0] MAX Duty = 5124%(X100), DQS PI = 18
7414 00:39:12.470904 [0] MIN Duty = 4907%(X100), DQS PI = 10
7415 00:39:12.474609 [0] AVG Duty = 5015%(X100)
7416 00:39:12.474714
7417 00:39:12.474805 ==DQS 1 ==
7418 00:39:12.477490 Final DQS duty delay cell = 0
7419 00:39:12.480706 [0] MAX Duty = 5093%(X100), DQS PI = 28
7420 00:39:12.484143 [0] MIN Duty = 4969%(X100), DQS PI = 54
7421 00:39:12.487615 [0] AVG Duty = 5031%(X100)
7422 00:39:12.487695
7423 00:39:12.490638 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7424 00:39:12.490744
7425 00:39:12.494296 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7426 00:39:12.497065 [DutyScan_Calibration_Flow] ====Done====
7427 00:39:12.497146
7428 00:39:12.500383 [DutyScan_Calibration_Flow] k_type=3
7429 00:39:12.518215
7430 00:39:12.518298 ==DQM 0 ==
7431 00:39:12.521462 Final DQM duty delay cell = 0
7432 00:39:12.524647 [0] MAX Duty = 5218%(X100), DQS PI = 38
7433 00:39:12.527576 [0] MIN Duty = 5000%(X100), DQS PI = 10
7434 00:39:12.530892 [0] AVG Duty = 5109%(X100)
7435 00:39:12.530972
7436 00:39:12.531035 ==DQM 1 ==
7437 00:39:12.534030 Final DQM duty delay cell = 0
7438 00:39:12.537471 [0] MAX Duty = 5156%(X100), DQS PI = 6
7439 00:39:12.541386 [0] MIN Duty = 4938%(X100), DQS PI = 34
7440 00:39:12.543928 [0] AVG Duty = 5047%(X100)
7441 00:39:12.544008
7442 00:39:12.547731 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7443 00:39:12.547811
7444 00:39:12.550489 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7445 00:39:12.554196 [DutyScan_Calibration_Flow] ====Done====
7446 00:39:12.554310
7447 00:39:12.557023 [DutyScan_Calibration_Flow] k_type=2
7448 00:39:12.574698
7449 00:39:12.574779 ==DQ 0 ==
7450 00:39:12.578418 Final DQ duty delay cell = 0
7451 00:39:12.581215 [0] MAX Duty = 5187%(X100), DQS PI = 32
7452 00:39:12.584625 [0] MIN Duty = 4906%(X100), DQS PI = 8
7453 00:39:12.584705 [0] AVG Duty = 5046%(X100)
7454 00:39:12.588136
7455 00:39:12.588216 ==DQ 1 ==
7456 00:39:12.591301 Final DQ duty delay cell = 0
7457 00:39:12.594377 [0] MAX Duty = 5156%(X100), DQS PI = 8
7458 00:39:12.597519 [0] MIN Duty = 4969%(X100), DQS PI = 32
7459 00:39:12.597600 [0] AVG Duty = 5062%(X100)
7460 00:39:12.601246
7461 00:39:12.604646 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7462 00:39:12.604752
7463 00:39:12.607843 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7464 00:39:12.610837 [DutyScan_Calibration_Flow] ====Done====
7465 00:39:12.614153 nWR fixed to 30
7466 00:39:12.614274 [ModeRegInit_LP4] CH0 RK0
7467 00:39:12.617650 [ModeRegInit_LP4] CH0 RK1
7468 00:39:12.620981 [ModeRegInit_LP4] CH1 RK0
7469 00:39:12.623899 [ModeRegInit_LP4] CH1 RK1
7470 00:39:12.623979 match AC timing 5
7471 00:39:12.630975 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7472 00:39:12.633904 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7473 00:39:12.637630 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7474 00:39:12.643899 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7475 00:39:12.647376 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7476 00:39:12.647457 [MiockJmeterHQA]
7477 00:39:12.647520
7478 00:39:12.650852 [DramcMiockJmeter] u1RxGatingPI = 0
7479 00:39:12.653780 0 : 4252, 4027
7480 00:39:12.653868 4 : 4252, 4027
7481 00:39:12.657370 8 : 4366, 4140
7482 00:39:12.657452 12 : 4255, 4029
7483 00:39:12.657517 16 : 4253, 4027
7484 00:39:12.661023 20 : 4365, 4140
7485 00:39:12.661105 24 : 4252, 4027
7486 00:39:12.663709 28 : 4252, 4027
7487 00:39:12.663791 32 : 4253, 4027
7488 00:39:12.667499 36 : 4252, 4027
7489 00:39:12.667581 40 : 4363, 4137
7490 00:39:12.670510 44 : 4250, 4026
7491 00:39:12.670591 48 : 4361, 4138
7492 00:39:12.673880 52 : 4250, 4026
7493 00:39:12.673988 56 : 4252, 4029
7494 00:39:12.674081 60 : 4250, 4027
7495 00:39:12.676752 64 : 4361, 4137
7496 00:39:12.676833 68 : 4250, 4026
7497 00:39:12.680225 72 : 4360, 4138
7498 00:39:12.680306 76 : 4250, 4026
7499 00:39:12.683544 80 : 4250, 4027
7500 00:39:12.683626 84 : 4250, 4026
7501 00:39:12.683689 88 : 4250, 4027
7502 00:39:12.686862 92 : 4360, 275
7503 00:39:12.686943 96 : 4250, 0
7504 00:39:12.690449 100 : 4360, 0
7505 00:39:12.690531 104 : 4363, 0
7506 00:39:12.690596 108 : 4361, 0
7507 00:39:12.693686 112 : 4249, 0
7508 00:39:12.693769 116 : 4250, 0
7509 00:39:12.696848 120 : 4250, 0
7510 00:39:12.696929 124 : 4249, 0
7511 00:39:12.696993 128 : 4250, 0
7512 00:39:12.700646 132 : 4250, 0
7513 00:39:12.700728 136 : 4250, 0
7514 00:39:12.703866 140 : 4361, 0
7515 00:39:12.703958 144 : 4360, 0
7516 00:39:12.704023 148 : 4250, 0
7517 00:39:12.706778 152 : 4250, 0
7518 00:39:12.706860 156 : 4360, 0
7519 00:39:12.710307 160 : 4361, 0
7520 00:39:12.710421 164 : 4250, 0
7521 00:39:12.710519 168 : 4250, 0
7522 00:39:12.714014 172 : 4250, 0
7523 00:39:12.714122 176 : 4250, 0
7524 00:39:12.714241 180 : 4250, 0
7525 00:39:12.716934 184 : 4250, 0
7526 00:39:12.717015 188 : 4250, 0
7527 00:39:12.719749 192 : 4361, 0
7528 00:39:12.719830 196 : 4360, 0
7529 00:39:12.719894 200 : 4247, 0
7530 00:39:12.723476 204 : 4250, 0
7531 00:39:12.723557 208 : 4360, 0
7532 00:39:12.726545 212 : 4361, 0
7533 00:39:12.726627 216 : 4250, 0
7534 00:39:12.726690 220 : 4250, 0
7535 00:39:12.730008 224 : 4250, 322
7536 00:39:12.730116 228 : 4253, 3307
7537 00:39:12.733250 232 : 4250, 4027
7538 00:39:12.733331 236 : 4253, 4029
7539 00:39:12.736547 240 : 4250, 4027
7540 00:39:12.736628 244 : 4250, 4026
7541 00:39:12.739760 248 : 4250, 4027
7542 00:39:12.739900 252 : 4250, 4027
7543 00:39:12.743006 256 : 4250, 4027
7544 00:39:12.743087 260 : 4360, 4138
7545 00:39:12.746554 264 : 4361, 4137
7546 00:39:12.746635 268 : 4250, 4027
7547 00:39:12.746700 272 : 4361, 4138
7548 00:39:12.749817 276 : 4250, 4027
7549 00:39:12.749899 280 : 4250, 4026
7550 00:39:12.753271 284 : 4250, 4027
7551 00:39:12.753353 288 : 4250, 4027
7552 00:39:12.756126 292 : 4250, 4027
7553 00:39:12.756214 296 : 4250, 4026
7554 00:39:12.759354 300 : 4250, 4027
7555 00:39:12.759479 304 : 4250, 4026
7556 00:39:12.763160 308 : 4250, 4027
7557 00:39:12.763241 312 : 4360, 4137
7558 00:39:12.766329 316 : 4361, 4137
7559 00:39:12.766411 320 : 4247, 4025
7560 00:39:12.769689 324 : 4361, 4137
7561 00:39:12.769771 328 : 4360, 4138
7562 00:39:12.772487 332 : 4250, 4026
7563 00:39:12.772568 336 : 4250, 3797
7564 00:39:12.772633 340 : 4250, 1878
7565 00:39:12.775732
7566 00:39:12.775837 MIOCK jitter meter ch=0
7567 00:39:12.775929
7568 00:39:12.779287 1T = (340-92) = 248 dly cells
7569 00:39:12.786122 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7570 00:39:12.786222 ==
7571 00:39:12.789494 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 00:39:12.792811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 00:39:12.792892 ==
7574 00:39:12.799159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 00:39:12.802561 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 00:39:12.805701 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 00:39:12.812336 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 00:39:12.821987 [CA 0] Center 43 (13~74) winsize 62
7579 00:39:12.825316 [CA 1] Center 43 (13~74) winsize 62
7580 00:39:12.828509 [CA 2] Center 39 (10~68) winsize 59
7581 00:39:12.831834 [CA 3] Center 38 (9~68) winsize 60
7582 00:39:12.835103 [CA 4] Center 37 (8~66) winsize 59
7583 00:39:12.838067 [CA 5] Center 36 (7~66) winsize 60
7584 00:39:12.838196
7585 00:39:12.841360 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 00:39:12.841442
7587 00:39:12.848449 [CATrainingPosCal] consider 1 rank data
7588 00:39:12.848531 u2DelayCellTimex100 = 262/100 ps
7589 00:39:12.854682 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7590 00:39:12.858111 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7591 00:39:12.861249 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7592 00:39:12.865115 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7593 00:39:12.867816 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7594 00:39:12.871600 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7595 00:39:12.871682
7596 00:39:12.874431 CA PerBit enable=1, Macro0, CA PI delay=36
7597 00:39:12.874513
7598 00:39:12.877899 [CBTSetCACLKResult] CA Dly = 36
7599 00:39:12.881162 CS Dly: 12 (0~43)
7600 00:39:12.884450 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 00:39:12.887608 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 00:39:12.887690 ==
7603 00:39:12.891228 Dram Type= 6, Freq= 0, CH_0, rank 1
7604 00:39:12.897571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 00:39:12.897658 ==
7606 00:39:12.900784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7607 00:39:12.907725 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7608 00:39:12.911187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7609 00:39:12.917872 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7610 00:39:12.925681 [CA 0] Center 42 (12~73) winsize 62
7611 00:39:12.928394 [CA 1] Center 43 (13~73) winsize 61
7612 00:39:12.932505 [CA 2] Center 37 (8~67) winsize 60
7613 00:39:12.935240 [CA 3] Center 37 (7~67) winsize 61
7614 00:39:12.938277 [CA 4] Center 35 (6~65) winsize 60
7615 00:39:12.941511 [CA 5] Center 35 (5~65) winsize 61
7616 00:39:12.941594
7617 00:39:12.945189 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7618 00:39:12.945271
7619 00:39:12.951563 [CATrainingPosCal] consider 2 rank data
7620 00:39:12.951645 u2DelayCellTimex100 = 262/100 ps
7621 00:39:12.957984 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7622 00:39:12.961490 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7623 00:39:12.964985 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7624 00:39:12.967876 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7625 00:39:12.971261 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7626 00:39:12.974815 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7627 00:39:12.974897
7628 00:39:12.977879 CA PerBit enable=1, Macro0, CA PI delay=36
7629 00:39:12.977961
7630 00:39:12.981369 [CBTSetCACLKResult] CA Dly = 36
7631 00:39:12.984665 CS Dly: 12 (0~44)
7632 00:39:12.987702 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7633 00:39:12.991172 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7634 00:39:12.991253
7635 00:39:12.994393 ----->DramcWriteLeveling(PI) begin...
7636 00:39:12.994477 ==
7637 00:39:12.997578 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 00:39:13.004218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 00:39:13.004392 ==
7640 00:39:13.007660 Write leveling (Byte 0): 33 => 33
7641 00:39:13.010799 Write leveling (Byte 1): 27 => 27
7642 00:39:13.014433 DramcWriteLeveling(PI) end<-----
7643 00:39:13.014518
7644 00:39:13.014590 ==
7645 00:39:13.017475 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 00:39:13.020685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 00:39:13.020790 ==
7648 00:39:13.023959 [Gating] SW mode calibration
7649 00:39:13.030695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7650 00:39:13.037348 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7651 00:39:13.040408 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 00:39:13.043694 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 00:39:13.050988 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 00:39:13.053756 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7655 00:39:13.057223 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7656 00:39:13.063633 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7657 00:39:13.066835 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7658 00:39:13.070556 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 00:39:13.076942 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 00:39:13.080543 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 00:39:13.083822 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7662 00:39:13.090086 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7663 00:39:13.093264 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7664 00:39:13.096803 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7665 00:39:13.103614 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
7666 00:39:13.106449 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 00:39:13.110054 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 00:39:13.116503 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 00:39:13.119674 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 00:39:13.123534 1 6 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7671 00:39:13.129331 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7672 00:39:13.132658 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7673 00:39:13.136139 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7674 00:39:13.142574 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 00:39:13.146105 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 00:39:13.149633 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 00:39:13.155975 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 00:39:13.159417 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7679 00:39:13.162223 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7680 00:39:13.169335 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7681 00:39:13.172544 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7682 00:39:13.175680 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 00:39:13.182734 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 00:39:13.185469 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 00:39:13.188863 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 00:39:13.195247 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 00:39:13.198881 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 00:39:13.202064 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 00:39:13.209157 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 00:39:13.211802 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 00:39:13.215388 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 00:39:13.221749 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 00:39:13.225086 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7694 00:39:13.228100 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7695 00:39:13.234773 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7696 00:39:13.234856 Total UI for P1: 0, mck2ui 16
7697 00:39:13.241284 best dqsien dly found for B0: ( 1, 9, 10)
7698 00:39:13.244650 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7699 00:39:13.248575 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7700 00:39:13.251694 Total UI for P1: 0, mck2ui 16
7701 00:39:13.254741 best dqsien dly found for B1: ( 1, 9, 20)
7702 00:39:13.257802 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7703 00:39:13.261340 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7704 00:39:13.261439
7705 00:39:13.267678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7706 00:39:13.271247 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7707 00:39:13.274416 [Gating] SW calibration Done
7708 00:39:13.274515 ==
7709 00:39:13.277692 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 00:39:13.280792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 00:39:13.280890 ==
7712 00:39:13.280979 RX Vref Scan: 0
7713 00:39:13.281069
7714 00:39:13.284499 RX Vref 0 -> 0, step: 1
7715 00:39:13.284573
7716 00:39:13.287199 RX Delay 0 -> 252, step: 8
7717 00:39:13.290671 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7718 00:39:13.293917 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7719 00:39:13.297977 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7720 00:39:13.304075 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7721 00:39:13.307163 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7722 00:39:13.310714 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7723 00:39:13.313840 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7724 00:39:13.320281 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7725 00:39:13.323877 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7726 00:39:13.327112 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7727 00:39:13.330051 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7728 00:39:13.333360 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7729 00:39:13.340371 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7730 00:39:13.343411 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7731 00:39:13.346683 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7732 00:39:13.350274 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7733 00:39:13.350373 ==
7734 00:39:13.353338 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 00:39:13.360320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 00:39:13.360421 ==
7737 00:39:13.360518 DQS Delay:
7738 00:39:13.363465 DQS0 = 0, DQS1 = 0
7739 00:39:13.363546 DQM Delay:
7740 00:39:13.363608 DQM0 = 134, DQM1 = 126
7741 00:39:13.366632 DQ Delay:
7742 00:39:13.369962 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7743 00:39:13.373270 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7744 00:39:13.376514 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7745 00:39:13.379617 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7746 00:39:13.379723
7747 00:39:13.379813
7748 00:39:13.379909 ==
7749 00:39:13.383044 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 00:39:13.389903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 00:39:13.390043 ==
7752 00:39:13.390152
7753 00:39:13.390266
7754 00:39:13.390352 TX Vref Scan disable
7755 00:39:13.392882 == TX Byte 0 ==
7756 00:39:13.396446 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7757 00:39:13.400014 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7758 00:39:13.403507 == TX Byte 1 ==
7759 00:39:13.406624 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7760 00:39:13.412869 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7761 00:39:13.412954 ==
7762 00:39:13.416231 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 00:39:13.419466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 00:39:13.419552 ==
7765 00:39:13.432740
7766 00:39:13.435744 TX Vref early break, caculate TX vref
7767 00:39:13.439064 TX Vref=16, minBit 4, minWin=22, winSum=374
7768 00:39:13.442139 TX Vref=18, minBit 4, minWin=22, winSum=380
7769 00:39:13.445589 TX Vref=20, minBit 1, minWin=23, winSum=388
7770 00:39:13.448646 TX Vref=22, minBit 4, minWin=23, winSum=401
7771 00:39:13.452309 TX Vref=24, minBit 5, minWin=24, winSum=411
7772 00:39:13.459078 TX Vref=26, minBit 4, minWin=25, winSum=419
7773 00:39:13.462122 TX Vref=28, minBit 7, minWin=24, winSum=419
7774 00:39:13.465394 TX Vref=30, minBit 0, minWin=25, winSum=414
7775 00:39:13.468520 TX Vref=32, minBit 5, minWin=23, winSum=399
7776 00:39:13.471974 TX Vref=34, minBit 4, minWin=23, winSum=392
7777 00:39:13.478901 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 26
7778 00:39:13.478987
7779 00:39:13.482315 Final TX Range 0 Vref 26
7780 00:39:13.482400
7781 00:39:13.482486 ==
7782 00:39:13.485240 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 00:39:13.488772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 00:39:13.488882 ==
7785 00:39:13.488978
7786 00:39:13.489075
7787 00:39:13.492333 TX Vref Scan disable
7788 00:39:13.498326 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7789 00:39:13.498409 == TX Byte 0 ==
7790 00:39:13.501646 u2DelayCellOfst[0]=14 cells (4 PI)
7791 00:39:13.505032 u2DelayCellOfst[1]=18 cells (5 PI)
7792 00:39:13.508361 u2DelayCellOfst[2]=14 cells (4 PI)
7793 00:39:13.512078 u2DelayCellOfst[3]=14 cells (4 PI)
7794 00:39:13.515235 u2DelayCellOfst[4]=11 cells (3 PI)
7795 00:39:13.518358 u2DelayCellOfst[5]=0 cells (0 PI)
7796 00:39:13.521392 u2DelayCellOfst[6]=18 cells (5 PI)
7797 00:39:13.524983 u2DelayCellOfst[7]=22 cells (6 PI)
7798 00:39:13.528469 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7799 00:39:13.531384 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7800 00:39:13.534592 == TX Byte 1 ==
7801 00:39:13.538023 u2DelayCellOfst[8]=0 cells (0 PI)
7802 00:39:13.538120 u2DelayCellOfst[9]=0 cells (0 PI)
7803 00:39:13.541759 u2DelayCellOfst[10]=3 cells (1 PI)
7804 00:39:13.544441 u2DelayCellOfst[11]=0 cells (0 PI)
7805 00:39:13.547864 u2DelayCellOfst[12]=7 cells (2 PI)
7806 00:39:13.551077 u2DelayCellOfst[13]=11 cells (3 PI)
7807 00:39:13.554805 u2DelayCellOfst[14]=11 cells (3 PI)
7808 00:39:13.557888 u2DelayCellOfst[15]=7 cells (2 PI)
7809 00:39:13.561198 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7810 00:39:13.567954 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7811 00:39:13.568064 DramC Write-DBI on
7812 00:39:13.568155 ==
7813 00:39:13.570904 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 00:39:13.577785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 00:39:13.577887 ==
7816 00:39:13.577977
7817 00:39:13.578074
7818 00:39:13.578167 TX Vref Scan disable
7819 00:39:13.581423 == TX Byte 0 ==
7820 00:39:13.585099 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7821 00:39:13.588729 == TX Byte 1 ==
7822 00:39:13.591821 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7823 00:39:13.594591 DramC Write-DBI off
7824 00:39:13.594666
7825 00:39:13.594726 [DATLAT]
7826 00:39:13.594805 Freq=1600, CH0 RK0
7827 00:39:13.594865
7828 00:39:13.598061 DATLAT Default: 0xf
7829 00:39:13.601293 0, 0xFFFF, sum = 0
7830 00:39:13.601393 1, 0xFFFF, sum = 0
7831 00:39:13.604986 2, 0xFFFF, sum = 0
7832 00:39:13.605094 3, 0xFFFF, sum = 0
7833 00:39:13.607951 4, 0xFFFF, sum = 0
7834 00:39:13.608037 5, 0xFFFF, sum = 0
7835 00:39:13.611317 6, 0xFFFF, sum = 0
7836 00:39:13.611392 7, 0xFFFF, sum = 0
7837 00:39:13.614337 8, 0xFFFF, sum = 0
7838 00:39:13.614414 9, 0xFFFF, sum = 0
7839 00:39:13.617642 10, 0xFFFF, sum = 0
7840 00:39:13.617746 11, 0xFFFF, sum = 0
7841 00:39:13.621115 12, 0xFFFF, sum = 0
7842 00:39:13.621215 13, 0xFFFF, sum = 0
7843 00:39:13.624507 14, 0x0, sum = 1
7844 00:39:13.624610 15, 0x0, sum = 2
7845 00:39:13.627651 16, 0x0, sum = 3
7846 00:39:13.627751 17, 0x0, sum = 4
7847 00:39:13.630770 best_step = 15
7848 00:39:13.630853
7849 00:39:13.630914 ==
7850 00:39:13.634112 Dram Type= 6, Freq= 0, CH_0, rank 0
7851 00:39:13.637348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7852 00:39:13.637455 ==
7853 00:39:13.640829 RX Vref Scan: 1
7854 00:39:13.640917
7855 00:39:13.641009 Set Vref Range= 24 -> 127
7856 00:39:13.641095
7857 00:39:13.644238 RX Vref 24 -> 127, step: 1
7858 00:39:13.644312
7859 00:39:13.647422 RX Delay 19 -> 252, step: 4
7860 00:39:13.647617
7861 00:39:13.650785 Set Vref, RX VrefLevel [Byte0]: 24
7862 00:39:13.654156 [Byte1]: 24
7863 00:39:13.654245
7864 00:39:13.657630 Set Vref, RX VrefLevel [Byte0]: 25
7865 00:39:13.660787 [Byte1]: 25
7866 00:39:13.664121
7867 00:39:13.664218 Set Vref, RX VrefLevel [Byte0]: 26
7868 00:39:13.667844 [Byte1]: 26
7869 00:39:13.672192
7870 00:39:13.672264 Set Vref, RX VrefLevel [Byte0]: 27
7871 00:39:13.675388 [Byte1]: 27
7872 00:39:13.679455
7873 00:39:13.679552 Set Vref, RX VrefLevel [Byte0]: 28
7874 00:39:13.682779 [Byte1]: 28
7875 00:39:13.686786
7876 00:39:13.686860 Set Vref, RX VrefLevel [Byte0]: 29
7877 00:39:13.690137 [Byte1]: 29
7878 00:39:13.694597
7879 00:39:13.694671 Set Vref, RX VrefLevel [Byte0]: 30
7880 00:39:13.697716 [Byte1]: 30
7881 00:39:13.702298
7882 00:39:13.702375 Set Vref, RX VrefLevel [Byte0]: 31
7883 00:39:13.705464 [Byte1]: 31
7884 00:39:13.709999
7885 00:39:13.710100 Set Vref, RX VrefLevel [Byte0]: 32
7886 00:39:13.712862 [Byte1]: 32
7887 00:39:13.717024
7888 00:39:13.717127 Set Vref, RX VrefLevel [Byte0]: 33
7889 00:39:13.720718 [Byte1]: 33
7890 00:39:13.724861
7891 00:39:13.724959 Set Vref, RX VrefLevel [Byte0]: 34
7892 00:39:13.727943 [Byte1]: 34
7893 00:39:13.732550
7894 00:39:13.732648 Set Vref, RX VrefLevel [Byte0]: 35
7895 00:39:13.736348 [Byte1]: 35
7896 00:39:13.740084
7897 00:39:13.740183 Set Vref, RX VrefLevel [Byte0]: 36
7898 00:39:13.743139 [Byte1]: 36
7899 00:39:13.747598
7900 00:39:13.747700 Set Vref, RX VrefLevel [Byte0]: 37
7901 00:39:13.751301 [Byte1]: 37
7902 00:39:13.754931
7903 00:39:13.755002 Set Vref, RX VrefLevel [Byte0]: 38
7904 00:39:13.758447 [Byte1]: 38
7905 00:39:13.762686
7906 00:39:13.762762 Set Vref, RX VrefLevel [Byte0]: 39
7907 00:39:13.765872 [Byte1]: 39
7908 00:39:13.770045
7909 00:39:13.770147 Set Vref, RX VrefLevel [Byte0]: 40
7910 00:39:13.773843 [Byte1]: 40
7911 00:39:13.777634
7912 00:39:13.777736 Set Vref, RX VrefLevel [Byte0]: 41
7913 00:39:13.781003 [Byte1]: 41
7914 00:39:13.785310
7915 00:39:13.785413 Set Vref, RX VrefLevel [Byte0]: 42
7916 00:39:13.788702 [Byte1]: 42
7917 00:39:13.792799
7918 00:39:13.792869 Set Vref, RX VrefLevel [Byte0]: 43
7919 00:39:13.796197 [Byte1]: 43
7920 00:39:13.800914
7921 00:39:13.801016 Set Vref, RX VrefLevel [Byte0]: 44
7922 00:39:13.803828 [Byte1]: 44
7923 00:39:13.807880
7924 00:39:13.807980 Set Vref, RX VrefLevel [Byte0]: 45
7925 00:39:13.811577 [Byte1]: 45
7926 00:39:13.816131
7927 00:39:13.816256 Set Vref, RX VrefLevel [Byte0]: 46
7928 00:39:13.818813 [Byte1]: 46
7929 00:39:13.823583
7930 00:39:13.823689 Set Vref, RX VrefLevel [Byte0]: 47
7931 00:39:13.826558 [Byte1]: 47
7932 00:39:13.830769
7933 00:39:13.830842 Set Vref, RX VrefLevel [Byte0]: 48
7934 00:39:13.834565 [Byte1]: 48
7935 00:39:13.838341
7936 00:39:13.838424 Set Vref, RX VrefLevel [Byte0]: 49
7937 00:39:13.841687 [Byte1]: 49
7938 00:39:13.846352
7939 00:39:13.846453 Set Vref, RX VrefLevel [Byte0]: 50
7940 00:39:13.849114 [Byte1]: 50
7941 00:39:13.853552
7942 00:39:13.853667 Set Vref, RX VrefLevel [Byte0]: 51
7943 00:39:13.857257 [Byte1]: 51
7944 00:39:13.861324
7945 00:39:13.861433 Set Vref, RX VrefLevel [Byte0]: 52
7946 00:39:13.864600 [Byte1]: 52
7947 00:39:13.868908
7948 00:39:13.868978 Set Vref, RX VrefLevel [Byte0]: 53
7949 00:39:13.872069 [Byte1]: 53
7950 00:39:13.876439
7951 00:39:13.876535 Set Vref, RX VrefLevel [Byte0]: 54
7952 00:39:13.879470 [Byte1]: 54
7953 00:39:13.883880
7954 00:39:13.883953 Set Vref, RX VrefLevel [Byte0]: 55
7955 00:39:13.886838 [Byte1]: 55
7956 00:39:13.891328
7957 00:39:13.891402 Set Vref, RX VrefLevel [Byte0]: 56
7958 00:39:13.894870 [Byte1]: 56
7959 00:39:13.899157
7960 00:39:13.899227 Set Vref, RX VrefLevel [Byte0]: 57
7961 00:39:13.902063 [Byte1]: 57
7962 00:39:13.906450
7963 00:39:13.906524 Set Vref, RX VrefLevel [Byte0]: 58
7964 00:39:13.909786 [Byte1]: 58
7965 00:39:13.913969
7966 00:39:13.914073 Set Vref, RX VrefLevel [Byte0]: 59
7967 00:39:13.917524 [Byte1]: 59
7968 00:39:13.921682
7969 00:39:13.921783 Set Vref, RX VrefLevel [Byte0]: 60
7970 00:39:13.925015 [Byte1]: 60
7971 00:39:13.929462
7972 00:39:13.929561 Set Vref, RX VrefLevel [Byte0]: 61
7973 00:39:13.932632 [Byte1]: 61
7974 00:39:13.937113
7975 00:39:13.937215 Set Vref, RX VrefLevel [Byte0]: 62
7976 00:39:13.940547 [Byte1]: 62
7977 00:39:13.944356
7978 00:39:13.944456 Set Vref, RX VrefLevel [Byte0]: 63
7979 00:39:13.947962 [Byte1]: 63
7980 00:39:13.952104
7981 00:39:13.952202 Set Vref, RX VrefLevel [Byte0]: 64
7982 00:39:13.955386 [Byte1]: 64
7983 00:39:13.959420
7984 00:39:13.959508 Set Vref, RX VrefLevel [Byte0]: 65
7985 00:39:13.962856 [Byte1]: 65
7986 00:39:13.967207
7987 00:39:13.967386 Set Vref, RX VrefLevel [Byte0]: 66
7988 00:39:13.970407 [Byte1]: 66
7989 00:39:13.975024
7990 00:39:13.975112 Set Vref, RX VrefLevel [Byte0]: 67
7991 00:39:13.978264 [Byte1]: 67
7992 00:39:13.982645
7993 00:39:13.982752 Set Vref, RX VrefLevel [Byte0]: 68
7994 00:39:13.985844 [Byte1]: 68
7995 00:39:13.989721
7996 00:39:13.989823 Set Vref, RX VrefLevel [Byte0]: 69
7997 00:39:13.993024 [Byte1]: 69
7998 00:39:13.997273
7999 00:39:13.997388 Set Vref, RX VrefLevel [Byte0]: 70
8000 00:39:14.001231 [Byte1]: 70
8001 00:39:14.004877
8002 00:39:14.004974 Set Vref, RX VrefLevel [Byte0]: 71
8003 00:39:14.011521 [Byte1]: 71
8004 00:39:14.011622
8005 00:39:14.015014 Set Vref, RX VrefLevel [Byte0]: 72
8006 00:39:14.017927 [Byte1]: 72
8007 00:39:14.018026
8008 00:39:14.021669 Set Vref, RX VrefLevel [Byte0]: 73
8009 00:39:14.024642 [Byte1]: 73
8010 00:39:14.024740
8011 00:39:14.027876 Set Vref, RX VrefLevel [Byte0]: 74
8012 00:39:14.031060 [Byte1]: 74
8013 00:39:14.035404
8014 00:39:14.035480 Set Vref, RX VrefLevel [Byte0]: 75
8015 00:39:14.038844 [Byte1]: 75
8016 00:39:14.042919
8017 00:39:14.043017 Set Vref, RX VrefLevel [Byte0]: 76
8018 00:39:14.046067 [Byte1]: 76
8019 00:39:14.050749
8020 00:39:14.050836 Set Vref, RX VrefLevel [Byte0]: 77
8021 00:39:14.054341 [Byte1]: 77
8022 00:39:14.058076
8023 00:39:14.058193 Set Vref, RX VrefLevel [Byte0]: 78
8024 00:39:14.061178 [Byte1]: 78
8025 00:39:14.065998
8026 00:39:14.066098 Set Vref, RX VrefLevel [Byte0]: 79
8027 00:39:14.069067 [Byte1]: 79
8028 00:39:14.073124
8029 00:39:14.073225 Final RX Vref Byte 0 = 65 to rank0
8030 00:39:14.076570 Final RX Vref Byte 1 = 58 to rank0
8031 00:39:14.079835 Final RX Vref Byte 0 = 65 to rank1
8032 00:39:14.082850 Final RX Vref Byte 1 = 58 to rank1==
8033 00:39:14.086351 Dram Type= 6, Freq= 0, CH_0, rank 0
8034 00:39:14.092978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 00:39:14.093067 ==
8036 00:39:14.093133 DQS Delay:
8037 00:39:14.096567 DQS0 = 0, DQS1 = 0
8038 00:39:14.096664 DQM Delay:
8039 00:39:14.096753 DQM0 = 132, DQM1 = 123
8040 00:39:14.099469 DQ Delay:
8041 00:39:14.102883 DQ0 =130, DQ1 =132, DQ2 =130, DQ3 =132
8042 00:39:14.106569 DQ4 =132, DQ5 =122, DQ6 =138, DQ7 =142
8043 00:39:14.109242 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
8044 00:39:14.112596 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8045 00:39:14.112692
8046 00:39:14.112783
8047 00:39:14.112869
8048 00:39:14.116279 [DramC_TX_OE_Calibration] TA2
8049 00:39:14.119348 Original DQ_B0 (3 6) =30, OEN = 27
8050 00:39:14.122451 Original DQ_B1 (3 6) =30, OEN = 27
8051 00:39:14.125620 24, 0x0, End_B0=24 End_B1=24
8052 00:39:14.129002 25, 0x0, End_B0=25 End_B1=25
8053 00:39:14.129104 26, 0x0, End_B0=26 End_B1=26
8054 00:39:14.132323 27, 0x0, End_B0=27 End_B1=27
8055 00:39:14.135911 28, 0x0, End_B0=28 End_B1=28
8056 00:39:14.139034 29, 0x0, End_B0=29 End_B1=29
8057 00:39:14.139145 30, 0x0, End_B0=30 End_B1=30
8058 00:39:14.142100 31, 0x4141, End_B0=30 End_B1=30
8059 00:39:14.145483 Byte0 end_step=30 best_step=27
8060 00:39:14.148899 Byte1 end_step=30 best_step=27
8061 00:39:14.152519 Byte0 TX OE(2T, 0.5T) = (3, 3)
8062 00:39:14.155815 Byte1 TX OE(2T, 0.5T) = (3, 3)
8063 00:39:14.155902
8064 00:39:14.156001
8065 00:39:14.161926 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8066 00:39:14.165639 CH0 RK0: MR19=303, MR18=2011
8067 00:39:14.172211 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8068 00:39:14.172323
8069 00:39:14.175812 ----->DramcWriteLeveling(PI) begin...
8070 00:39:14.175887 ==
8071 00:39:14.178753 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 00:39:14.181743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 00:39:14.181844 ==
8074 00:39:14.185096 Write leveling (Byte 0): 36 => 36
8075 00:39:14.188386 Write leveling (Byte 1): 30 => 30
8076 00:39:14.191929 DramcWriteLeveling(PI) end<-----
8077 00:39:14.192026
8078 00:39:14.192123 ==
8079 00:39:14.195188 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 00:39:14.198561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 00:39:14.202013 ==
8082 00:39:14.202114 [Gating] SW mode calibration
8083 00:39:14.212162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8084 00:39:14.215164 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8085 00:39:14.218514 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 00:39:14.224709 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 00:39:14.228133 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 00:39:14.231309 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8089 00:39:14.238402 1 4 16 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
8090 00:39:14.241250 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8091 00:39:14.244358 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8092 00:39:14.251017 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 00:39:14.254240 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 00:39:14.258004 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8095 00:39:14.264653 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8096 00:39:14.267504 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8097 00:39:14.271122 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8098 00:39:14.277458 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8099 00:39:14.280747 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 00:39:14.283939 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 00:39:14.290628 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 00:39:14.294659 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 00:39:14.297236 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 00:39:14.303769 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8105 00:39:14.307224 1 6 16 | B1->B0 | 2a2a 4343 | 0 0 | (1 1) (0 0)
8106 00:39:14.310571 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8107 00:39:14.316934 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 00:39:14.320467 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 00:39:14.323932 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 00:39:14.330387 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 00:39:14.333957 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 00:39:14.337201 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8113 00:39:14.343894 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8114 00:39:14.346775 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8115 00:39:14.350089 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 00:39:14.356966 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 00:39:14.360396 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 00:39:14.363504 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 00:39:14.369842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 00:39:14.373656 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 00:39:14.376802 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 00:39:14.383096 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 00:39:14.386321 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 00:39:14.390017 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 00:39:14.396347 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 00:39:14.400139 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 00:39:14.403178 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8128 00:39:14.409623 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 00:39:14.409739 Total UI for P1: 0, mck2ui 16
8130 00:39:14.416324 best dqsien dly found for B0: ( 1, 9, 8)
8131 00:39:14.419573 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8132 00:39:14.422675 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8133 00:39:14.429361 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 00:39:14.429441 Total UI for P1: 0, mck2ui 16
8135 00:39:14.435986 best dqsien dly found for B1: ( 1, 9, 16)
8136 00:39:14.439613 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8137 00:39:14.442546 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8138 00:39:14.442644
8139 00:39:14.445810 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8140 00:39:14.449523 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8141 00:39:14.452515 [Gating] SW calibration Done
8142 00:39:14.452612 ==
8143 00:39:14.456030 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 00:39:14.459364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 00:39:14.459436 ==
8146 00:39:14.462606 RX Vref Scan: 0
8147 00:39:14.462679
8148 00:39:14.462740 RX Vref 0 -> 0, step: 1
8149 00:39:14.465654
8150 00:39:14.465763 RX Delay 0 -> 252, step: 8
8151 00:39:14.472606 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8152 00:39:14.475776 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8153 00:39:14.478850 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8154 00:39:14.482050 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8155 00:39:14.485446 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8156 00:39:14.491817 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8157 00:39:14.496007 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8158 00:39:14.498921 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8159 00:39:14.502412 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8160 00:39:14.505641 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8161 00:39:14.511851 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8162 00:39:14.515031 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8163 00:39:14.518311 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8164 00:39:14.521697 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8165 00:39:14.524968 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8166 00:39:14.531490 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8167 00:39:14.531598 ==
8168 00:39:14.534773 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 00:39:14.538058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 00:39:14.538185 ==
8171 00:39:14.538291 DQS Delay:
8172 00:39:14.541729 DQS0 = 0, DQS1 = 0
8173 00:39:14.541823 DQM Delay:
8174 00:39:14.544619 DQM0 = 132, DQM1 = 130
8175 00:39:14.544723 DQ Delay:
8176 00:39:14.548066 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8177 00:39:14.551680 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8178 00:39:14.554766 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8179 00:39:14.561541 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8180 00:39:14.561646
8181 00:39:14.561794
8182 00:39:14.561928 ==
8183 00:39:14.564912 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 00:39:14.568034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 00:39:14.568133 ==
8186 00:39:14.568225
8187 00:39:14.568311
8188 00:39:14.571423 TX Vref Scan disable
8189 00:39:14.571536 == TX Byte 0 ==
8190 00:39:14.577665 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8191 00:39:14.581115 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8192 00:39:14.581219 == TX Byte 1 ==
8193 00:39:14.587838 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8194 00:39:14.591016 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8195 00:39:14.591115 ==
8196 00:39:14.594105 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 00:39:14.597353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 00:39:14.597429 ==
8199 00:39:14.611984
8200 00:39:14.615321 TX Vref early break, caculate TX vref
8201 00:39:14.618347 TX Vref=16, minBit 2, minWin=22, winSum=383
8202 00:39:14.622317 TX Vref=18, minBit 0, minWin=23, winSum=385
8203 00:39:14.625004 TX Vref=20, minBit 0, minWin=23, winSum=395
8204 00:39:14.628620 TX Vref=22, minBit 1, minWin=24, winSum=407
8205 00:39:14.632036 TX Vref=24, minBit 3, minWin=24, winSum=413
8206 00:39:14.638015 TX Vref=26, minBit 1, minWin=24, winSum=416
8207 00:39:14.641188 TX Vref=28, minBit 0, minWin=24, winSum=413
8208 00:39:14.644635 TX Vref=30, minBit 0, minWin=24, winSum=408
8209 00:39:14.648166 TX Vref=32, minBit 0, minWin=24, winSum=398
8210 00:39:14.651570 TX Vref=34, minBit 2, minWin=23, winSum=394
8211 00:39:14.657737 [TxChooseVref] Worse bit 1, Min win 24, Win sum 416, Final Vref 26
8212 00:39:14.657853
8213 00:39:14.661347 Final TX Range 0 Vref 26
8214 00:39:14.661445
8215 00:39:14.661537 ==
8216 00:39:14.664633 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 00:39:14.667753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 00:39:14.667895 ==
8219 00:39:14.667987
8220 00:39:14.668077
8221 00:39:14.671499 TX Vref Scan disable
8222 00:39:14.677792 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8223 00:39:14.677950 == TX Byte 0 ==
8224 00:39:14.681636 u2DelayCellOfst[0]=14 cells (4 PI)
8225 00:39:14.684445 u2DelayCellOfst[1]=18 cells (5 PI)
8226 00:39:14.687598 u2DelayCellOfst[2]=14 cells (4 PI)
8227 00:39:14.690915 u2DelayCellOfst[3]=14 cells (4 PI)
8228 00:39:14.694760 u2DelayCellOfst[4]=11 cells (3 PI)
8229 00:39:14.697807 u2DelayCellOfst[5]=0 cells (0 PI)
8230 00:39:14.700527 u2DelayCellOfst[6]=22 cells (6 PI)
8231 00:39:14.704348 u2DelayCellOfst[7]=18 cells (5 PI)
8232 00:39:14.707493 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8233 00:39:14.710762 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8234 00:39:14.713956 == TX Byte 1 ==
8235 00:39:14.717531 u2DelayCellOfst[8]=0 cells (0 PI)
8236 00:39:14.720694 u2DelayCellOfst[9]=3 cells (1 PI)
8237 00:39:14.724068 u2DelayCellOfst[10]=11 cells (3 PI)
8238 00:39:14.727283 u2DelayCellOfst[11]=3 cells (1 PI)
8239 00:39:14.730757 u2DelayCellOfst[12]=14 cells (4 PI)
8240 00:39:14.733477 u2DelayCellOfst[13]=14 cells (4 PI)
8241 00:39:14.736776 u2DelayCellOfst[14]=18 cells (5 PI)
8242 00:39:14.736884 u2DelayCellOfst[15]=14 cells (4 PI)
8243 00:39:14.743806 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8244 00:39:14.746673 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8245 00:39:14.750143 DramC Write-DBI on
8246 00:39:14.750225 ==
8247 00:39:14.753629 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 00:39:14.756762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 00:39:14.756863 ==
8250 00:39:14.756962
8251 00:39:14.757052
8252 00:39:14.760313 TX Vref Scan disable
8253 00:39:14.763299 == TX Byte 0 ==
8254 00:39:14.766424 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8255 00:39:14.766494 == TX Byte 1 ==
8256 00:39:14.772897 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8257 00:39:14.772995 DramC Write-DBI off
8258 00:39:14.773086
8259 00:39:14.773183 [DATLAT]
8260 00:39:14.776103 Freq=1600, CH0 RK1
8261 00:39:14.776205
8262 00:39:14.779373 DATLAT Default: 0xf
8263 00:39:14.779474 0, 0xFFFF, sum = 0
8264 00:39:14.782780 1, 0xFFFF, sum = 0
8265 00:39:14.782878 2, 0xFFFF, sum = 0
8266 00:39:14.786240 3, 0xFFFF, sum = 0
8267 00:39:14.786312 4, 0xFFFF, sum = 0
8268 00:39:14.789518 5, 0xFFFF, sum = 0
8269 00:39:14.789617 6, 0xFFFF, sum = 0
8270 00:39:14.792745 7, 0xFFFF, sum = 0
8271 00:39:14.792846 8, 0xFFFF, sum = 0
8272 00:39:14.795730 9, 0xFFFF, sum = 0
8273 00:39:14.795829 10, 0xFFFF, sum = 0
8274 00:39:14.799104 11, 0xFFFF, sum = 0
8275 00:39:14.799215 12, 0xFFFF, sum = 0
8276 00:39:14.802699 13, 0xFFFF, sum = 0
8277 00:39:14.802801 14, 0x0, sum = 1
8278 00:39:14.805561 15, 0x0, sum = 2
8279 00:39:14.805666 16, 0x0, sum = 3
8280 00:39:14.808870 17, 0x0, sum = 4
8281 00:39:14.808982 best_step = 15
8282 00:39:14.809076
8283 00:39:14.809171 ==
8284 00:39:14.812611 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 00:39:14.819056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 00:39:14.819166 ==
8287 00:39:14.819269 RX Vref Scan: 0
8288 00:39:14.819358
8289 00:39:14.822498 RX Vref 0 -> 0, step: 1
8290 00:39:14.822596
8291 00:39:14.825760 RX Delay 11 -> 252, step: 4
8292 00:39:14.829255 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8293 00:39:14.832378 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8294 00:39:14.839142 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8295 00:39:14.842521 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8296 00:39:14.845626 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8297 00:39:14.848913 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8298 00:39:14.852440 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8299 00:39:14.855627 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8300 00:39:14.862044 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8301 00:39:14.865591 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8302 00:39:14.868902 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8303 00:39:14.872322 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8304 00:39:14.878709 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8305 00:39:14.882256 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8306 00:39:14.885684 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8307 00:39:14.888669 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8308 00:39:14.888767 ==
8309 00:39:14.892151 Dram Type= 6, Freq= 0, CH_0, rank 1
8310 00:39:14.898370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 00:39:14.898447 ==
8312 00:39:14.898509 DQS Delay:
8313 00:39:14.898568 DQS0 = 0, DQS1 = 0
8314 00:39:14.902122 DQM Delay:
8315 00:39:14.902228 DQM0 = 130, DQM1 = 125
8316 00:39:14.904864 DQ Delay:
8317 00:39:14.908207 DQ0 =128, DQ1 =136, DQ2 =124, DQ3 =128
8318 00:39:14.911257 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8319 00:39:14.914517 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8320 00:39:14.918404 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8321 00:39:14.918505
8322 00:39:14.918607
8323 00:39:14.918696
8324 00:39:14.921038 [DramC_TX_OE_Calibration] TA2
8325 00:39:14.924837 Original DQ_B0 (3 6) =30, OEN = 27
8326 00:39:14.928123 Original DQ_B1 (3 6) =30, OEN = 27
8327 00:39:14.931499 24, 0x0, End_B0=24 End_B1=24
8328 00:39:14.934558 25, 0x0, End_B0=25 End_B1=25
8329 00:39:14.934657 26, 0x0, End_B0=26 End_B1=26
8330 00:39:14.938155 27, 0x0, End_B0=27 End_B1=27
8331 00:39:14.941525 28, 0x0, End_B0=28 End_B1=28
8332 00:39:14.944532 29, 0x0, End_B0=29 End_B1=29
8333 00:39:14.944632 30, 0x0, End_B0=30 End_B1=30
8334 00:39:14.947657 31, 0x4141, End_B0=30 End_B1=30
8335 00:39:14.951415 Byte0 end_step=30 best_step=27
8336 00:39:14.954417 Byte1 end_step=30 best_step=27
8337 00:39:14.957840 Byte0 TX OE(2T, 0.5T) = (3, 3)
8338 00:39:14.960790 Byte1 TX OE(2T, 0.5T) = (3, 3)
8339 00:39:14.960887
8340 00:39:14.960979
8341 00:39:14.967751 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8342 00:39:14.971427 CH0 RK1: MR19=303, MR18=1F03
8343 00:39:14.977325 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8344 00:39:14.980965 [RxdqsGatingPostProcess] freq 1600
8345 00:39:14.987919 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8346 00:39:14.988018 best DQS0 dly(2T, 0.5T) = (1, 1)
8347 00:39:14.990720 best DQS1 dly(2T, 0.5T) = (1, 1)
8348 00:39:14.994273 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8349 00:39:14.997259 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8350 00:39:15.000593 best DQS0 dly(2T, 0.5T) = (1, 1)
8351 00:39:15.004622 best DQS1 dly(2T, 0.5T) = (1, 1)
8352 00:39:15.007409 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8353 00:39:15.010509 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8354 00:39:15.013663 Pre-setting of DQS Precalculation
8355 00:39:15.017395 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8356 00:39:15.017492 ==
8357 00:39:15.020641 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 00:39:15.026780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 00:39:15.026888 ==
8360 00:39:15.030652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8361 00:39:15.036719 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8362 00:39:15.039959 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8363 00:39:15.046614 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8364 00:39:15.054738 [CA 0] Center 42 (13~72) winsize 60
8365 00:39:15.057879 [CA 1] Center 42 (13~72) winsize 60
8366 00:39:15.061040 [CA 2] Center 38 (9~67) winsize 59
8367 00:39:15.064655 [CA 3] Center 36 (7~66) winsize 60
8368 00:39:15.067769 [CA 4] Center 38 (9~67) winsize 59
8369 00:39:15.071282 [CA 5] Center 37 (8~67) winsize 60
8370 00:39:15.071383
8371 00:39:15.074849 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8372 00:39:15.074929
8373 00:39:15.078007 [CATrainingPosCal] consider 1 rank data
8374 00:39:15.081204 u2DelayCellTimex100 = 262/100 ps
8375 00:39:15.087752 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8376 00:39:15.090871 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8377 00:39:15.094396 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8378 00:39:15.097644 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8379 00:39:15.101063 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8380 00:39:15.104191 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8381 00:39:15.104292
8382 00:39:15.107419 CA PerBit enable=1, Macro0, CA PI delay=36
8383 00:39:15.107524
8384 00:39:15.111132 [CBTSetCACLKResult] CA Dly = 36
8385 00:39:15.113873 CS Dly: 9 (0~40)
8386 00:39:15.117147 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8387 00:39:15.120598 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8388 00:39:15.120702 ==
8389 00:39:15.123773 Dram Type= 6, Freq= 0, CH_1, rank 1
8390 00:39:15.131114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 00:39:15.131212 ==
8392 00:39:15.133613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8393 00:39:15.140233 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8394 00:39:15.143519 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8395 00:39:15.150411 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8396 00:39:15.158001 [CA 0] Center 42 (13~72) winsize 60
8397 00:39:15.161087 [CA 1] Center 42 (13~72) winsize 60
8398 00:39:15.164273 [CA 2] Center 37 (8~67) winsize 60
8399 00:39:15.167416 [CA 3] Center 37 (7~67) winsize 61
8400 00:39:15.171023 [CA 4] Center 38 (9~67) winsize 59
8401 00:39:15.174227 [CA 5] Center 37 (8~67) winsize 60
8402 00:39:15.174319
8403 00:39:15.177320 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8404 00:39:15.177391
8405 00:39:15.184127 [CATrainingPosCal] consider 2 rank data
8406 00:39:15.184234 u2DelayCellTimex100 = 262/100 ps
8407 00:39:15.190382 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8408 00:39:15.193914 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8409 00:39:15.197085 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8410 00:39:15.200667 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8411 00:39:15.204089 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8412 00:39:15.207327 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8413 00:39:15.207435
8414 00:39:15.211148 CA PerBit enable=1, Macro0, CA PI delay=36
8415 00:39:15.211245
8416 00:39:15.213793 [CBTSetCACLKResult] CA Dly = 36
8417 00:39:15.217309 CS Dly: 10 (0~43)
8418 00:39:15.220446 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8419 00:39:15.223935 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8420 00:39:15.224033
8421 00:39:15.227090 ----->DramcWriteLeveling(PI) begin...
8422 00:39:15.227174 ==
8423 00:39:15.230565 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 00:39:15.236847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 00:39:15.236954 ==
8426 00:39:15.240372 Write leveling (Byte 0): 22 => 22
8427 00:39:15.243191 Write leveling (Byte 1): 25 => 25
8428 00:39:15.246632 DramcWriteLeveling(PI) end<-----
8429 00:39:15.246705
8430 00:39:15.246765 ==
8431 00:39:15.250397 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 00:39:15.253273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 00:39:15.253370 ==
8434 00:39:15.257075 [Gating] SW mode calibration
8435 00:39:15.263365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8436 00:39:15.270095 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8437 00:39:15.273237 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 00:39:15.276161 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 00:39:15.282760 1 4 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
8440 00:39:15.286113 1 4 12 | B1->B0 | 2f2e 3434 | 1 0 | (0 0) (0 0)
8441 00:39:15.289708 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 00:39:15.296111 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 00:39:15.299486 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 00:39:15.302966 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 00:39:15.305841 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 00:39:15.312493 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 00:39:15.315703 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8448 00:39:15.322943 1 5 12 | B1->B0 | 3131 2727 | 0 0 | (1 0) (1 0)
8449 00:39:15.325742 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 00:39:15.328911 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 00:39:15.335598 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 00:39:15.339038 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 00:39:15.342344 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 00:39:15.349199 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 00:39:15.352393 1 6 8 | B1->B0 | 2525 2727 | 0 1 | (0 0) (0 0)
8456 00:39:15.355777 1 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
8457 00:39:15.361958 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 00:39:15.365369 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 00:39:15.368460 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 00:39:15.372029 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 00:39:15.378855 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 00:39:15.382145 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 00:39:15.385381 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8464 00:39:15.391657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8465 00:39:15.395263 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 00:39:15.398473 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 00:39:15.404888 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 00:39:15.408185 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 00:39:15.411362 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 00:39:15.418157 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 00:39:15.421348 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 00:39:15.427852 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 00:39:15.431375 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 00:39:15.434881 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 00:39:15.437819 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 00:39:15.444802 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 00:39:15.447716 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 00:39:15.451531 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 00:39:15.457740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8480 00:39:15.461063 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8481 00:39:15.464815 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 00:39:15.467436 Total UI for P1: 0, mck2ui 16
8483 00:39:15.471330 best dqsien dly found for B0: ( 1, 9, 10)
8484 00:39:15.474378 Total UI for P1: 0, mck2ui 16
8485 00:39:15.477584 best dqsien dly found for B1: ( 1, 9, 10)
8486 00:39:15.480907 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8487 00:39:15.487359 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8488 00:39:15.487460
8489 00:39:15.491209 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8490 00:39:15.494105 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8491 00:39:15.497246 [Gating] SW calibration Done
8492 00:39:15.497344 ==
8493 00:39:15.500558 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 00:39:15.503976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 00:39:15.504079 ==
8496 00:39:15.507654 RX Vref Scan: 0
8497 00:39:15.507755
8498 00:39:15.507847 RX Vref 0 -> 0, step: 1
8499 00:39:15.507934
8500 00:39:15.510346 RX Delay 0 -> 252, step: 8
8501 00:39:15.514133 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8502 00:39:15.520431 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8503 00:39:15.523646 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8504 00:39:15.527088 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8505 00:39:15.530105 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8506 00:39:15.533707 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8507 00:39:15.540251 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8508 00:39:15.543808 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8509 00:39:15.546926 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8510 00:39:15.549967 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8511 00:39:15.553163 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8512 00:39:15.559639 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8513 00:39:15.563407 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8514 00:39:15.566489 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8515 00:39:15.569655 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8516 00:39:15.576428 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8517 00:39:15.576528 ==
8518 00:39:15.579556 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 00:39:15.582936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 00:39:15.583078 ==
8521 00:39:15.583144 DQS Delay:
8522 00:39:15.586537 DQS0 = 0, DQS1 = 0
8523 00:39:15.586614 DQM Delay:
8524 00:39:15.589541 DQM0 = 137, DQM1 = 128
8525 00:39:15.589638 DQ Delay:
8526 00:39:15.592968 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8527 00:39:15.596380 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8528 00:39:15.599272 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8529 00:39:15.602879 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8530 00:39:15.602954
8531 00:39:15.603029
8532 00:39:15.605817 ==
8533 00:39:15.609456 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 00:39:15.612499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 00:39:15.612609 ==
8536 00:39:15.612702
8537 00:39:15.612797
8538 00:39:15.615843 TX Vref Scan disable
8539 00:39:15.615949 == TX Byte 0 ==
8540 00:39:15.622438 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8541 00:39:15.625557 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8542 00:39:15.625658 == TX Byte 1 ==
8543 00:39:15.632485 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8544 00:39:15.635702 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8545 00:39:15.635817 ==
8546 00:39:15.638929 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 00:39:15.642392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 00:39:15.642494 ==
8549 00:39:15.655697
8550 00:39:15.658920 TX Vref early break, caculate TX vref
8551 00:39:15.662122 TX Vref=16, minBit 5, minWin=21, winSum=374
8552 00:39:15.665198 TX Vref=18, minBit 0, minWin=22, winSum=385
8553 00:39:15.669146 TX Vref=20, minBit 0, minWin=23, winSum=398
8554 00:39:15.671960 TX Vref=22, minBit 0, minWin=23, winSum=402
8555 00:39:15.675985 TX Vref=24, minBit 5, minWin=24, winSum=411
8556 00:39:15.681793 TX Vref=26, minBit 0, minWin=24, winSum=420
8557 00:39:15.685095 TX Vref=28, minBit 5, minWin=24, winSum=420
8558 00:39:15.688562 TX Vref=30, minBit 0, minWin=23, winSum=407
8559 00:39:15.691606 TX Vref=32, minBit 0, minWin=23, winSum=405
8560 00:39:15.694835 TX Vref=34, minBit 0, minWin=23, winSum=390
8561 00:39:15.701824 [TxChooseVref] Worse bit 0, Min win 24, Win sum 420, Final Vref 26
8562 00:39:15.701925
8563 00:39:15.704972 Final TX Range 0 Vref 26
8564 00:39:15.705076
8565 00:39:15.705178 ==
8566 00:39:15.708262 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 00:39:15.711835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 00:39:15.711927 ==
8569 00:39:15.711992
8570 00:39:15.712051
8571 00:39:15.714676 TX Vref Scan disable
8572 00:39:15.721616 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8573 00:39:15.721729 == TX Byte 0 ==
8574 00:39:15.724864 u2DelayCellOfst[0]=18 cells (5 PI)
8575 00:39:15.728092 u2DelayCellOfst[1]=14 cells (4 PI)
8576 00:39:15.731371 u2DelayCellOfst[2]=0 cells (0 PI)
8577 00:39:15.735050 u2DelayCellOfst[3]=7 cells (2 PI)
8578 00:39:15.738153 u2DelayCellOfst[4]=11 cells (3 PI)
8579 00:39:15.741495 u2DelayCellOfst[5]=22 cells (6 PI)
8580 00:39:15.744471 u2DelayCellOfst[6]=18 cells (5 PI)
8581 00:39:15.747765 u2DelayCellOfst[7]=7 cells (2 PI)
8582 00:39:15.751570 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8583 00:39:15.754624 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8584 00:39:15.757818 == TX Byte 1 ==
8585 00:39:15.761438 u2DelayCellOfst[8]=0 cells (0 PI)
8586 00:39:15.764420 u2DelayCellOfst[9]=3 cells (1 PI)
8587 00:39:15.764523 u2DelayCellOfst[10]=11 cells (3 PI)
8588 00:39:15.767679 u2DelayCellOfst[11]=3 cells (1 PI)
8589 00:39:15.771150 u2DelayCellOfst[12]=14 cells (4 PI)
8590 00:39:15.774543 u2DelayCellOfst[13]=18 cells (5 PI)
8591 00:39:15.777765 u2DelayCellOfst[14]=18 cells (5 PI)
8592 00:39:15.780953 u2DelayCellOfst[15]=18 cells (5 PI)
8593 00:39:15.787333 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8594 00:39:15.790705 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8595 00:39:15.790805 DramC Write-DBI on
8596 00:39:15.790898 ==
8597 00:39:15.794121 Dram Type= 6, Freq= 0, CH_1, rank 0
8598 00:39:15.800894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8599 00:39:15.800994 ==
8600 00:39:15.801084
8601 00:39:15.801173
8602 00:39:15.803745 TX Vref Scan disable
8603 00:39:15.803838 == TX Byte 0 ==
8604 00:39:15.810426 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8605 00:39:15.810501 == TX Byte 1 ==
8606 00:39:15.813723 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8607 00:39:15.816992 DramC Write-DBI off
8608 00:39:15.817104
8609 00:39:15.817198 [DATLAT]
8610 00:39:15.820385 Freq=1600, CH1 RK0
8611 00:39:15.820485
8612 00:39:15.820580 DATLAT Default: 0xf
8613 00:39:15.824044 0, 0xFFFF, sum = 0
8614 00:39:15.824127 1, 0xFFFF, sum = 0
8615 00:39:15.827340 2, 0xFFFF, sum = 0
8616 00:39:15.827414 3, 0xFFFF, sum = 0
8617 00:39:15.830874 4, 0xFFFF, sum = 0
8618 00:39:15.830974 5, 0xFFFF, sum = 0
8619 00:39:15.833922 6, 0xFFFF, sum = 0
8620 00:39:15.833997 7, 0xFFFF, sum = 0
8621 00:39:15.837265 8, 0xFFFF, sum = 0
8622 00:39:15.837340 9, 0xFFFF, sum = 0
8623 00:39:15.840632 10, 0xFFFF, sum = 0
8624 00:39:15.843505 11, 0xFFFF, sum = 0
8625 00:39:15.843597 12, 0xFFFF, sum = 0
8626 00:39:15.847160 13, 0xFFFF, sum = 0
8627 00:39:15.847236 14, 0x0, sum = 1
8628 00:39:15.850104 15, 0x0, sum = 2
8629 00:39:15.850233 16, 0x0, sum = 3
8630 00:39:15.853447 17, 0x0, sum = 4
8631 00:39:15.853533 best_step = 15
8632 00:39:15.853622
8633 00:39:15.853707 ==
8634 00:39:15.857220 Dram Type= 6, Freq= 0, CH_1, rank 0
8635 00:39:15.860169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8636 00:39:15.860269 ==
8637 00:39:15.863567 RX Vref Scan: 1
8638 00:39:15.863655
8639 00:39:15.867015 Set Vref Range= 24 -> 127
8640 00:39:15.867089
8641 00:39:15.867150 RX Vref 24 -> 127, step: 1
8642 00:39:15.867208
8643 00:39:15.870049 RX Delay 11 -> 252, step: 4
8644 00:39:15.870148
8645 00:39:15.873171 Set Vref, RX VrefLevel [Byte0]: 24
8646 00:39:15.876510 [Byte1]: 24
8647 00:39:15.879826
8648 00:39:15.879930 Set Vref, RX VrefLevel [Byte0]: 25
8649 00:39:15.883716 [Byte1]: 25
8650 00:39:15.888031
8651 00:39:15.888136 Set Vref, RX VrefLevel [Byte0]: 26
8652 00:39:15.890887 [Byte1]: 26
8653 00:39:15.895549
8654 00:39:15.895647 Set Vref, RX VrefLevel [Byte0]: 27
8655 00:39:15.898916 [Byte1]: 27
8656 00:39:15.902741
8657 00:39:15.902816 Set Vref, RX VrefLevel [Byte0]: 28
8658 00:39:15.906074 [Byte1]: 28
8659 00:39:15.910369
8660 00:39:15.910467 Set Vref, RX VrefLevel [Byte0]: 29
8661 00:39:15.913659 [Byte1]: 29
8662 00:39:15.918156
8663 00:39:15.918271 Set Vref, RX VrefLevel [Byte0]: 30
8664 00:39:15.921730 [Byte1]: 30
8665 00:39:15.925547
8666 00:39:15.925652 Set Vref, RX VrefLevel [Byte0]: 31
8667 00:39:15.929024 [Byte1]: 31
8668 00:39:15.933215
8669 00:39:15.933330 Set Vref, RX VrefLevel [Byte0]: 32
8670 00:39:15.936742 [Byte1]: 32
8671 00:39:15.940831
8672 00:39:15.940934 Set Vref, RX VrefLevel [Byte0]: 33
8673 00:39:15.944237 [Byte1]: 33
8674 00:39:15.948736
8675 00:39:15.948818 Set Vref, RX VrefLevel [Byte0]: 34
8676 00:39:15.952017 [Byte1]: 34
8677 00:39:15.956110
8678 00:39:15.956210 Set Vref, RX VrefLevel [Byte0]: 35
8679 00:39:15.959543 [Byte1]: 35
8680 00:39:15.963747
8681 00:39:15.963845 Set Vref, RX VrefLevel [Byte0]: 36
8682 00:39:15.967058 [Byte1]: 36
8683 00:39:15.971543
8684 00:39:15.971645 Set Vref, RX VrefLevel [Byte0]: 37
8685 00:39:15.974833 [Byte1]: 37
8686 00:39:15.978955
8687 00:39:15.979058 Set Vref, RX VrefLevel [Byte0]: 38
8688 00:39:15.982409 [Byte1]: 38
8689 00:39:15.986808
8690 00:39:15.986882 Set Vref, RX VrefLevel [Byte0]: 39
8691 00:39:15.989921 [Byte1]: 39
8692 00:39:15.994052
8693 00:39:15.994171 Set Vref, RX VrefLevel [Byte0]: 40
8694 00:39:15.997380 [Byte1]: 40
8695 00:39:16.001846
8696 00:39:16.001947 Set Vref, RX VrefLevel [Byte0]: 41
8697 00:39:16.005716 [Byte1]: 41
8698 00:39:16.009469
8699 00:39:16.009568 Set Vref, RX VrefLevel [Byte0]: 42
8700 00:39:16.012676 [Byte1]: 42
8701 00:39:16.016981
8702 00:39:16.017178 Set Vref, RX VrefLevel [Byte0]: 43
8703 00:39:16.023891 [Byte1]: 43
8704 00:39:16.024002
8705 00:39:16.027003 Set Vref, RX VrefLevel [Byte0]: 44
8706 00:39:16.030023 [Byte1]: 44
8707 00:39:16.030145
8708 00:39:16.033639 Set Vref, RX VrefLevel [Byte0]: 45
8709 00:39:16.036781 [Byte1]: 45
8710 00:39:16.039847
8711 00:39:16.039917 Set Vref, RX VrefLevel [Byte0]: 46
8712 00:39:16.043492 [Byte1]: 46
8713 00:39:16.047816
8714 00:39:16.047919 Set Vref, RX VrefLevel [Byte0]: 47
8715 00:39:16.050773 [Byte1]: 47
8716 00:39:16.055367
8717 00:39:16.055465 Set Vref, RX VrefLevel [Byte0]: 48
8718 00:39:16.058689 [Byte1]: 48
8719 00:39:16.062517
8720 00:39:16.062589 Set Vref, RX VrefLevel [Byte0]: 49
8721 00:39:16.065829 [Byte1]: 49
8722 00:39:16.070342
8723 00:39:16.070441 Set Vref, RX VrefLevel [Byte0]: 50
8724 00:39:16.073606 [Byte1]: 50
8725 00:39:16.077969
8726 00:39:16.078069 Set Vref, RX VrefLevel [Byte0]: 51
8727 00:39:16.081041 [Byte1]: 51
8728 00:39:16.085562
8729 00:39:16.085665 Set Vref, RX VrefLevel [Byte0]: 52
8730 00:39:16.088702 [Byte1]: 52
8731 00:39:16.093193
8732 00:39:16.093310 Set Vref, RX VrefLevel [Byte0]: 53
8733 00:39:16.096389 [Byte1]: 53
8734 00:39:16.101103
8735 00:39:16.101205 Set Vref, RX VrefLevel [Byte0]: 54
8736 00:39:16.104067 [Byte1]: 54
8737 00:39:16.108240
8738 00:39:16.108343 Set Vref, RX VrefLevel [Byte0]: 55
8739 00:39:16.111625 [Byte1]: 55
8740 00:39:16.116192
8741 00:39:16.116304 Set Vref, RX VrefLevel [Byte0]: 56
8742 00:39:16.122790 [Byte1]: 56
8743 00:39:16.122870
8744 00:39:16.125806 Set Vref, RX VrefLevel [Byte0]: 57
8745 00:39:16.129159 [Byte1]: 57
8746 00:39:16.129256
8747 00:39:16.132339 Set Vref, RX VrefLevel [Byte0]: 58
8748 00:39:16.135736 [Byte1]: 58
8749 00:39:16.138936
8750 00:39:16.139036 Set Vref, RX VrefLevel [Byte0]: 59
8751 00:39:16.141932 [Byte1]: 59
8752 00:39:16.146326
8753 00:39:16.146428 Set Vref, RX VrefLevel [Byte0]: 60
8754 00:39:16.149917 [Byte1]: 60
8755 00:39:16.154246
8756 00:39:16.154318 Set Vref, RX VrefLevel [Byte0]: 61
8757 00:39:16.157185 [Byte1]: 61
8758 00:39:16.161675
8759 00:39:16.161775 Set Vref, RX VrefLevel [Byte0]: 62
8760 00:39:16.165092 [Byte1]: 62
8761 00:39:16.169091
8762 00:39:16.169199 Set Vref, RX VrefLevel [Byte0]: 63
8763 00:39:16.172523 [Byte1]: 63
8764 00:39:16.177034
8765 00:39:16.177109 Set Vref, RX VrefLevel [Byte0]: 64
8766 00:39:16.180585 [Byte1]: 64
8767 00:39:16.184551
8768 00:39:16.184648 Set Vref, RX VrefLevel [Byte0]: 65
8769 00:39:16.187918 [Byte1]: 65
8770 00:39:16.192045
8771 00:39:16.192144 Set Vref, RX VrefLevel [Byte0]: 66
8772 00:39:16.195224 [Byte1]: 66
8773 00:39:16.199467
8774 00:39:16.199579 Set Vref, RX VrefLevel [Byte0]: 67
8775 00:39:16.203105 [Byte1]: 67
8776 00:39:16.207372
8777 00:39:16.207470 Set Vref, RX VrefLevel [Byte0]: 68
8778 00:39:16.210496 [Byte1]: 68
8779 00:39:16.214900
8780 00:39:16.215003 Set Vref, RX VrefLevel [Byte0]: 69
8781 00:39:16.221848 [Byte1]: 69
8782 00:39:16.221954
8783 00:39:16.224984 Set Vref, RX VrefLevel [Byte0]: 70
8784 00:39:16.228153 [Byte1]: 70
8785 00:39:16.228251
8786 00:39:16.231326 Set Vref, RX VrefLevel [Byte0]: 71
8787 00:39:16.234271 [Byte1]: 71
8788 00:39:16.237807
8789 00:39:16.237905 Set Vref, RX VrefLevel [Byte0]: 72
8790 00:39:16.241025 [Byte1]: 72
8791 00:39:16.245304
8792 00:39:16.245375 Set Vref, RX VrefLevel [Byte0]: 73
8793 00:39:16.248910 [Byte1]: 73
8794 00:39:16.253281
8795 00:39:16.253350 Final RX Vref Byte 0 = 54 to rank0
8796 00:39:16.256410 Final RX Vref Byte 1 = 57 to rank0
8797 00:39:16.260266 Final RX Vref Byte 0 = 54 to rank1
8798 00:39:16.262929 Final RX Vref Byte 1 = 57 to rank1==
8799 00:39:16.266535 Dram Type= 6, Freq= 0, CH_1, rank 0
8800 00:39:16.272899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 00:39:16.273004 ==
8802 00:39:16.273069 DQS Delay:
8803 00:39:16.273126 DQS0 = 0, DQS1 = 0
8804 00:39:16.276140 DQM Delay:
8805 00:39:16.276213 DQM0 = 133, DQM1 = 127
8806 00:39:16.279790 DQ Delay:
8807 00:39:16.283066 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8808 00:39:16.286517 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8809 00:39:16.289537 DQ8 =114, DQ9 =114, DQ10 =130, DQ11 =116
8810 00:39:16.292726 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =138
8811 00:39:16.292824
8812 00:39:16.292911
8813 00:39:16.292997
8814 00:39:16.296263 [DramC_TX_OE_Calibration] TA2
8815 00:39:16.299164 Original DQ_B0 (3 6) =30, OEN = 27
8816 00:39:16.303044 Original DQ_B1 (3 6) =30, OEN = 27
8817 00:39:16.305983 24, 0x0, End_B0=24 End_B1=24
8818 00:39:16.306085 25, 0x0, End_B0=25 End_B1=25
8819 00:39:16.309406 26, 0x0, End_B0=26 End_B1=26
8820 00:39:16.312880 27, 0x0, End_B0=27 End_B1=27
8821 00:39:16.315928 28, 0x0, End_B0=28 End_B1=28
8822 00:39:16.319576 29, 0x0, End_B0=29 End_B1=29
8823 00:39:16.319680 30, 0x0, End_B0=30 End_B1=30
8824 00:39:16.322756 31, 0x4141, End_B0=30 End_B1=30
8825 00:39:16.325657 Byte0 end_step=30 best_step=27
8826 00:39:16.329069 Byte1 end_step=30 best_step=27
8827 00:39:16.332202 Byte0 TX OE(2T, 0.5T) = (3, 3)
8828 00:39:16.335455 Byte1 TX OE(2T, 0.5T) = (3, 3)
8829 00:39:16.335555
8830 00:39:16.335695
8831 00:39:16.342382 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8832 00:39:16.345912 CH1 RK0: MR19=303, MR18=1A10
8833 00:39:16.352226 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8834 00:39:16.352333
8835 00:39:16.355614 ----->DramcWriteLeveling(PI) begin...
8836 00:39:16.355726 ==
8837 00:39:16.358561 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 00:39:16.362015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 00:39:16.362112 ==
8840 00:39:16.365248 Write leveling (Byte 0): 24 => 24
8841 00:39:16.368866 Write leveling (Byte 1): 26 => 26
8842 00:39:16.372048 DramcWriteLeveling(PI) end<-----
8843 00:39:16.372154
8844 00:39:16.372223 ==
8845 00:39:16.374991 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 00:39:16.378667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 00:39:16.381728 ==
8848 00:39:16.381849 [Gating] SW mode calibration
8849 00:39:16.391628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8850 00:39:16.394919 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8851 00:39:16.398337 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 00:39:16.404866 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 00:39:16.408150 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
8854 00:39:16.411468 1 4 12 | B1->B0 | 3333 2323 | 0 1 | (0 0) (1 1)
8855 00:39:16.417760 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 00:39:16.421125 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 00:39:16.424186 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 00:39:16.430635 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 00:39:16.434471 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 00:39:16.440701 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8861 00:39:16.443989 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8862 00:39:16.447131 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8863 00:39:16.454248 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 00:39:16.457152 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 00:39:16.460490 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 00:39:16.466857 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 00:39:16.470574 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 00:39:16.473579 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 00:39:16.477068 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8870 00:39:16.483638 1 6 12 | B1->B0 | 4646 2626 | 0 0 | (0 0) (0 0)
8871 00:39:16.486914 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8872 00:39:16.490016 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 00:39:16.496999 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 00:39:16.500169 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 00:39:16.503218 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 00:39:16.510269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 00:39:16.513756 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 00:39:16.516645 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8879 00:39:16.523497 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 00:39:16.526878 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 00:39:16.529837 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 00:39:16.536373 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 00:39:16.539755 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 00:39:16.543030 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 00:39:16.549474 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 00:39:16.552837 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 00:39:16.556222 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 00:39:16.562529 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 00:39:16.565914 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 00:39:16.569175 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 00:39:16.575851 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 00:39:16.579010 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 00:39:16.585723 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8894 00:39:16.589383 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8895 00:39:16.592330 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 00:39:16.595674 Total UI for P1: 0, mck2ui 16
8897 00:39:16.598993 best dqsien dly found for B0: ( 1, 9, 10)
8898 00:39:16.602720 Total UI for P1: 0, mck2ui 16
8899 00:39:16.605469 best dqsien dly found for B1: ( 1, 9, 10)
8900 00:39:16.609000 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8901 00:39:16.612460 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8902 00:39:16.612560
8903 00:39:16.615635 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8904 00:39:16.621907 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8905 00:39:16.622013 [Gating] SW calibration Done
8906 00:39:16.625537 ==
8907 00:39:16.625639 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 00:39:16.632147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 00:39:16.632248 ==
8910 00:39:16.632340 RX Vref Scan: 0
8911 00:39:16.632426
8912 00:39:16.635231 RX Vref 0 -> 0, step: 1
8913 00:39:16.635327
8914 00:39:16.639177 RX Delay 0 -> 252, step: 8
8915 00:39:16.641863 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8916 00:39:16.645156 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8917 00:39:16.648769 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8918 00:39:16.655322 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8919 00:39:16.658346 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8920 00:39:16.661384 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8921 00:39:16.664966 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8922 00:39:16.667984 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8923 00:39:16.674536 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8924 00:39:16.678000 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8925 00:39:16.681353 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8926 00:39:16.684582 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8927 00:39:16.691501 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8928 00:39:16.694574 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8929 00:39:16.698409 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8930 00:39:16.701215 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8931 00:39:16.701319 ==
8932 00:39:16.704445 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 00:39:16.711517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 00:39:16.711627 ==
8935 00:39:16.711719 DQS Delay:
8936 00:39:16.711815 DQS0 = 0, DQS1 = 0
8937 00:39:16.714580 DQM Delay:
8938 00:39:16.714685 DQM0 = 136, DQM1 = 129
8939 00:39:16.717539 DQ Delay:
8940 00:39:16.721113 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8941 00:39:16.724801 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8942 00:39:16.727612 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8943 00:39:16.730909 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8944 00:39:16.731011
8945 00:39:16.731103
8946 00:39:16.731190 ==
8947 00:39:16.733962 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 00:39:16.737724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 00:39:16.740544 ==
8950 00:39:16.740640
8951 00:39:16.740728
8952 00:39:16.740820 TX Vref Scan disable
8953 00:39:16.744056 == TX Byte 0 ==
8954 00:39:16.747101 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8955 00:39:16.750567 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8956 00:39:16.753950 == TX Byte 1 ==
8957 00:39:16.757026 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8958 00:39:16.763906 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8959 00:39:16.764012 ==
8960 00:39:16.766954 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 00:39:16.770120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 00:39:16.770259 ==
8963 00:39:16.782988
8964 00:39:16.786862 TX Vref early break, caculate TX vref
8965 00:39:16.789539 TX Vref=16, minBit 0, minWin=23, winSum=388
8966 00:39:16.792646 TX Vref=18, minBit 0, minWin=24, winSum=398
8967 00:39:16.795710 TX Vref=20, minBit 0, minWin=24, winSum=405
8968 00:39:16.799024 TX Vref=22, minBit 0, minWin=24, winSum=410
8969 00:39:16.802519 TX Vref=24, minBit 1, minWin=25, winSum=418
8970 00:39:16.809081 TX Vref=26, minBit 0, minWin=25, winSum=426
8971 00:39:16.812132 TX Vref=28, minBit 0, minWin=26, winSum=422
8972 00:39:16.815352 TX Vref=30, minBit 0, minWin=24, winSum=413
8973 00:39:16.818684 TX Vref=32, minBit 0, minWin=24, winSum=408
8974 00:39:16.822665 TX Vref=34, minBit 0, minWin=23, winSum=397
8975 00:39:16.828682 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
8976 00:39:16.828790
8977 00:39:16.832105 Final TX Range 0 Vref 28
8978 00:39:16.832215
8979 00:39:16.832306 ==
8980 00:39:16.835462 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 00:39:16.838691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 00:39:16.838776 ==
8983 00:39:16.838846
8984 00:39:16.838948
8985 00:39:16.841770 TX Vref Scan disable
8986 00:39:16.848648 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8987 00:39:16.848753 == TX Byte 0 ==
8988 00:39:16.851736 u2DelayCellOfst[0]=22 cells (6 PI)
8989 00:39:16.855325 u2DelayCellOfst[1]=11 cells (3 PI)
8990 00:39:16.858453 u2DelayCellOfst[2]=0 cells (0 PI)
8991 00:39:16.862038 u2DelayCellOfst[3]=3 cells (1 PI)
8992 00:39:16.864899 u2DelayCellOfst[4]=7 cells (2 PI)
8993 00:39:16.868090 u2DelayCellOfst[5]=22 cells (6 PI)
8994 00:39:16.871780 u2DelayCellOfst[6]=18 cells (5 PI)
8995 00:39:16.874830 u2DelayCellOfst[7]=3 cells (1 PI)
8996 00:39:16.877890 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8997 00:39:16.881549 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8998 00:39:16.884882 == TX Byte 1 ==
8999 00:39:16.887940 u2DelayCellOfst[8]=0 cells (0 PI)
9000 00:39:16.891016 u2DelayCellOfst[9]=3 cells (1 PI)
9001 00:39:16.894588 u2DelayCellOfst[10]=14 cells (4 PI)
9002 00:39:16.894697 u2DelayCellOfst[11]=7 cells (2 PI)
9003 00:39:16.898047 u2DelayCellOfst[12]=18 cells (5 PI)
9004 00:39:16.900904 u2DelayCellOfst[13]=18 cells (5 PI)
9005 00:39:16.904547 u2DelayCellOfst[14]=18 cells (5 PI)
9006 00:39:16.907946 u2DelayCellOfst[15]=18 cells (5 PI)
9007 00:39:16.914118 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9008 00:39:16.917462 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9009 00:39:16.917564 DramC Write-DBI on
9010 00:39:16.920674 ==
9011 00:39:16.924158 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 00:39:16.927206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 00:39:16.927307 ==
9014 00:39:16.927405
9015 00:39:16.927491
9016 00:39:16.930976 TX Vref Scan disable
9017 00:39:16.931074 == TX Byte 0 ==
9018 00:39:16.937206 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9019 00:39:16.937285 == TX Byte 1 ==
9020 00:39:16.940801 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9021 00:39:16.943650 DramC Write-DBI off
9022 00:39:16.943744
9023 00:39:16.943833 [DATLAT]
9024 00:39:16.946753 Freq=1600, CH1 RK1
9025 00:39:16.946850
9026 00:39:16.946953 DATLAT Default: 0xf
9027 00:39:16.950109 0, 0xFFFF, sum = 0
9028 00:39:16.950223 1, 0xFFFF, sum = 0
9029 00:39:16.953492 2, 0xFFFF, sum = 0
9030 00:39:16.953587 3, 0xFFFF, sum = 0
9031 00:39:16.956817 4, 0xFFFF, sum = 0
9032 00:39:16.960628 5, 0xFFFF, sum = 0
9033 00:39:16.960726 6, 0xFFFF, sum = 0
9034 00:39:16.963336 7, 0xFFFF, sum = 0
9035 00:39:16.963460 8, 0xFFFF, sum = 0
9036 00:39:16.966733 9, 0xFFFF, sum = 0
9037 00:39:16.966803 10, 0xFFFF, sum = 0
9038 00:39:16.969974 11, 0xFFFF, sum = 0
9039 00:39:16.970089 12, 0xFFFF, sum = 0
9040 00:39:16.973093 13, 0xFFFF, sum = 0
9041 00:39:16.973163 14, 0x0, sum = 1
9042 00:39:16.976554 15, 0x0, sum = 2
9043 00:39:16.976656 16, 0x0, sum = 3
9044 00:39:16.979815 17, 0x0, sum = 4
9045 00:39:16.979921 best_step = 15
9046 00:39:16.980008
9047 00:39:16.980098 ==
9048 00:39:16.983417 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 00:39:16.989826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 00:39:16.989933 ==
9051 00:39:16.990023 RX Vref Scan: 0
9052 00:39:16.990115
9053 00:39:16.993183 RX Vref 0 -> 0, step: 1
9054 00:39:16.993280
9055 00:39:16.996348 RX Delay 11 -> 252, step: 4
9056 00:39:16.999767 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9057 00:39:17.002832 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9058 00:39:17.006491 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9059 00:39:17.013256 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9060 00:39:17.015964 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9061 00:39:17.019775 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9062 00:39:17.023064 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9063 00:39:17.026003 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9064 00:39:17.032850 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9065 00:39:17.036053 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9066 00:39:17.039845 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9067 00:39:17.043190 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9068 00:39:17.046202 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9069 00:39:17.052557 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9070 00:39:17.056142 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9071 00:39:17.059675 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9072 00:39:17.059782 ==
9073 00:39:17.062488 Dram Type= 6, Freq= 0, CH_1, rank 1
9074 00:39:17.065823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9075 00:39:17.069243 ==
9076 00:39:17.069339 DQS Delay:
9077 00:39:17.069428 DQS0 = 0, DQS1 = 0
9078 00:39:17.072579 DQM Delay:
9079 00:39:17.072673 DQM0 = 133, DQM1 = 126
9080 00:39:17.075690 DQ Delay:
9081 00:39:17.078739 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =130
9082 00:39:17.082526 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9083 00:39:17.085312 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9084 00:39:17.089066 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =138
9085 00:39:17.089162
9086 00:39:17.089260
9087 00:39:17.089347
9088 00:39:17.091969 [DramC_TX_OE_Calibration] TA2
9089 00:39:17.095218 Original DQ_B0 (3 6) =30, OEN = 27
9090 00:39:17.098764 Original DQ_B1 (3 6) =30, OEN = 27
9091 00:39:17.102350 24, 0x0, End_B0=24 End_B1=24
9092 00:39:17.102436 25, 0x0, End_B0=25 End_B1=25
9093 00:39:17.105527 26, 0x0, End_B0=26 End_B1=26
9094 00:39:17.108528 27, 0x0, End_B0=27 End_B1=27
9095 00:39:17.112009 28, 0x0, End_B0=28 End_B1=28
9096 00:39:17.115338 29, 0x0, End_B0=29 End_B1=29
9097 00:39:17.115452 30, 0x0, End_B0=30 End_B1=30
9098 00:39:17.118468 31, 0x4141, End_B0=30 End_B1=30
9099 00:39:17.121732 Byte0 end_step=30 best_step=27
9100 00:39:17.125036 Byte1 end_step=30 best_step=27
9101 00:39:17.128167 Byte0 TX OE(2T, 0.5T) = (3, 3)
9102 00:39:17.131680 Byte1 TX OE(2T, 0.5T) = (3, 3)
9103 00:39:17.131766
9104 00:39:17.131835
9105 00:39:17.137865 [DQSOSCAuto] RK1, (LSB)MR18= 0xb08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
9106 00:39:17.141336 CH1 RK1: MR19=303, MR18=B08
9107 00:39:17.147878 CH1_RK1: MR19=0x303, MR18=0xB08, DQSOSC=404, MR23=63, INC=22, DEC=15
9108 00:39:17.151332 [RxdqsGatingPostProcess] freq 1600
9109 00:39:17.154347 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9110 00:39:17.157880 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 00:39:17.161161 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 00:39:17.164701 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 00:39:17.168352 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 00:39:17.171196 best DQS0 dly(2T, 0.5T) = (1, 1)
9115 00:39:17.174317 best DQS1 dly(2T, 0.5T) = (1, 1)
9116 00:39:17.177951 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9117 00:39:17.181487 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9118 00:39:17.184277 Pre-setting of DQS Precalculation
9119 00:39:17.187429 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9120 00:39:17.194408 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9121 00:39:17.204119 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 00:39:17.204219
9123 00:39:17.204316
9124 00:39:17.207533 [Calibration Summary] 3200 Mbps
9125 00:39:17.207615 CH 0, Rank 0
9126 00:39:17.210762 SW Impedance : PASS
9127 00:39:17.210839 DUTY Scan : NO K
9128 00:39:17.214049 ZQ Calibration : PASS
9129 00:39:17.217537 Jitter Meter : NO K
9130 00:39:17.217641 CBT Training : PASS
9131 00:39:17.220685 Write leveling : PASS
9132 00:39:17.223986 RX DQS gating : PASS
9133 00:39:17.224084 RX DQ/DQS(RDDQC) : PASS
9134 00:39:17.227164 TX DQ/DQS : PASS
9135 00:39:17.230546 RX DATLAT : PASS
9136 00:39:17.230640 RX DQ/DQS(Engine): PASS
9137 00:39:17.233783 TX OE : PASS
9138 00:39:17.233896 All Pass.
9139 00:39:17.234018
9140 00:39:17.237697 CH 0, Rank 1
9141 00:39:17.237796 SW Impedance : PASS
9142 00:39:17.240293 DUTY Scan : NO K
9143 00:39:17.240398 ZQ Calibration : PASS
9144 00:39:17.243850 Jitter Meter : NO K
9145 00:39:17.247344 CBT Training : PASS
9146 00:39:17.247445 Write leveling : PASS
9147 00:39:17.250216 RX DQS gating : PASS
9148 00:39:17.253706 RX DQ/DQS(RDDQC) : PASS
9149 00:39:17.253818 TX DQ/DQS : PASS
9150 00:39:17.257416 RX DATLAT : PASS
9151 00:39:17.260639 RX DQ/DQS(Engine): PASS
9152 00:39:17.260710 TX OE : PASS
9153 00:39:17.263679 All Pass.
9154 00:39:17.263776
9155 00:39:17.263863 CH 1, Rank 0
9156 00:39:17.266694 SW Impedance : PASS
9157 00:39:17.266765 DUTY Scan : NO K
9158 00:39:17.269942 ZQ Calibration : PASS
9159 00:39:17.273337 Jitter Meter : NO K
9160 00:39:17.273439 CBT Training : PASS
9161 00:39:17.276280 Write leveling : PASS
9162 00:39:17.279838 RX DQS gating : PASS
9163 00:39:17.279932 RX DQ/DQS(RDDQC) : PASS
9164 00:39:17.283320 TX DQ/DQS : PASS
9165 00:39:17.286407 RX DATLAT : PASS
9166 00:39:17.286483 RX DQ/DQS(Engine): PASS
9167 00:39:17.289855 TX OE : PASS
9168 00:39:17.289933 All Pass.
9169 00:39:17.289994
9170 00:39:17.293228 CH 1, Rank 1
9171 00:39:17.293297 SW Impedance : PASS
9172 00:39:17.296326 DUTY Scan : NO K
9173 00:39:17.299770 ZQ Calibration : PASS
9174 00:39:17.299841 Jitter Meter : NO K
9175 00:39:17.302902 CBT Training : PASS
9176 00:39:17.306070 Write leveling : PASS
9177 00:39:17.306151 RX DQS gating : PASS
9178 00:39:17.309707 RX DQ/DQS(RDDQC) : PASS
9179 00:39:17.309779 TX DQ/DQS : PASS
9180 00:39:17.313130 RX DATLAT : PASS
9181 00:39:17.316014 RX DQ/DQS(Engine): PASS
9182 00:39:17.316086 TX OE : PASS
9183 00:39:17.319491 All Pass.
9184 00:39:17.319565
9185 00:39:17.319631 DramC Write-DBI on
9186 00:39:17.322647 PER_BANK_REFRESH: Hybrid Mode
9187 00:39:17.325860 TX_TRACKING: ON
9188 00:39:17.332907 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9189 00:39:17.342483 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9190 00:39:17.349081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9191 00:39:17.352616 [FAST_K] Save calibration result to emmc
9192 00:39:17.355544 sync common calibartion params.
9193 00:39:17.355624 sync cbt_mode0:1, 1:1
9194 00:39:17.359189 dram_init: ddr_geometry: 2
9195 00:39:17.362496 dram_init: ddr_geometry: 2
9196 00:39:17.365936 dram_init: ddr_geometry: 2
9197 00:39:17.366009 0:dram_rank_size:100000000
9198 00:39:17.369022 1:dram_rank_size:100000000
9199 00:39:17.375692 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9200 00:39:17.375775 DFS_SHUFFLE_HW_MODE: ON
9201 00:39:17.382270 dramc_set_vcore_voltage set vcore to 725000
9202 00:39:17.382346 Read voltage for 1600, 0
9203 00:39:17.385348 Vio18 = 0
9204 00:39:17.385422 Vcore = 725000
9205 00:39:17.385483 Vdram = 0
9206 00:39:17.389097 Vddq = 0
9207 00:39:17.389170 Vmddr = 0
9208 00:39:17.392023 switch to 3200 Mbps bootup
9209 00:39:17.392099 [DramcRunTimeConfig]
9210 00:39:17.392160 PHYPLL
9211 00:39:17.395877 DPM_CONTROL_AFTERK: ON
9212 00:39:17.398810 PER_BANK_REFRESH: ON
9213 00:39:17.398883 REFRESH_OVERHEAD_REDUCTION: ON
9214 00:39:17.402289 CMD_PICG_NEW_MODE: OFF
9215 00:39:17.405934 XRTWTW_NEW_MODE: ON
9216 00:39:17.406011 XRTRTR_NEW_MODE: ON
9217 00:39:17.408927 TX_TRACKING: ON
9218 00:39:17.409001 RDSEL_TRACKING: OFF
9219 00:39:17.412300 DQS Precalculation for DVFS: ON
9220 00:39:17.412372 RX_TRACKING: OFF
9221 00:39:17.415105 HW_GATING DBG: ON
9222 00:39:17.415176 ZQCS_ENABLE_LP4: ON
9223 00:39:17.418550 RX_PICG_NEW_MODE: ON
9224 00:39:17.421925 TX_PICG_NEW_MODE: ON
9225 00:39:17.422021 ENABLE_RX_DCM_DPHY: ON
9226 00:39:17.425187 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9227 00:39:17.428423 DUMMY_READ_FOR_TRACKING: OFF
9228 00:39:17.431681 !!! SPM_CONTROL_AFTERK: OFF
9229 00:39:17.434923 !!! SPM could not control APHY
9230 00:39:17.434993 IMPEDANCE_TRACKING: ON
9231 00:39:17.438792 TEMP_SENSOR: ON
9232 00:39:17.438861 HW_SAVE_FOR_SR: OFF
9233 00:39:17.441845 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9234 00:39:17.444827 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9235 00:39:17.448700 Read ODT Tracking: ON
9236 00:39:17.451505 Refresh Rate DeBounce: ON
9237 00:39:17.451579 DFS_NO_QUEUE_FLUSH: ON
9238 00:39:17.454992 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9239 00:39:17.457969 ENABLE_DFS_RUNTIME_MRW: OFF
9240 00:39:17.461319 DDR_RESERVE_NEW_MODE: ON
9241 00:39:17.461396 MR_CBT_SWITCH_FREQ: ON
9242 00:39:17.464444 =========================
9243 00:39:17.483376 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9244 00:39:17.486418 dram_init: ddr_geometry: 2
9245 00:39:17.504542 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9246 00:39:17.507733 dram_init: dram init end (result: 0)
9247 00:39:17.514324 DRAM-K: Full calibration passed in 24580 msecs
9248 00:39:17.517732 MRC: failed to locate region type 0.
9249 00:39:17.517819 DRAM rank0 size:0x100000000,
9250 00:39:17.520817 DRAM rank1 size=0x100000000
9251 00:39:17.530820 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9252 00:39:17.537468 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9253 00:39:17.547216 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9254 00:39:17.553926 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9255 00:39:17.554003 DRAM rank0 size:0x100000000,
9256 00:39:17.556977 DRAM rank1 size=0x100000000
9257 00:39:17.557051 CBMEM:
9258 00:39:17.560384 IMD: root @ 0xfffff000 254 entries.
9259 00:39:17.563812 IMD: root @ 0xffffec00 62 entries.
9260 00:39:17.570760 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9261 00:39:17.573865 WARNING: RO_VPD is uninitialized or empty.
9262 00:39:17.576876 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9263 00:39:17.584627 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9264 00:39:17.597567 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9265 00:39:17.608809 BS: romstage times (exec / console): total (unknown) / 24079 ms
9266 00:39:17.608895
9267 00:39:17.608960
9268 00:39:17.618764 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9269 00:39:17.622092 ARM64: Exception handlers installed.
9270 00:39:17.625479 ARM64: Testing exception
9271 00:39:17.628462 ARM64: Done test exception
9272 00:39:17.628535 Enumerating buses...
9273 00:39:17.632176 Show all devs... Before device enumeration.
9274 00:39:17.635395 Root Device: enabled 1
9275 00:39:17.638144 CPU_CLUSTER: 0: enabled 1
9276 00:39:17.638256 CPU: 00: enabled 1
9277 00:39:17.642138 Compare with tree...
9278 00:39:17.642253 Root Device: enabled 1
9279 00:39:17.645175 CPU_CLUSTER: 0: enabled 1
9280 00:39:17.648734 CPU: 00: enabled 1
9281 00:39:17.648808 Root Device scanning...
9282 00:39:17.651825 scan_static_bus for Root Device
9283 00:39:17.655140 CPU_CLUSTER: 0 enabled
9284 00:39:17.658758 scan_static_bus for Root Device done
9285 00:39:17.661654 scan_bus: bus Root Device finished in 8 msecs
9286 00:39:17.661727 done
9287 00:39:17.668186 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9288 00:39:17.671543 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9289 00:39:17.677877 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9290 00:39:17.684849 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9291 00:39:17.684926 Allocating resources...
9292 00:39:17.688002 Reading resources...
9293 00:39:17.691183 Root Device read_resources bus 0 link: 0
9294 00:39:17.694595 DRAM rank0 size:0x100000000,
9295 00:39:17.694669 DRAM rank1 size=0x100000000
9296 00:39:17.701002 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9297 00:39:17.701099 CPU: 00 missing read_resources
9298 00:39:17.707928 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9299 00:39:17.711223 Root Device read_resources bus 0 link: 0 done
9300 00:39:17.714437 Done reading resources.
9301 00:39:17.718147 Show resources in subtree (Root Device)...After reading.
9302 00:39:17.720839 Root Device child on link 0 CPU_CLUSTER: 0
9303 00:39:17.724200 CPU_CLUSTER: 0 child on link 0 CPU: 00
9304 00:39:17.734100 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9305 00:39:17.734234 CPU: 00
9306 00:39:17.740607 Root Device assign_resources, bus 0 link: 0
9307 00:39:17.744175 CPU_CLUSTER: 0 missing set_resources
9308 00:39:17.747364 Root Device assign_resources, bus 0 link: 0 done
9309 00:39:17.747444 Done setting resources.
9310 00:39:17.753980 Show resources in subtree (Root Device)...After assigning values.
9311 00:39:17.757451 Root Device child on link 0 CPU_CLUSTER: 0
9312 00:39:17.763842 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 00:39:17.770514 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 00:39:17.770592 CPU: 00
9315 00:39:17.773802 Done allocating resources.
9316 00:39:17.780247 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9317 00:39:17.780330 Enabling resources...
9318 00:39:17.783699 done.
9319 00:39:17.786635 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9320 00:39:17.789971 Initializing devices...
9321 00:39:17.790049 Root Device init
9322 00:39:17.793281 init hardware done!
9323 00:39:17.793354 0x00000018: ctrlr->caps
9324 00:39:17.796551 52.000 MHz: ctrlr->f_max
9325 00:39:17.799858 0.400 MHz: ctrlr->f_min
9326 00:39:17.799936 0x40ff8080: ctrlr->voltages
9327 00:39:17.803288 sclk: 390625
9328 00:39:17.803361 Bus Width = 1
9329 00:39:17.806606 sclk: 390625
9330 00:39:17.806683 Bus Width = 1
9331 00:39:17.809676 Early init status = 3
9332 00:39:17.813024 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9333 00:39:17.816723 in-header: 03 fc 00 00 01 00 00 00
9334 00:39:17.819668 in-data: 00
9335 00:39:17.822856 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9336 00:39:17.827922 in-header: 03 fd 00 00 00 00 00 00
9337 00:39:17.831210 in-data:
9338 00:39:17.834435 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9339 00:39:17.838736 in-header: 03 fc 00 00 01 00 00 00
9340 00:39:17.842122 in-data: 00
9341 00:39:17.845311 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9342 00:39:17.851220 in-header: 03 fd 00 00 00 00 00 00
9343 00:39:17.854595 in-data:
9344 00:39:17.857898 [SSUSB] Setting up USB HOST controller...
9345 00:39:17.860772 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9346 00:39:17.864524 [SSUSB] phy power-on done.
9347 00:39:17.867762 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9348 00:39:17.874195 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9349 00:39:17.877310 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9350 00:39:17.883890 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9351 00:39:17.890570 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9352 00:39:17.897142 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9353 00:39:17.903719 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9354 00:39:17.910638 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9355 00:39:17.913735 SPM: binary array size = 0x9dc
9356 00:39:17.916866 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9357 00:39:17.923560 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9358 00:39:17.930103 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9359 00:39:17.937109 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9360 00:39:17.940256 configure_display: Starting display init
9361 00:39:17.974302 anx7625_power_on_init: Init interface.
9362 00:39:17.977786 anx7625_disable_pd_protocol: Disabled PD feature.
9363 00:39:17.980765 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9364 00:39:18.008425 anx7625_start_dp_work: Secure OCM version=00
9365 00:39:18.011971 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9366 00:39:18.026875 sp_tx_get_edid_block: EDID Block = 1
9367 00:39:18.129193 Extracted contents:
9368 00:39:18.132468 header: 00 ff ff ff ff ff ff 00
9369 00:39:18.136077 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9370 00:39:18.139104 version: 01 04
9371 00:39:18.142386 basic params: 95 1f 11 78 0a
9372 00:39:18.145994 chroma info: 76 90 94 55 54 90 27 21 50 54
9373 00:39:18.148893 established: 00 00 00
9374 00:39:18.155726 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9375 00:39:18.159025 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9376 00:39:18.165649 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 00:39:18.172102 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9378 00:39:18.179255 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9379 00:39:18.182042 extensions: 00
9380 00:39:18.182126 checksum: fb
9381 00:39:18.182228
9382 00:39:18.188548 Manufacturer: IVO Model 57d Serial Number 0
9383 00:39:18.188630 Made week 0 of 2020
9384 00:39:18.191976 EDID version: 1.4
9385 00:39:18.192050 Digital display
9386 00:39:18.195034 6 bits per primary color channel
9387 00:39:18.195117 DisplayPort interface
9388 00:39:18.198394 Maximum image size: 31 cm x 17 cm
9389 00:39:18.201595 Gamma: 220%
9390 00:39:18.201674 Check DPMS levels
9391 00:39:18.208396 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9392 00:39:18.211534 First detailed timing is preferred timing
9393 00:39:18.211646 Established timings supported:
9394 00:39:18.215212 Standard timings supported:
9395 00:39:18.218699 Detailed timings
9396 00:39:18.221730 Hex of detail: 383680a07038204018303c0035ae10000019
9397 00:39:18.228058 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9398 00:39:18.231629 0780 0798 07c8 0820 hborder 0
9399 00:39:18.234644 0438 043b 0447 0458 vborder 0
9400 00:39:18.238133 -hsync -vsync
9401 00:39:18.238259 Did detailed timing
9402 00:39:18.244705 Hex of detail: 000000000000000000000000000000000000
9403 00:39:18.247917 Manufacturer-specified data, tag 0
9404 00:39:18.251341 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9405 00:39:18.254607 ASCII string: InfoVision
9406 00:39:18.257773 Hex of detail: 000000fe00523134304e574635205248200a
9407 00:39:18.261191 ASCII string: R140NWF5 RH
9408 00:39:18.261310 Checksum
9409 00:39:18.264004 Checksum: 0xfb (valid)
9410 00:39:18.267935 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9411 00:39:18.271053 DSI data_rate: 832800000 bps
9412 00:39:18.277889 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9413 00:39:18.280939 anx7625_parse_edid: pixelclock(138800).
9414 00:39:18.284698 hactive(1920), hsync(48), hfp(24), hbp(88)
9415 00:39:18.287458 vactive(1080), vsync(12), vfp(3), vbp(17)
9416 00:39:18.290787 anx7625_dsi_config: config dsi.
9417 00:39:18.297164 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9418 00:39:18.311517 anx7625_dsi_config: success to config DSI
9419 00:39:18.314826 anx7625_dp_start: MIPI phy setup OK.
9420 00:39:18.317818 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9421 00:39:18.321092 mtk_ddp_mode_set invalid vrefresh 60
9422 00:39:18.324409 main_disp_path_setup
9423 00:39:18.324486 ovl_layer_smi_id_en
9424 00:39:18.327886 ovl_layer_smi_id_en
9425 00:39:18.327959 ccorr_config
9426 00:39:18.328019 aal_config
9427 00:39:18.331063 gamma_config
9428 00:39:18.331146 postmask_config
9429 00:39:18.334341 dither_config
9430 00:39:18.337869 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9431 00:39:18.344577 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9432 00:39:18.347644 Root Device init finished in 553 msecs
9433 00:39:18.351171 CPU_CLUSTER: 0 init
9434 00:39:18.357624 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9435 00:39:18.363888 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9436 00:39:18.363969 APU_MBOX 0x190000b0 = 0x10001
9437 00:39:18.367634 APU_MBOX 0x190001b0 = 0x10001
9438 00:39:18.370537 APU_MBOX 0x190005b0 = 0x10001
9439 00:39:18.373680 APU_MBOX 0x190006b0 = 0x10001
9440 00:39:18.380765 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9441 00:39:18.390366 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9442 00:39:18.402746 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9443 00:39:18.408895 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9444 00:39:18.420942 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9445 00:39:18.430050 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9446 00:39:18.433322 CPU_CLUSTER: 0 init finished in 81 msecs
9447 00:39:18.436734 Devices initialized
9448 00:39:18.439834 Show all devs... After init.
9449 00:39:18.439915 Root Device: enabled 1
9450 00:39:18.443180 CPU_CLUSTER: 0: enabled 1
9451 00:39:18.446449 CPU: 00: enabled 1
9452 00:39:18.449863 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9453 00:39:18.453517 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9454 00:39:18.456397 ELOG: NV offset 0x57f000 size 0x1000
9455 00:39:18.463368 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9456 00:39:18.469529 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9457 00:39:18.472662 ELOG: Event(17) added with size 13 at 2024-06-05 00:39:18 UTC
9458 00:39:18.479726 out: cmd=0x121: 03 db 21 01 00 00 00 00
9459 00:39:18.482788 in-header: 03 68 00 00 2c 00 00 00
9460 00:39:18.496171 in-data: d5 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9461 00:39:18.499283 ELOG: Event(A1) added with size 10 at 2024-06-05 00:39:18 UTC
9462 00:39:18.506268 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9463 00:39:18.512676 ELOG: Event(A0) added with size 9 at 2024-06-05 00:39:18 UTC
9464 00:39:18.516213 elog_add_boot_reason: Logged dev mode boot
9465 00:39:18.522259 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9466 00:39:18.522359 Finalize devices...
9467 00:39:18.525561 Devices finalized
9468 00:39:18.529466 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9469 00:39:18.532461 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9470 00:39:18.535894 in-header: 03 07 00 00 08 00 00 00
9471 00:39:18.538881 in-data: aa e4 47 04 13 02 00 00
9472 00:39:18.542147 Chrome EC: UHEPI supported
9473 00:39:18.549300 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9474 00:39:18.552471 in-header: 03 a9 00 00 08 00 00 00
9475 00:39:18.556063 in-data: 84 60 60 08 00 00 00 00
9476 00:39:18.562048 ELOG: Event(91) added with size 10 at 2024-06-05 00:39:18 UTC
9477 00:39:18.565321 Chrome EC: clear events_b mask to 0x0000000020004000
9478 00:39:18.571992 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9479 00:39:18.575066 in-header: 03 fd 00 00 00 00 00 00
9480 00:39:18.578440 in-data:
9481 00:39:18.582247 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9482 00:39:18.585038 Writing coreboot table at 0xffe64000
9483 00:39:18.592171 0. 000000000010a000-0000000000113fff: RAMSTAGE
9484 00:39:18.595301 1. 0000000040000000-00000000400fffff: RAM
9485 00:39:18.598105 2. 0000000040100000-000000004032afff: RAMSTAGE
9486 00:39:18.601874 3. 000000004032b000-00000000545fffff: RAM
9487 00:39:18.605204 4. 0000000054600000-000000005465ffff: BL31
9488 00:39:18.611959 5. 0000000054660000-00000000ffe63fff: RAM
9489 00:39:18.614722 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9490 00:39:18.617903 7. 0000000100000000-000000023fffffff: RAM
9491 00:39:18.621223 Passing 5 GPIOs to payload:
9492 00:39:18.624691 NAME | PORT | POLARITY | VALUE
9493 00:39:18.631070 EC in RW | 0x000000aa | low | undefined
9494 00:39:18.634287 EC interrupt | 0x00000005 | low | undefined
9495 00:39:18.641386 TPM interrupt | 0x000000ab | high | undefined
9496 00:39:18.644566 SD card detect | 0x00000011 | high | undefined
9497 00:39:18.651170 speaker enable | 0x00000093 | high | undefined
9498 00:39:18.654301 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9499 00:39:18.657632 in-header: 03 f9 00 00 02 00 00 00
9500 00:39:18.657715 in-data: 02 00
9501 00:39:18.660755 ADC[4]: Raw value=901922 ID=7
9502 00:39:18.664261 ADC[3]: Raw value=212912 ID=1
9503 00:39:18.667843 RAM Code: 0x71
9504 00:39:18.667950 ADC[6]: Raw value=75036 ID=0
9505 00:39:18.670880 ADC[5]: Raw value=213652 ID=1
9506 00:39:18.673929 SKU Code: 0x1
9507 00:39:18.677202 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cb6c
9508 00:39:18.680656 coreboot table: 964 bytes.
9509 00:39:18.684605 IMD ROOT 0. 0xfffff000 0x00001000
9510 00:39:18.687312 IMD SMALL 1. 0xffffe000 0x00001000
9511 00:39:18.690952 RO MCACHE 2. 0xffffc000 0x00001104
9512 00:39:18.693913 CONSOLE 3. 0xfff7c000 0x00080000
9513 00:39:18.697220 FMAP 4. 0xfff7b000 0x00000452
9514 00:39:18.700833 TIME STAMP 5. 0xfff7a000 0x00000910
9515 00:39:18.703467 VBOOT WORK 6. 0xfff66000 0x00014000
9516 00:39:18.707022 RAMOOPS 7. 0xffe66000 0x00100000
9517 00:39:18.710204 COREBOOT 8. 0xffe64000 0x00002000
9518 00:39:18.710305 IMD small region:
9519 00:39:18.713745 IMD ROOT 0. 0xffffec00 0x00000400
9520 00:39:18.720164 VPD 1. 0xffffeb80 0x0000006c
9521 00:39:18.723523 MMC STATUS 2. 0xffffeb60 0x00000004
9522 00:39:18.727159 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9523 00:39:18.733231 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9524 00:39:18.773790 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9525 00:39:18.776950 Checking segment from ROM address 0x40100000
9526 00:39:18.780132 Checking segment from ROM address 0x4010001c
9527 00:39:18.786694 Loading segment from ROM address 0x40100000
9528 00:39:18.786780 code (compression=0)
9529 00:39:18.796368 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9530 00:39:18.803133 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9531 00:39:18.806735 it's not compressed!
9532 00:39:18.809682 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9533 00:39:18.816390 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9534 00:39:18.833767 Loading segment from ROM address 0x4010001c
9535 00:39:18.833850 Entry Point 0x80000000
9536 00:39:18.837165 Loaded segments
9537 00:39:18.840474 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9538 00:39:18.847071 Jumping to boot code at 0x80000000(0xffe64000)
9539 00:39:18.853636 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9540 00:39:18.860535 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9541 00:39:18.868481 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9542 00:39:18.872369 Checking segment from ROM address 0x40100000
9543 00:39:18.875002 Checking segment from ROM address 0x4010001c
9544 00:39:18.881939 Loading segment from ROM address 0x40100000
9545 00:39:18.882022 code (compression=1)
9546 00:39:18.888034 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9547 00:39:18.898063 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9548 00:39:18.898150 using LZMA
9549 00:39:18.907481 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9550 00:39:18.913517 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9551 00:39:18.917137 Loading segment from ROM address 0x4010001c
9552 00:39:18.920362 Entry Point 0x54601000
9553 00:39:18.920447 Loaded segments
9554 00:39:18.923405 NOTICE: MT8192 bl31_setup
9555 00:39:18.930299 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9556 00:39:18.934062 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9557 00:39:18.936858 WARNING: region 0:
9558 00:39:18.940654 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 00:39:18.940738 WARNING: region 1:
9560 00:39:18.947140 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9561 00:39:18.950172 WARNING: region 2:
9562 00:39:18.953814 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9563 00:39:18.956906 WARNING: region 3:
9564 00:39:18.960201 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9565 00:39:18.963350 WARNING: region 4:
9566 00:39:18.969979 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9567 00:39:18.970087 WARNING: region 5:
9568 00:39:18.973082 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9569 00:39:18.976574 WARNING: region 6:
9570 00:39:18.980100 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9571 00:39:18.983548 WARNING: region 7:
9572 00:39:18.986415 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9573 00:39:18.993209 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9574 00:39:18.996246 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9575 00:39:19.002868 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9576 00:39:19.006109 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9577 00:39:19.009548 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9578 00:39:19.016232 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9579 00:39:19.019900 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9580 00:39:19.023132 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9581 00:39:19.029321 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9582 00:39:19.032940 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9583 00:39:19.039963 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9584 00:39:19.042827 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9585 00:39:19.045957 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9586 00:39:19.052656 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9587 00:39:19.056254 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9588 00:39:19.059210 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9589 00:39:19.066299 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9590 00:39:19.069009 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9591 00:39:19.075599 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9592 00:39:19.079292 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9593 00:39:19.082529 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9594 00:39:19.088707 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9595 00:39:19.092017 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9596 00:39:19.098828 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9597 00:39:19.102127 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9598 00:39:19.105164 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9599 00:39:19.112132 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9600 00:39:19.115632 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9601 00:39:19.122104 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9602 00:39:19.125291 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9603 00:39:19.132032 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9604 00:39:19.135305 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9605 00:39:19.138834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9606 00:39:19.141952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9607 00:39:19.148588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9608 00:39:19.151757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9609 00:39:19.155071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9610 00:39:19.158330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9611 00:39:19.165026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9612 00:39:19.168586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9613 00:39:19.171615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9614 00:39:19.175324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9615 00:39:19.181315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9616 00:39:19.185085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9617 00:39:19.188320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9618 00:39:19.191385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9619 00:39:19.198009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9620 00:39:19.201133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9621 00:39:19.204525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9622 00:39:19.211082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9623 00:39:19.214827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9624 00:39:19.221163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9625 00:39:19.224404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9626 00:39:19.231052 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9627 00:39:19.234297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9628 00:39:19.237887 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9629 00:39:19.244372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9630 00:39:19.247779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9631 00:39:19.254205 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9632 00:39:19.257929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9633 00:39:19.264546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9634 00:39:19.268269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9635 00:39:19.274067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9636 00:39:19.277357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9637 00:39:19.284028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9638 00:39:19.287363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9639 00:39:19.290556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9640 00:39:19.297316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9641 00:39:19.300468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9642 00:39:19.307272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9643 00:39:19.310521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9644 00:39:19.317409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9645 00:39:19.320714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9646 00:39:19.323457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9647 00:39:19.330694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9648 00:39:19.333343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9649 00:39:19.340076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9650 00:39:19.343516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9651 00:39:19.350287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9652 00:39:19.353201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9653 00:39:19.360160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9654 00:39:19.363592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9655 00:39:19.369875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9656 00:39:19.373247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9657 00:39:19.376437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9658 00:39:19.383607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9659 00:39:19.386408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9660 00:39:19.393091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9661 00:39:19.396339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9662 00:39:19.402938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9663 00:39:19.406400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9664 00:39:19.412592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9665 00:39:19.415922 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9666 00:39:19.419446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9667 00:39:19.426089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9668 00:39:19.429140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9669 00:39:19.435947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9670 00:39:19.438911 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9671 00:39:19.442824 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9672 00:39:19.445967 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9673 00:39:19.452335 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9674 00:39:19.455642 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9675 00:39:19.458719 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9676 00:39:19.465686 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9677 00:39:19.468619 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9678 00:39:19.475233 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9679 00:39:19.478645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9680 00:39:19.485386 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9681 00:39:19.489069 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9682 00:39:19.491896 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9683 00:39:19.498676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9684 00:39:19.502039 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9685 00:39:19.508551 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9686 00:39:19.511881 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9687 00:39:19.515078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9688 00:39:19.521486 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9689 00:39:19.524961 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9690 00:39:19.528176 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9691 00:39:19.534543 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9692 00:39:19.537988 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9693 00:39:19.541284 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9694 00:39:19.544797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9695 00:39:19.551485 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9696 00:39:19.554485 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9697 00:39:19.557944 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9698 00:39:19.564909 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9699 00:39:19.567914 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9700 00:39:19.574499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9701 00:39:19.577461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9702 00:39:19.580807 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9703 00:39:19.587591 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9704 00:39:19.590809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9705 00:39:19.598032 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9706 00:39:19.600700 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9707 00:39:19.603995 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9708 00:39:19.610952 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9709 00:39:19.613840 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9710 00:39:19.620701 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9711 00:39:19.624029 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9712 00:39:19.627418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9713 00:39:19.633819 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9714 00:39:19.637294 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9715 00:39:19.644233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9716 00:39:19.647043 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9717 00:39:19.650679 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9718 00:39:19.656818 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9719 00:39:19.660759 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9720 00:39:19.666848 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9721 00:39:19.670666 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9722 00:39:19.673414 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9723 00:39:19.680414 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9724 00:39:19.683221 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9725 00:39:19.690016 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9726 00:39:19.693070 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9727 00:39:19.697154 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9728 00:39:19.703299 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9729 00:39:19.706599 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9730 00:39:19.713333 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9731 00:39:19.716322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9732 00:39:19.719343 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9733 00:39:19.725910 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9734 00:39:19.729682 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9735 00:39:19.736288 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9736 00:39:19.739539 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9737 00:39:19.742504 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9738 00:39:19.749498 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9739 00:39:19.752348 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9740 00:39:19.758920 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9741 00:39:19.762289 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9742 00:39:19.765488 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9743 00:39:19.772009 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9744 00:39:19.775639 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9745 00:39:19.782382 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9746 00:39:19.785296 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9747 00:39:19.788720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9748 00:39:19.795422 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9749 00:39:19.798643 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9750 00:39:19.805413 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9751 00:39:19.808386 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9752 00:39:19.811714 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9753 00:39:19.818576 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9754 00:39:19.821911 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9755 00:39:19.828289 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9756 00:39:19.832193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9757 00:39:19.835144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9758 00:39:19.841507 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9759 00:39:19.845321 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9760 00:39:19.851401 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9761 00:39:19.854743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9762 00:39:19.861438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9763 00:39:19.864639 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9764 00:39:19.867710 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9765 00:39:19.874425 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9766 00:39:19.877987 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9767 00:39:19.884169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9768 00:39:19.887740 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9769 00:39:19.894535 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9770 00:39:19.897338 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9771 00:39:19.900816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9772 00:39:19.907138 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9773 00:39:19.910719 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9774 00:39:19.917444 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9775 00:39:19.920745 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9776 00:39:19.923658 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9777 00:39:19.930352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9778 00:39:19.933860 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9779 00:39:19.940368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9780 00:39:19.943564 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9781 00:39:19.950166 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9782 00:39:19.953482 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9783 00:39:19.957017 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9784 00:39:19.963455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9785 00:39:19.966624 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9786 00:39:19.973639 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9787 00:39:19.977417 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9788 00:39:19.983329 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9789 00:39:19.986579 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9790 00:39:19.990067 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9791 00:39:19.996540 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9792 00:39:19.999914 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9793 00:39:20.006245 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9794 00:39:20.009720 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9795 00:39:20.016106 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9796 00:39:20.019827 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9797 00:39:20.022982 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9798 00:39:20.029524 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9799 00:39:20.033045 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9800 00:39:20.039547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9801 00:39:20.042946 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9802 00:39:20.046045 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9803 00:39:20.052562 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9804 00:39:20.055837 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9805 00:39:20.059233 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9806 00:39:20.062770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9807 00:39:20.069314 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9808 00:39:20.072948 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9809 00:39:20.076507 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9810 00:39:20.082545 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9811 00:39:20.085472 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9812 00:39:20.089004 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9813 00:39:20.095942 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9814 00:39:20.099042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9815 00:39:20.105422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9816 00:39:20.108882 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9817 00:39:20.111948 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9818 00:39:20.118636 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9819 00:39:20.122231 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9820 00:39:20.128742 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9821 00:39:20.131751 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9822 00:39:20.135352 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9823 00:39:20.141892 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9824 00:39:20.145218 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9825 00:39:20.148567 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9826 00:39:20.155207 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9827 00:39:20.158340 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9828 00:39:20.161956 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9829 00:39:20.168248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9830 00:39:20.171896 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9831 00:39:20.175261 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9832 00:39:20.181597 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9833 00:39:20.185172 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9834 00:39:20.191519 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9835 00:39:20.194816 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9836 00:39:20.198080 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9837 00:39:20.204785 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9838 00:39:20.208101 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9839 00:39:20.211636 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9840 00:39:20.217944 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9841 00:39:20.221542 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9842 00:39:20.224714 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9843 00:39:20.231336 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9844 00:39:20.234741 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9845 00:39:20.238100 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9846 00:39:20.241044 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9847 00:39:20.248053 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9848 00:39:20.251277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9849 00:39:20.254575 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9850 00:39:20.257777 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9851 00:39:20.264301 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9852 00:39:20.267537 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9853 00:39:20.271123 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9854 00:39:20.273967 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9855 00:39:20.280550 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9856 00:39:20.283949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9857 00:39:20.290420 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9858 00:39:20.293950 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9859 00:39:20.300705 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9860 00:39:20.303812 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9861 00:39:20.307334 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9862 00:39:20.313623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9863 00:39:20.316881 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9864 00:39:20.323745 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9865 00:39:20.327617 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9866 00:39:20.333842 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9867 00:39:20.337052 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9868 00:39:20.340646 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9869 00:39:20.346733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9870 00:39:20.350057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9871 00:39:20.356613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9872 00:39:20.359903 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9873 00:39:20.364034 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9874 00:39:20.369815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9875 00:39:20.373488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9876 00:39:20.379956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9877 00:39:20.382915 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9878 00:39:20.386664 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9879 00:39:20.392889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9880 00:39:20.396846 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9881 00:39:20.402885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9882 00:39:20.406028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9883 00:39:20.412786 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9884 00:39:20.415874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9885 00:39:20.419439 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9886 00:39:20.426512 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9887 00:39:20.429174 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9888 00:39:20.435844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9889 00:39:20.439084 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9890 00:39:20.442433 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9891 00:39:20.449146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9892 00:39:20.452406 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9893 00:39:20.458881 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9894 00:39:20.462293 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9895 00:39:20.468996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9896 00:39:20.472112 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9897 00:39:20.475501 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9898 00:39:20.482341 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9899 00:39:20.485897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9900 00:39:20.492418 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9901 00:39:20.495738 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9902 00:39:20.498650 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9903 00:39:20.505708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9904 00:39:20.508386 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9905 00:39:20.515463 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9906 00:39:20.518714 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9907 00:39:20.525069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9908 00:39:20.528012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9909 00:39:20.531940 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9910 00:39:20.538023 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9911 00:39:20.541258 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9912 00:39:20.547794 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9913 00:39:20.551369 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9914 00:39:20.557704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9915 00:39:20.561266 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9916 00:39:20.565184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9917 00:39:20.571162 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9918 00:39:20.574642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9919 00:39:20.580903 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9920 00:39:20.584348 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9921 00:39:20.587888 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9922 00:39:20.594670 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9923 00:39:20.597810 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9924 00:39:20.604415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9925 00:39:20.607582 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9926 00:39:20.610961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9927 00:39:20.617469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9928 00:39:20.620929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9929 00:39:20.626857 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9930 00:39:20.630683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9931 00:39:20.636927 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9932 00:39:20.640103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9933 00:39:20.647185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9934 00:39:20.650100 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9935 00:39:20.653264 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9936 00:39:20.659997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9937 00:39:20.663704 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9938 00:39:20.669987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9939 00:39:20.673333 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9940 00:39:20.680087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9941 00:39:20.683382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9942 00:39:20.689782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9943 00:39:20.692975 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9944 00:39:20.696384 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9945 00:39:20.703002 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9946 00:39:20.706338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9947 00:39:20.712980 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9948 00:39:20.716147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9949 00:39:20.723106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9950 00:39:20.726702 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9951 00:39:20.732930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9952 00:39:20.736034 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9953 00:39:20.739527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9954 00:39:20.746059 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9955 00:39:20.749349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9956 00:39:20.755846 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9957 00:39:20.759492 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9958 00:39:20.766306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9959 00:39:20.769366 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9960 00:39:20.772630 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9961 00:39:20.779455 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9962 00:39:20.782567 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9963 00:39:20.789310 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9964 00:39:20.793071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9965 00:39:20.798979 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9966 00:39:20.802758 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9967 00:39:20.805895 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9968 00:39:20.812480 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9969 00:39:20.815546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9970 00:39:20.822178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9971 00:39:20.825463 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9972 00:39:20.832175 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9973 00:39:20.835758 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9974 00:39:20.841795 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9975 00:39:20.845125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9976 00:39:20.848677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9977 00:39:20.855184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9978 00:39:20.858539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9979 00:39:20.865294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9980 00:39:20.868499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9981 00:39:20.875018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9982 00:39:20.878166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9983 00:39:20.884589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9984 00:39:20.888026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9985 00:39:20.894811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9986 00:39:20.898123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9987 00:39:20.904733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9988 00:39:20.907824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9989 00:39:20.914396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9990 00:39:20.917849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9991 00:39:20.924455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9992 00:39:20.927979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9993 00:39:20.934074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9994 00:39:20.937747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9995 00:39:20.944221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9996 00:39:20.947699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9997 00:39:20.954575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9998 00:39:20.957433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9999 00:39:20.964061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10000 00:39:20.967539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10001 00:39:20.974115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10002 00:39:20.977586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10003 00:39:20.984238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10004 00:39:20.986995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10005 00:39:20.994031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10006 00:39:20.996904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10007 00:39:21.003562 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10008 00:39:21.003643 INFO: [APUAPC] vio 0
10009 00:39:21.010358 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10010 00:39:21.013547 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10011 00:39:21.016938 INFO: [APUAPC] D0_APC_0: 0x400510
10012 00:39:21.020438 INFO: [APUAPC] D0_APC_1: 0x0
10013 00:39:21.024013 INFO: [APUAPC] D0_APC_2: 0x1540
10014 00:39:21.026842 INFO: [APUAPC] D0_APC_3: 0x0
10015 00:39:21.030091 INFO: [APUAPC] D1_APC_0: 0xffffffff
10016 00:39:21.033433 INFO: [APUAPC] D1_APC_1: 0xffffffff
10017 00:39:21.036756 INFO: [APUAPC] D1_APC_2: 0x3fffff
10018 00:39:21.040155 INFO: [APUAPC] D1_APC_3: 0x0
10019 00:39:21.043849 INFO: [APUAPC] D2_APC_0: 0xffffffff
10020 00:39:21.046621 INFO: [APUAPC] D2_APC_1: 0xffffffff
10021 00:39:21.050100 INFO: [APUAPC] D2_APC_2: 0x3fffff
10022 00:39:21.053197 INFO: [APUAPC] D2_APC_3: 0x0
10023 00:39:21.056657 INFO: [APUAPC] D3_APC_0: 0xffffffff
10024 00:39:21.059488 INFO: [APUAPC] D3_APC_1: 0xffffffff
10025 00:39:21.063316 INFO: [APUAPC] D3_APC_2: 0x3fffff
10026 00:39:21.066558 INFO: [APUAPC] D3_APC_3: 0x0
10027 00:39:21.069520 INFO: [APUAPC] D4_APC_0: 0xffffffff
10028 00:39:21.072975 INFO: [APUAPC] D4_APC_1: 0xffffffff
10029 00:39:21.076276 INFO: [APUAPC] D4_APC_2: 0x3fffff
10030 00:39:21.079798 INFO: [APUAPC] D4_APC_3: 0x0
10031 00:39:21.082655 INFO: [APUAPC] D5_APC_0: 0xffffffff
10032 00:39:21.086044 INFO: [APUAPC] D5_APC_1: 0xffffffff
10033 00:39:21.089384 INFO: [APUAPC] D5_APC_2: 0x3fffff
10034 00:39:21.092949 INFO: [APUAPC] D5_APC_3: 0x0
10035 00:39:21.095998 INFO: [APUAPC] D6_APC_0: 0xffffffff
10036 00:39:21.099660 INFO: [APUAPC] D6_APC_1: 0xffffffff
10037 00:39:21.102845 INFO: [APUAPC] D6_APC_2: 0x3fffff
10038 00:39:21.102925 INFO: [APUAPC] D6_APC_3: 0x0
10039 00:39:21.106055 INFO: [APUAPC] D7_APC_0: 0xffffffff
10040 00:39:21.112384 INFO: [APUAPC] D7_APC_1: 0xffffffff
10041 00:39:21.115939 INFO: [APUAPC] D7_APC_2: 0x3fffff
10042 00:39:21.116019 INFO: [APUAPC] D7_APC_3: 0x0
10043 00:39:21.119145 INFO: [APUAPC] D8_APC_0: 0xffffffff
10044 00:39:21.125783 INFO: [APUAPC] D8_APC_1: 0xffffffff
10045 00:39:21.125864 INFO: [APUAPC] D8_APC_2: 0x3fffff
10046 00:39:21.129068 INFO: [APUAPC] D8_APC_3: 0x0
10047 00:39:21.132262 INFO: [APUAPC] D9_APC_0: 0xffffffff
10048 00:39:21.135562 INFO: [APUAPC] D9_APC_1: 0xffffffff
10049 00:39:21.139454 INFO: [APUAPC] D9_APC_2: 0x3fffff
10050 00:39:21.142356 INFO: [APUAPC] D9_APC_3: 0x0
10051 00:39:21.145697 INFO: [APUAPC] D10_APC_0: 0xffffffff
10052 00:39:21.149101 INFO: [APUAPC] D10_APC_1: 0xffffffff
10053 00:39:21.152128 INFO: [APUAPC] D10_APC_2: 0x3fffff
10054 00:39:21.155589 INFO: [APUAPC] D10_APC_3: 0x0
10055 00:39:21.158977 INFO: [APUAPC] D11_APC_0: 0xffffffff
10056 00:39:21.162082 INFO: [APUAPC] D11_APC_1: 0xffffffff
10057 00:39:21.165538 INFO: [APUAPC] D11_APC_2: 0x3fffff
10058 00:39:21.168558 INFO: [APUAPC] D11_APC_3: 0x0
10059 00:39:21.172004 INFO: [APUAPC] D12_APC_0: 0xffffffff
10060 00:39:21.178800 INFO: [APUAPC] D12_APC_1: 0xffffffff
10061 00:39:21.181864 INFO: [APUAPC] D12_APC_2: 0x3fffff
10062 00:39:21.181945 INFO: [APUAPC] D12_APC_3: 0x0
10063 00:39:21.188413 INFO: [APUAPC] D13_APC_0: 0xffffffff
10064 00:39:21.191942 INFO: [APUAPC] D13_APC_1: 0xffffffff
10065 00:39:21.195141 INFO: [APUAPC] D13_APC_2: 0x3fffff
10066 00:39:21.195221 INFO: [APUAPC] D13_APC_3: 0x0
10067 00:39:21.201809 INFO: [APUAPC] D14_APC_0: 0xffffffff
10068 00:39:21.205269 INFO: [APUAPC] D14_APC_1: 0xffffffff
10069 00:39:21.208485 INFO: [APUAPC] D14_APC_2: 0x3fffff
10070 00:39:21.208569 INFO: [APUAPC] D14_APC_3: 0x0
10071 00:39:21.214819 INFO: [APUAPC] D15_APC_0: 0xffffffff
10072 00:39:21.218292 INFO: [APUAPC] D15_APC_1: 0xffffffff
10073 00:39:21.221826 INFO: [APUAPC] D15_APC_2: 0x3fffff
10074 00:39:21.225003 INFO: [APUAPC] D15_APC_3: 0x0
10075 00:39:21.225087 INFO: [APUAPC] APC_CON: 0x4
10076 00:39:21.228270 INFO: [NOCDAPC] D0_APC_0: 0x0
10077 00:39:21.231683 INFO: [NOCDAPC] D0_APC_1: 0x0
10078 00:39:21.234788 INFO: [NOCDAPC] D1_APC_0: 0x0
10079 00:39:21.238094 INFO: [NOCDAPC] D1_APC_1: 0xfff
10080 00:39:21.241528 INFO: [NOCDAPC] D2_APC_0: 0x0
10081 00:39:21.244792 INFO: [NOCDAPC] D2_APC_1: 0xfff
10082 00:39:21.248217 INFO: [NOCDAPC] D3_APC_0: 0x0
10083 00:39:21.251317 INFO: [NOCDAPC] D3_APC_1: 0xfff
10084 00:39:21.251402 INFO: [NOCDAPC] D4_APC_0: 0x0
10085 00:39:21.254792 INFO: [NOCDAPC] D4_APC_1: 0xfff
10086 00:39:21.258258 INFO: [NOCDAPC] D5_APC_0: 0x0
10087 00:39:21.262175 INFO: [NOCDAPC] D5_APC_1: 0xfff
10088 00:39:21.264494 INFO: [NOCDAPC] D6_APC_0: 0x0
10089 00:39:21.268346 INFO: [NOCDAPC] D6_APC_1: 0xfff
10090 00:39:21.271326 INFO: [NOCDAPC] D7_APC_0: 0x0
10091 00:39:21.274938 INFO: [NOCDAPC] D7_APC_1: 0xfff
10092 00:39:21.277886 INFO: [NOCDAPC] D8_APC_0: 0x0
10093 00:39:21.281242 INFO: [NOCDAPC] D8_APC_1: 0xfff
10094 00:39:21.284644 INFO: [NOCDAPC] D9_APC_0: 0x0
10095 00:39:21.287822 INFO: [NOCDAPC] D9_APC_1: 0xfff
10096 00:39:21.287906 INFO: [NOCDAPC] D10_APC_0: 0x0
10097 00:39:21.291095 INFO: [NOCDAPC] D10_APC_1: 0xfff
10098 00:39:21.294276 INFO: [NOCDAPC] D11_APC_0: 0x0
10099 00:39:21.298053 INFO: [NOCDAPC] D11_APC_1: 0xfff
10100 00:39:21.300817 INFO: [NOCDAPC] D12_APC_0: 0x0
10101 00:39:21.304586 INFO: [NOCDAPC] D12_APC_1: 0xfff
10102 00:39:21.307510 INFO: [NOCDAPC] D13_APC_0: 0x0
10103 00:39:21.311251 INFO: [NOCDAPC] D13_APC_1: 0xfff
10104 00:39:21.314453 INFO: [NOCDAPC] D14_APC_0: 0x0
10105 00:39:21.317665 INFO: [NOCDAPC] D14_APC_1: 0xfff
10106 00:39:21.320763 INFO: [NOCDAPC] D15_APC_0: 0x0
10107 00:39:21.324179 INFO: [NOCDAPC] D15_APC_1: 0xfff
10108 00:39:21.327377 INFO: [NOCDAPC] APC_CON: 0x4
10109 00:39:21.331132 INFO: [APUAPC] set_apusys_apc done
10110 00:39:21.334260 INFO: [DEVAPC] devapc_init done
10111 00:39:21.337557 INFO: GICv3 without legacy support detected.
10112 00:39:21.341139 INFO: ARM GICv3 driver initialized in EL3
10113 00:39:21.344006 INFO: Maximum SPI INTID supported: 639
10114 00:39:21.347711 INFO: BL31: Initializing runtime services
10115 00:39:21.353774 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10116 00:39:21.357396 INFO: SPM: enable CPC mode
10117 00:39:21.363760 INFO: mcdi ready for mcusys-off-idle and system suspend
10118 00:39:21.366909 INFO: BL31: Preparing for EL3 exit to normal world
10119 00:39:21.370654 INFO: Entry point address = 0x80000000
10120 00:39:21.373784 INFO: SPSR = 0x8
10121 00:39:21.378517
10122 00:39:21.378597
10123 00:39:21.378660
10124 00:39:21.381704 Starting depthcharge on Spherion...
10125 00:39:21.381785
10126 00:39:21.381847 Wipe memory regions:
10127 00:39:21.381906
10128 00:39:21.382516 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10129 00:39:21.382612 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10130 00:39:21.382693 Setting prompt string to ['asurada:']
10131 00:39:21.382777 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10132 00:39:21.384837 [0x00000040000000, 0x00000054600000)
10133 00:39:21.507536
10134 00:39:21.507655 [0x00000054660000, 0x00000080000000)
10135 00:39:21.768073
10136 00:39:21.768217 [0x000000821a7280, 0x000000ffe64000)
10137 00:39:22.513107
10138 00:39:22.513274 [0x00000100000000, 0x00000240000000)
10139 00:39:24.403234
10140 00:39:24.406210 Initializing XHCI USB controller at 0x11200000.
10141 00:39:25.445223
10142 00:39:25.448509 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10143 00:39:25.448599
10144 00:39:25.448716
10145 00:39:25.449028 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10147 00:39:25.549415 asurada: tftpboot 192.168.201.1 14173479/tftp-deploy-dv0tiued/kernel/image.itb 14173479/tftp-deploy-dv0tiued/kernel/cmdline
10148 00:39:25.549549 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10149 00:39:25.549659 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10150 00:39:25.554060 tftpboot 192.168.201.1 14173479/tftp-deploy-dv0tiued/kernel/image.itp-deploy-dv0tiued/kernel/cmdline
10151 00:39:25.554193
10152 00:39:25.554275 Waiting for link
10153 00:39:25.712286
10154 00:39:25.712418 R8152: Initializing
10155 00:39:25.712484
10156 00:39:25.715371 Version 6 (ocp_data = 5c30)
10157 00:39:25.715458
10158 00:39:25.718947 R8152: Done initializing
10159 00:39:25.719029
10160 00:39:25.719093 Adding net device
10161 00:39:27.687637
10162 00:39:27.687784 done.
10163 00:39:27.687849
10164 00:39:27.687909 MAC: 00:e0:4c:68:02:81
10165 00:39:27.687966
10166 00:39:27.691173 Sending DHCP discover... done.
10167 00:39:27.691257
10168 00:39:27.694837 Waiting for reply... done.
10169 00:39:27.694946
10170 00:39:27.697807 Sending DHCP request... done.
10171 00:39:27.697888
10172 00:39:27.697951 Waiting for reply... done.
10173 00:39:27.698011
10174 00:39:27.700965 My ip is 192.168.201.14
10175 00:39:27.701046
10176 00:39:27.704296 The DHCP server ip is 192.168.201.1
10177 00:39:27.704377
10178 00:39:27.707303 TFTP server IP predefined by user: 192.168.201.1
10179 00:39:27.707394
10180 00:39:27.714102 Bootfile predefined by user: 14173479/tftp-deploy-dv0tiued/kernel/image.itb
10181 00:39:27.714208
10182 00:39:27.717071 Sending tftp read request... done.
10183 00:39:27.717153
10184 00:39:27.723971 Waiting for the transfer...
10185 00:39:27.724054
10186 00:39:28.252351 00000000 ################################################################
10187 00:39:28.252494
10188 00:39:28.789508 00080000 ################################################################
10189 00:39:28.789664
10190 00:39:29.318947 00100000 ################################################################
10191 00:39:29.319088
10192 00:39:29.993681 00180000 ################################################################
10193 00:39:29.994230
10194 00:39:30.705818 00200000 ################################################################
10195 00:39:30.706429
10196 00:39:31.403496 00280000 ################################################################
10197 00:39:31.404042
10198 00:39:32.092729 00300000 ################################################################
10199 00:39:32.093212
10200 00:39:32.685018 00380000 ################################################################
10201 00:39:32.685261
10202 00:39:33.361112 00400000 ################################################################
10203 00:39:33.361610
10204 00:39:34.028088 00480000 ################################################################
10205 00:39:34.028615
10206 00:39:34.632211 00500000 ################################################################
10207 00:39:34.632735
10208 00:39:35.355533 00580000 ################################################################
10209 00:39:35.356044
10210 00:39:36.067222 00600000 ################################################################
10211 00:39:36.067727
10212 00:39:36.776749 00680000 ################################################################
10213 00:39:36.777311
10214 00:39:37.486236 00700000 ################################################################
10215 00:39:37.486735
10216 00:39:38.175585 00780000 ################################################################
10217 00:39:38.176102
10218 00:39:38.892465 00800000 ################################################################
10219 00:39:38.892997
10220 00:39:39.601756 00880000 ################################################################
10221 00:39:39.602589
10222 00:39:40.318233 00900000 ################################################################
10223 00:39:40.318772
10224 00:39:40.999549 00980000 ################################################################
10225 00:39:40.999700
10226 00:39:41.639398 00a00000 ################################################################
10227 00:39:41.639534
10228 00:39:42.269952 00a80000 ################################################################
10229 00:39:42.270096
10230 00:39:42.861345 00b00000 ################################################################
10231 00:39:42.861487
10232 00:39:43.500413 00b80000 ################################################################
10233 00:39:43.500929
10234 00:39:44.117618 00c00000 ################################################################
10235 00:39:44.117786
10236 00:39:44.694990 00c80000 ################################################################
10237 00:39:44.695125
10238 00:39:45.284801 00d00000 ################################################################
10239 00:39:45.285030
10240 00:39:45.938933 00d80000 ################################################################
10241 00:39:45.939435
10242 00:39:46.620234 00e00000 ################################################################
10243 00:39:46.620756
10244 00:39:47.211333 00e80000 ################################################################
10245 00:39:47.211470
10246 00:39:47.766960 00f00000 ################################################################
10247 00:39:47.767114
10248 00:39:48.345598 00f80000 ################################################################
10249 00:39:48.346094
10250 00:39:49.043283 01000000 ################################################################
10251 00:39:49.043436
10252 00:39:49.716731 01080000 ################################################################
10253 00:39:49.716863
10254 00:39:50.327928 01100000 ################################################################
10255 00:39:50.328101
10256 00:39:50.889357 01180000 ################################################################
10257 00:39:50.889510
10258 00:39:51.461779 01200000 ################################################################
10259 00:39:51.461944
10260 00:39:52.023663 01280000 ################################################################
10261 00:39:52.023802
10262 00:39:52.612879 01300000 ################################################################
10263 00:39:52.613365
10264 00:39:53.279612 01380000 ################################################################
10265 00:39:53.280164
10266 00:39:53.925577 01400000 ################################################################
10267 00:39:53.926290
10268 00:39:54.626649 01480000 ################################################################
10269 00:39:54.627189
10270 00:39:55.236093 01500000 ################################################################
10271 00:39:55.236232
10272 00:39:55.828523 01580000 ################################################################
10273 00:39:55.828736
10274 00:39:56.511798 01600000 ################################################################
10275 00:39:56.512369
10276 00:39:57.166477 01680000 ################################################################
10277 00:39:57.166623
10278 00:39:57.728591 01700000 ################################################################
10279 00:39:57.728767
10280 00:39:58.294352 01780000 ################################################################
10281 00:39:58.294504
10282 00:39:58.882630 01800000 ################################################################
10283 00:39:58.882795
10284 00:39:59.548674 01880000 ################################################################
10285 00:39:59.548833
10286 00:40:00.161061 01900000 ################################################################
10287 00:40:00.161212
10288 00:40:00.759956 01980000 ################################################################
10289 00:40:00.760106
10290 00:40:01.322564 01a00000 ################################################################
10291 00:40:01.322775
10292 00:40:01.908648 01a80000 ################################################################
10293 00:40:01.908860
10294 00:40:02.478027 01b00000 ################################################################
10295 00:40:02.478165
10296 00:40:03.054447 01b80000 ################################################################
10297 00:40:03.054590
10298 00:40:03.687168 01c00000 ################################################################
10299 00:40:03.687320
10300 00:40:04.344104 01c80000 ################################################################
10301 00:40:04.344274
10302 00:40:04.983134 01d00000 ################################################################
10303 00:40:04.983279
10304 00:40:05.590421 01d80000 ################################################################
10305 00:40:05.590556
10306 00:40:06.066159 01e00000 ############################################### done.
10307 00:40:06.066747
10308 00:40:06.069431 The bootfile was 31840886 bytes long.
10309 00:40:06.069945
10310 00:40:06.072737 Sending tftp read request... done.
10311 00:40:06.073158
10312 00:40:06.076664 Waiting for the transfer...
10313 00:40:06.077083
10314 00:40:06.077414 00000000 # done.
10315 00:40:06.077731
10316 00:40:06.082994 Command line loaded dynamically from TFTP file: 14173479/tftp-deploy-dv0tiued/kernel/cmdline
10317 00:40:06.086636
10318 00:40:06.106454 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10319 00:40:06.107193
10320 00:40:06.110091 Loading FIT.
10321 00:40:06.110625
10322 00:40:06.113475 Image ramdisk-1 has 18731676 bytes.
10323 00:40:06.113961
10324 00:40:06.114399 Image fdt-1 has 47258 bytes.
10325 00:40:06.114705
10326 00:40:06.116307 Image kernel-1 has 13059919 bytes.
10327 00:40:06.116724
10328 00:40:06.126382 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10329 00:40:06.126899
10330 00:40:06.142087 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10331 00:40:06.142574
10332 00:40:06.149423 Choosing best match conf-1 for compat google,spherion-rev2.
10333 00:40:06.153069
10334 00:40:06.157033 Connected to device vid:did:rid of 1ae0:0028:00
10335 00:40:06.164241
10336 00:40:06.167535 tpm_get_response: command 0x17b, return code 0x0
10337 00:40:06.167957
10338 00:40:06.170756 ec_init: CrosEC protocol v3 supported (256, 248)
10339 00:40:06.174790
10340 00:40:06.178583 tpm_cleanup: add release locality here.
10341 00:40:06.179289
10342 00:40:06.179653 Shutting down all USB controllers.
10343 00:40:06.181309
10344 00:40:06.181729 Removing current net device
10345 00:40:06.182062
10346 00:40:06.188021 Exiting depthcharge with code 4 at timestamp: 74207292
10347 00:40:06.188525
10348 00:40:06.191877 LZMA decompressing kernel-1 to 0x821a6718
10349 00:40:06.192399
10350 00:40:06.194784 LZMA decompressing kernel-1 to 0x40000000
10351 00:40:07.804293
10352 00:40:07.804849 jumping to kernel
10353 00:40:07.806655 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10354 00:40:07.807182 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10355 00:40:07.807667 Setting prompt string to ['Linux version [0-9]']
10356 00:40:07.808047 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10357 00:40:07.808416 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10358 00:40:07.886693
10359 00:40:07.889728 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10360 00:40:07.893773 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10361 00:40:07.894553 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10362 00:40:07.894971 Setting prompt string to []
10363 00:40:07.895399 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10364 00:40:07.895814 Using line separator: #'\n'#
10365 00:40:07.896198 No login prompt set.
10366 00:40:07.896586 Parsing kernel messages
10367 00:40:07.896908 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10368 00:40:07.897480 [login-action] Waiting for messages, (timeout 00:03:40)
10369 00:40:07.897848 Waiting using forced prompt support (timeout 00:01:50)
10370 00:40:07.913321 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10371 00:40:07.916167 [ 0.000000] random: crng init done
10372 00:40:07.922983 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10373 00:40:07.925991 [ 0.000000] efi: UEFI not found.
10374 00:40:07.932888 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10375 00:40:07.942990 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10376 00:40:07.952471 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10377 00:40:07.959031 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10378 00:40:07.965754 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10379 00:40:07.972269 [ 0.000000] printk: bootconsole [mtk8250] enabled
10380 00:40:07.979698 [ 0.000000] NUMA: No NUMA configuration found
10381 00:40:07.986196 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10382 00:40:07.992587 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10383 00:40:07.993186 [ 0.000000] Zone ranges:
10384 00:40:07.999215 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10385 00:40:08.001844 [ 0.000000] DMA32 empty
10386 00:40:08.008865 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10387 00:40:08.012414 [ 0.000000] Movable zone start for each node
10388 00:40:08.015240 [ 0.000000] Early memory node ranges
10389 00:40:08.022034 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10390 00:40:08.028702 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10391 00:40:08.035070 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10392 00:40:08.041577 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10393 00:40:08.047979 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10394 00:40:08.055051 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10395 00:40:08.111471 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10396 00:40:08.118133 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10397 00:40:08.125254 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10398 00:40:08.128441 [ 0.000000] psci: probing for conduit method from DT.
10399 00:40:08.134730 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10400 00:40:08.137779 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10401 00:40:08.144709 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10402 00:40:08.148008 [ 0.000000] psci: SMC Calling Convention v1.2
10403 00:40:08.154591 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10404 00:40:08.157719 [ 0.000000] Detected VIPT I-cache on CPU0
10405 00:40:08.164563 [ 0.000000] CPU features: detected: GIC system register CPU interface
10406 00:40:08.171166 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10407 00:40:08.177422 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10408 00:40:08.184689 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10409 00:40:08.194263 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10410 00:40:08.201016 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10411 00:40:08.204016 [ 0.000000] alternatives: applying boot alternatives
10412 00:40:08.210849 [ 0.000000] Fallback order for Node 0: 0
10413 00:40:08.217459 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10414 00:40:08.220557 [ 0.000000] Policy zone: Normal
10415 00:40:08.243460 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10416 00:40:08.253263 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10417 00:40:08.265112 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10418 00:40:08.274312 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10419 00:40:08.281426 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10420 00:40:08.284396 <6>[ 0.000000] software IO TLB: area num 8.
10421 00:40:08.341393 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10422 00:40:08.490688 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10423 00:40:08.497340 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10424 00:40:08.504032 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10425 00:40:08.507089 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10426 00:40:08.514012 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10427 00:40:08.520221 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10428 00:40:08.523376 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10429 00:40:08.533687 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10430 00:40:08.539931 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10431 00:40:08.546717 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10432 00:40:08.553456 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10433 00:40:08.556592 <6>[ 0.000000] GICv3: 608 SPIs implemented
10434 00:40:08.559511 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10435 00:40:08.566587 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10436 00:40:08.569887 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10437 00:40:08.576489 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10438 00:40:08.589533 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10439 00:40:08.602712 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10440 00:40:08.609209 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10441 00:40:08.617461 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10442 00:40:08.630588 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10443 00:40:08.636835 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10444 00:40:08.644220 <6>[ 0.009179] Console: colour dummy device 80x25
10445 00:40:08.653667 <6>[ 0.013894] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10446 00:40:08.660222 <6>[ 0.024400] pid_max: default: 32768 minimum: 301
10447 00:40:08.663395 <6>[ 0.029272] LSM: Security Framework initializing
10448 00:40:08.670221 <6>[ 0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10449 00:40:08.680324 <6>[ 0.042071] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10450 00:40:08.689984 <6>[ 0.051475] cblist_init_generic: Setting adjustable number of callback queues.
10451 00:40:08.696754 <6>[ 0.058965] cblist_init_generic: Setting shift to 3 and lim to 1.
10452 00:40:08.703130 <6>[ 0.065302] cblist_init_generic: Setting adjustable number of callback queues.
10453 00:40:08.709557 <6>[ 0.072776] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 00:40:08.713187 <6>[ 0.079212] rcu: Hierarchical SRCU implementation.
10455 00:40:08.719517 <6>[ 0.079214] rcu: Max phase no-delay instances is 1000.
10456 00:40:08.725887 <6>[ 0.079237] printk: bootconsole [mtk8250] printing thread started
10457 00:40:08.732835 <6>[ 0.097562] EFI services will not be available.
10458 00:40:08.736128 <6>[ 0.097734] smp: Bringing up secondary CPUs ...
10459 00:40:08.742776 <6>[ 0.098020] Detected VIPT I-cache on CPU1
10460 00:40:08.749115 <6>[ 0.098087] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10461 00:40:08.755689 <6>[ 0.098118] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10462 00:40:08.765666 <6>[ 0.125997] Detected VIPT I-cache on CPU2
10463 00:40:08.772278 <6>[ 0.126049] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10464 00:40:08.782239 <6>[ 0.126066] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10465 00:40:08.785546 <6>[ 0.126328] Detected VIPT I-cache on CPU3
10466 00:40:08.792407 <6>[ 0.126377] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10467 00:40:08.798691 <6>[ 0.126391] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10468 00:40:08.802134 <6>[ 0.126702] CPU features: detected: Spectre-v4
10469 00:40:08.808921 <6>[ 0.126708] CPU features: detected: Spectre-BHB
10470 00:40:08.811611 <6>[ 0.126713] Detected PIPT I-cache on CPU4
10471 00:40:08.818364 <6>[ 0.126773] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10472 00:40:08.825012 <6>[ 0.126789] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10473 00:40:08.831970 <6>[ 0.127079] Detected PIPT I-cache on CPU5
10474 00:40:08.838332 <6>[ 0.127141] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10475 00:40:08.844544 <6>[ 0.127157] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10476 00:40:08.848289 <6>[ 0.127427] Detected PIPT I-cache on CPU6
10477 00:40:08.855081 <6>[ 0.127491] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10478 00:40:08.865632 <6>[ 0.127507] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10479 00:40:08.869173 <6>[ 0.127793] Detected PIPT I-cache on CPU7
10480 00:40:08.875504 <6>[ 0.127856] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10481 00:40:08.882066 <6>[ 0.127872] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10482 00:40:08.885314 <6>[ 0.127918] smp: Brought up 1 node, 8 CPUs
10483 00:40:08.891801 <6>[ 0.127923] SMP: Total of 8 processors activated.
10484 00:40:08.898767 <6>[ 0.127925] CPU features: detected: 32-bit EL0 Support
10485 00:40:08.904939 <6>[ 0.127928] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10486 00:40:08.911541 <6>[ 0.127930] CPU features: detected: Common not Private translations
10487 00:40:08.918726 <6>[ 0.127932] CPU features: detected: CRC32 instructions
10488 00:40:08.924648 <6>[ 0.127934] CPU features: detected: RCpc load-acquire (LDAPR)
10489 00:40:08.928376 <6>[ 0.127936] CPU features: detected: LSE atomic instructions
10490 00:40:08.934902 <6>[ 0.127938] CPU features: detected: Privileged Access Never
10491 00:40:08.941531 <6>[ 0.127939] CPU features: detected: RAS Extension Support
10492 00:40:08.948025 <6>[ 0.127942] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10493 00:40:08.950948 <6>[ 0.128009] CPU: All CPU(s) started at EL2
10494 00:40:08.958295 <6>[ 0.128011] alternatives: applying system-wide alternatives
10495 00:40:08.961355 <6>[ 0.141209] devtmpfs: initialized
10496 00:40:08.970914 <6>[ 0.147550] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10497 00:40:08.977291 <6>[ 0.147564] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10498 00:40:09.004311 <6>[ 0.369280] printk: console [ttyS0]< printing thread started
10499 00:40:09.010723 6><6>[ 0.369312] printk: console [ttyS0] enabled
10500 00:40:09.013658 [ 0.148238] pinctrl core: initialized pinctrl subsystem
10501 00:40:09.023590 <6>[ 0.369317] printk: bootconsole [mtk8250] disabled
10502 00:40:09.029917 <6>[ 0.385038] printk: bootconsole [mtk8250] printing thread stopped
10503 00:40:09.033414 <6>[ 0.386361] SuperH (H)SCI(F) driver initialized
10504 00:40:09.040403 <6>[ 0.386848] msm_serial: driver initialized
10505 00:40:09.047066 <6>[ 0.391385] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10506 00:40:09.056142 <6>[ 0.391414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10507 00:40:09.063321 <6>[ 0.391443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10508 00:40:09.072169 <6>[ 0.391474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10509 00:40:09.082861 <6>[ 0.391497] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10510 00:40:09.095155 <6>[ 0.391524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10511 00:40:09.114495 <6>[ 0.391553] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10512 00:40:09.115742 <6>[ 0.391675] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10513 00:40:09.119383 <6>[ 0.391704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10514 00:40:09.123137 <6>[ 0.403908] loop: module loaded
10515 00:40:09.130957 <6>[ 0.406480] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10516 00:40:09.135434 <4>[ 0.423523] mtk-pmic-keys: Failed to locate of_node [id: -1]
10517 00:40:09.138626 <6>[ 0.424513] megasas: 07.719.03.00-rc1
10518 00:40:09.141859 <6>[ 0.436341] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10519 00:40:09.148637 <6>[ 0.440138] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10520 00:40:09.155371 <6>[ 0.451917] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10521 00:40:09.164782 <6>[ 0.509355] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10522 00:40:09.666906 <6>[ 1.031790] Freeing initrd memory: 18288K
10523 00:40:09.674973 <6>[ 1.039111] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10524 00:40:09.681786 <6>[ 1.043647] tun: Universal TUN/TAP device driver, 1.6
10525 00:40:09.685121 <6>[ 1.044390] thunder_xcv, ver 1.0
10526 00:40:09.688320 <6>[ 1.044407] thunder_bgx, ver 1.0
10527 00:40:09.692028 <6>[ 1.044423] nicpf, ver 1.0
10528 00:40:09.698696 <6>[ 1.045466] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10529 00:40:09.704985 <6>[ 1.045469] hns3: Copyright (c) 2017 Huawei Corporation.
10530 00:40:09.708315 <6>[ 1.045496] hclge is initializing
10531 00:40:09.714830 <6>[ 1.045512] e1000: Intel(R) PRO/1000 Network Driver
10532 00:40:09.717884 <6>[ 1.045514] e1000: Copyright (c) 1999-2006 Intel Corporation.
10533 00:40:09.724865 <6>[ 1.045530] e1000e: Intel(R) PRO/1000 Network Driver
10534 00:40:09.731934 <6>[ 1.045532] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10535 00:40:09.735739 <6>[ 1.045547] igb: Intel(R) Gigabit Ethernet Network Driver
10536 00:40:09.742273 <6>[ 1.045549] igb: Copyright (c) 2007-2014 Intel Corporation.
10537 00:40:09.748967 <6>[ 1.045562] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10538 00:40:09.755644 <6>[ 1.045564] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10539 00:40:09.759497 <6>[ 1.045854] sky2: driver version 1.30
10540 00:40:09.766071 <6>[ 1.046863] usbcore: registered new device driver r8152-cfgselector
10541 00:40:09.773088 <6>[ 1.046880] usbcore: registered new interface driver r8152
10542 00:40:09.776277 <6>[ 1.046952] VFIO - User Level meta-driver version: 0.3
10543 00:40:09.782955 <6>[ 1.049767] usbcore: registered new interface driver usb-storage
10544 00:40:09.789333 <6>[ 1.049946] usbcore: registered new device driver onboard-usb-hub
10545 00:40:09.795770 <6>[ 1.052672] mt6397-rtc mt6359-rtc: registered as rtc0
10546 00:40:09.802547 <6>[ 1.052824] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T00:40:09 UTC (1717548009)
10547 00:40:09.809530 <6>[ 1.053418] i2c_dev: i2c /dev entries driver
10548 00:40:09.816082 <6>[ 1.060426] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10549 00:40:09.822456 <4>[ 1.061146] cpu cpu0: supply cpu not found, using dummy regulator
10550 00:40:09.828758 <4>[ 1.061231] cpu cpu1: supply cpu not found, using dummy regulator
10551 00:40:09.835499 <4>[ 1.061287] cpu cpu2: supply cpu not found, using dummy regulator
10552 00:40:09.842378 <4>[ 1.061339] cpu cpu3: supply cpu not found, using dummy regulator
10553 00:40:09.848648 <4>[ 1.061393] cpu cpu4: supply cpu not found, using dummy regulator
10554 00:40:09.855060 <4>[ 1.061442] cpu cpu5: supply cpu not found, using dummy regulator
10555 00:40:09.861811 <4>[ 1.061507] cpu cpu6: supply cpu not found, using dummy regulator
10556 00:40:09.865318 <4>[ 1.061560] cpu cpu7: supply cpu not found, using dummy regulator
10557 00:40:09.872164 <6>[ 1.076838] cpu cpu0: EM: created perf domain
10558 00:40:09.875935 <6>[ 1.077148] cpu cpu4: EM: created perf domain
10559 00:40:09.881989 <6>[ 1.079001] sdhci: Secure Digital Host Controller Interface driver
10560 00:40:09.888570 <6>[ 1.079003] sdhci: Copyright(c) Pierre Ossman
10561 00:40:09.891414 <6>[ 1.079359] Synopsys Designware Multimedia Card Interface Driver
10562 00:40:09.898367 <6>[ 1.079716] sdhci-pltfm: SDHCI platform and OF driver helper
10563 00:40:09.901687 <6>[ 1.084275] mmc0: CQHCI version 5.10
10564 00:40:09.908273 <6>[ 1.090211] ledtrig-cpu: registered to indicate activity on CPUs
10565 00:40:09.914935 <6>[ 1.092539] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10566 00:40:09.921777 <6>[ 1.094145] usbcore: registered new interface driver usbhid
10567 00:40:09.924705 <6>[ 1.094151] usbhid: USB HID core driver
10568 00:40:09.931208 <6>[ 1.094467] spi_master spi0: will run message pump with realtime priority
10569 00:40:09.944407 <6>[ 1.127022] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10570 00:40:09.958197 <6>[ 1.129762] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10571 00:40:09.964800 <6>[ 1.130655] cros-ec-spi spi0.0: Chrome EC device registered
10572 00:40:09.974104 <6>[ 1.150111] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10573 00:40:09.977881 <6>[ 1.153690] NET: Registered PF_PACKET protocol family
10574 00:40:09.984599 <6>[ 1.153822] 9pnet: Installing 9P2000 support
10575 00:40:09.987755 <5>[ 1.153871] Key type dns_resolver registered
10576 00:40:09.994339 <6>[ 1.154268] registered taskstats version 1
10577 00:40:09.997929 <5>[ 1.154288] Loading compiled-in X.509 certificates
10578 00:40:10.007368 <4>[ 1.173188] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 00:40:10.017515 <4>[ 1.173355] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 00:40:10.024120 <3>[ 1.174768] mtk-msdc 11f60000.mmc: phase error: [map:0]
10581 00:40:10.031055 <3>[ 1.174774] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10582 00:40:10.037944 <3>[ 1.174777] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10583 00:40:10.040378 <3>[ 1.174784] mmc0: error -5 whilst initialising MMC card
10584 00:40:10.047407 <6>[ 1.182282] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10585 00:40:10.054101 <6>[ 1.182866] xhci-mtk 11200000.usb: xHCI Host Controller
10586 00:40:10.060646 <6>[ 1.182887] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10587 00:40:10.070458 <6>[ 1.183098] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10588 00:40:10.077759 <6>[ 1.183146] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10589 00:40:10.080446 <6>[ 1.183247] xhci-mtk 11200000.usb: xHCI Host Controller
10590 00:40:10.090274 <6>[ 1.183255] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10591 00:40:10.097298 <6>[ 1.183262] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10592 00:40:10.100232 <6>[ 1.183710] hub 1-0:1.0: USB hub found
10593 00:40:10.103696 <6>[ 1.183728] hub 1-0:1.0: 1 port detected
10594 00:40:10.113677 <6>[ 1.183912] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10595 00:40:10.117143 <6>[ 1.184246] hub 2-0:1.0: USB hub found
10596 00:40:10.120543 <6>[ 1.184260] hub 2-0:1.0: 1 port detected
10597 00:40:10.126861 <6>[ 1.187296] mtk-msdc 11f70000.mmc: Got CD GPIO
10598 00:40:10.133439 <6>[ 1.201587] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10599 00:40:10.143408 <6>[ 1.201597] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10600 00:40:10.150294 <4>[ 1.201766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10601 00:40:10.159585 <6>[ 1.202395] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10602 00:40:10.166547 <6>[ 1.202399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10603 00:40:10.175971 <6>[ 1.202516] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10604 00:40:10.182814 <6>[ 1.202527] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10605 00:40:10.189693 <6>[ 1.202531] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10606 00:40:10.199173 <6>[ 1.202536] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10607 00:40:10.209207 <6>[ 1.203964] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10608 00:40:10.215718 <6>[ 1.203980] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10609 00:40:10.225567 <6>[ 1.203985] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10610 00:40:10.232232 <6>[ 1.203991] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10611 00:40:10.242874 <6>[ 1.203996] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10612 00:40:10.249636 <6>[ 1.204002] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10613 00:40:10.258564 <6>[ 1.204007] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10614 00:40:10.265625 <6>[ 1.204013] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10615 00:40:10.275127 <6>[ 1.204018] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10616 00:40:10.281928 <6>[ 1.204024] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10617 00:40:10.292069 <6>[ 1.204029] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10618 00:40:10.298228 <6>[ 1.204035] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10619 00:40:10.308074 <6>[ 1.204040] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10620 00:40:10.314825 <6>[ 1.204046] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10621 00:40:10.324833 <6>[ 1.204051] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10622 00:40:10.331297 <6>[ 1.204566] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10623 00:40:10.337760 <6>[ 1.205542] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10624 00:40:10.344502 <6>[ 1.206103] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10625 00:40:10.351360 <6>[ 1.206736] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10626 00:40:10.357762 <6>[ 1.207340] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10627 00:40:10.367503 <6>[ 1.207538] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10628 00:40:10.377551 <6>[ 1.207553] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10629 00:40:10.384032 <6>[ 1.207559] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10630 00:40:10.394004 <6>[ 1.207565] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10631 00:40:10.404144 <6>[ 1.207571] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10632 00:40:10.413706 <6>[ 1.207578] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10633 00:40:10.423616 <6>[ 1.207584] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10634 00:40:10.429959 <6>[ 1.207590] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10635 00:40:10.440256 <6>[ 1.207598] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10636 00:40:10.449836 <6>[ 1.207606] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10637 00:40:10.459777 <6>[ 1.207610] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10638 00:40:10.470271 <6>[ 1.208196] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10639 00:40:10.477217 <6>[ 1.221384] Trying to probe devices needed for running init ...
10640 00:40:10.480109 <3>[ 1.270822] mtk-msdc 11f60000.mmc: phase error: [map:0]
10641 00:40:10.487038 <3>[ 1.270830] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10642 00:40:10.493237 <3>[ 1.270833] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10643 00:40:10.499583 <3>[ 1.270839] mmc0: error -5 whilst initialising MMC card
10644 00:40:10.506151 <6>[ 1.603392] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10645 00:40:10.512946 <6>[ 1.608793] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10646 00:40:10.515898 <6>[ 1.612040] mmc0: Command Queue Engine enabled
10647 00:40:10.522855 <6>[ 1.612055] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10648 00:40:10.529438 <6>[ 1.612796] mmcblk0: mmc0:0001 DA4128 116 GiB
10649 00:40:10.532786 <6>[ 1.616837] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10650 00:40:10.539008 <6>[ 1.618608] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10651 00:40:10.546102 <6>[ 1.619235] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10652 00:40:10.549230 <6>[ 1.619809] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10653 00:40:10.555716 <6>[ 1.764918] hub 1-1:1.0: USB hub found
10654 00:40:10.558779 <6>[ 1.765256] hub 1-1:1.0: 4 ports detected
10655 00:40:10.562266 <6>[ 1.768490] hub 1-1:1.0: USB hub found
10656 00:40:10.565177 <6>[ 1.768818] hub 1-1:1.0: 4 ports detected
10657 00:40:10.575319 <6>[ 1.897008] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10658 00:40:10.578690 <6>[ 1.921696] hub 2-1:1.0: USB hub found
10659 00:40:10.582152 <6>[ 1.922059] hub 2-1:1.0: 3 ports detected
10660 00:40:10.585469 <6>[ 1.924823] hub 2-1:1.0: USB hub found
10661 00:40:10.591919 <6>[ 1.925180] hub 2-1:1.0: 3 ports detected
10662 00:40:10.722426 <6>[ 2.081030] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10663 00:40:10.843440 <6>[ 2.207951] hub 1-1.4:1.0: USB hub found
10664 00:40:10.846763 <6>[ 2.208257] hub 1-1.4:1.0: 2 ports detected
10665 00:40:10.850107 <6>[ 2.210751] hub 1-1.4:1.0: USB hub found
10666 00:40:10.856596 <6>[ 2.211039] hub 1-1.4:1.0: 2 ports detected
10667 00:40:10.926643 <6>[ 2.285106] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10668 00:40:11.030663 <6>[ 2.389353] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10669 00:40:11.055059 <4>[ 2.412965] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10670 00:40:11.064408 <4>[ 2.412984] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10671 00:40:11.078965 <6>[ 2.441760] r8152 2-1.3:1.0 eth0: v1.12.13
10672 00:40:11.138458 <6>[ 2.497015] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10673 00:40:11.322518 <6>[ 2.681018] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10674 00:40:12.734543 <6>[ 4.097830] r8152 2-1.3:1.0 eth0: carrier on
10675 00:40:15.710948 <5>[ 4.128897] Sending DHCP requests .., OK
10676 00:40:15.717110 <6>[ 7.072877] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10677 00:40:15.720455 <6>[ 7.072895] IP-Config: Complete:
10678 00:40:15.733909 Loading, please <6>[ 7.072897] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10679 00:40:15.734379 wait...
10680 00:40:15.743563 <6>[ 7.072907] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10681 00:40:15.750502 <6>[ 7.072912] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10682 00:40:15.757156 Starting systemd<6>[ 7.072918] nameserver0=192.168.201.1
10683 00:40:15.763958 -udevd version 2<6>[ 7.073183] clk: Disabling unused clocks
10684 00:40:15.764487 52.22-1~deb12u1
10685 00:40:15.766713 <6>[ 7.074222] ALSA device list:
10686 00:40:15.767135
10687 00:40:15.769768 <6>[ 7.074234] No soundcards found.
10688 00:40:15.776943 <6>[ 7.078625] Freeing unused kernel memory: 8512K
10689 00:40:15.779706 <6>[ 7.078809] Run /init as init process
10690 00:40:16.033451 <6>[ 7.396239] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10691 00:40:16.040244 <6>[ 7.396380] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10692 00:40:16.050785 <6>[ 7.396403] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10693 00:40:16.057502 <6>[ 7.396664] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10694 00:40:16.063772 <6>[ 7.403216] remoteproc remoteproc0: scp is available
10695 00:40:16.070585 <6>[ 7.403409] remoteproc remoteproc0: powering up scp
10696 00:40:16.076616 <6>[ 7.403417] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10697 00:40:16.083623 <6>[ 7.403463] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10698 00:40:16.090335 <3>[ 7.432532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 00:40:16.100135 <3>[ 7.432547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 00:40:16.107039 <3>[ 7.432551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 00:40:16.113331 <4>[ 7.436539] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10702 00:40:16.123447 <4>[ 7.440365] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10703 00:40:16.129746 <3>[ 7.440749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 00:40:16.136590 <3>[ 7.440766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 00:40:16.146749 <3>[ 7.440770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 00:40:16.153237 <3>[ 7.440776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 00:40:16.163218 <3>[ 7.440780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 00:40:16.170369 <3>[ 7.454033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 00:40:16.176343 <6>[ 7.455866] mc: Linux media interface: v0.10
10710 00:40:16.183172 <3>[ 7.468220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 00:40:16.189718 <3>[ 7.468288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 00:40:16.200213 <3>[ 7.468301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 00:40:16.206622 <3>[ 7.492128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 00:40:16.216908 <3>[ 7.492181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 00:40:16.223875 <3>[ 7.492189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 00:40:16.230102 <3>[ 7.492199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 00:40:16.240008 <3>[ 7.492203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 00:40:16.246820 <3>[ 7.492265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 00:40:16.253003 <6>[ 7.497929] videodev: Linux video capture interface: v2.00
10720 00:40:16.259722 <6>[ 7.520834] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10721 00:40:16.266471 <6>[ 7.520852] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10722 00:40:16.273146 <6>[ 7.520853] pci_bus 0000:00: root bus resource [bus 00-ff]
10723 00:40:16.279739 <6>[ 7.520864] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10724 00:40:16.289542 <6>[ 7.520869] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10725 00:40:16.296182 <6>[ 7.520945] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10726 00:40:16.302636 <6>[ 7.520972] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10727 00:40:16.309875 <6>[ 7.521085] pci 0000:00:00.0: supports D1 D2
10728 00:40:16.315911 <6>[ 7.521091] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10729 00:40:16.322622 <6>[ 7.522857] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10730 00:40:16.329717 <6>[ 7.523017] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10731 00:40:16.339175 <6>[ 7.523051] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10732 00:40:16.345634 <6>[ 7.523071] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10733 00:40:16.352192 <6>[ 7.523090] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10734 00:40:16.355617 <6>[ 7.523215] pci 0000:01:00.0: supports D1 D2
10735 00:40:16.366084 <6>[ 7.523219] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10736 00:40:16.372312 <6>[ 7.530099] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10737 00:40:16.378969 <6>[ 7.530103] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10738 00:40:16.385481 <6>[ 7.530115] remoteproc remoteproc0: remote processor scp is now up
10739 00:40:16.392335 <6>[ 7.532921] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10740 00:40:16.401830 <6>[ 7.533004] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10741 00:40:16.408611 <6>[ 7.533012] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10742 00:40:16.418288 <6>[ 7.533029] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10743 00:40:16.424698 <6>[ 7.533045] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10744 00:40:16.431524 <6>[ 7.533060] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10745 00:40:16.438367 <6>[ 7.533081] pci 0000:00:00.0: PCI bridge to [bus 01]
10746 00:40:16.445265 <6>[ 7.533090] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10747 00:40:16.451615 <6>[ 7.533329] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10748 00:40:16.457959 <6>[ 7.534557] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10749 00:40:16.467817 <6>[ 7.534722] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10750 00:40:16.471145 <6>[ 7.534902] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10751 00:40:16.481160 <6>[ 7.536000] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10752 00:40:16.491442 <4>[ 7.551029] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10753 00:40:16.494218 <4>[ 7.551029] Fallback method does not support PEC.
10754 00:40:16.504437 <6>[ 7.552993] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10755 00:40:16.514058 <6>[ 7.557503] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10756 00:40:16.524334 <6>[ 7.557691] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10757 00:40:16.530534 <3>[ 7.567826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10758 00:40:16.540404 <5>[ 7.581422] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10759 00:40:16.543765 <6>[ 7.587466] Bluetooth: Core ver 2.22
10760 00:40:16.550081 <6>[ 7.587542] NET: Registered PF_BLUETOOTH protocol family
10761 00:40:16.556846 <6>[ 7.587544] Bluetooth: HCI device and connection manager initialized
10762 00:40:16.560362 <6>[ 7.587563] Bluetooth: HCI socket layer initialized
10763 00:40:16.567179 <6>[ 7.587573] Bluetooth: L2CAP socket layer initialized
10764 00:40:16.570068 <6>[ 7.587587] Bluetooth: SCO socket layer initialized
10765 00:40:16.576646 <5>[ 7.595074] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10766 00:40:16.586891 <5>[ 7.595393] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10767 00:40:16.596828 <4>[ 7.595457] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10768 00:40:16.600373 <6>[ 7.595464] cfg80211: failed to load regulatory.db
10769 00:40:16.609883 <3>[ 7.602802] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10770 00:40:16.616958 <6>[ 7.633358] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10771 00:40:16.629655 <6>[ 7.634604] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10772 00:40:16.633253 <6>[ 7.634702] usbcore: registered new interface driver uvcvideo
10773 00:40:16.639948 <6>[ 7.645726] usbcore: registered new interface driver btusb
10774 00:40:16.649609 <4>[ 7.646666] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10775 00:40:16.656114 <3>[ 7.646677] Bluetooth: hci0: Failed to load firmware file (-2)
10776 00:40:16.662811 <3>[ 7.646678] Bluetooth: hci0: Failed to set up firmware (-2)
10777 00:40:16.672576 <4>[ 7.646682] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10778 00:40:16.679184 <6>[ 7.662940] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10779 00:40:16.685621 <6>[ 7.696464] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10780 00:40:16.692596 <6>[ 7.696568] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10781 00:40:16.698417 <6>[ 7.716897] mt7921e 0000:01:00.0: ASIC revision: 79610010
10782 00:40:16.705433 <6>[ 7.815630] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10783 00:40:16.708257 <6>[ 7.815630]
10784 00:40:16.718454 <6>[ 8.071917] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10785 00:40:16.722037 Begin: Loading essential drivers ... done.
10786 00:40:16.725188 Begin: Running /scripts/init-premount ... done.
10787 00:40:16.731999 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10788 00:40:16.741644 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10789 00:40:16.745307 Device /sys/class/net/eth0 found
10790 00:40:16.745729 done.
10791 00:40:16.751630 Begin: Waiting up to 180 secs for any network device to become available ... done.
10792 00:40:16.782536 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10793 00:40:16.789211 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10794 00:40:16.796415 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10795 00:40:16.802823 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10796 00:40:16.808975 host : mt8192-asurada-spherion-r0-cbg-9
10797 00:40:16.815566 domain : lava-rack
10798 00:40:16.818990 rootserver: 192.168.201.1 rootpath:
10799 00:40:16.822063 filename :
10800 00:40:16.963298 done.
10801 00:40:16.971161 Begin: Running /scripts/nfs-bottom ... done.
10802 00:40:16.988329 Begin: Running /scripts/init-bottom ... done.
10803 00:40:18.342110 <6>[ 9.705827] NET: Registered PF_INET6 protocol family
10804 00:40:18.345325 <6>[ 9.707932] Segment Routing with IPv6
10805 00:40:18.352002 <6>[ 9.707959] In-situ OAM (IOAM) with IPv6
10806 00:40:18.524181 <30>[ 9.857731] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10807 00:40:18.527156 <30>[ 9.857771] systemd[1]: Detected architecture arm64.
10808 00:40:18.527683
10809 00:40:18.533751 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10810 00:40:18.534384
10811 00:40:18.558339 <30>[ 9.922902] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10812 00:40:19.745201 <30>[ 11.106610] systemd[1]: Queued start job for default target graphical.target.
10813 00:40:19.765880 [[0;32m OK [0m] Created slic<30>[ 11.125666] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10814 00:40:19.769119 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10815 00:40:19.794960 [[0;32m OK [0m] Created slic<30>[ 11.154810] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10816 00:40:19.798089 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10817 00:40:19.822557 [[0;32m OK [0m] Created slic<30>[ 11.182784] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10818 00:40:19.829025 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10819 00:40:19.850317 [[0;32m OK [0m] Created slic<30>[ 11.210317] systemd[1]: Created slice user.slice - User and Session Slice.
10820 00:40:19.853349 e [0;1;39muser.slice[0m - User and Session Slice.
10821 00:40:19.881707 [[0;32m OK [0m] Started [0;<30>[ 11.238274] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10822 00:40:19.884833 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10823 00:40:19.912344 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 11.269401] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10824 00:40:19.915364 -passwo… Requests to Wall Directory Watch.
10825 00:40:19.950340 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 11.297156] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10826 00:40:19.957391 <30>[ 11.297284] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10827 00:40:19.959876 ice[0m - /dev/ttyS0...
10828 00:40:19.981019 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 11.341341] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10829 00:40:19.984496 tsetup.…get[0m - Local Encrypted Volumes.
10830 00:40:20.008276 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 11.365016] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10831 00:40:20.010996 grityse…Local Integrity Protected Volumes.
10832 00:40:20.033334 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 11.393413] systemd[1]: Reached target paths.target - Path Units.
10833 00:40:20.033455 s.target[0m - Path Units.
10834 00:40:20.057457 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 11.417481] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10835 00:40:20.060512 te-fs.target[0m - Remote File Systems.
10836 00:40:20.080546 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 11.440996] systemd[1]: Reached target slices.target - Slice Units.
10837 00:40:20.083676 es.target[0m - Slice Units.
10838 00:40:20.105122 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 11.465520] systemd[1]: Reached target swap.target - Swaps.
10839 00:40:20.105233 .target[0m - Swaps.
10840 00:40:20.129341 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 11.489484] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10841 00:40:20.135836 tysetup… - Local Verity Protected Volumes.
10842 00:40:20.157756 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.517469] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10843 00:40:20.163842 d-initc… initctl Compatibility Named Pipe.
10844 00:40:20.189314 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.549208] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10845 00:40:20.196330 d-journ…socket[0m - Journal Audit Socket.
10846 00:40:20.218397 [[0;32m OK [0m] Listening on<30>[ 11.578707] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10847 00:40:20.225298 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10848 00:40:20.245769 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.605761] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10849 00:40:20.249142 d-journald.socket[0m - Journal Socket.
10850 00:40:20.270914 [[0;32m OK [0m] Listening on<30>[ 11.630697] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10851 00:40:20.277555 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10852 00:40:20.301382 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.661429] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10853 00:40:20.308420 d-udevd….socket[0m - udev Control Socket.
10854 00:40:20.329569 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.689527] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10855 00:40:20.335988 d-udevd…l.socket[0m - udev Kernel Socket.
10856 00:40:20.389361 Mounting [0;1;39mdev-hugepages.mount[<30>[ 11.749423] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10857 00:40:20.392839 0m - Huge Pages File System...
10858 00:40:20.411751 Mountin<30>[ 11.775361] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10859 00:40:20.418394 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10860 00:40:20.444960 Mounting [0;1;39msys-kernel-debug.…<30>[ 11.804851] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10861 00:40:20.448466 [0m - Kernel Debug File System...
10862 00:40:20.475753 <30>[ 11.829691] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10863 00:40:20.485732 <30>[ 11.837118] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10864 00:40:20.492502 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10865 00:40:20.521378 Starting [0;1;39mmodprobe@configfs…m<30>[ 11.880755] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10866 00:40:20.524595 - Load Kernel Module configfs...
10867 00:40:20.554505 Starting [0;1;39mmodpr<30>[ 11.914688] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10868 00:40:20.557585 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10869 00:40:20.584237 Startin<30>[ 11.948020] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10870 00:40:20.598009 g [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 11.959080] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10871 00:40:20.600792 l Module drm...
10872 00:40:20.627028 Starting [0;1;39mmodpr<30>[ 11.987049] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10873 00:40:20.630510 obe@efi_psto…- Load Kernel Module efi_pstore...
10874 00:40:20.658446 Starting [0;1;39mmodpr<30>[ 12.018726] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10875 00:40:20.662074 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10876 00:40:20.693889 <6>[ 12.060436] fuse: init (API version 7.37)
10877 00:40:20.721946 Starting [0;1;39mmodpr<30>[ 12.081873] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10878 00:40:20.724952 obe@loop.ser…e[0m - Load Kernel Module loop...
10879 00:40:20.756729 Startin<30>[ 12.119434] systemd[1]: Starting systemd-journald.service - Journal Service...
10880 00:40:20.762722 g [0;1;39msystemd-journald.service[0m - Journal Service...
10881 00:40:20.857535 Starting [0;1;39msyste<30>[ 12.218260] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10882 00:40:20.860953 md-modules-l…rvice[0m - Load Kernel Modules...
10883 00:40:20.893426 Starting [0;1;39msyste<30>[ 12.249881] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10884 00:40:20.896506 md-network-g… units from Kernel command line...
10885 00:40:20.927897 Startin<30>[ 12.287149] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10886 00:40:20.937354 g [0;1;39msyste<3>[ 12.294931] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 00:40:20.940730 md-remount-f…nt Root and Kernel File Systems...
10888 00:40:20.965084 <3>[ 12.328084] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 00:40:20.974826 <30>[ 12.332118] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10890 00:40:20.981233 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10891 00:40:20.996716 <3>[ 12.360254] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 00:40:21.025022 [[0;32m OK [<3>[ 12.382523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 00:40:21.031245 0m] Mounted [0;<30>[ 12.384404] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10894 00:40:21.041610 1;39mdev-hugepag<3>[ 12.402617] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 00:40:21.044146 es.mount[0m - Huge Pages File System.
10896 00:40:21.065151 <3>[ 12.424822] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 00:40:21.074842 <30>[ 12.429560] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10898 00:40:21.081464 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10899 00:40:21.101218 <3>[ 12.461476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 00:40:21.107809 <30>[ 12.465611] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10901 00:40:21.118261 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10902 00:40:21.125135 <3>[ 12.484895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 00:40:21.141705 [[0;32m OK [0m] Finished [0;1;39mkmod-stati<30>[ 12.501628] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10904 00:40:21.148453 c-nodes…reate List of Static Device Nodes.
10905 00:40:21.169794 [[0;32m OK [0m] Finished [0<30>[ 12.529713] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10906 00:40:21.180000 ;1;39mmodprobe@c<30>[ 12.530391] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10907 00:40:21.183563 onfigfs…[0m - Load Kernel Module configfs.
10908 00:40:21.209373 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 12.569437] systemd[1]: Started systemd-journald.service - Journal Service.
10909 00:40:21.212552 rnald.service[0m - Journal Service.
10910 00:40:21.238392 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10911 00:40:21.264424 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10912 00:40:21.288309 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10913 00:40:21.310979 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10914 00:40:21.330587 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10915 00:40:21.351406 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10916 00:40:21.375475 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10917 00:40:21.399627 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10918 00:40:21.424028 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10919 00:40:21.441636 <4>[ 12.804918] power_supply_show_property: 2 callbacks suppressed
10920 00:40:21.452323 <3>[ 12.804932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 00:40:21.468379 <4>[ 12.804945] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10922 00:40:21.475650 <3>[ 12.804947] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10923 00:40:21.482645 <3>[ 12.829654] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 00:40:21.492316 <3>[ 12.851731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 00:40:21.502906 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10926 00:40:21.513169 <3>[ 12.873282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 00:40:21.536148 Mountin<3>[ 12.896156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 00:40:21.539172 g [0;1;39msys-kernel-config…ernel Configuration File System...
10929 00:40:21.556820 <3>[ 12.917850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 00:40:21.581359 <3>[ 12.943714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 00:40:21.594465 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10932 00:40:21.605165 <3>[ 12.966733] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 00:40:21.626690 Starting [0;1;39msyste<3>[ 12.986549] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 00:40:21.629649 md-random-se…ice[0m - Load/Save Random Seed...
10935 00:40:21.656876 <3>[ 13.020298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 00:40:21.701098 <46>[ 13.063622] systemd-journald[318]: Received client request to flush runtime journal.
10937 00:40:21.707989 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10938 00:40:21.730954 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10939 00:40:22.011034 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10940 00:40:22.030443 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10941 00:40:22.049623 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10942 00:40:22.066235 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10943 00:40:22.738374 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10944 00:40:23.096528 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10945 00:40:23.118135 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10946 00:40:23.181347 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10947 00:40:23.283095 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10948 00:40:23.305594 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10949 00:40:23.320811 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10950 00:40:23.365809 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10951 00:40:23.389805 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10952 00:40:23.605144 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10953 00:40:23.651892 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10954 00:40:23.737410 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10955 00:40:24.022590 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10956 00:40:24.045356 <6>[ 15.410034] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10957 00:40:24.084986 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10958 00:40:24.166803 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10959 00:40:24.217572 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10960 00:40:24.239350 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10961 00:40:24.259007 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10962 00:40:24.301681 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10963 00:40:24.382830 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10964 00:40:24.406529 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10965 00:40:24.425578 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10966 00:40:24.451008 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10967 00:40:24.486417 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10968 00:40:24.529684 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10969 00:40:24.627079 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10970 00:40:24.645592 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10971 00:40:24.665727 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10972 00:40:24.684846 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10973 00:40:24.720925 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10974 00:40:24.741040 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10975 00:40:24.757481 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10976 00:40:24.776748 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10977 00:40:24.797438 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10978 00:40:24.813036 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10979 00:40:24.831368 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10980 00:40:24.849363 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10981 00:40:24.855508 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10982 00:40:24.906925 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10983 00:40:24.939565 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10984 00:40:25.008857 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10985 00:40:25.028987 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10986 00:40:25.190497 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10987 00:40:25.260693 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10988 00:40:25.303315 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10989 00:40:25.322342 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10990 00:40:25.349612 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10991 00:40:25.366726 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10992 00:40:25.402623 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10993 00:40:25.422090 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10994 00:40:25.440444 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10995 00:40:25.507921 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10996 00:40:25.556292 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10997 00:40:25.646902
10998 00:40:25.650211 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10999 00:40:25.650754
11000 00:40:25.653188 debian-bookworm-arm64 login: root (automatic login)
11001 00:40:25.653720
11002 00:40:25.950902 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
11003 00:40:25.951057
11004 00:40:25.957054 The programs included with the Debian GNU/Linux system are free software;
11005 00:40:25.963719 the exact distribution terms for each program are described in the
11006 00:40:25.967289 individual files in /usr/share/doc/*/copyright.
11007 00:40:25.967392
11008 00:40:25.973859 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11009 00:40:25.976958 permitted by applicable law.
11010 00:40:27.105859 Matched prompt #10: / #
11012 00:40:27.106265 Setting prompt string to ['/ #']
11013 00:40:27.106411 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11015 00:40:27.106729 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11016 00:40:27.106867 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11017 00:40:27.106981 Setting prompt string to ['/ #']
11018 00:40:27.107079 Forcing a shell prompt, looking for ['/ #']
11020 00:40:27.157432 / #
11021 00:40:27.157937 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11022 00:40:27.158346 Waiting using forced prompt support (timeout 00:02:30)
11023 00:40:27.163406
11024 00:40:27.164154 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 00:40:27.164625 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11027 00:40:27.265719 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf'
11028 00:40:27.272021 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173479/extract-nfsrootfs-mdlb1yrf'
11030 00:40:27.373540 / # export NFS_SERVER_IP='192.168.201.1'
11031 00:40:27.379556 export NFS_SERVER_IP='192.168.201.1'
11032 00:40:27.380377 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11033 00:40:27.380936 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11034 00:40:27.381455 end: 2 depthcharge-action (duration 00:01:39) [common]
11035 00:40:27.381978 start: 3 lava-test-retry (timeout 00:07:37) [common]
11036 00:40:27.382537 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
11037 00:40:27.383003 Using namespace: common
11039 00:40:27.484197 / # #
11040 00:40:27.484772 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11041 00:40:27.490234 #
11042 00:40:27.490984 Using /lava-14173479
11044 00:40:27.592190 / # export SHELL=/bin/bash
11045 00:40:27.598244 export SHELL=/bin/bash
11047 00:40:27.699674 / # . /lava-14173479/environment
11048 00:40:27.705626 . /lava-14173479/environment
11050 00:40:27.812739 / # /lava-14173479/bin/lava-test-runner /lava-14173479/0
11051 00:40:27.812959 Test shell timeout: 10s (minimum of the action and connection timeout)
11052 00:40:27.818583 /lava-14173479/bin/lava-test-runner /lava-14173479/0
11053 00:40:28.094989 + export TESTRUN_ID=0_timesync-off
11054 00:40:28.098043 + TESTRUN_ID=0_timesync-off
11055 00:40:28.101185 + cd /lava-14173479/0/tests/0_timesync-off
11056 00:40:28.105004 ++ cat uuid
11057 00:40:28.109260 + UUID=14173479_1.6.2.3.1
11058 00:40:28.109416 + set +x
11059 00:40:28.115869 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14173479_1.6.2.3.1>
11060 00:40:28.116134 Received signal: <STARTRUN> 0_timesync-off 14173479_1.6.2.3.1
11061 00:40:28.116208 Starting test lava.0_timesync-off (14173479_1.6.2.3.1)
11062 00:40:28.116296 Skipping test definition patterns.
11063 00:40:28.118873 + systemctl stop systemd-timesyncd
11064 00:40:28.189653 + set +x
11065 00:40:28.193288 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14173479_1.6.2.3.1>
11066 00:40:28.193547 Received signal: <ENDRUN> 0_timesync-off 14173479_1.6.2.3.1
11067 00:40:28.193632 Ending use of test pattern.
11068 00:40:28.193694 Ending test lava.0_timesync-off (14173479_1.6.2.3.1), duration 0.08
11070 00:40:28.275491 + export TESTRUN_ID=1_kselftest-dt
11071 00:40:28.278358 + TESTRUN_ID=1_kselftest-dt
11072 00:40:28.282214 + cd /lava-14173479/0/tests/1_kselftest-dt
11073 00:40:28.285357 ++ cat uuid
11074 00:40:28.289865 + UUID=14173479_1.6.2.3.5
11075 00:40:28.289948 + set +x
11076 00:40:28.296802 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14173479_1.6.2.3.5>
11077 00:40:28.297060 Received signal: <STARTRUN> 1_kselftest-dt 14173479_1.6.2.3.5
11078 00:40:28.297133 Starting test lava.1_kselftest-dt (14173479_1.6.2.3.5)
11079 00:40:28.297215 Skipping test definition patterns.
11080 00:40:28.299542 + cd ./automated/linux/kselftest/
11081 00:40:28.326056 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11082 00:40:28.371231 INFO: install_deps skipped
11083 00:40:28.880676 --2024-06-05 00:40:28-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11084 00:40:28.886736 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11085 00:40:29.011786 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11086 00:40:29.144499 HTTP request sent, awaiting response... 200 OK
11087 00:40:29.147507 Length: 1648104 (1.6M) [application/octet-stream]
11088 00:40:29.150881 Saving to: 'kselftest_armhf.tar.gz'
11089 00:40:29.151351
11090 00:40:29.151723
11091 00:40:29.402746 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11092 00:40:29.661302 kselftest_armhf.tar 2%[ ] 47.81K 183KB/s
11093 00:40:29.966210 kselftest_armhf.tar 13%[=> ] 217.50K 416KB/s
11094 00:40:30.097806 kselftest_armhf.tar 51%[=========> ] 824.13K 990KB/s
11095 00:40:30.104267 kselftest_armhf.tar 100%[===================>] 1.57M 1.63MB/s in 1.0s
11096 00:40:30.104369
11097 00:40:30.249314 2024-06-05 00:40:29 (1.63 MB/s) - 'kselftest_armhf.tar.gz' saved [1648104/1648104]
11098 00:40:30.249469
11099 00:40:35.320900 skiplist:
11100 00:40:35.324182 ========================================
11101 00:40:35.327104 ========================================
11102 00:40:35.407989 ============== Tests to run ===============
11103 00:40:35.414395 ===========End Tests to run ===============
11104 00:40:35.418987 shardfile-dt fail
11105 00:40:35.446243 ./kselftest.sh: 131: cannot open /lava-14173479/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11106 00:40:35.449504 + ../../utils/send-to-lava.sh ./output/result.txt
11107 00:40:35.537931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11108 00:40:35.538609 + set +x
11109 00:40:35.539241 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11111 00:40:35.544409 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14173479_1.6.2.3.5>
11112 00:40:35.545092 Received signal: <ENDRUN> 1_kselftest-dt 14173479_1.6.2.3.5
11113 00:40:35.545456 Ending use of test pattern.
11114 00:40:35.545761 Ending test lava.1_kselftest-dt (14173479_1.6.2.3.5), duration 7.25
11116 00:40:35.546896 ok: lava_test_shell seems to have completed
11117 00:40:35.547491 shardfile-dt: fail
11118 00:40:35.547913 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11119 00:40:35.548330 end: 3 lava-test-retry (duration 00:00:08) [common]
11120 00:40:35.548754 start: 4 finalize (timeout 00:07:29) [common]
11121 00:40:35.549192 start: 4.1 power-off (timeout 00:00:30) [common]
11122 00:40:35.549941 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11123 00:40:35.809782 >> Command sent successfully.
11124 00:40:35.821064 Returned 0 in 0 seconds
11125 00:40:35.922316 end: 4.1 power-off (duration 00:00:00) [common]
11127 00:40:35.923789 start: 4.2 read-feedback (timeout 00:07:28) [common]
11129 00:40:35.926019 Listened to connection for namespace 'common' for up to 1s
11130 00:40:36.925821 Finalising connection for namespace 'common'
11131 00:40:36.926532 Disconnecting from shell: Finalise
11132 00:40:36.926954 / #
11133 00:40:37.028062 end: 4.2 read-feedback (duration 00:00:01) [common]
11134 00:40:37.028840 end: 4 finalize (duration 00:00:01) [common]
11135 00:40:37.029460 Cleaning after the job
11136 00:40:37.030003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/ramdisk
11137 00:40:37.040429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/kernel
11138 00:40:37.072176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/dtb
11139 00:40:37.072532 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/nfsrootfs
11140 00:40:37.141212 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173479/tftp-deploy-dv0tiued/modules
11141 00:40:37.146779 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173479
11142 00:40:37.707367 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173479
11143 00:40:37.707547 Job finished correctly