Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 01:31:28.052272 lava-dispatcher, installed at version: 2024.03
2 01:31:28.052476 start: 0 validate
3 01:31:28.052618 Start time: 2024-06-05 01:31:28.052610+00:00 (UTC)
4 01:31:28.052736 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:31:28.052868 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:31:28.319068 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:31:28.319875 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:31:28.582769 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:31:28.583508 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:31:28.842614 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:31:28.843293 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:31:29.106263 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:31:29.107052 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:31:29.378726 validate duration: 1.33
16 01:31:29.380035 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:31:29.380612 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:31:29.381088 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:31:29.381722 Not decompressing ramdisk as can be used compressed.
20 01:31:29.382187 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:31:29.382569 saving as /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/ramdisk/initrd.cpio.gz
22 01:31:29.382931 total size: 5628169 (5 MB)
23 01:31:29.388550 progress 0 % (0 MB)
24 01:31:29.397316 progress 5 % (0 MB)
25 01:31:29.404011 progress 10 % (0 MB)
26 01:31:29.408368 progress 15 % (0 MB)
27 01:31:29.412236 progress 20 % (1 MB)
28 01:31:29.415473 progress 25 % (1 MB)
29 01:31:29.418354 progress 30 % (1 MB)
30 01:31:29.421085 progress 35 % (1 MB)
31 01:31:29.423230 progress 40 % (2 MB)
32 01:31:29.425672 progress 45 % (2 MB)
33 01:31:29.427582 progress 50 % (2 MB)
34 01:31:29.429767 progress 55 % (2 MB)
35 01:31:29.431740 progress 60 % (3 MB)
36 01:31:29.433415 progress 65 % (3 MB)
37 01:31:29.435297 progress 70 % (3 MB)
38 01:31:29.436845 progress 75 % (4 MB)
39 01:31:29.438589 progress 80 % (4 MB)
40 01:31:29.440125 progress 85 % (4 MB)
41 01:31:29.441763 progress 90 % (4 MB)
42 01:31:29.443400 progress 95 % (5 MB)
43 01:31:29.444799 progress 100 % (5 MB)
44 01:31:29.445005 5 MB downloaded in 0.06 s (86.44 MB/s)
45 01:31:29.445156 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:31:29.445410 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:31:29.445496 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:31:29.445581 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:31:29.445725 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:31:29.445792 saving as /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/kernel/Image
52 01:31:29.445852 total size: 54682112 (52 MB)
53 01:31:29.445912 No compression specified
54 01:31:29.447024 progress 0 % (0 MB)
55 01:31:29.460691 progress 5 % (2 MB)
56 01:31:29.474673 progress 10 % (5 MB)
57 01:31:29.488534 progress 15 % (7 MB)
58 01:31:29.502174 progress 20 % (10 MB)
59 01:31:29.516076 progress 25 % (13 MB)
60 01:31:29.529760 progress 30 % (15 MB)
61 01:31:29.543591 progress 35 % (18 MB)
62 01:31:29.557177 progress 40 % (20 MB)
63 01:31:29.570818 progress 45 % (23 MB)
64 01:31:29.584609 progress 50 % (26 MB)
65 01:31:29.598227 progress 55 % (28 MB)
66 01:31:29.611851 progress 60 % (31 MB)
67 01:31:29.625497 progress 65 % (33 MB)
68 01:31:29.639267 progress 70 % (36 MB)
69 01:31:29.652929 progress 75 % (39 MB)
70 01:31:29.666773 progress 80 % (41 MB)
71 01:31:29.680386 progress 85 % (44 MB)
72 01:31:29.693979 progress 90 % (46 MB)
73 01:31:29.707711 progress 95 % (49 MB)
74 01:31:29.721121 progress 100 % (52 MB)
75 01:31:29.721392 52 MB downloaded in 0.28 s (189.26 MB/s)
76 01:31:29.721543 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:31:29.721778 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:31:29.721864 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:31:29.721947 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:31:29.722079 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:31:29.722154 saving as /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/dtb/mt8192-asurada-spherion-r0.dtb
83 01:31:29.722214 total size: 47258 (0 MB)
84 01:31:29.722274 No compression specified
85 01:31:29.723391 progress 69 % (0 MB)
86 01:31:29.723677 progress 100 % (0 MB)
87 01:31:29.723830 0 MB downloaded in 0.00 s (27.92 MB/s)
88 01:31:29.723950 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:31:29.724170 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:31:29.724254 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:31:29.724336 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:31:29.724447 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:31:29.724513 saving as /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/nfsrootfs/full.rootfs.tar
95 01:31:29.724572 total size: 120894716 (115 MB)
96 01:31:29.724633 Using unxz to decompress xz
97 01:31:29.728590 progress 0 % (0 MB)
98 01:31:30.068630 progress 5 % (5 MB)
99 01:31:30.418348 progress 10 % (11 MB)
100 01:31:30.767036 progress 15 % (17 MB)
101 01:31:31.089167 progress 20 % (23 MB)
102 01:31:31.378802 progress 25 % (28 MB)
103 01:31:31.733163 progress 30 % (34 MB)
104 01:31:32.072346 progress 35 % (40 MB)
105 01:31:32.234970 progress 40 % (46 MB)
106 01:31:32.410108 progress 45 % (51 MB)
107 01:31:32.713304 progress 50 % (57 MB)
108 01:31:33.092554 progress 55 % (63 MB)
109 01:31:33.437811 progress 60 % (69 MB)
110 01:31:33.771362 progress 65 % (74 MB)
111 01:31:34.106870 progress 70 % (80 MB)
112 01:31:34.464452 progress 75 % (86 MB)
113 01:31:34.802018 progress 80 % (92 MB)
114 01:31:35.134144 progress 85 % (98 MB)
115 01:31:35.482771 progress 90 % (103 MB)
116 01:31:35.812176 progress 95 % (109 MB)
117 01:31:36.160905 progress 100 % (115 MB)
118 01:31:36.166334 115 MB downloaded in 6.44 s (17.90 MB/s)
119 01:31:36.166581 end: 1.4.1 http-download (duration 00:00:06) [common]
121 01:31:36.166842 end: 1.4 download-retry (duration 00:00:06) [common]
122 01:31:36.166936 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:31:36.167021 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:31:36.167169 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:31:36.167239 saving as /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/modules/modules.tar
126 01:31:36.167299 total size: 8605984 (8 MB)
127 01:31:36.167362 Using unxz to decompress xz
128 01:31:36.171552 progress 0 % (0 MB)
129 01:31:36.190189 progress 5 % (0 MB)
130 01:31:36.216924 progress 10 % (0 MB)
131 01:31:36.246321 progress 15 % (1 MB)
132 01:31:36.269547 progress 20 % (1 MB)
133 01:31:36.292860 progress 25 % (2 MB)
134 01:31:36.316123 progress 30 % (2 MB)
135 01:31:36.340076 progress 35 % (2 MB)
136 01:31:36.366520 progress 40 % (3 MB)
137 01:31:36.388890 progress 45 % (3 MB)
138 01:31:36.412461 progress 50 % (4 MB)
139 01:31:36.436921 progress 55 % (4 MB)
140 01:31:36.461014 progress 60 % (4 MB)
141 01:31:36.484923 progress 65 % (5 MB)
142 01:31:36.509312 progress 70 % (5 MB)
143 01:31:36.532641 progress 75 % (6 MB)
144 01:31:36.559864 progress 80 % (6 MB)
145 01:31:36.583937 progress 85 % (7 MB)
146 01:31:36.608998 progress 90 % (7 MB)
147 01:31:36.633961 progress 95 % (7 MB)
148 01:31:36.658635 progress 100 % (8 MB)
149 01:31:36.663925 8 MB downloaded in 0.50 s (16.53 MB/s)
150 01:31:36.664217 end: 1.5.1 http-download (duration 00:00:00) [common]
152 01:31:36.664618 end: 1.5 download-retry (duration 00:00:00) [common]
153 01:31:36.664743 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:31:36.664881 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:31:40.095245 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l
156 01:31:40.095450 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 01:31:40.095548 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:31:40.095713 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih
159 01:31:40.095841 makedir: /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin
160 01:31:40.095939 makedir: /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/tests
161 01:31:40.096036 makedir: /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/results
162 01:31:40.096134 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-add-keys
163 01:31:40.096276 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-add-sources
164 01:31:40.096402 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-background-process-start
165 01:31:40.096526 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-background-process-stop
166 01:31:40.096649 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-common-functions
167 01:31:40.096770 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-echo-ipv4
168 01:31:40.096892 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-install-packages
169 01:31:40.097012 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-installed-packages
170 01:31:40.097132 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-os-build
171 01:31:40.097254 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-probe-channel
172 01:31:40.097418 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-probe-ip
173 01:31:40.097540 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-target-ip
174 01:31:40.097660 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-target-mac
175 01:31:40.097780 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-target-storage
176 01:31:40.097905 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-case
177 01:31:40.098027 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-event
178 01:31:40.098148 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-feedback
179 01:31:40.098268 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-raise
180 01:31:40.098387 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-reference
181 01:31:40.098508 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-runner
182 01:31:40.098627 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-set
183 01:31:40.098750 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-test-shell
184 01:31:40.098871 Updating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-add-keys (debian)
185 01:31:40.099017 Updating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-add-sources (debian)
186 01:31:40.099153 Updating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-install-packages (debian)
187 01:31:40.099286 Updating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-installed-packages (debian)
188 01:31:40.099417 Updating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/bin/lava-os-build (debian)
189 01:31:40.099533 Creating /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/environment
190 01:31:40.099627 LAVA metadata
191 01:31:40.099690 - LAVA_JOB_ID=14173483
192 01:31:40.099751 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:31:40.099847 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:31:40.099912 skipped lava-vland-overlay
195 01:31:40.099984 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:31:40.100060 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:31:40.100121 skipped lava-multinode-overlay
198 01:31:40.100191 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:31:40.100266 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:31:40.100347 Loading test definitions
201 01:31:40.100434 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:31:40.100503 Using /lava-14173483 at stage 0
203 01:31:40.100773 uuid=14173483_1.6.2.3.1 testdef=None
204 01:31:40.100859 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:31:40.100941 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:31:40.101561 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:31:40.101787 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:31:40.102348 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:31:40.102576 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:31:40.103098 runner path: /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/0/tests/0_timesync-off test_uuid 14173483_1.6.2.3.1
213 01:31:40.103253 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:31:40.103474 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:31:40.103546 Using /lava-14173483 at stage 0
217 01:31:40.103640 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:31:40.103727 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/0/tests/1_kselftest-rtc'
219 01:31:42.351087 Running '/usr/bin/git checkout kernelci.org
220 01:31:42.497805 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 01:31:42.498524 uuid=14173483_1.6.2.3.5 testdef=None
222 01:31:42.498683 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 01:31:42.498920 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 01:31:42.499648 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:31:42.499875 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 01:31:42.500831 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:31:42.501098 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 01:31:42.502207 runner path: /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/0/tests/1_kselftest-rtc test_uuid 14173483_1.6.2.3.5
232 01:31:42.502298 BOARD='mt8192-asurada-spherion-r0'
233 01:31:42.502361 BRANCH='cip-gitlab'
234 01:31:42.502419 SKIPFILE='/dev/null'
235 01:31:42.502475 SKIP_INSTALL='True'
236 01:31:42.502530 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:31:42.502586 TST_CASENAME=''
238 01:31:42.502639 TST_CMDFILES='rtc'
239 01:31:42.502775 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:31:42.502977 Creating lava-test-runner.conf files
242 01:31:42.503039 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173483/lava-overlay-c065ulih/lava-14173483/0 for stage 0
243 01:31:42.503131 - 0_timesync-off
244 01:31:42.503198 - 1_kselftest-rtc
245 01:31:42.503292 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 01:31:42.503378 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 01:31:49.901827 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 01:31:49.901989 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 01:31:49.902082 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:31:49.902179 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 01:31:49.902292 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 01:31:50.067986 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:31:50.068386 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 01:31:50.068497 extracting modules file /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l
255 01:31:50.281889 extracting modules file /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173483/extract-overlay-ramdisk-uvusljr3/ramdisk
256 01:31:50.498961 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:31:50.499131 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 01:31:50.499226 [common] Applying overlay to NFS
259 01:31:50.499299 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173483/compress-overlay-y8b215k8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l
260 01:31:51.402057 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:31:51.402226 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 01:31:51.402323 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:31:51.402409 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 01:31:51.402490 Building ramdisk /var/lib/lava/dispatcher/tmp/14173483/extract-overlay-ramdisk-uvusljr3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173483/extract-overlay-ramdisk-uvusljr3/ramdisk
265 01:31:51.753063 >> 130348 blocks
266 01:31:53.763472 rename /var/lib/lava/dispatcher/tmp/14173483/extract-overlay-ramdisk-uvusljr3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/ramdisk/ramdisk.cpio.gz
267 01:31:53.763952 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:31:53.764080 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 01:31:53.764181 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 01:31:53.764290 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/kernel/Image']
271 01:32:06.479239 Returned 0 in 12 seconds
272 01:32:06.580318 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/kernel/image.itb
273 01:32:07.007569 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:32:07.007932 output: Created: Wed Jun 5 02:32:06 2024
275 01:32:07.008004 output: Image 0 (kernel-1)
276 01:32:07.008069 output: Description:
277 01:32:07.008131 output: Created: Wed Jun 5 02:32:06 2024
278 01:32:07.008195 output: Type: Kernel Image
279 01:32:07.008255 output: Compression: lzma compressed
280 01:32:07.008316 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
281 01:32:07.008375 output: Architecture: AArch64
282 01:32:07.008434 output: OS: Linux
283 01:32:07.008490 output: Load Address: 0x00000000
284 01:32:07.008545 output: Entry Point: 0x00000000
285 01:32:07.008600 output: Hash algo: crc32
286 01:32:07.008654 output: Hash value: 4c96ec19
287 01:32:07.008708 output: Image 1 (fdt-1)
288 01:32:07.008762 output: Description: mt8192-asurada-spherion-r0
289 01:32:07.008815 output: Created: Wed Jun 5 02:32:06 2024
290 01:32:07.008870 output: Type: Flat Device Tree
291 01:32:07.008924 output: Compression: uncompressed
292 01:32:07.008976 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 01:32:07.009028 output: Architecture: AArch64
294 01:32:07.009079 output: Hash algo: crc32
295 01:32:07.009131 output: Hash value: 0f8e4d2e
296 01:32:07.009182 output: Image 2 (ramdisk-1)
297 01:32:07.009233 output: Description: unavailable
298 01:32:07.009317 output: Created: Wed Jun 5 02:32:06 2024
299 01:32:07.009396 output: Type: RAMDisk Image
300 01:32:07.009447 output: Compression: Unknown Compression
301 01:32:07.009499 output: Data Size: 18721060 Bytes = 18282.29 KiB = 17.85 MiB
302 01:32:07.009550 output: Architecture: AArch64
303 01:32:07.009601 output: OS: Linux
304 01:32:07.009653 output: Load Address: unavailable
305 01:32:07.009704 output: Entry Point: unavailable
306 01:32:07.009755 output: Hash algo: crc32
307 01:32:07.009806 output: Hash value: 2d1f7a8d
308 01:32:07.009857 output: Default Configuration: 'conf-1'
309 01:32:07.009908 output: Configuration 0 (conf-1)
310 01:32:07.009959 output: Description: mt8192-asurada-spherion-r0
311 01:32:07.010011 output: Kernel: kernel-1
312 01:32:07.010062 output: Init Ramdisk: ramdisk-1
313 01:32:07.010113 output: FDT: fdt-1
314 01:32:07.010165 output: Loadables: kernel-1
315 01:32:07.010216 output:
316 01:32:07.010422 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:32:07.010519 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:32:07.010622 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 01:32:07.010716 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 01:32:07.010791 No LXC device requested
321 01:32:07.010866 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:32:07.010951 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 01:32:07.011028 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:32:07.011092 Checking files for TFTP limit of 4294967296 bytes.
325 01:32:07.011584 end: 1 tftp-deploy (duration 00:00:38) [common]
326 01:32:07.011687 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:32:07.011778 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:32:07.011906 substitutions:
329 01:32:07.011976 - {DTB}: 14173483/tftp-deploy-9poujol5/dtb/mt8192-asurada-spherion-r0.dtb
330 01:32:07.012039 - {INITRD}: 14173483/tftp-deploy-9poujol5/ramdisk/ramdisk.cpio.gz
331 01:32:07.012098 - {KERNEL}: 14173483/tftp-deploy-9poujol5/kernel/Image
332 01:32:07.012155 - {LAVA_MAC}: None
333 01:32:07.012210 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l
334 01:32:07.012265 - {NFS_SERVER_IP}: 192.168.201.1
335 01:32:07.012319 - {PRESEED_CONFIG}: None
336 01:32:07.012372 - {PRESEED_LOCAL}: None
337 01:32:07.012424 - {RAMDISK}: 14173483/tftp-deploy-9poujol5/ramdisk/ramdisk.cpio.gz
338 01:32:07.012477 - {ROOT_PART}: None
339 01:32:07.012529 - {ROOT}: None
340 01:32:07.012581 - {SERVER_IP}: 192.168.201.1
341 01:32:07.012632 - {TEE}: None
342 01:32:07.012683 Parsed boot commands:
343 01:32:07.012735 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:32:07.012911 Parsed boot commands: tftpboot 192.168.201.1 14173483/tftp-deploy-9poujol5/kernel/image.itb 14173483/tftp-deploy-9poujol5/kernel/cmdline
345 01:32:07.012995 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:32:07.013076 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:32:07.013167 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:32:07.013251 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:32:07.013393 Not connected, no need to disconnect.
350 01:32:07.013464 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:32:07.013543 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:32:07.013610 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 01:32:07.017263 Setting prompt string to ['lava-test: # ']
354 01:32:07.017705 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:32:07.017810 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:32:07.017928 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:32:07.018021 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:32:07.018214 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 01:32:21.316580 Returned 0 in 14 seconds
360 01:32:21.417574 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 01:32:21.418930 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 01:32:21.419402 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 01:32:21.419859 Setting prompt string to 'Starting depthcharge on Spherion...'
365 01:32:21.420218 Changing prompt to 'Starting depthcharge on Spherion...'
366 01:32:21.420554 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 01:32:21.422173 [Enter `^Ec?' for help]
368 01:32:21.422567
369 01:32:21.422886
370 01:32:21.423187 F0: 102B 0000
371 01:32:21.423483
372 01:32:21.423823 F3: 1001 0000 [0200]
373 01:32:21.424125
374 01:32:21.424405 F3: 1001 0000
375 01:32:21.424685
376 01:32:21.424960 F7: 102D 0000
377 01:32:21.425233
378 01:32:21.425553 F1: 0000 0000
379 01:32:21.425838
380 01:32:21.426162 V0: 0000 0000 [0001]
381 01:32:21.426439
382 01:32:21.426711 00: 0007 8000
383 01:32:21.426991
384 01:32:21.427262 01: 0000 0000
385 01:32:21.427543
386 01:32:21.427815 BP: 0C00 0209 [0000]
387 01:32:21.428084
388 01:32:21.428352 G0: 1182 0000
389 01:32:21.428619
390 01:32:21.428886 EC: 0000 0021 [4000]
391 01:32:21.429157
392 01:32:21.429456 S7: 0000 0000 [0000]
393 01:32:21.429729
394 01:32:21.429998 CC: 0000 0000 [0001]
395 01:32:21.430268
396 01:32:21.430536 T0: 0000 0040 [010F]
397 01:32:21.430805
398 01:32:21.431071 Jump to BL
399 01:32:21.431342
400 01:32:21.431611
401 01:32:21.431877
402 01:32:21.432318 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 01:32:21.432678 ARM64: Exception handlers installed.
404 01:32:21.432960 ARM64: Testing exception
405 01:32:21.433235 ARM64: Done test exception
406 01:32:21.433563 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 01:32:21.433843 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 01:32:21.434119 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 01:32:21.434396 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 01:32:21.434672 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 01:32:21.434944 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 01:32:21.435217 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 01:32:21.435494 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 01:32:21.435768 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 01:32:21.436042 WDT: Last reset was cold boot
416 01:32:21.436311 SPI1(PAD0) initialized at 2873684 Hz
417 01:32:21.436582 SPI5(PAD0) initialized at 992727 Hz
418 01:32:21.436887 VBOOT: Loading verstage.
419 01:32:21.437185 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 01:32:21.437487 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 01:32:21.437764 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 01:32:21.438039 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 01:32:21.438312 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 01:32:21.438588 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 01:32:21.438861 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 01:32:21.439131
427 01:32:21.439398
428 01:32:21.439666 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 01:32:21.439942 ARM64: Exception handlers installed.
430 01:32:21.440210 ARM64: Testing exception
431 01:32:21.440479 ARM64: Done test exception
432 01:32:21.440747 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 01:32:21.441019 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 01:32:21.441308 Probing TPM: . done!
435 01:32:21.441584 TPM ready after 0 ms
436 01:32:21.441860 Connected to device vid:did:rid of 1ae0:0028:00
437 01:32:21.442132 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 01:32:21.442403 Initialized TPM device CR50 revision 0
439 01:32:21.442672 tlcl_send_startup: Startup return code is 0
440 01:32:21.442943 TPM: setup succeeded
441 01:32:21.443212 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 01:32:21.443483 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 01:32:21.443753 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 01:32:21.444026 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:32:21.444296 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 01:32:21.444571 in-header: 03 07 00 00 08 00 00 00
447 01:32:21.444851 in-data: aa e4 47 04 13 02 00 00
448 01:32:21.445134 Chrome EC: UHEPI supported
449 01:32:21.445423 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 01:32:21.445697 in-header: 03 a9 00 00 08 00 00 00
451 01:32:21.445966 in-data: 84 60 60 08 00 00 00 00
452 01:32:21.446236 Phase 1
453 01:32:21.446504 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 01:32:21.446790 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 01:32:21.447064 VB2:vb2_check_recovery() Recovery was requested manually
456 01:32:21.447334 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 01:32:21.447603 Recovery requested (1009000e)
458 01:32:21.447872 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 01:32:21.448142 tlcl_extend: response is 0
460 01:32:21.448410 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 01:32:21.448677 tlcl_extend: response is 0
462 01:32:21.448947 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 01:32:21.449219 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 01:32:21.449476 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 01:32:21.449670
466 01:32:21.449861
467 01:32:21.450051 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 01:32:21.450247 ARM64: Exception handlers installed.
469 01:32:21.450437 ARM64: Testing exception
470 01:32:21.450631 ARM64: Done test exception
471 01:32:21.450822 pmic_efuse_setting: Set efuses in 11 msecs
472 01:32:21.451014 pmwrap_interface_init: Select PMIF_VLD_RDY
473 01:32:21.451205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 01:32:21.451398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 01:32:21.451892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 01:32:21.452379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 01:32:21.452866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 01:32:21.453368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 01:32:21.453848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 01:32:21.454333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 01:32:21.454689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 01:32:21.455049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 01:32:21.455405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 01:32:21.455611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 01:32:21.455769 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 01:32:21.455920 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 01:32:21.456069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 01:32:21.456218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 01:32:21.456364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 01:32:21.456519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 01:32:21.456667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 01:32:21.456814 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 01:32:21.456960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 01:32:21.457107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 01:32:21.457254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 01:32:21.457412 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 01:32:21.457559 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 01:32:21.457704 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 01:32:21.457850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 01:32:21.457995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 01:32:21.458141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 01:32:21.458287 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 01:32:21.458431 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 01:32:21.458578 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 01:32:21.458724 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 01:32:21.458869 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 01:32:21.459016 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 01:32:21.459161 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 01:32:21.459321 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 01:32:21.459440 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 01:32:21.459560 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 01:32:21.459678 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 01:32:21.459797 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 01:32:21.459915 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 01:32:21.460030 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 01:32:21.460147 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 01:32:21.460263 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 01:32:21.460378 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 01:32:21.460494 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 01:32:21.460625 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 01:32:21.460744 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 01:32:21.460861 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 01:32:21.460978 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 01:32:21.461095 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 01:32:21.461212 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 01:32:21.461357 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 01:32:21.461478 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 01:32:21.461598 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 01:32:21.461715 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 01:32:21.461832 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 01:32:21.461950 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:32:21.462067 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
533 01:32:21.462185 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 01:32:21.462303 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 01:32:21.462421 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 01:32:21.462545 [RTC]rtc_get_frequency_meter,154: input=15, output=852
537 01:32:21.462667 [RTC]rtc_get_frequency_meter,154: input=7, output=724
538 01:32:21.462785 [RTC]rtc_get_frequency_meter,154: input=11, output=788
539 01:32:21.462903 [RTC]rtc_get_frequency_meter,154: input=13, output=820
540 01:32:21.463020 [RTC]rtc_get_frequency_meter,154: input=12, output=804
541 01:32:21.463137 [RTC]rtc_get_frequency_meter,154: input=11, output=787
542 01:32:21.463254 [RTC]rtc_get_frequency_meter,154: input=12, output=804
543 01:32:21.463372 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 01:32:21.463490 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 01:32:21.463837 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 01:32:21.463970 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 01:32:21.464089 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 01:32:21.464207 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 01:32:21.464331 ADC[4]: Raw value=902955 ID=7
550 01:32:21.464429 ADC[3]: Raw value=213546 ID=1
551 01:32:21.464526 RAM Code: 0x71
552 01:32:21.464651 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 01:32:21.464753 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 01:32:21.464852 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 01:32:21.464951 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 01:32:21.465050 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 01:32:21.465149 in-header: 03 07 00 00 08 00 00 00
558 01:32:21.465245 in-data: aa e4 47 04 13 02 00 00
559 01:32:21.465410 Chrome EC: UHEPI supported
560 01:32:21.465553 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 01:32:21.465657 in-header: 03 a9 00 00 08 00 00 00
562 01:32:21.465754 in-data: 84 60 60 08 00 00 00 00
563 01:32:21.465852 MRC: failed to locate region type 0.
564 01:32:21.465951 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 01:32:21.466049 DRAM-K: Running full calibration
566 01:32:21.466147 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 01:32:21.466246 header.status = 0x0
568 01:32:21.466343 header.version = 0x6 (expected: 0x6)
569 01:32:21.466440 header.size = 0xd00 (expected: 0xd00)
570 01:32:21.466544 header.flags = 0x0
571 01:32:21.466696 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 01:32:21.466849 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 01:32:21.466954 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 01:32:21.467055 dram_init: ddr_geometry: 2
575 01:32:21.467154 [EMI] MDL number = 2
576 01:32:21.467252 [EMI] Get MDL freq = 0
577 01:32:21.467350 dram_init: ddr_type: 0
578 01:32:21.467448 is_discrete_lpddr4: 1
579 01:32:21.467546 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 01:32:21.467643
581 01:32:21.467741
582 01:32:21.467844 [Bian_co] ETT version 0.0.0.1
583 01:32:21.467952 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 01:32:21.468069
585 01:32:21.468169 dramc_set_vcore_voltage set vcore to 650000
586 01:32:21.468268 Read voltage for 800, 4
587 01:32:21.468365 Vio18 = 0
588 01:32:21.468462 Vcore = 650000
589 01:32:21.468559 Vdram = 0
590 01:32:21.468657 Vddq = 0
591 01:32:21.468754 Vmddr = 0
592 01:32:21.468850 dram_init: config_dvfs: 1
593 01:32:21.468948 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 01:32:21.469047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 01:32:21.469147 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 01:32:21.469245 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 01:32:21.469369 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 01:32:21.469454 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 01:32:21.469537 MEM_TYPE=3, freq_sel=18
600 01:32:21.469621 sv_algorithm_assistance_LP4_1600
601 01:32:21.469705 ============ PULL DRAM RESETB DOWN ============
602 01:32:21.469794 ========== PULL DRAM RESETB DOWN end =========
603 01:32:21.469878 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 01:32:21.469962 ===================================
605 01:32:21.470046 LPDDR4 DRAM CONFIGURATION
606 01:32:21.470130 ===================================
607 01:32:21.470213 EX_ROW_EN[0] = 0x0
608 01:32:21.470296 EX_ROW_EN[1] = 0x0
609 01:32:21.470383 LP4Y_EN = 0x0
610 01:32:21.470467 WORK_FSP = 0x0
611 01:32:21.470549 WL = 0x2
612 01:32:21.470632 RL = 0x2
613 01:32:21.470728 BL = 0x2
614 01:32:21.470815 RPST = 0x0
615 01:32:21.470899 RD_PRE = 0x0
616 01:32:21.470982 WR_PRE = 0x1
617 01:32:21.471065 WR_PST = 0x0
618 01:32:21.471148 DBI_WR = 0x0
619 01:32:21.471231 DBI_RD = 0x0
620 01:32:21.471314 OTF = 0x1
621 01:32:21.471398 ===================================
622 01:32:21.471482 ===================================
623 01:32:21.471565 ANA top config
624 01:32:21.471648 ===================================
625 01:32:21.471733 DLL_ASYNC_EN = 0
626 01:32:21.471817 ALL_SLAVE_EN = 1
627 01:32:21.471900 NEW_RANK_MODE = 1
628 01:32:21.471985 DLL_IDLE_MODE = 1
629 01:32:21.472068 LP45_APHY_COMB_EN = 1
630 01:32:21.472152 TX_ODT_DIS = 1
631 01:32:21.472235 NEW_8X_MODE = 1
632 01:32:21.472320 ===================================
633 01:32:21.472405 ===================================
634 01:32:21.472489 data_rate = 1600
635 01:32:21.472572 CKR = 1
636 01:32:21.472655 DQ_P2S_RATIO = 8
637 01:32:21.472739 ===================================
638 01:32:21.472822 CA_P2S_RATIO = 8
639 01:32:21.472904 DQ_CA_OPEN = 0
640 01:32:21.472988 DQ_SEMI_OPEN = 0
641 01:32:21.473071 CA_SEMI_OPEN = 0
642 01:32:21.473154 CA_FULL_RATE = 0
643 01:32:21.473237 DQ_CKDIV4_EN = 1
644 01:32:21.473338 CA_CKDIV4_EN = 1
645 01:32:21.473422 CA_PREDIV_EN = 0
646 01:32:21.473506 PH8_DLY = 0
647 01:32:21.473588 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 01:32:21.473671 DQ_AAMCK_DIV = 4
649 01:32:21.473755 CA_AAMCK_DIV = 4
650 01:32:21.473837 CA_ADMCK_DIV = 4
651 01:32:21.473920 DQ_TRACK_CA_EN = 0
652 01:32:21.474004 CA_PICK = 800
653 01:32:21.474086 CA_MCKIO = 800
654 01:32:21.474169 MCKIO_SEMI = 0
655 01:32:21.474253 PLL_FREQ = 3068
656 01:32:21.474347 DQ_UI_PI_RATIO = 32
657 01:32:21.474419 CA_UI_PI_RATIO = 0
658 01:32:21.474492 ===================================
659 01:32:21.474565 ===================================
660 01:32:21.474639 memory_type:LPDDR4
661 01:32:21.474712 GP_NUM : 10
662 01:32:21.474785 SRAM_EN : 1
663 01:32:21.474858 MD32_EN : 0
664 01:32:21.474930 ===================================
665 01:32:21.475235 [ANA_INIT] >>>>>>>>>>>>>>
666 01:32:21.475424 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 01:32:21.475610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 01:32:21.475789 ===================================
669 01:32:21.475970 data_rate = 1600,PCW = 0X7600
670 01:32:21.476150 ===================================
671 01:32:21.476329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 01:32:21.476508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 01:32:21.476686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:32:21.476817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 01:32:21.476895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 01:32:21.476971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:32:21.477046 [ANA_INIT] flow start
678 01:32:21.477119 [ANA_INIT] PLL >>>>>>>>
679 01:32:21.477192 [ANA_INIT] PLL <<<<<<<<
680 01:32:21.477278 [ANA_INIT] MIDPI >>>>>>>>
681 01:32:21.477354 [ANA_INIT] MIDPI <<<<<<<<
682 01:32:21.477428 [ANA_INIT] DLL >>>>>>>>
683 01:32:21.477501 [ANA_INIT] flow end
684 01:32:21.477574 ============ LP4 DIFF to SE enter ============
685 01:32:21.477648 ============ LP4 DIFF to SE exit ============
686 01:32:21.477722 [ANA_INIT] <<<<<<<<<<<<<
687 01:32:21.477795 [Flow] Enable top DCM control >>>>>
688 01:32:21.477869 [Flow] Enable top DCM control <<<<<
689 01:32:21.477942 Enable DLL master slave shuffle
690 01:32:21.478015 ==============================================================
691 01:32:21.478089 Gating Mode config
692 01:32:21.478162 ==============================================================
693 01:32:21.478236 Config description:
694 01:32:21.478309 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 01:32:21.478384 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 01:32:21.478458 SELPH_MODE 0: By rank 1: By Phase
697 01:32:21.478532 ==============================================================
698 01:32:21.478605 GAT_TRACK_EN = 1
699 01:32:21.478679 RX_GATING_MODE = 2
700 01:32:21.478752 RX_GATING_TRACK_MODE = 2
701 01:32:21.478826 SELPH_MODE = 1
702 01:32:21.478899 PICG_EARLY_EN = 1
703 01:32:21.478973 VALID_LAT_VALUE = 1
704 01:32:21.479046 ==============================================================
705 01:32:21.479120 Enter into Gating configuration >>>>
706 01:32:21.479194 Exit from Gating configuration <<<<
707 01:32:21.479267 Enter into DVFS_PRE_config >>>>>
708 01:32:21.479349 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 01:32:21.479416 Exit from DVFS_PRE_config <<<<<
710 01:32:21.479481 Enter into PICG configuration >>>>
711 01:32:21.479546 Exit from PICG configuration <<<<
712 01:32:21.479611 [RX_INPUT] configuration >>>>>
713 01:32:21.479677 [RX_INPUT] configuration <<<<<
714 01:32:21.479743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 01:32:21.479809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 01:32:21.479874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 01:32:21.479940 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 01:32:21.480006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 01:32:21.480071 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 01:32:21.480136 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 01:32:21.480202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 01:32:21.480267 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 01:32:21.480333 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 01:32:21.480398 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 01:32:21.480463 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 01:32:21.480529 ===================================
727 01:32:21.480594 LPDDR4 DRAM CONFIGURATION
728 01:32:21.480659 ===================================
729 01:32:21.480724 EX_ROW_EN[0] = 0x0
730 01:32:21.480790 EX_ROW_EN[1] = 0x0
731 01:32:21.480855 LP4Y_EN = 0x0
732 01:32:21.480920 WORK_FSP = 0x0
733 01:32:21.480985 WL = 0x2
734 01:32:21.481050 RL = 0x2
735 01:32:21.481115 BL = 0x2
736 01:32:21.481179 RPST = 0x0
737 01:32:21.481244 RD_PRE = 0x0
738 01:32:21.481321 WR_PRE = 0x1
739 01:32:21.481387 WR_PST = 0x0
740 01:32:21.481452 DBI_WR = 0x0
741 01:32:21.481517 DBI_RD = 0x0
742 01:32:21.481582 OTF = 0x1
743 01:32:21.481649 ===================================
744 01:32:21.481713 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 01:32:21.481779 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 01:32:21.481845 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 01:32:21.481911 ===================================
748 01:32:21.481976 LPDDR4 DRAM CONFIGURATION
749 01:32:21.482041 ===================================
750 01:32:21.482106 EX_ROW_EN[0] = 0x10
751 01:32:21.482172 EX_ROW_EN[1] = 0x0
752 01:32:21.482237 LP4Y_EN = 0x0
753 01:32:21.482302 WORK_FSP = 0x0
754 01:32:21.482367 WL = 0x2
755 01:32:21.482431 RL = 0x2
756 01:32:21.482495 BL = 0x2
757 01:32:21.482560 RPST = 0x0
758 01:32:21.482625 RD_PRE = 0x0
759 01:32:21.482693 WR_PRE = 0x1
760 01:32:21.482758 WR_PST = 0x0
761 01:32:21.482823 DBI_WR = 0x0
762 01:32:21.482888 DBI_RD = 0x0
763 01:32:21.482952 OTF = 0x1
764 01:32:21.483017 ===================================
765 01:32:21.483082 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 01:32:21.483148 nWR fixed to 40
767 01:32:21.483214 [ModeRegInit_LP4] CH0 RK0
768 01:32:21.483278 [ModeRegInit_LP4] CH0 RK1
769 01:32:21.483343 [ModeRegInit_LP4] CH1 RK0
770 01:32:21.483408 [ModeRegInit_LP4] CH1 RK1
771 01:32:21.483473 match AC timing 13
772 01:32:21.483537 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 01:32:21.483805 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 01:32:21.483879 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 01:32:21.483947 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 01:32:21.484013 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 01:32:21.484080 [EMI DOE] emi_dcm 0
778 01:32:21.484145 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 01:32:21.484210 ==
780 01:32:21.484303 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:32:21.484366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 01:32:21.484426 ==
783 01:32:21.484485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 01:32:21.484546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 01:32:21.484606 [CA 0] Center 37 (7~68) winsize 62
786 01:32:21.484665 [CA 1] Center 37 (7~68) winsize 62
787 01:32:21.484723 [CA 2] Center 34 (4~65) winsize 62
788 01:32:21.484782 [CA 3] Center 34 (4~65) winsize 62
789 01:32:21.484841 [CA 4] Center 33 (3~64) winsize 62
790 01:32:21.484899 [CA 5] Center 33 (3~64) winsize 62
791 01:32:21.484958
792 01:32:21.485016 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 01:32:21.485075
794 01:32:21.485133 [CATrainingPosCal] consider 1 rank data
795 01:32:21.485192 u2DelayCellTimex100 = 270/100 ps
796 01:32:21.485250 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 01:32:21.485320 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
798 01:32:21.485379 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 01:32:21.485438 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 01:32:21.485498 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 01:32:21.485556 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 01:32:21.485615
803 01:32:21.485673 CA PerBit enable=1, Macro0, CA PI delay=33
804 01:32:21.485732
805 01:32:21.485790 [CBTSetCACLKResult] CA Dly = 33
806 01:32:21.485848 CS Dly: 5 (0~36)
807 01:32:21.485906 ==
808 01:32:21.485965 Dram Type= 6, Freq= 0, CH_0, rank 1
809 01:32:21.486024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 01:32:21.486083 ==
811 01:32:21.486142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 01:32:21.486202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 01:32:21.486262 [CA 0] Center 38 (7~69) winsize 63
814 01:32:21.486321 [CA 1] Center 37 (7~68) winsize 62
815 01:32:21.486380 [CA 2] Center 35 (4~66) winsize 63
816 01:32:21.486439 [CA 3] Center 35 (4~66) winsize 63
817 01:32:21.486498 [CA 4] Center 34 (3~65) winsize 63
818 01:32:21.486556 [CA 5] Center 33 (3~64) winsize 62
819 01:32:21.486615
820 01:32:21.486674 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 01:32:21.486733
822 01:32:21.486791 [CATrainingPosCal] consider 2 rank data
823 01:32:21.486851 u2DelayCellTimex100 = 270/100 ps
824 01:32:21.486909 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 01:32:21.486969 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 01:32:21.487027 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 01:32:21.487086 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 01:32:21.487145 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 01:32:21.487204 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 01:32:21.487262
831 01:32:21.487321 CA PerBit enable=1, Macro0, CA PI delay=33
832 01:32:21.487380
833 01:32:21.487438 [CBTSetCACLKResult] CA Dly = 33
834 01:32:21.487497 CS Dly: 6 (0~38)
835 01:32:21.487555
836 01:32:21.487614 ----->DramcWriteLeveling(PI) begin...
837 01:32:21.487674 ==
838 01:32:21.487733 Dram Type= 6, Freq= 0, CH_0, rank 0
839 01:32:21.487792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 01:32:21.487852 ==
841 01:32:21.487910 Write leveling (Byte 0): 29 => 29
842 01:32:21.487969 Write leveling (Byte 1): 26 => 26
843 01:32:21.488028 DramcWriteLeveling(PI) end<-----
844 01:32:21.488087
845 01:32:21.488145 ==
846 01:32:21.488203 Dram Type= 6, Freq= 0, CH_0, rank 0
847 01:32:21.488262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 01:32:21.488343 ==
849 01:32:21.488403 [Gating] SW mode calibration
850 01:32:21.488463 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 01:32:21.488522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 01:32:21.488583 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 01:32:21.488642 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 01:32:21.488701 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 01:32:21.488761 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 01:32:21.488820 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:32:21.488879 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:32:21.488938 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:32:21.488997 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:32:21.489056 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:32:21.489115 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:32:21.489174 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:32:21.489233 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:32:21.489301 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:32:21.489371 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 01:32:21.489424 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:32:21.489477 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:32:21.489531 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:32:21.489584 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
870 01:32:21.489638 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
871 01:32:21.489692 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 01:32:21.489746 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 01:32:21.489799 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 01:32:21.489853 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 01:32:21.489906 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:32:21.489959 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:32:21.490012 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 01:32:21.490065 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
879 01:32:21.490118 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
880 01:32:21.490172 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 01:32:21.490423 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 01:32:21.490563 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 01:32:21.490698 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 01:32:21.490829 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 01:32:21.490961 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
886 01:32:21.491091 0 10 8 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 0)
887 01:32:21.491222 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
888 01:32:21.491352 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 01:32:21.491481 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 01:32:21.491558 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 01:32:21.491615 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 01:32:21.491670 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 01:32:21.491725 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
894 01:32:21.491779 0 11 8 | B1->B0 | 2525 4040 | 1 0 | (0 0) (1 1)
895 01:32:21.491834 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
896 01:32:21.491888 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 01:32:21.491942 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 01:32:21.491996 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 01:32:21.492049 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 01:32:21.492103 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 01:32:21.492158 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 01:32:21.492211 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 01:32:21.492265 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 01:32:21.492319 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 01:32:21.492373 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:32:21.492427 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:32:21.492481 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:32:21.492538 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:32:21.492636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:32:21.492730 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:32:21.492788 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:32:21.492847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 01:32:21.492902 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 01:32:21.492957 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 01:32:21.493011 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 01:32:21.493064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 01:32:21.493118 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
918 01:32:21.493172 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
919 01:32:21.493225 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 01:32:21.493290 Total UI for P1: 0, mck2ui 16
921 01:32:21.493347 best dqsien dly found for B0: ( 0, 14, 6)
922 01:32:21.493402 Total UI for P1: 0, mck2ui 16
923 01:32:21.493456 best dqsien dly found for B1: ( 0, 14, 6)
924 01:32:21.493510 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 01:32:21.493564 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
926 01:32:21.493618
927 01:32:21.493672 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 01:32:21.493725 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 01:32:21.493779 [Gating] SW calibration Done
930 01:32:21.493833 ==
931 01:32:21.493886 Dram Type= 6, Freq= 0, CH_0, rank 0
932 01:32:21.493940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 01:32:21.493994 ==
934 01:32:21.494047 RX Vref Scan: 0
935 01:32:21.494100
936 01:32:21.494153 RX Vref 0 -> 0, step: 1
937 01:32:21.494206
938 01:32:21.494259 RX Delay -130 -> 252, step: 16
939 01:32:21.494324 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 01:32:21.494377 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
941 01:32:21.494430 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 01:32:21.494482 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 01:32:21.494534 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 01:32:21.494586 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 01:32:21.494638 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 01:32:21.494690 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
947 01:32:21.494742 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 01:32:21.494794 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
949 01:32:21.494846 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 01:32:21.494898 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 01:32:21.494951 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
952 01:32:21.495003 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
953 01:32:21.495055 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 01:32:21.495108 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 01:32:21.495160 ==
956 01:32:21.495212 Dram Type= 6, Freq= 0, CH_0, rank 0
957 01:32:21.495264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 01:32:21.495316 ==
959 01:32:21.495368 DQS Delay:
960 01:32:21.495420 DQS0 = 0, DQS1 = 0
961 01:32:21.495472 DQM Delay:
962 01:32:21.495524 DQM0 = 89, DQM1 = 76
963 01:32:21.495576 DQ Delay:
964 01:32:21.495628 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
965 01:32:21.495680 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
966 01:32:21.495732 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
967 01:32:21.495784 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
968 01:32:21.495836
969 01:32:21.495888
970 01:32:21.495940 ==
971 01:32:21.495992 Dram Type= 6, Freq= 0, CH_0, rank 0
972 01:32:21.496044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 01:32:21.496097 ==
974 01:32:21.496149
975 01:32:21.496202
976 01:32:21.496253 TX Vref Scan disable
977 01:32:21.496305 == TX Byte 0 ==
978 01:32:21.496357 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
979 01:32:21.496410 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
980 01:32:21.496463 == TX Byte 1 ==
981 01:32:21.496514 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
982 01:32:21.496567 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
983 01:32:21.496620 ==
984 01:32:21.496672 Dram Type= 6, Freq= 0, CH_0, rank 0
985 01:32:21.496725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 01:32:21.496778 ==
987 01:32:21.496830 TX Vref=22, minBit 1, minWin=26, winSum=436
988 01:32:21.496883 TX Vref=24, minBit 1, minWin=26, winSum=440
989 01:32:21.497130 TX Vref=26, minBit 0, minWin=27, winSum=444
990 01:32:21.497220 TX Vref=28, minBit 1, minWin=27, winSum=447
991 01:32:21.497334 TX Vref=30, minBit 3, minWin=27, winSum=446
992 01:32:21.497389 TX Vref=32, minBit 2, minWin=27, winSum=447
993 01:32:21.497442 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
994 01:32:21.497496
995 01:32:21.497549 Final TX Range 1 Vref 28
996 01:32:21.497601
997 01:32:21.497653 ==
998 01:32:21.497705 Dram Type= 6, Freq= 0, CH_0, rank 0
999 01:32:21.497758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 01:32:21.497810 ==
1001 01:32:21.497862
1002 01:32:21.497914
1003 01:32:21.497966 TX Vref Scan disable
1004 01:32:21.498018 == TX Byte 0 ==
1005 01:32:21.498070 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1006 01:32:21.498123 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1007 01:32:21.498175 == TX Byte 1 ==
1008 01:32:21.498227 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1009 01:32:21.498279 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1010 01:32:21.498331
1011 01:32:21.498384 [DATLAT]
1012 01:32:21.498437 Freq=800, CH0 RK0
1013 01:32:21.498490
1014 01:32:21.498542 DATLAT Default: 0xa
1015 01:32:21.498594 0, 0xFFFF, sum = 0
1016 01:32:21.498648 1, 0xFFFF, sum = 0
1017 01:32:21.498701 2, 0xFFFF, sum = 0
1018 01:32:21.498754 3, 0xFFFF, sum = 0
1019 01:32:21.498807 4, 0xFFFF, sum = 0
1020 01:32:21.498860 5, 0xFFFF, sum = 0
1021 01:32:21.498913 6, 0xFFFF, sum = 0
1022 01:32:21.498966 7, 0xFFFF, sum = 0
1023 01:32:21.499019 8, 0xFFFF, sum = 0
1024 01:32:21.499072 9, 0x0, sum = 1
1025 01:32:21.499131 10, 0x0, sum = 2
1026 01:32:21.499190 11, 0x0, sum = 3
1027 01:32:21.499244 12, 0x0, sum = 4
1028 01:32:21.499297 best_step = 10
1029 01:32:21.499349
1030 01:32:21.499400 ==
1031 01:32:21.499451 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 01:32:21.499503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 01:32:21.499555 ==
1034 01:32:21.499606 RX Vref Scan: 1
1035 01:32:21.499657
1036 01:32:21.499708 Set Vref Range= 32 -> 127
1037 01:32:21.499760
1038 01:32:21.499811 RX Vref 32 -> 127, step: 1
1039 01:32:21.499862
1040 01:32:21.499913 RX Delay -95 -> 252, step: 8
1041 01:32:21.499964
1042 01:32:21.500015 Set Vref, RX VrefLevel [Byte0]: 32
1043 01:32:21.500067 [Byte1]: 32
1044 01:32:21.500118
1045 01:32:21.500169 Set Vref, RX VrefLevel [Byte0]: 33
1046 01:32:21.500220 [Byte1]: 33
1047 01:32:21.500271
1048 01:32:21.500321 Set Vref, RX VrefLevel [Byte0]: 34
1049 01:32:21.500373 [Byte1]: 34
1050 01:32:21.500424
1051 01:32:21.500475 Set Vref, RX VrefLevel [Byte0]: 35
1052 01:32:21.500527 [Byte1]: 35
1053 01:32:21.500578
1054 01:32:21.500629 Set Vref, RX VrefLevel [Byte0]: 36
1055 01:32:21.500680 [Byte1]: 36
1056 01:32:21.500731
1057 01:32:21.500782 Set Vref, RX VrefLevel [Byte0]: 37
1058 01:32:21.500833 [Byte1]: 37
1059 01:32:21.500884
1060 01:32:21.500935 Set Vref, RX VrefLevel [Byte0]: 38
1061 01:32:21.500987 [Byte1]: 38
1062 01:32:21.501038
1063 01:32:21.501088 Set Vref, RX VrefLevel [Byte0]: 39
1064 01:32:21.501139 [Byte1]: 39
1065 01:32:21.501190
1066 01:32:21.501240 Set Vref, RX VrefLevel [Byte0]: 40
1067 01:32:21.501329 [Byte1]: 40
1068 01:32:21.501395
1069 01:32:21.501446 Set Vref, RX VrefLevel [Byte0]: 41
1070 01:32:21.501498 [Byte1]: 41
1071 01:32:21.501549
1072 01:32:21.501600 Set Vref, RX VrefLevel [Byte0]: 42
1073 01:32:21.501652 [Byte1]: 42
1074 01:32:21.501703
1075 01:32:21.501753 Set Vref, RX VrefLevel [Byte0]: 43
1076 01:32:21.501805 [Byte1]: 43
1077 01:32:21.501856
1078 01:32:21.501907 Set Vref, RX VrefLevel [Byte0]: 44
1079 01:32:21.501958 [Byte1]: 44
1080 01:32:21.502008
1081 01:32:21.502060 Set Vref, RX VrefLevel [Byte0]: 45
1082 01:32:21.502111 [Byte1]: 45
1083 01:32:21.502162
1084 01:32:21.502212 Set Vref, RX VrefLevel [Byte0]: 46
1085 01:32:21.502263 [Byte1]: 46
1086 01:32:21.502314
1087 01:32:21.502365 Set Vref, RX VrefLevel [Byte0]: 47
1088 01:32:21.502416 [Byte1]: 47
1089 01:32:21.502467
1090 01:32:21.502518 Set Vref, RX VrefLevel [Byte0]: 48
1091 01:32:21.502569 [Byte1]: 48
1092 01:32:21.502620
1093 01:32:21.502671 Set Vref, RX VrefLevel [Byte0]: 49
1094 01:32:21.502721 [Byte1]: 49
1095 01:32:21.502773
1096 01:32:21.502823 Set Vref, RX VrefLevel [Byte0]: 50
1097 01:32:21.502874 [Byte1]: 50
1098 01:32:21.502925
1099 01:32:21.502976 Set Vref, RX VrefLevel [Byte0]: 51
1100 01:32:21.503027 [Byte1]: 51
1101 01:32:21.503078
1102 01:32:21.503128 Set Vref, RX VrefLevel [Byte0]: 52
1103 01:32:21.503180 [Byte1]: 52
1104 01:32:21.503231
1105 01:32:21.503284 Set Vref, RX VrefLevel [Byte0]: 53
1106 01:32:21.503366 [Byte1]: 53
1107 01:32:21.503417
1108 01:32:21.503468 Set Vref, RX VrefLevel [Byte0]: 54
1109 01:32:21.503518 [Byte1]: 54
1110 01:32:21.503570
1111 01:32:21.503620 Set Vref, RX VrefLevel [Byte0]: 55
1112 01:32:21.503671 [Byte1]: 55
1113 01:32:21.503721
1114 01:32:21.503772 Set Vref, RX VrefLevel [Byte0]: 56
1115 01:32:21.503823 [Byte1]: 56
1116 01:32:21.503873
1117 01:32:21.503924 Set Vref, RX VrefLevel [Byte0]: 57
1118 01:32:21.503975 [Byte1]: 57
1119 01:32:21.504026
1120 01:32:21.504077 Set Vref, RX VrefLevel [Byte0]: 58
1121 01:32:21.504128 [Byte1]: 58
1122 01:32:21.504179
1123 01:32:21.504229 Set Vref, RX VrefLevel [Byte0]: 59
1124 01:32:21.504280 [Byte1]: 59
1125 01:32:21.504330
1126 01:32:21.504381 Set Vref, RX VrefLevel [Byte0]: 60
1127 01:32:21.504432 [Byte1]: 60
1128 01:32:21.504483
1129 01:32:21.504533 Set Vref, RX VrefLevel [Byte0]: 61
1130 01:32:21.504585 [Byte1]: 61
1131 01:32:21.504636
1132 01:32:21.504686 Set Vref, RX VrefLevel [Byte0]: 62
1133 01:32:21.504737 [Byte1]: 62
1134 01:32:21.504789
1135 01:32:21.504839 Set Vref, RX VrefLevel [Byte0]: 63
1136 01:32:21.504890 [Byte1]: 63
1137 01:32:21.504941
1138 01:32:21.504992 Set Vref, RX VrefLevel [Byte0]: 64
1139 01:32:21.505043 [Byte1]: 64
1140 01:32:21.505094
1141 01:32:21.505145 Set Vref, RX VrefLevel [Byte0]: 65
1142 01:32:21.505196 [Byte1]: 65
1143 01:32:21.505247
1144 01:32:21.505349 Set Vref, RX VrefLevel [Byte0]: 66
1145 01:32:21.505402 [Byte1]: 66
1146 01:32:21.505453
1147 01:32:21.505504 Set Vref, RX VrefLevel [Byte0]: 67
1148 01:32:21.505556 [Byte1]: 67
1149 01:32:21.505608
1150 01:32:21.505659 Set Vref, RX VrefLevel [Byte0]: 68
1151 01:32:21.505710 [Byte1]: 68
1152 01:32:21.505761
1153 01:32:21.505813 Set Vref, RX VrefLevel [Byte0]: 69
1154 01:32:21.505864 [Byte1]: 69
1155 01:32:21.505915
1156 01:32:21.505966 Set Vref, RX VrefLevel [Byte0]: 70
1157 01:32:21.506209 [Byte1]: 70
1158 01:32:21.506337
1159 01:32:21.506462 Set Vref, RX VrefLevel [Byte0]: 71
1160 01:32:21.506588 [Byte1]: 71
1161 01:32:21.506743
1162 01:32:21.506868 Set Vref, RX VrefLevel [Byte0]: 72
1163 01:32:21.506992 [Byte1]: 72
1164 01:32:21.507116
1165 01:32:21.507240 Set Vref, RX VrefLevel [Byte0]: 73
1166 01:32:21.507346 [Byte1]: 73
1167 01:32:21.507402
1168 01:32:21.507455 Set Vref, RX VrefLevel [Byte0]: 74
1169 01:32:21.507507 [Byte1]: 74
1170 01:32:21.507559
1171 01:32:21.507611 Set Vref, RX VrefLevel [Byte0]: 75
1172 01:32:21.507708 [Byte1]: 75
1173 01:32:21.507762
1174 01:32:21.507814 Set Vref, RX VrefLevel [Byte0]: 76
1175 01:32:21.507866 [Byte1]: 76
1176 01:32:21.507918
1177 01:32:21.507969 Final RX Vref Byte 0 = 57 to rank0
1178 01:32:21.508021 Final RX Vref Byte 1 = 60 to rank0
1179 01:32:21.508073 Final RX Vref Byte 0 = 57 to rank1
1180 01:32:21.508125 Final RX Vref Byte 1 = 60 to rank1==
1181 01:32:21.508177 Dram Type= 6, Freq= 0, CH_0, rank 0
1182 01:32:21.508229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 01:32:21.508281 ==
1184 01:32:21.508333 DQS Delay:
1185 01:32:21.508384 DQS0 = 0, DQS1 = 0
1186 01:32:21.508436 DQM Delay:
1187 01:32:21.508487 DQM0 = 89, DQM1 = 76
1188 01:32:21.508538 DQ Delay:
1189 01:32:21.508589 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =88
1190 01:32:21.508641 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1191 01:32:21.508696 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1192 01:32:21.508748 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1193 01:32:21.508799
1194 01:32:21.508850
1195 01:32:21.508901 [DQSOSCAuto] RK0, (LSB)MR18= 0x312a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1196 01:32:21.508954 CH0 RK0: MR19=606, MR18=312A
1197 01:32:21.509006 CH0_RK0: MR19=0x606, MR18=0x312A, DQSOSC=397, MR23=63, INC=93, DEC=62
1198 01:32:21.509058
1199 01:32:21.509108 ----->DramcWriteLeveling(PI) begin...
1200 01:32:21.509161 ==
1201 01:32:21.509213 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 01:32:21.509274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 01:32:21.509370 ==
1204 01:32:21.509422 Write leveling (Byte 0): 32 => 32
1205 01:32:21.509474 Write leveling (Byte 1): 27 => 27
1206 01:32:21.509526 DramcWriteLeveling(PI) end<-----
1207 01:32:21.509577
1208 01:32:21.509628 ==
1209 01:32:21.509680 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 01:32:21.509764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 01:32:21.509816 ==
1212 01:32:21.509868 [Gating] SW mode calibration
1213 01:32:21.509920 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1214 01:32:21.509972 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1215 01:32:21.510024 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 01:32:21.510076 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1217 01:32:21.510128 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 01:32:21.510180 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1219 01:32:21.510232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 01:32:21.510283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 01:32:21.510335 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 01:32:21.510386 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 01:32:21.510438 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 01:32:21.510490 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 01:32:21.510541 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 01:32:21.510592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 01:32:21.510644 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 01:32:21.510695 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 01:32:21.510747 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 01:32:21.510798 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 01:32:21.510850 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1232 01:32:21.510901 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1233 01:32:21.510952 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1234 01:32:21.511003 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 01:32:21.511055 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 01:32:21.511106 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 01:32:21.511157 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 01:32:21.511209 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 01:32:21.511261 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 01:32:21.511313 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1241 01:32:21.511364 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
1242 01:32:21.511416 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1243 01:32:21.511467 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 01:32:21.511519 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 01:32:21.511570 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 01:32:21.511622 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 01:32:21.511674 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1248 01:32:21.511726 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1249 01:32:21.511777 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1250 01:32:21.511829 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 01:32:21.511881 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 01:32:21.511932 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 01:32:21.511984 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 01:32:21.512036 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 01:32:21.512087 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 01:32:21.512139 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1257 01:32:21.512190 0 11 8 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
1258 01:32:21.512241 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1259 01:32:21.512292 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 01:32:21.512344 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 01:32:21.512395 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 01:32:21.512446 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 01:32:21.512691 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 01:32:21.512820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1265 01:32:21.512947 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 01:32:21.513090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 01:32:21.513243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 01:32:21.513376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 01:32:21.513432 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 01:32:21.513485 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 01:32:21.513537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 01:32:21.513589 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 01:32:21.513641 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 01:32:21.513693 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 01:32:21.513744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 01:32:21.513795 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 01:32:21.513847 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 01:32:21.513899 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 01:32:21.513950 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 01:32:21.514000 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1281 01:32:21.514052 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1282 01:32:21.514104 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 01:32:21.514156 Total UI for P1: 0, mck2ui 16
1284 01:32:21.514208 best dqsien dly found for B0: ( 0, 14, 6)
1285 01:32:21.514260 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 01:32:21.514311 Total UI for P1: 0, mck2ui 16
1287 01:32:21.514363 best dqsien dly found for B1: ( 0, 14, 12)
1288 01:32:21.514414 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1289 01:32:21.514466 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1290 01:32:21.514518
1291 01:32:21.514569 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 01:32:21.514621 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1293 01:32:21.514672 [Gating] SW calibration Done
1294 01:32:21.514723 ==
1295 01:32:21.514775 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 01:32:21.514826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 01:32:21.514878 ==
1298 01:32:21.514929 RX Vref Scan: 0
1299 01:32:21.514980
1300 01:32:21.515031 RX Vref 0 -> 0, step: 1
1301 01:32:21.515082
1302 01:32:21.515133 RX Delay -130 -> 252, step: 16
1303 01:32:21.515184 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1304 01:32:21.515236 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1305 01:32:21.515287 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1306 01:32:21.515337 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1307 01:32:21.515389 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1308 01:32:21.515441 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1309 01:32:21.515492 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1310 01:32:21.515544 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1311 01:32:21.515595 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1312 01:32:21.515646 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1313 01:32:21.515697 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1314 01:32:21.515749 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1315 01:32:21.515800 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1316 01:32:21.515851 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1317 01:32:21.515903 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1318 01:32:21.515954 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1319 01:32:21.516005 ==
1320 01:32:21.516057 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 01:32:21.516108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 01:32:21.516160 ==
1323 01:32:21.516211 DQS Delay:
1324 01:32:21.516262 DQS0 = 0, DQS1 = 0
1325 01:32:21.516313 DQM Delay:
1326 01:32:21.516365 DQM0 = 89, DQM1 = 78
1327 01:32:21.516416 DQ Delay:
1328 01:32:21.516467 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1329 01:32:21.516518 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1330 01:32:21.516569 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1331 01:32:21.516621 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1332 01:32:21.516672
1333 01:32:21.516722
1334 01:32:21.516773 ==
1335 01:32:21.516824 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 01:32:21.516875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 01:32:21.516927 ==
1338 01:32:21.516978
1339 01:32:21.517029
1340 01:32:21.517080 TX Vref Scan disable
1341 01:32:21.517131 == TX Byte 0 ==
1342 01:32:21.517182 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1343 01:32:21.517234 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1344 01:32:21.517298 == TX Byte 1 ==
1345 01:32:21.517351 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1346 01:32:21.517403 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1347 01:32:21.517455 ==
1348 01:32:21.517507 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 01:32:21.517559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 01:32:21.517611 ==
1351 01:32:21.517662 TX Vref=22, minBit 1, minWin=27, winSum=439
1352 01:32:21.517714 TX Vref=24, minBit 1, minWin=27, winSum=443
1353 01:32:21.517766 TX Vref=26, minBit 1, minWin=27, winSum=448
1354 01:32:21.517818 TX Vref=28, minBit 0, minWin=28, winSum=453
1355 01:32:21.517870 TX Vref=30, minBit 1, minWin=27, winSum=450
1356 01:32:21.517922 TX Vref=32, minBit 1, minWin=27, winSum=450
1357 01:32:21.517973 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
1358 01:32:21.518025
1359 01:32:21.518076 Final TX Range 1 Vref 28
1360 01:32:21.518128
1361 01:32:21.518179 ==
1362 01:32:21.518231 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 01:32:21.518281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 01:32:21.518332 ==
1365 01:32:21.518383
1366 01:32:21.518433
1367 01:32:21.518483 TX Vref Scan disable
1368 01:32:21.518535 == TX Byte 0 ==
1369 01:32:21.518585 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1370 01:32:21.518637 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1371 01:32:21.518688 == TX Byte 1 ==
1372 01:32:21.518739 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1373 01:32:21.518790 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1374 01:32:21.518841
1375 01:32:21.518892 [DATLAT]
1376 01:32:21.518942 Freq=800, CH0 RK1
1377 01:32:21.518994
1378 01:32:21.519044 DATLAT Default: 0xa
1379 01:32:21.519095 0, 0xFFFF, sum = 0
1380 01:32:21.519147 1, 0xFFFF, sum = 0
1381 01:32:21.519199 2, 0xFFFF, sum = 0
1382 01:32:21.519251 3, 0xFFFF, sum = 0
1383 01:32:21.519302 4, 0xFFFF, sum = 0
1384 01:32:21.519354 5, 0xFFFF, sum = 0
1385 01:32:21.519406 6, 0xFFFF, sum = 0
1386 01:32:21.519458 7, 0xFFFF, sum = 0
1387 01:32:21.519509 8, 0xFFFF, sum = 0
1388 01:32:21.519561 9, 0x0, sum = 1
1389 01:32:21.519613 10, 0x0, sum = 2
1390 01:32:21.519860 11, 0x0, sum = 3
1391 01:32:21.519922 12, 0x0, sum = 4
1392 01:32:21.519975 best_step = 10
1393 01:32:21.520027
1394 01:32:21.520078 ==
1395 01:32:21.520130 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 01:32:21.520181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 01:32:21.520232 ==
1398 01:32:21.520283 RX Vref Scan: 0
1399 01:32:21.520334
1400 01:32:21.520384 RX Vref 0 -> 0, step: 1
1401 01:32:21.520434
1402 01:32:21.520484 RX Delay -95 -> 252, step: 8
1403 01:32:21.520536 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1404 01:32:21.520587 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1405 01:32:21.520638 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1406 01:32:21.520690 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1407 01:32:21.520742 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 01:32:21.520793 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 01:32:21.520843 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 01:32:21.520894 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 01:32:21.520944 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1412 01:32:21.520995 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1413 01:32:21.521046 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 01:32:21.521097 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1415 01:32:21.521147 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1416 01:32:21.521199 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1417 01:32:21.521250 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 01:32:21.521316 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1419 01:32:21.521368 ==
1420 01:32:21.521419 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 01:32:21.521470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 01:32:21.521522 ==
1423 01:32:21.521573 DQS Delay:
1424 01:32:21.521624 DQS0 = 0, DQS1 = 0
1425 01:32:21.521675 DQM Delay:
1426 01:32:21.521725 DQM0 = 86, DQM1 = 76
1427 01:32:21.521776 DQ Delay:
1428 01:32:21.521827 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1429 01:32:21.521878 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 01:32:21.521929 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1431 01:32:21.521980 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1432 01:32:21.522031
1433 01:32:21.522081
1434 01:32:21.522131 [DQSOSCAuto] RK1, (LSB)MR18= 0x2521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1435 01:32:21.522183 CH0 RK1: MR19=606, MR18=2521
1436 01:32:21.522235 CH0_RK1: MR19=0x606, MR18=0x2521, DQSOSC=400, MR23=63, INC=92, DEC=61
1437 01:32:21.522287 [RxdqsGatingPostProcess] freq 800
1438 01:32:21.522338 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 01:32:21.522389 Pre-setting of DQS Precalculation
1440 01:32:21.522440 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 01:32:21.522491 ==
1442 01:32:21.522542 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 01:32:21.522593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 01:32:21.522645 ==
1445 01:32:21.522696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 01:32:21.522748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 01:32:21.522799 [CA 0] Center 37 (6~68) winsize 63
1448 01:32:21.522850 [CA 1] Center 37 (6~68) winsize 63
1449 01:32:21.522900 [CA 2] Center 35 (5~66) winsize 62
1450 01:32:21.522951 [CA 3] Center 34 (4~65) winsize 62
1451 01:32:21.523003 [CA 4] Center 35 (4~66) winsize 63
1452 01:32:21.523053 [CA 5] Center 34 (4~65) winsize 62
1453 01:32:21.523103
1454 01:32:21.523154 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 01:32:21.523205
1456 01:32:21.523256 [CATrainingPosCal] consider 1 rank data
1457 01:32:21.523307 u2DelayCellTimex100 = 270/100 ps
1458 01:32:21.523358 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1459 01:32:21.523409 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1460 01:32:21.523461 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1461 01:32:21.523511 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 01:32:21.523562 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1463 01:32:21.523613 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 01:32:21.523666
1465 01:32:21.523725 CA PerBit enable=1, Macro0, CA PI delay=34
1466 01:32:21.523777
1467 01:32:21.523828 [CBTSetCACLKResult] CA Dly = 34
1468 01:32:21.523879 CS Dly: 4 (0~35)
1469 01:32:21.523930 ==
1470 01:32:21.523981 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 01:32:21.524032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 01:32:21.524084 ==
1473 01:32:21.524135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 01:32:21.524186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 01:32:21.524238 [CA 0] Center 37 (6~68) winsize 63
1476 01:32:21.524289 [CA 1] Center 36 (6~67) winsize 62
1477 01:32:21.524341 [CA 2] Center 35 (4~66) winsize 63
1478 01:32:21.524392 [CA 3] Center 34 (4~65) winsize 62
1479 01:32:21.524442 [CA 4] Center 34 (4~65) winsize 62
1480 01:32:21.524493 [CA 5] Center 34 (4~65) winsize 62
1481 01:32:21.524544
1482 01:32:21.524594 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 01:32:21.524645
1484 01:32:21.524696 [CATrainingPosCal] consider 2 rank data
1485 01:32:21.524747 u2DelayCellTimex100 = 270/100 ps
1486 01:32:21.524799 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1487 01:32:21.524850 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1488 01:32:21.524901 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1489 01:32:21.524990 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 01:32:21.525071 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 01:32:21.525122 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 01:32:21.525173
1493 01:32:21.525223 CA PerBit enable=1, Macro0, CA PI delay=34
1494 01:32:21.525281
1495 01:32:21.525333 [CBTSetCACLKResult] CA Dly = 34
1496 01:32:21.525384 CS Dly: 5 (0~37)
1497 01:32:21.525434
1498 01:32:21.525485 ----->DramcWriteLeveling(PI) begin...
1499 01:32:21.525537 ==
1500 01:32:21.525588 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 01:32:21.525639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 01:32:21.525691 ==
1503 01:32:21.525742 Write leveling (Byte 0): 28 => 28
1504 01:32:21.525793 Write leveling (Byte 1): 28 => 28
1505 01:32:21.525844 DramcWriteLeveling(PI) end<-----
1506 01:32:21.525895
1507 01:32:21.525946 ==
1508 01:32:21.525997 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 01:32:21.526048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 01:32:21.526100 ==
1511 01:32:21.526151 [Gating] SW mode calibration
1512 01:32:21.526202 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 01:32:21.526254 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 01:32:21.526305 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 01:32:21.526552 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1516 01:32:21.526713 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 01:32:21.526839 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 01:32:21.526965 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 01:32:21.527090 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 01:32:21.527215 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 01:32:21.527340 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 01:32:21.527465 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 01:32:21.527590 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 01:32:21.527686 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 01:32:21.527739 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 01:32:21.527791 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 01:32:21.527843 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 01:32:21.527895 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:32:21.527946 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:32:21.527997 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:32:21.528048 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1532 01:32:21.528100 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:32:21.528151 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 01:32:21.528202 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 01:32:21.528253 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 01:32:21.528304 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 01:32:21.528355 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 01:32:21.528406 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:32:21.528457 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:32:21.528508 0 9 8 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
1541 01:32:21.528559 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 01:32:21.528609 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 01:32:21.528660 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 01:32:21.528712 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 01:32:21.528763 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 01:32:21.528814 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 01:32:21.528865 0 10 4 | B1->B0 | 3333 3131 | 0 0 | (0 1) (0 1)
1548 01:32:21.528916 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
1549 01:32:21.528967 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 01:32:21.529018 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 01:32:21.529069 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 01:32:21.529119 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 01:32:21.529170 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 01:32:21.529221 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 01:32:21.529303 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1556 01:32:21.529370 0 11 8 | B1->B0 | 3b3b 4242 | 1 0 | (0 0) (0 0)
1557 01:32:21.529421 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 01:32:21.529473 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 01:32:21.529524 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 01:32:21.529575 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 01:32:21.529627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 01:32:21.529678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 01:32:21.529730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1564 01:32:21.529780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1565 01:32:21.529831 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 01:32:21.529883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 01:32:21.529934 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 01:32:21.530017 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 01:32:21.530068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 01:32:21.530119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 01:32:21.530170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 01:32:21.530221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 01:32:21.530272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 01:32:21.530322 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 01:32:21.530373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 01:32:21.530424 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 01:32:21.530475 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 01:32:21.530526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 01:32:21.530577 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1580 01:32:21.530628 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 01:32:21.530679 Total UI for P1: 0, mck2ui 16
1582 01:32:21.530731 best dqsien dly found for B0: ( 0, 14, 4)
1583 01:32:21.530782 Total UI for P1: 0, mck2ui 16
1584 01:32:21.530834 best dqsien dly found for B1: ( 0, 14, 4)
1585 01:32:21.530884 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1586 01:32:21.530936 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1587 01:32:21.530987
1588 01:32:21.531038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 01:32:21.531089 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1590 01:32:21.531141 [Gating] SW calibration Done
1591 01:32:21.531192 ==
1592 01:32:21.531244 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 01:32:21.531295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 01:32:21.531347 ==
1595 01:32:21.531398 RX Vref Scan: 0
1596 01:32:21.531449
1597 01:32:21.531500 RX Vref 0 -> 0, step: 1
1598 01:32:21.531551
1599 01:32:21.531601 RX Delay -130 -> 252, step: 16
1600 01:32:21.531652 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 01:32:21.531704 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1602 01:32:21.531754 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1603 01:32:21.531805 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1604 01:32:21.531856 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1605 01:32:21.532100 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1606 01:32:21.532229 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1607 01:32:21.532353 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1608 01:32:21.532479 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1609 01:32:21.532603 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1610 01:32:21.532678 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1611 01:32:21.532732 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1612 01:32:21.532784 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1613 01:32:21.532836 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1614 01:32:21.532887 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1615 01:32:21.532938 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1616 01:32:21.532990 ==
1617 01:32:21.533041 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 01:32:21.533093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 01:32:21.533144 ==
1620 01:32:21.533195 DQS Delay:
1621 01:32:21.533246 DQS0 = 0, DQS1 = 0
1622 01:32:21.533333 DQM Delay:
1623 01:32:21.533383 DQM0 = 89, DQM1 = 83
1624 01:32:21.533434 DQ Delay:
1625 01:32:21.533485 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1626 01:32:21.533536 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1627 01:32:21.533587 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1628 01:32:21.533639 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1629 01:32:21.533690
1630 01:32:21.533741
1631 01:32:21.533791 ==
1632 01:32:21.533842 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 01:32:21.533893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 01:32:21.533944 ==
1635 01:32:21.533995
1636 01:32:21.534046
1637 01:32:21.534096 TX Vref Scan disable
1638 01:32:21.534147 == TX Byte 0 ==
1639 01:32:21.534198 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1640 01:32:21.534250 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1641 01:32:21.534301 == TX Byte 1 ==
1642 01:32:21.534352 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 01:32:21.534403 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 01:32:21.534454 ==
1645 01:32:21.534505 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 01:32:21.534556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 01:32:21.534607 ==
1648 01:32:21.534658 TX Vref=22, minBit 3, minWin=26, winSum=437
1649 01:32:21.534709 TX Vref=24, minBit 2, minWin=27, winSum=446
1650 01:32:21.534760 TX Vref=26, minBit 0, minWin=27, winSum=448
1651 01:32:21.534811 TX Vref=28, minBit 4, minWin=27, winSum=452
1652 01:32:21.534863 TX Vref=30, minBit 0, minWin=27, winSum=453
1653 01:32:21.534914 TX Vref=32, minBit 0, minWin=27, winSum=452
1654 01:32:21.534965 [TxChooseVref] Worse bit 0, Min win 27, Win sum 453, Final Vref 30
1655 01:32:21.535016
1656 01:32:21.535067 Final TX Range 1 Vref 30
1657 01:32:21.535118
1658 01:32:21.535169 ==
1659 01:32:21.535219 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 01:32:21.535271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 01:32:21.535322 ==
1662 01:32:21.535373
1663 01:32:21.535423
1664 01:32:21.535473 TX Vref Scan disable
1665 01:32:21.535524 == TX Byte 0 ==
1666 01:32:21.535575 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1667 01:32:21.535626 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1668 01:32:21.535677 == TX Byte 1 ==
1669 01:32:21.535728 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1670 01:32:21.535780 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1671 01:32:21.535832
1672 01:32:21.535882 [DATLAT]
1673 01:32:21.535932 Freq=800, CH1 RK0
1674 01:32:21.535983
1675 01:32:21.536033 DATLAT Default: 0xa
1676 01:32:21.536084 0, 0xFFFF, sum = 0
1677 01:32:21.536136 1, 0xFFFF, sum = 0
1678 01:32:21.536189 2, 0xFFFF, sum = 0
1679 01:32:21.536240 3, 0xFFFF, sum = 0
1680 01:32:21.536292 4, 0xFFFF, sum = 0
1681 01:32:21.536344 5, 0xFFFF, sum = 0
1682 01:32:21.536395 6, 0xFFFF, sum = 0
1683 01:32:21.536447 7, 0xFFFF, sum = 0
1684 01:32:21.536499 8, 0xFFFF, sum = 0
1685 01:32:21.536550 9, 0x0, sum = 1
1686 01:32:21.536602 10, 0x0, sum = 2
1687 01:32:21.536653 11, 0x0, sum = 3
1688 01:32:21.536705 12, 0x0, sum = 4
1689 01:32:21.536756 best_step = 10
1690 01:32:21.536807
1691 01:32:21.536857 ==
1692 01:32:21.536908 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 01:32:21.536958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 01:32:21.537030 ==
1695 01:32:21.537111 RX Vref Scan: 1
1696 01:32:21.537191
1697 01:32:21.537315 Set Vref Range= 32 -> 127
1698 01:32:21.537371
1699 01:32:21.537422 RX Vref 32 -> 127, step: 1
1700 01:32:21.537473
1701 01:32:21.537524 RX Delay -79 -> 252, step: 8
1702 01:32:21.537575
1703 01:32:21.537626 Set Vref, RX VrefLevel [Byte0]: 32
1704 01:32:21.537677 [Byte1]: 32
1705 01:32:21.537728
1706 01:32:21.537778 Set Vref, RX VrefLevel [Byte0]: 33
1707 01:32:21.537829 [Byte1]: 33
1708 01:32:21.537880
1709 01:32:21.537930 Set Vref, RX VrefLevel [Byte0]: 34
1710 01:32:21.537981 [Byte1]: 34
1711 01:32:21.538031
1712 01:32:21.538081 Set Vref, RX VrefLevel [Byte0]: 35
1713 01:32:21.538132 [Byte1]: 35
1714 01:32:21.538183
1715 01:32:21.538234 Set Vref, RX VrefLevel [Byte0]: 36
1716 01:32:21.538285 [Byte1]: 36
1717 01:32:21.538374
1718 01:32:21.538425 Set Vref, RX VrefLevel [Byte0]: 37
1719 01:32:21.538475 [Byte1]: 37
1720 01:32:21.538526
1721 01:32:21.538576 Set Vref, RX VrefLevel [Byte0]: 38
1722 01:32:21.538627 [Byte1]: 38
1723 01:32:21.538677
1724 01:32:21.538727 Set Vref, RX VrefLevel [Byte0]: 39
1725 01:32:21.538778 [Byte1]: 39
1726 01:32:21.538829
1727 01:32:21.538879 Set Vref, RX VrefLevel [Byte0]: 40
1728 01:32:21.538929 [Byte1]: 40
1729 01:32:21.538980
1730 01:32:21.539030 Set Vref, RX VrefLevel [Byte0]: 41
1731 01:32:21.539081 [Byte1]: 41
1732 01:32:21.539131
1733 01:32:21.539181 Set Vref, RX VrefLevel [Byte0]: 42
1734 01:32:21.539232 [Byte1]: 42
1735 01:32:21.539283
1736 01:32:21.539333 Set Vref, RX VrefLevel [Byte0]: 43
1737 01:32:21.539384 [Byte1]: 43
1738 01:32:21.539435
1739 01:32:21.539485 Set Vref, RX VrefLevel [Byte0]: 44
1740 01:32:21.539536 [Byte1]: 44
1741 01:32:21.539586
1742 01:32:21.539637 Set Vref, RX VrefLevel [Byte0]: 45
1743 01:32:21.539688 [Byte1]: 45
1744 01:32:21.539739
1745 01:32:21.539789 Set Vref, RX VrefLevel [Byte0]: 46
1746 01:32:21.539840 [Byte1]: 46
1747 01:32:21.539891
1748 01:32:21.539940 Set Vref, RX VrefLevel [Byte0]: 47
1749 01:32:21.539991 [Byte1]: 47
1750 01:32:21.540041
1751 01:32:21.540091 Set Vref, RX VrefLevel [Byte0]: 48
1752 01:32:21.540142 [Byte1]: 48
1753 01:32:21.540193
1754 01:32:21.540243 Set Vref, RX VrefLevel [Byte0]: 49
1755 01:32:21.540293 [Byte1]: 49
1756 01:32:21.540344
1757 01:32:21.540394 Set Vref, RX VrefLevel [Byte0]: 50
1758 01:32:21.540446 [Byte1]: 50
1759 01:32:21.540497
1760 01:32:21.540547 Set Vref, RX VrefLevel [Byte0]: 51
1761 01:32:21.540598 [Byte1]: 51
1762 01:32:21.540649
1763 01:32:21.540699 Set Vref, RX VrefLevel [Byte0]: 52
1764 01:32:21.540942 [Byte1]: 52
1765 01:32:21.541002
1766 01:32:21.541054 Set Vref, RX VrefLevel [Byte0]: 53
1767 01:32:21.541104 [Byte1]: 53
1768 01:32:21.541155
1769 01:32:21.541205 Set Vref, RX VrefLevel [Byte0]: 54
1770 01:32:21.541260 [Byte1]: 54
1771 01:32:21.541349
1772 01:32:21.541400 Set Vref, RX VrefLevel [Byte0]: 55
1773 01:32:21.541451 [Byte1]: 55
1774 01:32:21.541501
1775 01:32:21.541552 Set Vref, RX VrefLevel [Byte0]: 56
1776 01:32:21.541603 [Byte1]: 56
1777 01:32:21.541654
1778 01:32:21.541705 Set Vref, RX VrefLevel [Byte0]: 57
1779 01:32:21.541755 [Byte1]: 57
1780 01:32:21.541806
1781 01:32:21.541856 Set Vref, RX VrefLevel [Byte0]: 58
1782 01:32:21.541907 [Byte1]: 58
1783 01:32:21.541958
1784 01:32:21.542007 Set Vref, RX VrefLevel [Byte0]: 59
1785 01:32:21.542058 [Byte1]: 59
1786 01:32:21.542108
1787 01:32:21.542159 Set Vref, RX VrefLevel [Byte0]: 60
1788 01:32:21.542209 [Byte1]: 60
1789 01:32:21.542259
1790 01:32:21.542310 Set Vref, RX VrefLevel [Byte0]: 61
1791 01:32:21.542361 [Byte1]: 61
1792 01:32:21.542411
1793 01:32:21.542461 Set Vref, RX VrefLevel [Byte0]: 62
1794 01:32:21.542512 [Byte1]: 62
1795 01:32:21.542562
1796 01:32:21.542612 Set Vref, RX VrefLevel [Byte0]: 63
1797 01:32:21.542663 [Byte1]: 63
1798 01:32:21.542714
1799 01:32:21.542765 Set Vref, RX VrefLevel [Byte0]: 64
1800 01:32:21.542816 [Byte1]: 64
1801 01:32:21.542867
1802 01:32:21.542917 Set Vref, RX VrefLevel [Byte0]: 65
1803 01:32:21.542967 [Byte1]: 65
1804 01:32:21.543018
1805 01:32:21.543068 Set Vref, RX VrefLevel [Byte0]: 66
1806 01:32:21.543119 [Byte1]: 66
1807 01:32:21.543169
1808 01:32:21.543220 Set Vref, RX VrefLevel [Byte0]: 67
1809 01:32:21.543270 [Byte1]: 67
1810 01:32:21.543321
1811 01:32:21.543371 Set Vref, RX VrefLevel [Byte0]: 68
1812 01:32:21.543422 [Byte1]: 68
1813 01:32:21.543472
1814 01:32:21.543523 Set Vref, RX VrefLevel [Byte0]: 69
1815 01:32:21.543573 [Byte1]: 69
1816 01:32:21.543624
1817 01:32:21.543674 Set Vref, RX VrefLevel [Byte0]: 70
1818 01:32:21.543725 [Byte1]: 70
1819 01:32:21.543775
1820 01:32:21.543825 Set Vref, RX VrefLevel [Byte0]: 71
1821 01:32:21.543876 [Byte1]: 71
1822 01:32:21.543926
1823 01:32:21.543977 Set Vref, RX VrefLevel [Byte0]: 72
1824 01:32:21.544028 [Byte1]: 72
1825 01:32:21.544078
1826 01:32:21.544129 Set Vref, RX VrefLevel [Byte0]: 73
1827 01:32:21.544179 [Byte1]: 73
1828 01:32:21.544229
1829 01:32:21.544279 Set Vref, RX VrefLevel [Byte0]: 74
1830 01:32:21.544355 [Byte1]: 74
1831 01:32:21.544437
1832 01:32:21.544501 Set Vref, RX VrefLevel [Byte0]: 75
1833 01:32:21.544551 [Byte1]: 75
1834 01:32:21.544602
1835 01:32:21.544652 Final RX Vref Byte 0 = 58 to rank0
1836 01:32:21.544704 Final RX Vref Byte 1 = 58 to rank0
1837 01:32:21.544754 Final RX Vref Byte 0 = 58 to rank1
1838 01:32:21.544806 Final RX Vref Byte 1 = 58 to rank1==
1839 01:32:21.544857 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 01:32:21.544908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 01:32:21.544959 ==
1842 01:32:21.545011 DQS Delay:
1843 01:32:21.545061 DQS0 = 0, DQS1 = 0
1844 01:32:21.545112 DQM Delay:
1845 01:32:21.545163 DQM0 = 86, DQM1 = 81
1846 01:32:21.545214 DQ Delay:
1847 01:32:21.545272 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1848 01:32:21.545325 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =84
1849 01:32:21.545376 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1850 01:32:21.545427 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1851 01:32:21.545478
1852 01:32:21.545528
1853 01:32:21.545578 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1854 01:32:21.545630 CH1 RK0: MR19=606, MR18=1A2D
1855 01:32:21.545682 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1856 01:32:21.545733
1857 01:32:21.545784 ----->DramcWriteLeveling(PI) begin...
1858 01:32:21.545836 ==
1859 01:32:21.545887 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 01:32:21.545938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 01:32:21.545989 ==
1862 01:32:21.546040 Write leveling (Byte 0): 27 => 27
1863 01:32:21.546091 Write leveling (Byte 1): 28 => 28
1864 01:32:21.546141 DramcWriteLeveling(PI) end<-----
1865 01:32:21.546191
1866 01:32:21.546241 ==
1867 01:32:21.546292 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 01:32:21.546343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 01:32:21.546394 ==
1870 01:32:21.546445 [Gating] SW mode calibration
1871 01:32:21.546496 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 01:32:21.546547 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 01:32:21.546598 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 01:32:21.546649 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1875 01:32:21.546701 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 01:32:21.546752 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 01:32:21.546803 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 01:32:21.546854 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 01:32:21.546904 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 01:32:21.546955 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 01:32:21.547007 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 01:32:21.547058 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 01:32:21.547109 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 01:32:21.547160 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 01:32:21.547211 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 01:32:21.547261 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 01:32:21.547312 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 01:32:21.547363 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 01:32:21.547414 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1890 01:32:21.547464 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1891 01:32:21.547515 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 01:32:21.547566 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 01:32:21.547617 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 01:32:21.547668 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 01:32:21.547913 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 01:32:21.548045 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 01:32:21.548172 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 01:32:21.548296 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1899 01:32:21.548421 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1900 01:32:21.548545 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 01:32:21.548669 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 01:32:21.548793 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 01:32:21.548917 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 01:32:21.549042 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 01:32:21.549143 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 01:32:21.549227 0 10 4 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (0 0)
1907 01:32:21.549333 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
1908 01:32:21.549388 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 01:32:21.549440 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 01:32:21.549492 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 01:32:21.549544 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 01:32:21.549596 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 01:32:21.549647 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 01:32:21.549699 0 11 4 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
1915 01:32:21.549750 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1916 01:32:21.549801 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 01:32:21.549853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 01:32:21.549904 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 01:32:21.549955 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 01:32:21.550007 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 01:32:21.550058 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1922 01:32:21.550109 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1923 01:32:21.550160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 01:32:21.550211 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 01:32:21.550261 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 01:32:21.550312 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 01:32:21.550363 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 01:32:21.550414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 01:32:21.550465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 01:32:21.550516 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 01:32:21.550567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 01:32:21.550617 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 01:32:21.550668 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 01:32:21.550718 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 01:32:21.550769 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 01:32:21.550820 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 01:32:21.550871 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 01:32:21.550922 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1939 01:32:21.550973 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1940 01:32:21.551024 Total UI for P1: 0, mck2ui 16
1941 01:32:21.551076 best dqsien dly found for B0: ( 0, 14, 4)
1942 01:32:21.551127 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 01:32:21.551178 Total UI for P1: 0, mck2ui 16
1944 01:32:21.551230 best dqsien dly found for B1: ( 0, 14, 6)
1945 01:32:21.551281 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1946 01:32:21.551332 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1947 01:32:21.551383
1948 01:32:21.551435 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1949 01:32:21.551486 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1950 01:32:21.551537 [Gating] SW calibration Done
1951 01:32:21.551588 ==
1952 01:32:21.551639 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 01:32:21.551690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 01:32:21.551742 ==
1955 01:32:21.551793 RX Vref Scan: 0
1956 01:32:21.551843
1957 01:32:21.551895 RX Vref 0 -> 0, step: 1
1958 01:32:21.551945
1959 01:32:21.551996 RX Delay -130 -> 252, step: 16
1960 01:32:21.552046 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1961 01:32:21.552097 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1962 01:32:21.552148 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1963 01:32:21.552199 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1964 01:32:21.552250 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1965 01:32:21.552300 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1966 01:32:21.552351 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1967 01:32:21.552402 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1968 01:32:21.552453 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1969 01:32:21.552504 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1970 01:32:21.552555 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1971 01:32:21.552605 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1972 01:32:21.552656 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1973 01:32:21.552707 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1974 01:32:21.552758 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1975 01:32:21.552808 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1976 01:32:21.552859 ==
1977 01:32:21.552909 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 01:32:21.552960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 01:32:21.553011 ==
1980 01:32:21.553062 DQS Delay:
1981 01:32:21.553113 DQS0 = 0, DQS1 = 0
1982 01:32:21.553163 DQM Delay:
1983 01:32:21.553214 DQM0 = 86, DQM1 = 85
1984 01:32:21.553269 DQ Delay:
1985 01:32:21.553353 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1986 01:32:21.553404 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1987 01:32:21.553455 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1988 01:32:21.715223 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1989 01:32:21.715700
1990 01:32:21.716021
1991 01:32:21.716316 ==
1992 01:32:21.716607 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 01:32:21.716892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 01:32:21.717176 ==
1995 01:32:21.717515
1996 01:32:21.717792
1997 01:32:21.718063 TX Vref Scan disable
1998 01:32:21.718332 == TX Byte 0 ==
1999 01:32:21.718602 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2000 01:32:21.719265 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2001 01:32:21.719937 == TX Byte 1 ==
2002 01:32:21.720587 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2003 01:32:21.721243 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2004 01:32:21.721932 ==
2005 01:32:21.722291 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 01:32:21.722576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 01:32:21.722851 ==
2008 01:32:21.723120 TX Vref=22, minBit 2, minWin=26, winSum=441
2009 01:32:21.723393 TX Vref=24, minBit 4, minWin=26, winSum=443
2010 01:32:21.723661 TX Vref=26, minBit 1, minWin=27, winSum=448
2011 01:32:21.723927 TX Vref=28, minBit 5, minWin=27, winSum=453
2012 01:32:21.724260 TX Vref=30, minBit 2, minWin=27, winSum=454
2013 01:32:21.724533 TX Vref=32, minBit 0, minWin=27, winSum=452
2014 01:32:21.724801 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
2015 01:32:21.725069
2016 01:32:21.725378 Final TX Range 1 Vref 30
2017 01:32:21.725658
2018 01:32:21.725919 ==
2019 01:32:21.726183 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 01:32:21.726449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 01:32:21.726713 ==
2022 01:32:21.726979
2023 01:32:21.727241
2024 01:32:21.727504 TX Vref Scan disable
2025 01:32:21.727770 == TX Byte 0 ==
2026 01:32:21.728033 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2027 01:32:21.728301 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2028 01:32:21.728566 == TX Byte 1 ==
2029 01:32:21.728828 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2030 01:32:21.729096 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2031 01:32:21.729381
2032 01:32:21.729645 [DATLAT]
2033 01:32:21.729908 Freq=800, CH1 RK1
2034 01:32:21.730173
2035 01:32:21.730434 DATLAT Default: 0xa
2036 01:32:21.730698 0, 0xFFFF, sum = 0
2037 01:32:21.730971 1, 0xFFFF, sum = 0
2038 01:32:21.731243 2, 0xFFFF, sum = 0
2039 01:32:21.731510 3, 0xFFFF, sum = 0
2040 01:32:21.731779 4, 0xFFFF, sum = 0
2041 01:32:21.732041 5, 0xFFFF, sum = 0
2042 01:32:21.732307 6, 0xFFFF, sum = 0
2043 01:32:21.732574 7, 0xFFFF, sum = 0
2044 01:32:21.732845 8, 0xFFFF, sum = 0
2045 01:32:21.733112 9, 0x0, sum = 1
2046 01:32:21.733398 10, 0x0, sum = 2
2047 01:32:21.733669 11, 0x0, sum = 3
2048 01:32:21.733936 12, 0x0, sum = 4
2049 01:32:21.734203 best_step = 10
2050 01:32:21.734460
2051 01:32:21.734722 ==
2052 01:32:21.734987 Dram Type= 6, Freq= 0, CH_1, rank 1
2053 01:32:21.735249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2054 01:32:21.735512 ==
2055 01:32:21.735776 RX Vref Scan: 0
2056 01:32:21.736039
2057 01:32:21.736301 RX Vref 0 -> 0, step: 1
2058 01:32:21.736563
2059 01:32:21.736820 RX Delay -95 -> 252, step: 8
2060 01:32:21.737084 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2061 01:32:21.737405 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2062 01:32:21.737709 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2063 01:32:21.737976 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2064 01:32:21.738239 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2065 01:32:21.738505 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2066 01:32:21.738770 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2067 01:32:21.739033 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2068 01:32:21.739310 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2069 01:32:21.739500 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2070 01:32:21.739689 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2071 01:32:21.739878 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2072 01:32:21.740066 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2073 01:32:21.740255 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2074 01:32:21.740441 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2075 01:32:21.740629 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2076 01:32:21.740817 ==
2077 01:32:21.741007 Dram Type= 6, Freq= 0, CH_1, rank 1
2078 01:32:21.741196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2079 01:32:21.741402 ==
2080 01:32:21.741591 DQS Delay:
2081 01:32:21.741778 DQS0 = 0, DQS1 = 0
2082 01:32:21.741967 DQM Delay:
2083 01:32:21.742153 DQM0 = 86, DQM1 = 83
2084 01:32:21.742341 DQ Delay:
2085 01:32:21.742527 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2086 01:32:21.742715 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2087 01:32:21.742903 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
2088 01:32:21.743091 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2089 01:32:21.743277
2090 01:32:21.743464
2091 01:32:21.743653 [DQSOSCAuto] RK1, (LSB)MR18= 0x203b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2092 01:32:21.743848 CH1 RK1: MR19=606, MR18=203B
2093 01:32:21.744038 CH1_RK1: MR19=0x606, MR18=0x203B, DQSOSC=394, MR23=63, INC=95, DEC=63
2094 01:32:21.744228 [RxdqsGatingPostProcess] freq 800
2095 01:32:21.744400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2096 01:32:21.744543 Pre-setting of DQS Precalculation
2097 01:32:21.744686 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2098 01:32:21.744830 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2099 01:32:21.744975 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2100 01:32:21.745118
2101 01:32:21.745276
2102 01:32:21.745422 [Calibration Summary] 1600 Mbps
2103 01:32:21.745567 CH 0, Rank 0
2104 01:32:21.745710 SW Impedance : PASS
2105 01:32:21.745853 DUTY Scan : NO K
2106 01:32:21.745996 ZQ Calibration : PASS
2107 01:32:21.746140 Jitter Meter : NO K
2108 01:32:21.746283 CBT Training : PASS
2109 01:32:21.746425 Write leveling : PASS
2110 01:32:21.746567 RX DQS gating : PASS
2111 01:32:21.746709 RX DQ/DQS(RDDQC) : PASS
2112 01:32:21.746853 TX DQ/DQS : PASS
2113 01:32:21.746996 RX DATLAT : PASS
2114 01:32:21.747140 RX DQ/DQS(Engine): PASS
2115 01:32:21.747282 TX OE : NO K
2116 01:32:21.747424 All Pass.
2117 01:32:21.747566
2118 01:32:21.747707 CH 0, Rank 1
2119 01:32:21.747848 SW Impedance : PASS
2120 01:32:21.747990 DUTY Scan : NO K
2121 01:32:21.748132 ZQ Calibration : PASS
2122 01:32:21.748275 Jitter Meter : NO K
2123 01:32:21.748417 CBT Training : PASS
2124 01:32:21.748558 Write leveling : PASS
2125 01:32:21.748699 RX DQS gating : PASS
2126 01:32:21.748842 RX DQ/DQS(RDDQC) : PASS
2127 01:32:21.748984 TX DQ/DQS : PASS
2128 01:32:21.749127 RX DATLAT : PASS
2129 01:32:21.749279 RX DQ/DQS(Engine): PASS
2130 01:32:21.749417 TX OE : NO K
2131 01:32:21.749532 All Pass.
2132 01:32:21.749647
2133 01:32:21.749760 CH 1, Rank 0
2134 01:32:21.749874 SW Impedance : PASS
2135 01:32:21.749989 DUTY Scan : NO K
2136 01:32:21.750104 ZQ Calibration : PASS
2137 01:32:21.750218 Jitter Meter : NO K
2138 01:32:21.750333 CBT Training : PASS
2139 01:32:21.750447 Write leveling : PASS
2140 01:32:21.750561 RX DQS gating : PASS
2141 01:32:21.750676 RX DQ/DQS(RDDQC) : PASS
2142 01:32:21.750790 TX DQ/DQS : PASS
2143 01:32:21.750905 RX DATLAT : PASS
2144 01:32:21.751018 RX DQ/DQS(Engine): PASS
2145 01:32:21.751381 TX OE : NO K
2146 01:32:21.751512 All Pass.
2147 01:32:21.751629
2148 01:32:21.751745 CH 1, Rank 1
2149 01:32:21.751859 SW Impedance : PASS
2150 01:32:21.751975 DUTY Scan : NO K
2151 01:32:21.752091 ZQ Calibration : PASS
2152 01:32:21.752205 Jitter Meter : NO K
2153 01:32:21.752320 CBT Training : PASS
2154 01:32:21.752434 Write leveling : PASS
2155 01:32:21.752547 RX DQS gating : PASS
2156 01:32:21.752661 RX DQ/DQS(RDDQC) : PASS
2157 01:32:21.752776 TX DQ/DQS : PASS
2158 01:32:21.752891 RX DATLAT : PASS
2159 01:32:21.753006 RX DQ/DQS(Engine): PASS
2160 01:32:21.753121 TX OE : NO K
2161 01:32:21.753236 All Pass.
2162 01:32:21.753364
2163 01:32:21.753479 DramC Write-DBI off
2164 01:32:21.753594 PER_BANK_REFRESH: Hybrid Mode
2165 01:32:21.753710 TX_TRACKING: ON
2166 01:32:21.753826 [GetDramInforAfterCalByMRR] Vendor 6.
2167 01:32:21.753940 [GetDramInforAfterCalByMRR] Revision 606.
2168 01:32:21.754056 [GetDramInforAfterCalByMRR] Revision 2 0.
2169 01:32:21.754170 MR0 0x3b3b
2170 01:32:21.754286 MR8 0x5151
2171 01:32:21.754401 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 01:32:21.754497
2173 01:32:21.754592 MR0 0x3b3b
2174 01:32:21.754687 MR8 0x5151
2175 01:32:21.754782 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 01:32:21.754878
2177 01:32:21.754973 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2178 01:32:21.755072 [FAST_K] Save calibration result to emmc
2179 01:32:21.755170 [FAST_K] Save calibration result to emmc
2180 01:32:21.755266 dram_init: config_dvfs: 1
2181 01:32:21.755362 dramc_set_vcore_voltage set vcore to 662500
2182 01:32:21.755459 Read voltage for 1200, 2
2183 01:32:21.755556 Vio18 = 0
2184 01:32:21.755652 Vcore = 662500
2185 01:32:21.755748 Vdram = 0
2186 01:32:21.755843 Vddq = 0
2187 01:32:21.755939 Vmddr = 0
2188 01:32:21.756035 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2189 01:32:21.756132 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2190 01:32:21.756229 MEM_TYPE=3, freq_sel=15
2191 01:32:21.756325 sv_algorithm_assistance_LP4_1600
2192 01:32:21.756420 ============ PULL DRAM RESETB DOWN ============
2193 01:32:21.756517 ========== PULL DRAM RESETB DOWN end =========
2194 01:32:21.756615 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2195 01:32:21.756712 ===================================
2196 01:32:21.756809 LPDDR4 DRAM CONFIGURATION
2197 01:32:21.756905 ===================================
2198 01:32:21.757001 EX_ROW_EN[0] = 0x0
2199 01:32:21.757097 EX_ROW_EN[1] = 0x0
2200 01:32:21.757192 LP4Y_EN = 0x0
2201 01:32:21.757294 WORK_FSP = 0x0
2202 01:32:21.757390 WL = 0x4
2203 01:32:21.757486 RL = 0x4
2204 01:32:21.757582 BL = 0x2
2205 01:32:21.757676 RPST = 0x0
2206 01:32:21.757771 RD_PRE = 0x0
2207 01:32:21.757865 WR_PRE = 0x1
2208 01:32:21.757961 WR_PST = 0x0
2209 01:32:21.758055 DBI_WR = 0x0
2210 01:32:21.758151 DBI_RD = 0x0
2211 01:32:21.758245 OTF = 0x1
2212 01:32:21.758342 ===================================
2213 01:32:21.758438 ===================================
2214 01:32:21.758534 ANA top config
2215 01:32:21.758629 ===================================
2216 01:32:21.758724 DLL_ASYNC_EN = 0
2217 01:32:21.758820 ALL_SLAVE_EN = 0
2218 01:32:21.758914 NEW_RANK_MODE = 1
2219 01:32:21.759011 DLL_IDLE_MODE = 1
2220 01:32:21.759106 LP45_APHY_COMB_EN = 1
2221 01:32:21.759202 TX_ODT_DIS = 1
2222 01:32:21.759298 NEW_8X_MODE = 1
2223 01:32:21.759396 ===================================
2224 01:32:21.759478 ===================================
2225 01:32:21.759561 data_rate = 2400
2226 01:32:21.759643 CKR = 1
2227 01:32:21.759725 DQ_P2S_RATIO = 8
2228 01:32:21.759808 ===================================
2229 01:32:21.759889 CA_P2S_RATIO = 8
2230 01:32:21.759971 DQ_CA_OPEN = 0
2231 01:32:21.760053 DQ_SEMI_OPEN = 0
2232 01:32:21.760135 CA_SEMI_OPEN = 0
2233 01:32:21.760216 CA_FULL_RATE = 0
2234 01:32:21.760298 DQ_CKDIV4_EN = 0
2235 01:32:21.760381 CA_CKDIV4_EN = 0
2236 01:32:21.760463 CA_PREDIV_EN = 0
2237 01:32:21.760544 PH8_DLY = 17
2238 01:32:21.760627 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2239 01:32:21.760708 DQ_AAMCK_DIV = 4
2240 01:32:21.760790 CA_AAMCK_DIV = 4
2241 01:32:21.760872 CA_ADMCK_DIV = 4
2242 01:32:21.760954 DQ_TRACK_CA_EN = 0
2243 01:32:21.761035 CA_PICK = 1200
2244 01:32:21.761117 CA_MCKIO = 1200
2245 01:32:21.761199 MCKIO_SEMI = 0
2246 01:32:21.761286 PLL_FREQ = 2366
2247 01:32:21.761370 DQ_UI_PI_RATIO = 32
2248 01:32:21.761452 CA_UI_PI_RATIO = 0
2249 01:32:21.761534 ===================================
2250 01:32:21.761616 ===================================
2251 01:32:21.761698 memory_type:LPDDR4
2252 01:32:21.761781 GP_NUM : 10
2253 01:32:21.761864 SRAM_EN : 1
2254 01:32:21.761946 MD32_EN : 0
2255 01:32:21.762027 ===================================
2256 01:32:21.762110 [ANA_INIT] >>>>>>>>>>>>>>
2257 01:32:21.762192 <<<<<< [CONFIGURE PHASE]: ANA_TX
2258 01:32:21.762276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2259 01:32:21.762357 ===================================
2260 01:32:21.762440 data_rate = 2400,PCW = 0X5b00
2261 01:32:21.762521 ===================================
2262 01:32:21.762604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2263 01:32:21.762686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 01:32:21.762769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 01:32:21.762852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2266 01:32:21.762935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2267 01:32:21.763018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2268 01:32:21.763100 [ANA_INIT] flow start
2269 01:32:21.763182 [ANA_INIT] PLL >>>>>>>>
2270 01:32:21.763264 [ANA_INIT] PLL <<<<<<<<
2271 01:32:21.763345 [ANA_INIT] MIDPI >>>>>>>>
2272 01:32:21.763426 [ANA_INIT] MIDPI <<<<<<<<
2273 01:32:21.763508 [ANA_INIT] DLL >>>>>>>>
2274 01:32:21.763589 [ANA_INIT] DLL <<<<<<<<
2275 01:32:21.763671 [ANA_INIT] flow end
2276 01:32:21.763753 ============ LP4 DIFF to SE enter ============
2277 01:32:21.763836 ============ LP4 DIFF to SE exit ============
2278 01:32:21.763919 [ANA_INIT] <<<<<<<<<<<<<
2279 01:32:21.764001 [Flow] Enable top DCM control >>>>>
2280 01:32:21.764083 [Flow] Enable top DCM control <<<<<
2281 01:32:21.764376 Enable DLL master slave shuffle
2282 01:32:21.764560 ==============================================================
2283 01:32:21.764737 Gating Mode config
2284 01:32:21.764913 ==============================================================
2285 01:32:21.765090 Config description:
2286 01:32:21.765284 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2287 01:32:21.765469 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2288 01:32:21.765649 SELPH_MODE 0: By rank 1: By Phase
2289 01:32:21.765826 ==============================================================
2290 01:32:21.765993 GAT_TRACK_EN = 1
2291 01:32:21.766074 RX_GATING_MODE = 2
2292 01:32:21.766150 RX_GATING_TRACK_MODE = 2
2293 01:32:21.766224 SELPH_MODE = 1
2294 01:32:21.766297 PICG_EARLY_EN = 1
2295 01:32:21.766369 VALID_LAT_VALUE = 1
2296 01:32:21.766442 ==============================================================
2297 01:32:21.766516 Enter into Gating configuration >>>>
2298 01:32:21.766589 Exit from Gating configuration <<<<
2299 01:32:21.766662 Enter into DVFS_PRE_config >>>>>
2300 01:32:21.766735 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2301 01:32:21.766810 Exit from DVFS_PRE_config <<<<<
2302 01:32:21.766882 Enter into PICG configuration >>>>
2303 01:32:21.766954 Exit from PICG configuration <<<<
2304 01:32:21.767027 [RX_INPUT] configuration >>>>>
2305 01:32:21.767099 [RX_INPUT] configuration <<<<<
2306 01:32:21.767172 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2307 01:32:21.767245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2308 01:32:21.767318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 01:32:21.767392 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 01:32:21.767464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 01:32:21.767538 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 01:32:21.767610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2313 01:32:21.767682 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2314 01:32:21.767755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2315 01:32:21.767828 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2316 01:32:21.767900 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2317 01:32:21.767972 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 01:32:21.768045 ===================================
2319 01:32:21.768118 LPDDR4 DRAM CONFIGURATION
2320 01:32:21.768190 ===================================
2321 01:32:21.768263 EX_ROW_EN[0] = 0x0
2322 01:32:21.768340 EX_ROW_EN[1] = 0x0
2323 01:32:21.768412 LP4Y_EN = 0x0
2324 01:32:21.768508 WORK_FSP = 0x0
2325 01:32:21.768583 WL = 0x4
2326 01:32:21.768656 RL = 0x4
2327 01:32:21.768728 BL = 0x2
2328 01:32:21.768801 RPST = 0x0
2329 01:32:21.768872 RD_PRE = 0x0
2330 01:32:21.768945 WR_PRE = 0x1
2331 01:32:21.769017 WR_PST = 0x0
2332 01:32:21.769088 DBI_WR = 0x0
2333 01:32:21.769159 DBI_RD = 0x0
2334 01:32:21.769231 OTF = 0x1
2335 01:32:21.769350 ===================================
2336 01:32:21.769418 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2337 01:32:21.769483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2338 01:32:21.769548 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2339 01:32:21.769613 ===================================
2340 01:32:21.769679 LPDDR4 DRAM CONFIGURATION
2341 01:32:21.769743 ===================================
2342 01:32:21.769807 EX_ROW_EN[0] = 0x10
2343 01:32:21.769872 EX_ROW_EN[1] = 0x0
2344 01:32:21.769936 LP4Y_EN = 0x0
2345 01:32:21.770000 WORK_FSP = 0x0
2346 01:32:21.770063 WL = 0x4
2347 01:32:21.770127 RL = 0x4
2348 01:32:21.770191 BL = 0x2
2349 01:32:21.770255 RPST = 0x0
2350 01:32:21.770317 RD_PRE = 0x0
2351 01:32:21.770381 WR_PRE = 0x1
2352 01:32:21.770444 WR_PST = 0x0
2353 01:32:21.770508 DBI_WR = 0x0
2354 01:32:21.770571 DBI_RD = 0x0
2355 01:32:21.770634 OTF = 0x1
2356 01:32:21.770698 ===================================
2357 01:32:21.770762 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2358 01:32:21.770827 ==
2359 01:32:21.770891 Dram Type= 6, Freq= 0, CH_0, rank 0
2360 01:32:21.770956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 01:32:21.771022 ==
2362 01:32:21.771086 [Duty_Offset_Calibration]
2363 01:32:21.771150 B0:2 B1:0 CA:4
2364 01:32:21.771224
2365 01:32:21.771291 [DutyScan_Calibration_Flow] k_type=0
2366 01:32:21.771354
2367 01:32:21.771418 ==CLK 0==
2368 01:32:21.771481 Final CLK duty delay cell = -4
2369 01:32:21.771546 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2370 01:32:21.771610 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2371 01:32:21.771674 [-4] AVG Duty = 4937%(X100)
2372 01:32:21.771738
2373 01:32:21.771801 CH0 CLK Duty spec in!! Max-Min= 187%
2374 01:32:21.771865 [DutyScan_Calibration_Flow] ====Done====
2375 01:32:21.771929
2376 01:32:21.771991 [DutyScan_Calibration_Flow] k_type=1
2377 01:32:21.772054
2378 01:32:21.772117 ==DQS 0 ==
2379 01:32:21.772180 Final DQS duty delay cell = 0
2380 01:32:21.772243 [0] MAX Duty = 5156%(X100), DQS PI = 18
2381 01:32:21.772307 [0] MIN Duty = 5093%(X100), DQS PI = 0
2382 01:32:21.772370 [0] AVG Duty = 5124%(X100)
2383 01:32:21.772434
2384 01:32:21.772496 ==DQS 1 ==
2385 01:32:21.772560 Final DQS duty delay cell = 0
2386 01:32:21.772624 [0] MAX Duty = 5093%(X100), DQS PI = 4
2387 01:32:21.772688 [0] MIN Duty = 5000%(X100), DQS PI = 0
2388 01:32:21.772752 [0] AVG Duty = 5046%(X100)
2389 01:32:21.772815
2390 01:32:21.772878 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2391 01:32:21.772941
2392 01:32:21.773004 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2393 01:32:21.773067 [DutyScan_Calibration_Flow] ====Done====
2394 01:32:21.773130
2395 01:32:21.773193 [DutyScan_Calibration_Flow] k_type=3
2396 01:32:21.773261
2397 01:32:21.773325 ==DQM 0 ==
2398 01:32:21.773389 Final DQM duty delay cell = 0
2399 01:32:21.773453 [0] MAX Duty = 5125%(X100), DQS PI = 20
2400 01:32:21.773517 [0] MIN Duty = 4844%(X100), DQS PI = 52
2401 01:32:21.773580 [0] AVG Duty = 4984%(X100)
2402 01:32:21.773643
2403 01:32:21.773707 ==DQM 1 ==
2404 01:32:21.773772 Final DQM duty delay cell = 0
2405 01:32:21.774043 [0] MAX Duty = 5000%(X100), DQS PI = 8
2406 01:32:21.774207 [0] MIN Duty = 4875%(X100), DQS PI = 22
2407 01:32:21.774374 [0] AVG Duty = 4937%(X100)
2408 01:32:21.774520
2409 01:32:21.774662 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2410 01:32:21.774736
2411 01:32:21.774796 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2412 01:32:21.774855 [DutyScan_Calibration_Flow] ====Done====
2413 01:32:21.774913
2414 01:32:21.774970 [DutyScan_Calibration_Flow] k_type=2
2415 01:32:21.775028
2416 01:32:21.775085 ==DQ 0 ==
2417 01:32:21.775143 Final DQ duty delay cell = 0
2418 01:32:21.775201 [0] MAX Duty = 5156%(X100), DQS PI = 20
2419 01:32:21.775259 [0] MIN Duty = 4938%(X100), DQS PI = 58
2420 01:32:21.775317 [0] AVG Duty = 5047%(X100)
2421 01:32:21.775374
2422 01:32:21.775430 ==DQ 1 ==
2423 01:32:21.775488 Final DQ duty delay cell = 0
2424 01:32:21.775546 [0] MAX Duty = 5125%(X100), DQS PI = 6
2425 01:32:21.775603 [0] MIN Duty = 4938%(X100), DQS PI = 16
2426 01:32:21.775660 [0] AVG Duty = 5031%(X100)
2427 01:32:21.775717
2428 01:32:21.775774 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2429 01:32:21.775832
2430 01:32:21.775888 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2431 01:32:21.775946 [DutyScan_Calibration_Flow] ====Done====
2432 01:32:21.776004 ==
2433 01:32:21.776061 Dram Type= 6, Freq= 0, CH_1, rank 0
2434 01:32:21.776118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2435 01:32:21.776176 ==
2436 01:32:21.776234 [Duty_Offset_Calibration]
2437 01:32:21.776291 B0:0 B1:-1 CA:3
2438 01:32:21.776348
2439 01:32:21.776405 [DutyScan_Calibration_Flow] k_type=0
2440 01:32:21.776462
2441 01:32:21.776519 ==CLK 0==
2442 01:32:21.776576 Final CLK duty delay cell = -4
2443 01:32:21.776634 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2444 01:32:21.776691 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2445 01:32:21.776748 [-4] AVG Duty = 4938%(X100)
2446 01:32:21.776805
2447 01:32:21.776864 CH1 CLK Duty spec in!! Max-Min= 124%
2448 01:32:21.776921 [DutyScan_Calibration_Flow] ====Done====
2449 01:32:21.776978
2450 01:32:21.777035 [DutyScan_Calibration_Flow] k_type=1
2451 01:32:21.777092
2452 01:32:21.777148 ==DQS 0 ==
2453 01:32:21.777205 Final DQS duty delay cell = 0
2454 01:32:21.777270 [0] MAX Duty = 5156%(X100), DQS PI = 18
2455 01:32:21.777328 [0] MIN Duty = 4907%(X100), DQS PI = 38
2456 01:32:21.777386 [0] AVG Duty = 5031%(X100)
2457 01:32:21.777442
2458 01:32:21.777499 ==DQS 1 ==
2459 01:32:21.777556 Final DQS duty delay cell = -4
2460 01:32:21.777613 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2461 01:32:21.777669 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2462 01:32:21.777726 [-4] AVG Duty = 4937%(X100)
2463 01:32:21.777784
2464 01:32:21.777841 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2465 01:32:21.777898
2466 01:32:21.777954 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2467 01:32:21.778011 [DutyScan_Calibration_Flow] ====Done====
2468 01:32:21.778068
2469 01:32:21.778125 [DutyScan_Calibration_Flow] k_type=3
2470 01:32:21.778181
2471 01:32:21.778237 ==DQM 0 ==
2472 01:32:21.778294 Final DQM duty delay cell = 0
2473 01:32:21.778351 [0] MAX Duty = 5031%(X100), DQS PI = 28
2474 01:32:21.778408 [0] MIN Duty = 4782%(X100), DQS PI = 38
2475 01:32:21.778465 [0] AVG Duty = 4906%(X100)
2476 01:32:21.778523
2477 01:32:21.778579 ==DQM 1 ==
2478 01:32:21.778636 Final DQM duty delay cell = 0
2479 01:32:21.778694 [0] MAX Duty = 5000%(X100), DQS PI = 34
2480 01:32:21.778751 [0] MIN Duty = 4813%(X100), DQS PI = 0
2481 01:32:21.778807 [0] AVG Duty = 4906%(X100)
2482 01:32:21.778864
2483 01:32:21.778920 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2484 01:32:21.778977
2485 01:32:21.779034 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2486 01:32:21.779090 [DutyScan_Calibration_Flow] ====Done====
2487 01:32:21.779147
2488 01:32:21.779203 [DutyScan_Calibration_Flow] k_type=2
2489 01:32:21.779260
2490 01:32:21.779330 ==DQ 0 ==
2491 01:32:21.779383 Final DQ duty delay cell = -4
2492 01:32:21.779435 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2493 01:32:21.779487 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2494 01:32:21.779539 [-4] AVG Duty = 4937%(X100)
2495 01:32:21.779591
2496 01:32:21.779643 ==DQ 1 ==
2497 01:32:21.779695 Final DQ duty delay cell = 0
2498 01:32:21.779747 [0] MAX Duty = 5031%(X100), DQS PI = 32
2499 01:32:21.779799 [0] MIN Duty = 4876%(X100), DQS PI = 0
2500 01:32:21.779851 [0] AVG Duty = 4953%(X100)
2501 01:32:21.779902
2502 01:32:21.779954 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2503 01:32:21.780006
2504 01:32:21.780058 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2505 01:32:21.780110 [DutyScan_Calibration_Flow] ====Done====
2506 01:32:21.780161 nWR fixed to 30
2507 01:32:21.780214 [ModeRegInit_LP4] CH0 RK0
2508 01:32:21.780266 [ModeRegInit_LP4] CH0 RK1
2509 01:32:21.780318 [ModeRegInit_LP4] CH1 RK0
2510 01:32:21.780370 [ModeRegInit_LP4] CH1 RK1
2511 01:32:21.780422 match AC timing 7
2512 01:32:21.780474 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2513 01:32:21.780526 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2514 01:32:21.780578 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2515 01:32:21.780631 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2516 01:32:21.780683 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2517 01:32:21.780734 ==
2518 01:32:21.780786 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 01:32:21.780838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 01:32:21.780891 ==
2521 01:32:21.780943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 01:32:21.780995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 01:32:21.781048 [CA 0] Center 39 (9~70) winsize 62
2524 01:32:21.781100 [CA 1] Center 39 (9~70) winsize 62
2525 01:32:21.781152 [CA 2] Center 35 (5~66) winsize 62
2526 01:32:21.781204 [CA 3] Center 35 (5~66) winsize 62
2527 01:32:21.781259 [CA 4] Center 33 (3~64) winsize 62
2528 01:32:21.781312 [CA 5] Center 33 (3~64) winsize 62
2529 01:32:21.781364
2530 01:32:21.781417 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2531 01:32:21.781469
2532 01:32:21.781520 [CATrainingPosCal] consider 1 rank data
2533 01:32:21.781572 u2DelayCellTimex100 = 270/100 ps
2534 01:32:21.781624 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2535 01:32:21.781677 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2536 01:32:21.781729 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2537 01:32:21.781781 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 01:32:21.781833 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2539 01:32:21.781885 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2540 01:32:21.781937
2541 01:32:21.781988 CA PerBit enable=1, Macro0, CA PI delay=33
2542 01:32:21.782040
2543 01:32:21.782091 [CBTSetCACLKResult] CA Dly = 33
2544 01:32:21.782143 CS Dly: 7 (0~38)
2545 01:32:21.782195 ==
2546 01:32:21.782247 Dram Type= 6, Freq= 0, CH_0, rank 1
2547 01:32:21.782299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 01:32:21.782351 ==
2549 01:32:21.782403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2550 01:32:21.782456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2551 01:32:21.782705 [CA 0] Center 39 (9~70) winsize 62
2552 01:32:21.782835 [CA 1] Center 39 (9~70) winsize 62
2553 01:32:21.782962 [CA 2] Center 35 (5~66) winsize 62
2554 01:32:21.783090 [CA 3] Center 35 (5~66) winsize 62
2555 01:32:21.783216 [CA 4] Center 34 (4~65) winsize 62
2556 01:32:21.783291 [CA 5] Center 33 (3~64) winsize 62
2557 01:32:21.783346
2558 01:32:21.783398 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2559 01:32:21.783451
2560 01:32:21.783503 [CATrainingPosCal] consider 2 rank data
2561 01:32:21.783556 u2DelayCellTimex100 = 270/100 ps
2562 01:32:21.783608 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2563 01:32:21.783660 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2564 01:32:21.783713 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2565 01:32:21.783765 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 01:32:21.783817 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2567 01:32:21.783869 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2568 01:32:21.783922
2569 01:32:21.783973 CA PerBit enable=1, Macro0, CA PI delay=33
2570 01:32:21.784026
2571 01:32:21.784078 [CBTSetCACLKResult] CA Dly = 33
2572 01:32:21.784130 CS Dly: 8 (0~41)
2573 01:32:21.784182
2574 01:32:21.784233 ----->DramcWriteLeveling(PI) begin...
2575 01:32:21.784300 ==
2576 01:32:21.784351 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 01:32:21.784402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 01:32:21.784453 ==
2579 01:32:21.784504 Write leveling (Byte 0): 31 => 31
2580 01:32:21.784555 Write leveling (Byte 1): 29 => 29
2581 01:32:21.784606 DramcWriteLeveling(PI) end<-----
2582 01:32:21.784657
2583 01:32:21.784707 ==
2584 01:32:21.784757 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 01:32:21.784808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 01:32:21.784860 ==
2587 01:32:21.784911 [Gating] SW mode calibration
2588 01:32:21.784962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2589 01:32:21.785014 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2590 01:32:21.785065 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2591 01:32:21.785117 0 15 4 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
2592 01:32:21.785168 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 01:32:21.785219 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 01:32:21.785303 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 01:32:21.785370 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 01:32:21.785421 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 01:32:21.785472 0 15 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
2598 01:32:21.785522 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
2599 01:32:21.785573 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 01:32:21.785625 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 01:32:21.785676 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 01:32:21.785727 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 01:32:21.785778 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 01:32:21.785830 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2605 01:32:21.785881 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2606 01:32:21.785931 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2607 01:32:21.785983 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2608 01:32:21.786034 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 01:32:21.786085 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 01:32:21.786136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 01:32:21.786188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 01:32:21.786239 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2613 01:32:21.786290 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2614 01:32:21.786341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2615 01:32:21.786393 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2616 01:32:21.786444 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 01:32:21.786495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 01:32:21.786546 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 01:32:21.786596 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 01:32:21.786648 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 01:32:21.786699 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 01:32:21.786750 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 01:32:21.786801 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 01:32:21.786851 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 01:32:21.786902 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 01:32:21.786953 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 01:32:21.787003 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 01:32:21.787054 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2629 01:32:21.787105 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2630 01:32:21.787156 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2631 01:32:21.787207 Total UI for P1: 0, mck2ui 16
2632 01:32:21.787259 best dqsien dly found for B0: ( 1, 3, 26)
2633 01:32:21.787310 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2634 01:32:21.787360 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 01:32:21.787411 Total UI for P1: 0, mck2ui 16
2636 01:32:21.787462 best dqsien dly found for B1: ( 1, 4, 2)
2637 01:32:21.787513 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2638 01:32:21.787564 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2639 01:32:21.787615
2640 01:32:21.787665 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2641 01:32:21.787717 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2642 01:32:21.787768 [Gating] SW calibration Done
2643 01:32:21.787818 ==
2644 01:32:21.787869 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 01:32:21.787919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 01:32:21.787971 ==
2647 01:32:21.788021 RX Vref Scan: 0
2648 01:32:21.788072
2649 01:32:21.788122 RX Vref 0 -> 0, step: 1
2650 01:32:21.788173
2651 01:32:21.788223 RX Delay -40 -> 252, step: 8
2652 01:32:21.788274 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2653 01:32:21.788325 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2654 01:32:21.788375 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2655 01:32:21.788426 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2656 01:32:21.788675 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2657 01:32:21.788733 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2658 01:32:21.788786 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2659 01:32:21.788837 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2660 01:32:21.788889 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2661 01:32:21.788940 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2662 01:32:21.788992 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2663 01:32:21.789042 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2664 01:32:21.789094 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2665 01:32:21.789145 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2666 01:32:21.789195 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2667 01:32:21.789247 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2668 01:32:21.789364 ==
2669 01:32:21.789451 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 01:32:21.789508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 01:32:21.789561 ==
2672 01:32:21.789613 DQS Delay:
2673 01:32:21.789664 DQS0 = 0, DQS1 = 0
2674 01:32:21.789715 DQM Delay:
2675 01:32:21.789766 DQM0 = 118, DQM1 = 107
2676 01:32:21.789817 DQ Delay:
2677 01:32:21.789868 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2678 01:32:21.789919 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2679 01:32:21.789970 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2680 01:32:21.790022 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2681 01:32:21.790073
2682 01:32:21.790123
2683 01:32:21.790174 ==
2684 01:32:21.790224 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 01:32:21.790275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 01:32:21.790327 ==
2687 01:32:21.790378
2688 01:32:21.790428
2689 01:32:21.790479 TX Vref Scan disable
2690 01:32:21.790530 == TX Byte 0 ==
2691 01:32:21.790580 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2692 01:32:21.790632 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2693 01:32:21.790683 == TX Byte 1 ==
2694 01:32:21.790734 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2695 01:32:21.790785 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2696 01:32:21.790835 ==
2697 01:32:21.790886 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 01:32:21.790937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 01:32:21.790988 ==
2700 01:32:21.791038 TX Vref=22, minBit 1, minWin=25, winSum=413
2701 01:32:21.791089 TX Vref=24, minBit 1, minWin=25, winSum=421
2702 01:32:21.791141 TX Vref=26, minBit 4, minWin=25, winSum=423
2703 01:32:21.791192 TX Vref=28, minBit 0, minWin=26, winSum=425
2704 01:32:21.791243 TX Vref=30, minBit 4, minWin=26, winSum=426
2705 01:32:21.791294 TX Vref=32, minBit 3, minWin=26, winSum=426
2706 01:32:21.791345 [TxChooseVref] Worse bit 4, Min win 26, Win sum 426, Final Vref 30
2707 01:32:21.791397
2708 01:32:21.791447 Final TX Range 1 Vref 30
2709 01:32:21.791498
2710 01:32:21.791552 ==
2711 01:32:21.791604 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 01:32:21.791655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 01:32:21.791706 ==
2714 01:32:21.791757
2715 01:32:21.791807
2716 01:32:21.791857 TX Vref Scan disable
2717 01:32:21.791908 == TX Byte 0 ==
2718 01:32:21.791959 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2719 01:32:21.792010 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2720 01:32:21.792061 == TX Byte 1 ==
2721 01:32:21.792113 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2722 01:32:21.792164 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2723 01:32:21.792215
2724 01:32:21.792266 [DATLAT]
2725 01:32:21.792316 Freq=1200, CH0 RK0
2726 01:32:21.792367
2727 01:32:21.792417 DATLAT Default: 0xd
2728 01:32:21.792468 0, 0xFFFF, sum = 0
2729 01:32:21.792520 1, 0xFFFF, sum = 0
2730 01:32:21.792572 2, 0xFFFF, sum = 0
2731 01:32:21.792624 3, 0xFFFF, sum = 0
2732 01:32:21.792675 4, 0xFFFF, sum = 0
2733 01:32:21.792726 5, 0xFFFF, sum = 0
2734 01:32:21.792778 6, 0xFFFF, sum = 0
2735 01:32:21.792829 7, 0xFFFF, sum = 0
2736 01:32:21.792881 8, 0xFFFF, sum = 0
2737 01:32:21.792932 9, 0xFFFF, sum = 0
2738 01:32:21.792984 10, 0xFFFF, sum = 0
2739 01:32:21.793035 11, 0xFFFF, sum = 0
2740 01:32:21.793087 12, 0x0, sum = 1
2741 01:32:21.793138 13, 0x0, sum = 2
2742 01:32:21.793190 14, 0x0, sum = 3
2743 01:32:21.793241 15, 0x0, sum = 4
2744 01:32:21.793336 best_step = 13
2745 01:32:21.793387
2746 01:32:21.793437 ==
2747 01:32:21.793488 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 01:32:21.793539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 01:32:21.793601 ==
2750 01:32:21.793653 RX Vref Scan: 1
2751 01:32:21.793703
2752 01:32:21.793754 Set Vref Range= 32 -> 127
2753 01:32:21.793805
2754 01:32:21.793855 RX Vref 32 -> 127, step: 1
2755 01:32:21.793906
2756 01:32:21.793957 RX Delay -21 -> 252, step: 4
2757 01:32:21.794008
2758 01:32:21.794058 Set Vref, RX VrefLevel [Byte0]: 32
2759 01:32:21.794132 [Byte1]: 32
2760 01:32:21.794231
2761 01:32:21.794297 Set Vref, RX VrefLevel [Byte0]: 33
2762 01:32:21.794351 [Byte1]: 33
2763 01:32:21.794403
2764 01:32:21.794453 Set Vref, RX VrefLevel [Byte0]: 34
2765 01:32:21.794505 [Byte1]: 34
2766 01:32:21.794556
2767 01:32:21.794607 Set Vref, RX VrefLevel [Byte0]: 35
2768 01:32:21.794659 [Byte1]: 35
2769 01:32:21.794709
2770 01:32:21.794760 Set Vref, RX VrefLevel [Byte0]: 36
2771 01:32:21.794810 [Byte1]: 36
2772 01:32:21.794861
2773 01:32:21.794911 Set Vref, RX VrefLevel [Byte0]: 37
2774 01:32:21.794962 [Byte1]: 37
2775 01:32:21.795013
2776 01:32:21.795063 Set Vref, RX VrefLevel [Byte0]: 38
2777 01:32:21.795113 [Byte1]: 38
2778 01:32:21.795164
2779 01:32:21.795214 Set Vref, RX VrefLevel [Byte0]: 39
2780 01:32:21.795265 [Byte1]: 39
2781 01:32:21.795315
2782 01:32:21.795366 Set Vref, RX VrefLevel [Byte0]: 40
2783 01:32:21.795417 [Byte1]: 40
2784 01:32:21.795467
2785 01:32:21.795517 Set Vref, RX VrefLevel [Byte0]: 41
2786 01:32:21.795568 [Byte1]: 41
2787 01:32:21.795619
2788 01:32:21.795669 Set Vref, RX VrefLevel [Byte0]: 42
2789 01:32:21.795720 [Byte1]: 42
2790 01:32:21.795770
2791 01:32:21.795821 Set Vref, RX VrefLevel [Byte0]: 43
2792 01:32:21.795872 [Byte1]: 43
2793 01:32:21.795923
2794 01:32:21.795972 Set Vref, RX VrefLevel [Byte0]: 44
2795 01:32:21.796023 [Byte1]: 44
2796 01:32:21.796074
2797 01:32:21.796124 Set Vref, RX VrefLevel [Byte0]: 45
2798 01:32:21.796174 [Byte1]: 45
2799 01:32:21.796225
2800 01:32:21.796275 Set Vref, RX VrefLevel [Byte0]: 46
2801 01:32:21.796325 [Byte1]: 46
2802 01:32:21.796376
2803 01:32:21.796426 Set Vref, RX VrefLevel [Byte0]: 47
2804 01:32:21.796476 [Byte1]: 47
2805 01:32:21.796527
2806 01:32:21.796577 Set Vref, RX VrefLevel [Byte0]: 48
2807 01:32:21.796628 [Byte1]: 48
2808 01:32:21.796679
2809 01:32:21.796730 Set Vref, RX VrefLevel [Byte0]: 49
2810 01:32:21.796781 [Byte1]: 49
2811 01:32:21.796831
2812 01:32:21.796881 Set Vref, RX VrefLevel [Byte0]: 50
2813 01:32:21.796932 [Byte1]: 50
2814 01:32:21.796983
2815 01:32:21.797243 Set Vref, RX VrefLevel [Byte0]: 51
2816 01:32:21.797391 [Byte1]: 51
2817 01:32:21.797517
2818 01:32:21.797641 Set Vref, RX VrefLevel [Byte0]: 52
2819 01:32:21.797766 [Byte1]: 52
2820 01:32:21.797890
2821 01:32:21.798014 Set Vref, RX VrefLevel [Byte0]: 53
2822 01:32:21.798138 [Byte1]: 53
2823 01:32:21.798261
2824 01:32:21.798354 Set Vref, RX VrefLevel [Byte0]: 54
2825 01:32:21.798409 [Byte1]: 54
2826 01:32:21.798461
2827 01:32:21.798513 Set Vref, RX VrefLevel [Byte0]: 55
2828 01:32:21.798564 [Byte1]: 55
2829 01:32:21.798616
2830 01:32:21.798667 Set Vref, RX VrefLevel [Byte0]: 56
2831 01:32:21.798718 [Byte1]: 56
2832 01:32:21.798769
2833 01:32:21.798819 Set Vref, RX VrefLevel [Byte0]: 57
2834 01:32:21.798870 [Byte1]: 57
2835 01:32:21.798922
2836 01:32:21.798972 Set Vref, RX VrefLevel [Byte0]: 58
2837 01:32:21.799023 [Byte1]: 58
2838 01:32:21.799074
2839 01:32:21.799125 Set Vref, RX VrefLevel [Byte0]: 59
2840 01:32:21.799175 [Byte1]: 59
2841 01:32:21.799226
2842 01:32:21.799277 Set Vref, RX VrefLevel [Byte0]: 60
2843 01:32:21.799327 [Byte1]: 60
2844 01:32:21.799378
2845 01:32:21.799428 Set Vref, RX VrefLevel [Byte0]: 61
2846 01:32:21.799479 [Byte1]: 61
2847 01:32:21.799529
2848 01:32:21.799580 Set Vref, RX VrefLevel [Byte0]: 62
2849 01:32:21.799630 [Byte1]: 62
2850 01:32:21.799682
2851 01:32:21.799733 Set Vref, RX VrefLevel [Byte0]: 63
2852 01:32:21.799783 [Byte1]: 63
2853 01:32:21.799834
2854 01:32:21.799885 Set Vref, RX VrefLevel [Byte0]: 64
2855 01:32:21.799935 [Byte1]: 64
2856 01:32:21.799986
2857 01:32:21.800036 Set Vref, RX VrefLevel [Byte0]: 65
2858 01:32:21.800086 [Byte1]: 65
2859 01:32:21.800137
2860 01:32:21.800187 Set Vref, RX VrefLevel [Byte0]: 66
2861 01:32:21.800238 [Byte1]: 66
2862 01:32:21.800289
2863 01:32:21.800339 Final RX Vref Byte 0 = 56 to rank0
2864 01:32:21.800391 Final RX Vref Byte 1 = 50 to rank0
2865 01:32:21.800442 Final RX Vref Byte 0 = 56 to rank1
2866 01:32:21.800493 Final RX Vref Byte 1 = 50 to rank1==
2867 01:32:21.800543 Dram Type= 6, Freq= 0, CH_0, rank 0
2868 01:32:21.800595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 01:32:21.800645 ==
2870 01:32:21.800696 DQS Delay:
2871 01:32:21.800747 DQS0 = 0, DQS1 = 0
2872 01:32:21.800798 DQM Delay:
2873 01:32:21.800848 DQM0 = 117, DQM1 = 104
2874 01:32:21.800898 DQ Delay:
2875 01:32:21.800949 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2876 01:32:21.801000 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =120
2877 01:32:21.801051 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2878 01:32:21.801102 DQ12 =112, DQ13 =108, DQ14 =116, DQ15 =112
2879 01:32:21.801153
2880 01:32:21.801203
2881 01:32:21.801254 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2882 01:32:21.801352 CH0 RK0: MR19=403, MR18=1FC
2883 01:32:21.801403 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2884 01:32:21.801455
2885 01:32:21.801506 ----->DramcWriteLeveling(PI) begin...
2886 01:32:21.801557 ==
2887 01:32:21.801608 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 01:32:21.801659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 01:32:21.801725 ==
2890 01:32:21.801777 Write leveling (Byte 0): 32 => 32
2891 01:32:21.801829 Write leveling (Byte 1): 27 => 27
2892 01:32:21.801881 DramcWriteLeveling(PI) end<-----
2893 01:32:21.801932
2894 01:32:21.801982 ==
2895 01:32:21.802032 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 01:32:21.802083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 01:32:21.802134 ==
2898 01:32:21.802185 [Gating] SW mode calibration
2899 01:32:21.802236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2900 01:32:21.802288 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2901 01:32:21.802339 0 15 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2902 01:32:21.802391 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2903 01:32:21.802442 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 01:32:21.802492 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 01:32:21.802544 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 01:32:21.802595 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 01:32:21.802646 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2908 01:32:21.802696 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2909 01:32:21.802747 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2910 01:32:21.802799 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2911 01:32:21.802895 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 01:32:21.802946 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 01:32:21.802997 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 01:32:21.803047 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 01:32:21.803098 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2916 01:32:21.803150 1 0 28 | B1->B0 | 2828 4242 | 0 0 | (0 0) (0 0)
2917 01:32:21.803200 1 1 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2918 01:32:21.803251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 01:32:21.803302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 01:32:21.803353 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 01:32:21.803404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 01:32:21.803455 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 01:32:21.803506 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2924 01:32:21.803556 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2925 01:32:21.803607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2926 01:32:21.803665 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2927 01:32:21.803718 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 01:32:21.803769 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 01:32:21.803819 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 01:32:21.803870 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 01:32:21.803921 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 01:32:21.803972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 01:32:21.804024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 01:32:21.804268 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 01:32:21.804329 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 01:32:21.804382 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 01:32:21.804434 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 01:32:21.804485 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 01:32:21.804536 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 01:32:21.804587 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2941 01:32:21.804638 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2942 01:32:21.804689 Total UI for P1: 0, mck2ui 16
2943 01:32:21.804741 best dqsien dly found for B0: ( 1, 3, 28)
2944 01:32:21.804793 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 01:32:21.804844 Total UI for P1: 0, mck2ui 16
2946 01:32:21.804895 best dqsien dly found for B1: ( 1, 4, 0)
2947 01:32:21.804947 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2948 01:32:21.804998 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2949 01:32:21.805049
2950 01:32:21.805100 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2951 01:32:21.805151 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2952 01:32:21.805202 [Gating] SW calibration Done
2953 01:32:21.805253 ==
2954 01:32:21.805349 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 01:32:21.805400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 01:32:21.805452 ==
2957 01:32:21.805503 RX Vref Scan: 0
2958 01:32:21.805553
2959 01:32:21.805603 RX Vref 0 -> 0, step: 1
2960 01:32:21.805654
2961 01:32:21.805704 RX Delay -40 -> 252, step: 8
2962 01:32:21.805755 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2963 01:32:21.805808 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2964 01:32:21.805859 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2965 01:32:21.805910 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2966 01:32:21.805961 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2967 01:32:21.806012 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2968 01:32:21.806062 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2969 01:32:21.806114 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2970 01:32:21.806165 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2971 01:32:21.806216 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2972 01:32:21.806267 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2973 01:32:21.806318 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2974 01:32:21.806368 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2975 01:32:21.806419 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2976 01:32:21.806470 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2977 01:32:21.806521 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2978 01:32:21.806571 ==
2979 01:32:21.806622 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 01:32:21.806673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 01:32:21.806724 ==
2982 01:32:21.806774 DQS Delay:
2983 01:32:21.806825 DQS0 = 0, DQS1 = 0
2984 01:32:21.806876 DQM Delay:
2985 01:32:21.806926 DQM0 = 115, DQM1 = 106
2986 01:32:21.806977 DQ Delay:
2987 01:32:21.807028 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2988 01:32:21.807079 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2989 01:32:21.807130 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2990 01:32:21.807180 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2991 01:32:21.807231
2992 01:32:21.807282
2993 01:32:21.807332 ==
2994 01:32:21.807382 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 01:32:21.807433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 01:32:21.807484 ==
2997 01:32:21.807535
2998 01:32:21.807585
2999 01:32:21.807635 TX Vref Scan disable
3000 01:32:21.807692 == TX Byte 0 ==
3001 01:32:21.807743 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3002 01:32:21.807794 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3003 01:32:21.916952 == TX Byte 1 ==
3004 01:32:21.917511 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3005 01:32:21.917878 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3006 01:32:21.918211 ==
3007 01:32:21.918531 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 01:32:21.918842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 01:32:21.919146 ==
3010 01:32:21.919443 TX Vref=22, minBit 8, minWin=25, winSum=419
3011 01:32:21.919742 TX Vref=24, minBit 13, minWin=25, winSum=423
3012 01:32:21.920043 TX Vref=26, minBit 2, minWin=26, winSum=430
3013 01:32:21.920340 TX Vref=28, minBit 2, minWin=26, winSum=429
3014 01:32:21.920638 TX Vref=30, minBit 10, minWin=26, winSum=430
3015 01:32:21.920928 TX Vref=32, minBit 4, minWin=26, winSum=427
3016 01:32:21.921224 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 26
3017 01:32:21.921565
3018 01:32:21.921859 Final TX Range 1 Vref 26
3019 01:32:21.922151
3020 01:32:21.922442 ==
3021 01:32:21.922734 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 01:32:21.923026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 01:32:21.923321 ==
3024 01:32:21.923610
3025 01:32:21.923898
3026 01:32:21.924182 TX Vref Scan disable
3027 01:32:21.924542 == TX Byte 0 ==
3028 01:32:21.924844 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3029 01:32:21.925139 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3030 01:32:21.925483 == TX Byte 1 ==
3031 01:32:21.925779 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3032 01:32:21.926072 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3033 01:32:21.926362
3034 01:32:21.926650 [DATLAT]
3035 01:32:21.926936 Freq=1200, CH0 RK1
3036 01:32:21.927226
3037 01:32:21.927511 DATLAT Default: 0xd
3038 01:32:21.927795 0, 0xFFFF, sum = 0
3039 01:32:21.928089 1, 0xFFFF, sum = 0
3040 01:32:21.928395 2, 0xFFFF, sum = 0
3041 01:32:21.928661 3, 0xFFFF, sum = 0
3042 01:32:21.928928 4, 0xFFFF, sum = 0
3043 01:32:21.929195 5, 0xFFFF, sum = 0
3044 01:32:21.929506 6, 0xFFFF, sum = 0
3045 01:32:21.929775 7, 0xFFFF, sum = 0
3046 01:32:21.930044 8, 0xFFFF, sum = 0
3047 01:32:21.930315 9, 0xFFFF, sum = 0
3048 01:32:21.930587 10, 0xFFFF, sum = 0
3049 01:32:21.930855 11, 0xFFFF, sum = 0
3050 01:32:21.931124 12, 0x0, sum = 1
3051 01:32:21.931392 13, 0x0, sum = 2
3052 01:32:21.931660 14, 0x0, sum = 3
3053 01:32:21.931925 15, 0x0, sum = 4
3054 01:32:21.932195 best_step = 13
3055 01:32:21.932499
3056 01:32:21.932768 ==
3057 01:32:21.933034 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 01:32:21.933339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 01:32:21.933617 ==
3060 01:32:21.933885 RX Vref Scan: 0
3061 01:32:21.934146
3062 01:32:21.934409 RX Vref 0 -> 0, step: 1
3063 01:32:21.934673
3064 01:32:21.934935 RX Delay -21 -> 252, step: 4
3065 01:32:21.935202 iDelay=191, Bit 0, Center 114 (51 ~ 178) 128
3066 01:32:21.935470 iDelay=191, Bit 1, Center 116 (47 ~ 186) 140
3067 01:32:21.935737 iDelay=191, Bit 2, Center 110 (43 ~ 178) 136
3068 01:32:21.936002 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3069 01:32:21.936266 iDelay=191, Bit 4, Center 118 (51 ~ 186) 136
3070 01:32:21.936527 iDelay=191, Bit 5, Center 108 (43 ~ 174) 132
3071 01:32:21.936790 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3072 01:32:21.937482 iDelay=191, Bit 7, Center 120 (55 ~ 186) 132
3073 01:32:21.938146 iDelay=191, Bit 8, Center 96 (27 ~ 166) 140
3074 01:32:21.938801 iDelay=191, Bit 9, Center 92 (23 ~ 162) 140
3075 01:32:21.939442 iDelay=191, Bit 10, Center 106 (39 ~ 174) 136
3076 01:32:21.940090 iDelay=191, Bit 11, Center 98 (31 ~ 166) 136
3077 01:32:21.940739 iDelay=191, Bit 12, Center 112 (47 ~ 178) 132
3078 01:32:21.941410 iDelay=191, Bit 13, Center 110 (43 ~ 178) 136
3079 01:32:21.942067 iDelay=191, Bit 14, Center 120 (55 ~ 186) 132
3080 01:32:21.942707 iDelay=191, Bit 15, Center 114 (47 ~ 182) 136
3081 01:32:21.943343 ==
3082 01:32:21.943643 Dram Type= 6, Freq= 0, CH_0, rank 1
3083 01:32:21.943916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 01:32:21.944189 ==
3085 01:32:21.944428 DQS Delay:
3086 01:32:21.944615 DQS0 = 0, DQS1 = 0
3087 01:32:21.944804 DQM Delay:
3088 01:32:21.944991 DQM0 = 115, DQM1 = 106
3089 01:32:21.945177 DQ Delay:
3090 01:32:21.945384 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3091 01:32:21.945572 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
3092 01:32:21.945761 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3093 01:32:21.945948 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3094 01:32:21.946135
3095 01:32:21.946321
3096 01:32:21.946509 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3097 01:32:21.946701 CH0 RK1: MR19=303, MR18=FFFC
3098 01:32:21.946890 CH0_RK1: MR19=0x303, MR18=0xFFFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3099 01:32:21.947079 [RxdqsGatingPostProcess] freq 1200
3100 01:32:21.947267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3101 01:32:21.947457 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 01:32:21.947644 best DQS1 dly(2T, 0.5T) = (0, 12)
3103 01:32:21.947831 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 01:32:21.948018 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3105 01:32:21.948205 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 01:32:21.948391 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 01:32:21.948579 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 01:32:21.948766 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 01:32:21.948953 Pre-setting of DQS Precalculation
3110 01:32:21.949138 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3111 01:32:21.949384 ==
3112 01:32:21.949533 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 01:32:21.949677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 01:32:21.949821 ==
3115 01:32:21.949961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 01:32:21.950105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3117 01:32:21.950250 [CA 0] Center 38 (8~68) winsize 61
3118 01:32:21.950394 [CA 1] Center 37 (7~68) winsize 62
3119 01:32:21.950536 [CA 2] Center 35 (6~65) winsize 60
3120 01:32:21.950679 [CA 3] Center 34 (4~64) winsize 61
3121 01:32:21.950821 [CA 4] Center 34 (4~65) winsize 62
3122 01:32:21.950963 [CA 5] Center 33 (3~63) winsize 61
3123 01:32:21.951104
3124 01:32:21.951246 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3125 01:32:21.951388
3126 01:32:21.951529 [CATrainingPosCal] consider 1 rank data
3127 01:32:21.951672 u2DelayCellTimex100 = 270/100 ps
3128 01:32:21.951815 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3129 01:32:21.951959 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 01:32:21.952102 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3131 01:32:21.952245 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 01:32:21.952386 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3133 01:32:21.952528 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3134 01:32:21.952671
3135 01:32:21.952812 CA PerBit enable=1, Macro0, CA PI delay=33
3136 01:32:21.952954
3137 01:32:21.953096 [CBTSetCACLKResult] CA Dly = 33
3138 01:32:21.953239 CS Dly: 4 (0~35)
3139 01:32:21.953395 ==
3140 01:32:21.953539 Dram Type= 6, Freq= 0, CH_1, rank 1
3141 01:32:21.953682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 01:32:21.953828 ==
3143 01:32:21.953971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 01:32:21.954117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3145 01:32:21.954260 [CA 0] Center 37 (7~68) winsize 62
3146 01:32:21.954394 [CA 1] Center 38 (8~68) winsize 61
3147 01:32:21.954509 [CA 2] Center 35 (5~65) winsize 61
3148 01:32:21.954624 [CA 3] Center 33 (3~64) winsize 62
3149 01:32:21.954739 [CA 4] Center 34 (4~64) winsize 61
3150 01:32:21.954853 [CA 5] Center 33 (3~64) winsize 62
3151 01:32:21.954969
3152 01:32:21.955083 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3153 01:32:21.955198
3154 01:32:21.955312 [CATrainingPosCal] consider 2 rank data
3155 01:32:21.955427 u2DelayCellTimex100 = 270/100 ps
3156 01:32:21.955541 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3157 01:32:21.955656 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3158 01:32:21.955770 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3159 01:32:21.955883 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 01:32:21.955998 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 01:32:21.956113 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3162 01:32:21.956226
3163 01:32:21.956339 CA PerBit enable=1, Macro0, CA PI delay=33
3164 01:32:21.956454
3165 01:32:21.956568 [CBTSetCACLKResult] CA Dly = 33
3166 01:32:21.956684 CS Dly: 5 (0~38)
3167 01:32:21.956799
3168 01:32:21.956913 ----->DramcWriteLeveling(PI) begin...
3169 01:32:21.957030 ==
3170 01:32:21.957146 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 01:32:21.957267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 01:32:21.957385 ==
3173 01:32:21.957500 Write leveling (Byte 0): 23 => 23
3174 01:32:21.957614 Write leveling (Byte 1): 27 => 27
3175 01:32:21.957729 DramcWriteLeveling(PI) end<-----
3176 01:32:21.957842
3177 01:32:21.957955 ==
3178 01:32:21.958069 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 01:32:21.958184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 01:32:21.958298 ==
3181 01:32:21.958412 [Gating] SW mode calibration
3182 01:32:21.958527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3183 01:32:21.958644 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3184 01:32:21.958758 0 15 0 | B1->B0 | 2d2d 3232 | 1 0 | (0 0) (0 0)
3185 01:32:21.958873 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 01:32:21.958988 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 01:32:21.959104 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 01:32:21.959219 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 01:32:21.959341 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 01:32:21.959675 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3191 01:32:21.959786 0 15 28 | B1->B0 | 2e2e 2525 | 0 0 | (1 0) (0 0)
3192 01:32:21.959886 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 01:32:21.959983 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 01:32:21.960080 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 01:32:21.960176 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 01:32:21.960273 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 01:32:21.960370 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 01:32:21.960466 1 0 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 1)
3199 01:32:21.960563 1 0 28 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
3200 01:32:21.960659 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 01:32:21.960755 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 01:32:21.960852 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 01:32:21.960948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 01:32:21.961044 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 01:32:21.961140 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 01:32:21.961237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 01:32:21.961347 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3208 01:32:21.961444 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3209 01:32:21.961539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 01:32:21.961635 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 01:32:21.961731 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 01:32:21.961826 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 01:32:21.961922 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 01:32:21.962018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 01:32:21.962115 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 01:32:21.962210 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 01:32:21.962305 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 01:32:21.962401 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 01:32:21.962497 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 01:32:21.962593 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 01:32:21.962688 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 01:32:21.962784 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 01:32:21.962880 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 01:32:21.962975 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 01:32:21.963071 Total UI for P1: 0, mck2ui 16
3226 01:32:21.963169 best dqsien dly found for B0: ( 1, 3, 28)
3227 01:32:21.963267 Total UI for P1: 0, mck2ui 16
3228 01:32:21.963364 best dqsien dly found for B1: ( 1, 3, 28)
3229 01:32:21.963460 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3230 01:32:21.963557 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3231 01:32:21.963653
3232 01:32:21.963748 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3233 01:32:21.963844 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3234 01:32:21.963940 [Gating] SW calibration Done
3235 01:32:21.964035 ==
3236 01:32:21.964131 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 01:32:21.964227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 01:32:21.964329 ==
3239 01:32:21.964411 RX Vref Scan: 0
3240 01:32:21.964493
3241 01:32:21.964576 RX Vref 0 -> 0, step: 1
3242 01:32:21.964658
3243 01:32:21.964740 RX Delay -40 -> 252, step: 8
3244 01:32:21.964823 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3245 01:32:21.964905 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3246 01:32:21.964988 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3247 01:32:21.965070 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3248 01:32:21.965153 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3249 01:32:21.965236 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3250 01:32:21.965326 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3251 01:32:21.965409 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3252 01:32:21.965492 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3253 01:32:21.965575 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3254 01:32:21.965657 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3255 01:32:21.965740 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3256 01:32:21.965823 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3257 01:32:21.965906 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3258 01:32:21.965988 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3259 01:32:21.966070 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3260 01:32:21.966153 ==
3261 01:32:21.966236 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 01:32:21.966319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 01:32:21.966403 ==
3264 01:32:21.966486 DQS Delay:
3265 01:32:21.966569 DQS0 = 0, DQS1 = 0
3266 01:32:21.966651 DQM Delay:
3267 01:32:21.966733 DQM0 = 116, DQM1 = 112
3268 01:32:21.966816 DQ Delay:
3269 01:32:21.966898 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3270 01:32:21.966981 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3271 01:32:21.967063 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3272 01:32:21.967145 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3273 01:32:21.967227
3274 01:32:21.967309
3275 01:32:21.967390 ==
3276 01:32:21.967473 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 01:32:21.967555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 01:32:21.967639 ==
3279 01:32:21.967720
3280 01:32:21.967802
3281 01:32:21.967882 TX Vref Scan disable
3282 01:32:21.967964 == TX Byte 0 ==
3283 01:32:21.968046 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3284 01:32:21.968130 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3285 01:32:21.968212 == TX Byte 1 ==
3286 01:32:21.968294 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3287 01:32:21.968377 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3288 01:32:21.968459 ==
3289 01:32:21.968541 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 01:32:21.968628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 01:32:21.968712 ==
3292 01:32:21.968807 TX Vref=22, minBit 9, minWin=24, winSum=413
3293 01:32:21.968904 TX Vref=24, minBit 9, minWin=24, winSum=412
3294 01:32:21.968988 TX Vref=26, minBit 3, minWin=25, winSum=420
3295 01:32:21.969071 TX Vref=28, minBit 8, minWin=25, winSum=425
3296 01:32:21.969154 TX Vref=30, minBit 8, minWin=25, winSum=428
3297 01:32:21.969237 TX Vref=32, minBit 9, minWin=25, winSum=424
3298 01:32:21.969552 [TxChooseVref] Worse bit 8, Min win 25, Win sum 428, Final Vref 30
3299 01:32:21.969734
3300 01:32:21.969884 Final TX Range 1 Vref 30
3301 01:32:21.969964
3302 01:32:21.970040 ==
3303 01:32:21.970114 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 01:32:21.970186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 01:32:21.970258 ==
3306 01:32:21.970330
3307 01:32:21.970402
3308 01:32:21.970474 TX Vref Scan disable
3309 01:32:21.970546 == TX Byte 0 ==
3310 01:32:21.970618 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3311 01:32:21.970692 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3312 01:32:21.970765 == TX Byte 1 ==
3313 01:32:21.970837 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3314 01:32:21.970909 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3315 01:32:21.971005
3316 01:32:21.971078 [DATLAT]
3317 01:32:21.971151 Freq=1200, CH1 RK0
3318 01:32:21.971223
3319 01:32:21.971295 DATLAT Default: 0xd
3320 01:32:21.971368 0, 0xFFFF, sum = 0
3321 01:32:21.971442 1, 0xFFFF, sum = 0
3322 01:32:21.971516 2, 0xFFFF, sum = 0
3323 01:32:21.971610 3, 0xFFFF, sum = 0
3324 01:32:21.971686 4, 0xFFFF, sum = 0
3325 01:32:21.971759 5, 0xFFFF, sum = 0
3326 01:32:21.971833 6, 0xFFFF, sum = 0
3327 01:32:21.971906 7, 0xFFFF, sum = 0
3328 01:32:21.971980 8, 0xFFFF, sum = 0
3329 01:32:21.972052 9, 0xFFFF, sum = 0
3330 01:32:21.972125 10, 0xFFFF, sum = 0
3331 01:32:21.972197 11, 0xFFFF, sum = 0
3332 01:32:21.972271 12, 0x0, sum = 1
3333 01:32:21.972343 13, 0x0, sum = 2
3334 01:32:21.972416 14, 0x0, sum = 3
3335 01:32:21.972489 15, 0x0, sum = 4
3336 01:32:21.972561 best_step = 13
3337 01:32:21.972633
3338 01:32:21.972703 ==
3339 01:32:21.972775 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 01:32:21.972848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 01:32:21.972921 ==
3342 01:32:21.972993 RX Vref Scan: 1
3343 01:32:21.973064
3344 01:32:21.973136 Set Vref Range= 32 -> 127
3345 01:32:21.973208
3346 01:32:21.973291 RX Vref 32 -> 127, step: 1
3347 01:32:21.973365
3348 01:32:21.973436 RX Delay -13 -> 252, step: 4
3349 01:32:21.973508
3350 01:32:21.973580 Set Vref, RX VrefLevel [Byte0]: 32
3351 01:32:21.973653 [Byte1]: 32
3352 01:32:21.973725
3353 01:32:21.973797 Set Vref, RX VrefLevel [Byte0]: 33
3354 01:32:21.973868 [Byte1]: 33
3355 01:32:21.973940
3356 01:32:21.974011 Set Vref, RX VrefLevel [Byte0]: 34
3357 01:32:21.974083 [Byte1]: 34
3358 01:32:21.974155
3359 01:32:21.974238 Set Vref, RX VrefLevel [Byte0]: 35
3360 01:32:21.974334 [Byte1]: 35
3361 01:32:21.974398
3362 01:32:21.974461 Set Vref, RX VrefLevel [Byte0]: 36
3363 01:32:21.974525 [Byte1]: 36
3364 01:32:21.974588
3365 01:32:21.974651 Set Vref, RX VrefLevel [Byte0]: 37
3366 01:32:21.974715 [Byte1]: 37
3367 01:32:21.974778
3368 01:32:21.974841 Set Vref, RX VrefLevel [Byte0]: 38
3369 01:32:21.974904 [Byte1]: 38
3370 01:32:21.974967
3371 01:32:21.975029 Set Vref, RX VrefLevel [Byte0]: 39
3372 01:32:21.975093 [Byte1]: 39
3373 01:32:21.975157
3374 01:32:21.975219 Set Vref, RX VrefLevel [Byte0]: 40
3375 01:32:21.975283 [Byte1]: 40
3376 01:32:21.975346
3377 01:32:21.975409 Set Vref, RX VrefLevel [Byte0]: 41
3378 01:32:21.975472 [Byte1]: 41
3379 01:32:21.975536
3380 01:32:21.975599 Set Vref, RX VrefLevel [Byte0]: 42
3381 01:32:21.975662 [Byte1]: 42
3382 01:32:21.975725
3383 01:32:21.975788 Set Vref, RX VrefLevel [Byte0]: 43
3384 01:32:21.975851 [Byte1]: 43
3385 01:32:21.975913
3386 01:32:21.975976 Set Vref, RX VrefLevel [Byte0]: 44
3387 01:32:21.976039 [Byte1]: 44
3388 01:32:21.976102
3389 01:32:21.976165 Set Vref, RX VrefLevel [Byte0]: 45
3390 01:32:21.976228 [Byte1]: 45
3391 01:32:21.976291
3392 01:32:21.976354 Set Vref, RX VrefLevel [Byte0]: 46
3393 01:32:21.976417 [Byte1]: 46
3394 01:32:21.976480
3395 01:32:21.976543 Set Vref, RX VrefLevel [Byte0]: 47
3396 01:32:21.976606 [Byte1]: 47
3397 01:32:21.976669
3398 01:32:21.976731 Set Vref, RX VrefLevel [Byte0]: 48
3399 01:32:21.976794 [Byte1]: 48
3400 01:32:21.976857
3401 01:32:21.976919 Set Vref, RX VrefLevel [Byte0]: 49
3402 01:32:21.976981 [Byte1]: 49
3403 01:32:21.977046
3404 01:32:21.977108 Set Vref, RX VrefLevel [Byte0]: 50
3405 01:32:21.977171 [Byte1]: 50
3406 01:32:21.977234
3407 01:32:21.977303 Set Vref, RX VrefLevel [Byte0]: 51
3408 01:32:21.977367 [Byte1]: 51
3409 01:32:21.977430
3410 01:32:21.977493 Set Vref, RX VrefLevel [Byte0]: 52
3411 01:32:21.977556 [Byte1]: 52
3412 01:32:21.977619
3413 01:32:21.977682 Set Vref, RX VrefLevel [Byte0]: 53
3414 01:32:21.977745 [Byte1]: 53
3415 01:32:21.977808
3416 01:32:21.977893 Set Vref, RX VrefLevel [Byte0]: 54
3417 01:32:21.977961 [Byte1]: 54
3418 01:32:21.978025
3419 01:32:21.978088 Set Vref, RX VrefLevel [Byte0]: 55
3420 01:32:21.978151 [Byte1]: 55
3421 01:32:21.978215
3422 01:32:21.978277 Set Vref, RX VrefLevel [Byte0]: 56
3423 01:32:21.978339 [Byte1]: 56
3424 01:32:21.978403
3425 01:32:21.978465 Set Vref, RX VrefLevel [Byte0]: 57
3426 01:32:21.978527 [Byte1]: 57
3427 01:32:21.978589
3428 01:32:21.978652 Set Vref, RX VrefLevel [Byte0]: 58
3429 01:32:21.978715 [Byte1]: 58
3430 01:32:21.978777
3431 01:32:21.978839 Set Vref, RX VrefLevel [Byte0]: 59
3432 01:32:21.978902 [Byte1]: 59
3433 01:32:21.978966
3434 01:32:21.979028 Set Vref, RX VrefLevel [Byte0]: 60
3435 01:32:21.979092 [Byte1]: 60
3436 01:32:21.979154
3437 01:32:21.979217 Set Vref, RX VrefLevel [Byte0]: 61
3438 01:32:21.979281 [Byte1]: 61
3439 01:32:21.979354
3440 01:32:21.979411 Set Vref, RX VrefLevel [Byte0]: 62
3441 01:32:21.979467 [Byte1]: 62
3442 01:32:21.979524
3443 01:32:21.979581 Set Vref, RX VrefLevel [Byte0]: 63
3444 01:32:21.979638 [Byte1]: 63
3445 01:32:21.979696
3446 01:32:21.979752 Set Vref, RX VrefLevel [Byte0]: 64
3447 01:32:21.979809 [Byte1]: 64
3448 01:32:21.979867
3449 01:32:21.979923 Set Vref, RX VrefLevel [Byte0]: 65
3450 01:32:21.979979 [Byte1]: 65
3451 01:32:21.980036
3452 01:32:21.980093 Final RX Vref Byte 0 = 52 to rank0
3453 01:32:21.980151 Final RX Vref Byte 1 = 47 to rank0
3454 01:32:21.980208 Final RX Vref Byte 0 = 52 to rank1
3455 01:32:21.980266 Final RX Vref Byte 1 = 47 to rank1==
3456 01:32:21.980322 Dram Type= 6, Freq= 0, CH_1, rank 0
3457 01:32:21.980380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 01:32:21.980437 ==
3459 01:32:21.980494 DQS Delay:
3460 01:32:21.980551 DQS0 = 0, DQS1 = 0
3461 01:32:21.980608 DQM Delay:
3462 01:32:21.980664 DQM0 = 114, DQM1 = 111
3463 01:32:21.980721 DQ Delay:
3464 01:32:21.980778 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3465 01:32:21.980836 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3466 01:32:21.980893 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =106
3467 01:32:21.980971 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =118
3468 01:32:21.981030
3469 01:32:21.981087
3470 01:32:21.981309 [DQSOSCAuto] RK0, (LSB)MR18= 0xf401, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
3471 01:32:21.981375 CH1 RK0: MR19=304, MR18=F401
3472 01:32:21.981434 CH1_RK0: MR19=0x304, MR18=0xF401, DQSOSC=409, MR23=63, INC=39, DEC=26
3473 01:32:21.981493
3474 01:32:21.981550 ----->DramcWriteLeveling(PI) begin...
3475 01:32:21.981608 ==
3476 01:32:21.981665 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 01:32:21.981723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 01:32:21.981781 ==
3479 01:32:21.981837 Write leveling (Byte 0): 24 => 24
3480 01:32:21.981895 Write leveling (Byte 1): 29 => 29
3481 01:32:21.981951 DramcWriteLeveling(PI) end<-----
3482 01:32:21.982008
3483 01:32:21.982064 ==
3484 01:32:21.982121 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 01:32:21.982179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 01:32:21.982237 ==
3487 01:32:21.982295 [Gating] SW mode calibration
3488 01:32:21.982352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3489 01:32:21.982424 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3490 01:32:21.982486 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 01:32:21.982544 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 01:32:21.982601 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 01:32:21.982658 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 01:32:21.982715 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 01:32:21.982772 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 01:32:21.982829 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
3497 01:32:21.982885 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3498 01:32:21.982942 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 01:32:21.982999 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 01:32:21.983056 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 01:32:21.983114 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 01:32:21.983171 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 01:32:21.983228 1 0 20 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3504 01:32:21.983285 1 0 24 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
3505 01:32:21.983342 1 0 28 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3506 01:32:21.983399 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 01:32:21.983456 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 01:32:21.983513 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 01:32:21.983571 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 01:32:21.983628 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 01:32:21.983685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 01:32:21.983742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3513 01:32:21.983799 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3514 01:32:21.983856 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 01:32:21.983935 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 01:32:21.983995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 01:32:21.984052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 01:32:21.984110 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 01:32:21.984168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 01:32:21.984226 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 01:32:21.984295 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 01:32:21.984347 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 01:32:21.984399 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 01:32:21.984452 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 01:32:21.984504 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 01:32:21.984556 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 01:32:21.984608 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3528 01:32:21.984660 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3529 01:32:21.984712 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3530 01:32:21.984764 Total UI for P1: 0, mck2ui 16
3531 01:32:21.984816 best dqsien dly found for B0: ( 1, 3, 22)
3532 01:32:21.984869 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 01:32:21.984921 Total UI for P1: 0, mck2ui 16
3534 01:32:21.984974 best dqsien dly found for B1: ( 1, 3, 26)
3535 01:32:21.985026 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3536 01:32:21.985078 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3537 01:32:21.985130
3538 01:32:21.985181 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3539 01:32:21.985233 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3540 01:32:21.985295 [Gating] SW calibration Done
3541 01:32:21.985348 ==
3542 01:32:21.985400 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 01:32:21.985451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 01:32:21.985503 ==
3545 01:32:21.985555 RX Vref Scan: 0
3546 01:32:21.985607
3547 01:32:21.985658 RX Vref 0 -> 0, step: 1
3548 01:32:21.985710
3549 01:32:21.985761 RX Delay -40 -> 252, step: 8
3550 01:32:21.985813 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3551 01:32:21.985865 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3552 01:32:21.985917 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3553 01:32:21.985968 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3554 01:32:21.986020 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3555 01:32:21.986072 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3556 01:32:21.986124 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3557 01:32:21.986176 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3558 01:32:21.986229 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3559 01:32:21.986281 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3560 01:32:21.986333 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3561 01:32:21.986385 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3562 01:32:21.986459 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3563 01:32:21.986512 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3564 01:32:21.986565 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3565 01:32:21.986616 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3566 01:32:21.986668 ==
3567 01:32:21.986913 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 01:32:21.986975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 01:32:21.987029 ==
3570 01:32:21.987082 DQS Delay:
3571 01:32:21.987134 DQS0 = 0, DQS1 = 0
3572 01:32:21.987206 DQM Delay:
3573 01:32:21.987261 DQM0 = 115, DQM1 = 111
3574 01:32:21.987313 DQ Delay:
3575 01:32:21.987365 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3576 01:32:21.987418 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3577 01:32:21.987470 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3578 01:32:21.987523 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3579 01:32:21.987575
3580 01:32:21.987627
3581 01:32:21.987678 ==
3582 01:32:21.987730 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 01:32:21.987782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 01:32:21.987835 ==
3585 01:32:21.987887
3586 01:32:21.987938
3587 01:32:21.987989 TX Vref Scan disable
3588 01:32:21.988041 == TX Byte 0 ==
3589 01:32:21.988093 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3590 01:32:21.988146 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3591 01:32:21.988198 == TX Byte 1 ==
3592 01:32:21.988249 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3593 01:32:21.988302 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3594 01:32:21.988354 ==
3595 01:32:21.988410 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 01:32:21.988463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 01:32:21.988517 ==
3598 01:32:21.988569 TX Vref=22, minBit 9, minWin=25, winSum=421
3599 01:32:21.988621 TX Vref=24, minBit 9, minWin=25, winSum=421
3600 01:32:21.988674 TX Vref=26, minBit 1, minWin=26, winSum=428
3601 01:32:21.988726 TX Vref=28, minBit 3, minWin=26, winSum=432
3602 01:32:21.988778 TX Vref=30, minBit 9, minWin=26, winSum=435
3603 01:32:21.988830 TX Vref=32, minBit 2, minWin=26, winSum=432
3604 01:32:21.988882 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3605 01:32:21.988935
3606 01:32:21.988987 Final TX Range 1 Vref 30
3607 01:32:21.989039
3608 01:32:21.989090 ==
3609 01:32:21.989142 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 01:32:21.989194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 01:32:21.989247 ==
3612 01:32:21.989310
3613 01:32:21.989375
3614 01:32:21.989425 TX Vref Scan disable
3615 01:32:21.989476 == TX Byte 0 ==
3616 01:32:21.989527 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3617 01:32:21.989578 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3618 01:32:21.989629 == TX Byte 1 ==
3619 01:32:21.989680 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3620 01:32:21.989731 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3621 01:32:21.989792
3622 01:32:21.989847 [DATLAT]
3623 01:32:21.989898 Freq=1200, CH1 RK1
3624 01:32:21.989949
3625 01:32:21.989999 DATLAT Default: 0xd
3626 01:32:21.990050 0, 0xFFFF, sum = 0
3627 01:32:21.990102 1, 0xFFFF, sum = 0
3628 01:32:21.990153 2, 0xFFFF, sum = 0
3629 01:32:21.990205 3, 0xFFFF, sum = 0
3630 01:32:21.990257 4, 0xFFFF, sum = 0
3631 01:32:21.990309 5, 0xFFFF, sum = 0
3632 01:32:21.990360 6, 0xFFFF, sum = 0
3633 01:32:21.990418 7, 0xFFFF, sum = 0
3634 01:32:21.990470 8, 0xFFFF, sum = 0
3635 01:32:21.990522 9, 0xFFFF, sum = 0
3636 01:32:21.990574 10, 0xFFFF, sum = 0
3637 01:32:21.990624 11, 0xFFFF, sum = 0
3638 01:32:21.990676 12, 0x0, sum = 1
3639 01:32:21.990728 13, 0x0, sum = 2
3640 01:32:21.990797 14, 0x0, sum = 3
3641 01:32:21.990850 15, 0x0, sum = 4
3642 01:32:21.990903 best_step = 13
3643 01:32:21.990953
3644 01:32:21.991004 ==
3645 01:32:21.991055 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 01:32:21.991106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 01:32:21.991157 ==
3648 01:32:21.991208 RX Vref Scan: 0
3649 01:32:21.991258
3650 01:32:21.991309 RX Vref 0 -> 0, step: 1
3651 01:32:21.991360
3652 01:32:21.991410 RX Delay -13 -> 252, step: 4
3653 01:32:21.991460 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3654 01:32:21.991511 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3655 01:32:21.991562 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3656 01:32:21.991612 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3657 01:32:21.991663 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3658 01:32:21.991714 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3659 01:32:21.991764 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3660 01:32:21.991815 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3661 01:32:21.991866 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3662 01:32:21.991917 iDelay=195, Bit 9, Center 100 (39 ~ 162) 124
3663 01:32:21.991968 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3664 01:32:21.992019 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3665 01:32:21.992069 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3666 01:32:21.992120 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3667 01:32:21.992171 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3668 01:32:21.992221 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3669 01:32:21.992272 ==
3670 01:32:21.992323 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 01:32:21.992373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 01:32:21.992425 ==
3673 01:32:21.992475 DQS Delay:
3674 01:32:21.992525 DQS0 = 0, DQS1 = 0
3675 01:32:21.992577 DQM Delay:
3676 01:32:21.992627 DQM0 = 115, DQM1 = 111
3677 01:32:21.992678 DQ Delay:
3678 01:32:21.992728 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3679 01:32:21.992779 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =112
3680 01:32:21.992831 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =104
3681 01:32:21.992882 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =122
3682 01:32:21.992933
3683 01:32:21.992983
3684 01:32:21.993033 [DQSOSCAuto] RK1, (LSB)MR18= 0xf204, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3685 01:32:21.993085 CH1 RK1: MR19=304, MR18=F204
3686 01:32:21.993136 CH1_RK1: MR19=0x304, MR18=0xF204, DQSOSC=408, MR23=63, INC=39, DEC=26
3687 01:32:21.993187 [RxdqsGatingPostProcess] freq 1200
3688 01:32:21.993238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3689 01:32:21.993333 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 01:32:21.993385 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 01:32:21.993436 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 01:32:21.993487 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 01:32:21.993537 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 01:32:21.993587 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 01:32:21.993638 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 01:32:21.993689 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 01:32:21.993740 Pre-setting of DQS Precalculation
3698 01:32:21.993791 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3699 01:32:21.993842 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3700 01:32:21.993893 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3701 01:32:21.993945
3702 01:32:21.993995
3703 01:32:21.994045 [Calibration Summary] 2400 Mbps
3704 01:32:21.994095 CH 0, Rank 0
3705 01:32:21.994146 SW Impedance : PASS
3706 01:32:21.994216 DUTY Scan : NO K
3707 01:32:21.994270 ZQ Calibration : PASS
3708 01:32:21.994517 Jitter Meter : NO K
3709 01:32:21.994580 CBT Training : PASS
3710 01:32:21.994634 Write leveling : PASS
3711 01:32:21.994686 RX DQS gating : PASS
3712 01:32:21.994737 RX DQ/DQS(RDDQC) : PASS
3713 01:32:21.994788 TX DQ/DQS : PASS
3714 01:32:21.994840 RX DATLAT : PASS
3715 01:32:21.994891 RX DQ/DQS(Engine): PASS
3716 01:32:21.994942 TX OE : NO K
3717 01:32:21.994993 All Pass.
3718 01:32:21.995051
3719 01:32:21.995146 CH 0, Rank 1
3720 01:32:21.995230 SW Impedance : PASS
3721 01:32:21.995284 DUTY Scan : NO K
3722 01:32:21.995336 ZQ Calibration : PASS
3723 01:32:21.995387 Jitter Meter : NO K
3724 01:32:21.995438 CBT Training : PASS
3725 01:32:21.995489 Write leveling : PASS
3726 01:32:21.995539 RX DQS gating : PASS
3727 01:32:21.995589 RX DQ/DQS(RDDQC) : PASS
3728 01:32:21.995639 TX DQ/DQS : PASS
3729 01:32:21.995690 RX DATLAT : PASS
3730 01:32:21.995741 RX DQ/DQS(Engine): PASS
3731 01:32:21.995791 TX OE : NO K
3732 01:32:21.995841 All Pass.
3733 01:32:21.995892
3734 01:32:21.995942 CH 1, Rank 0
3735 01:32:21.995993 SW Impedance : PASS
3736 01:32:21.996043 DUTY Scan : NO K
3737 01:32:21.996094 ZQ Calibration : PASS
3738 01:32:21.996144 Jitter Meter : NO K
3739 01:32:21.996195 CBT Training : PASS
3740 01:32:21.996249 Write leveling : PASS
3741 01:32:21.996299 RX DQS gating : PASS
3742 01:32:21.996350 RX DQ/DQS(RDDQC) : PASS
3743 01:32:21.996400 TX DQ/DQS : PASS
3744 01:32:21.996451 RX DATLAT : PASS
3745 01:32:21.996501 RX DQ/DQS(Engine): PASS
3746 01:32:21.996551 TX OE : NO K
3747 01:32:21.996602 All Pass.
3748 01:32:21.996653
3749 01:32:21.996703 CH 1, Rank 1
3750 01:32:21.996753 SW Impedance : PASS
3751 01:32:21.996803 DUTY Scan : NO K
3752 01:32:21.996854 ZQ Calibration : PASS
3753 01:32:21.996905 Jitter Meter : NO K
3754 01:32:21.996954 CBT Training : PASS
3755 01:32:21.997005 Write leveling : PASS
3756 01:32:21.997055 RX DQS gating : PASS
3757 01:32:21.997106 RX DQ/DQS(RDDQC) : PASS
3758 01:32:21.997156 TX DQ/DQS : PASS
3759 01:32:21.997207 RX DATLAT : PASS
3760 01:32:21.997264 RX DQ/DQS(Engine): PASS
3761 01:32:21.997351 TX OE : NO K
3762 01:32:21.997402 All Pass.
3763 01:32:21.997453
3764 01:32:21.997504 DramC Write-DBI off
3765 01:32:21.997575 PER_BANK_REFRESH: Hybrid Mode
3766 01:32:21.997628 TX_TRACKING: ON
3767 01:32:21.997680 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3768 01:32:21.997733 [FAST_K] Save calibration result to emmc
3769 01:32:21.997784 dramc_set_vcore_voltage set vcore to 650000
3770 01:32:21.997836 Read voltage for 600, 5
3771 01:32:21.997887 Vio18 = 0
3772 01:32:21.997937 Vcore = 650000
3773 01:32:21.997988 Vdram = 0
3774 01:32:21.998038 Vddq = 0
3775 01:32:21.998088 Vmddr = 0
3776 01:32:21.998139 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3777 01:32:21.998190 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3778 01:32:21.998241 MEM_TYPE=3, freq_sel=19
3779 01:32:21.998292 sv_algorithm_assistance_LP4_1600
3780 01:32:21.998343 ============ PULL DRAM RESETB DOWN ============
3781 01:32:21.998394 ========== PULL DRAM RESETB DOWN end =========
3782 01:32:21.998446 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3783 01:32:21.998496 ===================================
3784 01:32:21.998547 LPDDR4 DRAM CONFIGURATION
3785 01:32:21.998598 ===================================
3786 01:32:21.998649 EX_ROW_EN[0] = 0x0
3787 01:32:21.998699 EX_ROW_EN[1] = 0x0
3788 01:32:21.998750 LP4Y_EN = 0x0
3789 01:32:21.998800 WORK_FSP = 0x0
3790 01:32:21.998850 WL = 0x2
3791 01:32:21.998901 RL = 0x2
3792 01:32:21.998952 BL = 0x2
3793 01:32:21.999002 RPST = 0x0
3794 01:32:21.999052 RD_PRE = 0x0
3795 01:32:21.999102 WR_PRE = 0x1
3796 01:32:21.999152 WR_PST = 0x0
3797 01:32:21.999202 DBI_WR = 0x0
3798 01:32:21.999253 DBI_RD = 0x0
3799 01:32:21.999303 OTF = 0x1
3800 01:32:21.999354 ===================================
3801 01:32:21.999404 ===================================
3802 01:32:21.999455 ANA top config
3803 01:32:21.999505 ===================================
3804 01:32:21.999557 DLL_ASYNC_EN = 0
3805 01:32:21.999607 ALL_SLAVE_EN = 1
3806 01:32:21.999658 NEW_RANK_MODE = 1
3807 01:32:21.999709 DLL_IDLE_MODE = 1
3808 01:32:21.999759 LP45_APHY_COMB_EN = 1
3809 01:32:21.999810 TX_ODT_DIS = 1
3810 01:32:21.999860 NEW_8X_MODE = 1
3811 01:32:21.999911 ===================================
3812 01:32:21.999962 ===================================
3813 01:32:22.000013 data_rate = 1200
3814 01:32:22.000063 CKR = 1
3815 01:32:22.000114 DQ_P2S_RATIO = 8
3816 01:32:22.000165 ===================================
3817 01:32:22.000216 CA_P2S_RATIO = 8
3818 01:32:22.000266 DQ_CA_OPEN = 0
3819 01:32:22.000316 DQ_SEMI_OPEN = 0
3820 01:32:22.000367 CA_SEMI_OPEN = 0
3821 01:32:22.000417 CA_FULL_RATE = 0
3822 01:32:22.000468 DQ_CKDIV4_EN = 1
3823 01:32:22.000519 CA_CKDIV4_EN = 1
3824 01:32:22.000570 CA_PREDIV_EN = 0
3825 01:32:22.000620 PH8_DLY = 0
3826 01:32:22.000671 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3827 01:32:22.000722 DQ_AAMCK_DIV = 4
3828 01:32:22.000785 CA_AAMCK_DIV = 4
3829 01:32:22.000839 CA_ADMCK_DIV = 4
3830 01:32:22.000891 DQ_TRACK_CA_EN = 0
3831 01:32:22.000941 CA_PICK = 600
3832 01:32:22.000992 CA_MCKIO = 600
3833 01:32:22.001043 MCKIO_SEMI = 0
3834 01:32:22.001093 PLL_FREQ = 2288
3835 01:32:22.001145 DQ_UI_PI_RATIO = 32
3836 01:32:22.001195 CA_UI_PI_RATIO = 0
3837 01:32:22.001246 ===================================
3838 01:32:22.001345 ===================================
3839 01:32:22.001397 memory_type:LPDDR4
3840 01:32:22.001448 GP_NUM : 10
3841 01:32:22.001499 SRAM_EN : 1
3842 01:32:22.001549 MD32_EN : 0
3843 01:32:22.001600 ===================================
3844 01:32:22.001652 [ANA_INIT] >>>>>>>>>>>>>>
3845 01:32:22.001703 <<<<<< [CONFIGURE PHASE]: ANA_TX
3846 01:32:22.001754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3847 01:32:22.001805 ===================================
3848 01:32:22.001856 data_rate = 1200,PCW = 0X5800
3849 01:32:22.001907 ===================================
3850 01:32:22.001958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3851 01:32:22.002010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 01:32:22.002061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 01:32:22.002303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3854 01:32:22.002362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3855 01:32:22.002415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3856 01:32:22.002477 [ANA_INIT] flow start
3857 01:32:22.002530 [ANA_INIT] PLL >>>>>>>>
3858 01:32:22.002581 [ANA_INIT] PLL <<<<<<<<
3859 01:32:22.002632 [ANA_INIT] MIDPI >>>>>>>>
3860 01:32:22.002684 [ANA_INIT] MIDPI <<<<<<<<
3861 01:32:22.002735 [ANA_INIT] DLL >>>>>>>>
3862 01:32:22.002786 [ANA_INIT] flow end
3863 01:32:22.002837 ============ LP4 DIFF to SE enter ============
3864 01:32:22.002888 ============ LP4 DIFF to SE exit ============
3865 01:32:22.002940 [ANA_INIT] <<<<<<<<<<<<<
3866 01:32:22.002991 [Flow] Enable top DCM control >>>>>
3867 01:32:22.003042 [Flow] Enable top DCM control <<<<<
3868 01:32:22.003092 Enable DLL master slave shuffle
3869 01:32:22.003144 ==============================================================
3870 01:32:22.003195 Gating Mode config
3871 01:32:22.003246 ==============================================================
3872 01:32:22.003297 Config description:
3873 01:32:22.003348 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3874 01:32:22.003400 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3875 01:32:22.003452 SELPH_MODE 0: By rank 1: By Phase
3876 01:32:22.003503 ==============================================================
3877 01:32:22.003555 GAT_TRACK_EN = 1
3878 01:32:22.003605 RX_GATING_MODE = 2
3879 01:32:22.003656 RX_GATING_TRACK_MODE = 2
3880 01:32:22.003724 SELPH_MODE = 1
3881 01:32:22.003779 PICG_EARLY_EN = 1
3882 01:32:22.003830 VALID_LAT_VALUE = 1
3883 01:32:22.003881 ==============================================================
3884 01:32:22.003933 Enter into Gating configuration >>>>
3885 01:32:22.003984 Exit from Gating configuration <<<<
3886 01:32:22.004036 Enter into DVFS_PRE_config >>>>>
3887 01:32:22.004087 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3888 01:32:22.004140 Exit from DVFS_PRE_config <<<<<
3889 01:32:22.004190 Enter into PICG configuration >>>>
3890 01:32:22.004242 Exit from PICG configuration <<<<
3891 01:32:22.004305 [RX_INPUT] configuration >>>>>
3892 01:32:22.007530 [RX_INPUT] configuration <<<<<
3893 01:32:22.010895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3894 01:32:22.017321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3895 01:32:22.024039 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 01:32:22.030489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 01:32:22.037124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 01:32:22.044096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 01:32:22.047169 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3900 01:32:22.050171 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3901 01:32:22.053566 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3902 01:32:22.060495 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3903 01:32:22.063648 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3904 01:32:22.066934 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 01:32:22.070450 ===================================
3906 01:32:22.073956 LPDDR4 DRAM CONFIGURATION
3907 01:32:22.076284 ===================================
3908 01:32:22.076794 EX_ROW_EN[0] = 0x0
3909 01:32:22.079955 EX_ROW_EN[1] = 0x0
3910 01:32:22.082942 LP4Y_EN = 0x0
3911 01:32:22.083348 WORK_FSP = 0x0
3912 01:32:22.086130 WL = 0x2
3913 01:32:22.086537 RL = 0x2
3914 01:32:22.089692 BL = 0x2
3915 01:32:22.090259 RPST = 0x0
3916 01:32:22.093414 RD_PRE = 0x0
3917 01:32:22.093914 WR_PRE = 0x1
3918 01:32:22.096015 WR_PST = 0x0
3919 01:32:22.096421 DBI_WR = 0x0
3920 01:32:22.099781 DBI_RD = 0x0
3921 01:32:22.100286 OTF = 0x1
3922 01:32:22.102616 ===================================
3923 01:32:22.105768 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3924 01:32:22.113287 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3925 01:32:22.116666 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 01:32:22.119773 ===================================
3927 01:32:22.122876 LPDDR4 DRAM CONFIGURATION
3928 01:32:22.126190 ===================================
3929 01:32:22.126709 EX_ROW_EN[0] = 0x10
3930 01:32:22.129885 EX_ROW_EN[1] = 0x0
3931 01:32:22.132688 LP4Y_EN = 0x0
3932 01:32:22.133195 WORK_FSP = 0x0
3933 01:32:22.136737 WL = 0x2
3934 01:32:22.137237 RL = 0x2
3935 01:32:22.139409 BL = 0x2
3936 01:32:22.139817 RPST = 0x0
3937 01:32:22.142590 RD_PRE = 0x0
3938 01:32:22.142996 WR_PRE = 0x1
3939 01:32:22.145523 WR_PST = 0x0
3940 01:32:22.145932 DBI_WR = 0x0
3941 01:32:22.149014 DBI_RD = 0x0
3942 01:32:22.149456 OTF = 0x1
3943 01:32:22.152161 ===================================
3944 01:32:22.159158 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3945 01:32:22.163661 nWR fixed to 30
3946 01:32:22.166667 [ModeRegInit_LP4] CH0 RK0
3947 01:32:22.166969 [ModeRegInit_LP4] CH0 RK1
3948 01:32:22.169755 [ModeRegInit_LP4] CH1 RK0
3949 01:32:22.173625 [ModeRegInit_LP4] CH1 RK1
3950 01:32:22.173918 match AC timing 17
3951 01:32:22.179459 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3952 01:32:22.182627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3953 01:32:22.186340 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3954 01:32:22.192791 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3955 01:32:22.195904 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3956 01:32:22.196373 ==
3957 01:32:22.199747 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 01:32:22.202598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 01:32:22.206665 ==
3960 01:32:22.209243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 01:32:22.216338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3962 01:32:22.219579 [CA 0] Center 36 (6~67) winsize 62
3963 01:32:22.222561 [CA 1] Center 36 (6~66) winsize 61
3964 01:32:22.226161 [CA 2] Center 34 (4~65) winsize 62
3965 01:32:22.231728 [CA 3] Center 34 (3~65) winsize 63
3966 01:32:22.232714 [CA 4] Center 33 (3~64) winsize 62
3967 01:32:22.236053 [CA 5] Center 33 (3~64) winsize 62
3968 01:32:22.236575
3969 01:32:22.238973 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3970 01:32:22.239382
3971 01:32:22.242694 [CATrainingPosCal] consider 1 rank data
3972 01:32:22.245922 u2DelayCellTimex100 = 270/100 ps
3973 01:32:22.248978 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3974 01:32:22.253101 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 01:32:22.255718 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 01:32:22.262229 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3977 01:32:22.265874 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 01:32:22.269064 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 01:32:22.269759
3980 01:32:22.272491 CA PerBit enable=1, Macro0, CA PI delay=33
3981 01:32:22.272946
3982 01:32:22.275875 [CBTSetCACLKResult] CA Dly = 33
3983 01:32:22.276431 CS Dly: 4 (0~35)
3984 01:32:22.276792 ==
3985 01:32:22.278781 Dram Type= 6, Freq= 0, CH_0, rank 1
3986 01:32:22.285480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 01:32:22.285942 ==
3988 01:32:22.288412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 01:32:22.295256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3990 01:32:22.299036 [CA 0] Center 36 (6~67) winsize 62
3991 01:32:22.302499 [CA 1] Center 36 (6~67) winsize 62
3992 01:32:22.305441 [CA 2] Center 34 (4~65) winsize 62
3993 01:32:22.309144 [CA 3] Center 34 (4~65) winsize 62
3994 01:32:22.311982 [CA 4] Center 33 (3~64) winsize 62
3995 01:32:22.315398 [CA 5] Center 33 (3~64) winsize 62
3996 01:32:22.316067
3997 01:32:22.318383 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3998 01:32:22.318838
3999 01:32:22.322258 [CATrainingPosCal] consider 2 rank data
4000 01:32:22.325492 u2DelayCellTimex100 = 270/100 ps
4001 01:32:22.328663 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4002 01:32:22.335816 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4003 01:32:22.338350 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 01:32:22.341648 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4005 01:32:22.345147 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 01:32:22.348536 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 01:32:22.349050
4008 01:32:22.351664 CA PerBit enable=1, Macro0, CA PI delay=33
4009 01:32:22.352175
4010 01:32:22.354848 [CBTSetCACLKResult] CA Dly = 33
4011 01:32:22.357989 CS Dly: 4 (0~36)
4012 01:32:22.358515
4013 01:32:22.361007 ----->DramcWriteLeveling(PI) begin...
4014 01:32:22.361456 ==
4015 01:32:22.364745 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 01:32:22.367932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 01:32:22.368345 ==
4018 01:32:22.370964 Write leveling (Byte 0): 32 => 32
4019 01:32:22.374362 Write leveling (Byte 1): 30 => 30
4020 01:32:22.378005 DramcWriteLeveling(PI) end<-----
4021 01:32:22.378415
4022 01:32:22.378736 ==
4023 01:32:22.381747 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 01:32:22.384819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 01:32:22.385230 ==
4026 01:32:22.387683 [Gating] SW mode calibration
4027 01:32:22.394684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 01:32:22.400563 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4029 01:32:22.404070 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 01:32:22.407735 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 01:32:22.414107 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 01:32:22.417938 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4033 01:32:22.420651 0 9 16 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
4034 01:32:22.426935 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 01:32:22.430329 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 01:32:22.433605 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 01:32:22.440341 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 01:32:22.443687 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 01:32:22.450403 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 01:32:22.453864 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4041 01:32:22.456929 0 10 16 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4042 01:32:22.463185 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 01:32:22.467158 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 01:32:22.469834 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 01:32:22.477072 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 01:32:22.480014 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 01:32:22.483263 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 01:32:22.489921 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4049 01:32:22.493358 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 01:32:22.496402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 01:32:22.503067 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 01:32:22.505861 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 01:32:22.510261 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 01:32:22.516041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 01:32:22.519910 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 01:32:22.522811 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 01:32:22.529139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 01:32:22.533032 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 01:32:22.535841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 01:32:22.543289 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 01:32:22.546179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 01:32:22.549013 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 01:32:22.555509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 01:32:22.559496 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 01:32:22.562079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4066 01:32:22.565312 Total UI for P1: 0, mck2ui 16
4067 01:32:22.568711 best dqsien dly found for B0: ( 0, 13, 14)
4068 01:32:22.575202 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 01:32:22.575777 Total UI for P1: 0, mck2ui 16
4070 01:32:22.578894 best dqsien dly found for B1: ( 0, 13, 16)
4071 01:32:22.585016 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4072 01:32:22.589077 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4073 01:32:22.589523
4074 01:32:22.591766 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4075 01:32:22.595131 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4076 01:32:22.598183 [Gating] SW calibration Done
4077 01:32:22.598614 ==
4078 01:32:22.601717 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 01:32:22.605059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 01:32:22.605568 ==
4081 01:32:22.608393 RX Vref Scan: 0
4082 01:32:22.608800
4083 01:32:22.609123 RX Vref 0 -> 0, step: 1
4084 01:32:22.609474
4085 01:32:22.611058 RX Delay -230 -> 252, step: 16
4086 01:32:22.618049 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4087 01:32:22.621160 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4088 01:32:22.624566 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4089 01:32:22.627577 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4090 01:32:22.634374 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4091 01:32:22.637489 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4092 01:32:22.641357 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4093 01:32:22.644269 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4094 01:32:22.647416 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4095 01:32:22.654223 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4096 01:32:22.657215 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4097 01:32:22.660356 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4098 01:32:22.664199 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4099 01:32:22.670505 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4100 01:32:22.673881 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4101 01:32:22.676980 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4102 01:32:22.677411 ==
4103 01:32:22.680541 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 01:32:22.686689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 01:32:22.687119 ==
4106 01:32:22.687443 DQS Delay:
4107 01:32:22.690170 DQS0 = 0, DQS1 = 0
4108 01:32:22.690586 DQM Delay:
4109 01:32:22.690909 DQM0 = 41, DQM1 = 33
4110 01:32:22.693387 DQ Delay:
4111 01:32:22.697112 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4112 01:32:22.700277 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4113 01:32:22.703592 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4114 01:32:22.707047 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4115 01:32:22.707461
4116 01:32:22.707785
4117 01:32:22.708088 ==
4118 01:32:22.710233 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 01:32:22.713639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 01:32:22.714151 ==
4121 01:32:22.714480
4122 01:32:22.714779
4123 01:32:22.717086 TX Vref Scan disable
4124 01:32:22.720228 == TX Byte 0 ==
4125 01:32:22.724140 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4126 01:32:22.726674 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4127 01:32:22.729904 == TX Byte 1 ==
4128 01:32:22.733538 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4129 01:32:22.736838 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4130 01:32:22.737396 ==
4131 01:32:22.739627 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 01:32:22.743100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 01:32:22.746553 ==
4134 01:32:22.747059
4135 01:32:22.747384
4136 01:32:22.747683 TX Vref Scan disable
4137 01:32:22.750072 == TX Byte 0 ==
4138 01:32:22.753682 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4139 01:32:22.760652 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4140 01:32:22.761192 == TX Byte 1 ==
4141 01:32:22.763464 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4142 01:32:22.769952 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4143 01:32:22.770496
4144 01:32:22.770834 [DATLAT]
4145 01:32:22.771139 Freq=600, CH0 RK0
4146 01:32:22.771433
4147 01:32:22.773275 DATLAT Default: 0x9
4148 01:32:22.773685 0, 0xFFFF, sum = 0
4149 01:32:22.776915 1, 0xFFFF, sum = 0
4150 01:32:22.777475 2, 0xFFFF, sum = 0
4151 01:32:22.779910 3, 0xFFFF, sum = 0
4152 01:32:22.783637 4, 0xFFFF, sum = 0
4153 01:32:22.784157 5, 0xFFFF, sum = 0
4154 01:32:22.786779 6, 0xFFFF, sum = 0
4155 01:32:22.787192 7, 0xFFFF, sum = 0
4156 01:32:22.790241 8, 0x0, sum = 1
4157 01:32:22.790657 9, 0x0, sum = 2
4158 01:32:22.790988 10, 0x0, sum = 3
4159 01:32:22.793485 11, 0x0, sum = 4
4160 01:32:22.793903 best_step = 9
4161 01:32:22.794229
4162 01:32:22.796902 ==
4163 01:32:22.797452 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 01:32:22.802831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 01:32:22.803243 ==
4166 01:32:22.803566 RX Vref Scan: 1
4167 01:32:22.803870
4168 01:32:22.806468 RX Vref 0 -> 0, step: 1
4169 01:32:22.806899
4170 01:32:22.809557 RX Delay -195 -> 252, step: 8
4171 01:32:22.809968
4172 01:32:22.812875 Set Vref, RX VrefLevel [Byte0]: 56
4173 01:32:22.815868 [Byte1]: 50
4174 01:32:22.816275
4175 01:32:22.819200 Final RX Vref Byte 0 = 56 to rank0
4176 01:32:22.823060 Final RX Vref Byte 1 = 50 to rank0
4177 01:32:22.825785 Final RX Vref Byte 0 = 56 to rank1
4178 01:32:22.829106 Final RX Vref Byte 1 = 50 to rank1==
4179 01:32:22.832863 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 01:32:22.835779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 01:32:22.839163 ==
4182 01:32:22.839570 DQS Delay:
4183 01:32:22.839894 DQS0 = 0, DQS1 = 0
4184 01:32:22.842591 DQM Delay:
4185 01:32:22.843094 DQM0 = 41, DQM1 = 34
4186 01:32:22.845886 DQ Delay:
4187 01:32:22.849155 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =36
4188 01:32:22.849605 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4189 01:32:22.852343 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4190 01:32:22.855884 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4191 01:32:22.858824
4192 01:32:22.859234
4193 01:32:22.865597 [DQSOSCAuto] RK0, (LSB)MR18= 0x463e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4194 01:32:22.869785 CH0 RK0: MR19=808, MR18=463E
4195 01:32:22.875293 CH0_RK0: MR19=0x808, MR18=0x463E, DQSOSC=396, MR23=63, INC=167, DEC=111
4196 01:32:22.875709
4197 01:32:22.879165 ----->DramcWriteLeveling(PI) begin...
4198 01:32:22.879596 ==
4199 01:32:22.882140 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 01:32:22.885299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 01:32:22.885735 ==
4202 01:32:22.889322 Write leveling (Byte 0): 33 => 33
4203 01:32:22.891639 Write leveling (Byte 1): 29 => 29
4204 01:32:22.895185 DramcWriteLeveling(PI) end<-----
4205 01:32:22.895595
4206 01:32:22.895951 ==
4207 01:32:22.898324 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 01:32:22.901990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 01:32:22.902407 ==
4210 01:32:22.904874 [Gating] SW mode calibration
4211 01:32:22.911767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4212 01:32:22.918118 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4213 01:32:22.921463 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 01:32:22.927886 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 01:32:22.931834 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 01:32:22.934459 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4217 01:32:22.941305 0 9 16 | B1->B0 | 2e2e 2525 | 1 1 | (1 1) (1 0)
4218 01:32:22.944215 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 01:32:22.947461 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 01:32:22.954543 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 01:32:22.957532 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 01:32:22.960616 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 01:32:22.967371 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 01:32:22.970841 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
4225 01:32:22.974158 0 10 16 | B1->B0 | 3f3e 4646 | 1 0 | (1 1) (0 0)
4226 01:32:22.980574 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 01:32:22.984069 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 01:32:22.987528 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 01:32:22.993781 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 01:32:22.996967 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 01:32:23.000222 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 01:32:23.006614 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 01:32:23.009912 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4234 01:32:23.013392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 01:32:23.019806 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 01:32:23.022989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 01:32:23.026473 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 01:32:23.032937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 01:32:23.036311 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 01:32:23.039825 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 01:32:23.046200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 01:32:23.049525 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 01:32:23.052643 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 01:32:23.059890 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 01:32:23.062782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 01:32:23.066110 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 01:32:23.072438 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4248 01:32:23.076194 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4249 01:32:23.079214 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4250 01:32:23.086205 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 01:32:23.088961 Total UI for P1: 0, mck2ui 16
4252 01:32:23.092545 best dqsien dly found for B0: ( 0, 13, 12)
4253 01:32:23.095547 Total UI for P1: 0, mck2ui 16
4254 01:32:23.098949 best dqsien dly found for B1: ( 0, 13, 14)
4255 01:32:23.102206 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4256 01:32:23.105797 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4257 01:32:23.106209
4258 01:32:23.108860 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4259 01:32:23.112051 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4260 01:32:23.115235 [Gating] SW calibration Done
4261 01:32:23.115735 ==
4262 01:32:23.118776 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 01:32:23.121728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 01:32:23.125347 ==
4265 01:32:23.125760 RX Vref Scan: 0
4266 01:32:23.126087
4267 01:32:23.128156 RX Vref 0 -> 0, step: 1
4268 01:32:23.128567
4269 01:32:23.131716 RX Delay -230 -> 252, step: 16
4270 01:32:23.135110 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4271 01:32:23.138437 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4272 01:32:23.141586 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4273 01:32:23.148143 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4274 01:32:23.151392 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4275 01:32:23.155319 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4276 01:32:23.157948 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4277 01:32:23.164778 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4278 01:32:23.167779 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4279 01:32:23.171112 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4280 01:32:23.174775 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4281 01:32:23.181580 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4282 01:32:23.184549 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4283 01:32:23.187921 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4284 01:32:23.190754 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4285 01:32:23.197113 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4286 01:32:23.197651 ==
4287 01:32:23.200687 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 01:32:23.203522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 01:32:23.203986 ==
4290 01:32:23.204317 DQS Delay:
4291 01:32:23.206919 DQS0 = 0, DQS1 = 0
4292 01:32:23.207397 DQM Delay:
4293 01:32:23.210709 DQM0 = 43, DQM1 = 33
4294 01:32:23.211117 DQ Delay:
4295 01:32:23.213535 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4296 01:32:23.217019 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4297 01:32:23.220143 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4298 01:32:23.224418 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4299 01:32:23.225052
4300 01:32:23.225485
4301 01:32:23.225937 ==
4302 01:32:23.226768 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 01:32:23.231026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 01:32:23.231438 ==
4305 01:32:23.233534
4306 01:32:23.233937
4307 01:32:23.234259 TX Vref Scan disable
4308 01:32:23.237330 == TX Byte 0 ==
4309 01:32:23.240205 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4310 01:32:23.243420 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4311 01:32:23.246492 == TX Byte 1 ==
4312 01:32:23.250438 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4313 01:32:23.252949 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4314 01:32:23.256636 ==
4315 01:32:23.259724 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 01:32:23.262707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 01:32:23.263118 ==
4318 01:32:23.263528
4319 01:32:23.263968
4320 01:32:23.266330 TX Vref Scan disable
4321 01:32:23.269318 == TX Byte 0 ==
4322 01:32:23.272996 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4323 01:32:23.275914 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4324 01:32:23.279238 == TX Byte 1 ==
4325 01:32:23.282801 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4326 01:32:23.285926 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4327 01:32:23.286341
4328 01:32:23.289304 [DATLAT]
4329 01:32:23.289710 Freq=600, CH0 RK1
4330 01:32:23.290033
4331 01:32:23.292567 DATLAT Default: 0x9
4332 01:32:23.293029 0, 0xFFFF, sum = 0
4333 01:32:23.295858 1, 0xFFFF, sum = 0
4334 01:32:23.296378 2, 0xFFFF, sum = 0
4335 01:32:23.299152 3, 0xFFFF, sum = 0
4336 01:32:23.299667 4, 0xFFFF, sum = 0
4337 01:32:23.302833 5, 0xFFFF, sum = 0
4338 01:32:23.303352 6, 0xFFFF, sum = 0
4339 01:32:23.306057 7, 0xFFFF, sum = 0
4340 01:32:23.306473 8, 0x0, sum = 1
4341 01:32:23.308941 9, 0x0, sum = 2
4342 01:32:23.309391 10, 0x0, sum = 3
4343 01:32:23.312624 11, 0x0, sum = 4
4344 01:32:23.313036 best_step = 9
4345 01:32:23.313404
4346 01:32:23.313717 ==
4347 01:32:23.316268 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 01:32:23.319754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 01:32:23.322655 ==
4350 01:32:23.323166 RX Vref Scan: 0
4351 01:32:23.323495
4352 01:32:23.325410 RX Vref 0 -> 0, step: 1
4353 01:32:23.325824
4354 01:32:23.328976 RX Delay -195 -> 252, step: 8
4355 01:32:23.332395 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4356 01:32:23.335510 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4357 01:32:23.342047 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4358 01:32:23.345549 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4359 01:32:23.348580 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4360 01:32:23.351654 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4361 01:32:23.358203 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4362 01:32:23.361567 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4363 01:32:23.364933 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4364 01:32:23.368651 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4365 01:32:23.374534 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4366 01:32:23.378210 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4367 01:32:23.381473 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4368 01:32:23.384904 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4369 01:32:23.391026 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4370 01:32:23.394964 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4371 01:32:23.395475 ==
4372 01:32:23.398057 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 01:32:23.401026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 01:32:23.401468 ==
4375 01:32:23.404671 DQS Delay:
4376 01:32:23.405433 DQS0 = 0, DQS1 = 0
4377 01:32:23.405782 DQM Delay:
4378 01:32:23.408051 DQM0 = 39, DQM1 = 34
4379 01:32:23.408561 DQ Delay:
4380 01:32:23.411071 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4381 01:32:23.414449 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4382 01:32:23.418088 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4383 01:32:23.420800 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4384 01:32:23.421209
4385 01:32:23.421560
4386 01:32:23.431058 [DQSOSCAuto] RK1, (LSB)MR18= 0x3935, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4387 01:32:23.433780 CH0 RK1: MR19=808, MR18=3935
4388 01:32:23.437636 CH0_RK1: MR19=0x808, MR18=0x3935, DQSOSC=399, MR23=63, INC=164, DEC=109
4389 01:32:23.440830 [RxdqsGatingPostProcess] freq 600
4390 01:32:23.448099 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 01:32:23.450664 Pre-setting of DQS Precalculation
4392 01:32:23.454250 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 01:32:23.457331 ==
4394 01:32:23.457869 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 01:32:23.463754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 01:32:23.464166 ==
4397 01:32:23.466789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 01:32:23.473365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 01:32:23.477711 [CA 0] Center 36 (6~66) winsize 61
4400 01:32:23.480484 [CA 1] Center 35 (5~66) winsize 62
4401 01:32:23.484129 [CA 2] Center 34 (4~65) winsize 62
4402 01:32:23.487038 [CA 3] Center 34 (3~65) winsize 63
4403 01:32:23.490540 [CA 4] Center 34 (4~65) winsize 62
4404 01:32:23.493874 [CA 5] Center 34 (3~65) winsize 63
4405 01:32:23.494284
4406 01:32:23.497486 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 01:32:23.497893
4408 01:32:23.500517 [CATrainingPosCal] consider 1 rank data
4409 01:32:23.503547 u2DelayCellTimex100 = 270/100 ps
4410 01:32:23.506697 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4411 01:32:23.513865 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4412 01:32:23.517148 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 01:32:23.520439 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4414 01:32:23.523731 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4415 01:32:23.527177 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4416 01:32:23.527765
4417 01:32:23.529862 CA PerBit enable=1, Macro0, CA PI delay=34
4418 01:32:23.530271
4419 01:32:23.533634 [CBTSetCACLKResult] CA Dly = 34
4420 01:32:23.536885 CS Dly: 4 (0~35)
4421 01:32:23.537316 ==
4422 01:32:23.540115 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 01:32:23.543708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 01:32:23.544220 ==
4425 01:32:23.549900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 01:32:23.553150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4427 01:32:23.557368 [CA 0] Center 35 (5~66) winsize 62
4428 01:32:23.560261 [CA 1] Center 35 (5~66) winsize 62
4429 01:32:23.563899 [CA 2] Center 34 (4~65) winsize 62
4430 01:32:23.567887 [CA 3] Center 34 (3~65) winsize 63
4431 01:32:23.570326 [CA 4] Center 34 (3~65) winsize 63
4432 01:32:23.573691 [CA 5] Center 34 (3~65) winsize 63
4433 01:32:23.574102
4434 01:32:23.577004 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4435 01:32:23.577440
4436 01:32:23.580657 [CATrainingPosCal] consider 2 rank data
4437 01:32:23.583383 u2DelayCellTimex100 = 270/100 ps
4438 01:32:23.587145 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4439 01:32:23.593320 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4440 01:32:23.596561 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4441 01:32:23.600205 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4442 01:32:23.603297 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4443 01:32:23.607654 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4444 01:32:23.608249
4445 01:32:23.610038 CA PerBit enable=1, Macro0, CA PI delay=34
4446 01:32:23.610447
4447 01:32:23.612867 [CBTSetCACLKResult] CA Dly = 34
4448 01:32:23.616655 CS Dly: 4 (0~36)
4449 01:32:23.617165
4450 01:32:23.619930 ----->DramcWriteLeveling(PI) begin...
4451 01:32:23.620344 ==
4452 01:32:23.623136 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 01:32:23.626573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 01:32:23.626986 ==
4455 01:32:23.629469 Write leveling (Byte 0): 28 => 28
4456 01:32:23.633119 Write leveling (Byte 1): 32 => 32
4457 01:32:23.636243 DramcWriteLeveling(PI) end<-----
4458 01:32:23.636767
4459 01:32:23.637094 ==
4460 01:32:23.639713 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 01:32:23.643537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 01:32:23.644053 ==
4463 01:32:23.646094 [Gating] SW mode calibration
4464 01:32:23.652430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 01:32:23.659140 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 01:32:23.662751 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 01:32:23.669497 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 01:32:23.672458 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 01:32:23.675844 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4470 01:32:23.682210 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 01:32:23.685211 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 01:32:23.688578 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 01:32:23.694973 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 01:32:23.699038 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 01:32:23.701719 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 01:32:23.708257 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 01:32:23.712507 0 10 12 | B1->B0 | 2c2c 3737 | 0 1 | (0 0) (0 0)
4478 01:32:23.714979 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 01:32:23.721365 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 01:32:23.724837 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 01:32:23.727759 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 01:32:23.734770 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 01:32:23.738292 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 01:32:23.741437 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 01:32:23.748251 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4486 01:32:23.751220 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 01:32:23.754714 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 01:32:23.761437 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 01:32:23.765040 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 01:32:23.768251 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 01:32:23.774344 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 01:32:23.778261 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 01:32:23.781290 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 01:32:23.787674 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 01:32:23.790649 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 01:32:23.794178 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 01:32:23.800570 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 01:32:23.804723 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 01:32:23.807102 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 01:32:23.813824 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 01:32:23.817505 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4502 01:32:23.820607 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 01:32:23.823743 Total UI for P1: 0, mck2ui 16
4504 01:32:23.827150 best dqsien dly found for B0: ( 0, 13, 12)
4505 01:32:23.831017 Total UI for P1: 0, mck2ui 16
4506 01:32:23.833832 best dqsien dly found for B1: ( 0, 13, 14)
4507 01:32:23.837372 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4508 01:32:23.840249 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4509 01:32:23.840800
4510 01:32:23.846874 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4511 01:32:23.850050 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4512 01:32:23.853758 [Gating] SW calibration Done
4513 01:32:23.854330 ==
4514 01:32:23.857034 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 01:32:23.859821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 01:32:23.860277 ==
4517 01:32:23.860713 RX Vref Scan: 0
4518 01:32:23.861058
4519 01:32:23.863478 RX Vref 0 -> 0, step: 1
4520 01:32:23.863997
4521 01:32:23.866747 RX Delay -230 -> 252, step: 16
4522 01:32:23.869940 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4523 01:32:23.872982 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4524 01:32:23.879491 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4525 01:32:23.883097 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4526 01:32:23.886117 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4527 01:32:23.889834 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4528 01:32:23.896427 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4529 01:32:23.899786 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4530 01:32:23.902905 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4531 01:32:23.905761 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4532 01:32:23.912167 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4533 01:32:23.915589 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4534 01:32:23.919109 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4535 01:32:23.922731 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4536 01:32:23.928569 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4537 01:32:23.932634 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4538 01:32:23.933150 ==
4539 01:32:23.935489 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 01:32:23.939081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 01:32:23.939595 ==
4542 01:32:23.941876 DQS Delay:
4543 01:32:23.942285 DQS0 = 0, DQS1 = 0
4544 01:32:23.942609 DQM Delay:
4545 01:32:23.945528 DQM0 = 44, DQM1 = 39
4546 01:32:23.945965 DQ Delay:
4547 01:32:23.948547 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4548 01:32:23.952754 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4549 01:32:23.955147 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4550 01:32:23.958161 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4551 01:32:23.958574
4552 01:32:23.958899
4553 01:32:23.959201 ==
4554 01:32:23.961898 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 01:32:23.969419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 01:32:23.969939 ==
4557 01:32:23.970269
4558 01:32:23.970570
4559 01:32:23.971922 TX Vref Scan disable
4560 01:32:23.972385 == TX Byte 0 ==
4561 01:32:23.978730 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4562 01:32:23.981773 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4563 01:32:23.982186 == TX Byte 1 ==
4564 01:32:23.987909 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4565 01:32:23.991574 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4566 01:32:23.992104 ==
4567 01:32:23.994570 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 01:32:23.998375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 01:32:23.998888 ==
4570 01:32:23.999213
4571 01:32:23.999512
4572 01:32:24.001217 TX Vref Scan disable
4573 01:32:24.004451 == TX Byte 0 ==
4574 01:32:24.008184 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4575 01:32:24.010986 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4576 01:32:24.014195 == TX Byte 1 ==
4577 01:32:24.017867 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4578 01:32:24.024297 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4579 01:32:24.024812
4580 01:32:24.025136 [DATLAT]
4581 01:32:24.025499 Freq=600, CH1 RK0
4582 01:32:24.025797
4583 01:32:24.027377 DATLAT Default: 0x9
4584 01:32:24.027784 0, 0xFFFF, sum = 0
4585 01:32:24.031068 1, 0xFFFF, sum = 0
4586 01:32:24.034408 2, 0xFFFF, sum = 0
4587 01:32:24.034823 3, 0xFFFF, sum = 0
4588 01:32:24.037630 4, 0xFFFF, sum = 0
4589 01:32:24.038062 5, 0xFFFF, sum = 0
4590 01:32:24.040879 6, 0xFFFF, sum = 0
4591 01:32:24.041442 7, 0xFFFF, sum = 0
4592 01:32:24.043780 8, 0x0, sum = 1
4593 01:32:24.044261 9, 0x0, sum = 2
4594 01:32:24.044597 10, 0x0, sum = 3
4595 01:32:24.047262 11, 0x0, sum = 4
4596 01:32:24.047780 best_step = 9
4597 01:32:24.048105
4598 01:32:24.048407 ==
4599 01:32:24.050542 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 01:32:24.057311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 01:32:24.057828 ==
4602 01:32:24.058208 RX Vref Scan: 1
4603 01:32:24.058522
4604 01:32:24.060625 RX Vref 0 -> 0, step: 1
4605 01:32:24.061032
4606 01:32:24.063636 RX Delay -179 -> 252, step: 8
4607 01:32:24.064047
4608 01:32:24.067125 Set Vref, RX VrefLevel [Byte0]: 52
4609 01:32:24.070192 [Byte1]: 47
4610 01:32:24.070603
4611 01:32:24.073805 Final RX Vref Byte 0 = 52 to rank0
4612 01:32:24.077254 Final RX Vref Byte 1 = 47 to rank0
4613 01:32:24.080160 Final RX Vref Byte 0 = 52 to rank1
4614 01:32:24.083215 Final RX Vref Byte 1 = 47 to rank1==
4615 01:32:24.086741 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 01:32:24.089803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 01:32:24.092963 ==
4618 01:32:24.093399 DQS Delay:
4619 01:32:24.093723 DQS0 = 0, DQS1 = 0
4620 01:32:24.096511 DQM Delay:
4621 01:32:24.096917 DQM0 = 42, DQM1 = 34
4622 01:32:24.099840 DQ Delay:
4623 01:32:24.100247 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4624 01:32:24.103109 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4625 01:32:24.106336 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4626 01:32:24.109622 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4627 01:32:24.110266
4628 01:32:24.112866
4629 01:32:24.119996 [DQSOSCAuto] RK0, (LSB)MR18= 0x304a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4630 01:32:24.123541 CH1 RK0: MR19=808, MR18=304A
4631 01:32:24.129362 CH1_RK0: MR19=0x808, MR18=0x304A, DQSOSC=395, MR23=63, INC=168, DEC=112
4632 01:32:24.129855
4633 01:32:24.133130 ----->DramcWriteLeveling(PI) begin...
4634 01:32:24.133692 ==
4635 01:32:24.136013 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 01:32:24.140027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 01:32:24.140569 ==
4638 01:32:24.142662 Write leveling (Byte 0): 31 => 31
4639 01:32:24.146186 Write leveling (Byte 1): 31 => 31
4640 01:32:24.149676 DramcWriteLeveling(PI) end<-----
4641 01:32:24.150086
4642 01:32:24.150409 ==
4643 01:32:24.152569 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 01:32:24.156044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 01:32:24.156460 ==
4646 01:32:24.159212 [Gating] SW mode calibration
4647 01:32:24.165638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4648 01:32:24.172495 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4649 01:32:24.175624 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 01:32:24.181994 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 01:32:24.185450 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 01:32:24.188837 0 9 12 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 0)
4653 01:32:24.195247 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 01:32:24.199054 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 01:32:24.201819 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 01:32:24.208543 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 01:32:24.212339 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 01:32:24.215682 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 01:32:24.222081 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4660 01:32:24.225132 0 10 12 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
4661 01:32:24.228115 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 01:32:24.234728 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 01:32:24.238183 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 01:32:24.241573 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 01:32:24.247849 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 01:32:24.251519 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 01:32:24.254813 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 01:32:24.261291 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4669 01:32:24.264722 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 01:32:24.267893 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 01:32:24.274155 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 01:32:24.278047 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 01:32:24.281179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 01:32:24.288018 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 01:32:24.290744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 01:32:24.294228 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 01:32:24.301248 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 01:32:24.304027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 01:32:24.307493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 01:32:24.313929 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 01:32:24.317630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 01:32:24.320211 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 01:32:24.327108 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 01:32:24.330916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4685 01:32:24.334703 Total UI for P1: 0, mck2ui 16
4686 01:32:24.336900 best dqsien dly found for B0: ( 0, 13, 10)
4687 01:32:24.340382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 01:32:24.343446 Total UI for P1: 0, mck2ui 16
4689 01:32:24.347276 best dqsien dly found for B1: ( 0, 13, 12)
4690 01:32:24.350272 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4691 01:32:24.353889 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4692 01:32:24.354400
4693 01:32:24.360345 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4694 01:32:24.363971 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4695 01:32:24.366769 [Gating] SW calibration Done
4696 01:32:24.367179 ==
4697 01:32:24.369756 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 01:32:24.373094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 01:32:24.373663 ==
4700 01:32:24.373997 RX Vref Scan: 0
4701 01:32:24.374305
4702 01:32:24.377042 RX Vref 0 -> 0, step: 1
4703 01:32:24.377496
4704 01:32:24.380007 RX Delay -230 -> 252, step: 16
4705 01:32:24.382828 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4706 01:32:24.389559 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4707 01:32:24.392735 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4708 01:32:24.396369 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4709 01:32:24.399509 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4710 01:32:24.402899 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4711 01:32:24.409698 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4712 01:32:24.412999 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4713 01:32:24.415983 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4714 01:32:24.419056 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4715 01:32:24.425804 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4716 01:32:24.428773 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4717 01:32:24.432346 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4718 01:32:24.435683 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4719 01:32:24.442226 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4720 01:32:24.445566 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4721 01:32:24.445978 ==
4722 01:32:24.448635 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 01:32:24.452013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 01:32:24.452423 ==
4725 01:32:24.455382 DQS Delay:
4726 01:32:24.455790 DQS0 = 0, DQS1 = 0
4727 01:32:24.459172 DQM Delay:
4728 01:32:24.459580 DQM0 = 43, DQM1 = 38
4729 01:32:24.459960 DQ Delay:
4730 01:32:24.462588 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4731 01:32:24.465570 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4732 01:32:24.468232 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4733 01:32:24.471827 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4734 01:32:24.472235
4735 01:32:24.472556
4736 01:32:24.475615 ==
4737 01:32:24.476024 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 01:32:24.482392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 01:32:24.482908 ==
4740 01:32:24.483239
4741 01:32:24.483540
4742 01:32:24.485193 TX Vref Scan disable
4743 01:32:24.485628 == TX Byte 0 ==
4744 01:32:24.491838 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4745 01:32:24.494957 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4746 01:32:24.495424 == TX Byte 1 ==
4747 01:32:24.501340 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4748 01:32:24.505050 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4749 01:32:24.505605 ==
4750 01:32:24.508223 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 01:32:24.510997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 01:32:24.511411 ==
4753 01:32:24.511736
4754 01:32:24.512034
4755 01:32:24.514390 TX Vref Scan disable
4756 01:32:24.517733 == TX Byte 0 ==
4757 01:32:24.521067 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4758 01:32:24.524563 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4759 01:32:24.527354 == TX Byte 1 ==
4760 01:32:24.531081 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 01:32:24.534231 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 01:32:24.537600
4763 01:32:24.538100 [DATLAT]
4764 01:32:24.538426 Freq=600, CH1 RK1
4765 01:32:24.538732
4766 01:32:24.540828 DATLAT Default: 0x9
4767 01:32:24.541375 0, 0xFFFF, sum = 0
4768 01:32:24.544034 1, 0xFFFF, sum = 0
4769 01:32:24.544545 2, 0xFFFF, sum = 0
4770 01:32:24.547616 3, 0xFFFF, sum = 0
4771 01:32:24.551059 4, 0xFFFF, sum = 0
4772 01:32:24.551572 5, 0xFFFF, sum = 0
4773 01:32:24.553942 6, 0xFFFF, sum = 0
4774 01:32:24.554455 7, 0xFFFF, sum = 0
4775 01:32:24.557970 8, 0x0, sum = 1
4776 01:32:24.558482 9, 0x0, sum = 2
4777 01:32:24.558810 10, 0x0, sum = 3
4778 01:32:24.560723 11, 0x0, sum = 4
4779 01:32:24.561247 best_step = 9
4780 01:32:24.561647
4781 01:32:24.561975 ==
4782 01:32:24.564296 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 01:32:24.570539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 01:32:24.571109 ==
4785 01:32:24.571470 RX Vref Scan: 0
4786 01:32:24.571797
4787 01:32:24.574231 RX Vref 0 -> 0, step: 1
4788 01:32:24.574678
4789 01:32:24.576717 RX Delay -179 -> 252, step: 8
4790 01:32:24.584359 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4791 01:32:24.587115 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4792 01:32:24.590066 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4793 01:32:24.593627 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4794 01:32:24.596818 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4795 01:32:24.603758 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4796 01:32:24.606353 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4797 01:32:24.610062 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4798 01:32:24.613124 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4799 01:32:24.619728 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4800 01:32:24.622965 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4801 01:32:24.626750 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4802 01:32:24.629338 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4803 01:32:24.636096 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4804 01:32:24.639281 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4805 01:32:24.642619 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4806 01:32:24.643026 ==
4807 01:32:24.646765 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 01:32:24.649170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 01:32:24.652955 ==
4810 01:32:24.653386 DQS Delay:
4811 01:32:24.653707 DQS0 = 0, DQS1 = 0
4812 01:32:24.655949 DQM Delay:
4813 01:32:24.656352 DQM0 = 37, DQM1 = 35
4814 01:32:24.659284 DQ Delay:
4815 01:32:24.662381 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4816 01:32:24.662801 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4817 01:32:24.665738 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4818 01:32:24.672737 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4819 01:32:24.673247
4820 01:32:24.673638
4821 01:32:24.679217 [DQSOSCAuto] RK1, (LSB)MR18= 0x3257, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4822 01:32:24.681774 CH1 RK1: MR19=808, MR18=3257
4823 01:32:24.689045 CH1_RK1: MR19=0x808, MR18=0x3257, DQSOSC=393, MR23=63, INC=169, DEC=113
4824 01:32:24.692300 [RxdqsGatingPostProcess] freq 600
4825 01:32:24.695517 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4826 01:32:24.698762 Pre-setting of DQS Precalculation
4827 01:32:24.705197 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4828 01:32:24.711995 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4829 01:32:24.718414 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4830 01:32:24.718868
4831 01:32:24.719225
4832 01:32:24.722520 [Calibration Summary] 1200 Mbps
4833 01:32:24.723085 CH 0, Rank 0
4834 01:32:24.724827 SW Impedance : PASS
4835 01:32:24.728346 DUTY Scan : NO K
4836 01:32:24.728719 ZQ Calibration : PASS
4837 01:32:24.731109 Jitter Meter : NO K
4838 01:32:24.735180 CBT Training : PASS
4839 01:32:24.735712 Write leveling : PASS
4840 01:32:24.737976 RX DQS gating : PASS
4841 01:32:24.741460 RX DQ/DQS(RDDQC) : PASS
4842 01:32:24.741966 TX DQ/DQS : PASS
4843 01:32:24.744617 RX DATLAT : PASS
4844 01:32:24.748348 RX DQ/DQS(Engine): PASS
4845 01:32:24.748859 TX OE : NO K
4846 01:32:24.751432 All Pass.
4847 01:32:24.751943
4848 01:32:24.752290 CH 0, Rank 1
4849 01:32:24.755194 SW Impedance : PASS
4850 01:32:24.755705 DUTY Scan : NO K
4851 01:32:24.757506 ZQ Calibration : PASS
4852 01:32:24.760903 Jitter Meter : NO K
4853 01:32:24.761361 CBT Training : PASS
4854 01:32:24.764526 Write leveling : PASS
4855 01:32:24.767670 RX DQS gating : PASS
4856 01:32:24.768191 RX DQ/DQS(RDDQC) : PASS
4857 01:32:24.770996 TX DQ/DQS : PASS
4858 01:32:24.773924 RX DATLAT : PASS
4859 01:32:24.774380 RX DQ/DQS(Engine): PASS
4860 01:32:24.777205 TX OE : NO K
4861 01:32:24.777658 All Pass.
4862 01:32:24.777981
4863 01:32:24.780722 CH 1, Rank 0
4864 01:32:24.781128 SW Impedance : PASS
4865 01:32:24.783739 DUTY Scan : NO K
4866 01:32:24.787347 ZQ Calibration : PASS
4867 01:32:24.787863 Jitter Meter : NO K
4868 01:32:24.791250 CBT Training : PASS
4869 01:32:24.794226 Write leveling : PASS
4870 01:32:24.794639 RX DQS gating : PASS
4871 01:32:24.796924 RX DQ/DQS(RDDQC) : PASS
4872 01:32:24.800329 TX DQ/DQS : PASS
4873 01:32:24.800741 RX DATLAT : PASS
4874 01:32:24.803525 RX DQ/DQS(Engine): PASS
4875 01:32:24.803932 TX OE : NO K
4876 01:32:24.806859 All Pass.
4877 01:32:24.807266
4878 01:32:24.807588 CH 1, Rank 1
4879 01:32:24.810859 SW Impedance : PASS
4880 01:32:24.811280 DUTY Scan : NO K
4881 01:32:24.813658 ZQ Calibration : PASS
4882 01:32:24.816679 Jitter Meter : NO K
4883 01:32:24.817089 CBT Training : PASS
4884 01:32:24.820595 Write leveling : PASS
4885 01:32:24.823412 RX DQS gating : PASS
4886 01:32:24.823821 RX DQ/DQS(RDDQC) : PASS
4887 01:32:24.827009 TX DQ/DQS : PASS
4888 01:32:24.830209 RX DATLAT : PASS
4889 01:32:24.830620 RX DQ/DQS(Engine): PASS
4890 01:32:24.833561 TX OE : NO K
4891 01:32:24.833971 All Pass.
4892 01:32:24.834294
4893 01:32:24.836723 DramC Write-DBI off
4894 01:32:24.840612 PER_BANK_REFRESH: Hybrid Mode
4895 01:32:24.841020 TX_TRACKING: ON
4896 01:32:24.849726 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4897 01:32:24.853353 [FAST_K] Save calibration result to emmc
4898 01:32:24.856534 dramc_set_vcore_voltage set vcore to 662500
4899 01:32:24.859616 Read voltage for 933, 3
4900 01:32:24.860125 Vio18 = 0
4901 01:32:24.860456 Vcore = 662500
4902 01:32:24.862805 Vdram = 0
4903 01:32:24.863214 Vddq = 0
4904 01:32:24.863535 Vmddr = 0
4905 01:32:24.869814 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4906 01:32:24.873052 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4907 01:32:24.876539 MEM_TYPE=3, freq_sel=17
4908 01:32:24.879654 sv_algorithm_assistance_LP4_1600
4909 01:32:24.883077 ============ PULL DRAM RESETB DOWN ============
4910 01:32:24.889413 ========== PULL DRAM RESETB DOWN end =========
4911 01:32:24.892533 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4912 01:32:24.895765 ===================================
4913 01:32:24.899719 LPDDR4 DRAM CONFIGURATION
4914 01:32:24.902717 ===================================
4915 01:32:24.903127 EX_ROW_EN[0] = 0x0
4916 01:32:24.905985 EX_ROW_EN[1] = 0x0
4917 01:32:24.906393 LP4Y_EN = 0x0
4918 01:32:24.909087 WORK_FSP = 0x0
4919 01:32:24.909627 WL = 0x3
4920 01:32:24.912752 RL = 0x3
4921 01:32:24.915514 BL = 0x2
4922 01:32:24.915923 RPST = 0x0
4923 01:32:24.919174 RD_PRE = 0x0
4924 01:32:24.919690 WR_PRE = 0x1
4925 01:32:24.922543 WR_PST = 0x0
4926 01:32:24.923042 DBI_WR = 0x0
4927 01:32:24.925588 DBI_RD = 0x0
4928 01:32:24.925999 OTF = 0x1
4929 01:32:24.928942 ===================================
4930 01:32:24.932557 ===================================
4931 01:32:24.935839 ANA top config
4932 01:32:24.939344 ===================================
4933 01:32:24.939847 DLL_ASYNC_EN = 0
4934 01:32:24.942167 ALL_SLAVE_EN = 1
4935 01:32:24.945074 NEW_RANK_MODE = 1
4936 01:32:24.948936 DLL_IDLE_MODE = 1
4937 01:32:24.951970 LP45_APHY_COMB_EN = 1
4938 01:32:24.952384 TX_ODT_DIS = 1
4939 01:32:24.955891 NEW_8X_MODE = 1
4940 01:32:24.958655 ===================================
4941 01:32:24.961654 ===================================
4942 01:32:24.964995 data_rate = 1866
4943 01:32:24.968425 CKR = 1
4944 01:32:24.971753 DQ_P2S_RATIO = 8
4945 01:32:24.975207 ===================================
4946 01:32:24.975631 CA_P2S_RATIO = 8
4947 01:32:24.978777 DQ_CA_OPEN = 0
4948 01:32:24.981891 DQ_SEMI_OPEN = 0
4949 01:32:24.985066 CA_SEMI_OPEN = 0
4950 01:32:24.988616 CA_FULL_RATE = 0
4951 01:32:24.991743 DQ_CKDIV4_EN = 1
4952 01:32:24.994989 CA_CKDIV4_EN = 1
4953 01:32:24.995402 CA_PREDIV_EN = 0
4954 01:32:24.998427 PH8_DLY = 0
4955 01:32:25.001527 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4956 01:32:25.004584 DQ_AAMCK_DIV = 4
4957 01:32:25.008081 CA_AAMCK_DIV = 4
4958 01:32:25.011247 CA_ADMCK_DIV = 4
4959 01:32:25.011686 DQ_TRACK_CA_EN = 0
4960 01:32:25.014563 CA_PICK = 933
4961 01:32:25.017768 CA_MCKIO = 933
4962 01:32:25.021349 MCKIO_SEMI = 0
4963 01:32:25.024423 PLL_FREQ = 3732
4964 01:32:25.027507 DQ_UI_PI_RATIO = 32
4965 01:32:25.030828 CA_UI_PI_RATIO = 0
4966 01:32:25.034535 ===================================
4967 01:32:25.037854 ===================================
4968 01:32:25.038368 memory_type:LPDDR4
4969 01:32:25.041335 GP_NUM : 10
4970 01:32:25.044517 SRAM_EN : 1
4971 01:32:25.045026 MD32_EN : 0
4972 01:32:25.047393 ===================================
4973 01:32:25.050919 [ANA_INIT] >>>>>>>>>>>>>>
4974 01:32:25.054018 <<<<<< [CONFIGURE PHASE]: ANA_TX
4975 01:32:25.057340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4976 01:32:25.060812 ===================================
4977 01:32:25.064521 data_rate = 1866,PCW = 0X8f00
4978 01:32:25.066987 ===================================
4979 01:32:25.070711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4980 01:32:25.074005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 01:32:25.080527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 01:32:25.083820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4983 01:32:25.090294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4984 01:32:25.093434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4985 01:32:25.093846 [ANA_INIT] flow start
4986 01:32:25.096509 [ANA_INIT] PLL >>>>>>>>
4987 01:32:25.100413 [ANA_INIT] PLL <<<<<<<<
4988 01:32:25.100948 [ANA_INIT] MIDPI >>>>>>>>
4989 01:32:25.103487 [ANA_INIT] MIDPI <<<<<<<<
4990 01:32:25.106843 [ANA_INIT] DLL >>>>>>>>
4991 01:32:25.107380 [ANA_INIT] flow end
4992 01:32:25.113053 ============ LP4 DIFF to SE enter ============
4993 01:32:25.116289 ============ LP4 DIFF to SE exit ============
4994 01:32:25.121102 [ANA_INIT] <<<<<<<<<<<<<
4995 01:32:25.121663 [Flow] Enable top DCM control >>>>>
4996 01:32:25.122803 [Flow] Enable top DCM control <<<<<
4997 01:32:25.126617 Enable DLL master slave shuffle
4998 01:32:25.133355 ==============================================================
4999 01:32:25.136422 Gating Mode config
5000 01:32:25.139549 ==============================================================
5001 01:32:25.142773 Config description:
5002 01:32:25.153090 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5003 01:32:25.159160 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5004 01:32:25.162670 SELPH_MODE 0: By rank 1: By Phase
5005 01:32:25.168840 ==============================================================
5006 01:32:25.172223 GAT_TRACK_EN = 1
5007 01:32:25.175288 RX_GATING_MODE = 2
5008 01:32:25.178778 RX_GATING_TRACK_MODE = 2
5009 01:32:25.182150 SELPH_MODE = 1
5010 01:32:25.185814 PICG_EARLY_EN = 1
5011 01:32:25.188848 VALID_LAT_VALUE = 1
5012 01:32:25.192283 ==============================================================
5013 01:32:25.195699 Enter into Gating configuration >>>>
5014 01:32:25.198746 Exit from Gating configuration <<<<
5015 01:32:25.201671 Enter into DVFS_PRE_config >>>>>
5016 01:32:25.214959 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5017 01:32:25.215404 Exit from DVFS_PRE_config <<<<<
5018 01:32:25.218315 Enter into PICG configuration >>>>
5019 01:32:25.221906 Exit from PICG configuration <<<<
5020 01:32:25.224807 [RX_INPUT] configuration >>>>>
5021 01:32:25.228048 [RX_INPUT] configuration <<<<<
5022 01:32:25.235660 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5023 01:32:25.238799 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5024 01:32:25.244863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 01:32:25.251158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 01:32:25.257767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 01:32:25.264545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 01:32:25.267414 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5029 01:32:25.271295 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5030 01:32:25.274050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5031 01:32:25.281130 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5032 01:32:25.284723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5033 01:32:25.287760 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 01:32:25.290603 ===================================
5035 01:32:25.294259 LPDDR4 DRAM CONFIGURATION
5036 01:32:25.297143 ===================================
5037 01:32:25.301231 EX_ROW_EN[0] = 0x0
5038 01:32:25.301810 EX_ROW_EN[1] = 0x0
5039 01:32:25.303900 LP4Y_EN = 0x0
5040 01:32:25.304419 WORK_FSP = 0x0
5041 01:32:25.307217 WL = 0x3
5042 01:32:25.307752 RL = 0x3
5043 01:32:25.310241 BL = 0x2
5044 01:32:25.310667 RPST = 0x0
5045 01:32:25.313930 RD_PRE = 0x0
5046 01:32:25.314359 WR_PRE = 0x1
5047 01:32:25.317059 WR_PST = 0x0
5048 01:32:25.317524 DBI_WR = 0x0
5049 01:32:25.321405 DBI_RD = 0x0
5050 01:32:25.323935 OTF = 0x1
5051 01:32:25.327358 ===================================
5052 01:32:25.330074 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5053 01:32:25.333972 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5054 01:32:25.337431 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 01:32:25.340327 ===================================
5056 01:32:25.343664 LPDDR4 DRAM CONFIGURATION
5057 01:32:25.346872 ===================================
5058 01:32:25.350509 EX_ROW_EN[0] = 0x10
5059 01:32:25.351016 EX_ROW_EN[1] = 0x0
5060 01:32:25.353656 LP4Y_EN = 0x0
5061 01:32:25.354166 WORK_FSP = 0x0
5062 01:32:25.356959 WL = 0x3
5063 01:32:25.357506 RL = 0x3
5064 01:32:25.359910 BL = 0x2
5065 01:32:25.360325 RPST = 0x0
5066 01:32:25.363303 RD_PRE = 0x0
5067 01:32:25.363717 WR_PRE = 0x1
5068 01:32:25.366560 WR_PST = 0x0
5069 01:32:25.369399 DBI_WR = 0x0
5070 01:32:25.369821 DBI_RD = 0x0
5071 01:32:25.373100 OTF = 0x1
5072 01:32:25.376148 ===================================
5073 01:32:25.380033 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5074 01:32:25.385027 nWR fixed to 30
5075 01:32:25.388648 [ModeRegInit_LP4] CH0 RK0
5076 01:32:25.389063 [ModeRegInit_LP4] CH0 RK1
5077 01:32:25.391611 [ModeRegInit_LP4] CH1 RK0
5078 01:32:25.394594 [ModeRegInit_LP4] CH1 RK1
5079 01:32:25.395011 match AC timing 9
5080 01:32:25.401699 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5081 01:32:25.405083 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5082 01:32:25.408137 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5083 01:32:25.414651 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5084 01:32:25.417709 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5085 01:32:25.418123 ==
5086 01:32:25.421544 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 01:32:25.424708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 01:32:25.425214 ==
5089 01:32:25.430953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 01:32:25.438131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 01:32:25.441083 [CA 0] Center 37 (7~68) winsize 62
5092 01:32:25.444894 [CA 1] Center 37 (7~68) winsize 62
5093 01:32:25.447720 [CA 2] Center 34 (4~65) winsize 62
5094 01:32:25.451200 [CA 3] Center 34 (4~65) winsize 62
5095 01:32:25.454230 [CA 4] Center 33 (3~63) winsize 61
5096 01:32:25.457329 [CA 5] Center 32 (2~63) winsize 62
5097 01:32:25.457748
5098 01:32:25.461170 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 01:32:25.461645
5100 01:32:25.464381 [CATrainingPosCal] consider 1 rank data
5101 01:32:25.467589 u2DelayCellTimex100 = 270/100 ps
5102 01:32:25.470459 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5103 01:32:25.473851 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5104 01:32:25.476999 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5105 01:32:25.483884 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5106 01:32:25.487404 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5107 01:32:25.490451 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5108 01:32:25.490864
5109 01:32:25.493927 CA PerBit enable=1, Macro0, CA PI delay=32
5110 01:32:25.494370
5111 01:32:25.496983 [CBTSetCACLKResult] CA Dly = 32
5112 01:32:25.497445 CS Dly: 5 (0~36)
5113 01:32:25.497819 ==
5114 01:32:25.500337 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 01:32:25.507549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 01:32:25.507987 ==
5117 01:32:25.510552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 01:32:25.516764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5119 01:32:25.520232 [CA 0] Center 37 (7~68) winsize 62
5120 01:32:25.523573 [CA 1] Center 37 (7~68) winsize 62
5121 01:32:25.526711 [CA 2] Center 35 (5~65) winsize 61
5122 01:32:25.530348 [CA 3] Center 34 (4~65) winsize 62
5123 01:32:25.533410 [CA 4] Center 33 (3~64) winsize 62
5124 01:32:25.536654 [CA 5] Center 32 (2~63) winsize 62
5125 01:32:25.537063
5126 01:32:25.539953 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5127 01:32:25.540553
5128 01:32:25.543465 [CATrainingPosCal] consider 2 rank data
5129 01:32:25.546422 u2DelayCellTimex100 = 270/100 ps
5130 01:32:25.550082 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5131 01:32:25.556946 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5132 01:32:25.559417 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5133 01:32:25.562926 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5134 01:32:25.566470 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5135 01:32:25.569836 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5136 01:32:25.570257
5137 01:32:25.573217 CA PerBit enable=1, Macro0, CA PI delay=32
5138 01:32:25.573663
5139 01:32:25.576719 [CBTSetCACLKResult] CA Dly = 32
5140 01:32:25.579365 CS Dly: 6 (0~38)
5141 01:32:25.579774
5142 01:32:25.583317 ----->DramcWriteLeveling(PI) begin...
5143 01:32:25.583834 ==
5144 01:32:25.586321 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 01:32:25.589359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 01:32:25.589772 ==
5147 01:32:25.593133 Write leveling (Byte 0): 32 => 32
5148 01:32:25.595983 Write leveling (Byte 1): 26 => 26
5149 01:32:25.598805 DramcWriteLeveling(PI) end<-----
5150 01:32:25.599213
5151 01:32:25.599533 ==
5152 01:32:25.603119 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 01:32:25.605794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 01:32:25.606220 ==
5155 01:32:25.608963 [Gating] SW mode calibration
5156 01:32:25.615691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5157 01:32:25.622750 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5158 01:32:25.626017 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5159 01:32:25.632136 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 01:32:25.635809 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 01:32:25.639074 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 01:32:25.645830 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 01:32:25.649030 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 01:32:25.651894 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 01:32:25.658852 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5166 01:32:25.662014 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5167 01:32:25.665798 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 01:32:25.672536 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 01:32:25.674962 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 01:32:25.678991 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 01:32:25.685428 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 01:32:25.688595 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 01:32:25.691469 0 15 28 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5174 01:32:25.698112 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5175 01:32:25.701515 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 01:32:25.704670 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 01:32:25.711076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 01:32:25.714318 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 01:32:25.717623 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 01:32:25.724758 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 01:32:25.728472 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5182 01:32:25.731033 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5183 01:32:25.738175 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 01:32:25.741179 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 01:32:25.744533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 01:32:25.751302 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 01:32:25.753836 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 01:32:25.758135 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 01:32:25.763849 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 01:32:25.767158 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 01:32:25.770824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 01:32:25.776690 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 01:32:25.779957 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 01:32:25.783855 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 01:32:25.790360 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 01:32:25.793689 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 01:32:25.796544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5198 01:32:25.802938 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5199 01:32:25.803353 Total UI for P1: 0, mck2ui 16
5200 01:32:25.810155 best dqsien dly found for B0: ( 1, 2, 28)
5201 01:32:25.813133 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5202 01:32:25.816075 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 01:32:25.819483 Total UI for P1: 0, mck2ui 16
5204 01:32:25.822413 best dqsien dly found for B1: ( 1, 3, 2)
5205 01:32:25.826093 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5206 01:32:25.829855 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5207 01:32:25.830371
5208 01:32:25.836047 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5209 01:32:25.839454 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5210 01:32:25.839972 [Gating] SW calibration Done
5211 01:32:25.842524 ==
5212 01:32:25.845895 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 01:32:25.849901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 01:32:25.850417 ==
5215 01:32:25.850745 RX Vref Scan: 0
5216 01:32:25.851048
5217 01:32:25.852476 RX Vref 0 -> 0, step: 1
5218 01:32:25.852886
5219 01:32:25.855884 RX Delay -80 -> 252, step: 8
5220 01:32:25.860168 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5221 01:32:25.862601 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5222 01:32:25.869149 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5223 01:32:25.872185 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5224 01:32:25.875727 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5225 01:32:25.878976 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5226 01:32:25.883015 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5227 01:32:25.885963 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5228 01:32:25.891735 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5229 01:32:25.895473 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5230 01:32:25.898364 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5231 01:32:25.901586 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5232 01:32:25.905132 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5233 01:32:25.911699 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5234 01:32:25.915122 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5235 01:32:25.918692 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5236 01:32:25.919205 ==
5237 01:32:25.921577 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 01:32:25.924803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 01:32:25.925367 ==
5240 01:32:25.928698 DQS Delay:
5241 01:32:25.929216 DQS0 = 0, DQS1 = 0
5242 01:32:25.929585 DQM Delay:
5243 01:32:25.931243 DQM0 = 100, DQM1 = 88
5244 01:32:25.931647 DQ Delay:
5245 01:32:25.935065 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5246 01:32:25.938202 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5247 01:32:25.941536 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5248 01:32:25.945126 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5249 01:32:25.945742
5250 01:32:25.946103
5251 01:32:25.948086 ==
5252 01:32:25.951634 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 01:32:25.954605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 01:32:25.955121 ==
5255 01:32:25.955591
5256 01:32:25.955935
5257 01:32:25.957805 TX Vref Scan disable
5258 01:32:25.958254 == TX Byte 0 ==
5259 01:32:25.964598 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5260 01:32:25.967943 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5261 01:32:25.968454 == TX Byte 1 ==
5262 01:32:25.974348 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5263 01:32:25.977286 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5264 01:32:25.977700 ==
5265 01:32:25.980533 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 01:32:25.983711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 01:32:25.984123 ==
5268 01:32:25.984445
5269 01:32:25.984743
5270 01:32:25.987388 TX Vref Scan disable
5271 01:32:25.991054 == TX Byte 0 ==
5272 01:32:25.994595 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5273 01:32:25.997116 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5274 01:32:26.001219 == TX Byte 1 ==
5275 01:32:26.004381 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5276 01:32:26.007039 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5277 01:32:26.007451
5278 01:32:26.010799 [DATLAT]
5279 01:32:26.011263 Freq=933, CH0 RK0
5280 01:32:26.011594
5281 01:32:26.013495 DATLAT Default: 0xd
5282 01:32:26.013991 0, 0xFFFF, sum = 0
5283 01:32:26.016920 1, 0xFFFF, sum = 0
5284 01:32:26.017487 2, 0xFFFF, sum = 0
5285 01:32:26.020077 3, 0xFFFF, sum = 0
5286 01:32:26.020592 4, 0xFFFF, sum = 0
5287 01:32:26.023663 5, 0xFFFF, sum = 0
5288 01:32:26.026657 6, 0xFFFF, sum = 0
5289 01:32:26.027177 7, 0xFFFF, sum = 0
5290 01:32:26.030150 8, 0xFFFF, sum = 0
5291 01:32:26.030673 9, 0xFFFF, sum = 0
5292 01:32:26.033313 10, 0x0, sum = 1
5293 01:32:26.033833 11, 0x0, sum = 2
5294 01:32:26.037321 12, 0x0, sum = 3
5295 01:32:26.037830 13, 0x0, sum = 4
5296 01:32:26.038162 best_step = 11
5297 01:32:26.038461
5298 01:32:26.039818 ==
5299 01:32:26.043448 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 01:32:26.046143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 01:32:26.046558 ==
5302 01:32:26.046882 RX Vref Scan: 1
5303 01:32:26.047182
5304 01:32:26.049936 RX Vref 0 -> 0, step: 1
5305 01:32:26.050348
5306 01:32:26.053303 RX Delay -61 -> 252, step: 4
5307 01:32:26.053819
5308 01:32:26.056671 Set Vref, RX VrefLevel [Byte0]: 56
5309 01:32:26.059964 [Byte1]: 50
5310 01:32:26.060474
5311 01:32:26.063229 Final RX Vref Byte 0 = 56 to rank0
5312 01:32:26.066022 Final RX Vref Byte 1 = 50 to rank0
5313 01:32:26.069453 Final RX Vref Byte 0 = 56 to rank1
5314 01:32:26.072793 Final RX Vref Byte 1 = 50 to rank1==
5315 01:32:26.075791 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 01:32:26.082467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 01:32:26.082922 ==
5318 01:32:26.083253 DQS Delay:
5319 01:32:26.085807 DQS0 = 0, DQS1 = 0
5320 01:32:26.086225 DQM Delay:
5321 01:32:26.086560 DQM0 = 98, DQM1 = 87
5322 01:32:26.089349 DQ Delay:
5323 01:32:26.092546 DQ0 =100, DQ1 =98, DQ2 =92, DQ3 =94
5324 01:32:26.096195 DQ4 =98, DQ5 =90, DQ6 =110, DQ7 =106
5325 01:32:26.099233 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5326 01:32:26.102522 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5327 01:32:26.103037
5328 01:32:26.103364
5329 01:32:26.109151 [DQSOSCAuto] RK0, (LSB)MR18= 0x1611, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5330 01:32:26.112636 CH0 RK0: MR19=505, MR18=1611
5331 01:32:26.118274 CH0_RK0: MR19=0x505, MR18=0x1611, DQSOSC=414, MR23=63, INC=63, DEC=42
5332 01:32:26.118815
5333 01:32:26.121893 ----->DramcWriteLeveling(PI) begin...
5334 01:32:26.122313 ==
5335 01:32:26.124874 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 01:32:26.128766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 01:32:26.129334 ==
5338 01:32:26.132199 Write leveling (Byte 0): 32 => 32
5339 01:32:26.135290 Write leveling (Byte 1): 28 => 28
5340 01:32:26.138703 DramcWriteLeveling(PI) end<-----
5341 01:32:26.139117
5342 01:32:26.139446 ==
5343 01:32:26.141463 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 01:32:26.147958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 01:32:26.148463 ==
5346 01:32:26.148790 [Gating] SW mode calibration
5347 01:32:26.158196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 01:32:26.161373 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 01:32:26.168328 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5350 01:32:26.171452 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 01:32:26.174597 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 01:32:26.181632 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 01:32:26.184343 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 01:32:26.188111 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 01:32:26.194787 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5356 01:32:26.197716 0 14 28 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
5357 01:32:26.200991 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5358 01:32:26.207460 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5359 01:32:26.210851 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 01:32:26.213945 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 01:32:26.220689 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 01:32:26.224168 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 01:32:26.227455 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 01:32:26.233668 0 15 28 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
5365 01:32:26.237321 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5366 01:32:26.240259 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 01:32:26.246680 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 01:32:26.250143 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 01:32:26.253581 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 01:32:26.260656 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 01:32:26.263308 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 01:32:26.267085 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5373 01:32:26.273507 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5374 01:32:26.276443 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 01:32:26.279864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 01:32:26.286232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 01:32:26.289751 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 01:32:26.293007 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 01:32:26.299591 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 01:32:26.302595 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 01:32:26.306165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 01:32:26.312568 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 01:32:26.316060 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 01:32:26.320358 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 01:32:26.325998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 01:32:26.329913 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 01:32:26.332794 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5388 01:32:26.339150 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5389 01:32:26.339702 Total UI for P1: 0, mck2ui 16
5390 01:32:26.346202 best dqsien dly found for B0: ( 1, 2, 24)
5391 01:32:26.349318 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5392 01:32:26.352745 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 01:32:26.355745 Total UI for P1: 0, mck2ui 16
5394 01:32:26.358880 best dqsien dly found for B1: ( 1, 3, 0)
5395 01:32:26.362223 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5396 01:32:26.365770 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5397 01:32:26.366326
5398 01:32:26.372130 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5399 01:32:26.375422 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5400 01:32:26.375880 [Gating] SW calibration Done
5401 01:32:26.378415 ==
5402 01:32:26.382214 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 01:32:26.385250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 01:32:26.385738 ==
5405 01:32:26.386094 RX Vref Scan: 0
5406 01:32:26.386425
5407 01:32:26.388500 RX Vref 0 -> 0, step: 1
5408 01:32:26.389008
5409 01:32:26.392711 RX Delay -80 -> 252, step: 8
5410 01:32:26.395020 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5411 01:32:26.398859 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5412 01:32:26.401788 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5413 01:32:26.408039 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5414 01:32:26.411454 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5415 01:32:26.414927 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5416 01:32:26.418092 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5417 01:32:26.421428 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5418 01:32:26.425023 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5419 01:32:26.431428 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5420 01:32:26.434528 iDelay=200, Bit 10, Center 87 (0 ~ 175) 176
5421 01:32:26.437534 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5422 01:32:26.441218 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5423 01:32:26.444652 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5424 01:32:26.451440 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5425 01:32:26.454207 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5426 01:32:26.454765 ==
5427 01:32:26.458108 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 01:32:26.460949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 01:32:26.461552 ==
5430 01:32:26.464182 DQS Delay:
5431 01:32:26.464740 DQS0 = 0, DQS1 = 0
5432 01:32:26.465103 DQM Delay:
5433 01:32:26.468098 DQM0 = 98, DQM1 = 88
5434 01:32:26.468648 DQ Delay:
5435 01:32:26.470686 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5436 01:32:26.474463 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5437 01:32:26.477308 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5438 01:32:26.480327 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5439 01:32:26.480791
5440 01:32:26.481145
5441 01:32:26.481501 ==
5442 01:32:26.483660 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 01:32:26.490924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 01:32:26.491478 ==
5445 01:32:26.491836
5446 01:32:26.492164
5447 01:32:26.492479 TX Vref Scan disable
5448 01:32:26.494241 == TX Byte 0 ==
5449 01:32:26.497516 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5450 01:32:26.504142 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5451 01:32:26.504697 == TX Byte 1 ==
5452 01:32:26.507609 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5453 01:32:26.514250 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5454 01:32:26.514823 ==
5455 01:32:26.517252 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 01:32:26.520601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 01:32:26.521162 ==
5458 01:32:26.521570
5459 01:32:26.521910
5460 01:32:26.524575 TX Vref Scan disable
5461 01:32:26.527568 == TX Byte 0 ==
5462 01:32:26.530174 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5463 01:32:26.533793 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5464 01:32:26.536878 == TX Byte 1 ==
5465 01:32:26.540425 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5466 01:32:26.544157 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5467 01:32:26.544711
5468 01:32:26.545077 [DATLAT]
5469 01:32:26.546784 Freq=933, CH0 RK1
5470 01:32:26.547244
5471 01:32:26.551169 DATLAT Default: 0xb
5472 01:32:26.551713 0, 0xFFFF, sum = 0
5473 01:32:26.553154 1, 0xFFFF, sum = 0
5474 01:32:26.553642 2, 0xFFFF, sum = 0
5475 01:32:26.556889 3, 0xFFFF, sum = 0
5476 01:32:26.557469 4, 0xFFFF, sum = 0
5477 01:32:26.560801 5, 0xFFFF, sum = 0
5478 01:32:26.561359 6, 0xFFFF, sum = 0
5479 01:32:26.563644 7, 0xFFFF, sum = 0
5480 01:32:26.564156 8, 0xFFFF, sum = 0
5481 01:32:26.567290 9, 0xFFFF, sum = 0
5482 01:32:26.567798 10, 0x0, sum = 1
5483 01:32:26.569939 11, 0x0, sum = 2
5484 01:32:26.570360 12, 0x0, sum = 3
5485 01:32:26.573477 13, 0x0, sum = 4
5486 01:32:26.573981 best_step = 11
5487 01:32:26.574312
5488 01:32:26.574619 ==
5489 01:32:26.576543 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 01:32:26.579970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 01:32:26.583362 ==
5492 01:32:26.583861 RX Vref Scan: 0
5493 01:32:26.584191
5494 01:32:26.586804 RX Vref 0 -> 0, step: 1
5495 01:32:26.587215
5496 01:32:26.590198 RX Delay -53 -> 252, step: 4
5497 01:32:26.592850 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5498 01:32:26.596470 iDelay=199, Bit 1, Center 100 (11 ~ 190) 180
5499 01:32:26.602845 iDelay=199, Bit 2, Center 94 (7 ~ 182) 176
5500 01:32:26.606261 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5501 01:32:26.609381 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5502 01:32:26.612805 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5503 01:32:26.616143 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5504 01:32:26.618938 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5505 01:32:26.625862 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5506 01:32:26.628871 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5507 01:32:26.632250 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5508 01:32:26.635574 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5509 01:32:26.638911 iDelay=199, Bit 12, Center 92 (7 ~ 178) 172
5510 01:32:26.645391 iDelay=199, Bit 13, Center 92 (7 ~ 178) 172
5511 01:32:26.648980 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5512 01:32:26.652584 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5513 01:32:26.653100 ==
5514 01:32:26.655444 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 01:32:26.658474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 01:32:26.658914 ==
5517 01:32:26.661817 DQS Delay:
5518 01:32:26.662240 DQS0 = 0, DQS1 = 0
5519 01:32:26.665178 DQM Delay:
5520 01:32:26.665759 DQM0 = 97, DQM1 = 87
5521 01:32:26.666200 DQ Delay:
5522 01:32:26.668759 DQ0 =96, DQ1 =100, DQ2 =94, DQ3 =94
5523 01:32:26.671665 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5524 01:32:26.674786 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5525 01:32:26.678617 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5526 01:32:26.681513
5527 01:32:26.681927
5528 01:32:26.688211 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5529 01:32:26.691271 CH0 RK1: MR19=505, MR18=1512
5530 01:32:26.697765 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5531 01:32:26.701198 [RxdqsGatingPostProcess] freq 933
5532 01:32:26.704675 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 01:32:26.708427 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 01:32:26.711001 best DQS1 dly(2T, 0.5T) = (0, 11)
5535 01:32:26.714589 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 01:32:26.718060 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5537 01:32:26.721295 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 01:32:26.725175 best DQS1 dly(2T, 0.5T) = (0, 11)
5539 01:32:26.727799 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 01:32:26.731820 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5541 01:32:26.734477 Pre-setting of DQS Precalculation
5542 01:32:26.737622 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 01:32:26.738156 ==
5544 01:32:26.740792 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 01:32:26.747154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 01:32:26.747570 ==
5547 01:32:26.750672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 01:32:26.757097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 01:32:26.760628 [CA 0] Center 36 (6~67) winsize 62
5550 01:32:26.764085 [CA 1] Center 36 (6~67) winsize 62
5551 01:32:26.767393 [CA 2] Center 34 (4~65) winsize 62
5552 01:32:26.770836 [CA 3] Center 34 (4~64) winsize 61
5553 01:32:26.773671 [CA 4] Center 34 (4~65) winsize 62
5554 01:32:26.777562 [CA 5] Center 33 (3~64) winsize 62
5555 01:32:26.777978
5556 01:32:26.780565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 01:32:26.781415
5558 01:32:26.783552 [CATrainingPosCal] consider 1 rank data
5559 01:32:26.787664 u2DelayCellTimex100 = 270/100 ps
5560 01:32:26.790800 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 01:32:26.797727 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 01:32:26.799877 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 01:32:26.803543 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 01:32:26.806797 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 01:32:26.810298 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 01:32:26.810715
5567 01:32:26.813166 CA PerBit enable=1, Macro0, CA PI delay=33
5568 01:32:26.813627
5569 01:32:26.817066 [CBTSetCACLKResult] CA Dly = 33
5570 01:32:26.819814 CS Dly: 4 (0~35)
5571 01:32:26.820226 ==
5572 01:32:26.823013 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 01:32:26.826944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 01:32:26.827514 ==
5575 01:32:26.832941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 01:32:26.840096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5577 01:32:26.843705 [CA 0] Center 36 (5~67) winsize 63
5578 01:32:26.846175 [CA 1] Center 36 (6~67) winsize 62
5579 01:32:26.849365 [CA 2] Center 34 (4~65) winsize 62
5580 01:32:26.852727 [CA 3] Center 33 (3~64) winsize 62
5581 01:32:26.856188 [CA 4] Center 34 (3~65) winsize 63
5582 01:32:26.860160 [CA 5] Center 33 (3~64) winsize 62
5583 01:32:26.860663
5584 01:32:26.862746 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5585 01:32:26.863250
5586 01:32:26.865762 [CATrainingPosCal] consider 2 rank data
5587 01:32:26.868882 u2DelayCellTimex100 = 270/100 ps
5588 01:32:26.872806 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 01:32:26.875644 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 01:32:26.878659 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5591 01:32:26.882190 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 01:32:26.885228 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5593 01:32:26.889955 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5594 01:32:26.890511
5595 01:32:26.895882 CA PerBit enable=1, Macro0, CA PI delay=33
5596 01:32:26.896288
5597 01:32:26.899332 [CBTSetCACLKResult] CA Dly = 33
5598 01:32:26.899834 CS Dly: 5 (0~38)
5599 01:32:26.900156
5600 01:32:26.902256 ----->DramcWriteLeveling(PI) begin...
5601 01:32:26.902691 ==
5602 01:32:26.905615 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 01:32:26.909227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 01:32:26.909787 ==
5605 01:32:26.911833 Write leveling (Byte 0): 27 => 27
5606 01:32:26.915253 Write leveling (Byte 1): 27 => 27
5607 01:32:26.918370 DramcWriteLeveling(PI) end<-----
5608 01:32:26.918803
5609 01:32:26.919128 ==
5610 01:32:26.921597 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 01:32:26.929050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 01:32:26.929628 ==
5613 01:32:26.929970 [Gating] SW mode calibration
5614 01:32:26.938159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 01:32:26.941700 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 01:32:26.948465 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5617 01:32:26.951596 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 01:32:26.954904 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 01:32:26.961498 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 01:32:26.964683 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 01:32:26.967776 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 01:32:26.974430 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5623 01:32:26.977840 0 14 28 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (1 0)
5624 01:32:26.980972 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 01:32:26.987427 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 01:32:26.990775 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 01:32:26.993996 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 01:32:27.000856 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 01:32:27.004248 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 01:32:27.007443 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 01:32:27.013949 0 15 28 | B1->B0 | 3737 3e3e | 0 1 | (0 0) (0 0)
5632 01:32:27.016682 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 01:32:27.020102 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 01:32:27.026856 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 01:32:27.030440 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 01:32:27.033334 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 01:32:27.040445 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 01:32:27.043177 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 01:32:27.046782 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 01:32:27.054115 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 01:32:27.056618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 01:32:27.059319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 01:32:27.066167 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 01:32:27.069856 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 01:32:27.073032 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 01:32:27.079134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 01:32:27.082386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 01:32:27.085880 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 01:32:27.093022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 01:32:27.096226 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 01:32:27.099478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 01:32:27.105329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 01:32:27.108709 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 01:32:27.111763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 01:32:27.118669 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5656 01:32:27.121694 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5657 01:32:27.125140 Total UI for P1: 0, mck2ui 16
5658 01:32:27.128536 best dqsien dly found for B0: ( 1, 2, 28)
5659 01:32:27.131904 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 01:32:27.135372 Total UI for P1: 0, mck2ui 16
5661 01:32:27.138105 best dqsien dly found for B1: ( 1, 2, 30)
5662 01:32:27.141423 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5663 01:32:27.148434 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5664 01:32:27.148939
5665 01:32:27.151653 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5666 01:32:27.154718 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5667 01:32:27.158191 [Gating] SW calibration Done
5668 01:32:27.158784 ==
5669 01:32:27.161196 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 01:32:27.165205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 01:32:27.165825 ==
5672 01:32:27.168201 RX Vref Scan: 0
5673 01:32:27.168747
5674 01:32:27.169107 RX Vref 0 -> 0, step: 1
5675 01:32:27.169506
5676 01:32:27.171237 RX Delay -80 -> 252, step: 8
5677 01:32:27.174596 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5678 01:32:27.180918 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5679 01:32:27.184712 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5680 01:32:27.188388 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5681 01:32:27.191453 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5682 01:32:27.194245 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5683 01:32:27.197876 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5684 01:32:27.204126 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5685 01:32:27.207249 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5686 01:32:27.210795 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5687 01:32:27.213773 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5688 01:32:27.217452 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5689 01:32:27.224048 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5690 01:32:27.226963 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5691 01:32:27.230588 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5692 01:32:27.234145 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5693 01:32:27.234574 ==
5694 01:32:27.237027 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 01:32:27.240489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 01:32:27.243692 ==
5697 01:32:27.244223 DQS Delay:
5698 01:32:27.244733 DQS0 = 0, DQS1 = 0
5699 01:32:27.247347 DQM Delay:
5700 01:32:27.247854 DQM0 = 100, DQM1 = 95
5701 01:32:27.250791 DQ Delay:
5702 01:32:27.253449 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5703 01:32:27.257320 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5704 01:32:27.260606 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5705 01:32:27.264237 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5706 01:32:27.264804
5707 01:32:27.265161
5708 01:32:27.265538 ==
5709 01:32:27.266882 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 01:32:27.270111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 01:32:27.270673 ==
5712 01:32:27.271036
5713 01:32:27.271362
5714 01:32:27.273747 TX Vref Scan disable
5715 01:32:27.276592 == TX Byte 0 ==
5716 01:32:27.279778 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5717 01:32:27.283069 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5718 01:32:27.286489 == TX Byte 1 ==
5719 01:32:27.289622 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5720 01:32:27.293474 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5721 01:32:27.293991 ==
5722 01:32:27.296751 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 01:32:27.299877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 01:32:27.303062 ==
5725 01:32:27.303503
5726 01:32:27.303822
5727 01:32:27.304121 TX Vref Scan disable
5728 01:32:27.306945 == TX Byte 0 ==
5729 01:32:27.310183 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5730 01:32:27.316886 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5731 01:32:27.317455 == TX Byte 1 ==
5732 01:32:27.319947 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5733 01:32:27.326391 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5734 01:32:27.326943
5735 01:32:27.327320 [DATLAT]
5736 01:32:27.327652 Freq=933, CH1 RK0
5737 01:32:27.327974
5738 01:32:27.329502 DATLAT Default: 0xd
5739 01:32:27.333355 0, 0xFFFF, sum = 0
5740 01:32:27.333870 1, 0xFFFF, sum = 0
5741 01:32:27.336178 2, 0xFFFF, sum = 0
5742 01:32:27.336590 3, 0xFFFF, sum = 0
5743 01:32:27.339638 4, 0xFFFF, sum = 0
5744 01:32:27.340156 5, 0xFFFF, sum = 0
5745 01:32:27.343041 6, 0xFFFF, sum = 0
5746 01:32:27.343736 7, 0xFFFF, sum = 0
5747 01:32:27.346225 8, 0xFFFF, sum = 0
5748 01:32:27.346639 9, 0xFFFF, sum = 0
5749 01:32:27.350020 10, 0x0, sum = 1
5750 01:32:27.350436 11, 0x0, sum = 2
5751 01:32:27.352878 12, 0x0, sum = 3
5752 01:32:27.353327 13, 0x0, sum = 4
5753 01:32:27.356085 best_step = 11
5754 01:32:27.356591
5755 01:32:27.356918 ==
5756 01:32:27.359291 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 01:32:27.362766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 01:32:27.363182 ==
5759 01:32:27.363510 RX Vref Scan: 1
5760 01:32:27.366538
5761 01:32:27.367015 RX Vref 0 -> 0, step: 1
5762 01:32:27.367347
5763 01:32:27.369418 RX Delay -53 -> 252, step: 4
5764 01:32:27.369919
5765 01:32:27.373938 Set Vref, RX VrefLevel [Byte0]: 52
5766 01:32:27.376094 [Byte1]: 47
5767 01:32:27.379055
5768 01:32:27.379468 Final RX Vref Byte 0 = 52 to rank0
5769 01:32:27.382770 Final RX Vref Byte 1 = 47 to rank0
5770 01:32:27.386021 Final RX Vref Byte 0 = 52 to rank1
5771 01:32:27.388984 Final RX Vref Byte 1 = 47 to rank1==
5772 01:32:27.392684 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 01:32:27.399173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 01:32:27.399676 ==
5775 01:32:27.400010 DQS Delay:
5776 01:32:27.402101 DQS0 = 0, DQS1 = 0
5777 01:32:27.402562 DQM Delay:
5778 01:32:27.402890 DQM0 = 98, DQM1 = 93
5779 01:32:27.405420 DQ Delay:
5780 01:32:27.409205 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =98
5781 01:32:27.412874 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5782 01:32:27.416438 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =88
5783 01:32:27.419351 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =100
5784 01:32:27.419773
5785 01:32:27.420099
5786 01:32:27.425703 [DQSOSCAuto] RK0, (LSB)MR18= 0x313, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 421 ps
5787 01:32:27.429039 CH1 RK0: MR19=505, MR18=313
5788 01:32:27.436338 CH1_RK0: MR19=0x505, MR18=0x313, DQSOSC=415, MR23=63, INC=62, DEC=41
5789 01:32:27.436761
5790 01:32:27.438531 ----->DramcWriteLeveling(PI) begin...
5791 01:32:27.438952 ==
5792 01:32:27.441984 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 01:32:27.445482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 01:32:27.445982 ==
5795 01:32:27.448804 Write leveling (Byte 0): 24 => 24
5796 01:32:27.452010 Write leveling (Byte 1): 28 => 28
5797 01:32:27.455665 DramcWriteLeveling(PI) end<-----
5798 01:32:27.456176
5799 01:32:27.456506 ==
5800 01:32:27.458555 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 01:32:27.465104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 01:32:27.465622 ==
5803 01:32:27.465948 [Gating] SW mode calibration
5804 01:32:27.474780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5805 01:32:27.478336 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5806 01:32:27.484719 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 01:32:27.488305 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 01:32:27.492008 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 01:32:27.494999 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 01:32:27.501398 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 01:32:27.504744 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 01:32:27.511199 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5813 01:32:27.514381 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5814 01:32:27.517682 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 01:32:27.524424 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 01:32:27.527887 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 01:32:27.531108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 01:32:27.538223 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 01:32:27.540500 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 01:32:27.543923 0 15 24 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (1 1)
5821 01:32:27.550175 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5822 01:32:27.553991 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 01:32:27.556904 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 01:32:27.563239 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 01:32:27.567358 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 01:32:27.569709 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 01:32:27.576829 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 01:32:27.580210 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 01:32:27.583343 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5830 01:32:27.589927 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5831 01:32:27.593028 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 01:32:27.596443 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 01:32:27.603365 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 01:32:27.606815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 01:32:27.609587 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 01:32:27.616066 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 01:32:27.619167 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 01:32:27.623344 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 01:32:27.629397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 01:32:27.632689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 01:32:27.636300 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 01:32:27.643039 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 01:32:27.645751 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 01:32:27.648866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 01:32:27.655819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5846 01:32:27.656286 Total UI for P1: 0, mck2ui 16
5847 01:32:27.662284 best dqsien dly found for B0: ( 1, 2, 26)
5848 01:32:27.665558 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 01:32:27.669138 Total UI for P1: 0, mck2ui 16
5850 01:32:27.671977 best dqsien dly found for B1: ( 1, 2, 28)
5851 01:32:27.675410 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5852 01:32:27.678487 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5853 01:32:27.678910
5854 01:32:27.682172 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5855 01:32:27.685199 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5856 01:32:27.688317 [Gating] SW calibration Done
5857 01:32:27.688738 ==
5858 01:32:27.691964 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 01:32:27.698283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 01:32:27.698712 ==
5861 01:32:27.699136 RX Vref Scan: 0
5862 01:32:27.699538
5863 01:32:27.701605 RX Vref 0 -> 0, step: 1
5864 01:32:27.702025
5865 01:32:27.705316 RX Delay -80 -> 252, step: 8
5866 01:32:27.708091 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5867 01:32:27.711654 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5868 01:32:27.714743 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5869 01:32:27.718455 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5870 01:32:27.725139 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5871 01:32:27.728019 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5872 01:32:27.731451 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5873 01:32:27.735053 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5874 01:32:27.737916 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5875 01:32:27.741465 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5876 01:32:27.748487 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5877 01:32:27.751319 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5878 01:32:27.754383 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5879 01:32:27.757712 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5880 01:32:27.761060 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5881 01:32:27.767548 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5882 01:32:27.768044 ==
5883 01:32:27.770817 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 01:32:27.773744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 01:32:27.774184 ==
5886 01:32:27.774617 DQS Delay:
5887 01:32:27.777609 DQS0 = 0, DQS1 = 0
5888 01:32:27.778132 DQM Delay:
5889 01:32:27.780306 DQM0 = 97, DQM1 = 94
5890 01:32:27.780729 DQ Delay:
5891 01:32:27.783848 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5892 01:32:27.787287 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5893 01:32:27.790460 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5894 01:32:27.793647 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5895 01:32:27.794124
5896 01:32:27.794454
5897 01:32:27.794755 ==
5898 01:32:27.796693 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 01:32:27.804049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 01:32:27.804579 ==
5901 01:32:27.804909
5902 01:32:27.805211
5903 01:32:27.805585 TX Vref Scan disable
5904 01:32:27.806670 == TX Byte 0 ==
5905 01:32:27.809989 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5906 01:32:27.816482 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5907 01:32:27.816989 == TX Byte 1 ==
5908 01:32:27.819968 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5909 01:32:27.826607 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5910 01:32:27.827128 ==
5911 01:32:27.829820 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 01:32:27.833063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 01:32:27.833618 ==
5914 01:32:27.834058
5915 01:32:27.834461
5916 01:32:27.836413 TX Vref Scan disable
5917 01:32:27.840529 == TX Byte 0 ==
5918 01:32:27.843182 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5919 01:32:27.847034 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5920 01:32:27.849709 == TX Byte 1 ==
5921 01:32:27.853181 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5922 01:32:27.856579 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5923 01:32:27.857041
5924 01:32:27.857499 [DATLAT]
5925 01:32:27.859718 Freq=933, CH1 RK1
5926 01:32:27.860140
5927 01:32:27.862767 DATLAT Default: 0xb
5928 01:32:27.863298 0, 0xFFFF, sum = 0
5929 01:32:27.866616 1, 0xFFFF, sum = 0
5930 01:32:27.867052 2, 0xFFFF, sum = 0
5931 01:32:27.869246 3, 0xFFFF, sum = 0
5932 01:32:27.869710 4, 0xFFFF, sum = 0
5933 01:32:27.872452 5, 0xFFFF, sum = 0
5934 01:32:27.872881 6, 0xFFFF, sum = 0
5935 01:32:27.875957 7, 0xFFFF, sum = 0
5936 01:32:27.876478 8, 0xFFFF, sum = 0
5937 01:32:27.879363 9, 0xFFFF, sum = 0
5938 01:32:27.879791 10, 0x0, sum = 1
5939 01:32:27.882338 11, 0x0, sum = 2
5940 01:32:27.882784 12, 0x0, sum = 3
5941 01:32:27.885615 13, 0x0, sum = 4
5942 01:32:27.886047 best_step = 11
5943 01:32:27.886475
5944 01:32:27.886870 ==
5945 01:32:27.888862 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 01:32:27.896636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 01:32:27.897064 ==
5948 01:32:27.897514 RX Vref Scan: 0
5949 01:32:27.897920
5950 01:32:27.898946 RX Vref 0 -> 0, step: 1
5951 01:32:27.899368
5952 01:32:27.901779 RX Delay -53 -> 252, step: 4
5953 01:32:27.905099 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5954 01:32:27.908324 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5955 01:32:27.914921 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5956 01:32:27.918453 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5957 01:32:27.921595 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5958 01:32:27.924912 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5959 01:32:27.928082 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5960 01:32:27.934956 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5961 01:32:27.938380 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5962 01:32:27.941041 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5963 01:32:27.944859 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5964 01:32:27.948506 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5965 01:32:27.954480 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5966 01:32:27.957791 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5967 01:32:27.961636 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5968 01:32:27.964550 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5969 01:32:27.964977 ==
5970 01:32:27.967952 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 01:32:27.974178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 01:32:27.974647 ==
5973 01:32:27.975249 DQS Delay:
5974 01:32:27.975662 DQS0 = 0, DQS1 = 0
5975 01:32:27.977798 DQM Delay:
5976 01:32:27.978219 DQM0 = 96, DQM1 = 92
5977 01:32:27.980691 DQ Delay:
5978 01:32:27.984225 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5979 01:32:27.987884 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5980 01:32:27.990758 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
5981 01:32:27.993945 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5982 01:32:27.994368
5983 01:32:27.994789
5984 01:32:28.000750 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5985 01:32:28.004063 CH1 RK1: MR19=505, MR18=B22
5986 01:32:28.010497 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5987 01:32:28.014150 [RxdqsGatingPostProcess] freq 933
5988 01:32:28.016717 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5989 01:32:28.020996 best DQS0 dly(2T, 0.5T) = (0, 10)
5990 01:32:28.023971 best DQS1 dly(2T, 0.5T) = (0, 10)
5991 01:32:28.027074 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5992 01:32:28.030207 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5993 01:32:28.033219 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 01:32:28.036644 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 01:32:28.040019 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 01:32:28.043443 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 01:32:28.046409 Pre-setting of DQS Precalculation
5998 01:32:28.053188 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5999 01:32:28.059711 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6000 01:32:28.066393 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6001 01:32:28.066927
6002 01:32:28.067266
6003 01:32:28.069640 [Calibration Summary] 1866 Mbps
6004 01:32:28.070103 CH 0, Rank 0
6005 01:32:28.072933 SW Impedance : PASS
6006 01:32:28.076060 DUTY Scan : NO K
6007 01:32:28.076495 ZQ Calibration : PASS
6008 01:32:28.079577 Jitter Meter : NO K
6009 01:32:28.082744 CBT Training : PASS
6010 01:32:28.083277 Write leveling : PASS
6011 01:32:28.086321 RX DQS gating : PASS
6012 01:32:28.089120 RX DQ/DQS(RDDQC) : PASS
6013 01:32:28.089582 TX DQ/DQS : PASS
6014 01:32:28.093178 RX DATLAT : PASS
6015 01:32:28.093643 RX DQ/DQS(Engine): PASS
6016 01:32:28.096114 TX OE : NO K
6017 01:32:28.096543 All Pass.
6018 01:32:28.096975
6019 01:32:28.099287 CH 0, Rank 1
6020 01:32:28.099767 SW Impedance : PASS
6021 01:32:28.102560 DUTY Scan : NO K
6022 01:32:28.105768 ZQ Calibration : PASS
6023 01:32:28.106190 Jitter Meter : NO K
6024 01:32:28.109481 CBT Training : PASS
6025 01:32:28.112313 Write leveling : PASS
6026 01:32:28.112739 RX DQS gating : PASS
6027 01:32:28.116057 RX DQ/DQS(RDDQC) : PASS
6028 01:32:28.119283 TX DQ/DQS : PASS
6029 01:32:28.119707 RX DATLAT : PASS
6030 01:32:28.122108 RX DQ/DQS(Engine): PASS
6031 01:32:28.125330 TX OE : NO K
6032 01:32:28.125758 All Pass.
6033 01:32:28.126180
6034 01:32:28.126760 CH 1, Rank 0
6035 01:32:28.128942 SW Impedance : PASS
6036 01:32:28.132226 DUTY Scan : NO K
6037 01:32:28.132648 ZQ Calibration : PASS
6038 01:32:28.135431 Jitter Meter : NO K
6039 01:32:28.138803 CBT Training : PASS
6040 01:32:28.139212 Write leveling : PASS
6041 01:32:28.142255 RX DQS gating : PASS
6042 01:32:28.145524 RX DQ/DQS(RDDQC) : PASS
6043 01:32:28.145930 TX DQ/DQS : PASS
6044 01:32:28.148563 RX DATLAT : PASS
6045 01:32:28.151981 RX DQ/DQS(Engine): PASS
6046 01:32:28.152389 TX OE : NO K
6047 01:32:28.155195 All Pass.
6048 01:32:28.155663
6049 01:32:28.155986 CH 1, Rank 1
6050 01:32:28.158721 SW Impedance : PASS
6051 01:32:28.159131 DUTY Scan : NO K
6052 01:32:28.161687 ZQ Calibration : PASS
6053 01:32:28.165016 Jitter Meter : NO K
6054 01:32:28.165571 CBT Training : PASS
6055 01:32:28.168378 Write leveling : PASS
6056 01:32:28.171719 RX DQS gating : PASS
6057 01:32:28.172248 RX DQ/DQS(RDDQC) : PASS
6058 01:32:28.175360 TX DQ/DQS : PASS
6059 01:32:28.178180 RX DATLAT : PASS
6060 01:32:28.178590 RX DQ/DQS(Engine): PASS
6061 01:32:28.181737 TX OE : NO K
6062 01:32:28.182152 All Pass.
6063 01:32:28.182477
6064 01:32:28.184741 DramC Write-DBI off
6065 01:32:28.187967 PER_BANK_REFRESH: Hybrid Mode
6066 01:32:28.188377 TX_TRACKING: ON
6067 01:32:28.198017 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6068 01:32:28.201171 [FAST_K] Save calibration result to emmc
6069 01:32:28.205107 dramc_set_vcore_voltage set vcore to 650000
6070 01:32:28.207626 Read voltage for 400, 6
6071 01:32:28.208034 Vio18 = 0
6072 01:32:28.208356 Vcore = 650000
6073 01:32:28.211381 Vdram = 0
6074 01:32:28.211908 Vddq = 0
6075 01:32:28.212246 Vmddr = 0
6076 01:32:28.217768 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6077 01:32:28.221043 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6078 01:32:28.224734 MEM_TYPE=3, freq_sel=20
6079 01:32:28.227488 sv_algorithm_assistance_LP4_800
6080 01:32:28.231185 ============ PULL DRAM RESETB DOWN ============
6081 01:32:28.234273 ========== PULL DRAM RESETB DOWN end =========
6082 01:32:28.241123 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6083 01:32:28.244517 ===================================
6084 01:32:28.247702 LPDDR4 DRAM CONFIGURATION
6085 01:32:28.250779 ===================================
6086 01:32:28.251204 EX_ROW_EN[0] = 0x0
6087 01:32:28.253723 EX_ROW_EN[1] = 0x0
6088 01:32:28.254163 LP4Y_EN = 0x0
6089 01:32:28.256836 WORK_FSP = 0x0
6090 01:32:28.257284 WL = 0x2
6091 01:32:28.260430 RL = 0x2
6092 01:32:28.260850 BL = 0x2
6093 01:32:28.264249 RPST = 0x0
6094 01:32:28.264671 RD_PRE = 0x0
6095 01:32:28.267005 WR_PRE = 0x1
6096 01:32:28.267427 WR_PST = 0x0
6097 01:32:28.270680 DBI_WR = 0x0
6098 01:32:28.271201 DBI_RD = 0x0
6099 01:32:28.273367 OTF = 0x1
6100 01:32:28.277159 ===================================
6101 01:32:28.280380 ===================================
6102 01:32:28.280805 ANA top config
6103 01:32:28.283396 ===================================
6104 01:32:28.286862 DLL_ASYNC_EN = 0
6105 01:32:28.290302 ALL_SLAVE_EN = 1
6106 01:32:28.293694 NEW_RANK_MODE = 1
6107 01:32:28.296985 DLL_IDLE_MODE = 1
6108 01:32:28.297435 LP45_APHY_COMB_EN = 1
6109 01:32:28.299880 TX_ODT_DIS = 1
6110 01:32:28.303080 NEW_8X_MODE = 1
6111 01:32:28.306543 ===================================
6112 01:32:28.309399 ===================================
6113 01:32:28.313032 data_rate = 800
6114 01:32:28.316360 CKR = 1
6115 01:32:28.319850 DQ_P2S_RATIO = 4
6116 01:32:28.322789 ===================================
6117 01:32:28.323218 CA_P2S_RATIO = 4
6118 01:32:28.325990 DQ_CA_OPEN = 0
6119 01:32:28.329454 DQ_SEMI_OPEN = 1
6120 01:32:28.332550 CA_SEMI_OPEN = 1
6121 01:32:28.335576 CA_FULL_RATE = 0
6122 01:32:28.338975 DQ_CKDIV4_EN = 0
6123 01:32:28.339384 CA_CKDIV4_EN = 1
6124 01:32:28.342595 CA_PREDIV_EN = 0
6125 01:32:28.346761 PH8_DLY = 0
6126 01:32:28.349335 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6127 01:32:28.352044 DQ_AAMCK_DIV = 0
6128 01:32:28.356069 CA_AAMCK_DIV = 0
6129 01:32:28.356477 CA_ADMCK_DIV = 4
6130 01:32:28.359025 DQ_TRACK_CA_EN = 0
6131 01:32:28.362228 CA_PICK = 800
6132 01:32:28.365523 CA_MCKIO = 400
6133 01:32:28.368543 MCKIO_SEMI = 400
6134 01:32:28.372386 PLL_FREQ = 3016
6135 01:32:28.375654 DQ_UI_PI_RATIO = 32
6136 01:32:28.378568 CA_UI_PI_RATIO = 32
6137 01:32:28.381907 ===================================
6138 01:32:28.385681 ===================================
6139 01:32:28.386091 memory_type:LPDDR4
6140 01:32:28.388989 GP_NUM : 10
6141 01:32:28.392027 SRAM_EN : 1
6142 01:32:28.392440 MD32_EN : 0
6143 01:32:28.395488 ===================================
6144 01:32:28.399069 [ANA_INIT] >>>>>>>>>>>>>>
6145 01:32:28.401972 <<<<<< [CONFIGURE PHASE]: ANA_TX
6146 01:32:28.405691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6147 01:32:28.408282 ===================================
6148 01:32:28.411812 data_rate = 800,PCW = 0X7400
6149 01:32:28.415098 ===================================
6150 01:32:28.418274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6151 01:32:28.421735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6152 01:32:28.435112 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 01:32:28.438061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6154 01:32:28.441238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6155 01:32:28.445126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6156 01:32:28.448003 [ANA_INIT] flow start
6157 01:32:28.450924 [ANA_INIT] PLL >>>>>>>>
6158 01:32:28.451381 [ANA_INIT] PLL <<<<<<<<
6159 01:32:28.454875 [ANA_INIT] MIDPI >>>>>>>>
6160 01:32:28.457767 [ANA_INIT] MIDPI <<<<<<<<
6161 01:32:28.458177 [ANA_INIT] DLL >>>>>>>>
6162 01:32:28.461630 [ANA_INIT] flow end
6163 01:32:28.464137 ============ LP4 DIFF to SE enter ============
6164 01:32:28.471255 ============ LP4 DIFF to SE exit ============
6165 01:32:28.471780 [ANA_INIT] <<<<<<<<<<<<<
6166 01:32:28.474517 [Flow] Enable top DCM control >>>>>
6167 01:32:28.477534 [Flow] Enable top DCM control <<<<<
6168 01:32:28.480887 Enable DLL master slave shuffle
6169 01:32:28.487621 ==============================================================
6170 01:32:28.488131 Gating Mode config
6171 01:32:28.493796 ==============================================================
6172 01:32:28.497498 Config description:
6173 01:32:28.506759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6174 01:32:28.513161 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6175 01:32:28.516483 SELPH_MODE 0: By rank 1: By Phase
6176 01:32:28.523011 ==============================================================
6177 01:32:28.526723 GAT_TRACK_EN = 0
6178 01:32:28.529761 RX_GATING_MODE = 2
6179 01:32:28.533114 RX_GATING_TRACK_MODE = 2
6180 01:32:28.533561 SELPH_MODE = 1
6181 01:32:28.536644 PICG_EARLY_EN = 1
6182 01:32:28.539570 VALID_LAT_VALUE = 1
6183 01:32:28.546066 ==============================================================
6184 01:32:28.549367 Enter into Gating configuration >>>>
6185 01:32:28.552835 Exit from Gating configuration <<<<
6186 01:32:28.556053 Enter into DVFS_PRE_config >>>>>
6187 01:32:28.566024 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6188 01:32:28.568978 Exit from DVFS_PRE_config <<<<<
6189 01:32:28.573027 Enter into PICG configuration >>>>
6190 01:32:28.575789 Exit from PICG configuration <<<<
6191 01:32:28.579143 [RX_INPUT] configuration >>>>>
6192 01:32:28.582836 [RX_INPUT] configuration <<<<<
6193 01:32:28.585650 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6194 01:32:28.592300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6195 01:32:28.598795 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 01:32:28.605240 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 01:32:28.612283 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6198 01:32:28.618397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6199 01:32:28.621535 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6200 01:32:28.625635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6201 01:32:28.629096 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6202 01:32:28.635333 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6203 01:32:28.638354 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6204 01:32:28.641804 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 01:32:28.645056 ===================================
6206 01:32:28.648627 LPDDR4 DRAM CONFIGURATION
6207 01:32:28.651456 ===================================
6208 01:32:28.651967 EX_ROW_EN[0] = 0x0
6209 01:32:28.654788 EX_ROW_EN[1] = 0x0
6210 01:32:28.658087 LP4Y_EN = 0x0
6211 01:32:28.658636 WORK_FSP = 0x0
6212 01:32:28.661786 WL = 0x2
6213 01:32:28.662313 RL = 0x2
6214 01:32:28.665235 BL = 0x2
6215 01:32:28.665785 RPST = 0x0
6216 01:32:28.668449 RD_PRE = 0x0
6217 01:32:28.668969 WR_PRE = 0x1
6218 01:32:28.671047 WR_PST = 0x0
6219 01:32:28.671457 DBI_WR = 0x0
6220 01:32:28.674517 DBI_RD = 0x0
6221 01:32:28.675020 OTF = 0x1
6222 01:32:28.677960 ===================================
6223 01:32:28.684691 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6224 01:32:28.687663 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6225 01:32:28.691567 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6226 01:32:28.694683 ===================================
6227 01:32:28.697944 LPDDR4 DRAM CONFIGURATION
6228 01:32:28.701020 ===================================
6229 01:32:28.704040 EX_ROW_EN[0] = 0x10
6230 01:32:28.704489 EX_ROW_EN[1] = 0x0
6231 01:32:28.707537 LP4Y_EN = 0x0
6232 01:32:28.708080 WORK_FSP = 0x0
6233 01:32:28.711007 WL = 0x2
6234 01:32:28.711585 RL = 0x2
6235 01:32:28.714001 BL = 0x2
6236 01:32:28.714467 RPST = 0x0
6237 01:32:28.717525 RD_PRE = 0x0
6238 01:32:28.718084 WR_PRE = 0x1
6239 01:32:28.720781 WR_PST = 0x0
6240 01:32:28.721335 DBI_WR = 0x0
6241 01:32:28.723708 DBI_RD = 0x0
6242 01:32:28.724174 OTF = 0x1
6243 01:32:28.727411 ===================================
6244 01:32:28.734656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6245 01:32:28.739116 nWR fixed to 30
6246 01:32:28.742212 [ModeRegInit_LP4] CH0 RK0
6247 01:32:28.742786 [ModeRegInit_LP4] CH0 RK1
6248 01:32:28.745401 [ModeRegInit_LP4] CH1 RK0
6249 01:32:28.748675 [ModeRegInit_LP4] CH1 RK1
6250 01:32:28.749216 match AC timing 19
6251 01:32:28.755155 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6252 01:32:28.758069 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6253 01:32:28.761825 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6254 01:32:28.768406 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6255 01:32:28.771845 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6256 01:32:28.772403 ==
6257 01:32:28.774398 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 01:32:28.777753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 01:32:28.781315 ==
6260 01:32:28.784339 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 01:32:28.791190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 01:32:28.794436 [CA 0] Center 36 (8~64) winsize 57
6263 01:32:28.797457 [CA 1] Center 36 (8~64) winsize 57
6264 01:32:28.801029 [CA 2] Center 36 (8~64) winsize 57
6265 01:32:28.804368 [CA 3] Center 36 (8~64) winsize 57
6266 01:32:28.807560 [CA 4] Center 36 (8~64) winsize 57
6267 01:32:28.810777 [CA 5] Center 36 (8~64) winsize 57
6268 01:32:28.811333
6269 01:32:28.814562 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 01:32:28.815306
6271 01:32:28.817119 [CATrainingPosCal] consider 1 rank data
6272 01:32:28.820628 u2DelayCellTimex100 = 270/100 ps
6273 01:32:28.824360 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 01:32:28.827349 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 01:32:28.830498 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 01:32:28.834033 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 01:32:28.837227 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 01:32:28.840331 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 01:32:28.843224
6280 01:32:28.846898 CA PerBit enable=1, Macro0, CA PI delay=36
6281 01:32:28.847445
6282 01:32:28.850460 [CBTSetCACLKResult] CA Dly = 36
6283 01:32:28.851007 CS Dly: 1 (0~32)
6284 01:32:28.851367 ==
6285 01:32:28.853341 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 01:32:28.857163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 01:32:28.857755 ==
6288 01:32:28.863202 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 01:32:28.869879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6290 01:32:28.873368 [CA 0] Center 36 (8~64) winsize 57
6291 01:32:28.876799 [CA 1] Center 36 (8~64) winsize 57
6292 01:32:28.880128 [CA 2] Center 36 (8~64) winsize 57
6293 01:32:28.883312 [CA 3] Center 36 (8~64) winsize 57
6294 01:32:28.886428 [CA 4] Center 36 (8~64) winsize 57
6295 01:32:28.889505 [CA 5] Center 36 (8~64) winsize 57
6296 01:32:28.889978
6297 01:32:28.893149 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6298 01:32:28.893721
6299 01:32:28.896246 [CATrainingPosCal] consider 2 rank data
6300 01:32:28.900320 u2DelayCellTimex100 = 270/100 ps
6301 01:32:28.902894 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 01:32:28.906950 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 01:32:28.909502 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 01:32:28.913042 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 01:32:28.916505 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 01:32:28.919383 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 01:32:28.919891
6308 01:32:28.925985 CA PerBit enable=1, Macro0, CA PI delay=36
6309 01:32:28.926398
6310 01:32:28.926721 [CBTSetCACLKResult] CA Dly = 36
6311 01:32:28.928995 CS Dly: 1 (0~32)
6312 01:32:28.929443
6313 01:32:28.932921 ----->DramcWriteLeveling(PI) begin...
6314 01:32:28.933492 ==
6315 01:32:28.936116 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 01:32:28.938935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 01:32:28.939350 ==
6318 01:32:28.942344 Write leveling (Byte 0): 40 => 8
6319 01:32:28.945817 Write leveling (Byte 1): 40 => 8
6320 01:32:28.949524 DramcWriteLeveling(PI) end<-----
6321 01:32:28.950025
6322 01:32:28.950352 ==
6323 01:32:28.952568 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 01:32:28.955711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 01:32:28.958867 ==
6326 01:32:28.959369 [Gating] SW mode calibration
6327 01:32:28.968876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6328 01:32:28.971859 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6329 01:32:28.975512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6330 01:32:28.982613 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 01:32:28.985301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 01:32:28.988454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 01:32:28.995148 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 01:32:28.998500 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 01:32:29.001560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 01:32:29.008460 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 01:32:29.011905 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 01:32:29.015059 Total UI for P1: 0, mck2ui 16
6339 01:32:29.017923 best dqsien dly found for B0: ( 0, 14, 24)
6340 01:32:29.021324 Total UI for P1: 0, mck2ui 16
6341 01:32:29.024949 best dqsien dly found for B1: ( 0, 14, 24)
6342 01:32:29.028208 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6343 01:32:29.031378 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6344 01:32:29.031836
6345 01:32:29.034741 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6346 01:32:29.041399 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 01:32:29.041812 [Gating] SW calibration Done
6348 01:32:29.042138 ==
6349 01:32:29.044225 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 01:32:29.051389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 01:32:29.051892 ==
6352 01:32:29.052220 RX Vref Scan: 0
6353 01:32:29.052515
6354 01:32:29.054448 RX Vref 0 -> 0, step: 1
6355 01:32:29.054968
6356 01:32:29.057656 RX Delay -410 -> 252, step: 16
6357 01:32:29.060963 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6358 01:32:29.064988 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6359 01:32:29.071394 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6360 01:32:29.074245 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6361 01:32:29.077288 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6362 01:32:29.080503 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6363 01:32:29.087739 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6364 01:32:29.090692 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6365 01:32:29.093736 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6366 01:32:29.097539 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6367 01:32:29.103856 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6368 01:32:29.106868 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6369 01:32:29.110445 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6370 01:32:29.116975 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6371 01:32:29.120545 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6372 01:32:29.123684 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6373 01:32:29.124098 ==
6374 01:32:29.126616 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 01:32:29.133721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 01:32:29.134135 ==
6377 01:32:29.134462 DQS Delay:
6378 01:32:29.137109 DQS0 = 35, DQS1 = 59
6379 01:32:29.137558 DQM Delay:
6380 01:32:29.137883 DQM0 = 4, DQM1 = 17
6381 01:32:29.139850 DQ Delay:
6382 01:32:29.143592 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6383 01:32:29.144132 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6384 01:32:29.146472 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6385 01:32:29.149576 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6386 01:32:29.149997
6387 01:32:29.150323
6388 01:32:29.153399 ==
6389 01:32:29.156621 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 01:32:29.159967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 01:32:29.160478 ==
6392 01:32:29.160805
6393 01:32:29.161104
6394 01:32:29.162659 TX Vref Scan disable
6395 01:32:29.163067 == TX Byte 0 ==
6396 01:32:29.166448 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 01:32:29.173416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 01:32:29.173924 == TX Byte 1 ==
6399 01:32:29.176364 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 01:32:29.182884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 01:32:29.183398 ==
6402 01:32:29.186582 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 01:32:29.189668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 01:32:29.190183 ==
6405 01:32:29.190511
6406 01:32:29.190808
6407 01:32:29.192740 TX Vref Scan disable
6408 01:32:29.193249 == TX Byte 0 ==
6409 01:32:29.199619 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 01:32:29.202123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 01:32:29.202541 == TX Byte 1 ==
6412 01:32:29.209324 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 01:32:29.212694 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 01:32:29.213201
6415 01:32:29.213591 [DATLAT]
6416 01:32:29.215562 Freq=400, CH0 RK0
6417 01:32:29.216078
6418 01:32:29.216442 DATLAT Default: 0xf
6419 01:32:29.218964 0, 0xFFFF, sum = 0
6420 01:32:29.219484 1, 0xFFFF, sum = 0
6421 01:32:29.222042 2, 0xFFFF, sum = 0
6422 01:32:29.222625 3, 0xFFFF, sum = 0
6423 01:32:29.225470 4, 0xFFFF, sum = 0
6424 01:32:29.225883 5, 0xFFFF, sum = 0
6425 01:32:29.229096 6, 0xFFFF, sum = 0
6426 01:32:29.229541 7, 0xFFFF, sum = 0
6427 01:32:29.232193 8, 0xFFFF, sum = 0
6428 01:32:29.232702 9, 0xFFFF, sum = 0
6429 01:32:29.235618 10, 0xFFFF, sum = 0
6430 01:32:29.238767 11, 0xFFFF, sum = 0
6431 01:32:29.239187 12, 0xFFFF, sum = 0
6432 01:32:29.242236 13, 0x0, sum = 1
6433 01:32:29.242694 14, 0x0, sum = 2
6434 01:32:29.243055 15, 0x0, sum = 3
6435 01:32:29.245287 16, 0x0, sum = 4
6436 01:32:29.245895 best_step = 14
6437 01:32:29.246446
6438 01:32:29.248873 ==
6439 01:32:29.249421 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 01:32:29.255204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 01:32:29.255695 ==
6442 01:32:29.256049 RX Vref Scan: 1
6443 01:32:29.256505
6444 01:32:29.259263 RX Vref 0 -> 0, step: 1
6445 01:32:29.259780
6446 01:32:29.261532 RX Delay -359 -> 252, step: 8
6447 01:32:29.262120
6448 01:32:29.265169 Set Vref, RX VrefLevel [Byte0]: 56
6449 01:32:29.267926 [Byte1]: 50
6450 01:32:29.271979
6451 01:32:29.272635 Final RX Vref Byte 0 = 56 to rank0
6452 01:32:29.275372 Final RX Vref Byte 1 = 50 to rank0
6453 01:32:29.278719 Final RX Vref Byte 0 = 56 to rank1
6454 01:32:29.281535 Final RX Vref Byte 1 = 50 to rank1==
6455 01:32:29.284995 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 01:32:29.291785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 01:32:29.292325 ==
6458 01:32:29.292791 DQS Delay:
6459 01:32:29.295354 DQS0 = 44, DQS1 = 60
6460 01:32:29.295851 DQM Delay:
6461 01:32:29.296175 DQM0 = 11, DQM1 = 17
6462 01:32:29.298312 DQ Delay:
6463 01:32:29.301846 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6464 01:32:29.304828 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6465 01:32:29.305530 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6466 01:32:29.311661 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6467 01:32:29.312070
6468 01:32:29.312386
6469 01:32:29.318122 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6470 01:32:29.321507 CH0 RK0: MR19=C0C, MR18=8C7F
6471 01:32:29.328125 CH0_RK0: MR19=0xC0C, MR18=0x8C7F, DQSOSC=392, MR23=63, INC=384, DEC=256
6472 01:32:29.328560 ==
6473 01:32:29.331347 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 01:32:29.335233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 01:32:29.335738 ==
6476 01:32:29.337619 [Gating] SW mode calibration
6477 01:32:29.344261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6478 01:32:29.351033 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6479 01:32:29.354555 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6480 01:32:29.357706 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 01:32:29.364258 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 01:32:29.368032 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 01:32:29.370576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 01:32:29.377494 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 01:32:29.381066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 01:32:29.383769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 01:32:29.390417 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 01:32:29.393752 Total UI for P1: 0, mck2ui 16
6489 01:32:29.397696 best dqsien dly found for B0: ( 0, 14, 24)
6490 01:32:29.400244 Total UI for P1: 0, mck2ui 16
6491 01:32:29.404054 best dqsien dly found for B1: ( 0, 14, 24)
6492 01:32:29.407551 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6493 01:32:29.410221 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6494 01:32:29.410720
6495 01:32:29.413471 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6496 01:32:29.416821 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 01:32:29.420056 [Gating] SW calibration Done
6498 01:32:29.420592 ==
6499 01:32:29.423379 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 01:32:29.427549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 01:32:29.428060 ==
6502 01:32:29.430510 RX Vref Scan: 0
6503 01:32:29.430919
6504 01:32:29.433336 RX Vref 0 -> 0, step: 1
6505 01:32:29.433748
6506 01:32:29.434071 RX Delay -410 -> 252, step: 16
6507 01:32:29.440656 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6508 01:32:29.444067 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6509 01:32:29.447170 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6510 01:32:29.450403 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6511 01:32:29.456786 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6512 01:32:29.459904 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6513 01:32:29.463268 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6514 01:32:29.469903 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6515 01:32:29.473107 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6516 01:32:29.476981 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6517 01:32:29.479938 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6518 01:32:29.486092 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6519 01:32:29.489735 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6520 01:32:29.493482 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6521 01:32:29.496446 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6522 01:32:29.502829 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6523 01:32:29.503335 ==
6524 01:32:29.506073 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 01:32:29.509659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 01:32:29.510164 ==
6527 01:32:29.510494 DQS Delay:
6528 01:32:29.512912 DQS0 = 35, DQS1 = 59
6529 01:32:29.513449 DQM Delay:
6530 01:32:29.516363 DQM0 = 5, DQM1 = 17
6531 01:32:29.516865 DQ Delay:
6532 01:32:29.519319 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6533 01:32:29.522494 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6534 01:32:29.525782 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6535 01:32:29.529451 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6536 01:32:29.529962
6537 01:32:29.530305
6538 01:32:29.530626 ==
6539 01:32:29.532508 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 01:32:29.536537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 01:32:29.537045 ==
6542 01:32:29.537408
6543 01:32:29.539708
6544 01:32:29.540251 TX Vref Scan disable
6545 01:32:29.542319 == TX Byte 0 ==
6546 01:32:29.545781 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6547 01:32:29.548973 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6548 01:32:29.552360 == TX Byte 1 ==
6549 01:32:29.556273 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6550 01:32:29.558997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6551 01:32:29.559543 ==
6552 01:32:29.562183 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 01:32:29.565531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 01:32:29.569020 ==
6555 01:32:29.569610
6556 01:32:29.569968
6557 01:32:29.570299 TX Vref Scan disable
6558 01:32:29.572340 == TX Byte 0 ==
6559 01:32:29.575234 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6560 01:32:29.578678 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6561 01:32:29.582077 == TX Byte 1 ==
6562 01:32:29.585175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6563 01:32:29.588353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6564 01:32:29.588775
6565 01:32:29.591882 [DATLAT]
6566 01:32:29.592434 Freq=400, CH0 RK1
6567 01:32:29.592770
6568 01:32:29.595336 DATLAT Default: 0xe
6569 01:32:29.595832 0, 0xFFFF, sum = 0
6570 01:32:29.598342 1, 0xFFFF, sum = 0
6571 01:32:29.598759 2, 0xFFFF, sum = 0
6572 01:32:29.601486 3, 0xFFFF, sum = 0
6573 01:32:29.601901 4, 0xFFFF, sum = 0
6574 01:32:29.605071 5, 0xFFFF, sum = 0
6575 01:32:29.605523 6, 0xFFFF, sum = 0
6576 01:32:29.607808 7, 0xFFFF, sum = 0
6577 01:32:29.608228 8, 0xFFFF, sum = 0
6578 01:32:29.611753 9, 0xFFFF, sum = 0
6579 01:32:29.612264 10, 0xFFFF, sum = 0
6580 01:32:29.614790 11, 0xFFFF, sum = 0
6581 01:32:29.617870 12, 0xFFFF, sum = 0
6582 01:32:29.618293 13, 0x0, sum = 1
6583 01:32:29.621689 14, 0x0, sum = 2
6584 01:32:29.622175 15, 0x0, sum = 3
6585 01:32:29.622512 16, 0x0, sum = 4
6586 01:32:29.624545 best_step = 14
6587 01:32:29.624955
6588 01:32:29.625315 ==
6589 01:32:29.628437 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 01:32:29.631251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 01:32:29.631759 ==
6592 01:32:29.634383 RX Vref Scan: 0
6593 01:32:29.634795
6594 01:32:29.635121 RX Vref 0 -> 0, step: 1
6595 01:32:29.637848
6596 01:32:29.638256 RX Delay -359 -> 252, step: 8
6597 01:32:29.646809 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6598 01:32:29.649896 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6599 01:32:29.653216 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6600 01:32:29.659547 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6601 01:32:29.662856 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6602 01:32:29.666759 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6603 01:32:29.669477 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6604 01:32:29.676137 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6605 01:32:29.679540 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6606 01:32:29.682420 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6607 01:32:29.686273 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6608 01:32:29.692506 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6609 01:32:29.695700 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6610 01:32:29.698668 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6611 01:32:29.705502 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6612 01:32:29.708626 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6613 01:32:29.709091 ==
6614 01:32:29.711641 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 01:32:29.715173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 01:32:29.715680 ==
6617 01:32:29.719349 DQS Delay:
6618 01:32:29.719769 DQS0 = 48, DQS1 = 60
6619 01:32:29.720197 DQM Delay:
6620 01:32:29.721941 DQM0 = 13, DQM1 = 13
6621 01:32:29.722373 DQ Delay:
6622 01:32:29.725045 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6623 01:32:29.728662 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6624 01:32:29.731714 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6625 01:32:29.735008 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6626 01:32:29.735429
6627 01:32:29.735851
6628 01:32:29.745825 [DQSOSCAuto] RK1, (LSB)MR18= 0x847e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6629 01:32:29.746347 CH0 RK1: MR19=C0C, MR18=847E
6630 01:32:29.751843 CH0_RK1: MR19=0xC0C, MR18=0x847E, DQSOSC=393, MR23=63, INC=382, DEC=254
6631 01:32:29.754428 [RxdqsGatingPostProcess] freq 400
6632 01:32:29.761323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6633 01:32:29.764635 best DQS0 dly(2T, 0.5T) = (0, 10)
6634 01:32:29.768125 best DQS1 dly(2T, 0.5T) = (0, 10)
6635 01:32:29.771135 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6636 01:32:29.774407 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6637 01:32:29.778267 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 01:32:29.781162 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 01:32:29.784741 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 01:32:29.787627 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 01:32:29.791153 Pre-setting of DQS Precalculation
6642 01:32:29.794703 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6643 01:32:29.795255 ==
6644 01:32:29.797457 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 01:32:29.801204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 01:32:29.801694 ==
6647 01:32:29.807472 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 01:32:29.814090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6649 01:32:29.817391 [CA 0] Center 36 (8~64) winsize 57
6650 01:32:29.820613 [CA 1] Center 36 (8~64) winsize 57
6651 01:32:29.824414 [CA 2] Center 36 (8~64) winsize 57
6652 01:32:29.827012 [CA 3] Center 36 (8~64) winsize 57
6653 01:32:29.831234 [CA 4] Center 36 (8~64) winsize 57
6654 01:32:29.833892 [CA 5] Center 36 (8~64) winsize 57
6655 01:32:29.834477
6656 01:32:29.837093 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6657 01:32:29.837684
6658 01:32:29.840025 [CATrainingPosCal] consider 1 rank data
6659 01:32:29.844079 u2DelayCellTimex100 = 270/100 ps
6660 01:32:29.846939 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 01:32:29.849898 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 01:32:29.853725 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 01:32:29.856810 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 01:32:29.860173 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 01:32:29.863716 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 01:32:29.864170
6667 01:32:29.869936 CA PerBit enable=1, Macro0, CA PI delay=36
6668 01:32:29.870486
6669 01:32:29.870845 [CBTSetCACLKResult] CA Dly = 36
6670 01:32:29.873033 CS Dly: 1 (0~32)
6671 01:32:29.873541 ==
6672 01:32:29.876653 Dram Type= 6, Freq= 0, CH_1, rank 1
6673 01:32:29.879996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 01:32:29.880549 ==
6675 01:32:29.886334 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 01:32:29.893006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6677 01:32:29.896309 [CA 0] Center 36 (8~64) winsize 57
6678 01:32:29.900276 [CA 1] Center 36 (8~64) winsize 57
6679 01:32:29.903159 [CA 2] Center 36 (8~64) winsize 57
6680 01:32:29.906051 [CA 3] Center 36 (8~64) winsize 57
6681 01:32:29.910060 [CA 4] Center 36 (8~64) winsize 57
6682 01:32:29.910515 [CA 5] Center 36 (8~64) winsize 57
6683 01:32:29.912747
6684 01:32:29.916485 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6685 01:32:29.917028
6686 01:32:29.918928 [CATrainingPosCal] consider 2 rank data
6687 01:32:29.922381 u2DelayCellTimex100 = 270/100 ps
6688 01:32:29.926024 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 01:32:29.929462 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 01:32:29.932896 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 01:32:29.935809 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 01:32:29.938920 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 01:32:29.942199 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 01:32:29.942653
6695 01:32:29.949198 CA PerBit enable=1, Macro0, CA PI delay=36
6696 01:32:29.949788
6697 01:32:29.950144 [CBTSetCACLKResult] CA Dly = 36
6698 01:32:29.952686 CS Dly: 1 (0~32)
6699 01:32:29.953237
6700 01:32:29.955637 ----->DramcWriteLeveling(PI) begin...
6701 01:32:29.956194 ==
6702 01:32:29.958859 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 01:32:29.962562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 01:32:29.963113 ==
6705 01:32:29.965398 Write leveling (Byte 0): 40 => 8
6706 01:32:29.969115 Write leveling (Byte 1): 40 => 8
6707 01:32:29.971898 DramcWriteLeveling(PI) end<-----
6708 01:32:29.972352
6709 01:32:29.972706 ==
6710 01:32:29.975910 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 01:32:29.978485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 01:32:29.981956 ==
6713 01:32:29.982501 [Gating] SW mode calibration
6714 01:32:29.992384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6715 01:32:29.994817 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6716 01:32:29.998264 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6717 01:32:30.005417 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 01:32:30.008251 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 01:32:30.011270 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 01:32:30.017885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 01:32:30.021713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 01:32:30.024490 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 01:32:30.031627 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 01:32:30.035430 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 01:32:30.037652 Total UI for P1: 0, mck2ui 16
6726 01:32:30.041223 best dqsien dly found for B0: ( 0, 14, 24)
6727 01:32:30.044383 Total UI for P1: 0, mck2ui 16
6728 01:32:30.048015 best dqsien dly found for B1: ( 0, 14, 24)
6729 01:32:30.051381 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6730 01:32:30.054184 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6731 01:32:30.054646
6732 01:32:30.057594 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6733 01:32:30.064447 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 01:32:30.064991 [Gating] SW calibration Done
6735 01:32:30.065526 ==
6736 01:32:30.067874 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 01:32:30.073703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 01:32:30.074163 ==
6739 01:32:30.074519 RX Vref Scan: 0
6740 01:32:30.074849
6741 01:32:30.076935 RX Vref 0 -> 0, step: 1
6742 01:32:30.077426
6743 01:32:30.080384 RX Delay -410 -> 252, step: 16
6744 01:32:30.083712 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6745 01:32:30.087096 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6746 01:32:30.093727 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6747 01:32:30.096995 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6748 01:32:30.100351 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6749 01:32:30.103364 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6750 01:32:30.110279 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6751 01:32:30.113382 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6752 01:32:30.116592 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6753 01:32:30.120224 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6754 01:32:30.126472 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6755 01:32:30.129873 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6756 01:32:30.133705 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6757 01:32:30.140144 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6758 01:32:30.142820 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6759 01:32:30.146570 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6760 01:32:30.147124 ==
6761 01:32:30.149770 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 01:32:30.156542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 01:32:30.157096 ==
6764 01:32:30.157580 DQS Delay:
6765 01:32:30.159617 DQS0 = 43, DQS1 = 51
6766 01:32:30.160069 DQM Delay:
6767 01:32:30.160426 DQM0 = 13, DQM1 = 15
6768 01:32:30.163238 DQ Delay:
6769 01:32:30.165956 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6770 01:32:30.166416 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6771 01:32:30.169450 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6772 01:32:30.172722 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =16
6773 01:32:30.173179
6774 01:32:30.175551
6775 01:32:30.176059 ==
6776 01:32:30.178996 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 01:32:30.182541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 01:32:30.183060 ==
6779 01:32:30.183389
6780 01:32:30.183692
6781 01:32:30.185367 TX Vref Scan disable
6782 01:32:30.185785 == TX Byte 0 ==
6783 01:32:30.189291 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 01:32:30.195470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 01:32:30.195971 == TX Byte 1 ==
6786 01:32:30.199426 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 01:32:30.206102 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 01:32:30.206637 ==
6789 01:32:30.208793 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 01:32:30.212393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 01:32:30.213046 ==
6792 01:32:30.213439
6793 01:32:30.213752
6794 01:32:30.215701 TX Vref Scan disable
6795 01:32:30.216203 == TX Byte 0 ==
6796 01:32:30.221765 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 01:32:30.225391 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 01:32:30.225806 == TX Byte 1 ==
6799 01:32:30.231965 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 01:32:30.235826 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 01:32:30.236331
6802 01:32:30.236655 [DATLAT]
6803 01:32:30.237997 Freq=400, CH1 RK0
6804 01:32:30.238409
6805 01:32:30.238732 DATLAT Default: 0xf
6806 01:32:30.241854 0, 0xFFFF, sum = 0
6807 01:32:30.242371 1, 0xFFFF, sum = 0
6808 01:32:30.245349 2, 0xFFFF, sum = 0
6809 01:32:30.245854 3, 0xFFFF, sum = 0
6810 01:32:30.248104 4, 0xFFFF, sum = 0
6811 01:32:30.248524 5, 0xFFFF, sum = 0
6812 01:32:30.251780 6, 0xFFFF, sum = 0
6813 01:32:30.252290 7, 0xFFFF, sum = 0
6814 01:32:30.254730 8, 0xFFFF, sum = 0
6815 01:32:30.258065 9, 0xFFFF, sum = 0
6816 01:32:30.258565 10, 0xFFFF, sum = 0
6817 01:32:30.261003 11, 0xFFFF, sum = 0
6818 01:32:30.261558 12, 0xFFFF, sum = 0
6819 01:32:30.264759 13, 0x0, sum = 1
6820 01:32:30.265321 14, 0x0, sum = 2
6821 01:32:30.267912 15, 0x0, sum = 3
6822 01:32:30.268417 16, 0x0, sum = 4
6823 01:32:30.268751 best_step = 14
6824 01:32:30.271499
6825 01:32:30.272014 ==
6826 01:32:30.274150 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 01:32:30.277481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 01:32:30.277985 ==
6829 01:32:30.278319 RX Vref Scan: 1
6830 01:32:30.278628
6831 01:32:30.281093 RX Vref 0 -> 0, step: 1
6832 01:32:30.281640
6833 01:32:30.283932 RX Delay -343 -> 252, step: 8
6834 01:32:30.284344
6835 01:32:30.287158 Set Vref, RX VrefLevel [Byte0]: 52
6836 01:32:30.290757 [Byte1]: 47
6837 01:32:30.295195
6838 01:32:30.295695 Final RX Vref Byte 0 = 52 to rank0
6839 01:32:30.298031 Final RX Vref Byte 1 = 47 to rank0
6840 01:32:30.301862 Final RX Vref Byte 0 = 52 to rank1
6841 01:32:30.304351 Final RX Vref Byte 1 = 47 to rank1==
6842 01:32:30.307571 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 01:32:30.314310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 01:32:30.314805 ==
6845 01:32:30.315134 DQS Delay:
6846 01:32:30.318098 DQS0 = 44, DQS1 = 56
6847 01:32:30.318603 DQM Delay:
6848 01:32:30.320895 DQM0 = 12, DQM1 = 15
6849 01:32:30.321331 DQ Delay:
6850 01:32:30.324431 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6851 01:32:30.327536 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6852 01:32:30.328057 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6853 01:32:30.334110 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6854 01:32:30.334599
6855 01:32:30.334924
6856 01:32:30.340857 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 398 ps
6857 01:32:30.344070 CH1 RK0: MR19=C0C, MR18=5D84
6858 01:32:30.350718 CH1_RK0: MR19=0xC0C, MR18=0x5D84, DQSOSC=393, MR23=63, INC=382, DEC=254
6859 01:32:30.351278 ==
6860 01:32:30.353830 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 01:32:30.357443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 01:32:30.357987 ==
6863 01:32:30.360430 [Gating] SW mode calibration
6864 01:32:30.366964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6865 01:32:30.373873 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6866 01:32:30.376625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6867 01:32:30.380910 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 01:32:30.386522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 01:32:30.390007 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 01:32:30.393664 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 01:32:30.400273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 01:32:30.403706 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 01:32:30.406427 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 01:32:30.413368 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 01:32:30.416113 Total UI for P1: 0, mck2ui 16
6876 01:32:30.419592 best dqsien dly found for B0: ( 0, 14, 24)
6877 01:32:30.422838 Total UI for P1: 0, mck2ui 16
6878 01:32:30.425872 best dqsien dly found for B1: ( 0, 14, 24)
6879 01:32:30.429460 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6880 01:32:30.432909 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6881 01:32:30.433500
6882 01:32:30.435958 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6883 01:32:30.439210 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 01:32:30.442501 [Gating] SW calibration Done
6885 01:32:30.442914 ==
6886 01:32:30.446008 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 01:32:30.449716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 01:32:30.450298 ==
6889 01:32:30.452646 RX Vref Scan: 0
6890 01:32:30.453190
6891 01:32:30.456046 RX Vref 0 -> 0, step: 1
6892 01:32:30.456500
6893 01:32:30.459201 RX Delay -410 -> 252, step: 16
6894 01:32:30.463108 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6895 01:32:30.465749 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6896 01:32:30.468984 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6897 01:32:30.476009 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6898 01:32:30.479486 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6899 01:32:30.483401 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6900 01:32:30.485551 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6901 01:32:30.492689 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6902 01:32:30.495864 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6903 01:32:30.499196 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6904 01:32:30.502928 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6905 01:32:30.508641 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6906 01:32:30.511923 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6907 01:32:30.515649 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6908 01:32:30.521994 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6909 01:32:30.524915 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6910 01:32:30.525499 ==
6911 01:32:30.528887 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 01:32:30.531890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 01:32:30.532404 ==
6914 01:32:30.534994 DQS Delay:
6915 01:32:30.535404 DQS0 = 43, DQS1 = 51
6916 01:32:30.535729 DQM Delay:
6917 01:32:30.538223 DQM0 = 10, DQM1 = 12
6918 01:32:30.538635 DQ Delay:
6919 01:32:30.541412 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6920 01:32:30.544633 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6921 01:32:30.548518 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6922 01:32:30.551547 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6923 01:32:30.551965
6924 01:32:30.552293
6925 01:32:30.552702 ==
6926 01:32:30.554619 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 01:32:30.558081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 01:32:30.561297 ==
6929 01:32:30.561727
6930 01:32:30.562071
6931 01:32:30.562377 TX Vref Scan disable
6932 01:32:30.565045 == TX Byte 0 ==
6933 01:32:30.567814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6934 01:32:30.570930 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6935 01:32:30.574398 == TX Byte 1 ==
6936 01:32:30.577675 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6937 01:32:30.581008 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6938 01:32:30.581475 ==
6939 01:32:30.584022 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 01:32:30.590908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 01:32:30.591420 ==
6942 01:32:30.591752
6943 01:32:30.592057
6944 01:32:30.592348 TX Vref Scan disable
6945 01:32:30.594363 == TX Byte 0 ==
6946 01:32:30.597618 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6947 01:32:30.601334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6948 01:32:30.603991 == TX Byte 1 ==
6949 01:32:30.607377 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6950 01:32:30.611049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6951 01:32:30.611571
6952 01:32:30.613853 [DATLAT]
6953 01:32:30.614263 Freq=400, CH1 RK1
6954 01:32:30.614590
6955 01:32:30.617969 DATLAT Default: 0xe
6956 01:32:30.618468 0, 0xFFFF, sum = 0
6957 01:32:30.620488 1, 0xFFFF, sum = 0
6958 01:32:30.620905 2, 0xFFFF, sum = 0
6959 01:32:30.624415 3, 0xFFFF, sum = 0
6960 01:32:30.624940 4, 0xFFFF, sum = 0
6961 01:32:30.626957 5, 0xFFFF, sum = 0
6962 01:32:30.627367 6, 0xFFFF, sum = 0
6963 01:32:30.630087 7, 0xFFFF, sum = 0
6964 01:32:30.630497 8, 0xFFFF, sum = 0
6965 01:32:30.633393 9, 0xFFFF, sum = 0
6966 01:32:30.636798 10, 0xFFFF, sum = 0
6967 01:32:30.637235 11, 0xFFFF, sum = 0
6968 01:32:30.640072 12, 0xFFFF, sum = 0
6969 01:32:30.640485 13, 0x0, sum = 1
6970 01:32:30.643549 14, 0x0, sum = 2
6971 01:32:30.643969 15, 0x0, sum = 3
6972 01:32:30.647450 16, 0x0, sum = 4
6973 01:32:30.647961 best_step = 14
6974 01:32:30.648284
6975 01:32:30.648586 ==
6976 01:32:30.650245 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 01:32:30.653278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 01:32:30.653693 ==
6979 01:32:30.656914 RX Vref Scan: 0
6980 01:32:30.657494
6981 01:32:30.659983 RX Vref 0 -> 0, step: 1
6982 01:32:30.660390
6983 01:32:30.660711 RX Delay -343 -> 252, step: 8
6984 01:32:30.669329 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6985 01:32:30.672260 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6986 01:32:30.675420 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6987 01:32:30.682198 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6988 01:32:30.685049 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6989 01:32:30.689070 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6990 01:32:30.692184 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6991 01:32:30.699153 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6992 01:32:30.702101 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6993 01:32:30.705045 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6994 01:32:30.709013 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6995 01:32:30.715114 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6996 01:32:30.717878 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6997 01:32:30.721885 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6998 01:32:30.727632 iDelay=217, Bit 14, Center -36 (-271 ~ 200) 472
6999 01:32:30.731517 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7000 01:32:30.732107 ==
7001 01:32:30.734710 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 01:32:30.737959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 01:32:30.738408 ==
7004 01:32:30.741236 DQS Delay:
7005 01:32:30.741725 DQS0 = 48, DQS1 = 56
7006 01:32:30.742078 DQM Delay:
7007 01:32:30.744445 DQM0 = 11, DQM1 = 14
7008 01:32:30.744886 DQ Delay:
7009 01:32:30.747778 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7010 01:32:30.751289 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7011 01:32:30.754632 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7012 01:32:30.757748 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
7013 01:32:30.758155
7014 01:32:30.758471
7015 01:32:30.767616 [DQSOSCAuto] RK1, (LSB)MR18= 0x69a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
7016 01:32:30.768153 CH1 RK1: MR19=C0C, MR18=69A1
7017 01:32:30.773769 CH1_RK1: MR19=0xC0C, MR18=0x69A1, DQSOSC=389, MR23=63, INC=390, DEC=260
7018 01:32:30.777705 [RxdqsGatingPostProcess] freq 400
7019 01:32:30.784236 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7020 01:32:30.787221 best DQS0 dly(2T, 0.5T) = (0, 10)
7021 01:32:30.790489 best DQS1 dly(2T, 0.5T) = (0, 10)
7022 01:32:30.793650 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7023 01:32:30.796865 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7024 01:32:30.800347 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 01:32:30.803651 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 01:32:30.806772 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 01:32:30.809910 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 01:32:30.813634 Pre-setting of DQS Precalculation
7029 01:32:30.817007 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7030 01:32:30.823328 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7031 01:32:30.830219 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7032 01:32:30.830774
7033 01:32:30.833160
7034 01:32:30.833641 [Calibration Summary] 800 Mbps
7035 01:32:30.836782 CH 0, Rank 0
7036 01:32:30.837389 SW Impedance : PASS
7037 01:32:30.840010 DUTY Scan : NO K
7038 01:32:30.843905 ZQ Calibration : PASS
7039 01:32:30.844454 Jitter Meter : NO K
7040 01:32:30.846467 CBT Training : PASS
7041 01:32:30.849589 Write leveling : PASS
7042 01:32:30.850039 RX DQS gating : PASS
7043 01:32:30.853036 RX DQ/DQS(RDDQC) : PASS
7044 01:32:30.856528 TX DQ/DQS : PASS
7045 01:32:30.857077 RX DATLAT : PASS
7046 01:32:30.859226 RX DQ/DQS(Engine): PASS
7047 01:32:30.862721 TX OE : NO K
7048 01:32:30.863272 All Pass.
7049 01:32:30.863625
7050 01:32:30.863955 CH 0, Rank 1
7051 01:32:30.866346 SW Impedance : PASS
7052 01:32:30.869592 DUTY Scan : NO K
7053 01:32:30.870143 ZQ Calibration : PASS
7054 01:32:30.872243 Jitter Meter : NO K
7055 01:32:30.876055 CBT Training : PASS
7056 01:32:30.876509 Write leveling : NO K
7057 01:32:30.879219 RX DQS gating : PASS
7058 01:32:30.882887 RX DQ/DQS(RDDQC) : PASS
7059 01:32:30.883431 TX DQ/DQS : PASS
7060 01:32:30.886144 RX DATLAT : PASS
7061 01:32:30.888996 RX DQ/DQS(Engine): PASS
7062 01:32:30.889489 TX OE : NO K
7063 01:32:30.889854 All Pass.
7064 01:32:30.892210
7065 01:32:30.892752 CH 1, Rank 0
7066 01:32:30.895514 SW Impedance : PASS
7067 01:32:30.896063 DUTY Scan : NO K
7068 01:32:30.899143 ZQ Calibration : PASS
7069 01:32:30.901975 Jitter Meter : NO K
7070 01:32:30.902430 CBT Training : PASS
7071 01:32:30.905746 Write leveling : PASS
7072 01:32:30.906287 RX DQS gating : PASS
7073 01:32:30.909497 RX DQ/DQS(RDDQC) : PASS
7074 01:32:30.912492 TX DQ/DQS : PASS
7075 01:32:30.913036 RX DATLAT : PASS
7076 01:32:30.915319 RX DQ/DQS(Engine): PASS
7077 01:32:30.919033 TX OE : NO K
7078 01:32:30.919580 All Pass.
7079 01:32:30.919942
7080 01:32:30.920276 CH 1, Rank 1
7081 01:32:30.921832 SW Impedance : PASS
7082 01:32:30.925047 DUTY Scan : NO K
7083 01:32:30.925621 ZQ Calibration : PASS
7084 01:32:30.928664 Jitter Meter : NO K
7085 01:32:30.931834 CBT Training : PASS
7086 01:32:30.932286 Write leveling : NO K
7087 01:32:30.935484 RX DQS gating : PASS
7088 01:32:30.938747 RX DQ/DQS(RDDQC) : PASS
7089 01:32:30.939300 TX DQ/DQS : PASS
7090 01:32:30.941560 RX DATLAT : PASS
7091 01:32:30.945810 RX DQ/DQS(Engine): PASS
7092 01:32:30.946359 TX OE : NO K
7093 01:32:30.948718 All Pass.
7094 01:32:30.949302
7095 01:32:30.949672 DramC Write-DBI off
7096 01:32:30.952887 PER_BANK_REFRESH: Hybrid Mode
7097 01:32:30.953484 TX_TRACKING: ON
7098 01:32:30.961424 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7099 01:32:30.965877 [FAST_K] Save calibration result to emmc
7100 01:32:30.968334 dramc_set_vcore_voltage set vcore to 725000
7101 01:32:30.972171 Read voltage for 1600, 0
7102 01:32:30.972734 Vio18 = 0
7103 01:32:30.975298 Vcore = 725000
7104 01:32:30.975849 Vdram = 0
7105 01:32:30.976207 Vddq = 0
7106 01:32:30.977836 Vmddr = 0
7107 01:32:30.981228 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7108 01:32:30.987821 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7109 01:32:30.988371 MEM_TYPE=3, freq_sel=13
7110 01:32:30.990865 sv_algorithm_assistance_LP4_3733
7111 01:32:30.997823 ============ PULL DRAM RESETB DOWN ============
7112 01:32:31.000866 ========== PULL DRAM RESETB DOWN end =========
7113 01:32:31.004730 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7114 01:32:31.007423 ===================================
7115 01:32:31.011067 LPDDR4 DRAM CONFIGURATION
7116 01:32:31.013962 ===================================
7117 01:32:31.017634 EX_ROW_EN[0] = 0x0
7118 01:32:31.018192 EX_ROW_EN[1] = 0x0
7119 01:32:31.021479 LP4Y_EN = 0x0
7120 01:32:31.022023 WORK_FSP = 0x1
7121 01:32:31.024159 WL = 0x5
7122 01:32:31.024608 RL = 0x5
7123 01:32:31.027411 BL = 0x2
7124 01:32:31.027864 RPST = 0x0
7125 01:32:31.030498 RD_PRE = 0x0
7126 01:32:31.030948 WR_PRE = 0x1
7127 01:32:31.033389 WR_PST = 0x1
7128 01:32:31.037044 DBI_WR = 0x0
7129 01:32:31.037603 DBI_RD = 0x0
7130 01:32:31.040012 OTF = 0x1
7131 01:32:31.043451 ===================================
7132 01:32:31.046968 ===================================
7133 01:32:31.047481 ANA top config
7134 01:32:31.050101 ===================================
7135 01:32:31.053338 DLL_ASYNC_EN = 0
7136 01:32:31.056710 ALL_SLAVE_EN = 0
7137 01:32:31.057217 NEW_RANK_MODE = 1
7138 01:32:31.059830 DLL_IDLE_MODE = 1
7139 01:32:31.063616 LP45_APHY_COMB_EN = 1
7140 01:32:31.066340 TX_ODT_DIS = 0
7141 01:32:31.066753 NEW_8X_MODE = 1
7142 01:32:31.070504 ===================================
7143 01:32:31.072914 ===================================
7144 01:32:31.076305 data_rate = 3200
7145 01:32:31.079565 CKR = 1
7146 01:32:31.083529 DQ_P2S_RATIO = 8
7147 01:32:31.087433 ===================================
7148 01:32:31.089523 CA_P2S_RATIO = 8
7149 01:32:31.092909 DQ_CA_OPEN = 0
7150 01:32:31.096663 DQ_SEMI_OPEN = 0
7151 01:32:31.097165 CA_SEMI_OPEN = 0
7152 01:32:31.099738 CA_FULL_RATE = 0
7153 01:32:31.102458 DQ_CKDIV4_EN = 0
7154 01:32:31.106515 CA_CKDIV4_EN = 0
7155 01:32:31.109435 CA_PREDIV_EN = 0
7156 01:32:31.112475 PH8_DLY = 12
7157 01:32:31.112996 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7158 01:32:31.115844 DQ_AAMCK_DIV = 4
7159 01:32:31.118961 CA_AAMCK_DIV = 4
7160 01:32:31.122267 CA_ADMCK_DIV = 4
7161 01:32:31.126067 DQ_TRACK_CA_EN = 0
7162 01:32:31.129568 CA_PICK = 1600
7163 01:32:31.132342 CA_MCKIO = 1600
7164 01:32:31.132748 MCKIO_SEMI = 0
7165 01:32:31.135880 PLL_FREQ = 3068
7166 01:32:31.139135 DQ_UI_PI_RATIO = 32
7167 01:32:31.141832 CA_UI_PI_RATIO = 0
7168 01:32:31.145382 ===================================
7169 01:32:31.148997 ===================================
7170 01:32:31.152291 memory_type:LPDDR4
7171 01:32:31.152789 GP_NUM : 10
7172 01:32:31.155295 SRAM_EN : 1
7173 01:32:31.159356 MD32_EN : 0
7174 01:32:31.161828 ===================================
7175 01:32:31.162242 [ANA_INIT] >>>>>>>>>>>>>>
7176 01:32:31.165333 <<<<<< [CONFIGURE PHASE]: ANA_TX
7177 01:32:31.168468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7178 01:32:31.172092 ===================================
7179 01:32:31.175470 data_rate = 3200,PCW = 0X7600
7180 01:32:31.178438 ===================================
7181 01:32:31.181517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7182 01:32:31.188232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7183 01:32:31.194686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 01:32:31.198686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7185 01:32:31.201383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7186 01:32:31.206838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7187 01:32:31.208134 [ANA_INIT] flow start
7188 01:32:31.208745 [ANA_INIT] PLL >>>>>>>>
7189 01:32:31.211137 [ANA_INIT] PLL <<<<<<<<
7190 01:32:31.214657 [ANA_INIT] MIDPI >>>>>>>>
7191 01:32:31.215208 [ANA_INIT] MIDPI <<<<<<<<
7192 01:32:31.217929 [ANA_INIT] DLL >>>>>>>>
7193 01:32:31.221808 [ANA_INIT] DLL <<<<<<<<
7194 01:32:31.222359 [ANA_INIT] flow end
7195 01:32:31.228572 ============ LP4 DIFF to SE enter ============
7196 01:32:31.231402 ============ LP4 DIFF to SE exit ============
7197 01:32:31.234037 [ANA_INIT] <<<<<<<<<<<<<
7198 01:32:31.237766 [Flow] Enable top DCM control >>>>>
7199 01:32:31.241059 [Flow] Enable top DCM control <<<<<
7200 01:32:31.244626 Enable DLL master slave shuffle
7201 01:32:31.247642 ==============================================================
7202 01:32:31.251283 Gating Mode config
7203 01:32:31.254530 ==============================================================
7204 01:32:31.257848 Config description:
7205 01:32:31.267421 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7206 01:32:31.273983 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7207 01:32:31.277422 SELPH_MODE 0: By rank 1: By Phase
7208 01:32:31.283481 ==============================================================
7209 01:32:31.286800 GAT_TRACK_EN = 1
7210 01:32:31.290127 RX_GATING_MODE = 2
7211 01:32:31.293570 RX_GATING_TRACK_MODE = 2
7212 01:32:31.296985 SELPH_MODE = 1
7213 01:32:31.300153 PICG_EARLY_EN = 1
7214 01:32:31.303687 VALID_LAT_VALUE = 1
7215 01:32:31.306699 ==============================================================
7216 01:32:31.310357 Enter into Gating configuration >>>>
7217 01:32:31.313446 Exit from Gating configuration <<<<
7218 01:32:31.317731 Enter into DVFS_PRE_config >>>>>
7219 01:32:31.329584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7220 01:32:31.330044 Exit from DVFS_PRE_config <<<<<
7221 01:32:31.333038 Enter into PICG configuration >>>>
7222 01:32:31.336766 Exit from PICG configuration <<<<
7223 01:32:31.339994 [RX_INPUT] configuration >>>>>
7224 01:32:31.343103 [RX_INPUT] configuration <<<<<
7225 01:32:31.349589 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7226 01:32:31.353070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7227 01:32:31.360035 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 01:32:31.365871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 01:32:31.372717 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7230 01:32:31.379495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7231 01:32:31.383183 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7232 01:32:31.386043 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7233 01:32:31.392943 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7234 01:32:31.395785 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7235 01:32:31.399235 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7236 01:32:31.402256 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 01:32:31.405642 ===================================
7238 01:32:31.409047 LPDDR4 DRAM CONFIGURATION
7239 01:32:31.411908 ===================================
7240 01:32:31.415762 EX_ROW_EN[0] = 0x0
7241 01:32:31.416303 EX_ROW_EN[1] = 0x0
7242 01:32:31.418560 LP4Y_EN = 0x0
7243 01:32:31.419104 WORK_FSP = 0x1
7244 01:32:31.421835 WL = 0x5
7245 01:32:31.422280 RL = 0x5
7246 01:32:31.425239 BL = 0x2
7247 01:32:31.428326 RPST = 0x0
7248 01:32:31.428770 RD_PRE = 0x0
7249 01:32:31.432401 WR_PRE = 0x1
7250 01:32:31.432848 WR_PST = 0x1
7251 01:32:31.434971 DBI_WR = 0x0
7252 01:32:31.435451 DBI_RD = 0x0
7253 01:32:31.438171 OTF = 0x1
7254 01:32:31.441761 ===================================
7255 01:32:31.445361 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7256 01:32:31.448687 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7257 01:32:31.451966 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7258 01:32:31.454997 ===================================
7259 01:32:31.458171 LPDDR4 DRAM CONFIGURATION
7260 01:32:31.461223 ===================================
7261 01:32:31.465113 EX_ROW_EN[0] = 0x10
7262 01:32:31.465718 EX_ROW_EN[1] = 0x0
7263 01:32:31.468899 LP4Y_EN = 0x0
7264 01:32:31.469501 WORK_FSP = 0x1
7265 01:32:31.471970 WL = 0x5
7266 01:32:31.472522 RL = 0x5
7267 01:32:31.474444 BL = 0x2
7268 01:32:31.474897 RPST = 0x0
7269 01:32:31.478032 RD_PRE = 0x0
7270 01:32:31.482303 WR_PRE = 0x1
7271 01:32:31.482855 WR_PST = 0x1
7272 01:32:31.485087 DBI_WR = 0x0
7273 01:32:31.485591 DBI_RD = 0x0
7274 01:32:31.488566 OTF = 0x1
7275 01:32:31.491394 ===================================
7276 01:32:31.494989 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7277 01:32:31.498000 ==
7278 01:32:31.501519 Dram Type= 6, Freq= 0, CH_0, rank 0
7279 01:32:31.504859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7280 01:32:31.505497 ==
7281 01:32:31.508089 [Duty_Offset_Calibration]
7282 01:32:31.508640 B0:2 B1:0 CA:4
7283 01:32:31.509002
7284 01:32:31.511393 [DutyScan_Calibration_Flow] k_type=0
7285 01:32:31.520861
7286 01:32:31.521458 ==CLK 0==
7287 01:32:31.523929 Final CLK duty delay cell = -4
7288 01:32:31.526924 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7289 01:32:31.530267 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7290 01:32:31.533719 [-4] AVG Duty = 4937%(X100)
7291 01:32:31.534276
7292 01:32:31.536636 CH0 CLK Duty spec in!! Max-Min= 187%
7293 01:32:31.540589 [DutyScan_Calibration_Flow] ====Done====
7294 01:32:31.541133
7295 01:32:31.543551 [DutyScan_Calibration_Flow] k_type=1
7296 01:32:31.561081
7297 01:32:31.561669 ==DQS 0 ==
7298 01:32:31.563668 Final DQS duty delay cell = 0
7299 01:32:31.568016 [0] MAX Duty = 5218%(X100), DQS PI = 38
7300 01:32:31.570105 [0] MIN Duty = 5093%(X100), DQS PI = 12
7301 01:32:31.574402 [0] AVG Duty = 5155%(X100)
7302 01:32:31.574963
7303 01:32:31.575321 ==DQS 1 ==
7304 01:32:31.576929 Final DQS duty delay cell = 0
7305 01:32:31.579921 [0] MAX Duty = 5156%(X100), DQS PI = 0
7306 01:32:31.583656 [0] MIN Duty = 4969%(X100), DQS PI = 10
7307 01:32:31.587229 [0] AVG Duty = 5062%(X100)
7308 01:32:31.587694
7309 01:32:31.590464 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7310 01:32:31.591048
7311 01:32:31.593497 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7312 01:32:31.596408 [DutyScan_Calibration_Flow] ====Done====
7313 01:32:31.596859
7314 01:32:31.600254 [DutyScan_Calibration_Flow] k_type=3
7315 01:32:31.617749
7316 01:32:31.618295 ==DQM 0 ==
7317 01:32:31.621188 Final DQM duty delay cell = 0
7318 01:32:31.624783 [0] MAX Duty = 5124%(X100), DQS PI = 22
7319 01:32:31.627215 [0] MIN Duty = 4844%(X100), DQS PI = 56
7320 01:32:31.630902 [0] AVG Duty = 4984%(X100)
7321 01:32:31.631617
7322 01:32:31.632009 ==DQM 1 ==
7323 01:32:31.634245 Final DQM duty delay cell = 0
7324 01:32:31.637289 [0] MAX Duty = 5000%(X100), DQS PI = 4
7325 01:32:31.640483 [0] MIN Duty = 4844%(X100), DQS PI = 14
7326 01:32:31.644110 [0] AVG Duty = 4922%(X100)
7327 01:32:31.644689
7328 01:32:31.646943 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7329 01:32:31.647393
7330 01:32:31.650364 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7331 01:32:31.653936 [DutyScan_Calibration_Flow] ====Done====
7332 01:32:31.654343
7333 01:32:31.657169 [DutyScan_Calibration_Flow] k_type=2
7334 01:32:31.675404
7335 01:32:31.675947 ==DQ 0 ==
7336 01:32:31.678380 Final DQ duty delay cell = 0
7337 01:32:31.681598 [0] MAX Duty = 5125%(X100), DQS PI = 26
7338 01:32:31.684555 [0] MIN Duty = 4938%(X100), DQS PI = 12
7339 01:32:31.684964 [0] AVG Duty = 5031%(X100)
7340 01:32:31.688450
7341 01:32:31.689069 ==DQ 1 ==
7342 01:32:31.691395 Final DQ duty delay cell = 0
7343 01:32:31.694905 [0] MAX Duty = 5187%(X100), DQS PI = 4
7344 01:32:31.698441 [0] MIN Duty = 4907%(X100), DQS PI = 34
7345 01:32:31.698972 [0] AVG Duty = 5047%(X100)
7346 01:32:31.700909
7347 01:32:31.704481 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7348 01:32:31.704892
7349 01:32:31.707677 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7350 01:32:31.711377 [DutyScan_Calibration_Flow] ====Done====
7351 01:32:31.711790 ==
7352 01:32:31.715016 Dram Type= 6, Freq= 0, CH_1, rank 0
7353 01:32:31.717722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7354 01:32:31.718392 ==
7355 01:32:31.720828 [Duty_Offset_Calibration]
7356 01:32:31.721236 B0:0 B1:-1 CA:3
7357 01:32:31.721604
7358 01:32:31.723929 [DutyScan_Calibration_Flow] k_type=0
7359 01:32:31.735362
7360 01:32:31.735671 ==CLK 0==
7361 01:32:31.738198 Final CLK duty delay cell = 0
7362 01:32:31.741181 [0] MAX Duty = 5187%(X100), DQS PI = 4
7363 01:32:31.744679 [0] MIN Duty = 5000%(X100), DQS PI = 54
7364 01:32:31.747929 [0] AVG Duty = 5093%(X100)
7365 01:32:31.748220
7366 01:32:31.751915 CH1 CLK Duty spec in!! Max-Min= 187%
7367 01:32:31.754417 [DutyScan_Calibration_Flow] ====Done====
7368 01:32:31.754705
7369 01:32:31.757569 [DutyScan_Calibration_Flow] k_type=1
7370 01:32:31.773700
7371 01:32:31.774078 ==DQS 0 ==
7372 01:32:31.777131 Final DQS duty delay cell = 0
7373 01:32:31.780354 [0] MAX Duty = 5218%(X100), DQS PI = 28
7374 01:32:31.783695 [0] MIN Duty = 4907%(X100), DQS PI = 40
7375 01:32:31.787129 [0] AVG Duty = 5062%(X100)
7376 01:32:31.787580
7377 01:32:31.787900 ==DQS 1 ==
7378 01:32:31.790708 Final DQS duty delay cell = -4
7379 01:32:31.793340 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7380 01:32:31.797434 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7381 01:32:31.800322 [-4] AVG Duty = 4906%(X100)
7382 01:32:31.800831
7383 01:32:31.803493 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7384 01:32:31.803900
7385 01:32:31.806995 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7386 01:32:31.810149 [DutyScan_Calibration_Flow] ====Done====
7387 01:32:31.810553
7388 01:32:31.813324 [DutyScan_Calibration_Flow] k_type=3
7389 01:32:31.831339
7390 01:32:31.831839 ==DQM 0 ==
7391 01:32:31.834247 Final DQM duty delay cell = 0
7392 01:32:31.837579 [0] MAX Duty = 5062%(X100), DQS PI = 30
7393 01:32:31.840996 [0] MIN Duty = 4750%(X100), DQS PI = 40
7394 01:32:31.844677 [0] AVG Duty = 4906%(X100)
7395 01:32:31.845182
7396 01:32:31.845670 ==DQM 1 ==
7397 01:32:31.847949 Final DQM duty delay cell = 0
7398 01:32:31.850848 [0] MAX Duty = 4969%(X100), DQS PI = 30
7399 01:32:31.853915 [0] MIN Duty = 4813%(X100), DQS PI = 0
7400 01:32:31.857941 [0] AVG Duty = 4891%(X100)
7401 01:32:31.858466
7402 01:32:31.860812 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7403 01:32:31.861226
7404 01:32:31.864363 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7405 01:32:31.867330 [DutyScan_Calibration_Flow] ====Done====
7406 01:32:31.867840
7407 01:32:31.871125 [DutyScan_Calibration_Flow] k_type=2
7408 01:32:31.887379
7409 01:32:31.887929 ==DQ 0 ==
7410 01:32:31.890904 Final DQ duty delay cell = -4
7411 01:32:31.893818 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7412 01:32:31.897177 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7413 01:32:31.900628 [-4] AVG Duty = 4875%(X100)
7414 01:32:31.901172
7415 01:32:31.901577 ==DQ 1 ==
7416 01:32:31.904113 Final DQ duty delay cell = 0
7417 01:32:31.907007 [0] MAX Duty = 5062%(X100), DQS PI = 32
7418 01:32:31.910154 [0] MIN Duty = 4875%(X100), DQS PI = 56
7419 01:32:31.913934 [0] AVG Duty = 4968%(X100)
7420 01:32:31.914479
7421 01:32:31.916967 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7422 01:32:31.917550
7423 01:32:31.920356 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7424 01:32:31.923639 [DutyScan_Calibration_Flow] ====Done====
7425 01:32:31.926484 nWR fixed to 30
7426 01:32:31.929786 [ModeRegInit_LP4] CH0 RK0
7427 01:32:31.930264 [ModeRegInit_LP4] CH0 RK1
7428 01:32:31.933363 [ModeRegInit_LP4] CH1 RK0
7429 01:32:31.936881 [ModeRegInit_LP4] CH1 RK1
7430 01:32:31.937397 match AC timing 5
7431 01:32:31.943119 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7432 01:32:31.946648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7433 01:32:31.950628 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7434 01:32:31.956328 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7435 01:32:31.959665 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7436 01:32:31.960205 [MiockJmeterHQA]
7437 01:32:31.963702
7438 01:32:31.965979 [DramcMiockJmeter] u1RxGatingPI = 0
7439 01:32:31.966424 0 : 4255, 4029
7440 01:32:31.966782 4 : 4363, 4138
7441 01:32:31.969407 8 : 4252, 4027
7442 01:32:31.969949 12 : 4252, 4027
7443 01:32:31.973413 16 : 4253, 4027
7444 01:32:31.973953 20 : 4253, 4026
7445 01:32:31.976381 24 : 4363, 4138
7446 01:32:31.976995 28 : 4363, 4137
7447 01:32:31.977414 32 : 4252, 4027
7448 01:32:31.979130 36 : 4253, 4027
7449 01:32:31.979579 40 : 4253, 4026
7450 01:32:31.983332 44 : 4250, 4027
7451 01:32:31.983875 48 : 4254, 4029
7452 01:32:31.985804 52 : 4361, 4137
7453 01:32:31.986253 56 : 4250, 4027
7454 01:32:31.989236 60 : 4250, 4027
7455 01:32:31.989717 64 : 4250, 4027
7456 01:32:31.990071 68 : 4252, 4029
7457 01:32:31.992434 72 : 4250, 4027
7458 01:32:31.993090 76 : 4360, 4138
7459 01:32:31.995697 80 : 4360, 4137
7460 01:32:31.996165 84 : 4250, 4027
7461 01:32:31.999167 88 : 4250, 4027
7462 01:32:31.999714 92 : 4250, 4026
7463 01:32:32.001967 96 : 4250, 2855
7464 01:32:32.002444 100 : 4252, 0
7465 01:32:32.002811 104 : 4250, 0
7466 01:32:32.005443 108 : 4250, 0
7467 01:32:32.005898 112 : 4361, 0
7468 01:32:32.009112 116 : 4250, 0
7469 01:32:32.009668 120 : 4250, 0
7470 01:32:32.010015 124 : 4250, 0
7471 01:32:32.011887 128 : 4250, 0
7472 01:32:32.012313 132 : 4250, 0
7473 01:32:32.015629 136 : 4250, 0
7474 01:32:32.016141 140 : 4252, 0
7475 01:32:32.016470 144 : 4250, 0
7476 01:32:32.018914 148 : 4250, 0
7477 01:32:32.019423 152 : 4252, 0
7478 01:32:32.019751 156 : 4360, 0
7479 01:32:32.022399 160 : 4361, 0
7480 01:32:32.022911 164 : 4363, 0
7481 01:32:32.025972 168 : 4250, 0
7482 01:32:32.026384 172 : 4250, 0
7483 01:32:32.026710 176 : 4250, 0
7484 01:32:32.029418 180 : 4250, 0
7485 01:32:32.029831 184 : 4250, 0
7486 01:32:32.031697 188 : 4250, 0
7487 01:32:32.032107 192 : 4252, 0
7488 01:32:32.032432 196 : 4250, 0
7489 01:32:32.035100 200 : 4250, 0
7490 01:32:32.035517 204 : 4252, 0
7491 01:32:32.038613 208 : 4360, 0
7492 01:32:32.039127 212 : 4250, 0
7493 01:32:32.039456 216 : 4360, 0
7494 01:32:32.042855 220 : 4250, 508
7495 01:32:32.043266 224 : 4250, 4016
7496 01:32:32.045320 228 : 4361, 4138
7497 01:32:32.045733 232 : 4250, 4027
7498 01:32:32.049187 236 : 4250, 4027
7499 01:32:32.049635 240 : 4363, 4140
7500 01:32:32.051596 244 : 4250, 4026
7501 01:32:32.052105 248 : 4250, 4027
7502 01:32:32.055108 252 : 4250, 4027
7503 01:32:32.055618 256 : 4252, 4029
7504 01:32:32.058060 260 : 4250, 4026
7505 01:32:32.058469 264 : 4250, 4027
7506 01:32:32.058812 268 : 4360, 4138
7507 01:32:32.061404 272 : 4250, 4027
7508 01:32:32.061929 276 : 4250, 4026
7509 01:32:32.064771 280 : 4361, 4137
7510 01:32:32.065182 284 : 4250, 4027
7511 01:32:32.068030 288 : 4250, 4027
7512 01:32:32.068541 292 : 4360, 4137
7513 01:32:32.071891 296 : 4250, 4026
7514 01:32:32.072398 300 : 4250, 4027
7515 01:32:32.074786 304 : 4250, 4027
7516 01:32:32.075194 308 : 4252, 4029
7517 01:32:32.077801 312 : 4250, 4027
7518 01:32:32.078211 316 : 4250, 4027
7519 01:32:32.081228 320 : 4360, 4138
7520 01:32:32.081717 324 : 4250, 4027
7521 01:32:32.084426 328 : 4250, 4026
7522 01:32:32.084939 332 : 4360, 4090
7523 01:32:32.087457 336 : 4250, 1296
7524 01:32:32.088003
7525 01:32:32.088334 MIOCK jitter meter ch=0
7526 01:32:32.088636
7527 01:32:32.090985 1T = (336-100) = 236 dly cells
7528 01:32:32.097828 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7529 01:32:32.098332 ==
7530 01:32:32.101062 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 01:32:32.103871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 01:32:32.104291 ==
7533 01:32:32.110672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 01:32:32.114292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 01:32:32.117197 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 01:32:32.124100 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 01:32:32.133631 [CA 0] Center 43 (13~74) winsize 62
7538 01:32:32.137123 [CA 1] Center 42 (12~73) winsize 62
7539 01:32:32.140251 [CA 2] Center 37 (8~67) winsize 60
7540 01:32:32.144284 [CA 3] Center 37 (8~67) winsize 60
7541 01:32:32.147006 [CA 4] Center 36 (6~66) winsize 61
7542 01:32:32.149969 [CA 5] Center 35 (5~66) winsize 62
7543 01:32:32.150418
7544 01:32:32.153778 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 01:32:32.154325
7546 01:32:32.160206 [CATrainingPosCal] consider 1 rank data
7547 01:32:32.160750 u2DelayCellTimex100 = 275/100 ps
7548 01:32:32.167172 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7549 01:32:32.169572 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7550 01:32:32.173246 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7551 01:32:32.176599 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7552 01:32:32.179654 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7553 01:32:32.182884 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7554 01:32:32.183421
7555 01:32:32.186493 CA PerBit enable=1, Macro0, CA PI delay=35
7556 01:32:32.186942
7557 01:32:32.189418 [CBTSetCACLKResult] CA Dly = 35
7558 01:32:32.192590 CS Dly: 10 (0~41)
7559 01:32:32.196230 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 01:32:32.199453 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 01:32:32.199908 ==
7562 01:32:32.202432 Dram Type= 6, Freq= 0, CH_0, rank 1
7563 01:32:32.209027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 01:32:32.209624 ==
7565 01:32:32.212186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7566 01:32:32.219092 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7567 01:32:32.222317 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7568 01:32:32.228530 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7569 01:32:32.237762 [CA 0] Center 44 (14~75) winsize 62
7570 01:32:32.240606 [CA 1] Center 44 (14~74) winsize 61
7571 01:32:32.243877 [CA 2] Center 39 (10~69) winsize 60
7572 01:32:32.246891 [CA 3] Center 39 (10~68) winsize 59
7573 01:32:32.250126 [CA 4] Center 37 (7~67) winsize 61
7574 01:32:32.253519 [CA 5] Center 36 (7~66) winsize 60
7575 01:32:32.253978
7576 01:32:32.256994 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7577 01:32:32.259783
7578 01:32:32.263601 [CATrainingPosCal] consider 2 rank data
7579 01:32:32.264153 u2DelayCellTimex100 = 275/100 ps
7580 01:32:32.269545 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7581 01:32:32.273932 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7582 01:32:32.276290 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7583 01:32:32.279427 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7584 01:32:32.282929 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7585 01:32:32.286136 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7586 01:32:32.286575
7587 01:32:32.289349 CA PerBit enable=1, Macro0, CA PI delay=36
7588 01:32:32.292593
7589 01:32:32.293002 [CBTSetCACLKResult] CA Dly = 36
7590 01:32:32.296132 CS Dly: 11 (0~44)
7591 01:32:32.299158 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7592 01:32:32.302475 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7593 01:32:32.305975
7594 01:32:32.309281 ----->DramcWriteLeveling(PI) begin...
7595 01:32:32.309801 ==
7596 01:32:32.312462 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 01:32:32.316117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 01:32:32.316617 ==
7599 01:32:32.320367 Write leveling (Byte 0): 34 => 34
7600 01:32:32.322517 Write leveling (Byte 1): 26 => 26
7601 01:32:32.325736 DramcWriteLeveling(PI) end<-----
7602 01:32:32.326158
7603 01:32:32.326484 ==
7604 01:32:32.328888 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 01:32:32.332278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 01:32:32.332695 ==
7607 01:32:32.335175 [Gating] SW mode calibration
7608 01:32:32.342997 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7609 01:32:32.348792 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7610 01:32:32.352641 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 01:32:32.355412 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 01:32:32.362219 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
7613 01:32:32.365388 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7614 01:32:32.368595 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7615 01:32:32.375114 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7616 01:32:32.378062 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 01:32:32.381934 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 01:32:32.388224 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 01:32:32.391984 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 01:32:32.395196 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7621 01:32:32.401907 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7622 01:32:32.404758 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7623 01:32:32.407683 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
7624 01:32:32.414288 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7625 01:32:32.417843 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 01:32:32.421418 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 01:32:32.427215 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 01:32:32.431223 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
7629 01:32:32.434272 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
7630 01:32:32.440447 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7631 01:32:32.444136 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7632 01:32:32.447322 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 01:32:32.453857 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 01:32:32.457223 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 01:32:32.460654 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 01:32:32.467025 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 01:32:32.470448 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7638 01:32:32.477322 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7639 01:32:32.480097 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7640 01:32:32.483382 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 01:32:32.487075 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7642 01:32:32.493650 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 01:32:32.496752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 01:32:32.503384 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 01:32:32.506209 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 01:32:32.510126 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 01:32:32.516575 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 01:32:32.520161 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 01:32:32.523181 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 01:32:32.529414 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 01:32:32.532665 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 01:32:32.536103 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 01:32:32.543500 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 01:32:32.545736 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7655 01:32:32.549252 Total UI for P1: 0, mck2ui 16
7656 01:32:32.552798 best dqsien dly found for B0: ( 1, 9, 10)
7657 01:32:32.556114 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7658 01:32:32.562595 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 01:32:32.565866 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 01:32:32.569030 Total UI for P1: 0, mck2ui 16
7661 01:32:32.572427 best dqsien dly found for B1: ( 1, 9, 22)
7662 01:32:32.575864 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7663 01:32:32.579134 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7664 01:32:32.579633
7665 01:32:32.581778 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7666 01:32:32.585570 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7667 01:32:32.588437 [Gating] SW calibration Done
7668 01:32:32.588849 ==
7669 01:32:32.592326 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 01:32:32.595800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 01:32:32.598635 ==
7672 01:32:32.599052 RX Vref Scan: 0
7673 01:32:32.599382
7674 01:32:32.602176 RX Vref 0 -> 0, step: 1
7675 01:32:32.602672
7676 01:32:32.603003 RX Delay 0 -> 252, step: 8
7677 01:32:32.609060 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7678 01:32:32.612576 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7679 01:32:32.615257 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7680 01:32:32.618462 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7681 01:32:32.625556 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7682 01:32:32.628719 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7683 01:32:32.631722 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7684 01:32:32.634792 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7685 01:32:32.638525 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7686 01:32:32.645071 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7687 01:32:32.648435 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7688 01:32:32.652162 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7689 01:32:32.654592 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7690 01:32:32.658065 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7691 01:32:32.664364 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7692 01:32:32.668096 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7693 01:32:32.668598 ==
7694 01:32:32.671223 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 01:32:32.674446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 01:32:32.674953 ==
7697 01:32:32.677392 DQS Delay:
7698 01:32:32.677803 DQS0 = 0, DQS1 = 0
7699 01:32:32.680530 DQM Delay:
7700 01:32:32.680941 DQM0 = 130, DQM1 = 126
7701 01:32:32.684588 DQ Delay:
7702 01:32:32.688355 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7703 01:32:32.690381 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7704 01:32:32.694118 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
7705 01:32:32.697634 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7706 01:32:32.698137
7707 01:32:32.698466
7708 01:32:32.698769 ==
7709 01:32:32.700809 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 01:32:32.703693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 01:32:32.704203 ==
7712 01:32:32.704535
7713 01:32:32.706906
7714 01:32:32.707316 TX Vref Scan disable
7715 01:32:32.710233 == TX Byte 0 ==
7716 01:32:32.713614 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7717 01:32:32.717366 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7718 01:32:32.720455 == TX Byte 1 ==
7719 01:32:32.723916 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7720 01:32:32.726692 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7721 01:32:32.727111 ==
7722 01:32:32.729898 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 01:32:32.736655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 01:32:32.737159 ==
7725 01:32:32.749365
7726 01:32:32.752525 TX Vref early break, caculate TX vref
7727 01:32:32.755899 TX Vref=16, minBit 4, minWin=22, winSum=371
7728 01:32:32.759851 TX Vref=18, minBit 1, minWin=23, winSum=381
7729 01:32:32.762502 TX Vref=20, minBit 8, minWin=23, winSum=391
7730 01:32:32.765691 TX Vref=22, minBit 7, minWin=24, winSum=402
7731 01:32:32.768856 TX Vref=24, minBit 3, minWin=24, winSum=407
7732 01:32:32.775605 TX Vref=26, minBit 3, minWin=25, winSum=414
7733 01:32:32.779248 TX Vref=28, minBit 2, minWin=25, winSum=421
7734 01:32:32.782044 TX Vref=30, minBit 2, minWin=25, winSum=418
7735 01:32:32.785557 TX Vref=32, minBit 4, minWin=24, winSum=408
7736 01:32:32.788940 TX Vref=34, minBit 1, minWin=24, winSum=398
7737 01:32:32.795581 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 28
7738 01:32:32.796106
7739 01:32:32.799000 Final TX Range 0 Vref 28
7740 01:32:32.799512
7741 01:32:32.799844 ==
7742 01:32:32.802593 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 01:32:32.805236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 01:32:32.805721 ==
7745 01:32:32.806057
7746 01:32:32.806366
7747 01:32:32.808858 TX Vref Scan disable
7748 01:32:32.815566 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7749 01:32:32.816070 == TX Byte 0 ==
7750 01:32:32.818512 u2DelayCellOfst[0]=10 cells (3 PI)
7751 01:32:32.822063 u2DelayCellOfst[1]=14 cells (4 PI)
7752 01:32:32.825599 u2DelayCellOfst[2]=10 cells (3 PI)
7753 01:32:32.829354 u2DelayCellOfst[3]=10 cells (3 PI)
7754 01:32:32.832043 u2DelayCellOfst[4]=7 cells (2 PI)
7755 01:32:32.834890 u2DelayCellOfst[5]=0 cells (0 PI)
7756 01:32:32.838640 u2DelayCellOfst[6]=17 cells (5 PI)
7757 01:32:32.841849 u2DelayCellOfst[7]=14 cells (4 PI)
7758 01:32:32.845079 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7759 01:32:32.848165 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7760 01:32:32.851822 == TX Byte 1 ==
7761 01:32:32.855065 u2DelayCellOfst[8]=0 cells (0 PI)
7762 01:32:32.858544 u2DelayCellOfst[9]=0 cells (0 PI)
7763 01:32:32.859047 u2DelayCellOfst[10]=3 cells (1 PI)
7764 01:32:32.861537 u2DelayCellOfst[11]=0 cells (0 PI)
7765 01:32:32.864912 u2DelayCellOfst[12]=7 cells (2 PI)
7766 01:32:32.868196 u2DelayCellOfst[13]=10 cells (3 PI)
7767 01:32:32.871250 u2DelayCellOfst[14]=14 cells (4 PI)
7768 01:32:32.874347 u2DelayCellOfst[15]=10 cells (3 PI)
7769 01:32:32.881544 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7770 01:32:32.884933 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7771 01:32:32.885537 DramC Write-DBI on
7772 01:32:32.886160 ==
7773 01:32:32.887502 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 01:32:32.894581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 01:32:32.895094 ==
7776 01:32:32.895432
7777 01:32:32.895743
7778 01:32:32.897362 TX Vref Scan disable
7779 01:32:32.898030 == TX Byte 0 ==
7780 01:32:32.903942 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7781 01:32:32.904604 == TX Byte 1 ==
7782 01:32:32.907518 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7783 01:32:32.910489 DramC Write-DBI off
7784 01:32:32.911008
7785 01:32:32.911622 [DATLAT]
7786 01:32:32.913943 Freq=1600, CH0 RK0
7787 01:32:32.914357
7788 01:32:32.914680 DATLAT Default: 0xf
7789 01:32:32.917481 0, 0xFFFF, sum = 0
7790 01:32:32.917931 1, 0xFFFF, sum = 0
7791 01:32:32.920513 2, 0xFFFF, sum = 0
7792 01:32:32.920929 3, 0xFFFF, sum = 0
7793 01:32:32.923857 4, 0xFFFF, sum = 0
7794 01:32:32.924277 5, 0xFFFF, sum = 0
7795 01:32:32.927114 6, 0xFFFF, sum = 0
7796 01:32:32.930375 7, 0xFFFF, sum = 0
7797 01:32:32.930799 8, 0xFFFF, sum = 0
7798 01:32:32.933523 9, 0xFFFF, sum = 0
7799 01:32:32.933942 10, 0xFFFF, sum = 0
7800 01:32:32.936995 11, 0xFFFF, sum = 0
7801 01:32:32.937463 12, 0xFFFF, sum = 0
7802 01:32:32.940478 13, 0xFFFF, sum = 0
7803 01:32:32.940894 14, 0x0, sum = 1
7804 01:32:32.943992 15, 0x0, sum = 2
7805 01:32:32.944410 16, 0x0, sum = 3
7806 01:32:32.947196 17, 0x0, sum = 4
7807 01:32:32.947712 best_step = 15
7808 01:32:32.948060
7809 01:32:32.948629 ==
7810 01:32:32.950417 Dram Type= 6, Freq= 0, CH_0, rank 0
7811 01:32:32.953462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7812 01:32:32.956581 ==
7813 01:32:32.957126 RX Vref Scan: 1
7814 01:32:32.957555
7815 01:32:32.959967 Set Vref Range= 24 -> 127
7816 01:32:32.960379
7817 01:32:32.963667 RX Vref 24 -> 127, step: 1
7818 01:32:32.964081
7819 01:32:32.964411 RX Delay 11 -> 252, step: 4
7820 01:32:32.964721
7821 01:32:32.967509 Set Vref, RX VrefLevel [Byte0]: 24
7822 01:32:32.969775 [Byte1]: 24
7823 01:32:32.973544
7824 01:32:32.973953 Set Vref, RX VrefLevel [Byte0]: 25
7825 01:32:32.977106 [Byte1]: 25
7826 01:32:32.981555
7827 01:32:32.981969 Set Vref, RX VrefLevel [Byte0]: 26
7828 01:32:32.984479 [Byte1]: 26
7829 01:32:32.989144
7830 01:32:32.989618 Set Vref, RX VrefLevel [Byte0]: 27
7831 01:32:32.992391 [Byte1]: 27
7832 01:32:32.996725
7833 01:32:32.997134 Set Vref, RX VrefLevel [Byte0]: 28
7834 01:32:33.000028 [Byte1]: 28
7835 01:32:33.004702
7836 01:32:33.005237 Set Vref, RX VrefLevel [Byte0]: 29
7837 01:32:33.007867 [Byte1]: 29
7838 01:32:33.012222
7839 01:32:33.012647 Set Vref, RX VrefLevel [Byte0]: 30
7840 01:32:33.015133 [Byte1]: 30
7841 01:32:33.019478
7842 01:32:33.019990 Set Vref, RX VrefLevel [Byte0]: 31
7843 01:32:33.023283 [Byte1]: 31
7844 01:32:33.027392
7845 01:32:33.027807 Set Vref, RX VrefLevel [Byte0]: 32
7846 01:32:33.030436 [Byte1]: 32
7847 01:32:33.034462
7848 01:32:33.034873 Set Vref, RX VrefLevel [Byte0]: 33
7849 01:32:33.038081 [Byte1]: 33
7850 01:32:33.042109
7851 01:32:33.042522 Set Vref, RX VrefLevel [Byte0]: 34
7852 01:32:33.045527 [Byte1]: 34
7853 01:32:33.049861
7854 01:32:33.050272 Set Vref, RX VrefLevel [Byte0]: 35
7855 01:32:33.053811 [Byte1]: 35
7856 01:32:33.057567
7857 01:32:33.057979 Set Vref, RX VrefLevel [Byte0]: 36
7858 01:32:33.060674 [Byte1]: 36
7859 01:32:33.065215
7860 01:32:33.065666 Set Vref, RX VrefLevel [Byte0]: 37
7861 01:32:33.068607 [Byte1]: 37
7862 01:32:33.073214
7863 01:32:33.073762 Set Vref, RX VrefLevel [Byte0]: 38
7864 01:32:33.076559 [Byte1]: 38
7865 01:32:33.080372
7866 01:32:33.080816 Set Vref, RX VrefLevel [Byte0]: 39
7867 01:32:33.083465 [Byte1]: 39
7868 01:32:33.088015
7869 01:32:33.088426 Set Vref, RX VrefLevel [Byte0]: 40
7870 01:32:33.091105 [Byte1]: 40
7871 01:32:33.095911
7872 01:32:33.096321 Set Vref, RX VrefLevel [Byte0]: 41
7873 01:32:33.098588 [Byte1]: 41
7874 01:32:33.103353
7875 01:32:33.103870 Set Vref, RX VrefLevel [Byte0]: 42
7876 01:32:33.106410 [Byte1]: 42
7877 01:32:33.111455
7878 01:32:33.111966 Set Vref, RX VrefLevel [Byte0]: 43
7879 01:32:33.114114 [Byte1]: 43
7880 01:32:33.118789
7881 01:32:33.119202 Set Vref, RX VrefLevel [Byte0]: 44
7882 01:32:33.121883 [Byte1]: 44
7883 01:32:33.125880
7884 01:32:33.126288 Set Vref, RX VrefLevel [Byte0]: 45
7885 01:32:33.129148 [Byte1]: 45
7886 01:32:33.134056
7887 01:32:33.134468 Set Vref, RX VrefLevel [Byte0]: 46
7888 01:32:33.136782 [Byte1]: 46
7889 01:32:33.141343
7890 01:32:33.141941 Set Vref, RX VrefLevel [Byte0]: 47
7891 01:32:33.144554 [Byte1]: 47
7892 01:32:33.149368
7893 01:32:33.149915 Set Vref, RX VrefLevel [Byte0]: 48
7894 01:32:33.152524 [Byte1]: 48
7895 01:32:33.156521
7896 01:32:33.156931 Set Vref, RX VrefLevel [Byte0]: 49
7897 01:32:33.160023 [Byte1]: 49
7898 01:32:33.163968
7899 01:32:33.164486 Set Vref, RX VrefLevel [Byte0]: 50
7900 01:32:33.168009 [Byte1]: 50
7901 01:32:33.171732
7902 01:32:33.172243 Set Vref, RX VrefLevel [Byte0]: 51
7903 01:32:33.175341 [Byte1]: 51
7904 01:32:33.179508
7905 01:32:33.180060 Set Vref, RX VrefLevel [Byte0]: 52
7906 01:32:33.182586 [Byte1]: 52
7907 01:32:33.187037
7908 01:32:33.187554 Set Vref, RX VrefLevel [Byte0]: 53
7909 01:32:33.193891 [Byte1]: 53
7910 01:32:33.194459
7911 01:32:33.196507 Set Vref, RX VrefLevel [Byte0]: 54
7912 01:32:33.199683 [Byte1]: 54
7913 01:32:33.200139
7914 01:32:33.203530 Set Vref, RX VrefLevel [Byte0]: 55
7915 01:32:33.206456 [Byte1]: 55
7916 01:32:33.209751
7917 01:32:33.210178 Set Vref, RX VrefLevel [Byte0]: 56
7918 01:32:33.213138 [Byte1]: 56
7919 01:32:33.217513
7920 01:32:33.217925 Set Vref, RX VrefLevel [Byte0]: 57
7921 01:32:33.220620 [Byte1]: 57
7922 01:32:33.225342
7923 01:32:33.225753 Set Vref, RX VrefLevel [Byte0]: 58
7924 01:32:33.228886 [Byte1]: 58
7925 01:32:33.232462
7926 01:32:33.232874 Set Vref, RX VrefLevel [Byte0]: 59
7927 01:32:33.235758 [Byte1]: 59
7928 01:32:33.240231
7929 01:32:33.240635 Set Vref, RX VrefLevel [Byte0]: 60
7930 01:32:33.243538 [Byte1]: 60
7931 01:32:33.247799
7932 01:32:33.248202 Set Vref, RX VrefLevel [Byte0]: 61
7933 01:32:33.251092 [Byte1]: 61
7934 01:32:33.255321
7935 01:32:33.255725 Set Vref, RX VrefLevel [Byte0]: 62
7936 01:32:33.259317 [Byte1]: 62
7937 01:32:33.263555
7938 01:32:33.264055 Set Vref, RX VrefLevel [Byte0]: 63
7939 01:32:33.266500 [Byte1]: 63
7940 01:32:33.270584
7941 01:32:33.270985 Set Vref, RX VrefLevel [Byte0]: 64
7942 01:32:33.274187 [Byte1]: 64
7943 01:32:33.278554
7944 01:32:33.278955 Set Vref, RX VrefLevel [Byte0]: 65
7945 01:32:33.281638 [Byte1]: 65
7946 01:32:33.285948
7947 01:32:33.286452 Set Vref, RX VrefLevel [Byte0]: 66
7948 01:32:33.289671 [Byte1]: 66
7949 01:32:33.293779
7950 01:32:33.294301 Set Vref, RX VrefLevel [Byte0]: 67
7951 01:32:33.296984 [Byte1]: 67
7952 01:32:33.300980
7953 01:32:33.301552 Set Vref, RX VrefLevel [Byte0]: 68
7954 01:32:33.304565 [Byte1]: 68
7955 01:32:33.309309
7956 01:32:33.309853 Set Vref, RX VrefLevel [Byte0]: 69
7957 01:32:33.311947 [Byte1]: 69
7958 01:32:33.316855
7959 01:32:33.317434 Set Vref, RX VrefLevel [Byte0]: 70
7960 01:32:33.319660 [Byte1]: 70
7961 01:32:33.324220
7962 01:32:33.324775 Set Vref, RX VrefLevel [Byte0]: 71
7963 01:32:33.327298 [Byte1]: 71
7964 01:32:33.331636
7965 01:32:33.332091 Set Vref, RX VrefLevel [Byte0]: 72
7966 01:32:33.335097 [Byte1]: 72
7967 01:32:33.339621
7968 01:32:33.340175 Set Vref, RX VrefLevel [Byte0]: 73
7969 01:32:33.342961 [Byte1]: 73
7970 01:32:33.346899
7971 01:32:33.347354 Set Vref, RX VrefLevel [Byte0]: 74
7972 01:32:33.350577 [Byte1]: 74
7973 01:32:33.354357
7974 01:32:33.357733 Set Vref, RX VrefLevel [Byte0]: 75
7975 01:32:33.361403 [Byte1]: 75
7976 01:32:33.362021
7977 01:32:33.364327 Final RX Vref Byte 0 = 52 to rank0
7978 01:32:33.367884 Final RX Vref Byte 1 = 63 to rank0
7979 01:32:33.371306 Final RX Vref Byte 0 = 52 to rank1
7980 01:32:33.373933 Final RX Vref Byte 1 = 63 to rank1==
7981 01:32:33.377800 Dram Type= 6, Freq= 0, CH_0, rank 0
7982 01:32:33.381582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 01:32:33.382141 ==
7984 01:32:33.382506 DQS Delay:
7985 01:32:33.384045 DQS0 = 0, DQS1 = 0
7986 01:32:33.384500 DQM Delay:
7987 01:32:33.387406 DQM0 = 128, DQM1 = 123
7988 01:32:33.387957 DQ Delay:
7989 01:32:33.390443 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =124
7990 01:32:33.393880 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =132
7991 01:32:33.397338 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7992 01:32:33.400593 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =128
7993 01:32:33.401150
7994 01:32:33.404425
7995 01:32:33.404975
7996 01:32:33.405373 [DramC_TX_OE_Calibration] TA2
7997 01:32:33.408307 Original DQ_B0 (3 6) =30, OEN = 27
7998 01:32:33.410701 Original DQ_B1 (3 6) =30, OEN = 27
7999 01:32:33.413870 24, 0x0, End_B0=24 End_B1=24
8000 01:32:33.417417 25, 0x0, End_B0=25 End_B1=25
8001 01:32:33.420436 26, 0x0, End_B0=26 End_B1=26
8002 01:32:33.420997 27, 0x0, End_B0=27 End_B1=27
8003 01:32:33.423994 28, 0x0, End_B0=28 End_B1=28
8004 01:32:33.427130 29, 0x0, End_B0=29 End_B1=29
8005 01:32:33.430460 30, 0x0, End_B0=30 End_B1=30
8006 01:32:33.433654 31, 0x4141, End_B0=30 End_B1=30
8007 01:32:33.437499 Byte0 end_step=30 best_step=27
8008 01:32:33.438266 Byte1 end_step=30 best_step=27
8009 01:32:33.440161 Byte0 TX OE(2T, 0.5T) = (3, 3)
8010 01:32:33.443804 Byte1 TX OE(2T, 0.5T) = (3, 3)
8011 01:32:33.444370
8012 01:32:33.444732
8013 01:32:33.452985 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
8014 01:32:33.453570 CH0 RK0: MR19=303, MR18=1916
8015 01:32:33.460284 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
8016 01:32:33.460830
8017 01:32:33.462658 ----->DramcWriteLeveling(PI) begin...
8018 01:32:33.463120 ==
8019 01:32:33.466539 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 01:32:33.472836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 01:32:33.473436 ==
8022 01:32:33.476350 Write leveling (Byte 0): 34 => 34
8023 01:32:33.479206 Write leveling (Byte 1): 27 => 27
8024 01:32:33.482448 DramcWriteLeveling(PI) end<-----
8025 01:32:33.482905
8026 01:32:33.483264 ==
8027 01:32:33.485932 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 01:32:33.489423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 01:32:33.489964 ==
8030 01:32:33.492720 [Gating] SW mode calibration
8031 01:32:33.499164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8032 01:32:33.506406 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8033 01:32:33.508873 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 01:32:33.512866 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 01:32:33.518770 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8036 01:32:33.522276 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8037 01:32:33.525475 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8038 01:32:33.532006 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8039 01:32:33.535918 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 01:32:33.538546 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 01:32:33.545093 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 01:32:33.548388 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 01:32:33.551930 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8044 01:32:33.558423 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8045 01:32:33.562057 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8046 01:32:33.565137 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8047 01:32:33.571757 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 01:32:33.574865 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 01:32:33.578121 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 01:32:33.584853 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 01:32:33.588176 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8052 01:32:33.591316 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8053 01:32:33.597799 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8054 01:32:33.601138 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8055 01:32:33.604717 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 01:32:33.611171 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 01:32:33.614349 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 01:32:33.617647 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 01:32:33.624358 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8060 01:32:33.628131 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8061 01:32:33.630366 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8062 01:32:33.637458 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8063 01:32:33.640938 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 01:32:33.644098 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 01:32:33.650569 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 01:32:33.653889 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 01:32:33.657112 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 01:32:33.663558 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 01:32:33.666842 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 01:32:33.670244 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 01:32:33.677340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 01:32:33.679874 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 01:32:33.683377 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 01:32:33.689772 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 01:32:33.693108 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 01:32:33.696379 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8077 01:32:33.699747 Total UI for P1: 0, mck2ui 16
8078 01:32:33.703050 best dqsien dly found for B0: ( 1, 9, 8)
8079 01:32:33.709689 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8080 01:32:33.712712 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8081 01:32:33.716026 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 01:32:33.720284 Total UI for P1: 0, mck2ui 16
8083 01:32:33.722776 best dqsien dly found for B1: ( 1, 9, 18)
8084 01:32:33.726311 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8085 01:32:33.729571 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8086 01:32:33.732176
8087 01:32:33.735877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8088 01:32:33.739579 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8089 01:32:33.742922 [Gating] SW calibration Done
8090 01:32:33.743427 ==
8091 01:32:33.745937 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 01:32:33.748902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 01:32:33.749454 ==
8094 01:32:33.749795 RX Vref Scan: 0
8095 01:32:33.752355
8096 01:32:33.752855 RX Vref 0 -> 0, step: 1
8097 01:32:33.753188
8098 01:32:33.756165 RX Delay 0 -> 252, step: 8
8099 01:32:33.759086 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8100 01:32:33.762372 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8101 01:32:33.768899 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8102 01:32:33.771757 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8103 01:32:33.775453 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8104 01:32:33.778740 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8105 01:32:33.782015 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8106 01:32:33.788277 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8107 01:32:33.791391 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
8108 01:32:33.794974 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8109 01:32:33.797950 iDelay=192, Bit 10, Center 131 (72 ~ 191) 120
8110 01:32:33.804778 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
8111 01:32:33.807916 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
8112 01:32:33.811789 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
8113 01:32:33.814609 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8114 01:32:33.821048 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
8115 01:32:33.821798 ==
8116 01:32:33.824819 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 01:32:33.827786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 01:32:33.828244 ==
8119 01:32:33.828606 DQS Delay:
8120 01:32:33.831251 DQS0 = 0, DQS1 = 0
8121 01:32:33.831687 DQM Delay:
8122 01:32:33.834051 DQM0 = 131, DQM1 = 124
8123 01:32:33.834462 DQ Delay:
8124 01:32:33.837198 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8125 01:32:33.840864 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8126 01:32:33.843724 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =115
8127 01:32:33.846988 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8128 01:32:33.847400
8129 01:32:33.850488
8130 01:32:33.850989 ==
8131 01:32:33.853593 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 01:32:33.857333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 01:32:33.857850 ==
8134 01:32:33.858182
8135 01:32:33.858491
8136 01:32:33.860392 TX Vref Scan disable
8137 01:32:33.860805 == TX Byte 0 ==
8138 01:32:33.866885 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8139 01:32:33.869973 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8140 01:32:33.870393 == TX Byte 1 ==
8141 01:32:33.876905 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8142 01:32:33.880115 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8143 01:32:33.880528 ==
8144 01:32:33.883432 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 01:32:33.886421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 01:32:33.886929 ==
8147 01:32:33.901233
8148 01:32:33.905743 TX Vref early break, caculate TX vref
8149 01:32:33.907563 TX Vref=16, minBit 9, minWin=22, winSum=378
8150 01:32:33.910921 TX Vref=18, minBit 8, minWin=23, winSum=388
8151 01:32:33.914066 TX Vref=20, minBit 0, minWin=25, winSum=404
8152 01:32:33.917725 TX Vref=22, minBit 0, minWin=25, winSum=407
8153 01:32:33.920940 TX Vref=24, minBit 1, minWin=25, winSum=414
8154 01:32:33.927632 TX Vref=26, minBit 1, minWin=25, winSum=422
8155 01:32:33.930400 TX Vref=28, minBit 1, minWin=25, winSum=421
8156 01:32:33.933816 TX Vref=30, minBit 1, minWin=24, winSum=420
8157 01:32:33.937221 TX Vref=32, minBit 1, minWin=24, winSum=409
8158 01:32:33.940656 TX Vref=34, minBit 0, minWin=24, winSum=399
8159 01:32:33.946981 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 26
8160 01:32:33.947522
8161 01:32:33.951318 Final TX Range 0 Vref 26
8162 01:32:33.951866
8163 01:32:33.952253 ==
8164 01:32:33.953751 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 01:32:33.956565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 01:32:33.956985 ==
8167 01:32:33.957365
8168 01:32:33.959830
8169 01:32:33.960370 TX Vref Scan disable
8170 01:32:33.966589 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8171 01:32:33.967129 == TX Byte 0 ==
8172 01:32:33.969856 u2DelayCellOfst[0]=10 cells (3 PI)
8173 01:32:33.973191 u2DelayCellOfst[1]=14 cells (4 PI)
8174 01:32:33.976601 u2DelayCellOfst[2]=7 cells (2 PI)
8175 01:32:33.979629 u2DelayCellOfst[3]=10 cells (3 PI)
8176 01:32:33.983008 u2DelayCellOfst[4]=7 cells (2 PI)
8177 01:32:33.986735 u2DelayCellOfst[5]=0 cells (0 PI)
8178 01:32:33.990002 u2DelayCellOfst[6]=14 cells (4 PI)
8179 01:32:33.992675 u2DelayCellOfst[7]=14 cells (4 PI)
8180 01:32:33.996842 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8181 01:32:33.999914 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8182 01:32:34.002732 == TX Byte 1 ==
8183 01:32:34.005985 u2DelayCellOfst[8]=0 cells (0 PI)
8184 01:32:34.009396 u2DelayCellOfst[9]=0 cells (0 PI)
8185 01:32:34.012863 u2DelayCellOfst[10]=3 cells (1 PI)
8186 01:32:34.016136 u2DelayCellOfst[11]=0 cells (0 PI)
8187 01:32:34.019579 u2DelayCellOfst[12]=10 cells (3 PI)
8188 01:32:34.022148 u2DelayCellOfst[13]=10 cells (3 PI)
8189 01:32:34.025438 u2DelayCellOfst[14]=14 cells (4 PI)
8190 01:32:34.029039 u2DelayCellOfst[15]=10 cells (3 PI)
8191 01:32:34.032261 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8192 01:32:34.035350 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8193 01:32:34.039148 DramC Write-DBI on
8194 01:32:34.039701 ==
8195 01:32:34.042396 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 01:32:34.045395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 01:32:34.045950 ==
8198 01:32:34.046318
8199 01:32:34.046832
8200 01:32:34.048680 TX Vref Scan disable
8201 01:32:34.051819 == TX Byte 0 ==
8202 01:32:34.055911 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8203 01:32:34.056469 == TX Byte 1 ==
8204 01:32:34.061566 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8205 01:32:34.062024 DramC Write-DBI off
8206 01:32:34.062384
8207 01:32:34.062807 [DATLAT]
8208 01:32:34.065461 Freq=1600, CH0 RK1
8209 01:32:34.066009
8210 01:32:34.069313 DATLAT Default: 0xf
8211 01:32:34.069886 0, 0xFFFF, sum = 0
8212 01:32:34.071723 1, 0xFFFF, sum = 0
8213 01:32:34.072275 2, 0xFFFF, sum = 0
8214 01:32:34.075558 3, 0xFFFF, sum = 0
8215 01:32:34.076023 4, 0xFFFF, sum = 0
8216 01:32:34.078598 5, 0xFFFF, sum = 0
8217 01:32:34.079063 6, 0xFFFF, sum = 0
8218 01:32:34.081595 7, 0xFFFF, sum = 0
8219 01:32:34.082238 8, 0xFFFF, sum = 0
8220 01:32:34.084692 9, 0xFFFF, sum = 0
8221 01:32:34.085157 10, 0xFFFF, sum = 0
8222 01:32:34.088553 11, 0xFFFF, sum = 0
8223 01:32:34.089121 12, 0xFFFF, sum = 0
8224 01:32:34.091391 13, 0xFFFF, sum = 0
8225 01:32:34.091853 14, 0x0, sum = 1
8226 01:32:34.094708 15, 0x0, sum = 2
8227 01:32:34.095171 16, 0x0, sum = 3
8228 01:32:34.098372 17, 0x0, sum = 4
8229 01:32:34.098895 best_step = 15
8230 01:32:34.099227
8231 01:32:34.099537 ==
8232 01:32:34.101895 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 01:32:34.108316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 01:32:34.108819 ==
8235 01:32:34.109152 RX Vref Scan: 0
8236 01:32:34.109487
8237 01:32:34.111083 RX Vref 0 -> 0, step: 1
8238 01:32:34.111494
8239 01:32:34.114925 RX Delay 11 -> 252, step: 4
8240 01:32:34.117349 iDelay=187, Bit 0, Center 126 (79 ~ 174) 96
8241 01:32:34.120973 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8242 01:32:34.127953 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8243 01:32:34.130982 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8244 01:32:34.134013 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8245 01:32:34.137531 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8246 01:32:34.140603 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8247 01:32:34.147455 iDelay=187, Bit 7, Center 136 (87 ~ 186) 100
8248 01:32:34.151066 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8249 01:32:34.153689 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8250 01:32:34.157473 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8251 01:32:34.161611 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8252 01:32:34.167545 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8253 01:32:34.170271 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8254 01:32:34.174224 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8255 01:32:34.177130 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8256 01:32:34.177625 ==
8257 01:32:34.180290 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 01:32:34.186688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 01:32:34.187245 ==
8260 01:32:34.187613 DQS Delay:
8261 01:32:34.190416 DQS0 = 0, DQS1 = 0
8262 01:32:34.190872 DQM Delay:
8263 01:32:34.193466 DQM0 = 129, DQM1 = 123
8264 01:32:34.193921 DQ Delay:
8265 01:32:34.197083 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8266 01:32:34.200271 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
8267 01:32:34.203873 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8268 01:32:34.206999 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8269 01:32:34.207557
8270 01:32:34.207919
8271 01:32:34.208251
8272 01:32:34.209949 [DramC_TX_OE_Calibration] TA2
8273 01:32:34.213706 Original DQ_B0 (3 6) =30, OEN = 27
8274 01:32:34.217371 Original DQ_B1 (3 6) =30, OEN = 27
8275 01:32:34.219654 24, 0x0, End_B0=24 End_B1=24
8276 01:32:34.223898 25, 0x0, End_B0=25 End_B1=25
8277 01:32:34.224439 26, 0x0, End_B0=26 End_B1=26
8278 01:32:34.226761 27, 0x0, End_B0=27 End_B1=27
8279 01:32:34.230206 28, 0x0, End_B0=28 End_B1=28
8280 01:32:34.233609 29, 0x0, End_B0=29 End_B1=29
8281 01:32:34.234076 30, 0x0, End_B0=30 End_B1=30
8282 01:32:34.236296 31, 0x4141, End_B0=30 End_B1=30
8283 01:32:34.239618 Byte0 end_step=30 best_step=27
8284 01:32:34.243170 Byte1 end_step=30 best_step=27
8285 01:32:34.245815 Byte0 TX OE(2T, 0.5T) = (3, 3)
8286 01:32:34.249319 Byte1 TX OE(2T, 0.5T) = (3, 3)
8287 01:32:34.249744
8288 01:32:34.250070
8289 01:32:34.256066 [DQSOSCAuto] RK1, (LSB)MR18= 0x100e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8290 01:32:34.259455 CH0 RK1: MR19=303, MR18=100E
8291 01:32:34.265453 CH0_RK1: MR19=0x303, MR18=0x100E, DQSOSC=401, MR23=63, INC=22, DEC=15
8292 01:32:34.269462 [RxdqsGatingPostProcess] freq 1600
8293 01:32:34.275842 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8294 01:32:34.279138 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 01:32:34.279686 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 01:32:34.282245 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 01:32:34.285594 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 01:32:34.288983 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 01:32:34.292517 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 01:32:34.295357 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 01:32:34.298978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 01:32:34.302100 Pre-setting of DQS Precalculation
8303 01:32:34.308755 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8304 01:32:34.309172 ==
8305 01:32:34.311587 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 01:32:34.314936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 01:32:34.315354 ==
8308 01:32:34.322048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 01:32:34.325687 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 01:32:34.327987 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 01:32:34.334836 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 01:32:34.343393 [CA 0] Center 43 (13~73) winsize 61
8313 01:32:34.346419 [CA 1] Center 43 (13~73) winsize 61
8314 01:32:34.349874 [CA 2] Center 39 (10~68) winsize 59
8315 01:32:34.353035 [CA 3] Center 38 (8~68) winsize 61
8316 01:32:34.356725 [CA 4] Center 38 (8~69) winsize 62
8317 01:32:34.360463 [CA 5] Center 37 (8~67) winsize 60
8318 01:32:34.361079
8319 01:32:34.363119 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8320 01:32:34.363550
8321 01:32:34.369638 [CATrainingPosCal] consider 1 rank data
8322 01:32:34.370054 u2DelayCellTimex100 = 275/100 ps
8323 01:32:34.376545 CA0 delay=43 (13~73),Diff = 6 PI (21 cell)
8324 01:32:34.379463 CA1 delay=43 (13~73),Diff = 6 PI (21 cell)
8325 01:32:34.382971 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8326 01:32:34.386144 CA3 delay=38 (8~68),Diff = 1 PI (3 cell)
8327 01:32:34.389809 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8328 01:32:34.392757 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8329 01:32:34.393128
8330 01:32:34.396123 CA PerBit enable=1, Macro0, CA PI delay=37
8331 01:32:34.396541
8332 01:32:34.399222 [CBTSetCACLKResult] CA Dly = 37
8333 01:32:34.402822 CS Dly: 8 (0~39)
8334 01:32:34.405810 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 01:32:34.409407 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 01:32:34.409856 ==
8337 01:32:34.412383 Dram Type= 6, Freq= 0, CH_1, rank 1
8338 01:32:34.419149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 01:32:34.419602 ==
8340 01:32:34.421864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8341 01:32:34.428967 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8342 01:32:34.432608 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8343 01:32:34.438532 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8344 01:32:34.446428 [CA 0] Center 41 (11~71) winsize 61
8345 01:32:34.449995 [CA 1] Center 41 (12~71) winsize 60
8346 01:32:34.453015 [CA 2] Center 37 (8~67) winsize 60
8347 01:32:34.456349 [CA 3] Center 36 (7~66) winsize 60
8348 01:32:34.460285 [CA 4] Center 37 (8~66) winsize 59
8349 01:32:34.462818 [CA 5] Center 36 (7~66) winsize 60
8350 01:32:34.463296
8351 01:32:34.466508 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8352 01:32:34.466925
8353 01:32:34.473236 [CATrainingPosCal] consider 2 rank data
8354 01:32:34.473788 u2DelayCellTimex100 = 275/100 ps
8355 01:32:34.479863 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8356 01:32:34.482876 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8357 01:32:34.486370 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8358 01:32:34.489325 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8359 01:32:34.492738 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
8360 01:32:34.496546 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8361 01:32:34.496960
8362 01:32:34.498868 CA PerBit enable=1, Macro0, CA PI delay=37
8363 01:32:34.499282
8364 01:32:34.502180 [CBTSetCACLKResult] CA Dly = 37
8365 01:32:34.505982 CS Dly: 9 (0~42)
8366 01:32:34.508934 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8367 01:32:34.512844 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8368 01:32:34.513289
8369 01:32:34.515806 ----->DramcWriteLeveling(PI) begin...
8370 01:32:34.516225 ==
8371 01:32:34.519092 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 01:32:34.525788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 01:32:34.526302 ==
8374 01:32:34.528786 Write leveling (Byte 0): 24 => 24
8375 01:32:34.531764 Write leveling (Byte 1): 26 => 26
8376 01:32:34.535151 DramcWriteLeveling(PI) end<-----
8377 01:32:34.535565
8378 01:32:34.535887 ==
8379 01:32:34.538575 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 01:32:34.542040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 01:32:34.542545 ==
8382 01:32:34.544910 [Gating] SW mode calibration
8383 01:32:34.551861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8384 01:32:34.559181 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8385 01:32:34.561542 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 01:32:34.565315 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 01:32:34.571714 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 01:32:34.574623 1 4 12 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
8389 01:32:34.577908 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8390 01:32:34.584663 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 01:32:34.588295 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 01:32:34.591063 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 01:32:34.597745 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 01:32:34.601432 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 01:32:34.604397 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8396 01:32:34.610715 1 5 12 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
8397 01:32:34.614851 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8398 01:32:34.617967 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 01:32:34.624493 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 01:32:34.627743 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 01:32:34.630948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 01:32:34.637350 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 01:32:34.640599 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 01:32:34.644476 1 6 12 | B1->B0 | 2a29 4646 | 1 0 | (0 0) (0 0)
8405 01:32:34.650243 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 01:32:34.653560 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 01:32:34.657363 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 01:32:34.663929 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 01:32:34.666635 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 01:32:34.670189 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 01:32:34.677120 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8412 01:32:34.680350 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 01:32:34.683639 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8414 01:32:34.690192 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 01:32:34.692948 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 01:32:34.696457 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 01:32:34.702807 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 01:32:34.706626 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 01:32:34.709622 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 01:32:34.716317 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 01:32:34.719494 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 01:32:34.723026 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 01:32:34.729518 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 01:32:34.732760 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 01:32:34.735970 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 01:32:34.742901 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 01:32:34.745740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8428 01:32:34.749513 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 01:32:34.755909 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8430 01:32:34.756461 Total UI for P1: 0, mck2ui 16
8431 01:32:34.762797 best dqsien dly found for B0: ( 1, 9, 10)
8432 01:32:34.765568 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 01:32:34.769246 Total UI for P1: 0, mck2ui 16
8434 01:32:34.772511 best dqsien dly found for B1: ( 1, 9, 14)
8435 01:32:34.775615 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8436 01:32:34.778815 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8437 01:32:34.779358
8438 01:32:34.782854 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8439 01:32:34.789059 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8440 01:32:34.789650 [Gating] SW calibration Done
8441 01:32:34.790021 ==
8442 01:32:34.791780 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 01:32:34.798846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 01:32:34.799385 ==
8445 01:32:34.799753 RX Vref Scan: 0
8446 01:32:34.800095
8447 01:32:34.801447 RX Vref 0 -> 0, step: 1
8448 01:32:34.801907
8449 01:32:34.805952 RX Delay 0 -> 252, step: 8
8450 01:32:34.808867 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8451 01:32:34.811256 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8452 01:32:34.814935 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8453 01:32:34.821207 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8454 01:32:34.824743 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8455 01:32:34.827737 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8456 01:32:34.831271 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8457 01:32:34.834364 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8458 01:32:34.841034 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8459 01:32:34.845045 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8460 01:32:34.847790 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8461 01:32:34.851414 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8462 01:32:34.854091 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8463 01:32:34.861637 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8464 01:32:34.864478 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8465 01:32:34.867912 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8466 01:32:34.868469 ==
8467 01:32:34.870946 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 01:32:34.874009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 01:32:34.877585 ==
8470 01:32:34.878044 DQS Delay:
8471 01:32:34.878409 DQS0 = 0, DQS1 = 0
8472 01:32:34.880493 DQM Delay:
8473 01:32:34.880948 DQM0 = 136, DQM1 = 131
8474 01:32:34.884125 DQ Delay:
8475 01:32:34.887528 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8476 01:32:34.890777 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8477 01:32:34.893658 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8478 01:32:34.897489 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =135
8479 01:32:34.898052
8480 01:32:34.898416
8481 01:32:34.898746 ==
8482 01:32:34.900640 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 01:32:34.903974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 01:32:34.907369 ==
8485 01:32:34.907927
8486 01:32:34.908286
8487 01:32:34.908617 TX Vref Scan disable
8488 01:32:34.909943 == TX Byte 0 ==
8489 01:32:34.913651 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8490 01:32:34.916879 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8491 01:32:34.921069 == TX Byte 1 ==
8492 01:32:34.923293 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8493 01:32:34.926803 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8494 01:32:34.930361 ==
8495 01:32:34.933322 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 01:32:34.936507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 01:32:34.936966 ==
8498 01:32:34.949790
8499 01:32:34.952956 TX Vref early break, caculate TX vref
8500 01:32:34.956825 TX Vref=16, minBit 9, minWin=21, winSum=365
8501 01:32:34.959350 TX Vref=18, minBit 8, minWin=21, winSum=377
8502 01:32:34.962918 TX Vref=20, minBit 9, minWin=22, winSum=386
8503 01:32:34.966480 TX Vref=22, minBit 8, minWin=23, winSum=397
8504 01:32:34.969608 TX Vref=24, minBit 0, minWin=25, winSum=407
8505 01:32:34.976869 TX Vref=26, minBit 5, minWin=25, winSum=418
8506 01:32:34.980296 TX Vref=28, minBit 0, minWin=25, winSum=419
8507 01:32:34.982302 TX Vref=30, minBit 0, minWin=25, winSum=416
8508 01:32:34.986111 TX Vref=32, minBit 9, minWin=24, winSum=406
8509 01:32:34.989165 TX Vref=34, minBit 11, minWin=23, winSum=399
8510 01:32:34.996066 TX Vref=36, minBit 11, minWin=22, winSum=386
8511 01:32:34.999034 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8512 01:32:34.999496
8513 01:32:35.002163 Final TX Range 0 Vref 28
8514 01:32:35.002717
8515 01:32:35.003080 ==
8516 01:32:35.006270 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 01:32:35.008889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 01:32:35.012534 ==
8519 01:32:35.013090
8520 01:32:35.013499
8521 01:32:35.013840 TX Vref Scan disable
8522 01:32:35.019144 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8523 01:32:35.019708 == TX Byte 0 ==
8524 01:32:35.022198 u2DelayCellOfst[0]=17 cells (5 PI)
8525 01:32:35.025621 u2DelayCellOfst[1]=10 cells (3 PI)
8526 01:32:35.029628 u2DelayCellOfst[2]=0 cells (0 PI)
8527 01:32:35.032309 u2DelayCellOfst[3]=7 cells (2 PI)
8528 01:32:35.035791 u2DelayCellOfst[4]=10 cells (3 PI)
8529 01:32:35.039096 u2DelayCellOfst[5]=17 cells (5 PI)
8530 01:32:35.042175 u2DelayCellOfst[6]=17 cells (5 PI)
8531 01:32:35.045712 u2DelayCellOfst[7]=7 cells (2 PI)
8532 01:32:35.048956 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8533 01:32:35.052300 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8534 01:32:35.055407 == TX Byte 1 ==
8535 01:32:35.058435 u2DelayCellOfst[8]=0 cells (0 PI)
8536 01:32:35.061866 u2DelayCellOfst[9]=3 cells (1 PI)
8537 01:32:35.065360 u2DelayCellOfst[10]=10 cells (3 PI)
8538 01:32:35.068583 u2DelayCellOfst[11]=3 cells (1 PI)
8539 01:32:35.071618 u2DelayCellOfst[12]=14 cells (4 PI)
8540 01:32:35.075308 u2DelayCellOfst[13]=14 cells (4 PI)
8541 01:32:35.078294 u2DelayCellOfst[14]=17 cells (5 PI)
8542 01:32:35.081510 u2DelayCellOfst[15]=17 cells (5 PI)
8543 01:32:35.084728 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8544 01:32:35.088896 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8545 01:32:35.091476 DramC Write-DBI on
8546 01:32:35.092018 ==
8547 01:32:35.094921 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 01:32:35.097899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 01:32:35.098456 ==
8550 01:32:35.098827
8551 01:32:35.099166
8552 01:32:35.101460 TX Vref Scan disable
8553 01:32:35.101923 == TX Byte 0 ==
8554 01:32:35.108223 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8555 01:32:35.108774 == TX Byte 1 ==
8556 01:32:35.114551 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8557 01:32:35.115106 DramC Write-DBI off
8558 01:32:35.115476
8559 01:32:35.115815 [DATLAT]
8560 01:32:35.117917 Freq=1600, CH1 RK0
8561 01:32:35.118377
8562 01:32:35.121039 DATLAT Default: 0xf
8563 01:32:35.121710 0, 0xFFFF, sum = 0
8564 01:32:35.125166 1, 0xFFFF, sum = 0
8565 01:32:35.125789 2, 0xFFFF, sum = 0
8566 01:32:35.127855 3, 0xFFFF, sum = 0
8567 01:32:35.128405 4, 0xFFFF, sum = 0
8568 01:32:35.131054 5, 0xFFFF, sum = 0
8569 01:32:35.131519 6, 0xFFFF, sum = 0
8570 01:32:35.134598 7, 0xFFFF, sum = 0
8571 01:32:35.135079 8, 0xFFFF, sum = 0
8572 01:32:35.137437 9, 0xFFFF, sum = 0
8573 01:32:35.137901 10, 0xFFFF, sum = 0
8574 01:32:35.141087 11, 0xFFFF, sum = 0
8575 01:32:35.141551 12, 0xFFFF, sum = 0
8576 01:32:35.144067 13, 0xFFFF, sum = 0
8577 01:32:35.144578 14, 0x0, sum = 1
8578 01:32:35.147066 15, 0x0, sum = 2
8579 01:32:35.147486 16, 0x0, sum = 3
8580 01:32:35.150630 17, 0x0, sum = 4
8581 01:32:35.151052 best_step = 15
8582 01:32:35.151384
8583 01:32:35.151687 ==
8584 01:32:35.153992 Dram Type= 6, Freq= 0, CH_1, rank 0
8585 01:32:35.160781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8586 01:32:35.161327 ==
8587 01:32:35.161675 RX Vref Scan: 1
8588 01:32:35.161984
8589 01:32:35.164157 Set Vref Range= 24 -> 127
8590 01:32:35.164574
8591 01:32:35.167636 RX Vref 24 -> 127, step: 1
8592 01:32:35.168143
8593 01:32:35.170861 RX Delay 19 -> 252, step: 4
8594 01:32:35.171382
8595 01:32:35.173565 Set Vref, RX VrefLevel [Byte0]: 24
8596 01:32:35.176846 [Byte1]: 24
8597 01:32:35.177413
8598 01:32:35.180142 Set Vref, RX VrefLevel [Byte0]: 25
8599 01:32:35.183476 [Byte1]: 25
8600 01:32:35.183895
8601 01:32:35.186623 Set Vref, RX VrefLevel [Byte0]: 26
8602 01:32:35.190671 [Byte1]: 26
8603 01:32:35.194028
8604 01:32:35.194473 Set Vref, RX VrefLevel [Byte0]: 27
8605 01:32:35.196836 [Byte1]: 27
8606 01:32:35.201025
8607 01:32:35.201534 Set Vref, RX VrefLevel [Byte0]: 28
8608 01:32:35.204466 [Byte1]: 28
8609 01:32:35.208486
8610 01:32:35.209037 Set Vref, RX VrefLevel [Byte0]: 29
8611 01:32:35.211843 [Byte1]: 29
8612 01:32:35.216067
8613 01:32:35.216621 Set Vref, RX VrefLevel [Byte0]: 30
8614 01:32:35.219795 [Byte1]: 30
8615 01:32:35.223942
8616 01:32:35.224496 Set Vref, RX VrefLevel [Byte0]: 31
8617 01:32:35.226835 [Byte1]: 31
8618 01:32:35.231722
8619 01:32:35.232277 Set Vref, RX VrefLevel [Byte0]: 32
8620 01:32:35.234171 [Byte1]: 32
8621 01:32:35.239781
8622 01:32:35.240344 Set Vref, RX VrefLevel [Byte0]: 33
8623 01:32:35.242010 [Byte1]: 33
8624 01:32:35.246742
8625 01:32:35.247301 Set Vref, RX VrefLevel [Byte0]: 34
8626 01:32:35.250859 [Byte1]: 34
8627 01:32:35.254097
8628 01:32:35.254552 Set Vref, RX VrefLevel [Byte0]: 35
8629 01:32:35.257470 [Byte1]: 35
8630 01:32:35.261591
8631 01:32:35.262145 Set Vref, RX VrefLevel [Byte0]: 36
8632 01:32:35.264815 [Byte1]: 36
8633 01:32:35.269316
8634 01:32:35.269867 Set Vref, RX VrefLevel [Byte0]: 37
8635 01:32:35.273155 [Byte1]: 37
8636 01:32:35.276692
8637 01:32:35.277243 Set Vref, RX VrefLevel [Byte0]: 38
8638 01:32:35.279993 [Byte1]: 38
8639 01:32:35.284412
8640 01:32:35.284968 Set Vref, RX VrefLevel [Byte0]: 39
8641 01:32:35.287122 [Byte1]: 39
8642 01:32:35.291775
8643 01:32:35.292329 Set Vref, RX VrefLevel [Byte0]: 40
8644 01:32:35.295309 [Byte1]: 40
8645 01:32:35.299260
8646 01:32:35.299714 Set Vref, RX VrefLevel [Byte0]: 41
8647 01:32:35.303254 [Byte1]: 41
8648 01:32:35.307208
8649 01:32:35.307760 Set Vref, RX VrefLevel [Byte0]: 42
8650 01:32:35.310219 [Byte1]: 42
8651 01:32:35.314786
8652 01:32:35.315335 Set Vref, RX VrefLevel [Byte0]: 43
8653 01:32:35.317807 [Byte1]: 43
8654 01:32:35.321936
8655 01:32:35.322475 Set Vref, RX VrefLevel [Byte0]: 44
8656 01:32:35.325733 [Byte1]: 44
8657 01:32:35.329397
8658 01:32:35.329853 Set Vref, RX VrefLevel [Byte0]: 45
8659 01:32:35.333114 [Byte1]: 45
8660 01:32:35.337163
8661 01:32:35.337770 Set Vref, RX VrefLevel [Byte0]: 46
8662 01:32:35.341064 [Byte1]: 46
8663 01:32:35.345239
8664 01:32:35.345819 Set Vref, RX VrefLevel [Byte0]: 47
8665 01:32:35.348039 [Byte1]: 47
8666 01:32:35.352004
8667 01:32:35.352456 Set Vref, RX VrefLevel [Byte0]: 48
8668 01:32:35.356389 [Byte1]: 48
8669 01:32:35.360381
8670 01:32:35.360924 Set Vref, RX VrefLevel [Byte0]: 49
8671 01:32:35.363546 [Byte1]: 49
8672 01:32:35.367773
8673 01:32:35.368319 Set Vref, RX VrefLevel [Byte0]: 50
8674 01:32:35.371070 [Byte1]: 50
8675 01:32:35.375374
8676 01:32:35.375914 Set Vref, RX VrefLevel [Byte0]: 51
8677 01:32:35.378259 [Byte1]: 51
8678 01:32:35.383002
8679 01:32:35.383548 Set Vref, RX VrefLevel [Byte0]: 52
8680 01:32:35.385935 [Byte1]: 52
8681 01:32:35.390319
8682 01:32:35.390864 Set Vref, RX VrefLevel [Byte0]: 53
8683 01:32:35.393248 [Byte1]: 53
8684 01:32:35.397770
8685 01:32:35.398314 Set Vref, RX VrefLevel [Byte0]: 54
8686 01:32:35.401088 [Byte1]: 54
8687 01:32:35.405413
8688 01:32:35.405963 Set Vref, RX VrefLevel [Byte0]: 55
8689 01:32:35.409447 [Byte1]: 55
8690 01:32:35.413011
8691 01:32:35.413647 Set Vref, RX VrefLevel [Byte0]: 56
8692 01:32:35.416254 [Byte1]: 56
8693 01:32:35.421237
8694 01:32:35.421886 Set Vref, RX VrefLevel [Byte0]: 57
8695 01:32:35.423678 [Byte1]: 57
8696 01:32:35.428223
8697 01:32:35.428769 Set Vref, RX VrefLevel [Byte0]: 58
8698 01:32:35.431102 [Byte1]: 58
8699 01:32:35.435631
8700 01:32:35.436088 Set Vref, RX VrefLevel [Byte0]: 59
8701 01:32:35.438898 [Byte1]: 59
8702 01:32:35.443655
8703 01:32:35.444231 Set Vref, RX VrefLevel [Byte0]: 60
8704 01:32:35.447354 [Byte1]: 60
8705 01:32:35.450496
8706 01:32:35.450949 Set Vref, RX VrefLevel [Byte0]: 61
8707 01:32:35.454537 [Byte1]: 61
8708 01:32:35.458436
8709 01:32:35.458977 Set Vref, RX VrefLevel [Byte0]: 62
8710 01:32:35.461393 [Byte1]: 62
8711 01:32:35.465962
8712 01:32:35.466478 Set Vref, RX VrefLevel [Byte0]: 63
8713 01:32:35.469701 [Byte1]: 63
8714 01:32:35.473906
8715 01:32:35.474409 Set Vref, RX VrefLevel [Byte0]: 64
8716 01:32:35.476986 [Byte1]: 64
8717 01:32:35.481532
8718 01:32:35.482033 Set Vref, RX VrefLevel [Byte0]: 65
8719 01:32:35.484620 [Byte1]: 65
8720 01:32:35.488602
8721 01:32:35.489198 Set Vref, RX VrefLevel [Byte0]: 66
8722 01:32:35.492262 [Byte1]: 66
8723 01:32:35.496421
8724 01:32:35.496923 Set Vref, RX VrefLevel [Byte0]: 67
8725 01:32:35.499311 [Byte1]: 67
8726 01:32:35.504703
8727 01:32:35.505221 Set Vref, RX VrefLevel [Byte0]: 68
8728 01:32:35.506971 [Byte1]: 68
8729 01:32:35.511406
8730 01:32:35.512142 Set Vref, RX VrefLevel [Byte0]: 69
8731 01:32:35.514367 [Byte1]: 69
8732 01:32:35.518602
8733 01:32:35.519012 Set Vref, RX VrefLevel [Byte0]: 70
8734 01:32:35.522529 [Byte1]: 70
8735 01:32:35.526719
8736 01:32:35.527221 Final RX Vref Byte 0 = 58 to rank0
8737 01:32:35.529636 Final RX Vref Byte 1 = 59 to rank0
8738 01:32:35.533030 Final RX Vref Byte 0 = 58 to rank1
8739 01:32:35.536232 Final RX Vref Byte 1 = 59 to rank1==
8740 01:32:35.539821 Dram Type= 6, Freq= 0, CH_1, rank 0
8741 01:32:35.546338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 01:32:35.546844 ==
8743 01:32:35.547179 DQS Delay:
8744 01:32:35.549523 DQS0 = 0, DQS1 = 0
8745 01:32:35.550027 DQM Delay:
8746 01:32:35.550459 DQM0 = 133, DQM1 = 128
8747 01:32:35.552676 DQ Delay:
8748 01:32:35.555804 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8749 01:32:35.560134 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =128
8750 01:32:35.562387 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8751 01:32:35.565916 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8752 01:32:35.566332
8753 01:32:35.566656
8754 01:32:35.566959
8755 01:32:35.568898 [DramC_TX_OE_Calibration] TA2
8756 01:32:35.572799 Original DQ_B0 (3 6) =30, OEN = 27
8757 01:32:35.576367 Original DQ_B1 (3 6) =30, OEN = 27
8758 01:32:35.579376 24, 0x0, End_B0=24 End_B1=24
8759 01:32:35.582342 25, 0x0, End_B0=25 End_B1=25
8760 01:32:35.582771 26, 0x0, End_B0=26 End_B1=26
8761 01:32:35.585676 27, 0x0, End_B0=27 End_B1=27
8762 01:32:35.589349 28, 0x0, End_B0=28 End_B1=28
8763 01:32:35.592343 29, 0x0, End_B0=29 End_B1=29
8764 01:32:35.592767 30, 0x0, End_B0=30 End_B1=30
8765 01:32:35.595769 31, 0x4141, End_B0=30 End_B1=30
8766 01:32:35.598508 Byte0 end_step=30 best_step=27
8767 01:32:35.602200 Byte1 end_step=30 best_step=27
8768 01:32:35.605918 Byte0 TX OE(2T, 0.5T) = (3, 3)
8769 01:32:35.608795 Byte1 TX OE(2T, 0.5T) = (3, 3)
8770 01:32:35.609210
8771 01:32:35.609573
8772 01:32:35.615863 [DQSOSCAuto] RK0, (LSB)MR18= 0xe17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
8773 01:32:35.618783 CH1 RK0: MR19=303, MR18=E17
8774 01:32:35.625166 CH1_RK0: MR19=0x303, MR18=0xE17, DQSOSC=398, MR23=63, INC=23, DEC=15
8775 01:32:35.625651
8776 01:32:35.628597 ----->DramcWriteLeveling(PI) begin...
8777 01:32:35.629722 ==
8778 01:32:35.632007 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 01:32:35.635055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 01:32:35.635476 ==
8781 01:32:35.638528 Write leveling (Byte 0): 23 => 23
8782 01:32:35.641566 Write leveling (Byte 1): 24 => 24
8783 01:32:35.644891 DramcWriteLeveling(PI) end<-----
8784 01:32:35.645334
8785 01:32:35.645674 ==
8786 01:32:35.648465 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 01:32:35.654857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 01:32:35.655274 ==
8789 01:32:35.655605 [Gating] SW mode calibration
8790 01:32:35.664631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8791 01:32:35.667817 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8792 01:32:35.671095 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 01:32:35.677636 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 01:32:35.680975 1 4 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8795 01:32:35.687545 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8796 01:32:35.690705 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 01:32:35.694127 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 01:32:35.697233 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 01:32:35.703972 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 01:32:35.707411 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 01:32:35.713818 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8802 01:32:35.717617 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8803 01:32:35.720991 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8804 01:32:35.724251 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8805 01:32:35.730674 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 01:32:35.733552 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 01:32:35.740703 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 01:32:35.743297 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 01:32:35.747094 1 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8810 01:32:35.753347 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8811 01:32:35.756891 1 6 12 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8812 01:32:35.760806 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 01:32:35.763720 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 01:32:35.770003 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 01:32:35.773139 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 01:32:35.780434 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 01:32:35.783043 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 01:32:35.786641 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8819 01:32:35.793171 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8820 01:32:35.796700 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8821 01:32:35.799847 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 01:32:35.806759 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 01:32:35.809749 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 01:32:35.812778 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 01:32:35.819753 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 01:32:35.822793 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 01:32:35.825619 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 01:32:35.832869 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 01:32:35.835768 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 01:32:35.839913 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 01:32:35.845509 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 01:32:35.848909 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 01:32:35.852424 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8834 01:32:35.859176 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8835 01:32:35.863465 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8836 01:32:35.865032 Total UI for P1: 0, mck2ui 16
8837 01:32:35.868410 best dqsien dly found for B0: ( 1, 9, 6)
8838 01:32:35.871942 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 01:32:35.875088 Total UI for P1: 0, mck2ui 16
8840 01:32:35.878452 best dqsien dly found for B1: ( 1, 9, 10)
8841 01:32:35.881766 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8842 01:32:35.884811 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8843 01:32:35.885246
8844 01:32:35.891502 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8845 01:32:35.894368 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8846 01:32:35.898512 [Gating] SW calibration Done
8847 01:32:35.899018 ==
8848 01:32:35.901186 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 01:32:35.904529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 01:32:35.905040 ==
8851 01:32:35.905422 RX Vref Scan: 0
8852 01:32:35.905742
8853 01:32:35.907849 RX Vref 0 -> 0, step: 1
8854 01:32:35.908351
8855 01:32:35.911423 RX Delay 0 -> 252, step: 8
8856 01:32:35.914771 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8857 01:32:35.918412 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8858 01:32:35.924427 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8859 01:32:35.928362 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8860 01:32:35.931413 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8861 01:32:35.933843 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8862 01:32:35.937924 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8863 01:32:35.944312 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8864 01:32:35.947350 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8865 01:32:35.950697 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8866 01:32:35.953786 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8867 01:32:35.957616 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8868 01:32:35.964401 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8869 01:32:35.967031 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8870 01:32:35.970526 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8871 01:32:35.974441 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8872 01:32:35.974988 ==
8873 01:32:35.977128 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 01:32:35.983715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 01:32:35.984265 ==
8876 01:32:35.984625 DQS Delay:
8877 01:32:35.986609 DQS0 = 0, DQS1 = 0
8878 01:32:35.987061 DQM Delay:
8879 01:32:35.990003 DQM0 = 133, DQM1 = 130
8880 01:32:35.990457 DQ Delay:
8881 01:32:35.993445 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =131
8882 01:32:35.996869 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8883 01:32:36.000136 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8884 01:32:36.003393 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8885 01:32:36.003919
8886 01:32:36.004253
8887 01:32:36.004558 ==
8888 01:32:36.006698 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 01:32:36.013349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 01:32:36.013854 ==
8891 01:32:36.014187
8892 01:32:36.014492
8893 01:32:36.014784 TX Vref Scan disable
8894 01:32:36.016887 == TX Byte 0 ==
8895 01:32:36.019613 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8896 01:32:36.026637 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8897 01:32:36.027145 == TX Byte 1 ==
8898 01:32:36.029874 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8899 01:32:36.036621 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8900 01:32:36.037161 ==
8901 01:32:36.040928 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 01:32:36.042980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 01:32:36.043437 ==
8904 01:32:36.056867
8905 01:32:36.059778 TX Vref early break, caculate TX vref
8906 01:32:36.063470 TX Vref=16, minBit 1, minWin=23, winSum=380
8907 01:32:36.066325 TX Vref=18, minBit 9, minWin=23, winSum=387
8908 01:32:36.069815 TX Vref=20, minBit 9, minWin=23, winSum=398
8909 01:32:36.073007 TX Vref=22, minBit 9, minWin=24, winSum=407
8910 01:32:36.076751 TX Vref=24, minBit 5, minWin=25, winSum=416
8911 01:32:36.082920 TX Vref=26, minBit 9, minWin=24, winSum=421
8912 01:32:36.086033 TX Vref=28, minBit 13, minWin=25, winSum=422
8913 01:32:36.089759 TX Vref=30, minBit 5, minWin=25, winSum=419
8914 01:32:36.092534 TX Vref=32, minBit 0, minWin=25, winSum=413
8915 01:32:36.095778 TX Vref=34, minBit 0, minWin=24, winSum=403
8916 01:32:36.102570 TX Vref=36, minBit 0, minWin=24, winSum=398
8917 01:32:36.106431 [TxChooseVref] Worse bit 13, Min win 25, Win sum 422, Final Vref 28
8918 01:32:36.106889
8919 01:32:36.108996 Final TX Range 0 Vref 28
8920 01:32:36.109503
8921 01:32:36.109871 ==
8922 01:32:36.112121 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 01:32:36.115597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 01:32:36.118762 ==
8925 01:32:36.119175
8926 01:32:36.119503
8927 01:32:36.119808 TX Vref Scan disable
8928 01:32:36.125742 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8929 01:32:36.126239 == TX Byte 0 ==
8930 01:32:36.128787 u2DelayCellOfst[0]=14 cells (4 PI)
8931 01:32:36.132300 u2DelayCellOfst[1]=10 cells (3 PI)
8932 01:32:36.135888 u2DelayCellOfst[2]=0 cells (0 PI)
8933 01:32:36.138753 u2DelayCellOfst[3]=7 cells (2 PI)
8934 01:32:36.142177 u2DelayCellOfst[4]=10 cells (3 PI)
8935 01:32:36.145531 u2DelayCellOfst[5]=17 cells (5 PI)
8936 01:32:36.148967 u2DelayCellOfst[6]=14 cells (4 PI)
8937 01:32:36.152247 u2DelayCellOfst[7]=7 cells (2 PI)
8938 01:32:36.155514 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8939 01:32:36.158684 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8940 01:32:36.161970 == TX Byte 1 ==
8941 01:32:36.166222 u2DelayCellOfst[8]=0 cells (0 PI)
8942 01:32:36.168974 u2DelayCellOfst[9]=0 cells (0 PI)
8943 01:32:36.172002 u2DelayCellOfst[10]=10 cells (3 PI)
8944 01:32:36.176552 u2DelayCellOfst[11]=3 cells (1 PI)
8945 01:32:36.178296 u2DelayCellOfst[12]=14 cells (4 PI)
8946 01:32:36.181884 u2DelayCellOfst[13]=14 cells (4 PI)
8947 01:32:36.185801 u2DelayCellOfst[14]=17 cells (5 PI)
8948 01:32:36.188289 u2DelayCellOfst[15]=17 cells (5 PI)
8949 01:32:36.191600 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8950 01:32:36.194982 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8951 01:32:36.198344 DramC Write-DBI on
8952 01:32:36.198800 ==
8953 01:32:36.201310 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 01:32:36.205027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 01:32:36.205611 ==
8956 01:32:36.205952
8957 01:32:36.206261
8958 01:32:36.208279 TX Vref Scan disable
8959 01:32:36.208786 == TX Byte 0 ==
8960 01:32:36.215119 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8961 01:32:36.215681 == TX Byte 1 ==
8962 01:32:36.217833 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8963 01:32:36.221475 DramC Write-DBI off
8964 01:32:36.221977
8965 01:32:36.222309 [DATLAT]
8966 01:32:36.224346 Freq=1600, CH1 RK1
8967 01:32:36.224787
8968 01:32:36.225118 DATLAT Default: 0xf
8969 01:32:36.227971 0, 0xFFFF, sum = 0
8970 01:32:36.231294 1, 0xFFFF, sum = 0
8971 01:32:36.231845 2, 0xFFFF, sum = 0
8972 01:32:36.234240 3, 0xFFFF, sum = 0
8973 01:32:36.234762 4, 0xFFFF, sum = 0
8974 01:32:36.237498 5, 0xFFFF, sum = 0
8975 01:32:36.237935 6, 0xFFFF, sum = 0
8976 01:32:36.241590 7, 0xFFFF, sum = 0
8977 01:32:36.242094 8, 0xFFFF, sum = 0
8978 01:32:36.244677 9, 0xFFFF, sum = 0
8979 01:32:36.245220 10, 0xFFFF, sum = 0
8980 01:32:36.247802 11, 0xFFFF, sum = 0
8981 01:32:36.248346 12, 0xFFFF, sum = 0
8982 01:32:36.250827 13, 0xFFFF, sum = 0
8983 01:32:36.251282 14, 0x0, sum = 1
8984 01:32:36.254410 15, 0x0, sum = 2
8985 01:32:36.255059 16, 0x0, sum = 3
8986 01:32:36.258146 17, 0x0, sum = 4
8987 01:32:36.258759 best_step = 15
8988 01:32:36.259341
8989 01:32:36.259699 ==
8990 01:32:36.260755 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 01:32:36.266932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 01:32:36.267478 ==
8993 01:32:36.267840 RX Vref Scan: 0
8994 01:32:36.268172
8995 01:32:36.271487 RX Vref 0 -> 0, step: 1
8996 01:32:36.271901
8997 01:32:36.273606 RX Delay 11 -> 252, step: 4
8998 01:32:36.277624 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8999 01:32:36.280591 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9000 01:32:36.287444 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9001 01:32:36.290968 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9002 01:32:36.294210 iDelay=195, Bit 4, Center 128 (71 ~ 186) 116
9003 01:32:36.296742 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9004 01:32:36.300658 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9005 01:32:36.306587 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9006 01:32:36.310513 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9007 01:32:36.313422 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
9008 01:32:36.316838 iDelay=195, Bit 10, Center 132 (79 ~ 186) 108
9009 01:32:36.320073 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9010 01:32:36.326585 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9011 01:32:36.330004 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9012 01:32:36.333867 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9013 01:32:36.336460 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9014 01:32:36.336930 ==
9015 01:32:36.340168 Dram Type= 6, Freq= 0, CH_1, rank 1
9016 01:32:36.346538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9017 01:32:36.347033 ==
9018 01:32:36.347373 DQS Delay:
9019 01:32:36.349385 DQS0 = 0, DQS1 = 0
9020 01:32:36.349932 DQM Delay:
9021 01:32:36.353135 DQM0 = 130, DQM1 = 127
9022 01:32:36.353723 DQ Delay:
9023 01:32:36.356205 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9024 01:32:36.359642 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =126
9025 01:32:36.362985 DQ8 =114, DQ9 =116, DQ10 =132, DQ11 =120
9026 01:32:36.366313 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9027 01:32:36.366722
9028 01:32:36.367213
9029 01:32:36.367595
9030 01:32:36.369134 [DramC_TX_OE_Calibration] TA2
9031 01:32:36.372322 Original DQ_B0 (3 6) =30, OEN = 27
9032 01:32:36.376413 Original DQ_B1 (3 6) =30, OEN = 27
9033 01:32:36.379089 24, 0x0, End_B0=24 End_B1=24
9034 01:32:36.382503 25, 0x0, End_B0=25 End_B1=25
9035 01:32:36.383013 26, 0x0, End_B0=26 End_B1=26
9036 01:32:36.386293 27, 0x0, End_B0=27 End_B1=27
9037 01:32:36.389893 28, 0x0, End_B0=28 End_B1=28
9038 01:32:36.392363 29, 0x0, End_B0=29 End_B1=29
9039 01:32:36.395612 30, 0x0, End_B0=30 End_B1=30
9040 01:32:36.396028 31, 0x4141, End_B0=30 End_B1=30
9041 01:32:36.398746 Byte0 end_step=30 best_step=27
9042 01:32:36.402563 Byte1 end_step=30 best_step=27
9043 01:32:36.405850 Byte0 TX OE(2T, 0.5T) = (3, 3)
9044 01:32:36.408573 Byte1 TX OE(2T, 0.5T) = (3, 3)
9045 01:32:36.408979
9046 01:32:36.409366
9047 01:32:36.415495 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 403 ps
9048 01:32:36.418843 CH1 RK1: MR19=303, MR18=D1C
9049 01:32:36.425803 CH1_RK1: MR19=0x303, MR18=0xD1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9050 01:32:36.428828 [RxdqsGatingPostProcess] freq 1600
9051 01:32:36.435010 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9052 01:32:36.435622 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 01:32:36.438189 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 01:32:36.442166 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 01:32:36.445156 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 01:32:36.448500 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 01:32:36.451666 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 01:32:36.455096 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 01:32:36.458326 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 01:32:36.461374 Pre-setting of DQS Precalculation
9061 01:32:36.465229 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9062 01:32:36.474778 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9063 01:32:36.481102 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 01:32:36.481558
9065 01:32:36.481888
9066 01:32:36.484403 [Calibration Summary] 3200 Mbps
9067 01:32:36.484815 CH 0, Rank 0
9068 01:32:36.487972 SW Impedance : PASS
9069 01:32:36.488386 DUTY Scan : NO K
9070 01:32:36.491741 ZQ Calibration : PASS
9071 01:32:36.494454 Jitter Meter : NO K
9072 01:32:36.494873 CBT Training : PASS
9073 01:32:36.498483 Write leveling : PASS
9074 01:32:36.501381 RX DQS gating : PASS
9075 01:32:36.501798 RX DQ/DQS(RDDQC) : PASS
9076 01:32:36.504803 TX DQ/DQS : PASS
9077 01:32:36.507845 RX DATLAT : PASS
9078 01:32:36.508373 RX DQ/DQS(Engine): PASS
9079 01:32:36.511794 TX OE : PASS
9080 01:32:36.512339 All Pass.
9081 01:32:36.512705
9082 01:32:36.514068 CH 0, Rank 1
9083 01:32:36.514523 SW Impedance : PASS
9084 01:32:36.517361 DUTY Scan : NO K
9085 01:32:36.520797 ZQ Calibration : PASS
9086 01:32:36.521401 Jitter Meter : NO K
9087 01:32:36.524152 CBT Training : PASS
9088 01:32:36.527436 Write leveling : PASS
9089 01:32:36.527982 RX DQS gating : PASS
9090 01:32:36.530745 RX DQ/DQS(RDDQC) : PASS
9091 01:32:36.534200 TX DQ/DQS : PASS
9092 01:32:36.534752 RX DATLAT : PASS
9093 01:32:36.536920 RX DQ/DQS(Engine): PASS
9094 01:32:36.540336 TX OE : PASS
9095 01:32:36.540887 All Pass.
9096 01:32:36.541249
9097 01:32:36.541671 CH 1, Rank 0
9098 01:32:36.543574 SW Impedance : PASS
9099 01:32:36.547516 DUTY Scan : NO K
9100 01:32:36.548066 ZQ Calibration : PASS
9101 01:32:36.550005 Jitter Meter : NO K
9102 01:32:36.554083 CBT Training : PASS
9103 01:32:36.554703 Write leveling : PASS
9104 01:32:36.557233 RX DQS gating : PASS
9105 01:32:36.560059 RX DQ/DQS(RDDQC) : PASS
9106 01:32:36.560604 TX DQ/DQS : PASS
9107 01:32:36.563957 RX DATLAT : PASS
9108 01:32:36.567522 RX DQ/DQS(Engine): PASS
9109 01:32:36.568079 TX OE : PASS
9110 01:32:36.568445 All Pass.
9111 01:32:36.570342
9112 01:32:36.570887 CH 1, Rank 1
9113 01:32:36.573682 SW Impedance : PASS
9114 01:32:36.574226 DUTY Scan : NO K
9115 01:32:36.577112 ZQ Calibration : PASS
9116 01:32:36.580063 Jitter Meter : NO K
9117 01:32:36.580604 CBT Training : PASS
9118 01:32:36.583056 Write leveling : PASS
9119 01:32:36.583515 RX DQS gating : PASS
9120 01:32:36.586949 RX DQ/DQS(RDDQC) : PASS
9121 01:32:36.589763 TX DQ/DQS : PASS
9122 01:32:36.590317 RX DATLAT : PASS
9123 01:32:36.592942 RX DQ/DQS(Engine): PASS
9124 01:32:36.595958 TX OE : PASS
9125 01:32:36.596434 All Pass.
9126 01:32:36.596796
9127 01:32:36.599532 DramC Write-DBI on
9128 01:32:36.599988 PER_BANK_REFRESH: Hybrid Mode
9129 01:32:36.602826 TX_TRACKING: ON
9130 01:32:36.613079 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9131 01:32:36.619220 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9132 01:32:36.626527 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 01:32:36.628989 [FAST_K] Save calibration result to emmc
9134 01:32:36.632669 sync common calibartion params.
9135 01:32:36.635590 sync cbt_mode0:1, 1:1
9136 01:32:36.639792 dram_init: ddr_geometry: 2
9137 01:32:36.640337 dram_init: ddr_geometry: 2
9138 01:32:36.642452 dram_init: ddr_geometry: 2
9139 01:32:36.645436 0:dram_rank_size:100000000
9140 01:32:36.649157 1:dram_rank_size:100000000
9141 01:32:36.652330 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9142 01:32:36.655255 DFS_SHUFFLE_HW_MODE: ON
9143 01:32:36.658577 dramc_set_vcore_voltage set vcore to 725000
9144 01:32:36.661736 Read voltage for 1600, 0
9145 01:32:36.662194 Vio18 = 0
9146 01:32:36.662554 Vcore = 725000
9147 01:32:36.665215 Vdram = 0
9148 01:32:36.665686 Vddq = 0
9149 01:32:36.666018 Vmddr = 0
9150 01:32:36.668227 switch to 3200 Mbps bootup
9151 01:32:36.672234 [DramcRunTimeConfig]
9152 01:32:36.672904 PHYPLL
9153 01:32:36.673444 DPM_CONTROL_AFTERK: ON
9154 01:32:36.675043 PER_BANK_REFRESH: ON
9155 01:32:36.678670 REFRESH_OVERHEAD_REDUCTION: ON
9156 01:32:36.682735 CMD_PICG_NEW_MODE: OFF
9157 01:32:36.683242 XRTWTW_NEW_MODE: ON
9158 01:32:36.684747 XRTRTR_NEW_MODE: ON
9159 01:32:36.685162 TX_TRACKING: ON
9160 01:32:36.688591 RDSEL_TRACKING: OFF
9161 01:32:36.689095 DQS Precalculation for DVFS: ON
9162 01:32:36.691837 RX_TRACKING: OFF
9163 01:32:36.692394 HW_GATING DBG: ON
9164 01:32:36.694772 ZQCS_ENABLE_LP4: ON
9165 01:32:36.698068 RX_PICG_NEW_MODE: ON
9166 01:32:36.698480 TX_PICG_NEW_MODE: ON
9167 01:32:36.701209 ENABLE_RX_DCM_DPHY: ON
9168 01:32:36.704799 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9169 01:32:36.705221 DUMMY_READ_FOR_TRACKING: OFF
9170 01:32:36.707573 !!! SPM_CONTROL_AFTERK: OFF
9171 01:32:36.711351 !!! SPM could not control APHY
9172 01:32:36.714615 IMPEDANCE_TRACKING: ON
9173 01:32:36.715030 TEMP_SENSOR: ON
9174 01:32:36.718014 HW_SAVE_FOR_SR: OFF
9175 01:32:36.720904 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9176 01:32:36.724231 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9177 01:32:36.724672 Read ODT Tracking: ON
9178 01:32:36.727557 Refresh Rate DeBounce: ON
9179 01:32:36.730657 DFS_NO_QUEUE_FLUSH: ON
9180 01:32:36.733940 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9181 01:32:36.734356 ENABLE_DFS_RUNTIME_MRW: OFF
9182 01:32:36.737340 DDR_RESERVE_NEW_MODE: ON
9183 01:32:36.740772 MR_CBT_SWITCH_FREQ: ON
9184 01:32:36.741326 =========================
9185 01:32:36.761313 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9186 01:32:36.764252 dram_init: ddr_geometry: 2
9187 01:32:36.782486 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9188 01:32:36.785759 dram_init: dram init end (result: 0)
9189 01:32:36.792561 DRAM-K: Full calibration passed in 24441 msecs
9190 01:32:36.795560 MRC: failed to locate region type 0.
9191 01:32:36.795988 DRAM rank0 size:0x100000000,
9192 01:32:36.798791 DRAM rank1 size=0x100000000
9193 01:32:36.809390 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9194 01:32:36.815157 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9195 01:32:36.822119 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9196 01:32:36.831900 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9197 01:32:36.832404 DRAM rank0 size:0x100000000,
9198 01:32:36.835092 DRAM rank1 size=0x100000000
9199 01:32:36.835606 CBMEM:
9200 01:32:36.838099 IMD: root @ 0xfffff000 254 entries.
9201 01:32:36.841910 IMD: root @ 0xffffec00 62 entries.
9202 01:32:36.845596 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9203 01:32:36.851670 WARNING: RO_VPD is uninitialized or empty.
9204 01:32:36.854936 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9205 01:32:36.862497 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9206 01:32:36.875902 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9207 01:32:36.886899 BS: romstage times (exec / console): total (unknown) / 23976 ms
9208 01:32:36.887317
9209 01:32:36.887645
9210 01:32:36.896650 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9211 01:32:36.899837 ARM64: Exception handlers installed.
9212 01:32:36.902970 ARM64: Testing exception
9213 01:32:36.906845 ARM64: Done test exception
9214 01:32:36.907354 Enumerating buses...
9215 01:32:36.909858 Show all devs... Before device enumeration.
9216 01:32:36.913204 Root Device: enabled 1
9217 01:32:36.916547 CPU_CLUSTER: 0: enabled 1
9218 01:32:36.917063 CPU: 00: enabled 1
9219 01:32:36.919987 Compare with tree...
9220 01:32:36.920510 Root Device: enabled 1
9221 01:32:36.923174 CPU_CLUSTER: 0: enabled 1
9222 01:32:36.926054 CPU: 00: enabled 1
9223 01:32:36.926481 Root Device scanning...
9224 01:32:36.929922 scan_static_bus for Root Device
9225 01:32:36.932905 CPU_CLUSTER: 0 enabled
9226 01:32:36.936483 scan_static_bus for Root Device done
9227 01:32:36.939389 scan_bus: bus Root Device finished in 8 msecs
9228 01:32:36.939850 done
9229 01:32:36.946329 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9230 01:32:36.949292 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9231 01:32:36.955608 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9232 01:32:36.962338 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9233 01:32:36.962876 Allocating resources...
9234 01:32:36.965986 Reading resources...
9235 01:32:36.968845 Root Device read_resources bus 0 link: 0
9236 01:32:36.972762 DRAM rank0 size:0x100000000,
9237 01:32:36.973311 DRAM rank1 size=0x100000000
9238 01:32:36.979038 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9239 01:32:36.979590 CPU: 00 missing read_resources
9240 01:32:36.985352 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9241 01:32:36.988559 Root Device read_resources bus 0 link: 0 done
9242 01:32:36.992179 Done reading resources.
9243 01:32:36.995447 Show resources in subtree (Root Device)...After reading.
9244 01:32:36.999094 Root Device child on link 0 CPU_CLUSTER: 0
9245 01:32:37.002268 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 01:32:37.012236 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 01:32:37.012791 CPU: 00
9248 01:32:37.018743 Root Device assign_resources, bus 0 link: 0
9249 01:32:37.022021 CPU_CLUSTER: 0 missing set_resources
9250 01:32:37.025860 Root Device assign_resources, bus 0 link: 0 done
9251 01:32:37.029319 Done setting resources.
9252 01:32:37.031927 Show resources in subtree (Root Device)...After assigning values.
9253 01:32:37.034775 Root Device child on link 0 CPU_CLUSTER: 0
9254 01:32:37.041768 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 01:32:37.048068 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 01:32:37.051511 CPU: 00
9257 01:32:37.052058 Done allocating resources.
9258 01:32:37.058750 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9259 01:32:37.059304 Enabling resources...
9260 01:32:37.061585 done.
9261 01:32:37.065559 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9262 01:32:37.068130 Initializing devices...
9263 01:32:37.068611 Root Device init
9264 01:32:37.071412 init hardware done!
9265 01:32:37.071879 0x00000018: ctrlr->caps
9266 01:32:37.074493 52.000 MHz: ctrlr->f_max
9267 01:32:37.077733 0.400 MHz: ctrlr->f_min
9268 01:32:37.080900 0x40ff8080: ctrlr->voltages
9269 01:32:37.081347 sclk: 390625
9270 01:32:37.081696 Bus Width = 1
9271 01:32:37.084099 sclk: 390625
9272 01:32:37.084501 Bus Width = 1
9273 01:32:37.088239 Early init status = 3
9274 01:32:37.090609 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9275 01:32:37.094861 in-header: 03 fc 00 00 01 00 00 00
9276 01:32:37.097381 in-data: 00
9277 01:32:37.100852 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9278 01:32:37.105365 in-header: 03 fd 00 00 00 00 00 00
9279 01:32:37.109071 in-data:
9280 01:32:37.112353 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9281 01:32:37.116308 in-header: 03 fc 00 00 01 00 00 00
9282 01:32:37.120296 in-data: 00
9283 01:32:37.123030 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9284 01:32:37.128915 in-header: 03 fd 00 00 00 00 00 00
9285 01:32:37.132940 in-data:
9286 01:32:37.135455 [SSUSB] Setting up USB HOST controller...
9287 01:32:37.138349 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9288 01:32:37.142116 [SSUSB] phy power-on done.
9289 01:32:37.145612 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9290 01:32:37.152473 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9291 01:32:37.155329 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9292 01:32:37.161496 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9293 01:32:37.168418 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9294 01:32:37.174927 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9295 01:32:37.181794 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9296 01:32:37.188440 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9297 01:32:37.190903 SPM: binary array size = 0x9dc
9298 01:32:37.194923 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9299 01:32:37.200843 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9300 01:32:37.207389 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9301 01:32:37.213963 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9302 01:32:37.217876 configure_display: Starting display init
9303 01:32:37.251587 anx7625_power_on_init: Init interface.
9304 01:32:37.255454 anx7625_disable_pd_protocol: Disabled PD feature.
9305 01:32:37.258580 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9306 01:32:37.286270 anx7625_start_dp_work: Secure OCM version=00
9307 01:32:37.289653 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9308 01:32:37.304785 sp_tx_get_edid_block: EDID Block = 1
9309 01:32:37.407511 Extracted contents:
9310 01:32:37.410712 header: 00 ff ff ff ff ff ff 00
9311 01:32:37.413727 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9312 01:32:37.416985 version: 01 04
9313 01:32:37.420309 basic params: 95 1f 11 78 0a
9314 01:32:37.423328 chroma info: 76 90 94 55 54 90 27 21 50 54
9315 01:32:37.426914 established: 00 00 00
9316 01:32:37.434387 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9317 01:32:37.439526 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9318 01:32:37.442940 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9319 01:32:37.449730 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9320 01:32:37.456750 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9321 01:32:37.459498 extensions: 00
9322 01:32:37.459961 checksum: fb
9323 01:32:37.460316
9324 01:32:37.465787 Manufacturer: IVO Model 57d Serial Number 0
9325 01:32:37.466198 Made week 0 of 2020
9326 01:32:37.469405 EDID version: 1.4
9327 01:32:37.469918 Digital display
9328 01:32:37.472571 6 bits per primary color channel
9329 01:32:37.475952 DisplayPort interface
9330 01:32:37.476457 Maximum image size: 31 cm x 17 cm
9331 01:32:37.479364 Gamma: 220%
9332 01:32:37.479914 Check DPMS levels
9333 01:32:37.486138 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9334 01:32:37.489249 First detailed timing is preferred timing
9335 01:32:37.489699 Established timings supported:
9336 01:32:37.492342 Standard timings supported:
9337 01:32:37.496101 Detailed timings
9338 01:32:37.498773 Hex of detail: 383680a07038204018303c0035ae10000019
9339 01:32:37.505691 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9340 01:32:37.509429 0780 0798 07c8 0820 hborder 0
9341 01:32:37.512138 0438 043b 0447 0458 vborder 0
9342 01:32:37.515602 -hsync -vsync
9343 01:32:37.516279 Did detailed timing
9344 01:32:37.522285 Hex of detail: 000000000000000000000000000000000000
9345 01:32:37.525914 Manufacturer-specified data, tag 0
9346 01:32:37.529396 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9347 01:32:37.532764 ASCII string: InfoVision
9348 01:32:37.535441 Hex of detail: 000000fe00523134304e574635205248200a
9349 01:32:37.538774 ASCII string: R140NWF5 RH
9350 01:32:37.539184 Checksum
9351 01:32:37.542099 Checksum: 0xfb (valid)
9352 01:32:37.545396 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9353 01:32:37.548653 DSI data_rate: 832800000 bps
9354 01:32:37.555091 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9355 01:32:37.558323 anx7625_parse_edid: pixelclock(138800).
9356 01:32:37.561419 hactive(1920), hsync(48), hfp(24), hbp(88)
9357 01:32:37.565109 vactive(1080), vsync(12), vfp(3), vbp(17)
9358 01:32:37.568775 anx7625_dsi_config: config dsi.
9359 01:32:37.574903 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9360 01:32:37.588686 anx7625_dsi_config: success to config DSI
9361 01:32:37.592151 anx7625_dp_start: MIPI phy setup OK.
9362 01:32:37.595566 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9363 01:32:37.598643 mtk_ddp_mode_set invalid vrefresh 60
9364 01:32:37.602179 main_disp_path_setup
9365 01:32:37.602596 ovl_layer_smi_id_en
9366 01:32:37.605208 ovl_layer_smi_id_en
9367 01:32:37.605759 ccorr_config
9368 01:32:37.606076 aal_config
9369 01:32:37.608328 gamma_config
9370 01:32:37.608731 postmask_config
9371 01:32:37.612359 dither_config
9372 01:32:37.614989 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9373 01:32:37.621551 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9374 01:32:37.624932 Root Device init finished in 553 msecs
9375 01:32:37.628953 CPU_CLUSTER: 0 init
9376 01:32:37.635782 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9377 01:32:37.641106 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9378 01:32:37.641561 APU_MBOX 0x190000b0 = 0x10001
9379 01:32:37.645587 APU_MBOX 0x190001b0 = 0x10001
9380 01:32:37.648158 APU_MBOX 0x190005b0 = 0x10001
9381 01:32:37.651117 APU_MBOX 0x190006b0 = 0x10001
9382 01:32:37.658719 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9383 01:32:37.667661 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9384 01:32:37.681107 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9385 01:32:37.686915 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9386 01:32:37.699177 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9387 01:32:37.707938 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9388 01:32:37.710786 CPU_CLUSTER: 0 init finished in 81 msecs
9389 01:32:37.714288 Devices initialized
9390 01:32:37.717673 Show all devs... After init.
9391 01:32:37.718209 Root Device: enabled 1
9392 01:32:37.720522 CPU_CLUSTER: 0: enabled 1
9393 01:32:37.724361 CPU: 00: enabled 1
9394 01:32:37.727481 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9395 01:32:37.730547 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9396 01:32:37.734493 ELOG: NV offset 0x57f000 size 0x1000
9397 01:32:37.740444 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9398 01:32:37.747881 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9399 01:32:37.750827 ELOG: Event(17) added with size 13 at 2024-06-05 01:32:37 UTC
9400 01:32:37.757254 out: cmd=0x121: 03 db 21 01 00 00 00 00
9401 01:32:37.761037 in-header: 03 d7 00 00 2c 00 00 00
9402 01:32:37.770774 in-data: 66 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 01:32:37.777240 ELOG: Event(A1) added with size 10 at 2024-06-05 01:32:37 UTC
9404 01:32:37.783920 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9405 01:32:37.789946 ELOG: Event(A0) added with size 9 at 2024-06-05 01:32:37 UTC
9406 01:32:37.794426 elog_add_boot_reason: Logged dev mode boot
9407 01:32:37.799755 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9408 01:32:37.800316 Finalize devices...
9409 01:32:37.803920 Devices finalized
9410 01:32:37.806449 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9411 01:32:37.809844 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9412 01:32:37.813407 in-header: 03 07 00 00 08 00 00 00
9413 01:32:37.816617 in-data: aa e4 47 04 13 02 00 00
9414 01:32:37.819788 Chrome EC: UHEPI supported
9415 01:32:37.826151 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9416 01:32:37.829634 in-header: 03 a9 00 00 08 00 00 00
9417 01:32:37.832974 in-data: 84 60 60 08 00 00 00 00
9418 01:32:37.839259 ELOG: Event(91) added with size 10 at 2024-06-05 01:32:37 UTC
9419 01:32:37.842498 Chrome EC: clear events_b mask to 0x0000000020004000
9420 01:32:37.849444 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9421 01:32:37.853196 in-header: 03 fd 00 00 00 00 00 00
9422 01:32:37.856657 in-data:
9423 01:32:37.860586 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9424 01:32:37.863614 Writing coreboot table at 0xffe64000
9425 01:32:37.869628 0. 000000000010a000-0000000000113fff: RAMSTAGE
9426 01:32:37.873376 1. 0000000040000000-00000000400fffff: RAM
9427 01:32:37.877304 2. 0000000040100000-000000004032afff: RAMSTAGE
9428 01:32:37.880237 3. 000000004032b000-00000000545fffff: RAM
9429 01:32:37.883993 4. 0000000054600000-000000005465ffff: BL31
9430 01:32:37.886352 5. 0000000054660000-00000000ffe63fff: RAM
9431 01:32:37.892835 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9432 01:32:37.896760 7. 0000000100000000-000000023fffffff: RAM
9433 01:32:37.899919 Passing 5 GPIOs to payload:
9434 01:32:37.902951 NAME | PORT | POLARITY | VALUE
9435 01:32:37.909451 EC in RW | 0x000000aa | low | undefined
9436 01:32:37.913252 EC interrupt | 0x00000005 | low | undefined
9437 01:32:37.919146 TPM interrupt | 0x000000ab | high | undefined
9438 01:32:37.922696 SD card detect | 0x00000011 | high | undefined
9439 01:32:37.926072 speaker enable | 0x00000093 | high | undefined
9440 01:32:37.932843 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9441 01:32:37.936024 in-header: 03 f9 00 00 02 00 00 00
9442 01:32:37.936430 in-data: 02 00
9443 01:32:37.939302 ADC[4]: Raw value=901847 ID=7
9444 01:32:37.942428 ADC[3]: Raw value=213546 ID=1
9445 01:32:37.942869 RAM Code: 0x71
9446 01:32:37.945749 ADC[6]: Raw value=75000 ID=0
9447 01:32:37.949480 ADC[5]: Raw value=213546 ID=1
9448 01:32:37.949888 SKU Code: 0x1
9449 01:32:37.955991 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f9d9
9450 01:32:37.958669 coreboot table: 964 bytes.
9451 01:32:37.962080 IMD ROOT 0. 0xfffff000 0x00001000
9452 01:32:37.965350 IMD SMALL 1. 0xffffe000 0x00001000
9453 01:32:37.968997 RO MCACHE 2. 0xffffc000 0x00001104
9454 01:32:37.971962 CONSOLE 3. 0xfff7c000 0x00080000
9455 01:32:37.975442 FMAP 4. 0xfff7b000 0x00000452
9456 01:32:37.979123 TIME STAMP 5. 0xfff7a000 0x00000910
9457 01:32:37.981929 VBOOT WORK 6. 0xfff66000 0x00014000
9458 01:32:37.985239 RAMOOPS 7. 0xffe66000 0x00100000
9459 01:32:37.985820 COREBOOT 8. 0xffe64000 0x00002000
9460 01:32:37.988949 IMD small region:
9461 01:32:37.992154 IMD ROOT 0. 0xffffec00 0x00000400
9462 01:32:37.995219 VPD 1. 0xffffeb80 0x0000006c
9463 01:32:37.998530 MMC STATUS 2. 0xffffeb60 0x00000004
9464 01:32:38.005568 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9465 01:32:38.012396 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9466 01:32:38.051231 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9467 01:32:38.053627 Checking segment from ROM address 0x40100000
9468 01:32:38.060762 Checking segment from ROM address 0x4010001c
9469 01:32:38.064182 Loading segment from ROM address 0x40100000
9470 01:32:38.064687 code (compression=0)
9471 01:32:38.073608 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9472 01:32:38.080359 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9473 01:32:38.084136 it's not compressed!
9474 01:32:38.086475 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9475 01:32:38.092937 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9476 01:32:38.110884 Loading segment from ROM address 0x4010001c
9477 01:32:38.111301 Entry Point 0x80000000
9478 01:32:38.114746 Loaded segments
9479 01:32:38.118094 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9480 01:32:38.124122 Jumping to boot code at 0x80000000(0xffe64000)
9481 01:32:38.130558 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9482 01:32:38.137164 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9483 01:32:38.145585 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9484 01:32:38.148898 Checking segment from ROM address 0x40100000
9485 01:32:38.151940 Checking segment from ROM address 0x4010001c
9486 01:32:38.159103 Loading segment from ROM address 0x40100000
9487 01:32:38.159697 code (compression=1)
9488 01:32:38.168109 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9489 01:32:38.175048 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9490 01:32:38.175565 using LZMA
9491 01:32:38.183753 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9492 01:32:38.190334 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9493 01:32:38.194179 Loading segment from ROM address 0x4010001c
9494 01:32:38.196756 Entry Point 0x54601000
9495 01:32:38.197171 Loaded segments
9496 01:32:38.200107 NOTICE: MT8192 bl31_setup
9497 01:32:38.207702 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9498 01:32:38.210419 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9499 01:32:38.214060 WARNING: region 0:
9500 01:32:38.217964 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 01:32:38.218488 WARNING: region 1:
9502 01:32:38.224482 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9503 01:32:38.227898 WARNING: region 2:
9504 01:32:38.230775 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9505 01:32:38.233933 WARNING: region 3:
9506 01:32:38.237424 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 01:32:38.240433 WARNING: region 4:
9508 01:32:38.247293 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9509 01:32:38.247828 WARNING: region 5:
9510 01:32:38.250364 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 01:32:38.253328 WARNING: region 6:
9512 01:32:38.256726 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 01:32:38.260405 WARNING: region 7:
9514 01:32:38.263373 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 01:32:38.269971 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9516 01:32:38.273334 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9517 01:32:38.279961 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9518 01:32:38.283040 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9519 01:32:38.286641 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9520 01:32:38.292891 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9521 01:32:38.296394 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9522 01:32:38.300034 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9523 01:32:38.306183 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9524 01:32:38.309848 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9525 01:32:38.316407 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9526 01:32:38.319246 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9527 01:32:38.322991 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9528 01:32:38.329578 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9529 01:32:38.332819 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9530 01:32:38.339228 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9531 01:32:38.342662 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9532 01:32:38.346186 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9533 01:32:38.352680 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9534 01:32:38.356042 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9535 01:32:38.362287 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9536 01:32:38.365115 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9537 01:32:38.368891 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9538 01:32:38.375668 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9539 01:32:38.379249 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9540 01:32:38.385121 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9541 01:32:38.388157 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9542 01:32:38.391867 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9543 01:32:38.398765 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9544 01:32:38.402758 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9545 01:32:38.408656 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9546 01:32:38.411848 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9547 01:32:38.415144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9548 01:32:38.421898 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9549 01:32:38.424778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9550 01:32:38.428286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9551 01:32:38.431209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9552 01:32:38.438229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9553 01:32:38.441278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9554 01:32:38.444998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9555 01:32:38.447741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9556 01:32:38.454808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9557 01:32:38.457472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9558 01:32:38.461311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9559 01:32:38.464391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9560 01:32:38.470805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9561 01:32:38.474859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9562 01:32:38.477832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9563 01:32:38.483934 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9564 01:32:38.487221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9565 01:32:38.493848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9566 01:32:38.497955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9567 01:32:38.500407 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9568 01:32:38.508156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9569 01:32:38.510697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9570 01:32:38.517186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9571 01:32:38.521206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9572 01:32:38.526685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9573 01:32:38.530783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9574 01:32:38.537028 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9575 01:32:38.540679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9576 01:32:38.546975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9577 01:32:38.550201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9578 01:32:38.553342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9579 01:32:38.560480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9580 01:32:38.564111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9581 01:32:38.570144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9582 01:32:38.572893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9583 01:32:38.579793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9584 01:32:38.583018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9585 01:32:38.589528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9586 01:32:38.592845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9587 01:32:38.596499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9588 01:32:38.602829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9589 01:32:38.605830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9590 01:32:38.612467 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9591 01:32:38.615942 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9592 01:32:38.622513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9593 01:32:38.625770 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9594 01:32:38.632847 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9595 01:32:38.635451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9596 01:32:38.642257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9597 01:32:38.645574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9598 01:32:38.649068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9599 01:32:38.655459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9600 01:32:38.658477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9601 01:32:38.665359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9602 01:32:38.668975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9603 01:32:38.675366 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9604 01:32:38.678434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9605 01:32:38.685095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9606 01:32:38.687765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9607 01:32:38.694300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9608 01:32:38.697861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9609 01:32:38.701181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9610 01:32:38.707523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9611 01:32:38.711043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9612 01:32:38.714388 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9613 01:32:38.721052 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9614 01:32:38.724263 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9615 01:32:38.727829 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9616 01:32:38.733826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9617 01:32:38.737451 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9618 01:32:38.743655 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9619 01:32:38.747114 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9620 01:32:38.750373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9621 01:32:38.757814 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9622 01:32:38.760175 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9623 01:32:38.766855 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9624 01:32:38.770140 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9625 01:32:38.773216 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9626 01:32:38.780581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9627 01:32:38.783133 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9628 01:32:38.789903 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9629 01:32:38.793230 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9630 01:32:38.800003 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9631 01:32:38.802758 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9632 01:32:38.806201 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9633 01:32:38.809712 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9634 01:32:38.816877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9635 01:32:38.820135 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9636 01:32:38.823268 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9637 01:32:38.826732 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9638 01:32:38.832954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9639 01:32:38.836160 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9640 01:32:38.842605 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9641 01:32:38.845848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9642 01:32:38.850074 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9643 01:32:38.855797 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9644 01:32:38.859241 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9645 01:32:38.866136 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9646 01:32:38.868836 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9647 01:32:38.872427 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9648 01:32:38.879038 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9649 01:32:38.881835 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9650 01:32:38.888531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9651 01:32:38.892562 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9652 01:32:38.895261 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9653 01:32:38.902738 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9654 01:32:38.905240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9655 01:32:38.912027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9656 01:32:38.915416 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9657 01:32:38.918281 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9658 01:32:38.924745 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9659 01:32:38.927989 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9660 01:32:38.934483 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9661 01:32:38.937853 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9662 01:32:38.941121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9663 01:32:38.947947 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9664 01:32:38.951126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9665 01:32:38.957923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9666 01:32:38.961457 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9667 01:32:38.964391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9668 01:32:38.971106 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9669 01:32:38.974224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9670 01:32:38.980744 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9671 01:32:38.984224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9672 01:32:38.987990 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9673 01:32:38.994547 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9674 01:32:38.997588 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9675 01:32:39.004130 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9676 01:32:39.007221 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9677 01:32:39.010671 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9678 01:32:39.016939 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9679 01:32:39.020104 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9680 01:32:39.026566 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9681 01:32:39.030575 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9682 01:32:39.034070 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9683 01:32:39.040342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9684 01:32:39.043604 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9685 01:32:39.049995 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9686 01:32:39.053197 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9687 01:32:39.056499 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9688 01:32:39.063749 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9689 01:32:39.066350 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9690 01:32:39.072867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9691 01:32:39.076147 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9692 01:32:39.079772 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9693 01:32:39.086677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9694 01:32:39.089483 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9695 01:32:39.095808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9696 01:32:39.099698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9697 01:32:39.103516 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9698 01:32:39.109247 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9699 01:32:39.112978 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9700 01:32:39.118750 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9701 01:32:39.122469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9702 01:32:39.126316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9703 01:32:39.132528 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9704 01:32:39.135560 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9705 01:32:39.141886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9706 01:32:39.145545 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9707 01:32:39.152240 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9708 01:32:39.155267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9709 01:32:39.159221 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9710 01:32:39.165056 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9711 01:32:39.168948 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9712 01:32:39.175044 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9713 01:32:39.178456 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9714 01:32:39.185503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9715 01:32:39.188418 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9716 01:32:39.191731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9717 01:32:39.198412 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9718 01:32:39.201155 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9719 01:32:39.207879 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9720 01:32:39.211327 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9721 01:32:39.218123 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9722 01:32:39.221072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9723 01:32:39.224662 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9724 01:32:39.230758 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9725 01:32:39.234740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9726 01:32:39.240897 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9727 01:32:39.244469 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9728 01:32:39.251162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9729 01:32:39.254445 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9730 01:32:39.257752 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9731 01:32:39.263852 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9732 01:32:39.267521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9733 01:32:39.273698 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9734 01:32:39.277368 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9735 01:32:39.284233 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9736 01:32:39.287078 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9737 01:32:39.290252 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9738 01:32:39.297368 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9739 01:32:39.300699 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9740 01:32:39.307567 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9741 01:32:39.310928 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9742 01:32:39.316948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9743 01:32:39.320079 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9744 01:32:39.324056 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9745 01:32:39.326724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9746 01:32:39.333000 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9747 01:32:39.336147 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9748 01:32:39.339457 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9749 01:32:39.346580 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9750 01:32:39.349380 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9751 01:32:39.353148 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9752 01:32:39.359353 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9753 01:32:39.363054 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9754 01:32:39.365744 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9755 01:32:39.372468 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9756 01:32:39.376124 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9757 01:32:39.382417 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9758 01:32:39.386106 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9759 01:32:39.388959 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9760 01:32:39.395994 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9761 01:32:39.399090 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9762 01:32:39.406756 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9763 01:32:39.408892 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9764 01:32:39.412317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9765 01:32:39.418418 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9766 01:32:39.421860 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9767 01:32:39.425532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9768 01:32:39.431891 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9769 01:32:39.435548 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9770 01:32:39.438106 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9771 01:32:39.445359 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9772 01:32:39.448392 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9773 01:32:39.454915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9774 01:32:39.458371 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9775 01:32:39.461314 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9776 01:32:39.467848 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9777 01:32:39.471481 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9778 01:32:39.474697 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9779 01:32:39.481713 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9780 01:32:39.484737 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9781 01:32:39.491157 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9782 01:32:39.494193 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9783 01:32:39.497956 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9784 01:32:39.504670 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9785 01:32:39.508380 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9786 01:32:39.510931 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9787 01:32:39.514299 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9788 01:32:39.517231 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9789 01:32:39.524555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9790 01:32:39.527754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9791 01:32:39.531476 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9792 01:32:39.537905 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9793 01:32:39.540945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9794 01:32:39.544084 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9795 01:32:39.546941 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9796 01:32:39.553597 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9797 01:32:39.557489 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9798 01:32:39.563869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9799 01:32:39.567073 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9800 01:32:39.570349 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9801 01:32:39.576956 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9802 01:32:39.580376 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9803 01:32:39.587133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9804 01:32:39.589908 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9805 01:32:39.593302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9806 01:32:39.600526 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9807 01:32:39.603293 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9808 01:32:39.609955 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9809 01:32:39.614225 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9810 01:32:39.619812 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9811 01:32:39.623034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9812 01:32:39.626559 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9813 01:32:39.632809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9814 01:32:39.636817 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9815 01:32:39.642791 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9816 01:32:39.646135 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9817 01:32:39.649680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9818 01:32:39.656261 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9819 01:32:39.659677 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9820 01:32:39.665854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9821 01:32:39.670114 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9822 01:32:39.676348 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9823 01:32:39.679046 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9824 01:32:39.682567 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9825 01:32:39.689456 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9826 01:32:39.692474 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9827 01:32:39.699154 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9828 01:32:39.702699 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9829 01:32:39.705572 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9830 01:32:39.712505 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9831 01:32:39.715912 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9832 01:32:39.722040 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9833 01:32:39.725697 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9834 01:32:39.732427 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9835 01:32:39.735741 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9836 01:32:39.738377 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9837 01:32:39.745570 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9838 01:32:39.748825 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9839 01:32:39.754954 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9840 01:32:39.758208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9841 01:32:39.765785 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9842 01:32:39.768401 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9843 01:32:39.771508 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9844 01:32:39.778103 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9845 01:32:39.781123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9846 01:32:39.788528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9847 01:32:39.791074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9848 01:32:39.794186 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9849 01:32:39.801445 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9850 01:32:39.804247 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9851 01:32:39.811238 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9852 01:32:39.814453 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9853 01:32:39.817800 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9854 01:32:39.824893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9855 01:32:39.827251 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9856 01:32:39.834041 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9857 01:32:39.837190 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9858 01:32:39.844444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9859 01:32:39.847939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9860 01:32:39.851085 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9861 01:32:39.856991 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9862 01:32:39.860373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9863 01:32:39.867049 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9864 01:32:39.870300 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9865 01:32:39.876825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9866 01:32:39.879917 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9867 01:32:39.886379 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9868 01:32:39.889973 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9869 01:32:39.893287 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9870 01:32:39.899976 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9871 01:32:39.902940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9872 01:32:39.909545 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9873 01:32:39.912944 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9874 01:32:39.919428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9875 01:32:39.922363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9876 01:32:39.926030 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9877 01:32:39.933037 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9878 01:32:39.935648 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9879 01:32:39.942743 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9880 01:32:39.946363 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9881 01:32:39.952917 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9882 01:32:39.955819 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9883 01:32:39.962241 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9884 01:32:39.965435 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9885 01:32:39.969089 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9886 01:32:39.975617 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9887 01:32:39.978911 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9888 01:32:39.985234 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9889 01:32:39.989221 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9890 01:32:39.994865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9891 01:32:39.998595 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9892 01:32:40.005071 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9893 01:32:40.008078 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9894 01:32:40.011247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9895 01:32:40.018208 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9896 01:32:40.021832 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9897 01:32:40.028217 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9898 01:32:40.031442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9899 01:32:40.038247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9900 01:32:40.041807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9901 01:32:40.048114 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9902 01:32:40.051032 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9903 01:32:40.057731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9904 01:32:40.060680 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9905 01:32:40.065113 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9906 01:32:40.070982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9907 01:32:40.074355 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9908 01:32:40.080518 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9909 01:32:40.084196 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9910 01:32:40.090787 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9911 01:32:40.094052 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9912 01:32:40.100858 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9913 01:32:40.103768 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9914 01:32:40.107270 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9915 01:32:40.114275 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9916 01:32:40.117433 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9917 01:32:40.123936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9918 01:32:40.127077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9919 01:32:40.130224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9920 01:32:40.137010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9921 01:32:40.140310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9922 01:32:40.146560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9923 01:32:40.150230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9924 01:32:40.157001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9925 01:32:40.159896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9926 01:32:40.166331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9927 01:32:40.169364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9928 01:32:40.176300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9929 01:32:40.179583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9930 01:32:40.186538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9931 01:32:40.189643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9932 01:32:40.196476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9933 01:32:40.199453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9934 01:32:40.205690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9935 01:32:40.209526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9936 01:32:40.215942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9937 01:32:40.219269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9938 01:32:40.225726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9939 01:32:40.229165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9940 01:32:40.235607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9941 01:32:40.239160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9942 01:32:40.245514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9943 01:32:40.248608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9944 01:32:40.255291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9945 01:32:40.261516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9946 01:32:40.265147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9947 01:32:40.271982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9948 01:32:40.274954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9949 01:32:40.278114 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9950 01:32:40.281881 INFO: [APUAPC] vio 0
9951 01:32:40.288385 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9952 01:32:40.291118 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9953 01:32:40.295124 INFO: [APUAPC] D0_APC_0: 0x400510
9954 01:32:40.297867 INFO: [APUAPC] D0_APC_1: 0x0
9955 01:32:40.301293 INFO: [APUAPC] D0_APC_2: 0x1540
9956 01:32:40.304976 INFO: [APUAPC] D0_APC_3: 0x0
9957 01:32:40.308437 INFO: [APUAPC] D1_APC_0: 0xffffffff
9958 01:32:40.311105 INFO: [APUAPC] D1_APC_1: 0xffffffff
9959 01:32:40.314757 INFO: [APUAPC] D1_APC_2: 0x3fffff
9960 01:32:40.317390 INFO: [APUAPC] D1_APC_3: 0x0
9961 01:32:40.321194 INFO: [APUAPC] D2_APC_0: 0xffffffff
9962 01:32:40.325051 INFO: [APUAPC] D2_APC_1: 0xffffffff
9963 01:32:40.327788 INFO: [APUAPC] D2_APC_2: 0x3fffff
9964 01:32:40.328437 INFO: [APUAPC] D2_APC_3: 0x0
9965 01:32:40.334400 INFO: [APUAPC] D3_APC_0: 0xffffffff
9966 01:32:40.337236 INFO: [APUAPC] D3_APC_1: 0xffffffff
9967 01:32:40.341217 INFO: [APUAPC] D3_APC_2: 0x3fffff
9968 01:32:40.341804 INFO: [APUAPC] D3_APC_3: 0x0
9969 01:32:40.347232 INFO: [APUAPC] D4_APC_0: 0xffffffff
9970 01:32:40.350835 INFO: [APUAPC] D4_APC_1: 0xffffffff
9971 01:32:40.354136 INFO: [APUAPC] D4_APC_2: 0x3fffff
9972 01:32:40.354692 INFO: [APUAPC] D4_APC_3: 0x0
9973 01:32:40.357148 INFO: [APUAPC] D5_APC_0: 0xffffffff
9974 01:32:40.363628 INFO: [APUAPC] D5_APC_1: 0xffffffff
9975 01:32:40.366954 INFO: [APUAPC] D5_APC_2: 0x3fffff
9976 01:32:40.367414 INFO: [APUAPC] D5_APC_3: 0x0
9977 01:32:40.369962 INFO: [APUAPC] D6_APC_0: 0xffffffff
9978 01:32:40.373872 INFO: [APUAPC] D6_APC_1: 0xffffffff
9979 01:32:40.376863 INFO: [APUAPC] D6_APC_2: 0x3fffff
9980 01:32:40.379895 INFO: [APUAPC] D6_APC_3: 0x0
9981 01:32:40.383404 INFO: [APUAPC] D7_APC_0: 0xffffffff
9982 01:32:40.386807 INFO: [APUAPC] D7_APC_1: 0xffffffff
9983 01:32:40.389666 INFO: [APUAPC] D7_APC_2: 0x3fffff
9984 01:32:40.392981 INFO: [APUAPC] D7_APC_3: 0x0
9985 01:32:40.396450 INFO: [APUAPC] D8_APC_0: 0xffffffff
9986 01:32:40.399725 INFO: [APUAPC] D8_APC_1: 0xffffffff
9987 01:32:40.403162 INFO: [APUAPC] D8_APC_2: 0x3fffff
9988 01:32:40.406801 INFO: [APUAPC] D8_APC_3: 0x0
9989 01:32:40.409877 INFO: [APUAPC] D9_APC_0: 0xffffffff
9990 01:32:40.413052 INFO: [APUAPC] D9_APC_1: 0xffffffff
9991 01:32:40.416215 INFO: [APUAPC] D9_APC_2: 0x3fffff
9992 01:32:40.419915 INFO: [APUAPC] D9_APC_3: 0x0
9993 01:32:40.422603 INFO: [APUAPC] D10_APC_0: 0xffffffff
9994 01:32:40.426638 INFO: [APUAPC] D10_APC_1: 0xffffffff
9995 01:32:40.429143 INFO: [APUAPC] D10_APC_2: 0x3fffff
9996 01:32:40.432697 INFO: [APUAPC] D10_APC_3: 0x0
9997 01:32:40.436030 INFO: [APUAPC] D11_APC_0: 0xffffffff
9998 01:32:40.439392 INFO: [APUAPC] D11_APC_1: 0xffffffff
9999 01:32:40.442153 INFO: [APUAPC] D11_APC_2: 0x3fffff
10000 01:32:40.445677 INFO: [APUAPC] D11_APC_3: 0x0
10001 01:32:40.449801 INFO: [APUAPC] D12_APC_0: 0xffffffff
10002 01:32:40.455954 INFO: [APUAPC] D12_APC_1: 0xffffffff
10003 01:32:40.459439 INFO: [APUAPC] D12_APC_2: 0x3fffff
10004 01:32:40.460119 INFO: [APUAPC] D12_APC_3: 0x0
10005 01:32:40.465372 INFO: [APUAPC] D13_APC_0: 0xffffffff
10006 01:32:40.468802 INFO: [APUAPC] D13_APC_1: 0xffffffff
10007 01:32:40.472433 INFO: [APUAPC] D13_APC_2: 0x3fffff
10008 01:32:40.472982 INFO: [APUAPC] D13_APC_3: 0x0
10009 01:32:40.478874 INFO: [APUAPC] D14_APC_0: 0xffffffff
10010 01:32:40.482205 INFO: [APUAPC] D14_APC_1: 0xffffffff
10011 01:32:40.485055 INFO: [APUAPC] D14_APC_2: 0x3fffff
10012 01:32:40.488581 INFO: [APUAPC] D14_APC_3: 0x0
10013 01:32:40.491813 INFO: [APUAPC] D15_APC_0: 0xffffffff
10014 01:32:40.495137 INFO: [APUAPC] D15_APC_1: 0xffffffff
10015 01:32:40.497981 INFO: [APUAPC] D15_APC_2: 0x3fffff
10016 01:32:40.502154 INFO: [APUAPC] D15_APC_3: 0x0
10017 01:32:40.502571 INFO: [APUAPC] APC_CON: 0x4
10018 01:32:40.505065 INFO: [NOCDAPC] D0_APC_0: 0x0
10019 01:32:40.508288 INFO: [NOCDAPC] D0_APC_1: 0x0
10020 01:32:40.511832 INFO: [NOCDAPC] D1_APC_0: 0x0
10021 01:32:40.515060 INFO: [NOCDAPC] D1_APC_1: 0xfff
10022 01:32:40.518141 INFO: [NOCDAPC] D2_APC_0: 0x0
10023 01:32:40.521590 INFO: [NOCDAPC] D2_APC_1: 0xfff
10024 01:32:40.525444 INFO: [NOCDAPC] D3_APC_0: 0x0
10025 01:32:40.528247 INFO: [NOCDAPC] D3_APC_1: 0xfff
10026 01:32:40.530898 INFO: [NOCDAPC] D4_APC_0: 0x0
10027 01:32:40.534360 INFO: [NOCDAPC] D4_APC_1: 0xfff
10028 01:32:40.534960 INFO: [NOCDAPC] D5_APC_0: 0x0
10029 01:32:40.537621 INFO: [NOCDAPC] D5_APC_1: 0xfff
10030 01:32:40.541098 INFO: [NOCDAPC] D6_APC_0: 0x0
10031 01:32:40.544064 INFO: [NOCDAPC] D6_APC_1: 0xfff
10032 01:32:40.547501 INFO: [NOCDAPC] D7_APC_0: 0x0
10033 01:32:40.550751 INFO: [NOCDAPC] D7_APC_1: 0xfff
10034 01:32:40.554900 INFO: [NOCDAPC] D8_APC_0: 0x0
10035 01:32:40.557952 INFO: [NOCDAPC] D8_APC_1: 0xfff
10036 01:32:40.560606 INFO: [NOCDAPC] D9_APC_0: 0x0
10037 01:32:40.564380 INFO: [NOCDAPC] D9_APC_1: 0xfff
10038 01:32:40.567549 INFO: [NOCDAPC] D10_APC_0: 0x0
10039 01:32:40.570578 INFO: [NOCDAPC] D10_APC_1: 0xfff
10040 01:32:40.574157 INFO: [NOCDAPC] D11_APC_0: 0x0
10041 01:32:40.574664 INFO: [NOCDAPC] D11_APC_1: 0xfff
10042 01:32:40.577426 INFO: [NOCDAPC] D12_APC_0: 0x0
10043 01:32:40.580325 INFO: [NOCDAPC] D12_APC_1: 0xfff
10044 01:32:40.584548 INFO: [NOCDAPC] D13_APC_0: 0x0
10045 01:32:40.587263 INFO: [NOCDAPC] D13_APC_1: 0xfff
10046 01:32:40.591284 INFO: [NOCDAPC] D14_APC_0: 0x0
10047 01:32:40.593754 INFO: [NOCDAPC] D14_APC_1: 0xfff
10048 01:32:40.596815 INFO: [NOCDAPC] D15_APC_0: 0x0
10049 01:32:40.600303 INFO: [NOCDAPC] D15_APC_1: 0xfff
10050 01:32:40.603772 INFO: [NOCDAPC] APC_CON: 0x4
10051 01:32:40.606855 INFO: [APUAPC] set_apusys_apc done
10052 01:32:40.610356 INFO: [DEVAPC] devapc_init done
10053 01:32:40.613668 INFO: GICv3 without legacy support detected.
10054 01:32:40.617141 INFO: ARM GICv3 driver initialized in EL3
10055 01:32:40.620138 INFO: Maximum SPI INTID supported: 639
10056 01:32:40.626908 INFO: BL31: Initializing runtime services
10057 01:32:40.629920 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10058 01:32:40.633666 INFO: SPM: enable CPC mode
10059 01:32:40.640222 INFO: mcdi ready for mcusys-off-idle and system suspend
10060 01:32:40.644122 INFO: BL31: Preparing for EL3 exit to normal world
10061 01:32:40.646923 INFO: Entry point address = 0x80000000
10062 01:32:40.650282 INFO: SPSR = 0x8
10063 01:32:40.656525
10064 01:32:40.657091
10065 01:32:40.657622
10066 01:32:40.658654 Starting depthcharge on Spherion...
10067 01:32:40.659068
10068 01:32:40.659390 Wipe memory regions:
10069 01:32:40.659695
10070 01:32:40.661978 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10071 01:32:40.662516 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10072 01:32:40.662929 Setting prompt string to ['asurada:']
10073 01:32:40.663327 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10074 01:32:40.663962 [0x00000040000000, 0x00000054600000)
10075 01:32:40.784239
10076 01:32:40.784791 [0x00000054660000, 0x00000080000000)
10077 01:32:41.044798
10078 01:32:41.045385 [0x000000821a7280, 0x000000ffe64000)
10079 01:32:41.790063
10080 01:32:41.790333 [0x00000100000000, 0x00000240000000)
10081 01:32:43.680637
10082 01:32:43.683613 Initializing XHCI USB controller at 0x11200000.
10083 01:32:44.722863
10084 01:32:44.725610 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10085 01:32:44.726070
10086 01:32:44.726438
10087 01:32:44.727267 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 01:32:44.828626 asurada: tftpboot 192.168.201.1 14173483/tftp-deploy-9poujol5/kernel/image.itb 14173483/tftp-deploy-9poujol5/kernel/cmdline
10090 01:32:44.829308 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 01:32:44.829775 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10092 01:32:44.834575 tftpboot 192.168.201.1 14173483/tftp-deploy-9poujol5/kernel/image.ittp-deploy-9poujol5/kernel/cmdline
10093 01:32:44.835130
10094 01:32:44.835490 Waiting for link
10095 01:32:44.992747
10096 01:32:44.993346 R8152: Initializing
10097 01:32:44.993730
10098 01:32:44.995782 Version 6 (ocp_data = 5c30)
10099 01:32:44.996343
10100 01:32:44.999244 R8152: Done initializing
10101 01:32:44.999916
10102 01:32:45.000287 Adding net device
10103 01:32:46.933208
10104 01:32:46.933821 done.
10105 01:32:46.934184
10106 01:32:46.934520 MAC: 00:24:32:30:7c:7b
10107 01:32:46.934850
10108 01:32:46.935571 Sending DHCP discover... done.
10109 01:32:46.936021
10110 01:32:50.443189 Waiting for reply... done.
10111 01:32:50.443728
10112 01:32:50.444086 Sending DHCP request... done.
10113 01:32:50.446828
10114 01:32:50.452429 Waiting for reply... done.
10115 01:32:50.453047
10116 01:32:50.453479 My ip is 192.168.201.14
10117 01:32:50.453821
10118 01:32:50.455915 The DHCP server ip is 192.168.201.1
10119 01:32:50.456455
10120 01:32:50.462095 TFTP server IP predefined by user: 192.168.201.1
10121 01:32:50.462632
10122 01:32:50.468941 Bootfile predefined by user: 14173483/tftp-deploy-9poujol5/kernel/image.itb
10123 01:32:50.469536
10124 01:32:50.472039 Sending tftp read request... done.
10125 01:32:50.472490
10126 01:32:50.478753 Waiting for the transfer...
10127 01:32:50.479295
10128 01:32:51.165564 00000000 ################################################################
10129 01:32:51.166075
10130 01:32:51.866118 00080000 ################################################################
10131 01:32:51.866629
10132 01:32:52.578831 00100000 ################################################################
10133 01:32:52.579349
10134 01:32:53.275915 00180000 ################################################################
10135 01:32:53.276421
10136 01:32:53.980351 00200000 ################################################################
10137 01:32:53.980878
10138 01:32:54.682144 00280000 ################################################################
10139 01:32:54.682642
10140 01:32:55.375384 00300000 ################################################################
10141 01:32:55.375893
10142 01:32:56.066931 00380000 ################################################################
10143 01:32:56.067430
10144 01:32:56.747424 00400000 ################################################################
10145 01:32:56.747928
10146 01:32:57.442166 00480000 ################################################################
10147 01:32:57.442754
10148 01:32:58.151680 00500000 ################################################################
10149 01:32:58.152181
10150 01:32:58.848644 00580000 ################################################################
10151 01:32:58.849223
10152 01:32:59.545872 00600000 ################################################################
10153 01:32:59.546355
10154 01:33:00.235157 00680000 ################################################################
10155 01:33:00.235704
10156 01:33:00.934551 00700000 ################################################################
10157 01:33:00.935088
10158 01:33:01.652813 00780000 ################################################################
10159 01:33:01.653400
10160 01:33:02.352537 00800000 ################################################################
10161 01:33:02.353099
10162 01:33:03.046333 00880000 ################################################################
10163 01:33:03.046832
10164 01:33:03.748350 00900000 ################################################################
10165 01:33:03.748849
10166 01:33:04.460238 00980000 ################################################################
10167 01:33:04.460385
10168 01:33:05.138088 00a00000 ################################################################
10169 01:33:05.138590
10170 01:33:05.857968 00a80000 ################################################################
10171 01:33:05.858114
10172 01:33:06.541535 00b00000 ################################################################
10173 01:33:06.542046
10174 01:33:07.245777 00b80000 ################################################################
10175 01:33:07.246278
10176 01:33:07.932466 00c00000 ################################################################
10177 01:33:07.933099
10178 01:33:08.647051 00c80000 ################################################################
10179 01:33:08.647616
10180 01:33:09.367224 00d00000 ################################################################
10181 01:33:09.367755
10182 01:33:10.058314 00d80000 ################################################################
10183 01:33:10.058986
10184 01:33:10.759415 00e00000 ################################################################
10185 01:33:10.759950
10186 01:33:11.475728 00e80000 ################################################################
10187 01:33:11.476281
10188 01:33:12.185183 00f00000 ################################################################
10189 01:33:12.185723
10190 01:33:12.900632 00f80000 ################################################################
10191 01:33:12.901155
10192 01:33:13.593435 01000000 ################################################################
10193 01:33:13.593938
10194 01:33:14.280377 01080000 ################################################################
10195 01:33:14.280892
10196 01:33:14.964338 01100000 ################################################################
10197 01:33:14.964843
10198 01:33:15.672332 01180000 ################################################################
10199 01:33:15.672896
10200 01:33:16.360662 01200000 ################################################################
10201 01:33:16.361175
10202 01:33:17.040847 01280000 ################################################################
10203 01:33:17.041422
10204 01:33:17.720395 01300000 ################################################################
10205 01:33:17.720892
10206 01:33:18.396067 01380000 ################################################################
10207 01:33:18.396566
10208 01:33:19.110088 01400000 ################################################################
10209 01:33:19.110659
10210 01:33:19.813069 01480000 ################################################################
10211 01:33:19.813674
10212 01:33:20.524011 01500000 ################################################################
10213 01:33:20.524689
10214 01:33:21.218764 01580000 ################################################################
10215 01:33:21.219270
10216 01:33:21.910292 01600000 ################################################################
10217 01:33:21.910772
10218 01:33:22.598168 01680000 ################################################################
10219 01:33:22.598667
10220 01:33:23.318596 01700000 ################################################################
10221 01:33:23.319125
10222 01:33:24.033455 01780000 ################################################################
10223 01:33:24.033951
10224 01:33:24.745233 01800000 ################################################################
10225 01:33:24.745766
10226 01:33:25.461885 01880000 ################################################################
10227 01:33:25.462387
10228 01:33:26.179392 01900000 ################################################################
10229 01:33:26.179896
10230 01:33:26.878700 01980000 ################################################################
10231 01:33:26.879208
10232 01:33:27.580840 01a00000 ################################################################
10233 01:33:27.581380
10234 01:33:28.278986 01a80000 ################################################################
10235 01:33:28.279493
10236 01:33:28.971293 01b00000 ################################################################
10237 01:33:28.971794
10238 01:33:29.649852 01b80000 ################################################################
10239 01:33:29.650350
10240 01:33:30.328332 01c00000 ################################################################
10241 01:33:30.328840
10242 01:33:31.030972 01c80000 ################################################################
10243 01:33:31.031474
10244 01:33:31.716705 01d00000 ################################################################
10245 01:33:31.717203
10246 01:33:32.359118 01d80000 ################################################################
10247 01:33:32.359260
10248 01:33:32.840102 01e00000 ############################################## done.
10249 01:33:32.840670
10250 01:33:32.842682 The bootfile was 31830270 bytes long.
10251 01:33:32.843140
10252 01:33:32.845969 Sending tftp read request... done.
10253 01:33:32.846435
10254 01:33:32.849807 Waiting for the transfer...
10255 01:33:32.850263
10256 01:33:32.850676 00000000 # done.
10257 01:33:32.851033
10258 01:33:32.856666 Command line loaded dynamically from TFTP file: 14173483/tftp-deploy-9poujol5/kernel/cmdline
10259 01:33:32.857174
10260 01:33:32.879754 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10261 01:33:32.880278
10262 01:33:32.883014 Loading FIT.
10263 01:33:32.883435
10264 01:33:32.883757 Image ramdisk-1 has 18721060 bytes.
10265 01:33:32.886758
10266 01:33:32.887265 Image fdt-1 has 47258 bytes.
10267 01:33:32.887594
10268 01:33:32.889990 Image kernel-1 has 13059919 bytes.
10269 01:33:32.890433
10270 01:33:32.899607 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10271 01:33:32.900202
10272 01:33:32.916248 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10273 01:33:32.916774
10274 01:33:32.922724 Choosing best match conf-1 for compat google,spherion-rev2.
10275 01:33:32.926523
10276 01:33:32.930908 Connected to device vid:did:rid of 1ae0:0028:00
10277 01:33:32.939247
10278 01:33:32.942883 tpm_get_response: command 0x17b, return code 0x0
10279 01:33:32.943300
10280 01:33:32.945238 ec_init: CrosEC protocol v3 supported (256, 248)
10281 01:33:32.950952
10282 01:33:32.954688 tpm_cleanup: add release locality here.
10283 01:33:32.955103
10284 01:33:32.955423 Shutting down all USB controllers.
10285 01:33:32.957108
10286 01:33:32.957544 Removing current net device
10287 01:33:32.957872
10288 01:33:32.964240 Exiting depthcharge with code 4 at timestamp: 81563022
10289 01:33:32.964750
10290 01:33:32.966680 LZMA decompressing kernel-1 to 0x821a6718
10291 01:33:32.967129
10292 01:33:32.970121 LZMA decompressing kernel-1 to 0x40000000
10293 01:33:34.579916
10294 01:33:34.580465 jumping to kernel
10295 01:33:34.582227 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
10296 01:33:34.582744 start: 2.2.5 auto-login-action (timeout 00:03:32) [common]
10297 01:33:34.583149 Setting prompt string to ['Linux version [0-9]']
10298 01:33:34.583513 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10299 01:33:34.583877 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10300 01:33:34.661605
10301 01:33:34.664434 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10302 01:33:34.668261 start: 2.2.5.1 login-action (timeout 00:03:32) [common]
10303 01:33:34.668788 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10304 01:33:34.669179 Setting prompt string to []
10305 01:33:34.669636 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10306 01:33:34.670030 Using line separator: #'\n'#
10307 01:33:34.670354 No login prompt set.
10308 01:33:34.670723 Parsing kernel messages
10309 01:33:34.671054 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10310 01:33:34.671607 [login-action] Waiting for messages, (timeout 00:03:32)
10311 01:33:34.671966 Waiting using forced prompt support (timeout 00:01:46)
10312 01:33:34.688019 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10313 01:33:34.690763 [ 0.000000] random: crng init done
10314 01:33:34.698013 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 01:33:34.701455 [ 0.000000] efi: UEFI not found.
10316 01:33:34.707228 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 01:33:34.717197 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 01:33:34.727167 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 01:33:34.734150 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 01:33:34.740560 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 01:33:34.746738 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 01:33:34.753454 [ 0.000000] NUMA: No NUMA configuration found
10323 01:33:34.760442 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 01:33:34.767145 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10325 01:33:34.767698 [ 0.000000] Zone ranges:
10326 01:33:34.774372 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 01:33:34.776726 [ 0.000000] DMA32 empty
10328 01:33:34.783128 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 01:33:34.786698 [ 0.000000] Movable zone start for each node
10330 01:33:34.789940 [ 0.000000] Early memory node ranges
10331 01:33:34.796666 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 01:33:34.803630 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 01:33:34.810161 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 01:33:34.816455 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 01:33:34.822610 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 01:33:34.829529 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 01:33:34.886140 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 01:33:34.893042 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 01:33:34.899848 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 01:33:34.902689 [ 0.000000] psci: probing for conduit method from DT.
10341 01:33:34.909476 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 01:33:34.913639 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 01:33:34.920102 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 01:33:34.923055 [ 0.000000] psci: SMC Calling Convention v1.2
10345 01:33:34.929369 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10346 01:33:34.933211 [ 0.000000] Detected VIPT I-cache on CPU0
10347 01:33:34.939342 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 01:33:34.945970 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 01:33:34.952897 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 01:33:34.959509 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 01:33:34.969853 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 01:33:34.975700 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 01:33:34.979283 [ 0.000000] alternatives: applying boot alternatives
10354 01:33:34.985635 [ 0.000000] Fallback order for Node 0: 0
10355 01:33:34.992403 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 01:33:34.995575 [ 0.000000] Policy zone: Normal
10357 01:33:35.019081 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10358 01:33:35.029009 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 01:33:35.039989 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 01:33:35.049395 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 01:33:35.056091 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 01:33:35.059495 <6>[ 0.000000] software IO TLB: area num 8.
10363 01:33:35.117211 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 01:33:35.266996 <6>[ 0.000000] Memory: 7945908K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406860K reserved, 32768K cma-reserved)
10365 01:33:35.272785 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 01:33:35.279995 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 01:33:35.283236 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 01:33:35.289792 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 01:33:35.295949 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 01:33:35.299521 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 01:33:35.309715 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 01:33:35.316426 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 01:33:35.323407 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 01:33:35.330120 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 01:33:35.333005 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 01:33:35.335864 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 01:33:35.342873 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 01:33:35.345881 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 01:33:35.352795 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 01:33:35.365665 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 01:33:35.378814 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 01:33:35.385371 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 01:33:35.393354 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 01:33:35.406206 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 01:33:35.412867 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 01:33:35.419721 <6>[ 0.009233] Console: colour dummy device 80x25
10387 01:33:35.429423 <6>[ 0.013982] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 01:33:35.436235 <6>[ 0.024490] pid_max: default: 32768 minimum: 301
10389 01:33:35.439628 <6>[ 0.029393] LSM: Security Framework initializing
10390 01:33:35.445716 <6>[ 0.034361] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 01:33:35.455886 <6>[ 0.042175] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 01:33:35.466105 <6>[ 0.051577] cblist_init_generic: Setting adjustable number of callback queues.
10393 01:33:35.472134 <6>[ 0.059022] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 01:33:35.479574 <6>[ 0.065359] cblist_init_generic: Setting adjustable number of callback queues.
10395 01:33:35.485564 <6>[ 0.072831] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 01:33:35.489118 <6>[ 0.079309] rcu: Hierarchical SRCU implementation.
10397 01:33:35.495204 <6>[ 0.079312] rcu: Max phase no-delay instances is 1000.
10398 01:33:35.502046 <6>[ 0.079336] printk: bootconsole [mtk8250] printing thread started
10399 01:33:35.508736 <6>[ 0.097687] EFI services will not be available.
10400 01:33:35.512582 <6>[ 0.097889] smp: Bringing up secondary CPUs ...
10401 01:33:35.518700 <6>[ 0.098199] Detected VIPT I-cache on CPU1
10402 01:33:35.524964 <6>[ 0.098265] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10403 01:33:35.532573 <6>[ 0.098297] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10404 01:33:35.541330 <6>[ 0.126164] Detected VIPT I-cache on CPU2
10405 01:33:35.551854 <6>[ 0.126215] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10406 01:33:35.558221 <6>[ 0.126234] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10407 01:33:35.561191 <6>[ 0.126491] Detected VIPT I-cache on CPU3
10408 01:33:35.567889 <6>[ 0.126539] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10409 01:33:35.574321 <6>[ 0.126554] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10410 01:33:35.580979 <6>[ 0.126864] CPU features: detected: Spectre-v4
10411 01:33:35.584584 <6>[ 0.126870] CPU features: detected: Spectre-BHB
10412 01:33:35.588175 <6>[ 0.126875] Detected PIPT I-cache on CPU4
10413 01:33:35.594387 <6>[ 0.126933] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10414 01:33:35.603550 <6>[ 0.126949] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10415 01:33:35.607243 <6>[ 0.127237] Detected PIPT I-cache on CPU5
10416 01:33:35.613551 <6>[ 0.127298] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10417 01:33:35.620775 <6>[ 0.127313] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10418 01:33:35.623659 <6>[ 0.127584] Detected PIPT I-cache on CPU6
10419 01:33:35.633677 <6>[ 0.127647] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10420 01:33:35.640325 <6>[ 0.127662] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10421 01:33:35.643822 <6>[ 0.127949] Detected PIPT I-cache on CPU7
10422 01:33:35.650099 <6>[ 0.128013] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10423 01:33:35.656238 <6>[ 0.128028] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10424 01:33:35.663224 <6>[ 0.128075] smp: Brought up 1 node, 8 CPUs
10425 01:33:35.666309 <6>[ 0.128079] SMP: Total of 8 processors activated.
10426 01:33:35.673161 <6>[ 0.128082] CPU features: detected: 32-bit EL0 Support
10427 01:33:35.683116 <6>[ 0.128084] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10428 01:33:35.689641 <6>[ 0.128087] CPU features: detected: Common not Private translations
10429 01:33:35.693071 <6>[ 0.128089] CPU features: detected: CRC32 instructions
10430 01:33:35.699451 <6>[ 0.128091] CPU features: detected: RCpc load-acquire (LDAPR)
10431 01:33:35.706166 <6>[ 0.128093] CPU features: detected: LSE atomic instructions
10432 01:33:35.709652 <6>[ 0.128095] CPU features: detected: Privileged Access Never
10433 01:33:35.715640 <6>[ 0.128096] CPU features: detected: RAS Extension Support
10434 01:33:35.722456 <6>[ 0.128099] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10435 01:33:35.729474 <6>[ 0.128168] CPU: All CPU(s) started at EL2
10436 01:33:35.732304 <6>[ 0.128169] alternatives: applying system-wide alternatives
10437 01:33:35.738782 <6>[ 0.141294] devtmpfs: initialized
10438 01:33:35.748796 <6>[ 0.147632] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10439 01:33:35.755192 <6>[ 0.147646] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10440 01:33:35.758447 <6>[ 0.148507] pinctrl core: initialized pinctrl subsystem
10441 01:33:35.765378 <6>[ 0.149689] DMI not present or invalid.
10442 01:33:35.789174 <6>[ 0.378857] printk:< console [ttyS0] printing thread started
10443 01:33:35.795744 6>[ 0.150002] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10444 01:33:35.803625 <6>[ 0.378859] printk: console [ttyS0] enabled
10445 01:33:35.806616 <6>[ 0.378862] printk: bootconsole [mtk8250] disabled
10446 01:33:35.813687 <6>[ 0.390879] printk: bootconsole [mtk8250] printing thread stopped
10447 01:33:35.819967 <6>[ 0.391849] SuperH (H)SCI(F) driver initialized
10448 01:33:35.823704 <6>[ 0.392325] msm_serial: driver initialized
10449 01:33:35.833422 <6>[ 0.396883] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10450 01:33:35.839423 <6>[ 0.396917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10451 01:33:35.848330 <6>[ 0.396962] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10452 01:33:35.859244 <6>[ 0.396992] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10453 01:33:35.871532 <6>[ 0.397013] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10454 01:33:35.876400 <6>[ 0.397041] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10455 01:33:35.887815 <6>[ 0.397069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10456 01:33:35.893504 <6>[ 0.397184] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10457 01:33:35.901873 <6>[ 0.397213] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10458 01:33:35.905937 <6>[ 0.406196] loop: module loaded
10459 01:33:35.910323 <6>[ 0.408659] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10460 01:33:35.917491 <4>[ 0.425075] mtk-pmic-keys: Failed to locate of_node [id: -1]
10461 01:33:35.920402 <6>[ 0.425916] megasas: 07.719.03.00-rc1
10462 01:33:35.926845 <6>[ 0.436379] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10463 01:33:35.933998 <6>[ 0.440392] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10464 01:33:35.940462 <6>[ 0.452526] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10465 01:33:35.949634 <6>[ 0.506294] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10466 01:33:36.430967 <6>[ 1.020515] Freeing initrd memory: 18276K
10467 01:33:36.438851 <6>[ 1.027931] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10468 01:33:36.445446 <6>[ 1.032779] tun: Universal TUN/TAP device driver, 1.6
10469 01:33:36.448875 <6>[ 1.033554] thunder_xcv, ver 1.0
10470 01:33:36.452154 <6>[ 1.033573] thunder_bgx, ver 1.0
10471 01:33:36.455513 <6>[ 1.033590] nicpf, ver 1.0
10472 01:33:36.462113 <6>[ 1.034673] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10473 01:33:36.469078 <6>[ 1.034677] hns3: Copyright (c) 2017 Huawei Corporation.
10474 01:33:36.471820 <6>[ 1.034704] hclge is initializing
10475 01:33:36.478348 <6>[ 1.034719] e1000: Intel(R) PRO/1000 Network Driver
10476 01:33:36.482203 <6>[ 1.034721] e1000: Copyright (c) 1999-2006 Intel Corporation.
10477 01:33:36.488944 <6>[ 1.034740] e1000e: Intel(R) PRO/1000 Network Driver
10478 01:33:36.495893 <6>[ 1.034742] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10479 01:33:36.499518 <6>[ 1.034757] igb: Intel(R) Gigabit Ethernet Network Driver
10480 01:33:36.506005 <6>[ 1.034759] igb: Copyright (c) 2007-2014 Intel Corporation.
10481 01:33:36.513254 <6>[ 1.034773] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10482 01:33:36.519859 <6>[ 1.034775] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10483 01:33:36.523026 <6>[ 1.035065] sky2: driver version 1.30
10484 01:33:36.529580 <6>[ 1.036068] usbcore: registered new device driver r8152-cfgselector
10485 01:33:36.536557 <6>[ 1.036087] usbcore: registered new interface driver r8152
10486 01:33:36.539507 <6>[ 1.036167] VFIO - User Level meta-driver version: 0.3
10487 01:33:36.546107 <6>[ 1.039009] usbcore: registered new interface driver usb-storage
10488 01:33:36.552746 <6>[ 1.039190] usbcore: registered new device driver onboard-usb-hub
10489 01:33:36.559040 <6>[ 1.041973] mt6397-rtc mt6359-rtc: registered as rtc0
10490 01:33:36.565912 <6>[ 1.042121] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T01:33:35 UTC (1717551215)
10491 01:33:36.572223 <6>[ 1.042733] i2c_dev: i2c /dev entries driver
10492 01:33:36.579051 <6>[ 1.049875] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10493 01:33:36.585683 <4>[ 1.050601] cpu cpu0: supply cpu not found, using dummy regulator
10494 01:33:36.592584 <4>[ 1.050676] cpu cpu1: supply cpu not found, using dummy regulator
10495 01:33:36.599191 <4>[ 1.050734] cpu cpu2: supply cpu not found, using dummy regulator
10496 01:33:36.605157 <4>[ 1.050787] cpu cpu3: supply cpu not found, using dummy regulator
10497 01:33:36.611974 <4>[ 1.050841] cpu cpu4: supply cpu not found, using dummy regulator
10498 01:33:36.619056 <4>[ 1.050913] cpu cpu5: supply cpu not found, using dummy regulator
10499 01:33:36.625693 <4>[ 1.050963] cpu cpu6: supply cpu not found, using dummy regulator
10500 01:33:36.631600 <4>[ 1.051014] cpu cpu7: supply cpu not found, using dummy regulator
10501 01:33:36.635728 <6>[ 1.066093] cpu cpu0: EM: created perf domain
10502 01:33:36.638815 <6>[ 1.066434] cpu cpu4: EM: created perf domain
10503 01:33:36.645419 <6>[ 1.072283] sdhci: Secure Digital Host Controller Interface driver
10504 01:33:36.651590 <6>[ 1.072285] sdhci: Copyright(c) Pierre Ossman
10505 01:33:36.658285 <6>[ 1.072633] Synopsys Designware Multimedia Card Interface Driver
10506 01:33:36.661612 <6>[ 1.073021] sdhci-pltfm: SDHCI platform and OF driver helper
10507 01:33:36.668215 <6>[ 1.078152] ledtrig-cpu: registered to indicate activity on CPUs
10508 01:33:36.675228 <6>[ 1.078784] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10509 01:33:36.677728 <6>[ 1.078840] mmc0: CQHCI version 5.10
10510 01:33:36.684863 <6>[ 1.079073] usbcore: registered new interface driver usbhid
10511 01:33:36.688380 <6>[ 1.079075] usbhid: USB HID core driver
10512 01:33:36.698295 <6>[ 1.079185] spi_master spi0: will run message pump with realtime priority
10513 01:33:36.707909 <6>[ 1.110935] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10514 01:33:36.724988 <6>[ 1.114450] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10515 01:33:36.727602 <6>[ 1.115605] cros-ec-spi spi0.0: Chrome EC device registered
10516 01:33:36.737570 <6>[ 1.127197] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10517 01:33:36.744697 <6>[ 1.128171] NET: Registered PF_PACKET protocol family
10518 01:33:36.747692 <6>[ 1.128216] 9pnet: Installing 9P2000 support
10519 01:33:36.750458 <5>[ 1.128235] Key type dns_resolver registered
10520 01:33:36.757710 <6>[ 1.128431] registered taskstats version 1
10521 01:33:36.760681 <5>[ 1.128438] Loading compiled-in X.509 certificates
10522 01:33:36.770410 <4>[ 1.145232] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 01:33:36.783815 <4>[ 1.145514] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 01:33:36.787023 <6>[ 1.157683] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10525 01:33:36.793645 <6>[ 1.158285] xhci-mtk 11200000.usb: xHCI Host Controller
10526 01:33:36.800299 <6>[ 1.158308] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10527 01:33:36.809940 <6>[ 1.158522] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10528 01:33:36.817143 <6>[ 1.158564] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10529 01:33:36.823656 <6>[ 1.158649] xhci-mtk 11200000.usb: xHCI Host Controller
10530 01:33:36.830338 <6>[ 1.158656] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10531 01:33:36.836632 <6>[ 1.158663] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10532 01:33:36.843929 <6>[ 1.159087] hub 1-0:1.0: USB hub found
10533 01:33:36.846737 <6>[ 1.159118] hub 1-0:1.0: 1 port detected
10534 01:33:36.853661 <6>[ 1.159328] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10535 01:33:36.859700 <6>[ 1.159620] hub 2-0:1.0: USB hub found
10536 01:33:36.862828 <6>[ 1.159637] hub 2-0:1.0: 1 port detected
10537 01:33:36.866348 <6>[ 1.162166] mtk-msdc 11f70000.mmc: Got CD GPIO
10538 01:33:36.872739 <3>[ 1.171091] mtk-msdc 11f60000.mmc: phase error: [map:0]
10539 01:33:36.879605 <3>[ 1.171099] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10540 01:33:36.886031 <3>[ 1.171101] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10541 01:33:36.889355 <3>[ 1.171109] mmc0: error -5 whilst initialising MMC card
10542 01:33:36.899210 <6>[ 1.176322] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10543 01:33:36.906154 <6>[ 1.176328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10544 01:33:36.915519 <4>[ 1.176477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10545 01:33:36.922220 <6>[ 1.177132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10546 01:33:36.933142 <6>[ 1.177136] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10547 01:33:36.939171 <6>[ 1.177270] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10548 01:33:36.945692 <6>[ 1.177282] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10549 01:33:36.955163 <6>[ 1.177286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10550 01:33:36.965966 <6>[ 1.177291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10551 01:33:36.972129 <6>[ 1.178676] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10552 01:33:36.981398 <6>[ 1.178691] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10553 01:33:36.988247 <6>[ 1.178697] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10554 01:33:36.998230 <6>[ 1.178702] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10555 01:33:37.004605 <6>[ 1.178708] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10556 01:33:37.014738 <6>[ 1.178714] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10557 01:33:37.021608 <6>[ 1.178720] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10558 01:33:37.030550 <6>[ 1.178725] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10559 01:33:37.037408 <6>[ 1.178731] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10560 01:33:37.047420 <6>[ 1.178737] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10561 01:33:37.053634 <6>[ 1.178743] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10562 01:33:37.063698 <6>[ 1.178748] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10563 01:33:37.070174 <6>[ 1.178753] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10564 01:33:37.080452 <6>[ 1.178758] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10565 01:33:37.090889 <6>[ 1.178763] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10566 01:33:37.093307 <6>[ 1.179291] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10567 01:33:37.100538 <6>[ 1.180182] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10568 01:33:37.106919 <6>[ 1.180789] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10569 01:33:37.113471 <6>[ 1.181511] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10570 01:33:37.121120 <6>[ 1.182168] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10571 01:33:37.130008 <6>[ 1.182373] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10572 01:33:37.139862 <6>[ 1.182390] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10573 01:33:37.149858 <6>[ 1.182397] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10574 01:33:37.159426 <6>[ 1.182403] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10575 01:33:37.169800 <6>[ 1.182409] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10576 01:33:37.176361 <6>[ 1.182416] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10577 01:33:37.186238 <6>[ 1.182422] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10578 01:33:37.195797 <6>[ 1.182428] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10579 01:33:37.205764 <6>[ 1.182433] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10580 01:33:37.215573 <6>[ 1.182441] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10581 01:33:37.225746 <6>[ 1.182445] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10582 01:33:37.232512 <6>[ 1.183063] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10583 01:33:37.238771 <6>[ 1.197657] Trying to probe devices needed for running init ...
10584 01:33:37.245384 <3>[ 1.266614] mtk-msdc 11f60000.mmc: phase error: [map:0]
10585 01:33:37.251787 <3>[ 1.266624] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10586 01:33:37.258890 <3>[ 1.266627] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10587 01:33:37.261819 <3>[ 1.266633] mmc0: error -5 whilst initialising MMC card
10588 01:33:37.268991 <6>[ 1.541305] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10589 01:33:37.274721 <6>[ 1.567820] hub 2-1:1.0: USB hub found
10590 01:33:37.277843 <6>[ 1.568169] hub 2-1:1.0: 3 ports detected
10591 01:33:37.281632 <6>[ 1.570774] hub 2-1:1.0: USB hub found
10592 01:33:37.284867 <6>[ 1.571107] hub 2-1:1.0: 3 ports detected
10593 01:33:37.291730 <6>[ 1.598850] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16814
10594 01:33:37.297955 <6>[ 1.608577] mmc0: Command Queue Engine enabled
10595 01:33:37.304803 <6>[ 1.608592] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 01:33:37.307643 <6>[ 1.609231] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 01:33:37.314318 <6>[ 1.613012] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10598 01:33:37.317661 <6>[ 1.613847] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10599 01:33:37.324427 <6>[ 1.614371] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10600 01:33:37.331234 <6>[ 1.614833] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10601 01:33:37.337476 <6>[ 1.689027] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10602 01:33:37.341202 <6>[ 1.841969] hub 1-1:1.0: USB hub found
10603 01:33:37.347803 <6>[ 1.842360] hub 1-1:1.0: 4 ports detected
10604 01:33:37.351084 <6>[ 1.845315] hub 1-1:1.0: USB hub found
10605 01:33:37.354094 <6>[ 1.845553] hub 1-1:1.0: 4 ports detected
10606 01:33:37.360876 <6>[ 1.921220] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10607 01:33:37.438408 <6>[ 2.021769] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10608 01:33:37.466706 <4>[ 2.049008] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10609 01:33:37.476676 <4>[ 2.049035] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10610 01:33:37.494977 <6>[ 2.082830] r8152 2-1.3:1.0 eth0: v1.12.13
10611 01:33:37.574177 <6>[ 2.157240] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10612 01:33:37.699245 <6>[ 2.284997] hub 1-1.4:1.0: USB hub found
10613 01:33:37.703059 <6>[ 2.285452] hub 1-1.4:1.0: 2 ports detected
10614 01:33:37.705774 <6>[ 2.289708] hub 1-1.4:1.0: USB hub found
10615 01:33:37.712673 <6>[ 2.290092] hub 1-1.4:1.0: 2 ports detected
10616 01:33:37.994818 <6>[ 2.577064] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10617 01:33:38.178185 <6>[ 2.761138] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10618 01:33:39.102947 <6>[ 3.689242] r8152 2-1.3:1.0 eth0: carrier on
10619 01:33:41.634648 <5>[ 3.709171] Sending DHCP requests .., OK
10620 01:33:41.641224 <6>[ 6.221080] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10621 01:33:41.644203 <6>[ 6.221094] IP-Config: Complete:
10622 01:33:41.657771 <6>[ 6.221096] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10623 01:33:41.664620 <6>[ 6.221103] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10624 01:33:41.671197 <6>[ 6.221106] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10625 01:33:41.677444 <6>[ 6.221110] nameserver0=192.168.201.1
10626 01:33:41.681368 Loading, please <6>[ 6.221313] clk: Disabling unused clocks
10627 01:33:41.684342 <6>[ 6.222277] ALSA device list:
10628 01:33:41.687211 <6>[ 6.222289] No soundcards found.
10629 01:33:41.691323 wait...
10630 01:33:41.693945 Startin<6>[ 6.226671] Freeing unused kernel memory: 8512K
10631 01:33:41.701510 <6>[ 6.226854] Run /init as init process
10632 01:33:41.704002 g systemd-udevd version 252.22-1~deb12u1
10633 01:33:41.966409 <6>[ 6.551448] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10634 01:33:41.972379 <6>[ 6.551518] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10635 01:33:41.982503 <6>[ 6.551530] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10636 01:33:41.989553 <6>[ 6.552358] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10637 01:33:41.995187 <6>[ 6.571171] remoteproc remoteproc0: scp is available
10638 01:33:42.002934 <6>[ 6.571354] remoteproc remoteproc0: powering up scp
10639 01:33:42.008745 <6>[ 6.571361] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10640 01:33:42.015566 <6>[ 6.571392] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10641 01:33:42.021767 <3>[ 6.577065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10642 01:33:42.031971 <3>[ 6.577106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10643 01:33:42.038603 <3>[ 6.577114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10644 01:33:42.042067 <6>[ 6.591348] mc: Linux media interface: v0.10
10645 01:33:42.052464 <6>[ 6.592587] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10646 01:33:42.058627 <3>[ 6.593096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10647 01:33:42.066001 <3>[ 6.593175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10648 01:33:42.075417 <3>[ 6.593180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 01:33:42.082262 <3>[ 6.593192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 01:33:42.092834 <3>[ 6.593197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 01:33:42.098853 <3>[ 6.593250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 01:33:42.108353 <3>[ 6.593294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10653 01:33:42.115940 <3>[ 6.593297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 01:33:42.125140 <3>[ 6.593301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10655 01:33:42.131735 <3>[ 6.593344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 01:33:42.138112 <3>[ 6.593351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10657 01:33:42.148227 <3>[ 6.593357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10658 01:33:42.154653 <3>[ 6.593361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10659 01:33:42.164819 <3>[ 6.593365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10660 01:33:42.171606 <3>[ 6.593392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 01:33:42.178520 <4>[ 6.594065] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10662 01:33:42.188306 <4>[ 6.594329] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10663 01:33:42.191080 <6>[ 6.614670] videodev: Linux video capture interface: v2.00
10664 01:33:42.201111 <4>[ 6.615431] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10665 01:33:42.207762 <4>[ 6.615431] Fallback method does not support PEC.
10666 01:33:42.214042 <3>[ 6.638461] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10667 01:33:42.224262 <3>[ 6.663370] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10668 01:33:42.230634 <6>[ 6.676134] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10669 01:33:42.237914 <6>[ 6.676158] pci_bus 0000:00: root bus resource [bus 00-ff]
10670 01:33:42.244025 <6>[ 6.676165] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10671 01:33:42.254009 <6>[ 6.676176] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10672 01:33:42.260570 <6>[ 6.676250] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10673 01:33:42.266870 <6>[ 6.676279] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10674 01:33:42.270513 <6>[ 6.676399] pci 0000:00:00.0: supports D1 D2
10675 01:33:42.276962 <6>[ 6.676403] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10676 01:33:42.287168 <6>[ 6.678992] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10677 01:33:42.293165 <6>[ 6.683339] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10678 01:33:42.300337 <6>[ 6.683383] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10679 01:33:42.306538 <6>[ 6.683405] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10680 01:33:42.317238 <6>[ 6.683423] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10681 01:33:42.319718 <6>[ 6.683557] pci 0000:01:00.0: supports D1 D2
10682 01:33:42.326256 <6>[ 6.683560] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10683 01:33:42.332981 <6>[ 6.696754] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10684 01:33:42.343022 <6>[ 6.696806] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10685 01:33:42.349501 <6>[ 6.696814] remoteproc remoteproc0: remote processor scp is now up
10686 01:33:42.356320 <6>[ 6.697020] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10687 01:33:42.362455 <6>[ 6.697095] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10688 01:33:42.372955 <6>[ 6.697102] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10689 01:33:42.379156 <6>[ 6.697117] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10690 01:33:42.389006 <6>[ 6.697132] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10691 01:33:42.396047 <6>[ 6.697148] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10692 01:33:42.402585 <6>[ 6.697164] pci 0000:00:00.0: PCI bridge to [bus 01]
10693 01:33:42.409680 <6>[ 6.697178] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10694 01:33:42.415764 <6>[ 6.697430] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10695 01:33:42.422017 <6>[ 6.698837] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10696 01:33:42.428401 <6>[ 6.699227] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10697 01:33:42.435287 <6>[ 6.701240] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10698 01:33:42.445087 <6>[ 6.712073] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10699 01:33:42.451982 <6>[ 6.713960] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10700 01:33:42.461637 <6>[ 6.761845] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10701 01:33:42.472593 <6>[ 6.762254] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10702 01:33:42.481386 <5>[ 6.787836] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10703 01:33:42.488625 <5>[ 6.801955] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10704 01:33:42.495079 <5>[ 6.802205] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10705 01:33:42.504435 <4>[ 6.802272] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10706 01:33:42.507921 <6>[ 6.802280] cfg80211: failed to load regulatory.db
10707 01:33:42.511071 <6>[ 6.811567] Bluetooth: Core ver 2.22
10708 01:33:42.517709 <6>[ 6.811698] NET: Registered PF_BLUETOOTH protocol family
10709 01:33:42.524422 <6>[ 6.811709] Bluetooth: HCI device and connection manager initialized
10710 01:33:42.530967 <6>[ 6.811743] Bluetooth: HCI socket layer initialized
10711 01:33:42.534117 <6>[ 6.811753] Bluetooth: L2CAP socket layer initialized
10712 01:33:42.540889 <6>[ 6.811769] Bluetooth: SCO socket layer initialized
10713 01:33:42.547485 <6>[ 6.812316] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10714 01:33:42.560505 <6>[ 6.813531] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10715 01:33:42.567142 <6>[ 6.813655] usbcore: registered new interface driver uvcvideo
10716 01:33:42.573493 <6>[ 6.855662] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10717 01:33:42.577412 <6>[ 6.874533] usbcore: registered new interface driver btusb
10718 01:33:42.589876 <4>[ 6.875613] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10719 01:33:42.593232 <3>[ 6.875627] Bluetooth: hci0: Failed to load firmware file (-2)
10720 01:33:42.600433 <3>[ 6.875630] Bluetooth: hci0: Failed to set up firmware (-2)
10721 01:33:42.610167 <4>[ 6.875632] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10722 01:33:42.620116 <6>[ 6.910032] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10723 01:33:42.623319 <6>[ 6.910135] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10724 01:33:42.630045 <6>[ 6.929130] mt7921e 0000:01:00.0: ASIC revision: 79610010
10725 01:33:42.639418 <6>[ 7.024392] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10726 01:33:42.639919 <6>[ 7.024392]
10727 01:33:42.643033 Begin: Loading essential drivers ... done.
10728 01:33:42.649868 Begin: Running /scripts/init-premount ... done.
10729 01:33:42.656352 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10730 01:33:42.662997 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10731 01:33:42.666809 Device /sys/class/net/eth0 found
10732 01:33:42.667215 done.
10733 01:33:42.694217 Begin: Waiting up to 180 secs for any network device to become available ... done.
10734 01:33:42.700962 <6>[ 7.285993] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10735 01:33:42.746633 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10736 01:33:42.754560 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10737 01:33:42.761503 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10738 01:33:42.767998 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10739 01:33:42.773779 host : mt8192-asurada-spherion-r0-cbg-2
10740 01:33:42.780442 domain : lava-rack
10741 01:33:42.783915 rootserver: 192.168.201.1 rootpath:
10742 01:33:42.787063 filename :
10743 01:33:42.924590 done.
10744 01:33:42.933184 Begin: Running /scripts/nfs-bottom ... done.
10745 01:33:42.958175 Begin: Running /scripts/init-bottom ... done.
10746 01:33:44.354187 <6>[ 8.942258] NET: Registered PF_INET6 protocol family
10747 01:33:44.357796 <6>[ 8.943785] Segment Routing with IPv6
10748 01:33:44.363932 <6>[ 8.943803] In-situ OAM (IOAM) with IPv6
10749 01:33:44.532974 <30>[ 9.093758] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10750 01:33:44.539572 <30>[ 9.093799] systemd[1]: Detected architecture arm64.
10751 01:33:44.540097
10752 01:33:44.546479 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10753 01:33:44.547000
10754 01:33:44.570468 <30>[ 9.159429] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10755 01:33:45.804987 <30>[ 10.390266] systemd[1]: Queued start job for default target graphical.target.
10756 01:33:45.862564 [[0;32m OK [0m] Created slic<30>[ 10.446469] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10757 01:33:45.865630 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10758 01:33:45.891729 [[0;32m OK [0m] Created slic<30>[ 10.475087] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10759 01:33:45.894607 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10760 01:33:45.918748 [[0;32m OK [0m] Created slic<30>[ 10.502936] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10761 01:33:45.925209 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10762 01:33:45.946037 [[0;32m OK [0m] Created slic<30>[ 10.530540] systemd[1]: Created slice user.slice - User and Session Slice.
10763 01:33:45.949459 e [0;1;39muser.slice[0m - User and Session Slice.
10764 01:33:45.977421 [[0;32m OK [0m] Started [0;<30>[ 10.558124] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10765 01:33:45.980328 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10766 01:33:46.004567 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 10.585467] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10767 01:33:46.007674 -passwo… Requests to Wall Directory Watch.
10768 01:33:46.042721 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 10.613456] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10769 01:33:46.048870 <30>[ 10.613590] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10770 01:33:46.052404 ice[0m - /dev/ttyS0...
10771 01:33:46.073342 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 10.657653] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10772 01:33:46.077293 tsetup.…get[0m - Local Encrypted Volumes.
10773 01:33:46.104357 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 10.685300] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10774 01:33:46.107533 grityse…Local Integrity Protected Volumes.
10775 01:33:46.129646 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 10.713778] systemd[1]: Reached target paths.target - Path Units.
10776 01:33:46.133242 s.target[0m - Path Units.
10777 01:33:46.154008 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 10.737679] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10778 01:33:46.157106 te-fs.target[0m - Remote File Systems.
10779 01:33:46.177352 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 10.761235] systemd[1]: Reached target slices.target - Slice Units.
10780 01:33:46.180329 es.target[0m - Slice Units.
10781 01:33:46.201292 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 10.785699] systemd[1]: Reached target swap.target - Swaps.
10782 01:33:46.201787 .target[0m - Swaps.
10783 01:33:46.225393 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 10.809785] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10784 01:33:46.231875 tysetup… - Local Verity Protected Volumes.
10785 01:33:46.253913 [[0;32m OK [0m] Listening on<30>[ 10.838169] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10786 01:33:46.260703 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10787 01:33:46.281710 <30>[ 10.868900] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10788 01:33:46.291363 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10789 01:33:46.310459 [[0;32m OK [0m] Listening on<30>[ 10.894861] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10790 01:33:46.317279 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10791 01:33:46.337583 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.921858] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10792 01:33:46.340538 d-journald.socket[0m - Journal Socket.
10793 01:33:46.362617 [[0;32m OK [0m] Listening on<30>[ 10.946900] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10794 01:33:46.369151 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10795 01:33:46.393656 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.977720] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10796 01:33:46.400583 d-udevd….socket[0m - udev Control Socket.
10797 01:33:46.421362 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.005725] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10798 01:33:46.425319 d-udevd…l.socket[0m - udev Kernel Socket.
10799 01:33:46.481783 Mounting [0;1;39mdev-hugepages.mount[<30>[ 11.065682] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10800 01:33:46.484847 0m - Huge Pages File System...
10801 01:33:46.503763 Mountin<30>[ 11.091660] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10802 01:33:46.510330 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10803 01:33:46.536689 Mounting [0;1;39msys-kernel-debug.…<30>[ 11.121010] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10804 01:33:46.539975 [0m - Kernel Debug File System...
10805 01:33:46.567957 <30>[ 11.145731] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10806 01:33:46.577809 <30>[ 11.153968] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10807 01:33:46.584369 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10808 01:33:46.614772 Starting [0;1;39mmodpr<30>[ 11.198206] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10809 01:33:46.617214 obe@configfs…m - Load Kernel Module configfs...
10810 01:33:46.646752 Starting [0;1;39mmodpr<30>[ 11.230911] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10811 01:33:46.650205 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10812 01:33:46.678782 Starting [0;1;39mmodpr<30>[ 11.262973] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10813 01:33:46.682371 obe@drm.service[0m - Load Kernel Module drm...
10814 01:33:46.693077 <6>[ 11.280771] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10815 01:33:46.712520 Startin<30>[ 11.296365] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10816 01:33:46.715572 g [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10817 01:33:46.742940 Starting [0;1;39mmodpr<30>[ 11.327012] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10818 01:33:46.746426 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10819 01:33:46.775222 Starting [0;1;39mmodpr<30>[ 11.359339] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10820 01:33:46.779248 obe@loop.ser…e[0m - Load Kernel Module loop...
10821 01:33:46.785884 <6>[ 11.374302] fuse: init (API version 7.37)
10822 01:33:46.804672 Startin<30>[ 11.391954] systemd[1]: Starting systemd-journald.service - Journal Service...
10823 01:33:46.811480 g [0;1;39msystemd-journald.service[0m - Journal Service...
10824 01:33:46.851196 Starting [0;1;39msyste<30>[ 11.434606] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10825 01:33:46.853604 md-modules-l…rvice[0m - Load Kernel Modules...
10826 01:33:46.883909 Startin<30>[ 11.467982] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10827 01:33:46.890776 g [0;1;39msystemd-network-g… units from Kernel command line...
10828 01:33:46.946274 Starting [0;1;39msyste<30>[ 11.530260] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10829 01:33:46.952868 md-remount-f…nt Root and Kernel File Systems...
10830 01:33:46.969422 <3>[ 11.553366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10831 01:33:46.979851 <30>[ 11.560213] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10832 01:33:46.989489 Starting [0;1;39msyste<3>[ 11.573850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 01:33:46.996440 md-udev-trig…[0m - Coldplug All udev Devices...
10834 01:33:47.017188 <3>[ 11.603777] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 01:33:47.027780 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepag<30>[ 11.605998] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10836 01:33:47.041039 es.mount[0m - H<3>[ 11.625409] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 01:33:47.041567 uge Pages File System.
10838 01:33:47.061081 <3>[ 11.645638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 01:33:47.071555 [[0;32m OK [0m] Mounted [0;<30>[ 11.658251] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10840 01:33:47.081930 1;39mdev-mqueue.<3>[ 11.667562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10841 01:33:47.088327 mount[…- POSIX Message Queue File System.
10842 01:33:47.100921 <3>[ 11.687889] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 01:33:47.111596 [[0;32m OK [0m] Mounted [0;<30>[ 11.698298] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10844 01:33:47.124689 1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 11.709645] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10845 01:33:47.128007 File System.
10846 01:33:47.145644 <3>[ 11.729819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 01:33:47.159952 [[0;32m OK [0m] Finished [0<30>[ 11.742804] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10848 01:33:47.169309 ;1;39mkmod-stati<3>[ 11.751189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 01:33:47.172741 c-nodes…reate List of Static Device Nodes.
10850 01:33:47.186285 <3>[ 11.771239] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 01:33:47.196810 [[0;32m OK [0m] Finished [0<30>[ 11.782990] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10852 01:33:47.206527 <30>[ 11.783422] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10853 01:33:47.216373 ;1;39mmodprobe@c<3>[ 11.795440] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 01:33:47.220135 onfigfs…[0m - Load Kernel Module configfs.
10855 01:33:47.242234 [[0;32m OK [0m] Finished [0<3>[ 11.825607] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 01:33:47.252434 ;1;39mmodprobe@d<30>[ 11.826097] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10857 01:33:47.259117 m_mod.s…e[0m <30>[ 11.826535] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10858 01:33:47.269063 - Load Kernel Mo<3>[ 11.849376] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 01:33:47.272225 dule dm_mod.
10860 01:33:47.296566 [[0;32m OK [0m] Finished [0<30>[ 11.882663] systemd[1]: modprobe@drm.service: Deactivated successfully.
10861 01:33:47.305917 ;1;39mmodprobe@d<30>[ 11.883322] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10862 01:33:47.309079 rm.service[0m - Load Kernel Module drm.
10863 01:33:47.338293 [[0;32m OK [0m] Started [0;<30>[ 11.922230] systemd[1]: Started systemd-journald.service - Journal Service.
10864 01:33:47.341842 1;39msystemd-journald.service[0m - Journal Service.
10865 01:33:47.363570 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10866 01:33:47.382938 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10867 01:33:47.408290 <4>[ 11.986472] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10868 01:33:47.418060 <3>[ 11.986485] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10869 01:33:47.424744 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10870 01:33:47.443270 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10871 01:33:47.463354 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10872 01:33:47.487288 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10873 01:33:47.506660 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10874 01:33:47.528702 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10875 01:33:47.594040 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10876 01:33:47.614415 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10877 01:33:47.638589 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10878 01:33:47.674038 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10879 01:33:47.708666 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10880 01:33:47.718575 <46>[ 12.304378] systemd-journald[314]: Received client request to flush runtime journal.
10881 01:33:47.733658 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10882 01:33:47.768713 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10883 01:33:47.786898 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10884 01:33:47.810956 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10885 01:33:48.404656 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10886 01:33:48.848685 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10887 01:33:48.902469 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10888 01:33:49.164163 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10889 01:33:49.302152 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10890 01:33:49.322170 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10891 01:33:49.341841 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10892 01:33:49.403282 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10893 01:33:49.425846 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10894 01:33:49.683260 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10895 01:33:49.735820 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10896 01:33:49.842506 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10897 01:33:50.111489 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10898 01:33:50.158094 <6>[ 14.745319] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10899 01:33:50.168430 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10900 01:33:50.207165 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10901 01:33:50.343855 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10902 01:33:50.362655 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10903 01:33:50.397675 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10904 01:33:50.454508 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10905 01:33:50.480252 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10906 01:33:50.498651 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10907 01:33:50.515123 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10908 01:33:50.570298 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10909 01:33:50.615952 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10910 01:33:50.646705 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10911 01:33:50.673942 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10912 01:33:50.694152 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10913 01:33:50.717376 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10914 01:33:50.737213 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10915 01:33:50.770035 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10916 01:33:50.789324 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10917 01:33:50.805338 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10918 01:33:50.826072 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10919 01:33:50.849760 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10920 01:33:50.869241 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10921 01:33:50.888068 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10922 01:33:50.905445 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10923 01:33:50.921935 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10924 01:33:50.974326 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10925 01:33:51.037449 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10926 01:33:51.127044 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10927 01:33:51.156493 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10928 01:33:51.204746 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10929 01:33:51.263113 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10930 01:33:51.287568 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10931 01:33:51.305644 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10932 01:33:51.437325 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10933 01:33:51.489598 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10934 01:33:51.512951 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10935 01:33:51.532657 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10936 01:33:51.550097 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10937 01:33:51.611647 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10938 01:33:51.695744 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10939 01:33:51.783503
10940 01:33:51.786481 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10941 01:33:51.786583
10942 01:33:51.789822 debian-bookworm-arm64 login: root (automatic login)
10943 01:33:51.789933
10944 01:33:52.131821 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10945 01:33:52.132367
10946 01:33:52.138757 The programs included with the Debian GNU/Linux system are free software;
10947 01:33:52.144983 the exact distribution terms for each program are described in the
10948 01:33:52.148295 individual files in /usr/share/doc/*/copyright.
10949 01:33:52.148376
10950 01:33:52.154650 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10951 01:33:52.157794 permitted by applicable law.
10952 01:33:53.378459 Matched prompt #10: / #
10954 01:33:53.379582 Setting prompt string to ['/ #']
10955 01:33:53.380003 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10957 01:33:53.380947 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10958 01:33:53.381406 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
10959 01:33:53.381759 Setting prompt string to ['/ #']
10960 01:33:53.382062 Forcing a shell prompt, looking for ['/ #']
10962 01:33:53.432853 / #
10963 01:33:53.433516 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10964 01:33:53.433945 Waiting using forced prompt support (timeout 00:02:30)
10965 01:33:53.439490
10966 01:33:53.440409 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10967 01:33:53.440907 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
10969 01:33:53.542300 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l'
10970 01:33:53.549060 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173483/extract-nfsrootfs-0yie_t6l'
10972 01:33:53.650818 / # export NFS_SERVER_IP='192.168.201.1'
10973 01:33:53.657663 export NFS_SERVER_IP='192.168.201.1'
10974 01:33:53.658591 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10975 01:33:53.659112 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
10976 01:33:53.659586 end: 2 depthcharge-action (duration 00:01:47) [common]
10977 01:33:53.660077 start: 3 lava-test-retry (timeout 00:07:36) [common]
10978 01:33:53.660528 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
10979 01:33:53.660983 Using namespace: common
10981 01:33:53.762243 / # #
10982 01:33:53.762873 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10983 01:33:53.768265 #
10984 01:33:53.769128 Using /lava-14173483
10986 01:33:53.870315 / # export SHELL=/bin/bash
10987 01:33:53.876577 export SHELL=/bin/bash
10989 01:33:53.978075 / # . /lava-14173483/environment
10990 01:33:53.984719 . /lava-14173483/environment
10992 01:33:54.092589 / # /lava-14173483/bin/lava-test-runner /lava-14173483/0
10993 01:33:54.093203 Test shell timeout: 10s (minimum of the action and connection timeout)
10994 01:33:54.099296 /lava-14173483/bin/lava-test-runner /lava-14173483/0
10995 01:33:54.435844 + export TESTRUN_ID=0_timesync-off
10996 01:33:54.439057 + TESTRUN_ID=0_timesync-off
10997 01:33:54.442550 + cd /lava-14173483/0/tests/0_timesync-off
10998 01:33:54.445831 ++ cat uuid
10999 01:33:54.456009 + UUID=14173483_1.6.2.3.1
11000 01:33:54.456425 + set +x
11001 01:33:54.462380 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14173483_1.6.2.3.1>
11002 01:33:54.463135 Received signal: <STARTRUN> 0_timesync-off 14173483_1.6.2.3.1
11003 01:33:54.463573 Starting test lava.0_timesync-off (14173483_1.6.2.3.1)
11004 01:33:54.463990 Skipping test definition patterns.
11005 01:33:54.465636 + systemctl stop systemd-timesyncd
11006 01:33:54.554412 + set +x
11007 01:33:54.557701 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14173483_1.6.2.3.1>
11008 01:33:54.558494 Received signal: <ENDRUN> 0_timesync-off 14173483_1.6.2.3.1
11009 01:33:54.558917 Ending use of test pattern.
11010 01:33:54.559257 Ending test lava.0_timesync-off (14173483_1.6.2.3.1), duration 0.10
11012 01:33:54.663021 + export TESTRUN_ID=1_kselftest-rtc
11013 01:33:54.666436 + TESTRUN_ID=1_kselftest-rtc
11014 01:33:54.669818 + cd /lava-14173483/0/tests/1_kselftest-rtc
11015 01:33:54.672632 ++ cat uuid
11016 01:33:54.680910 + UUID=14173483_1.6.2.3.5
11017 01:33:54.684656 + set +x
11018 01:33:54.687721 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14173483_1.6.2.3.5>
11019 01:33:54.688388 Received signal: <STARTRUN> 1_kselftest-rtc 14173483_1.6.2.3.5
11020 01:33:54.688735 Starting test lava.1_kselftest-rtc (14173483_1.6.2.3.5)
11021 01:33:54.689205 Skipping test definition patterns.
11022 01:33:54.691063 + cd ./automated/linux/kselftest/
11023 01:33:54.720755 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11024 01:33:54.783473 INFO: install_deps skipped
11025 01:33:55.308933 --2024-06-05 01:33:55-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11026 01:33:55.316346 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11027 01:33:55.436493 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11028 01:33:55.564860 HTTP request sent, awaiting response... 200 OK
11029 01:33:55.568182 Length: 1648104 (1.6M) [application/octet-stream]
11030 01:33:55.572571 Saving to: 'kselftest_armhf.tar.gz'
11031 01:33:55.573119
11032 01:33:55.573570
11033 01:33:55.816014 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11034 01:33:56.068020 kselftest_armhf.tar 2%[ ] 47.81K 191KB/s
11035 01:33:56.492023 kselftest_armhf.tar 13%[=> ] 219.84K 438KB/s
11036 01:33:56.570666 kselftest_armhf.tar 50%[=========> ] 812.82K 877KB/s
11037 01:33:56.577115 kselftest_armhf.tar 100%[===================>] 1.57M 1.56MB/s in 1.0s
11038 01:33:56.577618
11039 01:33:56.721842 2024-06-05 01:33:56 (1.56 MB/s) - 'kselftest_armhf.tar.gz' saved [1648104/1648104]
11040 01:33:56.722000
11041 01:34:02.443612 skiplist:
11042 01:34:02.446998 ========================================
11043 01:34:02.449992 ========================================
11044 01:34:02.510380 rtc:rtctest
11045 01:34:02.534513 ============== Tests to run ===============
11046 01:34:02.538360 rtc:rtctest
11047 01:34:02.541321 ===========End Tests to run ===============
11048 01:34:02.547148 shardfile-rtc pass
11049 01:34:02.679986 <12>[ 27.272700] kselftest: Running tests in rtc
11050 01:34:02.686247 TAP version 13
11051 01:34:02.704022 1..1
11052 01:34:02.744675 # selftests: rtc: rtctest
11053 01:34:03.255429 # TAP version 13
11054 01:34:03.256170 # 1..8
11055 01:34:03.258316 # # Starting 8 tests from 2 test cases.
11056 01:34:03.261760 # # RUN rtc.date_read ...
11057 01:34:03.268178 # # rtctest.c:49:date_read:Current RTC date/time is 05/06/2024 01:34:02.
11058 01:34:03.271153 # # OK rtc.date_read
11059 01:34:03.274594 # ok 1 rtc.date_read
11060 01:34:03.277926 # # RUN rtc.date_read_loop ...
11061 01:34:03.287893 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11062 01:34:13.296191 <6>[ 37.889241] vpu: disabling
11063 01:34:13.298988 <6>[ 37.889362] vproc2: disabling
11064 01:34:13.302531 <6>[ 37.889416] vproc1: disabling
11065 01:34:13.305804 <6>[ 37.889469] vaud18: disabling
11066 01:34:13.309165 <6>[ 37.889718] vsram_others: disabling
11067 01:34:13.312494 <6>[ 37.889895] va09: disabling
11068 01:34:13.315619 <6>[ 37.889972] vsram_md: disabling
11069 01:34:13.319070 <6>[ 37.890102] Vgpu: disabling
11070 01:34:33.007705 # # rtctest.c:115:date_read_loop:Performed 2612 RTC time reads.
11071 01:34:33.014175 # # OK rtc.date_read_loop
11072 01:34:33.014629 # ok 2 rtc.date_read_loop
11073 01:34:33.017587 # # RUN rtc.uie_read ...
11074 01:34:35.992376 # # OK rtc.uie_read
11075 01:34:35.995534 # ok 3 rtc.uie_read
11076 01:34:35.999139 # # RUN rtc.uie_select ...
11077 01:34:38.991658 # # OK rtc.uie_select
11078 01:34:38.995070 # ok 4 rtc.uie_select
11079 01:34:38.998097 # # RUN rtc.alarm_alm_set ...
11080 01:34:39.005350 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 01:34:42.
11081 01:34:39.008315 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11082 01:34:39.015151 # # alarm_alm_set: Test terminated by assertion
11083 01:34:39.017804 # # FAIL rtc.alarm_alm_set
11084 01:34:39.021655 # not ok 5 rtc.alarm_alm_set
11085 01:34:39.024654 # # RUN rtc.alarm_wkalm_set ...
11086 01:34:39.031389 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 05/06/2024 01:34:42.
11087 01:34:41.994524 # # OK rtc.alarm_wkalm_set
11088 01:34:41.995019 # ok 6 rtc.alarm_wkalm_set
11089 01:34:42.001686 # # RUN rtc.alarm_alm_set_minute ...
11090 01:34:42.004547 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 01:35:00.
11091 01:34:42.011223 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11092 01:34:42.018778 # # alarm_alm_set_minute: Test terminated by assertion
11093 01:34:42.020533 # # FAIL rtc.alarm_alm_set_minute
11094 01:34:42.024042 # not ok 7 rtc.alarm_alm_set_minute
11095 01:34:42.027425 # # RUN rtc.alarm_wkalm_set_minute ...
11096 01:34:42.034400 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 05/06/2024 01:35:00.
11097 01:34:59.992423 # # OK rtc.alarm_wkalm_set_minute
11098 01:34:59.995634 # ok 8 rtc.alarm_wkalm_set_minute
11099 01:34:59.998663 # # FAILED: 6 / 8 tests passed.
11100 01:35:00.001979 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11101 01:35:00.005083 not ok 1 selftests: rtc: rtctest # exit=1
11102 01:35:01.647575 rtc_rtctest_rtc_date_read pass
11103 01:35:01.650918 rtc_rtctest_rtc_date_read_loop pass
11104 01:35:01.654043 rtc_rtctest_rtc_uie_read pass
11105 01:35:01.657302 rtc_rtctest_rtc_uie_select pass
11106 01:35:01.660807 rtc_rtctest_rtc_alarm_alm_set fail
11107 01:35:01.663805 rtc_rtctest_rtc_alarm_wkalm_set pass
11108 01:35:01.667320 rtc_rtctest_rtc_alarm_alm_set_minute fail
11109 01:35:01.670787 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11110 01:35:01.674030 rtc_rtctest fail
11111 01:35:01.725707 + ../../utils/send-to-lava.sh ./output/result.txt
11112 01:35:01.831305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11113 01:35:01.832090 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11115 01:35:01.901398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11116 01:35:01.902147 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11118 01:35:01.973815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11119 01:35:01.974570 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11121 01:35:02.035057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11122 01:35:02.035766 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11124 01:35:02.109372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11125 01:35:02.110121 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11127 01:35:02.181847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11128 01:35:02.182633 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11130 01:35:02.250799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11131 01:35:02.251603 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11133 01:35:02.317639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11134 01:35:02.318359 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11136 01:35:02.391469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11137 01:35:02.392248 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11139 01:35:02.458328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11140 01:35:02.458855 + set +x
11141 01:35:02.459459 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11143 01:35:02.464685 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14173483_1.6.2.3.5>
11144 01:35:02.465389 Received signal: <ENDRUN> 1_kselftest-rtc 14173483_1.6.2.3.5
11145 01:35:02.465766 Ending use of test pattern.
11146 01:35:02.466077 Ending test lava.1_kselftest-rtc (14173483_1.6.2.3.5), duration 67.78
11148 01:35:02.467139 ok: lava_test_shell seems to have completed
11149 01:35:02.467808 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11150 01:35:02.468352 end: 3.1 lava-test-shell (duration 00:01:09) [common]
11151 01:35:02.468758 end: 3 lava-test-retry (duration 00:01:09) [common]
11152 01:35:02.469218 start: 4 finalize (timeout 00:06:27) [common]
11153 01:35:02.469685 start: 4.1 power-off (timeout 00:00:30) [common]
11154 01:35:02.470424 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11155 01:35:02.736241 >> Command sent successfully.
11156 01:35:02.747141 Returned 0 in 0 seconds
11157 01:35:02.848488 end: 4.1 power-off (duration 00:00:00) [common]
11159 01:35:02.850118 start: 4.2 read-feedback (timeout 00:06:27) [common]
11161 01:35:02.852531 Listened to connection for namespace 'common' for up to 1s
11162 01:35:03.852192 Finalising connection for namespace 'common'
11163 01:35:03.852934 Disconnecting from shell: Finalise
11164 01:35:03.853383 / #
11165 01:35:03.954396 end: 4.2 read-feedback (duration 00:00:01) [common]
11166 01:35:03.955134 end: 4 finalize (duration 00:00:01) [common]
11167 01:35:03.955786 Cleaning after the job
11168 01:35:03.956354 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/ramdisk
11169 01:35:03.961099 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/kernel
11170 01:35:03.971391 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/dtb
11171 01:35:03.971563 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/nfsrootfs
11172 01:35:04.033946 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173483/tftp-deploy-9poujol5/modules
11173 01:35:04.039405 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173483
11174 01:35:04.597283 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173483
11175 01:35:04.597472 Job finished correctly