Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
1 00:39:11.137314 lava-dispatcher, installed at version: 2024.03
2 00:39:11.137515 start: 0 validate
3 00:39:11.137650 Start time: 2024-06-05 00:39:11.137643+00:00 (UTC)
4 00:39:11.137768 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:39:11.137896 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:39:11.140568 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:39:11.140693 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:39:22.642414 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:39:22.643107 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:39:22.895606 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:39:22.895784 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:39:23.143318 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:39:23.143536 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:39:28.145238 validate duration: 17.01
16 00:39:28.145512 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:39:28.145610 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:39:28.145697 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:39:28.145819 Not decompressing ramdisk as can be used compressed.
20 00:39:28.145905 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:39:28.145970 saving as /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/ramdisk/initrd.cpio.gz
22 00:39:28.146035 total size: 5628169 (5 MB)
23 00:39:28.147110 progress 0 % (0 MB)
24 00:39:28.148720 progress 5 % (0 MB)
25 00:39:28.150272 progress 10 % (0 MB)
26 00:39:28.151662 progress 15 % (0 MB)
27 00:39:28.153209 progress 20 % (1 MB)
28 00:39:28.154658 progress 25 % (1 MB)
29 00:39:28.156213 progress 30 % (1 MB)
30 00:39:28.157751 progress 35 % (1 MB)
31 00:39:28.159160 progress 40 % (2 MB)
32 00:39:28.160734 progress 45 % (2 MB)
33 00:39:28.162097 progress 50 % (2 MB)
34 00:39:28.163618 progress 55 % (2 MB)
35 00:39:28.165190 progress 60 % (3 MB)
36 00:39:28.166635 progress 65 % (3 MB)
37 00:39:28.168168 progress 70 % (3 MB)
38 00:39:28.169589 progress 75 % (4 MB)
39 00:39:28.171120 progress 80 % (4 MB)
40 00:39:28.172488 progress 85 % (4 MB)
41 00:39:28.174053 progress 90 % (4 MB)
42 00:39:28.175567 progress 95 % (5 MB)
43 00:39:28.176994 progress 100 % (5 MB)
44 00:39:28.177203 5 MB downloaded in 0.03 s (172.22 MB/s)
45 00:39:28.177355 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:39:28.177672 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:39:28.177759 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:39:28.177844 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:39:28.177976 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:39:28.178045 saving as /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/kernel/Image
52 00:39:28.178106 total size: 54682112 (52 MB)
53 00:39:28.178167 No compression specified
54 00:39:28.179205 progress 0 % (0 MB)
55 00:39:28.193092 progress 5 % (2 MB)
56 00:39:28.206991 progress 10 % (5 MB)
57 00:39:28.220942 progress 15 % (7 MB)
58 00:39:28.234782 progress 20 % (10 MB)
59 00:39:28.248667 progress 25 % (13 MB)
60 00:39:28.262536 progress 30 % (15 MB)
61 00:39:28.276451 progress 35 % (18 MB)
62 00:39:28.290241 progress 40 % (20 MB)
63 00:39:28.304157 progress 45 % (23 MB)
64 00:39:28.318451 progress 50 % (26 MB)
65 00:39:28.332392 progress 55 % (28 MB)
66 00:39:28.346272 progress 60 % (31 MB)
67 00:39:28.360331 progress 65 % (33 MB)
68 00:39:28.374306 progress 70 % (36 MB)
69 00:39:28.388085 progress 75 % (39 MB)
70 00:39:28.402111 progress 80 % (41 MB)
71 00:39:28.415925 progress 85 % (44 MB)
72 00:39:28.430235 progress 90 % (46 MB)
73 00:39:28.444169 progress 95 % (49 MB)
74 00:39:28.457796 progress 100 % (52 MB)
75 00:39:28.458052 52 MB downloaded in 0.28 s (186.28 MB/s)
76 00:39:28.458206 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:39:28.458483 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:39:28.458573 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:39:28.458660 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:39:28.458789 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:39:28.458867 saving as /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/dtb/mt8192-asurada-spherion-r0.dtb
83 00:39:28.458933 total size: 47258 (0 MB)
84 00:39:28.458998 No compression specified
85 00:39:28.460218 progress 69 % (0 MB)
86 00:39:28.460528 progress 100 % (0 MB)
87 00:39:28.460714 0 MB downloaded in 0.00 s (25.34 MB/s)
88 00:39:28.460841 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:39:28.461074 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:39:28.461161 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:39:28.461246 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:39:28.461357 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:39:28.461430 saving as /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/nfsrootfs/full.rootfs.tar
95 00:39:28.461494 total size: 120894716 (115 MB)
96 00:39:28.461559 Using unxz to decompress xz
97 00:39:28.465324 progress 0 % (0 MB)
98 00:39:28.812542 progress 5 % (5 MB)
99 00:39:29.172037 progress 10 % (11 MB)
100 00:39:29.523789 progress 15 % (17 MB)
101 00:39:29.851850 progress 20 % (23 MB)
102 00:39:30.149681 progress 25 % (28 MB)
103 00:39:30.517092 progress 30 % (34 MB)
104 00:39:30.855232 progress 35 % (40 MB)
105 00:39:31.020486 progress 40 % (46 MB)
106 00:39:31.198243 progress 45 % (51 MB)
107 00:39:31.509003 progress 50 % (57 MB)
108 00:39:31.881820 progress 55 % (63 MB)
109 00:39:32.225101 progress 60 % (69 MB)
110 00:39:32.564778 progress 65 % (74 MB)
111 00:39:32.907637 progress 70 % (80 MB)
112 00:39:33.272258 progress 75 % (86 MB)
113 00:39:33.614949 progress 80 % (92 MB)
114 00:39:33.956285 progress 85 % (98 MB)
115 00:39:34.321794 progress 90 % (103 MB)
116 00:39:34.650587 progress 95 % (109 MB)
117 00:39:35.008345 progress 100 % (115 MB)
118 00:39:35.013812 115 MB downloaded in 6.55 s (17.60 MB/s)
119 00:39:35.014071 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:39:35.014350 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:39:35.014447 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:39:35.014539 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:39:35.014692 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:39:35.014766 saving as /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/modules/modules.tar
126 00:39:35.014831 total size: 8605984 (8 MB)
127 00:39:35.014899 Using unxz to decompress xz
128 00:39:35.266546 progress 0 % (0 MB)
129 00:39:35.286266 progress 5 % (0 MB)
130 00:39:35.313460 progress 10 % (0 MB)
131 00:39:35.343509 progress 15 % (1 MB)
132 00:39:35.367036 progress 20 % (1 MB)
133 00:39:35.391000 progress 25 % (2 MB)
134 00:39:35.414699 progress 30 % (2 MB)
135 00:39:35.439172 progress 35 % (2 MB)
136 00:39:35.466037 progress 40 % (3 MB)
137 00:39:35.488998 progress 45 % (3 MB)
138 00:39:35.512941 progress 50 % (4 MB)
139 00:39:35.537997 progress 55 % (4 MB)
140 00:39:35.562521 progress 60 % (4 MB)
141 00:39:35.586716 progress 65 % (5 MB)
142 00:39:35.611811 progress 70 % (5 MB)
143 00:39:35.635711 progress 75 % (6 MB)
144 00:39:35.663839 progress 80 % (6 MB)
145 00:39:35.688631 progress 85 % (7 MB)
146 00:39:35.713854 progress 90 % (7 MB)
147 00:39:35.738995 progress 95 % (7 MB)
148 00:39:35.764003 progress 100 % (8 MB)
149 00:39:35.769560 8 MB downloaded in 0.75 s (10.87 MB/s)
150 00:39:35.769826 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:39:35.770113 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:39:35.770210 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:39:35.770316 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:39:39.062972 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35
156 00:39:39.063183 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:39:39.063289 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:39:39.063455 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw
159 00:39:39.063578 makedir: /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin
160 00:39:39.063678 makedir: /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/tests
161 00:39:39.063774 makedir: /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/results
162 00:39:39.063873 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-add-keys
163 00:39:39.064010 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-add-sources
164 00:39:39.064136 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-background-process-start
165 00:39:39.064260 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-background-process-stop
166 00:39:39.064383 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-common-functions
167 00:39:39.064503 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-echo-ipv4
168 00:39:39.064641 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-install-packages
169 00:39:39.064764 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-installed-packages
170 00:39:39.064885 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-os-build
171 00:39:39.065005 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-probe-channel
172 00:39:39.065125 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-probe-ip
173 00:39:39.065246 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-target-ip
174 00:39:39.065365 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-target-mac
175 00:39:39.065484 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-target-storage
176 00:39:39.065605 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-case
177 00:39:39.065731 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-event
178 00:39:39.065851 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-feedback
179 00:39:39.065970 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-raise
180 00:39:39.066089 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-reference
181 00:39:39.066208 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-runner
182 00:39:39.066327 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-set
183 00:39:39.066447 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-test-shell
184 00:39:39.066568 Updating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-add-keys (debian)
185 00:39:39.066714 Updating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-add-sources (debian)
186 00:39:39.066859 Updating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-install-packages (debian)
187 00:39:39.066996 Updating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-installed-packages (debian)
188 00:39:39.067133 Updating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/bin/lava-os-build (debian)
189 00:39:39.067255 Creating /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/environment
190 00:39:39.067354 LAVA metadata
191 00:39:39.067421 - LAVA_JOB_ID=14173470
192 00:39:39.067483 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:39:39.067581 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:39:39.067648 skipped lava-vland-overlay
195 00:39:39.067724 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:39:39.067804 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:39:39.067865 skipped lava-multinode-overlay
198 00:39:39.067938 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:39:39.068016 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:39:39.068088 Loading test definitions
201 00:39:39.068175 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:39:39.068246 Using /lava-14173470 at stage 0
203 00:39:39.068511 uuid=14173470_1.6.2.3.1 testdef=None
204 00:39:39.068814 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:39:39.068902 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:39:39.069355 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:39:39.069580 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:39:39.070128 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:39:39.070365 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:39:39.070899 runner path: /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/0/tests/0_timesync-off test_uuid 14173470_1.6.2.3.1
213 00:39:39.071054 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:39:39.071282 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:39:39.071355 Using /lava-14173470 at stage 0
217 00:39:39.071451 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:39:39.071552 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/0/tests/1_kselftest-tpm2'
219 00:39:41.746969 Running '/usr/bin/git checkout kernelci.org
220 00:39:41.890814 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 00:39:41.891552 uuid=14173470_1.6.2.3.5 testdef=None
222 00:39:41.891713 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:39:41.891966 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 00:39:41.892764 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:39:41.893005 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 00:39:41.894024 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:39:41.894281 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 00:39:41.895250 runner path: /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/0/tests/1_kselftest-tpm2 test_uuid 14173470_1.6.2.3.5
232 00:39:41.895347 BOARD='mt8192-asurada-spherion-r0'
233 00:39:41.895415 BRANCH='cip-gitlab'
234 00:39:41.895478 SKIPFILE='/dev/null'
235 00:39:41.895539 SKIP_INSTALL='True'
236 00:39:41.895599 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:39:41.895660 TST_CASENAME=''
238 00:39:41.895717 TST_CMDFILES='tpm2'
239 00:39:41.895858 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:39:41.896074 Creating lava-test-runner.conf files
242 00:39:41.896141 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173470/lava-overlay-i1yuefbw/lava-14173470/0 for stage 0
243 00:39:41.896234 - 0_timesync-off
244 00:39:41.896307 - 1_kselftest-tpm2
245 00:39:41.896402 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:39:41.896497 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 00:39:49.339117 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:39:49.339282 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 00:39:49.339382 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:39:49.339485 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:39:49.339579 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 00:39:49.499629 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:39:49.499990 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:39:49.500111 extracting modules file /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35
255 00:39:49.704952 extracting modules file /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173470/extract-overlay-ramdisk-qfq2ew3v/ramdisk
256 00:39:49.920670 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:39:49.920846 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 00:39:49.920953 [common] Applying overlay to NFS
259 00:39:49.921052 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173470/compress-overlay-_cfqza32/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35
260 00:39:50.828064 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:39:50.828241 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 00:39:50.828344 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:39:50.828442 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 00:39:50.828533 Building ramdisk /var/lib/lava/dispatcher/tmp/14173470/extract-overlay-ramdisk-qfq2ew3v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173470/extract-overlay-ramdisk-qfq2ew3v/ramdisk
265 00:39:51.157182 >> 130348 blocks
266 00:39:53.190479 rename /var/lib/lava/dispatcher/tmp/14173470/extract-overlay-ramdisk-qfq2ew3v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/ramdisk/ramdisk.cpio.gz
267 00:39:53.190913 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:39:53.191036 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:39:53.191141 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:39:53.191246 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/kernel/Image']
271 00:40:06.842655 Returned 0 in 13 seconds
272 00:40:06.943254 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/kernel/image.itb
273 00:40:07.291786 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:40:07.292164 output: Created: Wed Jun 5 01:40:07 2024
275 00:40:07.292248 output: Image 0 (kernel-1)
276 00:40:07.292319 output: Description:
277 00:40:07.292385 output: Created: Wed Jun 5 01:40:07 2024
278 00:40:07.292462 output: Type: Kernel Image
279 00:40:07.292568 output: Compression: lzma compressed
280 00:40:07.292642 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
281 00:40:07.292706 output: Architecture: AArch64
282 00:40:07.292768 output: OS: Linux
283 00:40:07.292827 output: Load Address: 0x00000000
284 00:40:07.292887 output: Entry Point: 0x00000000
285 00:40:07.292956 output: Hash algo: crc32
286 00:40:07.293016 output: Hash value: 4c96ec19
287 00:40:07.293076 output: Image 1 (fdt-1)
288 00:40:07.293134 output: Description: mt8192-asurada-spherion-r0
289 00:40:07.293193 output: Created: Wed Jun 5 01:40:07 2024
290 00:40:07.293251 output: Type: Flat Device Tree
291 00:40:07.293316 output: Compression: uncompressed
292 00:40:07.293374 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:40:07.293430 output: Architecture: AArch64
294 00:40:07.293487 output: Hash algo: crc32
295 00:40:07.293543 output: Hash value: 0f8e4d2e
296 00:40:07.293598 output: Image 2 (ramdisk-1)
297 00:40:07.293657 output: Description: unavailable
298 00:40:07.293721 output: Created: Wed Jun 5 01:40:07 2024
299 00:40:07.293777 output: Type: RAMDisk Image
300 00:40:07.293831 output: Compression: Unknown Compression
301 00:40:07.293886 output: Data Size: 18735388 Bytes = 18296.28 KiB = 17.87 MiB
302 00:40:07.293941 output: Architecture: AArch64
303 00:40:07.293996 output: OS: Linux
304 00:40:07.294063 output: Load Address: unavailable
305 00:40:07.294120 output: Entry Point: unavailable
306 00:40:07.294176 output: Hash algo: crc32
307 00:40:07.294231 output: Hash value: 2c181c13
308 00:40:07.294286 output: Default Configuration: 'conf-1'
309 00:40:07.294342 output: Configuration 0 (conf-1)
310 00:40:07.294409 output: Description: mt8192-asurada-spherion-r0
311 00:40:07.294466 output: Kernel: kernel-1
312 00:40:07.294522 output: Init Ramdisk: ramdisk-1
313 00:40:07.294577 output: FDT: fdt-1
314 00:40:07.294632 output: Loadables: kernel-1
315 00:40:07.294688 output:
316 00:40:07.294913 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:40:07.295045 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:40:07.295192 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 00:40:07.295319 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 00:40:07.295428 No LXC device requested
321 00:40:07.295546 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:40:07.295667 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 00:40:07.295777 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:40:07.295876 Checking files for TFTP limit of 4294967296 bytes.
325 00:40:07.296406 end: 1 tftp-deploy (duration 00:00:39) [common]
326 00:40:07.296580 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:40:07.296682 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:40:07.296808 substitutions:
329 00:40:07.296887 - {DTB}: 14173470/tftp-deploy-mz3f2d94/dtb/mt8192-asurada-spherion-r0.dtb
330 00:40:07.296982 - {INITRD}: 14173470/tftp-deploy-mz3f2d94/ramdisk/ramdisk.cpio.gz
331 00:40:07.297074 - {KERNEL}: 14173470/tftp-deploy-mz3f2d94/kernel/Image
332 00:40:07.297163 - {LAVA_MAC}: None
333 00:40:07.297253 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35
334 00:40:07.297341 - {NFS_SERVER_IP}: 192.168.201.1
335 00:40:07.297429 - {PRESEED_CONFIG}: None
336 00:40:07.297516 - {PRESEED_LOCAL}: None
337 00:40:07.297603 - {RAMDISK}: 14173470/tftp-deploy-mz3f2d94/ramdisk/ramdisk.cpio.gz
338 00:40:07.297690 - {ROOT_PART}: None
339 00:40:07.297776 - {ROOT}: None
340 00:40:07.297862 - {SERVER_IP}: 192.168.201.1
341 00:40:07.297948 - {TEE}: None
342 00:40:07.298007 Parsed boot commands:
343 00:40:07.298063 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:40:07.298247 Parsed boot commands: tftpboot 192.168.201.1 14173470/tftp-deploy-mz3f2d94/kernel/image.itb 14173470/tftp-deploy-mz3f2d94/kernel/cmdline
345 00:40:07.298338 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:40:07.298433 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:40:07.298530 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:40:07.298619 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:40:07.298692 Not connected, no need to disconnect.
350 00:40:07.298768 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:40:07.298855 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:40:07.298926 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 00:40:07.302356 Setting prompt string to ['lava-test: # ']
354 00:40:07.302758 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:40:07.302875 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:40:07.303003 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:40:07.303131 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:40:07.303351 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 00:40:20.801243 Returned 0 in 13 seconds
360 00:40:20.901907 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:40:20.902372 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:40:20.902505 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:40:20.902630 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:40:20.902729 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:40:20.902840 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:40:20.903431 [Enter `^Ec?' for help]
368 00:40:20.903564
369 00:40:20.903694
370 00:40:20.903810 F0: 102B 0000
371 00:40:20.903905
372 00:40:20.903996 F3: 1001 0000 [0200]
373 00:40:20.904092
374 00:40:20.904182 F3: 1001 0000
375 00:40:20.904275
376 00:40:20.904382 F7: 102D 0000
377 00:40:20.904471
378 00:40:20.904588 F1: 0000 0000
379 00:40:20.904676
380 00:40:20.904762 V0: 0000 0000 [0001]
381 00:40:20.904856
382 00:40:20.904979 00: 0007 8000
383 00:40:20.905075
384 00:40:20.905160 01: 0000 0000
385 00:40:20.905248
386 00:40:20.905340 BP: 0C00 0209 [0000]
387 00:40:20.905425
388 00:40:20.905509 G0: 1182 0000
389 00:40:20.905602
390 00:40:20.905687 EC: 0000 0021 [4000]
391 00:40:20.905774
392 00:40:20.905863 S7: 0000 0000 [0000]
393 00:40:20.905948
394 00:40:20.906039 CC: 0000 0000 [0001]
395 00:40:20.906125
396 00:40:20.906209 T0: 0000 0040 [010F]
397 00:40:20.906300
398 00:40:20.906405 Jump to BL
399 00:40:20.906506
400 00:40:20.906599
401 00:40:20.906684
402 00:40:20.906772 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:40:20.906868 ARM64: Exception handlers installed.
404 00:40:20.906956 ARM64: Testing exception
405 00:40:20.907047 ARM64: Done test exception
406 00:40:20.907135 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:40:20.907223 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:40:20.907318 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:40:20.907406 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:40:20.907493 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:40:20.907586 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:40:20.907674 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:40:20.907761 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:40:20.907856 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:40:20.907942 WDT: Last reset was cold boot
416 00:40:20.908034 SPI1(PAD0) initialized at 2873684 Hz
417 00:40:20.908121 SPI5(PAD0) initialized at 992727 Hz
418 00:40:20.908206 VBOOT: Loading verstage.
419 00:40:20.908298 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:40:20.908386 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:40:20.908473 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:40:20.908583 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:40:20.908659 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:40:20.908717 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:40:20.908782 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 00:40:20.908844
427 00:40:20.908901
428 00:40:20.908957 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:40:20.909014 ARM64: Exception handlers installed.
430 00:40:20.909085 ARM64: Testing exception
431 00:40:20.909142 ARM64: Done test exception
432 00:40:20.909198 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:40:20.909254 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:40:20.909345 Probing TPM: . done!
435 00:40:20.909430 TPM ready after 0 ms
436 00:40:20.909516 Connected to device vid:did:rid of 1ae0:0028:00
437 00:40:20.909611 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 00:40:20.909698 Initialized TPM device CR50 revision 0
439 00:40:20.909790 tlcl_send_startup: Startup return code is 0
440 00:40:20.909877 TPM: setup succeeded
441 00:40:20.909963 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:40:20.910057 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:40:20.910144 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:40:20.910231 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:40:20.910323 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:40:20.910427 in-header: 03 07 00 00 08 00 00 00
447 00:40:20.910533 in-data: aa e4 47 04 13 02 00 00
448 00:40:20.910621 Chrome EC: UHEPI supported
449 00:40:20.910707 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:40:20.910801 in-header: 03 a9 00 00 08 00 00 00
451 00:40:20.910887 in-data: 84 60 60 08 00 00 00 00
452 00:40:20.910972 Phase 1
453 00:40:20.911065 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:40:20.911152 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:40:20.911238 VB2:vb2_check_recovery() Recovery was requested manually
456 00:40:20.911332 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:40:20.911422 Recovery requested (1009000e)
458 00:40:20.911509 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:40:20.911580 tlcl_extend: response is 0
460 00:40:20.911638 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:40:20.911695 tlcl_extend: response is 0
462 00:40:20.911751 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:40:20.911823 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 00:40:20.911881 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:40:20.911937
466 00:40:20.911994
467 00:40:20.912077 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:40:20.912164 ARM64: Exception handlers installed.
469 00:40:20.912250 ARM64: Testing exception
470 00:40:20.912343 ARM64: Done test exception
471 00:40:20.912428 pmic_efuse_setting: Set efuses in 11 msecs
472 00:40:20.912532 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:40:20.912663 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:40:20.912784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:40:20.913087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:40:20.913196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:40:20.913324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:40:20.913413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:40:20.913502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:40:20.913598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:40:20.913698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:40:20.913791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:40:20.913878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:40:20.913963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:40:20.914057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:40:20.914144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:40:20.914231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:40:20.914324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:40:20.914411 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:40:20.914497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:40:20.914590 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:40:20.914716 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:40:20.914808 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:40:20.914896 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:40:20.914982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:40:20.915075 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:40:20.915162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:40:20.915247 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:40:20.915341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:40:20.915427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:40:20.915512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:40:20.915606 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:40:20.915692 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:40:20.915784 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:40:20.915872 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:40:20.915957 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:40:20.916050 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:40:20.916137 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:40:20.916223 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:40:20.916316 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:40:20.916402 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:40:20.916488 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:40:20.916638 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:40:20.916790 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:40:20.916914 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:40:20.917002 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:40:20.917097 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:40:20.917198 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:40:20.917289 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:40:20.917376 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:40:20.917462 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:40:20.917554 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:40:20.917640 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:40:20.917727 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:40:20.917822 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:40:20.917909 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:40:20.917995 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:40:20.918090 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:40:20.918176 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:40:20.918261 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:40:20.918386 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:40:20.918472 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x35
533 00:40:20.918565 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:40:20.918672 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 00:40:20.918773 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:40:20.918864 [RTC]rtc_get_frequency_meter,154: input=15, output=773
537 00:40:20.918950 [RTC]rtc_get_frequency_meter,154: input=23, output=958
538 00:40:20.919041 [RTC]rtc_get_frequency_meter,154: input=19, output=866
539 00:40:20.919128 [RTC]rtc_get_frequency_meter,154: input=17, output=818
540 00:40:20.919214 [RTC]rtc_get_frequency_meter,154: input=16, output=794
541 00:40:20.919306 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 00:40:20.919392 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 00:40:20.919478 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
544 00:40:20.919571 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 00:40:20.919868 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
546 00:40:20.919961 ADC[4]: Raw value=902876 ID=7
547 00:40:20.920057 ADC[3]: Raw value=212810 ID=1
548 00:40:20.920145 RAM Code: 0x71
549 00:40:20.920233 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 00:40:20.920344 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 00:40:20.920448 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 00:40:20.920556 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 00:40:20.920647 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 00:40:20.920767 in-header: 03 07 00 00 08 00 00 00
555 00:40:20.920862 in-data: aa e4 47 04 13 02 00 00
556 00:40:20.920949 Chrome EC: UHEPI supported
557 00:40:20.921042 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 00:40:20.921132 in-header: 03 a9 00 00 08 00 00 00
559 00:40:20.921220 in-data: 84 60 60 08 00 00 00 00
560 00:40:20.921314 MRC: failed to locate region type 0.
561 00:40:20.921403 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 00:40:20.921490 DRAM-K: Running full calibration
563 00:40:20.921586 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 00:40:20.921674 header.status = 0x0
565 00:40:20.921761 header.version = 0x6 (expected: 0x6)
566 00:40:20.921856 header.size = 0xd00 (expected: 0xd00)
567 00:40:20.921943 header.flags = 0x0
568 00:40:20.922036 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 00:40:20.922126 read SPI 0x72590 0x1c583: 12496 us, 9290 KB/s, 74.320 Mbps
570 00:40:20.922218 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 00:40:20.922313 dram_init: ddr_geometry: 2
572 00:40:20.922401 [EMI] MDL number = 2
573 00:40:20.922487 [EMI] Get MDL freq = 0
574 00:40:20.922581 dram_init: ddr_type: 0
575 00:40:20.922700 is_discrete_lpddr4: 1
576 00:40:20.922855 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 00:40:20.922955
578 00:40:20.923046
579 00:40:20.923132 [Bian_co] ETT version 0.0.0.1
580 00:40:20.923218 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 00:40:20.923327
582 00:40:20.923427 dramc_set_vcore_voltage set vcore to 650000
583 00:40:20.923511 Read voltage for 800, 4
584 00:40:20.923603 Vio18 = 0
585 00:40:20.923688 Vcore = 650000
586 00:40:20.923776 Vdram = 0
587 00:40:20.923865 Vddq = 0
588 00:40:20.923949 Vmddr = 0
589 00:40:20.924040 dram_init: config_dvfs: 1
590 00:40:20.924127 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 00:40:20.924214 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 00:40:20.924306 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
593 00:40:20.924393 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
594 00:40:20.924500 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 00:40:20.924614 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 00:40:20.924700 MEM_TYPE=3, freq_sel=18
597 00:40:20.924791 sv_algorithm_assistance_LP4_1600
598 00:40:20.924878 ============ PULL DRAM RESETB DOWN ============
599 00:40:20.924964 ========== PULL DRAM RESETB DOWN end =========
600 00:40:20.925074 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 00:40:20.925174 ===================================
602 00:40:20.925259 LPDDR4 DRAM CONFIGURATION
603 00:40:20.925352 ===================================
604 00:40:20.925437 EX_ROW_EN[0] = 0x0
605 00:40:20.925526 EX_ROW_EN[1] = 0x0
606 00:40:20.925614 LP4Y_EN = 0x0
607 00:40:20.925699 WORK_FSP = 0x0
608 00:40:20.925789 WL = 0x2
609 00:40:20.925875 RL = 0x2
610 00:40:20.925959 BL = 0x2
611 00:40:20.926050 RPST = 0x0
612 00:40:20.926135 RD_PRE = 0x0
613 00:40:20.926219 WR_PRE = 0x1
614 00:40:20.926310 WR_PST = 0x0
615 00:40:20.926395 DBI_WR = 0x0
616 00:40:20.926479 DBI_RD = 0x0
617 00:40:20.926571 OTF = 0x1
618 00:40:20.926688 ===================================
619 00:40:20.926777 ===================================
620 00:40:20.926865 ANA top config
621 00:40:20.926950 ===================================
622 00:40:20.927042 DLL_ASYNC_EN = 0
623 00:40:20.927127 ALL_SLAVE_EN = 1
624 00:40:20.927212 NEW_RANK_MODE = 1
625 00:40:20.927306 DLL_IDLE_MODE = 1
626 00:40:20.927391 LP45_APHY_COMB_EN = 1
627 00:40:20.927476 TX_ODT_DIS = 1
628 00:40:20.927568 NEW_8X_MODE = 1
629 00:40:20.927655 ===================================
630 00:40:20.927740 ===================================
631 00:40:20.927833 data_rate = 1600
632 00:40:20.927918 CKR = 1
633 00:40:20.928003 DQ_P2S_RATIO = 8
634 00:40:20.928095 ===================================
635 00:40:20.928181 CA_P2S_RATIO = 8
636 00:40:20.928267 DQ_CA_OPEN = 0
637 00:40:20.928375 DQ_SEMI_OPEN = 0
638 00:40:20.928490 CA_SEMI_OPEN = 0
639 00:40:20.928596 CA_FULL_RATE = 0
640 00:40:20.928674 DQ_CKDIV4_EN = 1
641 00:40:20.928763 CA_CKDIV4_EN = 1
642 00:40:20.928847 CA_PREDIV_EN = 0
643 00:40:20.928903 PH8_DLY = 0
644 00:40:20.928958 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 00:40:20.929013 DQ_AAMCK_DIV = 4
646 00:40:20.929082 CA_AAMCK_DIV = 4
647 00:40:20.929138 CA_ADMCK_DIV = 4
648 00:40:20.929193 DQ_TRACK_CA_EN = 0
649 00:40:20.929250 CA_PICK = 800
650 00:40:20.929320 CA_MCKIO = 800
651 00:40:20.929377 MCKIO_SEMI = 0
652 00:40:20.929432 PLL_FREQ = 3068
653 00:40:20.929488 DQ_UI_PI_RATIO = 32
654 00:40:20.929557 CA_UI_PI_RATIO = 0
655 00:40:20.929614 ===================================
656 00:40:20.929670 ===================================
657 00:40:20.929726 memory_type:LPDDR4
658 00:40:20.929792 GP_NUM : 10
659 00:40:20.929850 SRAM_EN : 1
660 00:40:20.929905 MD32_EN : 0
661 00:40:20.929961 ===================================
662 00:40:20.930017 [ANA_INIT] >>>>>>>>>>>>>>
663 00:40:20.930084 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 00:40:20.930143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 00:40:20.930199 ===================================
666 00:40:20.930488 data_rate = 1600,PCW = 0X7600
667 00:40:20.930581 ===================================
668 00:40:20.930671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 00:40:20.930761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 00:40:20.930859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 00:40:20.930948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 00:40:20.931055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 00:40:20.931142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 00:40:20.931227 [ANA_INIT] flow start
675 00:40:20.931320 [ANA_INIT] PLL >>>>>>>>
676 00:40:20.931405 [ANA_INIT] PLL <<<<<<<<
677 00:40:20.931490 [ANA_INIT] MIDPI >>>>>>>>
678 00:40:20.931582 [ANA_INIT] MIDPI <<<<<<<<
679 00:40:20.931685 [ANA_INIT] DLL >>>>>>>>
680 00:40:20.931791 [ANA_INIT] flow end
681 00:40:20.931878 ============ LP4 DIFF to SE enter ============
682 00:40:20.931964 ============ LP4 DIFF to SE exit ============
683 00:40:20.932057 [ANA_INIT] <<<<<<<<<<<<<
684 00:40:20.932143 [Flow] Enable top DCM control >>>>>
685 00:40:20.932228 [Flow] Enable top DCM control <<<<<
686 00:40:20.932321 Enable DLL master slave shuffle
687 00:40:20.932407 ==============================================================
688 00:40:20.932492 Gating Mode config
689 00:40:20.932621 ==============================================================
690 00:40:20.932721 Config description:
691 00:40:20.932816 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 00:40:20.932905 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 00:40:20.932991 SELPH_MODE 0: By rank 1: By Phase
694 00:40:20.933085 ==============================================================
695 00:40:20.933172 GAT_TRACK_EN = 1
696 00:40:20.933257 RX_GATING_MODE = 2
697 00:40:20.933372 RX_GATING_TRACK_MODE = 2
698 00:40:20.933472 SELPH_MODE = 1
699 00:40:20.933564 PICG_EARLY_EN = 1
700 00:40:20.933650 VALID_LAT_VALUE = 1
701 00:40:20.933736 ==============================================================
702 00:40:20.933829 Enter into Gating configuration >>>>
703 00:40:20.933915 Exit from Gating configuration <<<<
704 00:40:20.934000 Enter into DVFS_PRE_config >>>>>
705 00:40:20.934095 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 00:40:20.934184 Exit from DVFS_PRE_config <<<<<
707 00:40:20.934272 Enter into PICG configuration >>>>
708 00:40:20.934362 Exit from PICG configuration <<<<
709 00:40:20.934448 [RX_INPUT] configuration >>>>>
710 00:40:20.934539 [RX_INPUT] configuration <<<<<
711 00:40:20.934626 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 00:40:20.934717 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 00:40:20.934810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 00:40:20.934897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 00:40:20.935002 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 00:40:20.935110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 00:40:20.935195 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 00:40:20.935288 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 00:40:20.935375 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 00:40:20.935461 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 00:40:20.935553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 00:40:20.935640 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 00:40:20.935726 ===================================
724 00:40:20.935818 LPDDR4 DRAM CONFIGURATION
725 00:40:20.935904 ===================================
726 00:40:20.935989 EX_ROW_EN[0] = 0x0
727 00:40:20.936081 EX_ROW_EN[1] = 0x0
728 00:40:20.936166 LP4Y_EN = 0x0
729 00:40:20.936250 WORK_FSP = 0x0
730 00:40:20.936342 WL = 0x2
731 00:40:20.936444 RL = 0x2
732 00:40:20.936537 BL = 0x2
733 00:40:20.936632 RPST = 0x0
734 00:40:20.936733 RD_PRE = 0x0
735 00:40:20.936826 WR_PRE = 0x1
736 00:40:20.936911 WR_PST = 0x0
737 00:40:20.936995 DBI_WR = 0x0
738 00:40:20.937087 DBI_RD = 0x0
739 00:40:20.937173 OTF = 0x1
740 00:40:20.937258 ===================================
741 00:40:20.937352 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 00:40:20.937438 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 00:40:20.937528 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 00:40:20.937617 ===================================
745 00:40:20.937703 LPDDR4 DRAM CONFIGURATION
746 00:40:20.937795 ===================================
747 00:40:20.937881 EX_ROW_EN[0] = 0x10
748 00:40:20.937966 EX_ROW_EN[1] = 0x0
749 00:40:20.938075 LP4Y_EN = 0x0
750 00:40:20.938176 WORK_FSP = 0x0
751 00:40:20.938260 WL = 0x2
752 00:40:20.938353 RL = 0x2
753 00:40:20.938437 BL = 0x2
754 00:40:20.938526 RPST = 0x0
755 00:40:20.938631 RD_PRE = 0x0
756 00:40:20.938764 WR_PRE = 0x1
757 00:40:20.938856 WR_PST = 0x0
758 00:40:20.938941 DBI_WR = 0x0
759 00:40:20.939030 DBI_RD = 0x0
760 00:40:20.939117 OTF = 0x1
761 00:40:20.939203 ===================================
762 00:40:20.939296 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 00:40:20.939382 nWR fixed to 40
764 00:40:20.939468 [ModeRegInit_LP4] CH0 RK0
765 00:40:20.939560 [ModeRegInit_LP4] CH0 RK1
766 00:40:20.939645 [ModeRegInit_LP4] CH1 RK0
767 00:40:20.939730 [ModeRegInit_LP4] CH1 RK1
768 00:40:20.939821 match AC timing 13
769 00:40:20.939907 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 00:40:20.939993 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 00:40:20.940086 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 00:40:20.940173 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 00:40:20.940462 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 00:40:20.940584 [EMI DOE] emi_dcm 0
775 00:40:20.940688 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 00:40:20.940777 ==
777 00:40:20.940868 Dram Type= 6, Freq= 0, CH_0, rank 0
778 00:40:20.940955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 00:40:20.941048 ==
780 00:40:20.941136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 00:40:20.941223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 00:40:20.941317 [CA 0] Center 38 (7~69) winsize 63
783 00:40:20.941404 [CA 1] Center 38 (7~69) winsize 63
784 00:40:20.941489 [CA 2] Center 35 (5~66) winsize 62
785 00:40:20.941581 [CA 3] Center 35 (5~66) winsize 62
786 00:40:20.941667 [CA 4] Center 35 (4~66) winsize 63
787 00:40:20.941752 [CA 5] Center 33 (3~64) winsize 62
788 00:40:20.941845
789 00:40:20.941932 [CmdBusTrainingLP45] Vref(ca) range 1: 32
790 00:40:20.942017
791 00:40:20.942109 [CATrainingPosCal] consider 1 rank data
792 00:40:20.942195 u2DelayCellTimex100 = 270/100 ps
793 00:40:20.942287 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
794 00:40:20.942374 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
795 00:40:20.942460 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
796 00:40:20.942552 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
797 00:40:20.942639 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
798 00:40:20.942725 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
799 00:40:20.942816
800 00:40:20.942902 CA PerBit enable=1, Macro0, CA PI delay=33
801 00:40:20.942987
802 00:40:20.943079 [CBTSetCACLKResult] CA Dly = 33
803 00:40:20.943165 CS Dly: 6 (0~37)
804 00:40:20.943249 ==
805 00:40:20.943342 Dram Type= 6, Freq= 0, CH_0, rank 1
806 00:40:20.943429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 00:40:20.943514 ==
808 00:40:20.943608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 00:40:20.943695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 00:40:20.943787 [CA 0] Center 38 (7~69) winsize 63
811 00:40:20.943874 [CA 1] Center 38 (8~69) winsize 62
812 00:40:20.943959 [CA 2] Center 36 (6~67) winsize 62
813 00:40:20.944051 [CA 3] Center 36 (5~67) winsize 63
814 00:40:20.944137 [CA 4] Center 35 (4~66) winsize 63
815 00:40:20.944222 [CA 5] Center 34 (4~65) winsize 62
816 00:40:20.944313
817 00:40:20.944399 [CmdBusTrainingLP45] Vref(ca) range 1: 34
818 00:40:20.944484
819 00:40:20.944607 [CATrainingPosCal] consider 2 rank data
820 00:40:20.944707 u2DelayCellTimex100 = 270/100 ps
821 00:40:20.944799 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 00:40:20.944886 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
823 00:40:20.944972 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
824 00:40:20.945063 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 00:40:20.945150 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
826 00:40:20.945236 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
827 00:40:20.945327
828 00:40:20.945414 CA PerBit enable=1, Macro0, CA PI delay=34
829 00:40:20.945498
830 00:40:20.945574 [CBTSetCACLKResult] CA Dly = 34
831 00:40:20.945632 CS Dly: 6 (0~38)
832 00:40:20.945688
833 00:40:20.945744 ----->DramcWriteLeveling(PI) begin...
834 00:40:20.945816 ==
835 00:40:20.945874 Dram Type= 6, Freq= 0, CH_0, rank 0
836 00:40:20.945931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 00:40:20.945987 ==
838 00:40:20.946064 Write leveling (Byte 0): 31 => 31
839 00:40:20.946151 Write leveling (Byte 1): 30 => 30
840 00:40:20.946236 DramcWriteLeveling(PI) end<-----
841 00:40:20.946328
842 00:40:20.946413 ==
843 00:40:20.946490 Dram Type= 6, Freq= 0, CH_0, rank 0
844 00:40:20.946563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 00:40:20.946621 ==
846 00:40:20.946679 [Gating] SW mode calibration
847 00:40:20.946735 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 00:40:20.946805 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 00:40:20.946863 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
850 00:40:20.946919 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 00:40:20.946975 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 00:40:20.947041 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:40:20.947100 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:40:20.947156 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:40:20.947212 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:40:20.947271 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:40:20.947336 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:40:20.947393 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:40:20.947448 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:40:20.947503 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:40:20.947575 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:40:20.947632 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:40:20.947688 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:40:20.947743 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:40:20.947814 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:40:20.947872 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
867 00:40:20.947928 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:40:20.947984 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:40:20.948053 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:40:20.948111 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:40:20.948166 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:40:20.948223 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:40:20.948289 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:40:20.948377 0 9 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
875 00:40:20.948462 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
876 00:40:20.948582 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
877 00:40:20.948684 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 00:40:20.948772 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 00:40:20.948863 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 00:40:20.948949 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:40:20.949248 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:40:20.949349 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
883 00:40:20.949438 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
884 00:40:20.949529 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 00:40:20.949619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 00:40:20.949705 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:40:20.949798 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:40:20.949885 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:40:20.949970 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:40:20.950063 0 11 4 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
891 00:40:20.950150 0 11 8 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
892 00:40:20.950235 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
893 00:40:20.950329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 00:40:20.950415 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:40:20.950502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:40:20.950595 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:40:20.950682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
898 00:40:20.950768 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
899 00:40:20.950836 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 00:40:20.950892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:40:20.950948 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:40:20.951004 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:40:20.951076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:40:20.951132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:40:20.951187 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:40:20.951243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:40:20.951320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:40:20.951407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:40:20.951493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:40:20.951585 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:40:20.951672 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:40:20.951771 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:40:20.951858 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:40:20.951917 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 00:40:20.951974 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 00:40:20.952029 Total UI for P1: 0, mck2ui 16
917 00:40:20.952086 best dqsien dly found for B0: ( 0, 14, 4)
918 00:40:20.952142 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 00:40:20.952197 Total UI for P1: 0, mck2ui 16
920 00:40:20.952253 best dqsien dly found for B1: ( 0, 14, 8)
921 00:40:20.952309 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
922 00:40:20.952364 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
923 00:40:20.952419
924 00:40:20.952474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
925 00:40:20.952530 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
926 00:40:20.952651 [Gating] SW calibration Done
927 00:40:20.952736 ==
928 00:40:20.952821 Dram Type= 6, Freq= 0, CH_0, rank 0
929 00:40:20.952906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 00:40:20.952991 ==
931 00:40:20.953075 RX Vref Scan: 0
932 00:40:20.953159
933 00:40:20.953243 RX Vref 0 -> 0, step: 1
934 00:40:20.953326
935 00:40:20.953411 RX Delay -130 -> 252, step: 16
936 00:40:20.953495 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
937 00:40:20.953580 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 00:40:20.953665 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
939 00:40:20.953750 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
940 00:40:20.953834 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
941 00:40:20.953920 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 00:40:20.953978 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 00:40:20.954034 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 00:40:20.954090 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 00:40:20.954145 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
946 00:40:20.954200 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
947 00:40:20.954255 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 00:40:20.954310 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
949 00:40:20.954365 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 00:40:20.954420 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 00:40:20.954475 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
952 00:40:20.954530 ==
953 00:40:20.954585 Dram Type= 6, Freq= 0, CH_0, rank 0
954 00:40:20.954641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 00:40:20.954697 ==
956 00:40:20.954752 DQS Delay:
957 00:40:20.954808 DQS0 = 0, DQS1 = 0
958 00:40:20.954863 DQM Delay:
959 00:40:20.954918 DQM0 = 89, DQM1 = 78
960 00:40:20.954973 DQ Delay:
961 00:40:20.955028 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
962 00:40:20.955083 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
963 00:40:20.955138 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
964 00:40:20.955193 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
965 00:40:20.955248
966 00:40:20.955303
967 00:40:20.955357 ==
968 00:40:20.955412 Dram Type= 6, Freq= 0, CH_0, rank 0
969 00:40:20.955467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 00:40:20.955522 ==
971 00:40:20.955577
972 00:40:20.955631
973 00:40:20.955686 TX Vref Scan disable
974 00:40:20.955741 == TX Byte 0 ==
975 00:40:20.955796 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
976 00:40:20.955851 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
977 00:40:20.955906 == TX Byte 1 ==
978 00:40:20.955960 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
979 00:40:20.956016 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
980 00:40:20.956070 ==
981 00:40:20.956125 Dram Type= 6, Freq= 0, CH_0, rank 0
982 00:40:20.956180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 00:40:20.956236 ==
984 00:40:20.956290 TX Vref=22, minBit 6, minWin=27, winSum=442
985 00:40:20.956346 TX Vref=24, minBit 8, minWin=27, winSum=445
986 00:40:20.956401 TX Vref=26, minBit 8, minWin=27, winSum=451
987 00:40:20.956456 TX Vref=28, minBit 8, minWin=27, winSum=453
988 00:40:20.956511 TX Vref=30, minBit 6, minWin=28, winSum=458
989 00:40:20.956807 TX Vref=32, minBit 6, minWin=28, winSum=458
990 00:40:20.956870 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 30
991 00:40:20.956928
992 00:40:20.956983 Final TX Range 1 Vref 30
993 00:40:20.957051
994 00:40:20.957109 ==
995 00:40:20.957166 Dram Type= 6, Freq= 0, CH_0, rank 0
996 00:40:20.957222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 00:40:20.957288 ==
998 00:40:20.957346
999 00:40:20.957403
1000 00:40:20.957458 TX Vref Scan disable
1001 00:40:20.957513 == TX Byte 0 ==
1002 00:40:20.957581 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1003 00:40:20.957637 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1004 00:40:20.957694 == TX Byte 1 ==
1005 00:40:20.957749 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1006 00:40:20.957820 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1007 00:40:20.957877
1008 00:40:20.957933 [DATLAT]
1009 00:40:20.957988 Freq=800, CH0 RK0
1010 00:40:20.958058
1011 00:40:20.958116 DATLAT Default: 0xa
1012 00:40:20.958172 0, 0xFFFF, sum = 0
1013 00:40:20.958229 1, 0xFFFF, sum = 0
1014 00:40:20.958297 2, 0xFFFF, sum = 0
1015 00:40:20.958355 3, 0xFFFF, sum = 0
1016 00:40:20.958412 4, 0xFFFF, sum = 0
1017 00:40:20.958468 5, 0xFFFF, sum = 0
1018 00:40:20.958532 6, 0xFFFF, sum = 0
1019 00:40:20.958621 7, 0xFFFF, sum = 0
1020 00:40:20.958707 8, 0xFFFF, sum = 0
1021 00:40:20.958800 9, 0x0, sum = 1
1022 00:40:20.958887 10, 0x0, sum = 2
1023 00:40:20.958974 11, 0x0, sum = 3
1024 00:40:20.959068 12, 0x0, sum = 4
1025 00:40:20.959162 best_step = 10
1026 00:40:20.959250
1027 00:40:20.959342 ==
1028 00:40:20.959428 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 00:40:20.959512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 00:40:20.959604 ==
1031 00:40:20.959688 RX Vref Scan: 1
1032 00:40:20.959774
1033 00:40:20.959862 Set Vref Range= 32 -> 127
1034 00:40:20.959946
1035 00:40:20.960036 RX Vref 32 -> 127, step: 1
1036 00:40:20.960120
1037 00:40:20.960204 RX Delay -95 -> 252, step: 8
1038 00:40:20.960293
1039 00:40:20.960378 Set Vref, RX VrefLevel [Byte0]: 32
1040 00:40:20.960462 [Byte1]: 32
1041 00:40:20.960578
1042 00:40:20.960654 Set Vref, RX VrefLevel [Byte0]: 33
1043 00:40:20.960709 [Byte1]: 33
1044 00:40:20.960765
1045 00:40:20.960831 Set Vref, RX VrefLevel [Byte0]: 34
1046 00:40:20.960887 [Byte1]: 34
1047 00:40:20.960942
1048 00:40:20.960997 Set Vref, RX VrefLevel [Byte0]: 35
1049 00:40:20.961068 [Byte1]: 35
1050 00:40:20.961124
1051 00:40:20.961178 Set Vref, RX VrefLevel [Byte0]: 36
1052 00:40:20.961231 [Byte1]: 36
1053 00:40:20.961296
1054 00:40:20.961377 Set Vref, RX VrefLevel [Byte0]: 37
1055 00:40:20.961446 [Byte1]: 37
1056 00:40:20.961500
1057 00:40:20.961569 Set Vref, RX VrefLevel [Byte0]: 38
1058 00:40:20.961624 [Byte1]: 38
1059 00:40:20.961679
1060 00:40:20.961732 Set Vref, RX VrefLevel [Byte0]: 39
1061 00:40:20.961797 [Byte1]: 39
1062 00:40:20.961853
1063 00:40:20.961908 Set Vref, RX VrefLevel [Byte0]: 40
1064 00:40:20.961963 [Byte1]: 40
1065 00:40:20.962021
1066 00:40:20.962083 Set Vref, RX VrefLevel [Byte0]: 41
1067 00:40:20.962138 [Byte1]: 41
1068 00:40:20.962193
1069 00:40:20.962247 Set Vref, RX VrefLevel [Byte0]: 42
1070 00:40:20.962331 [Byte1]: 42
1071 00:40:20.962414
1072 00:40:20.962497 Set Vref, RX VrefLevel [Byte0]: 43
1073 00:40:20.962588 [Byte1]: 43
1074 00:40:20.962671
1075 00:40:20.962754 Set Vref, RX VrefLevel [Byte0]: 44
1076 00:40:20.962846 [Byte1]: 44
1077 00:40:20.962930
1078 00:40:20.963013 Set Vref, RX VrefLevel [Byte0]: 45
1079 00:40:20.963104 [Byte1]: 45
1080 00:40:20.963187
1081 00:40:20.963272 Set Vref, RX VrefLevel [Byte0]: 46
1082 00:40:20.963361 [Byte1]: 46
1083 00:40:20.963444
1084 00:40:20.963533 Set Vref, RX VrefLevel [Byte0]: 47
1085 00:40:20.963619 [Byte1]: 47
1086 00:40:20.963702
1087 00:40:20.963792 Set Vref, RX VrefLevel [Byte0]: 48
1088 00:40:20.963877 [Byte1]: 48
1089 00:40:20.963959
1090 00:40:20.964049 Set Vref, RX VrefLevel [Byte0]: 49
1091 00:40:20.964133 [Byte1]: 49
1092 00:40:20.964216
1093 00:40:20.964305 Set Vref, RX VrefLevel [Byte0]: 50
1094 00:40:20.964390 [Byte1]: 50
1095 00:40:20.964473
1096 00:40:20.964597 Set Vref, RX VrefLevel [Byte0]: 51
1097 00:40:20.964670 [Byte1]: 51
1098 00:40:20.964725
1099 00:40:20.964805 Set Vref, RX VrefLevel [Byte0]: 52
1100 00:40:20.964878 [Byte1]: 52
1101 00:40:20.964933
1102 00:40:20.964987 Set Vref, RX VrefLevel [Byte0]: 53
1103 00:40:20.965053 [Byte1]: 53
1104 00:40:20.965111
1105 00:40:20.965165 Set Vref, RX VrefLevel [Byte0]: 54
1106 00:40:20.965220 [Byte1]: 54
1107 00:40:20.965283
1108 00:40:20.965341 Set Vref, RX VrefLevel [Byte0]: 55
1109 00:40:20.965396 [Byte1]: 55
1110 00:40:20.965451
1111 00:40:20.965505 Set Vref, RX VrefLevel [Byte0]: 56
1112 00:40:20.965574 [Byte1]: 56
1113 00:40:20.965630
1114 00:40:20.965685 Set Vref, RX VrefLevel [Byte0]: 57
1115 00:40:20.965740 [Byte1]: 57
1116 00:40:20.965809
1117 00:40:20.965865 Set Vref, RX VrefLevel [Byte0]: 58
1118 00:40:20.965919 [Byte1]: 58
1119 00:40:20.965974
1120 00:40:20.966038 Set Vref, RX VrefLevel [Byte0]: 59
1121 00:40:20.966095 [Byte1]: 59
1122 00:40:20.966149
1123 00:40:20.966204 Set Vref, RX VrefLevel [Byte0]: 60
1124 00:40:20.966258 [Byte1]: 60
1125 00:40:20.966348
1126 00:40:20.966432 Set Vref, RX VrefLevel [Byte0]: 61
1127 00:40:20.966517 [Byte1]: 61
1128 00:40:20.966623
1129 00:40:20.966752 Set Vref, RX VrefLevel [Byte0]: 62
1130 00:40:20.966844 [Byte1]: 62
1131 00:40:20.966927
1132 00:40:20.967010 Set Vref, RX VrefLevel [Byte0]: 63
1133 00:40:20.967102 [Byte1]: 63
1134 00:40:20.967185
1135 00:40:20.967270 Set Vref, RX VrefLevel [Byte0]: 64
1136 00:40:20.967359 [Byte1]: 64
1137 00:40:20.967441
1138 00:40:20.967530 Set Vref, RX VrefLevel [Byte0]: 65
1139 00:40:20.967617 [Byte1]: 65
1140 00:40:20.967717
1141 00:40:20.967822 Set Vref, RX VrefLevel [Byte0]: 66
1142 00:40:20.967906 [Byte1]: 66
1143 00:40:20.967989
1144 00:40:20.968079 Set Vref, RX VrefLevel [Byte0]: 67
1145 00:40:20.968163 [Byte1]: 67
1146 00:40:20.968246
1147 00:40:20.968353 Set Vref, RX VrefLevel [Byte0]: 68
1148 00:40:20.968439 [Byte1]: 68
1149 00:40:20.968530
1150 00:40:20.968624 Set Vref, RX VrefLevel [Byte0]: 69
1151 00:40:20.968741 [Byte1]: 69
1152 00:40:20.968834
1153 00:40:20.968932 Set Vref, RX VrefLevel [Byte0]: 70
1154 00:40:20.969016 [Byte1]: 70
1155 00:40:20.969106
1156 00:40:20.969189 Set Vref, RX VrefLevel [Byte0]: 71
1157 00:40:20.969277 [Byte1]: 71
1158 00:40:20.969363
1159 00:40:20.969447 Set Vref, RX VrefLevel [Byte0]: 72
1160 00:40:20.969756 [Byte1]: 72
1161 00:40:20.969858
1162 00:40:20.969945 Set Vref, RX VrefLevel [Byte0]: 73
1163 00:40:20.970039 [Byte1]: 73
1164 00:40:20.970126
1165 00:40:20.970211 Set Vref, RX VrefLevel [Byte0]: 74
1166 00:40:20.970317 [Byte1]: 74
1167 00:40:20.970401
1168 00:40:20.970484 Set Vref, RX VrefLevel [Byte0]: 75
1169 00:40:20.970575 [Byte1]: 75
1170 00:40:20.970707
1171 00:40:20.970812 Set Vref, RX VrefLevel [Byte0]: 76
1172 00:40:20.970897 [Byte1]: 76
1173 00:40:20.970979
1174 00:40:20.971070 Set Vref, RX VrefLevel [Byte0]: 77
1175 00:40:20.971154 [Byte1]: 77
1176 00:40:20.971237
1177 00:40:20.971328 Set Vref, RX VrefLevel [Byte0]: 78
1178 00:40:20.971412 [Byte1]: 78
1179 00:40:20.971494
1180 00:40:20.971585 Set Vref, RX VrefLevel [Byte0]: 79
1181 00:40:20.971669 [Byte1]: 79
1182 00:40:20.971772
1183 00:40:20.971873 Final RX Vref Byte 0 = 61 to rank0
1184 00:40:20.971958 Final RX Vref Byte 1 = 58 to rank0
1185 00:40:20.972049 Final RX Vref Byte 0 = 61 to rank1
1186 00:40:20.972134 Final RX Vref Byte 1 = 58 to rank1==
1187 00:40:20.972218 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 00:40:20.972309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 00:40:20.972393 ==
1190 00:40:20.972477 DQS Delay:
1191 00:40:20.972592 DQS0 = 0, DQS1 = 0
1192 00:40:20.972741 DQM Delay:
1193 00:40:20.972848 DQM0 = 92, DQM1 = 83
1194 00:40:20.972932 DQ Delay:
1195 00:40:20.973015 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1196 00:40:20.973108 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1197 00:40:20.973192 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1198 00:40:20.973300 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1199 00:40:20.973399
1200 00:40:20.973482
1201 00:40:20.973574 [DQSOSCAuto] RK0, (LSB)MR18= 0x433e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1202 00:40:20.973659 CH0 RK0: MR19=606, MR18=433E
1203 00:40:20.973744 CH0_RK0: MR19=0x606, MR18=0x433E, DQSOSC=393, MR23=63, INC=95, DEC=63
1204 00:40:20.973835
1205 00:40:20.973919 ----->DramcWriteLeveling(PI) begin...
1206 00:40:20.974003 ==
1207 00:40:20.974096 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 00:40:20.974180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 00:40:20.974263 ==
1210 00:40:20.974355 Write leveling (Byte 0): 31 => 31
1211 00:40:20.974439 Write leveling (Byte 1): 29 => 29
1212 00:40:20.974526 DramcWriteLeveling(PI) end<-----
1213 00:40:20.974630
1214 00:40:20.974727 ==
1215 00:40:20.974836 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 00:40:20.974935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 00:40:20.975021 ==
1218 00:40:20.975110 [Gating] SW mode calibration
1219 00:40:20.975195 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 00:40:20.975286 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 00:40:20.975372 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 00:40:20.975456 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 00:40:20.975547 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 00:40:20.975633 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:40:20.975717 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:40:20.975807 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:40:20.975892 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:40:20.975976 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:40:20.976067 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:40:20.976152 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:40:20.976236 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:40:20.976326 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:40:20.976411 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:40:20.976495 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:40:20.976614 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:40:20.976722 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:40:20.976820 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:40:20.976880 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1239 00:40:20.976936 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1240 00:40:20.976993 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:40:20.977068 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:40:20.977154 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:40:20.977240 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:40:20.977334 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:40:20.977420 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:40:20.977506 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1247 00:40:20.977600 0 9 8 | B1->B0 | 2e2e 3333 | 0 1 | (1 1) (1 1)
1248 00:40:20.977686 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 00:40:20.977774 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 00:40:20.977865 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 00:40:20.977951 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 00:40:20.978044 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 00:40:20.978131 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 00:40:20.978217 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
1255 00:40:20.978310 0 10 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
1256 00:40:20.978396 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 00:40:20.978482 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 00:40:20.978576 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 00:40:20.978693 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 00:40:20.978798 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 00:40:20.978883 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 00:40:20.978966 0 11 4 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
1263 00:40:20.979057 0 11 8 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
1264 00:40:20.979142 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 00:40:20.979226 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 00:40:20.979317 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 00:40:20.979623 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 00:40:20.979695 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 00:40:20.979753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 00:40:20.979828 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1271 00:40:20.979885 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 00:40:20.979942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:40:20.979997 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:40:20.980083 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:40:20.980139 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:40:20.980194 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:40:20.980249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:40:20.980318 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 00:40:20.980391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:40:20.980448 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:40:20.980504 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:40:20.980605 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:40:20.980663 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:40:20.980743 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:40:20.980845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:40:20.980917 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1287 00:40:20.980989 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1288 00:40:20.981103 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 00:40:20.981191 Total UI for P1: 0, mck2ui 16
1290 00:40:20.981269 best dqsien dly found for B0: ( 0, 14, 6)
1291 00:40:20.981361 Total UI for P1: 0, mck2ui 16
1292 00:40:20.981448 best dqsien dly found for B1: ( 0, 14, 6)
1293 00:40:20.981554 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1294 00:40:20.981640 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1295 00:40:20.981723
1296 00:40:20.981813 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1297 00:40:20.981898 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1298 00:40:20.981981 [Gating] SW calibration Done
1299 00:40:20.982072 ==
1300 00:40:20.982157 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 00:40:20.982241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 00:40:20.982319 ==
1303 00:40:20.982376 RX Vref Scan: 0
1304 00:40:20.982431
1305 00:40:20.982486 RX Vref 0 -> 0, step: 1
1306 00:40:20.982559
1307 00:40:20.982661 RX Delay -130 -> 252, step: 16
1308 00:40:20.982747 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1309 00:40:20.982852 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1310 00:40:20.982936 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1311 00:40:20.983022 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1312 00:40:20.983111 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1313 00:40:20.983195 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1314 00:40:20.983285 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1315 00:40:20.983371 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1316 00:40:20.983455 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1317 00:40:20.983545 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1318 00:40:20.983630 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1319 00:40:20.983714 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1320 00:40:20.983805 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1321 00:40:20.983890 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
1322 00:40:20.983973 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1323 00:40:20.984065 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1324 00:40:20.984148 ==
1325 00:40:20.984232 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 00:40:20.984324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 00:40:20.984409 ==
1328 00:40:20.984492 DQS Delay:
1329 00:40:20.984637 DQS0 = 0, DQS1 = 0
1330 00:40:20.984723 DQM Delay:
1331 00:40:20.984847 DQM0 = 87, DQM1 = 77
1332 00:40:20.984944 DQ Delay:
1333 00:40:20.985052 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1334 00:40:20.985139 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1335 00:40:20.985237 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1336 00:40:20.985328 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1337 00:40:20.985411
1338 00:40:20.985494
1339 00:40:20.985584 ==
1340 00:40:20.985669 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 00:40:20.985753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 00:40:20.985843 ==
1343 00:40:20.985927
1344 00:40:20.986009
1345 00:40:20.986100 TX Vref Scan disable
1346 00:40:20.986183 == TX Byte 0 ==
1347 00:40:20.986269 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1348 00:40:20.986359 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1349 00:40:20.986442 == TX Byte 1 ==
1350 00:40:20.986531 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1351 00:40:20.986618 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1352 00:40:20.986701 ==
1353 00:40:20.986791 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 00:40:20.986877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 00:40:20.986960 ==
1356 00:40:20.987050 TX Vref=22, minBit 8, minWin=27, winSum=446
1357 00:40:20.987153 TX Vref=24, minBit 8, minWin=27, winSum=451
1358 00:40:20.987253 TX Vref=26, minBit 8, minWin=27, winSum=452
1359 00:40:20.987345 TX Vref=28, minBit 8, minWin=27, winSum=455
1360 00:40:20.987430 TX Vref=30, minBit 8, minWin=27, winSum=456
1361 00:40:20.987513 TX Vref=32, minBit 8, minWin=28, winSum=458
1362 00:40:20.987603 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1363 00:40:20.987686
1364 00:40:20.987771 Final TX Range 1 Vref 32
1365 00:40:20.987858
1366 00:40:20.987939 ==
1367 00:40:20.988023 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 00:40:20.988142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 00:40:20.988224 ==
1370 00:40:20.988313
1371 00:40:20.988394
1372 00:40:20.988475 TX Vref Scan disable
1373 00:40:20.988585 == TX Byte 0 ==
1374 00:40:20.988672 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1375 00:40:20.988729 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1376 00:40:20.988811 == TX Byte 1 ==
1377 00:40:20.988866 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1378 00:40:20.988919 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1379 00:40:20.988972
1380 00:40:20.989027 [DATLAT]
1381 00:40:20.989089 Freq=800, CH0 RK1
1382 00:40:20.989148
1383 00:40:20.989201 DATLAT Default: 0xa
1384 00:40:20.989254 0, 0xFFFF, sum = 0
1385 00:40:20.989325 1, 0xFFFF, sum = 0
1386 00:40:20.989380 2, 0xFFFF, sum = 0
1387 00:40:20.989434 3, 0xFFFF, sum = 0
1388 00:40:20.989488 4, 0xFFFF, sum = 0
1389 00:40:20.989557 5, 0xFFFF, sum = 0
1390 00:40:20.989613 6, 0xFFFF, sum = 0
1391 00:40:20.989667 7, 0xFFFF, sum = 0
1392 00:40:20.989721 8, 0xFFFF, sum = 0
1393 00:40:20.989995 9, 0x0, sum = 1
1394 00:40:20.990109 10, 0x0, sum = 2
1395 00:40:20.990175 11, 0x0, sum = 3
1396 00:40:20.990237 12, 0x0, sum = 4
1397 00:40:20.990313 best_step = 10
1398 00:40:20.990384
1399 00:40:20.990440 ==
1400 00:40:20.990495 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 00:40:20.990567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 00:40:20.990636 ==
1403 00:40:20.990689 RX Vref Scan: 0
1404 00:40:20.990743
1405 00:40:20.990828 RX Vref 0 -> 0, step: 1
1406 00:40:20.990883
1407 00:40:20.990937 RX Delay -95 -> 252, step: 8
1408 00:40:20.990990 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1409 00:40:20.991073 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1410 00:40:20.991127 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1411 00:40:20.991181 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1412 00:40:20.991233 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1413 00:40:20.991342 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1414 00:40:20.991401 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1415 00:40:20.991461 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1416 00:40:20.991515 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1417 00:40:20.991599 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1418 00:40:20.991653 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1419 00:40:20.991707 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1420 00:40:20.991760 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1421 00:40:20.991843 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1422 00:40:20.991896 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1423 00:40:20.991949 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1424 00:40:20.992003 ==
1425 00:40:20.992086 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 00:40:20.992140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 00:40:20.992194 ==
1428 00:40:20.992247 DQS Delay:
1429 00:40:20.992331 DQS0 = 0, DQS1 = 0
1430 00:40:20.992385 DQM Delay:
1431 00:40:20.992438 DQM0 = 90, DQM1 = 81
1432 00:40:20.992492 DQ Delay:
1433 00:40:20.992571 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1434 00:40:20.992641 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1435 00:40:20.992695 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1436 00:40:20.992749 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1437 00:40:20.992874
1438 00:40:20.992931
1439 00:40:20.992993 [DQSOSCAuto] RK1, (LSB)MR18= 0x4821, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1440 00:40:20.993079 CH0 RK1: MR19=606, MR18=4821
1441 00:40:20.993148 CH0_RK1: MR19=0x606, MR18=0x4821, DQSOSC=391, MR23=63, INC=96, DEC=64
1442 00:40:20.993202 [RxdqsGatingPostProcess] freq 800
1443 00:40:20.993271 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 00:40:20.993340 Pre-setting of DQS Precalculation
1445 00:40:20.993394 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 00:40:20.993447 ==
1447 00:40:20.993501 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 00:40:20.993584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 00:40:20.993638 ==
1450 00:40:20.993691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 00:40:20.993744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 00:40:20.993828 [CA 0] Center 36 (6~67) winsize 62
1453 00:40:20.993881 [CA 1] Center 36 (6~67) winsize 62
1454 00:40:20.993935 [CA 2] Center 34 (4~65) winsize 62
1455 00:40:20.993988 [CA 3] Center 34 (3~65) winsize 63
1456 00:40:20.994056 [CA 4] Center 34 (4~65) winsize 62
1457 00:40:20.994123 [CA 5] Center 33 (3~64) winsize 62
1458 00:40:20.994176
1459 00:40:20.994229 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1460 00:40:20.994297
1461 00:40:20.994366 [CATrainingPosCal] consider 1 rank data
1462 00:40:20.994419 u2DelayCellTimex100 = 270/100 ps
1463 00:40:20.994473 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1464 00:40:20.994586 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1465 00:40:20.994642 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1466 00:40:20.994696 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1467 00:40:20.994750 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1468 00:40:20.994832 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1469 00:40:20.994885
1470 00:40:20.994939 CA PerBit enable=1, Macro0, CA PI delay=33
1471 00:40:20.994996
1472 00:40:20.995097 [CBTSetCACLKResult] CA Dly = 33
1473 00:40:20.995151 CS Dly: 5 (0~36)
1474 00:40:20.995205 ==
1475 00:40:20.995258 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 00:40:20.995340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 00:40:20.995394 ==
1478 00:40:20.995447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 00:40:20.995501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 00:40:20.995586 [CA 0] Center 36 (6~67) winsize 62
1481 00:40:20.995640 [CA 1] Center 37 (6~68) winsize 63
1482 00:40:20.995694 [CA 2] Center 35 (5~66) winsize 62
1483 00:40:20.995747 [CA 3] Center 34 (4~65) winsize 62
1484 00:40:20.995829 [CA 4] Center 34 (4~65) winsize 62
1485 00:40:20.995882 [CA 5] Center 34 (4~65) winsize 62
1486 00:40:20.995935
1487 00:40:20.995987 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1488 00:40:20.996057
1489 00:40:20.996123 [CATrainingPosCal] consider 2 rank data
1490 00:40:20.996177 u2DelayCellTimex100 = 270/100 ps
1491 00:40:20.996230 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 00:40:20.996298 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 00:40:20.996367 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1494 00:40:20.996420 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 00:40:20.996473 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 00:40:20.996542 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1497 00:40:20.996651
1498 00:40:20.996707 CA PerBit enable=1, Macro0, CA PI delay=34
1499 00:40:20.996761
1500 00:40:20.996845 [CBTSetCACLKResult] CA Dly = 34
1501 00:40:20.996899 CS Dly: 6 (0~38)
1502 00:40:20.996952
1503 00:40:20.997009 ----->DramcWriteLeveling(PI) begin...
1504 00:40:20.997097 ==
1505 00:40:20.997152 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 00:40:20.997219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 00:40:20.997287 ==
1508 00:40:20.997355 Write leveling (Byte 0): 27 => 27
1509 00:40:20.997408 Write leveling (Byte 1): 28 => 28
1510 00:40:20.997461 DramcWriteLeveling(PI) end<-----
1511 00:40:20.997514
1512 00:40:20.997595 ==
1513 00:40:20.997648 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 00:40:20.997701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 00:40:20.997755 ==
1516 00:40:20.997837 [Gating] SW mode calibration
1517 00:40:20.997890 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 00:40:20.997945 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 00:40:20.997998 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 00:40:20.998306 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1521 00:40:20.998429 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:40:20.998550 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:40:20.998670 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:40:20.998784 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:40:20.998870 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:40:20.998969 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:40:20.999083 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:40:20.999166 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:40:20.999249 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:40:20.999363 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:40:20.999445 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:40:20.999543 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:40:20.999641 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:40:20.999724 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:40:20.999837 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1536 00:40:20.999920 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 00:40:21.000002 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:40:21.000117 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:40:21.000200 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:40:21.000298 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:40:21.000395 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:40:21.000478 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:40:21.000602 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:40:21.000686 0 9 4 | B1->B0 | 2323 2b2b | 1 1 | (1 1) (1 1)
1545 00:40:21.000784 0 9 8 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
1546 00:40:21.000881 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 00:40:21.000979 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 00:40:21.001093 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 00:40:21.001175 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 00:40:21.001259 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 00:40:21.001370 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 00:40:21.001426 0 10 4 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
1553 00:40:21.001481 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1554 00:40:21.001551 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 00:40:21.001620 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 00:40:21.001674 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 00:40:21.001728 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 00:40:21.001796 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 00:40:21.001863 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 00:40:21.001917 0 11 4 | B1->B0 | 3333 3939 | 0 1 | (0 0) (0 0)
1561 00:40:21.001970 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 00:40:21.002039 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 00:40:21.002107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 00:40:21.002160 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 00:40:21.002213 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 00:40:21.002282 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 00:40:21.002350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 00:40:21.002403 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1569 00:40:21.002456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:40:21.002510 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:40:21.002592 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:40:21.002645 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:40:21.002697 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:40:21.002751 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:40:21.002834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:40:21.002887 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 00:40:21.002940 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:40:21.002993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:40:21.003076 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:40:21.003130 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:40:21.003183 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:40:21.003236 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:40:21.003304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:40:21.003371 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1585 00:40:21.003425 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 00:40:21.003478 Total UI for P1: 0, mck2ui 16
1587 00:40:21.003548 best dqsien dly found for B0: ( 0, 14, 4)
1588 00:40:21.003616 Total UI for P1: 0, mck2ui 16
1589 00:40:21.003671 best dqsien dly found for B1: ( 0, 14, 6)
1590 00:40:21.003725 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1591 00:40:21.003793 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1592 00:40:21.003860
1593 00:40:21.003913 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 00:40:21.003966 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1595 00:40:21.004034 [Gating] SW calibration Done
1596 00:40:21.004103 ==
1597 00:40:21.004156 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 00:40:21.004210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 00:40:21.004263 ==
1600 00:40:21.004347 RX Vref Scan: 0
1601 00:40:21.004400
1602 00:40:21.004453 RX Vref 0 -> 0, step: 1
1603 00:40:21.004507
1604 00:40:21.004599 RX Delay -130 -> 252, step: 16
1605 00:40:21.004664 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1606 00:40:21.004733 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1607 00:40:21.004820 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1608 00:40:21.004875 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1609 00:40:21.005141 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1610 00:40:21.005224 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1611 00:40:21.005290 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1612 00:40:21.005351 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1613 00:40:21.005410 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1614 00:40:21.005468 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1615 00:40:21.005525 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1616 00:40:21.005581 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1617 00:40:21.005636 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1618 00:40:21.005691 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1619 00:40:21.005746 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1620 00:40:21.005801 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1621 00:40:21.005855 ==
1622 00:40:21.005910 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 00:40:21.005964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 00:40:21.006020 ==
1625 00:40:21.006074 DQS Delay:
1626 00:40:21.006128 DQS0 = 0, DQS1 = 0
1627 00:40:21.006182 DQM Delay:
1628 00:40:21.006237 DQM0 = 88, DQM1 = 80
1629 00:40:21.006291 DQ Delay:
1630 00:40:21.006345 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1631 00:40:21.006399 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1632 00:40:21.006453 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1633 00:40:21.006511 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1634 00:40:21.006605
1635 00:40:21.006658
1636 00:40:21.006712 ==
1637 00:40:21.006766 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 00:40:21.006819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 00:40:21.006874 ==
1640 00:40:21.006928
1641 00:40:21.006981
1642 00:40:21.007034 TX Vref Scan disable
1643 00:40:21.007088 == TX Byte 0 ==
1644 00:40:21.007142 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1645 00:40:21.007196 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1646 00:40:21.007250 == TX Byte 1 ==
1647 00:40:21.007304 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1648 00:40:21.007358 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1649 00:40:21.007411 ==
1650 00:40:21.007465 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 00:40:21.007519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 00:40:21.007573 ==
1653 00:40:21.007626 TX Vref=22, minBit 8, minWin=27, winSum=448
1654 00:40:21.007681 TX Vref=24, minBit 10, minWin=27, winSum=453
1655 00:40:21.007735 TX Vref=26, minBit 1, minWin=28, winSum=458
1656 00:40:21.007789 TX Vref=28, minBit 1, minWin=28, winSum=459
1657 00:40:21.007843 TX Vref=30, minBit 1, minWin=28, winSum=458
1658 00:40:21.007897 TX Vref=32, minBit 14, minWin=27, winSum=456
1659 00:40:21.007951 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 28
1660 00:40:21.008005
1661 00:40:21.008058 Final TX Range 1 Vref 28
1662 00:40:21.008112
1663 00:40:21.008165 ==
1664 00:40:21.008219 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 00:40:21.008273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 00:40:21.008327 ==
1667 00:40:21.008381
1668 00:40:21.008433
1669 00:40:21.008487 TX Vref Scan disable
1670 00:40:21.008567 == TX Byte 0 ==
1671 00:40:21.008637 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1672 00:40:21.008692 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1673 00:40:21.008746 == TX Byte 1 ==
1674 00:40:21.008800 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1675 00:40:21.008855 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1676 00:40:21.008909
1677 00:40:21.008961 [DATLAT]
1678 00:40:21.009015 Freq=800, CH1 RK0
1679 00:40:21.009070
1680 00:40:21.009130 DATLAT Default: 0xa
1681 00:40:21.009206 0, 0xFFFF, sum = 0
1682 00:40:21.009264 1, 0xFFFF, sum = 0
1683 00:40:21.009320 2, 0xFFFF, sum = 0
1684 00:40:21.009376 3, 0xFFFF, sum = 0
1685 00:40:21.009431 4, 0xFFFF, sum = 0
1686 00:40:21.009487 5, 0xFFFF, sum = 0
1687 00:40:21.009542 6, 0xFFFF, sum = 0
1688 00:40:21.009597 7, 0xFFFF, sum = 0
1689 00:40:21.009652 8, 0xFFFF, sum = 0
1690 00:40:21.009707 9, 0x0, sum = 1
1691 00:40:21.009762 10, 0x0, sum = 2
1692 00:40:21.009818 11, 0x0, sum = 3
1693 00:40:21.009872 12, 0x0, sum = 4
1694 00:40:21.009927 best_step = 10
1695 00:40:21.009981
1696 00:40:21.010034 ==
1697 00:40:21.010088 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 00:40:21.010143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 00:40:21.010197 ==
1700 00:40:21.010251 RX Vref Scan: 1
1701 00:40:21.010305
1702 00:40:21.010358 Set Vref Range= 32 -> 127
1703 00:40:21.010412
1704 00:40:21.010465 RX Vref 32 -> 127, step: 1
1705 00:40:21.010555
1706 00:40:21.010609 RX Delay -95 -> 252, step: 8
1707 00:40:21.010663
1708 00:40:21.010717 Set Vref, RX VrefLevel [Byte0]: 32
1709 00:40:21.010771 [Byte1]: 32
1710 00:40:21.010826
1711 00:40:21.010880 Set Vref, RX VrefLevel [Byte0]: 33
1712 00:40:21.010934 [Byte1]: 33
1713 00:40:21.010988
1714 00:40:21.011048 Set Vref, RX VrefLevel [Byte0]: 34
1715 00:40:21.011103 [Byte1]: 34
1716 00:40:21.011158
1717 00:40:21.011211 Set Vref, RX VrefLevel [Byte0]: 35
1718 00:40:21.011265 [Byte1]: 35
1719 00:40:21.011319
1720 00:40:21.011372 Set Vref, RX VrefLevel [Byte0]: 36
1721 00:40:21.011426 [Byte1]: 36
1722 00:40:21.011480
1723 00:40:21.011533 Set Vref, RX VrefLevel [Byte0]: 37
1724 00:40:21.011588 [Byte1]: 37
1725 00:40:21.011642
1726 00:40:21.011695 Set Vref, RX VrefLevel [Byte0]: 38
1727 00:40:21.011749 [Byte1]: 38
1728 00:40:21.011803
1729 00:40:21.011856 Set Vref, RX VrefLevel [Byte0]: 39
1730 00:40:21.011911 [Byte1]: 39
1731 00:40:21.011965
1732 00:40:21.012018 Set Vref, RX VrefLevel [Byte0]: 40
1733 00:40:21.012072 [Byte1]: 40
1734 00:40:21.012126
1735 00:40:21.012179 Set Vref, RX VrefLevel [Byte0]: 41
1736 00:40:21.012233 [Byte1]: 41
1737 00:40:21.012287
1738 00:40:21.012341 Set Vref, RX VrefLevel [Byte0]: 42
1739 00:40:21.012395 [Byte1]: 42
1740 00:40:21.012449
1741 00:40:21.012502 Set Vref, RX VrefLevel [Byte0]: 43
1742 00:40:21.012580 [Byte1]: 43
1743 00:40:21.012649
1744 00:40:21.012703 Set Vref, RX VrefLevel [Byte0]: 44
1745 00:40:21.012763 [Byte1]: 44
1746 00:40:21.012837
1747 00:40:21.012892 Set Vref, RX VrefLevel [Byte0]: 45
1748 00:40:21.012947 [Byte1]: 45
1749 00:40:21.013001
1750 00:40:21.013055 Set Vref, RX VrefLevel [Byte0]: 46
1751 00:40:21.013110 [Byte1]: 46
1752 00:40:21.013164
1753 00:40:21.013217 Set Vref, RX VrefLevel [Byte0]: 47
1754 00:40:21.013272 [Byte1]: 47
1755 00:40:21.013326
1756 00:40:21.013379 Set Vref, RX VrefLevel [Byte0]: 48
1757 00:40:21.013434 [Byte1]: 48
1758 00:40:21.013488
1759 00:40:21.013541 Set Vref, RX VrefLevel [Byte0]: 49
1760 00:40:21.013595 [Byte1]: 49
1761 00:40:21.013669
1762 00:40:21.013725 Set Vref, RX VrefLevel [Byte0]: 50
1763 00:40:21.013780 [Byte1]: 50
1764 00:40:21.013834
1765 00:40:21.013888 Set Vref, RX VrefLevel [Byte0]: 51
1766 00:40:21.013941 [Byte1]: 51
1767 00:40:21.013995
1768 00:40:21.014247 Set Vref, RX VrefLevel [Byte0]: 52
1769 00:40:21.014339 [Byte1]: 52
1770 00:40:21.014395
1771 00:40:21.014450 Set Vref, RX VrefLevel [Byte0]: 53
1772 00:40:21.014512 [Byte1]: 53
1773 00:40:21.014583
1774 00:40:21.014669 Set Vref, RX VrefLevel [Byte0]: 54
1775 00:40:21.014725 [Byte1]: 54
1776 00:40:21.014781
1777 00:40:21.014836 Set Vref, RX VrefLevel [Byte0]: 55
1778 00:40:21.014891 [Byte1]: 55
1779 00:40:21.014946
1780 00:40:21.015001 Set Vref, RX VrefLevel [Byte0]: 56
1781 00:40:21.015056 [Byte1]: 56
1782 00:40:21.015111
1783 00:40:21.015166 Set Vref, RX VrefLevel [Byte0]: 57
1784 00:40:21.015221 [Byte1]: 57
1785 00:40:21.015276
1786 00:40:21.015331 Set Vref, RX VrefLevel [Byte0]: 58
1787 00:40:21.015386 [Byte1]: 58
1788 00:40:21.015441
1789 00:40:21.015495 Set Vref, RX VrefLevel [Byte0]: 59
1790 00:40:21.015551 [Byte1]: 59
1791 00:40:21.015606
1792 00:40:21.015660 Set Vref, RX VrefLevel [Byte0]: 60
1793 00:40:21.015716 [Byte1]: 60
1794 00:40:21.015771
1795 00:40:21.015826 Set Vref, RX VrefLevel [Byte0]: 61
1796 00:40:21.015881 [Byte1]: 61
1797 00:40:21.015937
1798 00:40:21.015991 Set Vref, RX VrefLevel [Byte0]: 62
1799 00:40:21.016048 [Byte1]: 62
1800 00:40:21.016103
1801 00:40:21.016158 Set Vref, RX VrefLevel [Byte0]: 63
1802 00:40:21.016214 [Byte1]: 63
1803 00:40:21.016269
1804 00:40:21.016325 Set Vref, RX VrefLevel [Byte0]: 64
1805 00:40:21.016380 [Byte1]: 64
1806 00:40:21.016435
1807 00:40:21.016490 Set Vref, RX VrefLevel [Byte0]: 65
1808 00:40:21.016553 [Byte1]: 65
1809 00:40:21.016612
1810 00:40:21.016667 Set Vref, RX VrefLevel [Byte0]: 66
1811 00:40:21.016722 [Byte1]: 66
1812 00:40:21.016777
1813 00:40:21.016832 Set Vref, RX VrefLevel [Byte0]: 67
1814 00:40:21.016888 [Byte1]: 67
1815 00:40:21.016943
1816 00:40:21.016998 Set Vref, RX VrefLevel [Byte0]: 68
1817 00:40:21.017075 [Byte1]: 68
1818 00:40:21.017179
1819 00:40:21.017234 Set Vref, RX VrefLevel [Byte0]: 69
1820 00:40:21.017289 [Byte1]: 69
1821 00:40:21.017344
1822 00:40:21.017397 Set Vref, RX VrefLevel [Byte0]: 70
1823 00:40:21.017452 [Byte1]: 70
1824 00:40:21.017506
1825 00:40:21.017559 Set Vref, RX VrefLevel [Byte0]: 71
1826 00:40:21.017613 [Byte1]: 71
1827 00:40:21.017667
1828 00:40:21.017721 Set Vref, RX VrefLevel [Byte0]: 72
1829 00:40:21.017775 [Byte1]: 72
1830 00:40:21.017830
1831 00:40:21.017902 Set Vref, RX VrefLevel [Byte0]: 73
1832 00:40:21.017971 [Byte1]: 73
1833 00:40:21.018025
1834 00:40:21.018079 Set Vref, RX VrefLevel [Byte0]: 74
1835 00:40:21.018133 [Byte1]: 74
1836 00:40:21.018187
1837 00:40:21.018240 Set Vref, RX VrefLevel [Byte0]: 75
1838 00:40:21.018295 [Byte1]: 75
1839 00:40:21.018348
1840 00:40:21.018402 Set Vref, RX VrefLevel [Byte0]: 76
1841 00:40:21.018457 [Byte1]: 76
1842 00:40:21.018510
1843 00:40:21.018564 Set Vref, RX VrefLevel [Byte0]: 77
1844 00:40:21.018619 [Byte1]: 77
1845 00:40:21.018673
1846 00:40:21.018743 Final RX Vref Byte 0 = 52 to rank0
1847 00:40:21.018829 Final RX Vref Byte 1 = 61 to rank0
1848 00:40:21.018899 Final RX Vref Byte 0 = 52 to rank1
1849 00:40:21.018952 Final RX Vref Byte 1 = 61 to rank1==
1850 00:40:21.019007 Dram Type= 6, Freq= 0, CH_1, rank 0
1851 00:40:21.019061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 00:40:21.019115 ==
1853 00:40:21.019169 DQS Delay:
1854 00:40:21.019223 DQS0 = 0, DQS1 = 0
1855 00:40:21.019278 DQM Delay:
1856 00:40:21.019332 DQM0 = 92, DQM1 = 81
1857 00:40:21.019386 DQ Delay:
1858 00:40:21.019439 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1859 00:40:21.019493 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1860 00:40:21.019548 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1861 00:40:21.019602 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =84
1862 00:40:21.019656
1863 00:40:21.019710
1864 00:40:21.019764 [DQSOSCAuto] RK0, (LSB)MR18= 0x3856, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
1865 00:40:21.019819 CH1 RK0: MR19=606, MR18=3856
1866 00:40:21.019874 CH1_RK0: MR19=0x606, MR18=0x3856, DQSOSC=388, MR23=63, INC=98, DEC=65
1867 00:40:21.019929
1868 00:40:21.019983 ----->DramcWriteLeveling(PI) begin...
1869 00:40:21.020038 ==
1870 00:40:21.020093 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 00:40:21.020148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 00:40:21.020203 ==
1873 00:40:21.020257 Write leveling (Byte 0): 27 => 27
1874 00:40:21.020311 Write leveling (Byte 1): 31 => 31
1875 00:40:21.020365 DramcWriteLeveling(PI) end<-----
1876 00:40:21.020419
1877 00:40:21.020472 ==
1878 00:40:21.020526 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 00:40:21.020623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 00:40:21.020679 ==
1881 00:40:21.020733 [Gating] SW mode calibration
1882 00:40:21.020788 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1883 00:40:21.020848 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1884 00:40:21.020926 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1885 00:40:21.020982 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1886 00:40:21.021037 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1887 00:40:21.021092 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:40:21.021146 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:40:21.021201 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:40:21.021255 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:40:21.021310 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:40:21.021364 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:40:21.021418 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:40:21.021472 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:40:21.021526 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:40:21.021579 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:40:21.021634 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:40:21.021687 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:40:21.021741 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:40:21.021795 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:40:21.021849 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1902 00:40:21.021903 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:40:21.022161 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:40:21.022225 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:40:21.022280 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:40:21.022353 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:40:21.022422 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 00:40:21.022476 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:40:21.022531 0 9 4 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
1910 00:40:21.022584 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 00:40:21.022639 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 00:40:21.022692 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 00:40:21.022746 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 00:40:21.022800 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 00:40:21.022855 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 00:40:21.022909 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 00:40:21.022964 0 10 4 | B1->B0 | 2e2e 3030 | 1 0 | (1 0) (0 0)
1918 00:40:21.023018 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:40:21.023071 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 00:40:21.023125 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 00:40:21.023179 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 00:40:21.023232 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 00:40:21.023286 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 00:40:21.023340 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 00:40:21.023394 0 11 4 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
1926 00:40:21.023448 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 00:40:21.023502 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 00:40:21.023556 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 00:40:21.023609 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 00:40:21.023663 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 00:40:21.023717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 00:40:21.023771 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 00:40:21.023825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1934 00:40:21.023879 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1935 00:40:21.023932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:40:21.023986 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:40:21.024040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:40:21.024094 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:40:21.024148 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:40:21.024202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:40:21.024256 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:40:21.024310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:40:21.024363 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:40:21.024417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:40:21.024471 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 00:40:21.024525 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 00:40:21.024621 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 00:40:21.024677 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 00:40:21.024732 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1950 00:40:21.024786 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1951 00:40:21.024840 Total UI for P1: 0, mck2ui 16
1952 00:40:21.024898 best dqsien dly found for B0: ( 0, 14, 4)
1953 00:40:21.024977 Total UI for P1: 0, mck2ui 16
1954 00:40:21.025034 best dqsien dly found for B1: ( 0, 14, 4)
1955 00:40:21.025089 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1956 00:40:21.025144 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1957 00:40:21.025198
1958 00:40:21.025252 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1959 00:40:21.025306 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1960 00:40:21.025359 [Gating] SW calibration Done
1961 00:40:21.025414 ==
1962 00:40:21.025468 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 00:40:21.025522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 00:40:21.025577 ==
1965 00:40:21.025631 RX Vref Scan: 0
1966 00:40:21.025685
1967 00:40:21.025739 RX Vref 0 -> 0, step: 1
1968 00:40:21.025793
1969 00:40:21.025847 RX Delay -130 -> 252, step: 16
1970 00:40:21.025901 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1971 00:40:21.025955 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1972 00:40:21.026009 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1973 00:40:21.026063 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1974 00:40:21.026117 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1975 00:40:21.026171 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1976 00:40:21.026224 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1977 00:40:21.026278 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1978 00:40:21.026331 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1979 00:40:21.026385 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1980 00:40:21.026439 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1981 00:40:21.026492 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1982 00:40:21.026546 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1983 00:40:21.026600 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1984 00:40:21.026655 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1985 00:40:21.026709 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1986 00:40:21.179580 ==
1987 00:40:21.179728 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 00:40:21.179798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 00:40:21.179860 ==
1990 00:40:21.179921 DQS Delay:
1991 00:40:21.179979 DQS0 = 0, DQS1 = 0
1992 00:40:21.180036 DQM Delay:
1993 00:40:21.180092 DQM0 = 92, DQM1 = 82
1994 00:40:21.180148 DQ Delay:
1995 00:40:21.180204 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1996 00:40:21.180259 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1997 00:40:21.180315 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1998 00:40:21.180369 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1999 00:40:21.180424
2000 00:40:21.180478
2001 00:40:21.180532 ==
2002 00:40:21.180647 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 00:40:21.180914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 00:40:21.180979 ==
2005 00:40:21.181053
2006 00:40:21.181122
2007 00:40:21.181176 TX Vref Scan disable
2008 00:40:21.181232 == TX Byte 0 ==
2009 00:40:21.181303 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2010 00:40:21.181374 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2011 00:40:21.181429 == TX Byte 1 ==
2012 00:40:21.181484 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2013 00:40:21.181563 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2014 00:40:21.181671 ==
2015 00:40:21.181729 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 00:40:21.181785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 00:40:21.181842 ==
2018 00:40:21.181911 TX Vref=22, minBit 13, minWin=27, winSum=454
2019 00:40:21.181967 TX Vref=24, minBit 13, minWin=27, winSum=456
2020 00:40:21.182022 TX Vref=26, minBit 15, minWin=27, winSum=458
2021 00:40:21.182077 TX Vref=28, minBit 13, minWin=27, winSum=459
2022 00:40:21.182132 TX Vref=30, minBit 15, minWin=27, winSum=461
2023 00:40:21.182187 TX Vref=32, minBit 15, minWin=27, winSum=459
2024 00:40:21.182242 [TxChooseVref] Worse bit 15, Min win 27, Win sum 461, Final Vref 30
2025 00:40:21.182297
2026 00:40:21.182351 Final TX Range 1 Vref 30
2027 00:40:21.182406
2028 00:40:21.182460 ==
2029 00:40:21.182514 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 00:40:21.182568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 00:40:21.182623 ==
2032 00:40:21.182677
2033 00:40:21.182731
2034 00:40:21.182785 TX Vref Scan disable
2035 00:40:21.182839 == TX Byte 0 ==
2036 00:40:21.182893 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2037 00:40:21.182947 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2038 00:40:21.183001 == TX Byte 1 ==
2039 00:40:21.183055 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2040 00:40:21.183110 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2041 00:40:21.183164
2042 00:40:21.183217 [DATLAT]
2043 00:40:21.183270 Freq=800, CH1 RK1
2044 00:40:21.183325
2045 00:40:21.183379 DATLAT Default: 0xa
2046 00:40:21.183432 0, 0xFFFF, sum = 0
2047 00:40:21.183488 1, 0xFFFF, sum = 0
2048 00:40:21.183543 2, 0xFFFF, sum = 0
2049 00:40:21.183598 3, 0xFFFF, sum = 0
2050 00:40:21.183652 4, 0xFFFF, sum = 0
2051 00:40:21.183708 5, 0xFFFF, sum = 0
2052 00:40:21.183763 6, 0xFFFF, sum = 0
2053 00:40:21.183818 7, 0xFFFF, sum = 0
2054 00:40:21.183873 8, 0xFFFF, sum = 0
2055 00:40:21.183928 9, 0x0, sum = 1
2056 00:40:21.183983 10, 0x0, sum = 2
2057 00:40:21.184039 11, 0x0, sum = 3
2058 00:40:21.184093 12, 0x0, sum = 4
2059 00:40:21.184148 best_step = 10
2060 00:40:21.184203
2061 00:40:21.184257 ==
2062 00:40:21.184312 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 00:40:21.184366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 00:40:21.184421 ==
2065 00:40:21.184475 RX Vref Scan: 0
2066 00:40:21.184529
2067 00:40:21.184625 RX Vref 0 -> 0, step: 1
2068 00:40:21.184679
2069 00:40:21.184733 RX Delay -95 -> 252, step: 8
2070 00:40:21.184788 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2071 00:40:21.184843 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2072 00:40:21.184902 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2073 00:40:21.184957 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2074 00:40:21.185012 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2075 00:40:21.185066 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2076 00:40:21.185120 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2077 00:40:21.185174 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2078 00:40:21.185228 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2079 00:40:21.185282 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2080 00:40:21.185338 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2081 00:40:21.185392 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2082 00:40:21.185448 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2083 00:40:21.185502 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2084 00:40:21.185558 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2085 00:40:21.185612 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2086 00:40:21.185682 ==
2087 00:40:21.185749 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 00:40:21.185806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 00:40:21.185863 ==
2090 00:40:21.185919 DQS Delay:
2091 00:40:21.185975 DQS0 = 0, DQS1 = 0
2092 00:40:21.186030 DQM Delay:
2093 00:40:21.186086 DQM0 = 91, DQM1 = 83
2094 00:40:21.186143 DQ Delay:
2095 00:40:21.186198 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2096 00:40:21.186254 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2097 00:40:21.186310 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2098 00:40:21.186366 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2099 00:40:21.186422
2100 00:40:21.186478
2101 00:40:21.186534 [DQSOSCAuto] RK1, (LSB)MR18= 0x4217, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
2102 00:40:21.186592 CH1 RK1: MR19=606, MR18=4217
2103 00:40:21.186648 CH1_RK1: MR19=0x606, MR18=0x4217, DQSOSC=393, MR23=63, INC=95, DEC=63
2104 00:40:21.186705 [RxdqsGatingPostProcess] freq 800
2105 00:40:21.186761 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 00:40:21.186818 Pre-setting of DQS Precalculation
2107 00:40:21.186874 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 00:40:21.186930 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 00:40:21.186987 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 00:40:21.187044
2111 00:40:21.187099
2112 00:40:21.187154 [Calibration Summary] 1600 Mbps
2113 00:40:21.187211 CH 0, Rank 0
2114 00:40:21.187266 SW Impedance : PASS
2115 00:40:21.187322 DUTY Scan : NO K
2116 00:40:21.187377 ZQ Calibration : PASS
2117 00:40:21.187434 Jitter Meter : NO K
2118 00:40:21.187489 CBT Training : PASS
2119 00:40:21.187545 Write leveling : PASS
2120 00:40:21.187601 RX DQS gating : PASS
2121 00:40:21.187656 RX DQ/DQS(RDDQC) : PASS
2122 00:40:21.187711 TX DQ/DQS : PASS
2123 00:40:21.187767 RX DATLAT : PASS
2124 00:40:21.187823 RX DQ/DQS(Engine): PASS
2125 00:40:21.187878 TX OE : NO K
2126 00:40:21.187935 All Pass.
2127 00:40:21.187990
2128 00:40:21.188045 CH 0, Rank 1
2129 00:40:21.188101 SW Impedance : PASS
2130 00:40:21.188157 DUTY Scan : NO K
2131 00:40:21.188212 ZQ Calibration : PASS
2132 00:40:21.188267 Jitter Meter : NO K
2133 00:40:21.188323 CBT Training : PASS
2134 00:40:21.188379 Write leveling : PASS
2135 00:40:21.188435 RX DQS gating : PASS
2136 00:40:21.188490 RX DQ/DQS(RDDQC) : PASS
2137 00:40:21.188549 TX DQ/DQS : PASS
2138 00:40:21.188637 RX DATLAT : PASS
2139 00:40:21.188693 RX DQ/DQS(Engine): PASS
2140 00:40:21.188749 TX OE : NO K
2141 00:40:21.188805 All Pass.
2142 00:40:21.188861
2143 00:40:21.188917 CH 1, Rank 0
2144 00:40:21.188973 SW Impedance : PASS
2145 00:40:21.189028 DUTY Scan : NO K
2146 00:40:21.189084 ZQ Calibration : PASS
2147 00:40:21.189140 Jitter Meter : NO K
2148 00:40:21.189196 CBT Training : PASS
2149 00:40:21.189251 Write leveling : PASS
2150 00:40:21.189524 RX DQS gating : PASS
2151 00:40:21.189590 RX DQ/DQS(RDDQC) : PASS
2152 00:40:21.189649 TX DQ/DQS : PASS
2153 00:40:21.189708 RX DATLAT : PASS
2154 00:40:21.189765 RX DQ/DQS(Engine): PASS
2155 00:40:21.189836 TX OE : NO K
2156 00:40:21.189892 All Pass.
2157 00:40:21.189947
2158 00:40:21.190003 CH 1, Rank 1
2159 00:40:21.190059 SW Impedance : PASS
2160 00:40:21.190115 DUTY Scan : NO K
2161 00:40:21.190172 ZQ Calibration : PASS
2162 00:40:21.190228 Jitter Meter : NO K
2163 00:40:21.190283 CBT Training : PASS
2164 00:40:21.190339 Write leveling : PASS
2165 00:40:21.190395 RX DQS gating : PASS
2166 00:40:21.190450 RX DQ/DQS(RDDQC) : PASS
2167 00:40:21.190506 TX DQ/DQS : PASS
2168 00:40:21.190561 RX DATLAT : PASS
2169 00:40:21.190616 RX DQ/DQS(Engine): PASS
2170 00:40:21.190672 TX OE : NO K
2171 00:40:21.190728 All Pass.
2172 00:40:21.190784
2173 00:40:21.190838 DramC Write-DBI off
2174 00:40:21.190894 PER_BANK_REFRESH: Hybrid Mode
2175 00:40:21.190951 TX_TRACKING: ON
2176 00:40:21.191008 [GetDramInforAfterCalByMRR] Vendor 6.
2177 00:40:21.191064 [GetDramInforAfterCalByMRR] Revision 606.
2178 00:40:21.191119 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 00:40:21.191174 MR0 0x3b3b
2180 00:40:21.191230 MR8 0x5151
2181 00:40:21.191285 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 00:40:21.191340
2183 00:40:21.191395 MR0 0x3b3b
2184 00:40:21.191450 MR8 0x5151
2185 00:40:21.191506 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 00:40:21.191563
2187 00:40:21.191619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 00:40:21.191676 [FAST_K] Save calibration result to emmc
2189 00:40:21.191732 [FAST_K] Save calibration result to emmc
2190 00:40:21.191788 dram_init: config_dvfs: 1
2191 00:40:21.191843 dramc_set_vcore_voltage set vcore to 662500
2192 00:40:21.191900 Read voltage for 1200, 2
2193 00:40:21.191955 Vio18 = 0
2194 00:40:21.192011 Vcore = 662500
2195 00:40:21.192067 Vdram = 0
2196 00:40:21.192122 Vddq = 0
2197 00:40:21.192177 Vmddr = 0
2198 00:40:21.192233 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 00:40:21.192289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 00:40:21.192344 MEM_TYPE=3, freq_sel=15
2201 00:40:21.192400 sv_algorithm_assistance_LP4_1600
2202 00:40:21.192456 ============ PULL DRAM RESETB DOWN ============
2203 00:40:21.192512 ========== PULL DRAM RESETB DOWN end =========
2204 00:40:21.192606 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 00:40:21.192663 ===================================
2206 00:40:21.192719 LPDDR4 DRAM CONFIGURATION
2207 00:40:21.192775 ===================================
2208 00:40:21.192830 EX_ROW_EN[0] = 0x0
2209 00:40:21.192886 EX_ROW_EN[1] = 0x0
2210 00:40:21.192960 LP4Y_EN = 0x0
2211 00:40:21.193017 WORK_FSP = 0x0
2212 00:40:21.193103 WL = 0x4
2213 00:40:21.193159 RL = 0x4
2214 00:40:21.193215 BL = 0x2
2215 00:40:21.193271 RPST = 0x0
2216 00:40:21.193326 RD_PRE = 0x0
2217 00:40:21.193382 WR_PRE = 0x1
2218 00:40:21.193461 WR_PST = 0x0
2219 00:40:21.193522 DBI_WR = 0x0
2220 00:40:21.193578 DBI_RD = 0x0
2221 00:40:21.193634 OTF = 0x1
2222 00:40:21.193690 ===================================
2223 00:40:21.193748 ===================================
2224 00:40:21.193804 ANA top config
2225 00:40:21.193860 ===================================
2226 00:40:21.193916 DLL_ASYNC_EN = 0
2227 00:40:21.193971 ALL_SLAVE_EN = 0
2228 00:40:21.194027 NEW_RANK_MODE = 1
2229 00:40:21.194084 DLL_IDLE_MODE = 1
2230 00:40:21.194140 LP45_APHY_COMB_EN = 1
2231 00:40:21.194195 TX_ODT_DIS = 1
2232 00:40:21.194252 NEW_8X_MODE = 1
2233 00:40:21.194308 ===================================
2234 00:40:21.194364 ===================================
2235 00:40:21.194421 data_rate = 2400
2236 00:40:21.194476 CKR = 1
2237 00:40:21.194532 DQ_P2S_RATIO = 8
2238 00:40:21.194587 ===================================
2239 00:40:21.194643 CA_P2S_RATIO = 8
2240 00:40:21.194699 DQ_CA_OPEN = 0
2241 00:40:21.194755 DQ_SEMI_OPEN = 0
2242 00:40:21.194810 CA_SEMI_OPEN = 0
2243 00:40:21.194866 CA_FULL_RATE = 0
2244 00:40:21.194927 DQ_CKDIV4_EN = 0
2245 00:40:21.194984 CA_CKDIV4_EN = 0
2246 00:40:21.195039 CA_PREDIV_EN = 0
2247 00:40:21.195095 PH8_DLY = 17
2248 00:40:21.195151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 00:40:21.195207 DQ_AAMCK_DIV = 4
2250 00:40:21.195262 CA_AAMCK_DIV = 4
2251 00:40:21.195317 CA_ADMCK_DIV = 4
2252 00:40:21.195372 DQ_TRACK_CA_EN = 0
2253 00:40:21.195428 CA_PICK = 1200
2254 00:40:21.195483 CA_MCKIO = 1200
2255 00:40:21.195539 MCKIO_SEMI = 0
2256 00:40:21.195594 PLL_FREQ = 2366
2257 00:40:21.195650 DQ_UI_PI_RATIO = 32
2258 00:40:21.195705 CA_UI_PI_RATIO = 0
2259 00:40:21.195760 ===================================
2260 00:40:21.195816 ===================================
2261 00:40:21.195871 memory_type:LPDDR4
2262 00:40:21.195927 GP_NUM : 10
2263 00:40:21.195983 SRAM_EN : 1
2264 00:40:21.196039 MD32_EN : 0
2265 00:40:21.196094 ===================================
2266 00:40:21.196151 [ANA_INIT] >>>>>>>>>>>>>>
2267 00:40:21.196207 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 00:40:21.196263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 00:40:21.196319 ===================================
2270 00:40:21.196375 data_rate = 2400,PCW = 0X5b00
2271 00:40:21.196430 ===================================
2272 00:40:21.196486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 00:40:21.196543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 00:40:21.196641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 00:40:21.196697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 00:40:21.196753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 00:40:21.196810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 00:40:21.196866 [ANA_INIT] flow start
2279 00:40:21.196941 [ANA_INIT] PLL >>>>>>>>
2280 00:40:21.197028 [ANA_INIT] PLL <<<<<<<<
2281 00:40:21.197088 [ANA_INIT] MIDPI >>>>>>>>
2282 00:40:21.197145 [ANA_INIT] MIDPI <<<<<<<<
2283 00:40:21.197201 [ANA_INIT] DLL >>>>>>>>
2284 00:40:21.197257 [ANA_INIT] DLL <<<<<<<<
2285 00:40:21.197313 [ANA_INIT] flow end
2286 00:40:21.197368 ============ LP4 DIFF to SE enter ============
2287 00:40:21.197654 ============ LP4 DIFF to SE exit ============
2288 00:40:21.197727 [ANA_INIT] <<<<<<<<<<<<<
2289 00:40:21.197787 [Flow] Enable top DCM control >>>>>
2290 00:40:21.197846 [Flow] Enable top DCM control <<<<<
2291 00:40:21.197903 Enable DLL master slave shuffle
2292 00:40:21.197961 ==============================================================
2293 00:40:21.198018 Gating Mode config
2294 00:40:21.198076 ==============================================================
2295 00:40:21.198148 Config description:
2296 00:40:21.198204 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 00:40:21.198261 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 00:40:21.198318 SELPH_MODE 0: By rank 1: By Phase
2299 00:40:21.198374 ==============================================================
2300 00:40:21.198431 GAT_TRACK_EN = 1
2301 00:40:21.198487 RX_GATING_MODE = 2
2302 00:40:21.198542 RX_GATING_TRACK_MODE = 2
2303 00:40:21.198598 SELPH_MODE = 1
2304 00:40:21.198654 PICG_EARLY_EN = 1
2305 00:40:21.198710 VALID_LAT_VALUE = 1
2306 00:40:21.198766 ==============================================================
2307 00:40:21.198822 Enter into Gating configuration >>>>
2308 00:40:21.198878 Exit from Gating configuration <<<<
2309 00:40:21.198934 Enter into DVFS_PRE_config >>>>>
2310 00:40:21.198990 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 00:40:21.199048 Exit from DVFS_PRE_config <<<<<
2312 00:40:21.199104 Enter into PICG configuration >>>>
2313 00:40:21.199176 Exit from PICG configuration <<<<
2314 00:40:21.199249 [RX_INPUT] configuration >>>>>
2315 00:40:21.199304 [RX_INPUT] configuration <<<<<
2316 00:40:21.199360 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 00:40:21.199417 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 00:40:21.199473 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 00:40:21.199529 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 00:40:21.199585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 00:40:21.199641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 00:40:21.199697 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 00:40:21.199754 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 00:40:21.199810 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 00:40:21.199866 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 00:40:21.199922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 00:40:21.199978 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 00:40:21.200034 ===================================
2329 00:40:21.200090 LPDDR4 DRAM CONFIGURATION
2330 00:40:21.200146 ===================================
2331 00:40:21.200202 EX_ROW_EN[0] = 0x0
2332 00:40:21.200258 EX_ROW_EN[1] = 0x0
2333 00:40:21.200314 LP4Y_EN = 0x0
2334 00:40:21.200369 WORK_FSP = 0x0
2335 00:40:21.200424 WL = 0x4
2336 00:40:21.200479 RL = 0x4
2337 00:40:21.200535 BL = 0x2
2338 00:40:21.200632 RPST = 0x0
2339 00:40:21.200689 RD_PRE = 0x0
2340 00:40:21.200745 WR_PRE = 0x1
2341 00:40:21.200800 WR_PST = 0x0
2342 00:40:21.200856 DBI_WR = 0x0
2343 00:40:21.200912 DBI_RD = 0x0
2344 00:40:21.200967 OTF = 0x1
2345 00:40:21.201023 ===================================
2346 00:40:21.201079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 00:40:21.201134 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 00:40:21.201190 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 00:40:21.201246 ===================================
2350 00:40:21.201334 LPDDR4 DRAM CONFIGURATION
2351 00:40:21.201390 ===================================
2352 00:40:21.201445 EX_ROW_EN[0] = 0x10
2353 00:40:21.201500 EX_ROW_EN[1] = 0x0
2354 00:40:21.201556 LP4Y_EN = 0x0
2355 00:40:21.201611 WORK_FSP = 0x0
2356 00:40:21.201667 WL = 0x4
2357 00:40:21.201722 RL = 0x4
2358 00:40:21.201777 BL = 0x2
2359 00:40:21.201858 RPST = 0x0
2360 00:40:21.201918 RD_PRE = 0x0
2361 00:40:21.201973 WR_PRE = 0x1
2362 00:40:21.202027 WR_PST = 0x0
2363 00:40:21.202081 DBI_WR = 0x0
2364 00:40:21.202135 DBI_RD = 0x0
2365 00:40:21.202189 OTF = 0x1
2366 00:40:21.202243 ===================================
2367 00:40:21.202297 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 00:40:21.202351 ==
2369 00:40:21.202406 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 00:40:21.202460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 00:40:21.202515 ==
2372 00:40:21.202568 [Duty_Offset_Calibration]
2373 00:40:21.202622 B0:2 B1:0 CA:1
2374 00:40:21.202677
2375 00:40:21.202731 [DutyScan_Calibration_Flow] k_type=0
2376 00:40:21.202785
2377 00:40:21.202838 ==CLK 0==
2378 00:40:21.202892 Final CLK duty delay cell = -4
2379 00:40:21.202978 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2380 00:40:21.203032 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2381 00:40:21.203085 [-4] AVG Duty = 4937%(X100)
2382 00:40:21.203139
2383 00:40:21.203193 CH0 CLK Duty spec in!! Max-Min= 125%
2384 00:40:21.203247 [DutyScan_Calibration_Flow] ====Done====
2385 00:40:21.203302
2386 00:40:21.203355 [DutyScan_Calibration_Flow] k_type=1
2387 00:40:21.203409
2388 00:40:21.203463 ==DQS 0 ==
2389 00:40:21.203516 Final DQS duty delay cell = 0
2390 00:40:21.203570 [0] MAX Duty = 5187%(X100), DQS PI = 30
2391 00:40:21.203624 [0] MIN Duty = 4938%(X100), DQS PI = 0
2392 00:40:21.203678 [0] AVG Duty = 5062%(X100)
2393 00:40:21.203732
2394 00:40:21.203785 ==DQS 1 ==
2395 00:40:21.203839 Final DQS duty delay cell = -4
2396 00:40:21.203893 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2397 00:40:21.203946 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2398 00:40:21.204001 [-4] AVG Duty = 5015%(X100)
2399 00:40:21.204055
2400 00:40:21.204108 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2401 00:40:21.204162
2402 00:40:21.204215 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2403 00:40:21.204268 [DutyScan_Calibration_Flow] ====Done====
2404 00:40:21.204323
2405 00:40:21.204377 [DutyScan_Calibration_Flow] k_type=3
2406 00:40:21.204430
2407 00:40:21.204483 ==DQM 0 ==
2408 00:40:21.204537 Final DQM duty delay cell = 0
2409 00:40:21.204847 [0] MAX Duty = 5062%(X100), DQS PI = 24
2410 00:40:21.204911 [0] MIN Duty = 4813%(X100), DQS PI = 0
2411 00:40:21.204968 [0] AVG Duty = 4937%(X100)
2412 00:40:21.205025
2413 00:40:21.205080 ==DQM 1 ==
2414 00:40:21.205136 Final DQM duty delay cell = 0
2415 00:40:21.205192 [0] MAX Duty = 5187%(X100), DQS PI = 48
2416 00:40:21.205247 [0] MIN Duty = 5000%(X100), DQS PI = 14
2417 00:40:21.205317 [0] AVG Duty = 5093%(X100)
2418 00:40:21.205371
2419 00:40:21.205424 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2420 00:40:21.205479
2421 00:40:21.205533 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2422 00:40:21.205586 [DutyScan_Calibration_Flow] ====Done====
2423 00:40:21.205640
2424 00:40:21.205693 [DutyScan_Calibration_Flow] k_type=2
2425 00:40:21.205747
2426 00:40:21.205801 ==DQ 0 ==
2427 00:40:21.205855 Final DQ duty delay cell = -4
2428 00:40:21.205910 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2429 00:40:21.205964 [-4] MIN Duty = 4844%(X100), DQS PI = 16
2430 00:40:21.206027 [-4] AVG Duty = 4937%(X100)
2431 00:40:21.206099
2432 00:40:21.206155 ==DQ 1 ==
2433 00:40:21.206210 Final DQ duty delay cell = 4
2434 00:40:21.206265 [4] MAX Duty = 5093%(X100), DQS PI = 4
2435 00:40:21.206320 [4] MIN Duty = 5031%(X100), DQS PI = 0
2436 00:40:21.206374 [4] AVG Duty = 5062%(X100)
2437 00:40:21.206429
2438 00:40:21.206483 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2439 00:40:21.206537
2440 00:40:21.206591 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2441 00:40:21.206645 [DutyScan_Calibration_Flow] ====Done====
2442 00:40:21.206700 ==
2443 00:40:21.206753 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 00:40:21.206808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 00:40:21.206863 ==
2446 00:40:21.206934 [Duty_Offset_Calibration]
2447 00:40:21.207004 B0:0 B1:-1 CA:2
2448 00:40:21.207059
2449 00:40:21.207112 [DutyScan_Calibration_Flow] k_type=0
2450 00:40:21.207167
2451 00:40:21.207220 ==CLK 0==
2452 00:40:21.207273 Final CLK duty delay cell = 0
2453 00:40:21.207328 [0] MAX Duty = 5156%(X100), DQS PI = 16
2454 00:40:21.207382 [0] MIN Duty = 4938%(X100), DQS PI = 44
2455 00:40:21.207437 [0] AVG Duty = 5047%(X100)
2456 00:40:21.207490
2457 00:40:21.207544 CH1 CLK Duty spec in!! Max-Min= 218%
2458 00:40:21.207598 [DutyScan_Calibration_Flow] ====Done====
2459 00:40:21.207652
2460 00:40:21.207706 [DutyScan_Calibration_Flow] k_type=1
2461 00:40:21.207761
2462 00:40:21.207815 ==DQS 0 ==
2463 00:40:21.207869 Final DQS duty delay cell = 0
2464 00:40:21.207924 [0] MAX Duty = 5093%(X100), DQS PI = 24
2465 00:40:21.207978 [0] MIN Duty = 4969%(X100), DQS PI = 0
2466 00:40:21.208032 [0] AVG Duty = 5031%(X100)
2467 00:40:21.208085
2468 00:40:21.208139 ==DQS 1 ==
2469 00:40:21.208193 Final DQS duty delay cell = 0
2470 00:40:21.208248 [0] MAX Duty = 5156%(X100), DQS PI = 0
2471 00:40:21.208302 [0] MIN Duty = 4844%(X100), DQS PI = 36
2472 00:40:21.208356 [0] AVG Duty = 5000%(X100)
2473 00:40:21.208410
2474 00:40:21.208464 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2475 00:40:21.208518
2476 00:40:21.208617 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2477 00:40:21.208673 [DutyScan_Calibration_Flow] ====Done====
2478 00:40:21.208727
2479 00:40:21.208781 [DutyScan_Calibration_Flow] k_type=3
2480 00:40:21.208835
2481 00:40:21.208889 ==DQM 0 ==
2482 00:40:21.208977 Final DQM duty delay cell = 4
2483 00:40:21.209061 [4] MAX Duty = 5093%(X100), DQS PI = 6
2484 00:40:21.209116 [4] MIN Duty = 4938%(X100), DQS PI = 32
2485 00:40:21.209170 [4] AVG Duty = 5015%(X100)
2486 00:40:21.209224
2487 00:40:21.209278 ==DQM 1 ==
2488 00:40:21.209331 Final DQM duty delay cell = -4
2489 00:40:21.209386 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2490 00:40:21.209441 [-4] MIN Duty = 4751%(X100), DQS PI = 34
2491 00:40:21.209496 [-4] AVG Duty = 4875%(X100)
2492 00:40:21.209550
2493 00:40:21.209603 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2494 00:40:21.209657
2495 00:40:21.209711 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2496 00:40:21.209765 [DutyScan_Calibration_Flow] ====Done====
2497 00:40:21.209818
2498 00:40:21.209872 [DutyScan_Calibration_Flow] k_type=2
2499 00:40:21.209950
2500 00:40:21.210008 ==DQ 0 ==
2501 00:40:21.210064 Final DQ duty delay cell = 0
2502 00:40:21.210119 [0] MAX Duty = 5062%(X100), DQS PI = 20
2503 00:40:21.210174 [0] MIN Duty = 4938%(X100), DQS PI = 0
2504 00:40:21.210229 [0] AVG Duty = 5000%(X100)
2505 00:40:21.210283
2506 00:40:21.210337 ==DQ 1 ==
2507 00:40:21.210391 Final DQ duty delay cell = 0
2508 00:40:21.210445 [0] MAX Duty = 5031%(X100), DQS PI = 2
2509 00:40:21.210500 [0] MIN Duty = 4813%(X100), DQS PI = 34
2510 00:40:21.210554 [0] AVG Duty = 4922%(X100)
2511 00:40:21.210608
2512 00:40:21.210661 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2513 00:40:21.210715
2514 00:40:21.210769 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2515 00:40:21.210823 [DutyScan_Calibration_Flow] ====Done====
2516 00:40:21.210877 nWR fixed to 30
2517 00:40:21.210933 [ModeRegInit_LP4] CH0 RK0
2518 00:40:21.210986 [ModeRegInit_LP4] CH0 RK1
2519 00:40:21.211040 [ModeRegInit_LP4] CH1 RK0
2520 00:40:21.211094 [ModeRegInit_LP4] CH1 RK1
2521 00:40:21.211148 match AC timing 7
2522 00:40:21.211202 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 00:40:21.211257 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 00:40:21.211311 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 00:40:21.211366 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 00:40:21.211421 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 00:40:21.211475 ==
2528 00:40:21.211529 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 00:40:21.211583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 00:40:21.211638 ==
2531 00:40:21.211692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 00:40:21.211747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 00:40:21.211802 [CA 0] Center 38 (8~69) winsize 62
2534 00:40:21.211856 [CA 1] Center 38 (7~69) winsize 63
2535 00:40:21.211910 [CA 2] Center 35 (5~66) winsize 62
2536 00:40:21.211965 [CA 3] Center 35 (5~66) winsize 62
2537 00:40:21.212019 [CA 4] Center 34 (4~65) winsize 62
2538 00:40:21.212073 [CA 5] Center 33 (3~63) winsize 61
2539 00:40:21.212127
2540 00:40:21.212181 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2541 00:40:21.212236
2542 00:40:21.212289 [CATrainingPosCal] consider 1 rank data
2543 00:40:21.212344 u2DelayCellTimex100 = 270/100 ps
2544 00:40:21.212398 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2545 00:40:21.212452 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2546 00:40:21.212507 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 00:40:21.212587 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 00:40:21.212657 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2549 00:40:21.212711 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2550 00:40:21.212766
2551 00:40:21.212820 CA PerBit enable=1, Macro0, CA PI delay=33
2552 00:40:21.212874
2553 00:40:21.212928 [CBTSetCACLKResult] CA Dly = 33
2554 00:40:21.212982 CS Dly: 6 (0~37)
2555 00:40:21.213036 ==
2556 00:40:21.213090 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 00:40:21.213143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 00:40:21.213198 ==
2559 00:40:21.213455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 00:40:21.213558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2561 00:40:21.213615 [CA 0] Center 39 (8~70) winsize 63
2562 00:40:21.213670 [CA 1] Center 38 (8~69) winsize 62
2563 00:40:21.213726 [CA 2] Center 35 (5~66) winsize 62
2564 00:40:21.213781 [CA 3] Center 35 (5~66) winsize 62
2565 00:40:21.213835 [CA 4] Center 34 (4~65) winsize 62
2566 00:40:21.213906 [CA 5] Center 34 (4~64) winsize 61
2567 00:40:21.213963
2568 00:40:21.214018 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2569 00:40:21.214072
2570 00:40:21.214127 [CATrainingPosCal] consider 2 rank data
2571 00:40:21.214181 u2DelayCellTimex100 = 270/100 ps
2572 00:40:21.214235 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2573 00:40:21.214290 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2574 00:40:21.214344 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 00:40:21.214398 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2576 00:40:21.214452 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2577 00:40:21.214530 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2578 00:40:21.214588
2579 00:40:21.214643 CA PerBit enable=1, Macro0, CA PI delay=33
2580 00:40:21.214698
2581 00:40:21.214752 [CBTSetCACLKResult] CA Dly = 33
2582 00:40:21.214807 CS Dly: 7 (0~39)
2583 00:40:21.214861
2584 00:40:21.214915 ----->DramcWriteLeveling(PI) begin...
2585 00:40:21.214971 ==
2586 00:40:21.215025 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 00:40:21.215079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 00:40:21.215134 ==
2589 00:40:21.215188 Write leveling (Byte 0): 33 => 33
2590 00:40:21.215242 Write leveling (Byte 1): 32 => 32
2591 00:40:21.215329 DramcWriteLeveling(PI) end<-----
2592 00:40:21.215382
2593 00:40:21.215436 ==
2594 00:40:21.215490 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 00:40:21.215544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 00:40:21.215599 ==
2597 00:40:21.215653 [Gating] SW mode calibration
2598 00:40:21.215707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 00:40:21.215762 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 00:40:21.215817 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2601 00:40:21.215871 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2602 00:40:21.215926 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 00:40:21.215979 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 00:40:21.216034 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 00:40:21.216088 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 00:40:21.216142 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2607 00:40:21.216195 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2608 00:40:21.216249 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2609 00:40:21.216304 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 00:40:21.216359 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 00:40:21.216412 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 00:40:21.216466 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 00:40:21.216520 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 00:40:21.216616 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2615 00:40:21.216671 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2616 00:40:21.216725 1 1 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
2617 00:40:21.216780 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 00:40:21.216834 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 00:40:21.216888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 00:40:21.216942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 00:40:21.216996 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 00:40:21.217050 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 00:40:21.217103 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2624 00:40:21.217157 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2625 00:40:21.217211 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:40:21.217265 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:40:21.217319 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:40:21.217373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:40:21.217427 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:40:21.217480 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:40:21.217534 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:40:21.217588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 00:40:21.217642 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 00:40:21.217696 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 00:40:21.217750 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 00:40:21.217804 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 00:40:21.217858 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 00:40:21.217912 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2639 00:40:21.217966 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2640 00:40:21.218020 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 00:40:21.218074 Total UI for P1: 0, mck2ui 16
2642 00:40:21.218129 best dqsien dly found for B0: ( 1, 3, 26)
2643 00:40:21.218184 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 00:40:21.218238 Total UI for P1: 0, mck2ui 16
2645 00:40:21.218293 best dqsien dly found for B1: ( 1, 3, 30)
2646 00:40:21.218347 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2647 00:40:21.218401 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2648 00:40:21.218464
2649 00:40:21.218557 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2650 00:40:21.218641 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2651 00:40:21.218725 [Gating] SW calibration Done
2652 00:40:21.218801 ==
2653 00:40:21.218857 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 00:40:21.218912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 00:40:21.218967 ==
2656 00:40:21.219020 RX Vref Scan: 0
2657 00:40:21.219075
2658 00:40:21.219128 RX Vref 0 -> 0, step: 1
2659 00:40:21.219182
2660 00:40:21.219236 RX Delay -40 -> 252, step: 8
2661 00:40:21.219290 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2662 00:40:21.219344 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2663 00:40:21.219600 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2664 00:40:21.219661 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2665 00:40:21.219717 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2666 00:40:21.219772 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2667 00:40:21.219827 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2668 00:40:21.219881 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2669 00:40:21.219936 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2670 00:40:21.219990 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2671 00:40:21.220044 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2672 00:40:21.220098 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2673 00:40:21.220152 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2674 00:40:21.220206 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2675 00:40:21.220260 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2676 00:40:21.220314 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2677 00:40:21.220368 ==
2678 00:40:21.220422 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 00:40:21.220476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 00:40:21.220531 ==
2681 00:40:21.220626 DQS Delay:
2682 00:40:21.220681 DQS0 = 0, DQS1 = 0
2683 00:40:21.220735 DQM Delay:
2684 00:40:21.220813 DQM0 = 122, DQM1 = 110
2685 00:40:21.220895 DQ Delay:
2686 00:40:21.220953 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2687 00:40:21.221008 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2688 00:40:21.221063 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2689 00:40:21.221117 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2690 00:40:21.221172
2691 00:40:21.221226
2692 00:40:21.221279 ==
2693 00:40:21.221333 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 00:40:21.221388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 00:40:21.221442 ==
2696 00:40:21.221496
2697 00:40:21.221549
2698 00:40:21.221603 TX Vref Scan disable
2699 00:40:21.221657 == TX Byte 0 ==
2700 00:40:21.221711 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2701 00:40:21.221766 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2702 00:40:21.221820 == TX Byte 1 ==
2703 00:40:21.221874 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2704 00:40:21.221928 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2705 00:40:21.221982 ==
2706 00:40:21.222036 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 00:40:21.222091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 00:40:21.222145 ==
2709 00:40:21.222199 TX Vref=22, minBit 2, minWin=24, winSum=407
2710 00:40:21.222254 TX Vref=24, minBit 0, minWin=25, winSum=413
2711 00:40:21.222308 TX Vref=26, minBit 0, minWin=25, winSum=420
2712 00:40:21.222375 TX Vref=28, minBit 1, minWin=25, winSum=422
2713 00:40:21.222461 TX Vref=30, minBit 0, minWin=26, winSum=424
2714 00:40:21.222516 TX Vref=32, minBit 1, minWin=25, winSum=419
2715 00:40:21.222571 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2716 00:40:21.222656
2717 00:40:21.222741 Final TX Range 1 Vref 30
2718 00:40:21.222796
2719 00:40:21.222850 ==
2720 00:40:21.222904 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 00:40:21.222959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 00:40:21.223013 ==
2723 00:40:21.223081
2724 00:40:21.223136
2725 00:40:21.223190 TX Vref Scan disable
2726 00:40:21.223245 == TX Byte 0 ==
2727 00:40:21.223299 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2728 00:40:21.223353 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2729 00:40:21.223408 == TX Byte 1 ==
2730 00:40:21.223462 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2731 00:40:21.223516 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2732 00:40:21.223571
2733 00:40:21.223624 [DATLAT]
2734 00:40:21.223678 Freq=1200, CH0 RK0
2735 00:40:21.223733
2736 00:40:21.223787 DATLAT Default: 0xd
2737 00:40:21.223842 0, 0xFFFF, sum = 0
2738 00:40:21.223898 1, 0xFFFF, sum = 0
2739 00:40:21.223953 2, 0xFFFF, sum = 0
2740 00:40:21.224008 3, 0xFFFF, sum = 0
2741 00:40:21.224063 4, 0xFFFF, sum = 0
2742 00:40:21.224118 5, 0xFFFF, sum = 0
2743 00:40:21.224173 6, 0xFFFF, sum = 0
2744 00:40:21.224228 7, 0xFFFF, sum = 0
2745 00:40:21.224283 8, 0xFFFF, sum = 0
2746 00:40:21.224338 9, 0xFFFF, sum = 0
2747 00:40:21.224392 10, 0xFFFF, sum = 0
2748 00:40:21.224448 11, 0xFFFF, sum = 0
2749 00:40:21.224521 12, 0x0, sum = 1
2750 00:40:21.224605 13, 0x0, sum = 2
2751 00:40:21.224661 14, 0x0, sum = 3
2752 00:40:21.224716 15, 0x0, sum = 4
2753 00:40:21.224771 best_step = 13
2754 00:40:21.224850
2755 00:40:21.224918 ==
2756 00:40:21.224994 Dram Type= 6, Freq= 0, CH_0, rank 0
2757 00:40:21.225160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2758 00:40:21.225259 ==
2759 00:40:21.225319 RX Vref Scan: 1
2760 00:40:21.225375
2761 00:40:21.225430 Set Vref Range= 32 -> 127
2762 00:40:21.225485
2763 00:40:21.225540 RX Vref 32 -> 127, step: 1
2764 00:40:21.225595
2765 00:40:21.225649 RX Delay -13 -> 252, step: 4
2766 00:40:21.225703
2767 00:40:21.225757 Set Vref, RX VrefLevel [Byte0]: 32
2768 00:40:21.225812 [Byte1]: 32
2769 00:40:21.225867
2770 00:40:21.225921 Set Vref, RX VrefLevel [Byte0]: 33
2771 00:40:21.225975 [Byte1]: 33
2772 00:40:21.226029
2773 00:40:21.226082 Set Vref, RX VrefLevel [Byte0]: 34
2774 00:40:21.226154 [Byte1]: 34
2775 00:40:21.226223
2776 00:40:21.226277 Set Vref, RX VrefLevel [Byte0]: 35
2777 00:40:21.226332 [Byte1]: 35
2778 00:40:21.226385
2779 00:40:21.226439 Set Vref, RX VrefLevel [Byte0]: 36
2780 00:40:21.226493 [Byte1]: 36
2781 00:40:21.226548
2782 00:40:21.226601 Set Vref, RX VrefLevel [Byte0]: 37
2783 00:40:21.226655 [Byte1]: 37
2784 00:40:21.226709
2785 00:40:21.226763 Set Vref, RX VrefLevel [Byte0]: 38
2786 00:40:21.226817 [Byte1]: 38
2787 00:40:21.226871
2788 00:40:21.226925 Set Vref, RX VrefLevel [Byte0]: 39
2789 00:40:21.226979 [Byte1]: 39
2790 00:40:21.227033
2791 00:40:21.227087 Set Vref, RX VrefLevel [Byte0]: 40
2792 00:40:21.227141 [Byte1]: 40
2793 00:40:21.227195
2794 00:40:21.227249 Set Vref, RX VrefLevel [Byte0]: 41
2795 00:40:21.227303 [Byte1]: 41
2796 00:40:21.227357
2797 00:40:21.227426 Set Vref, RX VrefLevel [Byte0]: 42
2798 00:40:21.227496 [Byte1]: 42
2799 00:40:21.227550
2800 00:40:21.227604 Set Vref, RX VrefLevel [Byte0]: 43
2801 00:40:21.227658 [Byte1]: 43
2802 00:40:21.227713
2803 00:40:21.227767 Set Vref, RX VrefLevel [Byte0]: 44
2804 00:40:21.227821 [Byte1]: 44
2805 00:40:21.227875
2806 00:40:21.227929 Set Vref, RX VrefLevel [Byte0]: 45
2807 00:40:21.227983 [Byte1]: 45
2808 00:40:21.228037
2809 00:40:21.228090 Set Vref, RX VrefLevel [Byte0]: 46
2810 00:40:21.228145 [Byte1]: 46
2811 00:40:21.228199
2812 00:40:21.228253 Set Vref, RX VrefLevel [Byte0]: 47
2813 00:40:21.228307 [Byte1]: 47
2814 00:40:21.228361
2815 00:40:21.228414 Set Vref, RX VrefLevel [Byte0]: 48
2816 00:40:21.228468 [Byte1]: 48
2817 00:40:21.228522
2818 00:40:21.228615 Set Vref, RX VrefLevel [Byte0]: 49
2819 00:40:21.228670 [Byte1]: 49
2820 00:40:21.228920
2821 00:40:21.228981 Set Vref, RX VrefLevel [Byte0]: 50
2822 00:40:21.229040 [Byte1]: 50
2823 00:40:21.229128
2824 00:40:21.229187 Set Vref, RX VrefLevel [Byte0]: 51
2825 00:40:21.229243 [Byte1]: 51
2826 00:40:21.229297
2827 00:40:21.229352 Set Vref, RX VrefLevel [Byte0]: 52
2828 00:40:21.229406 [Byte1]: 52
2829 00:40:21.229461
2830 00:40:21.229514 Set Vref, RX VrefLevel [Byte0]: 53
2831 00:40:21.229568 [Byte1]: 53
2832 00:40:21.229622
2833 00:40:21.229675 Set Vref, RX VrefLevel [Byte0]: 54
2834 00:40:21.229729 [Byte1]: 54
2835 00:40:21.229784
2836 00:40:21.229838 Set Vref, RX VrefLevel [Byte0]: 55
2837 00:40:21.229891 [Byte1]: 55
2838 00:40:21.229945
2839 00:40:21.229998 Set Vref, RX VrefLevel [Byte0]: 56
2840 00:40:21.230077 [Byte1]: 56
2841 00:40:21.230145
2842 00:40:21.230199 Set Vref, RX VrefLevel [Byte0]: 57
2843 00:40:21.230253 [Byte1]: 57
2844 00:40:21.230307
2845 00:40:21.230361 Set Vref, RX VrefLevel [Byte0]: 58
2846 00:40:21.230415 [Byte1]: 58
2847 00:40:21.230469
2848 00:40:21.230523 Set Vref, RX VrefLevel [Byte0]: 59
2849 00:40:21.230577 [Byte1]: 59
2850 00:40:21.230630
2851 00:40:21.230684 Set Vref, RX VrefLevel [Byte0]: 60
2852 00:40:21.230738 [Byte1]: 60
2853 00:40:21.230818
2854 00:40:21.230885 Set Vref, RX VrefLevel [Byte0]: 61
2855 00:40:21.230939 [Byte1]: 61
2856 00:40:21.230992
2857 00:40:21.231046 Set Vref, RX VrefLevel [Byte0]: 62
2858 00:40:21.231100 [Byte1]: 62
2859 00:40:21.231168
2860 00:40:21.231223 Set Vref, RX VrefLevel [Byte0]: 63
2861 00:40:21.231278 [Byte1]: 63
2862 00:40:21.231348
2863 00:40:21.231402 Set Vref, RX VrefLevel [Byte0]: 64
2864 00:40:21.231456 [Byte1]: 64
2865 00:40:21.231510
2866 00:40:21.231563 Set Vref, RX VrefLevel [Byte0]: 65
2867 00:40:21.231617 [Byte1]: 65
2868 00:40:21.231671
2869 00:40:21.231724 Set Vref, RX VrefLevel [Byte0]: 66
2870 00:40:21.231779 [Byte1]: 66
2871 00:40:21.231833
2872 00:40:21.231885 Set Vref, RX VrefLevel [Byte0]: 67
2873 00:40:21.231940 [Byte1]: 67
2874 00:40:21.231994
2875 00:40:21.232047 Set Vref, RX VrefLevel [Byte0]: 68
2876 00:40:21.232101 [Byte1]: 68
2877 00:40:21.232155
2878 00:40:21.232208 Set Vref, RX VrefLevel [Byte0]: 69
2879 00:40:21.232262 [Byte1]: 69
2880 00:40:21.232316
2881 00:40:21.232370 Final RX Vref Byte 0 = 58 to rank0
2882 00:40:21.232425 Final RX Vref Byte 1 = 49 to rank0
2883 00:40:21.232479 Final RX Vref Byte 0 = 58 to rank1
2884 00:40:21.232534 Final RX Vref Byte 1 = 49 to rank1==
2885 00:40:21.232631 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 00:40:21.232686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 00:40:21.232741 ==
2888 00:40:21.232795 DQS Delay:
2889 00:40:21.232848 DQS0 = 0, DQS1 = 0
2890 00:40:21.232903 DQM Delay:
2891 00:40:21.232957 DQM0 = 122, DQM1 = 108
2892 00:40:21.233011 DQ Delay:
2893 00:40:21.233066 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2894 00:40:21.233121 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2895 00:40:21.233176 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2896 00:40:21.233230 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =116
2897 00:40:21.233284
2898 00:40:21.233338
2899 00:40:21.233392 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2900 00:40:21.233448 CH0 RK0: MR19=404, MR18=D0A
2901 00:40:21.233503 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2902 00:40:21.233557
2903 00:40:21.233612 ----->DramcWriteLeveling(PI) begin...
2904 00:40:21.233667 ==
2905 00:40:21.233721 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 00:40:21.233779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 00:40:21.233903 ==
2908 00:40:21.233957 Write leveling (Byte 0): 35 => 35
2909 00:40:21.234011 Write leveling (Byte 1): 30 => 30
2910 00:40:21.234065 DramcWriteLeveling(PI) end<-----
2911 00:40:21.234119
2912 00:40:21.234172 ==
2913 00:40:21.234255 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 00:40:21.234310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 00:40:21.234364 ==
2916 00:40:21.234418 [Gating] SW mode calibration
2917 00:40:21.234472 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 00:40:21.234527 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 00:40:21.234581 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 00:40:21.234639 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 00:40:21.234694 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 00:40:21.234749 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 00:40:21.234804 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 00:40:21.234858 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 00:40:21.234912 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 00:40:21.234966 0 15 28 | B1->B0 | 2f2f 2c2c | 0 1 | (1 0) (1 0)
2927 00:40:21.235020 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 00:40:21.235074 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 00:40:21.235180 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 00:40:21.235236 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 00:40:21.235292 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 00:40:21.235351 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 00:40:21.235406 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2934 00:40:21.235461 1 0 28 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
2935 00:40:21.235516 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 00:40:21.235570 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 00:40:21.235624 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 00:40:21.235678 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 00:40:21.235732 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 00:40:21.235787 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 00:40:21.235840 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 00:40:21.235894 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2943 00:40:21.235948 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2944 00:40:21.236002 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 00:40:21.236056 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:40:21.236308 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:40:21.236373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:40:21.236436 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:40:21.236521 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:40:21.236627 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:40:21.236683 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:40:21.236738 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:40:21.236792 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:40:21.236846 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:40:21.236900 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:40:21.236955 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:40:21.237009 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2958 00:40:21.237063 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2959 00:40:21.237141 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2960 00:40:21.237198 Total UI for P1: 0, mck2ui 16
2961 00:40:21.237271 best dqsien dly found for B1: ( 1, 3, 28)
2962 00:40:21.237359 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 00:40:21.237432 Total UI for P1: 0, mck2ui 16
2964 00:40:21.237522 best dqsien dly found for B0: ( 1, 3, 28)
2965 00:40:21.237594 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2966 00:40:21.237649 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2967 00:40:21.237703
2968 00:40:21.237757 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2969 00:40:21.237843 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2970 00:40:21.237897 [Gating] SW calibration Done
2971 00:40:21.237951 ==
2972 00:40:21.238005 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 00:40:21.238059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 00:40:21.238146 ==
2975 00:40:21.238232 RX Vref Scan: 0
2976 00:40:21.238304
2977 00:40:21.238359 RX Vref 0 -> 0, step: 1
2978 00:40:21.238415
2979 00:40:21.238469 RX Delay -40 -> 252, step: 8
2980 00:40:21.238540 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2981 00:40:21.238595 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2982 00:40:21.238666 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2983 00:40:21.238735 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2984 00:40:21.238789 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2985 00:40:21.238843 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2986 00:40:21.238971 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2987 00:40:21.239116 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2988 00:40:21.239243 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2989 00:40:21.239301 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2990 00:40:21.239357 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2991 00:40:21.239411 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2992 00:40:21.239504 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2993 00:40:21.239559 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2994 00:40:21.239613 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2995 00:40:21.239699 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2996 00:40:21.239753 ==
2997 00:40:21.239807 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 00:40:21.239862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 00:40:21.239946 ==
3000 00:40:21.240001 DQS Delay:
3001 00:40:21.240054 DQS0 = 0, DQS1 = 0
3002 00:40:21.240108 DQM Delay:
3003 00:40:21.240177 DQM0 = 119, DQM1 = 107
3004 00:40:21.371532 DQ Delay:
3005 00:40:21.371679 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3006 00:40:21.371747 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =123
3007 00:40:21.371809 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
3008 00:40:21.371868 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3009 00:40:21.371927
3010 00:40:21.371984
3011 00:40:21.372039 ==
3012 00:40:21.372096 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 00:40:21.372151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 00:40:21.372208 ==
3015 00:40:21.372262
3016 00:40:21.372316
3017 00:40:21.372370 TX Vref Scan disable
3018 00:40:21.372425 == TX Byte 0 ==
3019 00:40:21.372480 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3020 00:40:21.372536 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3021 00:40:21.372629 == TX Byte 1 ==
3022 00:40:21.372684 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3023 00:40:21.372738 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3024 00:40:21.372793 ==
3025 00:40:21.372847 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 00:40:21.372901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 00:40:21.372956 ==
3028 00:40:21.373010 TX Vref=22, minBit 1, minWin=24, winSum=413
3029 00:40:21.373065 TX Vref=24, minBit 0, minWin=25, winSum=420
3030 00:40:21.373121 TX Vref=26, minBit 1, minWin=24, winSum=424
3031 00:40:21.373176 TX Vref=28, minBit 1, minWin=25, winSum=423
3032 00:40:21.373230 TX Vref=30, minBit 1, minWin=25, winSum=426
3033 00:40:21.373285 TX Vref=32, minBit 3, minWin=25, winSum=424
3034 00:40:21.373340 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 30
3035 00:40:21.373395
3036 00:40:21.373449 Final TX Range 1 Vref 30
3037 00:40:21.373503
3038 00:40:21.373556 ==
3039 00:40:21.373611 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 00:40:21.373665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 00:40:21.373719 ==
3042 00:40:21.373773
3043 00:40:21.373827
3044 00:40:21.373881 TX Vref Scan disable
3045 00:40:21.373935 == TX Byte 0 ==
3046 00:40:21.373989 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3047 00:40:21.374043 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3048 00:40:21.374097 == TX Byte 1 ==
3049 00:40:21.374151 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3050 00:40:21.374205 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3051 00:40:21.374259
3052 00:40:21.374348 [DATLAT]
3053 00:40:21.374402 Freq=1200, CH0 RK1
3054 00:40:21.374457
3055 00:40:21.374510 DATLAT Default: 0xd
3056 00:40:21.374564 0, 0xFFFF, sum = 0
3057 00:40:21.374620 1, 0xFFFF, sum = 0
3058 00:40:21.374675 2, 0xFFFF, sum = 0
3059 00:40:21.374731 3, 0xFFFF, sum = 0
3060 00:40:21.374786 4, 0xFFFF, sum = 0
3061 00:40:21.374842 5, 0xFFFF, sum = 0
3062 00:40:21.374897 6, 0xFFFF, sum = 0
3063 00:40:21.374951 7, 0xFFFF, sum = 0
3064 00:40:21.375006 8, 0xFFFF, sum = 0
3065 00:40:21.375061 9, 0xFFFF, sum = 0
3066 00:40:21.375116 10, 0xFFFF, sum = 0
3067 00:40:21.375170 11, 0xFFFF, sum = 0
3068 00:40:21.375225 12, 0x0, sum = 1
3069 00:40:21.375280 13, 0x0, sum = 2
3070 00:40:21.375335 14, 0x0, sum = 3
3071 00:40:21.375389 15, 0x0, sum = 4
3072 00:40:21.375444 best_step = 13
3073 00:40:21.375497
3074 00:40:21.375551 ==
3075 00:40:21.375604 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 00:40:21.375658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 00:40:21.375712 ==
3078 00:40:21.375766 RX Vref Scan: 0
3079 00:40:21.375820
3080 00:40:21.375874 RX Vref 0 -> 0, step: 1
3081 00:40:21.375928
3082 00:40:21.375981 RX Delay -21 -> 252, step: 4
3083 00:40:21.376249 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3084 00:40:21.376368 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3085 00:40:21.376439 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3086 00:40:21.376493 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3087 00:40:21.376566 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3088 00:40:21.376637 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3089 00:40:21.376691 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3090 00:40:21.376745 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3091 00:40:21.376799 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3092 00:40:21.376854 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3093 00:40:21.376908 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3094 00:40:21.376962 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3095 00:40:21.377015 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3096 00:40:21.377069 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3097 00:40:21.377122 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3098 00:40:21.377177 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3099 00:40:21.377230 ==
3100 00:40:21.377284 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 00:40:21.377373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 00:40:21.377428 ==
3103 00:40:21.377483 DQS Delay:
3104 00:40:21.377537 DQS0 = 0, DQS1 = 0
3105 00:40:21.377592 DQM Delay:
3106 00:40:21.377645 DQM0 = 119, DQM1 = 107
3107 00:40:21.377701 DQ Delay:
3108 00:40:21.377756 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3109 00:40:21.377812 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3110 00:40:21.377869 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3111 00:40:21.377925 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3112 00:40:21.377981
3113 00:40:21.378036
3114 00:40:21.378091 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 403 ps
3115 00:40:21.378148 CH0 RK1: MR19=403, MR18=10F6
3116 00:40:21.378238 CH0_RK1: MR19=0x403, MR18=0x10F6, DQSOSC=403, MR23=63, INC=40, DEC=26
3117 00:40:21.378294 [RxdqsGatingPostProcess] freq 1200
3118 00:40:21.378350 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 00:40:21.378406 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 00:40:21.378462 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 00:40:21.378517 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 00:40:21.378573 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 00:40:21.378629 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 00:40:21.378689 best DQS1 dly(2T, 0.5T) = (0, 11)
3125 00:40:21.378744 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 00:40:21.378800 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3127 00:40:21.378856 Pre-setting of DQS Precalculation
3128 00:40:21.378912 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 00:40:21.378968 ==
3130 00:40:21.379024 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 00:40:21.379080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 00:40:21.379136 ==
3133 00:40:21.379192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 00:40:21.379249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3135 00:40:21.379306 [CA 0] Center 37 (7~68) winsize 62
3136 00:40:21.379362 [CA 1] Center 37 (7~68) winsize 62
3137 00:40:21.379417 [CA 2] Center 35 (5~65) winsize 61
3138 00:40:21.379472 [CA 3] Center 34 (4~65) winsize 62
3139 00:40:21.379528 [CA 4] Center 34 (4~65) winsize 62
3140 00:40:21.379584 [CA 5] Center 33 (3~64) winsize 62
3141 00:40:21.379639
3142 00:40:21.379694 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 00:40:21.379750
3144 00:40:21.379805 [CATrainingPosCal] consider 1 rank data
3145 00:40:21.379861 u2DelayCellTimex100 = 270/100 ps
3146 00:40:21.379916 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 00:40:21.379972 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 00:40:21.380028 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3149 00:40:21.380083 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3150 00:40:21.380139 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3151 00:40:21.380194 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3152 00:40:21.380249
3153 00:40:21.380304 CA PerBit enable=1, Macro0, CA PI delay=33
3154 00:40:21.380360
3155 00:40:21.380416 [CBTSetCACLKResult] CA Dly = 33
3156 00:40:21.380472 CS Dly: 5 (0~36)
3157 00:40:21.380527 ==
3158 00:40:21.380621 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 00:40:21.380709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 00:40:21.380765 ==
3161 00:40:21.380820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 00:40:21.380903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3163 00:40:21.380962 [CA 0] Center 38 (8~68) winsize 61
3164 00:40:21.381019 [CA 1] Center 38 (7~69) winsize 63
3165 00:40:21.381075 [CA 2] Center 35 (5~66) winsize 62
3166 00:40:21.381130 [CA 3] Center 35 (5~65) winsize 61
3167 00:40:21.381218 [CA 4] Center 35 (5~65) winsize 61
3168 00:40:21.381273 [CA 5] Center 33 (3~64) winsize 62
3169 00:40:21.381329
3170 00:40:21.381384 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3171 00:40:21.381440
3172 00:40:21.381496 [CATrainingPosCal] consider 2 rank data
3173 00:40:21.381553 u2DelayCellTimex100 = 270/100 ps
3174 00:40:21.381609 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3175 00:40:21.381665 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3176 00:40:21.381721 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3177 00:40:21.381777 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3178 00:40:21.381832 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3179 00:40:21.381888 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 00:40:21.381944
3181 00:40:21.381999 CA PerBit enable=1, Macro0, CA PI delay=33
3182 00:40:21.382055
3183 00:40:21.382110 [CBTSetCACLKResult] CA Dly = 33
3184 00:40:21.382166 CS Dly: 6 (0~39)
3185 00:40:21.382251
3186 00:40:21.382308 ----->DramcWriteLeveling(PI) begin...
3187 00:40:21.382365 ==
3188 00:40:21.382420 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 00:40:21.382476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 00:40:21.382533 ==
3191 00:40:21.382588 Write leveling (Byte 0): 25 => 25
3192 00:40:21.382645 Write leveling (Byte 1): 28 => 28
3193 00:40:21.382700 DramcWriteLeveling(PI) end<-----
3194 00:40:21.382756
3195 00:40:21.382811 ==
3196 00:40:21.382866 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 00:40:21.382922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 00:40:21.382978 ==
3199 00:40:21.383034 [Gating] SW mode calibration
3200 00:40:21.383090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 00:40:21.383147 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 00:40:21.383401 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 00:40:21.383499 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 00:40:21.383557 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 00:40:21.383613 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 00:40:21.383669 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 00:40:21.383725 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 00:40:21.383780 0 15 24 | B1->B0 | 3030 2626 | 0 0 | (0 0) (1 0)
3209 00:40:21.383836 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3210 00:40:21.383892 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 00:40:21.383948 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 00:40:21.384004 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 00:40:21.384059 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 00:40:21.384115 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 00:40:21.384171 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3216 00:40:21.384227 1 0 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3217 00:40:21.384282 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 00:40:21.384338 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 00:40:21.384394 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 00:40:21.384450 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 00:40:21.384506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 00:40:21.384584 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 00:40:21.384655 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3224 00:40:21.384710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3225 00:40:21.384766 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3226 00:40:21.384822 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 00:40:21.384877 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 00:40:21.384933 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:40:21.384989 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:40:21.385044 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:40:21.385099 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:40:21.385155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:40:21.385211 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:40:21.385267 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:40:21.385323 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:40:21.385378 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:40:21.385433 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:40:21.385489 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:40:21.385544 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3240 00:40:21.385600 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3241 00:40:21.385655 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3242 00:40:21.385711 Total UI for P1: 0, mck2ui 16
3243 00:40:21.385767 best dqsien dly found for B0: ( 1, 3, 22)
3244 00:40:21.385824 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 00:40:21.385880 Total UI for P1: 0, mck2ui 16
3246 00:40:21.385936 best dqsien dly found for B1: ( 1, 3, 26)
3247 00:40:21.385992 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3248 00:40:21.386048 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3249 00:40:21.386103
3250 00:40:21.386159 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3251 00:40:21.386215 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3252 00:40:21.386271 [Gating] SW calibration Done
3253 00:40:21.386326 ==
3254 00:40:21.386383 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 00:40:21.386438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 00:40:21.386494 ==
3257 00:40:21.386588 RX Vref Scan: 0
3258 00:40:21.386644
3259 00:40:21.386699 RX Vref 0 -> 0, step: 1
3260 00:40:21.386755
3261 00:40:21.386811 RX Delay -40 -> 252, step: 8
3262 00:40:21.386867 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3263 00:40:21.386923 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3264 00:40:21.386979 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3265 00:40:21.387035 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3266 00:40:21.387091 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3267 00:40:21.387146 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3268 00:40:21.387202 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3269 00:40:21.387257 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3270 00:40:21.387313 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3271 00:40:21.387369 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3272 00:40:21.387424 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3273 00:40:21.387480 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3274 00:40:21.387536 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3275 00:40:21.387591 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3276 00:40:21.387647 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3277 00:40:21.387702 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3278 00:40:21.387757 ==
3279 00:40:21.387812 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 00:40:21.387868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 00:40:21.387925 ==
3282 00:40:21.387980 DQS Delay:
3283 00:40:21.388036 DQS0 = 0, DQS1 = 0
3284 00:40:21.388091 DQM Delay:
3285 00:40:21.388147 DQM0 = 119, DQM1 = 112
3286 00:40:21.388202 DQ Delay:
3287 00:40:21.388257 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3288 00:40:21.388313 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3289 00:40:21.388368 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3290 00:40:21.388425 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3291 00:40:21.388480
3292 00:40:21.388536
3293 00:40:21.388625 ==
3294 00:40:21.388681 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 00:40:21.388737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 00:40:21.388793 ==
3297 00:40:21.388848
3298 00:40:21.388904
3299 00:40:21.388959 TX Vref Scan disable
3300 00:40:21.389015 == TX Byte 0 ==
3301 00:40:21.389070 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3302 00:40:21.389126 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3303 00:40:21.389182 == TX Byte 1 ==
3304 00:40:21.389238 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3305 00:40:21.389294 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3306 00:40:21.389349 ==
3307 00:40:21.389405 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 00:40:21.389655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 00:40:21.389774 ==
3310 00:40:21.389847 TX Vref=22, minBit 10, minWin=24, winSum=407
3311 00:40:21.389904 TX Vref=24, minBit 11, minWin=24, winSum=409
3312 00:40:21.389960 TX Vref=26, minBit 8, minWin=25, winSum=412
3313 00:40:21.390016 TX Vref=28, minBit 9, minWin=25, winSum=421
3314 00:40:21.390072 TX Vref=30, minBit 11, minWin=25, winSum=424
3315 00:40:21.390128 TX Vref=32, minBit 11, minWin=25, winSum=423
3316 00:40:21.390185 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 30
3317 00:40:21.390241
3318 00:40:21.390297 Final TX Range 1 Vref 30
3319 00:40:21.390353
3320 00:40:21.390408 ==
3321 00:40:21.390496 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 00:40:21.390552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 00:40:21.390608 ==
3324 00:40:21.390664
3325 00:40:21.390719
3326 00:40:21.390790 TX Vref Scan disable
3327 00:40:21.390876 == TX Byte 0 ==
3328 00:40:21.390946 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3329 00:40:21.391002 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3330 00:40:21.391058 == TX Byte 1 ==
3331 00:40:21.391113 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3332 00:40:21.391169 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3333 00:40:21.391224
3334 00:40:21.391280 [DATLAT]
3335 00:40:21.391335 Freq=1200, CH1 RK0
3336 00:40:21.391391
3337 00:40:21.391446 DATLAT Default: 0xd
3338 00:40:21.391502 0, 0xFFFF, sum = 0
3339 00:40:21.391558 1, 0xFFFF, sum = 0
3340 00:40:21.391616 2, 0xFFFF, sum = 0
3341 00:40:21.391672 3, 0xFFFF, sum = 0
3342 00:40:21.391730 4, 0xFFFF, sum = 0
3343 00:40:21.391787 5, 0xFFFF, sum = 0
3344 00:40:21.391844 6, 0xFFFF, sum = 0
3345 00:40:21.391901 7, 0xFFFF, sum = 0
3346 00:40:21.391958 8, 0xFFFF, sum = 0
3347 00:40:21.392014 9, 0xFFFF, sum = 0
3348 00:40:21.392071 10, 0xFFFF, sum = 0
3349 00:40:21.392127 11, 0xFFFF, sum = 0
3350 00:40:21.392184 12, 0x0, sum = 1
3351 00:40:21.392240 13, 0x0, sum = 2
3352 00:40:21.392297 14, 0x0, sum = 3
3353 00:40:21.392354 15, 0x0, sum = 4
3354 00:40:21.392410 best_step = 13
3355 00:40:21.392466
3356 00:40:21.392521 ==
3357 00:40:21.392613 Dram Type= 6, Freq= 0, CH_1, rank 0
3358 00:40:21.392669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3359 00:40:21.392725 ==
3360 00:40:21.392781 RX Vref Scan: 1
3361 00:40:21.392836
3362 00:40:21.392890 Set Vref Range= 32 -> 127
3363 00:40:21.392945
3364 00:40:21.392999 RX Vref 32 -> 127, step: 1
3365 00:40:21.393053
3366 00:40:21.393106 RX Delay -13 -> 252, step: 4
3367 00:40:21.393160
3368 00:40:21.393214 Set Vref, RX VrefLevel [Byte0]: 32
3369 00:40:21.393268 [Byte1]: 32
3370 00:40:21.393359
3371 00:40:21.393412 Set Vref, RX VrefLevel [Byte0]: 33
3372 00:40:21.393466 [Byte1]: 33
3373 00:40:21.393520
3374 00:40:21.393574 Set Vref, RX VrefLevel [Byte0]: 34
3375 00:40:21.393627 [Byte1]: 34
3376 00:40:21.393681
3377 00:40:21.393734 Set Vref, RX VrefLevel [Byte0]: 35
3378 00:40:21.393788 [Byte1]: 35
3379 00:40:21.393842
3380 00:40:21.393896 Set Vref, RX VrefLevel [Byte0]: 36
3381 00:40:21.393950 [Byte1]: 36
3382 00:40:21.394003
3383 00:40:21.394087 Set Vref, RX VrefLevel [Byte0]: 37
3384 00:40:21.394173 [Byte1]: 37
3385 00:40:21.394226
3386 00:40:21.394280 Set Vref, RX VrefLevel [Byte0]: 38
3387 00:40:21.394334 [Byte1]: 38
3388 00:40:21.394387
3389 00:40:21.394441 Set Vref, RX VrefLevel [Byte0]: 39
3390 00:40:21.394496 [Byte1]: 39
3391 00:40:21.394580
3392 00:40:21.394633 Set Vref, RX VrefLevel [Byte0]: 40
3393 00:40:21.394687 [Byte1]: 40
3394 00:40:21.394740
3395 00:40:21.394794 Set Vref, RX VrefLevel [Byte0]: 41
3396 00:40:21.394848 [Byte1]: 41
3397 00:40:21.394902
3398 00:40:21.394956 Set Vref, RX VrefLevel [Byte0]: 42
3399 00:40:21.395010 [Byte1]: 42
3400 00:40:21.395065
3401 00:40:21.395118 Set Vref, RX VrefLevel [Byte0]: 43
3402 00:40:21.395173 [Byte1]: 43
3403 00:40:21.395226
3404 00:40:21.395282 Set Vref, RX VrefLevel [Byte0]: 44
3405 00:40:21.395336 [Byte1]: 44
3406 00:40:21.395390
3407 00:40:21.395443 Set Vref, RX VrefLevel [Byte0]: 45
3408 00:40:21.395497 [Byte1]: 45
3409 00:40:21.395550
3410 00:40:21.395604 Set Vref, RX VrefLevel [Byte0]: 46
3411 00:40:21.395658 [Byte1]: 46
3412 00:40:21.395711
3413 00:40:21.395764 Set Vref, RX VrefLevel [Byte0]: 47
3414 00:40:21.395818 [Byte1]: 47
3415 00:40:21.395872
3416 00:40:21.395925 Set Vref, RX VrefLevel [Byte0]: 48
3417 00:40:21.395979 [Byte1]: 48
3418 00:40:21.396032
3419 00:40:21.396086 Set Vref, RX VrefLevel [Byte0]: 49
3420 00:40:21.396140 [Byte1]: 49
3421 00:40:21.396194
3422 00:40:21.396248 Set Vref, RX VrefLevel [Byte0]: 50
3423 00:40:21.396302 [Byte1]: 50
3424 00:40:21.396356
3425 00:40:21.396409 Set Vref, RX VrefLevel [Byte0]: 51
3426 00:40:21.396463 [Byte1]: 51
3427 00:40:21.396517
3428 00:40:21.396613 Set Vref, RX VrefLevel [Byte0]: 52
3429 00:40:21.396667 [Byte1]: 52
3430 00:40:21.396721
3431 00:40:21.396775 Set Vref, RX VrefLevel [Byte0]: 53
3432 00:40:21.396829 [Byte1]: 53
3433 00:40:21.396883
3434 00:40:21.396936 Set Vref, RX VrefLevel [Byte0]: 54
3435 00:40:21.396990 [Byte1]: 54
3436 00:40:21.397044
3437 00:40:21.397098 Set Vref, RX VrefLevel [Byte0]: 55
3438 00:40:21.397151 [Byte1]: 55
3439 00:40:21.397205
3440 00:40:21.397258 Set Vref, RX VrefLevel [Byte0]: 56
3441 00:40:21.397312 [Byte1]: 56
3442 00:40:21.397366
3443 00:40:21.397419 Set Vref, RX VrefLevel [Byte0]: 57
3444 00:40:21.397473 [Byte1]: 57
3445 00:40:21.397559
3446 00:40:21.397612 Set Vref, RX VrefLevel [Byte0]: 58
3447 00:40:21.397667 [Byte1]: 58
3448 00:40:21.397721
3449 00:40:21.397774 Set Vref, RX VrefLevel [Byte0]: 59
3450 00:40:21.397829 [Byte1]: 59
3451 00:40:21.397882
3452 00:40:21.397935 Set Vref, RX VrefLevel [Byte0]: 60
3453 00:40:21.397989 [Byte1]: 60
3454 00:40:21.398043
3455 00:40:21.398097 Set Vref, RX VrefLevel [Byte0]: 61
3456 00:40:21.398150 [Byte1]: 61
3457 00:40:21.398204
3458 00:40:21.398257 Set Vref, RX VrefLevel [Byte0]: 62
3459 00:40:21.398311 [Byte1]: 62
3460 00:40:21.398365
3461 00:40:21.398419 Set Vref, RX VrefLevel [Byte0]: 63
3462 00:40:21.398472 [Byte1]: 63
3463 00:40:21.398526
3464 00:40:21.398580 Set Vref, RX VrefLevel [Byte0]: 64
3465 00:40:21.398634 [Byte1]: 64
3466 00:40:21.398688
3467 00:40:21.398742 Set Vref, RX VrefLevel [Byte0]: 65
3468 00:40:21.398795 [Byte1]: 65
3469 00:40:21.398848
3470 00:40:21.398901 Set Vref, RX VrefLevel [Byte0]: 66
3471 00:40:21.398955 [Byte1]: 66
3472 00:40:21.399008
3473 00:40:21.399061 Final RX Vref Byte 0 = 50 to rank0
3474 00:40:21.399116 Final RX Vref Byte 1 = 52 to rank0
3475 00:40:21.399381 Final RX Vref Byte 0 = 50 to rank1
3476 00:40:21.399480 Final RX Vref Byte 1 = 52 to rank1==
3477 00:40:21.399536 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 00:40:21.399590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 00:40:21.399645 ==
3480 00:40:21.399699 DQS Delay:
3481 00:40:21.399753 DQS0 = 0, DQS1 = 0
3482 00:40:21.399807 DQM Delay:
3483 00:40:21.399860 DQM0 = 118, DQM1 = 111
3484 00:40:21.399914 DQ Delay:
3485 00:40:21.399968 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3486 00:40:21.400022 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3487 00:40:21.400076 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3488 00:40:21.400130 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =116
3489 00:40:21.400186
3490 00:40:21.400240
3491 00:40:21.400293 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3492 00:40:21.400348 CH1 RK0: MR19=404, MR18=518
3493 00:40:21.400402 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3494 00:40:21.400475
3495 00:40:21.400531 ----->DramcWriteLeveling(PI) begin...
3496 00:40:21.400607 ==
3497 00:40:21.400661 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 00:40:21.400715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 00:40:21.400769 ==
3500 00:40:21.400823 Write leveling (Byte 0): 26 => 26
3501 00:40:21.400877 Write leveling (Byte 1): 29 => 29
3502 00:40:21.400930 DramcWriteLeveling(PI) end<-----
3503 00:40:21.400984
3504 00:40:21.401037 ==
3505 00:40:21.401092 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 00:40:21.401170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 00:40:21.401239 ==
3508 00:40:21.401293 [Gating] SW mode calibration
3509 00:40:21.401348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 00:40:21.401403 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 00:40:21.401457 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 00:40:21.401512 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 00:40:21.401566 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 00:40:21.401620 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 00:40:21.401675 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 00:40:21.401729 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 00:40:21.401783 0 15 24 | B1->B0 | 2828 3333 | 0 0 | (1 0) (1 0)
3518 00:40:21.401837 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3519 00:40:21.401891 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 00:40:21.401945 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 00:40:21.401999 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 00:40:21.402052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 00:40:21.402107 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 00:40:21.402160 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 00:40:21.402214 1 0 24 | B1->B0 | 3d3d 2d2d | 0 0 | (0 0) (0 0)
3526 00:40:21.402269 1 0 28 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
3527 00:40:21.402322 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 00:40:21.402376 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 00:40:21.402430 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 00:40:21.402484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 00:40:21.402538 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 00:40:21.402592 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 00:40:21.402646 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3534 00:40:21.402700 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3535 00:40:21.402753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 00:40:21.402807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 00:40:21.402861 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 00:40:21.402914 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 00:40:21.402968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 00:40:21.403022 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:40:21.403076 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:40:21.403129 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:40:21.403231 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:40:21.403287 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 00:40:21.403341 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 00:40:21.403395 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 00:40:21.403449 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 00:40:21.403503 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 00:40:21.403556 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 00:40:21.403611 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3551 00:40:21.403665 Total UI for P1: 0, mck2ui 16
3552 00:40:21.403720 best dqsien dly found for B0: ( 1, 3, 24)
3553 00:40:21.403773 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 00:40:21.403827 Total UI for P1: 0, mck2ui 16
3555 00:40:21.403882 best dqsien dly found for B1: ( 1, 3, 26)
3556 00:40:21.403936 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3557 00:40:21.403990 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3558 00:40:21.404043
3559 00:40:21.404097 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 00:40:21.404152 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3561 00:40:21.404206 [Gating] SW calibration Done
3562 00:40:21.404260 ==
3563 00:40:21.404314 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 00:40:21.404380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 00:40:21.404437 ==
3566 00:40:21.404491 RX Vref Scan: 0
3567 00:40:21.404545
3568 00:40:21.404635 RX Vref 0 -> 0, step: 1
3569 00:40:21.404689
3570 00:40:21.404743 RX Delay -40 -> 252, step: 8
3571 00:40:21.404797 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3572 00:40:21.404851 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3573 00:40:21.404905 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3574 00:40:21.404960 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3575 00:40:21.405014 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3576 00:40:21.405068 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3577 00:40:21.405122 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3578 00:40:21.405176 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3579 00:40:21.405427 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3580 00:40:21.405489 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3581 00:40:21.405544 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3582 00:40:21.405599 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3583 00:40:21.405653 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3584 00:40:21.405707 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3585 00:40:21.405762 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3586 00:40:21.405816 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3587 00:40:21.405870 ==
3588 00:40:21.405924 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 00:40:21.405977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 00:40:21.406032 ==
3591 00:40:21.406085 DQS Delay:
3592 00:40:21.406139 DQS0 = 0, DQS1 = 0
3593 00:40:21.406193 DQM Delay:
3594 00:40:21.406248 DQM0 = 119, DQM1 = 112
3595 00:40:21.406301 DQ Delay:
3596 00:40:21.406355 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3597 00:40:21.406409 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3598 00:40:21.406463 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3599 00:40:21.406518 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3600 00:40:21.406572
3601 00:40:21.406625
3602 00:40:21.406679 ==
3603 00:40:21.406733 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 00:40:21.406787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 00:40:21.406841 ==
3606 00:40:21.406894
3607 00:40:21.406948
3608 00:40:21.407001 TX Vref Scan disable
3609 00:40:21.407055 == TX Byte 0 ==
3610 00:40:21.407109 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3611 00:40:21.407187 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3612 00:40:21.407284 == TX Byte 1 ==
3613 00:40:21.407370 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3614 00:40:21.407455 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3615 00:40:21.407509 ==
3616 00:40:21.407563 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 00:40:21.407617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 00:40:21.407671 ==
3619 00:40:21.407725 TX Vref=22, minBit 8, minWin=25, winSum=417
3620 00:40:21.407779 TX Vref=24, minBit 1, minWin=25, winSum=418
3621 00:40:21.407833 TX Vref=26, minBit 1, minWin=25, winSum=426
3622 00:40:21.407887 TX Vref=28, minBit 8, minWin=26, winSum=427
3623 00:40:21.407941 TX Vref=30, minBit 10, minWin=25, winSum=426
3624 00:40:21.407996 TX Vref=32, minBit 1, minWin=26, winSum=429
3625 00:40:21.408049 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 32
3626 00:40:21.408103
3627 00:40:21.408157 Final TX Range 1 Vref 32
3628 00:40:21.408211
3629 00:40:21.408265 ==
3630 00:40:21.408319 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 00:40:21.408373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 00:40:21.408427 ==
3633 00:40:21.408481
3634 00:40:21.408534
3635 00:40:21.408624 TX Vref Scan disable
3636 00:40:21.408679 == TX Byte 0 ==
3637 00:40:21.408732 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 00:40:21.408787 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 00:40:21.408841 == TX Byte 1 ==
3640 00:40:21.408895 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3641 00:40:21.408950 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3642 00:40:21.409004
3643 00:40:21.409057 [DATLAT]
3644 00:40:21.409111 Freq=1200, CH1 RK1
3645 00:40:21.409165
3646 00:40:21.409218 DATLAT Default: 0xd
3647 00:40:21.409272 0, 0xFFFF, sum = 0
3648 00:40:21.409328 1, 0xFFFF, sum = 0
3649 00:40:21.409384 2, 0xFFFF, sum = 0
3650 00:40:21.409439 3, 0xFFFF, sum = 0
3651 00:40:21.409493 4, 0xFFFF, sum = 0
3652 00:40:21.409548 5, 0xFFFF, sum = 0
3653 00:40:21.409603 6, 0xFFFF, sum = 0
3654 00:40:21.409658 7, 0xFFFF, sum = 0
3655 00:40:21.409712 8, 0xFFFF, sum = 0
3656 00:40:21.409767 9, 0xFFFF, sum = 0
3657 00:40:21.409821 10, 0xFFFF, sum = 0
3658 00:40:21.409876 11, 0xFFFF, sum = 0
3659 00:40:21.409931 12, 0x0, sum = 1
3660 00:40:21.409986 13, 0x0, sum = 2
3661 00:40:21.410041 14, 0x0, sum = 3
3662 00:40:21.410096 15, 0x0, sum = 4
3663 00:40:21.410150 best_step = 13
3664 00:40:21.410204
3665 00:40:21.410258 ==
3666 00:40:21.410312 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 00:40:21.410366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 00:40:21.410421 ==
3669 00:40:21.410474 RX Vref Scan: 0
3670 00:40:21.410528
3671 00:40:21.410582 RX Vref 0 -> 0, step: 1
3672 00:40:21.410635
3673 00:40:21.410688 RX Delay -13 -> 252, step: 4
3674 00:40:21.410742 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3675 00:40:21.410795 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3676 00:40:21.410850 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3677 00:40:21.410903 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3678 00:40:21.410957 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3679 00:40:21.411012 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3680 00:40:21.411065 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3681 00:40:21.411119 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3682 00:40:21.411209 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3683 00:40:21.411301 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3684 00:40:21.411355 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3685 00:40:21.411455 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3686 00:40:21.411539 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3687 00:40:21.411608 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3688 00:40:21.411661 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3689 00:40:21.411715 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3690 00:40:21.411769 ==
3691 00:40:21.411823 Dram Type= 6, Freq= 0, CH_1, rank 1
3692 00:40:21.411877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3693 00:40:21.411931 ==
3694 00:40:21.411985 DQS Delay:
3695 00:40:21.412039 DQS0 = 0, DQS1 = 0
3696 00:40:21.412093 DQM Delay:
3697 00:40:21.412146 DQM0 = 119, DQM1 = 113
3698 00:40:21.412200 DQ Delay:
3699 00:40:21.412254 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3700 00:40:21.412309 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3701 00:40:21.412362 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3702 00:40:21.412416 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3703 00:40:21.412470
3704 00:40:21.412523
3705 00:40:21.412612 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3706 00:40:21.412668 CH1 RK1: MR19=403, MR18=DF2
3707 00:40:21.412722 CH1_RK1: MR19=0x403, MR18=0xDF2, DQSOSC=405, MR23=63, INC=39, DEC=26
3708 00:40:21.412777 [RxdqsGatingPostProcess] freq 1200
3709 00:40:21.412831 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3710 00:40:21.412885 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 00:40:21.412940 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 00:40:21.412994 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 00:40:21.413048 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 00:40:21.413101 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 00:40:21.413156 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 00:40:21.413209 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 00:40:21.413263 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 00:40:21.413508 Pre-setting of DQS Precalculation
3719 00:40:21.413569 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3720 00:40:21.413625 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3721 00:40:21.413681 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3722 00:40:21.413736
3723 00:40:21.413790
3724 00:40:21.413844 [Calibration Summary] 2400 Mbps
3725 00:40:21.413898 CH 0, Rank 0
3726 00:40:21.413952 SW Impedance : PASS
3727 00:40:21.414006 DUTY Scan : NO K
3728 00:40:21.414061 ZQ Calibration : PASS
3729 00:40:21.414115 Jitter Meter : NO K
3730 00:40:21.414188 CBT Training : PASS
3731 00:40:21.414245 Write leveling : PASS
3732 00:40:21.414300 RX DQS gating : PASS
3733 00:40:21.414354 RX DQ/DQS(RDDQC) : PASS
3734 00:40:21.414409 TX DQ/DQS : PASS
3735 00:40:21.414464 RX DATLAT : PASS
3736 00:40:21.414517 RX DQ/DQS(Engine): PASS
3737 00:40:21.414572 TX OE : NO K
3738 00:40:21.414626 All Pass.
3739 00:40:21.414680
3740 00:40:21.414734 CH 0, Rank 1
3741 00:40:21.414788 SW Impedance : PASS
3742 00:40:21.414841 DUTY Scan : NO K
3743 00:40:21.414895 ZQ Calibration : PASS
3744 00:40:21.414949 Jitter Meter : NO K
3745 00:40:21.415003 CBT Training : PASS
3746 00:40:21.415057 Write leveling : PASS
3747 00:40:21.415110 RX DQS gating : PASS
3748 00:40:21.415164 RX DQ/DQS(RDDQC) : PASS
3749 00:40:21.415255 TX DQ/DQS : PASS
3750 00:40:21.415310 RX DATLAT : PASS
3751 00:40:21.415363 RX DQ/DQS(Engine): PASS
3752 00:40:21.415417 TX OE : NO K
3753 00:40:21.415471 All Pass.
3754 00:40:21.415525
3755 00:40:21.415578 CH 1, Rank 0
3756 00:40:21.415632 SW Impedance : PASS
3757 00:40:21.415685 DUTY Scan : NO K
3758 00:40:21.415739 ZQ Calibration : PASS
3759 00:40:21.415792 Jitter Meter : NO K
3760 00:40:21.415846 CBT Training : PASS
3761 00:40:21.415900 Write leveling : PASS
3762 00:40:21.415954 RX DQS gating : PASS
3763 00:40:21.416008 RX DQ/DQS(RDDQC) : PASS
3764 00:40:21.416063 TX DQ/DQS : PASS
3765 00:40:21.416116 RX DATLAT : PASS
3766 00:40:21.416171 RX DQ/DQS(Engine): PASS
3767 00:40:21.416225 TX OE : NO K
3768 00:40:21.416278 All Pass.
3769 00:40:21.416332
3770 00:40:21.416386 CH 1, Rank 1
3771 00:40:21.416440 SW Impedance : PASS
3772 00:40:21.416494 DUTY Scan : NO K
3773 00:40:21.416600 ZQ Calibration : PASS
3774 00:40:21.416693 Jitter Meter : NO K
3775 00:40:21.416777 CBT Training : PASS
3776 00:40:21.416860 Write leveling : PASS
3777 00:40:21.416943 RX DQS gating : PASS
3778 00:40:21.417026 RX DQ/DQS(RDDQC) : PASS
3779 00:40:21.417108 TX DQ/DQS : PASS
3780 00:40:21.417230 RX DATLAT : PASS
3781 00:40:21.417313 RX DQ/DQS(Engine): PASS
3782 00:40:21.417396 TX OE : NO K
3783 00:40:21.417479 All Pass.
3784 00:40:21.417561
3785 00:40:21.417643 DramC Write-DBI off
3786 00:40:21.417726 PER_BANK_REFRESH: Hybrid Mode
3787 00:40:21.417809 TX_TRACKING: ON
3788 00:40:21.417894 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3789 00:40:21.417979 [FAST_K] Save calibration result to emmc
3790 00:40:21.418063 dramc_set_vcore_voltage set vcore to 650000
3791 00:40:21.418146 Read voltage for 600, 5
3792 00:40:21.418228 Vio18 = 0
3793 00:40:21.418310 Vcore = 650000
3794 00:40:21.418393 Vdram = 0
3795 00:40:21.418475 Vddq = 0
3796 00:40:21.418557 Vmddr = 0
3797 00:40:21.418640 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3798 00:40:21.418725 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3799 00:40:21.418808 MEM_TYPE=3, freq_sel=19
3800 00:40:21.418891 sv_algorithm_assistance_LP4_1600
3801 00:40:21.418975 ============ PULL DRAM RESETB DOWN ============
3802 00:40:21.419059 ========== PULL DRAM RESETB DOWN end =========
3803 00:40:21.419154 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3804 00:40:21.419214 ===================================
3805 00:40:21.419271 LPDDR4 DRAM CONFIGURATION
3806 00:40:21.419326 ===================================
3807 00:40:21.419381 EX_ROW_EN[0] = 0x0
3808 00:40:21.419472 EX_ROW_EN[1] = 0x0
3809 00:40:21.419526 LP4Y_EN = 0x0
3810 00:40:21.419580 WORK_FSP = 0x0
3811 00:40:21.419635 WL = 0x2
3812 00:40:21.419689 RL = 0x2
3813 00:40:21.419743 BL = 0x2
3814 00:40:21.419798 RPST = 0x0
3815 00:40:21.419851 RD_PRE = 0x0
3816 00:40:21.419905 WR_PRE = 0x1
3817 00:40:21.419959 WR_PST = 0x0
3818 00:40:21.420013 DBI_WR = 0x0
3819 00:40:21.420067 DBI_RD = 0x0
3820 00:40:21.420121 OTF = 0x1
3821 00:40:21.420175 ===================================
3822 00:40:21.420230 ===================================
3823 00:40:21.420284 ANA top config
3824 00:40:21.420338 ===================================
3825 00:40:21.420393 DLL_ASYNC_EN = 0
3826 00:40:21.420447 ALL_SLAVE_EN = 1
3827 00:40:21.420518 NEW_RANK_MODE = 1
3828 00:40:21.420607 DLL_IDLE_MODE = 1
3829 00:40:21.420691 LP45_APHY_COMB_EN = 1
3830 00:40:21.420774 TX_ODT_DIS = 1
3831 00:40:21.420857 NEW_8X_MODE = 1
3832 00:40:21.420940 ===================================
3833 00:40:21.421024 ===================================
3834 00:40:21.421107 data_rate = 1200
3835 00:40:21.421179 CKR = 1
3836 00:40:21.421236 DQ_P2S_RATIO = 8
3837 00:40:21.421290 ===================================
3838 00:40:21.421344 CA_P2S_RATIO = 8
3839 00:40:21.421398 DQ_CA_OPEN = 0
3840 00:40:21.421452 DQ_SEMI_OPEN = 0
3841 00:40:21.421507 CA_SEMI_OPEN = 0
3842 00:40:21.421560 CA_FULL_RATE = 0
3843 00:40:21.421614 DQ_CKDIV4_EN = 1
3844 00:40:21.421668 CA_CKDIV4_EN = 1
3845 00:40:21.421722 CA_PREDIV_EN = 0
3846 00:40:21.421778 PH8_DLY = 0
3847 00:40:21.421832 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3848 00:40:21.421885 DQ_AAMCK_DIV = 4
3849 00:40:21.421939 CA_AAMCK_DIV = 4
3850 00:40:21.421993 CA_ADMCK_DIV = 4
3851 00:40:21.422046 DQ_TRACK_CA_EN = 0
3852 00:40:21.422099 CA_PICK = 600
3853 00:40:21.422153 CA_MCKIO = 600
3854 00:40:21.422207 MCKIO_SEMI = 0
3855 00:40:21.422261 PLL_FREQ = 2288
3856 00:40:21.422314 DQ_UI_PI_RATIO = 32
3857 00:40:21.422368 CA_UI_PI_RATIO = 0
3858 00:40:21.422422 ===================================
3859 00:40:21.422476 ===================================
3860 00:40:21.422530 memory_type:LPDDR4
3861 00:40:21.422589 GP_NUM : 10
3862 00:40:21.422643 SRAM_EN : 1
3863 00:40:21.422697 MD32_EN : 0
3864 00:40:21.422751 ===================================
3865 00:40:21.423005 [ANA_INIT] >>>>>>>>>>>>>>
3866 00:40:21.423069 <<<<<< [CONFIGURE PHASE]: ANA_TX
3867 00:40:21.423126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3868 00:40:21.423203 ===================================
3869 00:40:21.423259 data_rate = 1200,PCW = 0X5800
3870 00:40:21.423314 ===================================
3871 00:40:21.423370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3872 00:40:21.423462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 00:40:21.423517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 00:40:21.423572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3875 00:40:21.423627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3876 00:40:21.423681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3877 00:40:21.423736 [ANA_INIT] flow start
3878 00:40:21.423790 [ANA_INIT] PLL >>>>>>>>
3879 00:40:21.423844 [ANA_INIT] PLL <<<<<<<<
3880 00:40:21.424085 [ANA_INIT] MIDPI >>>>>>>>
3881 00:40:21.427141 [ANA_INIT] MIDPI <<<<<<<<
3882 00:40:21.427252 [ANA_INIT] DLL >>>>>>>>
3883 00:40:21.430456 [ANA_INIT] flow end
3884 00:40:21.433631 ============ LP4 DIFF to SE enter ============
3885 00:40:21.437215 ============ LP4 DIFF to SE exit ============
3886 00:40:21.440312 [ANA_INIT] <<<<<<<<<<<<<
3887 00:40:21.443794 [Flow] Enable top DCM control >>>>>
3888 00:40:21.447465 [Flow] Enable top DCM control <<<<<
3889 00:40:21.450575 Enable DLL master slave shuffle
3890 00:40:21.457091 ==============================================================
3891 00:40:21.457179 Gating Mode config
3892 00:40:21.463641 ==============================================================
3893 00:40:21.463727 Config description:
3894 00:40:21.473728 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3895 00:40:21.480684 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3896 00:40:21.487192 SELPH_MODE 0: By rank 1: By Phase
3897 00:40:21.490568 ==============================================================
3898 00:40:21.493453 GAT_TRACK_EN = 1
3899 00:40:21.496917 RX_GATING_MODE = 2
3900 00:40:21.499973 RX_GATING_TRACK_MODE = 2
3901 00:40:21.503418 SELPH_MODE = 1
3902 00:40:21.507020 PICG_EARLY_EN = 1
3903 00:40:21.510502 VALID_LAT_VALUE = 1
3904 00:40:21.513544 ==============================================================
3905 00:40:21.519830 Enter into Gating configuration >>>>
3906 00:40:21.519944 Exit from Gating configuration <<<<
3907 00:40:21.523601 Enter into DVFS_PRE_config >>>>>
3908 00:40:21.536916 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3909 00:40:21.539993 Exit from DVFS_PRE_config <<<<<
3910 00:40:21.543655 Enter into PICG configuration >>>>
3911 00:40:21.546725 Exit from PICG configuration <<<<
3912 00:40:21.546823 [RX_INPUT] configuration >>>>>
3913 00:40:21.550063 [RX_INPUT] configuration <<<<<
3914 00:40:21.556652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3915 00:40:21.560320 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3916 00:40:21.566598 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 00:40:21.573280 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 00:40:21.579723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 00:40:21.586733 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 00:40:21.589854 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3921 00:40:21.593146 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3922 00:40:21.600032 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3923 00:40:21.603165 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3924 00:40:21.606778 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3925 00:40:21.609682 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 00:40:21.613061 ===================================
3927 00:40:21.616455 LPDDR4 DRAM CONFIGURATION
3928 00:40:21.620111 ===================================
3929 00:40:21.623259 EX_ROW_EN[0] = 0x0
3930 00:40:21.623367 EX_ROW_EN[1] = 0x0
3931 00:40:21.626554 LP4Y_EN = 0x0
3932 00:40:21.626626 WORK_FSP = 0x0
3933 00:40:21.630112 WL = 0x2
3934 00:40:21.630184 RL = 0x2
3935 00:40:21.633167 BL = 0x2
3936 00:40:21.633239 RPST = 0x0
3937 00:40:21.636544 RD_PRE = 0x0
3938 00:40:21.636635 WR_PRE = 0x1
3939 00:40:21.639818 WR_PST = 0x0
3940 00:40:21.639920 DBI_WR = 0x0
3941 00:40:21.643206 DBI_RD = 0x0
3942 00:40:21.643289 OTF = 0x1
3943 00:40:21.646312 ===================================
3944 00:40:21.653545 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3945 00:40:21.656533 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3946 00:40:21.660013 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 00:40:21.663441 ===================================
3948 00:40:21.666405 LPDDR4 DRAM CONFIGURATION
3949 00:40:21.669660 ===================================
3950 00:40:21.669764 EX_ROW_EN[0] = 0x10
3951 00:40:21.673075 EX_ROW_EN[1] = 0x0
3952 00:40:21.676374 LP4Y_EN = 0x0
3953 00:40:21.676470 WORK_FSP = 0x0
3954 00:40:21.679626 WL = 0x2
3955 00:40:21.679723 RL = 0x2
3956 00:40:21.683034 BL = 0x2
3957 00:40:21.683131 RPST = 0x0
3958 00:40:21.686553 RD_PRE = 0x0
3959 00:40:21.686626 WR_PRE = 0x1
3960 00:40:21.689695 WR_PST = 0x0
3961 00:40:21.689798 DBI_WR = 0x0
3962 00:40:21.692988 DBI_RD = 0x0
3963 00:40:21.693093 OTF = 0x1
3964 00:40:21.696532 ===================================
3965 00:40:21.702890 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3966 00:40:21.707559 nWR fixed to 30
3967 00:40:21.710658 [ModeRegInit_LP4] CH0 RK0
3968 00:40:21.710756 [ModeRegInit_LP4] CH0 RK1
3969 00:40:21.714368 [ModeRegInit_LP4] CH1 RK0
3970 00:40:21.717085 [ModeRegInit_LP4] CH1 RK1
3971 00:40:21.717186 match AC timing 17
3972 00:40:21.723882 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3973 00:40:21.727483 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3974 00:40:21.730680 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3975 00:40:21.737061 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3976 00:40:21.740852 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3977 00:40:21.740935 ==
3978 00:40:21.743894 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 00:40:21.747038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 00:40:21.747120 ==
3981 00:40:21.754146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 00:40:21.760458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3983 00:40:21.764088 [CA 0] Center 36 (5~67) winsize 63
3984 00:40:21.767388 [CA 1] Center 36 (6~67) winsize 62
3985 00:40:21.770812 [CA 2] Center 34 (4~65) winsize 62
3986 00:40:21.774015 [CA 3] Center 34 (3~65) winsize 63
3987 00:40:21.777418 [CA 4] Center 33 (3~64) winsize 62
3988 00:40:21.780465 [CA 5] Center 33 (2~64) winsize 63
3989 00:40:21.780600
3990 00:40:21.784206 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3991 00:40:21.784309
3992 00:40:21.787512 [CATrainingPosCal] consider 1 rank data
3993 00:40:21.790767 u2DelayCellTimex100 = 270/100 ps
3994 00:40:21.794005 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3995 00:40:21.797513 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3996 00:40:21.800500 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3997 00:40:21.804253 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3998 00:40:21.807293 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 00:40:21.810543 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4000 00:40:21.810618
4001 00:40:21.817452 CA PerBit enable=1, Macro0, CA PI delay=33
4002 00:40:21.817559
4003 00:40:21.817662 [CBTSetCACLKResult] CA Dly = 33
4004 00:40:21.820586 CS Dly: 6 (0~37)
4005 00:40:21.820691 ==
4006 00:40:21.823968 Dram Type= 6, Freq= 0, CH_0, rank 1
4007 00:40:21.827380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 00:40:21.827459 ==
4009 00:40:21.833887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 00:40:21.840699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4011 00:40:21.844005 [CA 0] Center 36 (6~67) winsize 62
4012 00:40:21.847541 [CA 1] Center 36 (6~67) winsize 62
4013 00:40:21.850630 [CA 2] Center 35 (5~65) winsize 61
4014 00:40:21.853955 [CA 3] Center 34 (4~65) winsize 62
4015 00:40:21.857098 [CA 4] Center 34 (3~65) winsize 63
4016 00:40:21.860696 [CA 5] Center 33 (3~64) winsize 62
4017 00:40:21.860799
4018 00:40:21.864046 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4019 00:40:21.864151
4020 00:40:21.867413 [CATrainingPosCal] consider 2 rank data
4021 00:40:21.870463 u2DelayCellTimex100 = 270/100 ps
4022 00:40:21.873819 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4023 00:40:21.877243 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4024 00:40:21.880615 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4025 00:40:21.884163 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4026 00:40:21.887598 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 00:40:21.890511 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 00:40:21.893909
4029 00:40:21.897223 CA PerBit enable=1, Macro0, CA PI delay=33
4030 00:40:21.897299
4031 00:40:21.900487 [CBTSetCACLKResult] CA Dly = 33
4032 00:40:21.900588 CS Dly: 6 (0~37)
4033 00:40:21.900657
4034 00:40:21.904181 ----->DramcWriteLeveling(PI) begin...
4035 00:40:21.904285 ==
4036 00:40:21.907365 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 00:40:21.910693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 00:40:21.913948 ==
4039 00:40:21.914050 Write leveling (Byte 0): 33 => 33
4040 00:40:21.917042 Write leveling (Byte 1): 29 => 29
4041 00:40:21.920645 DramcWriteLeveling(PI) end<-----
4042 00:40:21.920721
4043 00:40:21.920784 ==
4044 00:40:21.923561 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 00:40:21.930530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 00:40:21.930620 ==
4047 00:40:21.930722 [Gating] SW mode calibration
4048 00:40:21.940619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4049 00:40:21.943726 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4050 00:40:21.947011 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 00:40:21.953643 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 00:40:21.957136 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4053 00:40:21.960485 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4054 00:40:21.967218 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4055 00:40:21.970448 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 00:40:21.973690 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 00:40:21.980277 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 00:40:21.983635 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 00:40:21.987255 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 00:40:21.993823 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4061 00:40:21.996988 0 10 12 | B1->B0 | 2d2d 3e3d | 0 1 | (0 0) (0 0)
4062 00:40:22.000331 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4063 00:40:22.007325 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 00:40:22.010327 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 00:40:22.013726 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 00:40:22.020484 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 00:40:22.023656 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 00:40:22.027100 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 00:40:22.033804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4070 00:40:22.036791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4071 00:40:22.040468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 00:40:22.043594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 00:40:22.050219 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 00:40:22.053632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 00:40:22.056908 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:40:22.063413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:40:22.066966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 00:40:22.070265 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 00:40:22.076985 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 00:40:22.080278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 00:40:22.083390 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 00:40:22.090519 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 00:40:22.093820 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 00:40:22.096979 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 00:40:22.103411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4086 00:40:22.107147 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4087 00:40:22.110143 Total UI for P1: 0, mck2ui 16
4088 00:40:22.113390 best dqsien dly found for B0: ( 0, 13, 12)
4089 00:40:22.116674 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 00:40:22.120403 Total UI for P1: 0, mck2ui 16
4091 00:40:22.123505 best dqsien dly found for B1: ( 0, 13, 16)
4092 00:40:22.126686 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4093 00:40:22.130303 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4094 00:40:22.130383
4095 00:40:22.136689 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4096 00:40:22.140228 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4097 00:40:22.140336 [Gating] SW calibration Done
4098 00:40:22.143533 ==
4099 00:40:22.146507 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 00:40:22.149816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 00:40:22.149919 ==
4102 00:40:22.150015 RX Vref Scan: 0
4103 00:40:22.150106
4104 00:40:22.153664 RX Vref 0 -> 0, step: 1
4105 00:40:22.153749
4106 00:40:22.156536 RX Delay -230 -> 252, step: 16
4107 00:40:22.160150 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4108 00:40:22.163258 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4109 00:40:22.170022 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4110 00:40:22.173221 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4111 00:40:22.176570 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4112 00:40:22.179812 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4113 00:40:22.186732 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4114 00:40:22.190039 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4115 00:40:22.193197 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4116 00:40:22.196558 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4117 00:40:22.200068 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4118 00:40:22.206867 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4119 00:40:22.209852 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4120 00:40:22.213029 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4121 00:40:22.216778 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4122 00:40:22.223203 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4123 00:40:22.223305 ==
4124 00:40:22.226312 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 00:40:22.229871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 00:40:22.229955 ==
4127 00:40:22.230019 DQS Delay:
4128 00:40:22.233033 DQS0 = 0, DQS1 = 0
4129 00:40:22.233116 DQM Delay:
4130 00:40:22.236612 DQM0 = 52, DQM1 = 40
4131 00:40:22.236702 DQ Delay:
4132 00:40:22.239613 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4133 00:40:22.243500 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4134 00:40:22.246541 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4135 00:40:22.249657 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4136 00:40:22.249732
4137 00:40:22.249796
4138 00:40:22.249855 ==
4139 00:40:22.253030 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 00:40:22.256337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 00:40:22.256420 ==
4142 00:40:22.256487
4143 00:40:22.259657
4144 00:40:22.259745 TX Vref Scan disable
4145 00:40:22.262887 == TX Byte 0 ==
4146 00:40:22.266365 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4147 00:40:22.269755 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4148 00:40:22.272998 == TX Byte 1 ==
4149 00:40:22.276275 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4150 00:40:22.279842 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4151 00:40:22.279933 ==
4152 00:40:22.282940 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 00:40:22.289700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 00:40:22.289795 ==
4155 00:40:22.289888
4156 00:40:22.289969
4157 00:40:22.290080 TX Vref Scan disable
4158 00:40:22.294432 == TX Byte 0 ==
4159 00:40:22.297495 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4160 00:40:22.304124 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4161 00:40:22.304253 == TX Byte 1 ==
4162 00:40:22.307403 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4163 00:40:22.314146 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4164 00:40:22.314235
4165 00:40:22.314322 [DATLAT]
4166 00:40:22.314404 Freq=600, CH0 RK0
4167 00:40:22.314484
4168 00:40:22.317699 DATLAT Default: 0x9
4169 00:40:22.317786 0, 0xFFFF, sum = 0
4170 00:40:22.320787 1, 0xFFFF, sum = 0
4171 00:40:22.320876 2, 0xFFFF, sum = 0
4172 00:40:22.324329 3, 0xFFFF, sum = 0
4173 00:40:22.327454 4, 0xFFFF, sum = 0
4174 00:40:22.327543 5, 0xFFFF, sum = 0
4175 00:40:22.331210 6, 0xFFFF, sum = 0
4176 00:40:22.331298 7, 0xFFFF, sum = 0
4177 00:40:22.331385 8, 0x0, sum = 1
4178 00:40:22.334147 9, 0x0, sum = 2
4179 00:40:22.334238 10, 0x0, sum = 3
4180 00:40:22.337444 11, 0x0, sum = 4
4181 00:40:22.337532 best_step = 9
4182 00:40:22.337617
4183 00:40:22.337697 ==
4184 00:40:22.340777 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 00:40:22.347580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 00:40:22.347676 ==
4187 00:40:22.347765 RX Vref Scan: 1
4188 00:40:22.347846
4189 00:40:22.351081 RX Vref 0 -> 0, step: 1
4190 00:40:22.351168
4191 00:40:22.354158 RX Delay -179 -> 252, step: 8
4192 00:40:22.354264
4193 00:40:22.357654 Set Vref, RX VrefLevel [Byte0]: 58
4194 00:40:22.360646 [Byte1]: 49
4195 00:40:22.360734
4196 00:40:22.363898 Final RX Vref Byte 0 = 58 to rank0
4197 00:40:22.367674 Final RX Vref Byte 1 = 49 to rank0
4198 00:40:22.370730 Final RX Vref Byte 0 = 58 to rank1
4199 00:40:22.373933 Final RX Vref Byte 1 = 49 to rank1==
4200 00:40:22.377374 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 00:40:22.380491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 00:40:22.380617 ==
4203 00:40:22.384283 DQS Delay:
4204 00:40:22.384372 DQS0 = 0, DQS1 = 0
4205 00:40:22.384480 DQM Delay:
4206 00:40:22.387491 DQM0 = 50, DQM1 = 36
4207 00:40:22.387617 DQ Delay:
4208 00:40:22.390653 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4209 00:40:22.393845 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =60
4210 00:40:22.397133 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4211 00:40:22.400531 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4212 00:40:22.400663
4213 00:40:22.400750
4214 00:40:22.410399 [DQSOSCAuto] RK0, (LSB)MR18= 0x615b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4215 00:40:22.413831 CH0 RK0: MR19=808, MR18=615B
4216 00:40:22.417271 CH0_RK0: MR19=0x808, MR18=0x615B, DQSOSC=391, MR23=63, INC=171, DEC=114
4217 00:40:22.420661
4218 00:40:22.424128 ----->DramcWriteLeveling(PI) begin...
4219 00:40:22.424243 ==
4220 00:40:22.427274 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 00:40:22.430295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 00:40:22.430385 ==
4223 00:40:22.434163 Write leveling (Byte 0): 34 => 34
4224 00:40:22.437094 Write leveling (Byte 1): 31 => 31
4225 00:40:22.440738 DramcWriteLeveling(PI) end<-----
4226 00:40:22.440826
4227 00:40:22.440917 ==
4228 00:40:22.443808 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 00:40:22.447120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 00:40:22.447209 ==
4231 00:40:22.450568 [Gating] SW mode calibration
4232 00:40:22.457024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4233 00:40:22.463508 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4234 00:40:22.467106 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 00:40:22.470072 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 00:40:22.477127 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4237 00:40:22.480354 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
4238 00:40:22.483614 0 9 16 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 0)
4239 00:40:22.487378 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 00:40:22.493569 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 00:40:22.496896 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 00:40:22.500178 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 00:40:22.506965 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 00:40:22.510111 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4245 00:40:22.513442 0 10 12 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (0 0)
4246 00:40:22.520097 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4247 00:40:22.523385 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 00:40:22.526940 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 00:40:22.533532 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 00:40:22.536893 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 00:40:22.539906 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 00:40:22.546661 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 00:40:22.549964 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 00:40:22.553243 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 00:40:22.560229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:40:22.563272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:40:22.566522 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:40:22.573614 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:40:22.576712 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:40:22.580087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:40:22.586451 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:40:22.589755 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:40:22.593456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:40:22.599870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:40:22.603222 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:40:22.606385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:40:22.613250 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 00:40:22.616769 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4269 00:40:22.619877 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4270 00:40:22.623323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 00:40:22.626627 Total UI for P1: 0, mck2ui 16
4272 00:40:22.630074 best dqsien dly found for B0: ( 0, 13, 10)
4273 00:40:22.633047 Total UI for P1: 0, mck2ui 16
4274 00:40:22.636483 best dqsien dly found for B1: ( 0, 13, 14)
4275 00:40:22.639664 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4276 00:40:22.646507 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 00:40:22.646613
4278 00:40:22.649597 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4279 00:40:22.653186 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 00:40:22.656499 [Gating] SW calibration Done
4281 00:40:22.656627 ==
4282 00:40:22.659592 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 00:40:22.662875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 00:40:22.662976 ==
4285 00:40:22.666427 RX Vref Scan: 0
4286 00:40:22.666511
4287 00:40:22.666579 RX Vref 0 -> 0, step: 1
4288 00:40:22.666642
4289 00:40:22.669554 RX Delay -230 -> 252, step: 16
4290 00:40:22.673245 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 00:40:22.679982 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4292 00:40:22.683394 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4293 00:40:22.686224 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4294 00:40:22.689517 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4295 00:40:22.693453 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4296 00:40:22.699834 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4297 00:40:22.703033 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4298 00:40:22.706489 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4299 00:40:22.709835 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4300 00:40:22.716313 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4301 00:40:22.719976 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4302 00:40:22.723437 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4303 00:40:22.726358 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4304 00:40:22.729771 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4305 00:40:22.736544 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4306 00:40:22.736660 ==
4307 00:40:22.739680 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 00:40:22.743392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 00:40:22.743480 ==
4310 00:40:22.743548 DQS Delay:
4311 00:40:22.746265 DQS0 = 0, DQS1 = 0
4312 00:40:22.746349 DQM Delay:
4313 00:40:22.749781 DQM0 = 48, DQM1 = 42
4314 00:40:22.749866 DQ Delay:
4315 00:40:22.753031 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4316 00:40:22.756443 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4317 00:40:22.759935 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4318 00:40:22.762898 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4319 00:40:22.763016
4320 00:40:22.763083
4321 00:40:22.763146 ==
4322 00:40:22.766217 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 00:40:22.769677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 00:40:22.772933 ==
4325 00:40:22.773019
4326 00:40:22.773087
4327 00:40:22.773149 TX Vref Scan disable
4328 00:40:22.776473 == TX Byte 0 ==
4329 00:40:22.779472 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 00:40:22.783200 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 00:40:22.786320 == TX Byte 1 ==
4332 00:40:22.789445 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 00:40:22.792808 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 00:40:22.796353 ==
4335 00:40:22.799490 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 00:40:22.802828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 00:40:22.802914 ==
4338 00:40:22.802981
4339 00:40:22.803044
4340 00:40:22.805936 TX Vref Scan disable
4341 00:40:22.809566 == TX Byte 0 ==
4342 00:40:22.812654 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4343 00:40:22.815918 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4344 00:40:22.819257 == TX Byte 1 ==
4345 00:40:22.822808 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4346 00:40:22.825738 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4347 00:40:22.825826
4348 00:40:22.825895 [DATLAT]
4349 00:40:22.829068 Freq=600, CH0 RK1
4350 00:40:22.829159
4351 00:40:22.829226 DATLAT Default: 0x9
4352 00:40:22.832542 0, 0xFFFF, sum = 0
4353 00:40:22.832666 1, 0xFFFF, sum = 0
4354 00:40:22.836191 2, 0xFFFF, sum = 0
4355 00:40:22.839318 3, 0xFFFF, sum = 0
4356 00:40:22.839425 4, 0xFFFF, sum = 0
4357 00:40:22.842277 5, 0xFFFF, sum = 0
4358 00:40:22.842360 6, 0xFFFF, sum = 0
4359 00:40:22.845645 7, 0xFFFF, sum = 0
4360 00:40:22.845723 8, 0x0, sum = 1
4361 00:40:22.849408 9, 0x0, sum = 2
4362 00:40:22.849526 10, 0x0, sum = 3
4363 00:40:22.849624 11, 0x0, sum = 4
4364 00:40:22.852478 best_step = 9
4365 00:40:22.852613
4366 00:40:22.852703 ==
4367 00:40:22.855820 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 00:40:22.859313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 00:40:22.859416 ==
4370 00:40:22.862277 RX Vref Scan: 0
4371 00:40:22.862374
4372 00:40:22.862462 RX Vref 0 -> 0, step: 1
4373 00:40:22.862558
4374 00:40:22.865668 RX Delay -179 -> 252, step: 8
4375 00:40:22.873272 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4376 00:40:22.876448 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4377 00:40:22.879795 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4378 00:40:22.883223 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4379 00:40:22.886410 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4380 00:40:22.893531 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4381 00:40:22.896767 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4382 00:40:22.899803 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4383 00:40:22.903545 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4384 00:40:22.906453 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4385 00:40:22.913232 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4386 00:40:22.916369 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4387 00:40:22.919778 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4388 00:40:22.923308 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4389 00:40:22.929751 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4390 00:40:22.933040 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4391 00:40:22.933117 ==
4392 00:40:22.936467 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 00:40:22.939759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 00:40:22.939860 ==
4395 00:40:22.943130 DQS Delay:
4396 00:40:22.943234 DQS0 = 0, DQS1 = 0
4397 00:40:22.943323 DQM Delay:
4398 00:40:22.946452 DQM0 = 48, DQM1 = 39
4399 00:40:22.946528 DQ Delay:
4400 00:40:22.949758 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4401 00:40:22.953289 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4402 00:40:22.956160 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4403 00:40:22.959520 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4404 00:40:22.959623
4405 00:40:22.959702
4406 00:40:22.969508 [DQSOSCAuto] RK1, (LSB)MR18= 0x6633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4407 00:40:22.969622 CH0 RK1: MR19=808, MR18=6633
4408 00:40:22.976161 CH0_RK1: MR19=0x808, MR18=0x6633, DQSOSC=390, MR23=63, INC=172, DEC=114
4409 00:40:22.979501 [RxdqsGatingPostProcess] freq 600
4410 00:40:22.986382 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 00:40:22.989844 Pre-setting of DQS Precalculation
4412 00:40:22.993177 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 00:40:22.993252 ==
4414 00:40:22.996152 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 00:40:22.999617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 00:40:23.003033 ==
4417 00:40:23.006089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 00:40:23.012890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 00:40:23.016130 [CA 0] Center 35 (5~66) winsize 62
4420 00:40:23.019595 [CA 1] Center 35 (5~66) winsize 62
4421 00:40:23.023087 [CA 2] Center 34 (4~65) winsize 62
4422 00:40:23.026623 [CA 3] Center 34 (4~64) winsize 61
4423 00:40:23.029756 [CA 4] Center 34 (4~65) winsize 62
4424 00:40:23.033142 [CA 5] Center 33 (3~64) winsize 62
4425 00:40:23.033220
4426 00:40:23.036463 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 00:40:23.036584
4428 00:40:23.039645 [CATrainingPosCal] consider 1 rank data
4429 00:40:23.042728 u2DelayCellTimex100 = 270/100 ps
4430 00:40:23.046076 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 00:40:23.049368 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 00:40:23.052704 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 00:40:23.059409 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4434 00:40:23.062783 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 00:40:23.065976 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 00:40:23.066076
4437 00:40:23.069801 CA PerBit enable=1, Macro0, CA PI delay=33
4438 00:40:23.069871
4439 00:40:23.072918 [CBTSetCACLKResult] CA Dly = 33
4440 00:40:23.072992 CS Dly: 4 (0~35)
4441 00:40:23.073057 ==
4442 00:40:23.076094 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 00:40:23.082679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 00:40:23.082784 ==
4445 00:40:23.086032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 00:40:23.093007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4447 00:40:23.095885 [CA 0] Center 35 (5~66) winsize 62
4448 00:40:23.099474 [CA 1] Center 35 (5~66) winsize 62
4449 00:40:23.102622 [CA 2] Center 34 (4~65) winsize 62
4450 00:40:23.106295 [CA 3] Center 34 (4~65) winsize 62
4451 00:40:23.109566 [CA 4] Center 34 (4~65) winsize 62
4452 00:40:23.112921 [CA 5] Center 33 (3~64) winsize 62
4453 00:40:23.113016
4454 00:40:23.116380 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4455 00:40:23.116473
4456 00:40:23.119479 [CATrainingPosCal] consider 2 rank data
4457 00:40:23.122850 u2DelayCellTimex100 = 270/100 ps
4458 00:40:23.126081 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 00:40:23.129202 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 00:40:23.132791 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 00:40:23.139618 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4462 00:40:23.142554 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 00:40:23.146028 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 00:40:23.146131
4465 00:40:23.149245 CA PerBit enable=1, Macro0, CA PI delay=33
4466 00:40:23.149319
4467 00:40:23.152661 [CBTSetCACLKResult] CA Dly = 33
4468 00:40:23.152729 CS Dly: 5 (0~37)
4469 00:40:23.152792
4470 00:40:23.155914 ----->DramcWriteLeveling(PI) begin...
4471 00:40:23.156021 ==
4472 00:40:23.159523 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 00:40:23.166015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 00:40:23.166119 ==
4475 00:40:23.169264 Write leveling (Byte 0): 28 => 28
4476 00:40:23.172596 Write leveling (Byte 1): 29 => 29
4477 00:40:23.175736 DramcWriteLeveling(PI) end<-----
4478 00:40:23.175835
4479 00:40:23.175925 ==
4480 00:40:23.179351 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 00:40:23.182577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 00:40:23.182680 ==
4483 00:40:23.186105 [Gating] SW mode calibration
4484 00:40:23.193013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 00:40:23.195916 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 00:40:23.202488 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 00:40:23.205736 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 00:40:23.209098 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4489 00:40:23.215964 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (1 1)
4490 00:40:23.218975 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 00:40:23.222385 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 00:40:23.229215 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 00:40:23.232372 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 00:40:23.235565 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 00:40:23.242108 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 00:40:23.245613 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4497 00:40:23.248893 0 10 12 | B1->B0 | 3b3b 4040 | 1 0 | (0 0) (0 0)
4498 00:40:23.255430 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 00:40:23.258941 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 00:40:23.262173 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 00:40:23.268985 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 00:40:23.272181 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 00:40:23.275597 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 00:40:23.282397 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4505 00:40:23.285426 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 00:40:23.289179 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 00:40:23.295889 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 00:40:23.298997 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 00:40:23.302562 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 00:40:23.305568 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 00:40:23.311960 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 00:40:23.315837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 00:40:23.318949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 00:40:23.325338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 00:40:23.328880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 00:40:23.332098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 00:40:23.338923 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 00:40:23.341846 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 00:40:23.345407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 00:40:23.352185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4521 00:40:23.355232 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 00:40:23.358616 Total UI for P1: 0, mck2ui 16
4523 00:40:23.362530 best dqsien dly found for B0: ( 0, 13, 10)
4524 00:40:23.365307 Total UI for P1: 0, mck2ui 16
4525 00:40:23.368805 best dqsien dly found for B1: ( 0, 13, 8)
4526 00:40:23.372118 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4527 00:40:23.375609 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4528 00:40:23.375704
4529 00:40:23.378623 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4530 00:40:23.382594 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4531 00:40:23.385413 [Gating] SW calibration Done
4532 00:40:23.385482 ==
4533 00:40:23.388778 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 00:40:23.392254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 00:40:23.392357 ==
4536 00:40:23.395633 RX Vref Scan: 0
4537 00:40:23.395731
4538 00:40:23.398768 RX Vref 0 -> 0, step: 1
4539 00:40:23.398840
4540 00:40:23.402171 RX Delay -230 -> 252, step: 16
4541 00:40:23.405587 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4542 00:40:23.408693 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4543 00:40:23.412042 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4544 00:40:23.415456 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4545 00:40:23.422166 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4546 00:40:23.425270 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4547 00:40:23.428498 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4548 00:40:23.432396 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4549 00:40:23.438952 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4550 00:40:23.441875 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4551 00:40:23.445187 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4552 00:40:23.448894 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4553 00:40:23.451701 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4554 00:40:23.458734 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4555 00:40:23.462218 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4556 00:40:23.465245 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4557 00:40:23.465318 ==
4558 00:40:23.468669 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 00:40:23.475288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 00:40:23.475367 ==
4561 00:40:23.475436 DQS Delay:
4562 00:40:23.475499 DQS0 = 0, DQS1 = 0
4563 00:40:23.478385 DQM Delay:
4564 00:40:23.478459 DQM0 = 48, DQM1 = 42
4565 00:40:23.481873 DQ Delay:
4566 00:40:23.485214 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4567 00:40:23.485291 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4568 00:40:23.488370 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4569 00:40:23.495155 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4570 00:40:23.495258
4571 00:40:23.495352
4572 00:40:23.495441 ==
4573 00:40:23.498626 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 00:40:23.501753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 00:40:23.501828 ==
4576 00:40:23.501891
4577 00:40:23.501958
4578 00:40:23.505235 TX Vref Scan disable
4579 00:40:23.505305 == TX Byte 0 ==
4580 00:40:23.511993 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4581 00:40:23.515168 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4582 00:40:23.515264 == TX Byte 1 ==
4583 00:40:23.522055 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 00:40:23.525122 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 00:40:23.525193 ==
4586 00:40:23.529001 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 00:40:23.531790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 00:40:23.531862 ==
4589 00:40:23.531925
4590 00:40:23.531984
4591 00:40:23.535235 TX Vref Scan disable
4592 00:40:23.538524 == TX Byte 0 ==
4593 00:40:23.542125 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4594 00:40:23.545253 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4595 00:40:23.548725 == TX Byte 1 ==
4596 00:40:23.552245 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4597 00:40:23.555021 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4598 00:40:23.555125
4599 00:40:23.558475 [DATLAT]
4600 00:40:23.558581 Freq=600, CH1 RK0
4601 00:40:23.558672
4602 00:40:23.561744 DATLAT Default: 0x9
4603 00:40:23.561826 0, 0xFFFF, sum = 0
4604 00:40:23.565494 1, 0xFFFF, sum = 0
4605 00:40:23.565598 2, 0xFFFF, sum = 0
4606 00:40:23.568385 3, 0xFFFF, sum = 0
4607 00:40:23.568483 4, 0xFFFF, sum = 0
4608 00:40:23.571844 5, 0xFFFF, sum = 0
4609 00:40:23.571944 6, 0xFFFF, sum = 0
4610 00:40:23.575300 7, 0xFFFF, sum = 0
4611 00:40:23.575372 8, 0x0, sum = 1
4612 00:40:23.578401 9, 0x0, sum = 2
4613 00:40:23.578474 10, 0x0, sum = 3
4614 00:40:23.581596 11, 0x0, sum = 4
4615 00:40:23.581695 best_step = 9
4616 00:40:23.581788
4617 00:40:23.581875 ==
4618 00:40:23.585155 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 00:40:23.588520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 00:40:23.591668 ==
4621 00:40:23.591774 RX Vref Scan: 1
4622 00:40:23.591871
4623 00:40:23.595167 RX Vref 0 -> 0, step: 1
4624 00:40:23.595243
4625 00:40:23.598841 RX Delay -179 -> 252, step: 8
4626 00:40:23.598917
4627 00:40:23.602150 Set Vref, RX VrefLevel [Byte0]: 50
4628 00:40:23.605011 [Byte1]: 52
4629 00:40:23.605083
4630 00:40:23.608419 Final RX Vref Byte 0 = 50 to rank0
4631 00:40:23.612150 Final RX Vref Byte 1 = 52 to rank0
4632 00:40:23.614975 Final RX Vref Byte 0 = 50 to rank1
4633 00:40:23.618242 Final RX Vref Byte 1 = 52 to rank1==
4634 00:40:23.621772 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 00:40:23.625003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 00:40:23.625103 ==
4637 00:40:23.625204 DQS Delay:
4638 00:40:23.628641 DQS0 = 0, DQS1 = 0
4639 00:40:23.628716 DQM Delay:
4640 00:40:23.631567 DQM0 = 50, DQM1 = 41
4641 00:40:23.631651 DQ Delay:
4642 00:40:23.634910 DQ0 =56, DQ1 =48, DQ2 =36, DQ3 =48
4643 00:40:23.638337 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4644 00:40:23.641530 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4645 00:40:23.645067 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4646 00:40:23.645146
4647 00:40:23.645214
4648 00:40:23.655194 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4649 00:40:23.655302 CH1 RK0: MR19=808, MR18=4C73
4650 00:40:23.661856 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4651 00:40:23.661931
4652 00:40:23.665242 ----->DramcWriteLeveling(PI) begin...
4653 00:40:23.665344 ==
4654 00:40:23.668036 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 00:40:23.674792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 00:40:23.674892 ==
4657 00:40:23.678094 Write leveling (Byte 0): 31 => 31
4658 00:40:23.681362 Write leveling (Byte 1): 28 => 28
4659 00:40:23.684967 DramcWriteLeveling(PI) end<-----
4660 00:40:23.685066
4661 00:40:23.685155 ==
4662 00:40:23.688165 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 00:40:23.691327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 00:40:23.691423 ==
4665 00:40:23.694634 [Gating] SW mode calibration
4666 00:40:23.701312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4667 00:40:23.704404 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4668 00:40:23.711321 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 00:40:23.714273 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 00:40:23.717821 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 00:40:23.724288 0 9 12 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
4672 00:40:23.727555 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4673 00:40:23.731465 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 00:40:23.738200 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 00:40:23.741240 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 00:40:23.744591 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 00:40:23.751346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 00:40:23.754668 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 00:40:23.758019 0 10 12 | B1->B0 | 3e3e 3232 | 0 0 | (0 0) (0 0)
4680 00:40:23.764238 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 00:40:23.767877 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 00:40:23.771148 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 00:40:23.777601 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 00:40:23.780996 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 00:40:23.784379 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 00:40:23.790544 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 00:40:23.794120 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4688 00:40:23.797496 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 00:40:23.804421 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 00:40:23.807168 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 00:40:23.810601 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 00:40:23.817316 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 00:40:23.820644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 00:40:23.824263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 00:40:23.830789 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 00:40:23.833701 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 00:40:23.837316 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 00:40:23.840677 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 00:40:23.847807 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 00:40:23.850543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 00:40:23.853954 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 00:40:23.860448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4703 00:40:23.864073 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4704 00:40:23.867227 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 00:40:23.870826 Total UI for P1: 0, mck2ui 16
4706 00:40:23.874099 best dqsien dly found for B0: ( 0, 13, 10)
4707 00:40:23.877385 Total UI for P1: 0, mck2ui 16
4708 00:40:23.880246 best dqsien dly found for B1: ( 0, 13, 12)
4709 00:40:23.883987 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4710 00:40:23.890596 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4711 00:40:23.890681
4712 00:40:23.893888 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4713 00:40:23.897153 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4714 00:40:23.900373 [Gating] SW calibration Done
4715 00:40:23.900496 ==
4716 00:40:23.903802 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 00:40:23.906923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 00:40:23.907018 ==
4719 00:40:23.907088 RX Vref Scan: 0
4720 00:40:23.910423
4721 00:40:23.910531 RX Vref 0 -> 0, step: 1
4722 00:40:23.910595
4723 00:40:23.913662 RX Delay -230 -> 252, step: 16
4724 00:40:23.916832 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4725 00:40:23.923835 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4726 00:40:23.927098 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4727 00:40:23.930322 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4728 00:40:23.933811 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4729 00:40:23.937129 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4730 00:40:23.943939 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4731 00:40:23.946977 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4732 00:40:23.950393 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4733 00:40:23.953654 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4734 00:40:23.957160 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4735 00:40:23.963816 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4736 00:40:23.967213 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4737 00:40:23.970514 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4738 00:40:23.973665 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4739 00:40:23.980696 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4740 00:40:23.980796 ==
4741 00:40:23.983610 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 00:40:23.987152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 00:40:23.987237 ==
4744 00:40:23.987309 DQS Delay:
4745 00:40:23.990616 DQS0 = 0, DQS1 = 0
4746 00:40:23.990708 DQM Delay:
4747 00:40:23.993556 DQM0 = 51, DQM1 = 47
4748 00:40:23.993641 DQ Delay:
4749 00:40:23.996812 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4750 00:40:24.000325 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4751 00:40:24.003794 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4752 00:40:24.006885 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4753 00:40:24.006967
4754 00:40:24.007035
4755 00:40:24.007097 ==
4756 00:40:24.010438 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 00:40:24.013427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 00:40:24.013516 ==
4759 00:40:24.013585
4760 00:40:24.017442
4761 00:40:24.017527 TX Vref Scan disable
4762 00:40:24.020114 == TX Byte 0 ==
4763 00:40:24.023436 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4764 00:40:24.027130 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4765 00:40:24.030295 == TX Byte 1 ==
4766 00:40:24.033623 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4767 00:40:24.037063 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4768 00:40:24.037157 ==
4769 00:40:24.040140 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 00:40:24.046935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 00:40:24.047039 ==
4772 00:40:24.047110
4773 00:40:24.047181
4774 00:40:24.047242 TX Vref Scan disable
4775 00:40:24.051140 == TX Byte 0 ==
4776 00:40:24.054708 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4777 00:40:24.058098 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4778 00:40:24.061833 == TX Byte 1 ==
4779 00:40:24.065011 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4780 00:40:24.068343 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4781 00:40:24.071407
4782 00:40:24.071483 [DATLAT]
4783 00:40:24.071556 Freq=600, CH1 RK1
4784 00:40:24.071618
4785 00:40:24.074885 DATLAT Default: 0x9
4786 00:40:24.074960 0, 0xFFFF, sum = 0
4787 00:40:24.078225 1, 0xFFFF, sum = 0
4788 00:40:24.078307 2, 0xFFFF, sum = 0
4789 00:40:24.081775 3, 0xFFFF, sum = 0
4790 00:40:24.081870 4, 0xFFFF, sum = 0
4791 00:40:24.084732 5, 0xFFFF, sum = 0
4792 00:40:24.084849 6, 0xFFFF, sum = 0
4793 00:40:24.088167 7, 0xFFFF, sum = 0
4794 00:40:24.088258 8, 0x0, sum = 1
4795 00:40:24.091373 9, 0x0, sum = 2
4796 00:40:24.091465 10, 0x0, sum = 3
4797 00:40:24.094658 11, 0x0, sum = 4
4798 00:40:24.094750 best_step = 9
4799 00:40:24.094839
4800 00:40:24.094922 ==
4801 00:40:24.098211 Dram Type= 6, Freq= 0, CH_1, rank 1
4802 00:40:24.105017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4803 00:40:24.105114 ==
4804 00:40:24.105205 RX Vref Scan: 0
4805 00:40:24.105288
4806 00:40:24.107969 RX Vref 0 -> 0, step: 1
4807 00:40:24.108058
4808 00:40:24.111372 RX Delay -163 -> 252, step: 8
4809 00:40:24.114664 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4810 00:40:24.118182 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4811 00:40:24.124587 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4812 00:40:24.127963 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4813 00:40:24.131205 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4814 00:40:24.134788 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4815 00:40:24.137799 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4816 00:40:24.145081 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4817 00:40:24.148025 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4818 00:40:24.151898 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4819 00:40:24.154553 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4820 00:40:24.161543 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4821 00:40:24.165047 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4822 00:40:24.168172 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4823 00:40:24.171242 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4824 00:40:24.174663 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4825 00:40:24.174752 ==
4826 00:40:24.177853 Dram Type= 6, Freq= 0, CH_1, rank 1
4827 00:40:24.184520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4828 00:40:24.184646 ==
4829 00:40:24.184741 DQS Delay:
4830 00:40:24.187900 DQS0 = 0, DQS1 = 0
4831 00:40:24.188012 DQM Delay:
4832 00:40:24.188109 DQM0 = 49, DQM1 = 43
4833 00:40:24.191396 DQ Delay:
4834 00:40:24.194708 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4835 00:40:24.198340 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4836 00:40:24.201493 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4837 00:40:24.204618 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4838 00:40:24.204709
4839 00:40:24.204773
4840 00:40:24.211496 [DQSOSCAuto] RK1, (LSB)MR18= 0x6128, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4841 00:40:24.214772 CH1 RK1: MR19=808, MR18=6128
4842 00:40:24.221372 CH1_RK1: MR19=0x808, MR18=0x6128, DQSOSC=391, MR23=63, INC=171, DEC=114
4843 00:40:24.224662 [RxdqsGatingPostProcess] freq 600
4844 00:40:24.227842 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4845 00:40:24.231101 Pre-setting of DQS Precalculation
4846 00:40:24.237663 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4847 00:40:24.244243 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4848 00:40:24.250872 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4849 00:40:24.250960
4850 00:40:24.251029
4851 00:40:24.254401 [Calibration Summary] 1200 Mbps
4852 00:40:24.254501 CH 0, Rank 0
4853 00:40:24.257622 SW Impedance : PASS
4854 00:40:24.260910 DUTY Scan : NO K
4855 00:40:24.260992 ZQ Calibration : PASS
4856 00:40:24.264395 Jitter Meter : NO K
4857 00:40:24.267486 CBT Training : PASS
4858 00:40:24.267557 Write leveling : PASS
4859 00:40:24.270965 RX DQS gating : PASS
4860 00:40:24.274346 RX DQ/DQS(RDDQC) : PASS
4861 00:40:24.274421 TX DQ/DQS : PASS
4862 00:40:24.277537 RX DATLAT : PASS
4863 00:40:24.280879 RX DQ/DQS(Engine): PASS
4864 00:40:24.280947 TX OE : NO K
4865 00:40:24.284156 All Pass.
4866 00:40:24.284227
4867 00:40:24.284288 CH 0, Rank 1
4868 00:40:24.287538 SW Impedance : PASS
4869 00:40:24.287608 DUTY Scan : NO K
4870 00:40:24.291036 ZQ Calibration : PASS
4871 00:40:24.291105 Jitter Meter : NO K
4872 00:40:24.294168 CBT Training : PASS
4873 00:40:24.297618 Write leveling : PASS
4874 00:40:24.297701 RX DQS gating : PASS
4875 00:40:24.301118 RX DQ/DQS(RDDQC) : PASS
4876 00:40:24.304592 TX DQ/DQS : PASS
4877 00:40:24.304673 RX DATLAT : PASS
4878 00:40:24.307536 RX DQ/DQS(Engine): PASS
4879 00:40:24.311126 TX OE : NO K
4880 00:40:24.311200 All Pass.
4881 00:40:24.311262
4882 00:40:24.311321 CH 1, Rank 0
4883 00:40:24.314103 SW Impedance : PASS
4884 00:40:24.317661 DUTY Scan : NO K
4885 00:40:24.317737 ZQ Calibration : PASS
4886 00:40:24.321023 Jitter Meter : NO K
4887 00:40:24.324381 CBT Training : PASS
4888 00:40:24.324455 Write leveling : PASS
4889 00:40:24.327368 RX DQS gating : PASS
4890 00:40:24.331195 RX DQ/DQS(RDDQC) : PASS
4891 00:40:24.331263 TX DQ/DQS : PASS
4892 00:40:24.334062 RX DATLAT : PASS
4893 00:40:24.337534 RX DQ/DQS(Engine): PASS
4894 00:40:24.337601 TX OE : NO K
4895 00:40:24.337665 All Pass.
4896 00:40:24.337725
4897 00:40:24.341058 CH 1, Rank 1
4898 00:40:24.344246 SW Impedance : PASS
4899 00:40:24.344315 DUTY Scan : NO K
4900 00:40:24.347503 ZQ Calibration : PASS
4901 00:40:24.347575 Jitter Meter : NO K
4902 00:40:24.350691 CBT Training : PASS
4903 00:40:24.354205 Write leveling : PASS
4904 00:40:24.354295 RX DQS gating : PASS
4905 00:40:24.357516 RX DQ/DQS(RDDQC) : PASS
4906 00:40:24.360934 TX DQ/DQS : PASS
4907 00:40:24.361026 RX DATLAT : PASS
4908 00:40:24.364030 RX DQ/DQS(Engine): PASS
4909 00:40:24.367555 TX OE : NO K
4910 00:40:24.367644 All Pass.
4911 00:40:24.367741
4912 00:40:24.370963 DramC Write-DBI off
4913 00:40:24.371052 PER_BANK_REFRESH: Hybrid Mode
4914 00:40:24.374052 TX_TRACKING: ON
4915 00:40:24.380806 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4916 00:40:24.384060 [FAST_K] Save calibration result to emmc
4917 00:40:24.391019 dramc_set_vcore_voltage set vcore to 662500
4918 00:40:24.391108 Read voltage for 933, 3
4919 00:40:24.394048 Vio18 = 0
4920 00:40:24.394134 Vcore = 662500
4921 00:40:24.394219 Vdram = 0
4922 00:40:24.397472 Vddq = 0
4923 00:40:24.397559 Vmddr = 0
4924 00:40:24.400845 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4925 00:40:24.407527 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4926 00:40:24.410886 MEM_TYPE=3, freq_sel=17
4927 00:40:24.410979 sv_algorithm_assistance_LP4_1600
4928 00:40:24.417512 ============ PULL DRAM RESETB DOWN ============
4929 00:40:24.421132 ========== PULL DRAM RESETB DOWN end =========
4930 00:40:24.424274 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4931 00:40:24.427420 ===================================
4932 00:40:24.430882 LPDDR4 DRAM CONFIGURATION
4933 00:40:24.434062 ===================================
4934 00:40:24.437294 EX_ROW_EN[0] = 0x0
4935 00:40:24.437396 EX_ROW_EN[1] = 0x0
4936 00:40:24.440674 LP4Y_EN = 0x0
4937 00:40:24.440760 WORK_FSP = 0x0
4938 00:40:24.443989 WL = 0x3
4939 00:40:24.444076 RL = 0x3
4940 00:40:24.447264 BL = 0x2
4941 00:40:24.447350 RPST = 0x0
4942 00:40:24.450662 RD_PRE = 0x0
4943 00:40:24.450748 WR_PRE = 0x1
4944 00:40:24.453818 WR_PST = 0x0
4945 00:40:24.453904 DBI_WR = 0x0
4946 00:40:24.457333 DBI_RD = 0x0
4947 00:40:24.457459 OTF = 0x1
4948 00:40:24.460789 ===================================
4949 00:40:24.463868 ===================================
4950 00:40:24.467267 ANA top config
4951 00:40:24.470747 ===================================
4952 00:40:24.473978 DLL_ASYNC_EN = 0
4953 00:40:24.474066 ALL_SLAVE_EN = 1
4954 00:40:24.477602 NEW_RANK_MODE = 1
4955 00:40:24.481027 DLL_IDLE_MODE = 1
4956 00:40:24.484043 LP45_APHY_COMB_EN = 1
4957 00:40:24.484129 TX_ODT_DIS = 1
4958 00:40:24.487391 NEW_8X_MODE = 1
4959 00:40:24.491085 ===================================
4960 00:40:24.494193 ===================================
4961 00:40:24.497303 data_rate = 1866
4962 00:40:24.500728 CKR = 1
4963 00:40:24.504119 DQ_P2S_RATIO = 8
4964 00:40:24.507301 ===================================
4965 00:40:24.511020 CA_P2S_RATIO = 8
4966 00:40:24.511108 DQ_CA_OPEN = 0
4967 00:40:24.513990 DQ_SEMI_OPEN = 0
4968 00:40:24.517463 CA_SEMI_OPEN = 0
4969 00:40:24.520483 CA_FULL_RATE = 0
4970 00:40:24.523898 DQ_CKDIV4_EN = 1
4971 00:40:24.527252 CA_CKDIV4_EN = 1
4972 00:40:24.527366 CA_PREDIV_EN = 0
4973 00:40:24.530614 PH8_DLY = 0
4974 00:40:24.534188 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4975 00:40:24.537383 DQ_AAMCK_DIV = 4
4976 00:40:24.540361 CA_AAMCK_DIV = 4
4977 00:40:24.543815 CA_ADMCK_DIV = 4
4978 00:40:24.543893 DQ_TRACK_CA_EN = 0
4979 00:40:24.547017 CA_PICK = 933
4980 00:40:24.550481 CA_MCKIO = 933
4981 00:40:24.553899 MCKIO_SEMI = 0
4982 00:40:24.556799 PLL_FREQ = 3732
4983 00:40:24.560354 DQ_UI_PI_RATIO = 32
4984 00:40:24.563539 CA_UI_PI_RATIO = 0
4985 00:40:24.566942 ===================================
4986 00:40:24.570310 ===================================
4987 00:40:24.570389 memory_type:LPDDR4
4988 00:40:24.573688 GP_NUM : 10
4989 00:40:24.576953 SRAM_EN : 1
4990 00:40:24.577031 MD32_EN : 0
4991 00:40:24.580198 ===================================
4992 00:40:24.583506 [ANA_INIT] >>>>>>>>>>>>>>
4993 00:40:24.586830 <<<<<< [CONFIGURE PHASE]: ANA_TX
4994 00:40:24.590368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4995 00:40:24.593499 ===================================
4996 00:40:24.597138 data_rate = 1866,PCW = 0X8f00
4997 00:40:24.600382 ===================================
4998 00:40:24.603251 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4999 00:40:24.606646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5000 00:40:24.613529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 00:40:24.616899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5002 00:40:24.619767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5003 00:40:24.623281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5004 00:40:24.626436 [ANA_INIT] flow start
5005 00:40:24.629547 [ANA_INIT] PLL >>>>>>>>
5006 00:40:24.629649 [ANA_INIT] PLL <<<<<<<<
5007 00:40:24.633126 [ANA_INIT] MIDPI >>>>>>>>
5008 00:40:24.636528 [ANA_INIT] MIDPI <<<<<<<<
5009 00:40:24.639902 [ANA_INIT] DLL >>>>>>>>
5010 00:40:24.639979 [ANA_INIT] flow end
5011 00:40:24.643435 ============ LP4 DIFF to SE enter ============
5012 00:40:24.649743 ============ LP4 DIFF to SE exit ============
5013 00:40:24.649824 [ANA_INIT] <<<<<<<<<<<<<
5014 00:40:24.653017 [Flow] Enable top DCM control >>>>>
5015 00:40:24.656412 [Flow] Enable top DCM control <<<<<
5016 00:40:24.659663 Enable DLL master slave shuffle
5017 00:40:24.666512 ==============================================================
5018 00:40:24.666597 Gating Mode config
5019 00:40:24.672766 ==============================================================
5020 00:40:24.676427 Config description:
5021 00:40:24.682841 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5022 00:40:24.689492 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5023 00:40:24.696344 SELPH_MODE 0: By rank 1: By Phase
5024 00:40:24.702838 ==============================================================
5025 00:40:24.706172 GAT_TRACK_EN = 1
5026 00:40:24.706247 RX_GATING_MODE = 2
5027 00:40:24.709412 RX_GATING_TRACK_MODE = 2
5028 00:40:24.712939 SELPH_MODE = 1
5029 00:40:24.716036 PICG_EARLY_EN = 1
5030 00:40:24.719468 VALID_LAT_VALUE = 1
5031 00:40:24.726203 ==============================================================
5032 00:40:24.729563 Enter into Gating configuration >>>>
5033 00:40:24.733018 Exit from Gating configuration <<<<
5034 00:40:24.736498 Enter into DVFS_PRE_config >>>>>
5035 00:40:24.746320 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5036 00:40:24.749558 Exit from DVFS_PRE_config <<<<<
5037 00:40:24.752938 Enter into PICG configuration >>>>
5038 00:40:24.756330 Exit from PICG configuration <<<<
5039 00:40:24.759388 [RX_INPUT] configuration >>>>>
5040 00:40:24.759499 [RX_INPUT] configuration <<<<<
5041 00:40:24.766325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5042 00:40:24.772695 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5043 00:40:24.776000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 00:40:24.782557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 00:40:24.789188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 00:40:24.795904 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 00:40:24.799378 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5048 00:40:24.802481 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5049 00:40:24.809506 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5050 00:40:24.812739 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5051 00:40:24.815856 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5052 00:40:24.822485 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 00:40:24.826388 ===================================
5054 00:40:24.826466 LPDDR4 DRAM CONFIGURATION
5055 00:40:24.829412 ===================================
5056 00:40:24.832453 EX_ROW_EN[0] = 0x0
5057 00:40:24.832593 EX_ROW_EN[1] = 0x0
5058 00:40:24.836142 LP4Y_EN = 0x0
5059 00:40:24.836238 WORK_FSP = 0x0
5060 00:40:24.839322 WL = 0x3
5061 00:40:24.842530 RL = 0x3
5062 00:40:24.842628 BL = 0x2
5063 00:40:24.846141 RPST = 0x0
5064 00:40:24.846238 RD_PRE = 0x0
5065 00:40:24.849088 WR_PRE = 0x1
5066 00:40:24.849183 WR_PST = 0x0
5067 00:40:24.852774 DBI_WR = 0x0
5068 00:40:24.852870 DBI_RD = 0x0
5069 00:40:24.855896 OTF = 0x1
5070 00:40:24.859362 ===================================
5071 00:40:24.862344 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5072 00:40:24.865893 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5073 00:40:24.869288 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5074 00:40:24.872417 ===================================
5075 00:40:24.875708 LPDDR4 DRAM CONFIGURATION
5076 00:40:24.879098 ===================================
5077 00:40:24.882784 EX_ROW_EN[0] = 0x10
5078 00:40:24.882886 EX_ROW_EN[1] = 0x0
5079 00:40:24.885827 LP4Y_EN = 0x0
5080 00:40:24.885908 WORK_FSP = 0x0
5081 00:40:24.888879 WL = 0x3
5082 00:40:24.888985 RL = 0x3
5083 00:40:24.892404 BL = 0x2
5084 00:40:24.892501 RPST = 0x0
5085 00:40:24.895671 RD_PRE = 0x0
5086 00:40:24.895769 WR_PRE = 0x1
5087 00:40:24.898995 WR_PST = 0x0
5088 00:40:24.902262 DBI_WR = 0x0
5089 00:40:24.902336 DBI_RD = 0x0
5090 00:40:24.905580 OTF = 0x1
5091 00:40:24.909090 ===================================
5092 00:40:24.912157 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5093 00:40:24.917336 nWR fixed to 30
5094 00:40:24.920831 [ModeRegInit_LP4] CH0 RK0
5095 00:40:24.920938 [ModeRegInit_LP4] CH0 RK1
5096 00:40:24.923856 [ModeRegInit_LP4] CH1 RK0
5097 00:40:24.927139 [ModeRegInit_LP4] CH1 RK1
5098 00:40:24.927239 match AC timing 9
5099 00:40:24.933911 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5100 00:40:24.937304 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5101 00:40:24.940982 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5102 00:40:24.947320 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5103 00:40:24.950470 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5104 00:40:24.950543 ==
5105 00:40:24.954051 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 00:40:24.957461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 00:40:24.957568 ==
5108 00:40:24.963932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 00:40:24.971029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5110 00:40:24.973971 [CA 0] Center 38 (7~69) winsize 63
5111 00:40:24.977399 [CA 1] Center 38 (8~69) winsize 62
5112 00:40:24.983877 [CA 2] Center 35 (5~66) winsize 62
5113 00:40:24.984347 [CA 3] Center 35 (5~65) winsize 61
5114 00:40:24.987122 [CA 4] Center 34 (4~64) winsize 61
5115 00:40:24.990972 [CA 5] Center 33 (3~64) winsize 62
5116 00:40:24.991073
5117 00:40:24.994163 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5118 00:40:24.994265
5119 00:40:24.997541 [CATrainingPosCal] consider 1 rank data
5120 00:40:25.000577 u2DelayCellTimex100 = 270/100 ps
5121 00:40:25.004144 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5122 00:40:25.007564 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5123 00:40:25.010610 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5124 00:40:25.013901 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5125 00:40:25.017117 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5126 00:40:25.020480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5127 00:40:25.024090
5128 00:40:25.027297 CA PerBit enable=1, Macro0, CA PI delay=33
5129 00:40:25.027388
5130 00:40:25.030760 [CBTSetCACLKResult] CA Dly = 33
5131 00:40:25.030838 CS Dly: 6 (0~37)
5132 00:40:25.030904 ==
5133 00:40:25.034292 Dram Type= 6, Freq= 0, CH_0, rank 1
5134 00:40:25.037271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 00:40:25.037345 ==
5136 00:40:25.043936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 00:40:25.050481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5138 00:40:25.054052 [CA 0] Center 38 (8~69) winsize 62
5139 00:40:25.057277 [CA 1] Center 38 (8~69) winsize 62
5140 00:40:25.060533 [CA 2] Center 36 (6~67) winsize 62
5141 00:40:25.063930 [CA 3] Center 35 (5~66) winsize 62
5142 00:40:25.067093 [CA 4] Center 34 (4~65) winsize 62
5143 00:40:25.070343 [CA 5] Center 34 (4~64) winsize 61
5144 00:40:25.070424
5145 00:40:25.074045 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5146 00:40:25.074118
5147 00:40:25.077143 [CATrainingPosCal] consider 2 rank data
5148 00:40:25.080396 u2DelayCellTimex100 = 270/100 ps
5149 00:40:25.083804 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5150 00:40:25.087193 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5151 00:40:25.090600 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5152 00:40:25.093729 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5153 00:40:25.097113 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5154 00:40:25.103989 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5155 00:40:25.104078
5156 00:40:25.106874 CA PerBit enable=1, Macro0, CA PI delay=34
5157 00:40:25.106947
5158 00:40:25.110413 [CBTSetCACLKResult] CA Dly = 34
5159 00:40:25.110488 CS Dly: 7 (0~40)
5160 00:40:25.110558
5161 00:40:25.114014 ----->DramcWriteLeveling(PI) begin...
5162 00:40:25.114088 ==
5163 00:40:25.116824 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 00:40:25.120379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 00:40:25.123648 ==
5166 00:40:25.123739 Write leveling (Byte 0): 34 => 34
5167 00:40:25.126958 Write leveling (Byte 1): 29 => 29
5168 00:40:25.130233 DramcWriteLeveling(PI) end<-----
5169 00:40:25.130310
5170 00:40:25.130378 ==
5171 00:40:25.133480 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 00:40:25.140698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 00:40:25.140779 ==
5174 00:40:25.143702 [Gating] SW mode calibration
5175 00:40:25.150218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5176 00:40:25.153360 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5177 00:40:25.160426 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5178 00:40:25.163471 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 00:40:25.167014 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 00:40:25.173408 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 00:40:25.176863 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 00:40:25.180142 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 00:40:25.186825 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)
5184 00:40:25.190247 0 14 28 | B1->B0 | 3232 2424 | 0 0 | (0 0) (1 0)
5185 00:40:25.193417 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
5186 00:40:25.196751 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 00:40:25.203254 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 00:40:25.206912 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 00:40:25.210173 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 00:40:25.217266 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 00:40:25.220176 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5192 00:40:25.223356 0 15 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5193 00:40:25.230413 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 00:40:25.233733 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 00:40:25.236733 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 00:40:25.243635 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 00:40:25.246677 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 00:40:25.250054 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 00:40:25.256642 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 00:40:25.259867 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5201 00:40:25.263467 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 00:40:25.270076 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 00:40:25.273015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 00:40:25.276769 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 00:40:25.283508 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 00:40:25.286677 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 00:40:25.289963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 00:40:25.296730 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 00:40:25.299886 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 00:40:25.303197 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 00:40:25.306463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 00:40:25.313207 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 00:40:25.316704 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 00:40:25.320329 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 00:40:25.326591 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5216 00:40:25.329742 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5217 00:40:25.333407 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 00:40:25.336537 Total UI for P1: 0, mck2ui 16
5219 00:40:25.339987 best dqsien dly found for B0: ( 1, 2, 26)
5220 00:40:25.343168 Total UI for P1: 0, mck2ui 16
5221 00:40:25.346606 best dqsien dly found for B1: ( 1, 2, 30)
5222 00:40:25.350079 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5223 00:40:25.352998 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5224 00:40:25.353069
5225 00:40:25.359654 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5226 00:40:25.363025 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5227 00:40:25.366407 [Gating] SW calibration Done
5228 00:40:25.366482 ==
5229 00:40:25.369841 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 00:40:25.373002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 00:40:25.373087 ==
5232 00:40:25.373153 RX Vref Scan: 0
5233 00:40:25.373215
5234 00:40:25.376369 RX Vref 0 -> 0, step: 1
5235 00:40:25.376474
5236 00:40:25.379805 RX Delay -80 -> 252, step: 8
5237 00:40:25.383155 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5238 00:40:25.386514 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5239 00:40:25.389875 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5240 00:40:25.396484 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5241 00:40:25.399887 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5242 00:40:25.403308 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5243 00:40:25.407109 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5244 00:40:25.409909 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5245 00:40:25.416927 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5246 00:40:25.419719 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5247 00:40:25.423060 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5248 00:40:25.426259 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5249 00:40:25.429464 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5250 00:40:25.433222 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5251 00:40:25.439699 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5252 00:40:25.443098 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5253 00:40:25.443185 ==
5254 00:40:25.446254 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 00:40:25.449573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 00:40:25.449661 ==
5257 00:40:25.452675 DQS Delay:
5258 00:40:25.452762 DQS0 = 0, DQS1 = 0
5259 00:40:25.452847 DQM Delay:
5260 00:40:25.455860 DQM0 = 107, DQM1 = 90
5261 00:40:25.455947 DQ Delay:
5262 00:40:25.459247 DQ0 =107, DQ1 =111, DQ2 =99, DQ3 =107
5263 00:40:25.462813 DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115
5264 00:40:25.465661 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5265 00:40:25.469783 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5266 00:40:25.469881
5267 00:40:25.469973
5268 00:40:25.470061 ==
5269 00:40:25.472427 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 00:40:25.479235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 00:40:25.479335 ==
5272 00:40:25.479427
5273 00:40:25.479515
5274 00:40:25.482391 TX Vref Scan disable
5275 00:40:25.482487 == TX Byte 0 ==
5276 00:40:25.485748 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5277 00:40:25.492537 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5278 00:40:25.492652 == TX Byte 1 ==
5279 00:40:25.495816 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5280 00:40:25.502212 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5281 00:40:25.502286 ==
5282 00:40:25.505691 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 00:40:25.509113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 00:40:25.509187 ==
5285 00:40:25.509252
5286 00:40:25.509311
5287 00:40:25.512287 TX Vref Scan disable
5288 00:40:25.515678 == TX Byte 0 ==
5289 00:40:25.518691 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5290 00:40:25.522398 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5291 00:40:25.525698 == TX Byte 1 ==
5292 00:40:25.528956 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5293 00:40:25.532123 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5294 00:40:25.532221
5295 00:40:25.535702 [DATLAT]
5296 00:40:25.535798 Freq=933, CH0 RK0
5297 00:40:25.535888
5298 00:40:25.538966 DATLAT Default: 0xd
5299 00:40:25.539075 0, 0xFFFF, sum = 0
5300 00:40:25.542340 1, 0xFFFF, sum = 0
5301 00:40:25.542444 2, 0xFFFF, sum = 0
5302 00:40:25.545731 3, 0xFFFF, sum = 0
5303 00:40:25.545828 4, 0xFFFF, sum = 0
5304 00:40:25.548755 5, 0xFFFF, sum = 0
5305 00:40:25.548826 6, 0xFFFF, sum = 0
5306 00:40:25.552265 7, 0xFFFF, sum = 0
5307 00:40:25.552379 8, 0xFFFF, sum = 0
5308 00:40:25.555460 9, 0xFFFF, sum = 0
5309 00:40:25.555556 10, 0x0, sum = 1
5310 00:40:25.558680 11, 0x0, sum = 2
5311 00:40:25.558783 12, 0x0, sum = 3
5312 00:40:25.562249 13, 0x0, sum = 4
5313 00:40:25.562395 best_step = 11
5314 00:40:25.562487
5315 00:40:25.562575 ==
5316 00:40:25.565391 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 00:40:25.568641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 00:40:25.571962 ==
5319 00:40:25.572058 RX Vref Scan: 1
5320 00:40:25.572149
5321 00:40:25.575494 RX Vref 0 -> 0, step: 1
5322 00:40:25.575594
5323 00:40:25.578765 RX Delay -53 -> 252, step: 4
5324 00:40:25.578835
5325 00:40:25.581916 Set Vref, RX VrefLevel [Byte0]: 58
5326 00:40:25.585311 [Byte1]: 49
5327 00:40:25.585382
5328 00:40:25.588677 Final RX Vref Byte 0 = 58 to rank0
5329 00:40:25.591781 Final RX Vref Byte 1 = 49 to rank0
5330 00:40:25.594871 Final RX Vref Byte 0 = 58 to rank1
5331 00:40:25.598292 Final RX Vref Byte 1 = 49 to rank1==
5332 00:40:25.601530 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 00:40:25.605085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 00:40:25.605156 ==
5335 00:40:25.608164 DQS Delay:
5336 00:40:25.608262 DQS0 = 0, DQS1 = 0
5337 00:40:25.608353 DQM Delay:
5338 00:40:25.611540 DQM0 = 106, DQM1 = 92
5339 00:40:25.611608 DQ Delay:
5340 00:40:25.615009 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5341 00:40:25.618387 DQ4 =106, DQ5 =98, DQ6 =114, DQ7 =114
5342 00:40:25.621741 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5343 00:40:25.624970 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =100
5344 00:40:25.625042
5345 00:40:25.628388
5346 00:40:25.634938 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5347 00:40:25.638171 CH0 RK0: MR19=505, MR18=2521
5348 00:40:25.644696 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5349 00:40:25.644778
5350 00:40:25.648080 ----->DramcWriteLeveling(PI) begin...
5351 00:40:25.648180 ==
5352 00:40:25.651630 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 00:40:25.655095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 00:40:25.655194 ==
5355 00:40:25.658151 Write leveling (Byte 0): 34 => 34
5356 00:40:25.661436 Write leveling (Byte 1): 28 => 28
5357 00:40:25.664568 DramcWriteLeveling(PI) end<-----
5358 00:40:25.664647
5359 00:40:25.664712 ==
5360 00:40:25.668335 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 00:40:25.671395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 00:40:25.671497 ==
5363 00:40:25.674830 [Gating] SW mode calibration
5364 00:40:25.681333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5365 00:40:25.687859 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5366 00:40:25.691301 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 00:40:25.694552 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 00:40:25.701344 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 00:40:25.704444 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 00:40:25.707699 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 00:40:25.714514 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 00:40:25.717588 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
5373 00:40:25.721525 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (1 0)
5374 00:40:25.727860 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 00:40:25.731533 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 00:40:25.734583 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 00:40:25.741512 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 00:40:25.744877 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 00:40:25.747904 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 00:40:25.754496 0 15 24 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
5381 00:40:25.757885 0 15 28 | B1->B0 | 3d3d 4242 | 0 1 | (0 0) (0 0)
5382 00:40:25.761535 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 00:40:25.764379 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 00:40:25.771323 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 00:40:25.774676 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:40:25.778121 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 00:40:25.784318 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 00:40:25.787760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 00:40:25.791195 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5390 00:40:25.797946 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 00:40:25.801249 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:40:25.804426 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:40:25.811293 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:40:25.814459 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:40:25.817991 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:40:25.824667 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:40:25.828278 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:40:25.831525 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:40:25.837896 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:40:25.841056 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:40:25.844836 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:40:25.851058 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:40:25.854545 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:40:25.857703 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 00:40:25.861295 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5406 00:40:25.864899 Total UI for P1: 0, mck2ui 16
5407 00:40:25.867854 best dqsien dly found for B1: ( 1, 2, 26)
5408 00:40:25.874789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 00:40:25.877655 Total UI for P1: 0, mck2ui 16
5410 00:40:25.881521 best dqsien dly found for B0: ( 1, 2, 28)
5411 00:40:25.884780 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5412 00:40:25.888336 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5413 00:40:25.888438
5414 00:40:25.891409 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5415 00:40:25.894549 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5416 00:40:25.897654 [Gating] SW calibration Done
5417 00:40:25.897758 ==
5418 00:40:25.901184 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 00:40:25.904322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 00:40:25.904423 ==
5421 00:40:25.907890 RX Vref Scan: 0
5422 00:40:25.907987
5423 00:40:25.908077 RX Vref 0 -> 0, step: 1
5424 00:40:25.908166
5425 00:40:25.911348 RX Delay -80 -> 252, step: 8
5426 00:40:25.917709 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5427 00:40:25.921483 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5428 00:40:25.924433 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5429 00:40:25.928146 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5430 00:40:25.931081 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5431 00:40:25.934639 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5432 00:40:25.941365 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5433 00:40:25.944417 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5434 00:40:25.947634 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5435 00:40:25.950908 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5436 00:40:25.954146 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5437 00:40:25.957886 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5438 00:40:25.964225 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5439 00:40:25.967799 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5440 00:40:25.970932 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5441 00:40:25.974241 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5442 00:40:25.974343 ==
5443 00:40:25.977666 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 00:40:25.981006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 00:40:25.981108 ==
5446 00:40:25.984452 DQS Delay:
5447 00:40:25.984575 DQS0 = 0, DQS1 = 0
5448 00:40:25.987859 DQM Delay:
5449 00:40:25.987959 DQM0 = 104, DQM1 = 89
5450 00:40:25.988051 DQ Delay:
5451 00:40:25.991566 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5452 00:40:25.994320 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5453 00:40:25.997807 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5454 00:40:26.000819 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5455 00:40:26.004489
5456 00:40:26.004624
5457 00:40:26.004694 ==
5458 00:40:26.007377 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 00:40:26.010840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 00:40:26.010942 ==
5461 00:40:26.011034
5462 00:40:26.011122
5463 00:40:26.014342 TX Vref Scan disable
5464 00:40:26.014441 == TX Byte 0 ==
5465 00:40:26.020809 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5466 00:40:26.024174 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5467 00:40:26.024249 == TX Byte 1 ==
5468 00:40:26.030476 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5469 00:40:26.034099 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5470 00:40:26.034178 ==
5471 00:40:26.037321 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 00:40:26.040606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 00:40:26.040682 ==
5474 00:40:26.040746
5475 00:40:26.040806
5476 00:40:26.044141 TX Vref Scan disable
5477 00:40:26.047367 == TX Byte 0 ==
5478 00:40:26.050942 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5479 00:40:26.054204 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5480 00:40:26.057365 == TX Byte 1 ==
5481 00:40:26.061021 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5482 00:40:26.064058 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5483 00:40:26.064159
5484 00:40:26.067608 [DATLAT]
5485 00:40:26.067700 Freq=933, CH0 RK1
5486 00:40:26.067792
5487 00:40:26.070734 DATLAT Default: 0xb
5488 00:40:26.070833 0, 0xFFFF, sum = 0
5489 00:40:26.074250 1, 0xFFFF, sum = 0
5490 00:40:26.074355 2, 0xFFFF, sum = 0
5491 00:40:26.077407 3, 0xFFFF, sum = 0
5492 00:40:26.077483 4, 0xFFFF, sum = 0
5493 00:40:26.080495 5, 0xFFFF, sum = 0
5494 00:40:26.080619 6, 0xFFFF, sum = 0
5495 00:40:26.084088 7, 0xFFFF, sum = 0
5496 00:40:26.084191 8, 0xFFFF, sum = 0
5497 00:40:26.087427 9, 0xFFFF, sum = 0
5498 00:40:26.087528 10, 0x0, sum = 1
5499 00:40:26.090875 11, 0x0, sum = 2
5500 00:40:26.090973 12, 0x0, sum = 3
5501 00:40:26.094177 13, 0x0, sum = 4
5502 00:40:26.094276 best_step = 11
5503 00:40:26.094364
5504 00:40:26.094451 ==
5505 00:40:26.097526 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 00:40:26.104112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 00:40:26.104193 ==
5508 00:40:26.104258 RX Vref Scan: 0
5509 00:40:26.104318
5510 00:40:26.107477 RX Vref 0 -> 0, step: 1
5511 00:40:26.107572
5512 00:40:26.111142 RX Delay -53 -> 252, step: 4
5513 00:40:26.114118 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5514 00:40:26.117323 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5515 00:40:26.124264 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5516 00:40:26.127672 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5517 00:40:26.130828 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5518 00:40:26.134225 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5519 00:40:26.137515 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5520 00:40:26.141062 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5521 00:40:26.147769 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5522 00:40:26.150738 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5523 00:40:26.154141 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5524 00:40:26.157594 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5525 00:40:26.160744 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5526 00:40:26.167330 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5527 00:40:26.171306 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5528 00:40:26.174271 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5529 00:40:26.174371 ==
5530 00:40:26.177479 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 00:40:26.180993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 00:40:26.181080 ==
5533 00:40:26.184044 DQS Delay:
5534 00:40:26.184144 DQS0 = 0, DQS1 = 0
5535 00:40:26.184235 DQM Delay:
5536 00:40:26.187349 DQM0 = 104, DQM1 = 92
5537 00:40:26.187451 DQ Delay:
5538 00:40:26.190613 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5539 00:40:26.194051 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5540 00:40:26.197346 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =92
5541 00:40:26.200892 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5542 00:40:26.201036
5543 00:40:26.203886
5544 00:40:26.210457 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5545 00:40:26.213853 CH0 RK1: MR19=505, MR18=2D0E
5546 00:40:26.220777 CH0_RK1: MR19=0x505, MR18=0x2D0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5547 00:40:26.223873 [RxdqsGatingPostProcess] freq 933
5548 00:40:26.227451 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5549 00:40:26.230595 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 00:40:26.234204 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 00:40:26.237485 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 00:40:26.240494 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 00:40:26.244056 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 00:40:26.247178 best DQS1 dly(2T, 0.5T) = (0, 10)
5555 00:40:26.250411 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 00:40:26.253860 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5557 00:40:26.257200 Pre-setting of DQS Precalculation
5558 00:40:26.260661 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5559 00:40:26.260766 ==
5560 00:40:26.264173 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 00:40:26.267285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 00:40:26.270679 ==
5563 00:40:26.273845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 00:40:26.280436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5565 00:40:26.283624 [CA 0] Center 37 (7~68) winsize 62
5566 00:40:26.287209 [CA 1] Center 37 (7~68) winsize 62
5567 00:40:26.290631 [CA 2] Center 35 (5~65) winsize 61
5568 00:40:26.293693 [CA 3] Center 34 (4~65) winsize 62
5569 00:40:26.297147 [CA 4] Center 35 (5~65) winsize 61
5570 00:40:26.300673 [CA 5] Center 34 (4~64) winsize 61
5571 00:40:26.300767
5572 00:40:26.303933 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5573 00:40:26.304010
5574 00:40:26.307328 [CATrainingPosCal] consider 1 rank data
5575 00:40:26.310368 u2DelayCellTimex100 = 270/100 ps
5576 00:40:26.314046 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5577 00:40:26.317287 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5578 00:40:26.320444 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5579 00:40:26.323769 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5580 00:40:26.330308 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5581 00:40:26.333639 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5582 00:40:26.333733
5583 00:40:26.337544 CA PerBit enable=1, Macro0, CA PI delay=34
5584 00:40:26.337634
5585 00:40:26.340239 [CBTSetCACLKResult] CA Dly = 34
5586 00:40:26.340327 CS Dly: 6 (0~37)
5587 00:40:26.340395 ==
5588 00:40:26.343738 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 00:40:26.347134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 00:40:26.350494 ==
5591 00:40:26.353650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 00:40:26.360467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5593 00:40:26.363907 [CA 0] Center 38 (8~69) winsize 62
5594 00:40:26.367274 [CA 1] Center 38 (8~69) winsize 62
5595 00:40:26.370330 [CA 2] Center 36 (6~66) winsize 61
5596 00:40:26.373883 [CA 3] Center 35 (5~65) winsize 61
5597 00:40:26.377224 [CA 4] Center 35 (5~65) winsize 61
5598 00:40:26.380225 [CA 5] Center 35 (5~65) winsize 61
5599 00:40:26.380310
5600 00:40:26.383762 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5601 00:40:26.383845
5602 00:40:26.387160 [CATrainingPosCal] consider 2 rank data
5603 00:40:26.390069 u2DelayCellTimex100 = 270/100 ps
5604 00:40:26.393698 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5605 00:40:26.396897 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5606 00:40:26.400245 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5607 00:40:26.403468 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5608 00:40:26.410076 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5609 00:40:26.413594 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5610 00:40:26.413677
5611 00:40:26.417065 CA PerBit enable=1, Macro0, CA PI delay=34
5612 00:40:26.417148
5613 00:40:26.420219 [CBTSetCACLKResult] CA Dly = 34
5614 00:40:26.420301 CS Dly: 7 (0~40)
5615 00:40:26.420367
5616 00:40:26.423709 ----->DramcWriteLeveling(PI) begin...
5617 00:40:26.423793 ==
5618 00:40:26.427015 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 00:40:26.433586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 00:40:26.433670 ==
5621 00:40:26.437258 Write leveling (Byte 0): 26 => 26
5622 00:40:26.437341 Write leveling (Byte 1): 28 => 28
5623 00:40:26.440190 DramcWriteLeveling(PI) end<-----
5624 00:40:26.440272
5625 00:40:26.443296 ==
5626 00:40:26.443396 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 00:40:26.450315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 00:40:26.450399 ==
5629 00:40:26.453450 [Gating] SW mode calibration
5630 00:40:26.460002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5631 00:40:26.463620 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5632 00:40:26.469939 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 00:40:26.473549 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 00:40:26.476774 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 00:40:26.483127 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 00:40:26.486553 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 00:40:26.490292 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5638 00:40:26.496838 0 14 24 | B1->B0 | 3131 3232 | 1 0 | (1 0) (1 0)
5639 00:40:26.500092 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5640 00:40:26.503447 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 00:40:26.506812 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 00:40:26.513389 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 00:40:26.516579 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 00:40:26.520257 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 00:40:26.526600 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 00:40:26.529971 0 15 24 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
5647 00:40:26.533398 0 15 28 | B1->B0 | 4342 4545 | 1 0 | (0 0) (0 0)
5648 00:40:26.539702 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 00:40:26.543197 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 00:40:26.546394 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 00:40:26.553431 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 00:40:26.556921 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 00:40:26.559649 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5654 00:40:26.566745 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5655 00:40:26.569525 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5656 00:40:26.573147 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 00:40:26.579566 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 00:40:26.582984 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 00:40:26.586037 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 00:40:26.592931 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 00:40:26.596344 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 00:40:26.599729 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 00:40:26.605941 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 00:40:26.609273 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 00:40:26.612957 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 00:40:26.619408 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 00:40:26.622538 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 00:40:26.626294 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 00:40:26.632648 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5670 00:40:26.636045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5671 00:40:26.639164 Total UI for P1: 0, mck2ui 16
5672 00:40:26.642431 best dqsien dly found for B0: ( 1, 2, 20)
5673 00:40:26.645676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5674 00:40:26.648997 Total UI for P1: 0, mck2ui 16
5675 00:40:26.652194 best dqsien dly found for B1: ( 1, 2, 24)
5676 00:40:26.655914 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5677 00:40:26.659019 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5678 00:40:26.659133
5679 00:40:26.665928 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5680 00:40:26.669084 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5681 00:40:26.669202 [Gating] SW calibration Done
5682 00:40:26.672349 ==
5683 00:40:26.675655 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 00:40:26.678917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 00:40:26.679001 ==
5686 00:40:26.679068 RX Vref Scan: 0
5687 00:40:26.679131
5688 00:40:26.682279 RX Vref 0 -> 0, step: 1
5689 00:40:26.682395
5690 00:40:26.685750 RX Delay -80 -> 252, step: 8
5691 00:40:26.688941 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5692 00:40:26.692432 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5693 00:40:26.695689 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5694 00:40:26.702109 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5695 00:40:26.705320 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5696 00:40:26.708660 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5697 00:40:26.712134 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5698 00:40:26.715419 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5699 00:40:26.721910 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5700 00:40:26.725413 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5701 00:40:26.728666 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5702 00:40:26.732354 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5703 00:40:26.735249 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5704 00:40:26.738839 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5705 00:40:26.745626 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5706 00:40:26.748980 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5707 00:40:26.749064 ==
5708 00:40:26.751925 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 00:40:26.755522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 00:40:26.755607 ==
5711 00:40:26.755674 DQS Delay:
5712 00:40:26.758914 DQS0 = 0, DQS1 = 0
5713 00:40:26.758998 DQM Delay:
5714 00:40:26.762194 DQM0 = 103, DQM1 = 95
5715 00:40:26.762279 DQ Delay:
5716 00:40:26.765329 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5717 00:40:26.768777 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5718 00:40:26.771968 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5719 00:40:26.775708 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5720 00:40:26.775836
5721 00:40:26.775936
5722 00:40:26.776027 ==
5723 00:40:26.779050 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 00:40:26.785296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 00:40:26.785384 ==
5726 00:40:26.785457
5727 00:40:26.785521
5728 00:40:26.785581 TX Vref Scan disable
5729 00:40:26.789308 == TX Byte 0 ==
5730 00:40:26.792505 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5731 00:40:26.799193 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5732 00:40:26.799278 == TX Byte 1 ==
5733 00:40:26.802611 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5734 00:40:26.809296 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5735 00:40:26.809381 ==
5736 00:40:26.812179 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 00:40:26.815966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 00:40:26.816071 ==
5739 00:40:26.816163
5740 00:40:26.816289
5741 00:40:26.819129 TX Vref Scan disable
5742 00:40:26.819224 == TX Byte 0 ==
5743 00:40:26.825727 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5744 00:40:26.829004 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5745 00:40:26.829078 == TX Byte 1 ==
5746 00:40:26.835823 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5747 00:40:26.839152 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5748 00:40:26.839228
5749 00:40:26.839320 [DATLAT]
5750 00:40:26.842437 Freq=933, CH1 RK0
5751 00:40:26.842536
5752 00:40:26.842625 DATLAT Default: 0xd
5753 00:40:26.845265 0, 0xFFFF, sum = 0
5754 00:40:26.845336 1, 0xFFFF, sum = 0
5755 00:40:26.848877 2, 0xFFFF, sum = 0
5756 00:40:26.848974 3, 0xFFFF, sum = 0
5757 00:40:26.852263 4, 0xFFFF, sum = 0
5758 00:40:26.855424 5, 0xFFFF, sum = 0
5759 00:40:26.855493 6, 0xFFFF, sum = 0
5760 00:40:26.859005 7, 0xFFFF, sum = 0
5761 00:40:26.859103 8, 0xFFFF, sum = 0
5762 00:40:26.862044 9, 0xFFFF, sum = 0
5763 00:40:26.862144 10, 0x0, sum = 1
5764 00:40:26.865454 11, 0x0, sum = 2
5765 00:40:26.865529 12, 0x0, sum = 3
5766 00:40:26.865593 13, 0x0, sum = 4
5767 00:40:26.868778 best_step = 11
5768 00:40:26.868850
5769 00:40:26.868912 ==
5770 00:40:26.871899 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 00:40:26.875681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 00:40:26.875782 ==
5773 00:40:26.878930 RX Vref Scan: 1
5774 00:40:26.879027
5775 00:40:26.879116 RX Vref 0 -> 0, step: 1
5776 00:40:26.879203
5777 00:40:26.882449 RX Delay -53 -> 252, step: 4
5778 00:40:26.882525
5779 00:40:26.886033 Set Vref, RX VrefLevel [Byte0]: 50
5780 00:40:26.888869 [Byte1]: 52
5781 00:40:26.893153
5782 00:40:26.893223 Final RX Vref Byte 0 = 50 to rank0
5783 00:40:26.896453 Final RX Vref Byte 1 = 52 to rank0
5784 00:40:26.899788 Final RX Vref Byte 0 = 50 to rank1
5785 00:40:26.903257 Final RX Vref Byte 1 = 52 to rank1==
5786 00:40:26.906370 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 00:40:26.913283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 00:40:26.913357 ==
5789 00:40:26.913422 DQS Delay:
5790 00:40:26.913481 DQS0 = 0, DQS1 = 0
5791 00:40:26.916349 DQM Delay:
5792 00:40:26.916443 DQM0 = 104, DQM1 = 96
5793 00:40:26.919961 DQ Delay:
5794 00:40:26.923189 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5795 00:40:26.926440 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5796 00:40:26.929923 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =90
5797 00:40:26.933007 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =100
5798 00:40:26.933075
5799 00:40:26.933135
5800 00:40:26.939804 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e37, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5801 00:40:26.943272 CH1 RK0: MR19=505, MR18=1E37
5802 00:40:26.949416 CH1_RK0: MR19=0x505, MR18=0x1E37, DQSOSC=404, MR23=63, INC=66, DEC=44
5803 00:40:26.949490
5804 00:40:26.952678 ----->DramcWriteLeveling(PI) begin...
5805 00:40:26.952748 ==
5806 00:40:26.956722 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 00:40:26.959264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 00:40:26.959358 ==
5809 00:40:26.963059 Write leveling (Byte 0): 29 => 29
5810 00:40:26.966011 Write leveling (Byte 1): 29 => 29
5811 00:40:26.969072 DramcWriteLeveling(PI) end<-----
5812 00:40:26.969169
5813 00:40:26.969257 ==
5814 00:40:26.972753 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 00:40:26.979103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 00:40:26.979177 ==
5817 00:40:26.979267 [Gating] SW mode calibration
5818 00:40:26.989236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5819 00:40:26.992427 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5820 00:40:26.995746 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5821 00:40:27.002502 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 00:40:27.006037 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 00:40:27.008989 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 00:40:27.015575 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 00:40:27.018977 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 00:40:27.022214 0 14 24 | B1->B0 | 2f2f 3333 | 0 0 | (0 1) (0 0)
5827 00:40:27.028981 0 14 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 0)
5828 00:40:27.032685 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5829 00:40:27.035718 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 00:40:27.042146 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 00:40:27.045349 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 00:40:27.049024 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 00:40:27.055554 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 00:40:27.058668 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5835 00:40:27.061999 0 15 28 | B1->B0 | 4040 3a3a | 0 0 | (0 0) (0 0)
5836 00:40:27.068504 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 00:40:27.072133 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 00:40:27.075248 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 00:40:27.081953 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 00:40:27.085108 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 00:40:27.088796 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 00:40:27.095844 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 00:40:27.098948 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5844 00:40:27.101993 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 00:40:27.108576 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 00:40:27.111704 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 00:40:27.115185 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 00:40:27.121773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 00:40:27.125150 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:40:27.128362 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 00:40:27.135038 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 00:40:27.138292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 00:40:27.141684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 00:40:27.148499 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 00:40:27.151704 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 00:40:27.155063 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 00:40:27.161813 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 00:40:27.164990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 00:40:27.168779 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5860 00:40:27.171648 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 00:40:27.175032 Total UI for P1: 0, mck2ui 16
5862 00:40:27.178282 best dqsien dly found for B0: ( 1, 2, 28)
5863 00:40:27.181939 Total UI for P1: 0, mck2ui 16
5864 00:40:27.184954 best dqsien dly found for B1: ( 1, 2, 28)
5865 00:40:27.188171 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5866 00:40:27.191546 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5867 00:40:27.194792
5868 00:40:27.198146 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5869 00:40:27.201608 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5870 00:40:27.204690 [Gating] SW calibration Done
5871 00:40:27.204759 ==
5872 00:40:27.208161 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 00:40:27.211477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 00:40:27.211549 ==
5875 00:40:27.211610 RX Vref Scan: 0
5876 00:40:27.214840
5877 00:40:27.214937 RX Vref 0 -> 0, step: 1
5878 00:40:27.215027
5879 00:40:27.218240 RX Delay -80 -> 252, step: 8
5880 00:40:27.221505 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5881 00:40:27.224812 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5882 00:40:27.231382 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5883 00:40:27.234957 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5884 00:40:27.237979 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5885 00:40:27.241250 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5886 00:40:27.244646 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5887 00:40:27.251522 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5888 00:40:27.254668 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5889 00:40:27.257825 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5890 00:40:27.261370 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5891 00:40:27.264702 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5892 00:40:27.268033 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5893 00:40:27.274768 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5894 00:40:27.278099 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5895 00:40:27.281046 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5896 00:40:27.281117 ==
5897 00:40:27.284856 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 00:40:27.287840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 00:40:27.287937 ==
5900 00:40:27.291368 DQS Delay:
5901 00:40:27.291437 DQS0 = 0, DQS1 = 0
5902 00:40:27.294506 DQM Delay:
5903 00:40:27.294603 DQM0 = 102, DQM1 = 95
5904 00:40:27.294692 DQ Delay:
5905 00:40:27.297954 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5906 00:40:27.301238 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5907 00:40:27.304889 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =91
5908 00:40:27.311290 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5909 00:40:27.311386
5910 00:40:27.311475
5911 00:40:27.311562 ==
5912 00:40:27.314499 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 00:40:27.317881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 00:40:27.317977 ==
5915 00:40:27.318067
5916 00:40:27.318155
5917 00:40:27.321619 TX Vref Scan disable
5918 00:40:27.321712 == TX Byte 0 ==
5919 00:40:27.328074 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5920 00:40:27.331424 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5921 00:40:27.331518 == TX Byte 1 ==
5922 00:40:27.337920 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5923 00:40:27.340929 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5924 00:40:27.340997 ==
5925 00:40:27.344593 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 00:40:27.347728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 00:40:27.347825 ==
5928 00:40:27.347915
5929 00:40:27.348001
5930 00:40:27.351336 TX Vref Scan disable
5931 00:40:27.354459 == TX Byte 0 ==
5932 00:40:27.357607 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5933 00:40:27.361093 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5934 00:40:27.364243 == TX Byte 1 ==
5935 00:40:27.367933 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5936 00:40:27.371215 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5937 00:40:27.371314
5938 00:40:27.374322 [DATLAT]
5939 00:40:27.374393 Freq=933, CH1 RK1
5940 00:40:27.374456
5941 00:40:27.377536 DATLAT Default: 0xb
5942 00:40:27.377634 0, 0xFFFF, sum = 0
5943 00:40:27.380940 1, 0xFFFF, sum = 0
5944 00:40:27.381011 2, 0xFFFF, sum = 0
5945 00:40:27.384040 3, 0xFFFF, sum = 0
5946 00:40:27.384139 4, 0xFFFF, sum = 0
5947 00:40:27.387588 5, 0xFFFF, sum = 0
5948 00:40:27.387684 6, 0xFFFF, sum = 0
5949 00:40:27.390928 7, 0xFFFF, sum = 0
5950 00:40:27.391029 8, 0xFFFF, sum = 0
5951 00:40:27.394126 9, 0xFFFF, sum = 0
5952 00:40:27.394208 10, 0x0, sum = 1
5953 00:40:27.397661 11, 0x0, sum = 2
5954 00:40:27.397744 12, 0x0, sum = 3
5955 00:40:27.400736 13, 0x0, sum = 4
5956 00:40:27.400811 best_step = 11
5957 00:40:27.400872
5958 00:40:27.400930 ==
5959 00:40:27.404190 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 00:40:27.410757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 00:40:27.410834 ==
5962 00:40:27.410898 RX Vref Scan: 0
5963 00:40:27.410958
5964 00:40:27.413999 RX Vref 0 -> 0, step: 1
5965 00:40:27.414070
5966 00:40:27.417366 RX Delay -61 -> 252, step: 4
5967 00:40:27.420801 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5968 00:40:27.427626 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5969 00:40:27.430796 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5970 00:40:27.434224 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5971 00:40:27.437420 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5972 00:40:27.440762 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5973 00:40:27.444269 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5974 00:40:27.450502 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5975 00:40:27.453879 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5976 00:40:27.457172 iDelay=199, Bit 9, Center 90 (7 ~ 174) 168
5977 00:40:27.460796 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5978 00:40:27.463848 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5979 00:40:27.470820 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5980 00:40:27.474119 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5981 00:40:27.477639 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5982 00:40:27.480833 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5983 00:40:27.480941 ==
5984 00:40:27.484359 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 00:40:27.487787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 00:40:27.490604 ==
5987 00:40:27.490713 DQS Delay:
5988 00:40:27.490821 DQS0 = 0, DQS1 = 0
5989 00:40:27.493998 DQM Delay:
5990 00:40:27.494118 DQM0 = 105, DQM1 = 98
5991 00:40:27.497506 DQ Delay:
5992 00:40:27.500728 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =104
5993 00:40:27.503803 DQ4 =104, DQ5 =116, DQ6 =112, DQ7 =102
5994 00:40:27.507583 DQ8 =84, DQ9 =90, DQ10 =98, DQ11 =92
5995 00:40:27.510818 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5996 00:40:27.510921
5997 00:40:27.511012
5998 00:40:27.517508 [DQSOSCAuto] RK1, (LSB)MR18= 0x23ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5999 00:40:27.520689 CH1 RK1: MR19=504, MR18=23FF
6000 00:40:27.527416 CH1_RK1: MR19=0x504, MR18=0x23FF, DQSOSC=410, MR23=63, INC=64, DEC=42
6001 00:40:27.530724 [RxdqsGatingPostProcess] freq 933
6002 00:40:27.537281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6003 00:40:27.537365 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 00:40:27.540437 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 00:40:27.543990 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 00:40:27.547171 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 00:40:27.550625 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 00:40:27.553749 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 00:40:27.557515 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 00:40:27.560440 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 00:40:27.563790 Pre-setting of DQS Precalculation
6012 00:40:27.567405 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6013 00:40:27.577160 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6014 00:40:27.584005 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6015 00:40:27.584088
6016 00:40:27.584153
6017 00:40:27.587190 [Calibration Summary] 1866 Mbps
6018 00:40:27.587272 CH 0, Rank 0
6019 00:40:27.590606 SW Impedance : PASS
6020 00:40:27.590689 DUTY Scan : NO K
6021 00:40:27.593982 ZQ Calibration : PASS
6022 00:40:27.597184 Jitter Meter : NO K
6023 00:40:27.597266 CBT Training : PASS
6024 00:40:27.600435 Write leveling : PASS
6025 00:40:27.604041 RX DQS gating : PASS
6026 00:40:27.604124 RX DQ/DQS(RDDQC) : PASS
6027 00:40:27.606975 TX DQ/DQS : PASS
6028 00:40:27.610504 RX DATLAT : PASS
6029 00:40:27.610587 RX DQ/DQS(Engine): PASS
6030 00:40:27.614009 TX OE : NO K
6031 00:40:27.614092 All Pass.
6032 00:40:27.614158
6033 00:40:27.617050 CH 0, Rank 1
6034 00:40:27.617132 SW Impedance : PASS
6035 00:40:27.620436 DUTY Scan : NO K
6036 00:40:27.624283 ZQ Calibration : PASS
6037 00:40:27.624366 Jitter Meter : NO K
6038 00:40:27.627083 CBT Training : PASS
6039 00:40:27.627165 Write leveling : PASS
6040 00:40:27.630146 RX DQS gating : PASS
6041 00:40:27.633926 RX DQ/DQS(RDDQC) : PASS
6042 00:40:27.634008 TX DQ/DQS : PASS
6043 00:40:27.637321 RX DATLAT : PASS
6044 00:40:27.640615 RX DQ/DQS(Engine): PASS
6045 00:40:27.640698 TX OE : NO K
6046 00:40:27.643876 All Pass.
6047 00:40:27.643958
6048 00:40:27.644024 CH 1, Rank 0
6049 00:40:27.647169 SW Impedance : PASS
6050 00:40:27.647251 DUTY Scan : NO K
6051 00:40:27.650310 ZQ Calibration : PASS
6052 00:40:27.654004 Jitter Meter : NO K
6053 00:40:27.654112 CBT Training : PASS
6054 00:40:27.657170 Write leveling : PASS
6055 00:40:27.660272 RX DQS gating : PASS
6056 00:40:27.660354 RX DQ/DQS(RDDQC) : PASS
6057 00:40:27.663783 TX DQ/DQS : PASS
6058 00:40:27.667160 RX DATLAT : PASS
6059 00:40:27.667242 RX DQ/DQS(Engine): PASS
6060 00:40:27.670299 TX OE : NO K
6061 00:40:27.670382 All Pass.
6062 00:40:27.670448
6063 00:40:27.673639 CH 1, Rank 1
6064 00:40:27.673745 SW Impedance : PASS
6065 00:40:27.677107 DUTY Scan : NO K
6066 00:40:27.677190 ZQ Calibration : PASS
6067 00:40:27.680140 Jitter Meter : NO K
6068 00:40:27.683601 CBT Training : PASS
6069 00:40:27.683684 Write leveling : PASS
6070 00:40:27.687018 RX DQS gating : PASS
6071 00:40:27.690114 RX DQ/DQS(RDDQC) : PASS
6072 00:40:27.690219 TX DQ/DQS : PASS
6073 00:40:27.693862 RX DATLAT : PASS
6074 00:40:27.696541 RX DQ/DQS(Engine): PASS
6075 00:40:27.696661 TX OE : NO K
6076 00:40:27.700286 All Pass.
6077 00:40:27.700368
6078 00:40:27.700434 DramC Write-DBI off
6079 00:40:27.703587 PER_BANK_REFRESH: Hybrid Mode
6080 00:40:27.703669 TX_TRACKING: ON
6081 00:40:27.713586 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6082 00:40:27.717165 [FAST_K] Save calibration result to emmc
6083 00:40:27.720227 dramc_set_vcore_voltage set vcore to 650000
6084 00:40:27.723150 Read voltage for 400, 6
6085 00:40:27.723232 Vio18 = 0
6086 00:40:27.726872 Vcore = 650000
6087 00:40:27.726954 Vdram = 0
6088 00:40:27.727019 Vddq = 0
6089 00:40:27.729998 Vmddr = 0
6090 00:40:27.733279 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6091 00:40:27.739997 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6092 00:40:27.740081 MEM_TYPE=3, freq_sel=20
6093 00:40:27.743186 sv_algorithm_assistance_LP4_800
6094 00:40:27.746905 ============ PULL DRAM RESETB DOWN ============
6095 00:40:27.753206 ========== PULL DRAM RESETB DOWN end =========
6096 00:40:27.756675 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6097 00:40:27.759875 ===================================
6098 00:40:27.763527 LPDDR4 DRAM CONFIGURATION
6099 00:40:27.766722 ===================================
6100 00:40:27.766832 EX_ROW_EN[0] = 0x0
6101 00:40:27.769988 EX_ROW_EN[1] = 0x0
6102 00:40:27.773490 LP4Y_EN = 0x0
6103 00:40:27.773572 WORK_FSP = 0x0
6104 00:40:27.776509 WL = 0x2
6105 00:40:27.776631 RL = 0x2
6106 00:40:27.779784 BL = 0x2
6107 00:40:27.779867 RPST = 0x0
6108 00:40:27.783252 RD_PRE = 0x0
6109 00:40:27.783340 WR_PRE = 0x1
6110 00:40:27.786782 WR_PST = 0x0
6111 00:40:27.786892 DBI_WR = 0x0
6112 00:40:27.789959 DBI_RD = 0x0
6113 00:40:27.790042 OTF = 0x1
6114 00:40:27.793196 ===================================
6115 00:40:27.796692 ===================================
6116 00:40:27.799891 ANA top config
6117 00:40:27.803337 ===================================
6118 00:40:27.803420 DLL_ASYNC_EN = 0
6119 00:40:27.806524 ALL_SLAVE_EN = 1
6120 00:40:27.809698 NEW_RANK_MODE = 1
6121 00:40:27.813197 DLL_IDLE_MODE = 1
6122 00:40:27.813279 LP45_APHY_COMB_EN = 1
6123 00:40:27.816436 TX_ODT_DIS = 1
6124 00:40:27.820286 NEW_8X_MODE = 1
6125 00:40:27.823168 ===================================
6126 00:40:27.826518 ===================================
6127 00:40:27.830275 data_rate = 800
6128 00:40:27.833404 CKR = 1
6129 00:40:27.836778 DQ_P2S_RATIO = 4
6130 00:40:27.836860 ===================================
6131 00:40:27.839922 CA_P2S_RATIO = 4
6132 00:40:27.843339 DQ_CA_OPEN = 0
6133 00:40:27.846828 DQ_SEMI_OPEN = 1
6134 00:40:27.850067 CA_SEMI_OPEN = 1
6135 00:40:27.853243 CA_FULL_RATE = 0
6136 00:40:27.853325 DQ_CKDIV4_EN = 0
6137 00:40:27.856879 CA_CKDIV4_EN = 1
6138 00:40:27.860381 CA_PREDIV_EN = 0
6139 00:40:27.863452 PH8_DLY = 0
6140 00:40:27.866635 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6141 00:40:27.869855 DQ_AAMCK_DIV = 0
6142 00:40:27.869937 CA_AAMCK_DIV = 0
6143 00:40:27.873580 CA_ADMCK_DIV = 4
6144 00:40:27.876736 DQ_TRACK_CA_EN = 0
6145 00:40:27.879899 CA_PICK = 800
6146 00:40:27.883367 CA_MCKIO = 400
6147 00:40:27.886912 MCKIO_SEMI = 400
6148 00:40:27.890357 PLL_FREQ = 3016
6149 00:40:27.890440 DQ_UI_PI_RATIO = 32
6150 00:40:27.893486 CA_UI_PI_RATIO = 32
6151 00:40:27.896663 ===================================
6152 00:40:27.900092 ===================================
6153 00:40:27.903202 memory_type:LPDDR4
6154 00:40:27.906742 GP_NUM : 10
6155 00:40:27.906824 SRAM_EN : 1
6156 00:40:27.909915 MD32_EN : 0
6157 00:40:27.913269 ===================================
6158 00:40:27.916463 [ANA_INIT] >>>>>>>>>>>>>>
6159 00:40:27.916550 <<<<<< [CONFIGURE PHASE]: ANA_TX
6160 00:40:27.919982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6161 00:40:27.923144 ===================================
6162 00:40:27.926697 data_rate = 800,PCW = 0X7400
6163 00:40:27.929875 ===================================
6164 00:40:27.933293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6165 00:40:27.939897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6166 00:40:27.949850 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 00:40:27.956802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6168 00:40:27.959998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6169 00:40:27.963159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6170 00:40:27.963242 [ANA_INIT] flow start
6171 00:40:27.966604 [ANA_INIT] PLL >>>>>>>>
6172 00:40:27.970052 [ANA_INIT] PLL <<<<<<<<
6173 00:40:27.970135 [ANA_INIT] MIDPI >>>>>>>>
6174 00:40:27.973382 [ANA_INIT] MIDPI <<<<<<<<
6175 00:40:27.977076 [ANA_INIT] DLL >>>>>>>>
6176 00:40:27.977159 [ANA_INIT] flow end
6177 00:40:27.983112 ============ LP4 DIFF to SE enter ============
6178 00:40:27.986433 ============ LP4 DIFF to SE exit ============
6179 00:40:27.990055 [ANA_INIT] <<<<<<<<<<<<<
6180 00:40:27.993518 [Flow] Enable top DCM control >>>>>
6181 00:40:27.996637 [Flow] Enable top DCM control <<<<<
6182 00:40:27.996720 Enable DLL master slave shuffle
6183 00:40:28.003516 ==============================================================
6184 00:40:28.006656 Gating Mode config
6185 00:40:28.010093 ==============================================================
6186 00:40:28.013517 Config description:
6187 00:40:28.023400 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6188 00:40:28.030088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6189 00:40:28.033574 SELPH_MODE 0: By rank 1: By Phase
6190 00:40:28.039858 ==============================================================
6191 00:40:28.043584 GAT_TRACK_EN = 0
6192 00:40:28.046657 RX_GATING_MODE = 2
6193 00:40:28.050288 RX_GATING_TRACK_MODE = 2
6194 00:40:28.050370 SELPH_MODE = 1
6195 00:40:28.053232 PICG_EARLY_EN = 1
6196 00:40:28.056528 VALID_LAT_VALUE = 1
6197 00:40:28.063239 ==============================================================
6198 00:40:28.066401 Enter into Gating configuration >>>>
6199 00:40:28.070328 Exit from Gating configuration <<<<
6200 00:40:28.073276 Enter into DVFS_PRE_config >>>>>
6201 00:40:28.083212 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6202 00:40:28.086276 Exit from DVFS_PRE_config <<<<<
6203 00:40:28.089636 Enter into PICG configuration >>>>
6204 00:40:28.092718 Exit from PICG configuration <<<<
6205 00:40:28.096082 [RX_INPUT] configuration >>>>>
6206 00:40:28.099439 [RX_INPUT] configuration <<<<<
6207 00:40:28.102766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6208 00:40:28.109341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6209 00:40:28.116231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 00:40:28.122750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 00:40:28.129230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 00:40:28.132703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 00:40:28.139524 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6214 00:40:28.142775 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6215 00:40:28.145877 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6216 00:40:28.149424 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6217 00:40:28.155831 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6218 00:40:28.159123 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 00:40:28.162824 ===================================
6220 00:40:28.166024 LPDDR4 DRAM CONFIGURATION
6221 00:40:28.169191 ===================================
6222 00:40:28.169272 EX_ROW_EN[0] = 0x0
6223 00:40:28.172788 EX_ROW_EN[1] = 0x0
6224 00:40:28.172861 LP4Y_EN = 0x0
6225 00:40:28.175908 WORK_FSP = 0x0
6226 00:40:28.176010 WL = 0x2
6227 00:40:28.179114 RL = 0x2
6228 00:40:28.179209 BL = 0x2
6229 00:40:28.182683 RPST = 0x0
6230 00:40:28.182785 RD_PRE = 0x0
6231 00:40:28.186205 WR_PRE = 0x1
6232 00:40:28.186307 WR_PST = 0x0
6233 00:40:28.193354 DBI_WR = 0x0
6234 00:40:28.193436 DBI_RD = 0x0
6235 00:40:28.193505 OTF = 0x1
6236 00:40:28.196022 ===================================
6237 00:40:28.199237 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6238 00:40:28.202429 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6239 00:40:28.209364 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 00:40:28.212662 ===================================
6241 00:40:28.212760 LPDDR4 DRAM CONFIGURATION
6242 00:40:28.216361 ===================================
6243 00:40:28.219148 EX_ROW_EN[0] = 0x10
6244 00:40:28.222446 EX_ROW_EN[1] = 0x0
6245 00:40:28.222529 LP4Y_EN = 0x0
6246 00:40:28.225894 WORK_FSP = 0x0
6247 00:40:28.225977 WL = 0x2
6248 00:40:28.229539 RL = 0x2
6249 00:40:28.229622 BL = 0x2
6250 00:40:28.232760 RPST = 0x0
6251 00:40:28.232843 RD_PRE = 0x0
6252 00:40:28.235995 WR_PRE = 0x1
6253 00:40:28.236098 WR_PST = 0x0
6254 00:40:28.239272 DBI_WR = 0x0
6255 00:40:28.239370 DBI_RD = 0x0
6256 00:40:28.242455 OTF = 0x1
6257 00:40:28.246121 ===================================
6258 00:40:28.252389 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6259 00:40:28.255731 nWR fixed to 30
6260 00:40:28.255837 [ModeRegInit_LP4] CH0 RK0
6261 00:40:28.259014 [ModeRegInit_LP4] CH0 RK1
6262 00:40:28.262404 [ModeRegInit_LP4] CH1 RK0
6263 00:40:28.265899 [ModeRegInit_LP4] CH1 RK1
6264 00:40:28.265970 match AC timing 19
6265 00:40:28.272434 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6266 00:40:28.275790 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6267 00:40:28.278983 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6268 00:40:28.285699 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6269 00:40:28.289038 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6270 00:40:28.289121 ==
6271 00:40:28.292755 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 00:40:28.295915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 00:40:28.296020 ==
6274 00:40:28.302484 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 00:40:28.308923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6276 00:40:28.312484 [CA 0] Center 36 (8~64) winsize 57
6277 00:40:28.312617 [CA 1] Center 36 (8~64) winsize 57
6278 00:40:28.315677 [CA 2] Center 36 (8~64) winsize 57
6279 00:40:28.319061 [CA 3] Center 36 (8~64) winsize 57
6280 00:40:28.322205 [CA 4] Center 36 (8~64) winsize 57
6281 00:40:28.326082 [CA 5] Center 36 (8~64) winsize 57
6282 00:40:28.326164
6283 00:40:28.329105 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6284 00:40:28.329188
6285 00:40:28.332592 [CATrainingPosCal] consider 1 rank data
6286 00:40:28.335608 u2DelayCellTimex100 = 270/100 ps
6287 00:40:28.339279 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 00:40:28.345603 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 00:40:28.348941 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 00:40:28.352459 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 00:40:28.355720 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 00:40:28.358692 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 00:40:28.358800
6294 00:40:28.362423 CA PerBit enable=1, Macro0, CA PI delay=36
6295 00:40:28.362530
6296 00:40:28.365856 [CBTSetCACLKResult] CA Dly = 36
6297 00:40:28.365929 CS Dly: 1 (0~32)
6298 00:40:28.368701 ==
6299 00:40:28.372031 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 00:40:28.375617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 00:40:28.375715 ==
6302 00:40:28.378767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6303 00:40:28.385599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6304 00:40:28.388763 [CA 0] Center 36 (8~64) winsize 57
6305 00:40:28.392532 [CA 1] Center 36 (8~64) winsize 57
6306 00:40:28.395651 [CA 2] Center 36 (8~64) winsize 57
6307 00:40:28.398978 [CA 3] Center 36 (8~64) winsize 57
6308 00:40:28.402264 [CA 4] Center 36 (8~64) winsize 57
6309 00:40:28.405839 [CA 5] Center 36 (8~64) winsize 57
6310 00:40:28.405935
6311 00:40:28.408788 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6312 00:40:28.408859
6313 00:40:28.412249 [CATrainingPosCal] consider 2 rank data
6314 00:40:28.415618 u2DelayCellTimex100 = 270/100 ps
6315 00:40:28.419118 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 00:40:28.422112 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 00:40:28.425514 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 00:40:28.428748 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 00:40:28.431942 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 00:40:28.438889 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 00:40:28.438972
6322 00:40:28.441936 CA PerBit enable=1, Macro0, CA PI delay=36
6323 00:40:28.442019
6324 00:40:28.445260 [CBTSetCACLKResult] CA Dly = 36
6325 00:40:28.445342 CS Dly: 1 (0~32)
6326 00:40:28.445406
6327 00:40:28.448691 ----->DramcWriteLeveling(PI) begin...
6328 00:40:28.448774 ==
6329 00:40:28.452598 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 00:40:28.455305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 00:40:28.459131 ==
6332 00:40:28.459212 Write leveling (Byte 0): 40 => 8
6333 00:40:28.462028 Write leveling (Byte 1): 32 => 0
6334 00:40:28.465668 DramcWriteLeveling(PI) end<-----
6335 00:40:28.465750
6336 00:40:28.465816 ==
6337 00:40:28.468717 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 00:40:28.475246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 00:40:28.475353 ==
6340 00:40:28.475455 [Gating] SW mode calibration
6341 00:40:28.485527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6342 00:40:28.488448 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6343 00:40:28.495394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6344 00:40:28.498621 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 00:40:28.502146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 00:40:28.505409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 00:40:28.511929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 00:40:28.515340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 00:40:28.518608 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 00:40:28.525429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 00:40:28.528782 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 00:40:28.531808 Total UI for P1: 0, mck2ui 16
6353 00:40:28.535133 best dqsien dly found for B0: ( 0, 14, 24)
6354 00:40:28.538405 Total UI for P1: 0, mck2ui 16
6355 00:40:28.542045 best dqsien dly found for B1: ( 0, 14, 24)
6356 00:40:28.545184 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6357 00:40:28.548377 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6358 00:40:28.548485
6359 00:40:28.552086 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6360 00:40:28.554978 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 00:40:28.558374 [Gating] SW calibration Done
6362 00:40:28.558463 ==
6363 00:40:28.561753 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 00:40:28.568253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 00:40:28.568368 ==
6366 00:40:28.568485 RX Vref Scan: 0
6367 00:40:28.568598
6368 00:40:28.571776 RX Vref 0 -> 0, step: 1
6369 00:40:28.571857
6370 00:40:28.574945 RX Delay -410 -> 252, step: 16
6371 00:40:28.578215 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6372 00:40:28.581890 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6373 00:40:28.588320 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6374 00:40:28.591526 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6375 00:40:28.594824 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6376 00:40:28.598037 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6377 00:40:28.604635 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6378 00:40:28.607980 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6379 00:40:28.611432 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6380 00:40:28.614838 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6381 00:40:28.621567 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6382 00:40:28.624782 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6383 00:40:28.627938 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6384 00:40:28.631215 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6385 00:40:28.637822 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6386 00:40:28.641334 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6387 00:40:28.641416 ==
6388 00:40:28.644575 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 00:40:28.648461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 00:40:28.648603 ==
6391 00:40:28.651523 DQS Delay:
6392 00:40:28.651619 DQS0 = 27, DQS1 = 43
6393 00:40:28.651706 DQM Delay:
6394 00:40:28.654344 DQM0 = 11, DQM1 = 10
6395 00:40:28.654414 DQ Delay:
6396 00:40:28.657846 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6397 00:40:28.661195 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6398 00:40:28.664457 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6399 00:40:28.667835 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6400 00:40:28.667932
6401 00:40:28.668027
6402 00:40:28.668113 ==
6403 00:40:28.671324 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 00:40:28.674770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 00:40:28.678198 ==
6406 00:40:28.678300
6407 00:40:28.678387
6408 00:40:28.678472 TX Vref Scan disable
6409 00:40:28.681428 == TX Byte 0 ==
6410 00:40:28.684658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 00:40:28.688108 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 00:40:28.691207 == TX Byte 1 ==
6413 00:40:28.694438 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6414 00:40:28.697746 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6415 00:40:28.697844 ==
6416 00:40:28.700884 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 00:40:28.707843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 00:40:28.707940 ==
6419 00:40:28.708034
6420 00:40:28.708119
6421 00:40:28.708203 TX Vref Scan disable
6422 00:40:28.711121 == TX Byte 0 ==
6423 00:40:28.714432 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 00:40:28.717611 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 00:40:28.720920 == TX Byte 1 ==
6426 00:40:28.724540 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6427 00:40:28.727668 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6428 00:40:28.727770
6429 00:40:28.731394 [DATLAT]
6430 00:40:28.731491 Freq=400, CH0 RK0
6431 00:40:28.731582
6432 00:40:28.734212 DATLAT Default: 0xf
6433 00:40:28.734312 0, 0xFFFF, sum = 0
6434 00:40:28.737943 1, 0xFFFF, sum = 0
6435 00:40:28.738022 2, 0xFFFF, sum = 0
6436 00:40:28.740894 3, 0xFFFF, sum = 0
6437 00:40:28.740993 4, 0xFFFF, sum = 0
6438 00:40:28.744417 5, 0xFFFF, sum = 0
6439 00:40:28.744520 6, 0xFFFF, sum = 0
6440 00:40:28.747411 7, 0xFFFF, sum = 0
6441 00:40:28.747514 8, 0xFFFF, sum = 0
6442 00:40:28.751019 9, 0xFFFF, sum = 0
6443 00:40:28.754291 10, 0xFFFF, sum = 0
6444 00:40:28.754364 11, 0xFFFF, sum = 0
6445 00:40:28.757783 12, 0xFFFF, sum = 0
6446 00:40:28.757881 13, 0x0, sum = 1
6447 00:40:28.761133 14, 0x0, sum = 2
6448 00:40:28.761204 15, 0x0, sum = 3
6449 00:40:28.761275 16, 0x0, sum = 4
6450 00:40:28.764222 best_step = 14
6451 00:40:28.764320
6452 00:40:28.764408 ==
6453 00:40:28.767866 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 00:40:28.770867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 00:40:28.770976 ==
6456 00:40:28.774289 RX Vref Scan: 1
6457 00:40:28.774372
6458 00:40:28.774448 RX Vref 0 -> 0, step: 1
6459 00:40:28.777691
6460 00:40:28.777774 RX Delay -327 -> 252, step: 8
6461 00:40:28.777841
6462 00:40:28.781527 Set Vref, RX VrefLevel [Byte0]: 58
6463 00:40:28.784270 [Byte1]: 49
6464 00:40:28.789261
6465 00:40:28.789344 Final RX Vref Byte 0 = 58 to rank0
6466 00:40:28.792578 Final RX Vref Byte 1 = 49 to rank0
6467 00:40:28.795674 Final RX Vref Byte 0 = 58 to rank1
6468 00:40:28.799176 Final RX Vref Byte 1 = 49 to rank1==
6469 00:40:28.802387 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 00:40:28.809125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 00:40:28.809209 ==
6472 00:40:28.809276 DQS Delay:
6473 00:40:28.812296 DQS0 = 28, DQS1 = 48
6474 00:40:28.812379 DQM Delay:
6475 00:40:28.812444 DQM0 = 12, DQM1 = 15
6476 00:40:28.816018 DQ Delay:
6477 00:40:28.819282 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6478 00:40:28.819366 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6479 00:40:28.822628 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6480 00:40:28.825849 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6481 00:40:28.825933
6482 00:40:28.829483
6483 00:40:28.835830 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6484 00:40:28.839076 CH0 RK0: MR19=C0C, MR18=B0A8
6485 00:40:28.845691 CH0_RK0: MR19=0xC0C, MR18=0xB0A8, DQSOSC=387, MR23=63, INC=394, DEC=262
6486 00:40:28.845784 ==
6487 00:40:28.848859 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 00:40:28.852432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 00:40:28.852541 ==
6490 00:40:28.855580 [Gating] SW mode calibration
6491 00:40:28.862389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 00:40:28.869125 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6493 00:40:28.872196 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 00:40:28.875695 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 00:40:28.879026 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 00:40:28.885560 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 00:40:28.888941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 00:40:28.895588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 00:40:28.898956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 00:40:28.902394 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 00:40:28.905630 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 00:40:28.908903 Total UI for P1: 0, mck2ui 16
6503 00:40:28.912136 best dqsien dly found for B0: ( 0, 14, 24)
6504 00:40:28.915274 Total UI for P1: 0, mck2ui 16
6505 00:40:28.918853 best dqsien dly found for B1: ( 0, 14, 24)
6506 00:40:28.922406 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6507 00:40:28.928594 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6508 00:40:28.928678
6509 00:40:28.932371 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6510 00:40:28.935430 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 00:40:28.938899 [Gating] SW calibration Done
6512 00:40:28.938983 ==
6513 00:40:28.941953 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 00:40:28.945366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 00:40:28.945451 ==
6516 00:40:28.945518 RX Vref Scan: 0
6517 00:40:28.949085
6518 00:40:28.949169 RX Vref 0 -> 0, step: 1
6519 00:40:28.949236
6520 00:40:28.951969 RX Delay -410 -> 252, step: 16
6521 00:40:28.955622 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6522 00:40:28.962046 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6523 00:40:28.965271 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6524 00:40:28.968796 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6525 00:40:28.972217 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6526 00:40:28.978908 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6527 00:40:28.982458 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6528 00:40:28.985574 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6529 00:40:28.988782 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6530 00:40:28.995708 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6531 00:40:28.998779 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6532 00:40:29.002323 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6533 00:40:29.005570 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6534 00:40:29.012249 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6535 00:40:29.015610 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6536 00:40:29.018806 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6537 00:40:29.018891 ==
6538 00:40:29.022316 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 00:40:29.025469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 00:40:29.028814 ==
6541 00:40:29.028898 DQS Delay:
6542 00:40:29.028965 DQS0 = 27, DQS1 = 43
6543 00:40:29.031950 DQM Delay:
6544 00:40:29.032033 DQM0 = 9, DQM1 = 14
6545 00:40:29.035569 DQ Delay:
6546 00:40:29.035652 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6547 00:40:29.038592 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6548 00:40:29.042461 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6549 00:40:29.045432 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6550 00:40:29.045516
6551 00:40:29.045583
6552 00:40:29.045645 ==
6553 00:40:29.048873 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 00:40:29.055543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 00:40:29.055628 ==
6556 00:40:29.055696
6557 00:40:29.055759
6558 00:40:29.055819 TX Vref Scan disable
6559 00:40:29.058968 == TX Byte 0 ==
6560 00:40:29.062192 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6561 00:40:29.065278 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6562 00:40:29.068784 == TX Byte 1 ==
6563 00:40:29.072173 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6564 00:40:29.075625 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6565 00:40:29.075710 ==
6566 00:40:29.078463 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 00:40:29.085221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 00:40:29.085306 ==
6569 00:40:29.085374
6570 00:40:29.085435
6571 00:40:29.085495 TX Vref Scan disable
6572 00:40:29.088732 == TX Byte 0 ==
6573 00:40:29.091971 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6574 00:40:29.095231 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6575 00:40:29.098433 == TX Byte 1 ==
6576 00:40:29.101807 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6577 00:40:29.105054 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6578 00:40:29.105138
6579 00:40:29.108699 [DATLAT]
6580 00:40:29.108782 Freq=400, CH0 RK1
6581 00:40:29.108850
6582 00:40:29.112145 DATLAT Default: 0xe
6583 00:40:29.112229 0, 0xFFFF, sum = 0
6584 00:40:29.115010 1, 0xFFFF, sum = 0
6585 00:40:29.115096 2, 0xFFFF, sum = 0
6586 00:40:29.118541 3, 0xFFFF, sum = 0
6587 00:40:29.118627 4, 0xFFFF, sum = 0
6588 00:40:29.122044 5, 0xFFFF, sum = 0
6589 00:40:29.122130 6, 0xFFFF, sum = 0
6590 00:40:29.125057 7, 0xFFFF, sum = 0
6591 00:40:29.125142 8, 0xFFFF, sum = 0
6592 00:40:29.128577 9, 0xFFFF, sum = 0
6593 00:40:29.131942 10, 0xFFFF, sum = 0
6594 00:40:29.132028 11, 0xFFFF, sum = 0
6595 00:40:29.134962 12, 0xFFFF, sum = 0
6596 00:40:29.135047 13, 0x0, sum = 1
6597 00:40:29.138455 14, 0x0, sum = 2
6598 00:40:29.138540 15, 0x0, sum = 3
6599 00:40:29.138608 16, 0x0, sum = 4
6600 00:40:29.141623 best_step = 14
6601 00:40:29.141707
6602 00:40:29.141774 ==
6603 00:40:29.145147 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 00:40:29.148359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 00:40:29.148443 ==
6606 00:40:29.151841 RX Vref Scan: 0
6607 00:40:29.151925
6608 00:40:29.151992 RX Vref 0 -> 0, step: 1
6609 00:40:29.154921
6610 00:40:29.155009 RX Delay -327 -> 252, step: 8
6611 00:40:29.163393 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6612 00:40:29.166695 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6613 00:40:29.169884 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6614 00:40:29.176712 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6615 00:40:29.179867 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6616 00:40:29.183099 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6617 00:40:29.186466 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6618 00:40:29.189694 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6619 00:40:29.196377 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6620 00:40:29.199873 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6621 00:40:29.203174 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6622 00:40:29.206661 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6623 00:40:29.213493 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6624 00:40:29.216353 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6625 00:40:29.219678 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6626 00:40:29.226656 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6627 00:40:29.226735 ==
6628 00:40:29.229531 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 00:40:29.232742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 00:40:29.232816 ==
6631 00:40:29.232879 DQS Delay:
6632 00:40:29.236458 DQS0 = 28, DQS1 = 40
6633 00:40:29.236598 DQM Delay:
6634 00:40:29.239433 DQM0 = 10, DQM1 = 11
6635 00:40:29.239510 DQ Delay:
6636 00:40:29.243059 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6637 00:40:29.246329 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6638 00:40:29.249381 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6639 00:40:29.253054 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6640 00:40:29.253125
6641 00:40:29.253186
6642 00:40:29.259300 [DQSOSCAuto] RK1, (LSB)MR18= 0xc071, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6643 00:40:29.262799 CH0 RK1: MR19=C0C, MR18=C071
6644 00:40:29.269242 CH0_RK1: MR19=0xC0C, MR18=0xC071, DQSOSC=386, MR23=63, INC=396, DEC=264
6645 00:40:29.272804 [RxdqsGatingPostProcess] freq 400
6646 00:40:29.279748 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6647 00:40:29.279824 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 00:40:29.283071 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 00:40:29.285931 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 00:40:29.289256 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 00:40:29.292573 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 00:40:29.296275 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 00:40:29.299227 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 00:40:29.302865 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 00:40:29.305795 Pre-setting of DQS Precalculation
6656 00:40:29.312705 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6657 00:40:29.312786 ==
6658 00:40:29.315967 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 00:40:29.319439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 00:40:29.319520 ==
6661 00:40:29.326030 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 00:40:29.329442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6663 00:40:29.332440 [CA 0] Center 36 (8~64) winsize 57
6664 00:40:29.335792 [CA 1] Center 36 (8~64) winsize 57
6665 00:40:29.339268 [CA 2] Center 36 (8~64) winsize 57
6666 00:40:29.342531 [CA 3] Center 36 (8~64) winsize 57
6667 00:40:29.346001 [CA 4] Center 36 (8~64) winsize 57
6668 00:40:29.349158 [CA 5] Center 36 (8~64) winsize 57
6669 00:40:29.349240
6670 00:40:29.352625 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6671 00:40:29.352699
6672 00:40:29.355979 [CATrainingPosCal] consider 1 rank data
6673 00:40:29.359337 u2DelayCellTimex100 = 270/100 ps
6674 00:40:29.362572 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 00:40:29.366198 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 00:40:29.369391 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 00:40:29.372633 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 00:40:29.376130 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 00:40:29.382951 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 00:40:29.383034
6681 00:40:29.386076 CA PerBit enable=1, Macro0, CA PI delay=36
6682 00:40:29.386148
6683 00:40:29.389152 [CBTSetCACLKResult] CA Dly = 36
6684 00:40:29.389222 CS Dly: 1 (0~32)
6685 00:40:29.389290 ==
6686 00:40:29.392499 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 00:40:29.396049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 00:40:29.399478 ==
6689 00:40:29.402664 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6690 00:40:29.409529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6691 00:40:29.413174 [CA 0] Center 36 (8~64) winsize 57
6692 00:40:29.416275 [CA 1] Center 36 (8~64) winsize 57
6693 00:40:29.419525 [CA 2] Center 36 (8~64) winsize 57
6694 00:40:29.422621 [CA 3] Center 36 (8~64) winsize 57
6695 00:40:29.426324 [CA 4] Center 36 (8~64) winsize 57
6696 00:40:29.429662 [CA 5] Center 36 (8~64) winsize 57
6697 00:40:29.429735
6698 00:40:29.433313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6699 00:40:29.433393
6700 00:40:29.436155 [CATrainingPosCal] consider 2 rank data
6701 00:40:29.439288 u2DelayCellTimex100 = 270/100 ps
6702 00:40:29.442861 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 00:40:29.446251 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 00:40:29.449353 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 00:40:29.453035 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 00:40:29.456135 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 00:40:29.459632 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 00:40:29.459703
6709 00:40:29.462690 CA PerBit enable=1, Macro0, CA PI delay=36
6710 00:40:29.462800
6711 00:40:29.466214 [CBTSetCACLKResult] CA Dly = 36
6712 00:40:29.469394 CS Dly: 1 (0~32)
6713 00:40:29.469466
6714 00:40:29.473116 ----->DramcWriteLeveling(PI) begin...
6715 00:40:29.473188 ==
6716 00:40:29.476229 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 00:40:29.479206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 00:40:29.479280 ==
6719 00:40:29.482776 Write leveling (Byte 0): 40 => 8
6720 00:40:29.486277 Write leveling (Byte 1): 32 => 0
6721 00:40:29.489295 DramcWriteLeveling(PI) end<-----
6722 00:40:29.489368
6723 00:40:29.489430 ==
6724 00:40:29.492992 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 00:40:29.495801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 00:40:29.495872 ==
6727 00:40:29.499260 [Gating] SW mode calibration
6728 00:40:29.505779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6729 00:40:29.512498 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6730 00:40:29.515789 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6731 00:40:29.519038 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 00:40:29.525851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 00:40:29.529129 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 00:40:29.532420 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 00:40:29.538882 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 00:40:29.542588 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 00:40:29.545761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 00:40:29.552177 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 00:40:29.555816 Total UI for P1: 0, mck2ui 16
6740 00:40:29.558894 best dqsien dly found for B0: ( 0, 14, 24)
6741 00:40:29.558968 Total UI for P1: 0, mck2ui 16
6742 00:40:29.566068 best dqsien dly found for B1: ( 0, 14, 24)
6743 00:40:29.569302 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6744 00:40:29.572465 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6745 00:40:29.572573
6746 00:40:29.576071 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6747 00:40:29.579078 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 00:40:29.582668 [Gating] SW calibration Done
6749 00:40:29.582752 ==
6750 00:40:29.586102 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 00:40:29.589107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 00:40:29.589194 ==
6753 00:40:29.592381 RX Vref Scan: 0
6754 00:40:29.592464
6755 00:40:29.592530 RX Vref 0 -> 0, step: 1
6756 00:40:29.592635
6757 00:40:29.596223 RX Delay -410 -> 252, step: 16
6758 00:40:29.602557 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6759 00:40:29.605759 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6760 00:40:29.609446 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6761 00:40:29.612588 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6762 00:40:29.618974 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6763 00:40:29.622475 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6764 00:40:29.625977 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6765 00:40:29.628970 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6766 00:40:29.635938 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6767 00:40:29.639109 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6768 00:40:29.642558 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6769 00:40:29.645863 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6770 00:40:29.652420 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6771 00:40:29.655779 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6772 00:40:29.659090 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6773 00:40:29.662307 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6774 00:40:29.662390 ==
6775 00:40:29.665528 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 00:40:29.672498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 00:40:29.672608 ==
6778 00:40:29.672676 DQS Delay:
6779 00:40:29.675589 DQS0 = 27, DQS1 = 35
6780 00:40:29.675676 DQM Delay:
6781 00:40:29.675757 DQM0 = 5, DQM1 = 8
6782 00:40:29.679154 DQ Delay:
6783 00:40:29.682694 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6784 00:40:29.682777 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6785 00:40:29.685647 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6786 00:40:29.689387 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6787 00:40:29.689470
6788 00:40:29.689535
6789 00:40:29.692473 ==
6790 00:40:29.692583 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 00:40:29.699296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 00:40:29.699379 ==
6793 00:40:29.699445
6794 00:40:29.699505
6795 00:40:29.702376 TX Vref Scan disable
6796 00:40:29.702464 == TX Byte 0 ==
6797 00:40:29.705790 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 00:40:29.712644 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 00:40:29.712727 == TX Byte 1 ==
6800 00:40:29.715926 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6801 00:40:29.722214 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6802 00:40:29.722298 ==
6803 00:40:29.725965 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 00:40:29.729075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 00:40:29.729159 ==
6806 00:40:29.729225
6807 00:40:29.729285
6808 00:40:29.732246 TX Vref Scan disable
6809 00:40:29.732328 == TX Byte 0 ==
6810 00:40:29.735576 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 00:40:29.742383 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 00:40:29.742466 == TX Byte 1 ==
6813 00:40:29.745654 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6814 00:40:29.752179 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6815 00:40:29.752263
6816 00:40:29.752329 [DATLAT]
6817 00:40:29.752396 Freq=400, CH1 RK0
6818 00:40:29.752475
6819 00:40:29.755738 DATLAT Default: 0xf
6820 00:40:29.759116 0, 0xFFFF, sum = 0
6821 00:40:29.759201 1, 0xFFFF, sum = 0
6822 00:40:29.762209 2, 0xFFFF, sum = 0
6823 00:40:29.762294 3, 0xFFFF, sum = 0
6824 00:40:29.765620 4, 0xFFFF, sum = 0
6825 00:40:29.765706 5, 0xFFFF, sum = 0
6826 00:40:29.768950 6, 0xFFFF, sum = 0
6827 00:40:29.769036 7, 0xFFFF, sum = 0
6828 00:40:29.772395 8, 0xFFFF, sum = 0
6829 00:40:29.772479 9, 0xFFFF, sum = 0
6830 00:40:29.775921 10, 0xFFFF, sum = 0
6831 00:40:29.776006 11, 0xFFFF, sum = 0
6832 00:40:29.779115 12, 0xFFFF, sum = 0
6833 00:40:29.779200 13, 0x0, sum = 1
6834 00:40:29.782164 14, 0x0, sum = 2
6835 00:40:29.782249 15, 0x0, sum = 3
6836 00:40:29.785863 16, 0x0, sum = 4
6837 00:40:29.785948 best_step = 14
6838 00:40:29.786016
6839 00:40:29.786078 ==
6840 00:40:29.788979 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 00:40:29.792368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 00:40:29.795491 ==
6843 00:40:29.795574 RX Vref Scan: 1
6844 00:40:29.795641
6845 00:40:29.798988 RX Vref 0 -> 0, step: 1
6846 00:40:29.799073
6847 00:40:29.802287 RX Delay -311 -> 252, step: 8
6848 00:40:29.802371
6849 00:40:29.805753 Set Vref, RX VrefLevel [Byte0]: 50
6850 00:40:29.809112 [Byte1]: 52
6851 00:40:29.809197
6852 00:40:29.812533 Final RX Vref Byte 0 = 50 to rank0
6853 00:40:29.815683 Final RX Vref Byte 1 = 52 to rank0
6854 00:40:29.818788 Final RX Vref Byte 0 = 50 to rank1
6855 00:40:29.822340 Final RX Vref Byte 1 = 52 to rank1==
6856 00:40:29.825665 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 00:40:29.828901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 00:40:29.828986 ==
6859 00:40:29.832484 DQS Delay:
6860 00:40:29.832607 DQS0 = 32, DQS1 = 40
6861 00:40:29.835584 DQM Delay:
6862 00:40:29.835667 DQM0 = 11, DQM1 = 12
6863 00:40:29.835734 DQ Delay:
6864 00:40:29.839264 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6865 00:40:29.842493 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6866 00:40:29.845562 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6867 00:40:29.848724 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6868 00:40:29.848809
6869 00:40:29.848875
6870 00:40:29.858789 [DQSOSCAuto] RK0, (LSB)MR18= 0x9dd8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6871 00:40:29.858875 CH1 RK0: MR19=C0C, MR18=9DD8
6872 00:40:29.865389 CH1_RK0: MR19=0xC0C, MR18=0x9DD8, DQSOSC=383, MR23=63, INC=402, DEC=268
6873 00:40:29.865475 ==
6874 00:40:29.868965 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 00:40:29.875674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 00:40:29.875759 ==
6877 00:40:29.875827 [Gating] SW mode calibration
6878 00:40:29.885434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6879 00:40:29.888858 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6880 00:40:29.891988 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6881 00:40:29.898448 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 00:40:29.902059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 00:40:29.905507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 00:40:29.912059 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 00:40:29.915404 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 00:40:29.919108 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 00:40:29.925664 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 00:40:29.928682 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 00:40:29.932386 Total UI for P1: 0, mck2ui 16
6890 00:40:29.935449 best dqsien dly found for B0: ( 0, 14, 24)
6891 00:40:29.938600 Total UI for P1: 0, mck2ui 16
6892 00:40:29.942226 best dqsien dly found for B1: ( 0, 14, 24)
6893 00:40:29.945351 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6894 00:40:29.948867 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6895 00:40:29.948938
6896 00:40:29.952241 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6897 00:40:29.955470 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 00:40:29.958861 [Gating] SW calibration Done
6899 00:40:29.958941 ==
6900 00:40:29.962064 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 00:40:29.965612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 00:40:29.968938 ==
6903 00:40:29.969012 RX Vref Scan: 0
6904 00:40:29.969075
6905 00:40:29.972185 RX Vref 0 -> 0, step: 1
6906 00:40:29.972268
6907 00:40:29.975179 RX Delay -410 -> 252, step: 16
6908 00:40:29.978625 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6909 00:40:29.981788 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6910 00:40:29.985414 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6911 00:40:29.991822 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6912 00:40:29.995252 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6913 00:40:29.998735 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6914 00:40:30.001997 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6915 00:40:30.008206 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6916 00:40:30.011727 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6917 00:40:30.014913 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6918 00:40:30.018627 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6919 00:40:30.025075 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6920 00:40:30.028685 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6921 00:40:30.031578 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6922 00:40:30.038132 iDelay=230, Bit 14, Center -19 (-266 ~ 229) 496
6923 00:40:30.041831 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6924 00:40:30.041910 ==
6925 00:40:30.044624 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 00:40:30.048194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 00:40:30.048266 ==
6928 00:40:30.051364 DQS Delay:
6929 00:40:30.051434 DQS0 = 35, DQS1 = 43
6930 00:40:30.051495 DQM Delay:
6931 00:40:30.054919 DQM0 = 16, DQM1 = 20
6932 00:40:30.054989 DQ Delay:
6933 00:40:30.058089 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6934 00:40:30.061313 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6935 00:40:30.064997 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6936 00:40:30.068080 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6937 00:40:30.068162
6938 00:40:30.068224
6939 00:40:30.068283 ==
6940 00:40:30.071596 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 00:40:30.078136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 00:40:30.078211 ==
6943 00:40:30.078274
6944 00:40:30.078333
6945 00:40:30.078398 TX Vref Scan disable
6946 00:40:30.081471 == TX Byte 0 ==
6947 00:40:30.085204 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6948 00:40:30.088057 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6949 00:40:30.091305 == TX Byte 1 ==
6950 00:40:30.094915 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6951 00:40:30.098132 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6952 00:40:30.098218 ==
6953 00:40:30.101478 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 00:40:30.108249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 00:40:30.108333 ==
6956 00:40:30.108399
6957 00:40:30.108503
6958 00:40:30.108644 TX Vref Scan disable
6959 00:40:30.111338 == TX Byte 0 ==
6960 00:40:30.114885 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6961 00:40:30.117882 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6962 00:40:30.121562 == TX Byte 1 ==
6963 00:40:30.124848 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6964 00:40:30.128094 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6965 00:40:30.128178
6966 00:40:30.131353 [DATLAT]
6967 00:40:30.131435 Freq=400, CH1 RK1
6968 00:40:30.131502
6969 00:40:30.134870 DATLAT Default: 0xe
6970 00:40:30.134953 0, 0xFFFF, sum = 0
6971 00:40:30.137870 1, 0xFFFF, sum = 0
6972 00:40:30.137955 2, 0xFFFF, sum = 0
6973 00:40:30.141277 3, 0xFFFF, sum = 0
6974 00:40:30.141362 4, 0xFFFF, sum = 0
6975 00:40:30.144815 5, 0xFFFF, sum = 0
6976 00:40:30.144900 6, 0xFFFF, sum = 0
6977 00:40:30.148015 7, 0xFFFF, sum = 0
6978 00:40:30.148098 8, 0xFFFF, sum = 0
6979 00:40:30.151386 9, 0xFFFF, sum = 0
6980 00:40:30.151471 10, 0xFFFF, sum = 0
6981 00:40:30.154790 11, 0xFFFF, sum = 0
6982 00:40:30.154875 12, 0xFFFF, sum = 0
6983 00:40:30.157875 13, 0x0, sum = 1
6984 00:40:30.157959 14, 0x0, sum = 2
6985 00:40:30.161255 15, 0x0, sum = 3
6986 00:40:30.161339 16, 0x0, sum = 4
6987 00:40:30.164807 best_step = 14
6988 00:40:30.164916
6989 00:40:30.165009 ==
6990 00:40:30.167844 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 00:40:30.171306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 00:40:30.171390 ==
6993 00:40:30.174577 RX Vref Scan: 0
6994 00:40:30.174660
6995 00:40:30.174726 RX Vref 0 -> 0, step: 1
6996 00:40:30.174789
6997 00:40:30.178073 RX Delay -327 -> 252, step: 8
6998 00:40:30.186071 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6999 00:40:30.189472 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7000 00:40:30.192469 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7001 00:40:30.195757 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7002 00:40:30.202222 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7003 00:40:30.205793 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7004 00:40:30.209230 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7005 00:40:30.212246 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7006 00:40:30.219274 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7007 00:40:30.222621 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7008 00:40:30.225435 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7009 00:40:30.232167 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7010 00:40:30.235793 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7011 00:40:30.239016 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7012 00:40:30.242101 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7013 00:40:30.248871 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7014 00:40:30.248968 ==
7015 00:40:30.252288 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 00:40:30.255415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 00:40:30.255501 ==
7018 00:40:30.255569 DQS Delay:
7019 00:40:30.259229 DQS0 = 28, DQS1 = 36
7020 00:40:30.259318 DQM Delay:
7021 00:40:30.262106 DQM0 = 8, DQM1 = 11
7022 00:40:30.262191 DQ Delay:
7023 00:40:30.265625 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
7024 00:40:30.268853 DQ4 =12, DQ5 =16, DQ6 =16, DQ7 =8
7025 00:40:30.272360 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7026 00:40:30.275402 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7027 00:40:30.275500
7028 00:40:30.275569
7029 00:40:30.282164 [DQSOSCAuto] RK1, (LSB)MR18= 0xb159, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
7030 00:40:30.285881 CH1 RK1: MR19=C0C, MR18=B159
7031 00:40:30.292792 CH1_RK1: MR19=0xC0C, MR18=0xB159, DQSOSC=387, MR23=63, INC=394, DEC=262
7032 00:40:30.295480 [RxdqsGatingPostProcess] freq 400
7033 00:40:30.302067 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7034 00:40:30.302171 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 00:40:30.305296 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 00:40:30.308737 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 00:40:30.312082 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 00:40:30.315293 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 00:40:30.318947 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 00:40:30.322135 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 00:40:30.325424 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 00:40:30.328506 Pre-setting of DQS Precalculation
7043 00:40:30.335254 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7044 00:40:30.341988 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7045 00:40:30.348841 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7046 00:40:30.348951
7047 00:40:30.349021
7048 00:40:30.352027 [Calibration Summary] 800 Mbps
7049 00:40:30.352112 CH 0, Rank 0
7050 00:40:30.355481 SW Impedance : PASS
7051 00:40:30.355574 DUTY Scan : NO K
7052 00:40:30.358525 ZQ Calibration : PASS
7053 00:40:30.362258 Jitter Meter : NO K
7054 00:40:30.362350 CBT Training : PASS
7055 00:40:30.365632 Write leveling : PASS
7056 00:40:30.369060 RX DQS gating : PASS
7057 00:40:30.369161 RX DQ/DQS(RDDQC) : PASS
7058 00:40:30.372046 TX DQ/DQS : PASS
7059 00:40:30.375150 RX DATLAT : PASS
7060 00:40:30.375256 RX DQ/DQS(Engine): PASS
7061 00:40:30.378619 TX OE : NO K
7062 00:40:30.378745 All Pass.
7063 00:40:30.378814
7064 00:40:30.381886 CH 0, Rank 1
7065 00:40:30.381971 SW Impedance : PASS
7066 00:40:30.385459 DUTY Scan : NO K
7067 00:40:30.388453 ZQ Calibration : PASS
7068 00:40:30.388541 Jitter Meter : NO K
7069 00:40:30.392019 CBT Training : PASS
7070 00:40:30.392106 Write leveling : NO K
7071 00:40:30.395587 RX DQS gating : PASS
7072 00:40:30.398625 RX DQ/DQS(RDDQC) : PASS
7073 00:40:30.398787 TX DQ/DQS : PASS
7074 00:40:30.402078 RX DATLAT : PASS
7075 00:40:30.405257 RX DQ/DQS(Engine): PASS
7076 00:40:30.405350 TX OE : NO K
7077 00:40:30.408945 All Pass.
7078 00:40:30.409029
7079 00:40:30.409096 CH 1, Rank 0
7080 00:40:30.412051 SW Impedance : PASS
7081 00:40:30.412161 DUTY Scan : NO K
7082 00:40:30.415280 ZQ Calibration : PASS
7083 00:40:30.418659 Jitter Meter : NO K
7084 00:40:30.418744 CBT Training : PASS
7085 00:40:30.422111 Write leveling : PASS
7086 00:40:30.425480 RX DQS gating : PASS
7087 00:40:30.425569 RX DQ/DQS(RDDQC) : PASS
7088 00:40:30.428415 TX DQ/DQS : PASS
7089 00:40:30.431658 RX DATLAT : PASS
7090 00:40:30.431743 RX DQ/DQS(Engine): PASS
7091 00:40:30.435194 TX OE : NO K
7092 00:40:30.435278 All Pass.
7093 00:40:30.435345
7094 00:40:30.438564 CH 1, Rank 1
7095 00:40:30.438647 SW Impedance : PASS
7096 00:40:30.441939 DUTY Scan : NO K
7097 00:40:30.442023 ZQ Calibration : PASS
7098 00:40:30.445586 Jitter Meter : NO K
7099 00:40:30.448518 CBT Training : PASS
7100 00:40:30.448646 Write leveling : NO K
7101 00:40:30.452393 RX DQS gating : PASS
7102 00:40:30.455437 RX DQ/DQS(RDDQC) : PASS
7103 00:40:30.455521 TX DQ/DQS : PASS
7104 00:40:30.458865 RX DATLAT : PASS
7105 00:40:30.461824 RX DQ/DQS(Engine): PASS
7106 00:40:30.461908 TX OE : NO K
7107 00:40:30.465345 All Pass.
7108 00:40:30.465428
7109 00:40:30.465494 DramC Write-DBI off
7110 00:40:30.468303 PER_BANK_REFRESH: Hybrid Mode
7111 00:40:30.468387 TX_TRACKING: ON
7112 00:40:30.478542 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7113 00:40:30.481789 [FAST_K] Save calibration result to emmc
7114 00:40:30.485231 dramc_set_vcore_voltage set vcore to 725000
7115 00:40:30.488814 Read voltage for 1600, 0
7116 00:40:30.488897 Vio18 = 0
7117 00:40:30.491715 Vcore = 725000
7118 00:40:30.491799 Vdram = 0
7119 00:40:30.491865 Vddq = 0
7120 00:40:30.495528 Vmddr = 0
7121 00:40:30.498347 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7122 00:40:30.505105 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7123 00:40:30.505189 MEM_TYPE=3, freq_sel=13
7124 00:40:30.508502 sv_algorithm_assistance_LP4_3733
7125 00:40:30.511716 ============ PULL DRAM RESETB DOWN ============
7126 00:40:30.518626 ========== PULL DRAM RESETB DOWN end =========
7127 00:40:30.521481 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7128 00:40:30.524961 ===================================
7129 00:40:30.528132 LPDDR4 DRAM CONFIGURATION
7130 00:40:30.531561 ===================================
7131 00:40:30.531645 EX_ROW_EN[0] = 0x0
7132 00:40:30.535145 EX_ROW_EN[1] = 0x0
7133 00:40:30.535228 LP4Y_EN = 0x0
7134 00:40:30.538768 WORK_FSP = 0x1
7135 00:40:30.541628 WL = 0x5
7136 00:40:30.541711 RL = 0x5
7137 00:40:30.544766 BL = 0x2
7138 00:40:30.544849 RPST = 0x0
7139 00:40:30.548356 RD_PRE = 0x0
7140 00:40:30.548439 WR_PRE = 0x1
7141 00:40:30.551644 WR_PST = 0x1
7142 00:40:30.551727 DBI_WR = 0x0
7143 00:40:30.555168 DBI_RD = 0x0
7144 00:40:30.555251 OTF = 0x1
7145 00:40:30.558272 ===================================
7146 00:40:30.561680 ===================================
7147 00:40:30.564874 ANA top config
7148 00:40:30.568318 ===================================
7149 00:40:30.568403 DLL_ASYNC_EN = 0
7150 00:40:30.571511 ALL_SLAVE_EN = 0
7151 00:40:30.574774 NEW_RANK_MODE = 1
7152 00:40:30.578320 DLL_IDLE_MODE = 1
7153 00:40:30.578404 LP45_APHY_COMB_EN = 1
7154 00:40:30.581691 TX_ODT_DIS = 0
7155 00:40:30.584960 NEW_8X_MODE = 1
7156 00:40:30.588346 ===================================
7157 00:40:30.591778 ===================================
7158 00:40:30.594875 data_rate = 3200
7159 00:40:30.598217 CKR = 1
7160 00:40:30.601619 DQ_P2S_RATIO = 8
7161 00:40:30.604932 ===================================
7162 00:40:30.605017 CA_P2S_RATIO = 8
7163 00:40:30.608413 DQ_CA_OPEN = 0
7164 00:40:30.611662 DQ_SEMI_OPEN = 0
7165 00:40:30.614852 CA_SEMI_OPEN = 0
7166 00:40:30.618258 CA_FULL_RATE = 0
7167 00:40:30.618381 DQ_CKDIV4_EN = 0
7168 00:40:30.621343 CA_CKDIV4_EN = 0
7169 00:40:30.624861 CA_PREDIV_EN = 0
7170 00:40:30.628089 PH8_DLY = 12
7171 00:40:30.631448 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7172 00:40:30.634606 DQ_AAMCK_DIV = 4
7173 00:40:30.637942 CA_AAMCK_DIV = 4
7174 00:40:30.638027 CA_ADMCK_DIV = 4
7175 00:40:30.641267 DQ_TRACK_CA_EN = 0
7176 00:40:30.644742 CA_PICK = 1600
7177 00:40:30.647955 CA_MCKIO = 1600
7178 00:40:30.651434 MCKIO_SEMI = 0
7179 00:40:30.654626 PLL_FREQ = 3068
7180 00:40:30.658001 DQ_UI_PI_RATIO = 32
7181 00:40:30.658088 CA_UI_PI_RATIO = 0
7182 00:40:30.661245 ===================================
7183 00:40:30.664699 ===================================
7184 00:40:30.667793 memory_type:LPDDR4
7185 00:40:30.671322 GP_NUM : 10
7186 00:40:30.671406 SRAM_EN : 1
7187 00:40:30.674755 MD32_EN : 0
7188 00:40:30.678019 ===================================
7189 00:40:30.681613 [ANA_INIT] >>>>>>>>>>>>>>
7190 00:40:30.684543 <<<<<< [CONFIGURE PHASE]: ANA_TX
7191 00:40:30.687967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7192 00:40:30.691441 ===================================
7193 00:40:30.691526 data_rate = 3200,PCW = 0X7600
7194 00:40:30.694635 ===================================
7195 00:40:30.697819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7196 00:40:30.704474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7197 00:40:30.711322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 00:40:30.714700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7199 00:40:30.718478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7200 00:40:30.721193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7201 00:40:30.724613 [ANA_INIT] flow start
7202 00:40:30.724697 [ANA_INIT] PLL >>>>>>>>
7203 00:40:30.727952 [ANA_INIT] PLL <<<<<<<<
7204 00:40:30.731438 [ANA_INIT] MIDPI >>>>>>>>
7205 00:40:30.734628 [ANA_INIT] MIDPI <<<<<<<<
7206 00:40:30.734713 [ANA_INIT] DLL >>>>>>>>
7207 00:40:30.737770 [ANA_INIT] DLL <<<<<<<<
7208 00:40:30.737854 [ANA_INIT] flow end
7209 00:40:30.744570 ============ LP4 DIFF to SE enter ============
7210 00:40:30.747705 ============ LP4 DIFF to SE exit ============
7211 00:40:30.751226 [ANA_INIT] <<<<<<<<<<<<<
7212 00:40:30.754523 [Flow] Enable top DCM control >>>>>
7213 00:40:30.758091 [Flow] Enable top DCM control <<<<<
7214 00:40:30.758176 Enable DLL master slave shuffle
7215 00:40:30.764528 ==============================================================
7216 00:40:30.768465 Gating Mode config
7217 00:40:30.771676 ==============================================================
7218 00:40:30.774911 Config description:
7219 00:40:30.785054 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7220 00:40:30.791303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7221 00:40:30.794946 SELPH_MODE 0: By rank 1: By Phase
7222 00:40:30.801505 ==============================================================
7223 00:40:30.804805 GAT_TRACK_EN = 1
7224 00:40:30.807999 RX_GATING_MODE = 2
7225 00:40:30.811684 RX_GATING_TRACK_MODE = 2
7226 00:40:30.811768 SELPH_MODE = 1
7227 00:40:30.814538 PICG_EARLY_EN = 1
7228 00:40:30.817995 VALID_LAT_VALUE = 1
7229 00:40:30.825067 ==============================================================
7230 00:40:30.827874 Enter into Gating configuration >>>>
7231 00:40:30.831435 Exit from Gating configuration <<<<
7232 00:40:30.834425 Enter into DVFS_PRE_config >>>>>
7233 00:40:30.844557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7234 00:40:30.847729 Exit from DVFS_PRE_config <<<<<
7235 00:40:30.851314 Enter into PICG configuration >>>>
7236 00:40:30.854609 Exit from PICG configuration <<<<
7237 00:40:30.857765 [RX_INPUT] configuration >>>>>
7238 00:40:30.861216 [RX_INPUT] configuration <<<<<
7239 00:40:30.864209 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7240 00:40:30.870897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7241 00:40:30.877949 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 00:40:30.884373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 00:40:30.891209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 00:40:30.894435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 00:40:30.900865 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7246 00:40:30.904206 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7247 00:40:30.907875 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7248 00:40:30.911021 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7249 00:40:30.914259 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7250 00:40:30.920965 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 00:40:30.924536 ===================================
7252 00:40:30.927784 LPDDR4 DRAM CONFIGURATION
7253 00:40:30.931035 ===================================
7254 00:40:30.931111 EX_ROW_EN[0] = 0x0
7255 00:40:30.934787 EX_ROW_EN[1] = 0x0
7256 00:40:30.934889 LP4Y_EN = 0x0
7257 00:40:30.937513 WORK_FSP = 0x1
7258 00:40:30.937591 WL = 0x5
7259 00:40:30.941366 RL = 0x5
7260 00:40:30.941443 BL = 0x2
7261 00:40:30.944169 RPST = 0x0
7262 00:40:30.944270 RD_PRE = 0x0
7263 00:40:30.947604 WR_PRE = 0x1
7264 00:40:30.947706 WR_PST = 0x1
7265 00:40:30.951121 DBI_WR = 0x0
7266 00:40:30.951194 DBI_RD = 0x0
7267 00:40:30.954094 OTF = 0x1
7268 00:40:30.957390 ===================================
7269 00:40:30.960926 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7270 00:40:30.963997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7271 00:40:30.970596 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 00:40:30.974063 ===================================
7273 00:40:30.974145 LPDDR4 DRAM CONFIGURATION
7274 00:40:30.977717 ===================================
7275 00:40:30.980580 EX_ROW_EN[0] = 0x10
7276 00:40:30.983738 EX_ROW_EN[1] = 0x0
7277 00:40:30.983813 LP4Y_EN = 0x0
7278 00:40:30.987481 WORK_FSP = 0x1
7279 00:40:30.987578 WL = 0x5
7280 00:40:30.990481 RL = 0x5
7281 00:40:30.990552 BL = 0x2
7282 00:40:30.994284 RPST = 0x0
7283 00:40:30.994361 RD_PRE = 0x0
7284 00:40:30.997657 WR_PRE = 0x1
7285 00:40:30.997730 WR_PST = 0x1
7286 00:40:31.000986 DBI_WR = 0x0
7287 00:40:31.001085 DBI_RD = 0x0
7288 00:40:31.004164 OTF = 0x1
7289 00:40:31.007410 ===================================
7290 00:40:31.014078 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7291 00:40:31.014160 ==
7292 00:40:31.017468 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 00:40:31.020718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 00:40:31.020820 ==
7295 00:40:31.024143 [Duty_Offset_Calibration]
7296 00:40:31.024217 B0:2 B1:0 CA:1
7297 00:40:31.024279
7298 00:40:31.027218 [DutyScan_Calibration_Flow] k_type=0
7299 00:40:31.036941
7300 00:40:31.037047 ==CLK 0==
7301 00:40:31.040701 Final CLK duty delay cell = -4
7302 00:40:31.043748 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7303 00:40:31.047193 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7304 00:40:31.050393 [-4] AVG Duty = 4906%(X100)
7305 00:40:31.050471
7306 00:40:31.053890 CH0 CLK Duty spec in!! Max-Min= 187%
7307 00:40:31.057013 [DutyScan_Calibration_Flow] ====Done====
7308 00:40:31.057087
7309 00:40:31.060424 [DutyScan_Calibration_Flow] k_type=1
7310 00:40:31.076950
7311 00:40:31.077057 ==DQS 0 ==
7312 00:40:31.079951 Final DQS duty delay cell = 0
7313 00:40:31.083253 [0] MAX Duty = 5249%(X100), DQS PI = 36
7314 00:40:31.086476 [0] MIN Duty = 4938%(X100), DQS PI = 0
7315 00:40:31.086554 [0] AVG Duty = 5093%(X100)
7316 00:40:31.090137
7317 00:40:31.090211 ==DQS 1 ==
7318 00:40:31.092984 Final DQS duty delay cell = -4
7319 00:40:31.096452 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7320 00:40:31.100082 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7321 00:40:31.103282 [-4] AVG Duty = 4969%(X100)
7322 00:40:31.103357
7323 00:40:31.106520 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7324 00:40:31.106595
7325 00:40:31.110026 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7326 00:40:31.113600 [DutyScan_Calibration_Flow] ====Done====
7327 00:40:31.113676
7328 00:40:31.116398 [DutyScan_Calibration_Flow] k_type=3
7329 00:40:31.133822
7330 00:40:31.133928 ==DQM 0 ==
7331 00:40:31.137611 Final DQM duty delay cell = 0
7332 00:40:31.140736 [0] MAX Duty = 5124%(X100), DQS PI = 26
7333 00:40:31.144131 [0] MIN Duty = 4813%(X100), DQS PI = 50
7334 00:40:31.147367 [0] AVG Duty = 4968%(X100)
7335 00:40:31.147467
7336 00:40:31.147561 ==DQM 1 ==
7337 00:40:31.150623 Final DQM duty delay cell = 0
7338 00:40:31.153853 [0] MAX Duty = 5249%(X100), DQS PI = 30
7339 00:40:31.157201 [0] MIN Duty = 5000%(X100), DQS PI = 20
7340 00:40:31.160506 [0] AVG Duty = 5124%(X100)
7341 00:40:31.160631
7342 00:40:31.164348 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7343 00:40:31.164452
7344 00:40:31.167224 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7345 00:40:31.170525 [DutyScan_Calibration_Flow] ====Done====
7346 00:40:31.170606
7347 00:40:31.173809 [DutyScan_Calibration_Flow] k_type=2
7348 00:40:31.191129
7349 00:40:31.191210 ==DQ 0 ==
7350 00:40:31.194445 Final DQ duty delay cell = 0
7351 00:40:31.197789 [0] MAX Duty = 5124%(X100), DQS PI = 34
7352 00:40:31.200954 [0] MIN Duty = 5000%(X100), DQS PI = 0
7353 00:40:31.204254 [0] AVG Duty = 5062%(X100)
7354 00:40:31.204331
7355 00:40:31.204430 ==DQ 1 ==
7356 00:40:31.207693 Final DQ duty delay cell = 0
7357 00:40:31.210985 [0] MAX Duty = 4969%(X100), DQS PI = 50
7358 00:40:31.214350 [0] MIN Duty = 4875%(X100), DQS PI = 0
7359 00:40:31.214432 [0] AVG Duty = 4922%(X100)
7360 00:40:31.214498
7361 00:40:31.217811 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7362 00:40:31.221085
7363 00:40:31.224309 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7364 00:40:31.227564 [DutyScan_Calibration_Flow] ====Done====
7365 00:40:31.227645 ==
7366 00:40:31.230676 Dram Type= 6, Freq= 0, CH_1, rank 0
7367 00:40:31.233869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7368 00:40:31.233950 ==
7369 00:40:31.237496 [Duty_Offset_Calibration]
7370 00:40:31.237575 B0:0 B1:-1 CA:2
7371 00:40:31.237639
7372 00:40:31.240568 [DutyScan_Calibration_Flow] k_type=0
7373 00:40:31.251666
7374 00:40:31.251746 ==CLK 0==
7375 00:40:31.254877 Final CLK duty delay cell = 0
7376 00:40:31.258140 [0] MAX Duty = 5156%(X100), DQS PI = 10
7377 00:40:31.261094 [0] MIN Duty = 4906%(X100), DQS PI = 46
7378 00:40:31.264660 [0] AVG Duty = 5031%(X100)
7379 00:40:31.264740
7380 00:40:31.267650 CH1 CLK Duty spec in!! Max-Min= 250%
7381 00:40:31.271364 [DutyScan_Calibration_Flow] ====Done====
7382 00:40:31.271445
7383 00:40:31.274454 [DutyScan_Calibration_Flow] k_type=1
7384 00:40:31.290970
7385 00:40:31.291050 ==DQS 0 ==
7386 00:40:31.294437 Final DQS duty delay cell = 0
7387 00:40:31.297728 [0] MAX Duty = 5124%(X100), DQS PI = 26
7388 00:40:31.300932 [0] MIN Duty = 4969%(X100), DQS PI = 2
7389 00:40:31.304145 [0] AVG Duty = 5046%(X100)
7390 00:40:31.304225
7391 00:40:31.304288 ==DQS 1 ==
7392 00:40:31.307637 Final DQS duty delay cell = 0
7393 00:40:31.310848 [0] MAX Duty = 5187%(X100), DQS PI = 0
7394 00:40:31.314175 [0] MIN Duty = 4844%(X100), DQS PI = 32
7395 00:40:31.317824 [0] AVG Duty = 5015%(X100)
7396 00:40:31.317904
7397 00:40:31.320664 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7398 00:40:31.320745
7399 00:40:31.324350 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7400 00:40:31.327589 [DutyScan_Calibration_Flow] ====Done====
7401 00:40:31.327669
7402 00:40:31.330532 [DutyScan_Calibration_Flow] k_type=3
7403 00:40:31.348811
7404 00:40:31.348892 ==DQM 0 ==
7405 00:40:31.351731 Final DQM duty delay cell = 4
7406 00:40:31.355213 [4] MAX Duty = 5125%(X100), DQS PI = 8
7407 00:40:31.358579 [4] MIN Duty = 4969%(X100), DQS PI = 46
7408 00:40:31.358659 [4] AVG Duty = 5047%(X100)
7409 00:40:31.362092
7410 00:40:31.362172 ==DQM 1 ==
7411 00:40:31.365222 Final DQM duty delay cell = 0
7412 00:40:31.368673 [0] MAX Duty = 5312%(X100), DQS PI = 60
7413 00:40:31.372185 [0] MIN Duty = 4876%(X100), DQS PI = 34
7414 00:40:31.372266 [0] AVG Duty = 5094%(X100)
7415 00:40:31.375283
7416 00:40:31.378811 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7417 00:40:31.378891
7418 00:40:31.382036 CH1 DQM 1 Duty spec in!! Max-Min= 436%
7419 00:40:31.385477 [DutyScan_Calibration_Flow] ====Done====
7420 00:40:31.385558
7421 00:40:31.388699 [DutyScan_Calibration_Flow] k_type=2
7422 00:40:31.405558
7423 00:40:31.405658 ==DQ 0 ==
7424 00:40:31.408938 Final DQ duty delay cell = 0
7425 00:40:31.412148 [0] MAX Duty = 5062%(X100), DQS PI = 22
7426 00:40:31.415407 [0] MIN Duty = 4969%(X100), DQS PI = 0
7427 00:40:31.415488 [0] AVG Duty = 5015%(X100)
7428 00:40:31.415562
7429 00:40:31.419030 ==DQ 1 ==
7430 00:40:31.422415 Final DQ duty delay cell = 0
7431 00:40:31.425550 [0] MAX Duty = 5062%(X100), DQS PI = 2
7432 00:40:31.428716 [0] MIN Duty = 4813%(X100), DQS PI = 34
7433 00:40:31.428797 [0] AVG Duty = 4937%(X100)
7434 00:40:31.428859
7435 00:40:31.432459 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7436 00:40:31.432539
7437 00:40:31.435479 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7438 00:40:31.442001 [DutyScan_Calibration_Flow] ====Done====
7439 00:40:31.445199 nWR fixed to 30
7440 00:40:31.445280 [ModeRegInit_LP4] CH0 RK0
7441 00:40:31.448885 [ModeRegInit_LP4] CH0 RK1
7442 00:40:31.451916 [ModeRegInit_LP4] CH1 RK0
7443 00:40:31.452022 [ModeRegInit_LP4] CH1 RK1
7444 00:40:31.455467 match AC timing 5
7445 00:40:31.458653 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7446 00:40:31.462232 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7447 00:40:31.468528 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7448 00:40:31.472090 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7449 00:40:31.478548 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7450 00:40:31.478630 [MiockJmeterHQA]
7451 00:40:31.478694
7452 00:40:31.482325 [DramcMiockJmeter] u1RxGatingPI = 0
7453 00:40:31.485272 0 : 4362, 4137
7454 00:40:31.485355 4 : 4252, 4027
7455 00:40:31.485421 8 : 4363, 4137
7456 00:40:31.488787 12 : 4252, 4027
7457 00:40:31.488870 16 : 4252, 4027
7458 00:40:31.491775 20 : 4363, 4137
7459 00:40:31.491882 24 : 4361, 4138
7460 00:40:31.495099 28 : 4253, 4027
7461 00:40:31.495182 32 : 4250, 4026
7462 00:40:31.495248 36 : 4250, 4027
7463 00:40:31.498599 40 : 4361, 4137
7464 00:40:31.498682 44 : 4250, 4026
7465 00:40:31.501654 48 : 4360, 4138
7466 00:40:31.501737 52 : 4252, 4027
7467 00:40:31.505307 56 : 4250, 4027
7468 00:40:31.505389 60 : 4250, 4027
7469 00:40:31.508418 64 : 4253, 4029
7470 00:40:31.508501 68 : 4250, 4027
7471 00:40:31.508593 72 : 4250, 4026
7472 00:40:31.511930 76 : 4363, 4140
7473 00:40:31.512011 80 : 4250, 4027
7474 00:40:31.515113 84 : 4253, 4029
7475 00:40:31.515195 88 : 4250, 3464
7476 00:40:31.518276 92 : 4361, 0
7477 00:40:31.518360 96 : 4250, 0
7478 00:40:31.518424 100 : 4250, 0
7479 00:40:31.521786 104 : 4250, 0
7480 00:40:31.521868 108 : 4250, 0
7481 00:40:31.525002 112 : 4360, 0
7482 00:40:31.525084 116 : 4360, 0
7483 00:40:31.525149 120 : 4250, 0
7484 00:40:31.528462 124 : 4253, 0
7485 00:40:31.528575 128 : 4363, 0
7486 00:40:31.528643 132 : 4250, 0
7487 00:40:31.531717 136 : 4250, 0
7488 00:40:31.531799 140 : 4250, 0
7489 00:40:31.535088 144 : 4253, 0
7490 00:40:31.535173 148 : 4250, 0
7491 00:40:31.535241 152 : 4250, 0
7492 00:40:31.538287 156 : 4253, 0
7493 00:40:31.538371 160 : 4250, 0
7494 00:40:31.541820 164 : 4360, 0
7495 00:40:31.541904 168 : 4250, 0
7496 00:40:31.541971 172 : 4250, 0
7497 00:40:31.544944 176 : 4249, 0
7498 00:40:31.545028 180 : 4363, 0
7499 00:40:31.548125 184 : 4250, 0
7500 00:40:31.548209 188 : 4250, 0
7501 00:40:31.548276 192 : 4250, 0
7502 00:40:31.552116 196 : 4253, 0
7503 00:40:31.552201 200 : 4361, 17
7504 00:40:31.554831 204 : 4250, 2809
7505 00:40:31.554914 208 : 4360, 4138
7506 00:40:31.558066 212 : 4361, 4137
7507 00:40:31.558151 216 : 4248, 4024
7508 00:40:31.558218 220 : 4363, 4139
7509 00:40:31.561420 224 : 4250, 4027
7510 00:40:31.561504 228 : 4253, 4027
7511 00:40:31.565315 232 : 4250, 4027
7512 00:40:31.565399 236 : 4253, 4029
7513 00:40:31.568224 240 : 4250, 4027
7514 00:40:31.568308 244 : 4250, 4027
7515 00:40:31.571761 248 : 4250, 4027
7516 00:40:31.571845 252 : 4253, 4029
7517 00:40:31.574784 256 : 4250, 4027
7518 00:40:31.574869 260 : 4360, 4138
7519 00:40:31.578009 264 : 4363, 4137
7520 00:40:31.578093 268 : 4250, 4026
7521 00:40:31.581351 272 : 4363, 4139
7522 00:40:31.581434 276 : 4361, 4137
7523 00:40:31.581501 280 : 4250, 4027
7524 00:40:31.585143 284 : 4250, 4027
7525 00:40:31.585227 288 : 4253, 4029
7526 00:40:31.588102 292 : 4250, 4027
7527 00:40:31.588186 296 : 4250, 4027
7528 00:40:31.591394 300 : 4253, 4026
7529 00:40:31.591478 304 : 4253, 4029
7530 00:40:31.594656 308 : 4250, 4027
7531 00:40:31.594741 312 : 4360, 3881
7532 00:40:31.598007 316 : 4361, 1694
7533 00:40:31.598091
7534 00:40:31.598157 MIOCK jitter meter ch=0
7535 00:40:31.598218
7536 00:40:31.601383 1T = (316-92) = 224 dly cells
7537 00:40:31.608095 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7538 00:40:31.608179 ==
7539 00:40:31.611173 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 00:40:31.614516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 00:40:31.614600 ==
7542 00:40:31.621085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 00:40:31.624696 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 00:40:31.627903 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 00:40:31.634385 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 00:40:31.644283 [CA 0] Center 43 (13~73) winsize 61
7547 00:40:31.647903 [CA 1] Center 43 (13~73) winsize 61
7548 00:40:31.650961 [CA 2] Center 38 (8~68) winsize 61
7549 00:40:31.654795 [CA 3] Center 37 (8~67) winsize 60
7550 00:40:31.657472 [CA 4] Center 36 (6~66) winsize 61
7551 00:40:31.660670 [CA 5] Center 35 (5~65) winsize 61
7552 00:40:31.660755
7553 00:40:31.664205 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 00:40:31.664331
7555 00:40:31.667517 [CATrainingPosCal] consider 1 rank data
7556 00:40:31.670909 u2DelayCellTimex100 = 290/100 ps
7557 00:40:31.674135 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7558 00:40:31.680537 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7559 00:40:31.684093 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7560 00:40:31.687398 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7561 00:40:31.690558 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7562 00:40:31.693794 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7563 00:40:31.693912
7564 00:40:31.697417 CA PerBit enable=1, Macro0, CA PI delay=35
7565 00:40:31.697536
7566 00:40:31.700831 [CBTSetCACLKResult] CA Dly = 35
7567 00:40:31.704107 CS Dly: 9 (0~40)
7568 00:40:31.707110 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 00:40:31.710738 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 00:40:31.710823 ==
7571 00:40:31.714163 Dram Type= 6, Freq= 0, CH_0, rank 1
7572 00:40:31.717244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 00:40:31.720756 ==
7574 00:40:31.724028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 00:40:31.727134 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 00:40:31.733744 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 00:40:31.737174 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 00:40:31.747348 [CA 0] Center 43 (13~73) winsize 61
7579 00:40:31.750998 [CA 1] Center 43 (13~73) winsize 61
7580 00:40:31.754028 [CA 2] Center 37 (8~67) winsize 60
7581 00:40:31.757388 [CA 3] Center 38 (8~68) winsize 61
7582 00:40:31.760855 [CA 4] Center 36 (6~66) winsize 61
7583 00:40:31.764094 [CA 5] Center 36 (6~66) winsize 61
7584 00:40:31.764177
7585 00:40:31.767551 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 00:40:31.767673
7587 00:40:31.770924 [CATrainingPosCal] consider 2 rank data
7588 00:40:31.774338 u2DelayCellTimex100 = 290/100 ps
7589 00:40:31.777353 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7590 00:40:31.784268 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7591 00:40:31.787655 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7592 00:40:31.791000 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7593 00:40:31.794478 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7594 00:40:31.797665 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7595 00:40:31.797750
7596 00:40:31.800720 CA PerBit enable=1, Macro0, CA PI delay=35
7597 00:40:31.800828
7598 00:40:31.804069 [CBTSetCACLKResult] CA Dly = 35
7599 00:40:31.804163 CS Dly: 10 (0~43)
7600 00:40:31.810901 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 00:40:31.814368 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 00:40:31.814473
7603 00:40:31.817387 ----->DramcWriteLeveling(PI) begin...
7604 00:40:31.817508 ==
7605 00:40:31.820799 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 00:40:31.824233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 00:40:31.827289 ==
7608 00:40:31.827366 Write leveling (Byte 0): 37 => 37
7609 00:40:31.830777 Write leveling (Byte 1): 31 => 31
7610 00:40:31.834084 DramcWriteLeveling(PI) end<-----
7611 00:40:31.834169
7612 00:40:31.834236 ==
7613 00:40:31.837609 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 00:40:31.843998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 00:40:31.844113 ==
7616 00:40:31.844212 [Gating] SW mode calibration
7617 00:40:31.854053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7618 00:40:31.857145 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7619 00:40:31.860543 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 00:40:31.867443 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 00:40:31.870751 1 4 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7622 00:40:31.874040 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7623 00:40:31.880819 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7624 00:40:31.884435 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7625 00:40:31.887403 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 00:40:31.894352 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 00:40:31.897182 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 00:40:31.900484 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 00:40:31.907231 1 5 8 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7630 00:40:31.910500 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7631 00:40:31.914260 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7632 00:40:31.920744 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7633 00:40:31.923779 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7634 00:40:31.927058 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 00:40:31.933935 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 00:40:31.937142 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7637 00:40:31.940841 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7638 00:40:31.947430 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7639 00:40:31.950676 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7640 00:40:31.954189 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7641 00:40:31.960890 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 00:40:31.963851 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 00:40:31.967106 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 00:40:31.973764 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 00:40:31.977247 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 00:40:31.980426 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7647 00:40:31.983739 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7648 00:40:31.990528 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7649 00:40:31.993854 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 00:40:31.997098 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 00:40:32.003940 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 00:40:32.007484 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 00:40:32.010626 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 00:40:32.016997 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 00:40:32.020351 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 00:40:32.023692 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 00:40:32.030202 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 00:40:32.033740 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 00:40:32.037142 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 00:40:32.043474 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 00:40:32.046982 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7662 00:40:32.050177 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 00:40:32.056714 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7664 00:40:32.056808 Total UI for P1: 0, mck2ui 16
7665 00:40:32.063660 best dqsien dly found for B0: ( 1, 9, 10)
7666 00:40:32.066987 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7667 00:40:32.069866 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 00:40:32.073498 Total UI for P1: 0, mck2ui 16
7669 00:40:32.076918 best dqsien dly found for B1: ( 1, 9, 20)
7670 00:40:32.080024 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7671 00:40:32.083099 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7672 00:40:32.083173
7673 00:40:32.089835 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7674 00:40:32.093557 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7675 00:40:32.096656 [Gating] SW calibration Done
7676 00:40:32.096734 ==
7677 00:40:32.099816 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 00:40:32.103133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 00:40:32.103208 ==
7680 00:40:32.103277 RX Vref Scan: 0
7681 00:40:32.103335
7682 00:40:32.106799 RX Vref 0 -> 0, step: 1
7683 00:40:32.106869
7684 00:40:32.110131 RX Delay 0 -> 252, step: 8
7685 00:40:32.113132 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7686 00:40:32.116707 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7687 00:40:32.119609 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7688 00:40:32.126108 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7689 00:40:32.129451 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7690 00:40:32.133117 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7691 00:40:32.136132 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7692 00:40:32.139519 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7693 00:40:32.146312 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7694 00:40:32.149596 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7695 00:40:32.152963 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7696 00:40:32.156044 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7697 00:40:32.159629 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7698 00:40:32.166524 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7699 00:40:32.169334 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7700 00:40:32.172663 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7701 00:40:32.172750 ==
7702 00:40:32.176211 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 00:40:32.179257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 00:40:32.179343 ==
7705 00:40:32.183144 DQS Delay:
7706 00:40:32.183245 DQS0 = 0, DQS1 = 0
7707 00:40:32.186110 DQM Delay:
7708 00:40:32.186193 DQM0 = 138, DQM1 = 126
7709 00:40:32.189453 DQ Delay:
7710 00:40:32.192642 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7711 00:40:32.196509 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7712 00:40:32.199335 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7713 00:40:32.202971 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7714 00:40:32.203092
7715 00:40:32.203159
7716 00:40:32.203220 ==
7717 00:40:32.206233 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 00:40:32.209134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 00:40:32.209218 ==
7720 00:40:32.209321
7721 00:40:32.209384
7722 00:40:32.212411 TX Vref Scan disable
7723 00:40:32.215889 == TX Byte 0 ==
7724 00:40:32.219570 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7725 00:40:32.222483 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7726 00:40:32.226070 == TX Byte 1 ==
7727 00:40:32.229165 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7728 00:40:32.232445 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7729 00:40:32.232530 ==
7730 00:40:32.236158 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 00:40:32.239258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 00:40:32.242468 ==
7733 00:40:32.254482
7734 00:40:32.257734 TX Vref early break, caculate TX vref
7735 00:40:32.260697 TX Vref=16, minBit 6, minWin=22, winSum=379
7736 00:40:32.264098 TX Vref=18, minBit 6, minWin=23, winSum=389
7737 00:40:32.267586 TX Vref=20, minBit 7, minWin=23, winSum=396
7738 00:40:32.270784 TX Vref=22, minBit 7, minWin=24, winSum=406
7739 00:40:32.274130 TX Vref=24, minBit 2, minWin=25, winSum=415
7740 00:40:32.280672 TX Vref=26, minBit 4, minWin=25, winSum=422
7741 00:40:32.283997 TX Vref=28, minBit 0, minWin=26, winSum=431
7742 00:40:32.287666 TX Vref=30, minBit 2, minWin=25, winSum=423
7743 00:40:32.290662 TX Vref=32, minBit 2, minWin=24, winSum=418
7744 00:40:32.293843 TX Vref=34, minBit 2, minWin=24, winSum=408
7745 00:40:32.300827 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7746 00:40:32.300913
7747 00:40:32.303826 Final TX Range 0 Vref 28
7748 00:40:32.303910
7749 00:40:32.303976 ==
7750 00:40:32.307387 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 00:40:32.310730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 00:40:32.310814 ==
7753 00:40:32.310915
7754 00:40:32.311009
7755 00:40:32.313729 TX Vref Scan disable
7756 00:40:32.320482 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7757 00:40:32.320591 == TX Byte 0 ==
7758 00:40:32.324062 u2DelayCellOfst[0]=13 cells (4 PI)
7759 00:40:32.326770 u2DelayCellOfst[1]=20 cells (6 PI)
7760 00:40:32.330232 u2DelayCellOfst[2]=13 cells (4 PI)
7761 00:40:32.333600 u2DelayCellOfst[3]=13 cells (4 PI)
7762 00:40:32.337182 u2DelayCellOfst[4]=6 cells (2 PI)
7763 00:40:32.340077 u2DelayCellOfst[5]=0 cells (0 PI)
7764 00:40:32.343734 u2DelayCellOfst[6]=20 cells (6 PI)
7765 00:40:32.347449 u2DelayCellOfst[7]=16 cells (5 PI)
7766 00:40:32.350086 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7767 00:40:32.353752 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7768 00:40:32.357248 == TX Byte 1 ==
7769 00:40:32.357332 u2DelayCellOfst[8]=0 cells (0 PI)
7770 00:40:32.360348 u2DelayCellOfst[9]=0 cells (0 PI)
7771 00:40:32.363578 u2DelayCellOfst[10]=6 cells (2 PI)
7772 00:40:32.366743 u2DelayCellOfst[11]=3 cells (1 PI)
7773 00:40:32.370278 u2DelayCellOfst[12]=10 cells (3 PI)
7774 00:40:32.373736 u2DelayCellOfst[13]=13 cells (4 PI)
7775 00:40:32.376805 u2DelayCellOfst[14]=16 cells (5 PI)
7776 00:40:32.379944 u2DelayCellOfst[15]=10 cells (3 PI)
7777 00:40:32.383524 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7778 00:40:32.390442 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7779 00:40:32.390527 DramC Write-DBI on
7780 00:40:32.390595 ==
7781 00:40:32.394021 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 00:40:32.397269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 00:40:32.400274 ==
7784 00:40:32.400357
7785 00:40:32.400422
7786 00:40:32.400495 TX Vref Scan disable
7787 00:40:32.403899 == TX Byte 0 ==
7788 00:40:32.407401 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7789 00:40:32.410315 == TX Byte 1 ==
7790 00:40:32.413622 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7791 00:40:32.413723 DramC Write-DBI off
7792 00:40:32.417409
7793 00:40:32.417494 [DATLAT]
7794 00:40:32.417595 Freq=1600, CH0 RK0
7795 00:40:32.417689
7796 00:40:32.420037 DATLAT Default: 0xf
7797 00:40:32.420143 0, 0xFFFF, sum = 0
7798 00:40:32.423739 1, 0xFFFF, sum = 0
7799 00:40:32.426709 2, 0xFFFF, sum = 0
7800 00:40:32.426796 3, 0xFFFF, sum = 0
7801 00:40:32.430105 4, 0xFFFF, sum = 0
7802 00:40:32.430192 5, 0xFFFF, sum = 0
7803 00:40:32.433419 6, 0xFFFF, sum = 0
7804 00:40:32.433506 7, 0xFFFF, sum = 0
7805 00:40:32.436479 8, 0xFFFF, sum = 0
7806 00:40:32.436584 9, 0xFFFF, sum = 0
7807 00:40:32.440041 10, 0xFFFF, sum = 0
7808 00:40:32.440142 11, 0xFFFF, sum = 0
7809 00:40:32.443167 12, 0xFFFF, sum = 0
7810 00:40:32.443252 13, 0xFFFF, sum = 0
7811 00:40:32.446620 14, 0x0, sum = 1
7812 00:40:32.446705 15, 0x0, sum = 2
7813 00:40:32.449840 16, 0x0, sum = 3
7814 00:40:32.449926 17, 0x0, sum = 4
7815 00:40:32.453096 best_step = 15
7816 00:40:32.453180
7817 00:40:32.453248 ==
7818 00:40:32.456731 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 00:40:32.459713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 00:40:32.459798 ==
7821 00:40:32.463298 RX Vref Scan: 1
7822 00:40:32.463401
7823 00:40:32.463483 Set Vref Range= 24 -> 127
7824 00:40:32.463546
7825 00:40:32.466356 RX Vref 24 -> 127, step: 1
7826 00:40:32.466440
7827 00:40:32.469684 RX Delay 19 -> 252, step: 4
7828 00:40:32.469782
7829 00:40:32.473141 Set Vref, RX VrefLevel [Byte0]: 24
7830 00:40:32.476450 [Byte1]: 24
7831 00:40:32.476595
7832 00:40:32.479913 Set Vref, RX VrefLevel [Byte0]: 25
7833 00:40:32.483432 [Byte1]: 25
7834 00:40:32.483516
7835 00:40:32.486634 Set Vref, RX VrefLevel [Byte0]: 26
7836 00:40:32.490141 [Byte1]: 26
7837 00:40:32.494204
7838 00:40:32.494287 Set Vref, RX VrefLevel [Byte0]: 27
7839 00:40:32.497214 [Byte1]: 27
7840 00:40:32.501344
7841 00:40:32.501427 Set Vref, RX VrefLevel [Byte0]: 28
7842 00:40:32.504707 [Byte1]: 28
7843 00:40:32.509210
7844 00:40:32.509295 Set Vref, RX VrefLevel [Byte0]: 29
7845 00:40:32.512475 [Byte1]: 29
7846 00:40:32.516579
7847 00:40:32.516693 Set Vref, RX VrefLevel [Byte0]: 30
7848 00:40:32.520001 [Byte1]: 30
7849 00:40:32.524189
7850 00:40:32.524275 Set Vref, RX VrefLevel [Byte0]: 31
7851 00:40:32.527472 [Byte1]: 31
7852 00:40:32.531523
7853 00:40:32.531623 Set Vref, RX VrefLevel [Byte0]: 32
7854 00:40:32.535264 [Byte1]: 32
7855 00:40:32.539148
7856 00:40:32.539246 Set Vref, RX VrefLevel [Byte0]: 33
7857 00:40:32.542500 [Byte1]: 33
7858 00:40:32.547225
7859 00:40:32.547309 Set Vref, RX VrefLevel [Byte0]: 34
7860 00:40:32.550410 [Byte1]: 34
7861 00:40:32.554383
7862 00:40:32.554487 Set Vref, RX VrefLevel [Byte0]: 35
7863 00:40:32.558015 [Byte1]: 35
7864 00:40:32.562296
7865 00:40:32.562402 Set Vref, RX VrefLevel [Byte0]: 36
7866 00:40:32.565748 [Byte1]: 36
7867 00:40:32.570159
7868 00:40:32.570241 Set Vref, RX VrefLevel [Byte0]: 37
7869 00:40:32.572958 [Byte1]: 37
7870 00:40:32.577246
7871 00:40:32.577359 Set Vref, RX VrefLevel [Byte0]: 38
7872 00:40:32.580557 [Byte1]: 38
7873 00:40:32.584863
7874 00:40:32.584948 Set Vref, RX VrefLevel [Byte0]: 39
7875 00:40:32.588160 [Byte1]: 39
7876 00:40:32.592446
7877 00:40:32.592554 Set Vref, RX VrefLevel [Byte0]: 40
7878 00:40:32.595647 [Byte1]: 40
7879 00:40:32.600231
7880 00:40:32.600314 Set Vref, RX VrefLevel [Byte0]: 41
7881 00:40:32.603415 [Byte1]: 41
7882 00:40:32.607359
7883 00:40:32.607441 Set Vref, RX VrefLevel [Byte0]: 42
7884 00:40:32.611057 [Byte1]: 42
7885 00:40:32.615203
7886 00:40:32.615287 Set Vref, RX VrefLevel [Byte0]: 43
7887 00:40:32.621667 [Byte1]: 43
7888 00:40:32.621753
7889 00:40:32.625088 Set Vref, RX VrefLevel [Byte0]: 44
7890 00:40:32.628281 [Byte1]: 44
7891 00:40:32.628365
7892 00:40:32.631686 Set Vref, RX VrefLevel [Byte0]: 45
7893 00:40:32.634985 [Byte1]: 45
7894 00:40:32.635070
7895 00:40:32.638089 Set Vref, RX VrefLevel [Byte0]: 46
7896 00:40:32.641339 [Byte1]: 46
7897 00:40:32.645528
7898 00:40:32.645621 Set Vref, RX VrefLevel [Byte0]: 47
7899 00:40:32.648889 [Byte1]: 47
7900 00:40:32.652977
7901 00:40:32.653058 Set Vref, RX VrefLevel [Byte0]: 48
7902 00:40:32.656331 [Byte1]: 48
7903 00:40:32.660380
7904 00:40:32.660453 Set Vref, RX VrefLevel [Byte0]: 49
7905 00:40:32.664053 [Byte1]: 49
7906 00:40:32.667959
7907 00:40:32.668046 Set Vref, RX VrefLevel [Byte0]: 50
7908 00:40:32.671470 [Byte1]: 50
7909 00:40:32.675888
7910 00:40:32.675986 Set Vref, RX VrefLevel [Byte0]: 51
7911 00:40:32.679293 [Byte1]: 51
7912 00:40:32.683374
7913 00:40:32.683460 Set Vref, RX VrefLevel [Byte0]: 52
7914 00:40:32.686775 [Byte1]: 52
7915 00:40:32.690753
7916 00:40:32.690833 Set Vref, RX VrefLevel [Byte0]: 53
7917 00:40:32.694477 [Byte1]: 53
7918 00:40:32.698320
7919 00:40:32.698395 Set Vref, RX VrefLevel [Byte0]: 54
7920 00:40:32.701813 [Byte1]: 54
7921 00:40:32.705796
7922 00:40:32.705882 Set Vref, RX VrefLevel [Byte0]: 55
7923 00:40:32.709587 [Byte1]: 55
7924 00:40:32.713460
7925 00:40:32.713590 Set Vref, RX VrefLevel [Byte0]: 56
7926 00:40:32.716795 [Byte1]: 56
7927 00:40:32.720895
7928 00:40:32.720980 Set Vref, RX VrefLevel [Byte0]: 57
7929 00:40:32.724461 [Byte1]: 57
7930 00:40:32.728968
7931 00:40:32.729081 Set Vref, RX VrefLevel [Byte0]: 58
7932 00:40:32.732275 [Byte1]: 58
7933 00:40:32.736259
7934 00:40:32.736402 Set Vref, RX VrefLevel [Byte0]: 59
7935 00:40:32.739482 [Byte1]: 59
7936 00:40:32.743641
7937 00:40:32.743745 Set Vref, RX VrefLevel [Byte0]: 60
7938 00:40:32.747166 [Byte1]: 60
7939 00:40:32.751650
7940 00:40:32.751795 Set Vref, RX VrefLevel [Byte0]: 61
7941 00:40:32.754760 [Byte1]: 61
7942 00:40:32.759199
7943 00:40:32.759284 Set Vref, RX VrefLevel [Byte0]: 62
7944 00:40:32.762220 [Byte1]: 62
7945 00:40:32.766757
7946 00:40:32.766842 Set Vref, RX VrefLevel [Byte0]: 63
7947 00:40:32.769603 [Byte1]: 63
7948 00:40:32.773866
7949 00:40:32.773972 Set Vref, RX VrefLevel [Byte0]: 64
7950 00:40:32.777177 [Byte1]: 64
7951 00:40:32.781903
7952 00:40:32.782009 Set Vref, RX VrefLevel [Byte0]: 65
7953 00:40:32.784841 [Byte1]: 65
7954 00:40:32.789369
7955 00:40:32.789472 Set Vref, RX VrefLevel [Byte0]: 66
7956 00:40:32.792674 [Byte1]: 66
7957 00:40:32.796828
7958 00:40:32.796912 Set Vref, RX VrefLevel [Byte0]: 67
7959 00:40:32.800093 [Byte1]: 67
7960 00:40:32.804347
7961 00:40:32.804452 Set Vref, RX VrefLevel [Byte0]: 68
7962 00:40:32.807704 [Byte1]: 68
7963 00:40:32.811847
7964 00:40:32.811924 Set Vref, RX VrefLevel [Byte0]: 69
7965 00:40:32.815295 [Byte1]: 69
7966 00:40:32.819672
7967 00:40:32.819748 Set Vref, RX VrefLevel [Byte0]: 70
7968 00:40:32.822801 [Byte1]: 70
7969 00:40:32.827425
7970 00:40:32.827505 Set Vref, RX VrefLevel [Byte0]: 71
7971 00:40:32.830779 [Byte1]: 71
7972 00:40:32.834774
7973 00:40:32.834853 Set Vref, RX VrefLevel [Byte0]: 72
7974 00:40:32.838047 [Byte1]: 72
7975 00:40:32.842065
7976 00:40:32.842148 Set Vref, RX VrefLevel [Byte0]: 73
7977 00:40:32.845751 [Byte1]: 73
7978 00:40:32.850016
7979 00:40:32.850098 Set Vref, RX VrefLevel [Byte0]: 74
7980 00:40:32.853168 [Byte1]: 74
7981 00:40:32.857722
7982 00:40:32.857802 Set Vref, RX VrefLevel [Byte0]: 75
7983 00:40:32.860570 [Byte1]: 75
7984 00:40:32.864931
7985 00:40:32.865035 Set Vref, RX VrefLevel [Byte0]: 76
7986 00:40:32.868432 [Byte1]: 76
7987 00:40:32.872656
7988 00:40:32.872737 Set Vref, RX VrefLevel [Byte0]: 77
7989 00:40:32.875669 [Byte1]: 77
7990 00:40:32.880214
7991 00:40:32.880317 Final RX Vref Byte 0 = 59 to rank0
7992 00:40:32.883763 Final RX Vref Byte 1 = 62 to rank0
7993 00:40:32.886896 Final RX Vref Byte 0 = 59 to rank1
7994 00:40:32.890268 Final RX Vref Byte 1 = 62 to rank1==
7995 00:40:32.893370 Dram Type= 6, Freq= 0, CH_0, rank 0
7996 00:40:32.900145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 00:40:32.900298 ==
7998 00:40:32.900398 DQS Delay:
7999 00:40:32.900489 DQS0 = 0, DQS1 = 0
8000 00:40:32.903423 DQM Delay:
8001 00:40:32.903523 DQM0 = 135, DQM1 = 124
8002 00:40:32.906804 DQ Delay:
8003 00:40:32.909847 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8004 00:40:32.913375 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =142
8005 00:40:32.916583 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8006 00:40:32.919960 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
8007 00:40:32.920074
8008 00:40:32.920165
8009 00:40:32.920236
8010 00:40:32.923692 [DramC_TX_OE_Calibration] TA2
8011 00:40:32.926947 Original DQ_B0 (3 6) =30, OEN = 27
8012 00:40:32.929864 Original DQ_B1 (3 6) =30, OEN = 27
8013 00:40:32.933287 24, 0x0, End_B0=24 End_B1=24
8014 00:40:32.933389 25, 0x0, End_B0=25 End_B1=25
8015 00:40:32.936713 26, 0x0, End_B0=26 End_B1=26
8016 00:40:32.939884 27, 0x0, End_B0=27 End_B1=27
8017 00:40:32.943153 28, 0x0, End_B0=28 End_B1=28
8018 00:40:32.943239 29, 0x0, End_B0=29 End_B1=29
8019 00:40:32.946803 30, 0x0, End_B0=30 End_B1=30
8020 00:40:32.949918 31, 0x4141, End_B0=30 End_B1=30
8021 00:40:32.953200 Byte0 end_step=30 best_step=27
8022 00:40:32.956397 Byte1 end_step=30 best_step=27
8023 00:40:32.959886 Byte0 TX OE(2T, 0.5T) = (3, 3)
8024 00:40:32.963285 Byte1 TX OE(2T, 0.5T) = (3, 3)
8025 00:40:32.963367
8026 00:40:32.963434
8027 00:40:32.969680 [DQSOSCAuto] RK0, (LSB)MR18= 0x2220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
8028 00:40:32.973369 CH0 RK0: MR19=303, MR18=2220
8029 00:40:32.979466 CH0_RK0: MR19=0x303, MR18=0x2220, DQSOSC=392, MR23=63, INC=24, DEC=16
8030 00:40:32.979595
8031 00:40:32.983359 ----->DramcWriteLeveling(PI) begin...
8032 00:40:32.983446 ==
8033 00:40:32.986461 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 00:40:32.989557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 00:40:32.989643 ==
8036 00:40:32.993175 Write leveling (Byte 0): 38 => 38
8037 00:40:32.996660 Write leveling (Byte 1): 30 => 30
8038 00:40:32.999950 DramcWriteLeveling(PI) end<-----
8039 00:40:33.000035
8040 00:40:33.000103 ==
8041 00:40:33.003039 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 00:40:33.006587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 00:40:33.006673 ==
8044 00:40:33.009814 [Gating] SW mode calibration
8045 00:40:33.016297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8046 00:40:33.023166 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8047 00:40:33.026557 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 00:40:33.029564 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 00:40:33.036349 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 00:40:33.039478 1 4 12 | B1->B0 | 2727 3131 | 0 1 | (0 0) (1 1)
8051 00:40:33.043041 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 00:40:33.049561 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 00:40:33.052994 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 00:40:33.056497 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 00:40:33.062665 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 00:40:33.066226 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 00:40:33.069642 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8058 00:40:33.076254 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8059 00:40:33.079728 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8060 00:40:33.082708 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 00:40:33.089492 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 00:40:33.092961 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 00:40:33.096148 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 00:40:33.102772 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 00:40:33.106227 1 6 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8066 00:40:33.109429 1 6 12 | B1->B0 | 2f2f 4343 | 0 0 | (1 1) (0 0)
8067 00:40:33.115926 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 00:40:33.119286 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 00:40:33.122959 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 00:40:33.126406 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 00:40:33.133092 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 00:40:33.136130 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 00:40:33.139440 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 00:40:33.146337 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8075 00:40:33.149362 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8076 00:40:33.153141 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 00:40:33.159352 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 00:40:33.162951 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 00:40:33.166050 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 00:40:33.172877 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 00:40:33.176302 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 00:40:33.179364 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 00:40:33.185871 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 00:40:33.189430 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 00:40:33.192384 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 00:40:33.199241 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 00:40:33.202466 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 00:40:33.205865 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 00:40:33.212793 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 00:40:33.216210 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8091 00:40:33.219449 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8092 00:40:33.222828 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 00:40:33.226164 Total UI for P1: 0, mck2ui 16
8094 00:40:33.229288 best dqsien dly found for B0: ( 1, 9, 14)
8095 00:40:33.232691 Total UI for P1: 0, mck2ui 16
8096 00:40:33.235772 best dqsien dly found for B1: ( 1, 9, 16)
8097 00:40:33.239428 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8098 00:40:33.245935 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8099 00:40:33.246027
8100 00:40:33.249365 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8101 00:40:33.252470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8102 00:40:33.255968 [Gating] SW calibration Done
8103 00:40:33.256080 ==
8104 00:40:33.259264 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 00:40:33.262787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 00:40:33.262873 ==
8107 00:40:33.266188 RX Vref Scan: 0
8108 00:40:33.266273
8109 00:40:33.266339 RX Vref 0 -> 0, step: 1
8110 00:40:33.266402
8111 00:40:33.269393 RX Delay 0 -> 252, step: 8
8112 00:40:33.272539 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8113 00:40:33.275951 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8114 00:40:33.282429 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8115 00:40:33.285844 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8116 00:40:33.289060 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8117 00:40:33.292765 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8118 00:40:33.295775 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8119 00:40:33.302614 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8120 00:40:33.305920 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8121 00:40:33.309306 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8122 00:40:33.312326 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8123 00:40:33.315596 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8124 00:40:33.322710 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8125 00:40:33.325628 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8126 00:40:33.329191 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8127 00:40:33.332211 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8128 00:40:33.332299 ==
8129 00:40:33.335820 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 00:40:33.342588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 00:40:33.342680 ==
8132 00:40:33.342767 DQS Delay:
8133 00:40:33.342847 DQS0 = 0, DQS1 = 0
8134 00:40:33.345621 DQM Delay:
8135 00:40:33.345707 DQM0 = 136, DQM1 = 125
8136 00:40:33.349178 DQ Delay:
8137 00:40:33.352725 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8138 00:40:33.355737 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8139 00:40:33.359354 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8140 00:40:33.362582 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8141 00:40:33.362668
8142 00:40:33.362753
8143 00:40:33.362833 ==
8144 00:40:33.365850 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 00:40:33.369321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 00:40:33.372501 ==
8147 00:40:33.372637
8148 00:40:33.372722
8149 00:40:33.372802 TX Vref Scan disable
8150 00:40:33.375863 == TX Byte 0 ==
8151 00:40:33.378995 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8152 00:40:33.382575 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8153 00:40:33.385692 == TX Byte 1 ==
8154 00:40:33.388966 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8155 00:40:33.392343 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8156 00:40:33.392431 ==
8157 00:40:33.396023 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 00:40:33.402272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 00:40:33.402374 ==
8160 00:40:33.415198
8161 00:40:33.418506 TX Vref early break, caculate TX vref
8162 00:40:33.421740 TX Vref=16, minBit 8, minWin=22, winSum=390
8163 00:40:33.424931 TX Vref=18, minBit 1, minWin=24, winSum=398
8164 00:40:33.428240 TX Vref=20, minBit 8, minWin=24, winSum=403
8165 00:40:33.431782 TX Vref=22, minBit 3, minWin=25, winSum=413
8166 00:40:33.434936 TX Vref=24, minBit 0, minWin=25, winSum=424
8167 00:40:33.441374 TX Vref=26, minBit 1, minWin=26, winSum=433
8168 00:40:33.444797 TX Vref=28, minBit 0, minWin=26, winSum=431
8169 00:40:33.448280 TX Vref=30, minBit 0, minWin=26, winSum=426
8170 00:40:33.451588 TX Vref=32, minBit 0, minWin=26, winSum=418
8171 00:40:33.454993 TX Vref=34, minBit 0, minWin=25, winSum=409
8172 00:40:33.461749 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 26
8173 00:40:33.461856
8174 00:40:33.464887 Final TX Range 0 Vref 26
8175 00:40:33.464961
8176 00:40:33.465023 ==
8177 00:40:33.468078 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 00:40:33.471707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 00:40:33.471816 ==
8180 00:40:33.471912
8181 00:40:33.472002
8182 00:40:33.475106 TX Vref Scan disable
8183 00:40:33.481586 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8184 00:40:33.481687 == TX Byte 0 ==
8185 00:40:33.484742 u2DelayCellOfst[0]=13 cells (4 PI)
8186 00:40:33.487951 u2DelayCellOfst[1]=20 cells (6 PI)
8187 00:40:33.491470 u2DelayCellOfst[2]=13 cells (4 PI)
8188 00:40:33.494717 u2DelayCellOfst[3]=13 cells (4 PI)
8189 00:40:33.498106 u2DelayCellOfst[4]=10 cells (3 PI)
8190 00:40:33.501395 u2DelayCellOfst[5]=0 cells (0 PI)
8191 00:40:33.504713 u2DelayCellOfst[6]=20 cells (6 PI)
8192 00:40:33.507830 u2DelayCellOfst[7]=16 cells (5 PI)
8193 00:40:33.511541 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8194 00:40:33.514467 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8195 00:40:33.518176 == TX Byte 1 ==
8196 00:40:33.518254 u2DelayCellOfst[8]=0 cells (0 PI)
8197 00:40:33.521075 u2DelayCellOfst[9]=3 cells (1 PI)
8198 00:40:33.524715 u2DelayCellOfst[10]=6 cells (2 PI)
8199 00:40:33.528002 u2DelayCellOfst[11]=3 cells (1 PI)
8200 00:40:33.531415 u2DelayCellOfst[12]=13 cells (4 PI)
8201 00:40:33.534446 u2DelayCellOfst[13]=13 cells (4 PI)
8202 00:40:33.537916 u2DelayCellOfst[14]=16 cells (5 PI)
8203 00:40:33.541363 u2DelayCellOfst[15]=10 cells (3 PI)
8204 00:40:33.544466 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8205 00:40:33.551312 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8206 00:40:33.551421 DramC Write-DBI on
8207 00:40:33.551514 ==
8208 00:40:33.554721 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 00:40:33.557659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 00:40:33.561105 ==
8211 00:40:33.561186
8212 00:40:33.561278
8213 00:40:33.561368 TX Vref Scan disable
8214 00:40:33.564725 == TX Byte 0 ==
8215 00:40:33.568063 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8216 00:40:33.571601 == TX Byte 1 ==
8217 00:40:33.574892 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8218 00:40:33.578132 DramC Write-DBI off
8219 00:40:33.578215
8220 00:40:33.578310 [DATLAT]
8221 00:40:33.578402 Freq=1600, CH0 RK1
8222 00:40:33.578490
8223 00:40:33.581111 DATLAT Default: 0xf
8224 00:40:33.581211 0, 0xFFFF, sum = 0
8225 00:40:33.584499 1, 0xFFFF, sum = 0
8226 00:40:33.584630 2, 0xFFFF, sum = 0
8227 00:40:33.587932 3, 0xFFFF, sum = 0
8228 00:40:33.591621 4, 0xFFFF, sum = 0
8229 00:40:33.591700 5, 0xFFFF, sum = 0
8230 00:40:33.594748 6, 0xFFFF, sum = 0
8231 00:40:33.594828 7, 0xFFFF, sum = 0
8232 00:40:33.597924 8, 0xFFFF, sum = 0
8233 00:40:33.597998 9, 0xFFFF, sum = 0
8234 00:40:33.601088 10, 0xFFFF, sum = 0
8235 00:40:33.601162 11, 0xFFFF, sum = 0
8236 00:40:33.604741 12, 0xFFFF, sum = 0
8237 00:40:33.604844 13, 0xFFFF, sum = 0
8238 00:40:33.608067 14, 0x0, sum = 1
8239 00:40:33.608141 15, 0x0, sum = 2
8240 00:40:33.611268 16, 0x0, sum = 3
8241 00:40:33.611371 17, 0x0, sum = 4
8242 00:40:33.614794 best_step = 15
8243 00:40:33.614884
8244 00:40:33.614947 ==
8245 00:40:33.618163 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 00:40:33.621180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 00:40:33.621303 ==
8248 00:40:33.621396 RX Vref Scan: 0
8249 00:40:33.624810
8250 00:40:33.624914 RX Vref 0 -> 0, step: 1
8251 00:40:33.625006
8252 00:40:33.627979 RX Delay 11 -> 252, step: 4
8253 00:40:33.631143 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8254 00:40:33.638072 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8255 00:40:33.641071 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8256 00:40:33.644737 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8257 00:40:33.648121 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8258 00:40:33.651221 iDelay=191, Bit 5, Center 122 (71 ~ 174) 104
8259 00:40:33.654397 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8260 00:40:33.661327 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8261 00:40:33.664597 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8262 00:40:33.668039 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8263 00:40:33.671348 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8264 00:40:33.674438 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8265 00:40:33.681112 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8266 00:40:33.684806 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8267 00:40:33.688016 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8268 00:40:33.691393 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8269 00:40:33.691469 ==
8270 00:40:33.694332 Dram Type= 6, Freq= 0, CH_0, rank 1
8271 00:40:33.701203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 00:40:33.701284 ==
8273 00:40:33.701353 DQS Delay:
8274 00:40:33.704369 DQS0 = 0, DQS1 = 0
8275 00:40:33.704467 DQM Delay:
8276 00:40:33.707926 DQM0 = 132, DQM1 = 123
8277 00:40:33.708026 DQ Delay:
8278 00:40:33.711111 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8279 00:40:33.714605 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =140
8280 00:40:33.717862 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8281 00:40:33.721116 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8282 00:40:33.721191
8283 00:40:33.721254
8284 00:40:33.721317
8285 00:40:33.724530 [DramC_TX_OE_Calibration] TA2
8286 00:40:33.727654 Original DQ_B0 (3 6) =30, OEN = 27
8287 00:40:33.731359 Original DQ_B1 (3 6) =30, OEN = 27
8288 00:40:33.734424 24, 0x0, End_B0=24 End_B1=24
8289 00:40:33.734528 25, 0x0, End_B0=25 End_B1=25
8290 00:40:33.737639 26, 0x0, End_B0=26 End_B1=26
8291 00:40:33.741084 27, 0x0, End_B0=27 End_B1=27
8292 00:40:33.744450 28, 0x0, End_B0=28 End_B1=28
8293 00:40:33.747918 29, 0x0, End_B0=29 End_B1=29
8294 00:40:33.748020 30, 0x0, End_B0=30 End_B1=30
8295 00:40:33.751473 31, 0x4141, End_B0=30 End_B1=30
8296 00:40:33.754587 Byte0 end_step=30 best_step=27
8297 00:40:33.757975 Byte1 end_step=30 best_step=27
8298 00:40:33.761231 Byte0 TX OE(2T, 0.5T) = (3, 3)
8299 00:40:33.761400 Byte1 TX OE(2T, 0.5T) = (3, 3)
8300 00:40:33.764536
8301 00:40:33.764706
8302 00:40:33.771138 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8303 00:40:33.774482 CH0 RK1: MR19=303, MR18=210E
8304 00:40:33.781110 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8305 00:40:33.784246 [RxdqsGatingPostProcess] freq 1600
8306 00:40:33.787932 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8307 00:40:33.791270 best DQS0 dly(2T, 0.5T) = (1, 1)
8308 00:40:33.794694 best DQS1 dly(2T, 0.5T) = (1, 1)
8309 00:40:33.797804 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8310 00:40:33.801137 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8311 00:40:33.804197 best DQS0 dly(2T, 0.5T) = (1, 1)
8312 00:40:33.807664 best DQS1 dly(2T, 0.5T) = (1, 1)
8313 00:40:33.810897 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8314 00:40:33.814405 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8315 00:40:33.817716 Pre-setting of DQS Precalculation
8316 00:40:33.821137 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8317 00:40:33.821216 ==
8318 00:40:33.824267 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 00:40:33.827630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 00:40:33.827707 ==
8321 00:40:33.834177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8322 00:40:33.837371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8323 00:40:33.844419 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8324 00:40:33.847439 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8325 00:40:33.857594 [CA 0] Center 42 (13~72) winsize 60
8326 00:40:33.861048 [CA 1] Center 42 (12~72) winsize 61
8327 00:40:33.864259 [CA 2] Center 38 (9~68) winsize 60
8328 00:40:33.867631 [CA 3] Center 37 (8~67) winsize 60
8329 00:40:33.871235 [CA 4] Center 37 (7~67) winsize 61
8330 00:40:33.874171 [CA 5] Center 37 (7~67) winsize 61
8331 00:40:33.874258
8332 00:40:33.877401 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8333 00:40:33.877485
8334 00:40:33.880914 [CATrainingPosCal] consider 1 rank data
8335 00:40:33.884306 u2DelayCellTimex100 = 290/100 ps
8336 00:40:33.887896 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8337 00:40:33.894281 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8338 00:40:33.897568 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8339 00:40:33.900785 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8340 00:40:33.904296 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8341 00:40:33.907552 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8342 00:40:33.907636
8343 00:40:33.911024 CA PerBit enable=1, Macro0, CA PI delay=37
8344 00:40:33.911108
8345 00:40:33.914242 [CBTSetCACLKResult] CA Dly = 37
8346 00:40:33.914326 CS Dly: 8 (0~39)
8347 00:40:33.920959 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8348 00:40:33.924146 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8349 00:40:33.924230 ==
8350 00:40:33.927922 Dram Type= 6, Freq= 0, CH_1, rank 1
8351 00:40:33.930665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 00:40:33.930750 ==
8353 00:40:33.937596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8354 00:40:33.940717 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8355 00:40:33.947739 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8356 00:40:33.950681 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8357 00:40:33.960917 [CA 0] Center 42 (12~72) winsize 61
8358 00:40:33.963890 [CA 1] Center 41 (11~72) winsize 62
8359 00:40:33.967544 [CA 2] Center 37 (8~67) winsize 60
8360 00:40:33.970646 [CA 3] Center 37 (8~66) winsize 59
8361 00:40:33.974186 [CA 4] Center 37 (8~67) winsize 60
8362 00:40:33.977259 [CA 5] Center 36 (7~66) winsize 60
8363 00:40:33.977345
8364 00:40:33.980568 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8365 00:40:33.980663
8366 00:40:33.984009 [CATrainingPosCal] consider 2 rank data
8367 00:40:33.987722 u2DelayCellTimex100 = 290/100 ps
8368 00:40:33.990740 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
8369 00:40:33.997527 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8370 00:40:34.000737 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8371 00:40:34.003885 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8372 00:40:34.007363 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8373 00:40:34.010874 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8374 00:40:34.010957
8375 00:40:34.013982 CA PerBit enable=1, Macro0, CA PI delay=36
8376 00:40:34.014064
8377 00:40:34.017424 [CBTSetCACLKResult] CA Dly = 36
8378 00:40:34.017506 CS Dly: 9 (0~41)
8379 00:40:34.024054 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8380 00:40:34.027158 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8381 00:40:34.027241
8382 00:40:34.030873 ----->DramcWriteLeveling(PI) begin...
8383 00:40:34.030957 ==
8384 00:40:34.033912 Dram Type= 6, Freq= 0, CH_1, rank 0
8385 00:40:34.037356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 00:40:34.040700 ==
8387 00:40:34.040783 Write leveling (Byte 0): 24 => 24
8388 00:40:34.043962 Write leveling (Byte 1): 29 => 29
8389 00:40:34.047248 DramcWriteLeveling(PI) end<-----
8390 00:40:34.047329
8391 00:40:34.047394 ==
8392 00:40:34.050486 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 00:40:34.057383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 00:40:34.057465 ==
8395 00:40:34.057530 [Gating] SW mode calibration
8396 00:40:34.067055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8397 00:40:34.070509 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8398 00:40:34.073872 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 00:40:34.080733 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 00:40:34.083851 1 4 8 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (1 1)
8401 00:40:34.087696 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 00:40:34.094089 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 00:40:34.097625 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 00:40:34.100756 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 00:40:34.107171 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 00:40:34.110815 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 00:40:34.113740 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8408 00:40:34.120648 1 5 8 | B1->B0 | 3333 2e2e | 1 1 | (0 0) (0 1)
8409 00:40:34.124112 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8410 00:40:34.127153 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 00:40:34.133913 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 00:40:34.137143 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 00:40:34.140963 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 00:40:34.147197 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 00:40:34.150369 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8416 00:40:34.154155 1 6 8 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
8417 00:40:34.160540 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 00:40:34.164036 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 00:40:34.167333 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 00:40:34.170457 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 00:40:34.177075 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 00:40:34.180352 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 00:40:34.183634 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8424 00:40:34.190672 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8425 00:40:34.193865 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8426 00:40:34.197158 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8427 00:40:34.203770 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 00:40:34.207165 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 00:40:34.210544 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 00:40:34.217118 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 00:40:34.220689 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 00:40:34.223633 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 00:40:34.230345 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 00:40:34.233495 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 00:40:34.237154 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 00:40:34.243561 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 00:40:34.246750 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 00:40:34.250383 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 00:40:34.257106 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8440 00:40:34.259975 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8441 00:40:34.263125 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8442 00:40:34.266713 Total UI for P1: 0, mck2ui 16
8443 00:40:34.270009 best dqsien dly found for B0: ( 1, 9, 6)
8444 00:40:34.276642 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 00:40:34.276735 Total UI for P1: 0, mck2ui 16
8446 00:40:34.283108 best dqsien dly found for B1: ( 1, 9, 10)
8447 00:40:34.286698 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8448 00:40:34.289920 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8449 00:40:34.290011
8450 00:40:34.293476 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8451 00:40:34.296781 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8452 00:40:34.300229 [Gating] SW calibration Done
8453 00:40:34.300330 ==
8454 00:40:34.303458 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 00:40:34.306724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 00:40:34.306805 ==
8457 00:40:34.309708 RX Vref Scan: 0
8458 00:40:34.309812
8459 00:40:34.309905 RX Vref 0 -> 0, step: 1
8460 00:40:34.309998
8461 00:40:34.313240 RX Delay 0 -> 252, step: 8
8462 00:40:34.316652 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8463 00:40:34.319767 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8464 00:40:34.326474 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8465 00:40:34.329643 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8466 00:40:34.333432 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8467 00:40:34.336507 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8468 00:40:34.340115 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8469 00:40:34.346425 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8470 00:40:34.349866 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8471 00:40:34.353036 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8472 00:40:34.356557 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8473 00:40:34.359817 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8474 00:40:34.366683 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8475 00:40:34.369680 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8476 00:40:34.372928 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8477 00:40:34.376320 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8478 00:40:34.376423 ==
8479 00:40:34.379906 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 00:40:34.386401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 00:40:34.386506 ==
8482 00:40:34.386604 DQS Delay:
8483 00:40:34.386699 DQS0 = 0, DQS1 = 0
8484 00:40:34.389672 DQM Delay:
8485 00:40:34.389772 DQM0 = 137, DQM1 = 129
8486 00:40:34.393170 DQ Delay:
8487 00:40:34.396615 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8488 00:40:34.399940 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8489 00:40:34.403277 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8490 00:40:34.406437 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8491 00:40:34.406521
8492 00:40:34.406587
8493 00:40:34.406649 ==
8494 00:40:34.409989 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 00:40:34.413229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 00:40:34.413314 ==
8497 00:40:34.416336
8498 00:40:34.416419
8499 00:40:34.416485 TX Vref Scan disable
8500 00:40:34.419812 == TX Byte 0 ==
8501 00:40:34.423347 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8502 00:40:34.426686 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8503 00:40:34.429910 == TX Byte 1 ==
8504 00:40:34.433208 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8505 00:40:34.436236 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8506 00:40:34.436321 ==
8507 00:40:34.439587 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 00:40:34.446279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 00:40:34.446364 ==
8510 00:40:34.459022
8511 00:40:34.462589 TX Vref early break, caculate TX vref
8512 00:40:34.465846 TX Vref=16, minBit 9, minWin=22, winSum=373
8513 00:40:34.469216 TX Vref=18, minBit 12, minWin=22, winSum=380
8514 00:40:34.472406 TX Vref=20, minBit 15, minWin=23, winSum=392
8515 00:40:34.475741 TX Vref=22, minBit 3, minWin=24, winSum=403
8516 00:40:34.479273 TX Vref=24, minBit 15, minWin=24, winSum=415
8517 00:40:34.485493 TX Vref=26, minBit 13, minWin=25, winSum=419
8518 00:40:34.488907 TX Vref=28, minBit 10, minWin=25, winSum=423
8519 00:40:34.492274 TX Vref=30, minBit 10, minWin=24, winSum=418
8520 00:40:34.495406 TX Vref=32, minBit 10, minWin=24, winSum=411
8521 00:40:34.499098 TX Vref=34, minBit 13, minWin=23, winSum=403
8522 00:40:34.505467 TX Vref=36, minBit 10, minWin=22, winSum=387
8523 00:40:34.509024 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 28
8524 00:40:34.509111
8525 00:40:34.512121 Final TX Range 0 Vref 28
8526 00:40:34.512206
8527 00:40:34.512277 ==
8528 00:40:34.515489 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 00:40:34.518830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 00:40:34.522373 ==
8531 00:40:34.522458
8532 00:40:34.522525
8533 00:40:34.522587 TX Vref Scan disable
8534 00:40:34.529161 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8535 00:40:34.529245 == TX Byte 0 ==
8536 00:40:34.532310 u2DelayCellOfst[0]=16 cells (5 PI)
8537 00:40:34.535601 u2DelayCellOfst[1]=10 cells (3 PI)
8538 00:40:34.538912 u2DelayCellOfst[2]=0 cells (0 PI)
8539 00:40:34.542419 u2DelayCellOfst[3]=6 cells (2 PI)
8540 00:40:34.545646 u2DelayCellOfst[4]=6 cells (2 PI)
8541 00:40:34.549144 u2DelayCellOfst[5]=16 cells (5 PI)
8542 00:40:34.552396 u2DelayCellOfst[6]=16 cells (5 PI)
8543 00:40:34.555968 u2DelayCellOfst[7]=3 cells (1 PI)
8544 00:40:34.559028 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8545 00:40:34.562302 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8546 00:40:34.565890 == TX Byte 1 ==
8547 00:40:34.569312 u2DelayCellOfst[8]=0 cells (0 PI)
8548 00:40:34.572619 u2DelayCellOfst[9]=0 cells (0 PI)
8549 00:40:34.575750 u2DelayCellOfst[10]=6 cells (2 PI)
8550 00:40:34.575830 u2DelayCellOfst[11]=3 cells (1 PI)
8551 00:40:34.579271 u2DelayCellOfst[12]=13 cells (4 PI)
8552 00:40:34.582316 u2DelayCellOfst[13]=13 cells (4 PI)
8553 00:40:34.585882 u2DelayCellOfst[14]=13 cells (4 PI)
8554 00:40:34.589202 u2DelayCellOfst[15]=13 cells (4 PI)
8555 00:40:34.595598 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8556 00:40:34.598895 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8557 00:40:34.598974 DramC Write-DBI on
8558 00:40:34.599056 ==
8559 00:40:34.602350 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 00:40:34.608911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 00:40:34.608991 ==
8562 00:40:34.609073
8563 00:40:34.609156
8564 00:40:34.609231 TX Vref Scan disable
8565 00:40:34.613167 == TX Byte 0 ==
8566 00:40:34.616508 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8567 00:40:34.619861 == TX Byte 1 ==
8568 00:40:34.622998 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8569 00:40:34.623139 DramC Write-DBI off
8570 00:40:34.626367
8571 00:40:34.626451 [DATLAT]
8572 00:40:34.626517 Freq=1600, CH1 RK0
8573 00:40:34.626580
8574 00:40:34.629562 DATLAT Default: 0xf
8575 00:40:34.629645 0, 0xFFFF, sum = 0
8576 00:40:34.632798 1, 0xFFFF, sum = 0
8577 00:40:34.632883 2, 0xFFFF, sum = 0
8578 00:40:34.636374 3, 0xFFFF, sum = 0
8579 00:40:34.639628 4, 0xFFFF, sum = 0
8580 00:40:34.639714 5, 0xFFFF, sum = 0
8581 00:40:34.642900 6, 0xFFFF, sum = 0
8582 00:40:34.642985 7, 0xFFFF, sum = 0
8583 00:40:34.646091 8, 0xFFFF, sum = 0
8584 00:40:34.646177 9, 0xFFFF, sum = 0
8585 00:40:34.649603 10, 0xFFFF, sum = 0
8586 00:40:34.649689 11, 0xFFFF, sum = 0
8587 00:40:34.652849 12, 0xFFFF, sum = 0
8588 00:40:34.652934 13, 0xFFFF, sum = 0
8589 00:40:34.656710 14, 0x0, sum = 1
8590 00:40:34.656795 15, 0x0, sum = 2
8591 00:40:34.659789 16, 0x0, sum = 3
8592 00:40:34.659875 17, 0x0, sum = 4
8593 00:40:34.662951 best_step = 15
8594 00:40:34.663035
8595 00:40:34.663103 ==
8596 00:40:34.666494 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 00:40:34.669885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 00:40:34.669970 ==
8599 00:40:34.670037 RX Vref Scan: 1
8600 00:40:34.670099
8601 00:40:34.673152 Set Vref Range= 24 -> 127
8602 00:40:34.673237
8603 00:40:34.676380 RX Vref 24 -> 127, step: 1
8604 00:40:34.676465
8605 00:40:34.680061 RX Delay 19 -> 252, step: 4
8606 00:40:34.680145
8607 00:40:34.683340 Set Vref, RX VrefLevel [Byte0]: 24
8608 00:40:34.686553 [Byte1]: 24
8609 00:40:34.686638
8610 00:40:34.689583 Set Vref, RX VrefLevel [Byte0]: 25
8611 00:40:34.692997 [Byte1]: 25
8612 00:40:34.693081
8613 00:40:34.696509 Set Vref, RX VrefLevel [Byte0]: 26
8614 00:40:34.699642 [Byte1]: 26
8615 00:40:34.703214
8616 00:40:34.703298 Set Vref, RX VrefLevel [Byte0]: 27
8617 00:40:34.706599 [Byte1]: 27
8618 00:40:34.710992
8619 00:40:34.711093 Set Vref, RX VrefLevel [Byte0]: 28
8620 00:40:34.713986 [Byte1]: 28
8621 00:40:34.718437
8622 00:40:34.718535 Set Vref, RX VrefLevel [Byte0]: 29
8623 00:40:34.721520 [Byte1]: 29
8624 00:40:34.725974
8625 00:40:34.726046 Set Vref, RX VrefLevel [Byte0]: 30
8626 00:40:34.729135 [Byte1]: 30
8627 00:40:34.733447
8628 00:40:34.733547 Set Vref, RX VrefLevel [Byte0]: 31
8629 00:40:34.737111 [Byte1]: 31
8630 00:40:34.741253
8631 00:40:34.741328 Set Vref, RX VrefLevel [Byte0]: 32
8632 00:40:34.744427 [Byte1]: 32
8633 00:40:34.748477
8634 00:40:34.748614 Set Vref, RX VrefLevel [Byte0]: 33
8635 00:40:34.752067 [Byte1]: 33
8636 00:40:34.756397
8637 00:40:34.756497 Set Vref, RX VrefLevel [Byte0]: 34
8638 00:40:34.759533 [Byte1]: 34
8639 00:40:34.763695
8640 00:40:34.763794 Set Vref, RX VrefLevel [Byte0]: 35
8641 00:40:34.767092 [Byte1]: 35
8642 00:40:34.771173
8643 00:40:34.771275 Set Vref, RX VrefLevel [Byte0]: 36
8644 00:40:34.774615 [Byte1]: 36
8645 00:40:34.778928
8646 00:40:34.779030 Set Vref, RX VrefLevel [Byte0]: 37
8647 00:40:34.782065 [Byte1]: 37
8648 00:40:34.786701
8649 00:40:34.786804 Set Vref, RX VrefLevel [Byte0]: 38
8650 00:40:34.789728 [Byte1]: 38
8651 00:40:34.794326
8652 00:40:34.794433 Set Vref, RX VrefLevel [Byte0]: 39
8653 00:40:34.797261 [Byte1]: 39
8654 00:40:34.801758
8655 00:40:34.801903 Set Vref, RX VrefLevel [Byte0]: 40
8656 00:40:34.804826 [Byte1]: 40
8657 00:40:34.809446
8658 00:40:34.809560 Set Vref, RX VrefLevel [Byte0]: 41
8659 00:40:34.812565 [Byte1]: 41
8660 00:40:34.817111
8661 00:40:34.817257 Set Vref, RX VrefLevel [Byte0]: 42
8662 00:40:34.820030 [Byte1]: 42
8663 00:40:34.824567
8664 00:40:34.824772 Set Vref, RX VrefLevel [Byte0]: 43
8665 00:40:34.827463 [Byte1]: 43
8666 00:40:34.831619
8667 00:40:34.835172 Set Vref, RX VrefLevel [Byte0]: 44
8668 00:40:34.838307 [Byte1]: 44
8669 00:40:34.838409
8670 00:40:34.841456 Set Vref, RX VrefLevel [Byte0]: 45
8671 00:40:34.844993 [Byte1]: 45
8672 00:40:34.845070
8673 00:40:34.848334 Set Vref, RX VrefLevel [Byte0]: 46
8674 00:40:34.851507 [Byte1]: 46
8675 00:40:34.851582
8676 00:40:34.854991 Set Vref, RX VrefLevel [Byte0]: 47
8677 00:40:34.858261 [Byte1]: 47
8678 00:40:34.862413
8679 00:40:34.862500 Set Vref, RX VrefLevel [Byte0]: 48
8680 00:40:34.865563 [Byte1]: 48
8681 00:40:34.870025
8682 00:40:34.870123 Set Vref, RX VrefLevel [Byte0]: 49
8683 00:40:34.873279 [Byte1]: 49
8684 00:40:34.877327
8685 00:40:34.877409 Set Vref, RX VrefLevel [Byte0]: 50
8686 00:40:34.880777 [Byte1]: 50
8687 00:40:34.884989
8688 00:40:34.885094 Set Vref, RX VrefLevel [Byte0]: 51
8689 00:40:34.888236 [Byte1]: 51
8690 00:40:34.892499
8691 00:40:34.892625 Set Vref, RX VrefLevel [Byte0]: 52
8692 00:40:34.896136 [Byte1]: 52
8693 00:40:34.900258
8694 00:40:34.900341 Set Vref, RX VrefLevel [Byte0]: 53
8695 00:40:34.903427 [Byte1]: 53
8696 00:40:34.907756
8697 00:40:34.907840 Set Vref, RX VrefLevel [Byte0]: 54
8698 00:40:34.910962 [Byte1]: 54
8699 00:40:34.915349
8700 00:40:34.915461 Set Vref, RX VrefLevel [Byte0]: 55
8701 00:40:34.918469 [Byte1]: 55
8702 00:40:34.922681
8703 00:40:34.922770 Set Vref, RX VrefLevel [Byte0]: 56
8704 00:40:34.926154 [Byte1]: 56
8705 00:40:34.930518
8706 00:40:34.930601 Set Vref, RX VrefLevel [Byte0]: 57
8707 00:40:34.933657 [Byte1]: 57
8708 00:40:34.937900
8709 00:40:34.937984 Set Vref, RX VrefLevel [Byte0]: 58
8710 00:40:34.941148 [Byte1]: 58
8711 00:40:34.945696
8712 00:40:34.945780 Set Vref, RX VrefLevel [Byte0]: 59
8713 00:40:34.949159 [Byte1]: 59
8714 00:40:34.953495
8715 00:40:34.953581 Set Vref, RX VrefLevel [Byte0]: 60
8716 00:40:34.956494 [Byte1]: 60
8717 00:40:34.960735
8718 00:40:34.960818 Set Vref, RX VrefLevel [Byte0]: 61
8719 00:40:34.964000 [Byte1]: 61
8720 00:40:34.968132
8721 00:40:34.968217 Set Vref, RX VrefLevel [Byte0]: 62
8722 00:40:34.971708 [Byte1]: 62
8723 00:40:34.975955
8724 00:40:34.976041 Set Vref, RX VrefLevel [Byte0]: 63
8725 00:40:34.979412 [Byte1]: 63
8726 00:40:34.983414
8727 00:40:34.983498 Set Vref, RX VrefLevel [Byte0]: 64
8728 00:40:34.986498 [Byte1]: 64
8729 00:40:34.991031
8730 00:40:34.991115 Set Vref, RX VrefLevel [Byte0]: 65
8731 00:40:34.994378 [Byte1]: 65
8732 00:40:34.998698
8733 00:40:34.998782 Set Vref, RX VrefLevel [Byte0]: 66
8734 00:40:35.001699 [Byte1]: 66
8735 00:40:35.006237
8736 00:40:35.006320 Set Vref, RX VrefLevel [Byte0]: 67
8737 00:40:35.009344 [Byte1]: 67
8738 00:40:35.013531
8739 00:40:35.013614 Set Vref, RX VrefLevel [Byte0]: 68
8740 00:40:35.016893 [Byte1]: 68
8741 00:40:35.021119
8742 00:40:35.021217 Set Vref, RX VrefLevel [Byte0]: 69
8743 00:40:35.024439 [Byte1]: 69
8744 00:40:35.028926
8745 00:40:35.029010 Set Vref, RX VrefLevel [Byte0]: 70
8746 00:40:35.032162 [Byte1]: 70
8747 00:40:35.036376
8748 00:40:35.036461 Set Vref, RX VrefLevel [Byte0]: 71
8749 00:40:35.039972 [Byte1]: 71
8750 00:40:35.043984
8751 00:40:35.044070 Set Vref, RX VrefLevel [Byte0]: 72
8752 00:40:35.047133 [Byte1]: 72
8753 00:40:35.051436
8754 00:40:35.051520 Set Vref, RX VrefLevel [Byte0]: 73
8755 00:40:35.054677 [Byte1]: 73
8756 00:40:35.059344
8757 00:40:35.059428 Set Vref, RX VrefLevel [Byte0]: 74
8758 00:40:35.062767 [Byte1]: 74
8759 00:40:35.066843
8760 00:40:35.066927 Final RX Vref Byte 0 = 57 to rank0
8761 00:40:35.070314 Final RX Vref Byte 1 = 65 to rank0
8762 00:40:35.073425 Final RX Vref Byte 0 = 57 to rank1
8763 00:40:35.076760 Final RX Vref Byte 1 = 65 to rank1==
8764 00:40:35.080313 Dram Type= 6, Freq= 0, CH_1, rank 0
8765 00:40:35.086490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 00:40:35.086575 ==
8767 00:40:35.086643 DQS Delay:
8768 00:40:35.086705 DQS0 = 0, DQS1 = 0
8769 00:40:35.089896 DQM Delay:
8770 00:40:35.089979 DQM0 = 134, DQM1 = 128
8771 00:40:35.093176 DQ Delay:
8772 00:40:35.096143 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8773 00:40:35.099485 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8774 00:40:35.102739 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8775 00:40:35.106194 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8776 00:40:35.106278
8777 00:40:35.106345
8778 00:40:35.106407
8779 00:40:35.109718 [DramC_TX_OE_Calibration] TA2
8780 00:40:35.112821 Original DQ_B0 (3 6) =30, OEN = 27
8781 00:40:35.116459 Original DQ_B1 (3 6) =30, OEN = 27
8782 00:40:35.119416 24, 0x0, End_B0=24 End_B1=24
8783 00:40:35.119501 25, 0x0, End_B0=25 End_B1=25
8784 00:40:35.123050 26, 0x0, End_B0=26 End_B1=26
8785 00:40:35.126297 27, 0x0, End_B0=27 End_B1=27
8786 00:40:35.129529 28, 0x0, End_B0=28 End_B1=28
8787 00:40:35.132873 29, 0x0, End_B0=29 End_B1=29
8788 00:40:35.132958 30, 0x0, End_B0=30 End_B1=30
8789 00:40:35.136377 31, 0x4141, End_B0=30 End_B1=30
8790 00:40:35.139805 Byte0 end_step=30 best_step=27
8791 00:40:35.143149 Byte1 end_step=30 best_step=27
8792 00:40:35.146315 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 00:40:35.149351 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 00:40:35.149434
8795 00:40:35.149501
8796 00:40:35.156345 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8797 00:40:35.159530 CH1 RK0: MR19=303, MR18=1A28
8798 00:40:35.166263 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8799 00:40:35.166348
8800 00:40:35.169322 ----->DramcWriteLeveling(PI) begin...
8801 00:40:35.169408 ==
8802 00:40:35.172788 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 00:40:35.176364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 00:40:35.176474 ==
8805 00:40:35.179404 Write leveling (Byte 0): 21 => 21
8806 00:40:35.182859 Write leveling (Byte 1): 28 => 28
8807 00:40:35.186243 DramcWriteLeveling(PI) end<-----
8808 00:40:35.186327
8809 00:40:35.186394 ==
8810 00:40:35.189491 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 00:40:35.192880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 00:40:35.192970 ==
8813 00:40:35.196029 [Gating] SW mode calibration
8814 00:40:35.202603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8815 00:40:35.209247 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8816 00:40:35.213120 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 00:40:35.216231 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 00:40:35.222802 1 4 8 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
8819 00:40:35.225932 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8820 00:40:35.229319 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8821 00:40:35.236221 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 00:40:35.239655 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 00:40:35.242566 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 00:40:35.249357 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 00:40:35.252642 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 00:40:35.256088 1 5 8 | B1->B0 | 2e2e 3434 | 0 1 | (1 0) (1 0)
8827 00:40:35.262802 1 5 12 | B1->B0 | 2323 3232 | 0 0 | (1 0) (0 1)
8828 00:40:35.266104 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 00:40:35.269418 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 00:40:35.275982 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 00:40:35.279557 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 00:40:35.282710 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 00:40:35.289084 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 00:40:35.292615 1 6 8 | B1->B0 | 3d3d 2525 | 1 0 | (0 0) (0 0)
8835 00:40:35.295901 1 6 12 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
8836 00:40:35.302729 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 00:40:35.305898 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 00:40:35.309200 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 00:40:35.313021 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 00:40:35.319531 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 00:40:35.322755 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 00:40:35.326165 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8843 00:40:35.332765 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8844 00:40:35.336137 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 00:40:35.339156 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 00:40:35.345974 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 00:40:35.349292 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 00:40:35.352792 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 00:40:35.359772 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 00:40:35.363073 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 00:40:35.366166 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 00:40:35.372625 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 00:40:35.376340 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 00:40:35.379432 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 00:40:35.385999 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 00:40:35.389216 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 00:40:35.392727 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 00:40:35.399654 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 00:40:35.402387 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 00:40:35.406215 Total UI for P1: 0, mck2ui 16
8861 00:40:35.409313 best dqsien dly found for B0: ( 1, 9, 8)
8862 00:40:35.412457 Total UI for P1: 0, mck2ui 16
8863 00:40:35.415782 best dqsien dly found for B1: ( 1, 9, 8)
8864 00:40:35.419454 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8865 00:40:35.422681 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8866 00:40:35.422766
8867 00:40:35.425976 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8868 00:40:35.429103 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8869 00:40:35.432509 [Gating] SW calibration Done
8870 00:40:35.432624 ==
8871 00:40:35.435866 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 00:40:35.439250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 00:40:35.439336 ==
8874 00:40:35.442746 RX Vref Scan: 0
8875 00:40:35.442829
8876 00:40:35.442906 RX Vref 0 -> 0, step: 1
8877 00:40:35.445848
8878 00:40:35.445922 RX Delay 0 -> 252, step: 8
8879 00:40:35.449090 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8880 00:40:35.455911 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8881 00:40:35.459204 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8882 00:40:35.462549 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8883 00:40:35.465856 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8884 00:40:35.469263 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8885 00:40:35.475941 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8886 00:40:35.478940 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8887 00:40:35.482624 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8888 00:40:35.486164 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8889 00:40:35.489313 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8890 00:40:35.495648 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8891 00:40:35.499316 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8892 00:40:35.502612 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8893 00:40:35.505933 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8894 00:40:35.509204 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8895 00:40:35.512638 ==
8896 00:40:35.512718 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 00:40:35.519253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 00:40:35.519332 ==
8899 00:40:35.519405 DQS Delay:
8900 00:40:35.522437 DQS0 = 0, DQS1 = 0
8901 00:40:35.522537 DQM Delay:
8902 00:40:35.525985 DQM0 = 137, DQM1 = 130
8903 00:40:35.526058 DQ Delay:
8904 00:40:35.529055 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8905 00:40:35.532639 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8906 00:40:35.535768 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8907 00:40:35.539078 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8908 00:40:35.539161
8909 00:40:35.539225
8910 00:40:35.539285 ==
8911 00:40:35.542569 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 00:40:35.549116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 00:40:35.549195 ==
8914 00:40:35.549259
8915 00:40:35.549320
8916 00:40:35.549387 TX Vref Scan disable
8917 00:40:35.552481 == TX Byte 0 ==
8918 00:40:35.556280 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8919 00:40:35.559230 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8920 00:40:35.562709 == TX Byte 1 ==
8921 00:40:35.565846 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8922 00:40:35.572563 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8923 00:40:35.572663 ==
8924 00:40:35.575759 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 00:40:35.579006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 00:40:35.579083 ==
8927 00:40:35.591626
8928 00:40:35.594943 TX Vref early break, caculate TX vref
8929 00:40:35.598643 TX Vref=16, minBit 12, minWin=23, winSum=389
8930 00:40:35.601724 TX Vref=18, minBit 13, minWin=23, winSum=397
8931 00:40:35.605503 TX Vref=20, minBit 9, minWin=24, winSum=403
8932 00:40:35.608128 TX Vref=22, minBit 9, minWin=25, winSum=416
8933 00:40:35.612006 TX Vref=24, minBit 0, minWin=25, winSum=421
8934 00:40:35.618597 TX Vref=26, minBit 9, minWin=25, winSum=424
8935 00:40:35.621877 TX Vref=28, minBit 0, minWin=26, winSum=428
8936 00:40:35.625272 TX Vref=30, minBit 10, minWin=25, winSum=420
8937 00:40:35.628256 TX Vref=32, minBit 1, minWin=25, winSum=414
8938 00:40:35.631546 TX Vref=34, minBit 10, minWin=24, winSum=403
8939 00:40:35.638051 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8940 00:40:35.638136
8941 00:40:35.641554 Final TX Range 0 Vref 28
8942 00:40:35.641638
8943 00:40:35.641709 ==
8944 00:40:35.645133 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 00:40:35.648468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 00:40:35.648609 ==
8947 00:40:35.648676
8948 00:40:35.648738
8949 00:40:35.651431 TX Vref Scan disable
8950 00:40:35.658278 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8951 00:40:35.658363 == TX Byte 0 ==
8952 00:40:35.661622 u2DelayCellOfst[0]=16 cells (5 PI)
8953 00:40:35.664915 u2DelayCellOfst[1]=13 cells (4 PI)
8954 00:40:35.668391 u2DelayCellOfst[2]=0 cells (0 PI)
8955 00:40:35.671617 u2DelayCellOfst[3]=6 cells (2 PI)
8956 00:40:35.675067 u2DelayCellOfst[4]=10 cells (3 PI)
8957 00:40:35.678264 u2DelayCellOfst[5]=20 cells (6 PI)
8958 00:40:35.681783 u2DelayCellOfst[6]=20 cells (6 PI)
8959 00:40:35.685054 u2DelayCellOfst[7]=6 cells (2 PI)
8960 00:40:35.688292 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8961 00:40:35.691397 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8962 00:40:35.694644 == TX Byte 1 ==
8963 00:40:35.698335 u2DelayCellOfst[8]=0 cells (0 PI)
8964 00:40:35.698420 u2DelayCellOfst[9]=3 cells (1 PI)
8965 00:40:35.701429 u2DelayCellOfst[10]=6 cells (2 PI)
8966 00:40:35.705011 u2DelayCellOfst[11]=3 cells (1 PI)
8967 00:40:35.708433 u2DelayCellOfst[12]=10 cells (3 PI)
8968 00:40:35.711392 u2DelayCellOfst[13]=10 cells (3 PI)
8969 00:40:35.714798 u2DelayCellOfst[14]=13 cells (4 PI)
8970 00:40:35.717760 u2DelayCellOfst[15]=13 cells (4 PI)
8971 00:40:35.721763 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8972 00:40:35.727836 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8973 00:40:35.727922 DramC Write-DBI on
8974 00:40:35.727990 ==
8975 00:40:35.731579 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 00:40:35.734549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 00:40:35.738103 ==
8978 00:40:35.738188
8979 00:40:35.738255
8980 00:40:35.738319 TX Vref Scan disable
8981 00:40:35.741438 == TX Byte 0 ==
8982 00:40:35.745019 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8983 00:40:35.748377 == TX Byte 1 ==
8984 00:40:35.751588 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8985 00:40:35.754938 DramC Write-DBI off
8986 00:40:35.755021
8987 00:40:35.755086 [DATLAT]
8988 00:40:35.755148 Freq=1600, CH1 RK1
8989 00:40:35.755209
8990 00:40:35.758243 DATLAT Default: 0xf
8991 00:40:35.758326 0, 0xFFFF, sum = 0
8992 00:40:35.761387 1, 0xFFFF, sum = 0
8993 00:40:35.761472 2, 0xFFFF, sum = 0
8994 00:40:35.764555 3, 0xFFFF, sum = 0
8995 00:40:35.768183 4, 0xFFFF, sum = 0
8996 00:40:35.768267 5, 0xFFFF, sum = 0
8997 00:40:35.771595 6, 0xFFFF, sum = 0
8998 00:40:35.771680 7, 0xFFFF, sum = 0
8999 00:40:35.774790 8, 0xFFFF, sum = 0
9000 00:40:35.774875 9, 0xFFFF, sum = 0
9001 00:40:35.778043 10, 0xFFFF, sum = 0
9002 00:40:35.778128 11, 0xFFFF, sum = 0
9003 00:40:35.781635 12, 0xFFFF, sum = 0
9004 00:40:35.781721 13, 0xFFFF, sum = 0
9005 00:40:35.784504 14, 0x0, sum = 1
9006 00:40:35.784625 15, 0x0, sum = 2
9007 00:40:35.787898 16, 0x0, sum = 3
9008 00:40:35.787982 17, 0x0, sum = 4
9009 00:40:35.791399 best_step = 15
9010 00:40:35.791482
9011 00:40:35.791548 ==
9012 00:40:35.794920 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 00:40:35.797961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 00:40:35.798045 ==
9015 00:40:35.798111 RX Vref Scan: 0
9016 00:40:35.801589
9017 00:40:35.801671 RX Vref 0 -> 0, step: 1
9018 00:40:35.801737
9019 00:40:35.804839 RX Delay 19 -> 252, step: 4
9020 00:40:35.808218 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9021 00:40:35.814617 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9022 00:40:35.818069 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
9023 00:40:35.821425 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9024 00:40:35.824657 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9025 00:40:35.828075 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9026 00:40:35.831253 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9027 00:40:35.838217 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9028 00:40:35.841665 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9029 00:40:35.844525 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9030 00:40:35.848022 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9031 00:40:35.851562 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9032 00:40:35.858135 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9033 00:40:35.861164 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9034 00:40:35.864856 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9035 00:40:35.867738 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9036 00:40:35.867838 ==
9037 00:40:35.871421 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 00:40:35.874920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 00:40:35.878046 ==
9040 00:40:35.878136 DQS Delay:
9041 00:40:35.878203 DQS0 = 0, DQS1 = 0
9042 00:40:35.881497 DQM Delay:
9043 00:40:35.881586 DQM0 = 134, DQM1 = 129
9044 00:40:35.884472 DQ Delay:
9045 00:40:35.888031 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =132
9046 00:40:35.891256 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9047 00:40:35.894592 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9048 00:40:35.898098 DQ12 =136, DQ13 =136, DQ14 =138, DQ15 =138
9049 00:40:35.898187
9050 00:40:35.898256
9051 00:40:35.898319
9052 00:40:35.901493 [DramC_TX_OE_Calibration] TA2
9053 00:40:35.904510 Original DQ_B0 (3 6) =30, OEN = 27
9054 00:40:35.907702 Original DQ_B1 (3 6) =30, OEN = 27
9055 00:40:35.911220 24, 0x0, End_B0=24 End_B1=24
9056 00:40:35.911306 25, 0x0, End_B0=25 End_B1=25
9057 00:40:35.914767 26, 0x0, End_B0=26 End_B1=26
9058 00:40:35.917959 27, 0x0, End_B0=27 End_B1=27
9059 00:40:35.921139 28, 0x0, End_B0=28 End_B1=28
9060 00:40:35.921256 29, 0x0, End_B0=29 End_B1=29
9061 00:40:35.924743 30, 0x0, End_B0=30 End_B1=30
9062 00:40:35.927820 31, 0x4141, End_B0=30 End_B1=30
9063 00:40:35.931001 Byte0 end_step=30 best_step=27
9064 00:40:35.934917 Byte1 end_step=30 best_step=27
9065 00:40:35.938005 Byte0 TX OE(2T, 0.5T) = (3, 3)
9066 00:40:35.938089 Byte1 TX OE(2T, 0.5T) = (3, 3)
9067 00:40:35.938156
9068 00:40:35.941495
9069 00:40:35.947901 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9070 00:40:35.951263 CH1 RK1: MR19=303, MR18=1C07
9071 00:40:35.957940 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9072 00:40:35.961284 [RxdqsGatingPostProcess] freq 1600
9073 00:40:35.964595 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9074 00:40:35.968009 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 00:40:35.971225 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 00:40:35.974634 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 00:40:35.977866 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 00:40:35.981522 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 00:40:35.984834 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 00:40:35.987963 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 00:40:35.988048 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 00:40:35.991506 Pre-setting of DQS Precalculation
9083 00:40:35.998224 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9084 00:40:36.004760 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9085 00:40:36.011397 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 00:40:36.011483
9087 00:40:36.011550
9088 00:40:36.014639 [Calibration Summary] 3200 Mbps
9089 00:40:36.018081 CH 0, Rank 0
9090 00:40:36.018165 SW Impedance : PASS
9091 00:40:36.021820 DUTY Scan : NO K
9092 00:40:36.021905 ZQ Calibration : PASS
9093 00:40:36.024826 Jitter Meter : NO K
9094 00:40:36.028159 CBT Training : PASS
9095 00:40:36.028242 Write leveling : PASS
9096 00:40:36.031585 RX DQS gating : PASS
9097 00:40:36.034657 RX DQ/DQS(RDDQC) : PASS
9098 00:40:36.034740 TX DQ/DQS : PASS
9099 00:40:36.038141 RX DATLAT : PASS
9100 00:40:36.041616 RX DQ/DQS(Engine): PASS
9101 00:40:36.041699 TX OE : PASS
9102 00:40:36.044711 All Pass.
9103 00:40:36.044794
9104 00:40:36.044859 CH 0, Rank 1
9105 00:40:36.048002 SW Impedance : PASS
9106 00:40:36.048084 DUTY Scan : NO K
9107 00:40:36.051549 ZQ Calibration : PASS
9108 00:40:36.054543 Jitter Meter : NO K
9109 00:40:36.054625 CBT Training : PASS
9110 00:40:36.057982 Write leveling : PASS
9111 00:40:36.061475 RX DQS gating : PASS
9112 00:40:36.061558 RX DQ/DQS(RDDQC) : PASS
9113 00:40:36.064461 TX DQ/DQS : PASS
9114 00:40:36.064544 RX DATLAT : PASS
9115 00:40:36.067806 RX DQ/DQS(Engine): PASS
9116 00:40:36.071283 TX OE : PASS
9117 00:40:36.071366 All Pass.
9118 00:40:36.071431
9119 00:40:36.071491 CH 1, Rank 0
9120 00:40:36.074362 SW Impedance : PASS
9121 00:40:36.077951 DUTY Scan : NO K
9122 00:40:36.078034 ZQ Calibration : PASS
9123 00:40:36.081481 Jitter Meter : NO K
9124 00:40:36.084376 CBT Training : PASS
9125 00:40:36.084459 Write leveling : PASS
9126 00:40:36.088031 RX DQS gating : PASS
9127 00:40:36.091183 RX DQ/DQS(RDDQC) : PASS
9128 00:40:36.091265 TX DQ/DQS : PASS
9129 00:40:36.094562 RX DATLAT : PASS
9130 00:40:36.098382 RX DQ/DQS(Engine): PASS
9131 00:40:36.098465 TX OE : PASS
9132 00:40:36.101078 All Pass.
9133 00:40:36.101160
9134 00:40:36.101226 CH 1, Rank 1
9135 00:40:36.104553 SW Impedance : PASS
9136 00:40:36.104649 DUTY Scan : NO K
9137 00:40:36.107996 ZQ Calibration : PASS
9138 00:40:36.111150 Jitter Meter : NO K
9139 00:40:36.111233 CBT Training : PASS
9140 00:40:36.114392 Write leveling : PASS
9141 00:40:36.117790 RX DQS gating : PASS
9142 00:40:36.117873 RX DQ/DQS(RDDQC) : PASS
9143 00:40:36.121080 TX DQ/DQS : PASS
9144 00:40:36.121163 RX DATLAT : PASS
9145 00:40:36.124299 RX DQ/DQS(Engine): PASS
9146 00:40:36.127517 TX OE : PASS
9147 00:40:36.127601 All Pass.
9148 00:40:36.127667
9149 00:40:36.130902 DramC Write-DBI on
9150 00:40:36.130984 PER_BANK_REFRESH: Hybrid Mode
9151 00:40:36.134082 TX_TRACKING: ON
9152 00:40:36.144330 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9153 00:40:36.150628 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9154 00:40:36.157403 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9155 00:40:36.160425 [FAST_K] Save calibration result to emmc
9156 00:40:36.163915 sync common calibartion params.
9157 00:40:36.167425 sync cbt_mode0:1, 1:1
9158 00:40:36.167508 dram_init: ddr_geometry: 2
9159 00:40:36.170408 dram_init: ddr_geometry: 2
9160 00:40:36.173948 dram_init: ddr_geometry: 2
9161 00:40:36.177284 0:dram_rank_size:100000000
9162 00:40:36.177369 1:dram_rank_size:100000000
9163 00:40:36.183981 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9164 00:40:36.187154 DFS_SHUFFLE_HW_MODE: ON
9165 00:40:36.190563 dramc_set_vcore_voltage set vcore to 725000
9166 00:40:36.193810 Read voltage for 1600, 0
9167 00:40:36.193893 Vio18 = 0
9168 00:40:36.193959 Vcore = 725000
9169 00:40:36.197164 Vdram = 0
9170 00:40:36.197246 Vddq = 0
9171 00:40:36.197312 Vmddr = 0
9172 00:40:36.200585 switch to 3200 Mbps bootup
9173 00:40:36.200668 [DramcRunTimeConfig]
9174 00:40:36.203819 PHYPLL
9175 00:40:36.203902 DPM_CONTROL_AFTERK: ON
9176 00:40:36.207363 PER_BANK_REFRESH: ON
9177 00:40:36.210545 REFRESH_OVERHEAD_REDUCTION: ON
9178 00:40:36.210628 CMD_PICG_NEW_MODE: OFF
9179 00:40:36.214071 XRTWTW_NEW_MODE: ON
9180 00:40:36.214153 XRTRTR_NEW_MODE: ON
9181 00:40:36.217278 TX_TRACKING: ON
9182 00:40:36.217361 RDSEL_TRACKING: OFF
9183 00:40:36.220438 DQS Precalculation for DVFS: ON
9184 00:40:36.223900 RX_TRACKING: OFF
9185 00:40:36.223982 HW_GATING DBG: ON
9186 00:40:36.227188 ZQCS_ENABLE_LP4: ON
9187 00:40:36.227272 RX_PICG_NEW_MODE: ON
9188 00:40:36.230808 TX_PICG_NEW_MODE: ON
9189 00:40:36.230890 ENABLE_RX_DCM_DPHY: ON
9190 00:40:36.233915 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9191 00:40:36.236965 DUMMY_READ_FOR_TRACKING: OFF
9192 00:40:36.240705 !!! SPM_CONTROL_AFTERK: OFF
9193 00:40:36.243626 !!! SPM could not control APHY
9194 00:40:36.243714 IMPEDANCE_TRACKING: ON
9195 00:40:36.247276 TEMP_SENSOR: ON
9196 00:40:36.247358 HW_SAVE_FOR_SR: OFF
9197 00:40:36.250339 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9198 00:40:36.253903 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9199 00:40:36.256895 Read ODT Tracking: ON
9200 00:40:36.260477 Refresh Rate DeBounce: ON
9201 00:40:36.260581 DFS_NO_QUEUE_FLUSH: ON
9202 00:40:36.263670 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9203 00:40:36.267142 ENABLE_DFS_RUNTIME_MRW: OFF
9204 00:40:36.270467 DDR_RESERVE_NEW_MODE: ON
9205 00:40:36.270550 MR_CBT_SWITCH_FREQ: ON
9206 00:40:36.273485 =========================
9207 00:40:36.292327 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9208 00:40:36.295637 dram_init: ddr_geometry: 2
9209 00:40:36.314239 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9210 00:40:36.317005 dram_init: dram init end (result: 0)
9211 00:40:36.323714 DRAM-K: Full calibration passed in 24490 msecs
9212 00:40:36.327285 MRC: failed to locate region type 0.
9213 00:40:36.327369 DRAM rank0 size:0x100000000,
9214 00:40:36.330189 DRAM rank1 size=0x100000000
9215 00:40:36.340431 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9216 00:40:36.346902 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9217 00:40:36.353896 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9218 00:40:36.360488 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9219 00:40:36.363476 DRAM rank0 size:0x100000000,
9220 00:40:36.366758 DRAM rank1 size=0x100000000
9221 00:40:36.366842 CBMEM:
9222 00:40:36.370195 IMD: root @ 0xfffff000 254 entries.
9223 00:40:36.373363 IMD: root @ 0xffffec00 62 entries.
9224 00:40:36.377025 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9225 00:40:36.380147 WARNING: RO_VPD is uninitialized or empty.
9226 00:40:36.386550 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9227 00:40:36.393857 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9228 00:40:36.406897 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9229 00:40:36.418068 BS: romstage times (exec / console): total (unknown) / 23990 ms
9230 00:40:36.418155
9231 00:40:36.418221
9232 00:40:36.427825 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9233 00:40:36.431430 ARM64: Exception handlers installed.
9234 00:40:36.434616 ARM64: Testing exception
9235 00:40:36.437796 ARM64: Done test exception
9236 00:40:36.437879 Enumerating buses...
9237 00:40:36.441334 Show all devs... Before device enumeration.
9238 00:40:36.444494 Root Device: enabled 1
9239 00:40:36.448188 CPU_CLUSTER: 0: enabled 1
9240 00:40:36.448271 CPU: 00: enabled 1
9241 00:40:36.451146 Compare with tree...
9242 00:40:36.451229 Root Device: enabled 1
9243 00:40:36.454461 CPU_CLUSTER: 0: enabled 1
9244 00:40:36.458142 CPU: 00: enabled 1
9245 00:40:36.458225 Root Device scanning...
9246 00:40:36.461167 scan_static_bus for Root Device
9247 00:40:36.464388 CPU_CLUSTER: 0 enabled
9248 00:40:36.467751 scan_static_bus for Root Device done
9249 00:40:36.471217 scan_bus: bus Root Device finished in 8 msecs
9250 00:40:36.471301 done
9251 00:40:36.477668 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9252 00:40:36.481326 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9253 00:40:36.487652 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9254 00:40:36.490679 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9255 00:40:36.494020 Allocating resources...
9256 00:40:36.497734 Reading resources...
9257 00:40:36.500918 Root Device read_resources bus 0 link: 0
9258 00:40:36.501002 DRAM rank0 size:0x100000000,
9259 00:40:36.504252 DRAM rank1 size=0x100000000
9260 00:40:36.507514 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9261 00:40:36.510681 CPU: 00 missing read_resources
9262 00:40:36.517492 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9263 00:40:36.520569 Root Device read_resources bus 0 link: 0 done
9264 00:40:36.520666 Done reading resources.
9265 00:40:36.527398 Show resources in subtree (Root Device)...After reading.
9266 00:40:36.530524 Root Device child on link 0 CPU_CLUSTER: 0
9267 00:40:36.534025 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 00:40:36.544180 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 00:40:36.544268 CPU: 00
9270 00:40:36.547531 Root Device assign_resources, bus 0 link: 0
9271 00:40:36.551074 CPU_CLUSTER: 0 missing set_resources
9272 00:40:36.557500 Root Device assign_resources, bus 0 link: 0 done
9273 00:40:36.557586 Done setting resources.
9274 00:40:36.564089 Show resources in subtree (Root Device)...After assigning values.
9275 00:40:36.567155 Root Device child on link 0 CPU_CLUSTER: 0
9276 00:40:36.570793 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 00:40:36.580798 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 00:40:36.580886 CPU: 00
9279 00:40:36.583675 Done allocating resources.
9280 00:40:36.586993 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9281 00:40:36.590576 Enabling resources...
9282 00:40:36.590659 done.
9283 00:40:36.597135 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9284 00:40:36.597218 Initializing devices...
9285 00:40:36.600332 Root Device init
9286 00:40:36.600414 init hardware done!
9287 00:40:36.603726 0x00000018: ctrlr->caps
9288 00:40:36.607229 52.000 MHz: ctrlr->f_max
9289 00:40:36.607317 0.400 MHz: ctrlr->f_min
9290 00:40:36.610505 0x40ff8080: ctrlr->voltages
9291 00:40:36.610590 sclk: 390625
9292 00:40:36.613741 Bus Width = 1
9293 00:40:36.613824 sclk: 390625
9294 00:40:36.617279 Bus Width = 1
9295 00:40:36.617362 Early init status = 3
9296 00:40:36.624141 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9297 00:40:36.627016 in-header: 03 fc 00 00 01 00 00 00
9298 00:40:36.630368 in-data: 00
9299 00:40:36.634042 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9300 00:40:36.638550 in-header: 03 fd 00 00 00 00 00 00
9301 00:40:36.642176 in-data:
9302 00:40:36.645248 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9303 00:40:36.649590 in-header: 03 fc 00 00 01 00 00 00
9304 00:40:36.653145 in-data: 00
9305 00:40:36.656203 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9306 00:40:36.661998 in-header: 03 fd 00 00 00 00 00 00
9307 00:40:36.665702 in-data:
9308 00:40:36.668843 [SSUSB] Setting up USB HOST controller...
9309 00:40:36.672144 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9310 00:40:36.675677 [SSUSB] phy power-on done.
9311 00:40:36.678999 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9312 00:40:36.685487 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9313 00:40:36.688793 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9314 00:40:36.695455 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9315 00:40:36.702192 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9316 00:40:36.708867 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9317 00:40:36.715766 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9318 00:40:36.722228 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9319 00:40:36.722313 SPM: binary array size = 0x9dc
9320 00:40:36.728697 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9321 00:40:36.735739 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9322 00:40:36.742214 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9323 00:40:36.745673 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9324 00:40:36.748578 configure_display: Starting display init
9325 00:40:36.785721 anx7625_power_on_init: Init interface.
9326 00:40:36.788914 anx7625_disable_pd_protocol: Disabled PD feature.
9327 00:40:36.792194 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9328 00:40:36.819678 anx7625_start_dp_work: Secure OCM version=00
9329 00:40:36.823113 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9330 00:40:36.837752 sp_tx_get_edid_block: EDID Block = 1
9331 00:40:36.940395 Extracted contents:
9332 00:40:36.943625 header: 00 ff ff ff ff ff ff 00
9333 00:40:36.946877 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9334 00:40:36.950114 version: 01 04
9335 00:40:36.953539 basic params: 95 1f 11 78 0a
9336 00:40:36.956778 chroma info: 76 90 94 55 54 90 27 21 50 54
9337 00:40:36.960185 established: 00 00 00
9338 00:40:36.966813 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9339 00:40:36.970649 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9340 00:40:36.976679 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 00:40:36.983154 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9342 00:40:36.990104 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9343 00:40:36.993584 extensions: 00
9344 00:40:36.993668 checksum: fb
9345 00:40:36.993734
9346 00:40:36.996779 Manufacturer: IVO Model 57d Serial Number 0
9347 00:40:37.000017 Made week 0 of 2020
9348 00:40:37.000125 EDID version: 1.4
9349 00:40:37.003342 Digital display
9350 00:40:37.006622 6 bits per primary color channel
9351 00:40:37.006707 DisplayPort interface
9352 00:40:37.009977 Maximum image size: 31 cm x 17 cm
9353 00:40:37.013253 Gamma: 220%
9354 00:40:37.013337 Check DPMS levels
9355 00:40:37.016776 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9356 00:40:37.023197 First detailed timing is preferred timing
9357 00:40:37.023281 Established timings supported:
9358 00:40:37.026510 Standard timings supported:
9359 00:40:37.029855 Detailed timings
9360 00:40:37.033156 Hex of detail: 383680a07038204018303c0035ae10000019
9361 00:40:37.036584 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9362 00:40:37.042984 0780 0798 07c8 0820 hborder 0
9363 00:40:37.046231 0438 043b 0447 0458 vborder 0
9364 00:40:37.049561 -hsync -vsync
9365 00:40:37.049644 Did detailed timing
9366 00:40:37.056501 Hex of detail: 000000000000000000000000000000000000
9367 00:40:37.059776 Manufacturer-specified data, tag 0
9368 00:40:37.063130 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9369 00:40:37.066108 ASCII string: InfoVision
9370 00:40:37.069649 Hex of detail: 000000fe00523134304e574635205248200a
9371 00:40:37.072975 ASCII string: R140NWF5 RH
9372 00:40:37.073058 Checksum
9373 00:40:37.076502 Checksum: 0xfb (valid)
9374 00:40:37.079768 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9375 00:40:37.082902 DSI data_rate: 832800000 bps
9376 00:40:37.089434 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9377 00:40:37.092868 anx7625_parse_edid: pixelclock(138800).
9378 00:40:37.096130 hactive(1920), hsync(48), hfp(24), hbp(88)
9379 00:40:37.099683 vactive(1080), vsync(12), vfp(3), vbp(17)
9380 00:40:37.102779 anx7625_dsi_config: config dsi.
9381 00:40:37.109434 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9382 00:40:37.122409 anx7625_dsi_config: success to config DSI
9383 00:40:37.125785 anx7625_dp_start: MIPI phy setup OK.
9384 00:40:37.129288 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9385 00:40:37.132321 mtk_ddp_mode_set invalid vrefresh 60
9386 00:40:37.135570 main_disp_path_setup
9387 00:40:37.135653 ovl_layer_smi_id_en
9388 00:40:37.139091 ovl_layer_smi_id_en
9389 00:40:37.139180 ccorr_config
9390 00:40:37.139246 aal_config
9391 00:40:37.142210 gamma_config
9392 00:40:37.142292 postmask_config
9393 00:40:37.145663 dither_config
9394 00:40:37.148952 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9395 00:40:37.155479 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9396 00:40:37.158775 Root Device init finished in 555 msecs
9397 00:40:37.162405 CPU_CLUSTER: 0 init
9398 00:40:37.168974 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9399 00:40:37.172086 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9400 00:40:37.175698 APU_MBOX 0x190000b0 = 0x10001
9401 00:40:37.178758 APU_MBOX 0x190001b0 = 0x10001
9402 00:40:37.182311 APU_MBOX 0x190005b0 = 0x10001
9403 00:40:37.185426 APU_MBOX 0x190006b0 = 0x10001
9404 00:40:37.188707 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9405 00:40:37.201682 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9406 00:40:37.214102 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9407 00:40:37.220529 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9408 00:40:37.232175 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9409 00:40:37.241106 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9410 00:40:37.244688 CPU_CLUSTER: 0 init finished in 81 msecs
9411 00:40:37.247589 Devices initialized
9412 00:40:37.250928 Show all devs... After init.
9413 00:40:37.251014 Root Device: enabled 1
9414 00:40:37.254363 CPU_CLUSTER: 0: enabled 1
9415 00:40:37.257806 CPU: 00: enabled 1
9416 00:40:37.261436 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9417 00:40:37.264390 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9418 00:40:37.267738 ELOG: NV offset 0x57f000 size 0x1000
9419 00:40:37.274100 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9420 00:40:37.280756 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9421 00:40:37.284176 ELOG: Event(17) added with size 13 at 2024-06-05 00:39:10 UTC
9422 00:40:37.290699 out: cmd=0x121: 03 db 21 01 00 00 00 00
9423 00:40:37.294320 in-header: 03 76 00 00 2c 00 00 00
9424 00:40:37.303964 in-data: c9 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9425 00:40:37.310724 ELOG: Event(A1) added with size 10 at 2024-06-05 00:39:10 UTC
9426 00:40:37.317105 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9427 00:40:37.323647 ELOG: Event(A0) added with size 9 at 2024-06-05 00:39:10 UTC
9428 00:40:37.327198 elog_add_boot_reason: Logged dev mode boot
9429 00:40:37.333934 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9430 00:40:37.334021 Finalize devices...
9431 00:40:37.336974 Devices finalized
9432 00:40:37.340653 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9433 00:40:37.343704 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9434 00:40:37.347149 in-header: 03 07 00 00 08 00 00 00
9435 00:40:37.350210 in-data: aa e4 47 04 13 02 00 00
9436 00:40:37.353554 Chrome EC: UHEPI supported
9437 00:40:37.359973 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9438 00:40:37.363700 in-header: 03 a9 00 00 08 00 00 00
9439 00:40:37.366912 in-data: 84 60 60 08 00 00 00 00
9440 00:40:37.373299 ELOG: Event(91) added with size 10 at 2024-06-05 00:39:10 UTC
9441 00:40:37.376589 Chrome EC: clear events_b mask to 0x0000000020004000
9442 00:40:37.383141 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9443 00:40:37.386990 in-header: 03 fd 00 00 00 00 00 00
9444 00:40:37.387080 in-data:
9445 00:40:37.393453 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9446 00:40:37.397229 Writing coreboot table at 0xffe64000
9447 00:40:37.400188 0. 000000000010a000-0000000000113fff: RAMSTAGE
9448 00:40:37.403842 1. 0000000040000000-00000000400fffff: RAM
9449 00:40:37.410385 2. 0000000040100000-000000004032afff: RAMSTAGE
9450 00:40:37.413634 3. 000000004032b000-00000000545fffff: RAM
9451 00:40:37.417206 4. 0000000054600000-000000005465ffff: BL31
9452 00:40:37.420314 5. 0000000054660000-00000000ffe63fff: RAM
9453 00:40:37.427021 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9454 00:40:37.430189 7. 0000000100000000-000000023fffffff: RAM
9455 00:40:37.433865 Passing 5 GPIOs to payload:
9456 00:40:37.436980 NAME | PORT | POLARITY | VALUE
9457 00:40:37.440172 EC in RW | 0x000000aa | low | undefined
9458 00:40:37.446816 EC interrupt | 0x00000005 | low | undefined
9459 00:40:37.450129 TPM interrupt | 0x000000ab | high | undefined
9460 00:40:37.456682 SD card detect | 0x00000011 | high | undefined
9461 00:40:37.460217 speaker enable | 0x00000093 | high | undefined
9462 00:40:37.463606 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9463 00:40:37.467045 in-header: 03 f9 00 00 02 00 00 00
9464 00:40:37.470015 in-data: 02 00
9465 00:40:37.470100 ADC[4]: Raw value=901401 ID=7
9466 00:40:37.473524 ADC[3]: Raw value=212810 ID=1
9467 00:40:37.476606 RAM Code: 0x71
9468 00:40:37.476726 ADC[6]: Raw value=74502 ID=0
9469 00:40:37.480271 ADC[5]: Raw value=212072 ID=1
9470 00:40:37.483766 SKU Code: 0x1
9471 00:40:37.487024 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 23f
9472 00:40:37.490379 coreboot table: 964 bytes.
9473 00:40:37.493473 IMD ROOT 0. 0xfffff000 0x00001000
9474 00:40:37.496727 IMD SMALL 1. 0xffffe000 0x00001000
9475 00:40:37.500245 RO MCACHE 2. 0xffffc000 0x00001104
9476 00:40:37.503444 CONSOLE 3. 0xfff7c000 0x00080000
9477 00:40:37.506703 FMAP 4. 0xfff7b000 0x00000452
9478 00:40:37.510278 TIME STAMP 5. 0xfff7a000 0x00000910
9479 00:40:37.513401 VBOOT WORK 6. 0xfff66000 0x00014000
9480 00:40:37.516658 RAMOOPS 7. 0xffe66000 0x00100000
9481 00:40:37.520179 COREBOOT 8. 0xffe64000 0x00002000
9482 00:40:37.520266 IMD small region:
9483 00:40:37.523610 IMD ROOT 0. 0xffffec00 0x00000400
9484 00:40:37.526902 VPD 1. 0xffffeb80 0x0000006c
9485 00:40:37.529991 MMC STATUS 2. 0xffffeb60 0x00000004
9486 00:40:37.536722 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9487 00:40:37.543106 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9488 00:40:37.583114 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9489 00:40:37.586406 Checking segment from ROM address 0x40100000
9490 00:40:37.589748 Checking segment from ROM address 0x4010001c
9491 00:40:37.596447 Loading segment from ROM address 0x40100000
9492 00:40:37.596570 code (compression=0)
9493 00:40:37.606431 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9494 00:40:37.613088 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9495 00:40:37.613205 it's not compressed!
9496 00:40:37.619824 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9497 00:40:37.623034 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9498 00:40:37.643604 Loading segment from ROM address 0x4010001c
9499 00:40:37.643725 Entry Point 0x80000000
9500 00:40:37.647216 Loaded segments
9501 00:40:37.650144 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9502 00:40:37.656738 Jumping to boot code at 0x80000000(0xffe64000)
9503 00:40:37.663689 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9504 00:40:37.670188 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9505 00:40:37.678277 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9506 00:40:37.681365 Checking segment from ROM address 0x40100000
9507 00:40:37.684718 Checking segment from ROM address 0x4010001c
9508 00:40:37.691536 Loading segment from ROM address 0x40100000
9509 00:40:37.691622 code (compression=1)
9510 00:40:37.697882 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9511 00:40:37.707966 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9512 00:40:37.708051 using LZMA
9513 00:40:37.716670 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9514 00:40:37.723015 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9515 00:40:37.726170 Loading segment from ROM address 0x4010001c
9516 00:40:37.726254 Entry Point 0x54601000
9517 00:40:37.729624 Loaded segments
9518 00:40:37.733012 NOTICE: MT8192 bl31_setup
9519 00:40:37.740251 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9520 00:40:37.743367 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9521 00:40:37.746659 WARNING: region 0:
9522 00:40:37.750149 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 00:40:37.750234 WARNING: region 1:
9524 00:40:37.756472 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9525 00:40:37.760216 WARNING: region 2:
9526 00:40:37.763463 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9527 00:40:37.766580 WARNING: region 3:
9528 00:40:37.769909 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 00:40:37.773203 WARNING: region 4:
9530 00:40:37.779908 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9531 00:40:37.779993 WARNING: region 5:
9532 00:40:37.783140 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 00:40:37.786577 WARNING: region 6:
9534 00:40:37.789729 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 00:40:37.793145 WARNING: region 7:
9536 00:40:37.796448 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 00:40:37.802992 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9538 00:40:37.806609 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9539 00:40:37.810166 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9540 00:40:37.816458 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9541 00:40:37.820007 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9542 00:40:37.823238 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9543 00:40:37.829695 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9544 00:40:37.833272 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9545 00:40:37.839945 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9546 00:40:37.842981 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9547 00:40:37.846624 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9548 00:40:37.853206 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9549 00:40:37.856530 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9550 00:40:37.859946 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9551 00:40:37.866595 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9552 00:40:37.869694 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9553 00:40:37.876499 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9554 00:40:37.879836 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9555 00:40:37.882817 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9556 00:40:37.889567 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9557 00:40:37.892930 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9558 00:40:37.896337 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9559 00:40:37.902886 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9560 00:40:37.906467 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9561 00:40:37.913123 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9562 00:40:37.916325 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9563 00:40:37.919596 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9564 00:40:37.926228 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9565 00:40:37.929956 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9566 00:40:37.936592 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9567 00:40:37.939962 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9568 00:40:37.942936 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9569 00:40:37.949835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9570 00:40:37.953221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9571 00:40:37.956074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9572 00:40:37.959485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9573 00:40:37.966287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9574 00:40:37.969674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9575 00:40:37.972564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9576 00:40:37.976305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9577 00:40:37.982848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9578 00:40:37.986031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9579 00:40:37.989496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9580 00:40:37.992782 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9581 00:40:37.999382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9582 00:40:38.003532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9583 00:40:38.006611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9584 00:40:38.009800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9585 00:40:38.016013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9586 00:40:38.019493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9587 00:40:38.026000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9588 00:40:38.029419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9589 00:40:38.035955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9590 00:40:38.039636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9591 00:40:38.042838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9592 00:40:38.049687 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9593 00:40:38.052762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9594 00:40:38.059269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9595 00:40:38.062662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9596 00:40:38.069430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9597 00:40:38.072685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9598 00:40:38.075854 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9599 00:40:38.082558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9600 00:40:38.086133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9601 00:40:38.092521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9602 00:40:38.095731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9603 00:40:38.102468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9604 00:40:38.106232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9605 00:40:38.112418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9606 00:40:38.116153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9607 00:40:38.119205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9608 00:40:38.125724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9609 00:40:38.129406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9610 00:40:38.135783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9611 00:40:38.139085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9612 00:40:38.146197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9613 00:40:38.149405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9614 00:40:38.152611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9615 00:40:38.159282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9616 00:40:38.162434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9617 00:40:38.169111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9618 00:40:38.172434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9619 00:40:38.179104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9620 00:40:38.182310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9621 00:40:38.185917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9622 00:40:38.192367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9623 00:40:38.195908 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9624 00:40:38.202264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9625 00:40:38.205533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9626 00:40:38.212307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9627 00:40:38.215844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9628 00:40:38.222275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9629 00:40:38.225614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9630 00:40:38.228973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9631 00:40:38.235742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9632 00:40:38.238901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9633 00:40:38.245779 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9634 00:40:38.249155 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9635 00:40:38.252144 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9636 00:40:38.255480 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9637 00:40:38.262326 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9638 00:40:38.265967 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9639 00:40:38.269228 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9640 00:40:38.275569 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9641 00:40:38.279104 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9642 00:40:38.282508 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9643 00:40:38.288785 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9644 00:40:38.292387 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9645 00:40:38.299572 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9646 00:40:38.302359 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9647 00:40:38.305602 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9648 00:40:38.312277 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9649 00:40:38.315817 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9650 00:40:38.322033 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9651 00:40:38.325715 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9652 00:40:38.328778 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9653 00:40:38.335245 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9654 00:40:38.338493 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9655 00:40:38.342049 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9656 00:40:38.348974 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9657 00:40:38.352311 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9658 00:40:38.355436 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9659 00:40:38.358773 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9660 00:40:38.365583 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9661 00:40:38.368966 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9662 00:40:38.372060 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9663 00:40:38.378866 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9664 00:40:38.382154 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9665 00:40:38.389123 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9666 00:40:38.392147 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9667 00:40:38.395205 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9668 00:40:38.402177 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9669 00:40:38.405523 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9670 00:40:38.411912 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9671 00:40:38.415274 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9672 00:40:38.418843 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9673 00:40:38.425608 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9674 00:40:38.428834 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9675 00:40:38.432285 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9676 00:40:38.438697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9677 00:40:38.441873 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9678 00:40:38.448524 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9679 00:40:38.451881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9680 00:40:38.455559 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9681 00:40:38.462392 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9682 00:40:38.465368 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9683 00:40:38.469008 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9684 00:40:38.475602 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9685 00:40:38.478956 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9686 00:40:38.485335 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9687 00:40:38.488533 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9688 00:40:38.492041 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9689 00:40:38.498962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9690 00:40:38.502039 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9691 00:40:38.508509 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9692 00:40:38.511860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9693 00:40:38.515206 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9694 00:40:38.522069 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9695 00:40:38.525323 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9696 00:40:38.528821 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9697 00:40:38.535500 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9698 00:40:38.538707 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9699 00:40:38.545302 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9700 00:40:38.548739 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9701 00:40:38.551988 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9702 00:40:38.558699 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9703 00:40:38.561796 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9704 00:40:38.568538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9705 00:40:38.571982 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9706 00:40:38.575136 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9707 00:40:38.582087 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9708 00:40:38.585482 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9709 00:40:38.592197 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9710 00:40:38.595185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9711 00:40:38.598732 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9712 00:40:38.605067 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9713 00:40:38.608329 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9714 00:40:38.615338 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9715 00:40:38.618806 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9716 00:40:38.621852 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9717 00:40:38.628599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9718 00:40:38.631766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9719 00:40:38.635588 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9720 00:40:38.641724 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9721 00:40:38.645124 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9722 00:40:38.651810 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9723 00:40:38.655146 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9724 00:40:38.658485 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9725 00:40:38.665127 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9726 00:40:38.668503 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9727 00:40:38.675156 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9728 00:40:38.678383 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9729 00:40:38.681576 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9730 00:40:38.688329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9731 00:40:38.691788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9732 00:40:38.698261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9733 00:40:38.701673 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9734 00:40:38.708166 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9735 00:40:38.711662 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9736 00:40:38.714948 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9737 00:40:38.721582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9738 00:40:38.725006 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9739 00:40:38.731653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9740 00:40:38.734821 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9741 00:40:38.737955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9742 00:40:38.744856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9743 00:40:38.748210 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9744 00:40:38.754926 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9745 00:40:38.758066 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9746 00:40:38.764759 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9747 00:40:38.768298 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9748 00:40:38.771365 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9749 00:40:38.778511 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9750 00:40:38.781535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9751 00:40:38.788408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9752 00:40:38.791540 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9753 00:40:38.794736 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9754 00:40:38.801301 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9755 00:40:38.804594 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9756 00:40:38.811434 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9757 00:40:38.814443 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9758 00:40:38.817866 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9759 00:40:38.824764 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9760 00:40:38.827933 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9761 00:40:38.834687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9762 00:40:38.838122 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9763 00:40:38.844410 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9764 00:40:38.847854 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9765 00:40:38.851415 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9766 00:40:38.858006 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9767 00:40:38.861181 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9768 00:40:38.864661 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9769 00:40:38.867986 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9770 00:40:38.871106 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9771 00:40:38.877855 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9772 00:40:38.881212 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9773 00:40:38.887997 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9774 00:40:38.891230 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9775 00:40:38.894520 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9776 00:40:38.901188 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9777 00:40:38.904509 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9778 00:40:38.908146 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9779 00:40:38.914422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9780 00:40:38.917997 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9781 00:40:38.921340 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9782 00:40:38.927824 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9783 00:40:38.931362 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9784 00:40:38.937907 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9785 00:40:38.941300 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9786 00:40:38.944476 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9787 00:40:38.951170 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9788 00:40:38.954348 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9789 00:40:38.958016 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9790 00:40:38.964519 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9791 00:40:38.967860 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9792 00:40:38.971202 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9793 00:40:38.977873 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9794 00:40:38.981220 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9795 00:40:38.984573 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9796 00:40:38.991187 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9797 00:40:38.994556 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9798 00:40:39.001078 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9799 00:40:39.004509 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9800 00:40:39.007673 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9801 00:40:39.014340 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9802 00:40:39.017566 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9803 00:40:39.021058 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9804 00:40:39.028042 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9805 00:40:39.031129 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9806 00:40:39.034648 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9807 00:40:39.037577 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9808 00:40:39.044459 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9809 00:40:39.047711 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9810 00:40:39.051288 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9811 00:40:39.054463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9812 00:40:39.061005 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9813 00:40:39.064168 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9814 00:40:39.067567 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9815 00:40:39.071161 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9816 00:40:39.077708 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9817 00:40:39.081299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9818 00:40:39.084335 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9819 00:40:39.091055 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9820 00:40:39.094656 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9821 00:40:39.097925 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9822 00:40:39.104575 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9823 00:40:39.107703 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9824 00:40:39.114736 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9825 00:40:39.118012 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9826 00:40:39.121135 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9827 00:40:39.128382 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9828 00:40:39.131537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9829 00:40:39.137875 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9830 00:40:39.141271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9831 00:40:39.147952 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9832 00:40:39.151156 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9833 00:40:39.154703 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9834 00:40:39.161388 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9835 00:40:39.164586 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9836 00:40:39.168078 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9837 00:40:39.174668 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9838 00:40:39.178261 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9839 00:40:39.184568 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9840 00:40:39.187975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9841 00:40:39.194338 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9842 00:40:39.198226 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9843 00:40:39.201159 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9844 00:40:39.207825 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9845 00:40:39.211123 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9846 00:40:39.214505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9847 00:40:39.221222 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9848 00:40:39.224835 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9849 00:40:39.231383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9850 00:40:39.234807 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9851 00:40:39.238062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9852 00:40:39.244533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9853 00:40:39.248034 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9854 00:40:39.254722 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9855 00:40:39.258319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9856 00:40:39.264960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9857 00:40:39.268474 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9858 00:40:39.271423 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9859 00:40:39.277881 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9860 00:40:39.281534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9861 00:40:39.284532 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9862 00:40:39.291382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9863 00:40:39.294784 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9864 00:40:39.301093 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9865 00:40:39.304553 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9866 00:40:39.308191 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9867 00:40:39.314583 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9868 00:40:39.317710 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9869 00:40:39.324485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9870 00:40:39.327896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9871 00:40:39.334551 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9872 00:40:39.337838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9873 00:40:39.341187 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9874 00:40:39.348001 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9875 00:40:39.351293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9876 00:40:39.357994 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9877 00:40:39.361579 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9878 00:40:39.364713 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9879 00:40:39.371666 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9880 00:40:39.374645 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9881 00:40:39.381108 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9882 00:40:39.384591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9883 00:40:39.387879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9884 00:40:39.394415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9885 00:40:39.397719 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9886 00:40:39.404541 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9887 00:40:39.407997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9888 00:40:39.411249 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9889 00:40:39.417927 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9890 00:40:39.421417 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9891 00:40:39.428127 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9892 00:40:39.431372 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9893 00:40:39.434651 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9894 00:40:39.441366 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9895 00:40:39.444517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9896 00:40:39.451152 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9897 00:40:39.454715 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9898 00:40:39.458252 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9899 00:40:39.464558 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9900 00:40:39.468303 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9901 00:40:39.474663 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9902 00:40:39.478156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9903 00:40:39.484746 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9904 00:40:39.487948 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9905 00:40:39.494742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9906 00:40:39.497879 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9907 00:40:39.501401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9908 00:40:39.508326 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9909 00:40:39.511458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9910 00:40:39.518186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9911 00:40:39.521537 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9912 00:40:39.527697 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9913 00:40:39.531665 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9914 00:40:39.534471 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9915 00:40:39.541219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9916 00:40:39.544480 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9917 00:40:39.551152 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9918 00:40:39.554228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9919 00:40:39.561190 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9920 00:40:39.564804 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9921 00:40:39.571135 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9922 00:40:39.574337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9923 00:40:39.577875 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9924 00:40:39.584213 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9925 00:40:39.588154 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9926 00:40:39.594328 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9927 00:40:39.597542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9928 00:40:39.604435 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9929 00:40:39.607494 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9930 00:40:39.610956 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9931 00:40:39.617429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9932 00:40:39.621002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9933 00:40:39.627622 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9934 00:40:39.630720 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9935 00:40:39.637498 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9936 00:40:39.640834 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9937 00:40:39.644321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9938 00:40:39.650788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9939 00:40:39.654343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9940 00:40:39.661079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9941 00:40:39.664201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9942 00:40:39.667713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9943 00:40:39.674345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9944 00:40:39.677403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9945 00:40:39.684237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9946 00:40:39.687738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9947 00:40:39.694022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9948 00:40:39.697447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9949 00:40:39.704327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9950 00:40:39.707501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9951 00:40:39.714085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9952 00:40:39.717551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9953 00:40:39.723992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9954 00:40:39.727361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9955 00:40:39.733853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9956 00:40:39.737219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9957 00:40:39.743912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9958 00:40:39.747011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9959 00:40:39.753560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9960 00:40:39.757080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9961 00:40:39.763569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9962 00:40:39.766889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9963 00:40:39.773454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9964 00:40:39.776830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9965 00:40:39.783321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9966 00:40:39.786732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9967 00:40:39.793504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9968 00:40:39.796827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9969 00:40:39.803393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9970 00:40:39.806614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9971 00:40:39.809861 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9972 00:40:39.813124 INFO: [APUAPC] vio 0
9973 00:40:39.819908 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9974 00:40:39.823326 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9975 00:40:39.826658 INFO: [APUAPC] D0_APC_0: 0x400510
9976 00:40:39.830010 INFO: [APUAPC] D0_APC_1: 0x0
9977 00:40:39.833193 INFO: [APUAPC] D0_APC_2: 0x1540
9978 00:40:39.836393 INFO: [APUAPC] D0_APC_3: 0x0
9979 00:40:39.839896 INFO: [APUAPC] D1_APC_0: 0xffffffff
9980 00:40:39.843428 INFO: [APUAPC] D1_APC_1: 0xffffffff
9981 00:40:39.846491 INFO: [APUAPC] D1_APC_2: 0x3fffff
9982 00:40:39.849950 INFO: [APUAPC] D1_APC_3: 0x0
9983 00:40:39.853206 INFO: [APUAPC] D2_APC_0: 0xffffffff
9984 00:40:39.856574 INFO: [APUAPC] D2_APC_1: 0xffffffff
9985 00:40:39.859934 INFO: [APUAPC] D2_APC_2: 0x3fffff
9986 00:40:39.863209 INFO: [APUAPC] D2_APC_3: 0x0
9987 00:40:39.866581 INFO: [APUAPC] D3_APC_0: 0xffffffff
9988 00:40:39.869944 INFO: [APUAPC] D3_APC_1: 0xffffffff
9989 00:40:39.873360 INFO: [APUAPC] D3_APC_2: 0x3fffff
9990 00:40:39.873468 INFO: [APUAPC] D3_APC_3: 0x0
9991 00:40:39.876454 INFO: [APUAPC] D4_APC_0: 0xffffffff
9992 00:40:39.883317 INFO: [APUAPC] D4_APC_1: 0xffffffff
9993 00:40:39.883410 INFO: [APUAPC] D4_APC_2: 0x3fffff
9994 00:40:39.886790 INFO: [APUAPC] D4_APC_3: 0x0
9995 00:40:39.889720 INFO: [APUAPC] D5_APC_0: 0xffffffff
9996 00:40:39.893647 INFO: [APUAPC] D5_APC_1: 0xffffffff
9997 00:40:39.896647 INFO: [APUAPC] D5_APC_2: 0x3fffff
9998 00:40:39.899856 INFO: [APUAPC] D5_APC_3: 0x0
9999 00:40:39.903135 INFO: [APUAPC] D6_APC_0: 0xffffffff
10000 00:40:39.906764 INFO: [APUAPC] D6_APC_1: 0xffffffff
10001 00:40:39.909814 INFO: [APUAPC] D6_APC_2: 0x3fffff
10002 00:40:39.913166 INFO: [APUAPC] D6_APC_3: 0x0
10003 00:40:39.916349 INFO: [APUAPC] D7_APC_0: 0xffffffff
10004 00:40:39.919514 INFO: [APUAPC] D7_APC_1: 0xffffffff
10005 00:40:39.923256 INFO: [APUAPC] D7_APC_2: 0x3fffff
10006 00:40:39.926293 INFO: [APUAPC] D7_APC_3: 0x0
10007 00:40:39.929695 INFO: [APUAPC] D8_APC_0: 0xffffffff
10008 00:40:39.933328 INFO: [APUAPC] D8_APC_1: 0xffffffff
10009 00:40:39.936631 INFO: [APUAPC] D8_APC_2: 0x3fffff
10010 00:40:39.940015 INFO: [APUAPC] D8_APC_3: 0x0
10011 00:40:39.943082 INFO: [APUAPC] D9_APC_0: 0xffffffff
10012 00:40:39.946464 INFO: [APUAPC] D9_APC_1: 0xffffffff
10013 00:40:39.949494 INFO: [APUAPC] D9_APC_2: 0x3fffff
10014 00:40:39.953111 INFO: [APUAPC] D9_APC_3: 0x0
10015 00:40:39.956264 INFO: [APUAPC] D10_APC_0: 0xffffffff
10016 00:40:39.959559 INFO: [APUAPC] D10_APC_1: 0xffffffff
10017 00:40:39.963163 INFO: [APUAPC] D10_APC_2: 0x3fffff
10018 00:40:39.966290 INFO: [APUAPC] D10_APC_3: 0x0
10019 00:40:39.969288 INFO: [APUAPC] D11_APC_0: 0xffffffff
10020 00:40:39.972974 INFO: [APUAPC] D11_APC_1: 0xffffffff
10021 00:40:39.976263 INFO: [APUAPC] D11_APC_2: 0x3fffff
10022 00:40:39.979396 INFO: [APUAPC] D11_APC_3: 0x0
10023 00:40:39.982960 INFO: [APUAPC] D12_APC_0: 0xffffffff
10024 00:40:39.985931 INFO: [APUAPC] D12_APC_1: 0xffffffff
10025 00:40:39.989292 INFO: [APUAPC] D12_APC_2: 0x3fffff
10026 00:40:39.992898 INFO: [APUAPC] D12_APC_3: 0x0
10027 00:40:39.996065 INFO: [APUAPC] D13_APC_0: 0xffffffff
10028 00:40:39.999479 INFO: [APUAPC] D13_APC_1: 0xffffffff
10029 00:40:40.002633 INFO: [APUAPC] D13_APC_2: 0x3fffff
10030 00:40:40.005863 INFO: [APUAPC] D13_APC_3: 0x0
10031 00:40:40.009176 INFO: [APUAPC] D14_APC_0: 0xffffffff
10032 00:40:40.012436 INFO: [APUAPC] D14_APC_1: 0xffffffff
10033 00:40:40.015896 INFO: [APUAPC] D14_APC_2: 0x3fffff
10034 00:40:40.019383 INFO: [APUAPC] D14_APC_3: 0x0
10035 00:40:40.022806 INFO: [APUAPC] D15_APC_0: 0xffffffff
10036 00:40:40.025827 INFO: [APUAPC] D15_APC_1: 0xffffffff
10037 00:40:40.029477 INFO: [APUAPC] D15_APC_2: 0x3fffff
10038 00:40:40.032440 INFO: [APUAPC] D15_APC_3: 0x0
10039 00:40:40.035731 INFO: [APUAPC] APC_CON: 0x4
10040 00:40:40.039273 INFO: [NOCDAPC] D0_APC_0: 0x0
10041 00:40:40.042823 INFO: [NOCDAPC] D0_APC_1: 0x0
10042 00:40:40.045745 INFO: [NOCDAPC] D1_APC_0: 0x0
10043 00:40:40.045832 INFO: [NOCDAPC] D1_APC_1: 0xfff
10044 00:40:40.049291 INFO: [NOCDAPC] D2_APC_0: 0x0
10045 00:40:40.052321 INFO: [NOCDAPC] D2_APC_1: 0xfff
10046 00:40:40.055802 INFO: [NOCDAPC] D3_APC_0: 0x0
10047 00:40:40.058944 INFO: [NOCDAPC] D3_APC_1: 0xfff
10048 00:40:40.062576 INFO: [NOCDAPC] D4_APC_0: 0x0
10049 00:40:40.065961 INFO: [NOCDAPC] D4_APC_1: 0xfff
10050 00:40:40.069028 INFO: [NOCDAPC] D5_APC_0: 0x0
10051 00:40:40.072555 INFO: [NOCDAPC] D5_APC_1: 0xfff
10052 00:40:40.076194 INFO: [NOCDAPC] D6_APC_0: 0x0
10053 00:40:40.078985 INFO: [NOCDAPC] D6_APC_1: 0xfff
10054 00:40:40.079126 INFO: [NOCDAPC] D7_APC_0: 0x0
10055 00:40:40.082400 INFO: [NOCDAPC] D7_APC_1: 0xfff
10056 00:40:40.085933 INFO: [NOCDAPC] D8_APC_0: 0x0
10057 00:40:40.089117 INFO: [NOCDAPC] D8_APC_1: 0xfff
10058 00:40:40.092711 INFO: [NOCDAPC] D9_APC_0: 0x0
10059 00:40:40.095566 INFO: [NOCDAPC] D9_APC_1: 0xfff
10060 00:40:40.098749 INFO: [NOCDAPC] D10_APC_0: 0x0
10061 00:40:40.102097 INFO: [NOCDAPC] D10_APC_1: 0xfff
10062 00:40:40.105699 INFO: [NOCDAPC] D11_APC_0: 0x0
10063 00:40:40.108899 INFO: [NOCDAPC] D11_APC_1: 0xfff
10064 00:40:40.112440 INFO: [NOCDAPC] D12_APC_0: 0x0
10065 00:40:40.115307 INFO: [NOCDAPC] D12_APC_1: 0xfff
10066 00:40:40.118903 INFO: [NOCDAPC] D13_APC_0: 0x0
10067 00:40:40.122062 INFO: [NOCDAPC] D13_APC_1: 0xfff
10068 00:40:40.122145 INFO: [NOCDAPC] D14_APC_0: 0x0
10069 00:40:40.125320 INFO: [NOCDAPC] D14_APC_1: 0xfff
10070 00:40:40.128814 INFO: [NOCDAPC] D15_APC_0: 0x0
10071 00:40:40.132142 INFO: [NOCDAPC] D15_APC_1: 0xfff
10072 00:40:40.135451 INFO: [NOCDAPC] APC_CON: 0x4
10073 00:40:40.138554 INFO: [APUAPC] set_apusys_apc done
10074 00:40:40.141987 INFO: [DEVAPC] devapc_init done
10075 00:40:40.145745 INFO: GICv3 without legacy support detected.
10076 00:40:40.151915 INFO: ARM GICv3 driver initialized in EL3
10077 00:40:40.155321 INFO: Maximum SPI INTID supported: 639
10078 00:40:40.158858 INFO: BL31: Initializing runtime services
10079 00:40:40.165211 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10080 00:40:40.165298 INFO: SPM: enable CPC mode
10081 00:40:40.171883 INFO: mcdi ready for mcusys-off-idle and system suspend
10082 00:40:40.175576 INFO: BL31: Preparing for EL3 exit to normal world
10083 00:40:40.178712 INFO: Entry point address = 0x80000000
10084 00:40:40.181937 INFO: SPSR = 0x8
10085 00:40:40.187959
10086 00:40:40.188062
10087 00:40:40.188134
10088 00:40:40.190970 Starting depthcharge on Spherion...
10089 00:40:40.191057
10090 00:40:40.191124 Wipe memory regions:
10091 00:40:40.191186
10092 00:40:40.191775 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10093 00:40:40.191881 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10094 00:40:40.191968 Setting prompt string to ['asurada:']
10095 00:40:40.192050 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10096 00:40:40.194654 [0x00000040000000, 0x00000054600000)
10097 00:40:40.316919
10098 00:40:40.317317 [0x00000054660000, 0x00000080000000)
10099 00:40:40.577743
10100 00:40:40.578268 [0x000000821a7280, 0x000000ffe64000)
10101 00:40:41.321975
10102 00:40:41.322137 [0x00000100000000, 0x00000240000000)
10103 00:40:43.212182
10104 00:40:43.215623 Initializing XHCI USB controller at 0x11200000.
10105 00:40:44.253538
10106 00:40:44.256689 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10107 00:40:44.256782
10108 00:40:44.256850
10109 00:40:44.257140 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10111 00:40:44.357497 asurada: tftpboot 192.168.201.1 14173470/tftp-deploy-mz3f2d94/kernel/image.itb 14173470/tftp-deploy-mz3f2d94/kernel/cmdline
10112 00:40:44.357669 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 00:40:44.357816 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10114 00:40:44.361694 tftpboot 192.168.201.1 14173470/tftp-deploy-mz3f2d94/kernel/image.ittp-deploy-mz3f2d94/kernel/cmdline
10115 00:40:44.361797
10116 00:40:44.361879 Waiting for link
10117 00:40:44.520044
10118 00:40:44.520238 R8152: Initializing
10119 00:40:44.520351
10120 00:40:44.523247 Version 9 (ocp_data = 6010)
10121 00:40:44.523360
10122 00:40:44.526710 R8152: Done initializing
10123 00:40:44.526835
10124 00:40:44.526930 Adding net device
10125 00:40:46.401428
10126 00:40:46.401598 done.
10127 00:40:46.401670
10128 00:40:46.401761 MAC: 00:e0:4c:72:2d:d6
10129 00:40:46.401850
10130 00:40:46.404762 Sending DHCP discover... done.
10131 00:40:46.404861
10132 00:40:46.407758 Waiting for reply... done.
10133 00:40:46.407892
10134 00:40:46.411215 Sending DHCP request... done.
10135 00:40:46.411348
10136 00:40:46.418469 Waiting for reply... done.
10137 00:40:46.418581
10138 00:40:46.418647 My ip is 192.168.201.21
10139 00:40:46.418708
10140 00:40:46.421510 The DHCP server ip is 192.168.201.1
10141 00:40:46.421593
10142 00:40:46.428351 TFTP server IP predefined by user: 192.168.201.1
10143 00:40:46.428434
10144 00:40:46.434836 Bootfile predefined by user: 14173470/tftp-deploy-mz3f2d94/kernel/image.itb
10145 00:40:46.434919
10146 00:40:46.438403 Sending tftp read request... done.
10147 00:40:46.438485
10148 00:40:46.438582 Waiting for the transfer...
10149 00:40:46.441306
10150 00:40:46.729296 00000000 ################################################################
10151 00:40:46.729442
10152 00:40:47.026624 00080000 ################################################################
10153 00:40:47.026772
10154 00:40:47.315596 00100000 ################################################################
10155 00:40:47.315744
10156 00:40:47.578827 00180000 ################################################################
10157 00:40:47.578974
10158 00:40:47.865480 00200000 ################################################################
10159 00:40:47.865621
10160 00:40:48.155255 00280000 ################################################################
10161 00:40:48.155397
10162 00:40:48.430062 00300000 ################################################################
10163 00:40:48.430210
10164 00:40:48.682920 00380000 ################################################################
10165 00:40:48.683065
10166 00:40:48.935953 00400000 ################################################################
10167 00:40:48.936088
10168 00:40:49.189058 00480000 ################################################################
10169 00:40:49.189199
10170 00:40:49.443108 00500000 ################################################################
10171 00:40:49.443252
10172 00:40:49.696095 00580000 ################################################################
10173 00:40:49.696245
10174 00:40:49.953396 00600000 ################################################################
10175 00:40:49.953536
10176 00:40:50.221947 00680000 ################################################################
10177 00:40:50.222091
10178 00:40:50.471251 00700000 ################################################################
10179 00:40:50.471387
10180 00:40:50.719123 00780000 ################################################################
10181 00:40:50.719281
10182 00:40:50.964094 00800000 ################################################################
10183 00:40:50.964237
10184 00:40:51.205588 00880000 ################################################################
10185 00:40:51.205741
10186 00:40:51.450348 00900000 ################################################################
10187 00:40:51.450539
10188 00:40:51.692058 00980000 ################################################################
10189 00:40:51.692249
10190 00:40:51.933942 00a00000 ################################################################
10191 00:40:51.934101
10192 00:40:52.175683 00a80000 ################################################################
10193 00:40:52.175862
10194 00:40:52.416937 00b00000 ################################################################
10195 00:40:52.417101
10196 00:40:52.658931 00b80000 ################################################################
10197 00:40:52.659084
10198 00:40:52.904674 00c00000 ################################################################
10199 00:40:52.904871
10200 00:40:53.150236 00c80000 ################################################################
10201 00:40:53.150371
10202 00:40:53.400944 00d00000 ################################################################
10203 00:40:53.401085
10204 00:40:53.647917 00d80000 ################################################################
10205 00:40:53.648065
10206 00:40:53.909822 00e00000 ################################################################
10207 00:40:53.909967
10208 00:40:54.160753 00e80000 ################################################################
10209 00:40:54.160920
10210 00:40:54.412697 00f00000 ################################################################
10211 00:40:54.412855
10212 00:40:54.659496 00f80000 ################################################################
10213 00:40:54.659641
10214 00:40:54.908829 01000000 ################################################################
10215 00:40:54.908967
10216 00:40:55.159944 01080000 ################################################################
10217 00:40:55.160116
10218 00:40:55.409981 01100000 ################################################################
10219 00:40:55.410137
10220 00:40:55.660904 01180000 ################################################################
10221 00:40:55.661047
10222 00:40:55.919047 01200000 ################################################################
10223 00:40:55.919191
10224 00:40:56.181117 01280000 ################################################################
10225 00:40:56.181252
10226 00:40:56.431114 01300000 ################################################################
10227 00:40:56.431284
10228 00:40:56.680723 01380000 ################################################################
10229 00:40:56.680881
10230 00:40:56.929483 01400000 ################################################################
10231 00:40:56.929748
10232 00:40:57.189834 01480000 ################################################################
10233 00:40:57.189982
10234 00:40:57.461224 01500000 ################################################################
10235 00:40:57.461366
10236 00:40:57.745036 01580000 ################################################################
10237 00:40:57.745172
10238 00:40:58.017423 01600000 ################################################################
10239 00:40:58.017569
10240 00:40:58.290961 01680000 ################################################################
10241 00:40:58.291102
10242 00:40:58.546719 01700000 ################################################################
10243 00:40:58.546857
10244 00:40:58.800155 01780000 ################################################################
10245 00:40:58.800318
10246 00:40:59.049250 01800000 ################################################################
10247 00:40:59.049441
10248 00:40:59.298118 01880000 ################################################################
10249 00:40:59.298284
10250 00:40:59.544719 01900000 ################################################################
10251 00:40:59.544881
10252 00:40:59.790548 01980000 ################################################################
10253 00:40:59.790722
10254 00:41:00.039022 01a00000 ################################################################
10255 00:41:00.039198
10256 00:41:00.286466 01a80000 ################################################################
10257 00:41:00.286605
10258 00:41:00.535191 01b00000 ################################################################
10259 00:41:00.535327
10260 00:41:00.783122 01b80000 ################################################################
10261 00:41:00.783258
10262 00:41:01.031621 01c00000 ################################################################
10263 00:41:01.031759
10264 00:41:01.279984 01c80000 ################################################################
10265 00:41:01.280122
10266 00:41:01.526492 01d00000 ################################################################
10267 00:41:01.526633
10268 00:41:01.773886 01d80000 ################################################################
10269 00:41:01.774024
10270 00:41:01.957395 01e00000 ################################################ done.
10271 00:41:01.957537
10272 00:41:01.960427 The bootfile was 31844598 bytes long.
10273 00:41:01.960516
10274 00:41:01.963763 Sending tftp read request... done.
10275 00:41:01.963851
10276 00:41:01.967040 Waiting for the transfer...
10277 00:41:01.967127
10278 00:41:01.967196 00000000 # done.
10279 00:41:01.967263
10280 00:41:01.977291 Command line loaded dynamically from TFTP file: 14173470/tftp-deploy-mz3f2d94/kernel/cmdline
10281 00:41:01.977381
10282 00:41:01.996973 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10283 00:41:01.997067
10284 00:41:02.000373 Loading FIT.
10285 00:41:02.000459
10286 00:41:02.003491 Image ramdisk-1 has 18735388 bytes.
10287 00:41:02.003580
10288 00:41:02.003650 Image fdt-1 has 47258 bytes.
10289 00:41:02.003715
10290 00:41:02.007045 Image kernel-1 has 13059919 bytes.
10291 00:41:02.007132
10292 00:41:02.016783 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10293 00:41:02.016870
10294 00:41:02.033177 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10295 00:41:02.033272
10296 00:41:02.039929 Choosing best match conf-1 for compat google,spherion-rev2.
10297 00:41:02.044110
10298 00:41:02.048981 Connected to device vid:did:rid of 1ae0:0028:00
10299 00:41:02.056864
10300 00:41:02.059964 tpm_get_response: command 0x17b, return code 0x0
10301 00:41:02.060051
10302 00:41:02.067090 ec_init: CrosEC protocol v3 supported (256, 248)
10303 00:41:02.067178
10304 00:41:02.070396 tpm_cleanup: add release locality here.
10305 00:41:02.070500
10306 00:41:02.073701 Shutting down all USB controllers.
10307 00:41:02.073788
10308 00:41:02.076919 Removing current net device
10309 00:41:02.077004
10310 00:41:02.079974 Exiting depthcharge with code 4 at timestamp: 51182021
10311 00:41:02.080060
10312 00:41:02.083359 LZMA decompressing kernel-1 to 0x821a6718
10313 00:41:02.083443
10314 00:41:02.086521 LZMA decompressing kernel-1 to 0x40000000
10315 00:41:03.698271
10316 00:41:03.698411 jumping to kernel
10317 00:41:03.698877 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10318 00:41:03.698980 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10319 00:41:03.699061 Setting prompt string to ['Linux version [0-9]']
10320 00:41:03.699135 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10321 00:41:03.699207 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10322 00:41:03.779876
10323 00:41:03.783316 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10324 00:41:03.786772 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10325 00:41:03.786876 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10326 00:41:03.786953 Setting prompt string to []
10327 00:41:03.787034 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10328 00:41:03.787115 Using line separator: #'\n'#
10329 00:41:03.787180 No login prompt set.
10330 00:41:03.787246 Parsing kernel messages
10331 00:41:03.787307 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10332 00:41:03.787418 [login-action] Waiting for messages, (timeout 00:04:04)
10333 00:41:03.787490 Waiting using forced prompt support (timeout 00:02:02)
10334 00:41:03.806716 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10335 00:41:03.810022 [ 0.000000] random: crng init done
10336 00:41:03.816225 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 00:41:03.819712 [ 0.000000] efi: UEFI not found.
10338 00:41:03.826269 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 00:41:03.836139 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 00:41:03.846193 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 00:41:03.852643 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 00:41:03.859418 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 00:41:03.866160 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 00:41:03.872306 [ 0.000000] NUMA: No NUMA configuration found
10345 00:41:03.878913 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 00:41:03.885298 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10347 00:41:03.885386 [ 0.000000] Zone ranges:
10348 00:41:03.892334 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 00:41:03.895442 [ 0.000000] DMA32 empty
10350 00:41:03.902071 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 00:41:03.905514 [ 0.000000] Movable zone start for each node
10352 00:41:03.908738 [ 0.000000] Early memory node ranges
10353 00:41:03.915019 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 00:41:03.921922 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 00:41:03.928285 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 00:41:03.935308 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 00:41:03.941623 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 00:41:03.948163 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 00:41:04.005128 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 00:41:04.011817 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 00:41:04.018460 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 00:41:04.021589 [ 0.000000] psci: probing for conduit method from DT.
10363 00:41:04.028323 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 00:41:04.031414 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 00:41:04.038250 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 00:41:04.041423 [ 0.000000] psci: SMC Calling Convention v1.2
10367 00:41:04.048208 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10368 00:41:04.051497 [ 0.000000] Detected VIPT I-cache on CPU0
10369 00:41:04.058240 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 00:41:04.065035 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 00:41:04.071410 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 00:41:04.077751 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 00:41:04.087691 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 00:41:04.094463 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 00:41:04.097739 [ 0.000000] alternatives: applying boot alternatives
10376 00:41:04.104387 [ 0.000000] Fallback order for Node 0: 0
10377 00:41:04.110538 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 00:41:04.114183 [ 0.000000] Policy zone: Normal
10379 00:41:04.137241 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10380 00:41:04.146861 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 00:41:04.158422 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 00:41:04.168086 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 00:41:04.174826 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10384 00:41:04.178169 <6>[ 0.000000] software IO TLB: area num 8.
10385 00:41:04.234514 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 00:41:04.383920 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10387 00:41:04.390431 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 00:41:04.396985 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 00:41:04.400353 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 00:41:04.407035 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 00:41:04.413530 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 00:41:04.416887 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 00:41:04.426841 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 00:41:04.433405 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 00:41:04.439693 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 00:41:04.446460 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 00:41:04.450136 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 00:41:04.452894 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 00:41:04.459678 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 00:41:04.462894 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 00:41:04.469478 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 00:41:04.482932 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 00:41:04.495902 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 00:41:04.502571 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 00:41:04.510306 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 00:41:04.523285 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 00:41:04.530249 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 00:41:04.536652 <6>[ 0.009183] Console: colour dummy device 80x25
10409 00:41:04.546480 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 00:41:04.553038 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10411 00:41:04.556830 <6>[ 0.029287] LSM: Security Framework initializing
10412 00:41:04.563257 <6>[ 0.034256] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 00:41:04.573148 <6>[ 0.042069] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 00:41:04.583157 <6>[ 0.051475] cblist_init_generic: Setting adjustable number of callback queues.
10415 00:41:04.586435 <6>[ 0.058918] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 00:41:04.596118 <6>[ 0.065255] cblist_init_generic: Setting adjustable number of callback queues.
10417 00:41:04.602617 <6>[ 0.072728] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 00:41:04.606298 <6>[ 0.079168] rcu: Hierarchical SRCU implementation.
10419 00:41:04.612734 <6>[ 0.079170] rcu: Max phase no-delay instances is 1000.
10420 00:41:04.619143 <6>[ 0.079194] printk: bootconsole [mtk8250] printing thread started
10421 00:41:04.626304 <6>[ 0.097523] EFI services will not be available.
10422 00:41:04.629176 <6>[ 0.097721] smp: Bringing up secondary CPUs ...
10423 00:41:04.635763 <6>[ 0.098021] Detected VIPT I-cache on CPU1
10424 00:41:04.642655 <6>[ 0.098087] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 00:41:04.649041 <6>[ 0.098119] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 00:41:04.658718 <6>[ 0.125966] Detected VIPT I-cache on CPU2
10427 00:41:04.665506 <6>[ 0.126018] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 00:41:04.675575 <6>[ 0.126034] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 00:41:04.678673 <6>[ 0.126289] Detected VIPT I-cache on CPU3
10430 00:41:04.685138 <6>[ 0.126340] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 00:41:04.691619 <6>[ 0.126354] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 00:41:04.695187 <6>[ 0.126664] CPU features: detected: Spectre-v4
10433 00:41:04.701655 <6>[ 0.126669] CPU features: detected: Spectre-BHB
10434 00:41:04.704911 <6>[ 0.126674] Detected PIPT I-cache on CPU4
10435 00:41:04.711604 <6>[ 0.126734] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 00:41:04.718091 <6>[ 0.126751] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 00:41:04.724589 <6>[ 0.127039] Detected PIPT I-cache on CPU5
10438 00:41:04.731311 <6>[ 0.127101] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 00:41:04.737909 <6>[ 0.127116] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 00:41:04.740942 <6>[ 0.127385] Detected PIPT I-cache on CPU6
10441 00:41:04.747635 <6>[ 0.127451] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 00:41:04.758394 <6>[ 0.127466] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 00:41:04.761787 <6>[ 0.127755] Detected PIPT I-cache on CPU7
10444 00:41:04.768390 <6>[ 0.127818] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 00:41:04.774748 <6>[ 0.127834] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 00:41:04.778159 <6>[ 0.127881] smp: Brought up 1 node, 8 CPUs
10447 00:41:04.785005 <6>[ 0.127886] SMP: Total of 8 processors activated.
10448 00:41:04.788054 <6>[ 0.127888] CPU features: detected: 32-bit EL0 Support
10449 00:41:04.797929 <6>[ 0.127891] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10450 00:41:04.804775 <6>[ 0.127893] CPU features: detected: Common not Private translations
10451 00:41:04.811101 <6>[ 0.127895] CPU features: detected: CRC32 instructions
10452 00:41:04.817944 <6>[ 0.127898] CPU features: detected: RCpc load-acquire (LDAPR)
10453 00:41:04.821095 <6>[ 0.127899] CPU features: detected: LSE atomic instructions
10454 00:41:04.827526 <6>[ 0.127901] CPU features: detected: Privileged Access Never
10455 00:41:04.834557 <6>[ 0.127902] CPU features: detected: RAS Extension Support
10456 00:41:04.841161 <6>[ 0.127905] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10457 00:41:04.844537 <6>[ 0.127970] CPU: All CPU(s) started at EL2
10458 00:41:04.850846 <6>[ 0.127972] alternatives: applying system-wide alternatives
10459 00:41:04.854088 <6>[ 0.141161] devtmpfs: initialized
10460 00:41:04.864022 <6>[ 0.147464] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10461 00:41:04.870809 <6>[ 0.147479] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10462 00:41:04.877252 <6>[ 0.148341] pinctrl core: initialized pinctrl subsystem
10463 00:41:04.880894 <6>[ 0.149523] DMI not present or invalid.
10464 00:41:04.906324 <6>[ 0.378716] printk:< console [ttyS0] printing thread started
10465 00:41:04.913064 6>[ 0.149835] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10466 00:41:04.920348 <6>[ 0.378723] printk: console [ttyS0] enabled
10467 00:41:04.923818 <6>[ 0.378726] printk: bootconsole [mtk8250] disabled
10468 00:41:04.930087 <6>[ 0.390743] printk: bootconsole [mtk8250] printing thread stopped
10469 00:41:04.936913 <6>[ 0.392105] SuperH (H)SCI(F) driver initialized
10470 00:41:04.940432 <6>[ 0.392587] msm_serial: driver initialized
10471 00:41:04.949954 <6>[ 0.397166] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10472 00:41:04.956741 <6>[ 0.397196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10473 00:41:04.973292 <6>[ 0.397226] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10474 00:41:04.983377 <6>[ 0.397255] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10475 00:41:04.991868 <6>[ 0.397276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10476 00:41:04.992202 <6>[ 0.397303] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10477 00:41:05.008283 <6>[ 0.397332] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10478 00:41:05.008382 <6>[ 0.397450] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10479 00:41:05.021465 <6>[ 0.397479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10480 00:41:05.025324 <6>[ 0.406018] loop: module loaded
10481 00:41:05.029509 <6>[ 0.408495] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10482 00:41:05.032801 <4>[ 0.425594] mtk-pmic-keys: Failed to locate of_node [id: -1]
10483 00:41:05.036643 <6>[ 0.426519] megasas: 07.719.03.00-rc1
10484 00:41:05.042806 <6>[ 0.436134] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10485 00:41:05.049603 <6>[ 0.444113] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10486 00:41:05.056335 <6>[ 0.455787] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10487 00:41:05.066380 <6>[ 0.508221] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10488 00:41:05.575980 <6>[ 1.045889] Freeing initrd memory: 18292K
10489 00:41:05.584447 <6>[ 1.053372] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10490 00:41:05.591013 <6>[ 1.057962] tun: Universal TUN/TAP device driver, 1.6
10491 00:41:05.594473 <6>[ 1.058713] thunder_xcv, ver 1.0
10492 00:41:05.597626 <6>[ 1.058731] thunder_bgx, ver 1.0
10493 00:41:05.600929 <6>[ 1.058744] nicpf, ver 1.0
10494 00:41:05.607770 <6>[ 1.059797] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10495 00:41:05.614894 <6>[ 1.059801] hns3: Copyright (c) 2017 Huawei Corporation.
10496 00:41:05.617942 <6>[ 1.059824] hclge is initializing
10497 00:41:05.621057 <6>[ 1.059840] e1000: Intel(R) PRO/1000 Network Driver
10498 00:41:05.628631 <6>[ 1.059842] e1000: Copyright (c) 1999-2006 Intel Corporation.
10499 00:41:05.635537 <6>[ 1.059860] e1000e: Intel(R) PRO/1000 Network Driver
10500 00:41:05.639204 <6>[ 1.059861] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10501 00:41:05.645982 <6>[ 1.059879] igb: Intel(R) Gigabit Ethernet Network Driver
10502 00:41:05.652867 <6>[ 1.059881] igb: Copyright (c) 2007-2014 Intel Corporation.
10503 00:41:05.659569 <6>[ 1.059895] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10504 00:41:05.662923 <6>[ 1.059897] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10505 00:41:05.666981 <6>[ 1.060183] sky2: driver version 1.30
10506 00:41:05.673086 <6>[ 1.061196] usbcore: registered new device driver r8152-cfgselector
10507 00:41:05.679720 <6>[ 1.061212] usbcore: registered new interface driver r8152
10508 00:41:05.686834 <6>[ 1.061284] VFIO - User Level meta-driver version: 0.3
10509 00:41:05.693506 <6>[ 1.064078] usbcore: registered new interface driver usb-storage
10510 00:41:05.696840 <6>[ 1.064256] usbcore: registered new device driver onboard-usb-hub
10511 00:41:05.703244 <6>[ 1.067038] mt6397-rtc mt6359-rtc: registered as rtc0
10512 00:41:05.713520 <6>[ 1.067185] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T00:39:39 UTC (1717547979)
10513 00:41:05.716461 <6>[ 1.067785] i2c_dev: i2c /dev entries driver
10514 00:41:05.726468 <6>[ 1.074842] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10515 00:41:05.729972 <4>[ 1.075564] cpu cpu0: supply cpu not found, using dummy regulator
10516 00:41:05.736743 <4>[ 1.075635] cpu cpu1: supply cpu not found, using dummy regulator
10517 00:41:05.742958 <4>[ 1.075701] cpu cpu2: supply cpu not found, using dummy regulator
10518 00:41:05.749794 <4>[ 1.075784] cpu cpu3: supply cpu not found, using dummy regulator
10519 00:41:05.756385 <4>[ 1.075837] cpu cpu4: supply cpu not found, using dummy regulator
10520 00:41:05.763214 <4>[ 1.075891] cpu cpu5: supply cpu not found, using dummy regulator
10521 00:41:05.769374 <4>[ 1.075942] cpu cpu6: supply cpu not found, using dummy regulator
10522 00:41:05.776064 <4>[ 1.075997] cpu cpu7: supply cpu not found, using dummy regulator
10523 00:41:05.779638 <6>[ 1.091299] cpu cpu0: EM: created perf domain
10524 00:41:05.786603 <6>[ 1.091605] cpu cpu4: EM: created perf domain
10525 00:41:05.789804 <6>[ 1.094999] sdhci: Secure Digital Host Controller Interface driver
10526 00:41:05.796489 <6>[ 1.095000] sdhci: Copyright(c) Pierre Ossman
10527 00:41:05.803344 <6>[ 1.095357] Synopsys Designware Multimedia Card Interface Driver
10528 00:41:05.806882 <6>[ 1.095742] sdhci-pltfm: SDHCI platform and OF driver helper
10529 00:41:05.813040 <6>[ 1.099978] ledtrig-cpu: registered to indicate activity on CPUs
10530 00:41:05.816345 <6>[ 1.100618] mmc0: CQHCI version 5.10
10531 00:41:05.826182 <6>[ 1.100671] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10532 00:41:05.829535 <6>[ 1.100988] usbcore: registered new interface driver usbhid
10533 00:41:05.836666 <6>[ 1.100989] usbhid: USB HID core driver
10534 00:41:05.842860 <6>[ 1.101111] spi_master spi0: will run message pump with realtime priority
10535 00:41:05.852962 <6>[ 1.135372] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10536 00:41:05.866405 <6>[ 1.138208] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10537 00:41:05.872950 <6>[ 1.139526] cros-ec-spi spi0.0: Chrome EC device registered
10538 00:41:05.882942 <6>[ 1.157251] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10539 00:41:05.889664 <6>[ 1.159515] NET: Registered PF_PACKET protocol family
10540 00:41:05.893050 <6>[ 1.159613] 9pnet: Installing 9P2000 support
10541 00:41:05.896076 <5>[ 1.159650] Key type dns_resolver registered
10542 00:41:05.902895 <6>[ 1.160000] registered taskstats version 1
10543 00:41:05.906113 <5>[ 1.160017] Loading compiled-in X.509 certificates
10544 00:41:05.916186 <4>[ 1.183818] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 00:41:05.926102 <4>[ 1.183987] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 00:41:05.932768 <3>[ 1.191304] mtk-msdc 11f60000.mmc: phase error: [map:0]
10547 00:41:05.939769 <3>[ 1.191310] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10548 00:41:05.945881 <3>[ 1.191312] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10549 00:41:05.949288 <3>[ 1.191321] mmc0: error -5 whilst initialising MMC card
10550 00:41:05.955731 <6>[ 1.194223] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10551 00:41:05.962807 <6>[ 1.194897] xhci-mtk 11200000.usb: xHCI Host Controller
10552 00:41:05.969378 <6>[ 1.194920] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10553 00:41:05.979016 <6>[ 1.195177] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10554 00:41:05.985667 <6>[ 1.195249] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10555 00:41:05.992342 <6>[ 1.195411] xhci-mtk 11200000.usb: xHCI Host Controller
10556 00:41:05.998978 <6>[ 1.195421] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10557 00:41:06.005463 <6>[ 1.195430] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10558 00:41:06.008852 <6>[ 1.196178] hub 1-0:1.0: USB hub found
10559 00:41:06.015563 <6>[ 1.196215] hub 1-0:1.0: 1 port detected
10560 00:41:06.022276 <6>[ 1.196640] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10561 00:41:06.025692 <6>[ 1.197251] hub 2-0:1.0: USB hub found
10562 00:41:06.032202 <6>[ 1.197286] hub 2-0:1.0: 1 port detected
10563 00:41:06.035348 <6>[ 1.200536] mtk-msdc 11f70000.mmc: Got CD GPIO
10564 00:41:06.042336 <6>[ 1.216466] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10565 00:41:06.051844 <6>[ 1.216474] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10566 00:41:06.058428 <4>[ 1.216625] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10567 00:41:06.068511 <6>[ 1.217284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10568 00:41:06.074860 <6>[ 1.217288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10569 00:41:06.084903 <6>[ 1.217420] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10570 00:41:06.092117 <6>[ 1.217431] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10571 00:41:06.098488 <6>[ 1.217435] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10572 00:41:06.108399 <6>[ 1.217440] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10573 00:41:06.118018 <6>[ 1.218883] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10574 00:41:06.124634 <6>[ 1.218902] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10575 00:41:06.134558 <6>[ 1.218908] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10576 00:41:06.141144 <6>[ 1.218914] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10577 00:41:06.151565 <6>[ 1.218919] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10578 00:41:06.157911 <6>[ 1.218925] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10579 00:41:06.168094 <6>[ 1.218930] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10580 00:41:06.174443 <6>[ 1.218936] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10581 00:41:06.184421 <6>[ 1.218942] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10582 00:41:06.191095 <6>[ 1.218947] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10583 00:41:06.200882 <6>[ 1.218953] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10584 00:41:06.207683 <6>[ 1.218959] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10585 00:41:06.217509 <6>[ 1.218965] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10586 00:41:06.223904 <6>[ 1.218971] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10587 00:41:06.234120 <6>[ 1.218976] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10588 00:41:06.240694 <6>[ 1.219512] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10589 00:41:06.247419 <6>[ 1.220421] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10590 00:41:06.254026 <6>[ 1.221048] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10591 00:41:06.260218 <6>[ 1.221716] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10592 00:41:06.266842 <6>[ 1.222346] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10593 00:41:06.277071 <6>[ 1.222566] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10594 00:41:06.283402 <6>[ 1.222583] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10595 00:41:06.293928 <6>[ 1.222592] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10596 00:41:06.303381 <6>[ 1.222599] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10597 00:41:06.313090 <6>[ 1.222605] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10598 00:41:06.323128 <6>[ 1.222612] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10599 00:41:06.333181 <6>[ 1.222618] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10600 00:41:06.339618 <6>[ 1.222624] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10601 00:41:06.349651 <6>[ 1.222629] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10602 00:41:06.359619 <6>[ 1.222637] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10603 00:41:06.369385 <6>[ 1.222641] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10604 00:41:06.379424 <6>[ 1.223683] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10605 00:41:06.386023 <6>[ 1.233718] Trying to probe devices needed for running init ...
10606 00:41:06.389577 <3>[ 1.287295] mtk-msdc 11f60000.mmc: phase error: [map:0]
10607 00:41:06.396160 <3>[ 1.287300] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10608 00:41:06.402507 <3>[ 1.287303] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10609 00:41:06.409009 <3>[ 1.287309] mmc0: error -5 whilst initialising MMC card
10610 00:41:06.412425 <6>[ 1.620061] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10611 00:41:06.418952 <6>[ 1.628030] mmc0: Command Queue Engine enabled
10612 00:41:06.425619 <6>[ 1.628046] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10613 00:41:06.428972 <6>[ 1.628782] mmcblk0: mmc0:0001 DA4128 116 GiB
10614 00:41:06.435654 <6>[ 1.632755] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10615 00:41:06.441985 <6>[ 1.632990] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10616 00:41:06.448781 <6>[ 1.635060] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10617 00:41:06.452266 <6>[ 1.635816] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10618 00:41:06.458653 <6>[ 1.636526] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10619 00:41:06.462004 <6>[ 1.784441] hub 1-1:1.0: USB hub found
10620 00:41:06.468649 <6>[ 1.784711] hub 1-1:1.0: 4 ports detected
10621 00:41:06.472045 <6>[ 1.787612] hub 1-1:1.0: USB hub found
10622 00:41:06.475244 <6>[ 1.787911] hub 1-1:1.0: 4 ports detected
10623 00:41:06.481855 <6>[ 1.909071] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10624 00:41:06.485299 <6>[ 1.937230] hub 2-1:1.0: USB hub found
10625 00:41:06.491838 <6>[ 1.937622] hub 2-1:1.0: 3 ports detected
10626 00:41:06.495012 <6>[ 1.939534] hub 2-1:1.0: USB hub found
10627 00:41:06.498352 <6>[ 1.939815] hub 2-1:1.0: 3 ports detected
10628 00:41:06.635541 <6>[ 2.101059] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10629 00:41:06.756503 <6>[ 2.228390] hub 1-1.4:1.0: USB hub found
10630 00:41:06.759561 <6>[ 2.228775] hub 1-1.4:1.0: 2 ports detected
10631 00:41:06.763074 <6>[ 2.232039] hub 1-1.4:1.0: USB hub found
10632 00:41:06.769554 <6>[ 2.232371] hub 1-1.4:1.0: 2 ports detected
10633 00:41:06.839556 <6>[ 2.305211] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10634 00:41:06.943758 <6>[ 2.409576] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10635 00:41:06.967774 <4>[ 2.435999] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10636 00:41:06.977702 <4>[ 2.436018] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10637 00:41:07.004658 <6>[ 2.474389] r8152 2-1.3:1.0 eth0: v1.12.13
10638 00:41:07.059841 <6>[ 2.525046] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10639 00:41:07.243461 <6>[ 2.709037] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10640 00:41:08.656068 <6>[ 4.128189] r8152 2-1.3:1.0 eth0: carrier on
10641 00:41:11.331941 <5>[ 4.153004] Sending DHCP requests .., OK
10642 00:41:11.338318 <6>[ 6.800953] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10643 00:41:11.345123 Loading, please <6>[ 6.800971] IP-Config: Complete:
10644 00:41:11.345206 wait...
10645 00:41:11.355028 <6>[ 6.800973] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10646 00:41:11.365117 <6>[ 6.800983] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10647 00:41:11.371275 <6>[ 6.800988] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10648 00:41:11.378104 Starting systemd<6>[ 6.800993] nameserver0=192.168.201.1
10649 00:41:11.381561 -udevd version 2<6>[ 6.801279] clk: Disabling unused clocks
10650 00:41:11.384888 52.22-1~deb12u1
10651 00:41:11.388340 <6>[ 6.802593] ALSA device list:
10652 00:41:11.388422
10653 00:41:11.391575 <6>[ 6.802606] No soundcards found.
10654 00:41:11.394883 <6>[ 6.806947] Freeing unused kernel memory: 8512K
10655 00:41:11.401101 <6>[ 6.807140] Run /init as init process
10656 00:41:11.614814 <6>[ 7.083064] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10657 00:41:11.621743 <6>[ 7.083091] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10658 00:41:11.631336 <6>[ 7.083097] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10659 00:41:11.638440 <6>[ 7.096114] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10660 00:41:11.644813 <6>[ 7.099995] remoteproc remoteproc0: scp is available
10661 00:41:11.651346 <6>[ 7.100630] remoteproc remoteproc0: powering up scp
10662 00:41:11.657907 <6>[ 7.100636] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10663 00:41:11.664792 <6>[ 7.100658] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10664 00:41:11.671149 <3>[ 7.128130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 00:41:11.681180 <3>[ 7.128159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 00:41:11.687629 <3>[ 7.128162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 00:41:11.697658 <3>[ 7.128556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 00:41:11.704400 <3>[ 7.128565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 00:41:11.710771 <3>[ 7.128572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 00:41:11.721030 <3>[ 7.128580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 00:41:11.727423 <3>[ 7.128584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 00:41:11.737537 <3>[ 7.128617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 00:41:11.743970 <3>[ 7.128654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 00:41:11.754332 <3>[ 7.128656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 00:41:11.760557 <3>[ 7.128660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 00:41:11.770412 <3>[ 7.128684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 00:41:11.777057 <3>[ 7.128687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 00:41:11.783856 <3>[ 7.128690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 00:41:11.793546 <3>[ 7.128693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 00:41:11.800426 <3>[ 7.128696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 00:41:11.810294 <3>[ 7.128719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 00:41:11.816720 <4>[ 7.128771] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10683 00:41:11.823218 <4>[ 7.128906] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10684 00:41:11.833223 <6>[ 7.133122] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10685 00:41:11.839828 <4>[ 7.158384] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10686 00:41:11.846901 <4>[ 7.158384] Fallback method does not support PEC.
10687 00:41:11.850141 <6>[ 7.177700] mc: Linux media interface: v0.10
10688 00:41:11.856862 <6>[ 7.202266] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10689 00:41:11.863164 <6>[ 7.202278] pci_bus 0000:00: root bus resource [bus 00-ff]
10690 00:41:11.869949 <6>[ 7.202283] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10691 00:41:11.879954 <6>[ 7.202286] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10692 00:41:11.886668 <6>[ 7.202317] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10693 00:41:11.893440 <6>[ 7.202331] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10694 00:41:11.896501 <6>[ 7.202414] pci 0000:00:00.0: supports D1 D2
10695 00:41:11.902941 <6>[ 7.202416] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10696 00:41:11.912898 <6>[ 7.203461] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10697 00:41:11.919401 <6>[ 7.203650] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10698 00:41:11.926503 <6>[ 7.203676] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10699 00:41:11.933062 <6>[ 7.203695] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10700 00:41:11.942678 <6>[ 7.203710] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10701 00:41:11.946407 <6>[ 7.203825] pci 0000:01:00.0: supports D1 D2
10702 00:41:11.952999 <6>[ 7.203828] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10703 00:41:11.959147 <6>[ 7.212826] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10704 00:41:11.969170 <6>[ 7.212861] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10705 00:41:11.976034 <6>[ 7.212864] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10706 00:41:11.982415 <6>[ 7.212871] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10707 00:41:11.992355 <6>[ 7.212884] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10708 00:41:11.999084 <6>[ 7.212897] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10709 00:41:12.005674 <6>[ 7.212908] pci 0000:00:00.0: PCI bridge to [bus 01]
10710 00:41:12.012344 <6>[ 7.212913] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10711 00:41:12.018814 <6>[ 7.213067] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10712 00:41:12.025871 <6>[ 7.213586] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10713 00:41:12.032519 <6>[ 7.213989] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10714 00:41:12.038856 <6>[ 7.225886] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10715 00:41:12.045750 <6>[ 7.225913] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10716 00:41:12.052289 <6>[ 7.225920] remoteproc remoteproc0: remote processor scp is now up
10717 00:41:12.062309 <6>[ 7.233164] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10718 00:41:12.071789 <6>[ 7.233488] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10719 00:41:12.082061 <6>[ 7.236781] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10720 00:41:12.088681 <6>[ 7.242194] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10721 00:41:12.098756 <6>[ 7.247078] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10722 00:41:12.105314 <6>[ 7.256852] videodev: Linux video capture interface: v2.00
10723 00:41:12.108582 <6>[ 7.264327] Bluetooth: Core ver 2.22
10724 00:41:12.112057 <6>[ 7.264398] NET: Registered PF_BLUETOOTH protocol family
10725 00:41:12.118371 <6>[ 7.264402] Bluetooth: HCI device and connection manager initialized
10726 00:41:12.125151 <6>[ 7.264431] Bluetooth: HCI socket layer initialized
10727 00:41:12.131796 <6>[ 7.264441] Bluetooth: L2CAP socket layer initialized
10728 00:41:12.135013 <6>[ 7.264458] Bluetooth: SCO socket layer initialized
10729 00:41:12.145004 <5>[ 7.282479] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10730 00:41:12.151470 <5>[ 7.295902] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10731 00:41:12.158413 <5>[ 7.296460] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10732 00:41:12.168501 <4>[ 7.296542] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10733 00:41:12.171488 <6>[ 7.296551] cfg80211: failed to load regulatory.db
10734 00:41:12.178484 <6>[ 7.326238] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10735 00:41:12.191629 <6>[ 7.327534] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10736 00:41:12.197798 <6>[ 7.327656] usbcore: registered new interface driver uvcvideo
10737 00:41:12.204662 <6>[ 7.335908] usbcore: registered new interface driver btusb
10738 00:41:12.214688 <4>[ 7.336721] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10739 00:41:12.220885 <3>[ 7.336758] Bluetooth: hci0: Failed to load firmware file (-2)
10740 00:41:12.228111 <3>[ 7.336760] Bluetooth: hci0: Failed to set up firmware (-2)
10741 00:41:12.237721 <4>[ 7.336763] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10742 00:41:12.244500 <6>[ 7.358933] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10743 00:41:12.250748 <6>[ 7.403338] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10744 00:41:12.257311 <6>[ 7.403440] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10745 00:41:12.260822 <6>[ 7.420871] mt7921e 0000:01:00.0: ASIC revision: 79610010
10746 00:41:12.270689 <6>[ 7.519508] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10747 00:41:12.274324 <6>[ 7.519508]
10748 00:41:12.277331 Begin: Loading essential drivers ... done.
10749 00:41:12.280444 Begin: Running /scripts/init-premount ... done.
10750 00:41:12.287204 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10751 00:41:12.296810 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10752 00:41:12.306875 Device /sys/class/net/eth0 fou<6>[ 7.776336] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10753 00:41:12.306959 nd
10754 00:41:12.307026 done.
10755 00:41:12.319806 Begin: Waiting up to 180 secs for any network device to become available ... done.
10756 00:41:12.407867 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10757 00:41:12.516056 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10758 00:41:12.522506 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10759 00:41:12.529055 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10760 00:41:12.535611 host : mt8192-asurada-spherion-r0-cbg-1
10761 00:41:12.542306 domain : lava-rack
10762 00:41:12.545759 rootserver: 192.168.201.1 rootpath:
10763 00:41:12.548925 filename :
10764 00:41:12.655491 done.
10765 00:41:12.661978 Begin: Running /scripts/nfs-bottom ... done.
10766 00:41:12.677663 Begin: Running /scripts/init-bottom ... done.
10767 00:41:13.975375 <6>[ 9.448629] NET: Registered PF_INET6 protocol family
10768 00:41:13.978580 <6>[ 9.450588] Segment Routing with IPv6
10769 00:41:13.985138 <6>[ 9.450605] In-situ OAM (IOAM) with IPv6
10770 00:41:14.134245 <30>[ 9.578256] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10771 00:41:14.140523 <30>[ 9.578297] systemd[1]: Detected architecture arm64.
10772 00:41:14.140643
10773 00:41:14.143867 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10774 00:41:14.147389
10775 00:41:14.171242 <30>[ 9.641823] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10776 00:41:15.118531 <30>[ 10.585780] systemd[1]: Queued start job for default target graphical.target.
10777 00:41:15.167909 [[0;32m OK [0m] Created slic<30>[ 10.634514] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10778 00:41:15.171686 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10779 00:41:15.196507 [[0;32m OK [0m] Created slic<30>[ 10.662892] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10780 00:41:15.200010 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10781 00:41:15.224187 [[0;32m OK [0m] Created slic<30>[ 10.690909] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10782 00:41:15.230938 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10783 00:41:15.251929 [[0;32m OK [0m] Created slic<30>[ 10.718509] systemd[1]: Created slice user.slice - User and Session Slice.
10784 00:41:15.255068 e [0;1;39muser.slice[0m - User and Session Slice.
10785 00:41:15.282493 [[0;32m OK [0m] Started [0;<30>[ 10.745912] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10786 00:41:15.285795 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10787 00:41:15.309951 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 10.773311] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10788 00:41:15.313073 -passwo… Requests to Wall Directory Watch.
10789 00:41:15.345274 Expecting device [0;1;<30>[ 10.801728] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10790 00:41:15.355372 39mdev-ttyS0.dev<30>[ 10.801911] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10791 00:41:15.358238 ice[0m - /dev/ttyS0...
10792 00:41:15.379200 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 10.845366] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10793 00:41:15.382174 tsetup.…get[0m - Local Encrypted Volumes.
10794 00:41:15.406317 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 10.873151] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10795 00:41:15.413324 grityse…Local Integrity Protected Volumes.
10796 00:41:15.434782 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 10.901572] systemd[1]: Reached target paths.target - Path Units.
10797 00:41:15.434870 s.target[0m - Path Units.
10798 00:41:15.459012 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 10.925527] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10799 00:41:15.462047 te-fs.target[0m - Remote File Systems.
10800 00:41:15.482058 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 10.949091] systemd[1]: Reached target slices.target - Slice Units.
10801 00:41:15.485431 es.target[0m - Slice Units.
10802 00:41:15.506987 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 10.973490] systemd[1]: Reached target swap.target - Swaps.
10803 00:41:15.507075 .target[0m - Swaps.
10804 00:41:15.530968 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 10.997552] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10805 00:41:15.537424 tysetup… - Local Verity Protected Volumes.
10806 00:41:15.559265 [[0;32m OK [0m] Listening on<30>[ 11.026017] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10807 00:41:15.566012 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10808 00:41:15.589257 [[0;32m OK [<30>[ 11.055803] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10809 00:41:15.595508 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10810 00:41:15.615625 [[0;32m OK [0m] Listening on<30>[ 11.082327] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10811 00:41:15.622146 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10812 00:41:15.642817 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.109704] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10813 00:41:15.646470 d-journald.socket[0m - Journal Socket.
10814 00:41:15.667957 [[0;32m OK [0m] Listening on<30>[ 11.134407] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10815 00:41:15.674286 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10816 00:41:15.694377 <30>[ 11.164694] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10817 00:41:15.704539 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10818 00:41:15.722935 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 11.189552] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10819 00:41:15.726057 d-udevd…l.socket[0m - udev Kernel Socket.
10820 00:41:15.774277 Mounting [0;1;39mdev-hugepages.mount[<30>[ 11.241160] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10821 00:41:15.777480 0m - Huge Pages File System...
10822 00:41:15.803226 Mounting [0;1;39mdev-m<30>[ 11.269781] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10823 00:41:15.806607 queue.mount…POSIX Message Queue File System...
10824 00:41:15.835466 Mounting [0;1;39msys-k<30>[ 11.301863] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10825 00:41:15.838882 ernel-debug.…[0m - Kernel Debug File System...
10826 00:41:15.872421 <30>[ 11.329655] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10827 00:41:15.882322 <30>[ 11.336010] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10828 00:41:15.889128 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10829 00:41:15.920657 Starting [0;1;39mmodpr<30>[ 11.386958] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10830 00:41:15.923936 obe@configfs…m - Load Kernel Module configfs...
10831 00:41:15.952267 Starting [0;1;39mmodpr<30>[ 11.418949] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10832 00:41:15.955702 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10833 00:41:15.984193 Starting [0;1;39mmodpr<30>[ 11.450709] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10834 00:41:15.987504 obe@drm.service[0m - Load Kernel Module drm...
10835 00:41:15.997422 <6>[ 11.462952] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10836 00:41:15.997510
10837 00:41:16.023830 Starting [0;1;39mmodpr<30>[ 11.490595] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10838 00:41:16.027158 obe@efi_psto…- Load Kernel Module efi_pstore...
10839 00:41:16.056144 Starting [0;1;39mmodpr<30>[ 11.522900] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10840 00:41:16.059390 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10841 00:41:16.088305 Starting [0;1;39mmodpr<30>[ 11.554849] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10842 00:41:16.094834 obe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 11.566732] fuse: init (API version 7.37)
10843 00:41:16.094923 .
10844 00:41:16.127740 Starting [0;1;39msyste<30>[ 11.594358] systemd[1]: Starting systemd-journald.service - Journal Service...
10845 00:41:16.131098 md-journald.service[0m - Journal Service...
10846 00:41:16.167225 Starting [0;1;39msyste<30>[ 11.633885] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10847 00:41:16.170564 md-modules-l…rvice[0m - Load Kernel Modules...
10848 00:41:16.203526 Starting [0;1;39msyste<30>[ 11.667047] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10849 00:41:16.206886 md-network-g… units from Kernel command line...
10850 00:41:16.237541 Startin<30>[ 11.703888] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10851 00:41:16.243946 g [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10852 00:41:16.306773 Starting [0;1;39msystemd-udev-trig…[<30>[ 11.773624] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10853 00:41:16.310407 0m - Coldplug All udev Devices...
10854 00:41:16.347490 [[0;32m OK [0m] Started [0;<30>[ 11.814272] systemd[1]: Started systemd-journald.service - Journal Service.
10855 00:41:16.350609 1;39msystemd-journald.service[0m - Journal Service.
10856 00:41:16.378979 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10857 00:41:16.399124 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10858 00:41:16.415384 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10859 00:41:16.431954 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10860 00:41:16.456945 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10861 00:41:16.477313 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10862 00:41:16.492401 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10863 00:41:16.512779 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10864 00:41:16.532128 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10865 00:41:16.552135 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10866 00:41:16.572482 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10867 00:41:16.592475 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10868 00:41:16.612537 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10869 00:41:16.633211 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10870 00:41:16.687404 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10871 00:41:16.711808 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10872 00:41:16.767456 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10873 00:41:16.796503 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10874 00:41:16.826287 <46>[ 12.293255] systemd-journald[316]: Received client request to flush runtime journal.
10875 00:41:16.875833 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10876 00:41:17.059559 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10877 00:41:17.084233 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10878 00:41:17.098197 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10879 00:41:17.387919 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10880 00:41:17.408240 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10881 00:41:18.229205 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10882 00:41:18.252435 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10883 00:41:18.272087 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10884 00:41:18.335140 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10885 00:41:18.409810 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10886 00:41:18.427419 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10887 00:41:18.446649 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10888 00:41:18.506512 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10889 00:41:18.529797 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10890 00:41:18.693965 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10891 00:41:18.745497 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10892 00:41:18.815075 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10893 00:41:19.099486 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10894 00:41:19.134891 <6>[ 14.605019] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10895 00:41:19.152491 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10896 00:41:19.194846 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10897 00:41:19.244412 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10898 00:41:19.290865 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10899 00:41:19.347284 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10900 00:41:19.374425 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10901 00:41:19.397902 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10902 00:41:19.419427 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10903 00:41:19.449260 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10904 00:41:19.495373 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10905 00:41:19.516877 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10906 00:41:19.556885 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10907 00:41:19.579301 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10908 00:41:19.599335 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10909 00:41:19.614744 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10910 00:41:19.630776 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10911 00:41:19.657950 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10912 00:41:19.677584 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10913 00:41:19.694703 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10914 00:41:19.721991 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10915 00:41:19.741325 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10916 00:41:19.758521 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10917 00:41:19.776079 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10918 00:41:19.794424 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10919 00:41:19.811127 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10920 00:41:19.864150 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10921 00:41:19.894797 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10922 00:41:19.939292 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10923 00:41:20.015430 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10924 00:41:20.128402 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10925 00:41:20.198004 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10926 00:41:20.222420 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10927 00:41:20.235826 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10928 00:41:20.252792 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10929 00:41:20.291116 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10930 00:41:20.324594 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10931 00:41:20.349165 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10932 00:41:20.371452 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10933 00:41:20.422194 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10934 00:41:20.469370 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10935 00:41:20.539851
10936 00:41:20.543059 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10937 00:41:20.543250
10938 00:41:20.546646 debian-bookworm-arm64 login: root (automatic login)
10939 00:41:20.546927
10940 00:41:20.824116 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10941 00:41:20.824639
10942 00:41:20.830743 The programs included with the Debian GNU/Linux system are free software;
10943 00:41:20.837743 the exact distribution terms for each program are described in the
10944 00:41:20.840612 individual files in /usr/share/doc/*/copyright.
10945 00:41:20.841045
10946 00:41:20.847248 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10947 00:41:20.850685 permitted by applicable law.
10948 00:41:21.902384 Matched prompt #10: / #
10950 00:41:21.903777 Setting prompt string to ['/ #']
10951 00:41:21.904312 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10953 00:41:21.905524 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10954 00:41:21.906066 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10955 00:41:21.906504 Setting prompt string to ['/ #']
10956 00:41:21.906884 Forcing a shell prompt, looking for ['/ #']
10958 00:41:21.957896 / #
10959 00:41:21.958440 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10960 00:41:21.958848 Waiting using forced prompt support (timeout 00:02:30)
10961 00:41:21.964128
10962 00:41:21.965228 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10963 00:41:21.966097 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10965 00:41:22.067818 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35'
10966 00:41:22.073899 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173470/extract-nfsrootfs-ctx3uf35'
10968 00:41:22.175608 / # export NFS_SERVER_IP='192.168.201.1'
10969 00:41:22.182411 export NFS_SERVER_IP='192.168.201.1'
10970 00:41:22.183367 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10971 00:41:22.184030 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10972 00:41:22.184674 end: 2 depthcharge-action (duration 00:01:15) [common]
10973 00:41:22.185200 start: 3 lava-test-retry (timeout 00:08:06) [common]
10974 00:41:22.185690 start: 3.1 lava-test-shell (timeout 00:08:06) [common]
10975 00:41:22.186318 Using namespace: common
10977 00:41:22.287689 / # #
10978 00:41:22.288365 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10979 00:41:22.294050 #
10980 00:41:22.294899 Using /lava-14173470
10982 00:41:22.396299 / # export SHELL=/bin/bash
10983 00:41:22.402750 export SHELL=/bin/bash
10985 00:41:22.504155 / # . /lava-14173470/environment
10986 00:41:22.510431 . /lava-14173470/environment
10988 00:41:22.617425 / # /lava-14173470/bin/lava-test-runner /lava-14173470/0
10989 00:41:22.617665 Test shell timeout: 10s (minimum of the action and connection timeout)
10990 00:41:22.622658 /lava-14173470/bin/lava-test-runner /lava-14173470/0
10991 00:41:22.886368 + export TESTRUN_ID=0_timesync-off
10992 00:41:22.889989 + TESTRUN_ID=0_timesync-off
10993 00:41:22.893133 + cd /lava-14173470/0/tests/0_timesync-off
10994 00:41:22.896574 ++ cat uuid
10995 00:41:22.900323 + UUID=14173470_1.6.2.3.1
10996 00:41:22.900869 + set +x
10997 00:41:22.907068 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14173470_1.6.2.3.1>
10998 00:41:22.907923 Received signal: <STARTRUN> 0_timesync-off 14173470_1.6.2.3.1
10999 00:41:22.908435 Starting test lava.0_timesync-off (14173470_1.6.2.3.1)
11000 00:41:22.908946 Skipping test definition patterns.
11001 00:41:22.910385 + systemctl stop systemd-timesyncd
11002 00:41:22.978387 + set +x
11003 00:41:22.981696 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14173470_1.6.2.3.1>
11004 00:41:22.982438 Received signal: <ENDRUN> 0_timesync-off 14173470_1.6.2.3.1
11005 00:41:22.982973 Ending use of test pattern.
11006 00:41:22.983508 Ending test lava.0_timesync-off (14173470_1.6.2.3.1), duration 0.08
11008 00:41:23.049637 + export TESTRUN_ID=1_kselftest-tpm2
11009 00:41:23.052845 + TESTRUN_ID=1_kselftest-tpm2
11010 00:41:23.059941 + cd /lava-14173470/0/tests/1_kselftest-tpm2
11011 00:41:23.060527 ++ cat uuid
11012 00:41:23.062831 + UUID=14173470_1.6.2.3.5
11013 00:41:23.063469 + set +x
11014 00:41:23.069412 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14173470_1.6.2.3.5>
11015 00:41:23.070249 Received signal: <STARTRUN> 1_kselftest-tpm2 14173470_1.6.2.3.5
11016 00:41:23.070926 Starting test lava.1_kselftest-tpm2 (14173470_1.6.2.3.5)
11017 00:41:23.071588 Skipping test definition patterns.
11018 00:41:23.072581 + cd ./automated/linux/kselftest/
11019 00:41:23.099373 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11020 00:41:23.136796 INFO: install_deps skipped
11021 00:41:23.631761 --2024-06-05 00:39:57-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11022 00:41:23.644706 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11023 00:41:23.773808 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11024 00:41:23.903679 HTTP request sent, awaiting response... 200 OK
11025 00:41:23.906913 Length: 1648104 (1.6M) [application/octet-stream]
11026 00:41:23.910841 Saving to: 'kselftest_armhf.tar.gz'
11027 00:41:23.911415
11028 00:41:23.911795
11029 00:41:24.162000 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11030 00:41:24.420280 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11031 00:41:24.725282 kselftest_armhf.tar 13%[=> ] 216.08K 418KB/s
11032 00:41:24.857129 kselftest_armhf.tar 51%[=========> ] 822.71K 1001KB/s
11033 00:41:24.863693 kselftest_armhf.tar 100%[===================>] 1.57M 1.65MB/s in 1.0s
11034 00:41:24.863835
11035 00:41:25.008139 2024-06-05 00:39:58 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1648104/1648104]
11036 00:41:25.008281
11037 00:41:29.581231 skiplist:
11038 00:41:29.584278 ========================================
11039 00:41:29.587315 ========================================
11040 00:41:29.639514 tpm2:test_smoke.sh
11041 00:41:29.643064 tpm2:test_space.sh
11042 00:41:29.661388 ============== Tests to run ===============
11043 00:41:29.661836 tpm2:test_smoke.sh
11044 00:41:29.664760 tpm2:test_space.sh
11045 00:41:29.668285 ===========End Tests to run ===============
11046 00:41:29.671290 shardfile-tpm2 pass
11047 00:41:29.785968 <12>[ 25.259814] kselftest: Running tests in tpm2
11048 00:41:29.791617 TAP version 13
11049 00:41:29.806742 1..2
11050 00:41:29.837246 # selftests: tpm2: test_smoke.sh
11051 00:41:31.692079 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11052 00:41:31.698938 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11053 00:41:31.705484 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11054 00:41:31.708846 # Traceback (most recent call last):
11055 00:41:31.719246 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11056 00:41:31.719456 # if self.tpm:
11057 00:41:31.722194 # ^^^^^^^^
11058 00:41:31.725920 # AttributeError: 'Client' object has no attribute 'tpm'
11059 00:41:31.732181 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11060 00:41:31.738682 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11061 00:41:31.742550 # Traceback (most recent call last):
11062 00:41:31.752507 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11063 00:41:31.752858 # if self.tpm:
11064 00:41:31.755572 # ^^^^^^^^
11065 00:41:31.759075 # AttributeError: 'Client' object has no attribute 'tpm'
11066 00:41:31.765835 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11067 00:41:31.772529 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11068 00:41:31.775547 # Traceback (most recent call last):
11069 00:41:31.785814 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11070 00:41:31.788987 # if self.tpm:
11071 00:41:31.789547 # ^^^^^^^^
11072 00:41:31.795728 # AttributeError: 'Client' object has no attribute 'tpm'
11073 00:41:31.802534 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11074 00:41:31.809017 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11075 00:41:31.812344 # Traceback (most recent call last):
11076 00:41:31.822502 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11077 00:41:31.822998 # if self.tpm:
11078 00:41:31.825799 # ^^^^^^^^
11079 00:41:31.828851 # AttributeError: 'Client' object has no attribute 'tpm'
11080 00:41:31.835459 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11081 00:41:31.842190 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11082 00:41:31.845663 # Traceback (most recent call last):
11083 00:41:31.855524 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11084 00:41:31.859176 # if self.tpm:
11085 00:41:31.859674 # ^^^^^^^^
11086 00:41:31.866168 # AttributeError: 'Client' object has no attribute 'tpm'
11087 00:41:31.869552 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11088 00:41:31.875512 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11089 00:41:31.879125 # Traceback (most recent call last):
11090 00:41:31.888946 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11091 00:41:31.892364 # if self.tpm:
11092 00:41:31.892874 # ^^^^^^^^
11093 00:41:31.899064 # AttributeError: 'Client' object has no attribute 'tpm'
11094 00:41:31.905495 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11095 00:41:31.912137 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11096 00:41:31.915483 # Traceback (most recent call last):
11097 00:41:31.925340 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11098 00:41:31.925832 # if self.tpm:
11099 00:41:31.928593 # ^^^^^^^^
11100 00:41:31.932204 # AttributeError: 'Client' object has no attribute 'tpm'
11101 00:41:31.942037 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11102 00:41:31.948598 # Exception ignored in: <function Client.__del__ at 0xffff8635ccc0>
11103 00:41:31.952089 # Traceback (most recent call last):
11104 00:41:31.961840 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11105 00:41:31.962315 # if self.tpm:
11106 00:41:31.965325 # ^^^^^^^^
11107 00:41:31.969126 # AttributeError: 'Client' object has no attribute 'tpm'
11108 00:41:31.969623 #
11109 00:41:31.975706 # ======================================================================
11110 00:41:31.985858 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11111 00:41:31.989144 # ----------------------------------------------------------------------
11112 00:41:31.992578 # Traceback (most recent call last):
11113 00:41:32.002877 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11114 00:41:32.009276 # self.root_key = self.client.create_root_key()
11115 00:41:32.012773 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11116 00:41:32.022741 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11117 00:41:32.029429 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11118 00:41:32.032693 # ^^^^^^^^^^^^^^^^^^
11119 00:41:32.043018 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11120 00:41:32.045984 # raise ProtocolError(cc, rc)
11121 00:41:32.053041 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11122 00:41:32.053525 #
11123 00:41:32.059552 # ======================================================================
11124 00:41:32.066458 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11125 00:41:32.072775 # ----------------------------------------------------------------------
11126 00:41:32.076267 # Traceback (most recent call last):
11127 00:41:32.085909 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11128 00:41:32.089542 # self.client = tpm2.Client()
11129 00:41:32.092360 # ^^^^^^^^^^^^^
11130 00:41:32.102479 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11131 00:41:32.105782 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11132 00:41:32.112766 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11133 00:41:32.115747 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11134 00:41:32.115864 #
11135 00:41:32.122493 # ======================================================================
11136 00:41:32.129283 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11137 00:41:32.136214 # ----------------------------------------------------------------------
11138 00:41:32.139584 # Traceback (most recent call last):
11139 00:41:32.149467 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11140 00:41:32.152619 # self.client = tpm2.Client()
11141 00:41:32.156096 # ^^^^^^^^^^^^^
11142 00:41:32.165858 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11143 00:41:32.169194 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11144 00:41:32.175825 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11145 00:41:32.179508 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11146 00:41:32.179583 #
11147 00:41:32.185965 # ======================================================================
11148 00:41:32.192757 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11149 00:41:32.198819 # ----------------------------------------------------------------------
11150 00:41:32.202418 # Traceback (most recent call last):
11151 00:41:32.212669 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11152 00:41:32.215810 # self.client = tpm2.Client()
11153 00:41:32.219148 # ^^^^^^^^^^^^^
11154 00:41:32.229664 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11155 00:41:32.236403 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11156 00:41:32.239254 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11157 00:41:32.245943 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11158 00:41:32.246468 #
11159 00:41:32.252723 # ======================================================================
11160 00:41:32.259362 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11161 00:41:32.266400 # ----------------------------------------------------------------------
11162 00:41:32.269951 # Traceback (most recent call last):
11163 00:41:32.280105 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11164 00:41:32.283766 # self.client = tpm2.Client()
11165 00:41:32.286799 # ^^^^^^^^^^^^^
11166 00:41:32.296468 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11167 00:41:32.299757 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11168 00:41:32.306494 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11169 00:41:32.310675 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11170 00:41:32.311147 #
11171 00:41:32.318253 # ======================================================================
11172 00:41:32.321582 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11173 00:41:32.328931 # ----------------------------------------------------------------------
11174 00:41:32.332226 # Traceback (most recent call last):
11175 00:41:32.341608 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11176 00:41:32.345125 # self.client = tpm2.Client()
11177 00:41:32.348921 # ^^^^^^^^^^^^^
11178 00:41:32.358698 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11179 00:41:32.365214 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11180 00:41:32.368285 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11181 00:41:32.375422 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11182 00:41:32.376026 #
11183 00:41:32.381745 # ======================================================================
11184 00:41:32.385087 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11185 00:41:32.391755 # ----------------------------------------------------------------------
11186 00:41:32.395120 # Traceback (most recent call last):
11187 00:41:32.408468 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11188 00:41:32.408988 # self.client = tpm2.Client()
11189 00:41:32.412067 # ^^^^^^^^^^^^^
11190 00:41:32.421921 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11191 00:41:32.428711 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11192 00:41:32.431988 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11193 00:41:32.438534 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11194 00:41:32.439230 #
11195 00:41:32.445015 # ======================================================================
11196 00:41:32.451452 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11197 00:41:32.458306 # ----------------------------------------------------------------------
11198 00:41:32.461775 # Traceback (most recent call last):
11199 00:41:32.471458 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11200 00:41:32.475656 # self.client = tpm2.Client()
11201 00:41:32.478658 # ^^^^^^^^^^^^^
11202 00:41:32.488503 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11203 00:41:32.491664 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11204 00:41:32.498508 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11205 00:41:32.501829 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11206 00:41:32.502530 #
11207 00:41:32.508110 # ======================================================================
11208 00:41:32.518297 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11209 00:41:32.525275 # ----------------------------------------------------------------------
11210 00:41:32.528544 # Traceback (most recent call last):
11211 00:41:32.538273 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11212 00:41:32.541569 # self.client = tpm2.Client()
11213 00:41:32.544944 # ^^^^^^^^^^^^^
11214 00:41:32.551773 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11215 00:41:32.558376 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11216 00:41:32.561885 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11217 00:41:32.568532 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11218 00:41:32.569001 #
11219 00:41:32.574868 # ----------------------------------------------------------------------
11220 00:41:32.578480 # Ran 9 tests in 0.050s
11221 00:41:32.579085 #
11222 00:41:32.579460 # FAILED (errors=9)
11223 00:41:32.585247 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11224 00:41:32.591625 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11225 00:41:32.592098 #
11226 00:41:32.598834 # ----------------------------------------------------------------------
11227 00:41:32.601717 # Ran 2 tests in 0.032s
11228 00:41:32.602140 #
11229 00:41:32.602479 # OK
11230 00:41:32.605160 ok 1 selftests: tpm2: test_smoke.sh
11231 00:41:32.608196 # selftests: tpm2: test_space.sh
11232 00:41:32.615190 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11233 00:41:32.621908 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11234 00:41:32.625316 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11235 00:41:32.631826 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11236 00:41:32.632369 #
11237 00:41:32.638381 # ======================================================================
11238 00:41:32.645271 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11239 00:41:32.652261 # ----------------------------------------------------------------------
11240 00:41:32.655109 # Traceback (most recent call last):
11241 00:41:32.668744 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11242 00:41:32.671867 # root1 = space1.create_root_key()
11243 00:41:32.675306 # ^^^^^^^^^^^^^^^^^^^^^^^^
11244 00:41:32.685010 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11245 00:41:32.688664 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11246 00:41:32.695392 # ^^^^^^^^^^^^^^^^^^
11247 00:41:32.705747 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11248 00:41:32.708539 # raise ProtocolError(cc, rc)
11249 00:41:32.712347 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11250 00:41:32.715259 #
11251 00:41:32.718840 # ======================================================================
11252 00:41:32.725229 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11253 00:41:32.731841 # ----------------------------------------------------------------------
11254 00:41:32.735338 # Traceback (most recent call last):
11255 00:41:32.745442 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11256 00:41:32.748305 # space1.create_root_key()
11257 00:41:32.758885 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11258 00:41:32.765411 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11259 00:41:32.768517 # ^^^^^^^^^^^^^^^^^^
11260 00:41:32.778619 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11261 00:41:32.781752 # raise ProtocolError(cc, rc)
11262 00:41:32.788501 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11263 00:41:32.789055 #
11264 00:41:32.795185 # ======================================================================
11265 00:41:32.802026 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11266 00:41:32.808146 # ----------------------------------------------------------------------
11267 00:41:32.811678 # Traceback (most recent call last):
11268 00:41:32.821738 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11269 00:41:32.824902 # root1 = space1.create_root_key()
11270 00:41:32.827984 # ^^^^^^^^^^^^^^^^^^^^^^^^
11271 00:41:32.838487 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11272 00:41:32.845282 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11273 00:41:32.848456 # ^^^^^^^^^^^^^^^^^^
11274 00:41:32.858480 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11275 00:41:32.861755 # raise ProtocolError(cc, rc)
11276 00:41:32.868738 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11277 00:41:32.869201 #
11278 00:41:32.875045 # ======================================================================
11279 00:41:32.881743 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11280 00:41:32.888451 # ----------------------------------------------------------------------
11281 00:41:32.891637 # Traceback (most recent call last):
11282 00:41:32.901693 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11283 00:41:32.905204 # root1 = space1.create_root_key()
11284 00:41:32.911993 # ^^^^^^^^^^^^^^^^^^^^^^^^
11285 00:41:32.922477 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11286 00:41:32.925219 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11287 00:41:32.932012 # ^^^^^^^^^^^^^^^^^^
11288 00:41:32.941442 # File "/lava-14173470/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11289 00:41:32.945318 # raise ProtocolError(cc, rc)
11290 00:41:32.948261 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11291 00:41:32.948346 #
11292 00:41:32.954809 # ----------------------------------------------------------------------
11293 00:41:32.958651 # Ran 4 tests in 0.086s
11294 00:41:32.958734 #
11295 00:41:32.961997 # FAILED (errors=4)
11296 00:41:32.965765 not ok 2 selftests: tpm2: test_space.sh # exit=1
11297 00:41:33.309735 tpm2_test_smoke_sh pass
11298 00:41:33.313271 tpm2_test_space_sh fail
11299 00:41:33.382139 + ../../utils/send-to-lava.sh ./output/result.txt
11300 00:41:33.461806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11301 00:41:33.462603 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11303 00:41:33.519181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11304 00:41:33.519944 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11306 00:41:33.569942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11307 00:41:33.570670 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11309 00:41:33.573229 + set +x
11310 00:41:33.576420 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14173470_1.6.2.3.5>
11311 00:41:33.577168 Received signal: <ENDRUN> 1_kselftest-tpm2 14173470_1.6.2.3.5
11312 00:41:33.577555 Ending use of test pattern.
11313 00:41:33.577884 Ending test lava.1_kselftest-tpm2 (14173470_1.6.2.3.5), duration 10.51
11315 00:41:33.579779 <LAVA_TEST_RUNNER EXIT>
11316 00:41:33.580482 ok: lava_test_shell seems to have completed
11317 00:41:33.581079 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11318 00:41:33.581512 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11319 00:41:33.581943 end: 3 lava-test-retry (duration 00:00:11) [common]
11320 00:41:33.582395 start: 4 finalize (timeout 00:07:55) [common]
11321 00:41:33.582857 start: 4.1 power-off (timeout 00:00:30) [common]
11322 00:41:33.583602 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11323 00:41:33.817684 >> Command sent successfully.
11324 00:41:33.819975 Returned 0 in 0 seconds
11325 00:41:33.920348 end: 4.1 power-off (duration 00:00:00) [common]
11327 00:41:33.920721 start: 4.2 read-feedback (timeout 00:07:54) [common]
11328 00:41:33.920976 Listened to connection for namespace 'common' for up to 1s
11329 00:41:34.921852 Finalising connection for namespace 'common'
11330 00:41:34.922038 Disconnecting from shell: Finalise
11331 00:41:34.922126 / #
11332 00:41:35.022450 end: 4.2 read-feedback (duration 00:00:01) [common]
11333 00:41:35.022614 end: 4 finalize (duration 00:00:01) [common]
11334 00:41:35.022729 Cleaning after the job
11335 00:41:35.022830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/ramdisk
11336 00:41:35.025069 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/kernel
11337 00:41:35.035565 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/dtb
11338 00:41:35.035719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/nfsrootfs
11339 00:41:35.097221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173470/tftp-deploy-mz3f2d94/modules
11340 00:41:35.102760 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173470
11341 00:41:35.621791 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173470
11342 00:41:35.621975 Job finished correctly