Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 42
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 00:37:37.508412 lava-dispatcher, installed at version: 2024.03
2 00:37:37.508621 start: 0 validate
3 00:37:37.508757 Start time: 2024-06-05 00:37:37.508749+00:00 (UTC)
4 00:37:37.508880 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:37:37.509009 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:37:37.767135 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:37:37.767869 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:37:38.031329 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:37:38.032068 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:37:56.377597 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:37:56.378264 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:37:57.137680 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:37:57.138790 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:37:57.403034 validate duration: 19.89
16 00:37:57.404318 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:37:57.404902 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:37:57.405459 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:37:57.406088 Not decompressing ramdisk as can be used compressed.
20 00:37:57.406566 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 00:37:57.406955 saving as /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/ramdisk/initrd.cpio.gz
22 00:37:57.407314 total size: 5628151 (5 MB)
23 00:37:59.863137 progress 0 % (0 MB)
24 00:37:59.868370 progress 5 % (0 MB)
25 00:37:59.869960 progress 10 % (0 MB)
26 00:37:59.871410 progress 15 % (0 MB)
27 00:37:59.873051 progress 20 % (1 MB)
28 00:37:59.874532 progress 25 % (1 MB)
29 00:37:59.876151 progress 30 % (1 MB)
30 00:37:59.877755 progress 35 % (1 MB)
31 00:37:59.879176 progress 40 % (2 MB)
32 00:37:59.880810 progress 45 % (2 MB)
33 00:37:59.882305 progress 50 % (2 MB)
34 00:37:59.883896 progress 55 % (2 MB)
35 00:37:59.885489 progress 60 % (3 MB)
36 00:37:59.886912 progress 65 % (3 MB)
37 00:37:59.888502 progress 70 % (3 MB)
38 00:37:59.889922 progress 75 % (4 MB)
39 00:37:59.891502 progress 80 % (4 MB)
40 00:37:59.892929 progress 85 % (4 MB)
41 00:37:59.894525 progress 90 % (4 MB)
42 00:37:59.896007 progress 95 % (5 MB)
43 00:37:59.897406 progress 100 % (5 MB)
44 00:37:59.897607 5 MB downloaded in 2.49 s (2.16 MB/s)
45 00:37:59.897759 end: 1.1.1 http-download (duration 00:00:02) [common]
47 00:37:59.897986 end: 1.1 download-retry (duration 00:00:02) [common]
48 00:37:59.898076 start: 1.2 download-retry (timeout 00:09:58) [common]
49 00:37:59.898188 start: 1.2.1 http-download (timeout 00:09:58) [common]
50 00:37:59.898340 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:37:59.898409 saving as /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/kernel/Image
52 00:37:59.898469 total size: 54682112 (52 MB)
53 00:37:59.898529 No compression specified
54 00:37:59.899630 progress 0 % (0 MB)
55 00:37:59.913332 progress 5 % (2 MB)
56 00:37:59.926829 progress 10 % (5 MB)
57 00:37:59.940823 progress 15 % (7 MB)
58 00:37:59.954591 progress 20 % (10 MB)
59 00:37:59.968459 progress 25 % (13 MB)
60 00:37:59.982043 progress 30 % (15 MB)
61 00:37:59.995916 progress 35 % (18 MB)
62 00:38:00.009646 progress 40 % (20 MB)
63 00:38:00.023299 progress 45 % (23 MB)
64 00:38:00.037278 progress 50 % (26 MB)
65 00:38:00.051146 progress 55 % (28 MB)
66 00:38:00.064942 progress 60 % (31 MB)
67 00:38:00.078451 progress 65 % (33 MB)
68 00:38:00.092150 progress 70 % (36 MB)
69 00:38:00.105742 progress 75 % (39 MB)
70 00:38:00.119554 progress 80 % (41 MB)
71 00:38:00.133209 progress 85 % (44 MB)
72 00:38:00.147374 progress 90 % (46 MB)
73 00:38:00.160884 progress 95 % (49 MB)
74 00:38:00.174029 progress 100 % (52 MB)
75 00:38:00.174240 52 MB downloaded in 0.28 s (189.10 MB/s)
76 00:38:00.174390 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:38:00.174624 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:38:00.174709 start: 1.3 download-retry (timeout 00:09:57) [common]
80 00:38:00.174793 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 00:38:00.174928 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:38:00.174999 saving as /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/dtb/mt8192-asurada-spherion-r0.dtb
83 00:38:00.175060 total size: 47258 (0 MB)
84 00:38:00.175119 No compression specified
85 00:38:00.176217 progress 69 % (0 MB)
86 00:38:00.176488 progress 100 % (0 MB)
87 00:38:00.176639 0 MB downloaded in 0.00 s (28.59 MB/s)
88 00:38:00.176759 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:38:00.176974 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:38:00.177058 start: 1.4 download-retry (timeout 00:09:57) [common]
92 00:38:00.177139 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 00:38:00.177250 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 00:38:00.177349 saving as /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/nfsrootfs/full.rootfs.tar
95 00:38:00.177422 total size: 69067788 (65 MB)
96 00:38:00.177481 Using unxz to decompress xz
97 00:38:00.181368 progress 0 % (0 MB)
98 00:38:00.373508 progress 5 % (3 MB)
99 00:38:00.574065 progress 10 % (6 MB)
100 00:38:00.779745 progress 15 % (9 MB)
101 00:38:00.945799 progress 20 % (13 MB)
102 00:38:01.123076 progress 25 % (16 MB)
103 00:38:01.323028 progress 30 % (19 MB)
104 00:38:01.441886 progress 35 % (23 MB)
105 00:38:01.538644 progress 40 % (26 MB)
106 00:38:01.749023 progress 45 % (29 MB)
107 00:38:01.968466 progress 50 % (32 MB)
108 00:38:02.173992 progress 55 % (36 MB)
109 00:38:02.394613 progress 60 % (39 MB)
110 00:38:02.590994 progress 65 % (42 MB)
111 00:38:02.788286 progress 70 % (46 MB)
112 00:38:02.984371 progress 75 % (49 MB)
113 00:38:03.203900 progress 80 % (52 MB)
114 00:38:03.385041 progress 85 % (56 MB)
115 00:38:03.574783 progress 90 % (59 MB)
116 00:38:03.775506 progress 95 % (62 MB)
117 00:38:03.975711 progress 100 % (65 MB)
118 00:38:03.981855 65 MB downloaded in 3.80 s (17.31 MB/s)
119 00:38:03.982112 end: 1.4.1 http-download (duration 00:00:04) [common]
121 00:38:03.982380 end: 1.4 download-retry (duration 00:00:04) [common]
122 00:38:03.982471 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:38:03.982557 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:38:03.982707 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:38:03.982777 saving as /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/modules/modules.tar
126 00:38:03.982839 total size: 8605984 (8 MB)
127 00:38:03.982900 Using unxz to decompress xz
128 00:38:03.986797 progress 0 % (0 MB)
129 00:38:04.005459 progress 5 % (0 MB)
130 00:38:04.032281 progress 10 % (0 MB)
131 00:38:04.062151 progress 15 % (1 MB)
132 00:38:04.085493 progress 20 % (1 MB)
133 00:38:04.108975 progress 25 % (2 MB)
134 00:38:04.132499 progress 30 % (2 MB)
135 00:38:04.156975 progress 35 % (2 MB)
136 00:38:04.183521 progress 40 % (3 MB)
137 00:38:04.206005 progress 45 % (3 MB)
138 00:38:04.229659 progress 50 % (4 MB)
139 00:38:04.254914 progress 55 % (4 MB)
140 00:38:04.279329 progress 60 % (4 MB)
141 00:38:04.303289 progress 65 % (5 MB)
142 00:38:04.327945 progress 70 % (5 MB)
143 00:38:04.351918 progress 75 % (6 MB)
144 00:38:04.379811 progress 80 % (6 MB)
145 00:38:04.404318 progress 85 % (7 MB)
146 00:38:04.429606 progress 90 % (7 MB)
147 00:38:04.456228 progress 95 % (7 MB)
148 00:38:04.482357 progress 100 % (8 MB)
149 00:38:04.487691 8 MB downloaded in 0.50 s (16.26 MB/s)
150 00:38:04.488018 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:38:04.488435 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:38:04.488577 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:38:04.488716 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:38:06.043024 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3
156 00:38:06.043213 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:38:06.043316 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 00:38:06.043485 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7
159 00:38:06.043613 makedir: /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin
160 00:38:06.043711 makedir: /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/tests
161 00:38:06.043807 makedir: /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/results
162 00:38:06.043906 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-add-keys
163 00:38:06.044042 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-add-sources
164 00:38:06.044166 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-background-process-start
165 00:38:06.044290 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-background-process-stop
166 00:38:06.044410 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-common-functions
167 00:38:06.044533 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-echo-ipv4
168 00:38:06.044652 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-install-packages
169 00:38:06.044771 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-installed-packages
170 00:38:06.044889 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-os-build
171 00:38:06.045008 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-probe-channel
172 00:38:06.045127 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-probe-ip
173 00:38:06.045246 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-target-ip
174 00:38:06.045407 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-target-mac
175 00:38:06.045526 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-target-storage
176 00:38:06.045646 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-case
177 00:38:06.045767 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-event
178 00:38:06.045885 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-feedback
179 00:38:06.046006 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-raise
180 00:38:06.046125 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-reference
181 00:38:06.046244 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-runner
182 00:38:06.046362 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-set
183 00:38:06.046481 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-test-shell
184 00:38:06.046603 Updating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-install-packages (oe)
185 00:38:06.046748 Updating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/bin/lava-installed-packages (oe)
186 00:38:06.046864 Creating /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/environment
187 00:38:06.046956 LAVA metadata
188 00:38:06.047021 - LAVA_JOB_ID=14173474
189 00:38:06.047079 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:38:06.047176 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 00:38:06.047240 skipped lava-vland-overlay
192 00:38:06.047312 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:38:06.047388 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 00:38:06.047447 skipped lava-multinode-overlay
195 00:38:06.047516 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:38:06.047590 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 00:38:06.047660 Loading test definitions
198 00:38:06.047747 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 00:38:06.047822 Using /lava-14173474 at stage 0
200 00:38:06.048114 uuid=14173474_1.6.2.3.1 testdef=None
201 00:38:06.048246 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:38:06.048331 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 00:38:06.048807 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:38:06.049021 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 00:38:06.049651 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:38:06.049875 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 00:38:06.050479 runner path: /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/0/tests/0_lc-compliance test_uuid 14173474_1.6.2.3.1
210 00:38:06.050747 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:38:06.050952 Creating lava-test-runner.conf files
213 00:38:06.051012 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173474/lava-overlay-l281rmd7/lava-14173474/0 for stage 0
214 00:38:06.051098 - 0_lc-compliance
215 00:38:06.051194 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:38:06.051278 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 00:38:06.057211 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:38:06.057347 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 00:38:06.057445 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:38:06.057528 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:38:06.057614 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 00:38:06.220978 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:38:06.221408 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 00:38:06.221528 extracting modules file /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3
225 00:38:06.433377 extracting modules file /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173474/extract-overlay-ramdisk-zjmnn172/ramdisk
226 00:38:06.650390 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:38:06.650554 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 00:38:06.650645 [common] Applying overlay to NFS
229 00:38:06.650714 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173474/compress-overlay-g6i4nr4n/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3
230 00:38:06.657472 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:38:06.657593 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 00:38:06.657682 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:38:06.657772 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 00:38:06.657854 Building ramdisk /var/lib/lava/dispatcher/tmp/14173474/extract-overlay-ramdisk-zjmnn172/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173474/extract-overlay-ramdisk-zjmnn172/ramdisk
235 00:38:07.011335 >> 130348 blocks
236 00:38:09.016729 rename /var/lib/lava/dispatcher/tmp/14173474/extract-overlay-ramdisk-zjmnn172/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/ramdisk/ramdisk.cpio.gz
237 00:38:09.017173 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:38:09.017307 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 00:38:09.017406 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 00:38:09.017513 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/kernel/Image']
241 00:38:22.099995 Returned 0 in 13 seconds
242 00:38:22.200626 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/kernel/image.itb
243 00:38:22.584918 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:38:22.585284 output: Created: Wed Jun 5 01:38:22 2024
245 00:38:22.585401 output: Image 0 (kernel-1)
246 00:38:22.585461 output: Description:
247 00:38:22.585521 output: Created: Wed Jun 5 01:38:22 2024
248 00:38:22.585581 output: Type: Kernel Image
249 00:38:22.585641 output: Compression: lzma compressed
250 00:38:22.585699 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
251 00:38:22.585757 output: Architecture: AArch64
252 00:38:22.585815 output: OS: Linux
253 00:38:22.585873 output: Load Address: 0x00000000
254 00:38:22.585930 output: Entry Point: 0x00000000
255 00:38:22.585986 output: Hash algo: crc32
256 00:38:22.586038 output: Hash value: 4c96ec19
257 00:38:22.586092 output: Image 1 (fdt-1)
258 00:38:22.586147 output: Description: mt8192-asurada-spherion-r0
259 00:38:22.586200 output: Created: Wed Jun 5 01:38:22 2024
260 00:38:22.586256 output: Type: Flat Device Tree
261 00:38:22.586309 output: Compression: uncompressed
262 00:38:22.586360 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 00:38:22.586412 output: Architecture: AArch64
264 00:38:22.586463 output: Hash algo: crc32
265 00:38:22.586513 output: Hash value: 0f8e4d2e
266 00:38:22.586564 output: Image 2 (ramdisk-1)
267 00:38:22.586615 output: Description: unavailable
268 00:38:22.586665 output: Created: Wed Jun 5 01:38:22 2024
269 00:38:22.586717 output: Type: RAMDisk Image
270 00:38:22.586768 output: Compression: Unknown Compression
271 00:38:22.586819 output: Data Size: 18725384 Bytes = 18286.51 KiB = 17.86 MiB
272 00:38:22.586870 output: Architecture: AArch64
273 00:38:22.586920 output: OS: Linux
274 00:38:22.586971 output: Load Address: unavailable
275 00:38:22.587021 output: Entry Point: unavailable
276 00:38:22.587072 output: Hash algo: crc32
277 00:38:22.587122 output: Hash value: 663007fa
278 00:38:22.587173 output: Default Configuration: 'conf-1'
279 00:38:22.587224 output: Configuration 0 (conf-1)
280 00:38:22.587274 output: Description: mt8192-asurada-spherion-r0
281 00:38:22.587325 output: Kernel: kernel-1
282 00:38:22.587375 output: Init Ramdisk: ramdisk-1
283 00:38:22.587426 output: FDT: fdt-1
284 00:38:22.587477 output: Loadables: kernel-1
285 00:38:22.587527 output:
286 00:38:22.587724 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 00:38:22.587821 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 00:38:22.587921 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 00:38:22.588015 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 00:38:22.588095 No LXC device requested
291 00:38:22.588173 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:38:22.588257 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 00:38:22.588330 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:38:22.588395 Checking files for TFTP limit of 4294967296 bytes.
295 00:38:22.588889 end: 1 tftp-deploy (duration 00:00:25) [common]
296 00:38:22.588991 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:38:22.589080 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:38:22.589200 substitutions:
299 00:38:22.589264 - {DTB}: 14173474/tftp-deploy-ty0tk77m/dtb/mt8192-asurada-spherion-r0.dtb
300 00:38:22.589375 - {INITRD}: 14173474/tftp-deploy-ty0tk77m/ramdisk/ramdisk.cpio.gz
301 00:38:22.589434 - {KERNEL}: 14173474/tftp-deploy-ty0tk77m/kernel/Image
302 00:38:22.589490 - {LAVA_MAC}: None
303 00:38:22.589544 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3
304 00:38:22.589599 - {NFS_SERVER_IP}: 192.168.201.1
305 00:38:22.589651 - {PRESEED_CONFIG}: None
306 00:38:22.589704 - {PRESEED_LOCAL}: None
307 00:38:22.589756 - {RAMDISK}: 14173474/tftp-deploy-ty0tk77m/ramdisk/ramdisk.cpio.gz
308 00:38:22.589808 - {ROOT_PART}: None
309 00:38:22.589860 - {ROOT}: None
310 00:38:22.589912 - {SERVER_IP}: 192.168.201.1
311 00:38:22.589963 - {TEE}: None
312 00:38:22.590014 Parsed boot commands:
313 00:38:22.590065 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:38:22.590246 Parsed boot commands: tftpboot 192.168.201.1 14173474/tftp-deploy-ty0tk77m/kernel/image.itb 14173474/tftp-deploy-ty0tk77m/kernel/cmdline
315 00:38:22.590334 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:38:22.590413 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:38:22.590506 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:38:22.590587 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:38:22.590658 Not connected, no need to disconnect.
320 00:38:22.590730 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:38:22.590808 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:38:22.590876 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
323 00:38:22.594529 Setting prompt string to ['lava-test: # ']
324 00:38:22.594882 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:38:22.594988 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:38:22.595083 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:38:22.595170 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:38:22.595396 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
329 00:38:27.723789 >> Command sent successfully.
330 00:38:27.726262 Returned 0 in 5 seconds
331 00:38:27.826688 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 00:38:27.827029 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 00:38:27.827126 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 00:38:27.827214 Setting prompt string to 'Starting depthcharge on Spherion...'
336 00:38:27.827278 Changing prompt to 'Starting depthcharge on Spherion...'
337 00:38:27.827346 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 00:38:27.827731 [Enter `^Ec?' for help]
339 00:38:28.006531
340 00:38:28.006696
341 00:38:28.006764 F0: 102B 0000
342 00:38:28.006828
343 00:38:28.006891 F3: 1001 0000 [0200]
344 00:38:28.006954
345 00:38:28.009679 F3: 1001 0000
346 00:38:28.009765
347 00:38:28.009830 F7: 102D 0000
348 00:38:28.009891
349 00:38:28.013268 F1: 0000 0000
350 00:38:28.013388
351 00:38:28.013453 V0: 0000 0000 [0001]
352 00:38:28.013514
353 00:38:28.016356 00: 0007 8000
354 00:38:28.016442
355 00:38:28.016507 01: 0000 0000
356 00:38:28.016568
357 00:38:28.019554 BP: 0C00 0209 [0000]
358 00:38:28.019636
359 00:38:28.019700 G0: 1182 0000
360 00:38:28.019761
361 00:38:28.019820 EC: 0000 0021 [4000]
362 00:38:28.023645
363 00:38:28.023727 S7: 0000 0000 [0000]
364 00:38:28.023792
365 00:38:28.026823 CC: 0000 0000 [0001]
366 00:38:28.026909
367 00:38:28.026974 T0: 0000 0040 [010F]
368 00:38:28.027040
369 00:38:28.027098 Jump to BL
370 00:38:28.027154
371 00:38:28.053168
372 00:38:28.053354
373 00:38:28.060107 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 00:38:28.063231 ARM64: Exception handlers installed.
375 00:38:28.066823 ARM64: Testing exception
376 00:38:28.070129 ARM64: Done test exception
377 00:38:28.076817 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 00:38:28.086990 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 00:38:28.094289 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 00:38:28.103961 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 00:38:28.110809 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 00:38:28.120772 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 00:38:28.131625 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 00:38:28.138285 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 00:38:28.156012 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 00:38:28.159291 WDT: Last reset was cold boot
387 00:38:28.162586 SPI1(PAD0) initialized at 2873684 Hz
388 00:38:28.165940 SPI5(PAD0) initialized at 992727 Hz
389 00:38:28.169250 VBOOT: Loading verstage.
390 00:38:28.175811 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 00:38:28.179303 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 00:38:28.182534 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 00:38:28.185779 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 00:38:28.193362 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 00:38:28.199944 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 00:38:28.210919 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
397 00:38:28.211055
398 00:38:28.211124
399 00:38:28.220752 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 00:38:28.224001 ARM64: Exception handlers installed.
401 00:38:28.227568 ARM64: Testing exception
402 00:38:28.227661 ARM64: Done test exception
403 00:38:28.234061 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 00:38:28.237319 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 00:38:28.252173 Probing TPM: . done!
406 00:38:28.252354 TPM ready after 0 ms
407 00:38:28.259255 Connected to device vid:did:rid of 1ae0:0028:00
408 00:38:28.265956 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
409 00:38:28.313682 Initialized TPM device CR50 revision 0
410 00:38:28.328684 tlcl_send_startup: Startup return code is 0
411 00:38:28.328837 TPM: setup succeeded
412 00:38:28.339464 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 00:38:28.348599 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 00:38:28.358042 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 00:38:28.366875 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 00:38:28.370281 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 00:38:28.373630 in-header: 03 07 00 00 08 00 00 00
418 00:38:28.376762 in-data: aa e4 47 04 13 02 00 00
419 00:38:28.380235 Chrome EC: UHEPI supported
420 00:38:28.386974 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 00:38:28.390308 in-header: 03 95 00 00 08 00 00 00
422 00:38:28.394071 in-data: 18 20 20 08 00 00 00 00
423 00:38:28.394178 Phase 1
424 00:38:28.397478 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 00:38:28.404921 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 00:38:28.408581 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 00:38:28.412234 Recovery requested (1009000e)
428 00:38:28.421476 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 00:38:28.427838 tlcl_extend: response is 0
430 00:38:28.436755 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 00:38:28.442213 tlcl_extend: response is 0
432 00:38:28.449418 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 00:38:28.469922 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
434 00:38:28.477003 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 00:38:28.477135
436 00:38:28.477200
437 00:38:28.484396 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 00:38:28.487950 ARM64: Exception handlers installed.
439 00:38:28.491861 ARM64: Testing exception
440 00:38:28.495018 ARM64: Done test exception
441 00:38:28.514883 pmic_efuse_setting: Set efuses in 11 msecs
442 00:38:28.517903 pmwrap_interface_init: Select PMIF_VLD_RDY
443 00:38:28.524761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 00:38:28.528006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 00:38:28.534536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 00:38:28.538019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 00:38:28.544633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 00:38:28.548076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 00:38:28.551346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 00:38:28.558300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 00:38:28.561479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 00:38:28.567936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 00:38:28.571351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 00:38:28.574621 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 00:38:28.581381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 00:38:28.588388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 00:38:28.591681 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 00:38:28.598883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 00:38:28.602800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 00:38:28.609994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 00:38:28.617315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 00:38:28.621165 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 00:38:28.624995 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 00:38:28.631929 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 00:38:28.639772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 00:38:28.643205 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 00:38:28.646729 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 00:38:28.654109 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 00:38:28.657957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 00:38:28.664726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 00:38:28.668651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 00:38:28.672599 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 00:38:28.679793 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 00:38:28.683264 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 00:38:28.690642 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 00:38:28.694293 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 00:38:28.698024 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 00:38:28.705228 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 00:38:28.708791 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 00:38:28.712577 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 00:38:28.719740 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 00:38:28.723647 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 00:38:28.726738 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 00:38:28.730459 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 00:38:28.734242 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 00:38:28.741184 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 00:38:28.744893 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 00:38:28.748557 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 00:38:28.752188 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 00:38:28.755897 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 00:38:28.763609 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 00:38:28.767145 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 00:38:28.770568 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 00:38:28.777643 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 00:38:28.785167 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 00:38:28.789018 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 00:38:28.799872 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 00:38:28.807007 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 00:38:28.810778 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 00:38:28.814624 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 00:38:28.821930 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:38:28.829327 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
503 00:38:28.832205 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 00:38:28.839860 [RTC]rtc_osc_init,62: osc32con val = 0xde70
505 00:38:28.843205 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 00:38:28.852210 [RTC]rtc_get_frequency_meter,154: input=15, output=763
507 00:38:28.861703 [RTC]rtc_get_frequency_meter,154: input=23, output=948
508 00:38:28.871088 [RTC]rtc_get_frequency_meter,154: input=19, output=856
509 00:38:28.880879 [RTC]rtc_get_frequency_meter,154: input=17, output=810
510 00:38:28.890202 [RTC]rtc_get_frequency_meter,154: input=16, output=788
511 00:38:28.899747 [RTC]rtc_get_frequency_meter,154: input=16, output=787
512 00:38:28.909664 [RTC]rtc_get_frequency_meter,154: input=17, output=810
513 00:38:28.912732 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
514 00:38:28.920188 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
515 00:38:28.923982 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 00:38:28.927662 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
517 00:38:28.931440 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 00:38:28.934793 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
519 00:38:28.938158 ADC[4]: Raw value=670432 ID=5
520 00:38:28.942213 ADC[3]: Raw value=212917 ID=1
521 00:38:28.942311 RAM Code: 0x51
522 00:38:28.945631 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 00:38:28.952765 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 00:38:28.960153 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
525 00:38:28.967134 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
526 00:38:28.970878 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 00:38:28.974450 in-header: 03 07 00 00 08 00 00 00
528 00:38:28.978087 in-data: aa e4 47 04 13 02 00 00
529 00:38:28.978195 Chrome EC: UHEPI supported
530 00:38:28.985535 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 00:38:28.989087 in-header: 03 95 00 00 08 00 00 00
532 00:38:28.992541 in-data: 18 20 20 08 00 00 00 00
533 00:38:28.996407 MRC: failed to locate region type 0.
534 00:38:29.003756 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 00:38:29.003892 DRAM-K: Running full calibration
536 00:38:29.011317 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
537 00:38:29.014672 header.status = 0x0
538 00:38:29.014769 header.version = 0x6 (expected: 0x6)
539 00:38:29.018460 header.size = 0xd00 (expected: 0xd00)
540 00:38:29.021959 header.flags = 0x0
541 00:38:29.029139 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 00:38:29.045848 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
543 00:38:29.053416 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 00:38:29.056798 dram_init: ddr_geometry: 0
545 00:38:29.056899 [EMI] MDL number = 0
546 00:38:29.060495 [EMI] Get MDL freq = 0
547 00:38:29.060585 dram_init: ddr_type: 0
548 00:38:29.064122 is_discrete_lpddr4: 1
549 00:38:29.068146 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 00:38:29.068244
551 00:38:29.068310
552 00:38:29.068370 [Bian_co] ETT version 0.0.0.1
553 00:38:29.075163 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
554 00:38:29.075272
555 00:38:29.079258 dramc_set_vcore_voltage set vcore to 650000
556 00:38:29.079350 Read voltage for 800, 4
557 00:38:29.083174 Vio18 = 0
558 00:38:29.083262 Vcore = 650000
559 00:38:29.083329 Vdram = 0
560 00:38:29.083389 Vddq = 0
561 00:38:29.086757 Vmddr = 0
562 00:38:29.086843 dram_init: config_dvfs: 1
563 00:38:29.093597 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 00:38:29.097557 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 00:38:29.100870 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
566 00:38:29.104743 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
567 00:38:29.108323 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
568 00:38:29.111742 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
569 00:38:29.115428 MEM_TYPE=3, freq_sel=18
570 00:38:29.118991 sv_algorithm_assistance_LP4_1600
571 00:38:29.122545 ============ PULL DRAM RESETB DOWN ============
572 00:38:29.126558 ========== PULL DRAM RESETB DOWN end =========
573 00:38:29.130415 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 00:38:29.133729 ===================================
575 00:38:29.137277 LPDDR4 DRAM CONFIGURATION
576 00:38:29.141015 ===================================
577 00:38:29.141108 EX_ROW_EN[0] = 0x0
578 00:38:29.144582 EX_ROW_EN[1] = 0x0
579 00:38:29.144670 LP4Y_EN = 0x0
580 00:38:29.149003 WORK_FSP = 0x0
581 00:38:29.149092 WL = 0x2
582 00:38:29.152134 RL = 0x2
583 00:38:29.152218 BL = 0x2
584 00:38:29.155776 RPST = 0x0
585 00:38:29.155862 RD_PRE = 0x0
586 00:38:29.159504 WR_PRE = 0x1
587 00:38:29.159590 WR_PST = 0x0
588 00:38:29.162991 DBI_WR = 0x0
589 00:38:29.163077 DBI_RD = 0x0
590 00:38:29.166914 OTF = 0x1
591 00:38:29.167005 ===================================
592 00:38:29.170399 ===================================
593 00:38:29.174353 ANA top config
594 00:38:29.177814 ===================================
595 00:38:29.177912 DLL_ASYNC_EN = 0
596 00:38:29.181238 ALL_SLAVE_EN = 1
597 00:38:29.185069 NEW_RANK_MODE = 1
598 00:38:29.185163 DLL_IDLE_MODE = 1
599 00:38:29.188786 LP45_APHY_COMB_EN = 1
600 00:38:29.192047 TX_ODT_DIS = 1
601 00:38:29.195293 NEW_8X_MODE = 1
602 00:38:29.198659 ===================================
603 00:38:29.202104 ===================================
604 00:38:29.205257 data_rate = 1600
605 00:38:29.205393 CKR = 1
606 00:38:29.208584 DQ_P2S_RATIO = 8
607 00:38:29.211907 ===================================
608 00:38:29.215329 CA_P2S_RATIO = 8
609 00:38:29.218878 DQ_CA_OPEN = 0
610 00:38:29.222435 DQ_SEMI_OPEN = 0
611 00:38:29.222528 CA_SEMI_OPEN = 0
612 00:38:29.226544 CA_FULL_RATE = 0
613 00:38:29.230038 DQ_CKDIV4_EN = 1
614 00:38:29.233434 CA_CKDIV4_EN = 1
615 00:38:29.233526 CA_PREDIV_EN = 0
616 00:38:29.237488 PH8_DLY = 0
617 00:38:29.240347 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 00:38:29.243630 DQ_AAMCK_DIV = 4
619 00:38:29.247366 CA_AAMCK_DIV = 4
620 00:38:29.247458 CA_ADMCK_DIV = 4
621 00:38:29.250249 DQ_TRACK_CA_EN = 0
622 00:38:29.254254 CA_PICK = 800
623 00:38:29.257473 CA_MCKIO = 800
624 00:38:29.260849 MCKIO_SEMI = 0
625 00:38:29.264791 PLL_FREQ = 3068
626 00:38:29.264885 DQ_UI_PI_RATIO = 32
627 00:38:29.267824 CA_UI_PI_RATIO = 0
628 00:38:29.271257 ===================================
629 00:38:29.275042 ===================================
630 00:38:29.278570 memory_type:LPDDR4
631 00:38:29.278669 GP_NUM : 10
632 00:38:29.281968 SRAM_EN : 1
633 00:38:29.282057 MD32_EN : 0
634 00:38:29.285613 ===================================
635 00:38:29.288976 [ANA_INIT] >>>>>>>>>>>>>>
636 00:38:29.292603 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 00:38:29.295849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 00:38:29.299669 ===================================
639 00:38:29.303476 data_rate = 1600,PCW = 0X7600
640 00:38:29.303571 ===================================
641 00:38:29.307226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 00:38:29.313909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 00:38:29.320616 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:38:29.324332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 00:38:29.327355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 00:38:29.330815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:38:29.334267 [ANA_INIT] flow start
648 00:38:29.334357 [ANA_INIT] PLL >>>>>>>>
649 00:38:29.337697 [ANA_INIT] PLL <<<<<<<<
650 00:38:29.340737 [ANA_INIT] MIDPI >>>>>>>>
651 00:38:29.340823 [ANA_INIT] MIDPI <<<<<<<<
652 00:38:29.344038 [ANA_INIT] DLL >>>>>>>>
653 00:38:29.347458 [ANA_INIT] flow end
654 00:38:29.350825 ============ LP4 DIFF to SE enter ============
655 00:38:29.354168 ============ LP4 DIFF to SE exit ============
656 00:38:29.357430 [ANA_INIT] <<<<<<<<<<<<<
657 00:38:29.360680 [Flow] Enable top DCM control >>>>>
658 00:38:29.364061 [Flow] Enable top DCM control <<<<<
659 00:38:29.367348 Enable DLL master slave shuffle
660 00:38:29.370595 ==============================================================
661 00:38:29.374137 Gating Mode config
662 00:38:29.377410 ==============================================================
663 00:38:29.380789 Config description:
664 00:38:29.391099 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 00:38:29.397577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 00:38:29.401023 SELPH_MODE 0: By rank 1: By Phase
667 00:38:29.407650 ==============================================================
668 00:38:29.410951 GAT_TRACK_EN = 1
669 00:38:29.414150 RX_GATING_MODE = 2
670 00:38:29.417456 RX_GATING_TRACK_MODE = 2
671 00:38:29.420933 SELPH_MODE = 1
672 00:38:29.424275 PICG_EARLY_EN = 1
673 00:38:29.424363 VALID_LAT_VALUE = 1
674 00:38:29.430918 ==============================================================
675 00:38:29.434430 Enter into Gating configuration >>>>
676 00:38:29.437467 Exit from Gating configuration <<<<
677 00:38:29.441099 Enter into DVFS_PRE_config >>>>>
678 00:38:29.451092 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 00:38:29.454371 Exit from DVFS_PRE_config <<<<<
680 00:38:29.457697 Enter into PICG configuration >>>>
681 00:38:29.460877 Exit from PICG configuration <<<<
682 00:38:29.464097 [RX_INPUT] configuration >>>>>
683 00:38:29.467582 [RX_INPUT] configuration <<<<<
684 00:38:29.470658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 00:38:29.477546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 00:38:29.484043 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 00:38:29.490871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 00:38:29.497327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 00:38:29.500739 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 00:38:29.507585 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 00:38:29.510726 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 00:38:29.514055 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 00:38:29.517659 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 00:38:29.524206 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 00:38:29.527385 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 00:38:29.531055 ===================================
697 00:38:29.534125 LPDDR4 DRAM CONFIGURATION
698 00:38:29.537493 ===================================
699 00:38:29.537583 EX_ROW_EN[0] = 0x0
700 00:38:29.540930 EX_ROW_EN[1] = 0x0
701 00:38:29.541014 LP4Y_EN = 0x0
702 00:38:29.543983 WORK_FSP = 0x0
703 00:38:29.544068 WL = 0x2
704 00:38:29.547449 RL = 0x2
705 00:38:29.547535 BL = 0x2
706 00:38:29.550663 RPST = 0x0
707 00:38:29.550748 RD_PRE = 0x0
708 00:38:29.554251 WR_PRE = 0x1
709 00:38:29.554336 WR_PST = 0x0
710 00:38:29.557508 DBI_WR = 0x0
711 00:38:29.557592 DBI_RD = 0x0
712 00:38:29.560699 OTF = 0x1
713 00:38:29.564031 ===================================
714 00:38:29.567197 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 00:38:29.570537 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 00:38:29.577489 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 00:38:29.580995 ===================================
718 00:38:29.581091 LPDDR4 DRAM CONFIGURATION
719 00:38:29.584330 ===================================
720 00:38:29.587620 EX_ROW_EN[0] = 0x10
721 00:38:29.590605 EX_ROW_EN[1] = 0x0
722 00:38:29.590693 LP4Y_EN = 0x0
723 00:38:29.594013 WORK_FSP = 0x0
724 00:38:29.594130 WL = 0x2
725 00:38:29.597352 RL = 0x2
726 00:38:29.597438 BL = 0x2
727 00:38:29.600633 RPST = 0x0
728 00:38:29.600716 RD_PRE = 0x0
729 00:38:29.603873 WR_PRE = 0x1
730 00:38:29.603957 WR_PST = 0x0
731 00:38:29.607139 DBI_WR = 0x0
732 00:38:29.607223 DBI_RD = 0x0
733 00:38:29.610633 OTF = 0x1
734 00:38:29.613942 ===================================
735 00:38:29.620825 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 00:38:29.624189 nWR fixed to 40
737 00:38:29.624283 [ModeRegInit_LP4] CH0 RK0
738 00:38:29.627219 [ModeRegInit_LP4] CH0 RK1
739 00:38:29.630935 [ModeRegInit_LP4] CH1 RK0
740 00:38:29.634089 [ModeRegInit_LP4] CH1 RK1
741 00:38:29.634202 match AC timing 12
742 00:38:29.640552 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
743 00:38:29.644134 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 00:38:29.647278 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 00:38:29.653830 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 00:38:29.657308 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 00:38:29.657402 [EMI DOE] emi_dcm 0
748 00:38:29.663876 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 00:38:29.663967 ==
750 00:38:29.667267 Dram Type= 6, Freq= 0, CH_0, rank 0
751 00:38:29.670637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
752 00:38:29.670723 ==
753 00:38:29.677257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 00:38:29.680619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 00:38:29.690982 [CA 0] Center 37 (7~68) winsize 62
756 00:38:29.694142 [CA 1] Center 37 (7~68) winsize 62
757 00:38:29.697563 [CA 2] Center 35 (5~66) winsize 62
758 00:38:29.700669 [CA 3] Center 35 (5~66) winsize 62
759 00:38:29.704194 [CA 4] Center 34 (4~65) winsize 62
760 00:38:29.707394 [CA 5] Center 34 (3~65) winsize 63
761 00:38:29.707480
762 00:38:29.710728 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 00:38:29.710812
764 00:38:29.714043 [CATrainingPosCal] consider 1 rank data
765 00:38:29.717432 u2DelayCellTimex100 = 270/100 ps
766 00:38:29.720674 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
767 00:38:29.724191 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
768 00:38:29.730737 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
769 00:38:29.734087 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
770 00:38:29.737599 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
771 00:38:29.740944 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
772 00:38:29.741033
773 00:38:29.744181 CA PerBit enable=1, Macro0, CA PI delay=34
774 00:38:29.744267
775 00:38:29.747657 [CBTSetCACLKResult] CA Dly = 34
776 00:38:29.747744 CS Dly: 5 (0~36)
777 00:38:29.747811 ==
778 00:38:29.750816 Dram Type= 6, Freq= 0, CH_0, rank 1
779 00:38:29.757600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
780 00:38:29.757700 ==
781 00:38:29.760730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:38:29.767761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:38:29.776928 [CA 0] Center 37 (7~68) winsize 62
784 00:38:29.780012 [CA 1] Center 37 (6~68) winsize 63
785 00:38:29.783167 [CA 2] Center 35 (5~66) winsize 62
786 00:38:29.787012 [CA 3] Center 35 (5~66) winsize 62
787 00:38:29.790041 [CA 4] Center 33 (3~64) winsize 62
788 00:38:29.793190 [CA 5] Center 34 (3~65) winsize 63
789 00:38:29.793298
790 00:38:29.796536 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:38:29.796625
792 00:38:29.800233 [CATrainingPosCal] consider 2 rank data
793 00:38:29.803249 u2DelayCellTimex100 = 270/100 ps
794 00:38:29.806665 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
795 00:38:29.809911 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
796 00:38:29.816617 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
797 00:38:29.820080 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
798 00:38:29.823732 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
799 00:38:29.826659 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
800 00:38:29.826744
801 00:38:29.830054 CA PerBit enable=1, Macro0, CA PI delay=34
802 00:38:29.830139
803 00:38:29.833102 [CBTSetCACLKResult] CA Dly = 34
804 00:38:29.833187 CS Dly: 6 (0~38)
805 00:38:29.833259
806 00:38:29.836529 ----->DramcWriteLeveling(PI) begin...
807 00:38:29.840122 ==
808 00:38:29.840206 Dram Type= 6, Freq= 0, CH_0, rank 0
809 00:38:29.846719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 00:38:29.846816 ==
811 00:38:29.849875 Write leveling (Byte 0): 28 => 28
812 00:38:29.853552 Write leveling (Byte 1): 26 => 26
813 00:38:29.853639 DramcWriteLeveling(PI) end<-----
814 00:38:29.857164
815 00:38:29.857251 ==
816 00:38:29.860609 Dram Type= 6, Freq= 0, CH_0, rank 0
817 00:38:29.864331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
818 00:38:29.864422 ==
819 00:38:29.864489 [Gating] SW mode calibration
820 00:38:29.871490 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 00:38:29.878468 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 00:38:29.882048 0 6 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
823 00:38:29.885790 0 6 4 | B1->B0 | 2b2b 2727 | 1 0 | (1 0) (1 0)
824 00:38:29.892489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:38:29.896130 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:38:29.899223 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:38:29.905782 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:38:29.909103 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:38:29.912695 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:38:29.919283 0 7 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
831 00:38:29.922558 0 7 4 | B1->B0 | 3f3f 4141 | 0 0 | (0 0) (0 0)
832 00:38:29.925802 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:38:29.929089 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:38:29.935824 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:38:29.939075 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 00:38:29.942445 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 00:38:29.949005 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 00:38:29.952327 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
839 00:38:29.955695 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
840 00:38:29.962762 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
841 00:38:29.966073 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:38:29.969117 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:38:29.975741 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:38:29.979280 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:38:29.982436 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:38:29.989215 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:38:29.992360 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:38:29.995933 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:38:30.002480 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:38:30.005835 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:38:30.009150 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:38:30.015779 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 00:38:30.019070 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 00:38:30.022632 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
855 00:38:30.029187 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:38:30.029294 Total UI for P1: 0, mck2ui 16
857 00:38:30.032352 best dqsien dly found for B0: ( 0, 10, 2)
858 00:38:30.035793 Total UI for P1: 0, mck2ui 16
859 00:38:30.039511 best dqsien dly found for B1: ( 0, 10, 0)
860 00:38:30.042466 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
861 00:38:30.045871 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
862 00:38:30.049215
863 00:38:30.052590 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
864 00:38:30.056214 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
865 00:38:30.059253 [Gating] SW calibration Done
866 00:38:30.059343 ==
867 00:38:30.062603 Dram Type= 6, Freq= 0, CH_0, rank 0
868 00:38:30.066140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
869 00:38:30.066229 ==
870 00:38:30.066295 RX Vref Scan: 0
871 00:38:30.066356
872 00:38:30.069246 RX Vref 0 -> 0, step: 1
873 00:38:30.069337
874 00:38:30.072772 RX Delay -130 -> 252, step: 16
875 00:38:30.076164 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
876 00:38:30.079364 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
877 00:38:30.086090 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
878 00:38:30.089216 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
879 00:38:30.092439 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
880 00:38:30.095826 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
881 00:38:30.099251 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
882 00:38:30.106040 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
883 00:38:30.109500 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
884 00:38:30.112818 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
885 00:38:30.116134 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
886 00:38:30.119195 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
887 00:38:30.125984 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
888 00:38:30.129064 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
889 00:38:30.132699 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
890 00:38:30.136150 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
891 00:38:30.136239 ==
892 00:38:30.139201 Dram Type= 6, Freq= 0, CH_0, rank 0
893 00:38:30.145947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
894 00:38:30.146051 ==
895 00:38:30.146121 DQS Delay:
896 00:38:30.146183 DQS0 = 0, DQS1 = 0
897 00:38:30.149116 DQM Delay:
898 00:38:30.149201 DQM0 = 82, DQM1 = 76
899 00:38:30.152368 DQ Delay:
900 00:38:30.156359 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
901 00:38:30.156450 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
902 00:38:30.159068 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
903 00:38:30.165674 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
904 00:38:30.165775
905 00:38:30.165842
906 00:38:30.165904 ==
907 00:38:30.169207 Dram Type= 6, Freq= 0, CH_0, rank 0
908 00:38:30.172255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
909 00:38:30.172343 ==
910 00:38:30.172409
911 00:38:30.172469
912 00:38:30.175532 TX Vref Scan disable
913 00:38:30.175616 == TX Byte 0 ==
914 00:38:30.182190 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
915 00:38:30.185585 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
916 00:38:30.185681 == TX Byte 1 ==
917 00:38:30.192471 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
918 00:38:30.195530 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
919 00:38:30.195625 ==
920 00:38:30.199197 Dram Type= 6, Freq= 0, CH_0, rank 0
921 00:38:30.201941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
922 00:38:30.202031 ==
923 00:38:30.216059 TX Vref=22, minBit 0, minWin=27, winSum=441
924 00:38:30.219381 TX Vref=24, minBit 4, minWin=27, winSum=445
925 00:38:30.222564 TX Vref=26, minBit 2, minWin=27, winSum=446
926 00:38:30.225987 TX Vref=28, minBit 0, minWin=28, winSum=450
927 00:38:30.229310 TX Vref=30, minBit 1, minWin=28, winSum=452
928 00:38:30.232704 TX Vref=32, minBit 0, minWin=27, winSum=446
929 00:38:30.239301 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 30
930 00:38:30.239403
931 00:38:30.242567 Final TX Range 1 Vref 30
932 00:38:30.242653
933 00:38:30.242719 ==
934 00:38:30.245951 Dram Type= 6, Freq= 0, CH_0, rank 0
935 00:38:30.249635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
936 00:38:30.249726 ==
937 00:38:30.249792
938 00:38:30.249853
939 00:38:30.253231 TX Vref Scan disable
940 00:38:30.256791 == TX Byte 0 ==
941 00:38:30.259782 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
942 00:38:30.263543 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
943 00:38:30.266616 == TX Byte 1 ==
944 00:38:30.269867 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
945 00:38:30.273184 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
946 00:38:30.273274
947 00:38:30.276457 [DATLAT]
948 00:38:30.276542 Freq=800, CH0 RK0
949 00:38:30.276610
950 00:38:30.279781 DATLAT Default: 0xa
951 00:38:30.279955 0, 0xFFFF, sum = 0
952 00:38:30.283065 1, 0xFFFF, sum = 0
953 00:38:30.283152 2, 0xFFFF, sum = 0
954 00:38:30.286411 3, 0xFFFF, sum = 0
955 00:38:30.286498 4, 0xFFFF, sum = 0
956 00:38:30.289731 5, 0xFFFF, sum = 0
957 00:38:30.289817 6, 0xFFFF, sum = 0
958 00:38:30.293223 7, 0xFFFF, sum = 0
959 00:38:30.293349 8, 0x0, sum = 1
960 00:38:30.296570 9, 0x0, sum = 2
961 00:38:30.296661 10, 0x0, sum = 3
962 00:38:30.299720 11, 0x0, sum = 4
963 00:38:30.299805 best_step = 9
964 00:38:30.299869
965 00:38:30.299929 ==
966 00:38:30.303004 Dram Type= 6, Freq= 0, CH_0, rank 0
967 00:38:30.306318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
968 00:38:30.309690 ==
969 00:38:30.309780 RX Vref Scan: 1
970 00:38:30.309845
971 00:38:30.312956 Set Vref Range= 32 -> 127
972 00:38:30.313039
973 00:38:30.316453 RX Vref 32 -> 127, step: 1
974 00:38:30.316536
975 00:38:30.316601 RX Delay -95 -> 252, step: 8
976 00:38:30.316663
977 00:38:30.319901 Set Vref, RX VrefLevel [Byte0]: 32
978 00:38:30.323073 [Byte1]: 32
979 00:38:30.326717
980 00:38:30.326802 Set Vref, RX VrefLevel [Byte0]: 33
981 00:38:30.330044 [Byte1]: 33
982 00:38:30.334699
983 00:38:30.334787 Set Vref, RX VrefLevel [Byte0]: 34
984 00:38:30.337626 [Byte1]: 34
985 00:38:30.341937
986 00:38:30.342022 Set Vref, RX VrefLevel [Byte0]: 35
987 00:38:30.345308 [Byte1]: 35
988 00:38:30.349899
989 00:38:30.349989 Set Vref, RX VrefLevel [Byte0]: 36
990 00:38:30.352864 [Byte1]: 36
991 00:38:30.357362
992 00:38:30.357452 Set Vref, RX VrefLevel [Byte0]: 37
993 00:38:30.360656 [Byte1]: 37
994 00:38:30.365007
995 00:38:30.365096 Set Vref, RX VrefLevel [Byte0]: 38
996 00:38:30.368024 [Byte1]: 38
997 00:38:30.372282
998 00:38:30.372372 Set Vref, RX VrefLevel [Byte0]: 39
999 00:38:30.375571 [Byte1]: 39
1000 00:38:30.380009
1001 00:38:30.380102 Set Vref, RX VrefLevel [Byte0]: 40
1002 00:38:30.383230 [Byte1]: 40
1003 00:38:30.387746
1004 00:38:30.387874 Set Vref, RX VrefLevel [Byte0]: 41
1005 00:38:30.390968 [Byte1]: 41
1006 00:38:30.395097
1007 00:38:30.395220 Set Vref, RX VrefLevel [Byte0]: 42
1008 00:38:30.398543 [Byte1]: 42
1009 00:38:30.402652
1010 00:38:30.402744 Set Vref, RX VrefLevel [Byte0]: 43
1011 00:38:30.405993 [Byte1]: 43
1012 00:38:30.410387
1013 00:38:30.410477 Set Vref, RX VrefLevel [Byte0]: 44
1014 00:38:30.413557 [Byte1]: 44
1015 00:38:30.418115
1016 00:38:30.418206 Set Vref, RX VrefLevel [Byte0]: 45
1017 00:38:30.421139 [Byte1]: 45
1018 00:38:30.425484
1019 00:38:30.425573 Set Vref, RX VrefLevel [Byte0]: 46
1020 00:38:30.429077 [Byte1]: 46
1021 00:38:30.433072
1022 00:38:30.433160 Set Vref, RX VrefLevel [Byte0]: 47
1023 00:38:30.436430 [Byte1]: 47
1024 00:38:30.440703
1025 00:38:30.440799 Set Vref, RX VrefLevel [Byte0]: 48
1026 00:38:30.444330 [Byte1]: 48
1027 00:38:30.448313
1028 00:38:30.448400 Set Vref, RX VrefLevel [Byte0]: 49
1029 00:38:30.451519 [Byte1]: 49
1030 00:38:30.456034
1031 00:38:30.456123 Set Vref, RX VrefLevel [Byte0]: 50
1032 00:38:30.459135 [Byte1]: 50
1033 00:38:30.463430
1034 00:38:30.463519 Set Vref, RX VrefLevel [Byte0]: 51
1035 00:38:30.466724 [Byte1]: 51
1036 00:38:30.471120
1037 00:38:30.471207 Set Vref, RX VrefLevel [Byte0]: 52
1038 00:38:30.474414 [Byte1]: 52
1039 00:38:30.478654
1040 00:38:30.478741 Set Vref, RX VrefLevel [Byte0]: 53
1041 00:38:30.482030 [Byte1]: 53
1042 00:38:30.486237
1043 00:38:30.486324 Set Vref, RX VrefLevel [Byte0]: 54
1044 00:38:30.489757 [Byte1]: 54
1045 00:38:30.493897
1046 00:38:30.493985 Set Vref, RX VrefLevel [Byte0]: 55
1047 00:38:30.497047 [Byte1]: 55
1048 00:38:30.501678
1049 00:38:30.501767 Set Vref, RX VrefLevel [Byte0]: 56
1050 00:38:30.504677 [Byte1]: 56
1051 00:38:30.509060
1052 00:38:30.509146 Set Vref, RX VrefLevel [Byte0]: 57
1053 00:38:30.512292 [Byte1]: 57
1054 00:38:30.516753
1055 00:38:30.516841 Set Vref, RX VrefLevel [Byte0]: 58
1056 00:38:30.520104 [Byte1]: 58
1057 00:38:30.524714
1058 00:38:30.524806 Set Vref, RX VrefLevel [Byte0]: 59
1059 00:38:30.528136 [Byte1]: 59
1060 00:38:30.532336
1061 00:38:30.532432 Set Vref, RX VrefLevel [Byte0]: 60
1062 00:38:30.535401 [Byte1]: 60
1063 00:38:30.539711
1064 00:38:30.539803 Set Vref, RX VrefLevel [Byte0]: 61
1065 00:38:30.543068 [Byte1]: 61
1066 00:38:30.547500
1067 00:38:30.547591 Set Vref, RX VrefLevel [Byte0]: 62
1068 00:38:30.550715 [Byte1]: 62
1069 00:38:30.555003
1070 00:38:30.555095 Set Vref, RX VrefLevel [Byte0]: 63
1071 00:38:30.558462 [Byte1]: 63
1072 00:38:30.562107
1073 00:38:30.562194 Set Vref, RX VrefLevel [Byte0]: 64
1074 00:38:30.565310 [Byte1]: 64
1075 00:38:30.569776
1076 00:38:30.569864 Set Vref, RX VrefLevel [Byte0]: 65
1077 00:38:30.573148 [Byte1]: 65
1078 00:38:30.577281
1079 00:38:30.577407 Set Vref, RX VrefLevel [Byte0]: 66
1080 00:38:30.580735 [Byte1]: 66
1081 00:38:30.585031
1082 00:38:30.585147 Set Vref, RX VrefLevel [Byte0]: 67
1083 00:38:30.588076 [Byte1]: 67
1084 00:38:30.592823
1085 00:38:30.592914 Set Vref, RX VrefLevel [Byte0]: 68
1086 00:38:30.595812 [Byte1]: 68
1087 00:38:30.600246
1088 00:38:30.600337 Set Vref, RX VrefLevel [Byte0]: 69
1089 00:38:30.603333 [Byte1]: 69
1090 00:38:30.607795
1091 00:38:30.607885 Set Vref, RX VrefLevel [Byte0]: 70
1092 00:38:30.610926 [Byte1]: 70
1093 00:38:30.615507
1094 00:38:30.615595 Set Vref, RX VrefLevel [Byte0]: 71
1095 00:38:30.618663 [Byte1]: 71
1096 00:38:30.622867
1097 00:38:30.622953 Set Vref, RX VrefLevel [Byte0]: 72
1098 00:38:30.626185 [Byte1]: 72
1099 00:38:30.630514
1100 00:38:30.630603 Set Vref, RX VrefLevel [Byte0]: 73
1101 00:38:30.633854 [Byte1]: 73
1102 00:38:30.638138
1103 00:38:30.638225 Set Vref, RX VrefLevel [Byte0]: 74
1104 00:38:30.641239 [Byte1]: 74
1105 00:38:30.645654
1106 00:38:30.645744 Final RX Vref Byte 0 = 51 to rank0
1107 00:38:30.649154 Final RX Vref Byte 1 = 54 to rank0
1108 00:38:30.652228 Final RX Vref Byte 0 = 51 to rank1
1109 00:38:30.655579 Final RX Vref Byte 1 = 54 to rank1==
1110 00:38:30.658929 Dram Type= 6, Freq= 0, CH_0, rank 0
1111 00:38:30.665472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1112 00:38:30.665605 ==
1113 00:38:30.665695 DQS Delay:
1114 00:38:30.665756 DQS0 = 0, DQS1 = 0
1115 00:38:30.669170 DQM Delay:
1116 00:38:30.669277 DQM0 = 84, DQM1 = 73
1117 00:38:30.672383 DQ Delay:
1118 00:38:30.675622 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1119 00:38:30.675708 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1120 00:38:30.679235 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1121 00:38:30.682255 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1122 00:38:30.685792
1123 00:38:30.685882
1124 00:38:30.692414 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1125 00:38:30.695772 CH0 RK0: MR19=606, MR18=3535
1126 00:38:30.702420 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1127 00:38:30.702532
1128 00:38:30.705641 ----->DramcWriteLeveling(PI) begin...
1129 00:38:30.705724 ==
1130 00:38:30.709013 Dram Type= 6, Freq= 0, CH_0, rank 1
1131 00:38:30.712276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1132 00:38:30.712389 ==
1133 00:38:30.715730 Write leveling (Byte 0): 30 => 30
1134 00:38:30.719216 Write leveling (Byte 1): 30 => 30
1135 00:38:30.722457 DramcWriteLeveling(PI) end<-----
1136 00:38:30.722545
1137 00:38:30.722613 ==
1138 00:38:30.725741 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 00:38:30.729052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 00:38:30.729142 ==
1141 00:38:30.732351 [Gating] SW mode calibration
1142 00:38:30.739091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1143 00:38:30.745836 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1144 00:38:30.749078 0 6 0 | B1->B0 | 3030 3030 | 1 0 | (1 0) (0 1)
1145 00:38:30.752538 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1146 00:38:30.759192 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 00:38:30.762744 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 00:38:30.765878 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 00:38:30.772488 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 00:38:30.776016 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 00:38:30.779393 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 00:38:30.782987 0 7 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
1153 00:38:30.789252 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1154 00:38:30.792615 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1155 00:38:30.795947 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1156 00:38:30.802957 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1157 00:38:30.806149 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1158 00:38:30.809513 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1159 00:38:30.816241 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1160 00:38:30.819666 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1161 00:38:30.822759 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1162 00:38:30.829496 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1163 00:38:30.832806 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1164 00:38:30.836441 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1165 00:38:30.842913 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1166 00:38:30.846333 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1167 00:38:30.849578 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1168 00:38:30.852862 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1169 00:38:30.859640 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1170 00:38:30.863259 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1171 00:38:30.869430 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1172 00:38:30.873181 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1173 00:38:30.876126 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1174 00:38:30.879655 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1175 00:38:30.886002 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1176 00:38:30.889318 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1177 00:38:30.892924 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1178 00:38:30.896273 Total UI for P1: 0, mck2ui 16
1179 00:38:30.899323 best dqsien dly found for B0: ( 0, 10, 2)
1180 00:38:30.902657 Total UI for P1: 0, mck2ui 16
1181 00:38:30.906090 best dqsien dly found for B1: ( 0, 10, 2)
1182 00:38:30.909283 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1183 00:38:30.912661 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1184 00:38:30.912743
1185 00:38:30.919731 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1186 00:38:30.922641 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1187 00:38:30.926125 [Gating] SW calibration Done
1188 00:38:30.926210 ==
1189 00:38:30.929234 Dram Type= 6, Freq= 0, CH_0, rank 1
1190 00:38:30.932526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1191 00:38:30.932607 ==
1192 00:38:30.932670 RX Vref Scan: 0
1193 00:38:30.932729
1194 00:38:30.976786 RX Vref 0 -> 0, step: 1
1195 00:38:30.976963
1196 00:38:30.977058 RX Delay -130 -> 252, step: 16
1197 00:38:30.977146 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1198 00:38:30.977432 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1199 00:38:30.977527 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1200 00:38:30.977614 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1201 00:38:30.977717 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1202 00:38:30.977968 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1203 00:38:30.978059 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1204 00:38:30.978161 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1205 00:38:30.978247 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1206 00:38:30.996971 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1207 00:38:30.997192 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1208 00:38:30.997259 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1209 00:38:30.997542 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1210 00:38:31.000326 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1211 00:38:31.000407 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1212 00:38:31.003683 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1213 00:38:31.003766 ==
1214 00:38:31.006957 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 00:38:31.010355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1216 00:38:31.010447 ==
1217 00:38:31.013802 DQS Delay:
1218 00:38:31.013886 DQS0 = 0, DQS1 = 0
1219 00:38:31.013950 DQM Delay:
1220 00:38:31.016815 DQM0 = 81, DQM1 = 74
1221 00:38:31.016896 DQ Delay:
1222 00:38:31.020272 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1223 00:38:31.023517 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1224 00:38:31.026905 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1225 00:38:31.030450 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1226 00:38:31.030538
1227 00:38:31.030602
1228 00:38:31.030661 ==
1229 00:38:31.033760 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 00:38:31.040149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1231 00:38:31.040252 ==
1232 00:38:31.040319
1233 00:38:31.040377
1234 00:38:31.040434 TX Vref Scan disable
1235 00:38:31.043701 == TX Byte 0 ==
1236 00:38:31.047341 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1237 00:38:31.053605 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1238 00:38:31.053708 == TX Byte 1 ==
1239 00:38:31.057003 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1240 00:38:31.060279 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1241 00:38:31.063528 ==
1242 00:38:31.067007 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 00:38:31.070374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1244 00:38:31.070461 ==
1245 00:38:31.082390 TX Vref=22, minBit 0, minWin=27, winSum=448
1246 00:38:31.085675 TX Vref=24, minBit 0, minWin=28, winSum=453
1247 00:38:31.089106 TX Vref=26, minBit 0, minWin=28, winSum=454
1248 00:38:31.092488 TX Vref=28, minBit 0, minWin=28, winSum=456
1249 00:38:31.095740 TX Vref=30, minBit 2, minWin=28, winSum=459
1250 00:38:31.102672 TX Vref=32, minBit 0, minWin=28, winSum=458
1251 00:38:31.106512 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1252 00:38:31.106612
1253 00:38:31.110075 Final TX Range 1 Vref 30
1254 00:38:31.110162
1255 00:38:31.110225 ==
1256 00:38:31.113951 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 00:38:31.117719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1258 00:38:31.117816 ==
1259 00:38:31.117894
1260 00:38:31.117955
1261 00:38:31.121207 TX Vref Scan disable
1262 00:38:31.121352 == TX Byte 0 ==
1263 00:38:31.127631 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1264 00:38:31.131520 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1265 00:38:31.131614 == TX Byte 1 ==
1266 00:38:31.135001 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1267 00:38:31.141799 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1268 00:38:31.141905
1269 00:38:31.141970 [DATLAT]
1270 00:38:31.142028 Freq=800, CH0 RK1
1271 00:38:31.145006
1272 00:38:31.145088 DATLAT Default: 0x9
1273 00:38:31.148584 0, 0xFFFF, sum = 0
1274 00:38:31.148670 1, 0xFFFF, sum = 0
1275 00:38:31.151590 2, 0xFFFF, sum = 0
1276 00:38:31.151674 3, 0xFFFF, sum = 0
1277 00:38:31.155219 4, 0xFFFF, sum = 0
1278 00:38:31.155304 5, 0xFFFF, sum = 0
1279 00:38:31.158501 6, 0xFFFF, sum = 0
1280 00:38:31.158585 7, 0xFFFF, sum = 0
1281 00:38:31.161726 8, 0x0, sum = 1
1282 00:38:31.161811 9, 0x0, sum = 2
1283 00:38:31.164968 10, 0x0, sum = 3
1284 00:38:31.165052 11, 0x0, sum = 4
1285 00:38:31.165117 best_step = 9
1286 00:38:31.165177
1287 00:38:31.168562 ==
1288 00:38:31.171717 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 00:38:31.175266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1290 00:38:31.175352 ==
1291 00:38:31.175417 RX Vref Scan: 0
1292 00:38:31.175476
1293 00:38:31.178440 RX Vref 0 -> 0, step: 1
1294 00:38:31.178524
1295 00:38:31.182118 RX Delay -111 -> 252, step: 8
1296 00:38:31.185135 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1297 00:38:31.191984 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1298 00:38:31.195170 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1299 00:38:31.198418 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1300 00:38:31.201789 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1301 00:38:31.205056 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1302 00:38:31.208454 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1303 00:38:31.215241 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1304 00:38:31.218545 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1305 00:38:31.221591 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1306 00:38:31.225162 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1307 00:38:31.231503 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1308 00:38:31.234834 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1309 00:38:31.238434 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1310 00:38:31.241457 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1311 00:38:31.244938 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1312 00:38:31.245025 ==
1313 00:38:31.248316 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 00:38:31.254860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1315 00:38:31.254956 ==
1316 00:38:31.255024 DQS Delay:
1317 00:38:31.258090 DQS0 = 0, DQS1 = 0
1318 00:38:31.258173 DQM Delay:
1319 00:38:31.261555 DQM0 = 85, DQM1 = 73
1320 00:38:31.261638 DQ Delay:
1321 00:38:31.265181 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =80
1322 00:38:31.268310 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1323 00:38:31.271514 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1324 00:38:31.274984 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1325 00:38:31.275070
1326 00:38:31.275134
1327 00:38:31.281540 [DQSOSCAuto] RK1, (LSB)MR18= 0x4646, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1328 00:38:31.285052 CH0 RK1: MR19=606, MR18=4646
1329 00:38:31.291639 CH0_RK1: MR19=0x606, MR18=0x4646, DQSOSC=392, MR23=63, INC=96, DEC=64
1330 00:38:31.294781 [RxdqsGatingPostProcess] freq 800
1331 00:38:31.298242 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1332 00:38:31.301576 Pre-setting of DQS Precalculation
1333 00:38:31.308144 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1334 00:38:31.308274 ==
1335 00:38:31.311410 Dram Type= 6, Freq= 0, CH_1, rank 0
1336 00:38:31.314760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1337 00:38:31.314846 ==
1338 00:38:31.321509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1339 00:38:31.325520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1340 00:38:31.335279 [CA 0] Center 37 (6~68) winsize 63
1341 00:38:31.338752 [CA 1] Center 37 (6~68) winsize 63
1342 00:38:31.341869 [CA 2] Center 34 (4~65) winsize 62
1343 00:38:31.345070 [CA 3] Center 34 (4~65) winsize 62
1344 00:38:31.348610 [CA 4] Center 33 (3~64) winsize 62
1345 00:38:31.351994 [CA 5] Center 33 (3~64) winsize 62
1346 00:38:31.352104
1347 00:38:31.355106 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1348 00:38:31.355189
1349 00:38:31.358668 [CATrainingPosCal] consider 1 rank data
1350 00:38:31.361826 u2DelayCellTimex100 = 270/100 ps
1351 00:38:31.364939 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1352 00:38:31.368433 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1353 00:38:31.375195 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1354 00:38:31.378412 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1355 00:38:31.381655 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1356 00:38:31.385253 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1357 00:38:31.385349
1358 00:38:31.388240 CA PerBit enable=1, Macro0, CA PI delay=33
1359 00:38:31.388321
1360 00:38:31.391638 [CBTSetCACLKResult] CA Dly = 33
1361 00:38:31.391720 CS Dly: 5 (0~36)
1362 00:38:31.395227 ==
1363 00:38:31.395308 Dram Type= 6, Freq= 0, CH_1, rank 1
1364 00:38:31.401677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 00:38:31.401782 ==
1366 00:38:31.404887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1367 00:38:31.411599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1368 00:38:31.421089 [CA 0] Center 36 (6~67) winsize 62
1369 00:38:31.424308 [CA 1] Center 37 (6~68) winsize 63
1370 00:38:31.427710 [CA 2] Center 34 (4~65) winsize 62
1371 00:38:31.431043 [CA 3] Center 34 (4~65) winsize 62
1372 00:38:31.434188 [CA 4] Center 33 (3~64) winsize 62
1373 00:38:31.437757 [CA 5] Center 33 (3~64) winsize 62
1374 00:38:31.437842
1375 00:38:31.441116 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1376 00:38:31.441216
1377 00:38:31.444284 [CATrainingPosCal] consider 2 rank data
1378 00:38:31.447545 u2DelayCellTimex100 = 270/100 ps
1379 00:38:31.450825 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1380 00:38:31.454304 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1381 00:38:31.460857 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1382 00:38:31.464387 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 00:38:31.467614 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1384 00:38:31.470918 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1385 00:38:31.471001
1386 00:38:31.474230 CA PerBit enable=1, Macro0, CA PI delay=33
1387 00:38:31.474312
1388 00:38:31.477546 [CBTSetCACLKResult] CA Dly = 33
1389 00:38:31.477627 CS Dly: 5 (0~36)
1390 00:38:31.477691
1391 00:38:31.480815 ----->DramcWriteLeveling(PI) begin...
1392 00:38:31.484197 ==
1393 00:38:31.487614 Dram Type= 6, Freq= 0, CH_1, rank 0
1394 00:38:31.490775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1395 00:38:31.490861 ==
1396 00:38:31.494024 Write leveling (Byte 0): 24 => 24
1397 00:38:31.497615 Write leveling (Byte 1): 23 => 23
1398 00:38:31.500700 DramcWriteLeveling(PI) end<-----
1399 00:38:31.500787
1400 00:38:31.500851 ==
1401 00:38:31.504028 Dram Type= 6, Freq= 0, CH_1, rank 0
1402 00:38:31.507541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1403 00:38:31.507625 ==
1404 00:38:31.510733 [Gating] SW mode calibration
1405 00:38:31.517415 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1406 00:38:31.520850 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1407 00:38:31.528010 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (1 0)
1408 00:38:31.531057 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1409 00:38:31.534174 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1410 00:38:31.540821 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1411 00:38:31.544054 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1412 00:38:31.547421 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1413 00:38:31.554088 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1414 00:38:31.557531 0 6 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1415 00:38:31.560704 0 7 0 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
1416 00:38:31.567637 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1417 00:38:31.570946 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1418 00:38:31.574206 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1419 00:38:31.580914 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1420 00:38:31.584160 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1421 00:38:31.587600 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1422 00:38:31.594378 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1423 00:38:31.597718 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1424 00:38:31.600807 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1425 00:38:31.604233 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1426 00:38:31.610790 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1427 00:38:31.614102 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1428 00:38:31.617616 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1429 00:38:31.624163 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1430 00:38:31.627607 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1431 00:38:31.630920 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1432 00:38:31.637549 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1433 00:38:31.640865 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1434 00:38:31.644222 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1435 00:38:31.650740 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1436 00:38:31.654170 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1437 00:38:31.657349 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1438 00:38:31.664097 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1439 00:38:31.667558 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1440 00:38:31.670723 Total UI for P1: 0, mck2ui 16
1441 00:38:31.674205 best dqsien dly found for B0: ( 0, 9, 28)
1442 00:38:31.677576 Total UI for P1: 0, mck2ui 16
1443 00:38:31.680975 best dqsien dly found for B1: ( 0, 9, 30)
1444 00:38:31.684446 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1445 00:38:31.687479 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1446 00:38:31.687566
1447 00:38:31.690689 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1448 00:38:31.694172 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1449 00:38:31.697224 [Gating] SW calibration Done
1450 00:38:31.697376 ==
1451 00:38:31.700840 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 00:38:31.704341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1453 00:38:31.707442 ==
1454 00:38:31.707529 RX Vref Scan: 0
1455 00:38:31.707593
1456 00:38:31.710614 RX Vref 0 -> 0, step: 1
1457 00:38:31.710697
1458 00:38:31.713801 RX Delay -130 -> 252, step: 16
1459 00:38:31.717221 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1460 00:38:31.720780 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1461 00:38:31.723935 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1462 00:38:31.727172 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1463 00:38:31.733721 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1464 00:38:31.737207 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1465 00:38:31.740497 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1466 00:38:31.743897 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1467 00:38:31.747031 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1468 00:38:31.753884 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1469 00:38:31.757179 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1470 00:38:31.760445 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1471 00:38:31.763857 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1472 00:38:31.767435 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1473 00:38:31.771273 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1474 00:38:31.778871 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1475 00:38:31.779008 ==
1476 00:38:31.779107 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 00:38:31.782687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1478 00:38:31.786154 ==
1479 00:38:31.786248 DQS Delay:
1480 00:38:31.786314 DQS0 = 0, DQS1 = 0
1481 00:38:31.790186 DQM Delay:
1482 00:38:31.790273 DQM0 = 81, DQM1 = 73
1483 00:38:31.790337 DQ Delay:
1484 00:38:31.793762 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1485 00:38:31.797500 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1486 00:38:31.801072 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1487 00:38:31.804753 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1488 00:38:31.804851
1489 00:38:31.804916
1490 00:38:31.804975 ==
1491 00:38:31.807796 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 00:38:31.811332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1493 00:38:31.811417 ==
1494 00:38:31.811482
1495 00:38:31.814714
1496 00:38:31.814795 TX Vref Scan disable
1497 00:38:31.817751 == TX Byte 0 ==
1498 00:38:31.821246 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1499 00:38:31.824632 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1500 00:38:31.827765 == TX Byte 1 ==
1501 00:38:31.831581 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1502 00:38:31.834566 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1503 00:38:31.834654 ==
1504 00:38:31.837858 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 00:38:31.844324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1506 00:38:31.844422 ==
1507 00:38:31.855969 TX Vref=22, minBit 9, minWin=27, winSum=448
1508 00:38:31.859253 TX Vref=24, minBit 0, minWin=28, winSum=451
1509 00:38:31.862891 TX Vref=26, minBit 0, minWin=28, winSum=454
1510 00:38:31.866154 TX Vref=28, minBit 0, minWin=28, winSum=457
1511 00:38:31.869416 TX Vref=30, minBit 0, minWin=28, winSum=460
1512 00:38:31.872712 TX Vref=32, minBit 3, minWin=27, winSum=453
1513 00:38:31.879334 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1514 00:38:31.879442
1515 00:38:31.882818 Final TX Range 1 Vref 30
1516 00:38:31.882904
1517 00:38:31.882968 ==
1518 00:38:31.885985 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 00:38:31.889519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 00:38:31.889607 ==
1521 00:38:31.889672
1522 00:38:31.889730
1523 00:38:31.892757 TX Vref Scan disable
1524 00:38:31.895912 == TX Byte 0 ==
1525 00:38:31.899321 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1526 00:38:31.902889 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1527 00:38:31.905986 == TX Byte 1 ==
1528 00:38:31.909330 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1529 00:38:31.912609 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1530 00:38:31.912695
1531 00:38:31.916186 [DATLAT]
1532 00:38:31.916269 Freq=800, CH1 RK0
1533 00:38:31.916333
1534 00:38:31.919426 DATLAT Default: 0xa
1535 00:38:31.919508 0, 0xFFFF, sum = 0
1536 00:38:31.922965 1, 0xFFFF, sum = 0
1537 00:38:31.923049 2, 0xFFFF, sum = 0
1538 00:38:31.926001 3, 0xFFFF, sum = 0
1539 00:38:31.926085 4, 0xFFFF, sum = 0
1540 00:38:31.929474 5, 0xFFFF, sum = 0
1541 00:38:31.929560 6, 0xFFFF, sum = 0
1542 00:38:31.932724 7, 0xFFFF, sum = 0
1543 00:38:31.932807 8, 0x0, sum = 1
1544 00:38:31.935978 9, 0x0, sum = 2
1545 00:38:31.936063 10, 0x0, sum = 3
1546 00:38:31.939362 11, 0x0, sum = 4
1547 00:38:31.939445 best_step = 9
1548 00:38:31.939508
1549 00:38:31.939566 ==
1550 00:38:31.942812 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 00:38:31.949620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1552 00:38:31.949724 ==
1553 00:38:31.949790 RX Vref Scan: 1
1554 00:38:31.949850
1555 00:38:31.952630 Set Vref Range= 32 -> 127
1556 00:38:31.952712
1557 00:38:31.955924 RX Vref 32 -> 127, step: 1
1558 00:38:31.956008
1559 00:38:31.956073 RX Delay -111 -> 252, step: 8
1560 00:38:31.959347
1561 00:38:31.959428 Set Vref, RX VrefLevel [Byte0]: 32
1562 00:38:31.962638 [Byte1]: 32
1563 00:38:31.967162
1564 00:38:31.967253 Set Vref, RX VrefLevel [Byte0]: 33
1565 00:38:31.970175 [Byte1]: 33
1566 00:38:31.974379
1567 00:38:31.974468 Set Vref, RX VrefLevel [Byte0]: 34
1568 00:38:31.977786 [Byte1]: 34
1569 00:38:31.982271
1570 00:38:31.982360 Set Vref, RX VrefLevel [Byte0]: 35
1571 00:38:31.985266 [Byte1]: 35
1572 00:38:31.989770
1573 00:38:31.989856 Set Vref, RX VrefLevel [Byte0]: 36
1574 00:38:31.993201 [Byte1]: 36
1575 00:38:31.997328
1576 00:38:31.997431 Set Vref, RX VrefLevel [Byte0]: 37
1577 00:38:32.000668 [Byte1]: 37
1578 00:38:32.005169
1579 00:38:32.005259 Set Vref, RX VrefLevel [Byte0]: 38
1580 00:38:32.008259 [Byte1]: 38
1581 00:38:32.012663
1582 00:38:32.012750 Set Vref, RX VrefLevel [Byte0]: 39
1583 00:38:32.015921 [Byte1]: 39
1584 00:38:32.020391
1585 00:38:32.020476 Set Vref, RX VrefLevel [Byte0]: 40
1586 00:38:32.023665 [Byte1]: 40
1587 00:38:32.028016
1588 00:38:32.028106 Set Vref, RX VrefLevel [Byte0]: 41
1589 00:38:32.031307 [Byte1]: 41
1590 00:38:32.035925
1591 00:38:32.036020 Set Vref, RX VrefLevel [Byte0]: 42
1592 00:38:32.038906 [Byte1]: 42
1593 00:38:32.043184
1594 00:38:32.043268 Set Vref, RX VrefLevel [Byte0]: 43
1595 00:38:32.046532 [Byte1]: 43
1596 00:38:32.051230
1597 00:38:32.051318 Set Vref, RX VrefLevel [Byte0]: 44
1598 00:38:32.054116 [Byte1]: 44
1599 00:38:32.058843
1600 00:38:32.058932 Set Vref, RX VrefLevel [Byte0]: 45
1601 00:38:32.061928 [Byte1]: 45
1602 00:38:32.066339
1603 00:38:32.066427 Set Vref, RX VrefLevel [Byte0]: 46
1604 00:38:32.069910 [Byte1]: 46
1605 00:38:32.073720
1606 00:38:32.073890 Set Vref, RX VrefLevel [Byte0]: 47
1607 00:38:32.077247 [Byte1]: 47
1608 00:38:32.081856
1609 00:38:32.081946 Set Vref, RX VrefLevel [Byte0]: 48
1610 00:38:32.084722 [Byte1]: 48
1611 00:38:32.089099
1612 00:38:32.089184 Set Vref, RX VrefLevel [Byte0]: 49
1613 00:38:32.092330 [Byte1]: 49
1614 00:38:32.096658
1615 00:38:32.096746 Set Vref, RX VrefLevel [Byte0]: 50
1616 00:38:32.099926 [Byte1]: 50
1617 00:38:32.104453
1618 00:38:32.104545 Set Vref, RX VrefLevel [Byte0]: 51
1619 00:38:32.107630 [Byte1]: 51
1620 00:38:32.112106
1621 00:38:32.112192 Set Vref, RX VrefLevel [Byte0]: 52
1622 00:38:32.115438 [Byte1]: 52
1623 00:38:32.119855
1624 00:38:32.119941 Set Vref, RX VrefLevel [Byte0]: 53
1625 00:38:32.123212 [Byte1]: 53
1626 00:38:32.127457
1627 00:38:32.127546 Set Vref, RX VrefLevel [Byte0]: 54
1628 00:38:32.130698 [Byte1]: 54
1629 00:38:32.135041
1630 00:38:32.135127 Set Vref, RX VrefLevel [Byte0]: 55
1631 00:38:32.138353 [Byte1]: 55
1632 00:38:32.142746
1633 00:38:32.142834 Set Vref, RX VrefLevel [Byte0]: 56
1634 00:38:32.146141 [Byte1]: 56
1635 00:38:32.150483
1636 00:38:32.150572 Set Vref, RX VrefLevel [Byte0]: 57
1637 00:38:32.153544 [Byte1]: 57
1638 00:38:32.158247
1639 00:38:32.158338 Set Vref, RX VrefLevel [Byte0]: 58
1640 00:38:32.161165 [Byte1]: 58
1641 00:38:32.165692
1642 00:38:32.165781 Set Vref, RX VrefLevel [Byte0]: 59
1643 00:38:32.168945 [Byte1]: 59
1644 00:38:32.173488
1645 00:38:32.173575 Set Vref, RX VrefLevel [Byte0]: 60
1646 00:38:32.176684 [Byte1]: 60
1647 00:38:32.181139
1648 00:38:32.181232 Set Vref, RX VrefLevel [Byte0]: 61
1649 00:38:32.184067 [Byte1]: 61
1650 00:38:32.188708
1651 00:38:32.188797 Set Vref, RX VrefLevel [Byte0]: 62
1652 00:38:32.191825 [Byte1]: 62
1653 00:38:32.196179
1654 00:38:32.196266 Set Vref, RX VrefLevel [Byte0]: 63
1655 00:38:32.199673 [Byte1]: 63
1656 00:38:32.204066
1657 00:38:32.204162 Set Vref, RX VrefLevel [Byte0]: 64
1658 00:38:32.207325 [Byte1]: 64
1659 00:38:32.211463
1660 00:38:32.211552 Set Vref, RX VrefLevel [Byte0]: 65
1661 00:38:32.215050 [Byte1]: 65
1662 00:38:32.219520
1663 00:38:32.219606 Set Vref, RX VrefLevel [Byte0]: 66
1664 00:38:32.222565 [Byte1]: 66
1665 00:38:32.226702
1666 00:38:32.226788 Set Vref, RX VrefLevel [Byte0]: 67
1667 00:38:32.230038 [Byte1]: 67
1668 00:38:32.234452
1669 00:38:32.234539 Set Vref, RX VrefLevel [Byte0]: 68
1670 00:38:32.237698 [Byte1]: 68
1671 00:38:32.242014
1672 00:38:32.242100 Set Vref, RX VrefLevel [Byte0]: 69
1673 00:38:32.245275 [Byte1]: 69
1674 00:38:32.249702
1675 00:38:32.249789 Set Vref, RX VrefLevel [Byte0]: 70
1676 00:38:32.253179 [Byte1]: 70
1677 00:38:32.257574
1678 00:38:32.257663 Set Vref, RX VrefLevel [Byte0]: 71
1679 00:38:32.260639 [Byte1]: 71
1680 00:38:32.264957
1681 00:38:32.265044 Set Vref, RX VrefLevel [Byte0]: 72
1682 00:38:32.268359 [Byte1]: 72
1683 00:38:32.272683
1684 00:38:32.272770 Set Vref, RX VrefLevel [Byte0]: 73
1685 00:38:32.276016 [Byte1]: 73
1686 00:38:32.280470
1687 00:38:32.280560 Set Vref, RX VrefLevel [Byte0]: 74
1688 00:38:32.283521 [Byte1]: 74
1689 00:38:32.288112
1690 00:38:32.288203 Set Vref, RX VrefLevel [Byte0]: 75
1691 00:38:32.291229 [Byte1]: 75
1692 00:38:32.295643
1693 00:38:32.295733 Set Vref, RX VrefLevel [Byte0]: 76
1694 00:38:32.298873 [Byte1]: 76
1695 00:38:32.303263
1696 00:38:32.303355 Set Vref, RX VrefLevel [Byte0]: 77
1697 00:38:32.306818 [Byte1]: 77
1698 00:38:32.310816
1699 00:38:32.310904 Set Vref, RX VrefLevel [Byte0]: 78
1700 00:38:32.314240 [Byte1]: 78
1701 00:38:32.318448
1702 00:38:32.318536 Set Vref, RX VrefLevel [Byte0]: 79
1703 00:38:32.321840 [Byte1]: 79
1704 00:38:32.326362
1705 00:38:32.326449 Final RX Vref Byte 0 = 60 to rank0
1706 00:38:32.329419 Final RX Vref Byte 1 = 57 to rank0
1707 00:38:32.332873 Final RX Vref Byte 0 = 60 to rank1
1708 00:38:32.336300 Final RX Vref Byte 1 = 57 to rank1==
1709 00:38:32.339673 Dram Type= 6, Freq= 0, CH_1, rank 0
1710 00:38:32.346558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1711 00:38:32.346640 ==
1712 00:38:32.346705 DQS Delay:
1713 00:38:32.346764 DQS0 = 0, DQS1 = 0
1714 00:38:32.350062 DQM Delay:
1715 00:38:32.350143 DQM0 = 81, DQM1 = 74
1716 00:38:32.350207 DQ Delay:
1717 00:38:32.353423 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1718 00:38:32.357011 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1719 00:38:32.360303 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1720 00:38:32.363480 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1721 00:38:32.363562
1722 00:38:32.363626
1723 00:38:32.373329 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1724 00:38:32.376726 CH1 RK0: MR19=606, MR18=4C4C
1725 00:38:32.380303 CH1_RK0: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1726 00:38:32.380390
1727 00:38:32.383492 ----->DramcWriteLeveling(PI) begin...
1728 00:38:32.386930 ==
1729 00:38:32.390324 Dram Type= 6, Freq= 0, CH_1, rank 1
1730 00:38:32.393633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1731 00:38:32.393715 ==
1732 00:38:32.397151 Write leveling (Byte 0): 24 => 24
1733 00:38:32.400545 Write leveling (Byte 1): 27 => 27
1734 00:38:32.403692 DramcWriteLeveling(PI) end<-----
1735 00:38:32.403774
1736 00:38:32.403838 ==
1737 00:38:32.406886 Dram Type= 6, Freq= 0, CH_1, rank 1
1738 00:38:32.410540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1739 00:38:32.410622 ==
1740 00:38:32.413634 [Gating] SW mode calibration
1741 00:38:32.420332 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1742 00:38:32.423653 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1743 00:38:32.430249 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1744 00:38:32.433558 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1745 00:38:32.436828 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1746 00:38:32.443547 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1747 00:38:32.446863 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1748 00:38:32.450319 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1749 00:38:32.456774 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1750 00:38:32.460329 0 6 28 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
1751 00:38:32.463650 0 7 0 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
1752 00:38:32.470175 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1753 00:38:32.473679 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1754 00:38:32.476804 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1755 00:38:32.483420 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1756 00:38:32.486870 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1757 00:38:32.490200 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1758 00:38:32.496905 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1759 00:38:32.500136 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1760 00:38:32.503541 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1761 00:38:32.510340 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1762 00:38:32.513670 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1763 00:38:32.516738 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1764 00:38:32.523368 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1765 00:38:32.526626 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1766 00:38:32.530072 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1767 00:38:32.536751 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1768 00:38:32.540045 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1769 00:38:32.543256 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1770 00:38:32.546860 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1771 00:38:32.553560 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1772 00:38:32.557093 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1773 00:38:32.560154 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1774 00:38:32.566816 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1775 00:38:32.570144 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1776 00:38:32.573525 Total UI for P1: 0, mck2ui 16
1777 00:38:32.577065 best dqsien dly found for B0: ( 0, 9, 26)
1778 00:38:32.580254 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1779 00:38:32.583911 Total UI for P1: 0, mck2ui 16
1780 00:38:32.586753 best dqsien dly found for B1: ( 0, 9, 30)
1781 00:38:32.590081 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1782 00:38:32.593507 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1783 00:38:32.593587
1784 00:38:32.600188 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1785 00:38:32.603478 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1786 00:38:32.606638 [Gating] SW calibration Done
1787 00:38:32.606751 ==
1788 00:38:32.609875 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 00:38:32.613483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1790 00:38:32.613565 ==
1791 00:38:32.613627 RX Vref Scan: 0
1792 00:38:32.613685
1793 00:38:32.616538 RX Vref 0 -> 0, step: 1
1794 00:38:32.616617
1795 00:38:32.619905 RX Delay -130 -> 252, step: 16
1796 00:38:32.623158 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1797 00:38:32.626582 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1798 00:38:32.633135 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1799 00:38:32.636804 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1800 00:38:32.639751 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1801 00:38:32.643069 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1802 00:38:32.646536 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1803 00:38:32.653165 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1804 00:38:32.656307 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1805 00:38:32.659781 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1806 00:38:32.662980 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1807 00:38:32.666467 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1808 00:38:32.673248 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1809 00:38:32.676557 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1810 00:38:32.679829 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1811 00:38:32.683034 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1812 00:38:32.683115 ==
1813 00:38:32.686587 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 00:38:32.693097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1815 00:38:32.693178 ==
1816 00:38:32.693242 DQS Delay:
1817 00:38:32.693309 DQS0 = 0, DQS1 = 0
1818 00:38:32.696507 DQM Delay:
1819 00:38:32.696587 DQM0 = 85, DQM1 = 74
1820 00:38:32.700002 DQ Delay:
1821 00:38:32.703183 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1822 00:38:32.703265 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1823 00:38:32.706630 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1824 00:38:32.713150 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1825 00:38:32.713231
1826 00:38:32.713301
1827 00:38:32.713390 ==
1828 00:38:32.716628 Dram Type= 6, Freq= 0, CH_1, rank 1
1829 00:38:32.719935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1830 00:38:32.720016 ==
1831 00:38:32.720080
1832 00:38:32.720138
1833 00:38:32.723116 TX Vref Scan disable
1834 00:38:32.723196 == TX Byte 0 ==
1835 00:38:32.730007 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1836 00:38:32.733226 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1837 00:38:32.733346 == TX Byte 1 ==
1838 00:38:32.739910 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1839 00:38:32.743230 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1840 00:38:32.743310 ==
1841 00:38:32.746634 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 00:38:32.749656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 00:38:32.749737 ==
1844 00:38:32.763706 TX Vref=22, minBit 8, minWin=27, winSum=450
1845 00:38:32.766915 TX Vref=24, minBit 8, minWin=27, winSum=451
1846 00:38:32.770397 TX Vref=26, minBit 0, minWin=28, winSum=455
1847 00:38:32.773580 TX Vref=28, minBit 9, minWin=27, winSum=457
1848 00:38:32.776910 TX Vref=30, minBit 0, minWin=28, winSum=458
1849 00:38:32.780554 TX Vref=32, minBit 0, minWin=28, winSum=456
1850 00:38:32.787012 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1851 00:38:32.787094
1852 00:38:32.790429 Final TX Range 1 Vref 30
1853 00:38:32.790510
1854 00:38:32.790573 ==
1855 00:38:32.793609 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 00:38:32.796881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 00:38:32.796962 ==
1858 00:38:32.797026
1859 00:38:32.800817
1860 00:38:32.800898 TX Vref Scan disable
1861 00:38:32.803761 == TX Byte 0 ==
1862 00:38:32.807284 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1863 00:38:32.810369 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1864 00:38:32.813556 == TX Byte 1 ==
1865 00:38:32.817045 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1866 00:38:32.823560 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1867 00:38:32.823641
1868 00:38:32.823704 [DATLAT]
1869 00:38:32.823763 Freq=800, CH1 RK1
1870 00:38:32.823822
1871 00:38:32.826979 DATLAT Default: 0x9
1872 00:38:32.827059 0, 0xFFFF, sum = 0
1873 00:38:32.830258 1, 0xFFFF, sum = 0
1874 00:38:32.830339 2, 0xFFFF, sum = 0
1875 00:38:32.833545 3, 0xFFFF, sum = 0
1876 00:38:32.836919 4, 0xFFFF, sum = 0
1877 00:38:32.837019 5, 0xFFFF, sum = 0
1878 00:38:32.840179 6, 0xFFFF, sum = 0
1879 00:38:32.840261 7, 0xFFFF, sum = 0
1880 00:38:32.840326 8, 0x0, sum = 1
1881 00:38:32.843817 9, 0x0, sum = 2
1882 00:38:32.843898 10, 0x0, sum = 3
1883 00:38:32.847179 11, 0x0, sum = 4
1884 00:38:32.847260 best_step = 9
1885 00:38:32.847323
1886 00:38:32.847381 ==
1887 00:38:32.850571 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 00:38:32.857032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1889 00:38:32.857113 ==
1890 00:38:32.857177 RX Vref Scan: 0
1891 00:38:32.857238
1892 00:38:32.860475 RX Vref 0 -> 0, step: 1
1893 00:38:32.860555
1894 00:38:32.863521 RX Delay -111 -> 252, step: 8
1895 00:38:32.866957 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1896 00:38:32.870130 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1897 00:38:32.877039 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1898 00:38:32.880200 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1899 00:38:32.883632 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1900 00:38:32.886737 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1901 00:38:32.890030 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1902 00:38:32.896831 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1903 00:38:32.899989 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1904 00:38:32.903364 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1905 00:38:32.906798 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1906 00:38:32.909992 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1907 00:38:32.916986 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1908 00:38:32.920160 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1909 00:38:32.923677 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1910 00:38:32.926743 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1911 00:38:32.926825 ==
1912 00:38:32.930146 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 00:38:32.933307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1914 00:38:32.936644 ==
1915 00:38:32.936724 DQS Delay:
1916 00:38:32.936787 DQS0 = 0, DQS1 = 0
1917 00:38:32.940158 DQM Delay:
1918 00:38:32.940238 DQM0 = 84, DQM1 = 74
1919 00:38:32.943562 DQ Delay:
1920 00:38:32.947071 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =80
1921 00:38:32.947152 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1922 00:38:32.950042 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1923 00:38:32.953222 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1924 00:38:32.956697
1925 00:38:32.956777
1926 00:38:32.963264 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1927 00:38:32.966670 CH1 RK1: MR19=606, MR18=3737
1928 00:38:32.973418 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1929 00:38:32.976568 [RxdqsGatingPostProcess] freq 800
1930 00:38:32.979758 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1931 00:38:32.983100 Pre-setting of DQS Precalculation
1932 00:38:32.989916 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1933 00:38:32.996413 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1934 00:38:33.003221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1935 00:38:33.003316
1936 00:38:33.003381
1937 00:38:33.006339 [Calibration Summary] 1600 Mbps
1938 00:38:33.006420 CH 0, Rank 0
1939 00:38:33.009641 SW Impedance : PASS
1940 00:38:33.012755 DUTY Scan : NO K
1941 00:38:33.012835 ZQ Calibration : PASS
1942 00:38:33.016218 Jitter Meter : NO K
1943 00:38:33.019501 CBT Training : PASS
1944 00:38:33.019582 Write leveling : PASS
1945 00:38:33.022906 RX DQS gating : PASS
1946 00:38:33.022987 RX DQ/DQS(RDDQC) : PASS
1947 00:38:33.026168 TX DQ/DQS : PASS
1948 00:38:33.029456 RX DATLAT : PASS
1949 00:38:33.029538 RX DQ/DQS(Engine): PASS
1950 00:38:33.032851 TX OE : NO K
1951 00:38:33.032932 All Pass.
1952 00:38:33.032996
1953 00:38:33.036066 CH 0, Rank 1
1954 00:38:33.036147 SW Impedance : PASS
1955 00:38:33.039441 DUTY Scan : NO K
1956 00:38:33.043086 ZQ Calibration : PASS
1957 00:38:33.043167 Jitter Meter : NO K
1958 00:38:33.046257 CBT Training : PASS
1959 00:38:33.049312 Write leveling : PASS
1960 00:38:33.049408 RX DQS gating : PASS
1961 00:38:33.052694 RX DQ/DQS(RDDQC) : PASS
1962 00:38:33.055999 TX DQ/DQS : PASS
1963 00:38:33.056082 RX DATLAT : PASS
1964 00:38:33.059632 RX DQ/DQS(Engine): PASS
1965 00:38:33.062569 TX OE : NO K
1966 00:38:33.062650 All Pass.
1967 00:38:33.062715
1968 00:38:33.062774 CH 1, Rank 0
1969 00:38:33.066091 SW Impedance : PASS
1970 00:38:33.069849 DUTY Scan : NO K
1971 00:38:33.069931 ZQ Calibration : PASS
1972 00:38:33.072727 Jitter Meter : NO K
1973 00:38:33.072807 CBT Training : PASS
1974 00:38:33.076549 Write leveling : PASS
1975 00:38:33.079255 RX DQS gating : PASS
1976 00:38:33.079343 RX DQ/DQS(RDDQC) : PASS
1977 00:38:33.082512 TX DQ/DQS : PASS
1978 00:38:33.085770 RX DATLAT : PASS
1979 00:38:33.085857 RX DQ/DQS(Engine): PASS
1980 00:38:33.089241 TX OE : NO K
1981 00:38:33.089377 All Pass.
1982 00:38:33.089441
1983 00:38:33.092510 CH 1, Rank 1
1984 00:38:33.092591 SW Impedance : PASS
1985 00:38:33.095906 DUTY Scan : NO K
1986 00:38:33.099141 ZQ Calibration : PASS
1987 00:38:33.099248 Jitter Meter : NO K
1988 00:38:33.102415 CBT Training : PASS
1989 00:38:33.105792 Write leveling : PASS
1990 00:38:33.105875 RX DQS gating : PASS
1991 00:38:33.109146 RX DQ/DQS(RDDQC) : PASS
1992 00:38:33.112478 TX DQ/DQS : PASS
1993 00:38:33.112561 RX DATLAT : PASS
1994 00:38:33.116099 RX DQ/DQS(Engine): PASS
1995 00:38:33.119052 TX OE : NO K
1996 00:38:33.119133 All Pass.
1997 00:38:33.119197
1998 00:38:33.119256 DramC Write-DBI off
1999 00:38:33.122440 PER_BANK_REFRESH: Hybrid Mode
2000 00:38:33.125918 TX_TRACKING: ON
2001 00:38:33.129431 [GetDramInforAfterCalByMRR] Vendor 6.
2002 00:38:33.132599 [GetDramInforAfterCalByMRR] Revision 606.
2003 00:38:33.135761 [GetDramInforAfterCalByMRR] Revision 2 0.
2004 00:38:33.135844 MR0 0x3939
2005 00:38:33.139271 MR8 0x1111
2006 00:38:33.142512 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2007 00:38:33.142600
2008 00:38:33.142686 MR0 0x3939
2009 00:38:33.142765 MR8 0x1111
2010 00:38:33.145994 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2011 00:38:33.146081
2012 00:38:33.155720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2013 00:38:33.159071 [FAST_K] Save calibration result to emmc
2014 00:38:33.162576 [FAST_K] Save calibration result to emmc
2015 00:38:33.165906 dram_init: config_dvfs: 1
2016 00:38:33.169004 dramc_set_vcore_voltage set vcore to 662500
2017 00:38:33.172509 Read voltage for 1200, 2
2018 00:38:33.172591 Vio18 = 0
2019 00:38:33.176262 Vcore = 662500
2020 00:38:33.176343 Vdram = 0
2021 00:38:33.176406 Vddq = 0
2022 00:38:33.176464 Vmddr = 0
2023 00:38:33.182625 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2024 00:38:33.186000 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2025 00:38:33.189118 MEM_TYPE=3, freq_sel=15
2026 00:38:33.192536 sv_algorithm_assistance_LP4_1600
2027 00:38:33.195850 ============ PULL DRAM RESETB DOWN ============
2028 00:38:33.202593 ========== PULL DRAM RESETB DOWN end =========
2029 00:38:33.205994 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2030 00:38:33.209386 ===================================
2031 00:38:33.212524 LPDDR4 DRAM CONFIGURATION
2032 00:38:33.215756 ===================================
2033 00:38:33.215843 EX_ROW_EN[0] = 0x0
2034 00:38:33.219057 EX_ROW_EN[1] = 0x0
2035 00:38:33.219143 LP4Y_EN = 0x0
2036 00:38:33.222527 WORK_FSP = 0x0
2037 00:38:33.222612 WL = 0x4
2038 00:38:33.225901 RL = 0x4
2039 00:38:33.225986 BL = 0x2
2040 00:38:33.229255 RPST = 0x0
2041 00:38:33.229389 RD_PRE = 0x0
2042 00:38:33.232572 WR_PRE = 0x1
2043 00:38:33.232655 WR_PST = 0x0
2044 00:38:33.235951 DBI_WR = 0x0
2045 00:38:33.236034 DBI_RD = 0x0
2046 00:38:33.239420 OTF = 0x1
2047 00:38:33.242669 ===================================
2048 00:38:33.245891 ===================================
2049 00:38:33.245984 ANA top config
2050 00:38:33.249280 ===================================
2051 00:38:33.252555 DLL_ASYNC_EN = 0
2052 00:38:33.255817 ALL_SLAVE_EN = 0
2053 00:38:33.259215 NEW_RANK_MODE = 1
2054 00:38:33.259307 DLL_IDLE_MODE = 1
2055 00:38:33.262635 LP45_APHY_COMB_EN = 1
2056 00:38:33.266017 TX_ODT_DIS = 1
2057 00:38:33.269209 NEW_8X_MODE = 1
2058 00:38:33.272550 ===================================
2059 00:38:33.275758 ===================================
2060 00:38:33.279154 data_rate = 2400
2061 00:38:33.279235 CKR = 1
2062 00:38:33.282624 DQ_P2S_RATIO = 8
2063 00:38:33.285902 ===================================
2064 00:38:33.289416 CA_P2S_RATIO = 8
2065 00:38:33.292708 DQ_CA_OPEN = 0
2066 00:38:33.296044 DQ_SEMI_OPEN = 0
2067 00:38:33.299262 CA_SEMI_OPEN = 0
2068 00:38:33.299343 CA_FULL_RATE = 0
2069 00:38:33.302728 DQ_CKDIV4_EN = 0
2070 00:38:33.305769 CA_CKDIV4_EN = 0
2071 00:38:33.309231 CA_PREDIV_EN = 0
2072 00:38:33.312626 PH8_DLY = 17
2073 00:38:33.315869 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2074 00:38:33.315951 DQ_AAMCK_DIV = 4
2075 00:38:33.319211 CA_AAMCK_DIV = 4
2076 00:38:33.322498 CA_ADMCK_DIV = 4
2077 00:38:33.325989 DQ_TRACK_CA_EN = 0
2078 00:38:33.329159 CA_PICK = 1200
2079 00:38:33.332499 CA_MCKIO = 1200
2080 00:38:33.332580 MCKIO_SEMI = 0
2081 00:38:33.335810 PLL_FREQ = 2366
2082 00:38:33.339174 DQ_UI_PI_RATIO = 32
2083 00:38:33.342818 CA_UI_PI_RATIO = 0
2084 00:38:33.346273 ===================================
2085 00:38:33.349277 ===================================
2086 00:38:33.352775 memory_type:LPDDR4
2087 00:38:33.352857 GP_NUM : 10
2088 00:38:33.355862 SRAM_EN : 1
2089 00:38:33.359175 MD32_EN : 0
2090 00:38:33.362711 ===================================
2091 00:38:33.362795 [ANA_INIT] >>>>>>>>>>>>>>
2092 00:38:33.366067 <<<<<< [CONFIGURE PHASE]: ANA_TX
2093 00:38:33.369133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2094 00:38:33.372706 ===================================
2095 00:38:33.376461 data_rate = 2400,PCW = 0X5b00
2096 00:38:33.379419 ===================================
2097 00:38:33.382727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2098 00:38:33.389445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2099 00:38:33.392828 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2100 00:38:33.399321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2101 00:38:33.402720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2102 00:38:33.405982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2103 00:38:33.406068 [ANA_INIT] flow start
2104 00:38:33.409372 [ANA_INIT] PLL >>>>>>>>
2105 00:38:33.412779 [ANA_INIT] PLL <<<<<<<<
2106 00:38:33.412861 [ANA_INIT] MIDPI >>>>>>>>
2107 00:38:33.416036 [ANA_INIT] MIDPI <<<<<<<<
2108 00:38:33.419261 [ANA_INIT] DLL >>>>>>>>
2109 00:38:33.422751 [ANA_INIT] DLL <<<<<<<<
2110 00:38:33.422833 [ANA_INIT] flow end
2111 00:38:33.425834 ============ LP4 DIFF to SE enter ============
2112 00:38:33.432564 ============ LP4 DIFF to SE exit ============
2113 00:38:33.432653 [ANA_INIT] <<<<<<<<<<<<<
2114 00:38:33.435974 [Flow] Enable top DCM control >>>>>
2115 00:38:33.439296 [Flow] Enable top DCM control <<<<<
2116 00:38:33.442485 Enable DLL master slave shuffle
2117 00:38:33.449174 ==============================================================
2118 00:38:33.449285 Gating Mode config
2119 00:38:33.455665 ==============================================================
2120 00:38:33.459279 Config description:
2121 00:38:33.465685 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2122 00:38:33.472386 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2123 00:38:33.479052 SELPH_MODE 0: By rank 1: By Phase
2124 00:38:33.485879 ==============================================================
2125 00:38:33.485971 GAT_TRACK_EN = 1
2126 00:38:33.489019 RX_GATING_MODE = 2
2127 00:38:33.492338 RX_GATING_TRACK_MODE = 2
2128 00:38:33.495802 SELPH_MODE = 1
2129 00:38:33.498953 PICG_EARLY_EN = 1
2130 00:38:33.502654 VALID_LAT_VALUE = 1
2131 00:38:33.508799 ==============================================================
2132 00:38:33.512320 Enter into Gating configuration >>>>
2133 00:38:33.515571 Exit from Gating configuration <<<<
2134 00:38:33.518759 Enter into DVFS_PRE_config >>>>>
2135 00:38:33.528710 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2136 00:38:33.532130 Exit from DVFS_PRE_config <<<<<
2137 00:38:33.535379 Enter into PICG configuration >>>>
2138 00:38:33.538700 Exit from PICG configuration <<<<
2139 00:38:33.541965 [RX_INPUT] configuration >>>>>
2140 00:38:33.545507 [RX_INPUT] configuration <<<<<
2141 00:38:33.548802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2142 00:38:33.555422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2143 00:38:33.562255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2144 00:38:33.565708 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2145 00:38:33.572172 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2146 00:38:33.578691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2147 00:38:33.582364 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2148 00:38:33.585401 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2149 00:38:33.591841 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2150 00:38:33.595354 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2151 00:38:33.598627 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2152 00:38:33.605174 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2153 00:38:33.609179 ===================================
2154 00:38:33.609297 LPDDR4 DRAM CONFIGURATION
2155 00:38:33.612184 ===================================
2156 00:38:33.615365 EX_ROW_EN[0] = 0x0
2157 00:38:33.615446 EX_ROW_EN[1] = 0x0
2158 00:38:33.618528 LP4Y_EN = 0x0
2159 00:38:33.618609 WORK_FSP = 0x0
2160 00:38:33.622019 WL = 0x4
2161 00:38:33.625490 RL = 0x4
2162 00:38:33.625571 BL = 0x2
2163 00:38:33.628660 RPST = 0x0
2164 00:38:33.628741 RD_PRE = 0x0
2165 00:38:33.631925 WR_PRE = 0x1
2166 00:38:33.632007 WR_PST = 0x0
2167 00:38:33.635147 DBI_WR = 0x0
2168 00:38:33.635227 DBI_RD = 0x0
2169 00:38:33.638549 OTF = 0x1
2170 00:38:33.642079 ===================================
2171 00:38:33.645182 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2172 00:38:33.648455 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2173 00:38:33.651823 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 00:38:33.655197 ===================================
2175 00:38:33.658711 LPDDR4 DRAM CONFIGURATION
2176 00:38:33.661863 ===================================
2177 00:38:33.665154 EX_ROW_EN[0] = 0x10
2178 00:38:33.665234 EX_ROW_EN[1] = 0x0
2179 00:38:33.668485 LP4Y_EN = 0x0
2180 00:38:33.668618 WORK_FSP = 0x0
2181 00:38:33.671908 WL = 0x4
2182 00:38:33.671988 RL = 0x4
2183 00:38:33.675670 BL = 0x2
2184 00:38:33.675775 RPST = 0x0
2185 00:38:33.678638 RD_PRE = 0x0
2186 00:38:33.678718 WR_PRE = 0x1
2187 00:38:33.681906 WR_PST = 0x0
2188 00:38:33.685174 DBI_WR = 0x0
2189 00:38:33.685255 DBI_RD = 0x0
2190 00:38:33.688494 OTF = 0x1
2191 00:38:33.692015 ===================================
2192 00:38:33.695181 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2193 00:38:33.695261 ==
2194 00:38:33.698397 Dram Type= 6, Freq= 0, CH_0, rank 0
2195 00:38:33.705114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2196 00:38:33.705225 ==
2197 00:38:33.705367 [Duty_Offset_Calibration]
2198 00:38:33.708436 B0:0 B1:2 CA:1
2199 00:38:33.708516
2200 00:38:33.711689 [DutyScan_Calibration_Flow] k_type=0
2201 00:38:33.721214
2202 00:38:33.721373 ==CLK 0==
2203 00:38:33.724336 Final CLK duty delay cell = 0
2204 00:38:33.727689 [0] MAX Duty = 5093%(X100), DQS PI = 12
2205 00:38:33.731133 [0] MIN Duty = 4938%(X100), DQS PI = 52
2206 00:38:33.731214 [0] AVG Duty = 5015%(X100)
2207 00:38:33.734345
2208 00:38:33.737537 CH0 CLK Duty spec in!! Max-Min= 155%
2209 00:38:33.741029 [DutyScan_Calibration_Flow] ====Done====
2210 00:38:33.741110
2211 00:38:33.744277 [DutyScan_Calibration_Flow] k_type=1
2212 00:38:33.760377
2213 00:38:33.760470 ==DQS 0 ==
2214 00:38:33.763678 Final DQS duty delay cell = 0
2215 00:38:33.767041 [0] MAX Duty = 5125%(X100), DQS PI = 32
2216 00:38:33.771062 [0] MIN Duty = 5031%(X100), DQS PI = 6
2217 00:38:33.771144 [0] AVG Duty = 5078%(X100)
2218 00:38:33.773671
2219 00:38:33.773752 ==DQS 1 ==
2220 00:38:33.776856 Final DQS duty delay cell = 0
2221 00:38:33.780565 [0] MAX Duty = 5031%(X100), DQS PI = 52
2222 00:38:33.783698 [0] MIN Duty = 4906%(X100), DQS PI = 14
2223 00:38:33.783781 [0] AVG Duty = 4968%(X100)
2224 00:38:33.787034
2225 00:38:33.790455 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2226 00:38:33.790537
2227 00:38:33.793682 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2228 00:38:33.796974 [DutyScan_Calibration_Flow] ====Done====
2229 00:38:33.797056
2230 00:38:33.800253 [DutyScan_Calibration_Flow] k_type=3
2231 00:38:33.817615
2232 00:38:33.817745 ==DQM 0 ==
2233 00:38:33.820904 Final DQM duty delay cell = 0
2234 00:38:33.824127 [0] MAX Duty = 5156%(X100), DQS PI = 22
2235 00:38:33.827529 [0] MIN Duty = 4969%(X100), DQS PI = 40
2236 00:38:33.827612 [0] AVG Duty = 5062%(X100)
2237 00:38:33.830725
2238 00:38:33.830806 ==DQM 1 ==
2239 00:38:33.834356 Final DQM duty delay cell = 4
2240 00:38:33.837733 [4] MAX Duty = 5187%(X100), DQS PI = 54
2241 00:38:33.840864 [4] MIN Duty = 5000%(X100), DQS PI = 16
2242 00:38:33.844190 [4] AVG Duty = 5093%(X100)
2243 00:38:33.844271
2244 00:38:33.847445 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2245 00:38:33.847527
2246 00:38:33.850715 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2247 00:38:33.854152 [DutyScan_Calibration_Flow] ====Done====
2248 00:38:33.854233
2249 00:38:33.857488 [DutyScan_Calibration_Flow] k_type=2
2250 00:38:33.872867
2251 00:38:33.872975 ==DQ 0 ==
2252 00:38:33.875921 Final DQ duty delay cell = -4
2253 00:38:33.879205 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2254 00:38:33.882547 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2255 00:38:33.885966 [-4] AVG Duty = 4937%(X100)
2256 00:38:33.886048
2257 00:38:33.886112 ==DQ 1 ==
2258 00:38:33.889467 Final DQ duty delay cell = -4
2259 00:38:33.892658 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2260 00:38:33.895776 [-4] MIN Duty = 4876%(X100), DQS PI = 38
2261 00:38:33.899121 [-4] AVG Duty = 4969%(X100)
2262 00:38:33.899204
2263 00:38:33.902458 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2264 00:38:33.902576
2265 00:38:33.905850 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2266 00:38:33.909196 [DutyScan_Calibration_Flow] ====Done====
2267 00:38:33.909329 ==
2268 00:38:33.912561 Dram Type= 6, Freq= 0, CH_1, rank 0
2269 00:38:33.916020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2270 00:38:33.916102 ==
2271 00:38:33.919679 [Duty_Offset_Calibration]
2272 00:38:33.919761 B0:0 B1:5 CA:-5
2273 00:38:33.919825
2274 00:38:33.922572 [DutyScan_Calibration_Flow] k_type=0
2275 00:38:33.933102
2276 00:38:33.933196 ==CLK 0==
2277 00:38:33.936586 Final CLK duty delay cell = 0
2278 00:38:33.939695 [0] MAX Duty = 5094%(X100), DQS PI = 24
2279 00:38:33.942995 [0] MIN Duty = 4876%(X100), DQS PI = 52
2280 00:38:33.943077 [0] AVG Duty = 4985%(X100)
2281 00:38:33.946581
2282 00:38:33.949713 CH1 CLK Duty spec in!! Max-Min= 218%
2283 00:38:33.953054 [DutyScan_Calibration_Flow] ====Done====
2284 00:38:33.953137
2285 00:38:33.956191 [DutyScan_Calibration_Flow] k_type=1
2286 00:38:33.971495
2287 00:38:33.971604 ==DQS 0 ==
2288 00:38:33.974903 Final DQS duty delay cell = 0
2289 00:38:33.978305 [0] MAX Duty = 5125%(X100), DQS PI = 16
2290 00:38:33.981818 [0] MIN Duty = 4875%(X100), DQS PI = 40
2291 00:38:33.984961 [0] AVG Duty = 5000%(X100)
2292 00:38:33.985043
2293 00:38:33.985106 ==DQS 1 ==
2294 00:38:33.988211 Final DQS duty delay cell = -4
2295 00:38:33.991739 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2296 00:38:33.994895 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2297 00:38:33.998257 [-4] AVG Duty = 4953%(X100)
2298 00:38:33.998359
2299 00:38:34.001563 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2300 00:38:34.001645
2301 00:38:34.004869 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2302 00:38:34.008139 [DutyScan_Calibration_Flow] ====Done====
2303 00:38:34.008222
2304 00:38:34.011505 [DutyScan_Calibration_Flow] k_type=3
2305 00:38:34.026758
2306 00:38:34.026886 ==DQM 0 ==
2307 00:38:34.030172 Final DQM duty delay cell = -4
2308 00:38:34.033389 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2309 00:38:34.037002 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2310 00:38:34.040370 [-4] AVG Duty = 4969%(X100)
2311 00:38:34.040451
2312 00:38:34.040514 ==DQM 1 ==
2313 00:38:34.043592 Final DQM duty delay cell = -4
2314 00:38:34.047029 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2315 00:38:34.050430 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2316 00:38:34.053709 [-4] AVG Duty = 5000%(X100)
2317 00:38:34.053791
2318 00:38:34.057269 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2319 00:38:34.057361
2320 00:38:34.060354 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2321 00:38:34.064062 [DutyScan_Calibration_Flow] ====Done====
2322 00:38:34.064143
2323 00:38:34.067210 [DutyScan_Calibration_Flow] k_type=2
2324 00:38:34.083965
2325 00:38:34.084088 ==DQ 0 ==
2326 00:38:34.087349 Final DQ duty delay cell = 0
2327 00:38:34.090613 [0] MAX Duty = 5062%(X100), DQS PI = 0
2328 00:38:34.093817 [0] MIN Duty = 4969%(X100), DQS PI = 42
2329 00:38:34.093899 [0] AVG Duty = 5015%(X100)
2330 00:38:34.093963
2331 00:38:34.097185 ==DQ 1 ==
2332 00:38:34.100735 Final DQ duty delay cell = 0
2333 00:38:34.104105 [0] MAX Duty = 5031%(X100), DQS PI = 8
2334 00:38:34.107326 [0] MIN Duty = 4907%(X100), DQS PI = 0
2335 00:38:34.107409 [0] AVG Duty = 4969%(X100)
2336 00:38:34.107473
2337 00:38:34.110630 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2338 00:38:34.110711
2339 00:38:34.113866 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2340 00:38:34.120446 [DutyScan_Calibration_Flow] ====Done====
2341 00:38:34.124036 nWR fixed to 30
2342 00:38:34.124117 [ModeRegInit_LP4] CH0 RK0
2343 00:38:34.127215 [ModeRegInit_LP4] CH0 RK1
2344 00:38:34.130399 [ModeRegInit_LP4] CH1 RK0
2345 00:38:34.130480 [ModeRegInit_LP4] CH1 RK1
2346 00:38:34.133838 match AC timing 6
2347 00:38:34.137063 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2348 00:38:34.140647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2349 00:38:34.147155 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2350 00:38:34.150809 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2351 00:38:34.157193 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2352 00:38:34.157323 ==
2353 00:38:34.160415 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 00:38:34.163716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2355 00:38:34.163797 ==
2356 00:38:34.170464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2357 00:38:34.173791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2358 00:38:34.183416 [CA 0] Center 39 (9~70) winsize 62
2359 00:38:34.187145 [CA 1] Center 39 (8~70) winsize 63
2360 00:38:34.190100 [CA 2] Center 36 (5~67) winsize 63
2361 00:38:34.193393 [CA 3] Center 35 (4~66) winsize 63
2362 00:38:34.196703 [CA 4] Center 34 (3~65) winsize 63
2363 00:38:34.200197 [CA 5] Center 33 (3~64) winsize 62
2364 00:38:34.200278
2365 00:38:34.203481 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2366 00:38:34.203563
2367 00:38:34.206899 [CATrainingPosCal] consider 1 rank data
2368 00:38:34.210215 u2DelayCellTimex100 = 270/100 ps
2369 00:38:34.213490 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2370 00:38:34.216809 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2371 00:38:34.223526 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2372 00:38:34.226899 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2373 00:38:34.229991 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2374 00:38:34.233553 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2375 00:38:34.233634
2376 00:38:34.236876 CA PerBit enable=1, Macro0, CA PI delay=33
2377 00:38:34.236957
2378 00:38:34.240186 [CBTSetCACLKResult] CA Dly = 33
2379 00:38:34.240267 CS Dly: 7 (0~38)
2380 00:38:34.240332 ==
2381 00:38:34.243443 Dram Type= 6, Freq= 0, CH_0, rank 1
2382 00:38:34.250283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2383 00:38:34.250366 ==
2384 00:38:34.253563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2385 00:38:34.260348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2386 00:38:34.268562 [CA 0] Center 39 (8~70) winsize 63
2387 00:38:34.271881 [CA 1] Center 39 (8~70) winsize 63
2388 00:38:34.275317 [CA 2] Center 35 (5~66) winsize 62
2389 00:38:34.278677 [CA 3] Center 35 (4~66) winsize 63
2390 00:38:34.281861 [CA 4] Center 33 (3~64) winsize 62
2391 00:38:34.285204 [CA 5] Center 34 (3~65) winsize 63
2392 00:38:34.285314
2393 00:38:34.288533 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2394 00:38:34.288615
2395 00:38:34.291890 [CATrainingPosCal] consider 2 rank data
2396 00:38:34.295145 u2DelayCellTimex100 = 270/100 ps
2397 00:38:34.298598 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2398 00:38:34.305200 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2399 00:38:34.308554 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2400 00:38:34.311916 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2401 00:38:34.315166 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2402 00:38:34.318620 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2403 00:38:34.318701
2404 00:38:34.321705 CA PerBit enable=1, Macro0, CA PI delay=33
2405 00:38:34.321786
2406 00:38:34.325173 [CBTSetCACLKResult] CA Dly = 33
2407 00:38:34.325279 CS Dly: 7 (0~39)
2408 00:38:34.328513
2409 00:38:34.331824 ----->DramcWriteLeveling(PI) begin...
2410 00:38:34.331907 ==
2411 00:38:34.334957 Dram Type= 6, Freq= 0, CH_0, rank 0
2412 00:38:34.338338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2413 00:38:34.338419 ==
2414 00:38:34.341946 Write leveling (Byte 0): 27 => 27
2415 00:38:34.345162 Write leveling (Byte 1): 25 => 25
2416 00:38:34.348793 DramcWriteLeveling(PI) end<-----
2417 00:38:34.348873
2418 00:38:34.348936 ==
2419 00:38:34.351745 Dram Type= 6, Freq= 0, CH_0, rank 0
2420 00:38:34.355019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2421 00:38:34.355100 ==
2422 00:38:34.358566 [Gating] SW mode calibration
2423 00:38:34.365116 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2424 00:38:34.372190 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2425 00:38:34.375254 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2426 00:38:34.378692 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2427 00:38:34.385179 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2428 00:38:34.388455 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2429 00:38:34.391745 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2430 00:38:34.395169 0 11 20 | B1->B0 | 2d2d 2a2a | 1 1 | (1 0) (1 0)
2431 00:38:34.401695 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2432 00:38:34.405057 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2433 00:38:34.408571 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2434 00:38:34.415063 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2435 00:38:34.418537 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2436 00:38:34.421878 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2437 00:38:34.428429 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2438 00:38:34.432204 0 12 20 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
2439 00:38:34.435472 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2440 00:38:34.441770 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2441 00:38:34.445077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2442 00:38:34.448479 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2443 00:38:34.455223 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2444 00:38:34.458350 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2445 00:38:34.461792 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2446 00:38:34.468660 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2447 00:38:34.471869 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2448 00:38:34.475111 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2449 00:38:34.481773 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2450 00:38:34.485087 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2451 00:38:34.488211 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2452 00:38:34.494866 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2453 00:38:34.498266 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2454 00:38:34.501747 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2455 00:38:34.505187 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2456 00:38:34.511556 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2457 00:38:34.514962 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2458 00:38:34.518434 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2459 00:38:34.524856 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2460 00:38:34.528246 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 00:38:34.531618 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2462 00:38:34.538533 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2463 00:38:34.541897 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 00:38:34.545047 Total UI for P1: 0, mck2ui 16
2465 00:38:34.548263 best dqsien dly found for B0: ( 0, 15, 18)
2466 00:38:34.551551 Total UI for P1: 0, mck2ui 16
2467 00:38:34.554902 best dqsien dly found for B1: ( 0, 15, 20)
2468 00:38:34.558173 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2469 00:38:34.561552 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2470 00:38:34.561635
2471 00:38:34.564951 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2472 00:38:34.568239 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2473 00:38:34.571729 [Gating] SW calibration Done
2474 00:38:34.571810 ==
2475 00:38:34.574931 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 00:38:34.581640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2477 00:38:34.581724 ==
2478 00:38:34.581789 RX Vref Scan: 0
2479 00:38:34.581848
2480 00:38:34.585008 RX Vref 0 -> 0, step: 1
2481 00:38:34.585088
2482 00:38:34.588113 RX Delay -40 -> 252, step: 8
2483 00:38:34.591405 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2484 00:38:34.594802 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2485 00:38:34.598250 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2486 00:38:34.601492 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2487 00:38:34.608186 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2488 00:38:34.611410 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2489 00:38:34.614695 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2490 00:38:34.618191 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2491 00:38:34.621828 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2492 00:38:34.624801 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2493 00:38:34.631345 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2494 00:38:34.635034 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2495 00:38:34.638144 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2496 00:38:34.641280 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2497 00:38:34.648042 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2498 00:38:34.651459 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2499 00:38:34.651543 ==
2500 00:38:34.654813 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 00:38:34.658166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2502 00:38:34.658249 ==
2503 00:38:34.658313 DQS Delay:
2504 00:38:34.661474 DQS0 = 0, DQS1 = 0
2505 00:38:34.661555 DQM Delay:
2506 00:38:34.665005 DQM0 = 115, DQM1 = 107
2507 00:38:34.665086 DQ Delay:
2508 00:38:34.668276 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2509 00:38:34.671501 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2510 00:38:34.674846 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =107
2511 00:38:34.678106 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2512 00:38:34.678213
2513 00:38:34.681539
2514 00:38:34.681619 ==
2515 00:38:34.685116 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 00:38:34.688310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2517 00:38:34.688392 ==
2518 00:38:34.688457
2519 00:38:34.688515
2520 00:38:34.691463 TX Vref Scan disable
2521 00:38:34.691544 == TX Byte 0 ==
2522 00:38:34.694942 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2523 00:38:34.701689 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2524 00:38:34.701773 == TX Byte 1 ==
2525 00:38:34.705082 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2526 00:38:34.711595 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2527 00:38:34.711681 ==
2528 00:38:34.715046 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 00:38:34.718303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2530 00:38:34.718387 ==
2531 00:38:34.730701 TX Vref=22, minBit 8, minWin=24, winSum=415
2532 00:38:34.733794 TX Vref=24, minBit 8, minWin=25, winSum=420
2533 00:38:34.737102 TX Vref=26, minBit 8, minWin=24, winSum=423
2534 00:38:34.740530 TX Vref=28, minBit 9, minWin=25, winSum=431
2535 00:38:34.743586 TX Vref=30, minBit 8, minWin=26, winSum=433
2536 00:38:34.747056 TX Vref=32, minBit 8, minWin=26, winSum=426
2537 00:38:34.753766 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
2538 00:38:34.753853
2539 00:38:34.756838 Final TX Range 1 Vref 30
2540 00:38:34.756921
2541 00:38:34.756985 ==
2542 00:38:34.760150 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 00:38:34.763634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 00:38:34.763717 ==
2545 00:38:34.766925
2546 00:38:34.767005
2547 00:38:34.767068 TX Vref Scan disable
2548 00:38:34.770160 == TX Byte 0 ==
2549 00:38:34.773429 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2550 00:38:34.776949 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2551 00:38:34.780120 == TX Byte 1 ==
2552 00:38:34.783544 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2553 00:38:34.786897 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2554 00:38:34.786980
2555 00:38:34.790531 [DATLAT]
2556 00:38:34.790612 Freq=1200, CH0 RK0
2557 00:38:34.790676
2558 00:38:34.793569 DATLAT Default: 0xd
2559 00:38:34.793674 0, 0xFFFF, sum = 0
2560 00:38:34.797072 1, 0xFFFF, sum = 0
2561 00:38:34.797154 2, 0xFFFF, sum = 0
2562 00:38:34.800200 3, 0xFFFF, sum = 0
2563 00:38:34.800282 4, 0xFFFF, sum = 0
2564 00:38:34.803805 5, 0xFFFF, sum = 0
2565 00:38:34.803916 6, 0xFFFF, sum = 0
2566 00:38:34.807044 7, 0xFFFF, sum = 0
2567 00:38:34.807128 8, 0xFFFF, sum = 0
2568 00:38:34.810310 9, 0xFFFF, sum = 0
2569 00:38:34.813653 10, 0xFFFF, sum = 0
2570 00:38:34.813736 11, 0x0, sum = 1
2571 00:38:34.813800 12, 0x0, sum = 2
2572 00:38:34.816954 13, 0x0, sum = 3
2573 00:38:34.817036 14, 0x0, sum = 4
2574 00:38:34.820117 best_step = 12
2575 00:38:34.820197
2576 00:38:34.820261 ==
2577 00:38:34.823605 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 00:38:34.826825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2579 00:38:34.826912 ==
2580 00:38:34.830105 RX Vref Scan: 1
2581 00:38:34.830185
2582 00:38:34.833264 Set Vref Range= 32 -> 127
2583 00:38:34.833353
2584 00:38:34.833417 RX Vref 32 -> 127, step: 1
2585 00:38:34.833477
2586 00:38:34.836788 RX Delay -21 -> 252, step: 4
2587 00:38:34.836869
2588 00:38:34.840198 Set Vref, RX VrefLevel [Byte0]: 32
2589 00:38:34.843289 [Byte1]: 32
2590 00:38:34.846827
2591 00:38:34.846909 Set Vref, RX VrefLevel [Byte0]: 33
2592 00:38:34.850065 [Byte1]: 33
2593 00:38:34.854832
2594 00:38:34.854914 Set Vref, RX VrefLevel [Byte0]: 34
2595 00:38:34.857887 [Byte1]: 34
2596 00:38:34.862965
2597 00:38:34.863048 Set Vref, RX VrefLevel [Byte0]: 35
2598 00:38:34.866163 [Byte1]: 35
2599 00:38:34.870835
2600 00:38:34.870917 Set Vref, RX VrefLevel [Byte0]: 36
2601 00:38:34.873910 [Byte1]: 36
2602 00:38:34.878426
2603 00:38:34.878509 Set Vref, RX VrefLevel [Byte0]: 37
2604 00:38:34.881739 [Byte1]: 37
2605 00:38:34.886587
2606 00:38:34.886672 Set Vref, RX VrefLevel [Byte0]: 38
2607 00:38:34.889843 [Byte1]: 38
2608 00:38:34.894414
2609 00:38:34.894496 Set Vref, RX VrefLevel [Byte0]: 39
2610 00:38:34.897640 [Byte1]: 39
2611 00:38:34.902191
2612 00:38:34.902272 Set Vref, RX VrefLevel [Byte0]: 40
2613 00:38:34.905435 [Byte1]: 40
2614 00:38:34.910255
2615 00:38:34.910339 Set Vref, RX VrefLevel [Byte0]: 41
2616 00:38:34.913409 [Byte1]: 41
2617 00:38:34.917987
2618 00:38:34.918068 Set Vref, RX VrefLevel [Byte0]: 42
2619 00:38:34.921250 [Byte1]: 42
2620 00:38:34.925881
2621 00:38:34.925962 Set Vref, RX VrefLevel [Byte0]: 43
2622 00:38:34.929640 [Byte1]: 43
2623 00:38:34.934023
2624 00:38:34.934103 Set Vref, RX VrefLevel [Byte0]: 44
2625 00:38:34.937164 [Byte1]: 44
2626 00:38:34.941913
2627 00:38:34.941993 Set Vref, RX VrefLevel [Byte0]: 45
2628 00:38:34.945414 [Byte1]: 45
2629 00:38:34.949795
2630 00:38:34.949881 Set Vref, RX VrefLevel [Byte0]: 46
2631 00:38:34.953013 [Byte1]: 46
2632 00:38:34.957653
2633 00:38:34.957738 Set Vref, RX VrefLevel [Byte0]: 47
2634 00:38:34.960969 [Byte1]: 47
2635 00:38:34.965568
2636 00:38:34.965653 Set Vref, RX VrefLevel [Byte0]: 48
2637 00:38:34.968900 [Byte1]: 48
2638 00:38:34.973794
2639 00:38:34.973879 Set Vref, RX VrefLevel [Byte0]: 49
2640 00:38:34.976929 [Byte1]: 49
2641 00:38:34.981481
2642 00:38:34.981568 Set Vref, RX VrefLevel [Byte0]: 50
2643 00:38:34.984636 [Byte1]: 50
2644 00:38:34.989412
2645 00:38:34.989497 Set Vref, RX VrefLevel [Byte0]: 51
2646 00:38:34.992590 [Byte1]: 51
2647 00:38:34.997207
2648 00:38:34.997322 Set Vref, RX VrefLevel [Byte0]: 52
2649 00:38:35.000475 [Byte1]: 52
2650 00:38:35.005242
2651 00:38:35.005384 Set Vref, RX VrefLevel [Byte0]: 53
2652 00:38:35.008765 [Byte1]: 53
2653 00:38:35.013022
2654 00:38:35.013132 Set Vref, RX VrefLevel [Byte0]: 54
2655 00:38:35.016339 [Byte1]: 54
2656 00:38:35.020969
2657 00:38:35.021053 Set Vref, RX VrefLevel [Byte0]: 55
2658 00:38:35.024493 [Byte1]: 55
2659 00:38:35.028924
2660 00:38:35.029009 Set Vref, RX VrefLevel [Byte0]: 56
2661 00:38:35.032379 [Byte1]: 56
2662 00:38:35.036825
2663 00:38:35.036909 Set Vref, RX VrefLevel [Byte0]: 57
2664 00:38:35.040163 [Byte1]: 57
2665 00:38:35.044975
2666 00:38:35.045060 Set Vref, RX VrefLevel [Byte0]: 58
2667 00:38:35.048229 [Byte1]: 58
2668 00:38:35.052787
2669 00:38:35.052871 Set Vref, RX VrefLevel [Byte0]: 59
2670 00:38:35.056183 [Byte1]: 59
2671 00:38:35.060896
2672 00:38:35.060981 Set Vref, RX VrefLevel [Byte0]: 60
2673 00:38:35.064126 [Byte1]: 60
2674 00:38:35.068615
2675 00:38:35.068699 Set Vref, RX VrefLevel [Byte0]: 61
2676 00:38:35.071827 [Byte1]: 61
2677 00:38:35.076542
2678 00:38:35.076624 Set Vref, RX VrefLevel [Byte0]: 62
2679 00:38:35.079868 [Byte1]: 62
2680 00:38:35.084565
2681 00:38:35.084647 Set Vref, RX VrefLevel [Byte0]: 63
2682 00:38:35.087601 [Byte1]: 63
2683 00:38:35.092529
2684 00:38:35.092611 Set Vref, RX VrefLevel [Byte0]: 64
2685 00:38:35.095899 [Byte1]: 64
2686 00:38:35.100396
2687 00:38:35.100478 Set Vref, RX VrefLevel [Byte0]: 65
2688 00:38:35.103618 [Byte1]: 65
2689 00:38:35.108212
2690 00:38:35.108297 Set Vref, RX VrefLevel [Byte0]: 66
2691 00:38:35.111525 [Byte1]: 66
2692 00:38:35.115966
2693 00:38:35.116047 Final RX Vref Byte 0 = 53 to rank0
2694 00:38:35.119436 Final RX Vref Byte 1 = 50 to rank0
2695 00:38:35.122768 Final RX Vref Byte 0 = 53 to rank1
2696 00:38:35.126117 Final RX Vref Byte 1 = 50 to rank1==
2697 00:38:35.129515 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 00:38:35.136017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2699 00:38:35.136101 ==
2700 00:38:35.136166 DQS Delay:
2701 00:38:35.136226 DQS0 = 0, DQS1 = 0
2702 00:38:35.139380 DQM Delay:
2703 00:38:35.139460 DQM0 = 114, DQM1 = 106
2704 00:38:35.142811 DQ Delay:
2705 00:38:35.146302 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2706 00:38:35.149413 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2707 00:38:35.152783 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98
2708 00:38:35.156418 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2709 00:38:35.156499
2710 00:38:35.156562
2711 00:38:35.162817 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2712 00:38:35.166165 CH0 RK0: MR19=404, MR18=606
2713 00:38:35.172894 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2714 00:38:35.172976
2715 00:38:35.175954 ----->DramcWriteLeveling(PI) begin...
2716 00:38:35.176037 ==
2717 00:38:35.179566 Dram Type= 6, Freq= 0, CH_0, rank 1
2718 00:38:35.182845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2719 00:38:35.182927 ==
2720 00:38:35.186194 Write leveling (Byte 0): 27 => 27
2721 00:38:35.189571 Write leveling (Byte 1): 24 => 24
2722 00:38:35.193176 DramcWriteLeveling(PI) end<-----
2723 00:38:35.193257
2724 00:38:35.193369 ==
2725 00:38:35.196252 Dram Type= 6, Freq= 0, CH_0, rank 1
2726 00:38:35.199524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2727 00:38:35.199607 ==
2728 00:38:35.202863 [Gating] SW mode calibration
2729 00:38:35.209670 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2730 00:38:35.216499 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2731 00:38:35.219765 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2732 00:38:35.226213 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2733 00:38:35.229532 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2734 00:38:35.232758 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2735 00:38:35.239625 0 11 16 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
2736 00:38:35.242873 0 11 20 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 0)
2737 00:38:35.246113 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2738 00:38:35.252932 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2739 00:38:35.256103 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2740 00:38:35.259570 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2741 00:38:35.262860 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2742 00:38:35.269597 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2743 00:38:35.272881 0 12 16 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2744 00:38:35.276381 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2745 00:38:35.282957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2746 00:38:35.286447 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2747 00:38:35.289633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2748 00:38:35.296504 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2749 00:38:35.299529 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2750 00:38:35.303038 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2751 00:38:35.309758 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2752 00:38:35.312972 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2753 00:38:35.316202 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2754 00:38:35.322890 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2755 00:38:35.326382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2756 00:38:35.329663 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2757 00:38:35.336417 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2758 00:38:35.339510 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2759 00:38:35.342958 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2760 00:38:35.349560 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2761 00:38:35.352813 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2762 00:38:35.356459 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2763 00:38:35.359525 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2764 00:38:35.366498 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2765 00:38:35.369923 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2766 00:38:35.372909 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2767 00:38:35.379542 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2768 00:38:35.382870 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2769 00:38:35.386339 Total UI for P1: 0, mck2ui 16
2770 00:38:35.389505 best dqsien dly found for B0: ( 0, 15, 16)
2771 00:38:35.392965 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2772 00:38:35.396106 Total UI for P1: 0, mck2ui 16
2773 00:38:35.399541 best dqsien dly found for B1: ( 0, 15, 18)
2774 00:38:35.403214 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2775 00:38:35.406388 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2776 00:38:35.406487
2777 00:38:35.413202 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2778 00:38:35.416496 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2779 00:38:35.419819 [Gating] SW calibration Done
2780 00:38:35.419905 ==
2781 00:38:35.423163 Dram Type= 6, Freq= 0, CH_0, rank 1
2782 00:38:35.426228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2783 00:38:35.426314 ==
2784 00:38:35.426380 RX Vref Scan: 0
2785 00:38:35.426439
2786 00:38:35.429607 RX Vref 0 -> 0, step: 1
2787 00:38:35.429688
2788 00:38:35.432761 RX Delay -40 -> 252, step: 8
2789 00:38:35.436415 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2790 00:38:35.439764 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2791 00:38:35.446236 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2792 00:38:35.449951 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2793 00:38:35.452891 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2794 00:38:35.456159 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2795 00:38:35.459605 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2796 00:38:35.462873 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2797 00:38:35.469666 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2798 00:38:35.473021 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2799 00:38:35.476215 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2800 00:38:35.479970 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2801 00:38:35.482758 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2802 00:38:35.489763 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2803 00:38:35.492728 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2804 00:38:35.496056 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2805 00:38:35.496145 ==
2806 00:38:35.499616 Dram Type= 6, Freq= 0, CH_0, rank 1
2807 00:38:35.502737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2808 00:38:35.502825 ==
2809 00:38:35.506053 DQS Delay:
2810 00:38:35.506142 DQS0 = 0, DQS1 = 0
2811 00:38:35.509438 DQM Delay:
2812 00:38:35.509522 DQM0 = 114, DQM1 = 107
2813 00:38:35.512697 DQ Delay:
2814 00:38:35.516241 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2815 00:38:35.519545 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2816 00:38:35.522867 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2817 00:38:35.525951 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2818 00:38:35.526038
2819 00:38:35.526124
2820 00:38:35.526204 ==
2821 00:38:35.529409 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 00:38:35.532624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2823 00:38:35.532711 ==
2824 00:38:35.532796
2825 00:38:35.532876
2826 00:38:35.536238 TX Vref Scan disable
2827 00:38:35.539514 == TX Byte 0 ==
2828 00:38:35.542778 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2829 00:38:35.545937 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2830 00:38:35.549552 == TX Byte 1 ==
2831 00:38:35.553450 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2832 00:38:35.555945 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2833 00:38:35.556033 ==
2834 00:38:35.559517 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 00:38:35.562741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2836 00:38:35.565780 ==
2837 00:38:35.576119 TX Vref=22, minBit 5, minWin=25, winSum=420
2838 00:38:35.579490 TX Vref=24, minBit 8, minWin=25, winSum=424
2839 00:38:35.582710 TX Vref=26, minBit 8, minWin=25, winSum=427
2840 00:38:35.586104 TX Vref=28, minBit 8, minWin=26, winSum=430
2841 00:38:35.589501 TX Vref=30, minBit 9, minWin=26, winSum=436
2842 00:38:35.595951 TX Vref=32, minBit 9, minWin=26, winSum=433
2843 00:38:35.599561 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
2844 00:38:35.599647
2845 00:38:35.602626 Final TX Range 1 Vref 30
2846 00:38:35.602708
2847 00:38:35.602771 ==
2848 00:38:35.606101 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 00:38:35.609403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2850 00:38:35.609486 ==
2851 00:38:35.609550
2852 00:38:35.612857
2853 00:38:35.612937 TX Vref Scan disable
2854 00:38:35.616041 == TX Byte 0 ==
2855 00:38:35.619855 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2856 00:38:35.622720 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2857 00:38:35.626033 == TX Byte 1 ==
2858 00:38:35.629282 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2859 00:38:35.632747 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2860 00:38:35.635876
2861 00:38:35.635959 [DATLAT]
2862 00:38:35.636023 Freq=1200, CH0 RK1
2863 00:38:35.636083
2864 00:38:35.639275 DATLAT Default: 0xc
2865 00:38:35.639357 0, 0xFFFF, sum = 0
2866 00:38:35.642574 1, 0xFFFF, sum = 0
2867 00:38:35.642657 2, 0xFFFF, sum = 0
2868 00:38:35.645983 3, 0xFFFF, sum = 0
2869 00:38:35.646066 4, 0xFFFF, sum = 0
2870 00:38:35.649243 5, 0xFFFF, sum = 0
2871 00:38:35.652773 6, 0xFFFF, sum = 0
2872 00:38:35.652856 7, 0xFFFF, sum = 0
2873 00:38:35.655844 8, 0xFFFF, sum = 0
2874 00:38:35.655926 9, 0xFFFF, sum = 0
2875 00:38:35.659397 10, 0xFFFF, sum = 0
2876 00:38:35.659483 11, 0x0, sum = 1
2877 00:38:35.662759 12, 0x0, sum = 2
2878 00:38:35.662845 13, 0x0, sum = 3
2879 00:38:35.662911 14, 0x0, sum = 4
2880 00:38:35.665906 best_step = 12
2881 00:38:35.665987
2882 00:38:35.666051 ==
2883 00:38:35.669233 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 00:38:35.672562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2885 00:38:35.672645 ==
2886 00:38:35.676012 RX Vref Scan: 0
2887 00:38:35.676093
2888 00:38:35.676157 RX Vref 0 -> 0, step: 1
2889 00:38:35.679214
2890 00:38:35.679295 RX Delay -21 -> 252, step: 4
2891 00:38:35.686290 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2892 00:38:35.689775 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2893 00:38:35.692894 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2894 00:38:35.696482 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2895 00:38:35.699679 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2896 00:38:35.706286 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2897 00:38:35.709801 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2898 00:38:35.713093 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2899 00:38:35.716233 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2900 00:38:35.719592 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2901 00:38:35.726339 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2902 00:38:35.729949 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2903 00:38:35.732882 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2904 00:38:35.736305 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2905 00:38:35.739838 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2906 00:38:35.746424 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2907 00:38:35.746509 ==
2908 00:38:35.749667 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 00:38:35.752922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2910 00:38:35.753003 ==
2911 00:38:35.753068 DQS Delay:
2912 00:38:35.756292 DQS0 = 0, DQS1 = 0
2913 00:38:35.756373 DQM Delay:
2914 00:38:35.759750 DQM0 = 114, DQM1 = 106
2915 00:38:35.759832 DQ Delay:
2916 00:38:35.762960 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2917 00:38:35.766207 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2918 00:38:35.769582 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2919 00:38:35.773176 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2920 00:38:35.773258
2921 00:38:35.773363
2922 00:38:35.782882 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2923 00:38:35.786261 CH0 RK1: MR19=404, MR18=E0E
2924 00:38:35.789552 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2925 00:38:35.792965 [RxdqsGatingPostProcess] freq 1200
2926 00:38:35.799688 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2927 00:38:35.803044 Pre-setting of DQS Precalculation
2928 00:38:35.806277 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2929 00:38:35.806368 ==
2930 00:38:35.809674 Dram Type= 6, Freq= 0, CH_1, rank 0
2931 00:38:35.816196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2932 00:38:35.816283 ==
2933 00:38:35.819611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2934 00:38:35.826051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2935 00:38:35.834671 [CA 0] Center 37 (7~68) winsize 62
2936 00:38:35.838026 [CA 1] Center 37 (7~68) winsize 62
2937 00:38:35.841394 [CA 2] Center 34 (4~65) winsize 62
2938 00:38:35.844839 [CA 3] Center 33 (3~64) winsize 62
2939 00:38:35.848022 [CA 4] Center 32 (2~63) winsize 62
2940 00:38:35.851628 [CA 5] Center 32 (2~63) winsize 62
2941 00:38:35.851711
2942 00:38:35.854821 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2943 00:38:35.854904
2944 00:38:35.858198 [CATrainingPosCal] consider 1 rank data
2945 00:38:35.861438 u2DelayCellTimex100 = 270/100 ps
2946 00:38:35.864795 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2947 00:38:35.868005 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2948 00:38:35.874696 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2949 00:38:35.878168 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2950 00:38:35.881499 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2951 00:38:35.884809 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2952 00:38:35.884893
2953 00:38:35.888008 CA PerBit enable=1, Macro0, CA PI delay=32
2954 00:38:35.888092
2955 00:38:35.891332 [CBTSetCACLKResult] CA Dly = 32
2956 00:38:35.891416 CS Dly: 6 (0~37)
2957 00:38:35.891499 ==
2958 00:38:35.894793 Dram Type= 6, Freq= 0, CH_1, rank 1
2959 00:38:35.901266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2960 00:38:35.901405 ==
2961 00:38:35.904836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2962 00:38:35.911708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2963 00:38:35.919974 [CA 0] Center 37 (7~68) winsize 62
2964 00:38:35.923227 [CA 1] Center 37 (6~68) winsize 63
2965 00:38:35.926912 [CA 2] Center 33 (3~64) winsize 62
2966 00:38:35.929874 [CA 3] Center 33 (3~64) winsize 62
2967 00:38:35.933170 [CA 4] Center 32 (2~63) winsize 62
2968 00:38:35.936547 [CA 5] Center 32 (2~62) winsize 61
2969 00:38:35.936629
2970 00:38:35.940215 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2971 00:38:35.940300
2972 00:38:35.943203 [CATrainingPosCal] consider 2 rank data
2973 00:38:35.946666 u2DelayCellTimex100 = 270/100 ps
2974 00:38:35.949941 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2975 00:38:35.956539 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2976 00:38:35.959884 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2977 00:38:35.963267 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2978 00:38:35.966555 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2979 00:38:35.969864 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2980 00:38:35.969948
2981 00:38:35.973247 CA PerBit enable=1, Macro0, CA PI delay=32
2982 00:38:35.973375
2983 00:38:35.976439 [CBTSetCACLKResult] CA Dly = 32
2984 00:38:35.976519 CS Dly: 6 (0~38)
2985 00:38:35.976584
2986 00:38:35.980047 ----->DramcWriteLeveling(PI) begin...
2987 00:38:35.983141 ==
2988 00:38:35.986263 Dram Type= 6, Freq= 0, CH_1, rank 0
2989 00:38:35.989800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2990 00:38:35.989882 ==
2991 00:38:35.992849 Write leveling (Byte 0): 20 => 20
2992 00:38:35.996123 Write leveling (Byte 1): 22 => 22
2993 00:38:35.999520 DramcWriteLeveling(PI) end<-----
2994 00:38:35.999601
2995 00:38:35.999665 ==
2996 00:38:36.002885 Dram Type= 6, Freq= 0, CH_1, rank 0
2997 00:38:36.006072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2998 00:38:36.006186 ==
2999 00:38:36.009556 [Gating] SW mode calibration
3000 00:38:36.016047 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3001 00:38:36.022796 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3002 00:38:36.025995 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3003 00:38:36.029339 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3004 00:38:36.035815 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3005 00:38:36.039216 0 11 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3006 00:38:36.042864 0 11 16 | B1->B0 | 2e2e 2727 | 1 0 | (1 0) (1 0)
3007 00:38:36.049458 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3008 00:38:36.052665 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3009 00:38:36.055937 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3010 00:38:36.062729 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3011 00:38:36.066087 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3012 00:38:36.069056 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3013 00:38:36.075872 0 12 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3014 00:38:36.079046 0 12 16 | B1->B0 | 2f2f 4242 | 0 0 | (1 1) (0 0)
3015 00:38:36.082335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3016 00:38:36.085810 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3017 00:38:36.092569 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3018 00:38:36.095940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3019 00:38:36.099196 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3020 00:38:36.106236 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3021 00:38:36.109253 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3022 00:38:36.112691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3023 00:38:36.119039 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3024 00:38:36.122365 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3025 00:38:36.125732 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3026 00:38:36.132289 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3027 00:38:36.135681 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3028 00:38:36.138916 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3029 00:38:36.145695 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3030 00:38:36.149129 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3031 00:38:36.152566 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3032 00:38:36.158972 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3033 00:38:36.162290 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3034 00:38:36.165544 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3035 00:38:36.172110 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3036 00:38:36.175610 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3037 00:38:36.178795 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3038 00:38:36.185451 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3039 00:38:36.189007 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3040 00:38:36.192282 Total UI for P1: 0, mck2ui 16
3041 00:38:36.195651 best dqsien dly found for B0: ( 0, 15, 14)
3042 00:38:36.198775 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3043 00:38:36.202133 Total UI for P1: 0, mck2ui 16
3044 00:38:36.205541 best dqsien dly found for B1: ( 0, 15, 18)
3045 00:38:36.208742 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3046 00:38:36.212344 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3047 00:38:36.212424
3048 00:38:36.215549 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3049 00:38:36.222292 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3050 00:38:36.222372 [Gating] SW calibration Done
3051 00:38:36.222435 ==
3052 00:38:36.225459 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 00:38:36.232208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3054 00:38:36.232289 ==
3055 00:38:36.232352 RX Vref Scan: 0
3056 00:38:36.232411
3057 00:38:36.235785 RX Vref 0 -> 0, step: 1
3058 00:38:36.235865
3059 00:38:36.238699 RX Delay -40 -> 252, step: 8
3060 00:38:36.242011 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3061 00:38:36.245596 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3062 00:38:36.248753 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3063 00:38:36.255342 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3064 00:38:36.258721 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3065 00:38:36.262120 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3066 00:38:36.265470 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3067 00:38:36.268680 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3068 00:38:36.272179 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3069 00:38:36.278889 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3070 00:38:36.282013 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3071 00:38:36.285670 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3072 00:38:36.288715 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3073 00:38:36.291990 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3074 00:38:36.298591 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3075 00:38:36.301959 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3076 00:38:36.302039 ==
3077 00:38:36.305267 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 00:38:36.308604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3079 00:38:36.308687 ==
3080 00:38:36.311892 DQS Delay:
3081 00:38:36.311973 DQS0 = 0, DQS1 = 0
3082 00:38:36.312036 DQM Delay:
3083 00:38:36.315440 DQM0 = 116, DQM1 = 109
3084 00:38:36.315520 DQ Delay:
3085 00:38:36.318643 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3086 00:38:36.322330 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3087 00:38:36.325459 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =99
3088 00:38:36.332127 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3089 00:38:36.332209
3090 00:38:36.332271
3091 00:38:36.332329 ==
3092 00:38:36.335615 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 00:38:36.338516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3094 00:38:36.338596 ==
3095 00:38:36.338660
3096 00:38:36.338719
3097 00:38:36.341879 TX Vref Scan disable
3098 00:38:36.341959 == TX Byte 0 ==
3099 00:38:36.348630 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3100 00:38:36.351870 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3101 00:38:36.351950 == TX Byte 1 ==
3102 00:38:36.358535 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3103 00:38:36.361933 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3104 00:38:36.362017 ==
3105 00:38:36.365354 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 00:38:36.368533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3107 00:38:36.368614 ==
3108 00:38:36.381060 TX Vref=22, minBit 1, minWin=25, winSum=414
3109 00:38:36.384373 TX Vref=24, minBit 1, minWin=25, winSum=415
3110 00:38:36.387734 TX Vref=26, minBit 15, minWin=25, winSum=421
3111 00:38:36.391083 TX Vref=28, minBit 3, minWin=26, winSum=425
3112 00:38:36.394436 TX Vref=30, minBit 0, minWin=26, winSum=428
3113 00:38:36.401045 TX Vref=32, minBit 9, minWin=26, winSum=430
3114 00:38:36.404657 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 32
3115 00:38:36.404747
3116 00:38:36.407693 Final TX Range 1 Vref 32
3117 00:38:36.407783
3118 00:38:36.407848 ==
3119 00:38:36.411236 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 00:38:36.414268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3121 00:38:36.414351 ==
3122 00:38:36.417952
3123 00:38:36.418035
3124 00:38:36.418099 TX Vref Scan disable
3125 00:38:36.421079 == TX Byte 0 ==
3126 00:38:36.424400 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3127 00:38:36.427875 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3128 00:38:36.431324 == TX Byte 1 ==
3129 00:38:36.434582 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3130 00:38:36.437779 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3131 00:38:36.437862
3132 00:38:36.441313 [DATLAT]
3133 00:38:36.441395 Freq=1200, CH1 RK0
3134 00:38:36.441460
3135 00:38:36.444672 DATLAT Default: 0xd
3136 00:38:36.444753 0, 0xFFFF, sum = 0
3137 00:38:36.447798 1, 0xFFFF, sum = 0
3138 00:38:36.447881 2, 0xFFFF, sum = 0
3139 00:38:36.451156 3, 0xFFFF, sum = 0
3140 00:38:36.451238 4, 0xFFFF, sum = 0
3141 00:38:36.454373 5, 0xFFFF, sum = 0
3142 00:38:36.454456 6, 0xFFFF, sum = 0
3143 00:38:36.457942 7, 0xFFFF, sum = 0
3144 00:38:36.461043 8, 0xFFFF, sum = 0
3145 00:38:36.461128 9, 0xFFFF, sum = 0
3146 00:38:36.464293 10, 0xFFFF, sum = 0
3147 00:38:36.464377 11, 0x0, sum = 1
3148 00:38:36.467655 12, 0x0, sum = 2
3149 00:38:36.467738 13, 0x0, sum = 3
3150 00:38:36.467803 14, 0x0, sum = 4
3151 00:38:36.471140 best_step = 12
3152 00:38:36.471221
3153 00:38:36.471285 ==
3154 00:38:36.474493 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 00:38:36.477870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3156 00:38:36.477951 ==
3157 00:38:36.481063 RX Vref Scan: 1
3158 00:38:36.481143
3159 00:38:36.484470 Set Vref Range= 32 -> 127
3160 00:38:36.484551
3161 00:38:36.484615 RX Vref 32 -> 127, step: 1
3162 00:38:36.484674
3163 00:38:36.487724 RX Delay -29 -> 252, step: 4
3164 00:38:36.487808
3165 00:38:36.491207 Set Vref, RX VrefLevel [Byte0]: 32
3166 00:38:36.494345 [Byte1]: 32
3167 00:38:36.497707
3168 00:38:36.497787 Set Vref, RX VrefLevel [Byte0]: 33
3169 00:38:36.500929 [Byte1]: 33
3170 00:38:36.505957
3171 00:38:36.506039 Set Vref, RX VrefLevel [Byte0]: 34
3172 00:38:36.508917 [Byte1]: 34
3173 00:38:36.513671
3174 00:38:36.513761 Set Vref, RX VrefLevel [Byte0]: 35
3175 00:38:36.516797 [Byte1]: 35
3176 00:38:36.521809
3177 00:38:36.521894 Set Vref, RX VrefLevel [Byte0]: 36
3178 00:38:36.524789 [Byte1]: 36
3179 00:38:36.529421
3180 00:38:36.529502 Set Vref, RX VrefLevel [Byte0]: 37
3181 00:38:36.533061 [Byte1]: 37
3182 00:38:36.537435
3183 00:38:36.537519 Set Vref, RX VrefLevel [Byte0]: 38
3184 00:38:36.540633 [Byte1]: 38
3185 00:38:36.545543
3186 00:38:36.545625 Set Vref, RX VrefLevel [Byte0]: 39
3187 00:38:36.548849 [Byte1]: 39
3188 00:38:36.553547
3189 00:38:36.553628 Set Vref, RX VrefLevel [Byte0]: 40
3190 00:38:36.556821 [Byte1]: 40
3191 00:38:36.561267
3192 00:38:36.561361 Set Vref, RX VrefLevel [Byte0]: 41
3193 00:38:36.564585 [Byte1]: 41
3194 00:38:36.569177
3195 00:38:36.569315 Set Vref, RX VrefLevel [Byte0]: 42
3196 00:38:36.572578 [Byte1]: 42
3197 00:38:36.577218
3198 00:38:36.577358 Set Vref, RX VrefLevel [Byte0]: 43
3199 00:38:36.580624 [Byte1]: 43
3200 00:38:36.585113
3201 00:38:36.585220 Set Vref, RX VrefLevel [Byte0]: 44
3202 00:38:36.588501 [Byte1]: 44
3203 00:38:36.593054
3204 00:38:36.593148 Set Vref, RX VrefLevel [Byte0]: 45
3205 00:38:36.596391 [Byte1]: 45
3206 00:38:36.601007
3207 00:38:36.601094 Set Vref, RX VrefLevel [Byte0]: 46
3208 00:38:36.604770 [Byte1]: 46
3209 00:38:36.609011
3210 00:38:36.609131 Set Vref, RX VrefLevel [Byte0]: 47
3211 00:38:36.612197 [Byte1]: 47
3212 00:38:36.617215
3213 00:38:36.617353 Set Vref, RX VrefLevel [Byte0]: 48
3214 00:38:36.620417 [Byte1]: 48
3215 00:38:36.624915
3216 00:38:36.624998 Set Vref, RX VrefLevel [Byte0]: 49
3217 00:38:36.628184 [Byte1]: 49
3218 00:38:36.632876
3219 00:38:36.632959 Set Vref, RX VrefLevel [Byte0]: 50
3220 00:38:36.636245 [Byte1]: 50
3221 00:38:36.640807
3222 00:38:36.640888 Set Vref, RX VrefLevel [Byte0]: 51
3223 00:38:36.644508 [Byte1]: 51
3224 00:38:36.648768
3225 00:38:36.648850 Set Vref, RX VrefLevel [Byte0]: 52
3226 00:38:36.652287 [Byte1]: 52
3227 00:38:36.656684
3228 00:38:36.656769 Set Vref, RX VrefLevel [Byte0]: 53
3229 00:38:36.660159 [Byte1]: 53
3230 00:38:36.664925
3231 00:38:36.665008 Set Vref, RX VrefLevel [Byte0]: 54
3232 00:38:36.668093 [Byte1]: 54
3233 00:38:36.672571
3234 00:38:36.672669 Set Vref, RX VrefLevel [Byte0]: 55
3235 00:38:36.675955 [Byte1]: 55
3236 00:38:36.680633
3237 00:38:36.680714 Set Vref, RX VrefLevel [Byte0]: 56
3238 00:38:36.683888 [Byte1]: 56
3239 00:38:36.689165
3240 00:38:36.689277 Set Vref, RX VrefLevel [Byte0]: 57
3241 00:38:36.691992 [Byte1]: 57
3242 00:38:36.696582
3243 00:38:36.696668 Set Vref, RX VrefLevel [Byte0]: 58
3244 00:38:36.699821 [Byte1]: 58
3245 00:38:36.704550
3246 00:38:36.704633 Set Vref, RX VrefLevel [Byte0]: 59
3247 00:38:36.707813 [Byte1]: 59
3248 00:38:36.712676
3249 00:38:36.712763 Set Vref, RX VrefLevel [Byte0]: 60
3250 00:38:36.716102 [Byte1]: 60
3251 00:38:36.720453
3252 00:38:36.720542 Set Vref, RX VrefLevel [Byte0]: 61
3253 00:38:36.723681 [Byte1]: 61
3254 00:38:36.728315
3255 00:38:36.728396 Set Vref, RX VrefLevel [Byte0]: 62
3256 00:38:36.731874 [Byte1]: 62
3257 00:38:36.736373
3258 00:38:36.736454 Set Vref, RX VrefLevel [Byte0]: 63
3259 00:38:36.739686 [Byte1]: 63
3260 00:38:36.744328
3261 00:38:36.744408 Set Vref, RX VrefLevel [Byte0]: 64
3262 00:38:36.747876 [Byte1]: 64
3263 00:38:36.752373
3264 00:38:36.752454 Set Vref, RX VrefLevel [Byte0]: 65
3265 00:38:36.755592 [Byte1]: 65
3266 00:38:36.760154
3267 00:38:36.760235 Set Vref, RX VrefLevel [Byte0]: 66
3268 00:38:36.763405 [Byte1]: 66
3269 00:38:36.768116
3270 00:38:36.768196 Final RX Vref Byte 0 = 56 to rank0
3271 00:38:36.771521 Final RX Vref Byte 1 = 48 to rank0
3272 00:38:36.774772 Final RX Vref Byte 0 = 56 to rank1
3273 00:38:36.778332 Final RX Vref Byte 1 = 48 to rank1==
3274 00:38:36.781503 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 00:38:36.788475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3276 00:38:36.788561 ==
3277 00:38:36.788626 DQS Delay:
3278 00:38:36.788684 DQS0 = 0, DQS1 = 0
3279 00:38:36.791707 DQM Delay:
3280 00:38:36.791786 DQM0 = 115, DQM1 = 105
3281 00:38:36.794956 DQ Delay:
3282 00:38:36.798142 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3283 00:38:36.801536 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3284 00:38:36.805077 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3285 00:38:36.808255 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3286 00:38:36.808336
3287 00:38:36.808400
3288 00:38:36.814941 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3289 00:38:36.818478 CH1 RK0: MR19=404, MR18=1414
3290 00:38:36.825156 CH1_RK0: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
3291 00:38:36.825238
3292 00:38:36.828386 ----->DramcWriteLeveling(PI) begin...
3293 00:38:36.828467 ==
3294 00:38:36.831674 Dram Type= 6, Freq= 0, CH_1, rank 1
3295 00:38:36.835095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3296 00:38:36.835176 ==
3297 00:38:36.838620 Write leveling (Byte 0): 21 => 21
3298 00:38:36.841900 Write leveling (Byte 1): 21 => 21
3299 00:38:36.844823 DramcWriteLeveling(PI) end<-----
3300 00:38:36.844902
3301 00:38:36.844965 ==
3302 00:38:36.848169 Dram Type= 6, Freq= 0, CH_1, rank 1
3303 00:38:36.854931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3304 00:38:36.855012 ==
3305 00:38:36.855076 [Gating] SW mode calibration
3306 00:38:36.864903 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3307 00:38:36.868187 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3308 00:38:36.871540 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3309 00:38:36.878467 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3310 00:38:36.881650 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3311 00:38:36.884776 0 11 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3312 00:38:36.891534 0 11 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3313 00:38:36.894961 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3314 00:38:36.898234 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3315 00:38:36.904869 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3316 00:38:36.908325 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3317 00:38:36.911546 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3318 00:38:36.918206 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3319 00:38:36.921610 0 12 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
3320 00:38:36.924776 0 12 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3321 00:38:36.931629 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3322 00:38:36.934874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3323 00:38:36.938180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3324 00:38:36.944849 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3325 00:38:36.948288 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3326 00:38:36.951865 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3327 00:38:36.955024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3328 00:38:36.961625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3329 00:38:36.964888 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3330 00:38:36.968829 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3331 00:38:36.974831 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3332 00:38:36.978319 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3333 00:38:36.981820 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3334 00:38:36.988215 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3335 00:38:36.991767 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3336 00:38:36.994799 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3337 00:38:37.001576 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3338 00:38:37.004884 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3339 00:38:37.008114 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3340 00:38:37.014749 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3341 00:38:37.018135 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 00:38:37.021328 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 00:38:37.028168 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3344 00:38:37.031335 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3345 00:38:37.034665 Total UI for P1: 0, mck2ui 16
3346 00:38:37.038054 best dqsien dly found for B0: ( 0, 15, 12)
3347 00:38:37.041682 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3348 00:38:37.044849 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 00:38:37.048264 Total UI for P1: 0, mck2ui 16
3350 00:38:37.051410 best dqsien dly found for B1: ( 0, 15, 18)
3351 00:38:37.058324 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3352 00:38:37.061308 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3353 00:38:37.061389
3354 00:38:37.065043 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3355 00:38:37.068334 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3356 00:38:37.071385 [Gating] SW calibration Done
3357 00:38:37.071464 ==
3358 00:38:37.074872 Dram Type= 6, Freq= 0, CH_1, rank 1
3359 00:38:37.078015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3360 00:38:37.078095 ==
3361 00:38:37.081548 RX Vref Scan: 0
3362 00:38:37.081629
3363 00:38:37.081691 RX Vref 0 -> 0, step: 1
3364 00:38:37.081750
3365 00:38:37.084735 RX Delay -40 -> 252, step: 8
3366 00:38:37.088117 iDelay=208, Bit 0, Center 115 (40 ~ 191) 152
3367 00:38:37.094576 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3368 00:38:37.098231 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3369 00:38:37.101237 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3370 00:38:37.104821 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3371 00:38:37.108174 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3372 00:38:37.111256 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3373 00:38:37.118027 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3374 00:38:37.121321 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3375 00:38:37.124693 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3376 00:38:37.127962 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3377 00:38:37.131298 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3378 00:38:37.137765 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3379 00:38:37.141275 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3380 00:38:37.144505 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3381 00:38:37.147822 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3382 00:38:37.147903 ==
3383 00:38:37.151130 Dram Type= 6, Freq= 0, CH_1, rank 1
3384 00:38:37.157866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3385 00:38:37.157949 ==
3386 00:38:37.158013 DQS Delay:
3387 00:38:37.158071 DQS0 = 0, DQS1 = 0
3388 00:38:37.161300 DQM Delay:
3389 00:38:37.161381 DQM0 = 115, DQM1 = 105
3390 00:38:37.164479 DQ Delay:
3391 00:38:37.167755 DQ0 =115, DQ1 =111, DQ2 =107, DQ3 =115
3392 00:38:37.171100 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3393 00:38:37.174415 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3394 00:38:37.177774 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3395 00:38:37.177854
3396 00:38:37.177916
3397 00:38:37.177974 ==
3398 00:38:37.181535 Dram Type= 6, Freq= 0, CH_1, rank 1
3399 00:38:37.184584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3400 00:38:37.184665 ==
3401 00:38:37.184729
3402 00:38:37.187810
3403 00:38:37.187890 TX Vref Scan disable
3404 00:38:37.191251 == TX Byte 0 ==
3405 00:38:37.194575 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3406 00:38:37.197994 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3407 00:38:37.201208 == TX Byte 1 ==
3408 00:38:37.204535 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3409 00:38:37.207761 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3410 00:38:37.207843 ==
3411 00:38:37.211241 Dram Type= 6, Freq= 0, CH_1, rank 1
3412 00:38:37.217720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3413 00:38:37.217802 ==
3414 00:38:37.228096 TX Vref=22, minBit 8, minWin=25, winSum=419
3415 00:38:37.231296 TX Vref=24, minBit 9, minWin=25, winSum=426
3416 00:38:37.234943 TX Vref=26, minBit 11, minWin=25, winSum=426
3417 00:38:37.237872 TX Vref=28, minBit 3, minWin=26, winSum=429
3418 00:38:37.241236 TX Vref=30, minBit 0, minWin=26, winSum=433
3419 00:38:37.247959 TX Vref=32, minBit 0, minWin=26, winSum=432
3420 00:38:37.251301 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
3421 00:38:37.251382
3422 00:38:37.254472 Final TX Range 1 Vref 30
3423 00:38:37.254553
3424 00:38:37.254616 ==
3425 00:38:37.257979 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 00:38:37.261134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3427 00:38:37.261216 ==
3428 00:38:37.264622
3429 00:38:37.264702
3430 00:38:37.264765 TX Vref Scan disable
3431 00:38:37.268054 == TX Byte 0 ==
3432 00:38:37.271170 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3433 00:38:37.277872 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3434 00:38:37.277955 == TX Byte 1 ==
3435 00:38:37.280961 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3436 00:38:37.287842 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3437 00:38:37.287925
3438 00:38:37.287988 [DATLAT]
3439 00:38:37.288047 Freq=1200, CH1 RK1
3440 00:38:37.288105
3441 00:38:37.290955 DATLAT Default: 0xc
3442 00:38:37.291043 0, 0xFFFF, sum = 0
3443 00:38:37.294595 1, 0xFFFF, sum = 0
3444 00:38:37.294676 2, 0xFFFF, sum = 0
3445 00:38:37.297780 3, 0xFFFF, sum = 0
3446 00:38:37.301221 4, 0xFFFF, sum = 0
3447 00:38:37.301325 5, 0xFFFF, sum = 0
3448 00:38:37.304383 6, 0xFFFF, sum = 0
3449 00:38:37.304464 7, 0xFFFF, sum = 0
3450 00:38:37.307721 8, 0xFFFF, sum = 0
3451 00:38:37.307836 9, 0xFFFF, sum = 0
3452 00:38:37.311044 10, 0xFFFF, sum = 0
3453 00:38:37.311126 11, 0x0, sum = 1
3454 00:38:37.314294 12, 0x0, sum = 2
3455 00:38:37.314375 13, 0x0, sum = 3
3456 00:38:37.317538 14, 0x0, sum = 4
3457 00:38:37.317619 best_step = 12
3458 00:38:37.317682
3459 00:38:37.317741 ==
3460 00:38:37.320998 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 00:38:37.324293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3462 00:38:37.324375 ==
3463 00:38:37.327560 RX Vref Scan: 0
3464 00:38:37.327640
3465 00:38:37.331036 RX Vref 0 -> 0, step: 1
3466 00:38:37.331116
3467 00:38:37.331180 RX Delay -29 -> 252, step: 4
3468 00:38:37.338225 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3469 00:38:37.341641 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3470 00:38:37.344958 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3471 00:38:37.348605 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3472 00:38:37.351775 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3473 00:38:37.358571 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3474 00:38:37.361656 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3475 00:38:37.364990 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3476 00:38:37.368294 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3477 00:38:37.371804 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3478 00:38:37.378575 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3479 00:38:37.381572 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3480 00:38:37.385025 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3481 00:38:37.388332 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3482 00:38:37.391622 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3483 00:38:37.398544 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3484 00:38:37.398625 ==
3485 00:38:37.401786 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 00:38:37.405168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3487 00:38:37.405304 ==
3488 00:38:37.405388 DQS Delay:
3489 00:38:37.408370 DQS0 = 0, DQS1 = 0
3490 00:38:37.408484 DQM Delay:
3491 00:38:37.411605 DQM0 = 115, DQM1 = 103
3492 00:38:37.411685 DQ Delay:
3493 00:38:37.414911 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3494 00:38:37.418449 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3495 00:38:37.421534 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3496 00:38:37.424997 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =110
3497 00:38:37.425077
3498 00:38:37.425140
3499 00:38:37.435134 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3500 00:38:37.435217 CH1 RK1: MR19=404, MR18=707
3501 00:38:37.441919 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3502 00:38:37.445089 [RxdqsGatingPostProcess] freq 1200
3503 00:38:37.451860 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3504 00:38:37.455158 Pre-setting of DQS Precalculation
3505 00:38:37.458246 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3506 00:38:37.468625 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3507 00:38:37.475160 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3508 00:38:37.475247
3509 00:38:37.475312
3510 00:38:37.478303 [Calibration Summary] 2400 Mbps
3511 00:38:37.478383 CH 0, Rank 0
3512 00:38:37.481855 SW Impedance : PASS
3513 00:38:37.481936 DUTY Scan : NO K
3514 00:38:37.484961 ZQ Calibration : PASS
3515 00:38:37.488057 Jitter Meter : NO K
3516 00:38:37.488138 CBT Training : PASS
3517 00:38:37.491698 Write leveling : PASS
3518 00:38:37.494969 RX DQS gating : PASS
3519 00:38:37.495050 RX DQ/DQS(RDDQC) : PASS
3520 00:38:37.498161 TX DQ/DQS : PASS
3521 00:38:37.498242 RX DATLAT : PASS
3522 00:38:37.501554 RX DQ/DQS(Engine): PASS
3523 00:38:37.505017 TX OE : NO K
3524 00:38:37.505098 All Pass.
3525 00:38:37.505161
3526 00:38:37.505220 CH 0, Rank 1
3527 00:38:37.508371 SW Impedance : PASS
3528 00:38:37.511672 DUTY Scan : NO K
3529 00:38:37.511753 ZQ Calibration : PASS
3530 00:38:37.515121 Jitter Meter : NO K
3531 00:38:37.518328 CBT Training : PASS
3532 00:38:37.518408 Write leveling : PASS
3533 00:38:37.521670 RX DQS gating : PASS
3534 00:38:37.524776 RX DQ/DQS(RDDQC) : PASS
3535 00:38:37.524856 TX DQ/DQS : PASS
3536 00:38:37.528168 RX DATLAT : PASS
3537 00:38:37.531716 RX DQ/DQS(Engine): PASS
3538 00:38:37.531795 TX OE : NO K
3539 00:38:37.534743 All Pass.
3540 00:38:37.534824
3541 00:38:37.534887 CH 1, Rank 0
3542 00:38:37.538069 SW Impedance : PASS
3543 00:38:37.538149 DUTY Scan : NO K
3544 00:38:37.541734 ZQ Calibration : PASS
3545 00:38:37.544974 Jitter Meter : NO K
3546 00:38:37.545052 CBT Training : PASS
3547 00:38:37.548072 Write leveling : PASS
3548 00:38:37.548150 RX DQS gating : PASS
3549 00:38:37.551551 RX DQ/DQS(RDDQC) : PASS
3550 00:38:37.554936 TX DQ/DQS : PASS
3551 00:38:37.555015 RX DATLAT : PASS
3552 00:38:37.558304 RX DQ/DQS(Engine): PASS
3553 00:38:37.561542 TX OE : NO K
3554 00:38:37.561621 All Pass.
3555 00:38:37.561683
3556 00:38:37.561741 CH 1, Rank 1
3557 00:38:37.564777 SW Impedance : PASS
3558 00:38:37.568082 DUTY Scan : NO K
3559 00:38:37.568161 ZQ Calibration : PASS
3560 00:38:37.571333 Jitter Meter : NO K
3561 00:38:37.574882 CBT Training : PASS
3562 00:38:37.574960 Write leveling : PASS
3563 00:38:37.578282 RX DQS gating : PASS
3564 00:38:37.581345 RX DQ/DQS(RDDQC) : PASS
3565 00:38:37.581438 TX DQ/DQS : PASS
3566 00:38:37.584657 RX DATLAT : PASS
3567 00:38:37.588025 RX DQ/DQS(Engine): PASS
3568 00:38:37.588115 TX OE : NO K
3569 00:38:37.588180 All Pass.
3570 00:38:37.591363
3571 00:38:37.591441 DramC Write-DBI off
3572 00:38:37.594912 PER_BANK_REFRESH: Hybrid Mode
3573 00:38:37.595031 TX_TRACKING: ON
3574 00:38:37.604917 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3575 00:38:37.608223 [FAST_K] Save calibration result to emmc
3576 00:38:37.611476 dramc_set_vcore_voltage set vcore to 650000
3577 00:38:37.614682 Read voltage for 600, 5
3578 00:38:37.614762 Vio18 = 0
3579 00:38:37.618108 Vcore = 650000
3580 00:38:37.618187 Vdram = 0
3581 00:38:37.618250 Vddq = 0
3582 00:38:37.618308 Vmddr = 0
3583 00:38:37.625131 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3584 00:38:37.628280 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3585 00:38:37.631357 MEM_TYPE=3, freq_sel=19
3586 00:38:37.634737 sv_algorithm_assistance_LP4_1600
3587 00:38:37.637807 ============ PULL DRAM RESETB DOWN ============
3588 00:38:37.644505 ========== PULL DRAM RESETB DOWN end =========
3589 00:38:37.647711 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3590 00:38:37.651206 ===================================
3591 00:38:37.654401 LPDDR4 DRAM CONFIGURATION
3592 00:38:37.657634 ===================================
3593 00:38:37.657715 EX_ROW_EN[0] = 0x0
3594 00:38:37.660871 EX_ROW_EN[1] = 0x0
3595 00:38:37.660951 LP4Y_EN = 0x0
3596 00:38:37.664229 WORK_FSP = 0x0
3597 00:38:37.664310 WL = 0x2
3598 00:38:37.667659 RL = 0x2
3599 00:38:37.670909 BL = 0x2
3600 00:38:37.670990 RPST = 0x0
3601 00:38:37.674310 RD_PRE = 0x0
3602 00:38:37.674390 WR_PRE = 0x1
3603 00:38:37.677513 WR_PST = 0x0
3604 00:38:37.677593 DBI_WR = 0x0
3605 00:38:37.680886 DBI_RD = 0x0
3606 00:38:37.681001 OTF = 0x1
3607 00:38:37.684307 ===================================
3608 00:38:37.687577 ===================================
3609 00:38:37.690883 ANA top config
3610 00:38:37.694113 ===================================
3611 00:38:37.694196 DLL_ASYNC_EN = 0
3612 00:38:37.697332 ALL_SLAVE_EN = 1
3613 00:38:37.700718 NEW_RANK_MODE = 1
3614 00:38:37.704094 DLL_IDLE_MODE = 1
3615 00:38:37.704198 LP45_APHY_COMB_EN = 1
3616 00:38:37.707396 TX_ODT_DIS = 1
3617 00:38:37.710509 NEW_8X_MODE = 1
3618 00:38:37.713982 ===================================
3619 00:38:37.717076 ===================================
3620 00:38:37.720479 data_rate = 1200
3621 00:38:37.723778 CKR = 1
3622 00:38:37.727109 DQ_P2S_RATIO = 8
3623 00:38:37.730374 ===================================
3624 00:38:37.730455 CA_P2S_RATIO = 8
3625 00:38:37.733796 DQ_CA_OPEN = 0
3626 00:38:37.737087 DQ_SEMI_OPEN = 0
3627 00:38:37.740412 CA_SEMI_OPEN = 0
3628 00:38:37.743618 CA_FULL_RATE = 0
3629 00:38:37.746864 DQ_CKDIV4_EN = 1
3630 00:38:37.746944 CA_CKDIV4_EN = 1
3631 00:38:37.750285 CA_PREDIV_EN = 0
3632 00:38:37.753542 PH8_DLY = 0
3633 00:38:37.756726 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3634 00:38:37.760048 DQ_AAMCK_DIV = 4
3635 00:38:37.763699 CA_AAMCK_DIV = 4
3636 00:38:37.763780 CA_ADMCK_DIV = 4
3637 00:38:37.766767 DQ_TRACK_CA_EN = 0
3638 00:38:37.770047 CA_PICK = 600
3639 00:38:37.773304 CA_MCKIO = 600
3640 00:38:37.776722 MCKIO_SEMI = 0
3641 00:38:37.780105 PLL_FREQ = 2288
3642 00:38:37.783413 DQ_UI_PI_RATIO = 32
3643 00:38:37.783493 CA_UI_PI_RATIO = 0
3644 00:38:37.786549 ===================================
3645 00:38:37.790175 ===================================
3646 00:38:37.793381 memory_type:LPDDR4
3647 00:38:37.796490 GP_NUM : 10
3648 00:38:37.796571 SRAM_EN : 1
3649 00:38:37.800018 MD32_EN : 0
3650 00:38:37.803365 ===================================
3651 00:38:37.806655 [ANA_INIT] >>>>>>>>>>>>>>
3652 00:38:37.809935 <<<<<< [CONFIGURE PHASE]: ANA_TX
3653 00:38:37.813345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3654 00:38:37.816630 ===================================
3655 00:38:37.816711 data_rate = 1200,PCW = 0X5800
3656 00:38:37.819817 ===================================
3657 00:38:37.823171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3658 00:38:37.830215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3659 00:38:37.836342 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3660 00:38:37.839680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3661 00:38:37.842832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3662 00:38:37.846398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3663 00:38:37.849696 [ANA_INIT] flow start
3664 00:38:37.852995 [ANA_INIT] PLL >>>>>>>>
3665 00:38:37.853076 [ANA_INIT] PLL <<<<<<<<
3666 00:38:37.856371 [ANA_INIT] MIDPI >>>>>>>>
3667 00:38:37.859708 [ANA_INIT] MIDPI <<<<<<<<
3668 00:38:37.859788 [ANA_INIT] DLL >>>>>>>>
3669 00:38:37.862829 [ANA_INIT] flow end
3670 00:38:37.866160 ============ LP4 DIFF to SE enter ============
3671 00:38:37.869559 ============ LP4 DIFF to SE exit ============
3672 00:38:37.872845 [ANA_INIT] <<<<<<<<<<<<<
3673 00:38:37.875978 [Flow] Enable top DCM control >>>>>
3674 00:38:37.879300 [Flow] Enable top DCM control <<<<<
3675 00:38:37.882598 Enable DLL master slave shuffle
3676 00:38:37.889270 ==============================================================
3677 00:38:37.889417 Gating Mode config
3678 00:38:37.896012 ==============================================================
3679 00:38:37.896096 Config description:
3680 00:38:37.906018 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3681 00:38:37.912627 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3682 00:38:37.919058 SELPH_MODE 0: By rank 1: By Phase
3683 00:38:37.925785 ==============================================================
3684 00:38:37.925869 GAT_TRACK_EN = 1
3685 00:38:37.929081 RX_GATING_MODE = 2
3686 00:38:37.932169 RX_GATING_TRACK_MODE = 2
3687 00:38:37.935427 SELPH_MODE = 1
3688 00:38:37.938831 PICG_EARLY_EN = 1
3689 00:38:37.942299 VALID_LAT_VALUE = 1
3690 00:38:37.948670 ==============================================================
3691 00:38:37.951960 Enter into Gating configuration >>>>
3692 00:38:37.955462 Exit from Gating configuration <<<<
3693 00:38:37.958611 Enter into DVFS_PRE_config >>>>>
3694 00:38:37.968704 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3695 00:38:37.971619 Exit from DVFS_PRE_config <<<<<
3696 00:38:37.975193 Enter into PICG configuration >>>>
3697 00:38:37.978187 Exit from PICG configuration <<<<
3698 00:38:37.981559 [RX_INPUT] configuration >>>>>
3699 00:38:37.984849 [RX_INPUT] configuration <<<<<
3700 00:38:37.988129 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3701 00:38:37.994642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3702 00:38:38.001586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3703 00:38:38.008240 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3704 00:38:38.011264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3705 00:38:38.017942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3706 00:38:38.021155 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3707 00:38:38.027761 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3708 00:38:38.031080 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3709 00:38:38.034454 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3710 00:38:38.037860 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3711 00:38:38.044475 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3712 00:38:38.047696 ===================================
3713 00:38:38.051759 LPDDR4 DRAM CONFIGURATION
3714 00:38:38.051839 ===================================
3715 00:38:38.054454 EX_ROW_EN[0] = 0x0
3716 00:38:38.057798 EX_ROW_EN[1] = 0x0
3717 00:38:38.057906 LP4Y_EN = 0x0
3718 00:38:38.061065 WORK_FSP = 0x0
3719 00:38:38.061145 WL = 0x2
3720 00:38:38.064556 RL = 0x2
3721 00:38:38.064635 BL = 0x2
3722 00:38:38.067575 RPST = 0x0
3723 00:38:38.067654 RD_PRE = 0x0
3724 00:38:38.071234 WR_PRE = 0x1
3725 00:38:38.071313 WR_PST = 0x0
3726 00:38:38.074124 DBI_WR = 0x0
3727 00:38:38.074281 DBI_RD = 0x0
3728 00:38:38.077327 OTF = 0x1
3729 00:38:38.080793 ===================================
3730 00:38:38.083990 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3731 00:38:38.087422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3732 00:38:38.094243 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 00:38:38.097415 ===================================
3734 00:38:38.097496 LPDDR4 DRAM CONFIGURATION
3735 00:38:38.100937 ===================================
3736 00:38:38.103865 EX_ROW_EN[0] = 0x10
3737 00:38:38.107531 EX_ROW_EN[1] = 0x0
3738 00:38:38.107614 LP4Y_EN = 0x0
3739 00:38:38.110484 WORK_FSP = 0x0
3740 00:38:38.110567 WL = 0x2
3741 00:38:38.113965 RL = 0x2
3742 00:38:38.114045 BL = 0x2
3743 00:38:38.117210 RPST = 0x0
3744 00:38:38.117341 RD_PRE = 0x0
3745 00:38:38.120514 WR_PRE = 0x1
3746 00:38:38.120593 WR_PST = 0x0
3747 00:38:38.123815 DBI_WR = 0x0
3748 00:38:38.123894 DBI_RD = 0x0
3749 00:38:38.127185 OTF = 0x1
3750 00:38:38.130423 ===================================
3751 00:38:38.136856 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3752 00:38:38.140260 nWR fixed to 30
3753 00:38:38.143554 [ModeRegInit_LP4] CH0 RK0
3754 00:38:38.143635 [ModeRegInit_LP4] CH0 RK1
3755 00:38:38.147092 [ModeRegInit_LP4] CH1 RK0
3756 00:38:38.150267 [ModeRegInit_LP4] CH1 RK1
3757 00:38:38.150347 match AC timing 16
3758 00:38:38.156951 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3759 00:38:38.160361 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3760 00:38:38.163597 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3761 00:38:38.170134 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3762 00:38:38.173241 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3763 00:38:38.173342 ==
3764 00:38:38.176513 Dram Type= 6, Freq= 0, CH_0, rank 0
3765 00:38:38.180064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3766 00:38:38.180146 ==
3767 00:38:38.186619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3768 00:38:38.193000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3769 00:38:38.196477 [CA 0] Center 35 (5~66) winsize 62
3770 00:38:38.199697 [CA 1] Center 35 (5~66) winsize 62
3771 00:38:38.203125 [CA 2] Center 34 (4~65) winsize 62
3772 00:38:38.206209 [CA 3] Center 34 (3~65) winsize 63
3773 00:38:38.209621 [CA 4] Center 33 (3~64) winsize 62
3774 00:38:38.212819 [CA 5] Center 33 (3~64) winsize 62
3775 00:38:38.212900
3776 00:38:38.216252 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3777 00:38:38.216334
3778 00:38:38.219588 [CATrainingPosCal] consider 1 rank data
3779 00:38:38.222812 u2DelayCellTimex100 = 270/100 ps
3780 00:38:38.226151 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3781 00:38:38.229643 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3782 00:38:38.232829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3783 00:38:38.236217 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3784 00:38:38.239589 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3785 00:38:38.246243 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3786 00:38:38.246325
3787 00:38:38.249403 CA PerBit enable=1, Macro0, CA PI delay=33
3788 00:38:38.249484
3789 00:38:38.252899 [CBTSetCACLKResult] CA Dly = 33
3790 00:38:38.252979 CS Dly: 4 (0~35)
3791 00:38:38.253046 ==
3792 00:38:38.256061 Dram Type= 6, Freq= 0, CH_0, rank 1
3793 00:38:38.259392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3794 00:38:38.262849 ==
3795 00:38:38.266033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3796 00:38:38.272678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3797 00:38:38.276137 [CA 0] Center 35 (5~66) winsize 62
3798 00:38:38.279212 [CA 1] Center 35 (5~66) winsize 62
3799 00:38:38.282832 [CA 2] Center 34 (4~65) winsize 62
3800 00:38:38.285761 [CA 3] Center 34 (4~65) winsize 62
3801 00:38:38.289084 [CA 4] Center 33 (3~64) winsize 62
3802 00:38:38.292659 [CA 5] Center 33 (3~64) winsize 62
3803 00:38:38.292740
3804 00:38:38.295859 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3805 00:38:38.295940
3806 00:38:38.298819 [CATrainingPosCal] consider 2 rank data
3807 00:38:38.302219 u2DelayCellTimex100 = 270/100 ps
3808 00:38:38.305633 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3809 00:38:38.308761 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3810 00:38:38.315438 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3811 00:38:38.318602 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3812 00:38:38.321972 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3813 00:38:38.325270 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3814 00:38:38.325391
3815 00:38:38.328628 CA PerBit enable=1, Macro0, CA PI delay=33
3816 00:38:38.328708
3817 00:38:38.332034 [CBTSetCACLKResult] CA Dly = 33
3818 00:38:38.332114 CS Dly: 4 (0~36)
3819 00:38:38.332181
3820 00:38:38.335496 ----->DramcWriteLeveling(PI) begin...
3821 00:38:38.338525 ==
3822 00:38:38.341773 Dram Type= 6, Freq= 0, CH_0, rank 0
3823 00:38:38.345226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3824 00:38:38.345331 ==
3825 00:38:38.348410 Write leveling (Byte 0): 30 => 30
3826 00:38:38.351652 Write leveling (Byte 1): 30 => 30
3827 00:38:38.355007 DramcWriteLeveling(PI) end<-----
3828 00:38:38.355087
3829 00:38:38.355149 ==
3830 00:38:38.358427 Dram Type= 6, Freq= 0, CH_0, rank 0
3831 00:38:38.361763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3832 00:38:38.361844 ==
3833 00:38:38.365207 [Gating] SW mode calibration
3834 00:38:38.371662 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3835 00:38:38.378219 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3836 00:38:38.381492 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3837 00:38:38.384800 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3838 00:38:38.391404 0 5 8 | B1->B0 | 3232 3131 | 1 0 | (1 0) (1 1)
3839 00:38:38.394868 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
3840 00:38:38.398319 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3841 00:38:38.404598 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3842 00:38:38.408374 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3843 00:38:38.411405 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3844 00:38:38.415108 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3845 00:38:38.421510 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3846 00:38:38.424715 0 6 8 | B1->B0 | 2929 3232 | 0 0 | (1 1) (0 0)
3847 00:38:38.428241 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3848 00:38:38.434578 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3849 00:38:38.438083 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3850 00:38:38.441795 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3851 00:38:38.448039 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3852 00:38:38.451238 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3853 00:38:38.454461 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3854 00:38:38.461245 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3855 00:38:38.464463 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3856 00:38:38.467944 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3857 00:38:38.474423 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3858 00:38:38.477757 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3859 00:38:38.481026 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3860 00:38:38.487764 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3861 00:38:38.491236 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3862 00:38:38.494412 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3863 00:38:38.501240 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3864 00:38:38.504326 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3865 00:38:38.507962 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 00:38:38.514199 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 00:38:38.517574 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 00:38:38.520762 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 00:38:38.527335 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 00:38:38.530655 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3871 00:38:38.534108 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 00:38:38.537506 Total UI for P1: 0, mck2ui 16
3873 00:38:38.540511 best dqsien dly found for B0: ( 0, 9, 10)
3874 00:38:38.543922 Total UI for P1: 0, mck2ui 16
3875 00:38:38.547060 best dqsien dly found for B1: ( 0, 9, 8)
3876 00:38:38.550532 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3877 00:38:38.553871 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3878 00:38:38.553952
3879 00:38:38.560601 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3880 00:38:38.563909 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3881 00:38:38.563990 [Gating] SW calibration Done
3882 00:38:38.567303 ==
3883 00:38:38.570282 Dram Type= 6, Freq= 0, CH_0, rank 0
3884 00:38:38.573824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3885 00:38:38.573905 ==
3886 00:38:38.573970 RX Vref Scan: 0
3887 00:38:38.574029
3888 00:38:38.577013 RX Vref 0 -> 0, step: 1
3889 00:38:38.577094
3890 00:38:38.580327 RX Delay -230 -> 252, step: 16
3891 00:38:38.583791 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3892 00:38:38.587343 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3893 00:38:38.593818 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3894 00:38:38.597061 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3895 00:38:38.600330 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3896 00:38:38.603574 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3897 00:38:38.607010 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3898 00:38:38.613561 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3899 00:38:38.616781 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3900 00:38:38.620355 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3901 00:38:38.623403 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3902 00:38:38.629967 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3903 00:38:38.633436 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3904 00:38:38.636833 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3905 00:38:38.640129 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3906 00:38:38.646542 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3907 00:38:38.646623 ==
3908 00:38:38.649844 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 00:38:38.653235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3910 00:38:38.653323 ==
3911 00:38:38.653387 DQS Delay:
3912 00:38:38.656599 DQS0 = 0, DQS1 = 0
3913 00:38:38.656679 DQM Delay:
3914 00:38:38.659762 DQM0 = 39, DQM1 = 33
3915 00:38:38.659844 DQ Delay:
3916 00:38:38.663435 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3917 00:38:38.666590 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3918 00:38:38.669953 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3919 00:38:38.673243 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3920 00:38:38.673379
3921 00:38:38.673443
3922 00:38:38.673502 ==
3923 00:38:38.676706 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 00:38:38.680183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3925 00:38:38.680340 ==
3926 00:38:38.683253
3927 00:38:38.683401
3928 00:38:38.683485 TX Vref Scan disable
3929 00:38:38.686636 == TX Byte 0 ==
3930 00:38:38.689791 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3931 00:38:38.693225 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3932 00:38:38.696677 == TX Byte 1 ==
3933 00:38:38.699865 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3934 00:38:38.703301 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3935 00:38:38.706349 ==
3936 00:38:38.706467 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 00:38:38.713272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3938 00:38:38.713476 ==
3939 00:38:38.713552
3940 00:38:38.713618
3941 00:38:38.716689 TX Vref Scan disable
3942 00:38:38.716851 == TX Byte 0 ==
3943 00:38:38.723014 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3944 00:38:38.726335 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3945 00:38:38.726513 == TX Byte 1 ==
3946 00:38:38.732760 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3947 00:38:38.736524 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3948 00:38:38.736721
3949 00:38:38.736826 [DATLAT]
3950 00:38:38.739658 Freq=600, CH0 RK0
3951 00:38:38.739870
3952 00:38:38.739989 DATLAT Default: 0x9
3953 00:38:38.742801 0, 0xFFFF, sum = 0
3954 00:38:38.743072 1, 0xFFFF, sum = 0
3955 00:38:38.746403 2, 0xFFFF, sum = 0
3956 00:38:38.746635 3, 0xFFFF, sum = 0
3957 00:38:38.749498 4, 0xFFFF, sum = 0
3958 00:38:38.749750 5, 0xFFFF, sum = 0
3959 00:38:38.752822 6, 0xFFFF, sum = 0
3960 00:38:38.752995 7, 0x0, sum = 1
3961 00:38:38.756375 8, 0x0, sum = 2
3962 00:38:38.756656 9, 0x0, sum = 3
3963 00:38:38.760040 10, 0x0, sum = 4
3964 00:38:38.760368 best_step = 8
3965 00:38:38.760564
3966 00:38:38.760743 ==
3967 00:38:38.763065 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 00:38:38.769577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3969 00:38:38.770047 ==
3970 00:38:38.770353 RX Vref Scan: 1
3971 00:38:38.770635
3972 00:38:38.772895 RX Vref 0 -> 0, step: 1
3973 00:38:38.773327
3974 00:38:38.776630 RX Delay -195 -> 252, step: 8
3975 00:38:38.777099
3976 00:38:38.779633 Set Vref, RX VrefLevel [Byte0]: 53
3977 00:38:38.782921 [Byte1]: 50
3978 00:38:38.783004
3979 00:38:38.786067 Final RX Vref Byte 0 = 53 to rank0
3980 00:38:38.789247 Final RX Vref Byte 1 = 50 to rank0
3981 00:38:38.792395 Final RX Vref Byte 0 = 53 to rank1
3982 00:38:38.795708 Final RX Vref Byte 1 = 50 to rank1==
3983 00:38:38.799162 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 00:38:38.802362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3985 00:38:38.802474 ==
3986 00:38:38.805815 DQS Delay:
3987 00:38:38.805917 DQS0 = 0, DQS1 = 0
3988 00:38:38.805991 DQM Delay:
3989 00:38:38.809136 DQM0 = 40, DQM1 = 30
3990 00:38:38.809233 DQ Delay:
3991 00:38:38.812353 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3992 00:38:38.815813 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =52
3993 00:38:38.818960 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
3994 00:38:38.822127 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3995 00:38:38.822214
3996 00:38:38.822278
3997 00:38:38.832313 [DQSOSCAuto] RK0, (LSB)MR18= 0x5353, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3998 00:38:38.836140 CH0 RK0: MR19=808, MR18=5353
3999 00:38:38.838871 CH0_RK0: MR19=0x808, MR18=0x5353, DQSOSC=394, MR23=63, INC=168, DEC=112
4000 00:38:38.838954
4001 00:38:38.842125 ----->DramcWriteLeveling(PI) begin...
4002 00:38:38.845325 ==
4003 00:38:38.848761 Dram Type= 6, Freq= 0, CH_0, rank 1
4004 00:38:38.852222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4005 00:38:38.852301 ==
4006 00:38:38.855560 Write leveling (Byte 0): 32 => 32
4007 00:38:38.858809 Write leveling (Byte 1): 29 => 29
4008 00:38:38.861997 DramcWriteLeveling(PI) end<-----
4009 00:38:38.862076
4010 00:38:38.862138 ==
4011 00:38:38.865241 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 00:38:38.868563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4013 00:38:38.868658 ==
4014 00:38:38.871966 [Gating] SW mode calibration
4015 00:38:38.878565 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4016 00:38:38.884969 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4017 00:38:38.888536 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 00:38:38.891965 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 00:38:38.898421 0 5 8 | B1->B0 | 3232 3434 | 1 0 | (1 0) (0 1)
4020 00:38:38.901779 0 5 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4021 00:38:38.905090 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 00:38:38.911564 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 00:38:38.914973 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 00:38:38.918167 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 00:38:38.924834 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 00:38:38.928158 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 00:38:38.931419 0 6 8 | B1->B0 | 2929 3535 | 0 0 | (1 1) (0 0)
4028 00:38:38.934811 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 00:38:38.941254 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 00:38:38.944800 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 00:38:38.948318 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 00:38:38.954584 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 00:38:38.958039 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 00:38:38.961097 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 00:38:38.968083 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4036 00:38:38.971097 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 00:38:38.974398 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 00:38:38.981198 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 00:38:38.984532 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 00:38:38.988049 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 00:38:38.994601 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 00:38:38.997821 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 00:38:39.000890 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 00:38:39.007717 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 00:38:39.011022 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 00:38:39.014431 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 00:38:39.021113 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 00:38:39.024066 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 00:38:39.027534 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 00:38:39.034380 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 00:38:39.037542 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4052 00:38:39.041054 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 00:38:39.044256 Total UI for P1: 0, mck2ui 16
4054 00:38:39.047419 best dqsien dly found for B0: ( 0, 9, 8)
4055 00:38:39.050674 Total UI for P1: 0, mck2ui 16
4056 00:38:39.054392 best dqsien dly found for B1: ( 0, 9, 10)
4057 00:38:39.057398 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4058 00:38:39.060840 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4059 00:38:39.060920
4060 00:38:39.067446 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4061 00:38:39.070666 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4062 00:38:39.070747 [Gating] SW calibration Done
4063 00:38:39.074083 ==
4064 00:38:39.077255 Dram Type= 6, Freq= 0, CH_0, rank 1
4065 00:38:39.080533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4066 00:38:39.080613 ==
4067 00:38:39.080676 RX Vref Scan: 0
4068 00:38:39.080735
4069 00:38:39.083797 RX Vref 0 -> 0, step: 1
4070 00:38:39.083878
4071 00:38:39.087010 RX Delay -230 -> 252, step: 16
4072 00:38:39.090497 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4073 00:38:39.093804 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4074 00:38:39.100346 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4075 00:38:39.103723 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4076 00:38:39.106893 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4077 00:38:39.110169 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4078 00:38:39.117092 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4079 00:38:39.120297 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4080 00:38:39.123538 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4081 00:38:39.126751 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4082 00:38:39.130226 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4083 00:38:39.136808 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4084 00:38:39.140001 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4085 00:38:39.143264 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4086 00:38:39.150120 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4087 00:38:39.153417 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4088 00:38:39.153498 ==
4089 00:38:39.156712 Dram Type= 6, Freq= 0, CH_0, rank 1
4090 00:38:39.159854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4091 00:38:39.159952 ==
4092 00:38:39.160041 DQS Delay:
4093 00:38:39.163391 DQS0 = 0, DQS1 = 0
4094 00:38:39.163475 DQM Delay:
4095 00:38:39.166624 DQM0 = 40, DQM1 = 33
4096 00:38:39.166726 DQ Delay:
4097 00:38:39.169873 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4098 00:38:39.173281 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4099 00:38:39.176631 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4100 00:38:39.180191 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4101 00:38:39.180275
4102 00:38:39.180338
4103 00:38:39.180396 ==
4104 00:38:39.183167 Dram Type= 6, Freq= 0, CH_0, rank 1
4105 00:38:39.186970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4106 00:38:39.189966 ==
4107 00:38:39.190075
4108 00:38:39.190169
4109 00:38:39.190244 TX Vref Scan disable
4110 00:38:39.193250 == TX Byte 0 ==
4111 00:38:39.196905 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4112 00:38:39.203225 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4113 00:38:39.203382 == TX Byte 1 ==
4114 00:38:39.206657 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4115 00:38:39.213238 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4116 00:38:39.213440 ==
4117 00:38:39.216534 Dram Type= 6, Freq= 0, CH_0, rank 1
4118 00:38:39.219725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4119 00:38:39.219934 ==
4120 00:38:39.220109
4121 00:38:39.220234
4122 00:38:39.223483 TX Vref Scan disable
4123 00:38:39.226309 == TX Byte 0 ==
4124 00:38:39.229649 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4125 00:38:39.232883 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4126 00:38:39.236320 == TX Byte 1 ==
4127 00:38:39.239504 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4128 00:38:39.243106 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4129 00:38:39.243361
4130 00:38:39.243514 [DATLAT]
4131 00:38:39.246361 Freq=600, CH0 RK1
4132 00:38:39.246644
4133 00:38:39.249916 DATLAT Default: 0x8
4134 00:38:39.250270 0, 0xFFFF, sum = 0
4135 00:38:39.253052 1, 0xFFFF, sum = 0
4136 00:38:39.253317 2, 0xFFFF, sum = 0
4137 00:38:39.256554 3, 0xFFFF, sum = 0
4138 00:38:39.256942 4, 0xFFFF, sum = 0
4139 00:38:39.259779 5, 0xFFFF, sum = 0
4140 00:38:39.260260 6, 0xFFFF, sum = 0
4141 00:38:39.263455 7, 0x0, sum = 1
4142 00:38:39.263951 8, 0x0, sum = 2
4143 00:38:39.266366 9, 0x0, sum = 3
4144 00:38:39.266783 10, 0x0, sum = 4
4145 00:38:39.267114 best_step = 8
4146 00:38:39.267415
4147 00:38:39.270009 ==
4148 00:38:39.272976 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 00:38:39.276496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4150 00:38:39.277006 ==
4151 00:38:39.277374 RX Vref Scan: 0
4152 00:38:39.277682
4153 00:38:39.279677 RX Vref 0 -> 0, step: 1
4154 00:38:39.280184
4155 00:38:39.282554 RX Delay -195 -> 252, step: 8
4156 00:38:39.289440 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4157 00:38:39.292553 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4158 00:38:39.295835 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4159 00:38:39.299343 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4160 00:38:39.306071 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4161 00:38:39.309357 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4162 00:38:39.312245 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4163 00:38:39.316191 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4164 00:38:39.319420 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4165 00:38:39.326141 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4166 00:38:39.329141 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4167 00:38:39.332180 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4168 00:38:39.335706 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4169 00:38:39.342577 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4170 00:38:39.345762 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4171 00:38:39.349179 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4172 00:38:39.349723 ==
4173 00:38:39.352155 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 00:38:39.355366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4175 00:38:39.358823 ==
4176 00:38:39.359330 DQS Delay:
4177 00:38:39.359662 DQS0 = 0, DQS1 = 0
4178 00:38:39.362257 DQM Delay:
4179 00:38:39.362852 DQM0 = 41, DQM1 = 31
4180 00:38:39.365529 DQ Delay:
4181 00:38:39.365941 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
4182 00:38:39.368922 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4183 00:38:39.372259 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4184 00:38:39.375333 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4185 00:38:39.375841
4186 00:38:39.378866
4187 00:38:39.385118 [DQSOSCAuto] RK1, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4188 00:38:39.388652 CH0 RK1: MR19=808, MR18=7272
4189 00:38:39.394944 CH0_RK1: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4190 00:38:39.398285 [RxdqsGatingPostProcess] freq 600
4191 00:38:39.401683 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4192 00:38:39.405266 Pre-setting of DQS Precalculation
4193 00:38:39.411904 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4194 00:38:39.412413 ==
4195 00:38:39.415324 Dram Type= 6, Freq= 0, CH_1, rank 0
4196 00:38:39.418324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4197 00:38:39.418831 ==
4198 00:38:39.425032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4199 00:38:39.428213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4200 00:38:39.432755 [CA 0] Center 35 (5~66) winsize 62
4201 00:38:39.435910 [CA 1] Center 35 (5~66) winsize 62
4202 00:38:39.439262 [CA 2] Center 33 (3~64) winsize 62
4203 00:38:39.442631 [CA 3] Center 33 (3~64) winsize 62
4204 00:38:39.445840 [CA 4] Center 33 (2~64) winsize 63
4205 00:38:39.449573 [CA 5] Center 33 (2~64) winsize 63
4206 00:38:39.450085
4207 00:38:39.452984 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4208 00:38:39.453535
4209 00:38:39.455588 [CATrainingPosCal] consider 1 rank data
4210 00:38:39.459375 u2DelayCellTimex100 = 270/100 ps
4211 00:38:39.462515 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4212 00:38:39.465756 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4213 00:38:39.472793 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4214 00:38:39.475713 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4215 00:38:39.479082 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4216 00:38:39.482259 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4217 00:38:39.482780
4218 00:38:39.485453 CA PerBit enable=1, Macro0, CA PI delay=33
4219 00:38:39.485869
4220 00:38:39.489208 [CBTSetCACLKResult] CA Dly = 33
4221 00:38:39.489763 CS Dly: 4 (0~35)
4222 00:38:39.492304 ==
4223 00:38:39.495568 Dram Type= 6, Freq= 0, CH_1, rank 1
4224 00:38:39.499020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4225 00:38:39.499538 ==
4226 00:38:39.502037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4227 00:38:39.508989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4228 00:38:39.512584 [CA 0] Center 35 (5~66) winsize 62
4229 00:38:39.515655 [CA 1] Center 34 (4~65) winsize 62
4230 00:38:39.519237 [CA 2] Center 33 (3~64) winsize 62
4231 00:38:39.522705 [CA 3] Center 33 (2~64) winsize 63
4232 00:38:39.525602 [CA 4] Center 33 (2~64) winsize 63
4233 00:38:39.529534 [CA 5] Center 33 (2~64) winsize 63
4234 00:38:39.530175
4235 00:38:39.532333 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4236 00:38:39.532746
4237 00:38:39.535776 [CATrainingPosCal] consider 2 rank data
4238 00:38:39.539294 u2DelayCellTimex100 = 270/100 ps
4239 00:38:39.542085 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4240 00:38:39.548905 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4241 00:38:39.552495 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4242 00:38:39.555556 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4243 00:38:39.558428 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4244 00:38:39.562171 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4245 00:38:39.562680
4246 00:38:39.565360 CA PerBit enable=1, Macro0, CA PI delay=33
4247 00:38:39.565874
4248 00:38:39.568808 [CBTSetCACLKResult] CA Dly = 33
4249 00:38:39.571879 CS Dly: 4 (0~36)
4250 00:38:39.572390
4251 00:38:39.574907 ----->DramcWriteLeveling(PI) begin...
4252 00:38:39.575341 ==
4253 00:38:39.578522 Dram Type= 6, Freq= 0, CH_1, rank 0
4254 00:38:39.582302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4255 00:38:39.582812 ==
4256 00:38:39.585440 Write leveling (Byte 0): 29 => 29
4257 00:38:39.588632 Write leveling (Byte 1): 29 => 29
4258 00:38:39.591561 DramcWriteLeveling(PI) end<-----
4259 00:38:39.591976
4260 00:38:39.592305 ==
4261 00:38:39.595094 Dram Type= 6, Freq= 0, CH_1, rank 0
4262 00:38:39.598369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4263 00:38:39.598878 ==
4264 00:38:39.601526 [Gating] SW mode calibration
4265 00:38:39.608050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4266 00:38:39.615233 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4267 00:38:39.618099 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4268 00:38:39.621672 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4269 00:38:39.628362 0 5 8 | B1->B0 | 3030 2a2a | 0 0 | (1 0) (0 0)
4270 00:38:39.631547 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 00:38:39.635117 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 00:38:39.641444 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 00:38:39.644613 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 00:38:39.648323 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 00:38:39.654611 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 00:38:39.657974 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4277 00:38:39.661532 0 6 8 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
4278 00:38:39.668359 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 00:38:39.671278 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 00:38:39.674390 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 00:38:39.681560 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 00:38:39.684741 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 00:38:39.687941 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 00:38:39.694248 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4285 00:38:39.697673 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4286 00:38:39.701281 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 00:38:39.708011 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 00:38:39.711185 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 00:38:39.714214 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 00:38:39.721153 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 00:38:39.724306 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 00:38:39.727475 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 00:38:39.731428 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 00:38:39.737547 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 00:38:39.740874 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 00:38:39.744023 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 00:38:39.750709 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 00:38:39.754091 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 00:38:39.757647 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 00:38:39.764181 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4301 00:38:39.767139 Total UI for P1: 0, mck2ui 16
4302 00:38:39.770627 best dqsien dly found for B0: ( 0, 9, 2)
4303 00:38:39.774160 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 00:38:39.777859 Total UI for P1: 0, mck2ui 16
4305 00:38:39.780730 best dqsien dly found for B1: ( 0, 9, 6)
4306 00:38:39.784043 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4307 00:38:39.787473 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4308 00:38:39.787981
4309 00:38:39.790601 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4310 00:38:39.793809 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4311 00:38:39.797648 [Gating] SW calibration Done
4312 00:38:39.798156 ==
4313 00:38:39.800441 Dram Type= 6, Freq= 0, CH_1, rank 0
4314 00:38:39.803947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4315 00:38:39.807432 ==
4316 00:38:39.807943 RX Vref Scan: 0
4317 00:38:39.808274
4318 00:38:39.810234 RX Vref 0 -> 0, step: 1
4319 00:38:39.810647
4320 00:38:39.814126 RX Delay -230 -> 252, step: 16
4321 00:38:39.817350 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4322 00:38:39.820598 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4323 00:38:39.823679 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4324 00:38:39.830360 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4325 00:38:39.833693 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4326 00:38:39.837103 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4327 00:38:39.840360 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4328 00:38:39.847297 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4329 00:38:39.849940 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4330 00:38:39.853470 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4331 00:38:39.856827 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4332 00:38:39.860124 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4333 00:38:39.866686 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4334 00:38:39.869720 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4335 00:38:39.873343 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4336 00:38:39.876754 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4337 00:38:39.880096 ==
4338 00:38:39.880612 Dram Type= 6, Freq= 0, CH_1, rank 0
4339 00:38:39.886686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4340 00:38:39.887187 ==
4341 00:38:39.887515 DQS Delay:
4342 00:38:39.889684 DQS0 = 0, DQS1 = 0
4343 00:38:39.890098 DQM Delay:
4344 00:38:39.892996 DQM0 = 39, DQM1 = 30
4345 00:38:39.893445 DQ Delay:
4346 00:38:39.896366 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4347 00:38:39.899770 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4348 00:38:39.902815 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4349 00:38:39.906486 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4350 00:38:39.906988
4351 00:38:39.907313
4352 00:38:39.907608 ==
4353 00:38:39.910009 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 00:38:39.913336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4355 00:38:39.913858 ==
4356 00:38:39.914190
4357 00:38:39.914490
4358 00:38:39.915974 TX Vref Scan disable
4359 00:38:39.919511 == TX Byte 0 ==
4360 00:38:39.922753 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4361 00:38:39.926478 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4362 00:38:39.929451 == TX Byte 1 ==
4363 00:38:39.932708 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4364 00:38:39.936233 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4365 00:38:39.936742 ==
4366 00:38:39.940106 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 00:38:39.946296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4368 00:38:39.946806 ==
4369 00:38:39.947136
4370 00:38:39.947436
4371 00:38:39.947721 TX Vref Scan disable
4372 00:38:39.950341 == TX Byte 0 ==
4373 00:38:39.953801 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4374 00:38:39.960268 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4375 00:38:39.960776 == TX Byte 1 ==
4376 00:38:39.963909 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4377 00:38:39.971081 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4378 00:38:39.971587
4379 00:38:39.971916 [DATLAT]
4380 00:38:39.972216 Freq=600, CH1 RK0
4381 00:38:39.972507
4382 00:38:39.973378 DATLAT Default: 0x9
4383 00:38:39.973729 0, 0xFFFF, sum = 0
4384 00:38:39.977125 1, 0xFFFF, sum = 0
4385 00:38:39.977585 2, 0xFFFF, sum = 0
4386 00:38:39.980006 3, 0xFFFF, sum = 0
4387 00:38:39.983443 4, 0xFFFF, sum = 0
4388 00:38:39.983963 5, 0xFFFF, sum = 0
4389 00:38:39.986381 6, 0xFFFF, sum = 0
4390 00:38:39.986799 7, 0x0, sum = 1
4391 00:38:39.989829 8, 0x0, sum = 2
4392 00:38:39.990363 9, 0x0, sum = 3
4393 00:38:39.990700 10, 0x0, sum = 4
4394 00:38:39.993152 best_step = 8
4395 00:38:39.993587
4396 00:38:39.993914 ==
4397 00:38:39.996448 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 00:38:39.999616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4399 00:38:40.000033 ==
4400 00:38:40.003467 RX Vref Scan: 1
4401 00:38:40.003973
4402 00:38:40.004300 RX Vref 0 -> 0, step: 1
4403 00:38:40.004607
4404 00:38:40.006555 RX Delay -195 -> 252, step: 8
4405 00:38:40.007065
4406 00:38:40.009920 Set Vref, RX VrefLevel [Byte0]: 56
4407 00:38:40.012920 [Byte1]: 48
4408 00:38:40.017711
4409 00:38:40.018209 Final RX Vref Byte 0 = 56 to rank0
4410 00:38:40.020865 Final RX Vref Byte 1 = 48 to rank0
4411 00:38:40.024060 Final RX Vref Byte 0 = 56 to rank1
4412 00:38:40.026946 Final RX Vref Byte 1 = 48 to rank1==
4413 00:38:40.030718 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 00:38:40.037382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4415 00:38:40.037886 ==
4416 00:38:40.038223 DQS Delay:
4417 00:38:40.038526 DQS0 = 0, DQS1 = 0
4418 00:38:40.040252 DQM Delay:
4419 00:38:40.040662 DQM0 = 37, DQM1 = 30
4420 00:38:40.044017 DQ Delay:
4421 00:38:40.047115 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4422 00:38:40.050347 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4423 00:38:40.050764 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4424 00:38:40.057442 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4425 00:38:40.057942
4426 00:38:40.058269
4427 00:38:40.063844 [DQSOSCAuto] RK0, (LSB)MR18= 0x7575, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4428 00:38:40.067348 CH1 RK0: MR19=808, MR18=7575
4429 00:38:40.074014 CH1_RK0: MR19=0x808, MR18=0x7575, DQSOSC=387, MR23=63, INC=175, DEC=116
4430 00:38:40.074591
4431 00:38:40.077134 ----->DramcWriteLeveling(PI) begin...
4432 00:38:40.077679 ==
4433 00:38:40.080224 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 00:38:40.083522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4435 00:38:40.084040 ==
4436 00:38:40.086557 Write leveling (Byte 0): 29 => 29
4437 00:38:40.090050 Write leveling (Byte 1): 28 => 28
4438 00:38:40.093232 DramcWriteLeveling(PI) end<-----
4439 00:38:40.093702
4440 00:38:40.094033 ==
4441 00:38:40.096746 Dram Type= 6, Freq= 0, CH_1, rank 1
4442 00:38:40.100469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4443 00:38:40.100980 ==
4444 00:38:40.103945 [Gating] SW mode calibration
4445 00:38:40.110172 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4446 00:38:40.116853 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4447 00:38:40.120193 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 00:38:40.126561 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
4449 00:38:40.129835 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 1)
4450 00:38:40.133438 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 00:38:40.139783 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 00:38:40.143473 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 00:38:40.146668 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 00:38:40.150107 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 00:38:40.156299 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 00:38:40.159935 0 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4457 00:38:40.163401 0 6 8 | B1->B0 | 3737 4141 | 1 0 | (0 0) (0 0)
4458 00:38:40.169693 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 00:38:40.173083 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 00:38:40.176432 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 00:38:40.182887 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 00:38:40.186419 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 00:38:40.189126 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 00:38:40.196188 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4465 00:38:40.199332 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 00:38:40.202885 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 00:38:40.209476 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 00:38:40.212798 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 00:38:40.216059 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 00:38:40.222509 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 00:38:40.225679 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 00:38:40.229152 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 00:38:40.235912 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 00:38:40.238760 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 00:38:40.242451 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 00:38:40.248934 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 00:38:40.252423 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 00:38:40.255808 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:38:40.262219 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 00:38:40.265985 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4481 00:38:40.268592 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4482 00:38:40.272218 Total UI for P1: 0, mck2ui 16
4483 00:38:40.275595 best dqsien dly found for B0: ( 0, 9, 4)
4484 00:38:40.281834 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 00:38:40.282380 Total UI for P1: 0, mck2ui 16
4486 00:38:40.288573 best dqsien dly found for B1: ( 0, 9, 8)
4487 00:38:40.291911 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4488 00:38:40.295548 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4489 00:38:40.296026
4490 00:38:40.298918 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4491 00:38:40.301780 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4492 00:38:40.305241 [Gating] SW calibration Done
4493 00:38:40.305794 ==
4494 00:38:40.308635 Dram Type= 6, Freq= 0, CH_1, rank 1
4495 00:38:40.312135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4496 00:38:40.312669 ==
4497 00:38:40.315491 RX Vref Scan: 0
4498 00:38:40.315997
4499 00:38:40.316329 RX Vref 0 -> 0, step: 1
4500 00:38:40.316637
4501 00:38:40.318377 RX Delay -230 -> 252, step: 16
4502 00:38:40.324909 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4503 00:38:40.328501 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4504 00:38:40.332078 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4505 00:38:40.335333 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4506 00:38:40.338719 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4507 00:38:40.345458 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4508 00:38:40.348744 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4509 00:38:40.351969 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4510 00:38:40.355538 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4511 00:38:40.361948 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4512 00:38:40.365268 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4513 00:38:40.368269 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4514 00:38:40.371577 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4515 00:38:40.378362 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4516 00:38:40.381542 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4517 00:38:40.385101 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4518 00:38:40.385834 ==
4519 00:38:40.388366 Dram Type= 6, Freq= 0, CH_1, rank 1
4520 00:38:40.391717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4521 00:38:40.392237 ==
4522 00:38:40.394632 DQS Delay:
4523 00:38:40.395043 DQS0 = 0, DQS1 = 0
4524 00:38:40.398501 DQM Delay:
4525 00:38:40.399012 DQM0 = 39, DQM1 = 34
4526 00:38:40.399342 DQ Delay:
4527 00:38:40.401394 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4528 00:38:40.405188 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4529 00:38:40.408437 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4530 00:38:40.411538 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4531 00:38:40.412052
4532 00:38:40.412379
4533 00:38:40.414909 ==
4534 00:38:40.415425 Dram Type= 6, Freq= 0, CH_1, rank 1
4535 00:38:40.421482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4536 00:38:40.421979 ==
4537 00:38:40.422312
4538 00:38:40.422612
4539 00:38:40.424612 TX Vref Scan disable
4540 00:38:40.425025 == TX Byte 0 ==
4541 00:38:40.428444 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4542 00:38:40.434626 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4543 00:38:40.435131 == TX Byte 1 ==
4544 00:38:40.438331 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4545 00:38:40.444928 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4546 00:38:40.445471 ==
4547 00:38:40.448021 Dram Type= 6, Freq= 0, CH_1, rank 1
4548 00:38:40.451531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4549 00:38:40.452056 ==
4550 00:38:40.452389
4551 00:38:40.452692
4552 00:38:40.454981 TX Vref Scan disable
4553 00:38:40.458216 == TX Byte 0 ==
4554 00:38:40.461752 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4555 00:38:40.464743 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4556 00:38:40.467891 == TX Byte 1 ==
4557 00:38:40.471435 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4558 00:38:40.474592 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4559 00:38:40.475052
4560 00:38:40.477668 [DATLAT]
4561 00:38:40.478127 Freq=600, CH1 RK1
4562 00:38:40.478458
4563 00:38:40.480969 DATLAT Default: 0x8
4564 00:38:40.481421 0, 0xFFFF, sum = 0
4565 00:38:40.484183 1, 0xFFFF, sum = 0
4566 00:38:40.484601 2, 0xFFFF, sum = 0
4567 00:38:40.487615 3, 0xFFFF, sum = 0
4568 00:38:40.488034 4, 0xFFFF, sum = 0
4569 00:38:40.491679 5, 0xFFFF, sum = 0
4570 00:38:40.492197 6, 0xFFFF, sum = 0
4571 00:38:40.494306 7, 0x0, sum = 1
4572 00:38:40.494726 8, 0x0, sum = 2
4573 00:38:40.497998 9, 0x0, sum = 3
4574 00:38:40.498515 10, 0x0, sum = 4
4575 00:38:40.498852 best_step = 8
4576 00:38:40.501112
4577 00:38:40.501597 ==
4578 00:38:40.504171 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 00:38:40.507699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4580 00:38:40.508214 ==
4581 00:38:40.508547 RX Vref Scan: 0
4582 00:38:40.508855
4583 00:38:40.510995 RX Vref 0 -> 0, step: 1
4584 00:38:40.511507
4585 00:38:40.514756 RX Delay -195 -> 252, step: 8
4586 00:38:40.520670 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4587 00:38:40.524388 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4588 00:38:40.527658 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4589 00:38:40.530845 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4590 00:38:40.537464 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4591 00:38:40.540717 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4592 00:38:40.544074 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4593 00:38:40.547781 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4594 00:38:40.551243 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4595 00:38:40.557477 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4596 00:38:40.560590 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4597 00:38:40.564043 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4598 00:38:40.567280 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4599 00:38:40.573837 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4600 00:38:40.577534 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4601 00:38:40.580862 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4602 00:38:40.581419 ==
4603 00:38:40.584170 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 00:38:40.587106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4605 00:38:40.590554 ==
4606 00:38:40.591062 DQS Delay:
4607 00:38:40.591399 DQS0 = 0, DQS1 = 0
4608 00:38:40.593749 DQM Delay:
4609 00:38:40.594179 DQM0 = 36, DQM1 = 29
4610 00:38:40.597036 DQ Delay:
4611 00:38:40.600452 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4612 00:38:40.600966 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4613 00:38:40.603362 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4614 00:38:40.610044 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4615 00:38:40.610540
4616 00:38:40.610872
4617 00:38:40.617007 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4618 00:38:40.620318 CH1 RK1: MR19=808, MR18=5A5A
4619 00:38:40.627083 CH1_RK1: MR19=0x808, MR18=0x5A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4620 00:38:40.630222 [RxdqsGatingPostProcess] freq 600
4621 00:38:40.633881 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4622 00:38:40.637239 Pre-setting of DQS Precalculation
4623 00:38:40.643583 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4624 00:38:40.650201 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4625 00:38:40.657073 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4626 00:38:40.657545
4627 00:38:40.657881
4628 00:38:40.660201 [Calibration Summary] 1200 Mbps
4629 00:38:40.660712 CH 0, Rank 0
4630 00:38:40.663661 SW Impedance : PASS
4631 00:38:40.667161 DUTY Scan : NO K
4632 00:38:40.667677 ZQ Calibration : PASS
4633 00:38:40.670377 Jitter Meter : NO K
4634 00:38:40.673258 CBT Training : PASS
4635 00:38:40.673865 Write leveling : PASS
4636 00:38:40.676346 RX DQS gating : PASS
4637 00:38:40.679834 RX DQ/DQS(RDDQC) : PASS
4638 00:38:40.680345 TX DQ/DQS : PASS
4639 00:38:40.683180 RX DATLAT : PASS
4640 00:38:40.683692 RX DQ/DQS(Engine): PASS
4641 00:38:40.686356 TX OE : NO K
4642 00:38:40.686776 All Pass.
4643 00:38:40.687109
4644 00:38:40.689706 CH 0, Rank 1
4645 00:38:40.690122 SW Impedance : PASS
4646 00:38:40.692671 DUTY Scan : NO K
4647 00:38:40.696365 ZQ Calibration : PASS
4648 00:38:40.696782 Jitter Meter : NO K
4649 00:38:40.699612 CBT Training : PASS
4650 00:38:40.703174 Write leveling : PASS
4651 00:38:40.703684 RX DQS gating : PASS
4652 00:38:40.706742 RX DQ/DQS(RDDQC) : PASS
4653 00:38:40.709616 TX DQ/DQS : PASS
4654 00:38:40.710129 RX DATLAT : PASS
4655 00:38:40.712846 RX DQ/DQS(Engine): PASS
4656 00:38:40.716097 TX OE : NO K
4657 00:38:40.716614 All Pass.
4658 00:38:40.716949
4659 00:38:40.717257 CH 1, Rank 0
4660 00:38:40.719456 SW Impedance : PASS
4661 00:38:40.723150 DUTY Scan : NO K
4662 00:38:40.723569 ZQ Calibration : PASS
4663 00:38:40.726060 Jitter Meter : NO K
4664 00:38:40.729416 CBT Training : PASS
4665 00:38:40.729842 Write leveling : PASS
4666 00:38:40.732363 RX DQS gating : PASS
4667 00:38:40.735826 RX DQ/DQS(RDDQC) : PASS
4668 00:38:40.736337 TX DQ/DQS : PASS
4669 00:38:40.739912 RX DATLAT : PASS
4670 00:38:40.742637 RX DQ/DQS(Engine): PASS
4671 00:38:40.743051 TX OE : NO K
4672 00:38:40.743378 All Pass.
4673 00:38:40.745485
4674 00:38:40.745895 CH 1, Rank 1
4675 00:38:40.748963 SW Impedance : PASS
4676 00:38:40.749414 DUTY Scan : NO K
4677 00:38:40.752610 ZQ Calibration : PASS
4678 00:38:40.755730 Jitter Meter : NO K
4679 00:38:40.756247 CBT Training : PASS
4680 00:38:40.759073 Write leveling : PASS
4681 00:38:40.759586 RX DQS gating : PASS
4682 00:38:40.762774 RX DQ/DQS(RDDQC) : PASS
4683 00:38:40.765631 TX DQ/DQS : PASS
4684 00:38:40.766180 RX DATLAT : PASS
4685 00:38:40.769443 RX DQ/DQS(Engine): PASS
4686 00:38:40.772561 TX OE : NO K
4687 00:38:40.773363 All Pass.
4688 00:38:40.773765
4689 00:38:40.775472 DramC Write-DBI off
4690 00:38:40.775926 PER_BANK_REFRESH: Hybrid Mode
4691 00:38:40.779164 TX_TRACKING: ON
4692 00:38:40.788687 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4693 00:38:40.792155 [FAST_K] Save calibration result to emmc
4694 00:38:40.795374 dramc_set_vcore_voltage set vcore to 662500
4695 00:38:40.795841 Read voltage for 933, 3
4696 00:38:40.798947 Vio18 = 0
4697 00:38:40.799663 Vcore = 662500
4698 00:38:40.800040 Vdram = 0
4699 00:38:40.802041 Vddq = 0
4700 00:38:40.802649 Vmddr = 0
4701 00:38:40.805600 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4702 00:38:40.812038 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4703 00:38:40.815660 MEM_TYPE=3, freq_sel=17
4704 00:38:40.818959 sv_algorithm_assistance_LP4_1600
4705 00:38:40.822298 ============ PULL DRAM RESETB DOWN ============
4706 00:38:40.825375 ========== PULL DRAM RESETB DOWN end =========
4707 00:38:40.831965 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4708 00:38:40.835324 ===================================
4709 00:38:40.835808 LPDDR4 DRAM CONFIGURATION
4710 00:38:40.838546 ===================================
4711 00:38:40.841965 EX_ROW_EN[0] = 0x0
4712 00:38:40.842525 EX_ROW_EN[1] = 0x0
4713 00:38:40.845416 LP4Y_EN = 0x0
4714 00:38:40.848420 WORK_FSP = 0x0
4715 00:38:40.848966 WL = 0x3
4716 00:38:40.852206 RL = 0x3
4717 00:38:40.852751 BL = 0x2
4718 00:38:40.855206 RPST = 0x0
4719 00:38:40.855755 RD_PRE = 0x0
4720 00:38:40.858135 WR_PRE = 0x1
4721 00:38:40.858585 WR_PST = 0x0
4722 00:38:40.861853 DBI_WR = 0x0
4723 00:38:40.862399 DBI_RD = 0x0
4724 00:38:40.864957 OTF = 0x1
4725 00:38:40.868358 ===================================
4726 00:38:40.871822 ===================================
4727 00:38:40.872371 ANA top config
4728 00:38:40.875249 ===================================
4729 00:38:40.877919 DLL_ASYNC_EN = 0
4730 00:38:40.881692 ALL_SLAVE_EN = 1
4731 00:38:40.882331 NEW_RANK_MODE = 1
4732 00:38:40.884927 DLL_IDLE_MODE = 1
4733 00:38:40.888132 LP45_APHY_COMB_EN = 1
4734 00:38:40.891664 TX_ODT_DIS = 1
4735 00:38:40.894428 NEW_8X_MODE = 1
4736 00:38:40.898165 ===================================
4737 00:38:40.901495 ===================================
4738 00:38:40.901917 data_rate = 1866
4739 00:38:40.904678 CKR = 1
4740 00:38:40.908096 DQ_P2S_RATIO = 8
4741 00:38:40.911438 ===================================
4742 00:38:40.914874 CA_P2S_RATIO = 8
4743 00:38:40.917862 DQ_CA_OPEN = 0
4744 00:38:40.921281 DQ_SEMI_OPEN = 0
4745 00:38:40.921858 CA_SEMI_OPEN = 0
4746 00:38:40.924193 CA_FULL_RATE = 0
4747 00:38:40.927662 DQ_CKDIV4_EN = 1
4748 00:38:40.931113 CA_CKDIV4_EN = 1
4749 00:38:40.934245 CA_PREDIV_EN = 0
4750 00:38:40.937484 PH8_DLY = 0
4751 00:38:40.937891 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4752 00:38:40.941119 DQ_AAMCK_DIV = 4
4753 00:38:40.944761 CA_AAMCK_DIV = 4
4754 00:38:40.947778 CA_ADMCK_DIV = 4
4755 00:38:40.950829 DQ_TRACK_CA_EN = 0
4756 00:38:40.954392 CA_PICK = 933
4757 00:38:40.957829 CA_MCKIO = 933
4758 00:38:40.958341 MCKIO_SEMI = 0
4759 00:38:40.960789 PLL_FREQ = 3732
4760 00:38:40.964564 DQ_UI_PI_RATIO = 32
4761 00:38:40.968076 CA_UI_PI_RATIO = 0
4762 00:38:40.970936 ===================================
4763 00:38:40.974228 ===================================
4764 00:38:40.977426 memory_type:LPDDR4
4765 00:38:40.977924 GP_NUM : 10
4766 00:38:40.981043 SRAM_EN : 1
4767 00:38:40.984445 MD32_EN : 0
4768 00:38:40.987002 ===================================
4769 00:38:40.987411 [ANA_INIT] >>>>>>>>>>>>>>
4770 00:38:40.990606 <<<<<< [CONFIGURE PHASE]: ANA_TX
4771 00:38:40.993868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4772 00:38:40.997598 ===================================
4773 00:38:41.000649 data_rate = 1866,PCW = 0X8f00
4774 00:38:41.003997 ===================================
4775 00:38:41.007156 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4776 00:38:41.013446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4777 00:38:41.017691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4778 00:38:41.023612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4779 00:38:41.026815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4780 00:38:41.029969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4781 00:38:41.033939 [ANA_INIT] flow start
4782 00:38:41.034500 [ANA_INIT] PLL >>>>>>>>
4783 00:38:41.036848 [ANA_INIT] PLL <<<<<<<<
4784 00:38:41.040085 [ANA_INIT] MIDPI >>>>>>>>
4785 00:38:41.040609 [ANA_INIT] MIDPI <<<<<<<<
4786 00:38:41.043206 [ANA_INIT] DLL >>>>>>>>
4787 00:38:41.046474 [ANA_INIT] flow end
4788 00:38:41.049777 ============ LP4 DIFF to SE enter ============
4789 00:38:41.053254 ============ LP4 DIFF to SE exit ============
4790 00:38:41.056614 [ANA_INIT] <<<<<<<<<<<<<
4791 00:38:41.059832 [Flow] Enable top DCM control >>>>>
4792 00:38:41.063142 [Flow] Enable top DCM control <<<<<
4793 00:38:41.066461 Enable DLL master slave shuffle
4794 00:38:41.069552 ==============================================================
4795 00:38:41.073093 Gating Mode config
4796 00:38:41.079876 ==============================================================
4797 00:38:41.080385 Config description:
4798 00:38:41.090201 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4799 00:38:41.095921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4800 00:38:41.102463 SELPH_MODE 0: By rank 1: By Phase
4801 00:38:41.106162 ==============================================================
4802 00:38:41.109279 GAT_TRACK_EN = 1
4803 00:38:41.112817 RX_GATING_MODE = 2
4804 00:38:41.116000 RX_GATING_TRACK_MODE = 2
4805 00:38:41.119403 SELPH_MODE = 1
4806 00:38:41.122545 PICG_EARLY_EN = 1
4807 00:38:41.125726 VALID_LAT_VALUE = 1
4808 00:38:41.129405 ==============================================================
4809 00:38:41.132721 Enter into Gating configuration >>>>
4810 00:38:41.136052 Exit from Gating configuration <<<<
4811 00:38:41.138713 Enter into DVFS_PRE_config >>>>>
4812 00:38:41.152373 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4813 00:38:41.155624 Exit from DVFS_PRE_config <<<<<
4814 00:38:41.159056 Enter into PICG configuration >>>>
4815 00:38:41.159615 Exit from PICG configuration <<<<
4816 00:38:41.162269 [RX_INPUT] configuration >>>>>
4817 00:38:41.165446 [RX_INPUT] configuration <<<<<
4818 00:38:41.183766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4819 00:38:41.184190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4820 00:38:41.184518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4821 00:38:41.188571 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4822 00:38:41.196267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4823 00:38:41.201842 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4824 00:38:41.205012 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4825 00:38:41.208555 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4826 00:38:41.212086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4827 00:38:41.218602 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4828 00:38:41.221644 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4829 00:38:41.225496 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4830 00:38:41.228634 ===================================
4831 00:38:41.231762 LPDDR4 DRAM CONFIGURATION
4832 00:38:41.235047 ===================================
4833 00:38:41.238091 EX_ROW_EN[0] = 0x0
4834 00:38:41.238551 EX_ROW_EN[1] = 0x0
4835 00:38:41.241921 LP4Y_EN = 0x0
4836 00:38:41.242430 WORK_FSP = 0x0
4837 00:38:41.245208 WL = 0x3
4838 00:38:41.245752 RL = 0x3
4839 00:38:41.248298 BL = 0x2
4840 00:38:41.248805 RPST = 0x0
4841 00:38:41.251780 RD_PRE = 0x0
4842 00:38:41.252290 WR_PRE = 0x1
4843 00:38:41.255227 WR_PST = 0x0
4844 00:38:41.255733 DBI_WR = 0x0
4845 00:38:41.258221 DBI_RD = 0x0
4846 00:38:41.261632 OTF = 0x1
4847 00:38:41.262139 ===================================
4848 00:38:41.268582 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4849 00:38:41.271581 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4850 00:38:41.274699 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4851 00:38:41.277914 ===================================
4852 00:38:41.281463 LPDDR4 DRAM CONFIGURATION
4853 00:38:41.284485 ===================================
4854 00:38:41.287774 EX_ROW_EN[0] = 0x10
4855 00:38:41.288192 EX_ROW_EN[1] = 0x0
4856 00:38:41.291024 LP4Y_EN = 0x0
4857 00:38:41.291440 WORK_FSP = 0x0
4858 00:38:41.294443 WL = 0x3
4859 00:38:41.294904 RL = 0x3
4860 00:38:41.297657 BL = 0x2
4861 00:38:41.298070 RPST = 0x0
4862 00:38:41.301435 RD_PRE = 0x0
4863 00:38:41.301956 WR_PRE = 0x1
4864 00:38:41.304250 WR_PST = 0x0
4865 00:38:41.304668 DBI_WR = 0x0
4866 00:38:41.308072 DBI_RD = 0x0
4867 00:38:41.311030 OTF = 0x1
4868 00:38:41.311472 ===================================
4869 00:38:41.317552 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4870 00:38:41.322733 nWR fixed to 30
4871 00:38:41.326448 [ModeRegInit_LP4] CH0 RK0
4872 00:38:41.326865 [ModeRegInit_LP4] CH0 RK1
4873 00:38:41.329044 [ModeRegInit_LP4] CH1 RK0
4874 00:38:41.332427 [ModeRegInit_LP4] CH1 RK1
4875 00:38:41.332878 match AC timing 8
4876 00:38:41.339564 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4877 00:38:41.342644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4878 00:38:41.345936 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4879 00:38:41.352341 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4880 00:38:41.355922 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4881 00:38:41.356341 ==
4882 00:38:41.359108 Dram Type= 6, Freq= 0, CH_0, rank 0
4883 00:38:41.362686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4884 00:38:41.363191 ==
4885 00:38:41.368900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4886 00:38:41.375382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4887 00:38:41.379038 [CA 0] Center 38 (8~69) winsize 62
4888 00:38:41.382042 [CA 1] Center 38 (8~69) winsize 62
4889 00:38:41.385621 [CA 2] Center 36 (6~67) winsize 62
4890 00:38:41.388957 [CA 3] Center 36 (6~67) winsize 62
4891 00:38:41.392189 [CA 4] Center 34 (4~65) winsize 62
4892 00:38:41.395722 [CA 5] Center 34 (3~65) winsize 63
4893 00:38:41.396136
4894 00:38:41.398470 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4895 00:38:41.398888
4896 00:38:41.402162 [CATrainingPosCal] consider 1 rank data
4897 00:38:41.405679 u2DelayCellTimex100 = 270/100 ps
4898 00:38:41.408943 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4899 00:38:41.412055 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4900 00:38:41.415570 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4901 00:38:41.418868 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4902 00:38:41.421987 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4903 00:38:41.428499 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4904 00:38:41.428995
4905 00:38:41.431981 CA PerBit enable=1, Macro0, CA PI delay=34
4906 00:38:41.432401
4907 00:38:41.435164 [CBTSetCACLKResult] CA Dly = 34
4908 00:38:41.435578 CS Dly: 7 (0~38)
4909 00:38:41.435904 ==
4910 00:38:41.438779 Dram Type= 6, Freq= 0, CH_0, rank 1
4911 00:38:41.441823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4912 00:38:41.445243 ==
4913 00:38:41.449072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4914 00:38:41.455450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4915 00:38:41.458289 [CA 0] Center 38 (8~69) winsize 62
4916 00:38:41.462234 [CA 1] Center 38 (7~69) winsize 63
4917 00:38:41.465443 [CA 2] Center 36 (5~67) winsize 63
4918 00:38:41.468630 [CA 3] Center 35 (5~66) winsize 62
4919 00:38:41.471866 [CA 4] Center 34 (4~65) winsize 62
4920 00:38:41.475007 [CA 5] Center 34 (4~65) winsize 62
4921 00:38:41.475549
4922 00:38:41.478534 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4923 00:38:41.478989
4924 00:38:41.481739 [CATrainingPosCal] consider 2 rank data
4925 00:38:41.485189 u2DelayCellTimex100 = 270/100 ps
4926 00:38:41.488342 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4927 00:38:41.491394 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4928 00:38:41.494712 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4929 00:38:41.501547 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4930 00:38:41.504867 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4931 00:38:41.507977 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4932 00:38:41.508478
4933 00:38:41.511546 CA PerBit enable=1, Macro0, CA PI delay=34
4934 00:38:41.512053
4935 00:38:41.514893 [CBTSetCACLKResult] CA Dly = 34
4936 00:38:41.515408 CS Dly: 7 (0~39)
4937 00:38:41.515741
4938 00:38:41.518195 ----->DramcWriteLeveling(PI) begin...
4939 00:38:41.521755 ==
4940 00:38:41.522272 Dram Type= 6, Freq= 0, CH_0, rank 0
4941 00:38:41.527985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4942 00:38:41.528481 ==
4943 00:38:41.531560 Write leveling (Byte 0): 27 => 27
4944 00:38:41.534666 Write leveling (Byte 1): 27 => 27
4945 00:38:41.537900 DramcWriteLeveling(PI) end<-----
4946 00:38:41.538305
4947 00:38:41.538629 ==
4948 00:38:41.540998 Dram Type= 6, Freq= 0, CH_0, rank 0
4949 00:38:41.544658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4950 00:38:41.545208 ==
4951 00:38:41.548033 [Gating] SW mode calibration
4952 00:38:41.554461 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4953 00:38:41.557958 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4954 00:38:41.564619 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4955 00:38:41.568495 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4956 00:38:41.574140 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4957 00:38:41.577644 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4958 00:38:41.581195 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4959 00:38:41.584593 0 10 20 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 1)
4960 00:38:41.590645 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4961 00:38:41.594146 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4962 00:38:41.597624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4963 00:38:41.603921 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4964 00:38:41.607298 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4965 00:38:41.610754 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4966 00:38:41.617255 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4967 00:38:41.620776 0 11 20 | B1->B0 | 2828 3131 | 1 1 | (0 0) (0 0)
4968 00:38:41.623989 0 11 24 | B1->B0 | 3737 4141 | 0 0 | (0 0) (0 0)
4969 00:38:41.630434 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4970 00:38:41.633661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4971 00:38:41.637236 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4972 00:38:41.644106 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4973 00:38:41.647300 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4974 00:38:41.650353 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4975 00:38:41.657266 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4976 00:38:41.660424 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4977 00:38:41.663823 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4978 00:38:41.670461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4979 00:38:41.673695 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4980 00:38:41.676457 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4981 00:38:41.683559 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4982 00:38:41.686510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4983 00:38:41.689684 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4984 00:38:41.696507 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4985 00:38:41.699987 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4986 00:38:41.702902 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4987 00:38:41.709937 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 00:38:41.713158 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 00:38:41.716219 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 00:38:41.722859 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 00:38:41.726060 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 00:38:41.729211 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4993 00:38:41.733150 Total UI for P1: 0, mck2ui 16
4994 00:38:41.735891 best dqsien dly found for B1: ( 0, 14, 22)
4995 00:38:41.742575 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 00:38:41.745985 Total UI for P1: 0, mck2ui 16
4997 00:38:41.749106 best dqsien dly found for B0: ( 0, 14, 24)
4998 00:38:41.752510 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
4999 00:38:41.755990 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5000 00:38:41.756443
5001 00:38:41.759299 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
5002 00:38:41.762502 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5003 00:38:41.765594 [Gating] SW calibration Done
5004 00:38:41.765909 ==
5005 00:38:41.769119 Dram Type= 6, Freq= 0, CH_0, rank 0
5006 00:38:41.772041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5007 00:38:41.772276 ==
5008 00:38:41.775422 RX Vref Scan: 0
5009 00:38:41.775607
5010 00:38:41.778511 RX Vref 0 -> 0, step: 1
5011 00:38:41.778697
5012 00:38:41.778842 RX Delay -80 -> 252, step: 8
5013 00:38:41.785023 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5014 00:38:41.788424 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5015 00:38:41.792000 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5016 00:38:41.795442 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5017 00:38:41.798578 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5018 00:38:41.801674 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5019 00:38:41.808226 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5020 00:38:41.811813 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5021 00:38:41.815310 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5022 00:38:41.818622 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5023 00:38:41.821794 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5024 00:38:41.828362 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5025 00:38:41.831506 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5026 00:38:41.835024 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5027 00:38:41.838231 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5028 00:38:41.841314 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5029 00:38:41.841496 ==
5030 00:38:41.844904 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 00:38:41.851500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5032 00:38:41.852042 ==
5033 00:38:41.852514 DQS Delay:
5034 00:38:41.854929 DQS0 = 0, DQS1 = 0
5035 00:38:41.855353 DQM Delay:
5036 00:38:41.858169 DQM0 = 96, DQM1 = 86
5037 00:38:41.858582 DQ Delay:
5038 00:38:41.861560 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5039 00:38:41.864744 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5040 00:38:41.868031 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5041 00:38:41.871811 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5042 00:38:41.872258
5043 00:38:41.872614
5044 00:38:41.872924 ==
5045 00:38:41.874916 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 00:38:41.878110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5047 00:38:41.878536 ==
5048 00:38:41.878866
5049 00:38:41.879170
5050 00:38:41.881804 TX Vref Scan disable
5051 00:38:41.884800 == TX Byte 0 ==
5052 00:38:41.888072 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5053 00:38:41.891071 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5054 00:38:41.894478 == TX Byte 1 ==
5055 00:38:41.897839 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5056 00:38:41.901105 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5057 00:38:41.901254 ==
5058 00:38:41.904389 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 00:38:41.907882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5060 00:38:41.911137 ==
5061 00:38:41.911285
5062 00:38:41.911402
5063 00:38:41.911510 TX Vref Scan disable
5064 00:38:41.914529 == TX Byte 0 ==
5065 00:38:41.917769 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5066 00:38:41.924329 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5067 00:38:41.924483 == TX Byte 1 ==
5068 00:38:41.927729 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5069 00:38:41.934394 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5070 00:38:41.934534
5071 00:38:41.934626 [DATLAT]
5072 00:38:41.934708 Freq=933, CH0 RK0
5073 00:38:41.934788
5074 00:38:41.937615 DATLAT Default: 0xd
5075 00:38:41.940996 0, 0xFFFF, sum = 0
5076 00:38:41.941097 1, 0xFFFF, sum = 0
5077 00:38:41.944264 2, 0xFFFF, sum = 0
5078 00:38:41.944357 3, 0xFFFF, sum = 0
5079 00:38:41.947247 4, 0xFFFF, sum = 0
5080 00:38:41.947344 5, 0xFFFF, sum = 0
5081 00:38:41.950810 6, 0xFFFF, sum = 0
5082 00:38:41.950901 7, 0xFFFF, sum = 0
5083 00:38:41.953793 8, 0xFFFF, sum = 0
5084 00:38:41.953882 9, 0xFFFF, sum = 0
5085 00:38:41.957705 10, 0x0, sum = 1
5086 00:38:41.957800 11, 0x0, sum = 2
5087 00:38:41.960949 12, 0x0, sum = 3
5088 00:38:41.961039 13, 0x0, sum = 4
5089 00:38:41.961105 best_step = 11
5090 00:38:41.964059
5091 00:38:41.964144 ==
5092 00:38:41.967308 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 00:38:41.970495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5094 00:38:41.970595 ==
5095 00:38:41.970661 RX Vref Scan: 1
5096 00:38:41.970722
5097 00:38:41.974266 RX Vref 0 -> 0, step: 1
5098 00:38:41.974348
5099 00:38:41.977085 RX Delay -61 -> 252, step: 4
5100 00:38:41.977167
5101 00:38:41.980264 Set Vref, RX VrefLevel [Byte0]: 53
5102 00:38:41.983944 [Byte1]: 50
5103 00:38:41.987111
5104 00:38:41.987207 Final RX Vref Byte 0 = 53 to rank0
5105 00:38:41.990251 Final RX Vref Byte 1 = 50 to rank0
5106 00:38:41.993910 Final RX Vref Byte 0 = 53 to rank1
5107 00:38:41.997168 Final RX Vref Byte 1 = 50 to rank1==
5108 00:38:42.000151 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 00:38:42.006850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5110 00:38:42.006963 ==
5111 00:38:42.007068 DQS Delay:
5112 00:38:42.010533 DQS0 = 0, DQS1 = 0
5113 00:38:42.010640 DQM Delay:
5114 00:38:42.010739 DQM0 = 96, DQM1 = 87
5115 00:38:42.013402 DQ Delay:
5116 00:38:42.016805 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =94
5117 00:38:42.020077 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =102
5118 00:38:42.023398 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =80
5119 00:38:42.026624 DQ12 =92, DQ13 =94, DQ14 =100, DQ15 =96
5120 00:38:42.026729
5121 00:38:42.026819
5122 00:38:42.033414 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5123 00:38:42.036811 CH0 RK0: MR19=505, MR18=2626
5124 00:38:42.043319 CH0_RK0: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5125 00:38:42.043426
5126 00:38:42.046616 ----->DramcWriteLeveling(PI) begin...
5127 00:38:42.046698 ==
5128 00:38:42.050244 Dram Type= 6, Freq= 0, CH_0, rank 1
5129 00:38:42.053433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5130 00:38:42.053567 ==
5131 00:38:42.056436 Write leveling (Byte 0): 26 => 26
5132 00:38:42.059871 Write leveling (Byte 1): 26 => 26
5133 00:38:42.063042 DramcWriteLeveling(PI) end<-----
5134 00:38:42.063156
5135 00:38:42.063245 ==
5136 00:38:42.066865 Dram Type= 6, Freq= 0, CH_0, rank 1
5137 00:38:42.069646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5138 00:38:42.073071 ==
5139 00:38:42.073178 [Gating] SW mode calibration
5140 00:38:42.083012 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5141 00:38:42.086523 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5142 00:38:42.089509 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 00:38:42.096580 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 00:38:42.099528 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 00:38:42.103507 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 00:38:42.109628 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 00:38:42.112860 0 10 20 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
5148 00:38:42.116184 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
5149 00:38:42.123109 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 00:38:42.126579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 00:38:42.130204 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 00:38:42.136452 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 00:38:42.139628 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 00:38:42.143210 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5155 00:38:42.149452 0 11 20 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 0)
5156 00:38:42.152829 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5157 00:38:42.156455 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 00:38:42.162577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:38:42.165849 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 00:38:42.169252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 00:38:42.175753 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 00:38:42.179336 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 00:38:42.182606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5164 00:38:42.189434 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5165 00:38:42.192597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 00:38:42.196097 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 00:38:42.199129 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 00:38:42.205718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 00:38:42.208941 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 00:38:42.212501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 00:38:42.218859 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 00:38:42.222402 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 00:38:42.225782 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 00:38:42.232528 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 00:38:42.235729 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 00:38:42.238774 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 00:38:42.245366 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 00:38:42.248741 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 00:38:42.251909 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5180 00:38:42.258533 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5181 00:38:42.262358 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 00:38:42.265554 Total UI for P1: 0, mck2ui 16
5183 00:38:42.268666 best dqsien dly found for B0: ( 0, 14, 22)
5184 00:38:42.272016 Total UI for P1: 0, mck2ui 16
5185 00:38:42.275276 best dqsien dly found for B1: ( 0, 14, 22)
5186 00:38:42.278758 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5187 00:38:42.282119 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5188 00:38:42.282248
5189 00:38:42.285271 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5190 00:38:42.288503 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5191 00:38:42.292054 [Gating] SW calibration Done
5192 00:38:42.292174 ==
5193 00:38:42.295194 Dram Type= 6, Freq= 0, CH_0, rank 1
5194 00:38:42.302196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5195 00:38:42.302339 ==
5196 00:38:42.302404 RX Vref Scan: 0
5197 00:38:42.302464
5198 00:38:42.305238 RX Vref 0 -> 0, step: 1
5199 00:38:42.305358
5200 00:38:42.308471 RX Delay -80 -> 252, step: 8
5201 00:38:42.311808 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5202 00:38:42.315122 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5203 00:38:42.318487 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5204 00:38:42.322084 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5205 00:38:42.328708 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5206 00:38:42.331990 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5207 00:38:42.335167 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5208 00:38:42.338364 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5209 00:38:42.342058 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5210 00:38:42.345312 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5211 00:38:42.352079 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5212 00:38:42.355329 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5213 00:38:42.358646 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5214 00:38:42.362089 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5215 00:38:42.365518 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5216 00:38:42.372300 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5217 00:38:42.372850 ==
5218 00:38:42.375555 Dram Type= 6, Freq= 0, CH_0, rank 1
5219 00:38:42.378923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5220 00:38:42.379464 ==
5221 00:38:42.379835 DQS Delay:
5222 00:38:42.382010 DQS0 = 0, DQS1 = 0
5223 00:38:42.382468 DQM Delay:
5224 00:38:42.385430 DQM0 = 95, DQM1 = 87
5225 00:38:42.385890 DQ Delay:
5226 00:38:42.388377 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5227 00:38:42.391787 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5228 00:38:42.395428 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5229 00:38:42.398606 DQ12 =99, DQ13 =91, DQ14 =99, DQ15 =99
5230 00:38:42.399067
5231 00:38:42.399431
5232 00:38:42.399761 ==
5233 00:38:42.402211 Dram Type= 6, Freq= 0, CH_0, rank 1
5234 00:38:42.405671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5235 00:38:42.406226 ==
5236 00:38:42.406590
5237 00:38:42.408904
5238 00:38:42.409627 TX Vref Scan disable
5239 00:38:42.411885 == TX Byte 0 ==
5240 00:38:42.415623 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5241 00:38:42.418545 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5242 00:38:42.421729 == TX Byte 1 ==
5243 00:38:42.425265 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5244 00:38:42.429052 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5245 00:38:42.429658 ==
5246 00:38:42.431697 Dram Type= 6, Freq= 0, CH_0, rank 1
5247 00:38:42.438368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5248 00:38:42.438900 ==
5249 00:38:42.439268
5250 00:38:42.439604
5251 00:38:42.439925 TX Vref Scan disable
5252 00:38:42.442560 == TX Byte 0 ==
5253 00:38:42.445773 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5254 00:38:42.452250 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5255 00:38:42.452785 == TX Byte 1 ==
5256 00:38:42.455531 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5257 00:38:42.462179 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5258 00:38:42.462639
5259 00:38:42.463006 [DATLAT]
5260 00:38:42.463342 Freq=933, CH0 RK1
5261 00:38:42.463672
5262 00:38:42.465336 DATLAT Default: 0xb
5263 00:38:42.465944 0, 0xFFFF, sum = 0
5264 00:38:42.468810 1, 0xFFFF, sum = 0
5265 00:38:42.472142 2, 0xFFFF, sum = 0
5266 00:38:42.472569 3, 0xFFFF, sum = 0
5267 00:38:42.475450 4, 0xFFFF, sum = 0
5268 00:38:42.475873 5, 0xFFFF, sum = 0
5269 00:38:42.478789 6, 0xFFFF, sum = 0
5270 00:38:42.479373 7, 0xFFFF, sum = 0
5271 00:38:42.482078 8, 0xFFFF, sum = 0
5272 00:38:42.482498 9, 0xFFFF, sum = 0
5273 00:38:42.485650 10, 0x0, sum = 1
5274 00:38:42.486162 11, 0x0, sum = 2
5275 00:38:42.489012 12, 0x0, sum = 3
5276 00:38:42.489554 13, 0x0, sum = 4
5277 00:38:42.490059 best_step = 11
5278 00:38:42.492151
5279 00:38:42.492566 ==
5280 00:38:42.495329 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 00:38:42.498318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5282 00:38:42.498801 ==
5283 00:38:42.499143 RX Vref Scan: 0
5284 00:38:42.499457
5285 00:38:42.501838 RX Vref 0 -> 0, step: 1
5286 00:38:42.502253
5287 00:38:42.505060 RX Delay -69 -> 252, step: 4
5288 00:38:42.511729 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5289 00:38:42.515485 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5290 00:38:42.518609 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5291 00:38:42.521977 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5292 00:38:42.525426 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5293 00:38:42.528415 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5294 00:38:42.532108 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5295 00:38:42.538286 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5296 00:38:42.541636 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5297 00:38:42.545076 iDelay=203, Bit 9, Center 74 (-13 ~ 162) 176
5298 00:38:42.548267 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5299 00:38:42.551809 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5300 00:38:42.558247 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5301 00:38:42.561499 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5302 00:38:42.564799 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5303 00:38:42.568129 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5304 00:38:42.568672 ==
5305 00:38:42.571860 Dram Type= 6, Freq= 0, CH_0, rank 1
5306 00:38:42.574887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5307 00:38:42.578192 ==
5308 00:38:42.578608 DQS Delay:
5309 00:38:42.578939 DQS0 = 0, DQS1 = 0
5310 00:38:42.581662 DQM Delay:
5311 00:38:42.582079 DQM0 = 97, DQM1 = 87
5312 00:38:42.585064 DQ Delay:
5313 00:38:42.585633 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5314 00:38:42.588358 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =108
5315 00:38:42.595360 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =78
5316 00:38:42.597843 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5317 00:38:42.598261
5318 00:38:42.598592
5319 00:38:42.604750 [DQSOSCAuto] RK1, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5320 00:38:42.607883 CH0 RK1: MR19=505, MR18=3232
5321 00:38:42.615265 CH0_RK1: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5322 00:38:42.617784 [RxdqsGatingPostProcess] freq 933
5323 00:38:42.621364 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5324 00:38:42.624739 Pre-setting of DQS Precalculation
5325 00:38:42.631062 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5326 00:38:42.631562 ==
5327 00:38:42.634594 Dram Type= 6, Freq= 0, CH_1, rank 0
5328 00:38:42.637828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5329 00:38:42.638265 ==
5330 00:38:42.644708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5331 00:38:42.650896 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5332 00:38:42.654410 [CA 0] Center 37 (7~68) winsize 62
5333 00:38:42.657483 [CA 1] Center 37 (6~68) winsize 63
5334 00:38:42.660649 [CA 2] Center 34 (4~65) winsize 62
5335 00:38:42.664264 [CA 3] Center 34 (4~65) winsize 62
5336 00:38:42.667702 [CA 4] Center 33 (2~64) winsize 63
5337 00:38:42.668009 [CA 5] Center 33 (3~64) winsize 62
5338 00:38:42.670972
5339 00:38:42.674238 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5340 00:38:42.674550
5341 00:38:42.677578 [CATrainingPosCal] consider 1 rank data
5342 00:38:42.680928 u2DelayCellTimex100 = 270/100 ps
5343 00:38:42.684442 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5344 00:38:42.687024 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5345 00:38:42.690365 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5346 00:38:42.693946 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5347 00:38:42.697206 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5348 00:38:42.700592 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5349 00:38:42.700827
5350 00:38:42.703783 CA PerBit enable=1, Macro0, CA PI delay=33
5351 00:38:42.706959
5352 00:38:42.707235 [CBTSetCACLKResult] CA Dly = 33
5353 00:38:42.710570 CS Dly: 5 (0~36)
5354 00:38:42.710916 ==
5355 00:38:42.713665 Dram Type= 6, Freq= 0, CH_1, rank 1
5356 00:38:42.717266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5357 00:38:42.717843 ==
5358 00:38:42.723631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5359 00:38:42.730175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5360 00:38:42.733393 [CA 0] Center 37 (6~68) winsize 63
5361 00:38:42.736958 [CA 1] Center 37 (6~68) winsize 63
5362 00:38:42.740502 [CA 2] Center 34 (4~65) winsize 62
5363 00:38:42.743936 [CA 3] Center 34 (4~65) winsize 62
5364 00:38:42.747057 [CA 4] Center 33 (3~64) winsize 62
5365 00:38:42.749936 [CA 5] Center 32 (2~63) winsize 62
5366 00:38:42.750394
5367 00:38:42.753780 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5368 00:38:42.754326
5369 00:38:42.756735 [CATrainingPosCal] consider 2 rank data
5370 00:38:42.760240 u2DelayCellTimex100 = 270/100 ps
5371 00:38:42.763653 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5372 00:38:42.766834 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5373 00:38:42.770080 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5374 00:38:42.773487 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5375 00:38:42.776895 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5376 00:38:42.779933 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5377 00:38:42.783320
5378 00:38:42.786499 CA PerBit enable=1, Macro0, CA PI delay=33
5379 00:38:42.787056
5380 00:38:42.789838 [CBTSetCACLKResult] CA Dly = 33
5381 00:38:42.790297 CS Dly: 5 (0~37)
5382 00:38:42.790658
5383 00:38:42.793274 ----->DramcWriteLeveling(PI) begin...
5384 00:38:42.793880 ==
5385 00:38:42.796842 Dram Type= 6, Freq= 0, CH_1, rank 0
5386 00:38:42.799855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5387 00:38:42.803594 ==
5388 00:38:42.804146 Write leveling (Byte 0): 24 => 24
5389 00:38:42.806433 Write leveling (Byte 1): 24 => 24
5390 00:38:42.809786 DramcWriteLeveling(PI) end<-----
5391 00:38:42.810241
5392 00:38:42.810602 ==
5393 00:38:42.813393 Dram Type= 6, Freq= 0, CH_1, rank 0
5394 00:38:42.820002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5395 00:38:42.820550 ==
5396 00:38:42.820916 [Gating] SW mode calibration
5397 00:38:42.829902 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5398 00:38:42.833207 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5399 00:38:42.839385 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 00:38:42.843059 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 00:38:42.846009 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 00:38:42.852788 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 00:38:42.856635 0 10 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5404 00:38:42.859419 0 10 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
5405 00:38:42.865988 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 00:38:42.869254 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 00:38:42.872958 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 00:38:42.878921 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 00:38:42.882127 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 00:38:42.886002 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 00:38:42.892770 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5412 00:38:42.895793 0 11 20 | B1->B0 | 2929 4242 | 0 0 | (1 1) (0 0)
5413 00:38:42.898955 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5414 00:38:42.905508 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 00:38:42.909096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 00:38:42.912248 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 00:38:42.918837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 00:38:42.921926 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5419 00:38:42.925171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5420 00:38:42.928924 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5421 00:38:42.935244 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 00:38:42.938508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 00:38:42.945383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 00:38:42.948450 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 00:38:42.951729 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 00:38:42.955227 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 00:38:42.961986 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 00:38:42.965076 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 00:38:42.968370 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 00:38:42.975079 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 00:38:42.978314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 00:38:42.981478 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 00:38:42.988141 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 00:38:42.991594 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 00:38:42.994684 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5436 00:38:43.001458 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5437 00:38:43.004751 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 00:38:43.008174 Total UI for P1: 0, mck2ui 16
5439 00:38:43.011236 best dqsien dly found for B0: ( 0, 14, 18)
5440 00:38:43.015493 Total UI for P1: 0, mck2ui 16
5441 00:38:43.017901 best dqsien dly found for B1: ( 0, 14, 20)
5442 00:38:43.021523 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5443 00:38:43.024385 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5444 00:38:43.024955
5445 00:38:43.027742 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5446 00:38:43.034841 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5447 00:38:43.035484 [Gating] SW calibration Done
5448 00:38:43.035858 ==
5449 00:38:43.037547 Dram Type= 6, Freq= 0, CH_1, rank 0
5450 00:38:43.044724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5451 00:38:43.045267 ==
5452 00:38:43.045697 RX Vref Scan: 0
5453 00:38:43.046040
5454 00:38:43.047896 RX Vref 0 -> 0, step: 1
5455 00:38:43.048438
5456 00:38:43.051189 RX Delay -80 -> 252, step: 8
5457 00:38:43.053892 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5458 00:38:43.057447 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5459 00:38:43.061035 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5460 00:38:43.067531 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5461 00:38:43.070688 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5462 00:38:43.073823 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5463 00:38:43.077363 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5464 00:38:43.080694 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5465 00:38:43.083992 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5466 00:38:43.090244 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5467 00:38:43.093495 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5468 00:38:43.096895 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5469 00:38:43.100199 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5470 00:38:43.103690 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5471 00:38:43.110165 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5472 00:38:43.113776 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5473 00:38:43.114321 ==
5474 00:38:43.117466 Dram Type= 6, Freq= 0, CH_1, rank 0
5475 00:38:43.120146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5476 00:38:43.120694 ==
5477 00:38:43.121063 DQS Delay:
5478 00:38:43.123647 DQS0 = 0, DQS1 = 0
5479 00:38:43.124191 DQM Delay:
5480 00:38:43.126874 DQM0 = 95, DQM1 = 88
5481 00:38:43.127416 DQ Delay:
5482 00:38:43.130573 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5483 00:38:43.133271 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5484 00:38:43.136784 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5485 00:38:43.139851 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5486 00:38:43.140312
5487 00:38:43.140675
5488 00:38:43.141012 ==
5489 00:38:43.143962 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 00:38:43.149802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5491 00:38:43.150336 ==
5492 00:38:43.150700
5493 00:38:43.151037
5494 00:38:43.151360 TX Vref Scan disable
5495 00:38:43.153351 == TX Byte 0 ==
5496 00:38:43.156463 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5497 00:38:43.163438 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5498 00:38:43.164158 == TX Byte 1 ==
5499 00:38:43.166762 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5500 00:38:43.173063 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5501 00:38:43.173681 ==
5502 00:38:43.176255 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 00:38:43.179912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5504 00:38:43.180474 ==
5505 00:38:43.180843
5506 00:38:43.181181
5507 00:38:43.183230 TX Vref Scan disable
5508 00:38:43.183776 == TX Byte 0 ==
5509 00:38:43.189520 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5510 00:38:43.193031 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5511 00:38:43.193539 == TX Byte 1 ==
5512 00:38:43.199657 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5513 00:38:43.202653 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5514 00:38:43.203114
5515 00:38:43.203477 [DATLAT]
5516 00:38:43.206216 Freq=933, CH1 RK0
5517 00:38:43.206686
5518 00:38:43.207048 DATLAT Default: 0xd
5519 00:38:43.209285 0, 0xFFFF, sum = 0
5520 00:38:43.209828 1, 0xFFFF, sum = 0
5521 00:38:43.212749 2, 0xFFFF, sum = 0
5522 00:38:43.213351 3, 0xFFFF, sum = 0
5523 00:38:43.216083 4, 0xFFFF, sum = 0
5524 00:38:43.219131 5, 0xFFFF, sum = 0
5525 00:38:43.219595 6, 0xFFFF, sum = 0
5526 00:38:43.222778 7, 0xFFFF, sum = 0
5527 00:38:43.223325 8, 0xFFFF, sum = 0
5528 00:38:43.225962 9, 0xFFFF, sum = 0
5529 00:38:43.226428 10, 0x0, sum = 1
5530 00:38:43.229642 11, 0x0, sum = 2
5531 00:38:43.230195 12, 0x0, sum = 3
5532 00:38:43.230571 13, 0x0, sum = 4
5533 00:38:43.232520 best_step = 11
5534 00:38:43.232973
5535 00:38:43.233400 ==
5536 00:38:43.235859 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 00:38:43.239309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5538 00:38:43.239769 ==
5539 00:38:43.242639 RX Vref Scan: 1
5540 00:38:43.243095
5541 00:38:43.245815 RX Vref 0 -> 0, step: 1
5542 00:38:43.246274
5543 00:38:43.246639 RX Delay -69 -> 252, step: 4
5544 00:38:43.246978
5545 00:38:43.249323 Set Vref, RX VrefLevel [Byte0]: 56
5546 00:38:43.252570 [Byte1]: 48
5547 00:38:43.257369
5548 00:38:43.257896 Final RX Vref Byte 0 = 56 to rank0
5549 00:38:43.260584 Final RX Vref Byte 1 = 48 to rank0
5550 00:38:43.263773 Final RX Vref Byte 0 = 56 to rank1
5551 00:38:43.267393 Final RX Vref Byte 1 = 48 to rank1==
5552 00:38:43.270384 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 00:38:43.277116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5554 00:38:43.277718 ==
5555 00:38:43.278088 DQS Delay:
5556 00:38:43.280205 DQS0 = 0, DQS1 = 0
5557 00:38:43.280700 DQM Delay:
5558 00:38:43.281110 DQM0 = 94, DQM1 = 87
5559 00:38:43.283943 DQ Delay:
5560 00:38:43.287311 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5561 00:38:43.290398 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5562 00:38:43.293681 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5563 00:38:43.297033 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5564 00:38:43.297634
5565 00:38:43.298002
5566 00:38:43.303470 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5567 00:38:43.306916 CH1 RK0: MR19=505, MR18=3232
5568 00:38:43.313701 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5569 00:38:43.314302
5570 00:38:43.317089 ----->DramcWriteLeveling(PI) begin...
5571 00:38:43.317679 ==
5572 00:38:43.320211 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 00:38:43.323086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5574 00:38:43.323551 ==
5575 00:38:43.326554 Write leveling (Byte 0): 22 => 22
5576 00:38:43.329785 Write leveling (Byte 1): 22 => 22
5577 00:38:43.333282 DramcWriteLeveling(PI) end<-----
5578 00:38:43.333892
5579 00:38:43.334260 ==
5580 00:38:43.336448 Dram Type= 6, Freq= 0, CH_1, rank 1
5581 00:38:43.339502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5582 00:38:43.342940 ==
5583 00:38:43.343402 [Gating] SW mode calibration
5584 00:38:43.349834 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5585 00:38:43.356653 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5586 00:38:43.359574 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 00:38:43.366920 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 00:38:43.369563 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 00:38:43.373177 0 10 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5590 00:38:43.379642 0 10 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
5591 00:38:43.382682 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5592 00:38:43.386205 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 00:38:43.392304 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 00:38:43.395943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 00:38:43.399089 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 00:38:43.405745 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 00:38:43.409478 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 00:38:43.412483 0 11 16 | B1->B0 | 2626 4040 | 0 0 | (0 0) (0 0)
5599 00:38:43.419189 0 11 20 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
5600 00:38:43.422487 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5601 00:38:43.425894 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 00:38:43.432407 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 00:38:43.435889 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 00:38:43.439076 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 00:38:43.445641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 00:38:43.449095 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5607 00:38:43.452524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:38:43.459030 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:38:43.462513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 00:38:43.465860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 00:38:43.472171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 00:38:43.475416 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 00:38:43.478960 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 00:38:43.485239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 00:38:43.488988 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 00:38:43.491901 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 00:38:43.499037 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 00:38:43.502015 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 00:38:43.504977 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 00:38:43.508699 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 00:38:43.515373 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 00:38:43.518678 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5623 00:38:43.522076 Total UI for P1: 0, mck2ui 16
5624 00:38:43.525160 best dqsien dly found for B0: ( 0, 14, 14)
5625 00:38:43.528778 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5626 00:38:43.535110 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 00:38:43.538172 Total UI for P1: 0, mck2ui 16
5628 00:38:43.541702 best dqsien dly found for B1: ( 0, 14, 22)
5629 00:38:43.545030 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5630 00:38:43.548776 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5631 00:38:43.549374
5632 00:38:43.551502 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5633 00:38:43.555111 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5634 00:38:43.558017 [Gating] SW calibration Done
5635 00:38:43.558488 ==
5636 00:38:43.561428 Dram Type= 6, Freq= 0, CH_1, rank 1
5637 00:38:43.564682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5638 00:38:43.565252 ==
5639 00:38:43.568151 RX Vref Scan: 0
5640 00:38:43.568713
5641 00:38:43.571481 RX Vref 0 -> 0, step: 1
5642 00:38:43.572046
5643 00:38:43.572528 RX Delay -80 -> 252, step: 8
5644 00:38:43.578083 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5645 00:38:43.581190 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5646 00:38:43.584579 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5647 00:38:43.588160 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5648 00:38:43.591067 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5649 00:38:43.598286 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5650 00:38:43.601058 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5651 00:38:43.604656 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5652 00:38:43.608403 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5653 00:38:43.611206 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5654 00:38:43.614850 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5655 00:38:43.621105 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5656 00:38:43.624661 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5657 00:38:43.628141 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5658 00:38:43.630873 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5659 00:38:43.634232 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5660 00:38:43.637749 ==
5661 00:38:43.641018 Dram Type= 6, Freq= 0, CH_1, rank 1
5662 00:38:43.644050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5663 00:38:43.644480 ==
5664 00:38:43.644913 DQS Delay:
5665 00:38:43.647325 DQS0 = 0, DQS1 = 0
5666 00:38:43.647732 DQM Delay:
5667 00:38:43.650788 DQM0 = 98, DQM1 = 89
5668 00:38:43.651197 DQ Delay:
5669 00:38:43.653798 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =99
5670 00:38:43.657435 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =91
5671 00:38:43.660942 DQ8 =75, DQ9 =75, DQ10 =83, DQ11 =75
5672 00:38:43.663806 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5673 00:38:43.664213
5674 00:38:43.664534
5675 00:38:43.664873 ==
5676 00:38:43.667386 Dram Type= 6, Freq= 0, CH_1, rank 1
5677 00:38:43.670818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5678 00:38:43.671364 ==
5679 00:38:43.673800
5680 00:38:43.674239
5681 00:38:43.674660 TX Vref Scan disable
5682 00:38:43.677320 == TX Byte 0 ==
5683 00:38:43.680392 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5684 00:38:43.684358 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5685 00:38:43.687353 == TX Byte 1 ==
5686 00:38:43.690982 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5687 00:38:43.693704 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5688 00:38:43.694489 ==
5689 00:38:43.696948 Dram Type= 6, Freq= 0, CH_1, rank 1
5690 00:38:43.703879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5691 00:38:43.704553 ==
5692 00:38:43.704920
5693 00:38:43.705247
5694 00:38:43.705655 TX Vref Scan disable
5695 00:38:43.707903 == TX Byte 0 ==
5696 00:38:43.711688 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5697 00:38:43.714675 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5698 00:38:43.718127 == TX Byte 1 ==
5699 00:38:43.721274 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5700 00:38:43.724717 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5701 00:38:43.727948
5702 00:38:43.728357 [DATLAT]
5703 00:38:43.728685 Freq=933, CH1 RK1
5704 00:38:43.728989
5705 00:38:43.731418 DATLAT Default: 0xb
5706 00:38:43.731934 0, 0xFFFF, sum = 0
5707 00:38:43.734941 1, 0xFFFF, sum = 0
5708 00:38:43.735455 2, 0xFFFF, sum = 0
5709 00:38:43.737708 3, 0xFFFF, sum = 0
5710 00:38:43.741179 4, 0xFFFF, sum = 0
5711 00:38:43.741641 5, 0xFFFF, sum = 0
5712 00:38:43.744575 6, 0xFFFF, sum = 0
5713 00:38:43.744994 7, 0xFFFF, sum = 0
5714 00:38:43.747609 8, 0xFFFF, sum = 0
5715 00:38:43.748023 9, 0xFFFF, sum = 0
5716 00:38:43.750879 10, 0x0, sum = 1
5717 00:38:43.751297 11, 0x0, sum = 2
5718 00:38:43.754639 12, 0x0, sum = 3
5719 00:38:43.755186 13, 0x0, sum = 4
5720 00:38:43.755536 best_step = 11
5721 00:38:43.755842
5722 00:38:43.757612 ==
5723 00:38:43.760952 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 00:38:43.764167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5725 00:38:43.764581 ==
5726 00:38:43.764910 RX Vref Scan: 0
5727 00:38:43.765255
5728 00:38:43.767618 RX Vref 0 -> 0, step: 1
5729 00:38:43.768032
5730 00:38:43.771373 RX Delay -69 -> 252, step: 4
5731 00:38:43.774455 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5732 00:38:43.780851 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5733 00:38:43.783981 iDelay=203, Bit 2, Center 86 (-9 ~ 182) 192
5734 00:38:43.787533 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5735 00:38:43.790690 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5736 00:38:43.794003 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5737 00:38:43.800736 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5738 00:38:43.804117 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5739 00:38:43.807516 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5740 00:38:43.810517 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5741 00:38:43.814257 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5742 00:38:43.820936 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5743 00:38:43.824288 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5744 00:38:43.827453 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5745 00:38:43.831006 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5746 00:38:43.833733 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5747 00:38:43.834191 ==
5748 00:38:43.837552 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 00:38:43.843799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5750 00:38:43.844258 ==
5751 00:38:43.844616 DQS Delay:
5752 00:38:43.844945 DQS0 = 0, DQS1 = 0
5753 00:38:43.847140 DQM Delay:
5754 00:38:43.847594 DQM0 = 96, DQM1 = 88
5755 00:38:43.850283 DQ Delay:
5756 00:38:43.853531 DQ0 =98, DQ1 =92, DQ2 =86, DQ3 =92
5757 00:38:43.857129 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =96
5758 00:38:43.860796 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5759 00:38:43.864078 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5760 00:38:43.864630
5761 00:38:43.864995
5762 00:38:43.870222 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5763 00:38:43.874088 CH1 RK1: MR19=505, MR18=2020
5764 00:38:43.880122 CH1_RK1: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5765 00:38:43.883396 [RxdqsGatingPostProcess] freq 933
5766 00:38:43.887214 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5767 00:38:43.889832 Pre-setting of DQS Precalculation
5768 00:38:43.896422 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5769 00:38:43.902847 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5770 00:38:43.910127 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5771 00:38:43.910721
5772 00:38:43.911210
5773 00:38:43.913013 [Calibration Summary] 1866 Mbps
5774 00:38:43.916578 CH 0, Rank 0
5775 00:38:43.917137 SW Impedance : PASS
5776 00:38:43.920075 DUTY Scan : NO K
5777 00:38:43.920628 ZQ Calibration : PASS
5778 00:38:43.923088 Jitter Meter : NO K
5779 00:38:43.926446 CBT Training : PASS
5780 00:38:43.927006 Write leveling : PASS
5781 00:38:43.929426 RX DQS gating : PASS
5782 00:38:43.933171 RX DQ/DQS(RDDQC) : PASS
5783 00:38:43.933773 TX DQ/DQS : PASS
5784 00:38:43.936266 RX DATLAT : PASS
5785 00:38:43.939372 RX DQ/DQS(Engine): PASS
5786 00:38:43.939839 TX OE : NO K
5787 00:38:43.943125 All Pass.
5788 00:38:43.943684
5789 00:38:43.944048 CH 0, Rank 1
5790 00:38:43.945999 SW Impedance : PASS
5791 00:38:43.946461 DUTY Scan : NO K
5792 00:38:43.949693 ZQ Calibration : PASS
5793 00:38:43.952424 Jitter Meter : NO K
5794 00:38:43.952887 CBT Training : PASS
5795 00:38:43.956620 Write leveling : PASS
5796 00:38:43.959640 RX DQS gating : PASS
5797 00:38:43.960200 RX DQ/DQS(RDDQC) : PASS
5798 00:38:43.962813 TX DQ/DQS : PASS
5799 00:38:43.965803 RX DATLAT : PASS
5800 00:38:43.966264 RX DQ/DQS(Engine): PASS
5801 00:38:43.969252 TX OE : NO K
5802 00:38:43.969853 All Pass.
5803 00:38:43.970223
5804 00:38:43.972888 CH 1, Rank 0
5805 00:38:43.973500 SW Impedance : PASS
5806 00:38:43.975903 DUTY Scan : NO K
5807 00:38:43.978961 ZQ Calibration : PASS
5808 00:38:43.979423 Jitter Meter : NO K
5809 00:38:43.982471 CBT Training : PASS
5810 00:38:43.983036 Write leveling : PASS
5811 00:38:43.985887 RX DQS gating : PASS
5812 00:38:43.989452 RX DQ/DQS(RDDQC) : PASS
5813 00:38:43.990020 TX DQ/DQS : PASS
5814 00:38:43.992527 RX DATLAT : PASS
5815 00:38:43.995543 RX DQ/DQS(Engine): PASS
5816 00:38:43.996006 TX OE : NO K
5817 00:38:43.999228 All Pass.
5818 00:38:43.999788
5819 00:38:44.000263 CH 1, Rank 1
5820 00:38:44.002378 SW Impedance : PASS
5821 00:38:44.002840 DUTY Scan : NO K
5822 00:38:44.006004 ZQ Calibration : PASS
5823 00:38:44.009101 Jitter Meter : NO K
5824 00:38:44.009752 CBT Training : PASS
5825 00:38:44.012627 Write leveling : PASS
5826 00:38:44.015896 RX DQS gating : PASS
5827 00:38:44.016456 RX DQ/DQS(RDDQC) : PASS
5828 00:38:44.019034 TX DQ/DQS : PASS
5829 00:38:44.022748 RX DATLAT : PASS
5830 00:38:44.023305 RX DQ/DQS(Engine): PASS
5831 00:38:44.025667 TX OE : NO K
5832 00:38:44.026229 All Pass.
5833 00:38:44.026594
5834 00:38:44.028831 DramC Write-DBI off
5835 00:38:44.032187 PER_BANK_REFRESH: Hybrid Mode
5836 00:38:44.032752 TX_TRACKING: ON
5837 00:38:44.042068 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5838 00:38:44.045189 [FAST_K] Save calibration result to emmc
5839 00:38:44.048995 dramc_set_vcore_voltage set vcore to 650000
5840 00:38:44.052098 Read voltage for 400, 6
5841 00:38:44.052654 Vio18 = 0
5842 00:38:44.053020 Vcore = 650000
5843 00:38:44.055841 Vdram = 0
5844 00:38:44.056404 Vddq = 0
5845 00:38:44.056770 Vmddr = 0
5846 00:38:44.062231 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5847 00:38:44.065410 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5848 00:38:44.068493 MEM_TYPE=3, freq_sel=20
5849 00:38:44.071824 sv_algorithm_assistance_LP4_800
5850 00:38:44.075200 ============ PULL DRAM RESETB DOWN ============
5851 00:38:44.079091 ========== PULL DRAM RESETB DOWN end =========
5852 00:38:44.085225 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5853 00:38:44.088612 ===================================
5854 00:38:44.089164 LPDDR4 DRAM CONFIGURATION
5855 00:38:44.091397 ===================================
5856 00:38:44.094853 EX_ROW_EN[0] = 0x0
5857 00:38:44.097921 EX_ROW_EN[1] = 0x0
5858 00:38:44.098421 LP4Y_EN = 0x0
5859 00:38:44.101669 WORK_FSP = 0x0
5860 00:38:44.102127 WL = 0x2
5861 00:38:44.104699 RL = 0x2
5862 00:38:44.105153 BL = 0x2
5863 00:38:44.108359 RPST = 0x0
5864 00:38:44.108831 RD_PRE = 0x0
5865 00:38:44.111148 WR_PRE = 0x1
5866 00:38:44.111616 WR_PST = 0x0
5867 00:38:44.114714 DBI_WR = 0x0
5868 00:38:44.115265 DBI_RD = 0x0
5869 00:38:44.118189 OTF = 0x1
5870 00:38:44.121576 ===================================
5871 00:38:44.125028 ===================================
5872 00:38:44.125536 ANA top config
5873 00:38:44.128381 ===================================
5874 00:38:44.131833 DLL_ASYNC_EN = 0
5875 00:38:44.135235 ALL_SLAVE_EN = 1
5876 00:38:44.138195 NEW_RANK_MODE = 1
5877 00:38:44.138750 DLL_IDLE_MODE = 1
5878 00:38:44.141588 LP45_APHY_COMB_EN = 1
5879 00:38:44.144491 TX_ODT_DIS = 1
5880 00:38:44.147996 NEW_8X_MODE = 1
5881 00:38:44.151641 ===================================
5882 00:38:44.154977 ===================================
5883 00:38:44.157953 data_rate = 800
5884 00:38:44.158407 CKR = 1
5885 00:38:44.161525 DQ_P2S_RATIO = 4
5886 00:38:44.164889 ===================================
5887 00:38:44.167833 CA_P2S_RATIO = 4
5888 00:38:44.171026 DQ_CA_OPEN = 0
5889 00:38:44.174512 DQ_SEMI_OPEN = 1
5890 00:38:44.177691 CA_SEMI_OPEN = 1
5891 00:38:44.178144 CA_FULL_RATE = 0
5892 00:38:44.181196 DQ_CKDIV4_EN = 0
5893 00:38:44.184471 CA_CKDIV4_EN = 1
5894 00:38:44.188113 CA_PREDIV_EN = 0
5895 00:38:44.191352 PH8_DLY = 0
5896 00:38:44.194608 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5897 00:38:44.195064 DQ_AAMCK_DIV = 0
5898 00:38:44.197783 CA_AAMCK_DIV = 0
5899 00:38:44.201228 CA_ADMCK_DIV = 4
5900 00:38:44.204253 DQ_TRACK_CA_EN = 0
5901 00:38:44.207452 CA_PICK = 800
5902 00:38:44.211330 CA_MCKIO = 400
5903 00:38:44.214182 MCKIO_SEMI = 400
5904 00:38:44.214731 PLL_FREQ = 3016
5905 00:38:44.217692 DQ_UI_PI_RATIO = 32
5906 00:38:44.220629 CA_UI_PI_RATIO = 32
5907 00:38:44.224484 ===================================
5908 00:38:44.227635 ===================================
5909 00:38:44.231036 memory_type:LPDDR4
5910 00:38:44.234017 GP_NUM : 10
5911 00:38:44.234478 SRAM_EN : 1
5912 00:38:44.237750 MD32_EN : 0
5913 00:38:44.240581 ===================================
5914 00:38:44.241039 [ANA_INIT] >>>>>>>>>>>>>>
5915 00:38:44.244474 <<<<<< [CONFIGURE PHASE]: ANA_TX
5916 00:38:44.247134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5917 00:38:44.250572 ===================================
5918 00:38:44.253973 data_rate = 800,PCW = 0X7400
5919 00:38:44.257190 ===================================
5920 00:38:44.260930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5921 00:38:44.267366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5922 00:38:44.277212 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5923 00:38:44.283776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5924 00:38:44.287121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5925 00:38:44.290418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5926 00:38:44.290885 [ANA_INIT] flow start
5927 00:38:44.293975 [ANA_INIT] PLL >>>>>>>>
5928 00:38:44.296971 [ANA_INIT] PLL <<<<<<<<
5929 00:38:44.297481 [ANA_INIT] MIDPI >>>>>>>>
5930 00:38:44.300339 [ANA_INIT] MIDPI <<<<<<<<
5931 00:38:44.303484 [ANA_INIT] DLL >>>>>>>>
5932 00:38:44.303945 [ANA_INIT] flow end
5933 00:38:44.310256 ============ LP4 DIFF to SE enter ============
5934 00:38:44.313387 ============ LP4 DIFF to SE exit ============
5935 00:38:44.316528 [ANA_INIT] <<<<<<<<<<<<<
5936 00:38:44.319926 [Flow] Enable top DCM control >>>>>
5937 00:38:44.323512 [Flow] Enable top DCM control <<<<<
5938 00:38:44.326668 Enable DLL master slave shuffle
5939 00:38:44.330028 ==============================================================
5940 00:38:44.333389 Gating Mode config
5941 00:38:44.336795 ==============================================================
5942 00:38:44.339843 Config description:
5943 00:38:44.350270 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5944 00:38:44.356619 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5945 00:38:44.359586 SELPH_MODE 0: By rank 1: By Phase
5946 00:38:44.366348 ==============================================================
5947 00:38:44.369861 GAT_TRACK_EN = 0
5948 00:38:44.373281 RX_GATING_MODE = 2
5949 00:38:44.376578 RX_GATING_TRACK_MODE = 2
5950 00:38:44.379778 SELPH_MODE = 1
5951 00:38:44.382914 PICG_EARLY_EN = 1
5952 00:38:44.386688 VALID_LAT_VALUE = 1
5953 00:38:44.389696 ==============================================================
5954 00:38:44.392656 Enter into Gating configuration >>>>
5955 00:38:44.396201 Exit from Gating configuration <<<<
5956 00:38:44.399420 Enter into DVFS_PRE_config >>>>>
5957 00:38:44.412677 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5958 00:38:44.413235 Exit from DVFS_PRE_config <<<<<
5959 00:38:44.415932 Enter into PICG configuration >>>>
5960 00:38:44.419318 Exit from PICG configuration <<<<
5961 00:38:44.422916 [RX_INPUT] configuration >>>>>
5962 00:38:44.425762 [RX_INPUT] configuration <<<<<
5963 00:38:44.432682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5964 00:38:44.436138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5965 00:38:44.442500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5966 00:38:44.449044 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5967 00:38:44.455869 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5968 00:38:44.462675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5969 00:38:44.465734 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5970 00:38:44.469141 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5971 00:38:44.472757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5972 00:38:44.478986 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5973 00:38:44.482198 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5974 00:38:44.485484 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5975 00:38:44.489019 ===================================
5976 00:38:44.492122 LPDDR4 DRAM CONFIGURATION
5977 00:38:44.495556 ===================================
5978 00:38:44.496013 EX_ROW_EN[0] = 0x0
5979 00:38:44.499165 EX_ROW_EN[1] = 0x0
5980 00:38:44.502557 LP4Y_EN = 0x0
5981 00:38:44.502970 WORK_FSP = 0x0
5982 00:38:44.505725 WL = 0x2
5983 00:38:44.506186 RL = 0x2
5984 00:38:44.508957 BL = 0x2
5985 00:38:44.509391 RPST = 0x0
5986 00:38:44.512292 RD_PRE = 0x0
5987 00:38:44.512791 WR_PRE = 0x1
5988 00:38:44.515522 WR_PST = 0x0
5989 00:38:44.515980 DBI_WR = 0x0
5990 00:38:44.519006 DBI_RD = 0x0
5991 00:38:44.519418 OTF = 0x1
5992 00:38:44.522417 ===================================
5993 00:38:44.525855 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5994 00:38:44.532425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5995 00:38:44.535587 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5996 00:38:44.538580 ===================================
5997 00:38:44.542000 LPDDR4 DRAM CONFIGURATION
5998 00:38:44.545552 ===================================
5999 00:38:44.545969 EX_ROW_EN[0] = 0x10
6000 00:38:44.548759 EX_ROW_EN[1] = 0x0
6001 00:38:44.549170 LP4Y_EN = 0x0
6002 00:38:44.551853 WORK_FSP = 0x0
6003 00:38:44.552263 WL = 0x2
6004 00:38:44.555384 RL = 0x2
6005 00:38:44.558896 BL = 0x2
6006 00:38:44.559309 RPST = 0x0
6007 00:38:44.562089 RD_PRE = 0x0
6008 00:38:44.562502 WR_PRE = 0x1
6009 00:38:44.565455 WR_PST = 0x0
6010 00:38:44.565869 DBI_WR = 0x0
6011 00:38:44.569158 DBI_RD = 0x0
6012 00:38:44.569713 OTF = 0x1
6013 00:38:44.571874 ===================================
6014 00:38:44.578891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6015 00:38:44.582826 nWR fixed to 30
6016 00:38:44.585839 [ModeRegInit_LP4] CH0 RK0
6017 00:38:44.586391 [ModeRegInit_LP4] CH0 RK1
6018 00:38:44.589001 [ModeRegInit_LP4] CH1 RK0
6019 00:38:44.592447 [ModeRegInit_LP4] CH1 RK1
6020 00:38:44.592995 match AC timing 18
6021 00:38:44.599224 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6022 00:38:44.602398 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6023 00:38:44.605535 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6024 00:38:44.612654 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6025 00:38:44.615989 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6026 00:38:44.616537 ==
6027 00:38:44.619310 Dram Type= 6, Freq= 0, CH_0, rank 0
6028 00:38:44.622599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6029 00:38:44.623153 ==
6030 00:38:44.629441 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6031 00:38:44.635809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6032 00:38:44.639187 [CA 0] Center 36 (8~64) winsize 57
6033 00:38:44.642556 [CA 1] Center 36 (8~64) winsize 57
6034 00:38:44.645495 [CA 2] Center 36 (8~64) winsize 57
6035 00:38:44.645951 [CA 3] Center 36 (8~64) winsize 57
6036 00:38:44.648744 [CA 4] Center 36 (8~64) winsize 57
6037 00:38:44.652480 [CA 5] Center 36 (8~64) winsize 57
6038 00:38:44.653029
6039 00:38:44.659361 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6040 00:38:44.659906
6041 00:38:44.662144 [CATrainingPosCal] consider 1 rank data
6042 00:38:44.665544 u2DelayCellTimex100 = 270/100 ps
6043 00:38:44.668975 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6044 00:38:44.672308 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6045 00:38:44.675243 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6046 00:38:44.678763 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6047 00:38:44.682114 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6048 00:38:44.685793 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6049 00:38:44.686413
6050 00:38:44.688663 CA PerBit enable=1, Macro0, CA PI delay=36
6051 00:38:44.689251
6052 00:38:44.691947 [CBTSetCACLKResult] CA Dly = 36
6053 00:38:44.695224 CS Dly: 1 (0~32)
6054 00:38:44.695834 ==
6055 00:38:44.698934 Dram Type= 6, Freq= 0, CH_0, rank 1
6056 00:38:44.701845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6057 00:38:44.702303 ==
6058 00:38:44.708795 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6059 00:38:44.715382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6060 00:38:44.715892 [CA 0] Center 36 (8~64) winsize 57
6061 00:38:44.718487 [CA 1] Center 36 (8~64) winsize 57
6062 00:38:44.722029 [CA 2] Center 36 (8~64) winsize 57
6063 00:38:44.724999 [CA 3] Center 36 (8~64) winsize 57
6064 00:38:44.728801 [CA 4] Center 36 (8~64) winsize 57
6065 00:38:44.732257 [CA 5] Center 36 (8~64) winsize 57
6066 00:38:44.732765
6067 00:38:44.734976 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6068 00:38:44.735538
6069 00:38:44.738277 [CATrainingPosCal] consider 2 rank data
6070 00:38:44.741466 u2DelayCellTimex100 = 270/100 ps
6071 00:38:44.744502 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 00:38:44.751410 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 00:38:44.754687 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 00:38:44.757965 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6075 00:38:44.761282 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6076 00:38:44.764774 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6077 00:38:44.765357
6078 00:38:44.767966 CA PerBit enable=1, Macro0, CA PI delay=36
6079 00:38:44.768382
6080 00:38:44.771521 [CBTSetCACLKResult] CA Dly = 36
6081 00:38:44.771934 CS Dly: 1 (0~32)
6082 00:38:44.775128
6083 00:38:44.778103 ----->DramcWriteLeveling(PI) begin...
6084 00:38:44.778526 ==
6085 00:38:44.781173 Dram Type= 6, Freq= 0, CH_0, rank 0
6086 00:38:44.784359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6087 00:38:44.784772 ==
6088 00:38:44.787940 Write leveling (Byte 0): 32 => 0
6089 00:38:44.791260 Write leveling (Byte 1): 32 => 0
6090 00:38:44.794317 DramcWriteLeveling(PI) end<-----
6091 00:38:44.794732
6092 00:38:44.795062 ==
6093 00:38:44.797789 Dram Type= 6, Freq= 0, CH_0, rank 0
6094 00:38:44.801530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6095 00:38:44.802086 ==
6096 00:38:44.804787 [Gating] SW mode calibration
6097 00:38:44.811126 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6098 00:38:44.817748 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6099 00:38:44.821126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6100 00:38:44.824317 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6101 00:38:44.831359 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6102 00:38:44.834570 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6103 00:38:44.837776 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6104 00:38:44.841122 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6105 00:38:44.847871 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6106 00:38:44.850995 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6107 00:38:44.854148 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6108 00:38:44.857472 Total UI for P1: 0, mck2ui 16
6109 00:38:44.860979 best dqsien dly found for B0: ( 0, 10, 16)
6110 00:38:44.864264 Total UI for P1: 0, mck2ui 16
6111 00:38:44.867663 best dqsien dly found for B1: ( 0, 10, 16)
6112 00:38:44.870808 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6113 00:38:44.877472 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6114 00:38:44.877881
6115 00:38:44.880884 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6116 00:38:44.884112 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6117 00:38:44.887696 [Gating] SW calibration Done
6118 00:38:44.888222 ==
6119 00:38:44.890912 Dram Type= 6, Freq= 0, CH_0, rank 0
6120 00:38:44.894096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6121 00:38:44.894507 ==
6122 00:38:44.897337 RX Vref Scan: 0
6123 00:38:44.897750
6124 00:38:44.898266 RX Vref 0 -> 0, step: 1
6125 00:38:44.898752
6126 00:38:44.900615 RX Delay -410 -> 252, step: 16
6127 00:38:44.903900 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6128 00:38:44.910681 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6129 00:38:44.914107 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6130 00:38:44.917594 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6131 00:38:44.920643 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6132 00:38:44.927300 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6133 00:38:44.930641 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6134 00:38:44.934379 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6135 00:38:44.937369 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6136 00:38:44.944255 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6137 00:38:44.946726 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6138 00:38:44.950097 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6139 00:38:44.957131 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6140 00:38:44.960187 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6141 00:38:44.963705 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6142 00:38:44.966681 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6143 00:38:44.967096 ==
6144 00:38:44.970237 Dram Type= 6, Freq= 0, CH_0, rank 0
6145 00:38:44.976903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6146 00:38:44.977453 ==
6147 00:38:44.977792 DQS Delay:
6148 00:38:44.979866 DQS0 = 51, DQS1 = 59
6149 00:38:44.980272 DQM Delay:
6150 00:38:44.983432 DQM0 = 12, DQM1 = 16
6151 00:38:44.983840 DQ Delay:
6152 00:38:44.986999 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6153 00:38:44.990077 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6154 00:38:44.993155 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6155 00:38:44.996554 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6156 00:38:44.996975
6157 00:38:44.997348
6158 00:38:44.997664 ==
6159 00:38:45.000308 Dram Type= 6, Freq= 0, CH_0, rank 0
6160 00:38:45.003174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6161 00:38:45.003608 ==
6162 00:38:45.003936
6163 00:38:45.004236
6164 00:38:45.006767 TX Vref Scan disable
6165 00:38:45.007175 == TX Byte 0 ==
6166 00:38:45.013237 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6167 00:38:45.016671 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6168 00:38:45.017219 == TX Byte 1 ==
6169 00:38:45.023213 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6170 00:38:45.026620 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6171 00:38:45.027142 ==
6172 00:38:45.029532 Dram Type= 6, Freq= 0, CH_0, rank 0
6173 00:38:45.033063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6174 00:38:45.033621 ==
6175 00:38:45.033956
6176 00:38:45.034258
6177 00:38:45.036540 TX Vref Scan disable
6178 00:38:45.037074 == TX Byte 0 ==
6179 00:38:45.042631 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6180 00:38:45.046391 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6181 00:38:45.049370 == TX Byte 1 ==
6182 00:38:45.052873 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6183 00:38:45.056062 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6184 00:38:45.056581
6185 00:38:45.057017 [DATLAT]
6186 00:38:45.059626 Freq=400, CH0 RK0
6187 00:38:45.060148
6188 00:38:45.060587 DATLAT Default: 0xf
6189 00:38:45.062826 0, 0xFFFF, sum = 0
6190 00:38:45.065916 1, 0xFFFF, sum = 0
6191 00:38:45.066396 2, 0xFFFF, sum = 0
6192 00:38:45.069618 3, 0xFFFF, sum = 0
6193 00:38:45.070189 4, 0xFFFF, sum = 0
6194 00:38:45.072718 5, 0xFFFF, sum = 0
6195 00:38:45.073194 6, 0xFFFF, sum = 0
6196 00:38:45.076094 7, 0xFFFF, sum = 0
6197 00:38:45.076660 8, 0xFFFF, sum = 0
6198 00:38:45.079362 9, 0xFFFF, sum = 0
6199 00:38:45.079933 10, 0xFFFF, sum = 0
6200 00:38:45.082966 11, 0xFFFF, sum = 0
6201 00:38:45.083534 12, 0x0, sum = 1
6202 00:38:45.086022 13, 0x0, sum = 2
6203 00:38:45.086499 14, 0x0, sum = 3
6204 00:38:45.089441 15, 0x0, sum = 4
6205 00:38:45.090004 best_step = 13
6206 00:38:45.090487
6207 00:38:45.090935 ==
6208 00:38:45.092597 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 00:38:45.095945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6210 00:38:45.096484 ==
6211 00:38:45.099592 RX Vref Scan: 1
6212 00:38:45.100158
6213 00:38:45.102970 RX Vref 0 -> 0, step: 1
6214 00:38:45.103443
6215 00:38:45.103918 RX Delay -359 -> 252, step: 8
6216 00:38:45.105949
6217 00:38:45.106416 Set Vref, RX VrefLevel [Byte0]: 53
6218 00:38:45.109598 [Byte1]: 50
6219 00:38:45.114940
6220 00:38:45.115413 Final RX Vref Byte 0 = 53 to rank0
6221 00:38:45.118348 Final RX Vref Byte 1 = 50 to rank0
6222 00:38:45.121947 Final RX Vref Byte 0 = 53 to rank1
6223 00:38:45.125248 Final RX Vref Byte 1 = 50 to rank1==
6224 00:38:45.128168 Dram Type= 6, Freq= 0, CH_0, rank 0
6225 00:38:45.135115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6226 00:38:45.135685 ==
6227 00:38:45.136176 DQS Delay:
6228 00:38:45.137888 DQS0 = 52, DQS1 = 68
6229 00:38:45.138358 DQM Delay:
6230 00:38:45.138837 DQM0 = 8, DQM1 = 17
6231 00:38:45.141819 DQ Delay:
6232 00:38:45.144507 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6233 00:38:45.144957 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6234 00:38:45.148562 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6235 00:38:45.151275 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6236 00:38:45.151729
6237 00:38:45.152175
6238 00:38:45.161392 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6239 00:38:45.165090 CH0 RK0: MR19=C0C, MR18=A3A3
6240 00:38:45.171563 CH0_RK0: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6241 00:38:45.172183 ==
6242 00:38:45.174720 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 00:38:45.177862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6244 00:38:45.178321 ==
6245 00:38:45.181248 [Gating] SW mode calibration
6246 00:38:45.187807 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6247 00:38:45.191100 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6248 00:38:45.197663 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6249 00:38:45.201153 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6250 00:38:45.204382 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6251 00:38:45.210931 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6252 00:38:45.214288 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6253 00:38:45.217750 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6254 00:38:45.224198 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6255 00:38:45.227344 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6256 00:38:45.231131 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6257 00:38:45.234331 Total UI for P1: 0, mck2ui 16
6258 00:38:45.237541 best dqsien dly found for B0: ( 0, 10, 16)
6259 00:38:45.240610 Total UI for P1: 0, mck2ui 16
6260 00:38:45.244028 best dqsien dly found for B1: ( 0, 10, 16)
6261 00:38:45.247269 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6262 00:38:45.253861 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6263 00:38:45.254321
6264 00:38:45.257358 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6265 00:38:45.260672 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6266 00:38:45.263952 [Gating] SW calibration Done
6267 00:38:45.264410 ==
6268 00:38:45.267217 Dram Type= 6, Freq= 0, CH_0, rank 1
6269 00:38:45.270309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6270 00:38:45.270776 ==
6271 00:38:45.273786 RX Vref Scan: 0
6272 00:38:45.274337
6273 00:38:45.274701 RX Vref 0 -> 0, step: 1
6274 00:38:45.275040
6275 00:38:45.277149 RX Delay -410 -> 252, step: 16
6276 00:38:45.283690 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6277 00:38:45.287210 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6278 00:38:45.290205 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6279 00:38:45.293712 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6280 00:38:45.300210 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6281 00:38:45.303437 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6282 00:38:45.306675 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6283 00:38:45.310086 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6284 00:38:45.316601 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6285 00:38:45.320013 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6286 00:38:45.323429 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6287 00:38:45.326684 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6288 00:38:45.332828 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6289 00:38:45.336490 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6290 00:38:45.340017 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6291 00:38:45.343036 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6292 00:38:45.346396 ==
6293 00:38:45.349840 Dram Type= 6, Freq= 0, CH_0, rank 1
6294 00:38:45.352901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6295 00:38:45.353385 ==
6296 00:38:45.353754 DQS Delay:
6297 00:38:45.356598 DQS0 = 43, DQS1 = 59
6298 00:38:45.357052 DQM Delay:
6299 00:38:45.359729 DQM0 = 7, DQM1 = 15
6300 00:38:45.360182 DQ Delay:
6301 00:38:45.363287 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6302 00:38:45.366337 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6303 00:38:45.369714 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6304 00:38:45.373208 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6305 00:38:45.373784
6306 00:38:45.374148
6307 00:38:45.374484 ==
6308 00:38:45.376393 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 00:38:45.379732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6310 00:38:45.380305 ==
6311 00:38:45.380672
6312 00:38:45.381006
6313 00:38:45.383274 TX Vref Scan disable
6314 00:38:45.383822 == TX Byte 0 ==
6315 00:38:45.390080 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6316 00:38:45.393050 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6317 00:38:45.393551 == TX Byte 1 ==
6318 00:38:45.396373 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6319 00:38:45.403206 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6320 00:38:45.403876 ==
6321 00:38:45.406220 Dram Type= 6, Freq= 0, CH_0, rank 1
6322 00:38:45.409496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6323 00:38:45.409955 ==
6324 00:38:45.410320
6325 00:38:45.410654
6326 00:38:45.412719 TX Vref Scan disable
6327 00:38:45.413191 == TX Byte 0 ==
6328 00:38:45.419523 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6329 00:38:45.422931 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6330 00:38:45.423387 == TX Byte 1 ==
6331 00:38:45.429142 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6332 00:38:45.432571 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6333 00:38:45.433250
6334 00:38:45.433859 [DATLAT]
6335 00:38:45.435660 Freq=400, CH0 RK1
6336 00:38:45.436190
6337 00:38:45.436678 DATLAT Default: 0xd
6338 00:38:45.439101 0, 0xFFFF, sum = 0
6339 00:38:45.439581 1, 0xFFFF, sum = 0
6340 00:38:45.442487 2, 0xFFFF, sum = 0
6341 00:38:45.442968 3, 0xFFFF, sum = 0
6342 00:38:45.445644 4, 0xFFFF, sum = 0
6343 00:38:45.446069 5, 0xFFFF, sum = 0
6344 00:38:45.448880 6, 0xFFFF, sum = 0
6345 00:38:45.449283 7, 0xFFFF, sum = 0
6346 00:38:45.452394 8, 0xFFFF, sum = 0
6347 00:38:45.452789 9, 0xFFFF, sum = 0
6348 00:38:45.456124 10, 0xFFFF, sum = 0
6349 00:38:45.459037 11, 0xFFFF, sum = 0
6350 00:38:45.459341 12, 0x0, sum = 1
6351 00:38:45.459578 13, 0x0, sum = 2
6352 00:38:45.462196 14, 0x0, sum = 3
6353 00:38:45.462659 15, 0x0, sum = 4
6354 00:38:45.466037 best_step = 13
6355 00:38:45.466585
6356 00:38:45.466945 ==
6357 00:38:45.469096 Dram Type= 6, Freq= 0, CH_0, rank 1
6358 00:38:45.472740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6359 00:38:45.473377 ==
6360 00:38:45.476035 RX Vref Scan: 0
6361 00:38:45.476584
6362 00:38:45.476944 RX Vref 0 -> 0, step: 1
6363 00:38:45.477283
6364 00:38:45.478952 RX Delay -359 -> 252, step: 8
6365 00:38:45.487625 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6366 00:38:45.490840 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6367 00:38:45.493798 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6368 00:38:45.497068 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6369 00:38:45.503842 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6370 00:38:45.507282 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6371 00:38:45.511105 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6372 00:38:45.514119 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6373 00:38:45.520704 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6374 00:38:45.523969 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6375 00:38:45.526925 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6376 00:38:45.533486 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6377 00:38:45.537441 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6378 00:38:45.540785 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6379 00:38:45.543652 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6380 00:38:45.550268 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6381 00:38:45.550779 ==
6382 00:38:45.553596 Dram Type= 6, Freq= 0, CH_0, rank 1
6383 00:38:45.557467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6384 00:38:45.558011 ==
6385 00:38:45.558376 DQS Delay:
6386 00:38:45.560388 DQS0 = 52, DQS1 = 60
6387 00:38:45.561006 DQM Delay:
6388 00:38:45.563608 DQM0 = 10, DQM1 = 10
6389 00:38:45.564066 DQ Delay:
6390 00:38:45.567207 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6391 00:38:45.570427 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6392 00:38:45.573649 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6393 00:38:45.577144 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6394 00:38:45.577724
6395 00:38:45.578085
6396 00:38:45.583589 [DQSOSCAuto] RK1, (LSB)MR18= 0xc8c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6397 00:38:45.587048 CH0 RK1: MR19=C0C, MR18=C8C8
6398 00:38:45.593477 CH0_RK1: MR19=0xC0C, MR18=0xC8C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6399 00:38:45.596988 [RxdqsGatingPostProcess] freq 400
6400 00:38:45.603351 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6401 00:38:45.603896 Pre-setting of DQS Precalculation
6402 00:38:45.610203 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6403 00:38:45.610662 ==
6404 00:38:45.613391 Dram Type= 6, Freq= 0, CH_1, rank 0
6405 00:38:45.616637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6406 00:38:45.617170 ==
6407 00:38:45.623733 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6408 00:38:45.629923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6409 00:38:45.633488 [CA 0] Center 36 (8~64) winsize 57
6410 00:38:45.636737 [CA 1] Center 36 (8~64) winsize 57
6411 00:38:45.640074 [CA 2] Center 36 (8~64) winsize 57
6412 00:38:45.643054 [CA 3] Center 36 (8~64) winsize 57
6413 00:38:45.643607 [CA 4] Center 36 (8~64) winsize 57
6414 00:38:45.646628 [CA 5] Center 36 (8~64) winsize 57
6415 00:38:45.647175
6416 00:38:45.653419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6417 00:38:45.653977
6418 00:38:45.656539 [CATrainingPosCal] consider 1 rank data
6419 00:38:45.660003 u2DelayCellTimex100 = 270/100 ps
6420 00:38:45.662795 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6421 00:38:45.665985 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6422 00:38:45.669453 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6423 00:38:45.672903 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6424 00:38:45.676779 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6425 00:38:45.680099 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6426 00:38:45.680665
6427 00:38:45.682854 CA PerBit enable=1, Macro0, CA PI delay=36
6428 00:38:45.683499
6429 00:38:45.686141 [CBTSetCACLKResult] CA Dly = 36
6430 00:38:45.689555 CS Dly: 1 (0~32)
6431 00:38:45.690012 ==
6432 00:38:45.693135 Dram Type= 6, Freq= 0, CH_1, rank 1
6433 00:38:45.696081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6434 00:38:45.696574 ==
6435 00:38:45.702762 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6436 00:38:45.709120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6437 00:38:45.709659 [CA 0] Center 36 (8~64) winsize 57
6438 00:38:45.712767 [CA 1] Center 36 (8~64) winsize 57
6439 00:38:45.716149 [CA 2] Center 36 (8~64) winsize 57
6440 00:38:45.719576 [CA 3] Center 36 (8~64) winsize 57
6441 00:38:45.722554 [CA 4] Center 36 (8~64) winsize 57
6442 00:38:45.725910 [CA 5] Center 36 (8~64) winsize 57
6443 00:38:45.726465
6444 00:38:45.729473 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6445 00:38:45.730024
6446 00:38:45.732688 [CATrainingPosCal] consider 2 rank data
6447 00:38:45.736268 u2DelayCellTimex100 = 270/100 ps
6448 00:38:45.739080 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 00:38:45.745886 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 00:38:45.748918 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 00:38:45.752486 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6452 00:38:45.755568 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6453 00:38:45.759336 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6454 00:38:45.759957
6455 00:38:45.762494 CA PerBit enable=1, Macro0, CA PI delay=36
6456 00:38:45.762971
6457 00:38:45.765470 [CBTSetCACLKResult] CA Dly = 36
6458 00:38:45.768795 CS Dly: 1 (0~32)
6459 00:38:45.769246
6460 00:38:45.772408 ----->DramcWriteLeveling(PI) begin...
6461 00:38:45.772957 ==
6462 00:38:45.775850 Dram Type= 6, Freq= 0, CH_1, rank 0
6463 00:38:45.778837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6464 00:38:45.779321 ==
6465 00:38:45.782431 Write leveling (Byte 0): 32 => 0
6466 00:38:45.785442 Write leveling (Byte 1): 32 => 0
6467 00:38:45.789049 DramcWriteLeveling(PI) end<-----
6468 00:38:45.789672
6469 00:38:45.790059 ==
6470 00:38:45.791985 Dram Type= 6, Freq= 0, CH_1, rank 0
6471 00:38:45.795640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6472 00:38:45.796094 ==
6473 00:38:45.798545 [Gating] SW mode calibration
6474 00:38:45.805504 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 00:38:45.812306 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6476 00:38:45.815169 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 00:38:45.818771 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 00:38:45.825432 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 00:38:45.828225 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6480 00:38:45.831601 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 00:38:45.838088 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 00:38:45.841259 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 00:38:45.844717 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6484 00:38:45.851561 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 00:38:45.852022 Total UI for P1: 0, mck2ui 16
6486 00:38:45.857928 best dqsien dly found for B0: ( 0, 10, 16)
6487 00:38:45.858390 Total UI for P1: 0, mck2ui 16
6488 00:38:45.864630 best dqsien dly found for B1: ( 0, 10, 16)
6489 00:38:45.867792 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6490 00:38:45.871210 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6491 00:38:45.871741
6492 00:38:45.874375 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6493 00:38:45.877651 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6494 00:38:45.881119 [Gating] SW calibration Done
6495 00:38:45.881713 ==
6496 00:38:45.884222 Dram Type= 6, Freq= 0, CH_1, rank 0
6497 00:38:45.888068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6498 00:38:45.888628 ==
6499 00:38:45.891172 RX Vref Scan: 0
6500 00:38:45.891731
6501 00:38:45.892096 RX Vref 0 -> 0, step: 1
6502 00:38:45.894477
6503 00:38:45.894935 RX Delay -410 -> 252, step: 16
6504 00:38:45.900814 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6505 00:38:45.903924 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6506 00:38:45.907238 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6507 00:38:45.910720 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6508 00:38:45.917261 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6509 00:38:45.921014 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6510 00:38:45.924289 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6511 00:38:45.930480 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6512 00:38:45.933618 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6513 00:38:45.937064 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6514 00:38:45.940561 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6515 00:38:45.946913 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6516 00:38:45.950215 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6517 00:38:45.953417 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6518 00:38:45.956988 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6519 00:38:45.963369 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6520 00:38:45.963929 ==
6521 00:38:45.966854 Dram Type= 6, Freq= 0, CH_1, rank 0
6522 00:38:45.970434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6523 00:38:45.970887 ==
6524 00:38:45.971243 DQS Delay:
6525 00:38:45.973332 DQS0 = 43, DQS1 = 59
6526 00:38:45.973742 DQM Delay:
6527 00:38:45.976765 DQM0 = 6, DQM1 = 15
6528 00:38:45.977169 DQ Delay:
6529 00:38:45.980128 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6530 00:38:45.983401 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6531 00:38:45.986778 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6532 00:38:45.990007 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6533 00:38:45.990441
6534 00:38:45.990790
6535 00:38:45.991091 ==
6536 00:38:45.992988 Dram Type= 6, Freq= 0, CH_1, rank 0
6537 00:38:45.996624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6538 00:38:45.997176 ==
6539 00:38:45.997882
6540 00:38:45.998392
6541 00:38:45.999722 TX Vref Scan disable
6542 00:38:46.002824 == TX Byte 0 ==
6543 00:38:46.006354 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6544 00:38:46.009737 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6545 00:38:46.012978 == TX Byte 1 ==
6546 00:38:46.016469 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6547 00:38:46.019770 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6548 00:38:46.020197 ==
6549 00:38:46.023076 Dram Type= 6, Freq= 0, CH_1, rank 0
6550 00:38:46.029336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6551 00:38:46.029772 ==
6552 00:38:46.030201
6553 00:38:46.030601
6554 00:38:46.030992 TX Vref Scan disable
6555 00:38:46.032905 == TX Byte 0 ==
6556 00:38:46.035989 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6557 00:38:46.039310 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6558 00:38:46.042630 == TX Byte 1 ==
6559 00:38:46.045886 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6560 00:38:46.048960 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6561 00:38:46.049437
6562 00:38:46.052396 [DATLAT]
6563 00:38:46.052841 Freq=400, CH1 RK0
6564 00:38:46.053399
6565 00:38:46.056228 DATLAT Default: 0xf
6566 00:38:46.056733 0, 0xFFFF, sum = 0
6567 00:38:46.059409 1, 0xFFFF, sum = 0
6568 00:38:46.059939 2, 0xFFFF, sum = 0
6569 00:38:46.062518 3, 0xFFFF, sum = 0
6570 00:38:46.062947 4, 0xFFFF, sum = 0
6571 00:38:46.065642 5, 0xFFFF, sum = 0
6572 00:38:46.066072 6, 0xFFFF, sum = 0
6573 00:38:46.069376 7, 0xFFFF, sum = 0
6574 00:38:46.069806 8, 0xFFFF, sum = 0
6575 00:38:46.072493 9, 0xFFFF, sum = 0
6576 00:38:46.076314 10, 0xFFFF, sum = 0
6577 00:38:46.076846 11, 0xFFFF, sum = 0
6578 00:38:46.079377 12, 0x0, sum = 1
6579 00:38:46.079856 13, 0x0, sum = 2
6580 00:38:46.082569 14, 0x0, sum = 3
6581 00:38:46.083143 15, 0x0, sum = 4
6582 00:38:46.083688 best_step = 13
6583 00:38:46.084193
6584 00:38:46.085504 ==
6585 00:38:46.088638 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 00:38:46.092552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6587 00:38:46.093099 ==
6588 00:38:46.093648 RX Vref Scan: 1
6589 00:38:46.094058
6590 00:38:46.095575 RX Vref 0 -> 0, step: 1
6591 00:38:46.096080
6592 00:38:46.099052 RX Delay -359 -> 252, step: 8
6593 00:38:46.099474
6594 00:38:46.101992 Set Vref, RX VrefLevel [Byte0]: 56
6595 00:38:46.105248 [Byte1]: 48
6596 00:38:46.109193
6597 00:38:46.109811 Final RX Vref Byte 0 = 56 to rank0
6598 00:38:46.112615 Final RX Vref Byte 1 = 48 to rank0
6599 00:38:46.115748 Final RX Vref Byte 0 = 56 to rank1
6600 00:38:46.119192 Final RX Vref Byte 1 = 48 to rank1==
6601 00:38:46.122548 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 00:38:46.128836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6603 00:38:46.129261 ==
6604 00:38:46.129721 DQS Delay:
6605 00:38:46.132268 DQS0 = 48, DQS1 = 64
6606 00:38:46.132690 DQM Delay:
6607 00:38:46.133117 DQM0 = 7, DQM1 = 17
6608 00:38:46.135390 DQ Delay:
6609 00:38:46.138701 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =4
6610 00:38:46.139126 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6611 00:38:46.142060 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6612 00:38:46.145442 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =28
6613 00:38:46.145866
6614 00:38:46.146288
6615 00:38:46.155607 [DQSOSCAuto] RK0, (LSB)MR18= 0xd6d6, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6616 00:38:46.158667 CH1 RK0: MR19=C0C, MR18=D6D6
6617 00:38:46.165396 CH1_RK0: MR19=0xC0C, MR18=0xD6D6, DQSOSC=383, MR23=63, INC=402, DEC=268
6618 00:38:46.165833 ==
6619 00:38:46.168606 Dram Type= 6, Freq= 0, CH_1, rank 1
6620 00:38:46.171802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6621 00:38:46.172222 ==
6622 00:38:46.175310 [Gating] SW mode calibration
6623 00:38:46.182159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6624 00:38:46.185408 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6625 00:38:46.191983 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6626 00:38:46.195106 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6627 00:38:46.198483 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6628 00:38:46.205164 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6629 00:38:46.208531 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6630 00:38:46.212019 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6631 00:38:46.218283 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6632 00:38:46.221783 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6633 00:38:46.224909 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6634 00:38:46.228477 Total UI for P1: 0, mck2ui 16
6635 00:38:46.231698 best dqsien dly found for B0: ( 0, 10, 16)
6636 00:38:46.235069 Total UI for P1: 0, mck2ui 16
6637 00:38:46.238557 best dqsien dly found for B1: ( 0, 10, 16)
6638 00:38:46.241337 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6639 00:38:46.248713 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6640 00:38:46.249227
6641 00:38:46.252144 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6642 00:38:46.255018 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6643 00:38:46.258186 [Gating] SW calibration Done
6644 00:38:46.258662 ==
6645 00:38:46.261742 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 00:38:46.264740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6647 00:38:46.265154 ==
6648 00:38:46.268202 RX Vref Scan: 0
6649 00:38:46.268709
6650 00:38:46.269106 RX Vref 0 -> 0, step: 1
6651 00:38:46.269487
6652 00:38:46.271425 RX Delay -410 -> 252, step: 16
6653 00:38:46.274767 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6654 00:38:46.281680 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6655 00:38:46.284715 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6656 00:38:46.287892 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6657 00:38:46.291581 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6658 00:38:46.298215 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6659 00:38:46.301626 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6660 00:38:46.304559 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6661 00:38:46.307903 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6662 00:38:46.314750 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6663 00:38:46.317992 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6664 00:38:46.321267 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6665 00:38:46.324729 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6666 00:38:46.331324 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6667 00:38:46.334290 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6668 00:38:46.337880 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6669 00:38:46.338426 ==
6670 00:38:46.341496 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 00:38:46.347944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6672 00:38:46.348513 ==
6673 00:38:46.348995 DQS Delay:
6674 00:38:46.351037 DQS0 = 35, DQS1 = 59
6675 00:38:46.351505 DQM Delay:
6676 00:38:46.351980 DQM0 = 3, DQM1 = 17
6677 00:38:46.354177 DQ Delay:
6678 00:38:46.357802 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6679 00:38:46.358288 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6680 00:38:46.360886 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6681 00:38:46.364091 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6682 00:38:46.364586
6683 00:38:46.367502
6684 00:38:46.367957 ==
6685 00:38:46.370710 Dram Type= 6, Freq= 0, CH_1, rank 1
6686 00:38:46.374289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6687 00:38:46.374747 ==
6688 00:38:46.375107
6689 00:38:46.375440
6690 00:38:46.377616 TX Vref Scan disable
6691 00:38:46.378072 == TX Byte 0 ==
6692 00:38:46.381056 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6693 00:38:46.387495 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6694 00:38:46.387908 == TX Byte 1 ==
6695 00:38:46.390992 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6696 00:38:46.397410 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6697 00:38:46.397894 ==
6698 00:38:46.400966 Dram Type= 6, Freq= 0, CH_1, rank 1
6699 00:38:46.404473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6700 00:38:46.404894 ==
6701 00:38:46.405223
6702 00:38:46.405579
6703 00:38:46.407284 TX Vref Scan disable
6704 00:38:46.407701 == TX Byte 0 ==
6705 00:38:46.410713 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6706 00:38:46.417731 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6707 00:38:46.418310 == TX Byte 1 ==
6708 00:38:46.421009 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6709 00:38:46.427514 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6710 00:38:46.428060
6711 00:38:46.428421 [DATLAT]
6712 00:38:46.428754 Freq=400, CH1 RK1
6713 00:38:46.429083
6714 00:38:46.430556 DATLAT Default: 0xd
6715 00:38:46.434064 0, 0xFFFF, sum = 0
6716 00:38:46.434617 1, 0xFFFF, sum = 0
6717 00:38:46.437386 2, 0xFFFF, sum = 0
6718 00:38:46.437852 3, 0xFFFF, sum = 0
6719 00:38:46.440680 4, 0xFFFF, sum = 0
6720 00:38:46.441206 5, 0xFFFF, sum = 0
6721 00:38:46.443910 6, 0xFFFF, sum = 0
6722 00:38:46.444549 7, 0xFFFF, sum = 0
6723 00:38:46.447361 8, 0xFFFF, sum = 0
6724 00:38:46.447929 9, 0xFFFF, sum = 0
6725 00:38:46.450500 10, 0xFFFF, sum = 0
6726 00:38:46.450966 11, 0xFFFF, sum = 0
6727 00:38:46.454198 12, 0x0, sum = 1
6728 00:38:46.454667 13, 0x0, sum = 2
6729 00:38:46.457385 14, 0x0, sum = 3
6730 00:38:46.457856 15, 0x0, sum = 4
6731 00:38:46.460604 best_step = 13
6732 00:38:46.461096
6733 00:38:46.461519 ==
6734 00:38:46.464059 Dram Type= 6, Freq= 0, CH_1, rank 1
6735 00:38:46.467280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6736 00:38:46.467853 ==
6737 00:38:46.468318 RX Vref Scan: 0
6738 00:38:46.468669
6739 00:38:46.470485 RX Vref 0 -> 0, step: 1
6740 00:38:46.470984
6741 00:38:46.473688 RX Delay -359 -> 252, step: 8
6742 00:38:46.481370 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6743 00:38:46.484458 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6744 00:38:46.488104 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6745 00:38:46.491222 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6746 00:38:46.497825 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6747 00:38:46.501333 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6748 00:38:46.504197 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6749 00:38:46.507706 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6750 00:38:46.514330 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6751 00:38:46.517831 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6752 00:38:46.521112 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6753 00:38:46.524431 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6754 00:38:46.531143 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6755 00:38:46.534366 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6756 00:38:46.538128 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6757 00:38:46.544566 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6758 00:38:46.545200 ==
6759 00:38:46.547720 Dram Type= 6, Freq= 0, CH_1, rank 1
6760 00:38:46.551024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6761 00:38:46.551675 ==
6762 00:38:46.552052 DQS Delay:
6763 00:38:46.554194 DQS0 = 48, DQS1 = 64
6764 00:38:46.554869 DQM Delay:
6765 00:38:46.557715 DQM0 = 9, DQM1 = 15
6766 00:38:46.558255 DQ Delay:
6767 00:38:46.561120 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6768 00:38:46.564461 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6769 00:38:46.567578 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6770 00:38:46.571075 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6771 00:38:46.571693
6772 00:38:46.572078
6773 00:38:46.577237 [DQSOSCAuto] RK1, (LSB)MR18= 0xbcbc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6774 00:38:46.581177 CH1 RK1: MR19=C0C, MR18=BCBC
6775 00:38:46.587288 CH1_RK1: MR19=0xC0C, MR18=0xBCBC, DQSOSC=386, MR23=63, INC=396, DEC=264
6776 00:38:46.591156 [RxdqsGatingPostProcess] freq 400
6777 00:38:46.597798 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6778 00:38:46.598265 Pre-setting of DQS Precalculation
6779 00:38:46.603908 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6780 00:38:46.610672 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6781 00:38:46.617152 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6782 00:38:46.617693
6783 00:38:46.618088
6784 00:38:46.620312 [Calibration Summary] 800 Mbps
6785 00:38:46.624163 CH 0, Rank 0
6786 00:38:46.624744 SW Impedance : PASS
6787 00:38:46.627384 DUTY Scan : NO K
6788 00:38:46.630489 ZQ Calibration : PASS
6789 00:38:46.630973 Jitter Meter : NO K
6790 00:38:46.633957 CBT Training : PASS
6791 00:38:46.634420 Write leveling : PASS
6792 00:38:46.637394 RX DQS gating : PASS
6793 00:38:46.640533 RX DQ/DQS(RDDQC) : PASS
6794 00:38:46.640989 TX DQ/DQS : PASS
6795 00:38:46.644326 RX DATLAT : PASS
6796 00:38:46.647385 RX DQ/DQS(Engine): PASS
6797 00:38:46.647947 TX OE : NO K
6798 00:38:46.650725 All Pass.
6799 00:38:46.651279
6800 00:38:46.651639 CH 0, Rank 1
6801 00:38:46.653587 SW Impedance : PASS
6802 00:38:46.654043 DUTY Scan : NO K
6803 00:38:46.656926 ZQ Calibration : PASS
6804 00:38:46.660176 Jitter Meter : NO K
6805 00:38:46.660627 CBT Training : PASS
6806 00:38:46.664079 Write leveling : NO K
6807 00:38:46.667452 RX DQS gating : PASS
6808 00:38:46.668000 RX DQ/DQS(RDDQC) : PASS
6809 00:38:46.670177 TX DQ/DQS : PASS
6810 00:38:46.673566 RX DATLAT : PASS
6811 00:38:46.674107 RX DQ/DQS(Engine): PASS
6812 00:38:46.677309 TX OE : NO K
6813 00:38:46.677778 All Pass.
6814 00:38:46.678135
6815 00:38:46.680170 CH 1, Rank 0
6816 00:38:46.680618 SW Impedance : PASS
6817 00:38:46.683379 DUTY Scan : NO K
6818 00:38:46.687029 ZQ Calibration : PASS
6819 00:38:46.687586 Jitter Meter : NO K
6820 00:38:46.690283 CBT Training : PASS
6821 00:38:46.690736 Write leveling : PASS
6822 00:38:46.693686 RX DQS gating : PASS
6823 00:38:46.696809 RX DQ/DQS(RDDQC) : PASS
6824 00:38:46.697343 TX DQ/DQS : PASS
6825 00:38:46.700221 RX DATLAT : PASS
6826 00:38:46.703694 RX DQ/DQS(Engine): PASS
6827 00:38:46.704256 TX OE : NO K
6828 00:38:46.706678 All Pass.
6829 00:38:46.707169
6830 00:38:46.707541 CH 1, Rank 1
6831 00:38:46.709980 SW Impedance : PASS
6832 00:38:46.710432 DUTY Scan : NO K
6833 00:38:46.713738 ZQ Calibration : PASS
6834 00:38:46.716574 Jitter Meter : NO K
6835 00:38:46.717026 CBT Training : PASS
6836 00:38:46.719795 Write leveling : NO K
6837 00:38:46.723684 RX DQS gating : PASS
6838 00:38:46.724232 RX DQ/DQS(RDDQC) : PASS
6839 00:38:46.726591 TX DQ/DQS : PASS
6840 00:38:46.729846 RX DATLAT : PASS
6841 00:38:46.730344 RX DQ/DQS(Engine): PASS
6842 00:38:46.733065 TX OE : NO K
6843 00:38:46.733550 All Pass.
6844 00:38:46.733908
6845 00:38:46.736329 DramC Write-DBI off
6846 00:38:46.739591 PER_BANK_REFRESH: Hybrid Mode
6847 00:38:46.740141 TX_TRACKING: ON
6848 00:38:46.749457 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6849 00:38:46.752755 [FAST_K] Save calibration result to emmc
6850 00:38:46.756079 dramc_set_vcore_voltage set vcore to 725000
6851 00:38:46.759852 Read voltage for 1600, 0
6852 00:38:46.760523 Vio18 = 0
6853 00:38:46.761005 Vcore = 725000
6854 00:38:46.762617 Vdram = 0
6855 00:38:46.763178 Vddq = 0
6856 00:38:46.763700 Vmddr = 0
6857 00:38:46.769357 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6858 00:38:46.772738 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6859 00:38:46.776611 MEM_TYPE=3, freq_sel=13
6860 00:38:46.779652 sv_algorithm_assistance_LP4_3733
6861 00:38:46.782550 ============ PULL DRAM RESETB DOWN ============
6862 00:38:46.786223 ========== PULL DRAM RESETB DOWN end =========
6863 00:38:46.793243 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6864 00:38:46.795959 ===================================
6865 00:38:46.798887 LPDDR4 DRAM CONFIGURATION
6866 00:38:46.802700 ===================================
6867 00:38:46.803228 EX_ROW_EN[0] = 0x0
6868 00:38:46.805920 EX_ROW_EN[1] = 0x0
6869 00:38:46.806383 LP4Y_EN = 0x0
6870 00:38:46.809122 WORK_FSP = 0x1
6871 00:38:46.809602 WL = 0x5
6872 00:38:46.812418 RL = 0x5
6873 00:38:46.812969 BL = 0x2
6874 00:38:46.815866 RPST = 0x0
6875 00:38:46.816331 RD_PRE = 0x0
6876 00:38:46.819084 WR_PRE = 0x1
6877 00:38:46.819546 WR_PST = 0x1
6878 00:38:46.822554 DBI_WR = 0x0
6879 00:38:46.825928 DBI_RD = 0x0
6880 00:38:46.826460 OTF = 0x1
6881 00:38:46.828838 ===================================
6882 00:38:46.832514 ===================================
6883 00:38:46.832976 ANA top config
6884 00:38:46.835685 ===================================
6885 00:38:46.838976 DLL_ASYNC_EN = 0
6886 00:38:46.842436 ALL_SLAVE_EN = 0
6887 00:38:46.845625 NEW_RANK_MODE = 1
6888 00:38:46.848892 DLL_IDLE_MODE = 1
6889 00:38:46.849394 LP45_APHY_COMB_EN = 1
6890 00:38:46.852109 TX_ODT_DIS = 0
6891 00:38:46.855402 NEW_8X_MODE = 1
6892 00:38:46.858739 ===================================
6893 00:38:46.861875 ===================================
6894 00:38:46.865117 data_rate = 3200
6895 00:38:46.868523 CKR = 1
6896 00:38:46.868981 DQ_P2S_RATIO = 8
6897 00:38:46.871871 ===================================
6898 00:38:46.875043 CA_P2S_RATIO = 8
6899 00:38:46.878344 DQ_CA_OPEN = 0
6900 00:38:46.881991 DQ_SEMI_OPEN = 0
6901 00:38:46.885236 CA_SEMI_OPEN = 0
6902 00:38:46.888240 CA_FULL_RATE = 0
6903 00:38:46.888785 DQ_CKDIV4_EN = 0
6904 00:38:46.891974 CA_CKDIV4_EN = 0
6905 00:38:46.895020 CA_PREDIV_EN = 0
6906 00:38:46.898214 PH8_DLY = 12
6907 00:38:46.901700 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6908 00:38:46.905215 DQ_AAMCK_DIV = 4
6909 00:38:46.905769 CA_AAMCK_DIV = 4
6910 00:38:46.908333 CA_ADMCK_DIV = 4
6911 00:38:46.911683 DQ_TRACK_CA_EN = 0
6912 00:38:46.914914 CA_PICK = 1600
6913 00:38:46.918312 CA_MCKIO = 1600
6914 00:38:46.922066 MCKIO_SEMI = 0
6915 00:38:46.924824 PLL_FREQ = 3068
6916 00:38:46.928128 DQ_UI_PI_RATIO = 32
6917 00:38:46.928554 CA_UI_PI_RATIO = 0
6918 00:38:46.931809 ===================================
6919 00:38:46.934511 ===================================
6920 00:38:46.938187 memory_type:LPDDR4
6921 00:38:46.941324 GP_NUM : 10
6922 00:38:46.941844 SRAM_EN : 1
6923 00:38:46.944554 MD32_EN : 0
6924 00:38:46.948138 ===================================
6925 00:38:46.951196 [ANA_INIT] >>>>>>>>>>>>>>
6926 00:38:46.954578 <<<<<< [CONFIGURE PHASE]: ANA_TX
6927 00:38:46.957550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6928 00:38:46.961369 ===================================
6929 00:38:46.961793 data_rate = 3200,PCW = 0X7600
6930 00:38:46.964632 ===================================
6931 00:38:46.967626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6932 00:38:46.974499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6933 00:38:46.980699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6934 00:38:46.983944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6935 00:38:46.987274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6936 00:38:46.990596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6937 00:38:46.993942 [ANA_INIT] flow start
6938 00:38:46.997166 [ANA_INIT] PLL >>>>>>>>
6939 00:38:46.997747 [ANA_INIT] PLL <<<<<<<<
6940 00:38:47.000510 [ANA_INIT] MIDPI >>>>>>>>
6941 00:38:47.003980 [ANA_INIT] MIDPI <<<<<<<<
6942 00:38:47.004490 [ANA_INIT] DLL >>>>>>>>
6943 00:38:47.007477 [ANA_INIT] DLL <<<<<<<<
6944 00:38:47.010498 [ANA_INIT] flow end
6945 00:38:47.014175 ============ LP4 DIFF to SE enter ============
6946 00:38:47.016997 ============ LP4 DIFF to SE exit ============
6947 00:38:47.020449 [ANA_INIT] <<<<<<<<<<<<<
6948 00:38:47.023947 [Flow] Enable top DCM control >>>>>
6949 00:38:47.027458 [Flow] Enable top DCM control <<<<<
6950 00:38:47.030631 Enable DLL master slave shuffle
6951 00:38:47.033867 ==============================================================
6952 00:38:47.037150 Gating Mode config
6953 00:38:47.043395 ==============================================================
6954 00:38:47.043875 Config description:
6955 00:38:47.053403 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6956 00:38:47.060196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6957 00:38:47.067271 SELPH_MODE 0: By rank 1: By Phase
6958 00:38:47.070143 ==============================================================
6959 00:38:47.073179 GAT_TRACK_EN = 1
6960 00:38:47.076781 RX_GATING_MODE = 2
6961 00:38:47.080326 RX_GATING_TRACK_MODE = 2
6962 00:38:47.083218 SELPH_MODE = 1
6963 00:38:47.086324 PICG_EARLY_EN = 1
6964 00:38:47.089882 VALID_LAT_VALUE = 1
6965 00:38:47.093233 ==============================================================
6966 00:38:47.096264 Enter into Gating configuration >>>>
6967 00:38:47.099951 Exit from Gating configuration <<<<
6968 00:38:47.103019 Enter into DVFS_PRE_config >>>>>
6969 00:38:47.116157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6970 00:38:47.119294 Exit from DVFS_PRE_config <<<<<
6971 00:38:47.122726 Enter into PICG configuration >>>>
6972 00:38:47.126069 Exit from PICG configuration <<<<
6973 00:38:47.126489 [RX_INPUT] configuration >>>>>
6974 00:38:47.129924 [RX_INPUT] configuration <<<<<
6975 00:38:47.136157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6976 00:38:47.139659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6977 00:38:47.146288 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6978 00:38:47.152615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6979 00:38:47.160022 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6980 00:38:47.165579 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6981 00:38:47.169249 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6982 00:38:47.172468 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6983 00:38:47.179112 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6984 00:38:47.182179 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6985 00:38:47.185588 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6986 00:38:47.192425 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6987 00:38:47.195582 ===================================
6988 00:38:47.196106 LPDDR4 DRAM CONFIGURATION
6989 00:38:47.198658 ===================================
6990 00:38:47.202390 EX_ROW_EN[0] = 0x0
6991 00:38:47.202882 EX_ROW_EN[1] = 0x0
6992 00:38:47.206136 LP4Y_EN = 0x0
6993 00:38:47.206614 WORK_FSP = 0x1
6994 00:38:47.208625 WL = 0x5
6995 00:38:47.209103 RL = 0x5
6996 00:38:47.212119 BL = 0x2
6997 00:38:47.215415 RPST = 0x0
6998 00:38:47.215890 RD_PRE = 0x0
6999 00:38:47.218395 WR_PRE = 0x1
7000 00:38:47.218873 WR_PST = 0x1
7001 00:38:47.222182 DBI_WR = 0x0
7002 00:38:47.222749 DBI_RD = 0x0
7003 00:38:47.225346 OTF = 0x1
7004 00:38:47.228829 ===================================
7005 00:38:47.232136 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7006 00:38:47.235038 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7007 00:38:47.238427 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7008 00:38:47.241785 ===================================
7009 00:38:47.244993 LPDDR4 DRAM CONFIGURATION
7010 00:38:47.248252 ===================================
7011 00:38:47.251767 EX_ROW_EN[0] = 0x10
7012 00:38:47.252386 EX_ROW_EN[1] = 0x0
7013 00:38:47.255067 LP4Y_EN = 0x0
7014 00:38:47.255617 WORK_FSP = 0x1
7015 00:38:47.258391 WL = 0x5
7016 00:38:47.258851 RL = 0x5
7017 00:38:47.261744 BL = 0x2
7018 00:38:47.262200 RPST = 0x0
7019 00:38:47.265204 RD_PRE = 0x0
7020 00:38:47.265705 WR_PRE = 0x1
7021 00:38:47.268649 WR_PST = 0x1
7022 00:38:47.271841 DBI_WR = 0x0
7023 00:38:47.272429 DBI_RD = 0x0
7024 00:38:47.275402 OTF = 0x1
7025 00:38:47.278486 ===================================
7026 00:38:47.281577 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7027 00:38:47.285343 ==
7028 00:38:47.288200 Dram Type= 6, Freq= 0, CH_0, rank 0
7029 00:38:47.291345 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7030 00:38:47.291805 ==
7031 00:38:47.294691 [Duty_Offset_Calibration]
7032 00:38:47.295145 B0:0 B1:2 CA:1
7033 00:38:47.295535
7034 00:38:47.298027 [DutyScan_Calibration_Flow] k_type=0
7035 00:38:47.308152
7036 00:38:47.308704 ==CLK 0==
7037 00:38:47.311356 Final CLK duty delay cell = 0
7038 00:38:47.315039 [0] MAX Duty = 5187%(X100), DQS PI = 24
7039 00:38:47.317788 [0] MIN Duty = 4938%(X100), DQS PI = 54
7040 00:38:47.321439 [0] AVG Duty = 5062%(X100)
7041 00:38:47.321901
7042 00:38:47.324483 CH0 CLK Duty spec in!! Max-Min= 249%
7043 00:38:47.327906 [DutyScan_Calibration_Flow] ====Done====
7044 00:38:47.328468
7045 00:38:47.331627 [DutyScan_Calibration_Flow] k_type=1
7046 00:38:47.348123
7047 00:38:47.348683 ==DQS 0 ==
7048 00:38:47.351644 Final DQS duty delay cell = 0
7049 00:38:47.354703 [0] MAX Duty = 5156%(X100), DQS PI = 36
7050 00:38:47.357800 [0] MIN Duty = 5031%(X100), DQS PI = 8
7051 00:38:47.361168 [0] AVG Duty = 5093%(X100)
7052 00:38:47.361667
7053 00:38:47.362032 ==DQS 1 ==
7054 00:38:47.364422 Final DQS duty delay cell = 0
7055 00:38:47.367713 [0] MAX Duty = 5031%(X100), DQS PI = 6
7056 00:38:47.370988 [0] MIN Duty = 4876%(X100), DQS PI = 18
7057 00:38:47.374432 [0] AVG Duty = 4953%(X100)
7058 00:38:47.374896
7059 00:38:47.377854 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7060 00:38:47.378318
7061 00:38:47.380938 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7062 00:38:47.384205 [DutyScan_Calibration_Flow] ====Done====
7063 00:38:47.384665
7064 00:38:47.387389 [DutyScan_Calibration_Flow] k_type=3
7065 00:38:47.404724
7066 00:38:47.404942 ==DQM 0 ==
7067 00:38:47.407857 Final DQM duty delay cell = 0
7068 00:38:47.411753 [0] MAX Duty = 5187%(X100), DQS PI = 22
7069 00:38:47.415009 [0] MIN Duty = 4907%(X100), DQS PI = 44
7070 00:38:47.417903 [0] AVG Duty = 5047%(X100)
7071 00:38:47.418022
7072 00:38:47.418115 ==DQM 1 ==
7073 00:38:47.421079 Final DQM duty delay cell = 0
7074 00:38:47.424608 [0] MAX Duty = 5031%(X100), DQS PI = 52
7075 00:38:47.427996 [0] MIN Duty = 4782%(X100), DQS PI = 14
7076 00:38:47.431162 [0] AVG Duty = 4906%(X100)
7077 00:38:47.431279
7078 00:38:47.434569 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7079 00:38:47.434766
7080 00:38:47.437759 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7081 00:38:47.441124 [DutyScan_Calibration_Flow] ====Done====
7082 00:38:47.441241
7083 00:38:47.444529 [DutyScan_Calibration_Flow] k_type=2
7084 00:38:47.461281
7085 00:38:47.461491 ==DQ 0 ==
7086 00:38:47.464959 Final DQ duty delay cell = 0
7087 00:38:47.468044 [0] MAX Duty = 5218%(X100), DQS PI = 18
7088 00:38:47.471454 [0] MIN Duty = 4938%(X100), DQS PI = 56
7089 00:38:47.471667 [0] AVG Duty = 5078%(X100)
7090 00:38:47.474526
7091 00:38:47.474697 ==DQ 1 ==
7092 00:38:47.477960 Final DQ duty delay cell = -4
7093 00:38:47.481220 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7094 00:38:47.484592 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7095 00:38:47.487862 [-4] AVG Duty = 4953%(X100)
7096 00:38:47.488141
7097 00:38:47.491454 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7098 00:38:47.491771
7099 00:38:47.494576 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7100 00:38:47.497802 [DutyScan_Calibration_Flow] ====Done====
7101 00:38:47.498220 ==
7102 00:38:47.500941 Dram Type= 6, Freq= 0, CH_1, rank 0
7103 00:38:47.504625 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7104 00:38:47.504979 ==
7105 00:38:47.508178 [Duty_Offset_Calibration]
7106 00:38:47.508781 B0:0 B1:4 CA:-5
7107 00:38:47.509387
7108 00:38:47.511847 [DutyScan_Calibration_Flow] k_type=0
7109 00:38:47.522366
7110 00:38:47.522915 ==CLK 0==
7111 00:38:47.525889 Final CLK duty delay cell = 0
7112 00:38:47.528632 [0] MAX Duty = 5156%(X100), DQS PI = 22
7113 00:38:47.532384 [0] MIN Duty = 4906%(X100), DQS PI = 50
7114 00:38:47.535745 [0] AVG Duty = 5031%(X100)
7115 00:38:47.536296
7116 00:38:47.539203 CH1 CLK Duty spec in!! Max-Min= 250%
7117 00:38:47.541853 [DutyScan_Calibration_Flow] ====Done====
7118 00:38:47.542308
7119 00:38:47.545022 [DutyScan_Calibration_Flow] k_type=1
7120 00:38:47.561238
7121 00:38:47.561822 ==DQS 0 ==
7122 00:38:47.564282 Final DQS duty delay cell = 0
7123 00:38:47.568063 [0] MAX Duty = 5187%(X100), DQS PI = 20
7124 00:38:47.571160 [0] MIN Duty = 4876%(X100), DQS PI = 42
7125 00:38:47.574722 [0] AVG Duty = 5031%(X100)
7126 00:38:47.575273
7127 00:38:47.575637 ==DQS 1 ==
7128 00:38:47.577687 Final DQS duty delay cell = -4
7129 00:38:47.581673 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7130 00:38:47.584595 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7131 00:38:47.587378 [-4] AVG Duty = 4922%(X100)
7132 00:38:47.587837
7133 00:38:47.591442 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7134 00:38:47.591999
7135 00:38:47.594297 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7136 00:38:47.597866 [DutyScan_Calibration_Flow] ====Done====
7137 00:38:47.598369
7138 00:38:47.600520 [DutyScan_Calibration_Flow] k_type=3
7139 00:38:47.616770
7140 00:38:47.617361 ==DQM 0 ==
7141 00:38:47.620161 Final DQM duty delay cell = -4
7142 00:38:47.623523 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7143 00:38:47.626962 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7144 00:38:47.630245 [-4] AVG Duty = 4953%(X100)
7145 00:38:47.630794
7146 00:38:47.631151 ==DQM 1 ==
7147 00:38:47.633437 Final DQM duty delay cell = -4
7148 00:38:47.637181 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7149 00:38:47.639976 [-4] MIN Duty = 4875%(X100), DQS PI = 40
7150 00:38:47.642964 [-4] AVG Duty = 4984%(X100)
7151 00:38:47.643414
7152 00:38:47.646450 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7153 00:38:47.646904
7154 00:38:47.649658 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7155 00:38:47.652934 [DutyScan_Calibration_Flow] ====Done====
7156 00:38:47.653509
7157 00:38:47.656727 [DutyScan_Calibration_Flow] k_type=2
7158 00:38:47.674593
7159 00:38:47.675138 ==DQ 0 ==
7160 00:38:47.677447 Final DQ duty delay cell = 0
7161 00:38:47.680955 [0] MAX Duty = 5093%(X100), DQS PI = 34
7162 00:38:47.684611 [0] MIN Duty = 4969%(X100), DQS PI = 46
7163 00:38:47.687666 [0] AVG Duty = 5031%(X100)
7164 00:38:47.688215
7165 00:38:47.688576 ==DQ 1 ==
7166 00:38:47.690825 Final DQ duty delay cell = 0
7167 00:38:47.694269 [0] MAX Duty = 5031%(X100), DQS PI = 4
7168 00:38:47.697440 [0] MIN Duty = 4876%(X100), DQS PI = 28
7169 00:38:47.697997 [0] AVG Duty = 4953%(X100)
7170 00:38:47.700894
7171 00:38:47.703866 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7172 00:38:47.704375
7173 00:38:47.707832 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7174 00:38:47.710603 [DutyScan_Calibration_Flow] ====Done====
7175 00:38:47.713715 nWR fixed to 30
7176 00:38:47.717536 [ModeRegInit_LP4] CH0 RK0
7177 00:38:47.718097 [ModeRegInit_LP4] CH0 RK1
7178 00:38:47.720634 [ModeRegInit_LP4] CH1 RK0
7179 00:38:47.724106 [ModeRegInit_LP4] CH1 RK1
7180 00:38:47.724659 match AC timing 4
7181 00:38:47.730497 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7182 00:38:47.733886 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7183 00:38:47.737271 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7184 00:38:47.743711 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7185 00:38:47.746843 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7186 00:38:47.747393 [MiockJmeterHQA]
7187 00:38:47.747801
7188 00:38:47.749916 [DramcMiockJmeter] u1RxGatingPI = 0
7189 00:38:47.753801 0 : 4257, 4030
7190 00:38:47.754372 4 : 4363, 4138
7191 00:38:47.756847 8 : 4252, 4027
7192 00:38:47.757345 12 : 4363, 4138
7193 00:38:47.759949 16 : 4363, 4137
7194 00:38:47.760628 20 : 4252, 4027
7195 00:38:47.761017 24 : 4252, 4027
7196 00:38:47.763418 28 : 4252, 4027
7197 00:38:47.763974 32 : 4365, 4140
7198 00:38:47.766757 36 : 4252, 4026
7199 00:38:47.767220 40 : 4363, 4138
7200 00:38:47.769910 44 : 4250, 4027
7201 00:38:47.770373 48 : 4252, 4027
7202 00:38:47.772968 52 : 4250, 4027
7203 00:38:47.773475 56 : 4252, 4026
7204 00:38:47.773849 60 : 4360, 4138
7205 00:38:47.776591 64 : 4250, 4027
7206 00:38:47.777144 68 : 4361, 4137
7207 00:38:47.779909 72 : 4250, 4026
7208 00:38:47.780459 76 : 4250, 4026
7209 00:38:47.783151 80 : 4250, 4027
7210 00:38:47.783825 84 : 4361, 4137
7211 00:38:47.786563 88 : 4250, 4026
7212 00:38:47.787211 92 : 4360, 4138
7213 00:38:47.787768 96 : 4250, 4027
7214 00:38:47.789850 100 : 4250, 1832
7215 00:38:47.790314 104 : 4360, 0
7216 00:38:47.793177 108 : 4360, 0
7217 00:38:47.793775 112 : 4252, 0
7218 00:38:47.794148 116 : 4250, 0
7219 00:38:47.796378 120 : 4250, 0
7220 00:38:47.796935 124 : 4250, 0
7221 00:38:47.799426 128 : 4250, 0
7222 00:38:47.799896 132 : 4250, 0
7223 00:38:47.800266 136 : 4252, 0
7224 00:38:47.802943 140 : 4250, 0
7225 00:38:47.803410 144 : 4360, 0
7226 00:38:47.806620 148 : 4250, 0
7227 00:38:47.807177 152 : 4250, 0
7228 00:38:47.807548 156 : 4360, 0
7229 00:38:47.809701 160 : 4361, 0
7230 00:38:47.810347 164 : 4252, 0
7231 00:38:47.812921 168 : 4250, 0
7232 00:38:47.813534 172 : 4250, 0
7233 00:38:47.814071 176 : 4250, 0
7234 00:38:47.816098 180 : 4250, 0
7235 00:38:47.816581 184 : 4250, 0
7236 00:38:47.816998 188 : 4252, 0
7237 00:38:47.819547 192 : 4361, 0
7238 00:38:47.820014 196 : 4360, 0
7239 00:38:47.822725 200 : 4247, 0
7240 00:38:47.823194 204 : 4361, 0
7241 00:38:47.823562 208 : 4360, 0
7242 00:38:47.826244 212 : 4361, 0
7243 00:38:47.826798 216 : 4250, 0
7244 00:38:47.830002 220 : 4250, 865
7245 00:38:47.830561 224 : 4254, 4028
7246 00:38:47.832799 228 : 4360, 4137
7247 00:38:47.833261 232 : 4360, 4137
7248 00:38:47.833674 236 : 4250, 4027
7249 00:38:47.836405 240 : 4250, 4026
7250 00:38:47.836964 244 : 4250, 4027
7251 00:38:47.839591 248 : 4250, 4027
7252 00:38:47.840147 252 : 4250, 4027
7253 00:38:47.843158 256 : 4250, 4027
7254 00:38:47.843712 260 : 4250, 4026
7255 00:38:47.846163 264 : 4250, 4027
7256 00:38:47.846725 268 : 4363, 4140
7257 00:38:47.850062 272 : 4361, 4137
7258 00:38:47.850623 276 : 4250, 4026
7259 00:38:47.852883 280 : 4361, 4137
7260 00:38:47.853393 284 : 4360, 4138
7261 00:38:47.856117 288 : 4250, 4026
7262 00:38:47.856672 292 : 4250, 4027
7263 00:38:47.859814 296 : 4250, 4026
7264 00:38:47.860281 300 : 4250, 4027
7265 00:38:47.860660 304 : 4250, 4026
7266 00:38:47.862550 308 : 4250, 4027
7267 00:38:47.863016 312 : 4250, 4026
7268 00:38:47.865814 316 : 4250, 4027
7269 00:38:47.866318 320 : 4360, 4138
7270 00:38:47.869169 324 : 4361, 4137
7271 00:38:47.869727 328 : 4248, 4025
7272 00:38:47.872519 332 : 4361, 4138
7273 00:38:47.872987 336 : 4360, 3789
7274 00:38:47.875825 340 : 4250, 1688
7275 00:38:47.876379
7276 00:38:47.876741 MIOCK jitter meter ch=0
7277 00:38:47.877081
7278 00:38:47.879763 1T = (340-100) = 240 dly cells
7279 00:38:47.885989 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7280 00:38:47.886543 ==
7281 00:38:47.888962 Dram Type= 6, Freq= 0, CH_0, rank 0
7282 00:38:47.892483 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7283 00:38:47.893037 ==
7284 00:38:47.899119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7285 00:38:47.902502 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7286 00:38:47.909412 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7287 00:38:47.912593 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7288 00:38:47.921335 [CA 0] Center 41 (11~72) winsize 62
7289 00:38:47.925073 [CA 1] Center 41 (11~72) winsize 62
7290 00:38:47.928222 [CA 2] Center 37 (7~67) winsize 61
7291 00:38:47.931433 [CA 3] Center 37 (7~67) winsize 61
7292 00:38:47.935406 [CA 4] Center 35 (5~66) winsize 62
7293 00:38:47.938444 [CA 5] Center 35 (5~65) winsize 61
7294 00:38:47.938995
7295 00:38:47.941265 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7296 00:38:47.941773
7297 00:38:47.945153 [CATrainingPosCal] consider 1 rank data
7298 00:38:47.948745 u2DelayCellTimex100 = 271/100 ps
7299 00:38:47.951675 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7300 00:38:47.958162 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7301 00:38:47.961328 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7302 00:38:47.964669 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7303 00:38:47.968381 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7304 00:38:47.971485 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7305 00:38:47.972033
7306 00:38:47.975073 CA PerBit enable=1, Macro0, CA PI delay=35
7307 00:38:47.975618
7308 00:38:47.978090 [CBTSetCACLKResult] CA Dly = 35
7309 00:38:47.981205 CS Dly: 11 (0~42)
7310 00:38:47.984776 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7311 00:38:47.987934 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7312 00:38:47.988492 ==
7313 00:38:47.991465 Dram Type= 6, Freq= 0, CH_0, rank 1
7314 00:38:47.994454 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7315 00:38:47.997687 ==
7316 00:38:48.001114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7317 00:38:48.004340 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7318 00:38:48.011411 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7319 00:38:48.017801 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7320 00:38:48.024792 [CA 0] Center 42 (12~73) winsize 62
7321 00:38:48.027600 [CA 1] Center 42 (12~73) winsize 62
7322 00:38:48.031090 [CA 2] Center 38 (9~68) winsize 60
7323 00:38:48.034169 [CA 3] Center 38 (8~68) winsize 61
7324 00:38:48.037460 [CA 4] Center 36 (6~66) winsize 61
7325 00:38:48.040992 [CA 5] Center 36 (6~66) winsize 61
7326 00:38:48.041616
7327 00:38:48.044204 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7328 00:38:48.044748
7329 00:38:48.047409 [CATrainingPosCal] consider 2 rank data
7330 00:38:48.050470 u2DelayCellTimex100 = 271/100 ps
7331 00:38:48.053698 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7332 00:38:48.060364 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7333 00:38:48.063794 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7334 00:38:48.067363 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7335 00:38:48.070843 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7336 00:38:48.073867 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7337 00:38:48.074412
7338 00:38:48.077596 CA PerBit enable=1, Macro0, CA PI delay=35
7339 00:38:48.078143
7340 00:38:48.081211 [CBTSetCACLKResult] CA Dly = 35
7341 00:38:48.083745 CS Dly: 11 (0~42)
7342 00:38:48.087310 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7343 00:38:48.090328 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7344 00:38:48.090786
7345 00:38:48.093876 ----->DramcWriteLeveling(PI) begin...
7346 00:38:48.094429 ==
7347 00:38:48.096907 Dram Type= 6, Freq= 0, CH_0, rank 0
7348 00:38:48.103658 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7349 00:38:48.104234 ==
7350 00:38:48.107002 Write leveling (Byte 0): 30 => 30
7351 00:38:48.110142 Write leveling (Byte 1): 25 => 25
7352 00:38:48.110704 DramcWriteLeveling(PI) end<-----
7353 00:38:48.111066
7354 00:38:48.113415 ==
7355 00:38:48.117007 Dram Type= 6, Freq= 0, CH_0, rank 0
7356 00:38:48.119912 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7357 00:38:48.120370 ==
7358 00:38:48.123231 [Gating] SW mode calibration
7359 00:38:48.130049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7360 00:38:48.133044 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7361 00:38:48.139857 0 12 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7362 00:38:48.143215 0 12 4 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
7363 00:38:48.146191 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7364 00:38:48.153257 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7365 00:38:48.156368 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7366 00:38:48.159740 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7367 00:38:48.166186 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7368 00:38:48.169608 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7369 00:38:48.176010 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7370 00:38:48.179117 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7371 00:38:48.182462 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7372 00:38:48.186101 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7373 00:38:48.192751 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7374 00:38:48.195927 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7375 00:38:48.198775 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7376 00:38:48.205989 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7377 00:38:48.208862 0 14 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7378 00:38:48.212204 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7379 00:38:48.218729 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7380 00:38:48.222058 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7381 00:38:48.225449 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7382 00:38:48.232027 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7383 00:38:48.235123 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7384 00:38:48.238294 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7385 00:38:48.245596 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7386 00:38:48.248534 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7387 00:38:48.252043 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7388 00:38:48.258474 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7389 00:38:48.261643 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7390 00:38:48.265275 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7391 00:38:48.271729 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7392 00:38:48.275143 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7393 00:38:48.278209 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7394 00:38:48.285434 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7395 00:38:48.288280 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7396 00:38:48.291611 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7397 00:38:48.298446 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 00:38:48.301406 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 00:38:48.304839 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 00:38:48.311325 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7401 00:38:48.314897 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7402 00:38:48.318142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7403 00:38:48.321376 Total UI for P1: 0, mck2ui 16
7404 00:38:48.324795 best dqsien dly found for B0: ( 1, 0, 30)
7405 00:38:48.331230 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 00:38:48.331714 Total UI for P1: 0, mck2ui 16
7407 00:38:48.337891 best dqsien dly found for B1: ( 1, 1, 4)
7408 00:38:48.341124 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7409 00:38:48.344677 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7410 00:38:48.345228
7411 00:38:48.348261 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7412 00:38:48.351393 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7413 00:38:48.354536 [Gating] SW calibration Done
7414 00:38:48.355081 ==
7415 00:38:48.357868 Dram Type= 6, Freq= 0, CH_0, rank 0
7416 00:38:48.361003 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7417 00:38:48.361509 ==
7418 00:38:48.364155 RX Vref Scan: 0
7419 00:38:48.364619
7420 00:38:48.364984 RX Vref 0 -> 0, step: 1
7421 00:38:48.365370
7422 00:38:48.367623 RX Delay 0 -> 252, step: 8
7423 00:38:48.370810 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7424 00:38:48.377966 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7425 00:38:48.380911 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7426 00:38:48.384465 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7427 00:38:48.387136 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7428 00:38:48.390858 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7429 00:38:48.397216 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7430 00:38:48.400799 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7431 00:38:48.403534 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7432 00:38:48.407224 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7433 00:38:48.410318 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7434 00:38:48.417345 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7435 00:38:48.420240 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7436 00:38:48.423817 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7437 00:38:48.427045 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7438 00:38:48.433703 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7439 00:38:48.434300 ==
7440 00:38:48.437124 Dram Type= 6, Freq= 0, CH_0, rank 0
7441 00:38:48.440352 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7442 00:38:48.440912 ==
7443 00:38:48.441361 DQS Delay:
7444 00:38:48.443334 DQS0 = 0, DQS1 = 0
7445 00:38:48.443788 DQM Delay:
7446 00:38:48.446834 DQM0 = 130, DQM1 = 123
7447 00:38:48.447293 DQ Delay:
7448 00:38:48.450036 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7449 00:38:48.453246 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7450 00:38:48.456582 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7451 00:38:48.459925 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7452 00:38:48.460343
7453 00:38:48.460667
7454 00:38:48.463323 ==
7455 00:38:48.466781 Dram Type= 6, Freq= 0, CH_0, rank 0
7456 00:38:48.470271 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7457 00:38:48.470863 ==
7458 00:38:48.471247
7459 00:38:48.471563
7460 00:38:48.473422 TX Vref Scan disable
7461 00:38:48.473843 == TX Byte 0 ==
7462 00:38:48.476517 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7463 00:38:48.483201 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7464 00:38:48.483615 == TX Byte 1 ==
7465 00:38:48.486639 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7466 00:38:48.492965 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7467 00:38:48.493538 ==
7468 00:38:48.496290 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 00:38:48.499804 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7470 00:38:48.500391 ==
7471 00:38:48.513172
7472 00:38:48.516454 TX Vref early break, caculate TX vref
7473 00:38:48.519821 TX Vref=16, minBit 9, minWin=22, winSum=369
7474 00:38:48.523152 TX Vref=18, minBit 9, minWin=22, winSum=376
7475 00:38:48.526657 TX Vref=20, minBit 8, minWin=23, winSum=386
7476 00:38:48.529664 TX Vref=22, minBit 8, minWin=23, winSum=396
7477 00:38:48.533067 TX Vref=24, minBit 8, minWin=24, winSum=406
7478 00:38:48.539577 TX Vref=26, minBit 8, minWin=24, winSum=411
7479 00:38:48.543621 TX Vref=28, minBit 6, minWin=25, winSum=413
7480 00:38:48.546264 TX Vref=30, minBit 6, minWin=24, winSum=408
7481 00:38:48.550359 TX Vref=32, minBit 1, minWin=24, winSum=400
7482 00:38:48.552748 TX Vref=34, minBit 3, minWin=23, winSum=390
7483 00:38:48.559916 [TxChooseVref] Worse bit 6, Min win 25, Win sum 413, Final Vref 28
7484 00:38:48.560428
7485 00:38:48.562721 Final TX Range 0 Vref 28
7486 00:38:48.563319
7487 00:38:48.563850 ==
7488 00:38:48.566037 Dram Type= 6, Freq= 0, CH_0, rank 0
7489 00:38:48.569404 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7490 00:38:48.569905 ==
7491 00:38:48.570241
7492 00:38:48.570547
7493 00:38:48.572928 TX Vref Scan disable
7494 00:38:48.579614 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7495 00:38:48.580024 == TX Byte 0 ==
7496 00:38:48.582706 u2DelayCellOfst[0]=14 cells (4 PI)
7497 00:38:48.586014 u2DelayCellOfst[1]=18 cells (5 PI)
7498 00:38:48.589501 u2DelayCellOfst[2]=14 cells (4 PI)
7499 00:38:48.592888 u2DelayCellOfst[3]=14 cells (4 PI)
7500 00:38:48.596519 u2DelayCellOfst[4]=10 cells (3 PI)
7501 00:38:48.599226 u2DelayCellOfst[5]=0 cells (0 PI)
7502 00:38:48.602506 u2DelayCellOfst[6]=18 cells (5 PI)
7503 00:38:48.606095 u2DelayCellOfst[7]=18 cells (5 PI)
7504 00:38:48.609552 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7505 00:38:48.612898 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7506 00:38:48.615704 == TX Byte 1 ==
7507 00:38:48.619414 u2DelayCellOfst[8]=3 cells (1 PI)
7508 00:38:48.619867 u2DelayCellOfst[9]=0 cells (0 PI)
7509 00:38:48.622296 u2DelayCellOfst[10]=10 cells (3 PI)
7510 00:38:48.625887 u2DelayCellOfst[11]=3 cells (1 PI)
7511 00:38:48.629537 u2DelayCellOfst[12]=14 cells (4 PI)
7512 00:38:48.632485 u2DelayCellOfst[13]=18 cells (5 PI)
7513 00:38:48.636139 u2DelayCellOfst[14]=18 cells (5 PI)
7514 00:38:48.639387 u2DelayCellOfst[15]=14 cells (4 PI)
7515 00:38:48.642602 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7516 00:38:48.649636 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7517 00:38:48.650202 DramC Write-DBI on
7518 00:38:48.650563 ==
7519 00:38:48.652739 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 00:38:48.658783 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7521 00:38:48.659310 ==
7522 00:38:48.659673
7523 00:38:48.660001
7524 00:38:48.660310 TX Vref Scan disable
7525 00:38:48.663110 == TX Byte 0 ==
7526 00:38:48.665959 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7527 00:38:48.669570 == TX Byte 1 ==
7528 00:38:48.672719 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7529 00:38:48.676224 DramC Write-DBI off
7530 00:38:48.676780
7531 00:38:48.677138 [DATLAT]
7532 00:38:48.677560 Freq=1600, CH0 RK0
7533 00:38:48.677895
7534 00:38:48.679326 DATLAT Default: 0xf
7535 00:38:48.679832 0, 0xFFFF, sum = 0
7536 00:38:48.682920 1, 0xFFFF, sum = 0
7537 00:38:48.685934 2, 0xFFFF, sum = 0
7538 00:38:48.686389 3, 0xFFFF, sum = 0
7539 00:38:48.689180 4, 0xFFFF, sum = 0
7540 00:38:48.689677 5, 0xFFFF, sum = 0
7541 00:38:48.692715 6, 0xFFFF, sum = 0
7542 00:38:48.693171 7, 0xFFFF, sum = 0
7543 00:38:48.696073 8, 0xFFFF, sum = 0
7544 00:38:48.696528 9, 0xFFFF, sum = 0
7545 00:38:48.699404 10, 0xFFFF, sum = 0
7546 00:38:48.699860 11, 0xFFFF, sum = 0
7547 00:38:48.702561 12, 0x8FFF, sum = 0
7548 00:38:48.703019 13, 0x0, sum = 1
7549 00:38:48.705674 14, 0x0, sum = 2
7550 00:38:48.706131 15, 0x0, sum = 3
7551 00:38:48.709175 16, 0x0, sum = 4
7552 00:38:48.709637 best_step = 14
7553 00:38:48.709962
7554 00:38:48.710258 ==
7555 00:38:48.712330 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 00:38:48.715886 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7557 00:38:48.719457 ==
7558 00:38:48.719983 RX Vref Scan: 1
7559 00:38:48.720318
7560 00:38:48.722485 Set Vref Range= 24 -> 127
7561 00:38:48.722892
7562 00:38:48.725929 RX Vref 24 -> 127, step: 1
7563 00:38:48.726339
7564 00:38:48.726659 RX Delay 11 -> 252, step: 4
7565 00:38:48.726988
7566 00:38:48.728938 Set Vref, RX VrefLevel [Byte0]: 24
7567 00:38:48.732724 [Byte1]: 24
7568 00:38:48.736087
7569 00:38:48.736496 Set Vref, RX VrefLevel [Byte0]: 25
7570 00:38:48.739406 [Byte1]: 25
7571 00:38:48.743860
7572 00:38:48.744399 Set Vref, RX VrefLevel [Byte0]: 26
7573 00:38:48.747018 [Byte1]: 26
7574 00:38:48.751371
7575 00:38:48.751874 Set Vref, RX VrefLevel [Byte0]: 27
7576 00:38:48.754518 [Byte1]: 27
7577 00:38:48.759091
7578 00:38:48.759594 Set Vref, RX VrefLevel [Byte0]: 28
7579 00:38:48.762711 [Byte1]: 28
7580 00:38:48.766498
7581 00:38:48.766906 Set Vref, RX VrefLevel [Byte0]: 29
7582 00:38:48.769969 [Byte1]: 29
7583 00:38:48.774043
7584 00:38:48.774448 Set Vref, RX VrefLevel [Byte0]: 30
7585 00:38:48.777736 [Byte1]: 30
7586 00:38:48.781802
7587 00:38:48.782302 Set Vref, RX VrefLevel [Byte0]: 31
7588 00:38:48.785190 [Byte1]: 31
7589 00:38:48.789559
7590 00:38:48.789968 Set Vref, RX VrefLevel [Byte0]: 32
7591 00:38:48.792972 [Byte1]: 32
7592 00:38:48.797144
7593 00:38:48.797729 Set Vref, RX VrefLevel [Byte0]: 33
7594 00:38:48.800167 [Byte1]: 33
7595 00:38:48.804657
7596 00:38:48.805105 Set Vref, RX VrefLevel [Byte0]: 34
7597 00:38:48.808335 [Byte1]: 34
7598 00:38:48.812273
7599 00:38:48.812726 Set Vref, RX VrefLevel [Byte0]: 35
7600 00:38:48.816176 [Byte1]: 35
7601 00:38:48.820029
7602 00:38:48.820576 Set Vref, RX VrefLevel [Byte0]: 36
7603 00:38:48.823154 [Byte1]: 36
7604 00:38:48.827834
7605 00:38:48.828391 Set Vref, RX VrefLevel [Byte0]: 37
7606 00:38:48.830729 [Byte1]: 37
7607 00:38:48.835234
7608 00:38:48.835780 Set Vref, RX VrefLevel [Byte0]: 38
7609 00:38:48.838538 [Byte1]: 38
7610 00:38:48.843195
7611 00:38:48.843740 Set Vref, RX VrefLevel [Byte0]: 39
7612 00:38:48.846158 [Byte1]: 39
7613 00:38:48.850287
7614 00:38:48.850829 Set Vref, RX VrefLevel [Byte0]: 40
7615 00:38:48.853715 [Byte1]: 40
7616 00:38:48.857978
7617 00:38:48.858424 Set Vref, RX VrefLevel [Byte0]: 41
7618 00:38:48.861196 [Byte1]: 41
7619 00:38:48.865848
7620 00:38:48.866527 Set Vref, RX VrefLevel [Byte0]: 42
7621 00:38:48.868761 [Byte1]: 42
7622 00:38:48.873691
7623 00:38:48.874247 Set Vref, RX VrefLevel [Byte0]: 43
7624 00:38:48.876583 [Byte1]: 43
7625 00:38:48.881024
7626 00:38:48.881625 Set Vref, RX VrefLevel [Byte0]: 44
7627 00:38:48.884439 [Byte1]: 44
7628 00:38:48.888666
7629 00:38:48.889220 Set Vref, RX VrefLevel [Byte0]: 45
7630 00:38:48.891648 [Byte1]: 45
7631 00:38:48.896315
7632 00:38:48.896875 Set Vref, RX VrefLevel [Byte0]: 46
7633 00:38:48.899583 [Byte1]: 46
7634 00:38:48.903790
7635 00:38:48.904361 Set Vref, RX VrefLevel [Byte0]: 47
7636 00:38:48.906879 [Byte1]: 47
7637 00:38:48.911476
7638 00:38:48.912067 Set Vref, RX VrefLevel [Byte0]: 48
7639 00:38:48.914802 [Byte1]: 48
7640 00:38:48.918848
7641 00:38:48.919393 Set Vref, RX VrefLevel [Byte0]: 49
7642 00:38:48.922087 [Byte1]: 49
7643 00:38:48.926400
7644 00:38:48.926851 Set Vref, RX VrefLevel [Byte0]: 50
7645 00:38:48.929903 [Byte1]: 50
7646 00:38:48.934306
7647 00:38:48.934867 Set Vref, RX VrefLevel [Byte0]: 51
7648 00:38:48.937284 [Byte1]: 51
7649 00:38:48.941743
7650 00:38:48.942289 Set Vref, RX VrefLevel [Byte0]: 52
7651 00:38:48.945252 [Byte1]: 52
7652 00:38:48.949468
7653 00:38:48.950027 Set Vref, RX VrefLevel [Byte0]: 53
7654 00:38:48.952738 [Byte1]: 53
7655 00:38:48.957213
7656 00:38:48.957814 Set Vref, RX VrefLevel [Byte0]: 54
7657 00:38:48.960328 [Byte1]: 54
7658 00:38:48.964670
7659 00:38:48.965222 Set Vref, RX VrefLevel [Byte0]: 55
7660 00:38:48.967838 [Byte1]: 55
7661 00:38:48.972093
7662 00:38:48.972638 Set Vref, RX VrefLevel [Byte0]: 56
7663 00:38:48.975592 [Byte1]: 56
7664 00:38:48.979979
7665 00:38:48.980524 Set Vref, RX VrefLevel [Byte0]: 57
7666 00:38:48.983377 [Byte1]: 57
7667 00:38:48.987934
7668 00:38:48.988506 Set Vref, RX VrefLevel [Byte0]: 58
7669 00:38:48.990759 [Byte1]: 58
7670 00:38:48.994978
7671 00:38:48.995519 Set Vref, RX VrefLevel [Byte0]: 59
7672 00:38:49.001696 [Byte1]: 59
7673 00:38:49.002237
7674 00:38:49.004997 Set Vref, RX VrefLevel [Byte0]: 60
7675 00:38:49.008204 [Byte1]: 60
7676 00:38:49.008754
7677 00:38:49.011544 Set Vref, RX VrefLevel [Byte0]: 61
7678 00:38:49.014858 [Byte1]: 61
7679 00:38:49.015324
7680 00:38:49.018034 Set Vref, RX VrefLevel [Byte0]: 62
7681 00:38:49.021385 [Byte1]: 62
7682 00:38:49.025813
7683 00:38:49.026360 Set Vref, RX VrefLevel [Byte0]: 63
7684 00:38:49.028885 [Byte1]: 63
7685 00:38:49.033238
7686 00:38:49.033820 Set Vref, RX VrefLevel [Byte0]: 64
7687 00:38:49.036597 [Byte1]: 64
7688 00:38:49.040578
7689 00:38:49.041124 Set Vref, RX VrefLevel [Byte0]: 65
7690 00:38:49.044102 [Byte1]: 65
7691 00:38:49.048497
7692 00:38:49.049043 Set Vref, RX VrefLevel [Byte0]: 66
7693 00:38:49.051766 [Byte1]: 66
7694 00:38:49.055968
7695 00:38:49.056485 Set Vref, RX VrefLevel [Byte0]: 67
7696 00:38:49.059633 [Byte1]: 67
7697 00:38:49.063533
7698 00:38:49.063981 Set Vref, RX VrefLevel [Byte0]: 68
7699 00:38:49.066809 [Byte1]: 68
7700 00:38:49.070967
7701 00:38:49.071432 Set Vref, RX VrefLevel [Byte0]: 69
7702 00:38:49.074292 [Byte1]: 69
7703 00:38:49.078612
7704 00:38:49.079067 Set Vref, RX VrefLevel [Byte0]: 70
7705 00:38:49.081935 [Byte1]: 70
7706 00:38:49.086296
7707 00:38:49.086811 Set Vref, RX VrefLevel [Byte0]: 71
7708 00:38:49.089414 [Byte1]: 71
7709 00:38:49.093941
7710 00:38:49.094425 Set Vref, RX VrefLevel [Byte0]: 72
7711 00:38:49.100304 [Byte1]: 72
7712 00:38:49.100935
7713 00:38:49.103665 Final RX Vref Byte 0 = 54 to rank0
7714 00:38:49.107223 Final RX Vref Byte 1 = 54 to rank0
7715 00:38:49.110307 Final RX Vref Byte 0 = 54 to rank1
7716 00:38:49.113682 Final RX Vref Byte 1 = 54 to rank1==
7717 00:38:49.116542 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 00:38:49.120082 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7719 00:38:49.120559 ==
7720 00:38:49.120916 DQS Delay:
7721 00:38:49.123293 DQS0 = 0, DQS1 = 0
7722 00:38:49.123754 DQM Delay:
7723 00:38:49.126538 DQM0 = 126, DQM1 = 120
7724 00:38:49.126987 DQ Delay:
7725 00:38:49.129788 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7726 00:38:49.133179 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7727 00:38:49.136602 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7728 00:38:49.139654 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7729 00:38:49.143711
7730 00:38:49.144148
7731 00:38:49.144503
7732 00:38:49.144837 [DramC_TX_OE_Calibration] TA2
7733 00:38:49.146630 Original DQ_B0 (3 6) =30, OEN = 27
7734 00:38:49.149729 Original DQ_B1 (3 6) =30, OEN = 27
7735 00:38:49.153523 24, 0x0, End_B0=24 End_B1=24
7736 00:38:49.156693 25, 0x0, End_B0=25 End_B1=25
7737 00:38:49.159492 26, 0x0, End_B0=26 End_B1=26
7738 00:38:49.159967 27, 0x0, End_B0=27 End_B1=27
7739 00:38:49.163191 28, 0x0, End_B0=28 End_B1=28
7740 00:38:49.166155 29, 0x0, End_B0=29 End_B1=29
7741 00:38:49.169345 30, 0x0, End_B0=30 End_B1=30
7742 00:38:49.172869 31, 0x4141, End_B0=30 End_B1=30
7743 00:38:49.173401 Byte0 end_step=30 best_step=27
7744 00:38:49.176185 Byte1 end_step=30 best_step=27
7745 00:38:49.179449 Byte0 TX OE(2T, 0.5T) = (3, 3)
7746 00:38:49.182945 Byte1 TX OE(2T, 0.5T) = (3, 3)
7747 00:38:49.183381
7748 00:38:49.183732
7749 00:38:49.192580 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7750 00:38:49.193018 CH0 RK0: MR19=303, MR18=1B1B
7751 00:38:49.199484 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7752 00:38:49.199950
7753 00:38:49.202825 ----->DramcWriteLeveling(PI) begin...
7754 00:38:49.203275 ==
7755 00:38:49.206242 Dram Type= 6, Freq= 0, CH_0, rank 1
7756 00:38:49.212601 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7757 00:38:49.213110 ==
7758 00:38:49.215989 Write leveling (Byte 0): 29 => 29
7759 00:38:49.219017 Write leveling (Byte 1): 25 => 25
7760 00:38:49.219457 DramcWriteLeveling(PI) end<-----
7761 00:38:49.219815
7762 00:38:49.222726 ==
7763 00:38:49.225944 Dram Type= 6, Freq= 0, CH_0, rank 1
7764 00:38:49.229050 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7765 00:38:49.229536 ==
7766 00:38:49.232120 [Gating] SW mode calibration
7767 00:38:49.239413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7768 00:38:49.242420 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7769 00:38:49.248750 0 12 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7770 00:38:49.252088 0 12 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7771 00:38:49.255740 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7772 00:38:49.262602 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7773 00:38:49.265396 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7774 00:38:49.268581 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7775 00:38:49.275215 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7776 00:38:49.278501 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7777 00:38:49.281748 0 13 0 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
7778 00:38:49.288623 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7779 00:38:49.291849 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7780 00:38:49.295118 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7781 00:38:49.301805 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7782 00:38:49.305072 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7783 00:38:49.308330 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7784 00:38:49.314916 0 13 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7785 00:38:49.318284 0 14 0 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7786 00:38:49.321560 0 14 4 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
7787 00:38:49.328359 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7788 00:38:49.331347 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7789 00:38:49.334821 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7790 00:38:49.342160 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7791 00:38:49.344910 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7792 00:38:49.348549 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7793 00:38:49.354667 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7794 00:38:49.357933 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7795 00:38:49.361355 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7796 00:38:49.367880 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7797 00:38:49.371335 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7798 00:38:49.374661 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7799 00:38:49.381329 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7800 00:38:49.384643 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7801 00:38:49.387621 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7802 00:38:49.394196 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7803 00:38:49.397558 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7804 00:38:49.401134 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7805 00:38:49.407735 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7806 00:38:49.411333 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 00:38:49.414508 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 00:38:49.421023 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7809 00:38:49.424006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7810 00:38:49.427878 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7811 00:38:49.430768 Total UI for P1: 0, mck2ui 16
7812 00:38:49.433768 best dqsien dly found for B0: ( 1, 0, 30)
7813 00:38:49.440929 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7814 00:38:49.444254 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 00:38:49.447209 Total UI for P1: 0, mck2ui 16
7816 00:38:49.450628 best dqsien dly found for B1: ( 1, 1, 4)
7817 00:38:49.454168 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7818 00:38:49.457134 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7819 00:38:49.457617
7820 00:38:49.460325 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7821 00:38:49.463674 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7822 00:38:49.466905 [Gating] SW calibration Done
7823 00:38:49.467342 ==
7824 00:38:49.470407 Dram Type= 6, Freq= 0, CH_0, rank 1
7825 00:38:49.473784 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7826 00:38:49.474255 ==
7827 00:38:49.477272 RX Vref Scan: 0
7828 00:38:49.477813
7829 00:38:49.480889 RX Vref 0 -> 0, step: 1
7830 00:38:49.481368
7831 00:38:49.481770 RX Delay 0 -> 252, step: 8
7832 00:38:49.486761 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7833 00:38:49.490184 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7834 00:38:49.493349 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7835 00:38:49.496599 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7836 00:38:49.499932 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7837 00:38:49.506775 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7838 00:38:49.509710 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7839 00:38:49.513013 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7840 00:38:49.517212 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7841 00:38:49.520214 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7842 00:38:49.526403 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7843 00:38:49.529760 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7844 00:38:49.533277 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7845 00:38:49.536460 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7846 00:38:49.543169 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7847 00:38:49.546265 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7848 00:38:49.546738 ==
7849 00:38:49.549597 Dram Type= 6, Freq= 0, CH_0, rank 1
7850 00:38:49.552923 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7851 00:38:49.553421 ==
7852 00:38:49.553781 DQS Delay:
7853 00:38:49.556395 DQS0 = 0, DQS1 = 0
7854 00:38:49.556833 DQM Delay:
7855 00:38:49.559557 DQM0 = 130, DQM1 = 123
7856 00:38:49.560018 DQ Delay:
7857 00:38:49.562932 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7858 00:38:49.566308 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7859 00:38:49.569431 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7860 00:38:49.576038 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7861 00:38:49.576457
7862 00:38:49.576787
7863 00:38:49.577084 ==
7864 00:38:49.579500 Dram Type= 6, Freq= 0, CH_0, rank 1
7865 00:38:49.582708 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7866 00:38:49.583119 ==
7867 00:38:49.583444
7868 00:38:49.583738
7869 00:38:49.586110 TX Vref Scan disable
7870 00:38:49.586537 == TX Byte 0 ==
7871 00:38:49.592334 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7872 00:38:49.595871 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7873 00:38:49.596372 == TX Byte 1 ==
7874 00:38:49.602406 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7875 00:38:49.605824 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7876 00:38:49.606282 ==
7877 00:38:49.608724 Dram Type= 6, Freq= 0, CH_0, rank 1
7878 00:38:49.612030 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7879 00:38:49.612545 ==
7880 00:38:49.627905
7881 00:38:49.630814 TX Vref early break, caculate TX vref
7882 00:38:49.634174 TX Vref=16, minBit 8, minWin=22, winSum=373
7883 00:38:49.637502 TX Vref=18, minBit 1, minWin=23, winSum=382
7884 00:38:49.641133 TX Vref=20, minBit 8, minWin=23, winSum=393
7885 00:38:49.644066 TX Vref=22, minBit 1, minWin=24, winSum=397
7886 00:38:49.647728 TX Vref=24, minBit 9, minWin=24, winSum=407
7887 00:38:49.654044 TX Vref=26, minBit 8, minWin=24, winSum=412
7888 00:38:49.657367 TX Vref=28, minBit 0, minWin=25, winSum=413
7889 00:38:49.660863 TX Vref=30, minBit 1, minWin=24, winSum=409
7890 00:38:49.664053 TX Vref=32, minBit 7, minWin=24, winSum=401
7891 00:38:49.667361 TX Vref=34, minBit 8, minWin=23, winSum=392
7892 00:38:49.670650 TX Vref=36, minBit 4, minWin=23, winSum=381
7893 00:38:49.677251 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
7894 00:38:49.677730
7895 00:38:49.680616 Final TX Range 0 Vref 28
7896 00:38:49.681064
7897 00:38:49.681464 ==
7898 00:38:49.683757 Dram Type= 6, Freq= 0, CH_0, rank 1
7899 00:38:49.686889 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7900 00:38:49.687359 ==
7901 00:38:49.687717
7902 00:38:49.690295
7903 00:38:49.690730 TX Vref Scan disable
7904 00:38:49.697046 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7905 00:38:49.697639 == TX Byte 0 ==
7906 00:38:49.700431 u2DelayCellOfst[0]=14 cells (4 PI)
7907 00:38:49.703503 u2DelayCellOfst[1]=18 cells (5 PI)
7908 00:38:49.707010 u2DelayCellOfst[2]=14 cells (4 PI)
7909 00:38:49.710185 u2DelayCellOfst[3]=14 cells (4 PI)
7910 00:38:49.713810 u2DelayCellOfst[4]=7 cells (2 PI)
7911 00:38:49.716879 u2DelayCellOfst[5]=0 cells (0 PI)
7912 00:38:49.720146 u2DelayCellOfst[6]=21 cells (6 PI)
7913 00:38:49.723510 u2DelayCellOfst[7]=18 cells (5 PI)
7914 00:38:49.726856 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7915 00:38:49.730159 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7916 00:38:49.733460 == TX Byte 1 ==
7917 00:38:49.736729 u2DelayCellOfst[8]=3 cells (1 PI)
7918 00:38:49.740038 u2DelayCellOfst[9]=0 cells (0 PI)
7919 00:38:49.743977 u2DelayCellOfst[10]=10 cells (3 PI)
7920 00:38:49.744388 u2DelayCellOfst[11]=3 cells (1 PI)
7921 00:38:49.747004 u2DelayCellOfst[12]=18 cells (5 PI)
7922 00:38:49.750286 u2DelayCellOfst[13]=18 cells (5 PI)
7923 00:38:49.753585 u2DelayCellOfst[14]=18 cells (5 PI)
7924 00:38:49.756622 u2DelayCellOfst[15]=18 cells (5 PI)
7925 00:38:49.763276 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7926 00:38:49.766900 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7927 00:38:49.767312 DramC Write-DBI on
7928 00:38:49.770174 ==
7929 00:38:49.770741 Dram Type= 6, Freq= 0, CH_0, rank 1
7930 00:38:49.776891 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7931 00:38:49.777431 ==
7932 00:38:49.777793
7933 00:38:49.778120
7934 00:38:49.780053 TX Vref Scan disable
7935 00:38:49.780522 == TX Byte 0 ==
7936 00:38:49.786462 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7937 00:38:49.786898 == TX Byte 1 ==
7938 00:38:49.789725 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7939 00:38:49.793189 DramC Write-DBI off
7940 00:38:49.793704
7941 00:38:49.794056 [DATLAT]
7942 00:38:49.796426 Freq=1600, CH0 RK1
7943 00:38:49.796785
7944 00:38:49.797098 DATLAT Default: 0xe
7945 00:38:49.799787 0, 0xFFFF, sum = 0
7946 00:38:49.800293 1, 0xFFFF, sum = 0
7947 00:38:49.802922 2, 0xFFFF, sum = 0
7948 00:38:49.803396 3, 0xFFFF, sum = 0
7949 00:38:49.806527 4, 0xFFFF, sum = 0
7950 00:38:49.806963 5, 0xFFFF, sum = 0
7951 00:38:49.809669 6, 0xFFFF, sum = 0
7952 00:38:49.810119 7, 0xFFFF, sum = 0
7953 00:38:49.812938 8, 0xFFFF, sum = 0
7954 00:38:49.816201 9, 0xFFFF, sum = 0
7955 00:38:49.816633 10, 0xFFFF, sum = 0
7956 00:38:49.819997 11, 0xFFFF, sum = 0
7957 00:38:49.820440 12, 0xCFFF, sum = 0
7958 00:38:49.822709 13, 0x0, sum = 1
7959 00:38:49.823100 14, 0x0, sum = 2
7960 00:38:49.826135 15, 0x0, sum = 3
7961 00:38:49.826578 16, 0x0, sum = 4
7962 00:38:49.827021 best_step = 14
7963 00:38:49.827482
7964 00:38:49.829770 ==
7965 00:38:49.832937 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 00:38:49.836100 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7967 00:38:49.836211 ==
7968 00:38:49.836278 RX Vref Scan: 0
7969 00:38:49.836338
7970 00:38:49.839356 RX Vref 0 -> 0, step: 1
7971 00:38:49.839449
7972 00:38:49.842464 RX Delay 11 -> 252, step: 4
7973 00:38:49.845905 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7974 00:38:49.849235 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7975 00:38:49.856048 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7976 00:38:49.859244 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7977 00:38:49.862250 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7978 00:38:49.865776 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7979 00:38:49.869333 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7980 00:38:49.875512 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7981 00:38:49.878850 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7982 00:38:49.882309 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7983 00:38:49.885393 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7984 00:38:49.888715 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7985 00:38:49.895287 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7986 00:38:49.898700 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7987 00:38:49.902039 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
7988 00:38:49.905342 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7989 00:38:49.905425 ==
7990 00:38:49.908633 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 00:38:49.915402 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7992 00:38:49.915500 ==
7993 00:38:49.915591 DQS Delay:
7994 00:38:49.918459 DQS0 = 0, DQS1 = 0
7995 00:38:49.918552 DQM Delay:
7996 00:38:49.921765 DQM0 = 127, DQM1 = 120
7997 00:38:49.921839 DQ Delay:
7998 00:38:49.925508 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
7999 00:38:49.928607 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
8000 00:38:49.931957 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8001 00:38:49.935201 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =130
8002 00:38:49.935295
8003 00:38:49.935382
8004 00:38:49.935467
8005 00:38:49.938489 [DramC_TX_OE_Calibration] TA2
8006 00:38:49.941881 Original DQ_B0 (3 6) =30, OEN = 27
8007 00:38:49.945190 Original DQ_B1 (3 6) =30, OEN = 27
8008 00:38:49.948265 24, 0x0, End_B0=24 End_B1=24
8009 00:38:49.951720 25, 0x0, End_B0=25 End_B1=25
8010 00:38:49.951789 26, 0x0, End_B0=26 End_B1=26
8011 00:38:49.954899 27, 0x0, End_B0=27 End_B1=27
8012 00:38:49.958307 28, 0x0, End_B0=28 End_B1=28
8013 00:38:49.961902 29, 0x0, End_B0=29 End_B1=29
8014 00:38:49.961974 30, 0x0, End_B0=30 End_B1=30
8015 00:38:49.965349 31, 0x4141, End_B0=30 End_B1=30
8016 00:38:49.968433 Byte0 end_step=30 best_step=27
8017 00:38:49.971623 Byte1 end_step=30 best_step=27
8018 00:38:49.974849 Byte0 TX OE(2T, 0.5T) = (3, 3)
8019 00:38:49.978303 Byte1 TX OE(2T, 0.5T) = (3, 3)
8020 00:38:49.978395
8021 00:38:49.978482
8022 00:38:49.984735 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8023 00:38:49.988046 CH0 RK1: MR19=303, MR18=2525
8024 00:38:49.994822 CH0_RK1: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8025 00:38:49.997904 [RxdqsGatingPostProcess] freq 1600
8026 00:38:50.004409 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8027 00:38:50.004508 Pre-setting of DQS Precalculation
8028 00:38:50.011558 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8029 00:38:50.011649 ==
8030 00:38:50.014498 Dram Type= 6, Freq= 0, CH_1, rank 0
8031 00:38:50.017641 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8032 00:38:50.017738 ==
8033 00:38:50.024842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8034 00:38:50.027840 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8035 00:38:50.031222 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8036 00:38:50.037412 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8037 00:38:50.046561 [CA 0] Center 41 (11~71) winsize 61
8038 00:38:50.049803 [CA 1] Center 41 (11~72) winsize 62
8039 00:38:50.053578 [CA 2] Center 37 (8~67) winsize 60
8040 00:38:50.056683 [CA 3] Center 36 (7~66) winsize 60
8041 00:38:50.059924 [CA 4] Center 34 (4~64) winsize 61
8042 00:38:50.063446 [CA 5] Center 34 (5~64) winsize 60
8043 00:38:50.063542
8044 00:38:50.066441 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8045 00:38:50.066543
8046 00:38:50.069951 [CATrainingPosCal] consider 1 rank data
8047 00:38:50.073107 u2DelayCellTimex100 = 271/100 ps
8048 00:38:50.079702 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8049 00:38:50.082990 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8050 00:38:50.086255 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8051 00:38:50.089618 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8052 00:38:50.092835 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8053 00:38:50.096347 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8054 00:38:50.096418
8055 00:38:50.099569 CA PerBit enable=1, Macro0, CA PI delay=34
8056 00:38:50.099663
8057 00:38:50.102995 [CBTSetCACLKResult] CA Dly = 34
8058 00:38:50.106132 CS Dly: 8 (0~39)
8059 00:38:50.109512 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8060 00:38:50.112687 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8061 00:38:50.112780 ==
8062 00:38:50.116430 Dram Type= 6, Freq= 0, CH_1, rank 1
8063 00:38:50.119566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8064 00:38:50.122583 ==
8065 00:38:50.126142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8066 00:38:50.129657 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8067 00:38:50.135791 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8068 00:38:50.142428 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8069 00:38:50.148934 [CA 0] Center 40 (10~70) winsize 61
8070 00:38:50.152257 [CA 1] Center 39 (9~70) winsize 62
8071 00:38:50.155359 [CA 2] Center 35 (6~65) winsize 60
8072 00:38:50.158869 [CA 3] Center 35 (5~65) winsize 61
8073 00:38:50.162263 [CA 4] Center 33 (4~62) winsize 59
8074 00:38:50.165520 [CA 5] Center 33 (3~63) winsize 61
8075 00:38:50.165591
8076 00:38:50.168906 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8077 00:38:50.168978
8078 00:38:50.172254 [CATrainingPosCal] consider 2 rank data
8079 00:38:50.175366 u2DelayCellTimex100 = 271/100 ps
8080 00:38:50.178790 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8081 00:38:50.185903 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8082 00:38:50.188839 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8083 00:38:50.192429 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8084 00:38:50.195745 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8085 00:38:50.198883 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8086 00:38:50.198955
8087 00:38:50.201979 CA PerBit enable=1, Macro0, CA PI delay=33
8088 00:38:50.202074
8089 00:38:50.205517 [CBTSetCACLKResult] CA Dly = 33
8090 00:38:50.208643 CS Dly: 9 (0~41)
8091 00:38:50.212029 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8092 00:38:50.215465 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8093 00:38:50.215535
8094 00:38:50.218745 ----->DramcWriteLeveling(PI) begin...
8095 00:38:50.218817 ==
8096 00:38:50.222030 Dram Type= 6, Freq= 0, CH_1, rank 0
8097 00:38:50.228512 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8098 00:38:50.228589 ==
8099 00:38:50.231986 Write leveling (Byte 0): 22 => 22
8100 00:38:50.232056 Write leveling (Byte 1): 20 => 20
8101 00:38:50.235413 DramcWriteLeveling(PI) end<-----
8102 00:38:50.235490
8103 00:38:50.235548 ==
8104 00:38:50.238663 Dram Type= 6, Freq= 0, CH_1, rank 0
8105 00:38:50.244956 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8106 00:38:50.245027 ==
8107 00:38:50.248688 [Gating] SW mode calibration
8108 00:38:50.255008 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8109 00:38:50.258332 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8110 00:38:50.265194 0 12 0 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8111 00:38:50.268195 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8112 00:38:50.271727 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8113 00:38:50.278472 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 00:38:50.281659 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 00:38:50.284790 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 00:38:50.291180 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8117 00:38:50.294728 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8118 00:38:50.298047 0 13 0 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8119 00:38:50.304641 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8120 00:38:50.307920 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8121 00:38:50.311397 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 00:38:50.318312 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 00:38:50.321243 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 00:38:50.324369 0 13 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8125 00:38:50.331467 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8126 00:38:50.334485 0 14 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8127 00:38:50.337624 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8128 00:38:50.344477 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8129 00:38:50.347549 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 00:38:50.351094 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 00:38:50.357296 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 00:38:50.360681 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8133 00:38:50.364032 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8134 00:38:50.370885 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8135 00:38:50.374297 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8136 00:38:50.377245 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 00:38:50.383982 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 00:38:50.387200 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 00:38:50.390858 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 00:38:50.397220 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 00:38:50.400432 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 00:38:50.403749 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 00:38:50.407285 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 00:38:50.413737 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 00:38:50.417160 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 00:38:50.420518 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 00:38:50.426986 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 00:38:50.430516 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8149 00:38:50.433767 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8150 00:38:50.440440 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8151 00:38:50.443810 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8152 00:38:50.447499 Total UI for P1: 0, mck2ui 16
8153 00:38:50.450214 best dqsien dly found for B0: ( 1, 0, 28)
8154 00:38:50.454002 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 00:38:50.456979 Total UI for P1: 0, mck2ui 16
8156 00:38:50.460374 best dqsien dly found for B1: ( 1, 1, 4)
8157 00:38:50.463542 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8158 00:38:50.466996 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8159 00:38:50.467064
8160 00:38:50.473771 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8161 00:38:50.476875 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8162 00:38:50.476973 [Gating] SW calibration Done
8163 00:38:50.479970 ==
8164 00:38:50.483470 Dram Type= 6, Freq= 0, CH_1, rank 0
8165 00:38:50.486906 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8166 00:38:50.486982 ==
8167 00:38:50.487044 RX Vref Scan: 0
8168 00:38:50.487105
8169 00:38:50.490281 RX Vref 0 -> 0, step: 1
8170 00:38:50.490347
8171 00:38:50.493345 RX Delay 0 -> 252, step: 8
8172 00:38:50.496735 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8173 00:38:50.499880 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8174 00:38:50.503103 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8175 00:38:50.509925 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8176 00:38:50.513174 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8177 00:38:50.516619 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8178 00:38:50.519947 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8179 00:38:50.523461 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8180 00:38:50.529739 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8181 00:38:50.533212 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8182 00:38:50.536458 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8183 00:38:50.539837 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8184 00:38:50.542946 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8185 00:38:50.549641 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8186 00:38:50.552992 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8187 00:38:50.556466 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8188 00:38:50.556546 ==
8189 00:38:50.559654 Dram Type= 6, Freq= 0, CH_1, rank 0
8190 00:38:50.565917 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8191 00:38:50.565997 ==
8192 00:38:50.566059 DQS Delay:
8193 00:38:50.566116 DQS0 = 0, DQS1 = 0
8194 00:38:50.569724 DQM Delay:
8195 00:38:50.569802 DQM0 = 130, DQM1 = 126
8196 00:38:50.572662 DQ Delay:
8197 00:38:50.576242 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8198 00:38:50.579236 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8199 00:38:50.582853 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8200 00:38:50.585828 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8201 00:38:50.585907
8202 00:38:50.585969
8203 00:38:50.586026 ==
8204 00:38:50.589689 Dram Type= 6, Freq= 0, CH_1, rank 0
8205 00:38:50.592469 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8206 00:38:50.595795 ==
8207 00:38:50.595873
8208 00:38:50.595935
8209 00:38:50.595992 TX Vref Scan disable
8210 00:38:50.599333 == TX Byte 0 ==
8211 00:38:50.602579 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8212 00:38:50.605523 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8213 00:38:50.609234 == TX Byte 1 ==
8214 00:38:50.612059 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8215 00:38:50.615400 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8216 00:38:50.618826 ==
8217 00:38:50.622395 Dram Type= 6, Freq= 0, CH_1, rank 0
8218 00:38:50.625699 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8219 00:38:50.625779 ==
8220 00:38:50.637273
8221 00:38:50.640468 TX Vref early break, caculate TX vref
8222 00:38:50.644172 TX Vref=16, minBit 3, minWin=22, winSum=372
8223 00:38:50.647125 TX Vref=18, minBit 3, minWin=21, winSum=376
8224 00:38:50.650525 TX Vref=20, minBit 0, minWin=22, winSum=387
8225 00:38:50.653685 TX Vref=22, minBit 0, minWin=23, winSum=395
8226 00:38:50.657038 TX Vref=24, minBit 1, minWin=24, winSum=408
8227 00:38:50.663520 TX Vref=26, minBit 0, minWin=24, winSum=408
8228 00:38:50.666885 TX Vref=28, minBit 0, minWin=25, winSum=419
8229 00:38:50.670514 TX Vref=30, minBit 3, minWin=23, winSum=406
8230 00:38:50.673535 TX Vref=32, minBit 1, minWin=23, winSum=399
8231 00:38:50.676806 TX Vref=34, minBit 0, minWin=23, winSum=389
8232 00:38:50.683630 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8233 00:38:50.683709
8234 00:38:50.687400 Final TX Range 0 Vref 28
8235 00:38:50.687479
8236 00:38:50.687541 ==
8237 00:38:50.690382 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 00:38:50.693429 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8239 00:38:50.693510 ==
8240 00:38:50.693572
8241 00:38:50.693629
8242 00:38:50.696746 TX Vref Scan disable
8243 00:38:50.703427 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8244 00:38:50.703506 == TX Byte 0 ==
8245 00:38:50.706892 u2DelayCellOfst[0]=14 cells (4 PI)
8246 00:38:50.710117 u2DelayCellOfst[1]=10 cells (3 PI)
8247 00:38:50.713507 u2DelayCellOfst[2]=0 cells (0 PI)
8248 00:38:50.716713 u2DelayCellOfst[3]=7 cells (2 PI)
8249 00:38:50.720275 u2DelayCellOfst[4]=7 cells (2 PI)
8250 00:38:50.723278 u2DelayCellOfst[5]=14 cells (4 PI)
8251 00:38:50.726947 u2DelayCellOfst[6]=18 cells (5 PI)
8252 00:38:50.727022 u2DelayCellOfst[7]=7 cells (2 PI)
8253 00:38:50.733212 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8254 00:38:50.736792 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8255 00:38:50.736889 == TX Byte 1 ==
8256 00:38:50.740073 u2DelayCellOfst[8]=0 cells (0 PI)
8257 00:38:50.743378 u2DelayCellOfst[9]=3 cells (1 PI)
8258 00:38:50.746503 u2DelayCellOfst[10]=7 cells (2 PI)
8259 00:38:50.749811 u2DelayCellOfst[11]=3 cells (1 PI)
8260 00:38:50.753175 u2DelayCellOfst[12]=14 cells (4 PI)
8261 00:38:50.756648 u2DelayCellOfst[13]=14 cells (4 PI)
8262 00:38:50.759682 u2DelayCellOfst[14]=14 cells (4 PI)
8263 00:38:50.762961 u2DelayCellOfst[15]=14 cells (4 PI)
8264 00:38:50.766361 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8265 00:38:50.773198 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8266 00:38:50.773301 DramC Write-DBI on
8267 00:38:50.773382 ==
8268 00:38:50.776350 Dram Type= 6, Freq= 0, CH_1, rank 0
8269 00:38:50.779859 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8270 00:38:50.783037 ==
8271 00:38:50.783116
8272 00:38:50.783177
8273 00:38:50.783234 TX Vref Scan disable
8274 00:38:50.786354 == TX Byte 0 ==
8275 00:38:50.789951 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8276 00:38:50.793098 == TX Byte 1 ==
8277 00:38:50.796242 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8278 00:38:50.799549 DramC Write-DBI off
8279 00:38:50.799633
8280 00:38:50.799696 [DATLAT]
8281 00:38:50.799754 Freq=1600, CH1 RK0
8282 00:38:50.799810
8283 00:38:50.802768 DATLAT Default: 0xf
8284 00:38:50.802847 0, 0xFFFF, sum = 0
8285 00:38:50.806363 1, 0xFFFF, sum = 0
8286 00:38:50.809671 2, 0xFFFF, sum = 0
8287 00:38:50.809751 3, 0xFFFF, sum = 0
8288 00:38:50.812648 4, 0xFFFF, sum = 0
8289 00:38:50.812729 5, 0xFFFF, sum = 0
8290 00:38:50.816110 6, 0xFFFF, sum = 0
8291 00:38:50.816190 7, 0xFFFF, sum = 0
8292 00:38:50.819225 8, 0xFFFF, sum = 0
8293 00:38:50.819306 9, 0xFFFF, sum = 0
8294 00:38:50.822551 10, 0xFFFF, sum = 0
8295 00:38:50.822637 11, 0xFFFF, sum = 0
8296 00:38:50.826303 12, 0xFFF, sum = 0
8297 00:38:50.826384 13, 0x0, sum = 1
8298 00:38:50.829528 14, 0x0, sum = 2
8299 00:38:50.829608 15, 0x0, sum = 3
8300 00:38:50.832776 16, 0x0, sum = 4
8301 00:38:50.832855 best_step = 14
8302 00:38:50.832917
8303 00:38:50.832974 ==
8304 00:38:50.835954 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 00:38:50.839135 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8306 00:38:50.842619 ==
8307 00:38:50.842730 RX Vref Scan: 1
8308 00:38:50.842821
8309 00:38:50.846078 Set Vref Range= 24 -> 127
8310 00:38:50.846168
8311 00:38:50.849272 RX Vref 24 -> 127, step: 1
8312 00:38:50.849386
8313 00:38:50.849449 RX Delay 3 -> 252, step: 4
8314 00:38:50.849507
8315 00:38:50.852565 Set Vref, RX VrefLevel [Byte0]: 24
8316 00:38:50.855757 [Byte1]: 24
8317 00:38:50.859655
8318 00:38:50.859734 Set Vref, RX VrefLevel [Byte0]: 25
8319 00:38:50.862913 [Byte1]: 25
8320 00:38:50.867173
8321 00:38:50.867251 Set Vref, RX VrefLevel [Byte0]: 26
8322 00:38:50.870629 [Byte1]: 26
8323 00:38:50.875098
8324 00:38:50.875181 Set Vref, RX VrefLevel [Byte0]: 27
8325 00:38:50.878162 [Byte1]: 27
8326 00:38:50.882412
8327 00:38:50.882490 Set Vref, RX VrefLevel [Byte0]: 28
8328 00:38:50.886170 [Byte1]: 28
8329 00:38:50.890360
8330 00:38:50.890438 Set Vref, RX VrefLevel [Byte0]: 29
8331 00:38:50.893547 [Byte1]: 29
8332 00:38:50.898190
8333 00:38:50.898268 Set Vref, RX VrefLevel [Byte0]: 30
8334 00:38:50.901618 [Byte1]: 30
8335 00:38:50.906319
8336 00:38:50.906397 Set Vref, RX VrefLevel [Byte0]: 31
8337 00:38:50.908837 [Byte1]: 31
8338 00:38:50.912958
8339 00:38:50.916363 Set Vref, RX VrefLevel [Byte0]: 32
8340 00:38:50.919438 [Byte1]: 32
8341 00:38:50.919517
8342 00:38:50.923167 Set Vref, RX VrefLevel [Byte0]: 33
8343 00:38:50.926248 [Byte1]: 33
8344 00:38:50.926327
8345 00:38:50.929852 Set Vref, RX VrefLevel [Byte0]: 34
8346 00:38:50.932828 [Byte1]: 34
8347 00:38:50.936153
8348 00:38:50.936231 Set Vref, RX VrefLevel [Byte0]: 35
8349 00:38:50.939458 [Byte1]: 35
8350 00:38:50.943815
8351 00:38:50.943893 Set Vref, RX VrefLevel [Byte0]: 36
8352 00:38:50.947141 [Byte1]: 36
8353 00:38:50.951333
8354 00:38:50.951411 Set Vref, RX VrefLevel [Byte0]: 37
8355 00:38:50.954969 [Byte1]: 37
8356 00:38:50.959040
8357 00:38:50.959121 Set Vref, RX VrefLevel [Byte0]: 38
8358 00:38:50.962389 [Byte1]: 38
8359 00:38:50.966835
8360 00:38:50.966914 Set Vref, RX VrefLevel [Byte0]: 39
8361 00:38:50.969991 [Byte1]: 39
8362 00:38:50.974309
8363 00:38:50.974387 Set Vref, RX VrefLevel [Byte0]: 40
8364 00:38:50.977800 [Byte1]: 40
8365 00:38:50.982094
8366 00:38:50.982172 Set Vref, RX VrefLevel [Byte0]: 41
8367 00:38:50.985595 [Byte1]: 41
8368 00:38:50.989527
8369 00:38:50.989605 Set Vref, RX VrefLevel [Byte0]: 42
8370 00:38:50.992908 [Byte1]: 42
8371 00:38:50.997784
8372 00:38:50.997861 Set Vref, RX VrefLevel [Byte0]: 43
8373 00:38:51.000401 [Byte1]: 43
8374 00:38:51.005142
8375 00:38:51.005220 Set Vref, RX VrefLevel [Byte0]: 44
8376 00:38:51.008283 [Byte1]: 44
8377 00:38:51.012975
8378 00:38:51.013053 Set Vref, RX VrefLevel [Byte0]: 45
8379 00:38:51.015915 [Byte1]: 45
8380 00:38:51.020518
8381 00:38:51.020595 Set Vref, RX VrefLevel [Byte0]: 46
8382 00:38:51.023731 [Byte1]: 46
8383 00:38:51.028162
8384 00:38:51.028240 Set Vref, RX VrefLevel [Byte0]: 47
8385 00:38:51.031278 [Byte1]: 47
8386 00:38:51.035596
8387 00:38:51.035674 Set Vref, RX VrefLevel [Byte0]: 48
8388 00:38:51.038765 [Byte1]: 48
8389 00:38:51.043259
8390 00:38:51.043337 Set Vref, RX VrefLevel [Byte0]: 49
8391 00:38:51.046546 [Byte1]: 49
8392 00:38:51.051145
8393 00:38:51.051223 Set Vref, RX VrefLevel [Byte0]: 50
8394 00:38:51.054217 [Byte1]: 50
8395 00:38:51.058681
8396 00:38:51.058758 Set Vref, RX VrefLevel [Byte0]: 51
8397 00:38:51.061776 [Byte1]: 51
8398 00:38:51.066380
8399 00:38:51.066458 Set Vref, RX VrefLevel [Byte0]: 52
8400 00:38:51.069480 [Byte1]: 52
8401 00:38:51.074190
8402 00:38:51.074269 Set Vref, RX VrefLevel [Byte0]: 53
8403 00:38:51.077012 [Byte1]: 53
8404 00:38:51.081559
8405 00:38:51.081637 Set Vref, RX VrefLevel [Byte0]: 54
8406 00:38:51.085055 [Byte1]: 54
8407 00:38:51.089153
8408 00:38:51.089257 Set Vref, RX VrefLevel [Byte0]: 55
8409 00:38:51.092451 [Byte1]: 55
8410 00:38:51.097029
8411 00:38:51.097107 Set Vref, RX VrefLevel [Byte0]: 56
8412 00:38:51.100312 [Byte1]: 56
8413 00:38:51.104866
8414 00:38:51.104944 Set Vref, RX VrefLevel [Byte0]: 57
8415 00:38:51.107904 [Byte1]: 57
8416 00:38:51.112204
8417 00:38:51.112282 Set Vref, RX VrefLevel [Byte0]: 58
8418 00:38:51.115622 [Byte1]: 58
8419 00:38:51.119744
8420 00:38:51.119826 Set Vref, RX VrefLevel [Byte0]: 59
8421 00:38:51.123465 [Byte1]: 59
8422 00:38:51.127456
8423 00:38:51.127534 Set Vref, RX VrefLevel [Byte0]: 60
8424 00:38:51.130752 [Byte1]: 60
8425 00:38:51.135034
8426 00:38:51.135112 Set Vref, RX VrefLevel [Byte0]: 61
8427 00:38:51.138494 [Byte1]: 61
8428 00:38:51.143094
8429 00:38:51.143172 Set Vref, RX VrefLevel [Byte0]: 62
8430 00:38:51.145831 [Byte1]: 62
8431 00:38:51.150306
8432 00:38:51.150384 Set Vref, RX VrefLevel [Byte0]: 63
8433 00:38:51.153887 [Byte1]: 63
8434 00:38:51.158165
8435 00:38:51.158243 Set Vref, RX VrefLevel [Byte0]: 64
8436 00:38:51.161314 [Byte1]: 64
8437 00:38:51.165823
8438 00:38:51.165901 Set Vref, RX VrefLevel [Byte0]: 65
8439 00:38:51.169123 [Byte1]: 65
8440 00:38:51.173228
8441 00:38:51.173359 Set Vref, RX VrefLevel [Byte0]: 66
8442 00:38:51.176568 [Byte1]: 66
8443 00:38:51.181070
8444 00:38:51.181174 Set Vref, RX VrefLevel [Byte0]: 67
8445 00:38:51.184298 [Byte1]: 67
8446 00:38:51.188844
8447 00:38:51.188923 Set Vref, RX VrefLevel [Byte0]: 68
8448 00:38:51.191836 [Byte1]: 68
8449 00:38:51.196342
8450 00:38:51.196413 Set Vref, RX VrefLevel [Byte0]: 69
8451 00:38:51.199619 [Byte1]: 69
8452 00:38:51.204079
8453 00:38:51.204175 Set Vref, RX VrefLevel [Byte0]: 70
8454 00:38:51.207364 [Byte1]: 70
8455 00:38:51.211598
8456 00:38:51.211673 Set Vref, RX VrefLevel [Byte0]: 71
8457 00:38:51.214802 [Byte1]: 71
8458 00:38:51.219208
8459 00:38:51.219279 Set Vref, RX VrefLevel [Byte0]: 72
8460 00:38:51.222537 [Byte1]: 72
8461 00:38:51.226786
8462 00:38:51.226858 Set Vref, RX VrefLevel [Byte0]: 73
8463 00:38:51.230392 [Byte1]: 73
8464 00:38:51.234493
8465 00:38:51.234561 Set Vref, RX VrefLevel [Byte0]: 74
8466 00:38:51.237704 [Byte1]: 74
8467 00:38:51.242233
8468 00:38:51.242301 Set Vref, RX VrefLevel [Byte0]: 75
8469 00:38:51.245760 [Byte1]: 75
8470 00:38:51.250018
8471 00:38:51.250086 Set Vref, RX VrefLevel [Byte0]: 76
8472 00:38:51.253072 [Byte1]: 76
8473 00:38:51.257722
8474 00:38:51.257793 Set Vref, RX VrefLevel [Byte0]: 77
8475 00:38:51.260841 [Byte1]: 77
8476 00:38:51.265123
8477 00:38:51.265218 Final RX Vref Byte 0 = 60 to rank0
8478 00:38:51.268789 Final RX Vref Byte 1 = 54 to rank0
8479 00:38:51.271854 Final RX Vref Byte 0 = 60 to rank1
8480 00:38:51.275413 Final RX Vref Byte 1 = 54 to rank1==
8481 00:38:51.278561 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 00:38:51.285044 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8483 00:38:51.285120 ==
8484 00:38:51.285206 DQS Delay:
8485 00:38:51.285264 DQS0 = 0, DQS1 = 0
8486 00:38:51.288313 DQM Delay:
8487 00:38:51.288381 DQM0 = 129, DQM1 = 122
8488 00:38:51.292043 DQ Delay:
8489 00:38:51.295180 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
8490 00:38:51.298423 DQ4 =130, DQ5 =140, DQ6 =136, DQ7 =124
8491 00:38:51.301626 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8492 00:38:51.305116 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8493 00:38:51.305215
8494 00:38:51.305329
8495 00:38:51.305428
8496 00:38:51.308492 [DramC_TX_OE_Calibration] TA2
8497 00:38:51.311588 Original DQ_B0 (3 6) =30, OEN = 27
8498 00:38:51.314700 Original DQ_B1 (3 6) =30, OEN = 27
8499 00:38:51.318360 24, 0x0, End_B0=24 End_B1=24
8500 00:38:51.318431 25, 0x0, End_B0=25 End_B1=25
8501 00:38:51.321453 26, 0x0, End_B0=26 End_B1=26
8502 00:38:51.324819 27, 0x0, End_B0=27 End_B1=27
8503 00:38:51.327960 28, 0x0, End_B0=28 End_B1=28
8504 00:38:51.331393 29, 0x0, End_B0=29 End_B1=29
8505 00:38:51.331466 30, 0x0, End_B0=30 End_B1=30
8506 00:38:51.334662 31, 0x4141, End_B0=30 End_B1=30
8507 00:38:51.337862 Byte0 end_step=30 best_step=27
8508 00:38:51.342045 Byte1 end_step=30 best_step=27
8509 00:38:51.344648 Byte0 TX OE(2T, 0.5T) = (3, 3)
8510 00:38:51.348005 Byte1 TX OE(2T, 0.5T) = (3, 3)
8511 00:38:51.348098
8512 00:38:51.348183
8513 00:38:51.354590 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8514 00:38:51.357944 CH1 RK0: MR19=303, MR18=2626
8515 00:38:51.364630 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8516 00:38:51.364702
8517 00:38:51.368092 ----->DramcWriteLeveling(PI) begin...
8518 00:38:51.368167 ==
8519 00:38:51.371386 Dram Type= 6, Freq= 0, CH_1, rank 1
8520 00:38:51.374739 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8521 00:38:51.374814 ==
8522 00:38:51.377813 Write leveling (Byte 0): 22 => 22
8523 00:38:51.381167 Write leveling (Byte 1): 20 => 20
8524 00:38:51.384426 DramcWriteLeveling(PI) end<-----
8525 00:38:51.384505
8526 00:38:51.384567 ==
8527 00:38:51.387660 Dram Type= 6, Freq= 0, CH_1, rank 1
8528 00:38:51.391311 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8529 00:38:51.391391 ==
8530 00:38:51.394305 [Gating] SW mode calibration
8531 00:38:51.400923 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8532 00:38:51.407991 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8533 00:38:51.411070 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8534 00:38:51.417717 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8535 00:38:51.420769 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8536 00:38:51.424110 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8537 00:38:51.430959 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8538 00:38:51.434557 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8539 00:38:51.437315 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8540 00:38:51.440922 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8541 00:38:51.447903 0 13 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8542 00:38:51.450658 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8543 00:38:51.453979 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8544 00:38:51.460604 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8545 00:38:51.463925 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8546 00:38:51.467398 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8547 00:38:51.473793 0 13 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8548 00:38:51.476980 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8549 00:38:51.480614 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8550 00:38:51.487039 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8551 00:38:51.490532 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8552 00:38:51.493855 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8553 00:38:51.500443 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8554 00:38:51.503694 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8555 00:38:51.506770 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8556 00:38:51.513739 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8557 00:38:51.516893 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8558 00:38:51.519983 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 00:38:51.526919 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 00:38:51.530036 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 00:38:51.533476 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 00:38:51.539811 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 00:38:51.543177 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 00:38:51.546968 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 00:38:51.553179 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 00:38:51.556403 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 00:38:51.559843 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 00:38:51.566998 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 00:38:51.569641 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 00:38:51.573197 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8571 00:38:51.579607 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8572 00:38:51.582880 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8573 00:38:51.586264 Total UI for P1: 0, mck2ui 16
8574 00:38:51.589800 best dqsien dly found for B0: ( 1, 0, 22)
8575 00:38:51.592987 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8576 00:38:51.596227 Total UI for P1: 0, mck2ui 16
8577 00:38:51.599577 best dqsien dly found for B1: ( 1, 0, 28)
8578 00:38:51.603020 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8579 00:38:51.606176 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8580 00:38:51.606272
8581 00:38:51.612757 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8582 00:38:51.616362 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8583 00:38:51.616477 [Gating] SW calibration Done
8584 00:38:51.619347 ==
8585 00:38:51.622708 Dram Type= 6, Freq= 0, CH_1, rank 1
8586 00:38:51.626059 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8587 00:38:51.626131 ==
8588 00:38:51.626192 RX Vref Scan: 0
8589 00:38:51.626252
8590 00:38:51.629659 RX Vref 0 -> 0, step: 1
8591 00:38:51.629728
8592 00:38:51.632929 RX Delay 0 -> 252, step: 8
8593 00:38:51.636599 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8594 00:38:51.639563 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8595 00:38:51.642685 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8596 00:38:51.649419 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8597 00:38:51.652767 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8598 00:38:51.655719 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8599 00:38:51.659500 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8600 00:38:51.662733 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8601 00:38:51.669406 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8602 00:38:51.672268 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8603 00:38:51.675680 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8604 00:38:51.678913 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8605 00:38:51.685876 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8606 00:38:51.688869 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8607 00:38:51.692319 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8608 00:38:51.695549 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8609 00:38:51.695623 ==
8610 00:38:51.698882 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 00:38:51.705566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 00:38:51.705665 ==
8613 00:38:51.705753 DQS Delay:
8614 00:38:51.705840 DQS0 = 0, DQS1 = 0
8615 00:38:51.708961 DQM Delay:
8616 00:38:51.709029 DQM0 = 131, DQM1 = 125
8617 00:38:51.712147 DQ Delay:
8618 00:38:51.715314 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8619 00:38:51.718745 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8620 00:38:51.721818 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8621 00:38:51.725241 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8622 00:38:51.725331
8623 00:38:51.725392
8624 00:38:51.725454 ==
8625 00:38:51.728739 Dram Type= 6, Freq= 0, CH_1, rank 1
8626 00:38:51.731939 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8627 00:38:51.735648 ==
8628 00:38:51.735717
8629 00:38:51.735782
8630 00:38:51.735837 TX Vref Scan disable
8631 00:38:51.738620 == TX Byte 0 ==
8632 00:38:51.741742 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8633 00:38:51.745135 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8634 00:38:51.748480 == TX Byte 1 ==
8635 00:38:51.751550 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8636 00:38:51.755088 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8637 00:38:51.758166 ==
8638 00:38:51.761471 Dram Type= 6, Freq= 0, CH_1, rank 1
8639 00:38:51.764717 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8640 00:38:51.764791 ==
8641 00:38:51.777613
8642 00:38:51.781460 TX Vref early break, caculate TX vref
8643 00:38:51.784543 TX Vref=16, minBit 0, minWin=20, winSum=372
8644 00:38:51.787767 TX Vref=18, minBit 6, minWin=22, winSum=390
8645 00:38:51.791832 TX Vref=20, minBit 2, minWin=23, winSum=398
8646 00:38:51.794707 TX Vref=22, minBit 2, minWin=24, winSum=407
8647 00:38:51.797919 TX Vref=24, minBit 0, minWin=25, winSum=415
8648 00:38:51.804360 TX Vref=26, minBit 0, minWin=25, winSum=420
8649 00:38:51.807674 TX Vref=28, minBit 0, minWin=25, winSum=421
8650 00:38:51.810952 TX Vref=30, minBit 0, minWin=25, winSum=415
8651 00:38:51.814174 TX Vref=32, minBit 0, minWin=24, winSum=409
8652 00:38:51.817554 TX Vref=34, minBit 0, minWin=22, winSum=400
8653 00:38:51.820550 TX Vref=36, minBit 0, minWin=22, winSum=392
8654 00:38:51.827267 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8655 00:38:51.827344
8656 00:38:51.830714 Final TX Range 0 Vref 28
8657 00:38:51.830784
8658 00:38:51.830842 ==
8659 00:38:51.833898 Dram Type= 6, Freq= 0, CH_1, rank 1
8660 00:38:51.837245 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8661 00:38:51.837366 ==
8662 00:38:51.837440
8663 00:38:51.840570
8664 00:38:51.840638 TX Vref Scan disable
8665 00:38:51.847090 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8666 00:38:51.847165 == TX Byte 0 ==
8667 00:38:51.850666 u2DelayCellOfst[0]=14 cells (4 PI)
8668 00:38:51.853821 u2DelayCellOfst[1]=7 cells (2 PI)
8669 00:38:51.857020 u2DelayCellOfst[2]=0 cells (0 PI)
8670 00:38:51.860528 u2DelayCellOfst[3]=3 cells (1 PI)
8671 00:38:51.864066 u2DelayCellOfst[4]=7 cells (2 PI)
8672 00:38:51.866911 u2DelayCellOfst[5]=14 cells (4 PI)
8673 00:38:51.870954 u2DelayCellOfst[6]=14 cells (4 PI)
8674 00:38:51.873989 u2DelayCellOfst[7]=3 cells (1 PI)
8675 00:38:51.876849 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8676 00:38:51.880157 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8677 00:38:51.883320 == TX Byte 1 ==
8678 00:38:51.886936 u2DelayCellOfst[8]=0 cells (0 PI)
8679 00:38:51.890115 u2DelayCellOfst[9]=3 cells (1 PI)
8680 00:38:51.893242 u2DelayCellOfst[10]=7 cells (2 PI)
8681 00:38:51.893363 u2DelayCellOfst[11]=3 cells (1 PI)
8682 00:38:51.896643 u2DelayCellOfst[12]=14 cells (4 PI)
8683 00:38:51.899895 u2DelayCellOfst[13]=18 cells (5 PI)
8684 00:38:51.903637 u2DelayCellOfst[14]=18 cells (5 PI)
8685 00:38:51.906732 u2DelayCellOfst[15]=18 cells (5 PI)
8686 00:38:51.913406 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8687 00:38:51.916848 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8688 00:38:51.916959 DramC Write-DBI on
8689 00:38:51.917051 ==
8690 00:38:51.920088 Dram Type= 6, Freq= 0, CH_1, rank 1
8691 00:38:51.926874 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8692 00:38:51.926989 ==
8693 00:38:51.927081
8694 00:38:51.927168
8695 00:38:51.929887 TX Vref Scan disable
8696 00:38:51.929956 == TX Byte 0 ==
8697 00:38:51.936429 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8698 00:38:51.936504 == TX Byte 1 ==
8699 00:38:51.939565 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8700 00:38:51.943293 DramC Write-DBI off
8701 00:38:51.943393
8702 00:38:51.943484 [DATLAT]
8703 00:38:51.946227 Freq=1600, CH1 RK1
8704 00:38:51.946303
8705 00:38:51.946437 DATLAT Default: 0xe
8706 00:38:51.949662 0, 0xFFFF, sum = 0
8707 00:38:51.949733 1, 0xFFFF, sum = 0
8708 00:38:51.952749 2, 0xFFFF, sum = 0
8709 00:38:51.952818 3, 0xFFFF, sum = 0
8710 00:38:51.956176 4, 0xFFFF, sum = 0
8711 00:38:51.956274 5, 0xFFFF, sum = 0
8712 00:38:51.959605 6, 0xFFFF, sum = 0
8713 00:38:51.959703 7, 0xFFFF, sum = 0
8714 00:38:51.962667 8, 0xFFFF, sum = 0
8715 00:38:51.962762 9, 0xFFFF, sum = 0
8716 00:38:51.966078 10, 0xFFFF, sum = 0
8717 00:38:51.969945 11, 0xFFFF, sum = 0
8718 00:38:51.970058 12, 0xFFF, sum = 0
8719 00:38:51.972832 13, 0x0, sum = 1
8720 00:38:51.972931 14, 0x0, sum = 2
8721 00:38:51.973020 15, 0x0, sum = 3
8722 00:38:51.975896 16, 0x0, sum = 4
8723 00:38:51.975978 best_step = 14
8724 00:38:51.976040
8725 00:38:51.979203 ==
8726 00:38:51.982479 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 00:38:51.985823 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8728 00:38:51.985903 ==
8729 00:38:51.985966 RX Vref Scan: 0
8730 00:38:51.986024
8731 00:38:51.989210 RX Vref 0 -> 0, step: 1
8732 00:38:51.989296
8733 00:38:51.992638 RX Delay 3 -> 252, step: 4
8734 00:38:51.995795 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8735 00:38:51.999465 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8736 00:38:52.005545 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8737 00:38:52.009350 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8738 00:38:52.012388 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8739 00:38:52.015456 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8740 00:38:52.018864 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8741 00:38:52.025671 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8742 00:38:52.028891 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8743 00:38:52.032324 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8744 00:38:52.035467 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8745 00:38:52.041757 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8746 00:38:52.045152 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8747 00:38:52.048879 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8748 00:38:52.052165 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8749 00:38:52.055074 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8750 00:38:52.058409 ==
8751 00:38:52.058502 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 00:38:52.064981 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8753 00:38:52.065087 ==
8754 00:38:52.065186 DQS Delay:
8755 00:38:52.068697 DQS0 = 0, DQS1 = 0
8756 00:38:52.068793 DQM Delay:
8757 00:38:52.071887 DQM0 = 127, DQM1 = 122
8758 00:38:52.071968 DQ Delay:
8759 00:38:52.074937 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8760 00:38:52.078540 DQ4 =126, DQ5 =138, DQ6 =138, DQ7 =126
8761 00:38:52.081985 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8762 00:38:52.085077 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8763 00:38:52.085158
8764 00:38:52.085256
8765 00:38:52.085370
8766 00:38:52.088348 [DramC_TX_OE_Calibration] TA2
8767 00:38:52.091562 Original DQ_B0 (3 6) =30, OEN = 27
8768 00:38:52.095157 Original DQ_B1 (3 6) =30, OEN = 27
8769 00:38:52.098168 24, 0x0, End_B0=24 End_B1=24
8770 00:38:52.101410 25, 0x0, End_B0=25 End_B1=25
8771 00:38:52.101484 26, 0x0, End_B0=26 End_B1=26
8772 00:38:52.105070 27, 0x0, End_B0=27 End_B1=27
8773 00:38:52.108138 28, 0x0, End_B0=28 End_B1=28
8774 00:38:52.111465 29, 0x0, End_B0=29 End_B1=29
8775 00:38:52.114657 30, 0x0, End_B0=30 End_B1=30
8776 00:38:52.114757 31, 0x4141, End_B0=30 End_B1=30
8777 00:38:52.117852 Byte0 end_step=30 best_step=27
8778 00:38:52.121541 Byte1 end_step=30 best_step=27
8779 00:38:52.124730 Byte0 TX OE(2T, 0.5T) = (3, 3)
8780 00:38:52.128082 Byte1 TX OE(2T, 0.5T) = (3, 3)
8781 00:38:52.128164
8782 00:38:52.128227
8783 00:38:52.134724 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8784 00:38:52.137650 CH1 RK1: MR19=303, MR18=1E1E
8785 00:38:52.144556 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8786 00:38:52.147906 [RxdqsGatingPostProcess] freq 1600
8787 00:38:52.154623 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8788 00:38:52.154705 Pre-setting of DQS Precalculation
8789 00:38:52.161232 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8790 00:38:52.167620 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8791 00:38:52.174437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8792 00:38:52.174517
8793 00:38:52.174600
8794 00:38:52.177704 [Calibration Summary] 3200 Mbps
8795 00:38:52.181149 CH 0, Rank 0
8796 00:38:52.181247 SW Impedance : PASS
8797 00:38:52.184358 DUTY Scan : NO K
8798 00:38:52.187889 ZQ Calibration : PASS
8799 00:38:52.187985 Jitter Meter : NO K
8800 00:38:52.191110 CBT Training : PASS
8801 00:38:52.194337 Write leveling : PASS
8802 00:38:52.194407 RX DQS gating : PASS
8803 00:38:52.197652 RX DQ/DQS(RDDQC) : PASS
8804 00:38:52.197722 TX DQ/DQS : PASS
8805 00:38:52.200975 RX DATLAT : PASS
8806 00:38:52.203974 RX DQ/DQS(Engine): PASS
8807 00:38:52.204072 TX OE : PASS
8808 00:38:52.207771 All Pass.
8809 00:38:52.207857
8810 00:38:52.207952 CH 0, Rank 1
8811 00:38:52.210812 SW Impedance : PASS
8812 00:38:52.210883 DUTY Scan : NO K
8813 00:38:52.213892 ZQ Calibration : PASS
8814 00:38:52.217547 Jitter Meter : NO K
8815 00:38:52.217620 CBT Training : PASS
8816 00:38:52.221006 Write leveling : PASS
8817 00:38:52.224091 RX DQS gating : PASS
8818 00:38:52.224200 RX DQ/DQS(RDDQC) : PASS
8819 00:38:52.227366 TX DQ/DQS : PASS
8820 00:38:52.230495 RX DATLAT : PASS
8821 00:38:52.230572 RX DQ/DQS(Engine): PASS
8822 00:38:52.233912 TX OE : PASS
8823 00:38:52.233985 All Pass.
8824 00:38:52.234044
8825 00:38:52.237147 CH 1, Rank 0
8826 00:38:52.237214 SW Impedance : PASS
8827 00:38:52.240434 DUTY Scan : NO K
8828 00:38:52.243969 ZQ Calibration : PASS
8829 00:38:52.244039 Jitter Meter : NO K
8830 00:38:52.247233 CBT Training : PASS
8831 00:38:52.250464 Write leveling : PASS
8832 00:38:52.250531 RX DQS gating : PASS
8833 00:38:52.254062 RX DQ/DQS(RDDQC) : PASS
8834 00:38:52.257012 TX DQ/DQS : PASS
8835 00:38:52.257079 RX DATLAT : PASS
8836 00:38:52.260281 RX DQ/DQS(Engine): PASS
8837 00:38:52.263957 TX OE : PASS
8838 00:38:52.264051 All Pass.
8839 00:38:52.264143
8840 00:38:52.264229 CH 1, Rank 1
8841 00:38:52.266956 SW Impedance : PASS
8842 00:38:52.267037 DUTY Scan : NO K
8843 00:38:52.270436 ZQ Calibration : PASS
8844 00:38:52.273870 Jitter Meter : NO K
8845 00:38:52.273973 CBT Training : PASS
8846 00:38:52.277126 Write leveling : PASS
8847 00:38:52.280390 RX DQS gating : PASS
8848 00:38:52.280460 RX DQ/DQS(RDDQC) : PASS
8849 00:38:52.283637 TX DQ/DQS : PASS
8850 00:38:52.287084 RX DATLAT : PASS
8851 00:38:52.287178 RX DQ/DQS(Engine): PASS
8852 00:38:52.290086 TX OE : PASS
8853 00:38:52.290155 All Pass.
8854 00:38:52.290222
8855 00:38:52.293562 DramC Write-DBI on
8856 00:38:52.296896 PER_BANK_REFRESH: Hybrid Mode
8857 00:38:52.296966 TX_TRACKING: ON
8858 00:38:52.306835 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8859 00:38:52.313545 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8860 00:38:52.320037 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8861 00:38:52.326943 [FAST_K] Save calibration result to emmc
8862 00:38:52.327018 sync common calibartion params.
8863 00:38:52.329928 sync cbt_mode0:0, 1:0
8864 00:38:52.333186 dram_init: ddr_geometry: 0
8865 00:38:52.333255 dram_init: ddr_geometry: 0
8866 00:38:52.336628 dram_init: ddr_geometry: 0
8867 00:38:52.339919 0:dram_rank_size:80000000
8868 00:38:52.343172 1:dram_rank_size:80000000
8869 00:38:52.346541 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8870 00:38:52.349762 DFS_SHUFFLE_HW_MODE: ON
8871 00:38:52.353055 dramc_set_vcore_voltage set vcore to 725000
8872 00:38:52.356390 Read voltage for 1600, 0
8873 00:38:52.356485 Vio18 = 0
8874 00:38:52.356571 Vcore = 725000
8875 00:38:52.359691 Vdram = 0
8876 00:38:52.359758 Vddq = 0
8877 00:38:52.359814 Vmddr = 0
8878 00:38:52.362864 switch to 3200 Mbps bootup
8879 00:38:52.366401 [DramcRunTimeConfig]
8880 00:38:52.366502 PHYPLL
8881 00:38:52.366589 DPM_CONTROL_AFTERK: ON
8882 00:38:52.369671 PER_BANK_REFRESH: ON
8883 00:38:52.373086 REFRESH_OVERHEAD_REDUCTION: ON
8884 00:38:52.373178 CMD_PICG_NEW_MODE: OFF
8885 00:38:52.376575 XRTWTW_NEW_MODE: ON
8886 00:38:52.376672 XRTRTR_NEW_MODE: ON
8887 00:38:52.379607 TX_TRACKING: ON
8888 00:38:52.379690 RDSEL_TRACKING: OFF
8889 00:38:52.382900 DQS Precalculation for DVFS: ON
8890 00:38:52.386296 RX_TRACKING: OFF
8891 00:38:52.386372 HW_GATING DBG: ON
8892 00:38:52.389788 ZQCS_ENABLE_LP4: ON
8893 00:38:52.389888 RX_PICG_NEW_MODE: ON
8894 00:38:52.392709 TX_PICG_NEW_MODE: ON
8895 00:38:52.396361 ENABLE_RX_DCM_DPHY: ON
8896 00:38:52.399499 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8897 00:38:52.399569 DUMMY_READ_FOR_TRACKING: OFF
8898 00:38:52.402938 !!! SPM_CONTROL_AFTERK: OFF
8899 00:38:52.406176 !!! SPM could not control APHY
8900 00:38:52.409945 IMPEDANCE_TRACKING: ON
8901 00:38:52.410040 TEMP_SENSOR: ON
8902 00:38:52.412837 HW_SAVE_FOR_SR: OFF
8903 00:38:52.412933 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8904 00:38:52.419328 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8905 00:38:52.419400 Read ODT Tracking: ON
8906 00:38:52.422926 Refresh Rate DeBounce: ON
8907 00:38:52.423028 DFS_NO_QUEUE_FLUSH: ON
8908 00:38:52.426161 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8909 00:38:52.429274 ENABLE_DFS_RUNTIME_MRW: OFF
8910 00:38:52.432702 DDR_RESERVE_NEW_MODE: ON
8911 00:38:52.432772 MR_CBT_SWITCH_FREQ: ON
8912 00:38:52.435735 =========================
8913 00:38:52.455187 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8914 00:38:52.458566 dram_init: ddr_geometry: 0
8915 00:38:52.476393 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8916 00:38:52.479667 dram_init: dram init end (result: 0)
8917 00:38:52.486577 DRAM-K: Full calibration passed in 23469 msecs
8918 00:38:52.489788 MRC: failed to locate region type 0.
8919 00:38:52.489889 DRAM rank0 size:0x80000000,
8920 00:38:52.492919 DRAM rank1 size=0x80000000
8921 00:38:52.502876 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8922 00:38:52.509565 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8923 00:38:52.516302 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8924 00:38:52.522711 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8925 00:38:52.526184 DRAM rank0 size:0x80000000,
8926 00:38:52.529388 DRAM rank1 size=0x80000000
8927 00:38:52.529482 CBMEM:
8928 00:38:52.532469 IMD: root @ 0xfffff000 254 entries.
8929 00:38:52.535850 IMD: root @ 0xffffec00 62 entries.
8930 00:38:52.539449 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8931 00:38:52.543170 WARNING: RO_VPD is uninitialized or empty.
8932 00:38:52.549146 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8933 00:38:52.556079 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8934 00:38:52.568682 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
8935 00:38:52.580407 BS: romstage times (exec / console): total (unknown) / 23001 ms
8936 00:38:52.580503
8937 00:38:52.580566
8938 00:38:52.590128 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8939 00:38:52.593833 ARM64: Exception handlers installed.
8940 00:38:52.596706 ARM64: Testing exception
8941 00:38:52.600304 ARM64: Done test exception
8942 00:38:52.600384 Enumerating buses...
8943 00:38:52.603675 Show all devs... Before device enumeration.
8944 00:38:52.606759 Root Device: enabled 1
8945 00:38:52.610359 CPU_CLUSTER: 0: enabled 1
8946 00:38:52.610439 CPU: 00: enabled 1
8947 00:38:52.613855 Compare with tree...
8948 00:38:52.613934 Root Device: enabled 1
8949 00:38:52.616798 CPU_CLUSTER: 0: enabled 1
8950 00:38:52.620336 CPU: 00: enabled 1
8951 00:38:52.620415 Root Device scanning...
8952 00:38:52.623148 scan_static_bus for Root Device
8953 00:38:52.626407 CPU_CLUSTER: 0 enabled
8954 00:38:52.629589 scan_static_bus for Root Device done
8955 00:38:52.632938 scan_bus: bus Root Device finished in 8 msecs
8956 00:38:52.633017 done
8957 00:38:52.639677 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8958 00:38:52.643004 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8959 00:38:52.649854 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8960 00:38:52.652878 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8961 00:38:52.656459 Allocating resources...
8962 00:38:52.659412 Reading resources...
8963 00:38:52.662849 Root Device read_resources bus 0 link: 0
8964 00:38:52.666071 DRAM rank0 size:0x80000000,
8965 00:38:52.666149 DRAM rank1 size=0x80000000
8966 00:38:52.669576 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8967 00:38:52.672734 CPU: 00 missing read_resources
8968 00:38:52.679230 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8969 00:38:52.682701 Root Device read_resources bus 0 link: 0 done
8970 00:38:52.682780 Done reading resources.
8971 00:38:52.689561 Show resources in subtree (Root Device)...After reading.
8972 00:38:52.692643 Root Device child on link 0 CPU_CLUSTER: 0
8973 00:38:52.695648 CPU_CLUSTER: 0 child on link 0 CPU: 00
8974 00:38:52.705964 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8975 00:38:52.706066 CPU: 00
8976 00:38:52.708919 Root Device assign_resources, bus 0 link: 0
8977 00:38:52.712476 CPU_CLUSTER: 0 missing set_resources
8978 00:38:52.719175 Root Device assign_resources, bus 0 link: 0 done
8979 00:38:52.719274 Done setting resources.
8980 00:38:52.725886 Show resources in subtree (Root Device)...After assigning values.
8981 00:38:52.728902 Root Device child on link 0 CPU_CLUSTER: 0
8982 00:38:52.732420 CPU_CLUSTER: 0 child on link 0 CPU: 00
8983 00:38:52.742343 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8984 00:38:52.742423 CPU: 00
8985 00:38:52.745382 Done allocating resources.
8986 00:38:52.751925 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8987 00:38:52.752005 Enabling resources...
8988 00:38:52.752067 done.
8989 00:38:52.758852 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8990 00:38:52.758932 Initializing devices...
8991 00:38:52.761676 Root Device init
8992 00:38:52.765229 init hardware done!
8993 00:38:52.765342 0x00000018: ctrlr->caps
8994 00:38:52.768583 52.000 MHz: ctrlr->f_max
8995 00:38:52.768664 0.400 MHz: ctrlr->f_min
8996 00:38:52.771929 0x40ff8080: ctrlr->voltages
8997 00:38:52.775454 sclk: 390625
8998 00:38:52.775532 Bus Width = 1
8999 00:38:52.775595 sclk: 390625
9000 00:38:52.778470 Bus Width = 1
9001 00:38:52.778583 Early init status = 3
9002 00:38:52.784973 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9003 00:38:52.788413 in-header: 03 fc 00 00 01 00 00 00
9004 00:38:52.791830 in-data: 00
9005 00:38:52.794937 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9006 00:38:52.798852 in-header: 03 fd 00 00 00 00 00 00
9007 00:38:52.802114 in-data:
9008 00:38:52.805810 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9009 00:38:52.809016 in-header: 03 fc 00 00 01 00 00 00
9010 00:38:52.812270 in-data: 00
9011 00:38:52.815484 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9012 00:38:52.821150 in-header: 03 fd 00 00 00 00 00 00
9013 00:38:52.824389 in-data:
9014 00:38:52.827805 [SSUSB] Setting up USB HOST controller...
9015 00:38:52.831033 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9016 00:38:52.834236 [SSUSB] phy power-on done.
9017 00:38:52.837518 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9018 00:38:52.844096 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9019 00:38:52.847339 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9020 00:38:52.854103 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9021 00:38:52.860704 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9022 00:38:52.867785 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9023 00:38:52.873965 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9024 00:38:52.880961 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9025 00:38:52.883965 SPM: binary array size = 0x9dc
9026 00:38:52.887448 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9027 00:38:52.894008 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9028 00:38:52.900763 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9029 00:38:52.904297 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9030 00:38:52.910272 configure_display: Starting display init
9031 00:38:52.944741 anx7625_power_on_init: Init interface.
9032 00:38:52.947845 anx7625_disable_pd_protocol: Disabled PD feature.
9033 00:38:52.950937 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9034 00:38:52.978511 anx7625_start_dp_work: Secure OCM version=00
9035 00:38:52.981861 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9036 00:38:52.996739 sp_tx_get_edid_block: EDID Block = 1
9037 00:38:53.099269 Extracted contents:
9038 00:38:53.102725 header: 00 ff ff ff ff ff ff 00
9039 00:38:53.105987 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9040 00:38:53.109461 version: 01 04
9041 00:38:53.112633 basic params: 95 1f 11 78 0a
9042 00:38:53.115682 chroma info: 76 90 94 55 54 90 27 21 50 54
9043 00:38:53.119111 established: 00 00 00
9044 00:38:53.125591 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9045 00:38:53.132317 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9046 00:38:53.135826 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9047 00:38:53.142294 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9048 00:38:53.149002 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9049 00:38:53.152101 extensions: 00
9050 00:38:53.152180 checksum: fb
9051 00:38:53.152243
9052 00:38:53.158580 Manufacturer: IVO Model 57d Serial Number 0
9053 00:38:53.158660 Made week 0 of 2020
9054 00:38:53.161656 EDID version: 1.4
9055 00:38:53.161735 Digital display
9056 00:38:53.165046 6 bits per primary color channel
9057 00:38:53.165126 DisplayPort interface
9058 00:38:53.168480 Maximum image size: 31 cm x 17 cm
9059 00:38:53.171791 Gamma: 220%
9060 00:38:53.171870 Check DPMS levels
9061 00:38:53.178388 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9062 00:38:53.181921 First detailed timing is preferred timing
9063 00:38:53.182001 Established timings supported:
9064 00:38:53.185168 Standard timings supported:
9065 00:38:53.188423 Detailed timings
9066 00:38:53.191744 Hex of detail: 383680a07038204018303c0035ae10000019
9067 00:38:53.198255 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9068 00:38:53.201677 0780 0798 07c8 0820 hborder 0
9069 00:38:53.204784 0438 043b 0447 0458 vborder 0
9070 00:38:53.208354 -hsync -vsync
9071 00:38:53.208433 Did detailed timing
9072 00:38:53.214659 Hex of detail: 000000000000000000000000000000000000
9073 00:38:53.217942 Manufacturer-specified data, tag 0
9074 00:38:53.221641 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9075 00:38:53.224615 ASCII string: InfoVision
9076 00:38:53.228200 Hex of detail: 000000fe00523134304e574635205248200a
9077 00:38:53.231439 ASCII string: R140NWF5 RH
9078 00:38:53.231518 Checksum
9079 00:38:53.234950 Checksum: 0xfb (valid)
9080 00:38:53.237872 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9081 00:38:53.241238 DSI data_rate: 832800000 bps
9082 00:38:53.247721 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9083 00:38:53.251169 anx7625_parse_edid: pixelclock(138800).
9084 00:38:53.254384 hactive(1920), hsync(48), hfp(24), hbp(88)
9085 00:38:53.257671 vactive(1080), vsync(12), vfp(3), vbp(17)
9086 00:38:53.261543 anx7625_dsi_config: config dsi.
9087 00:38:53.267712 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9088 00:38:53.281524 anx7625_dsi_config: success to config DSI
9089 00:38:53.284692 anx7625_dp_start: MIPI phy setup OK.
9090 00:38:53.287924 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9091 00:38:53.291298 mtk_ddp_mode_set invalid vrefresh 60
9092 00:38:53.294652 main_disp_path_setup
9093 00:38:53.294726 ovl_layer_smi_id_en
9094 00:38:53.297687 ovl_layer_smi_id_en
9095 00:38:53.297783 ccorr_config
9096 00:38:53.297879 aal_config
9097 00:38:53.301123 gamma_config
9098 00:38:53.301221 postmask_config
9099 00:38:53.304479 dither_config
9100 00:38:53.308277 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9101 00:38:53.314559 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9102 00:38:53.317499 Root Device init finished in 552 msecs
9103 00:38:53.320974 CPU_CLUSTER: 0 init
9104 00:38:53.327560 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9105 00:38:53.334273 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9106 00:38:53.334355 APU_MBOX 0x190000b0 = 0x10001
9107 00:38:53.337674 APU_MBOX 0x190001b0 = 0x10001
9108 00:38:53.341065 APU_MBOX 0x190005b0 = 0x10001
9109 00:38:53.343970 APU_MBOX 0x190006b0 = 0x10001
9110 00:38:53.350759 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9111 00:38:53.360232 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9112 00:38:53.372752 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9113 00:38:53.379305 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9114 00:38:53.391056 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9115 00:38:53.400059 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9116 00:38:53.403318 CPU_CLUSTER: 0 init finished in 81 msecs
9117 00:38:53.406667 Devices initialized
9118 00:38:53.410066 Show all devs... After init.
9119 00:38:53.410145 Root Device: enabled 1
9120 00:38:53.413559 CPU_CLUSTER: 0: enabled 1
9121 00:38:53.416953 CPU: 00: enabled 1
9122 00:38:53.419828 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9123 00:38:53.423002 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9124 00:38:53.426281 ELOG: NV offset 0x57f000 size 0x1000
9125 00:38:53.433072 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9126 00:38:53.439760 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9127 00:38:53.443152 ELOG: Event(17) added with size 13 at 2024-06-05 00:38:53 UTC
9128 00:38:53.446435 out: cmd=0x121: 03 db 21 01 00 00 00 00
9129 00:38:53.451340 in-header: 03 c8 00 00 2c 00 00 00
9130 00:38:53.464599 in-data: 9b 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9131 00:38:53.471045 ELOG: Event(A1) added with size 10 at 2024-06-05 00:38:53 UTC
9132 00:38:53.477890 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9133 00:38:53.484373 ELOG: Event(A0) added with size 9 at 2024-06-05 00:38:53 UTC
9134 00:38:53.487486 elog_add_boot_reason: Logged dev mode boot
9135 00:38:53.490851 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9136 00:38:53.494181 Finalize devices...
9137 00:38:53.494260 Devices finalized
9138 00:38:53.500642 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9139 00:38:53.504407 Writing coreboot table at 0xffe64000
9140 00:38:53.507336 0. 000000000010a000-0000000000113fff: RAMSTAGE
9141 00:38:53.510647 1. 0000000040000000-00000000400fffff: RAM
9142 00:38:53.517378 2. 0000000040100000-000000004032afff: RAMSTAGE
9143 00:38:53.520603 3. 000000004032b000-00000000545fffff: RAM
9144 00:38:53.523960 4. 0000000054600000-000000005465ffff: BL31
9145 00:38:53.527475 5. 0000000054660000-00000000ffe63fff: RAM
9146 00:38:53.533933 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9147 00:38:53.537075 7. 0000000100000000-000000013fffffff: RAM
9148 00:38:53.537149 Passing 5 GPIOs to payload:
9149 00:38:53.543917 NAME | PORT | POLARITY | VALUE
9150 00:38:53.547133 EC in RW | 0x000000aa | low | undefined
9151 00:38:53.553726 EC interrupt | 0x00000005 | low | undefined
9152 00:38:53.556817 TPM interrupt | 0x000000ab | high | undefined
9153 00:38:53.563415 SD card detect | 0x00000011 | high | undefined
9154 00:38:53.566808 speaker enable | 0x00000093 | high | undefined
9155 00:38:53.570191 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9156 00:38:53.573434 in-header: 03 f4 00 00 02 00 00 00
9157 00:38:53.576816 in-data: 07 00
9158 00:38:53.576889 ADC[4]: Raw value=669327 ID=5
9159 00:38:53.580017 ADC[3]: Raw value=212549 ID=1
9160 00:38:53.583478 RAM Code: 0x51
9161 00:38:53.583553 ADC[6]: Raw value=74778 ID=0
9162 00:38:53.586341 ADC[5]: Raw value=211812 ID=1
9163 00:38:53.589711 SKU Code: 0x1
9164 00:38:53.593170 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 191d
9165 00:38:53.596398 coreboot table: 964 bytes.
9166 00:38:53.599952 IMD ROOT 0. 0xfffff000 0x00001000
9167 00:38:53.603096 IMD SMALL 1. 0xffffe000 0x00001000
9168 00:38:53.606223 RO MCACHE 2. 0xffffc000 0x00001104
9169 00:38:53.609779 CONSOLE 3. 0xfff7c000 0x00080000
9170 00:38:53.613159 FMAP 4. 0xfff7b000 0x00000452
9171 00:38:53.616354 TIME STAMP 5. 0xfff7a000 0x00000910
9172 00:38:53.619673 VBOOT WORK 6. 0xfff66000 0x00014000
9173 00:38:53.622926 RAMOOPS 7. 0xffe66000 0x00100000
9174 00:38:53.626179 COREBOOT 8. 0xffe64000 0x00002000
9175 00:38:53.626254 IMD small region:
9176 00:38:53.633019 IMD ROOT 0. 0xffffec00 0x00000400
9177 00:38:53.636354 VPD 1. 0xffffeb80 0x0000006c
9178 00:38:53.639356 MMC STATUS 2. 0xffffeb60 0x00000004
9179 00:38:53.642680 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9180 00:38:53.646083 Probing TPM: done!
9181 00:38:53.649406 Connected to device vid:did:rid of 1ae0:0028:00
9182 00:38:53.659343 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9183 00:38:53.662823 Initialized TPM device CR50 revision 0
9184 00:38:53.666498 Checking cr50 for pending updates
9185 00:38:53.670239 Reading cr50 TPM mode
9186 00:38:53.678867 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9187 00:38:53.685616 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9188 00:38:53.725607 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9189 00:38:53.728933 Checking segment from ROM address 0x40100000
9190 00:38:53.732300 Checking segment from ROM address 0x4010001c
9191 00:38:53.738736 Loading segment from ROM address 0x40100000
9192 00:38:53.738811 code (compression=0)
9193 00:38:53.748689 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9194 00:38:53.755621 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9195 00:38:53.755702 it's not compressed!
9196 00:38:53.762011 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9197 00:38:53.768798 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9198 00:38:53.785888 Loading segment from ROM address 0x4010001c
9199 00:38:53.785992 Entry Point 0x80000000
9200 00:38:53.789179 Loaded segments
9201 00:38:53.793024 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9202 00:38:53.799140 Jumping to boot code at 0x80000000(0xffe64000)
9203 00:38:53.806179 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9204 00:38:53.812760 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9205 00:38:53.820497 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9206 00:38:53.824114 Checking segment from ROM address 0x40100000
9207 00:38:53.827188 Checking segment from ROM address 0x4010001c
9208 00:38:53.833881 Loading segment from ROM address 0x40100000
9209 00:38:53.833966 code (compression=1)
9210 00:38:53.840509 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9211 00:38:53.850404 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9212 00:38:53.850483 using LZMA
9213 00:38:53.858890 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9214 00:38:53.865513 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9215 00:38:53.868665 Loading segment from ROM address 0x4010001c
9216 00:38:53.868767 Entry Point 0x54601000
9217 00:38:53.871990 Loaded segments
9218 00:38:53.875490 NOTICE: MT8192 bl31_setup
9219 00:38:53.882399 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9220 00:38:53.885841 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9221 00:38:53.888978 WARNING: region 0:
9222 00:38:53.892598 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9223 00:38:53.892693 WARNING: region 1:
9224 00:38:53.899082 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9225 00:38:53.902365 WARNING: region 2:
9226 00:38:53.905755 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9227 00:38:53.908876 WARNING: region 3:
9228 00:38:53.912383 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9229 00:38:53.915618 WARNING: region 4:
9230 00:38:53.922447 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9231 00:38:53.922528 WARNING: region 5:
9232 00:38:53.925641 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9233 00:38:53.929079 WARNING: region 6:
9234 00:38:53.932187 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9235 00:38:53.935660 WARNING: region 7:
9236 00:38:53.938872 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9237 00:38:53.945784 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9238 00:38:53.948900 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9239 00:38:53.952167 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9240 00:38:53.958645 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9241 00:38:53.962176 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9242 00:38:53.965522 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9243 00:38:53.972250 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9244 00:38:53.975593 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9245 00:38:53.982391 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9246 00:38:53.985717 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9247 00:38:53.988848 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9248 00:38:53.995819 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9249 00:38:53.998936 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9250 00:38:54.002401 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9251 00:38:54.009117 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9252 00:38:54.012445 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9253 00:38:54.018639 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9254 00:38:54.022157 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9255 00:38:54.025391 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9256 00:38:54.032263 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9257 00:38:54.035593 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9258 00:38:54.038691 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9259 00:38:54.045730 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9260 00:38:54.049013 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9261 00:38:54.055662 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9262 00:38:54.059164 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9263 00:38:54.062470 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9264 00:38:54.068830 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9265 00:38:54.072418 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9266 00:38:54.078877 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9267 00:38:54.082410 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9268 00:38:54.085474 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9269 00:38:54.092085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9270 00:38:54.095388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9271 00:38:54.098864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9272 00:38:54.102286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9273 00:38:54.108725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9274 00:38:54.111896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9275 00:38:54.115440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9276 00:38:54.118949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9277 00:38:54.125323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9278 00:38:54.128752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9279 00:38:54.132158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9280 00:38:54.135221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9281 00:38:54.142099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9282 00:38:54.145253 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9283 00:38:54.148548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9284 00:38:54.152033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9285 00:38:54.158579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9286 00:38:54.161937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9287 00:38:54.168736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9288 00:38:54.172128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9289 00:38:54.178428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9290 00:38:54.182027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9291 00:38:54.185256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9292 00:38:54.191847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9293 00:38:54.195195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9294 00:38:54.202005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9295 00:38:54.205702 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9296 00:38:54.211922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9297 00:38:54.215185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9298 00:38:54.218662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9299 00:38:54.225394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9300 00:38:54.228487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9301 00:38:54.235184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9302 00:38:54.238643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9303 00:38:54.245089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9304 00:38:54.248704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9305 00:38:54.251668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9306 00:38:54.258252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9307 00:38:54.261833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9308 00:38:54.268414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9309 00:38:54.271892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9310 00:38:54.278675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9311 00:38:54.281965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9312 00:38:54.288513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9313 00:38:54.291585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9314 00:38:54.295047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9315 00:38:54.301519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9316 00:38:54.304989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9317 00:38:54.311691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9318 00:38:54.315147 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9319 00:38:54.321874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9320 00:38:54.325223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9321 00:38:54.328298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9322 00:38:54.334796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9323 00:38:54.338371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9324 00:38:54.345186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9325 00:38:54.348380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9326 00:38:54.354942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9327 00:38:54.358303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9328 00:38:54.361729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9329 00:38:54.368244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9330 00:38:54.371433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9331 00:38:54.378277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9332 00:38:54.381605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9333 00:38:54.384907 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9334 00:38:54.391838 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9335 00:38:54.395050 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9336 00:38:54.398165 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9337 00:38:54.401840 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9338 00:38:54.408400 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9339 00:38:54.411508 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9340 00:38:54.418089 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9341 00:38:54.421836 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9342 00:38:54.425036 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9343 00:38:54.431732 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9344 00:38:54.434768 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9345 00:38:54.441468 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9346 00:38:54.444690 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9347 00:38:54.448168 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9348 00:38:54.454991 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9349 00:38:54.458204 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9350 00:38:54.465076 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9351 00:38:54.468264 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9352 00:38:54.471742 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9353 00:38:54.478387 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9354 00:38:54.481743 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9355 00:38:54.485184 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9356 00:38:54.488680 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9357 00:38:54.494987 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9358 00:38:54.498200 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9359 00:38:54.501527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9360 00:38:54.504947 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9361 00:38:54.511805 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9362 00:38:54.514973 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9363 00:38:54.521702 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9364 00:38:54.525068 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9365 00:38:54.528378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9366 00:38:54.534960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9367 00:38:54.538392 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9368 00:38:54.545406 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9369 00:38:54.548504 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9370 00:38:54.551444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9371 00:38:54.558335 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9372 00:38:54.561500 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9373 00:38:54.568582 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9374 00:38:54.571518 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9375 00:38:54.575116 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9376 00:38:54.581412 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9377 00:38:54.584646 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9378 00:38:54.588088 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9379 00:38:54.594836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9380 00:38:54.598348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9381 00:38:54.604879 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9382 00:38:54.607885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9383 00:38:54.611496 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9384 00:38:54.618063 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9385 00:38:54.621430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9386 00:38:54.628381 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9387 00:38:54.631360 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9388 00:38:54.634705 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9389 00:38:54.641524 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9390 00:38:54.644818 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9391 00:38:54.648008 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9392 00:38:54.654645 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9393 00:38:54.658069 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9394 00:38:54.665069 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9395 00:38:54.667883 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9396 00:38:54.671239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9397 00:38:54.678013 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9398 00:38:54.681224 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9399 00:38:54.688271 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9400 00:38:54.691124 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9401 00:38:54.694487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9402 00:38:54.701195 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9403 00:38:54.704495 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9404 00:38:54.711196 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9405 00:38:54.714618 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9406 00:38:54.717584 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9407 00:38:54.724614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9408 00:38:54.727882 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9409 00:38:54.734389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9410 00:38:54.737794 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9411 00:38:54.741199 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9412 00:38:54.747811 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9413 00:38:54.750818 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9414 00:38:54.757693 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9415 00:38:54.760934 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9416 00:38:54.764003 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9417 00:38:54.770646 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9418 00:38:54.774083 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9419 00:38:54.777441 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9420 00:38:54.783954 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9421 00:38:54.787431 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9422 00:38:54.794022 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9423 00:38:54.797018 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9424 00:38:54.800668 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9425 00:38:54.807181 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9426 00:38:54.810406 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9427 00:38:54.817412 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9428 00:38:54.820513 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9429 00:38:54.826849 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9430 00:38:54.830123 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9431 00:38:54.833298 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9432 00:38:54.840149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9433 00:38:54.843431 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9434 00:38:54.850469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9435 00:38:54.853246 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9436 00:38:54.860166 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9437 00:38:54.863149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9438 00:38:54.866419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9439 00:38:54.873497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9440 00:38:54.876421 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9441 00:38:54.883066 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9442 00:38:54.886366 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9443 00:38:54.893176 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9444 00:38:54.896693 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9445 00:38:54.899824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9446 00:38:54.906301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9447 00:38:54.909752 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9448 00:38:54.916278 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9449 00:38:54.919531 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9450 00:38:54.922833 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9451 00:38:54.929704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9452 00:38:54.932645 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9453 00:38:54.939481 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9454 00:38:54.942557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9455 00:38:54.949133 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9456 00:38:54.952443 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9457 00:38:54.955776 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9458 00:38:54.962542 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9459 00:38:54.966300 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9460 00:38:54.972507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9461 00:38:54.975718 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9462 00:38:54.982464 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9463 00:38:54.985647 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9464 00:38:54.989275 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9465 00:38:54.995764 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9466 00:38:54.998771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9467 00:38:55.002054 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9468 00:38:55.005447 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9469 00:38:55.012134 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9470 00:38:55.015557 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9471 00:38:55.018914 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9472 00:38:55.025329 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9473 00:38:55.028928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9474 00:38:55.035437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9475 00:38:55.038647 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9476 00:38:55.041608 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9477 00:38:55.048603 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9478 00:38:55.051836 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9479 00:38:55.055092 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9480 00:38:55.061797 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9481 00:38:55.065019 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9482 00:38:55.068271 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9483 00:38:55.075224 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9484 00:38:55.078400 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9485 00:38:55.081518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9486 00:38:55.088199 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9487 00:38:55.091702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9488 00:38:55.098095 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9489 00:38:55.101547 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9490 00:38:55.104786 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9491 00:38:55.111296 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9492 00:38:55.114975 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9493 00:38:55.118146 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9494 00:38:55.124770 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9495 00:38:55.128160 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9496 00:38:55.134852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9497 00:38:55.137884 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9498 00:38:55.141222 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9499 00:38:55.147803 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9500 00:38:55.151283 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9501 00:38:55.154381 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9502 00:38:55.161022 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9503 00:38:55.164418 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9504 00:38:55.171153 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9505 00:38:55.174746 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9506 00:38:55.177765 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9507 00:38:55.181233 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9508 00:38:55.184562 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9509 00:38:55.191162 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9510 00:38:55.194631 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9511 00:38:55.197474 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9512 00:38:55.201097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9513 00:38:55.207666 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9514 00:38:55.210793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9515 00:38:55.214227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9516 00:38:55.217330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9517 00:38:55.224148 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9518 00:38:55.227850 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9519 00:38:55.230717 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9520 00:38:55.237320 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9521 00:38:55.240884 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9522 00:38:55.247810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9523 00:38:55.250772 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9524 00:38:55.257476 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9525 00:38:55.260557 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9526 00:38:55.263970 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9527 00:38:55.270447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9528 00:38:55.273901 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9529 00:38:55.280648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9530 00:38:55.283831 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9531 00:38:55.287116 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9532 00:38:55.293968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9533 00:38:55.297185 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9534 00:38:55.303722 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9535 00:38:55.307163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9536 00:38:55.310728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9537 00:38:55.316921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9538 00:38:55.320214 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9539 00:38:55.327287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9540 00:38:55.330370 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9541 00:38:55.336851 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9542 00:38:55.340124 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9543 00:38:55.343448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9544 00:38:55.350367 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9545 00:38:55.353498 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9546 00:38:55.360383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9547 00:38:55.363387 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9548 00:38:55.366948 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9549 00:38:55.373671 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9550 00:38:55.376950 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9551 00:38:55.383370 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9552 00:38:55.386704 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9553 00:38:55.390126 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9554 00:38:55.396717 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9555 00:38:55.400169 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9556 00:38:55.406737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9557 00:38:55.410071 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9558 00:38:55.413311 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9559 00:38:55.419837 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9560 00:38:55.423526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9561 00:38:55.429901 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9562 00:38:55.433040 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9563 00:38:55.439803 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9564 00:38:55.442898 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9565 00:38:55.446197 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9566 00:38:55.453347 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9567 00:38:55.456428 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9568 00:38:55.463093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9569 00:38:55.466527 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9570 00:38:55.469397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9571 00:38:55.476032 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9572 00:38:55.479368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9573 00:38:55.486129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9574 00:38:55.489481 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9575 00:38:55.492910 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9576 00:38:55.499874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9577 00:38:55.502597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9578 00:38:55.509505 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9579 00:38:55.512495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9580 00:38:55.519174 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9581 00:38:55.522465 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9582 00:38:55.525873 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9583 00:38:55.532414 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9584 00:38:55.535771 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9585 00:38:55.542386 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9586 00:38:55.545846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9587 00:38:55.549195 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9588 00:38:55.555718 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9589 00:38:55.559003 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9590 00:38:55.565862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9591 00:38:55.568839 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9592 00:38:55.572399 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9593 00:38:55.578897 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9594 00:38:55.582103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9595 00:38:55.589253 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9596 00:38:55.592369 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9597 00:38:55.598829 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9598 00:38:55.602001 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9599 00:38:55.608709 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9600 00:38:55.611862 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9601 00:38:55.614997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9602 00:38:55.622138 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9603 00:38:55.624960 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9604 00:38:55.631940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9605 00:38:55.634985 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9606 00:38:55.641502 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9607 00:38:55.644778 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9608 00:38:55.651467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9609 00:38:55.654920 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9610 00:38:55.658214 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9611 00:38:55.664582 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9612 00:38:55.667977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9613 00:38:55.674663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9614 00:38:55.677751 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9615 00:38:55.684458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9616 00:38:55.687897 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9617 00:38:55.691164 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9618 00:38:55.698144 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9619 00:38:55.701441 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9620 00:38:55.707994 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9621 00:38:55.711441 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9622 00:38:55.718124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9623 00:38:55.721269 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9624 00:38:55.724478 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9625 00:38:55.731234 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9626 00:38:55.734674 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9627 00:38:55.741161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9628 00:38:55.744706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9629 00:38:55.751151 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9630 00:38:55.754551 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9631 00:38:55.761319 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9632 00:38:55.764818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9633 00:38:55.768116 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9634 00:38:55.774595 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9635 00:38:55.777918 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9636 00:38:55.784446 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9637 00:38:55.787793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9638 00:38:55.794524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9639 00:38:55.797585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9640 00:38:55.801164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9641 00:38:55.807823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9642 00:38:55.810828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9643 00:38:55.817473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9644 00:38:55.821399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9645 00:38:55.827797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9646 00:38:55.830899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9647 00:38:55.837766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9648 00:38:55.840803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9649 00:38:55.847459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9650 00:38:55.850895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9651 00:38:55.857455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9652 00:38:55.860539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9653 00:38:55.867216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9654 00:38:55.870473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9655 00:38:55.877100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9656 00:38:55.880351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9657 00:38:55.887180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9658 00:38:55.890555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9659 00:38:55.897134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9660 00:38:55.900589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9661 00:38:55.907413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9662 00:38:55.910511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9663 00:38:55.917399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9664 00:38:55.920506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9665 00:38:55.927149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9666 00:38:55.930524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9667 00:38:55.937030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9668 00:38:55.940215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9669 00:38:55.946809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9670 00:38:55.950191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9671 00:38:55.953497 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9672 00:38:55.956535 INFO: [APUAPC] vio 0
9673 00:38:55.963452 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9674 00:38:55.966758 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9675 00:38:55.970108 INFO: [APUAPC] D0_APC_0: 0x400510
9676 00:38:55.973186 INFO: [APUAPC] D0_APC_1: 0x0
9677 00:38:55.976788 INFO: [APUAPC] D0_APC_2: 0x1540
9678 00:38:55.980016 INFO: [APUAPC] D0_APC_3: 0x0
9679 00:38:55.983118 INFO: [APUAPC] D1_APC_0: 0xffffffff
9680 00:38:55.986668 INFO: [APUAPC] D1_APC_1: 0xffffffff
9681 00:38:55.989853 INFO: [APUAPC] D1_APC_2: 0x3fffff
9682 00:38:55.990288 INFO: [APUAPC] D1_APC_3: 0x0
9683 00:38:55.996486 INFO: [APUAPC] D2_APC_0: 0xffffffff
9684 00:38:55.999850 INFO: [APUAPC] D2_APC_1: 0xffffffff
9685 00:38:56.003073 INFO: [APUAPC] D2_APC_2: 0x3fffff
9686 00:38:56.003488 INFO: [APUAPC] D2_APC_3: 0x0
9687 00:38:56.006299 INFO: [APUAPC] D3_APC_0: 0xffffffff
9688 00:38:56.012920 INFO: [APUAPC] D3_APC_1: 0xffffffff
9689 00:38:56.016319 INFO: [APUAPC] D3_APC_2: 0x3fffff
9690 00:38:56.016718 INFO: [APUAPC] D3_APC_3: 0x0
9691 00:38:56.019396 INFO: [APUAPC] D4_APC_0: 0xffffffff
9692 00:38:56.023055 INFO: [APUAPC] D4_APC_1: 0xffffffff
9693 00:38:56.026182 INFO: [APUAPC] D4_APC_2: 0x3fffff
9694 00:38:56.029565 INFO: [APUAPC] D4_APC_3: 0x0
9695 00:38:56.033019 INFO: [APUAPC] D5_APC_0: 0xffffffff
9696 00:38:56.036002 INFO: [APUAPC] D5_APC_1: 0xffffffff
9697 00:38:56.039521 INFO: [APUAPC] D5_APC_2: 0x3fffff
9698 00:38:56.042713 INFO: [APUAPC] D5_APC_3: 0x0
9699 00:38:56.046166 INFO: [APUAPC] D6_APC_0: 0xffffffff
9700 00:38:56.049662 INFO: [APUAPC] D6_APC_1: 0xffffffff
9701 00:38:56.052621 INFO: [APUAPC] D6_APC_2: 0x3fffff
9702 00:38:56.055806 INFO: [APUAPC] D6_APC_3: 0x0
9703 00:38:56.059216 INFO: [APUAPC] D7_APC_0: 0xffffffff
9704 00:38:56.062899 INFO: [APUAPC] D7_APC_1: 0xffffffff
9705 00:38:56.065936 INFO: [APUAPC] D7_APC_2: 0x3fffff
9706 00:38:56.069258 INFO: [APUAPC] D7_APC_3: 0x0
9707 00:38:56.072638 INFO: [APUAPC] D8_APC_0: 0xffffffff
9708 00:38:56.075966 INFO: [APUAPC] D8_APC_1: 0xffffffff
9709 00:38:56.079212 INFO: [APUAPC] D8_APC_2: 0x3fffff
9710 00:38:56.082486 INFO: [APUAPC] D8_APC_3: 0x0
9711 00:38:56.085733 INFO: [APUAPC] D9_APC_0: 0xffffffff
9712 00:38:56.089128 INFO: [APUAPC] D9_APC_1: 0xffffffff
9713 00:38:56.092208 INFO: [APUAPC] D9_APC_2: 0x3fffff
9714 00:38:56.095483 INFO: [APUAPC] D9_APC_3: 0x0
9715 00:38:56.099023 INFO: [APUAPC] D10_APC_0: 0xffffffff
9716 00:38:56.102306 INFO: [APUAPC] D10_APC_1: 0xffffffff
9717 00:38:56.105453 INFO: [APUAPC] D10_APC_2: 0x3fffff
9718 00:38:56.108940 INFO: [APUAPC] D10_APC_3: 0x0
9719 00:38:56.112090 INFO: [APUAPC] D11_APC_0: 0xffffffff
9720 00:38:56.115652 INFO: [APUAPC] D11_APC_1: 0xffffffff
9721 00:38:56.118983 INFO: [APUAPC] D11_APC_2: 0x3fffff
9722 00:38:56.122009 INFO: [APUAPC] D11_APC_3: 0x0
9723 00:38:56.125665 INFO: [APUAPC] D12_APC_0: 0xffffffff
9724 00:38:56.128713 INFO: [APUAPC] D12_APC_1: 0xffffffff
9725 00:38:56.132131 INFO: [APUAPC] D12_APC_2: 0x3fffff
9726 00:38:56.135455 INFO: [APUAPC] D12_APC_3: 0x0
9727 00:38:56.138923 INFO: [APUAPC] D13_APC_0: 0xffffffff
9728 00:38:56.142200 INFO: [APUAPC] D13_APC_1: 0xffffffff
9729 00:38:56.145341 INFO: [APUAPC] D13_APC_2: 0x3fffff
9730 00:38:56.148753 INFO: [APUAPC] D13_APC_3: 0x0
9731 00:38:56.151943 INFO: [APUAPC] D14_APC_0: 0xffffffff
9732 00:38:56.155446 INFO: [APUAPC] D14_APC_1: 0xffffffff
9733 00:38:56.159209 INFO: [APUAPC] D14_APC_2: 0x3fffff
9734 00:38:56.161800 INFO: [APUAPC] D14_APC_3: 0x0
9735 00:38:56.165142 INFO: [APUAPC] D15_APC_0: 0xffffffff
9736 00:38:56.168502 INFO: [APUAPC] D15_APC_1: 0xffffffff
9737 00:38:56.171801 INFO: [APUAPC] D15_APC_2: 0x3fffff
9738 00:38:56.175449 INFO: [APUAPC] D15_APC_3: 0x0
9739 00:38:56.178950 INFO: [APUAPC] APC_CON: 0x4
9740 00:38:56.181778 INFO: [NOCDAPC] D0_APC_0: 0x0
9741 00:38:56.185129 INFO: [NOCDAPC] D0_APC_1: 0x0
9742 00:38:56.188336 INFO: [NOCDAPC] D1_APC_0: 0x0
9743 00:38:56.191805 INFO: [NOCDAPC] D1_APC_1: 0xfff
9744 00:38:56.192261 INFO: [NOCDAPC] D2_APC_0: 0x0
9745 00:38:56.195073 INFO: [NOCDAPC] D2_APC_1: 0xfff
9746 00:38:56.198360 INFO: [NOCDAPC] D3_APC_0: 0x0
9747 00:38:56.201555 INFO: [NOCDAPC] D3_APC_1: 0xfff
9748 00:38:56.204895 INFO: [NOCDAPC] D4_APC_0: 0x0
9749 00:38:56.208226 INFO: [NOCDAPC] D4_APC_1: 0xfff
9750 00:38:56.211465 INFO: [NOCDAPC] D5_APC_0: 0x0
9751 00:38:56.214783 INFO: [NOCDAPC] D5_APC_1: 0xfff
9752 00:38:56.218012 INFO: [NOCDAPC] D6_APC_0: 0x0
9753 00:38:56.221557 INFO: [NOCDAPC] D6_APC_1: 0xfff
9754 00:38:56.224924 INFO: [NOCDAPC] D7_APC_0: 0x0
9755 00:38:56.225364 INFO: [NOCDAPC] D7_APC_1: 0xfff
9756 00:38:56.228436 INFO: [NOCDAPC] D8_APC_0: 0x0
9757 00:38:56.231538 INFO: [NOCDAPC] D8_APC_1: 0xfff
9758 00:38:56.234964 INFO: [NOCDAPC] D9_APC_0: 0x0
9759 00:38:56.238021 INFO: [NOCDAPC] D9_APC_1: 0xfff
9760 00:38:56.241443 INFO: [NOCDAPC] D10_APC_0: 0x0
9761 00:38:56.244848 INFO: [NOCDAPC] D10_APC_1: 0xfff
9762 00:38:56.248393 INFO: [NOCDAPC] D11_APC_0: 0x0
9763 00:38:56.251582 INFO: [NOCDAPC] D11_APC_1: 0xfff
9764 00:38:56.254673 INFO: [NOCDAPC] D12_APC_0: 0x0
9765 00:38:56.258137 INFO: [NOCDAPC] D12_APC_1: 0xfff
9766 00:38:56.261598 INFO: [NOCDAPC] D13_APC_0: 0x0
9767 00:38:56.264923 INFO: [NOCDAPC] D13_APC_1: 0xfff
9768 00:38:56.268035 INFO: [NOCDAPC] D14_APC_0: 0x0
9769 00:38:56.268426 INFO: [NOCDAPC] D14_APC_1: 0xfff
9770 00:38:56.271162 INFO: [NOCDAPC] D15_APC_0: 0x0
9771 00:38:56.274902 INFO: [NOCDAPC] D15_APC_1: 0xfff
9772 00:38:56.277753 INFO: [NOCDAPC] APC_CON: 0x4
9773 00:38:56.281233 INFO: [APUAPC] set_apusys_apc done
9774 00:38:56.284727 INFO: [DEVAPC] devapc_init done
9775 00:38:56.287904 INFO: GICv3 without legacy support detected.
9776 00:38:56.294456 INFO: ARM GICv3 driver initialized in EL3
9777 00:38:56.297532 INFO: Maximum SPI INTID supported: 639
9778 00:38:56.300922 INFO: BL31: Initializing runtime services
9779 00:38:56.307993 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9780 00:38:56.310903 INFO: SPM: enable CPC mode
9781 00:38:56.314466 INFO: mcdi ready for mcusys-off-idle and system suspend
9782 00:38:56.320909 INFO: BL31: Preparing for EL3 exit to normal world
9783 00:38:56.324497 INFO: Entry point address = 0x80000000
9784 00:38:56.324929 INFO: SPSR = 0x8
9785 00:38:56.330739
9786 00:38:56.331227
9787 00:38:56.331695
9788 00:38:56.333782 Starting depthcharge on Spherion...
9789 00:38:56.334188
9790 00:38:56.334508 Wipe memory regions:
9791 00:38:56.334801
9792 00:38:56.337115 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9793 00:38:56.337656 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9794 00:38:56.338073 Setting prompt string to ['asurada:']
9795 00:38:56.338469 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9796 00:38:56.339137 [0x00000040000000, 0x00000054600000)
9797 00:38:56.459460
9798 00:38:56.459569 [0x00000054660000, 0x00000080000000)
9799 00:38:56.720010
9800 00:38:56.720142 [0x000000821a7280, 0x000000ffe64000)
9801 00:38:57.464579
9802 00:38:57.464717 [0x00000100000000, 0x00000140000000)
9803 00:38:57.845558
9804 00:38:57.849092 Initializing XHCI USB controller at 0x11200000.
9805 00:38:58.887072
9806 00:38:58.890258 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9807 00:38:58.890689
9808 00:38:58.891045
9809 00:38:58.891843 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9811 00:38:58.992995 asurada: tftpboot 192.168.201.1 14173474/tftp-deploy-ty0tk77m/kernel/image.itb 14173474/tftp-deploy-ty0tk77m/kernel/cmdline
9812 00:38:58.994840 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9813 00:38:58.995346 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9814 00:38:58.999486 tftpboot 192.168.201.1 14173474/tftp-deploy-ty0tk77m/kernel/image.ittp-deploy-ty0tk77m/kernel/cmdline
9815 00:38:58.999945
9816 00:38:59.000298 Waiting for link
9817 00:38:59.160077
9818 00:38:59.160640 R8152: Initializing
9819 00:38:59.161046
9820 00:38:59.163610 Version 9 (ocp_data = 6010)
9821 00:38:59.164046
9822 00:38:59.166641 R8152: Done initializing
9823 00:38:59.167024
9824 00:38:59.167351 Adding net device
9825 00:39:01.048236
9826 00:39:01.048379 done.
9827 00:39:01.048446
9828 00:39:01.048512 MAC: 00:e0:4c:68:03:bd
9829 00:39:01.048571
9830 00:39:01.051480 Sending DHCP discover... done.
9831 00:39:01.051585
9832 00:39:11.395894 Waiting for reply... R8152: Bulk read error 0xffffffbf
9833 00:39:11.396530
9834 00:39:11.399542 Receive failed.
9835 00:39:11.399994
9836 00:39:11.400346 done.
9837 00:39:11.400699
9838 00:39:11.402447 Sending DHCP request... done.
9839 00:39:11.402896
9840 00:39:11.405723 Waiting for reply... done.
9841 00:39:11.406171
9842 00:39:11.408949 My ip is 192.168.201.16
9843 00:39:11.409431
9844 00:39:11.412735 The DHCP server ip is 192.168.201.1
9845 00:39:11.413280
9846 00:39:11.415831 TFTP server IP predefined by user: 192.168.201.1
9847 00:39:11.416378
9848 00:39:11.422185 Bootfile predefined by user: 14173474/tftp-deploy-ty0tk77m/kernel/image.itb
9849 00:39:11.422635
9850 00:39:11.425687 Sending tftp read request... done.
9851 00:39:11.426151
9852 00:39:11.433405 Waiting for the transfer...
9853 00:39:11.433947
9854 00:39:11.711448 00000000 ################################################################
9855 00:39:11.711578
9856 00:39:11.962047 00080000 ################################################################
9857 00:39:11.962178
9858 00:39:12.225316 00100000 ################################################################
9859 00:39:12.225445
9860 00:39:12.474800 00180000 ################################################################
9861 00:39:12.474929
9862 00:39:12.743883 00200000 ################################################################
9863 00:39:12.744018
9864 00:39:13.025237 00280000 ################################################################
9865 00:39:13.025384
9866 00:39:13.319440 00300000 ################################################################
9867 00:39:13.319565
9868 00:39:13.603423 00380000 ################################################################
9869 00:39:13.603551
9870 00:39:13.889624 00400000 ################################################################
9871 00:39:13.889753
9872 00:39:14.177242 00480000 ################################################################
9873 00:39:14.177419
9874 00:39:14.460120 00500000 ################################################################
9875 00:39:14.460250
9876 00:39:14.711116 00580000 ################################################################
9877 00:39:14.711253
9878 00:39:14.961541 00600000 ################################################################
9879 00:39:14.961673
9880 00:39:15.211986 00680000 ################################################################
9881 00:39:15.212117
9882 00:39:15.489442 00700000 ################################################################
9883 00:39:15.489570
9884 00:39:15.773883 00780000 ################################################################
9885 00:39:15.774032
9886 00:39:16.109122 00800000 ################################################################
9887 00:39:16.109260
9888 00:39:16.393300 00880000 ################################################################
9889 00:39:16.393445
9890 00:39:16.683075 00900000 ################################################################
9891 00:39:16.683208
9892 00:39:16.972836 00980000 ################################################################
9893 00:39:16.972979
9894 00:39:17.257206 00a00000 ################################################################
9895 00:39:17.257378
9896 00:39:17.543724 00a80000 ################################################################
9897 00:39:17.543989
9898 00:39:17.829391 00b00000 ################################################################
9899 00:39:17.829515
9900 00:39:18.104155 00b80000 ################################################################
9901 00:39:18.104296
9902 00:39:18.353311 00c00000 ################################################################
9903 00:39:18.353451
9904 00:39:18.612409 00c80000 ################################################################
9905 00:39:18.612536
9906 00:39:18.862925 00d00000 ################################################################
9907 00:39:18.863065
9908 00:39:19.115949 00d80000 ################################################################
9909 00:39:19.116080
9910 00:39:19.378434 00e00000 ################################################################
9911 00:39:19.378602
9912 00:39:19.640431 00e80000 ################################################################
9913 00:39:19.640592
9914 00:39:19.905068 00f00000 ################################################################
9915 00:39:19.905202
9916 00:39:20.173322 00f80000 ################################################################
9917 00:39:20.173472
9918 00:39:20.457518 01000000 ################################################################
9919 00:39:20.457765
9920 00:39:20.717306 01080000 ################################################################
9921 00:39:20.717463
9922 00:39:20.984716 01100000 ################################################################
9923 00:39:20.984860
9924 00:39:21.234284 01180000 ################################################################
9925 00:39:21.234420
9926 00:39:21.483424 01200000 ################################################################
9927 00:39:21.483563
9928 00:39:21.736315 01280000 ################################################################
9929 00:39:21.736443
9930 00:39:21.987376 01300000 ################################################################
9931 00:39:21.987530
9932 00:39:22.241123 01380000 ################################################################
9933 00:39:22.241252
9934 00:39:22.498628 01400000 ################################################################
9935 00:39:22.498784
9936 00:39:22.773583 01480000 ################################################################
9937 00:39:22.773718
9938 00:39:23.030648 01500000 ################################################################
9939 00:39:23.030775
9940 00:39:23.281606 01580000 ################################################################
9941 00:39:23.281731
9942 00:39:23.595108 01600000 ################################################################
9943 00:39:23.595245
9944 00:39:23.934565 01680000 ################################################################
9945 00:39:23.934800
9946 00:39:24.263309 01700000 ################################################################
9947 00:39:24.263458
9948 00:39:24.577882 01780000 ################################################################
9949 00:39:24.578040
9950 00:39:24.885778 01800000 ################################################################
9951 00:39:24.885914
9952 00:39:25.135891 01880000 ################################################################
9953 00:39:25.136029
9954 00:39:25.404004 01900000 ################################################################
9955 00:39:25.404137
9956 00:39:25.673093 01980000 ################################################################
9957 00:39:25.673253
9958 00:39:25.942089 01a00000 ################################################################
9959 00:39:25.942221
9960 00:39:26.204708 01a80000 ################################################################
9961 00:39:26.204839
9962 00:39:26.476244 01b00000 ################################################################
9963 00:39:26.476372
9964 00:39:26.762941 01b80000 ################################################################
9965 00:39:26.763074
9966 00:39:27.045089 01c00000 ################################################################
9967 00:39:27.045258
9968 00:39:27.312444 01c80000 ################################################################
9969 00:39:27.312587
9970 00:39:27.595781 01d00000 ################################################################
9971 00:39:27.595921
9972 00:39:27.861337 01d80000 ################################################################
9973 00:39:27.861468
9974 00:39:28.055773 01e00000 ############################################### done.
9975 00:39:28.055910
9976 00:39:28.059002 The bootfile was 31834594 bytes long.
9977 00:39:28.059089
9978 00:39:28.062615 Sending tftp read request... done.
9979 00:39:28.062701
9980 00:39:28.062771 Waiting for the transfer...
9981 00:39:28.065481
9982 00:39:28.065576 00000000 # done.
9983 00:39:28.065652
9984 00:39:28.072210 Command line loaded dynamically from TFTP file: 14173474/tftp-deploy-ty0tk77m/kernel/cmdline
9985 00:39:28.072311
9986 00:39:28.095530 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9987 00:39:28.095799
9988 00:39:28.095946 Loading FIT.
9989 00:39:28.096080
9990 00:39:28.099567 Image ramdisk-1 has 18725384 bytes.
9991 00:39:28.099853
9992 00:39:28.102364 Image fdt-1 has 47258 bytes.
9993 00:39:28.102648
9994 00:39:28.105798 Image kernel-1 has 13059919 bytes.
9995 00:39:28.106125
9996 00:39:28.115632 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
9997 00:39:28.116040
9998 00:39:28.132524 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9999 00:39:28.133115
10000 00:39:28.138913 Choosing best match conf-1 for compat google,spherion.
10001 00:39:28.139471
10002 00:39:28.146247 Connected to device vid:did:rid of 1ae0:0028:00
10003 00:39:28.153360
10004 00:39:28.156099 tpm_get_response: command 0x17b, return code 0x0
10005 00:39:28.156560
10006 00:39:28.162900 ec_init: CrosEC protocol v3 supported (256, 248)
10007 00:39:28.163473
10008 00:39:28.166164 tpm_cleanup: add release locality here.
10009 00:39:28.166657
10010 00:39:28.169660 Shutting down all USB controllers.
10011 00:39:28.170116
10012 00:39:28.172941 Removing current net device
10013 00:39:28.173603
10014 00:39:28.176147 Exiting depthcharge with code 4 at timestamp: 60121331
10015 00:39:28.176605
10016 00:39:28.179215 LZMA decompressing kernel-1 to 0x821a6718
10017 00:39:28.182663
10018 00:39:28.185978 LZMA decompressing kernel-1 to 0x40000000
10019 00:39:29.793786
10020 00:39:29.794263 jumping to kernel
10021 00:39:29.796291 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10022 00:39:29.796763 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10023 00:39:29.797127 Setting prompt string to ['Linux version [0-9]']
10024 00:39:29.797513 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 00:39:29.797852 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10026 00:39:29.844240
10027 00:39:29.847522 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10028 00:39:29.851415 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10029 00:39:29.851882 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10030 00:39:29.852233 Setting prompt string to []
10031 00:39:29.852600 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10032 00:39:29.852946 Using line separator: #'\n'#
10033 00:39:29.853241 No login prompt set.
10034 00:39:29.853604 Parsing kernel messages
10035 00:39:29.853906 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10036 00:39:29.854425 [login-action] Waiting for messages, (timeout 00:03:53)
10037 00:39:29.854763 Waiting using forced prompt support (timeout 00:01:56)
10038 00:39:29.870735 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10039 00:39:29.873758 [ 0.000000] random: crng init done
10040 00:39:29.880721 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10041 00:39:29.883683 [ 0.000000] efi: UEFI not found.
10042 00:39:29.890562 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10043 00:39:29.900263 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10044 00:39:29.910011 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10045 00:39:29.917072 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10046 00:39:29.923917 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10047 00:39:29.929469 [ 0.000000] printk: bootconsole [mtk8250] enabled
10048 00:39:29.936308 [ 0.000000] NUMA: No NUMA configuration found
10049 00:39:29.943089 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10050 00:39:29.949658 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10051 00:39:29.950072 [ 0.000000] Zone ranges:
10052 00:39:29.955848 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10053 00:39:29.959032 [ 0.000000] DMA32 empty
10054 00:39:29.965553 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10055 00:39:29.969056 [ 0.000000] Movable zone start for each node
10056 00:39:29.972268 [ 0.000000] Early memory node ranges
10057 00:39:29.978773 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10058 00:39:29.985549 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10059 00:39:29.992216 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10060 00:39:29.999035 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10061 00:39:30.005329 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10062 00:39:30.012084 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10063 00:39:30.043241 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10064 00:39:30.049656 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10065 00:39:30.056180 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10066 00:39:30.059646 [ 0.000000] psci: probing for conduit method from DT.
10067 00:39:30.066074 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10068 00:39:30.070079 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10069 00:39:30.076660 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10070 00:39:30.079774 [ 0.000000] psci: SMC Calling Convention v1.2
10071 00:39:30.086254 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10072 00:39:30.089802 [ 0.000000] Detected VIPT I-cache on CPU0
10073 00:39:30.096308 [ 0.000000] CPU features: detected: GIC system register CPU interface
10074 00:39:30.102661 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10075 00:39:30.109561 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10076 00:39:30.115985 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10077 00:39:30.125632 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10078 00:39:30.132290 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10079 00:39:30.135983 [ 0.000000] alternatives: applying boot alternatives
10080 00:39:30.142208 [ 0.000000] Fallback order for Node 0: 0
10081 00:39:30.148833 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10082 00:39:30.152286 [ 0.000000] Policy zone: Normal
10083 00:39:30.175328 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10084 00:39:30.185077 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10085 00:39:30.195037 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10086 00:39:30.204825 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10087 00:39:30.211880 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10088 00:39:30.214969 <6>[ 0.000000] software IO TLB: area num 8.
10089 00:39:30.270371 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10090 00:39:30.351281 <6>[ 0.000000] Memory: 3831492K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 326972K reserved, 32768K cma-reserved)
10091 00:39:30.357950 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10092 00:39:30.364377 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10093 00:39:30.367558 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10094 00:39:30.374316 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10095 00:39:30.380870 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10096 00:39:30.384221 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10097 00:39:30.393945 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10098 00:39:30.400627 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10099 00:39:30.407069 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10100 00:39:30.413776 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10101 00:39:30.417095 <6>[ 0.000000] GICv3: 608 SPIs implemented
10102 00:39:30.420355 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10103 00:39:30.426856 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10104 00:39:30.430058 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10105 00:39:30.436800 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10106 00:39:30.449721 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10107 00:39:30.462878 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10108 00:39:30.469422 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10109 00:39:30.477499 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10110 00:39:30.490547 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10111 00:39:30.497358 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10112 00:39:30.504057 <6>[ 0.009176] Console: colour dummy device 80x25
10113 00:39:30.513911 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10114 00:39:30.520233 <6>[ 0.024343] pid_max: default: 32768 minimum: 301
10115 00:39:30.523744 <6>[ 0.029244] LSM: Security Framework initializing
10116 00:39:30.530371 <6>[ 0.034156] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10117 00:39:30.540513 <6>[ 0.041763] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10118 00:39:30.547345 <6>[ 0.050984] cblist_init_generic: Setting adjustable number of callback queues.
10119 00:39:30.553664 <6>[ 0.058428] cblist_init_generic: Setting shift to 3 and lim to 1.
10120 00:39:30.563171 <6>[ 0.064804] cblist_init_generic: Setting adjustable number of callback queues.
10121 00:39:30.569846 <6>[ 0.072231] cblist_init_generic: Setting shift to 3 and lim to 1.
10122 00:39:30.573252 <6>[ 0.078665] rcu: Hierarchical SRCU implementation.
10123 00:39:30.579811 <6>[ 0.078667] rcu: Max phase no-delay instances is 1000.
10124 00:39:30.586396 <6>[ 0.078690] printk: bootconsole [mtk8250] printing thread started
10125 00:39:30.592954 <6>[ 0.097033] EFI services will not be available.
10126 00:39:30.596716 <6>[ 0.097231] smp: Bringing up secondary CPUs ...
10127 00:39:30.599506 <6>[ 0.097535] Detected VIPT I-cache on CPU1
10128 00:39:30.609936 <6>[ 0.097600] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10129 00:39:30.616319 <6>[ 0.097632] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10130 00:39:30.625082 <6>[ 0.125480] Detected VIPT I-cache on CPU2
10131 00:39:30.631747 <6>[ 0.125532] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10132 00:39:30.638354 <6>[ 0.125548] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10133 00:39:30.644986 <6>[ 0.125801] Detected VIPT I-cache on CPU3
10134 00:39:30.651446 <6>[ 0.125851] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10135 00:39:30.658047 <6>[ 0.125866] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10136 00:39:30.661804 <6>[ 0.126175] CPU features: detected: Spectre-v4
10137 00:39:30.668025 <6>[ 0.126181] CPU features: detected: Spectre-BHB
10138 00:39:30.671277 <6>[ 0.126186] Detected PIPT I-cache on CPU4
10139 00:39:30.677638 <6>[ 0.126245] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10140 00:39:30.684145 <6>[ 0.126260] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10141 00:39:30.690766 <6>[ 0.126549] Detected PIPT I-cache on CPU5
10142 00:39:30.697539 <6>[ 0.126610] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10143 00:39:30.703902 <6>[ 0.126625] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10144 00:39:30.707446 <6>[ 0.126894] Detected PIPT I-cache on CPU6
10145 00:39:30.713795 <6>[ 0.126955] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10146 00:39:30.725390 <6>[ 0.126971] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10147 00:39:30.728489 <6>[ 0.127262] Detected PIPT I-cache on CPU7
10148 00:39:30.734815 <6>[ 0.127327] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10149 00:39:30.741434 <6>[ 0.127342] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10150 00:39:30.745065 <6>[ 0.127388] smp: Brought up 1 node, 8 CPUs
10151 00:39:30.751432 <6>[ 0.127392] SMP: Total of 8 processors activated.
10152 00:39:30.755032 <6>[ 0.127395] CPU features: detected: 32-bit EL0 Support
10153 00:39:30.764862 <6>[ 0.127397] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10154 00:39:30.771429 <6>[ 0.127400] CPU features: detected: Common not Private translations
10155 00:39:30.777846 <6>[ 0.127402] CPU features: detected: CRC32 instructions
10156 00:39:30.784453 <6>[ 0.127404] CPU features: detected: RCpc load-acquire (LDAPR)
10157 00:39:30.787795 <6>[ 0.127406] CPU features: detected: LSE atomic instructions
10158 00:39:30.794422 <6>[ 0.127407] CPU features: detected: Privileged Access Never
10159 00:39:30.801075 <6>[ 0.127409] CPU features: detected: RAS Extension Support
10160 00:39:30.807799 <6>[ 0.127412] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10161 00:39:30.811302 <6>[ 0.127477] CPU: All CPU(s) started at EL2
10162 00:39:30.817825 <6>[ 0.127479] alternatives: applying system-wide alternatives
10163 00:39:30.820624 <6>[ 0.139889] devtmpfs: initialized
10164 00:39:30.846648 <6>[ 0.351559] printk: console [ttyS0] prin<ting thread started
10165 00:39:30.853149 6>[<6>[ 0.351600] printk: console [ttyS0] enabled
10166 00:39:30.862831 0.145399] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10167 00:39:30.870094 <6>[ 0.351606] printk: bootconsole [mtk8250] disabled
10168 00:39:30.877030 <6>[ 0.371855] printk: bootconsole [mtk8250] printing thread stopped
10169 00:39:30.880450 <6>[ 0.373150] SuperH (H)SCI(F) driver initialized
10170 00:39:30.886631 <6>[ 0.373629] msm_serial: driver initialized
10171 00:39:30.893387 <6>[ 0.378243] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10172 00:39:30.903661 <6>[ 0.378278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10173 00:39:30.909920 <6>[ 0.378309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10174 00:39:30.924122 <6>[ 0.378337] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10175 00:39:30.930544 <6>[ 0.378359] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10176 00:39:30.942624 <6>[ 0.378386] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10177 00:39:30.947389 <6>[ 0.378415] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10178 00:39:30.961915 <6>[ 0.378532] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10179 00:39:30.962509 <6>[ 0.378561] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10180 00:39:30.966900 <6>[ 0.390321] loop: module loaded
10181 00:39:30.971570 <6>[ 0.392880] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10182 00:39:30.980462 <4>[ 0.409739] mtk-pmic-keys: Failed to locate of_node [id: -1]
10183 00:39:30.983815 <6>[ 0.410601] megasas: 07.719.03.00-rc1
10184 00:39:30.987540 <6>[ 0.422828] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10185 00:39:30.993671 <6>[ 0.426815] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10186 00:39:31.000050 <6>[ 0.439006] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10187 00:39:31.014068 <6>[ 0.490842] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10188 00:39:31.562399 <6>[ 1.064778] Freeing initrd memory: 18280K
10189 00:39:31.569772 <6>[ 1.071941] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10190 00:39:31.576656 <6>[ 1.076357] tun: Universal TUN/TAP device driver, 1.6
10191 00:39:31.579639 <6>[ 1.077089] thunder_xcv, ver 1.0
10192 00:39:31.583174 <6>[ 1.077106] thunder_bgx, ver 1.0
10193 00:39:31.586588 <6>[ 1.077119] nicpf, ver 1.0
10194 00:39:31.592822 <6>[ 1.078150] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10195 00:39:31.599465 <6>[ 1.078154] hns3: Copyright (c) 2017 Huawei Corporation.
10196 00:39:31.602806 <6>[ 1.078177] hclge is initializing
10197 00:39:31.609617 <6>[ 1.078190] e1000: Intel(R) PRO/1000 Network Driver
10198 00:39:31.613020 <6>[ 1.078191] e1000: Copyright (c) 1999-2006 Intel Corporation.
10199 00:39:31.620720 <6>[ 1.078207] e1000e: Intel(R) PRO/1000 Network Driver
10200 00:39:31.624511 <6>[ 1.078208] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10201 00:39:31.631327 <6>[ 1.078226] igb: Intel(R) Gigabit Ethernet Network Driver
10202 00:39:31.637913 <6>[ 1.078228] igb: Copyright (c) 2007-2014 Intel Corporation.
10203 00:39:31.644637 <6>[ 1.078245] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10204 00:39:31.652334 <6>[ 1.078247] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10205 00:39:31.655455 <6>[ 1.078534] sky2: driver version 1.30
10206 00:39:31.661848 <6>[ 1.079542] usbcore: registered new device driver r8152-cfgselector
10207 00:39:31.665066 <6>[ 1.079558] usbcore: registered new interface driver r8152
10208 00:39:31.671772 <6>[ 1.079629] VFIO - User Level meta-driver version: 0.3
10209 00:39:31.678276 <6>[ 1.082445] usbcore: registered new interface driver usb-storage
10210 00:39:31.684335 <6>[ 1.082622] usbcore: registered new device driver onboard-usb-hub
10211 00:39:31.688090 <6>[ 1.085370] mt6397-rtc mt6359-rtc: registered as rtc0
10212 00:39:31.698312 <6>[ 1.085518] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T00:39:31 UTC (1717547971)
10213 00:39:31.701304 <6>[ 1.086120] i2c_dev: i2c /dev entries driver
10214 00:39:31.711465 <6>[ 1.093098] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10215 00:39:31.718051 <4>[ 1.093811] cpu cpu0: supply cpu not found, using dummy regulator
10216 00:39:31.724659 <4>[ 1.093886] cpu cpu1: supply cpu not found, using dummy regulator
10217 00:39:31.728080 <4>[ 1.093957] cpu cpu2: supply cpu not found, using dummy regulator
10218 00:39:31.735016 <4>[ 1.094011] cpu cpu3: supply cpu not found, using dummy regulator
10219 00:39:31.741461 <4>[ 1.094060] cpu cpu4: supply cpu not found, using dummy regulator
10220 00:39:31.748294 <4>[ 1.094110] cpu cpu5: supply cpu not found, using dummy regulator
10221 00:39:31.754810 <4>[ 1.094159] cpu cpu6: supply cpu not found, using dummy regulator
10222 00:39:31.761517 <4>[ 1.094207] cpu cpu7: supply cpu not found, using dummy regulator
10223 00:39:31.764460 <6>[ 1.109486] cpu cpu0: EM: created perf domain
10224 00:39:31.770965 <6>[ 1.109779] cpu cpu4: EM: created perf domain
10225 00:39:31.777639 <6>[ 1.113605] sdhci: Secure Digital Host Controller Interface driver
10226 00:39:31.780821 <6>[ 1.113606] sdhci: Copyright(c) Pierre Ossman
10227 00:39:31.787715 <6>[ 1.113934] Synopsys Designware Multimedia Card Interface Driver
10228 00:39:31.794382 <6>[ 1.114297] sdhci-pltfm: SDHCI platform and OF driver helper
10229 00:39:31.800925 <6>[ 1.118617] ledtrig-cpu: registered to indicate activity on CPUs
10230 00:39:31.804023 <6>[ 1.119286] mmc0: CQHCI version 5.10
10231 00:39:31.810747 <6>[ 1.119293] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10232 00:39:31.817252 <6>[ 1.119566] usbcore: registered new interface driver usbhid
10233 00:39:31.820648 <6>[ 1.119567] usbhid: USB HID core driver
10234 00:39:31.827077 <6>[ 1.119680] spi_master spi0: will run message pump with realtime priority
10235 00:39:31.841232 <6>[ 1.154196] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10236 00:39:31.854614 <6>[ 1.156600] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10237 00:39:31.860999 <6>[ 1.157576] cros-ec-spi spi0.0: Chrome EC device registered
10238 00:39:31.867594 <6>[ 1.176554] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10239 00:39:31.874466 <6>[ 1.178892] NET: Registered PF_PACKET protocol family
10240 00:39:31.877779 <6>[ 1.178998] 9pnet: Installing 9P2000 support
10241 00:39:31.884399 <5>[ 1.179040] Key type dns_resolver registered
10242 00:39:31.887736 <6>[ 1.179359] registered taskstats version 1
10243 00:39:31.891611 <5>[ 1.179377] Loading compiled-in X.509 certificates
10244 00:39:31.904269 <4>[ 1.201907] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10245 00:39:31.914308 <4>[ 1.202075] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10246 00:39:31.917365 <3>[ 1.209072] mtk-msdc 11f60000.mmc: phase error: [map:0]
10247 00:39:31.924005 <3>[ 1.209081] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10248 00:39:31.930646 <3>[ 1.209084] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10249 00:39:31.937331 <3>[ 1.209091] mmc0: error -5 whilst initialising MMC card
10250 00:39:31.944127 <6>[ 1.212444] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10251 00:39:31.947617 <6>[ 1.213034] xhci-mtk 11200000.usb: xHCI Host Controller
10252 00:39:31.957321 <6>[ 1.213049] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10253 00:39:31.963753 <6>[ 1.213250] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10254 00:39:31.969917 <6>[ 1.213289] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10255 00:39:31.976540 <6>[ 1.213351] xhci-mtk 11200000.usb: xHCI Host Controller
10256 00:39:31.983164 <6>[ 1.213354] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10257 00:39:31.990077 <6>[ 1.213360] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10258 00:39:31.996148 <6>[ 1.213672] hub 1-0:1.0: USB hub found
10259 00:39:31.999705 <6>[ 1.213699] hub 1-0:1.0: 1 port detected
10260 00:39:32.005968 <6>[ 1.213891] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10261 00:39:32.012836 <6>[ 1.214228] hub 2-0:1.0: USB hub found
10262 00:39:32.016425 <6>[ 1.214244] hub 2-0:1.0: 1 port detected
10263 00:39:32.019940 <6>[ 1.217158] mtk-msdc 11f70000.mmc: Got CD GPIO
10264 00:39:32.029334 <6>[ 1.224512] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10265 00:39:32.036176 <6>[ 1.224518] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10266 00:39:32.046013 <4>[ 1.224596] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10267 00:39:32.052941 <6>[ 1.225090] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10268 00:39:32.062569 <6>[ 1.225092] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10269 00:39:32.069073 <6>[ 1.225369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10270 00:39:32.079056 <6>[ 1.225378] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10271 00:39:32.085769 <6>[ 1.225380] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10272 00:39:32.095482 <6>[ 1.225383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10273 00:39:32.102112 <6>[ 1.226314] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10274 00:39:32.111982 <6>[ 1.226323] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10275 00:39:32.118714 <6>[ 1.226325] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10276 00:39:32.128866 <6>[ 1.226328] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10277 00:39:32.135358 <6>[ 1.226330] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10278 00:39:32.145073 <6>[ 1.226333] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10279 00:39:32.151752 <6>[ 1.226335] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10280 00:39:32.161539 <6>[ 1.226338] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10281 00:39:32.168267 <6>[ 1.226340] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10282 00:39:32.178524 <6>[ 1.226342] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10283 00:39:32.184848 <6>[ 1.226345] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10284 00:39:32.194677 <6>[ 1.226347] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10285 00:39:32.201313 <6>[ 1.226350] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10286 00:39:32.211265 <6>[ 1.226353] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10287 00:39:32.221084 <6>[ 1.226356] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10288 00:39:32.224231 <6>[ 1.226568] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10289 00:39:32.231004 <6>[ 1.227171] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10290 00:39:32.237598 <6>[ 1.227609] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10291 00:39:32.243731 <6>[ 1.227923] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10292 00:39:32.250694 <6>[ 1.228206] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10293 00:39:32.260064 <6>[ 1.228372] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10294 00:39:32.270081 <6>[ 1.228384] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10295 00:39:32.280413 <6>[ 1.228387] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10296 00:39:32.290132 <6>[ 1.228391] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10297 00:39:32.300224 <6>[ 1.228394] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10298 00:39:32.306416 <6>[ 1.228397] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10299 00:39:32.316322 <6>[ 1.228401] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10300 00:39:32.326224 <6>[ 1.228404] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10301 00:39:32.335971 <6>[ 1.228406] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10302 00:39:32.346066 <6>[ 1.228410] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10303 00:39:32.356207 <6>[ 1.228413] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10304 00:39:32.362724 <6>[ 1.229308] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10305 00:39:32.369253 <6>[ 1.251972] Trying to probe devices needed for running init ...
10306 00:39:32.376176 <3>[ 1.310488] mtk-msdc 11f60000.mmc: phase error: [map:0]
10307 00:39:32.382463 <3>[ 1.310497] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10308 00:39:32.389438 <3>[ 1.310500] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10309 00:39:32.392251 <3>[ 1.310507] mmc0: error -5 whilst initialising MMC card
10310 00:39:32.398893 <6>[ 1.595793] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10311 00:39:32.405340 <6>[ 1.622472] hub 2-1:1.0: USB hub found
10312 00:39:32.408886 <6>[ 1.622878] hub 2-1:1.0: 3 ports detected
10313 00:39:32.412017 <6>[ 1.624910] hub 2-1:1.0: USB hub found
10314 00:39:32.415607 <6>[ 1.625243] hub 2-1:1.0: 3 ports detected
10315 00:39:32.422018 <6>[ 1.649469] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10316 00:39:32.428696 <6>[ 1.654975] mmc0: Command Queue Engine enabled
10317 00:39:32.435093 <6>[ 1.654992] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10318 00:39:32.438701 <6>[ 1.655797] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10319 00:39:32.445146 <6>[ 1.659520] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10320 00:39:32.448569 <6>[ 1.660642] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10321 00:39:32.455098 <6>[ 1.661415] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10322 00:39:32.461873 <6>[ 1.662113] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10323 00:39:32.468415 <6>[ 1.743512] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10324 00:39:32.471432 <6>[ 1.896508] hub 1-1:1.0: USB hub found
10325 00:39:32.478228 <6>[ 1.896883] hub 1-1:1.0: 4 ports detected
10326 00:39:32.481536 <6>[ 1.900813] hub 1-1:1.0: USB hub found
10327 00:39:32.484804 <6>[ 1.901187] hub 1-1:1.0: 4 ports detected
10328 00:39:32.491331 <6>[ 1.979754] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10329 00:39:32.585001 <6>[ 2.084241] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10330 00:39:32.609169 <4>[ 2.108643] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10331 00:39:32.618748 <4>[ 2.108658] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10332 00:39:32.641782 <6>[ 2.145466] r8152 2-1.3:1.0 eth0: v1.12.13
10333 00:39:32.713277 <6>[ 2.211726] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10334 00:39:32.834170 <6>[ 2.338801] hub 1-1.4:1.0: USB hub found
10335 00:39:32.837428 <6>[ 2.339119] hub 1-1.4:1.0: 2 ports detected
10336 00:39:32.840596 <6>[ 2.342145] hub 1-1.4:1.0: USB hub found
10337 00:39:32.847235 <6>[ 2.342509] hub 1-1.4:1.0: 2 ports detected
10338 00:39:33.133134 <6>[ 2.631693] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10339 00:39:33.317378 <6>[ 2.815625] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10340 00:39:34.241227 <6>[ 3.745875] r8152 2-1.3:1.0 eth0: carrier on
10341 00:39:36.905519 <5>[ 3.771727] Sending DHCP requests .., OK
10342 00:39:36.912185 <6>[ 6.407571] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10343 00:39:36.915568 <6>[ 6.407585] IP-Config: Complete:
10344 00:39:36.928843 <6>[ 6.407586] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10345 00:39:36.935380 <6>[ 6.407593] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10346 00:39:36.942181 <6>[ 6.407596] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10347 00:39:36.948482 <6>[ 6.407600] nameserver0=192.168.201.1
10348 00:39:36.951849 Loading, please <6>[ 6.407814] clk: Disabling unused clocks
10349 00:39:36.955501 <6>[ 6.408857] ALSA device list:
10350 00:39:36.962141 <6>[ 6.408871] No soundcards found.
10351 00:39:36.965230 <6>[ 6.413066] Freeing unused kernel memory: 8512K
10352 00:39:36.968670 <6>[ 6.413259] Run /init as init process
10353 00:39:36.969124 wait...
10354 00:39:36.975071 Starting systemd-udevd version 252.22-1~deb12u1
10355 00:39:37.188771 <6>[ 6.687582] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10356 00:39:37.195840 <6>[ 6.692435] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10357 00:39:37.205223 <6>[ 6.692462] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10358 00:39:37.212303 <6>[ 6.692468] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10359 00:39:37.220367 <6>[ 6.699542] remoteproc remoteproc0: scp is available
10360 00:39:37.226947 <6>[ 6.699629] remoteproc remoteproc0: powering up scp
10361 00:39:37.233670 <6>[ 6.699634] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10362 00:39:37.239989 <6>[ 6.699661] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10363 00:39:37.246800 <4>[ 6.738504] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10364 00:39:37.253550 <4>[ 6.741758] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10365 00:39:37.260046 <6>[ 6.751694] mc: Linux media interface: v0.10
10366 00:39:37.266770 <3>[ 6.754074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10367 00:39:37.276362 <3>[ 6.754100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10368 00:39:37.283568 <3>[ 6.754109] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10369 00:39:37.293014 <3>[ 6.758218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10370 00:39:37.300310 <3>[ 6.758245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10371 00:39:37.306802 <3>[ 6.758250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10372 00:39:37.317058 <3>[ 6.758257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10373 00:39:37.323929 <3>[ 6.758261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10374 00:39:37.333734 <3>[ 6.765702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10375 00:39:37.340433 <3>[ 6.767330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10376 00:39:37.350033 <3>[ 6.767371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10377 00:39:37.356913 <3>[ 6.767375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10378 00:39:37.363179 <3>[ 6.767517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10379 00:39:37.373794 <3>[ 6.767522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10380 00:39:37.379908 <3>[ 6.767524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10381 00:39:37.389791 <3>[ 6.767531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10382 00:39:37.396639 <3>[ 6.767534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10383 00:39:37.406290 <3>[ 6.767563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10384 00:39:37.412882 <6>[ 6.768151] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10385 00:39:37.422829 <4>[ 6.796415] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10386 00:39:37.425991 <4>[ 6.796415] Fallback method does not support PEC.
10387 00:39:37.435767 <3>[ 6.813159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10388 00:39:37.442238 <6>[ 6.816830] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10389 00:39:37.448837 <6>[ 6.816838] pci_bus 0000:00: root bus resource [bus 00-ff]
10390 00:39:37.455515 <6>[ 6.816842] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10391 00:39:37.465632 <6>[ 6.816844] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10392 00:39:37.472056 <6>[ 6.816878] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10393 00:39:37.478630 <6>[ 6.816891] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10394 00:39:37.481838 <6>[ 6.816964] pci 0000:00:00.0: supports D1 D2
10395 00:39:37.488707 <6>[ 6.816966] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10396 00:39:37.498332 <6>[ 6.817808] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10397 00:39:37.505034 <6>[ 6.817905] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10398 00:39:37.511606 <6>[ 6.817932] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10399 00:39:37.518277 <6>[ 6.817948] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10400 00:39:37.524939 <6>[ 6.817963] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10401 00:39:37.531479 <6>[ 6.818067] pci 0000:01:00.0: supports D1 D2
10402 00:39:37.538053 <6>[ 6.818069] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10403 00:39:37.544507 <6>[ 6.824768] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10404 00:39:37.554658 <6>[ 6.824845] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10405 00:39:37.560999 <6>[ 6.824854] remoteproc remoteproc0: remote processor scp is now up
10406 00:39:37.567700 <6>[ 6.827450] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10407 00:39:37.574327 <6>[ 6.827475] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10408 00:39:37.584321 <6>[ 6.827477] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10409 00:39:37.590846 <6>[ 6.827483] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10410 00:39:37.597529 <6>[ 6.827496] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10411 00:39:37.607249 <6>[ 6.827508] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10412 00:39:37.610772 <6>[ 6.827520] pci 0000:00:00.0: PCI bridge to [bus 01]
10413 00:39:37.620412 <6>[ 6.827526] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10414 00:39:37.627183 <6>[ 6.827641] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10415 00:39:37.633688 <6>[ 6.828114] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10416 00:39:37.637719 <6>[ 6.828674] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10417 00:39:37.647607 <3>[ 6.836672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10418 00:39:37.657042 <6>[ 6.845126] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10419 00:39:37.663662 <6>[ 6.847372] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10420 00:39:37.673416 Begin: Loading e<6>[ 6.848118] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10421 00:39:37.683286 <6>[ 6.872674] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10422 00:39:37.693278 <6>[ 6.873048] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10423 00:39:37.699781 <6>[ 6.893439] videodev: Linux video capture interface: v2.00
10424 00:39:37.706372 <5>[ 6.894068] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10425 00:39:37.713157 <5>[ 6.913321] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10426 00:39:37.723196 <5>[ 6.913529] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10427 00:39:37.729730 <4>[ 6.913604] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10428 00:39:37.736405 <6>[ 6.913611] cfg80211: failed to load regulatory.db
10429 00:39:37.739750 <6>[ 6.916758] Bluetooth: Core ver 2.22
10430 00:39:37.746526 <6>[ 6.916815] NET: Registered PF_BLUETOOTH protocol family
10431 00:39:37.752812 <6>[ 6.916818] Bluetooth: HCI device and connection manager initialized
10432 00:39:37.756462 <6>[ 6.916837] Bluetooth: HCI socket layer initialized
10433 00:39:37.762726 <6>[ 6.916846] Bluetooth: L2CAP socket layer initialized
10434 00:39:37.769501 <6>[ 6.916886] Bluetooth: SCO socket layer initialized
10435 00:39:37.776269 <6>[ 6.967447] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10436 00:39:37.786227 <6>[ 6.968826] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10437 00:39:37.792547 <6>[ 6.968959] usbcore: registered new interface driver uvcvideo
10438 00:39:37.798861 <6>[ 6.995081] usbcore: registered new interface driver btusb
10439 00:39:37.809385 <4>[ 6.996737] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10440 00:39:37.815863 <3>[ 6.996769] Bluetooth: hci0: Failed to load firmware file (-2)
10441 00:39:37.822474 <3>[ 6.996773] Bluetooth: hci0: Failed to set up firmware (-2)
10442 00:39:37.832396 <4>[ 6.996778] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10443 00:39:37.839041 <6>[ 7.010403] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10444 00:39:37.845740 <6>[ 7.022617] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10445 00:39:37.851932 <6>[ 7.022703] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10446 00:39:37.858643 <6>[ 7.039583] mt7921e 0000:01:00.0: ASIC revision: 79610010
10447 00:39:37.865231 <6>[ 7.137923] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10448 00:39:37.868534 <6>[ 7.137923]
10449 00:39:37.871810 ssential drivers ... done.
10450 00:39:37.875053 Begin: Running /scripts/init-premount ... done.
10451 00:39:37.881898 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10452 00:39:37.898188 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available<6>[ 7.398119] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10453 00:39:37.898939
10454 00:39:37.901487 Device /sys/class/net/eth0 found
10455 00:39:37.901937 done.
10456 00:39:37.911435 Begin: Waiting up to 180 secs for any network device to become available ... done.
10457 00:39:37.929815 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10458 00:39:37.936580 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10459 00:39:37.942946 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10460 00:39:37.949490 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10461 00:39:37.956007 host : mt8192-asurada-spherion-r0-cbg-4
10462 00:39:37.962566 domain : lava-rack
10463 00:39:37.965957 rootserver: 192.168.201.1 rootpath:
10464 00:39:37.966478 filename :
10465 00:39:38.086387 done.
10466 00:39:38.093498 Begin: Running /scripts/nfs-bottom ... done.
10467 00:39:38.105657 Begin: Running /scripts/init-bottom ... done.
10468 00:39:39.445071 <6>[ 8.949703] NET: Registered PF_INET6 protocol family
10469 00:39:39.448076 <6>[ 8.951628] Segment Routing with IPv6
10470 00:39:39.454824 <6>[ 8.951656] In-situ OAM (IOAM) with IPv6
10471 00:39:39.615460 <30>[ 9.093357] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10472 00:39:39.622287 <30>[ 9.093399] systemd[1]: Detected architecture arm64.
10473 00:39:39.622707
10474 00:39:39.628956 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10475 00:39:39.629400
10476 00:39:39.652953 <30>[ 9.157234] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10477 00:39:40.656671 <30>[ 10.155634] systemd[1]: Queued start job for default target graphical.target.
10478 00:39:40.709448 [[0;32m OK [0m] Created slic<30>[ 10.208727] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10479 00:39:40.713253 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10480 00:39:40.738640 [[0;32m OK [0m] Created slic<30>[ 10.237595] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10481 00:39:40.741580 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10482 00:39:40.768137 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 10.264351] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10483 00:39:40.771840 m-seria…[0m - Slice /system/serial-getty.
10484 00:39:40.793088 [[0;32m OK [0m] Created slic<30>[ 10.292855] systemd[1]: Created slice user.slice - User and Session Slice.
10485 00:39:40.796484 e [0;1;39muser.slice[0m - User and Session Slice.
10486 00:39:40.819838 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 10.316272] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10487 00:39:40.823504 -passwo…quests to Console Directory Watch.
10488 00:39:40.848447 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 10.344375] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10489 00:39:40.851539 -passwo… Requests to Wall Directory Watch.
10490 00:39:40.882888 Expecting device [0;1;<30>[ 10.372349] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10491 00:39:40.889695 <30>[ 10.372532] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10492 00:39:40.895939 39mdev-ttyS0.device[0m - /dev/ttyS0...
10493 00:39:40.916611 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 10.416011] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10494 00:39:40.920006 tsetup.…get[0m - Local Encrypted Volumes.
10495 00:39:40.943414 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 10.439752] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10496 00:39:40.946714 grityse…Local Integrity Protected Volumes.
10497 00:39:40.968215 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 10.467818] systemd[1]: Reached target paths.target - Path Units.
10498 00:39:40.968640 s.target[0m - Path Units.
10499 00:39:40.992582 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 10.492108] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10500 00:39:40.995797 te-fs.target[0m - Remote File Systems.
10501 00:39:41.015976 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 10.515712] systemd[1]: Reached target slices.target - Slice Units.
10502 00:39:41.019239 es.target[0m - Slice Units.
10503 00:39:41.037444 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 10.540147] systemd[1]: Reached target swap.target - Swaps.
10504 00:39:41.040782 .target[0m - Swaps.
10505 00:39:41.064790 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 10.564247] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10506 00:39:41.071409 tysetup… - Local Verity Protected Volumes.
10507 00:39:41.093115 [[0;32m OK [0m] Listening on<30>[ 10.592531] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10508 00:39:41.099736 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10509 00:39:41.122418 [[0;32m OK [<30>[ 10.622273] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10510 00:39:41.129088 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10511 00:39:41.150822 [[0;32m OK [<30>[ 10.650215] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10512 00:39:41.157511 0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10513 00:39:41.181039 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.680391] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10514 00:39:41.183763 d-journald.socket[0m - Journal Socket.
10515 00:39:41.205655 [[0;32m OK [0m] Listening on<30>[ 10.705377] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10516 00:39:41.212300 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10517 00:39:41.232060 [[0;32m OK [<30>[ 10.735007] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10518 00:39:41.241789 0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10519 00:39:41.260403 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.760212] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10520 00:39:41.263854 d-udevd…l.socket[0m - udev Kernel Socket.
10521 00:39:41.328294 Mounting [0;1;39mdev-hugepages.mount[<30>[ 10.827882] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10522 00:39:41.331652 0m - Huge Pages File System...
10523 00:39:41.355276 Mountin<30>[ 10.858188] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10524 00:39:41.361839 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10525 00:39:41.388599 Mounting [0;1;39msys-kernel-debug.…<30>[ 10.888368] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10526 00:39:41.391841 [0m - Kernel Debug File System...
10527 00:39:41.423202 <30>[ 10.916306] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10528 00:39:41.433032 <30>[ 10.922626] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10529 00:39:41.439723 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10530 00:39:41.469710 Starting [0;1;39mmodpr<30>[ 10.969321] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10531 00:39:41.473139 obe@configfs…m - Load Kernel Module configfs...
10532 00:39:41.501512 Starting [0;1;39mmodpr<30>[ 11.001120] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10533 00:39:41.505349 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10534 00:39:41.533452 Starting [0;1;39mmodpr<30>[ 11.033213] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10535 00:39:41.536864 obe@drm.service[0m - Load Kernel Module drm...
10536 00:39:41.552803 <6>[ 11.051966] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10537 00:39:41.571331 Startin<30>[ 11.070755] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10538 00:39:41.574519 g [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10539 00:39:41.602052 Starting [0;1;39mmodpr<30>[ 11.101608] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10540 00:39:41.605374 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10541 00:39:41.633468 Starting [0;1;39mmodpr<30>[ 11.133189] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10542 00:39:41.637199 obe@loop.ser…e[0m - Load Kernel Module loop...
10543 00:39:41.645036 <6>[ 11.151211] fuse: init (API version 7.37)
10544 00:39:41.667513 Startin<30>[ 11.170073] systemd[1]: Starting systemd-journald.service - Journal Service...
10545 00:39:41.673986 g [0;1;39msystemd-journald.service[0m - Journal Service...
10546 00:39:41.733468 Starting [0;1;39msyste<30>[ 11.232841] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10547 00:39:41.736518 md-modules-l…rvice[0m - Load Kernel Modules...
10548 00:39:41.771147 Startin<30>[ 11.270368] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10549 00:39:41.777462 g [0;1;39msystemd-network-g… units from Kernel command line...
10550 00:39:41.809401 Starting [0;1;39msyste<30>[ 11.307785] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10551 00:39:41.819020 md-remount-f…n<3>[ 11.315618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10552 00:39:41.822326 t Root and Kernel File Systems...
10553 00:39:41.840108 <3>[ 11.341449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10554 00:39:41.856431 Starting [0;1;39msystemd-udev-trig…[<30>[ 11.355563] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10555 00:39:41.866502 0m - Coldplug Al<3>[ 11.367614] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10556 00:39:41.869724 l udev Devices...
10557 00:39:41.892167 <3>[ 11.391698] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10558 00:39:41.899021 <30>[ 11.399854] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10559 00:39:41.913027 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepag<3>[ 11.412634] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10560 00:39:41.915945 es.mount[0m - Huge Pages File System.
10561 00:39:41.932452 <3>[ 11.434177] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10562 00:39:41.942999 [[0;32m OK [0m] Mounted [0;<30>[ 11.444859] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10563 00:39:41.956116 1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 11.456897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10564 00:39:41.959257 File System.
10565 00:39:41.980846 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-<30>[ 11.480487] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10566 00:39:41.990792 debug.m…nt[0m<3>[ 11.482184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10567 00:39:41.994182 - Kernel Debug File System.
10568 00:39:42.017663 [[0;32m OK [0m] Finished [0<30>[ 11.516972] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10569 00:39:42.024263 ;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10570 00:39:42.044439 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 11.544239] systemd[1]: Started systemd-journald.service - Journal Service.
10571 00:39:42.047966 rnald.service[0m - Journal Service.
10572 00:39:42.069878 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10573 00:39:42.095369 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10574 00:39:42.119825 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10575 00:39:42.140809 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10576 00:39:42.164117 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10577 00:39:42.188434 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10578 00:39:42.207001 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10579 00:39:42.227184 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10580 00:39:42.264058 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel F<4>[ 11.755594] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10581 00:39:42.267846 ile Systems.
10582 00:39:42.274095 <3>[ 11.755612] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10583 00:39:42.284757 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10584 00:39:42.303930 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10585 00:39:42.345631 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10586 00:39:42.373482 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10587 00:39:42.401624 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10588 00:39:42.425271 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10589 00:39:42.476057 <46>[ 11.978706] systemd-journald[311]: Received client request to flush runtime journal.
10590 00:39:42.482728 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10591 00:39:42.509663 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10592 00:39:42.796672 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10593 00:39:42.813230 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10594 00:39:42.834362 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10595 00:39:43.242738 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10596 00:39:43.609714 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10597 00:39:43.654308 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10598 00:39:43.910553 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10599 00:39:43.997457 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10600 00:39:44.020705 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10601 00:39:44.036373 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10602 00:39:44.088850 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10603 00:39:44.114390 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10604 00:39:44.315646 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10605 00:39:44.361628 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10606 00:39:44.421157 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10607 00:39:44.443666 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10608 00:39:44.617143 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10609 00:39:44.647062 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10610 00:39:44.772000 [[0;32m OK [0m] Created slice [0;1;39msyste<6>[ 14.272267] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10611 00:39:44.775138 m-syste…- Slice /system/systemd-backlight.
10612 00:39:44.822904 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10613 00:39:44.832472 <4>[ 14.336564] power_supply_show_property: 4 callbacks suppressed
10614 00:39:44.842040 <3>[ 14.336577] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10615 00:39:44.849010 <3>[ 14.337319] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10616 00:39:44.859866 <3>[ 14.363112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 00:39:44.887454 [[0;32m OK [0m] Reached target [0;1;39mblue<3>[ 14.387348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10618 00:39:44.890869 tooth.target[0m - Bluetooth Support.
10619 00:39:44.907641 <3>[ 14.409661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10620 00:39:44.932145 [[0;32m OK [0m] Finished [0;1;39msystemd-up<3>[ 14.431688] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10621 00:39:44.938860 date-ut…cord System Boot/Shutdown in UTMP.
10622 00:39:44.955451 <3>[ 14.455760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 00:39:44.965658 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10624 00:39:44.983773 <3>[ 14.485247] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10625 00:39:44.993827 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10626 00:39:45.004045 <3>[ 14.504978] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 00:39:45.014923 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10628 00:39:45.024656 <3>[ 14.526892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10629 00:39:45.044131 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10630 00:39:45.064923 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10631 00:39:45.080157 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10632 00:39:45.095566 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10633 00:39:45.122734 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10634 00:39:45.146317 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10635 00:39:45.167558 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10636 00:39:45.186533 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10637 00:39:45.206702 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10638 00:39:45.223071 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10639 00:39:45.241225 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10640 00:39:45.259047 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10641 00:39:45.274657 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10642 00:39:45.290038 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10643 00:39:45.335352 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10644 00:39:45.367991 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10645 00:39:45.521023 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10646 00:39:45.546025 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10647 00:39:45.609858 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10648 00:39:45.629940 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10649 00:39:45.655105 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10650 00:39:45.675552 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10651 00:39:45.697736 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10652 00:39:45.718765 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10653 00:39:45.750667 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10654 00:39:45.769806 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10655 00:39:45.920281 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10656 00:39:45.939046 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10657 00:39:45.956884 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10658 00:39:46.019717 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10659 00:39:46.083474 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10660 00:39:46.160999
10661 00:39:46.164218 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10662 00:39:46.164757
10663 00:39:46.167489 debian-bookworm-arm64 login: root (automatic login)
10664 00:39:46.167948
10665 00:39:46.389759 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10666 00:39:46.389884
10667 00:39:46.396481 The programs included with the Debian GNU/Linux system are free software;
10668 00:39:46.403262 the exact distribution terms for each program are described in the
10669 00:39:46.406289 individual files in /usr/share/doc/*/copyright.
10670 00:39:46.406370
10671 00:39:46.412923 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10672 00:39:46.416091 permitted by applicable law.
10673 00:39:46.485902 Matched prompt #10: / #
10675 00:39:46.486166 Setting prompt string to ['/ #']
10676 00:39:46.486281 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10678 00:39:46.486507 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10679 00:39:46.486619 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
10680 00:39:46.486701 Setting prompt string to ['/ #']
10681 00:39:46.486772 Forcing a shell prompt, looking for ['/ #']
10683 00:39:46.537044 / #
10684 00:39:46.537580 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10685 00:39:46.537949 Waiting using forced prompt support (timeout 00:02:30)
10686 00:39:46.543173
10687 00:39:46.543912 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10688 00:39:46.544421 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
10690 00:39:46.645483 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3'
10691 00:39:46.651231 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173474/extract-nfsrootfs-9s4r8sg3'
10693 00:39:46.752699 / # export NFS_SERVER_IP='192.168.201.1'
10694 00:39:46.759027 export NFS_SERVER_IP='192.168.201.1'
10695 00:39:46.759852 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10696 00:39:46.760361 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
10697 00:39:46.760826 end: 2 depthcharge-action (duration 00:01:24) [common]
10698 00:39:46.761337 start: 3 lava-test-retry (timeout 00:30:00) [common]
10699 00:39:46.761948 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10700 00:39:46.762496 Using namespace: common
10702 00:39:46.863701 / # #
10703 00:39:46.864299 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10704 00:39:46.870160 #
10705 00:39:46.870915 Using /lava-14173474
10707 00:39:46.972037 / # export SHELL=/bin/sh
10708 00:39:46.978004 export SHELL=/bin/sh
10710 00:39:47.079511 / # . /lava-14173474/environment
10711 00:39:47.085249 . /lava-14173474/environment
10713 00:39:47.192132 / # /lava-14173474/bin/lava-test-runner /lava-14173474/0
10714 00:39:47.192722 Test shell timeout: 10s (minimum of the action and connection timeout)
10715 00:39:47.198310 /lava-14173474/bin/lava-test-runner /lava-14173474/0
10716 00:39:47.400108 + export TESTRUN_ID=0_lc-compliance
10717 00:39:47.406326 + cd /lava-14173474/0/tests/0_lc-compliance
10718 00:39:47.406424 + cat uuid
10719 00:39:47.409806 + UUID=14173474_1.6.2.3.1
10720 00:39:47.409900 + set +x
10721 00:39:47.413206 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14173474_1.6.2.3.1>
10722 00:39:47.413532 Received signal: <STARTRUN> 0_lc-compliance 14173474_1.6.2.3.1
10723 00:39:47.413636 Starting test lava.0_lc-compliance (14173474_1.6.2.3.1)
10724 00:39:47.413743 Skipping test definition patterns.
10725 00:39:47.416616 + /usr/bin/lc-compliance-parser.sh
10726 00:39:49.007810 [0:00:18.502230715] [416] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
10727 00:39:49.011099 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10728 00:39:49.024190 [0:00:18.519021242] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10729 00:39:49.069791 [==========] Running 120 tests from 1 test suite.
10730 00:39:49.084950 [0:00:18.579814342] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10731 00:39:49.144577 [0:00:18.639747941] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10732 00:39:49.147708 [----------] Global test environment set-up.
10733 00:39:49.198433 [0:00:18.694036826] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10734 00:39:49.201711 [----------] 120 tests from CaptureTests/SingleStream
10735 00:39:49.251460 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10736 00:39:49.291066 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10737 00:39:49.291337 Received signal: <TESTSET> START CaptureTests/SingleStream
10738 00:39:49.291415 Starting test_set CaptureTests/SingleStream
10739 00:39:49.294237 Camera needs 4 requests, can't test only 1
10740 00:39:49.339612 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10741 00:39:49.396114
10742 00:39:49.465777 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
10743 00:39:49.542141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10744 00:39:49.542908 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10746 00:39:49.556063 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10747 00:39:49.599646 Camera needs 4 requests, can't test only 2
10748 00:39:49.627220 [0:00:19.124918286] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10749 00:39:49.668634 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10750 00:39:49.729041
10751 00:39:49.797017 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (57 ms)
10752 00:39:49.880141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10753 00:39:49.880922 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10755 00:39:49.896458 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10756 00:39:49.940819 Camera needs 4 requests, can't test only 3
10757 00:39:50.009572 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10758 00:39:50.073550
10759 00:39:50.143404 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (55 ms)
10760 00:39:50.217998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
10761 00:39:50.218755 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
10763 00:39:50.231118 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
10764 00:39:50.280581 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (431 ms)
10765 00:39:50.321105 [0:00:19.822383438] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10766 00:39:50.359726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
10767 00:39:50.360010 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
10769 00:39:50.374559 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
10770 00:39:50.411784 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (697 ms)
10771 00:39:50.466884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
10772 00:39:50.467161 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
10774 00:39:50.478231 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
10775 00:39:51.567977 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1260 ms)
10776 00:39:51.577331 [0:00:21.084425126] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10777 00:39:51.644029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
10778 00:39:51.644364 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
10780 00:39:51.659123 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
10781 00:39:53.384487 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1823 ms)
10782 00:39:53.394647 [0:00:22.907951497] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10783 00:39:53.452771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
10784 00:39:53.453088 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
10786 00:39:53.464727 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
10787 00:39:56.112306 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2734 ms)
10788 00:39:56.122465 [0:00:25.642957763] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10789 00:39:56.195332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
10790 00:39:56.196195 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
10792 00:39:56.207943 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
10793 00:40:00.309841 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4204 ms)
10794 00:40:00.319549 [0:00:29.847524320] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10795 00:40:00.390927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
10796 00:40:00.391230 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
10798 00:40:00.402012 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
10799 00:40:06.886567 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6582 ms)
10800 00:40:06.896200 [0:00:36.430481995] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10801 00:40:06.951048 [0:00:36.486010016] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10802 00:40:06.972685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
10803 00:40:06.973047 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
10805 00:40:06.983455 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
10806 00:40:07.006829 [0:00:36.541456071] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10807 00:40:07.029690 Camera needs 4 requests, can't test only 1
10808 00:40:07.060084 [0:00:36.594856029] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10809 00:40:07.100460 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10810 00:40:07.164305
10811 00:40:07.229797 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
10812 00:40:07.297546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
10813 00:40:07.298293 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
10815 00:40:07.312017 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
10816 00:40:07.356087 Camera needs 4 requests, can't test only 2
10817 00:40:07.417686 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10818 00:40:07.484073
10819 00:40:07.552367 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
10820 00:40:07.619566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
10821 00:40:07.620442 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
10823 00:40:07.631875 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
10824 00:40:07.674474 Camera needs 4 requests, can't test only 3
10825 00:40:07.740663 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10826 00:40:07.754546 [0:00:37.290098344] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10827 00:40:07.795695
10828 00:40:07.848438 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (53 ms)
10829 00:40:07.922998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
10830 00:40:07.923773 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
10832 00:40:07.936299 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
10833 00:40:07.979514 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (694 ms)
10834 00:40:08.051342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
10835 00:40:08.052052 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
10837 00:40:08.064256 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
10838 00:40:08.310824 <6>[ 37.819997] vpu: disabling
10839 00:40:08.314174 <6>[ 37.820118] vproc2: disabling
10840 00:40:08.317384 <6>[ 37.820172] vproc1: disabling
10841 00:40:08.320624 <6>[ 37.820227] vaud18: disabling
10842 00:40:08.327499 <6>[ 37.820476] vsram_others: disabling
10843 00:40:08.330953 <6>[ 37.820653] va09: disabling
10844 00:40:08.334431 <6>[ 37.820730] vsram_md: disabling
10845 00:40:08.337574 <6>[ 37.820863] Vgpu: disabling
10846 00:40:08.655179 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (908 ms)
10847 00:40:08.668154 [0:00:38.199271295] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10848 00:40:08.736837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
10849 00:40:08.737645 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
10851 00:40:08.749784 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
10852 00:40:09.910084 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1255 ms)
10853 00:40:09.923403 [0:00:39.454890190] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10854 00:40:09.993800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
10855 00:40:09.994656 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
10857 00:40:10.008373 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
10858 00:40:11.726173 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1816 ms)
10859 00:40:11.739402 [0:00:41.271637762] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10860 00:40:11.809488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
10861 00:40:11.810245 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
10863 00:40:11.822893 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
10864 00:40:14.453569 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2728 ms)
10865 00:40:14.466556 [0:00:44.001363140] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10866 00:40:14.538551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
10867 00:40:14.539276 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
10869 00:40:14.555222 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
10870 00:40:18.649451 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4196 ms)
10871 00:40:18.662444 [0:00:48.198392316] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10872 00:40:18.745177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
10873 00:40:18.745937 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
10875 00:40:18.760910 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
10876 00:40:25.225781 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6577 ms)
10877 00:40:25.238560 [0:00:54.775633588] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10878 00:40:25.287907 [0:00:54.828215288] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10879 00:40:25.301535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
10880 00:40:25.301828 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
10882 00:40:25.313712 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
10883 00:40:25.341865 [0:00:54.882369286] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10884 00:40:25.354446 Camera needs 4 requests, can't test only 1
10885 00:40:25.399321 [0:00:54.939718034] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10886 00:40:25.409981 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10887 00:40:25.452815
10888 00:40:25.513749 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (53 ms)
10889 00:40:25.577268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
10890 00:40:25.577659 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
10892 00:40:25.586958 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
10893 00:40:25.625805 Camera needs 4 requests, can't test only 2
10894 00:40:25.679327 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10895 00:40:25.733251
10896 00:40:25.791652 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
10897 00:40:25.857784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
10898 00:40:25.858135 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
10900 00:40:25.869548 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
10901 00:40:25.905967 Camera needs 4 requests, can't test only 3
10902 00:40:25.963058 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10903 00:40:26.014292
10904 00:40:26.071563 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
10905 00:40:26.096511 [0:00:55.637228369] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10906 00:40:26.144133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
10907 00:40:26.144455 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
10909 00:40:26.157607 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
10910 00:40:26.196244 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (696 ms)
10911 00:40:26.258220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
10912 00:40:26.258590 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
10914 00:40:26.269344 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
10915 00:40:26.995743 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (908 ms)
10916 00:40:27.008706 [0:00:56.545133338] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10917 00:40:27.068411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
10918 00:40:27.068735 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
10920 00:40:27.081503 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
10921 00:40:28.250880 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
10922 00:40:28.264051 [0:00:57.800383072] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10923 00:40:28.318520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
10924 00:40:28.318843 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
10926 00:40:28.327022 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
10927 00:40:30.066078 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1815 ms)
10928 00:40:30.079253 [0:00:59.615685716] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10929 00:40:30.131058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
10930 00:40:30.131393 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
10932 00:40:30.145096 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
10933 00:40:32.792319 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2727 ms)
10934 00:40:32.805296 [0:01:02.344315902] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10935 00:40:32.863011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
10936 00:40:32.863335 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
10938 00:40:32.874212 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
10939 00:40:36.988982 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
10940 00:40:37.002084 [0:01:06.541366261] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10941 00:40:37.062297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
10942 00:40:37.062618 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
10944 00:40:37.075437 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
10945 00:40:43.565686 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6577 ms)
10946 00:40:43.578882 [0:01:13.118937303] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10947 00:40:43.628376 [0:01:13.171576505] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10948 00:40:43.639598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
10949 00:40:43.639913 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
10951 00:40:43.651039 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
10952 00:40:43.681129 [0:01:13.224074322] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10953 00:40:43.693067 Camera needs 4 requests, can't test only 1
10954 00:40:43.737967 [0:01:13.280956541] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10955 00:40:43.751562 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10956 00:40:43.810872
10957 00:40:43.868041 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
10958 00:40:43.932560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
10959 00:40:43.932885 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
10961 00:40:43.943311 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
10962 00:40:43.980221 Camera needs 4 requests, can't test only 2
10963 00:40:44.040220 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10964 00:40:44.092466
10965 00:40:44.158483 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (52 ms)
10966 00:40:44.227063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
10967 00:40:44.227386 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
10969 00:40:44.238092 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
10970 00:40:44.274023 Camera needs 4 requests, can't test only 3
10971 00:40:44.331620 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10972 00:40:44.385458
10973 00:40:44.432879 [0:01:13.975617166] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10974 00:40:44.449150 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
10975 00:40:44.511084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
10976 00:40:44.511420 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
10978 00:40:44.521255 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
10979 00:40:44.555207 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (695 ms)
10980 00:40:44.617542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
10981 00:40:44.617896 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
10983 00:40:44.629263 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
10984 00:40:45.330982 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (907 ms)
10985 00:40:45.344264 [0:01:14.882797083] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10986 00:40:45.401551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
10987 00:40:45.401877 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
10989 00:40:45.411893 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
10990 00:40:46.586757 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1255 ms)
10991 00:40:46.599860 [0:01:16.138171028] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10992 00:40:46.672829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
10993 00:40:46.673541 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
10995 00:40:46.684007 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
10996 00:40:48.401899 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1815 ms)
10997 00:40:48.414481 [0:01:17.953644684] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10998 00:40:48.484641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
10999 00:40:48.484934 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11001 00:40:48.498024 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11002 00:40:51.127472 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2725 ms)
11003 00:40:51.140422 [0:01:20.680724276] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11004 00:40:51.208600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11005 00:40:51.209340 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11007 00:40:51.222045 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11008 00:40:55.323260 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4196 ms)
11009 00:40:55.336157 [0:01:24.877167276] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11010 00:40:55.407542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11011 00:40:55.408276 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11013 00:40:55.421735 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11014 00:41:01.898726 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6576 ms)
11015 00:41:01.911984 [0:01:31.454235835] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11016 00:41:01.962743 [0:01:31.507498392] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11017 00:41:01.969034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11018 00:41:01.969310 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11020 00:41:01.978257 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11021 00:41:02.016977 [0:01:31.562244564] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11022 00:41:02.020767 Camera needs 4 requests, can't test only 1
11023 00:41:02.074025 [0:01:31.618732889] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11024 00:41:02.077025 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11025 00:41:02.123389
11026 00:41:02.174809 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (55 ms)
11027 00:41:02.233060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11028 00:41:02.233378 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11030 00:41:02.242266 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11031 00:41:02.272190 Camera needs 4 requests, can't test only 2
11032 00:41:02.320558 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11033 00:41:02.371528
11034 00:41:02.423801 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11035 00:41:02.482017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11036 00:41:02.482346 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11038 00:41:02.492605 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11039 00:41:02.528447 Camera needs 4 requests, can't test only 3
11040 00:41:02.580078 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11041 00:41:02.630436
11042 00:41:02.687237 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (56 ms)
11043 00:41:02.743743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11044 00:41:02.744064 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11046 00:41:02.753749 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11047 00:41:04.141614 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2077 ms)
11048 00:41:04.154760 [0:01:33.696941935] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11049 00:41:04.209115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11050 00:41:04.209458 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11052 00:41:04.218562 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11053 00:41:06.855512 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2714 ms)
11054 00:41:06.869039 [0:01:36.411469261] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11055 00:41:06.914354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11056 00:41:06.914664 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11058 00:41:06.923448 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11059 00:41:10.614436 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3759 ms)
11060 00:41:10.627532 [0:01:40.170580533] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11061 00:41:10.685539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11062 00:41:10.685918 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11064 00:41:10.695820 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11065 00:41:16.052811 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5438 ms)
11066 00:41:16.065972 [0:01:45.609825548] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11067 00:41:16.118026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11068 00:41:16.118359 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11070 00:41:16.128012 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11071 00:41:24.225281 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8172 ms)
11072 00:41:24.238067 [0:01:53.782155873] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11073 00:41:24.321090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11074 00:41:24.321902 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11076 00:41:24.334365 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11077 00:41:36.803439 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12580 ms)
11078 00:41:36.816403 [0:02:06.362572283] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11079 00:41:36.871308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11080 00:41:36.871637 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11082 00:41:36.882985 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11083 00:41:56.523548 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19722 ms)
11084 00:41:56.536522 [0:02:26.084784999] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 00:41:56.587396 [0:02:26.138608768] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11086 00:41:56.614935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11087 00:41:56.615673 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11089 00:41:56.628882 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11090 00:41:56.643338 [0:02:26.194602691] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 00:41:56.677216 Camera needs 4 requests, can't test only 1
11092 00:41:56.698181 [0:02:26.249337999] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11093 00:41:56.749136 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11094 00:41:56.816226
11095 00:41:56.888456 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (54 ms)
11096 00:41:56.962323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11097 00:41:56.963030 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11099 00:41:56.973951 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11100 00:41:57.022634 Camera needs 4 requests, can't test only 2
11101 00:41:57.095171 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11102 00:41:57.156020
11103 00:41:57.221250 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11104 00:41:57.286575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11105 00:41:57.286977 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11107 00:41:57.295755 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11108 00:41:57.334129 Camera needs 4 requests, can't test only 3
11109 00:41:57.391880 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11110 00:41:57.454953
11111 00:41:57.523655 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11112 00:41:57.594603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11113 00:41:57.594901 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11115 00:41:57.602513 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11116 00:41:58.770621 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2077 ms)
11117 00:41:58.780341 [0:02:28.327068691] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11118 00:41:58.864924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11119 00:41:58.865681 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11121 00:41:58.874886 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11122 00:42:01.477846 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2708 ms)
11123 00:42:01.487796 [0:02:31.036116077] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11124 00:42:01.540615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11125 00:42:01.540884 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11127 00:42:01.548527 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11128 00:42:05.236752 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3758 ms)
11129 00:42:05.246750 [0:02:34.794770308] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11130 00:42:05.300594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11131 00:42:05.300905 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11133 00:42:05.307774 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11134 00:42:10.672988 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5437 ms)
11135 00:42:10.682741 [0:02:40.231525770] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 00:42:10.745638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11137 00:42:10.745953 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11139 00:42:10.754452 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11140 00:42:18.843943 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8171 ms)
11141 00:42:18.853529 [0:02:48.403613925] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11142 00:42:18.919999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11143 00:42:18.920716 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11145 00:42:18.931625 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11146 00:42:31.422914 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12580 ms)
11147 00:42:31.432732 [0:03:00.984474310] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11148 00:42:31.496467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11149 00:42:31.496786 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11151 00:42:31.504417 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11152 00:42:51.142367 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19721 ms)
11153 00:42:51.151958 [0:03:20.705671542] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11154 00:42:51.200484 [0:03:20.758276927] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11155 00:42:51.207091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11156 00:42:51.207465 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11158 00:42:51.213542 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11159 00:42:51.253082 [0:03:20.810652388] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11160 00:42:51.255917 Camera needs 4 requests, can't test only 1
11161 00:42:51.307498 [0:03:20.865030850] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11162 00:42:51.310424 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11163 00:42:51.354450
11164 00:42:51.407363 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11165 00:42:51.463804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11166 00:42:51.464199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11168 00:42:51.470991 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11169 00:42:51.512022 Camera needs 4 requests, can't test only 2
11170 00:42:51.570250 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11171 00:42:51.622155
11172 00:42:51.676702 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (52 ms)
11173 00:42:51.729516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11174 00:42:51.729825 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11176 00:42:51.736644 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11177 00:42:51.771324 Camera needs 4 requests, can't test only 3
11178 00:42:51.827878 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11179 00:42:51.874430
11180 00:42:51.933309 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11181 00:42:51.996553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11182 00:42:51.996912 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11184 00:42:52.005971 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11185 00:42:53.381155 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2078 ms)
11186 00:42:53.390878 [0:03:22.944421927] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11187 00:42:53.460557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11188 00:42:53.461411 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11190 00:42:53.469626 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11191 00:42:56.089402 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2708 ms)
11192 00:42:56.099191 [0:03:25.653277465] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11193 00:42:56.174064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11194 00:42:56.174785 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11196 00:42:56.184122 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11197 00:42:59.847233 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3758 ms)
11198 00:42:59.856993 [0:03:29.411697696] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11199 00:42:59.932488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11200 00:42:59.933435 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11202 00:42:59.943202 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11203 00:43:05.284164 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5438 ms)
11204 00:43:05.294519 [0:03:34.849836774] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11205 00:43:05.345413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11206 00:43:05.345712 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11208 00:43:05.352176 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11209 00:43:13.455523 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8171 ms)
11210 00:43:13.465419 [0:03:43.021419236] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 00:43:13.533810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11212 00:43:13.534488 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11214 00:43:13.543003 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11215 00:43:26.033448 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12579 ms)
11216 00:43:26.042767 [0:03:55.601015621] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 00:43:26.101412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11218 00:43:26.101716 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11220 00:43:26.108553 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11221 00:43:45.751136 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19720 ms)
11222 00:43:45.761016 [0:04:15.321471084] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 00:43:45.810188 [0:04:15.374426238] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 00:43:45.820469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11225 00:43:45.820756 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11227 00:43:45.827696 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11228 00:43:45.863071 [0:04:15.427572468] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 00:43:45.866912 Camera needs 4 requests, can't test only 1
11230 00:43:45.909522 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11231 00:43:45.919832 [0:04:15.480578930] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 00:43:45.956374
11233 00:43:46.010710 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11234 00:43:46.060243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11235 00:43:46.060550 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11237 00:43:46.068527 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11238 00:43:46.100241 Camera needs 4 requests, can't test only 2
11239 00:43:46.153268 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11240 00:43:46.201479
11241 00:43:46.261046 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (53 ms)
11242 00:43:46.326956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11243 00:43:46.327270 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11245 00:43:46.334495 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11246 00:43:46.374724 Camera needs 4 requests, can't test only 3
11247 00:43:46.428557 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11248 00:43:46.483633
11249 00:43:46.545325 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11250 00:43:46.613092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11251 00:43:46.613399 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11253 00:43:46.621425 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11254 00:43:47.991008 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2079 ms)
11255 00:43:48.000931 [0:04:17.561579238] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11256 00:43:48.059229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11257 00:43:48.059543 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11259 00:43:48.069282 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11260 00:43:50.703677 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2712 ms)
11261 00:43:50.713570 [0:04:20.274685469] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 00:43:50.788007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11263 00:43:50.788903 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11265 00:43:50.799594 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11266 00:43:54.466087 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3762 ms)
11267 00:43:54.475814 [0:04:24.037261238] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11268 00:43:54.535074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11269 00:43:54.535351 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11271 00:43:54.543253 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11272 00:43:59.905406 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5440 ms)
11273 00:43:59.915221 [0:04:29.477647469] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 00:43:59.975900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11275 00:43:59.976199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11277 00:43:59.983080 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11278 00:44:08.078642 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8173 ms)
11279 00:44:08.088242 [0:04:37.651510239] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 00:44:08.156530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11281 00:44:08.156809 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11283 00:44:08.165755 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11284 00:44:20.660218 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12583 ms)
11285 00:44:20.670201 [0:04:50.234595624] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 00:44:20.744792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11287 00:44:20.745600 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11289 00:44:20.755290 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11290 00:44:40.381686 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19723 ms)
11291 00:44:40.391461 [0:05:09.958770548] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 00:44:40.447295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11293 00:44:40.447602 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11295 00:44:40.456119 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11296 00:44:40.796180 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (417 ms)
11297 00:44:40.809515 [0:05:10.376562318] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 00:44:40.887051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11299 00:44:40.887743 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11301 00:44:40.903775 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11302 00:44:41.286125 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11303 00:44:41.299173 [0:05:10.865956549] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 00:44:41.367247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11305 00:44:41.367789 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11307 00:44:41.379582 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11308 00:44:41.843744 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11309 00:44:41.856933 [0:05:11.424082010] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 00:44:41.928052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11311 00:44:41.928961 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11313 00:44:41.942362 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11314 00:44:42.541893 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (697 ms)
11315 00:44:42.554921 [0:05:12.122221318] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 00:44:42.631478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11317 00:44:42.632209 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11319 00:44:42.645666 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11320 00:44:43.449771 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (908 ms)
11321 00:44:43.463042 [0:05:13.030092626] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 00:44:43.537893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11323 00:44:43.538681 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11325 00:44:43.552658 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11326 00:44:44.707459 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1257 ms)
11327 00:44:44.720264 [0:05:14.287856780] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11328 00:44:44.795631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11329 00:44:44.796387 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11331 00:44:44.811505 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11332 00:44:46.525228 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1818 ms)
11333 00:44:46.538133 [0:05:16.106705241] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11334 00:44:46.591964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11335 00:44:46.592274 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11337 00:44:46.601980 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11338 00:44:49.251019 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2726 ms)
11339 00:44:49.264626 [0:05:18.831771626] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11340 00:44:49.311894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11341 00:44:49.312243 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11343 00:44:49.323524 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11344 00:44:53.448525 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4197 ms)
11345 00:44:53.461949 [0:05:23.029474242] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 00:44:53.510266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11347 00:44:53.510570 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11349 00:44:53.519975 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11350 00:45:00.025267 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6577 ms)
11351 00:45:00.038185 [0:05:29.606864780] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 00:45:00.084436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11353 00:45:00.084749 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11355 00:45:00.093693 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11356 00:45:00.444710 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (416 ms)
11357 00:45:00.454559 [0:05:30.023027473] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 00:45:00.503624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11359 00:45:00.503931 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11361 00:45:00.510549 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11362 00:45:00.930805 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (486 ms)
11363 00:45:00.940816 [0:05:30.509461627] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 00:45:00.987293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11365 00:45:00.987616 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11367 00:45:00.994396 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11368 00:45:01.487305 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (555 ms)
11369 00:45:01.497054 [0:05:31.065572550] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 00:45:01.551413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11371 00:45:01.551706 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11373 00:45:01.557922 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11374 00:45:02.182990 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (696 ms)
11375 00:45:02.193192 [0:05:31.761938550] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 00:45:02.244581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11377 00:45:02.244883 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11379 00:45:02.251260 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11380 00:45:03.091259 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (907 ms)
11381 00:45:03.100920 [0:05:32.668562550] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 00:45:03.151400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11383 00:45:03.151726 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11385 00:45:03.158039 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11386 00:45:04.345854 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1254 ms)
11387 00:45:04.355379 [0:05:33.923727011] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 00:45:04.409670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11389 00:45:04.409986 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11391 00:45:04.416018 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11392 00:45:06.160996 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1815 ms)
11393 00:45:06.170651 [0:05:35.739319319] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11394 00:45:06.221841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11395 00:45:06.222200 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11397 00:45:06.228718 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11398 00:45:08.888529 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2727 ms)
11399 00:45:08.898024 [0:05:38.467150319] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11400 00:45:08.956104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11401 00:45:08.956470 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11403 00:45:08.962680 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11404 00:45:13.083756 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4195 ms)
11405 00:45:13.093955 [0:05:42.663179627] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 00:45:13.149137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11407 00:45:13.149424 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11409 00:45:13.157299 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11410 00:45:19.659689 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6576 ms)
11411 00:45:19.669369 [0:05:49.239490782] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 00:45:19.745153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11413 00:45:19.745454 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11415 00:45:19.754920 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11416 00:45:20.075604 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (415 ms)
11417 00:45:20.085162 [0:05:49.654934628] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 00:45:20.164281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11419 00:45:20.165268 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11421 00:45:20.175175 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11422 00:45:20.560813 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (485 ms)
11423 00:45:20.570931 [0:05:50.140354782] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 00:45:20.649365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11425 00:45:20.650114 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11427 00:45:20.661180 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11428 00:45:21.116116 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (555 ms)
11429 00:45:21.125966 [0:05:50.695694397] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 00:45:21.195338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11431 00:45:21.195667 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11433 00:45:21.204076 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11434 00:45:21.811357 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (695 ms)
11435 00:45:21.821237 [0:05:51.391105166] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 00:45:21.889094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11437 00:45:21.889866 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11439 00:45:21.900269 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11440 00:45:22.718082 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (906 ms)
11441 00:45:22.727762 [0:05:52.298286089] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 00:45:22.793447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11443 00:45:22.793732 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11445 00:45:22.799984 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11446 00:45:23.973072 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1255 ms)
11447 00:45:23.982852 [0:05:53.552851397] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 00:45:24.063997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11449 00:45:24.064729 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11451 00:45:24.074330 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11452 00:45:25.788175 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1815 ms)
11453 00:45:25.798504 [0:05:55.368278859] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11454 00:45:25.873398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11455 00:45:25.874132 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11457 00:45:25.883787 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11458 00:45:28.513656 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2725 ms)
11459 00:45:28.523565 [0:05:58.094508321] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11460 00:45:28.597846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11461 00:45:28.598828 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11463 00:45:28.609116 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11464 00:45:32.708917 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4195 ms)
11465 00:45:32.718748 [0:06:02.290366321] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11466 00:45:32.767487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11467 00:45:32.767837 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11469 00:45:32.773946 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11470 00:45:39.284757 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6576 ms)
11471 00:45:39.294524 [0:06:08.866859014] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11472 00:45:39.370902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11473 00:45:39.371916 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11475 00:45:39.383392 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11476 00:45:39.698896 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (415 ms)
11477 00:45:39.709084 [0:06:09.282442167] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 00:45:39.758663 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11480 00:45:39.762096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11481 00:45:39.769105 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11482 00:45:40.186418 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (486 ms)
11483 00:45:40.196088 [0:06:09.768576706] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 00:45:40.243992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11485 00:45:40.244320 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11487 00:45:40.252901 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11488 00:45:40.741525 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (555 ms)
11489 00:45:40.751089 [0:06:10.323980398] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 00:45:40.805646 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11492 00:45:40.808464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11493 00:45:40.815265 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11494 00:45:41.437728 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (695 ms)
11495 00:45:41.447423 [0:06:11.020158937] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 00:45:41.512524 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11498 00:45:41.515235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11499 00:45:41.524800 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11500 00:45:42.343679 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (905 ms)
11501 00:45:42.353424 [0:06:11.926512937] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 00:45:42.409593 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11504 00:45:42.412655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11505 00:45:42.422978 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11506 00:45:43.599624 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1255 ms)
11507 00:45:43.608883 [0:06:13.182502552] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 00:45:43.671317 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11510 00:45:43.674842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11511 00:45:43.681927 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11512 00:45:45.415204 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1815 ms)
11513 00:45:45.424453 [0:06:14.998270399] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 00:45:45.491614 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11516 00:45:45.494335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11517 00:45:45.504630 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11518 00:45:48.141166 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2726 ms)
11519 00:45:48.151220 [0:06:17.724506245] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 00:45:48.222951 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11522 00:45:48.226294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11523 00:45:48.235547 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11524 00:45:52.336950 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4195 ms)
11525 00:45:52.346674 [0:06:21.920331860] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 00:45:52.416853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11528 00:45:52.419579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11529 00:45:52.431321 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11530 00:45:58.912476 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6576 ms)
11531 00:45:58.978965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11532 00:45:58.979473 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11534 00:45:58.991235 [----------] 120 tests from CaptureTests/SingleStream (369979 ms total)
11535 00:45:59.048204
11536 00:45:59.107680 [----------] Global test environment tear-down
11537 00:45:59.166104 [==========] 120 tests from 1 test suite ran. (369979 ms total)
11538 00:45:59.230313 <LAVA_SIGNAL_TESTSET STOP>
11539 00:45:59.230988 + set +x
11540 00:45:59.231827 Received signal: <TESTSET> STOP
11541 00:45:59.232394 Closing test_set CaptureTests/SingleStream
11542 00:45:59.237074 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14173474_1.6.2.3.1>
11543 00:45:59.237836 Received signal: <ENDRUN> 0_lc-compliance 14173474_1.6.2.3.1
11544 00:45:59.238244 Ending use of test pattern.
11545 00:45:59.238563 Ending test lava.0_lc-compliance (14173474_1.6.2.3.1), duration 371.82
11547 00:45:59.240041 <LAVA_TEST_RUNNER EXIT>
11548 00:45:59.240649 ok: lava_test_shell seems to have completed
11549 00:45:59.249679 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11550 00:45:59.250533 end: 3.1 lava-test-shell (duration 00:06:12) [common]
11551 00:45:59.250967 end: 3 lava-test-retry (duration 00:06:12) [common]
11552 00:45:59.251400 start: 4 finalize (timeout 00:10:00) [common]
11553 00:45:59.251837 start: 4.1 power-off (timeout 00:00:30) [common]
11554 00:45:59.252561 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11555 00:45:59.369176 >> Command sent successfully.
11556 00:45:59.372341 Returned 0 in 0 seconds
11557 00:45:59.473234 end: 4.1 power-off (duration 00:00:00) [common]
11559 00:45:59.474805 start: 4.2 read-feedback (timeout 00:10:00) [common]
11560 00:45:59.476141 Listened to connection for namespace 'common' for up to 1s
11561 00:46:00.476580 Finalising connection for namespace 'common'
11562 00:46:00.476754 Disconnecting from shell: Finalise
11563 00:46:00.476833 / #
11564 00:46:00.577131 end: 4.2 read-feedback (duration 00:00:01) [common]
11565 00:46:00.577338 end: 4 finalize (duration 00:00:01) [common]
11566 00:46:00.577469 Cleaning after the job
11567 00:46:00.577570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/ramdisk
11568 00:46:00.579746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/kernel
11569 00:46:00.590489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/dtb
11570 00:46:00.590695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/nfsrootfs
11571 00:46:00.631644 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173474/tftp-deploy-ty0tk77m/modules
11572 00:46:00.637277 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173474
11573 00:46:00.900530 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173474
11574 00:46:00.900711 Job finished correctly