Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 19
1 01:35:48.194527 lava-dispatcher, installed at version: 2024.03
2 01:35:48.194767 start: 0 validate
3 01:35:48.194907 Start time: 2024-06-05 01:35:48.194899+00:00 (UTC)
4 01:35:48.195038 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:35:48.195172 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:35:48.461502 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:35:48.461672 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:35:48.712056 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:35:48.712242 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:35:48.969981 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:35:48.970151 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:35:49.229480 validate duration: 1.03
14 01:35:49.229768 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:35:49.229886 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:35:49.229988 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:35:49.230125 Not decompressing ramdisk as can be used compressed.
18 01:35:49.230210 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 01:35:49.230275 saving as /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/ramdisk/rootfs.cpio.gz
20 01:35:49.230339 total size: 28105535 (26 MB)
21 01:35:49.231416 progress 0 % (0 MB)
22 01:35:49.239032 progress 5 % (1 MB)
23 01:35:49.246549 progress 10 % (2 MB)
24 01:35:49.254594 progress 15 % (4 MB)
25 01:35:49.262537 progress 20 % (5 MB)
26 01:35:49.270152 progress 25 % (6 MB)
27 01:35:49.278054 progress 30 % (8 MB)
28 01:35:49.285722 progress 35 % (9 MB)
29 01:35:49.293314 progress 40 % (10 MB)
30 01:35:49.300684 progress 45 % (12 MB)
31 01:35:49.308706 progress 50 % (13 MB)
32 01:35:49.316190 progress 55 % (14 MB)
33 01:35:49.323566 progress 60 % (16 MB)
34 01:35:49.331284 progress 65 % (17 MB)
35 01:35:49.339100 progress 70 % (18 MB)
36 01:35:49.346710 progress 75 % (20 MB)
37 01:35:49.354214 progress 80 % (21 MB)
38 01:35:49.361906 progress 85 % (22 MB)
39 01:35:49.369166 progress 90 % (24 MB)
40 01:35:49.376411 progress 95 % (25 MB)
41 01:35:49.383432 progress 100 % (26 MB)
42 01:35:49.383679 26 MB downloaded in 0.15 s (174.80 MB/s)
43 01:35:49.383844 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:35:49.384085 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:35:49.384172 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:35:49.384255 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:35:49.384393 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:35:49.384462 saving as /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/kernel/Image
50 01:35:49.384523 total size: 54682112 (52 MB)
51 01:35:49.384586 No compression specified
52 01:35:49.385730 progress 0 % (0 MB)
53 01:35:49.399534 progress 5 % (2 MB)
54 01:35:49.413351 progress 10 % (5 MB)
55 01:35:49.427219 progress 15 % (7 MB)
56 01:35:49.440985 progress 20 % (10 MB)
57 01:35:49.455108 progress 25 % (13 MB)
58 01:35:49.468915 progress 30 % (15 MB)
59 01:35:49.482957 progress 35 % (18 MB)
60 01:35:49.496644 progress 40 % (20 MB)
61 01:35:49.510479 progress 45 % (23 MB)
62 01:35:49.524555 progress 50 % (26 MB)
63 01:35:49.538259 progress 55 % (28 MB)
64 01:35:49.552255 progress 60 % (31 MB)
65 01:35:49.566069 progress 65 % (33 MB)
66 01:35:49.580016 progress 70 % (36 MB)
67 01:35:49.593892 progress 75 % (39 MB)
68 01:35:49.607872 progress 80 % (41 MB)
69 01:35:49.621608 progress 85 % (44 MB)
70 01:35:49.635412 progress 90 % (46 MB)
71 01:35:49.649307 progress 95 % (49 MB)
72 01:35:49.662963 progress 100 % (52 MB)
73 01:35:49.663269 52 MB downloaded in 0.28 s (187.09 MB/s)
74 01:35:49.663431 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:35:49.663672 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:35:49.663759 start: 1.3 download-retry (timeout 00:10:00) [common]
78 01:35:49.663844 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 01:35:49.663980 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:35:49.664056 saving as /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/dtb/mt8192-asurada-spherion-r0.dtb
81 01:35:49.664118 total size: 47258 (0 MB)
82 01:35:49.664179 No compression specified
83 01:35:49.665366 progress 69 % (0 MB)
84 01:35:49.665639 progress 100 % (0 MB)
85 01:35:49.665794 0 MB downloaded in 0.00 s (26.92 MB/s)
86 01:35:49.665920 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:35:49.666142 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:35:49.666227 start: 1.4 download-retry (timeout 00:10:00) [common]
90 01:35:49.666311 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 01:35:49.666424 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:35:49.666493 saving as /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/modules/modules.tar
93 01:35:49.666553 total size: 8605984 (8 MB)
94 01:35:49.666616 Using unxz to decompress xz
95 01:35:49.670774 progress 0 % (0 MB)
96 01:35:49.689537 progress 5 % (0 MB)
97 01:35:49.717228 progress 10 % (0 MB)
98 01:35:49.747425 progress 15 % (1 MB)
99 01:35:49.771860 progress 20 % (1 MB)
100 01:35:49.795627 progress 25 % (2 MB)
101 01:35:49.819488 progress 30 % (2 MB)
102 01:35:49.844544 progress 35 % (2 MB)
103 01:35:49.871977 progress 40 % (3 MB)
104 01:35:49.894976 progress 45 % (3 MB)
105 01:35:49.919037 progress 50 % (4 MB)
106 01:35:49.944001 progress 55 % (4 MB)
107 01:35:49.968604 progress 60 % (4 MB)
108 01:35:49.993296 progress 65 % (5 MB)
109 01:35:50.018208 progress 70 % (5 MB)
110 01:35:50.041648 progress 75 % (6 MB)
111 01:35:50.070080 progress 80 % (6 MB)
112 01:35:50.094514 progress 85 % (7 MB)
113 01:35:50.119990 progress 90 % (7 MB)
114 01:35:50.145076 progress 95 % (7 MB)
115 01:35:50.170277 progress 100 % (8 MB)
116 01:35:50.175673 8 MB downloaded in 0.51 s (16.12 MB/s)
117 01:35:50.175921 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:35:50.176192 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:35:50.176286 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:35:50.176381 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:35:50.176464 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:35:50.176553 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:35:50.176784 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx
125 01:35:50.176917 makedir: /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin
126 01:35:50.177022 makedir: /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/tests
127 01:35:50.177122 makedir: /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/results
128 01:35:50.177239 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-add-keys
129 01:35:50.177391 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-add-sources
130 01:35:50.177523 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-background-process-start
131 01:35:50.177655 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-background-process-stop
132 01:35:50.177781 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-common-functions
133 01:35:50.177906 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-echo-ipv4
134 01:35:50.178031 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-install-packages
135 01:35:50.178156 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-installed-packages
136 01:35:50.178279 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-os-build
137 01:35:50.178402 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-probe-channel
138 01:35:50.178533 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-probe-ip
139 01:35:50.178697 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-target-ip
140 01:35:50.178825 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-target-mac
141 01:35:50.178949 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-target-storage
142 01:35:50.179084 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-case
143 01:35:50.179209 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-event
144 01:35:50.179332 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-feedback
145 01:35:50.179456 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-raise
146 01:35:50.179579 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-reference
147 01:35:50.179701 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-runner
148 01:35:50.179824 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-set
149 01:35:50.179948 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-test-shell
150 01:35:50.180074 Updating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-install-packages (oe)
151 01:35:50.180223 Updating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/bin/lava-installed-packages (oe)
152 01:35:50.180353 Creating /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/environment
153 01:35:50.180460 LAVA metadata
154 01:35:50.180533 - LAVA_JOB_ID=14173516
155 01:35:50.180598 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:35:50.180701 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:35:50.180772 skipped lava-vland-overlay
158 01:35:50.180847 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:35:50.180930 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:35:50.180996 skipped lava-multinode-overlay
161 01:35:50.181069 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:35:50.181163 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:35:50.181241 Loading test definitions
164 01:35:50.181407 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:35:50.181480 Using /lava-14173516 at stage 0
166 01:35:50.181786 uuid=14173516_1.5.2.3.1 testdef=None
167 01:35:50.181876 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:35:50.181961 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:35:50.182478 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:35:50.182700 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:35:50.183316 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:35:50.183548 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:35:50.184145 runner path: /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/0/tests/0_v4l2-compliance-uvc test_uuid 14173516_1.5.2.3.1
176 01:35:50.184305 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:35:50.184510 Creating lava-test-runner.conf files
179 01:35:50.184574 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173516/lava-overlay-yxu1wjzx/lava-14173516/0 for stage 0
180 01:35:50.184663 - 0_v4l2-compliance-uvc
181 01:35:50.184763 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:35:50.184848 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:35:50.192017 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:35:50.192122 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:35:50.192209 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:35:50.192294 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:35:50.192380 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:35:51.081173 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:35:51.081602 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:35:51.081718 extracting modules file /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173516/extract-overlay-ramdisk-5mg_17fn/ramdisk
191 01:35:51.301243 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:35:51.301466 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:35:51.301564 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173516/compress-overlay-w9us0qhm/overlay-1.5.2.4.tar.gz to ramdisk
194 01:35:51.301638 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173516/compress-overlay-w9us0qhm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173516/extract-overlay-ramdisk-5mg_17fn/ramdisk
195 01:35:51.308315 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:35:51.308437 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:35:51.308531 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:35:51.308623 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:35:51.308704 Building ramdisk /var/lib/lava/dispatcher/tmp/14173516/extract-overlay-ramdisk-5mg_17fn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173516/extract-overlay-ramdisk-5mg_17fn/ramdisk
200 01:35:52.049014 >> 275894 blocks
201 01:35:56.152752 rename /var/lib/lava/dispatcher/tmp/14173516/extract-overlay-ramdisk-5mg_17fn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/ramdisk/ramdisk.cpio.gz
202 01:35:56.153206 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 01:35:56.153376 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 01:35:56.153481 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 01:35:56.153586 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/kernel/Image']
206 01:36:09.097066 Returned 0 in 12 seconds
207 01:36:09.198028 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/kernel/image.itb
208 01:36:09.802407 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:36:09.802817 output: Created: Wed Jun 5 02:36:09 2024
210 01:36:09.802905 output: Image 0 (kernel-1)
211 01:36:09.802972 output: Description:
212 01:36:09.803034 output: Created: Wed Jun 5 02:36:09 2024
213 01:36:09.803097 output: Type: Kernel Image
214 01:36:09.803161 output: Compression: lzma compressed
215 01:36:09.803224 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
216 01:36:09.803285 output: Architecture: AArch64
217 01:36:09.803345 output: OS: Linux
218 01:36:09.803405 output: Load Address: 0x00000000
219 01:36:09.803465 output: Entry Point: 0x00000000
220 01:36:09.803523 output: Hash algo: crc32
221 01:36:09.803583 output: Hash value: 4c96ec19
222 01:36:09.803639 output: Image 1 (fdt-1)
223 01:36:09.803695 output: Description: mt8192-asurada-spherion-r0
224 01:36:09.803750 output: Created: Wed Jun 5 02:36:09 2024
225 01:36:09.803804 output: Type: Flat Device Tree
226 01:36:09.803858 output: Compression: uncompressed
227 01:36:09.803911 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 01:36:09.803965 output: Architecture: AArch64
229 01:36:09.804018 output: Hash algo: crc32
230 01:36:09.804072 output: Hash value: 0f8e4d2e
231 01:36:09.804125 output: Image 2 (ramdisk-1)
232 01:36:09.804178 output: Description: unavailable
233 01:36:09.804232 output: Created: Wed Jun 5 02:36:09 2024
234 01:36:09.804286 output: Type: RAMDisk Image
235 01:36:09.804339 output: Compression: Unknown Compression
236 01:36:09.804393 output: Data Size: 41204080 Bytes = 40238.36 KiB = 39.30 MiB
237 01:36:09.804447 output: Architecture: AArch64
238 01:36:09.804500 output: OS: Linux
239 01:36:09.804553 output: Load Address: unavailable
240 01:36:09.804606 output: Entry Point: unavailable
241 01:36:09.804659 output: Hash algo: crc32
242 01:36:09.804712 output: Hash value: 71c0ca19
243 01:36:09.804766 output: Default Configuration: 'conf-1'
244 01:36:09.804818 output: Configuration 0 (conf-1)
245 01:36:09.804872 output: Description: mt8192-asurada-spherion-r0
246 01:36:09.804925 output: Kernel: kernel-1
247 01:36:09.804979 output: Init Ramdisk: ramdisk-1
248 01:36:09.805032 output: FDT: fdt-1
249 01:36:09.805084 output: Loadables: kernel-1
250 01:36:09.805138 output:
251 01:36:09.805381 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:36:09.805477 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:36:09.805586 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 01:36:09.805680 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 01:36:09.805760 No LXC device requested
256 01:36:09.805841 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:36:09.805923 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 01:36:09.806000 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:36:09.806069 Checking files for TFTP limit of 4294967296 bytes.
260 01:36:09.806570 end: 1 tftp-deploy (duration 00:00:21) [common]
261 01:36:09.806677 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:36:09.806773 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:36:09.806893 substitutions:
264 01:36:09.806961 - {DTB}: 14173516/tftp-deploy-pbvb5vjh/dtb/mt8192-asurada-spherion-r0.dtb
265 01:36:09.807026 - {INITRD}: 14173516/tftp-deploy-pbvb5vjh/ramdisk/ramdisk.cpio.gz
266 01:36:09.807086 - {KERNEL}: 14173516/tftp-deploy-pbvb5vjh/kernel/Image
267 01:36:09.807144 - {LAVA_MAC}: None
268 01:36:09.807201 - {PRESEED_CONFIG}: None
269 01:36:09.807257 - {PRESEED_LOCAL}: None
270 01:36:09.807312 - {RAMDISK}: 14173516/tftp-deploy-pbvb5vjh/ramdisk/ramdisk.cpio.gz
271 01:36:09.807367 - {ROOT_PART}: None
272 01:36:09.807423 - {ROOT}: None
273 01:36:09.807477 - {SERVER_IP}: 192.168.201.1
274 01:36:09.807532 - {TEE}: None
275 01:36:09.807586 Parsed boot commands:
276 01:36:09.807640 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:36:09.807813 Parsed boot commands: tftpboot 192.168.201.1 14173516/tftp-deploy-pbvb5vjh/kernel/image.itb 14173516/tftp-deploy-pbvb5vjh/kernel/cmdline
278 01:36:09.807902 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:36:09.807987 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:36:09.808079 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:36:09.808164 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:36:09.808233 Not connected, no need to disconnect.
283 01:36:09.808306 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:36:09.808383 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:36:09.808453 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 01:36:09.812091 Setting prompt string to ['lava-test: # ']
287 01:36:09.812446 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:36:09.812548 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:36:09.812650 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:36:09.812744 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:36:09.812920 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 01:36:23.888951 Returned 0 in 14 seconds
293 01:36:23.989625 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 01:36:23.990223 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 01:36:23.990323 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 01:36:23.990411 Setting prompt string to 'Starting depthcharge on Spherion...'
298 01:36:23.990478 Changing prompt to 'Starting depthcharge on Spherion...'
299 01:36:23.990542 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 01:36:23.991101 [Enter `^Ec?' for help]
301 01:36:23.991261
302 01:36:23.991378
303 01:36:23.991442 F0: 102B 0000
304 01:36:23.991506
305 01:36:23.991565 F3: 1001 0000 [0200]
306 01:36:23.991627
307 01:36:23.991686 F3: 1001 0000
308 01:36:23.991747
309 01:36:23.991806 F7: 102D 0000
310 01:36:23.991862
311 01:36:23.991916 F1: 0000 0000
312 01:36:23.991970
313 01:36:23.992024 V0: 0000 0000 [0001]
314 01:36:23.992078
315 01:36:23.992132 00: 0007 8000
316 01:36:23.992189
317 01:36:23.992242 01: 0000 0000
318 01:36:23.992297
319 01:36:23.992350 BP: 0C00 0209 [0000]
320 01:36:23.992404
321 01:36:23.992456 G0: 1182 0000
322 01:36:23.992509
323 01:36:23.992563 EC: 0000 0021 [4000]
324 01:36:23.992616
325 01:36:23.992688 S7: 0000 0000 [0000]
326 01:36:23.992758
327 01:36:23.992811 CC: 0000 0000 [0001]
328 01:36:23.992864
329 01:36:23.992917 T0: 0000 0040 [010F]
330 01:36:23.992970
331 01:36:23.993023 Jump to BL
332 01:36:23.993076
333 01:36:23.993129
334 01:36:23.993199
335 01:36:23.993305 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 01:36:23.993366 ARM64: Exception handlers installed.
337 01:36:23.993420 ARM64: Testing exception
338 01:36:23.993474 ARM64: Done test exception
339 01:36:23.993527 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 01:36:23.993581 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 01:36:23.993636 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 01:36:23.993691 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 01:36:23.993745 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 01:36:23.993799 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 01:36:23.993853 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 01:36:23.993907 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 01:36:23.993960 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 01:36:23.994014 WDT: Last reset was cold boot
349 01:36:23.994067 SPI1(PAD0) initialized at 2873684 Hz
350 01:36:23.994120 SPI5(PAD0) initialized at 992727 Hz
351 01:36:23.994174 VBOOT: Loading verstage.
352 01:36:23.994227 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 01:36:23.994281 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 01:36:23.994358 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 01:36:23.994425 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 01:36:23.994478 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 01:36:23.994532 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 01:36:23.994586 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 01:36:23.994639
360 01:36:23.994692
361 01:36:23.994745 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 01:36:23.994798 ARM64: Exception handlers installed.
363 01:36:23.994851 ARM64: Testing exception
364 01:36:23.994904 ARM64: Done test exception
365 01:36:23.994957 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 01:36:23.995011 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 01:36:23.995065 Probing TPM: . done!
368 01:36:23.995118 TPM ready after 0 ms
369 01:36:23.995171 Connected to device vid:did:rid of 1ae0:0028:00
370 01:36:23.995224 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 01:36:23.995279 Initialized TPM device CR50 revision 0
372 01:36:23.995332 tlcl_send_startup: Startup return code is 0
373 01:36:23.995386 TPM: setup succeeded
374 01:36:23.995439 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 01:36:23.995493 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 01:36:23.995546 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 01:36:23.995600 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:36:23.995654 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 01:36:23.995707 in-header: 03 07 00 00 08 00 00 00
380 01:36:23.995761 in-data: aa e4 47 04 13 02 00 00
381 01:36:23.995814 Chrome EC: UHEPI supported
382 01:36:23.995867 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 01:36:23.995921 in-header: 03 a9 00 00 08 00 00 00
384 01:36:23.995974 in-data: 84 60 60 08 00 00 00 00
385 01:36:23.996028 Phase 1
386 01:36:23.996081 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 01:36:23.996135 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 01:36:23.996188 VB2:vb2_check_recovery() Recovery was requested manually
389 01:36:23.996242 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 01:36:23.996295 Recovery requested (1009000e)
391 01:36:23.996348 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 01:36:23.996401 tlcl_extend: response is 0
393 01:36:23.996455 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 01:36:23.996508 tlcl_extend: response is 0
395 01:36:23.996562 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 01:36:23.996616 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 01:36:23.996669 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 01:36:23.996723
399 01:36:23.996776
400 01:36:23.996828 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 01:36:23.996883 ARM64: Exception handlers installed.
402 01:36:23.996936 ARM64: Testing exception
403 01:36:23.996988 ARM64: Done test exception
404 01:36:23.997041 pmic_efuse_setting: Set efuses in 11 msecs
405 01:36:23.997094 pmwrap_interface_init: Select PMIF_VLD_RDY
406 01:36:23.997148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 01:36:23.997201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 01:36:23.997453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 01:36:23.997518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 01:36:23.997575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 01:36:23.997630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 01:36:23.997723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 01:36:23.997778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 01:36:23.997832 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 01:36:23.997886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 01:36:23.997940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 01:36:23.997993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 01:36:23.998047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 01:36:23.998100 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 01:36:23.998154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 01:36:23.998208 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 01:36:23.998262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 01:36:23.998315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 01:36:23.998369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 01:36:23.998422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 01:36:23.998476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 01:36:23.998530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 01:36:23.998583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 01:36:23.998637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 01:36:23.998690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 01:36:23.998743 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 01:36:23.998796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 01:36:23.998850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 01:36:23.998904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 01:36:23.998957 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 01:36:23.999010 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 01:36:23.999063 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 01:36:23.999116 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 01:36:23.999169 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 01:36:23.999222 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 01:36:23.999275 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 01:36:23.999329 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 01:36:23.999382 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 01:36:23.999436 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 01:36:23.999489 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 01:36:23.999542 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 01:36:23.999595 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 01:36:23.999649 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 01:36:23.999702 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 01:36:23.999755 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 01:36:23.999808 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 01:36:23.999861 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 01:36:23.999914 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 01:36:23.999967 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 01:36:24.000020 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 01:36:24.000073 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 01:36:24.000126 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 01:36:24.000193 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 01:36:24.000249 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 01:36:24.000303 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 01:36:24.000357 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 01:36:24.000411 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 01:36:24.000464 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 01:36:24.000518 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:36:24.000571 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
466 01:36:24.000625 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 01:36:24.000678 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 01:36:24.000732 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 01:36:24.000785 [RTC]rtc_get_frequency_meter,154: input=15, output=852
470 01:36:24.000839 [RTC]rtc_get_frequency_meter,154: input=7, output=723
471 01:36:24.000892 [RTC]rtc_get_frequency_meter,154: input=11, output=788
472 01:36:24.000945 [RTC]rtc_get_frequency_meter,154: input=13, output=820
473 01:36:24.000998 [RTC]rtc_get_frequency_meter,154: input=12, output=804
474 01:36:24.001051 [RTC]rtc_get_frequency_meter,154: input=11, output=787
475 01:36:24.001143 [RTC]rtc_get_frequency_meter,154: input=12, output=804
476 01:36:24.001229 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 01:36:24.001334 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 01:36:24.001581 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 01:36:24.001720 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 01:36:24.001853 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 01:36:24.001984 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 01:36:24.002114 ADC[4]: Raw value=903325 ID=7
483 01:36:24.002265 ADC[3]: Raw value=213916 ID=1
484 01:36:24.002412 RAM Code: 0x71
485 01:36:24.002541 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 01:36:24.002665 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 01:36:24.002741 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 01:36:24.002801 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 01:36:24.002857 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 01:36:24.002912 in-header: 03 07 00 00 08 00 00 00
491 01:36:24.002966 in-data: aa e4 47 04 13 02 00 00
492 01:36:24.003020 Chrome EC: UHEPI supported
493 01:36:24.003074 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 01:36:24.003129 in-header: 03 a9 00 00 08 00 00 00
495 01:36:24.003183 in-data: 84 60 60 08 00 00 00 00
496 01:36:24.003237 MRC: failed to locate region type 0.
497 01:36:24.003290 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 01:36:24.003344 DRAM-K: Running full calibration
499 01:36:24.003398 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 01:36:24.003451 header.status = 0x0
501 01:36:24.003505 header.version = 0x6 (expected: 0x6)
502 01:36:24.003557 header.size = 0xd00 (expected: 0xd00)
503 01:36:24.003610 header.flags = 0x0
504 01:36:24.003663 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 01:36:24.003717 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 01:36:24.003770 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 01:36:24.003824 dram_init: ddr_geometry: 2
508 01:36:24.003877 [EMI] MDL number = 2
509 01:36:24.003930 [EMI] Get MDL freq = 0
510 01:36:24.003983 dram_init: ddr_type: 0
511 01:36:24.004036 is_discrete_lpddr4: 1
512 01:36:24.004089 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 01:36:24.004142
514 01:36:24.004195
515 01:36:24.004248 [Bian_co] ETT version 0.0.0.1
516 01:36:24.004302 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 01:36:24.004355
518 01:36:24.004408 dramc_set_vcore_voltage set vcore to 650000
519 01:36:24.004499 Read voltage for 800, 4
520 01:36:24.004553 Vio18 = 0
521 01:36:24.004606 Vcore = 650000
522 01:36:24.004659 Vdram = 0
523 01:36:24.004713 Vddq = 0
524 01:36:24.004766 Vmddr = 0
525 01:36:24.004819 dram_init: config_dvfs: 1
526 01:36:24.004872 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 01:36:24.004925 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 01:36:24.004979 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 01:36:24.005032 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 01:36:24.005086 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 01:36:24.005139 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 01:36:24.005192 MEM_TYPE=3, freq_sel=18
533 01:36:24.005282 sv_algorithm_assistance_LP4_1600
534 01:36:24.005355 ============ PULL DRAM RESETB DOWN ============
535 01:36:24.005428 ========== PULL DRAM RESETB DOWN end =========
536 01:36:24.005500 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 01:36:24.005554 ===================================
538 01:36:24.005608 LPDDR4 DRAM CONFIGURATION
539 01:36:24.005661 ===================================
540 01:36:24.005714 EX_ROW_EN[0] = 0x0
541 01:36:24.005783 EX_ROW_EN[1] = 0x0
542 01:36:24.005850 LP4Y_EN = 0x0
543 01:36:24.005932 WORK_FSP = 0x0
544 01:36:24.006015 WL = 0x2
545 01:36:24.006068 RL = 0x2
546 01:36:24.006121 BL = 0x2
547 01:36:24.006174 RPST = 0x0
548 01:36:24.006248 RD_PRE = 0x0
549 01:36:24.006333 WR_PRE = 0x1
550 01:36:24.006417 WR_PST = 0x0
551 01:36:24.006501 DBI_WR = 0x0
552 01:36:24.006555 DBI_RD = 0x0
553 01:36:24.006610 OTF = 0x1
554 01:36:24.006664 ===================================
555 01:36:24.006719 ===================================
556 01:36:24.006773 ANA top config
557 01:36:24.006827 ===================================
558 01:36:24.006882 DLL_ASYNC_EN = 0
559 01:36:24.006936 ALL_SLAVE_EN = 1
560 01:36:24.006990 NEW_RANK_MODE = 1
561 01:36:24.007045 DLL_IDLE_MODE = 1
562 01:36:24.007099 LP45_APHY_COMB_EN = 1
563 01:36:24.007153 TX_ODT_DIS = 1
564 01:36:24.007208 NEW_8X_MODE = 1
565 01:36:24.007264 ===================================
566 01:36:24.007318 ===================================
567 01:36:24.007373 data_rate = 1600
568 01:36:24.007427 CKR = 1
569 01:36:24.007483 DQ_P2S_RATIO = 8
570 01:36:24.007537 ===================================
571 01:36:24.007591 CA_P2S_RATIO = 8
572 01:36:24.007646 DQ_CA_OPEN = 0
573 01:36:24.007701 DQ_SEMI_OPEN = 0
574 01:36:24.007755 CA_SEMI_OPEN = 0
575 01:36:24.007810 CA_FULL_RATE = 0
576 01:36:24.007864 DQ_CKDIV4_EN = 1
577 01:36:24.007918 CA_CKDIV4_EN = 1
578 01:36:24.007972 CA_PREDIV_EN = 0
579 01:36:24.008026 PH8_DLY = 0
580 01:36:24.008080 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 01:36:24.008134 DQ_AAMCK_DIV = 4
582 01:36:24.008189 CA_AAMCK_DIV = 4
583 01:36:24.008243 CA_ADMCK_DIV = 4
584 01:36:24.008297 DQ_TRACK_CA_EN = 0
585 01:36:24.008351 CA_PICK = 800
586 01:36:24.008405 CA_MCKIO = 800
587 01:36:24.008459 MCKIO_SEMI = 0
588 01:36:24.008514 PLL_FREQ = 3068
589 01:36:24.008568 DQ_UI_PI_RATIO = 32
590 01:36:24.008623 CA_UI_PI_RATIO = 0
591 01:36:24.008677 ===================================
592 01:36:24.008730 ===================================
593 01:36:24.008785 memory_type:LPDDR4
594 01:36:24.008839 GP_NUM : 10
595 01:36:24.008893 SRAM_EN : 1
596 01:36:24.008947 MD32_EN : 0
597 01:36:24.009208 ===================================
598 01:36:24.009365 [ANA_INIT] >>>>>>>>>>>>>>
599 01:36:24.009506 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 01:36:24.009675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 01:36:24.009809 ===================================
602 01:36:24.009901 data_rate = 1600,PCW = 0X7600
603 01:36:24.009959 ===================================
604 01:36:24.010015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 01:36:24.010071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 01:36:24.010127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:36:24.010181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 01:36:24.010236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 01:36:24.010289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:36:24.010343 [ANA_INIT] flow start
611 01:36:24.010396 [ANA_INIT] PLL >>>>>>>>
612 01:36:24.010449 [ANA_INIT] PLL <<<<<<<<
613 01:36:24.010503 [ANA_INIT] MIDPI >>>>>>>>
614 01:36:24.010556 [ANA_INIT] MIDPI <<<<<<<<
615 01:36:24.010610 [ANA_INIT] DLL >>>>>>>>
616 01:36:24.010663 [ANA_INIT] flow end
617 01:36:24.010717 ============ LP4 DIFF to SE enter ============
618 01:36:24.010771 ============ LP4 DIFF to SE exit ============
619 01:36:24.010824 [ANA_INIT] <<<<<<<<<<<<<
620 01:36:24.010878 [Flow] Enable top DCM control >>>>>
621 01:36:24.010932 [Flow] Enable top DCM control <<<<<
622 01:36:24.010985 Enable DLL master slave shuffle
623 01:36:24.011039 ==============================================================
624 01:36:24.011093 Gating Mode config
625 01:36:24.011147 ==============================================================
626 01:36:24.011201 Config description:
627 01:36:24.011254 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 01:36:24.011308 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 01:36:24.011362 SELPH_MODE 0: By rank 1: By Phase
630 01:36:24.011415 ==============================================================
631 01:36:24.011468 GAT_TRACK_EN = 1
632 01:36:24.011522 RX_GATING_MODE = 2
633 01:36:24.011592 RX_GATING_TRACK_MODE = 2
634 01:36:24.011647 SELPH_MODE = 1
635 01:36:24.011700 PICG_EARLY_EN = 1
636 01:36:24.011754 VALID_LAT_VALUE = 1
637 01:36:24.011807 ==============================================================
638 01:36:24.011860 Enter into Gating configuration >>>>
639 01:36:24.011914 Exit from Gating configuration <<<<
640 01:36:24.011967 Enter into DVFS_PRE_config >>>>>
641 01:36:24.012021 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 01:36:24.012077 Exit from DVFS_PRE_config <<<<<
643 01:36:24.012131 Enter into PICG configuration >>>>
644 01:36:24.012184 Exit from PICG configuration <<<<
645 01:36:24.012238 [RX_INPUT] configuration >>>>>
646 01:36:24.012291 [RX_INPUT] configuration <<<<<
647 01:36:24.012344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 01:36:24.012398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 01:36:24.012451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 01:36:24.012505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 01:36:24.012559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 01:36:24.012612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 01:36:24.012665 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 01:36:24.012719 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 01:36:24.012773 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 01:36:24.012826 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 01:36:24.012879 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 01:36:24.012933 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 01:36:24.012987 ===================================
660 01:36:24.013040 LPDDR4 DRAM CONFIGURATION
661 01:36:24.013093 ===================================
662 01:36:24.013146 EX_ROW_EN[0] = 0x0
663 01:36:24.013199 EX_ROW_EN[1] = 0x0
664 01:36:24.013252 LP4Y_EN = 0x0
665 01:36:24.013340 WORK_FSP = 0x0
666 01:36:24.013393 WL = 0x2
667 01:36:24.013447 RL = 0x2
668 01:36:24.013499 BL = 0x2
669 01:36:24.013552 RPST = 0x0
670 01:36:24.013673 RD_PRE = 0x0
671 01:36:24.013761 WR_PRE = 0x1
672 01:36:24.013814 WR_PST = 0x0
673 01:36:24.013867 DBI_WR = 0x0
674 01:36:24.013920 DBI_RD = 0x0
675 01:36:24.013974 OTF = 0x1
676 01:36:24.014027 ===================================
677 01:36:24.014081 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 01:36:24.014135 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 01:36:24.014188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 01:36:24.014242 ===================================
681 01:36:24.014296 LPDDR4 DRAM CONFIGURATION
682 01:36:24.014349 ===================================
683 01:36:24.014403 EX_ROW_EN[0] = 0x10
684 01:36:24.014456 EX_ROW_EN[1] = 0x0
685 01:36:24.014509 LP4Y_EN = 0x0
686 01:36:24.014562 WORK_FSP = 0x0
687 01:36:24.014614 WL = 0x2
688 01:36:24.014667 RL = 0x2
689 01:36:24.014720 BL = 0x2
690 01:36:24.014773 RPST = 0x0
691 01:36:24.014826 RD_PRE = 0x0
692 01:36:24.014878 WR_PRE = 0x1
693 01:36:24.014932 WR_PST = 0x0
694 01:36:24.014985 DBI_WR = 0x0
695 01:36:24.015037 DBI_RD = 0x0
696 01:36:24.015090 OTF = 0x1
697 01:36:24.015143 ===================================
698 01:36:24.015196 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 01:36:24.015250 nWR fixed to 40
700 01:36:24.015305 [ModeRegInit_LP4] CH0 RK0
701 01:36:24.015358 [ModeRegInit_LP4] CH0 RK1
702 01:36:24.015411 [ModeRegInit_LP4] CH1 RK0
703 01:36:24.015464 [ModeRegInit_LP4] CH1 RK1
704 01:36:24.015517 match AC timing 13
705 01:36:24.015571 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 01:36:24.015844 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 01:36:24.015932 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 01:36:24.015989 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 01:36:24.016045 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 01:36:24.016139 [EMI DOE] emi_dcm 0
711 01:36:24.016193 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 01:36:24.016246 ==
713 01:36:24.016301 Dram Type= 6, Freq= 0, CH_0, rank 0
714 01:36:24.016354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 01:36:24.016408 ==
716 01:36:24.016462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 01:36:24.016516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 01:36:24.016571 [CA 0] Center 37 (7~68) winsize 62
719 01:36:24.016624 [CA 1] Center 37 (7~68) winsize 62
720 01:36:24.016678 [CA 2] Center 34 (4~65) winsize 62
721 01:36:24.016731 [CA 3] Center 34 (4~65) winsize 62
722 01:36:24.016784 [CA 4] Center 33 (3~64) winsize 62
723 01:36:24.016837 [CA 5] Center 33 (3~64) winsize 62
724 01:36:24.016890
725 01:36:24.016943 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 01:36:24.016996
727 01:36:24.017048 [CATrainingPosCal] consider 1 rank data
728 01:36:24.017101 u2DelayCellTimex100 = 270/100 ps
729 01:36:24.017154 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 01:36:24.017208 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 01:36:24.017284 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 01:36:24.017354 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 01:36:24.017408 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 01:36:24.017461 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 01:36:24.017514
736 01:36:24.017566 CA PerBit enable=1, Macro0, CA PI delay=33
737 01:36:24.017620
738 01:36:24.017672 [CBTSetCACLKResult] CA Dly = 33
739 01:36:24.017743 CS Dly: 5 (0~36)
740 01:36:24.017810 ==
741 01:36:24.017864 Dram Type= 6, Freq= 0, CH_0, rank 1
742 01:36:24.017917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 01:36:24.017971 ==
744 01:36:24.018025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 01:36:24.018079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 01:36:24.018133 [CA 0] Center 38 (7~69) winsize 63
747 01:36:24.018186 [CA 1] Center 37 (7~68) winsize 62
748 01:36:24.018240 [CA 2] Center 35 (4~66) winsize 63
749 01:36:24.018292 [CA 3] Center 35 (4~66) winsize 63
750 01:36:24.018345 [CA 4] Center 34 (3~65) winsize 63
751 01:36:24.018398 [CA 5] Center 33 (3~64) winsize 62
752 01:36:24.018451
753 01:36:24.018505 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 01:36:24.018558
755 01:36:24.018611 [CATrainingPosCal] consider 2 rank data
756 01:36:24.018665 u2DelayCellTimex100 = 270/100 ps
757 01:36:24.018718 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 01:36:24.018771 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 01:36:24.018824 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 01:36:24.018877 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 01:36:24.018931 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 01:36:24.018984 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 01:36:24.019037
764 01:36:24.019090 CA PerBit enable=1, Macro0, CA PI delay=33
765 01:36:24.019143
766 01:36:24.019195 [CBTSetCACLKResult] CA Dly = 33
767 01:36:24.019248 CS Dly: 6 (0~38)
768 01:36:24.019301
769 01:36:24.019353 ----->DramcWriteLeveling(PI) begin...
770 01:36:24.019409 ==
771 01:36:24.019463 Dram Type= 6, Freq= 0, CH_0, rank 0
772 01:36:24.019516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 01:36:24.019571 ==
774 01:36:24.019624 Write leveling (Byte 0): 29 => 29
775 01:36:24.019678 Write leveling (Byte 1): 27 => 27
776 01:36:24.019731 DramcWriteLeveling(PI) end<-----
777 01:36:24.019784
778 01:36:24.019837 ==
779 01:36:24.019890 Dram Type= 6, Freq= 0, CH_0, rank 0
780 01:36:24.019943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 01:36:24.019997 ==
782 01:36:24.020050 [Gating] SW mode calibration
783 01:36:24.020103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 01:36:24.020157 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 01:36:24.020210 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 01:36:24.020263 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 01:36:24.020316 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 01:36:24.020370 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 01:36:24.020422 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:36:24.020475 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:36:24.020528 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:36:24.020581 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:36:24.020634 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:36:24.020687 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:36:24.020741 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:36:24.020794 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:36:24.020846 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:36:24.020899 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:36:24.020952 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:36:24.021005 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:36:24.021059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:36:24.021112 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
803 01:36:24.021166 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 01:36:24.021237 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 01:36:24.021310 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:36:24.021363 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:36:24.021417 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:36:24.021470 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:36:24.021523 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:36:24.021577 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 01:36:24.021630 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
812 01:36:24.021682 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
813 01:36:24.021736 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 01:36:24.021983 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 01:36:24.022116 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 01:36:24.022247 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 01:36:24.022376 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 01:36:24.022505 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)
819 01:36:24.022635 0 10 8 | B1->B0 | 3232 2828 | 1 0 | (1 1) (1 0)
820 01:36:24.022763 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
821 01:36:24.022893 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 01:36:24.023023 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:36:24.023092 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:36:24.023149 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:36:24.023221 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:36:24.023312 0 11 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
827 01:36:24.023380 0 11 8 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
828 01:36:24.023435 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
829 01:36:24.023489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 01:36:24.023542 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 01:36:24.023596 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 01:36:24.023673 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 01:36:24.023794 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 01:36:24.023861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 01:36:24.023915 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 01:36:24.023968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 01:36:24.024020 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:36:24.024073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:36:24.024126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:36:24.024180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:36:24.024233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:36:24.024286 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:36:24.024340 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:36:24.024393 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:36:24.024446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:36:24.024500 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:36:24.024553 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:36:24.024606 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:36:24.024659 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:36:24.024712 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:36:24.024765 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 01:36:24.024818 Total UI for P1: 0, mck2ui 16
853 01:36:24.024872 best dqsien dly found for B0: ( 0, 14, 6)
854 01:36:24.024926 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 01:36:24.024979 Total UI for P1: 0, mck2ui 16
856 01:36:24.025032 best dqsien dly found for B1: ( 0, 14, 8)
857 01:36:24.025086 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 01:36:24.025140 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 01:36:24.025210
860 01:36:24.025273 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 01:36:24.025343 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 01:36:24.025396 [Gating] SW calibration Done
863 01:36:24.025450 ==
864 01:36:24.025504 Dram Type= 6, Freq= 0, CH_0, rank 0
865 01:36:24.025558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 01:36:24.025612 ==
867 01:36:24.025666 RX Vref Scan: 0
868 01:36:24.025720
869 01:36:24.025773 RX Vref 0 -> 0, step: 1
870 01:36:24.025826
871 01:36:24.025880 RX Delay -130 -> 252, step: 16
872 01:36:24.025933 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 01:36:24.025988 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 01:36:24.026041 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 01:36:24.026094 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 01:36:24.026147 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 01:36:24.026200 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 01:36:24.026253 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 01:36:24.026306 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 01:36:24.026359 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 01:36:24.026412 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 01:36:24.026465 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 01:36:24.026518 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 01:36:24.026571 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 01:36:24.026624 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 01:36:24.026678 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 01:36:24.026730 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 01:36:24.026784 ==
889 01:36:24.026837 Dram Type= 6, Freq= 0, CH_0, rank 0
890 01:36:24.026891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 01:36:24.026945 ==
892 01:36:24.026998 DQS Delay:
893 01:36:24.027051 DQS0 = 0, DQS1 = 0
894 01:36:24.027104 DQM Delay:
895 01:36:24.027157 DQM0 = 89, DQM1 = 74
896 01:36:24.027211 DQ Delay:
897 01:36:24.027264 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
898 01:36:24.027317 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 01:36:24.027370 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
900 01:36:24.027423 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 01:36:24.027476
902 01:36:24.027529
903 01:36:24.027582 ==
904 01:36:24.027635 Dram Type= 6, Freq= 0, CH_0, rank 0
905 01:36:24.027689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 01:36:24.027742 ==
907 01:36:24.027795
908 01:36:24.027848
909 01:36:24.027900 TX Vref Scan disable
910 01:36:24.027954 == TX Byte 0 ==
911 01:36:24.028007 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
912 01:36:24.028061 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
913 01:36:24.028114 == TX Byte 1 ==
914 01:36:24.028167 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
915 01:36:24.028220 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
916 01:36:24.028274 ==
917 01:36:24.028327 Dram Type= 6, Freq= 0, CH_0, rank 0
918 01:36:24.028380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 01:36:24.028434 ==
920 01:36:24.028487 TX Vref=22, minBit 1, minWin=26, winSum=438
921 01:36:24.028542 TX Vref=24, minBit 0, minWin=27, winSum=443
922 01:36:24.028801 TX Vref=26, minBit 3, minWin=27, winSum=446
923 01:36:24.028935 TX Vref=28, minBit 1, minWin=27, winSum=446
924 01:36:24.029067 TX Vref=30, minBit 2, minWin=27, winSum=447
925 01:36:24.029198 TX Vref=32, minBit 1, minWin=27, winSum=444
926 01:36:24.029375 [TxChooseVref] Worse bit 2, Min win 27, Win sum 447, Final Vref 30
927 01:36:24.029441
928 01:36:24.029499 Final TX Range 1 Vref 30
929 01:36:24.029555
930 01:36:24.029610 ==
931 01:36:24.029664 Dram Type= 6, Freq= 0, CH_0, rank 0
932 01:36:24.029718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 01:36:24.029773 ==
934 01:36:24.029826
935 01:36:24.029880
936 01:36:24.029933 TX Vref Scan disable
937 01:36:24.029986 == TX Byte 0 ==
938 01:36:24.030040 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
939 01:36:24.030094 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
940 01:36:24.030147 == TX Byte 1 ==
941 01:36:24.030200 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
942 01:36:24.030253 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
943 01:36:24.030310
944 01:36:24.030364 [DATLAT]
945 01:36:24.030418 Freq=800, CH0 RK0
946 01:36:24.030472
947 01:36:24.030525 DATLAT Default: 0xa
948 01:36:24.030578 0, 0xFFFF, sum = 0
949 01:36:24.030633 1, 0xFFFF, sum = 0
950 01:36:24.030688 2, 0xFFFF, sum = 0
951 01:36:24.030742 3, 0xFFFF, sum = 0
952 01:36:24.030795 4, 0xFFFF, sum = 0
953 01:36:24.030849 5, 0xFFFF, sum = 0
954 01:36:24.030903 6, 0xFFFF, sum = 0
955 01:36:24.030957 7, 0xFFFF, sum = 0
956 01:36:24.031011 8, 0xFFFF, sum = 0
957 01:36:24.031066 9, 0x0, sum = 1
958 01:36:24.031120 10, 0x0, sum = 2
959 01:36:24.031173 11, 0x0, sum = 3
960 01:36:24.031228 12, 0x0, sum = 4
961 01:36:24.031281 best_step = 10
962 01:36:24.031335
963 01:36:24.031387 ==
964 01:36:24.031441 Dram Type= 6, Freq= 0, CH_0, rank 0
965 01:36:24.031494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 01:36:24.031549 ==
967 01:36:24.031602 RX Vref Scan: 1
968 01:36:24.031656
969 01:36:24.031709 Set Vref Range= 32 -> 127
970 01:36:24.031762
971 01:36:24.031815 RX Vref 32 -> 127, step: 1
972 01:36:24.031868
973 01:36:24.031921 RX Delay -111 -> 252, step: 8
974 01:36:24.031975
975 01:36:24.032028 Set Vref, RX VrefLevel [Byte0]: 32
976 01:36:24.032081 [Byte1]: 32
977 01:36:24.032135
978 01:36:24.032188 Set Vref, RX VrefLevel [Byte0]: 33
979 01:36:24.032240 [Byte1]: 33
980 01:36:24.032293
981 01:36:24.032347 Set Vref, RX VrefLevel [Byte0]: 34
982 01:36:24.032400 [Byte1]: 34
983 01:36:24.032453
984 01:36:24.032507 Set Vref, RX VrefLevel [Byte0]: 35
985 01:36:24.032560 [Byte1]: 35
986 01:36:24.032613
987 01:36:24.032666 Set Vref, RX VrefLevel [Byte0]: 36
988 01:36:24.032719 [Byte1]: 36
989 01:36:24.032772
990 01:36:24.032844 Set Vref, RX VrefLevel [Byte0]: 37
991 01:36:24.032912 [Byte1]: 37
992 01:36:24.032965
993 01:36:24.033018 Set Vref, RX VrefLevel [Byte0]: 38
994 01:36:24.033072 [Byte1]: 38
995 01:36:24.033125
996 01:36:24.033179 Set Vref, RX VrefLevel [Byte0]: 39
997 01:36:24.033232 [Byte1]: 39
998 01:36:24.033324
999 01:36:24.033379 Set Vref, RX VrefLevel [Byte0]: 40
1000 01:36:24.033432 [Byte1]: 40
1001 01:36:24.033485
1002 01:36:24.033539 Set Vref, RX VrefLevel [Byte0]: 41
1003 01:36:24.033592 [Byte1]: 41
1004 01:36:24.033645
1005 01:36:24.033699 Set Vref, RX VrefLevel [Byte0]: 42
1006 01:36:24.033752 [Byte1]: 42
1007 01:36:24.033805
1008 01:36:24.033858 Set Vref, RX VrefLevel [Byte0]: 43
1009 01:36:24.033911 [Byte1]: 43
1010 01:36:24.033964
1011 01:36:24.034017 Set Vref, RX VrefLevel [Byte0]: 44
1012 01:36:24.034071 [Byte1]: 44
1013 01:36:24.034124
1014 01:36:24.034177 Set Vref, RX VrefLevel [Byte0]: 45
1015 01:36:24.034231 [Byte1]: 45
1016 01:36:24.034284
1017 01:36:24.034338 Set Vref, RX VrefLevel [Byte0]: 46
1018 01:36:24.034392 [Byte1]: 46
1019 01:36:24.034446
1020 01:36:24.034523 Set Vref, RX VrefLevel [Byte0]: 47
1021 01:36:24.034593 [Byte1]: 47
1022 01:36:24.034647
1023 01:36:24.034700 Set Vref, RX VrefLevel [Byte0]: 48
1024 01:36:24.034753 [Byte1]: 48
1025 01:36:24.034812
1026 01:36:24.034868 Set Vref, RX VrefLevel [Byte0]: 49
1027 01:36:24.034922 [Byte1]: 49
1028 01:36:24.034976
1029 01:36:24.035029 Set Vref, RX VrefLevel [Byte0]: 50
1030 01:36:24.035083 [Byte1]: 50
1031 01:36:24.035136
1032 01:36:24.035189 Set Vref, RX VrefLevel [Byte0]: 51
1033 01:36:24.035242 [Byte1]: 51
1034 01:36:24.035306
1035 01:36:24.035362 Set Vref, RX VrefLevel [Byte0]: 52
1036 01:36:24.035415 [Byte1]: 52
1037 01:36:24.035468
1038 01:36:24.035521 Set Vref, RX VrefLevel [Byte0]: 53
1039 01:36:24.035574 [Byte1]: 53
1040 01:36:24.035626
1041 01:36:24.035679 Set Vref, RX VrefLevel [Byte0]: 54
1042 01:36:24.035731 [Byte1]: 54
1043 01:36:24.035784
1044 01:36:24.035836 Set Vref, RX VrefLevel [Byte0]: 55
1045 01:36:24.035889 [Byte1]: 55
1046 01:36:24.035942
1047 01:36:24.035994 Set Vref, RX VrefLevel [Byte0]: 56
1048 01:36:24.036048 [Byte1]: 56
1049 01:36:24.036100
1050 01:36:24.036153 Set Vref, RX VrefLevel [Byte0]: 57
1051 01:36:24.036206 [Byte1]: 57
1052 01:36:24.036258
1053 01:36:24.036310 Set Vref, RX VrefLevel [Byte0]: 58
1054 01:36:24.036363 [Byte1]: 58
1055 01:36:24.036416
1056 01:36:24.036468 Set Vref, RX VrefLevel [Byte0]: 59
1057 01:36:24.036521 [Byte1]: 59
1058 01:36:24.036573
1059 01:36:24.036626 Set Vref, RX VrefLevel [Byte0]: 60
1060 01:36:24.036678 [Byte1]: 60
1061 01:36:24.036762
1062 01:36:24.036813 Set Vref, RX VrefLevel [Byte0]: 61
1063 01:36:24.036866 [Byte1]: 61
1064 01:36:24.036918
1065 01:36:24.036971 Set Vref, RX VrefLevel [Byte0]: 62
1066 01:36:24.037023 [Byte1]: 62
1067 01:36:24.037076
1068 01:36:24.037129 Set Vref, RX VrefLevel [Byte0]: 63
1069 01:36:24.037182 [Byte1]: 63
1070 01:36:24.037234
1071 01:36:24.037311 Set Vref, RX VrefLevel [Byte0]: 64
1072 01:36:24.037378 [Byte1]: 64
1073 01:36:24.037431
1074 01:36:24.037483 Set Vref, RX VrefLevel [Byte0]: 65
1075 01:36:24.037535 [Byte1]: 65
1076 01:36:24.037588
1077 01:36:24.037640 Set Vref, RX VrefLevel [Byte0]: 66
1078 01:36:24.037693 [Byte1]: 66
1079 01:36:24.037745
1080 01:36:24.037797 Set Vref, RX VrefLevel [Byte0]: 67
1081 01:36:24.037850 [Byte1]: 67
1082 01:36:24.037903
1083 01:36:24.037955 Set Vref, RX VrefLevel [Byte0]: 68
1084 01:36:24.038008 [Byte1]: 68
1085 01:36:24.038060
1086 01:36:24.038113 Set Vref, RX VrefLevel [Byte0]: 69
1087 01:36:24.038165 [Byte1]: 69
1088 01:36:24.038218
1089 01:36:24.038270 Set Vref, RX VrefLevel [Byte0]: 70
1090 01:36:24.038517 [Byte1]: 70
1091 01:36:24.038652
1092 01:36:24.038780 Set Vref, RX VrefLevel [Byte0]: 71
1093 01:36:24.038909 [Byte1]: 71
1094 01:36:24.039036
1095 01:36:24.039144 Set Vref, RX VrefLevel [Byte0]: 72
1096 01:36:24.039201 [Byte1]: 72
1097 01:36:24.039255
1098 01:36:24.039309 Set Vref, RX VrefLevel [Byte0]: 73
1099 01:36:24.039393 [Byte1]: 73
1100 01:36:24.039447
1101 01:36:24.039499 Final RX Vref Byte 0 = 57 to rank0
1102 01:36:24.039554 Final RX Vref Byte 1 = 56 to rank0
1103 01:36:24.039607 Final RX Vref Byte 0 = 57 to rank1
1104 01:36:24.039661 Final RX Vref Byte 1 = 56 to rank1==
1105 01:36:24.039715 Dram Type= 6, Freq= 0, CH_0, rank 0
1106 01:36:24.039768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1107 01:36:24.039822 ==
1108 01:36:24.039875 DQS Delay:
1109 01:36:24.039927 DQS0 = 0, DQS1 = 0
1110 01:36:24.039980 DQM Delay:
1111 01:36:24.040032 DQM0 = 87, DQM1 = 75
1112 01:36:24.040085 DQ Delay:
1113 01:36:24.040138 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1114 01:36:24.040191 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1115 01:36:24.040243 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1116 01:36:24.040296 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1117 01:36:24.040349
1118 01:36:24.040401
1119 01:36:24.040454 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a23, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1120 01:36:24.040508 CH0 RK0: MR19=606, MR18=2A23
1121 01:36:24.040562 CH0_RK0: MR19=0x606, MR18=0x2A23, DQSOSC=399, MR23=63, INC=92, DEC=61
1122 01:36:24.040615
1123 01:36:24.040668 ----->DramcWriteLeveling(PI) begin...
1124 01:36:24.040721 ==
1125 01:36:24.040775 Dram Type= 6, Freq= 0, CH_0, rank 1
1126 01:36:24.040828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 01:36:24.040882 ==
1128 01:36:24.040934 Write leveling (Byte 0): 32 => 32
1129 01:36:24.040988 Write leveling (Byte 1): 26 => 26
1130 01:36:24.041040 DramcWriteLeveling(PI) end<-----
1131 01:36:24.041093
1132 01:36:24.041162 ==
1133 01:36:24.041215 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 01:36:24.041278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 01:36:24.041346 ==
1136 01:36:24.041400 [Gating] SW mode calibration
1137 01:36:24.041453 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1138 01:36:24.041507 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1139 01:36:24.041561 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1140 01:36:24.041655 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1141 01:36:24.041708 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1142 01:36:24.041761 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 01:36:24.041814 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 01:36:24.041867 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 01:36:24.041920 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 01:36:24.041972 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 01:36:24.042025 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 01:36:24.042117 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 01:36:24.042170 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 01:36:24.042223 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 01:36:24.042276 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 01:36:24.042328 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:36:24.042380 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:36:24.042451 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:36:24.042517 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1156 01:36:24.042570 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1157 01:36:24.042623 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1158 01:36:24.042676 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:36:24.042729 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:36:24.042782 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:36:24.042834 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:36:24.042887 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:36:24.042940 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:36:24.042993 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1165 01:36:24.043045 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1166 01:36:24.043098 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1167 01:36:24.043151 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 01:36:24.043204 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 01:36:24.043257 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 01:36:24.043309 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 01:36:24.043362 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 01:36:24.043415 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
1173 01:36:24.043467 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
1174 01:36:24.043520 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 01:36:24.043573 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:36:24.043626 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:36:24.043679 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:36:24.043732 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:36:24.043785 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 01:36:24.043837 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1181 01:36:24.043890 0 11 8 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1182 01:36:24.043943 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1183 01:36:24.043996 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 01:36:24.044049 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 01:36:24.044102 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 01:36:24.044155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 01:36:24.044208 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 01:36:24.044260 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1189 01:36:24.044313 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1190 01:36:24.044365 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 01:36:24.044611 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 01:36:24.044742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 01:36:24.044870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 01:36:24.044998 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 01:36:24.045126 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 01:36:24.045216 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 01:36:24.045350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 01:36:24.045456 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 01:36:24.045543 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 01:36:24.045612 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:36:24.045665 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:36:24.045719 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:36:24.045772 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:36:24.045825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1205 01:36:24.045878 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 01:36:24.045930 Total UI for P1: 0, mck2ui 16
1207 01:36:24.045984 best dqsien dly found for B0: ( 0, 14, 4)
1208 01:36:24.046068 Total UI for P1: 0, mck2ui 16
1209 01:36:24.046121 best dqsien dly found for B1: ( 0, 14, 4)
1210 01:36:24.046174 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1211 01:36:24.046227 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1212 01:36:24.046280
1213 01:36:24.046332 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1214 01:36:24.046385 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1215 01:36:24.046438 [Gating] SW calibration Done
1216 01:36:24.046491 ==
1217 01:36:24.046544 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 01:36:24.046598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 01:36:24.046652 ==
1220 01:36:24.046705 RX Vref Scan: 0
1221 01:36:24.046757
1222 01:36:24.046809 RX Vref 0 -> 0, step: 1
1223 01:36:24.046861
1224 01:36:24.046914 RX Delay -130 -> 252, step: 16
1225 01:36:24.046967 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1226 01:36:24.047020 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1227 01:36:24.047073 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1228 01:36:24.047150 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1229 01:36:24.047223 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1230 01:36:24.047276 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1231 01:36:24.047329 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1232 01:36:24.047381 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1233 01:36:24.047435 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1234 01:36:24.047578 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1235 01:36:24.047630 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1236 01:36:24.047683 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1237 01:36:24.047736 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1238 01:36:24.047789 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1239 01:36:24.047841 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1240 01:36:24.047894 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1241 01:36:24.047947 ==
1242 01:36:24.048000 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 01:36:24.048053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 01:36:24.048106 ==
1245 01:36:24.048159 DQS Delay:
1246 01:36:24.048212 DQS0 = 0, DQS1 = 0
1247 01:36:24.048264 DQM Delay:
1248 01:36:24.048317 DQM0 = 89, DQM1 = 78
1249 01:36:24.048370 DQ Delay:
1250 01:36:24.048422 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1251 01:36:24.048476 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1252 01:36:24.048529 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1253 01:36:24.048582 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1254 01:36:24.048635
1255 01:36:24.048687
1256 01:36:24.048739 ==
1257 01:36:24.048791 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 01:36:24.048845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 01:36:24.048898 ==
1260 01:36:24.048950
1261 01:36:24.049003
1262 01:36:24.049055 TX Vref Scan disable
1263 01:36:24.049108 == TX Byte 0 ==
1264 01:36:24.049161 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1265 01:36:24.049213 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1266 01:36:24.049293 == TX Byte 1 ==
1267 01:36:24.049362 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1268 01:36:24.049416 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1269 01:36:24.049468 ==
1270 01:36:24.049521 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 01:36:24.049574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 01:36:24.049637 ==
1273 01:36:24.049703 TX Vref=22, minBit 1, minWin=27, winSum=440
1274 01:36:24.049790 TX Vref=24, minBit 1, minWin=27, winSum=444
1275 01:36:24.049847 TX Vref=26, minBit 1, minWin=27, winSum=447
1276 01:36:24.049901 TX Vref=28, minBit 2, minWin=27, winSum=452
1277 01:36:24.049954 TX Vref=30, minBit 1, minWin=27, winSum=448
1278 01:36:24.050008 TX Vref=32, minBit 1, minWin=27, winSum=449
1279 01:36:24.050061 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 28
1280 01:36:24.050130
1281 01:36:24.050199 Final TX Range 1 Vref 28
1282 01:36:24.050252
1283 01:36:24.050305 ==
1284 01:36:24.050358 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 01:36:24.050410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 01:36:24.050464 ==
1287 01:36:24.050517
1288 01:36:24.050569
1289 01:36:24.050621 TX Vref Scan disable
1290 01:36:24.050674 == TX Byte 0 ==
1291 01:36:24.050727 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1292 01:36:24.050780 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1293 01:36:24.050833 == TX Byte 1 ==
1294 01:36:24.050886 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1295 01:36:24.050939 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1296 01:36:24.050991
1297 01:36:24.051043 [DATLAT]
1298 01:36:24.051095 Freq=800, CH0 RK1
1299 01:36:24.051148
1300 01:36:24.051199 DATLAT Default: 0xa
1301 01:36:24.051250 0, 0xFFFF, sum = 0
1302 01:36:24.051336 1, 0xFFFF, sum = 0
1303 01:36:24.051390 2, 0xFFFF, sum = 0
1304 01:36:24.051443 3, 0xFFFF, sum = 0
1305 01:36:24.051495 4, 0xFFFF, sum = 0
1306 01:36:24.051549 5, 0xFFFF, sum = 0
1307 01:36:24.051601 6, 0xFFFF, sum = 0
1308 01:36:24.051655 7, 0xFFFF, sum = 0
1309 01:36:24.051707 8, 0xFFFF, sum = 0
1310 01:36:24.051760 9, 0x0, sum = 1
1311 01:36:24.051813 10, 0x0, sum = 2
1312 01:36:24.051866 11, 0x0, sum = 3
1313 01:36:24.051918 12, 0x0, sum = 4
1314 01:36:24.051971 best_step = 10
1315 01:36:24.052022
1316 01:36:24.052074 ==
1317 01:36:24.052143 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 01:36:24.052199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 01:36:24.052253 ==
1320 01:36:24.052305 RX Vref Scan: 0
1321 01:36:24.052358
1322 01:36:24.052409 RX Vref 0 -> 0, step: 1
1323 01:36:24.052461
1324 01:36:24.052513 RX Delay -95 -> 252, step: 8
1325 01:36:24.052565 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1326 01:36:24.052618 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1327 01:36:24.052867 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1328 01:36:24.052998 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1329 01:36:24.053128 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1330 01:36:24.053254 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1331 01:36:24.053433 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1332 01:36:24.053502 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1333 01:36:24.053557 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1334 01:36:24.053611 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1335 01:36:24.053665 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1336 01:36:24.053719 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1337 01:36:24.053802 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1338 01:36:24.053855 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1339 01:36:24.053915 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1340 01:36:24.053968 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1341 01:36:24.054020 ==
1342 01:36:24.054072 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 01:36:24.054124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 01:36:24.054177 ==
1345 01:36:24.054229 DQS Delay:
1346 01:36:24.054281 DQS0 = 0, DQS1 = 0
1347 01:36:24.054333 DQM Delay:
1348 01:36:24.054385 DQM0 = 86, DQM1 = 77
1349 01:36:24.054437 DQ Delay:
1350 01:36:24.054489 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1351 01:36:24.054542 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1352 01:36:24.054594 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1353 01:36:24.054646 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1354 01:36:24.054697
1355 01:36:24.054749
1356 01:36:24.054801 [DQSOSCAuto] RK1, (LSB)MR18= 0x2622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1357 01:36:24.054855 CH0 RK1: MR19=606, MR18=2622
1358 01:36:24.054907 CH0_RK1: MR19=0x606, MR18=0x2622, DQSOSC=400, MR23=63, INC=92, DEC=61
1359 01:36:24.054960 [RxdqsGatingPostProcess] freq 800
1360 01:36:24.055012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 01:36:24.055064 Pre-setting of DQS Precalculation
1362 01:36:24.055116 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1363 01:36:24.055168 ==
1364 01:36:24.055221 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 01:36:24.055274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 01:36:24.055326 ==
1367 01:36:24.055378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 01:36:24.055431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 01:36:24.055484 [CA 0] Center 37 (6~68) winsize 63
1370 01:36:24.055537 [CA 1] Center 37 (6~68) winsize 63
1371 01:36:24.055589 [CA 2] Center 35 (5~66) winsize 62
1372 01:36:24.055641 [CA 3] Center 34 (4~65) winsize 62
1373 01:36:24.055693 [CA 4] Center 35 (4~66) winsize 63
1374 01:36:24.055746 [CA 5] Center 34 (4~65) winsize 62
1375 01:36:24.055798
1376 01:36:24.055849 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 01:36:24.055901
1378 01:36:24.055953 [CATrainingPosCal] consider 1 rank data
1379 01:36:24.056016 u2DelayCellTimex100 = 270/100 ps
1380 01:36:24.056089 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1381 01:36:24.056170 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1382 01:36:24.056225 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1383 01:36:24.056278 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1384 01:36:24.056331 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1385 01:36:24.056383 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1386 01:36:24.056435
1387 01:36:24.056487 CA PerBit enable=1, Macro0, CA PI delay=34
1388 01:36:24.056540
1389 01:36:24.056592 [CBTSetCACLKResult] CA Dly = 34
1390 01:36:24.056644 CS Dly: 4 (0~35)
1391 01:36:24.056695 ==
1392 01:36:24.056747 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 01:36:24.056799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 01:36:24.056852 ==
1395 01:36:24.056903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 01:36:24.056956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 01:36:24.057009 [CA 0] Center 36 (6~67) winsize 62
1398 01:36:24.057061 [CA 1] Center 37 (6~68) winsize 63
1399 01:36:24.057113 [CA 2] Center 35 (4~66) winsize 63
1400 01:36:24.057164 [CA 3] Center 34 (4~65) winsize 62
1401 01:36:24.057216 [CA 4] Center 34 (4~65) winsize 62
1402 01:36:24.057295 [CA 5] Center 34 (4~65) winsize 62
1403 01:36:24.057363
1404 01:36:24.057415 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 01:36:24.057468
1406 01:36:24.057520 [CATrainingPosCal] consider 2 rank data
1407 01:36:24.057572 u2DelayCellTimex100 = 270/100 ps
1408 01:36:24.057624 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 01:36:24.057677 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1410 01:36:24.057729 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1411 01:36:24.057806 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 01:36:24.057892 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 01:36:24.057946 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 01:36:24.057999
1415 01:36:24.058051 CA PerBit enable=1, Macro0, CA PI delay=34
1416 01:36:24.058103
1417 01:36:24.058155 [CBTSetCACLKResult] CA Dly = 34
1418 01:36:24.058207 CS Dly: 5 (0~37)
1419 01:36:24.058259
1420 01:36:24.058310 ----->DramcWriteLeveling(PI) begin...
1421 01:36:24.058363 ==
1422 01:36:24.058415 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 01:36:24.058467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 01:36:24.058520 ==
1425 01:36:24.058571 Write leveling (Byte 0): 25 => 25
1426 01:36:24.058623 Write leveling (Byte 1): 27 => 27
1427 01:36:24.058675 DramcWriteLeveling(PI) end<-----
1428 01:36:24.058727
1429 01:36:24.058778 ==
1430 01:36:24.058830 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 01:36:24.058882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 01:36:24.058934 ==
1433 01:36:24.058985 [Gating] SW mode calibration
1434 01:36:24.059037 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 01:36:24.059089 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 01:36:24.059141 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1437 01:36:24.059193 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1438 01:36:24.059244 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1439 01:36:24.059297 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 01:36:24.059349 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 01:36:24.059401 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 01:36:24.059453 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 01:36:24.059504 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 01:36:24.059755 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 01:36:24.059889 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 01:36:24.060017 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 01:36:24.060143 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 01:36:24.060271 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 01:36:24.060335 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 01:36:24.060389 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 01:36:24.060443 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 01:36:24.060496 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:36:24.060549 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1454 01:36:24.060602 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:36:24.060654 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:36:24.060706 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:36:24.060759 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:36:24.060811 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:36:24.060863 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:36:24.060915 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:36:24.060966 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1462 01:36:24.061019 0 9 8 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
1463 01:36:24.061071 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1464 01:36:24.061124 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 01:36:24.061177 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 01:36:24.061229 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 01:36:24.061307 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 01:36:24.061374 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 01:36:24.061427 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1470 01:36:24.061478 0 10 8 | B1->B0 | 2b2b 2626 | 0 0 | (1 1) (0 0)
1471 01:36:24.061530 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:36:24.061591 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:36:24.061652 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:36:24.061705 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:36:24.061758 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 01:36:24.061810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 01:36:24.061862 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1478 01:36:24.061915 0 11 8 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
1479 01:36:24.061968 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1480 01:36:24.062020 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 01:36:24.062072 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 01:36:24.062124 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 01:36:24.062176 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 01:36:24.062229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 01:36:24.062281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1486 01:36:24.062333 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1487 01:36:24.062385 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 01:36:24.062437 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 01:36:24.062490 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 01:36:24.062542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 01:36:24.062594 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 01:36:24.062646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 01:36:24.062698 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 01:36:24.062750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 01:36:24.062803 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 01:36:24.062855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 01:36:24.062908 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 01:36:24.062960 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:36:24.063013 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:36:24.063064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:36:24.063116 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1502 01:36:24.063168 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 01:36:24.063220 Total UI for P1: 0, mck2ui 16
1504 01:36:24.063273 best dqsien dly found for B0: ( 0, 14, 4)
1505 01:36:24.063326 Total UI for P1: 0, mck2ui 16
1506 01:36:24.063378 best dqsien dly found for B1: ( 0, 14, 4)
1507 01:36:24.063431 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1508 01:36:24.063483 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1509 01:36:24.063559
1510 01:36:24.063612 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1511 01:36:24.063665 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1512 01:36:24.063717 [Gating] SW calibration Done
1513 01:36:24.063801 ==
1514 01:36:24.063897 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 01:36:24.063950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 01:36:24.064003 ==
1517 01:36:24.064074 RX Vref Scan: 0
1518 01:36:24.064141
1519 01:36:24.064193 RX Vref 0 -> 0, step: 1
1520 01:36:24.064245
1521 01:36:24.064298 RX Delay -130 -> 252, step: 16
1522 01:36:24.064349 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1523 01:36:24.064402 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1524 01:36:24.064454 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1525 01:36:24.064505 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1526 01:36:24.064557 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1527 01:36:24.064609 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1528 01:36:24.064660 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1529 01:36:24.064713 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1530 01:36:24.064765 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1531 01:36:24.064816 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1532 01:36:24.064868 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1533 01:36:24.064920 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1534 01:36:24.065183 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1535 01:36:24.065276 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1536 01:36:24.065347 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1537 01:36:24.065401 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1538 01:36:24.065454 ==
1539 01:36:24.065507 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 01:36:24.065560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 01:36:24.065630 ==
1542 01:36:24.065683 DQS Delay:
1543 01:36:24.065736 DQS0 = 0, DQS1 = 0
1544 01:36:24.065788 DQM Delay:
1545 01:36:24.065839 DQM0 = 88, DQM1 = 81
1546 01:36:24.065892 DQ Delay:
1547 01:36:24.065944 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1548 01:36:24.065996 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1549 01:36:24.066048 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1550 01:36:24.066100 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1551 01:36:24.066152
1552 01:36:24.066204
1553 01:36:24.066255 ==
1554 01:36:24.066307 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 01:36:24.066359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 01:36:24.066412 ==
1557 01:36:24.066464
1558 01:36:24.066515
1559 01:36:24.066566 TX Vref Scan disable
1560 01:36:24.066619 == TX Byte 0 ==
1561 01:36:24.066671 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1562 01:36:24.066723 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1563 01:36:24.066776 == TX Byte 1 ==
1564 01:36:24.066828 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1565 01:36:24.066881 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1566 01:36:24.066933 ==
1567 01:36:24.066985 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 01:36:24.067037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 01:36:24.067090 ==
1570 01:36:24.067142 TX Vref=22, minBit 4, minWin=26, winSum=440
1571 01:36:24.067194 TX Vref=24, minBit 5, minWin=26, winSum=446
1572 01:36:24.067247 TX Vref=26, minBit 1, minWin=27, winSum=448
1573 01:36:24.067299 TX Vref=28, minBit 1, minWin=27, winSum=454
1574 01:36:24.067351 TX Vref=30, minBit 2, minWin=27, winSum=453
1575 01:36:24.067404 TX Vref=32, minBit 1, minWin=27, winSum=452
1576 01:36:24.067456 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
1577 01:36:24.067508
1578 01:36:24.067560 Final TX Range 1 Vref 28
1579 01:36:24.067612
1580 01:36:24.067664 ==
1581 01:36:24.067716 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 01:36:24.067767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 01:36:24.067901 ==
1584 01:36:24.067971
1585 01:36:24.068080
1586 01:36:24.068163 TX Vref Scan disable
1587 01:36:24.068230 == TX Byte 0 ==
1588 01:36:24.068282 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1589 01:36:24.068334 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1590 01:36:24.068386 == TX Byte 1 ==
1591 01:36:24.068438 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1592 01:36:24.068490 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1593 01:36:24.068542
1594 01:36:24.068593 [DATLAT]
1595 01:36:24.068644 Freq=800, CH1 RK0
1596 01:36:24.068696
1597 01:36:24.068747 DATLAT Default: 0xa
1598 01:36:24.068799 0, 0xFFFF, sum = 0
1599 01:36:24.068853 1, 0xFFFF, sum = 0
1600 01:36:24.068906 2, 0xFFFF, sum = 0
1601 01:36:24.068959 3, 0xFFFF, sum = 0
1602 01:36:24.069012 4, 0xFFFF, sum = 0
1603 01:36:24.069065 5, 0xFFFF, sum = 0
1604 01:36:24.069117 6, 0xFFFF, sum = 0
1605 01:36:24.069170 7, 0xFFFF, sum = 0
1606 01:36:24.069222 8, 0xFFFF, sum = 0
1607 01:36:24.069317 9, 0x0, sum = 1
1608 01:36:24.069371 10, 0x0, sum = 2
1609 01:36:24.069424 11, 0x0, sum = 3
1610 01:36:24.069478 12, 0x0, sum = 4
1611 01:36:24.069548 best_step = 10
1612 01:36:24.069601
1613 01:36:24.069653 ==
1614 01:36:24.069705 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 01:36:24.069757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 01:36:24.069810 ==
1617 01:36:24.069862 RX Vref Scan: 1
1618 01:36:24.069914
1619 01:36:24.069966 Set Vref Range= 32 -> 127
1620 01:36:24.070018
1621 01:36:24.070071 RX Vref 32 -> 127, step: 1
1622 01:36:24.070123
1623 01:36:24.070174 RX Delay -95 -> 252, step: 8
1624 01:36:24.070226
1625 01:36:24.070278 Set Vref, RX VrefLevel [Byte0]: 32
1626 01:36:24.070330 [Byte1]: 32
1627 01:36:24.070383
1628 01:36:24.070434 Set Vref, RX VrefLevel [Byte0]: 33
1629 01:36:24.070486 [Byte1]: 33
1630 01:36:24.070538
1631 01:36:24.070589 Set Vref, RX VrefLevel [Byte0]: 34
1632 01:36:24.070641 [Byte1]: 34
1633 01:36:24.070692
1634 01:36:24.070744 Set Vref, RX VrefLevel [Byte0]: 35
1635 01:36:24.070796 [Byte1]: 35
1636 01:36:24.070848
1637 01:36:24.070900 Set Vref, RX VrefLevel [Byte0]: 36
1638 01:36:24.070952 [Byte1]: 36
1639 01:36:24.071004
1640 01:36:24.071055 Set Vref, RX VrefLevel [Byte0]: 37
1641 01:36:24.071108 [Byte1]: 37
1642 01:36:24.071159
1643 01:36:24.071211 Set Vref, RX VrefLevel [Byte0]: 38
1644 01:36:24.071263 [Byte1]: 38
1645 01:36:24.071316
1646 01:36:24.071367 Set Vref, RX VrefLevel [Byte0]: 39
1647 01:36:24.071419 [Byte1]: 39
1648 01:36:24.071471
1649 01:36:24.071522 Set Vref, RX VrefLevel [Byte0]: 40
1650 01:36:24.071573 [Byte1]: 40
1651 01:36:24.071625
1652 01:36:24.071677 Set Vref, RX VrefLevel [Byte0]: 41
1653 01:36:24.071729 [Byte1]: 41
1654 01:36:24.071780
1655 01:36:24.071854 Set Vref, RX VrefLevel [Byte0]: 42
1656 01:36:24.071908 [Byte1]: 42
1657 01:36:24.071960
1658 01:36:24.072012 Set Vref, RX VrefLevel [Byte0]: 43
1659 01:36:24.072064 [Byte1]: 43
1660 01:36:24.072117
1661 01:36:24.072168 Set Vref, RX VrefLevel [Byte0]: 44
1662 01:36:24.072220 [Byte1]: 44
1663 01:36:24.072272
1664 01:36:24.072324 Set Vref, RX VrefLevel [Byte0]: 45
1665 01:36:24.072376 [Byte1]: 45
1666 01:36:24.072428
1667 01:36:24.072479 Set Vref, RX VrefLevel [Byte0]: 46
1668 01:36:24.072531 [Byte1]: 46
1669 01:36:24.072583
1670 01:36:24.072635 Set Vref, RX VrefLevel [Byte0]: 47
1671 01:36:24.072687 [Byte1]: 47
1672 01:36:24.072738
1673 01:36:24.072789 Set Vref, RX VrefLevel [Byte0]: 48
1674 01:36:24.072841 [Byte1]: 48
1675 01:36:24.072892
1676 01:36:24.072944 Set Vref, RX VrefLevel [Byte0]: 49
1677 01:36:24.072996 [Byte1]: 49
1678 01:36:24.073047
1679 01:36:24.073099 Set Vref, RX VrefLevel [Byte0]: 50
1680 01:36:24.073151 [Byte1]: 50
1681 01:36:24.073202
1682 01:36:24.073253 Set Vref, RX VrefLevel [Byte0]: 51
1683 01:36:24.073348 [Byte1]: 51
1684 01:36:24.073400
1685 01:36:24.073451 Set Vref, RX VrefLevel [Byte0]: 52
1686 01:36:24.073503 [Byte1]: 52
1687 01:36:24.073555
1688 01:36:24.073607 Set Vref, RX VrefLevel [Byte0]: 53
1689 01:36:24.073659 [Byte1]: 53
1690 01:36:24.073710
1691 01:36:24.073775 Set Vref, RX VrefLevel [Byte0]: 54
1692 01:36:24.073831 [Byte1]: 54
1693 01:36:24.073884
1694 01:36:24.073935 Set Vref, RX VrefLevel [Byte0]: 55
1695 01:36:24.073988 [Byte1]: 55
1696 01:36:24.074039
1697 01:36:24.074091 Set Vref, RX VrefLevel [Byte0]: 56
1698 01:36:24.074143 [Byte1]: 56
1699 01:36:24.074195
1700 01:36:24.074441 Set Vref, RX VrefLevel [Byte0]: 57
1701 01:36:24.074573 [Byte1]: 57
1702 01:36:24.074699
1703 01:36:24.074825 Set Vref, RX VrefLevel [Byte0]: 58
1704 01:36:24.074952 [Byte1]: 58
1705 01:36:24.075079
1706 01:36:24.075204 Set Vref, RX VrefLevel [Byte0]: 59
1707 01:36:24.075330 [Byte1]: 59
1708 01:36:24.075455
1709 01:36:24.075578 Set Vref, RX VrefLevel [Byte0]: 60
1710 01:36:24.075637 [Byte1]: 60
1711 01:36:24.075691
1712 01:36:24.075744 Set Vref, RX VrefLevel [Byte0]: 61
1713 01:36:24.075797 [Byte1]: 61
1714 01:36:24.075850
1715 01:36:24.075903 Set Vref, RX VrefLevel [Byte0]: 62
1716 01:36:24.075956 [Byte1]: 62
1717 01:36:24.076008
1718 01:36:24.076060 Set Vref, RX VrefLevel [Byte0]: 63
1719 01:36:24.076112 [Byte1]: 63
1720 01:36:24.076165
1721 01:36:24.076216 Set Vref, RX VrefLevel [Byte0]: 64
1722 01:36:24.076268 [Byte1]: 64
1723 01:36:24.076319
1724 01:36:24.076371 Set Vref, RX VrefLevel [Byte0]: 65
1725 01:36:24.076423 [Byte1]: 65
1726 01:36:24.076475
1727 01:36:24.076526 Set Vref, RX VrefLevel [Byte0]: 66
1728 01:36:24.076578 [Byte1]: 66
1729 01:36:24.076631
1730 01:36:24.076682 Set Vref, RX VrefLevel [Byte0]: 67
1731 01:36:24.076734 [Byte1]: 67
1732 01:36:24.076785
1733 01:36:24.076837 Set Vref, RX VrefLevel [Byte0]: 68
1734 01:36:24.076890 [Byte1]: 68
1735 01:36:24.076941
1736 01:36:24.076993 Set Vref, RX VrefLevel [Byte0]: 69
1737 01:36:24.077045 [Byte1]: 69
1738 01:36:24.077098
1739 01:36:24.077149 Set Vref, RX VrefLevel [Byte0]: 70
1740 01:36:24.077201 [Byte1]: 70
1741 01:36:24.077253
1742 01:36:24.077345 Set Vref, RX VrefLevel [Byte0]: 71
1743 01:36:24.077397 [Byte1]: 71
1744 01:36:24.077449
1745 01:36:24.077501 Set Vref, RX VrefLevel [Byte0]: 72
1746 01:36:24.077552 [Byte1]: 72
1747 01:36:24.077610
1748 01:36:24.077673 Set Vref, RX VrefLevel [Byte0]: 73
1749 01:36:24.077727 [Byte1]: 73
1750 01:36:24.077779
1751 01:36:24.077894 Set Vref, RX VrefLevel [Byte0]: 74
1752 01:36:24.077977 [Byte1]: 74
1753 01:36:24.078032
1754 01:36:24.078085 Final RX Vref Byte 0 = 59 to rank0
1755 01:36:24.078138 Final RX Vref Byte 1 = 58 to rank0
1756 01:36:24.078191 Final RX Vref Byte 0 = 59 to rank1
1757 01:36:24.078244 Final RX Vref Byte 1 = 58 to rank1==
1758 01:36:24.078297 Dram Type= 6, Freq= 0, CH_1, rank 0
1759 01:36:24.078349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1760 01:36:24.078401 ==
1761 01:36:24.078453 DQS Delay:
1762 01:36:24.078505 DQS0 = 0, DQS1 = 0
1763 01:36:24.078574 DQM Delay:
1764 01:36:24.078640 DQM0 = 87, DQM1 = 81
1765 01:36:24.078691 DQ Delay:
1766 01:36:24.078743 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1767 01:36:24.078795 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1768 01:36:24.078847 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1769 01:36:24.078900 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1770 01:36:24.078952
1771 01:36:24.079005
1772 01:36:24.079057 [DQSOSCAuto] RK0, (LSB)MR18= 0x1528, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1773 01:36:24.079110 CH1 RK0: MR19=606, MR18=1528
1774 01:36:24.079162 CH1_RK0: MR19=0x606, MR18=0x1528, DQSOSC=399, MR23=63, INC=92, DEC=61
1775 01:36:24.079215
1776 01:36:24.079266 ----->DramcWriteLeveling(PI) begin...
1777 01:36:24.079319 ==
1778 01:36:24.079371 Dram Type= 6, Freq= 0, CH_1, rank 1
1779 01:36:24.079424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 01:36:24.079476 ==
1781 01:36:24.079528 Write leveling (Byte 0): 25 => 25
1782 01:36:24.079580 Write leveling (Byte 1): 24 => 24
1783 01:36:24.079632 DramcWriteLeveling(PI) end<-----
1784 01:36:24.079684
1785 01:36:24.079735 ==
1786 01:36:24.079787 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 01:36:24.079839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 01:36:24.079892 ==
1789 01:36:24.079944 [Gating] SW mode calibration
1790 01:36:24.079995 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1791 01:36:24.080049 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1792 01:36:24.080101 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1793 01:36:24.080153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1794 01:36:24.080206 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1795 01:36:24.080258 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 01:36:24.080310 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 01:36:24.080362 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 01:36:24.080415 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 01:36:24.080467 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 01:36:24.080519 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 01:36:24.080571 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 01:36:24.080623 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 01:36:24.080675 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 01:36:24.080727 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 01:36:24.080779 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 01:36:24.080830 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 01:36:24.080882 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 01:36:24.080935 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1809 01:36:24.080987 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1810 01:36:24.081038 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:36:24.081090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 01:36:24.081141 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 01:36:24.081193 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 01:36:24.081244 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 01:36:24.081340 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:36:24.081392 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:36:24.081444 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1818 01:36:24.081496 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1819 01:36:24.081548 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1820 01:36:24.081600 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1821 01:36:24.081652 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 01:36:24.081900 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 01:36:24.081963 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 01:36:24.082018 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1825 01:36:24.082070 0 10 4 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
1826 01:36:24.082123 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1827 01:36:24.082176 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:36:24.082229 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 01:36:24.082281 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 01:36:24.082333 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:36:24.082385 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:36:24.082437 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:36:24.082490 0 11 4 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
1834 01:36:24.082542 0 11 8 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
1835 01:36:24.082594 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1836 01:36:24.082647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1837 01:36:24.082699 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 01:36:24.082751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 01:36:24.082804 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 01:36:24.082856 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 01:36:24.082909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1842 01:36:24.082961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1843 01:36:24.083014 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1844 01:36:24.083066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 01:36:24.083118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 01:36:24.083169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 01:36:24.083221 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 01:36:24.083273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 01:36:24.083325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 01:36:24.083377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 01:36:24.083429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 01:36:24.083481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 01:36:24.083533 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 01:36:24.083585 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 01:36:24.083636 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 01:36:24.083688 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 01:36:24.083740 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1858 01:36:24.083792 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1859 01:36:24.083844 Total UI for P1: 0, mck2ui 16
1860 01:36:24.083897 best dqsien dly found for B0: ( 0, 14, 4)
1861 01:36:24.083949 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 01:36:24.084000 Total UI for P1: 0, mck2ui 16
1863 01:36:24.084052 best dqsien dly found for B1: ( 0, 14, 6)
1864 01:36:24.084104 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1865 01:36:24.084156 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1866 01:36:24.084208
1867 01:36:24.084259 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1868 01:36:24.084312 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1869 01:36:24.084364 [Gating] SW calibration Done
1870 01:36:24.084416 ==
1871 01:36:24.084468 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 01:36:24.084520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 01:36:24.084573 ==
1874 01:36:24.084625 RX Vref Scan: 0
1875 01:36:24.084676
1876 01:36:24.084727 RX Vref 0 -> 0, step: 1
1877 01:36:24.084780
1878 01:36:24.084832 RX Delay -130 -> 252, step: 16
1879 01:36:24.084884 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1880 01:36:24.084937 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1881 01:36:24.084989 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1882 01:36:24.085041 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1883 01:36:24.085092 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1884 01:36:24.085144 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1885 01:36:24.085196 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1886 01:36:24.085248 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1887 01:36:24.085311 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1888 01:36:24.085363 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1889 01:36:24.085416 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1890 01:36:24.085468 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1891 01:36:24.085520 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1892 01:36:24.085572 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1893 01:36:24.085624 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1894 01:36:24.085676 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1895 01:36:24.085729 ==
1896 01:36:24.085796 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 01:36:24.085850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 01:36:24.085904 ==
1899 01:36:24.085957 DQS Delay:
1900 01:36:24.086009 DQS0 = 0, DQS1 = 0
1901 01:36:24.086061 DQM Delay:
1902 01:36:24.086113 DQM0 = 84, DQM1 = 82
1903 01:36:24.086166 DQ Delay:
1904 01:36:24.086218 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1905 01:36:24.086270 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1906 01:36:24.086323 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1907 01:36:24.086375 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1908 01:36:24.086427
1909 01:36:24.086478
1910 01:36:24.086530 ==
1911 01:36:24.086582 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 01:36:24.086634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 01:36:24.086687 ==
1914 01:36:24.086738
1915 01:36:24.086790
1916 01:36:24.086841 TX Vref Scan disable
1917 01:36:24.325758 == TX Byte 0 ==
1918 01:36:24.325890 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1919 01:36:24.325959 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1920 01:36:24.326048 == TX Byte 1 ==
1921 01:36:24.326106 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1922 01:36:24.326163 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1923 01:36:24.326219 ==
1924 01:36:24.326274 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 01:36:24.326328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 01:36:24.326383 ==
1927 01:36:24.326436 TX Vref=22, minBit 1, minWin=26, winSum=443
1928 01:36:24.326513 TX Vref=24, minBit 0, minWin=27, winSum=445
1929 01:36:24.326569 TX Vref=26, minBit 2, minWin=27, winSum=452
1930 01:36:24.326846 TX Vref=28, minBit 1, minWin=27, winSum=453
1931 01:36:24.326980 TX Vref=30, minBit 0, minWin=27, winSum=452
1932 01:36:24.327110 TX Vref=32, minBit 2, minWin=27, winSum=454
1933 01:36:24.327242 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 32
1934 01:36:24.327374
1935 01:36:24.327505 Final TX Range 1 Vref 32
1936 01:36:24.327634
1937 01:36:24.327763 ==
1938 01:36:24.327891 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 01:36:24.327976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 01:36:24.328033 ==
1941 01:36:24.328087
1942 01:36:24.328141
1943 01:36:24.328194 TX Vref Scan disable
1944 01:36:24.328247 == TX Byte 0 ==
1945 01:36:24.328300 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1946 01:36:24.328353 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1947 01:36:24.328406 == TX Byte 1 ==
1948 01:36:24.328467 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1949 01:36:24.328555 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1950 01:36:24.328614
1951 01:36:24.328667 [DATLAT]
1952 01:36:24.328720 Freq=800, CH1 RK1
1953 01:36:24.328773
1954 01:36:24.328826 DATLAT Default: 0xa
1955 01:36:24.328878 0, 0xFFFF, sum = 0
1956 01:36:24.328933 1, 0xFFFF, sum = 0
1957 01:36:24.328986 2, 0xFFFF, sum = 0
1958 01:36:24.329041 3, 0xFFFF, sum = 0
1959 01:36:24.329095 4, 0xFFFF, sum = 0
1960 01:36:24.329149 5, 0xFFFF, sum = 0
1961 01:36:24.329202 6, 0xFFFF, sum = 0
1962 01:36:24.329261 7, 0xFFFF, sum = 0
1963 01:36:24.329351 8, 0xFFFF, sum = 0
1964 01:36:24.329404 9, 0x0, sum = 1
1965 01:36:24.329458 10, 0x0, sum = 2
1966 01:36:24.329511 11, 0x0, sum = 3
1967 01:36:24.329564 12, 0x0, sum = 4
1968 01:36:24.329617 best_step = 10
1969 01:36:24.329669
1970 01:36:24.329721 ==
1971 01:36:24.329773 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 01:36:24.329826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 01:36:24.329878 ==
1974 01:36:24.329931 RX Vref Scan: 0
1975 01:36:24.329983
1976 01:36:24.330034 RX Vref 0 -> 0, step: 1
1977 01:36:24.330086
1978 01:36:24.330138 RX Delay -79 -> 252, step: 8
1979 01:36:24.330190 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1980 01:36:24.330243 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1981 01:36:24.330295 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1982 01:36:24.330348 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1983 01:36:24.330399 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1984 01:36:24.330451 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1985 01:36:24.330503 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1986 01:36:24.330556 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1987 01:36:24.330608 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1988 01:36:24.330660 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1989 01:36:24.330712 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1990 01:36:24.330764 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1991 01:36:24.330816 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1992 01:36:24.330868 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1993 01:36:24.330919 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1994 01:36:24.330971 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1995 01:36:24.331023 ==
1996 01:36:24.331075 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 01:36:24.331128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 01:36:24.331181 ==
1999 01:36:24.331233 DQS Delay:
2000 01:36:24.331285 DQS0 = 0, DQS1 = 0
2001 01:36:24.331336 DQM Delay:
2002 01:36:24.331387 DQM0 = 87, DQM1 = 83
2003 01:36:24.331439 DQ Delay:
2004 01:36:24.331491 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2005 01:36:24.331543 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2006 01:36:24.331595 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
2007 01:36:24.331647 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2008 01:36:24.331699
2009 01:36:24.331751
2010 01:36:24.331802 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2011 01:36:24.331856 CH1 RK1: MR19=606, MR18=1C39
2012 01:36:24.331909 CH1_RK1: MR19=0x606, MR18=0x1C39, DQSOSC=395, MR23=63, INC=94, DEC=63
2013 01:36:24.331962 [RxdqsGatingPostProcess] freq 800
2014 01:36:24.332014 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2015 01:36:24.332066 Pre-setting of DQS Precalculation
2016 01:36:24.332118 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2017 01:36:24.332170 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2018 01:36:24.332224 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2019 01:36:24.332276
2020 01:36:24.332327
2021 01:36:24.332379 [Calibration Summary] 1600 Mbps
2022 01:36:24.332431 CH 0, Rank 0
2023 01:36:24.332483 SW Impedance : PASS
2024 01:36:24.332537 DUTY Scan : NO K
2025 01:36:24.332589 ZQ Calibration : PASS
2026 01:36:24.332641 Jitter Meter : NO K
2027 01:36:24.332694 CBT Training : PASS
2028 01:36:24.332745 Write leveling : PASS
2029 01:36:24.332798 RX DQS gating : PASS
2030 01:36:24.332850 RX DQ/DQS(RDDQC) : PASS
2031 01:36:24.332903 TX DQ/DQS : PASS
2032 01:36:24.332955 RX DATLAT : PASS
2033 01:36:24.333007 RX DQ/DQS(Engine): PASS
2034 01:36:24.333059 TX OE : NO K
2035 01:36:24.333112 All Pass.
2036 01:36:24.333164
2037 01:36:24.333216 CH 0, Rank 1
2038 01:36:24.333294 SW Impedance : PASS
2039 01:36:24.333362 DUTY Scan : NO K
2040 01:36:24.333415 ZQ Calibration : PASS
2041 01:36:24.333467 Jitter Meter : NO K
2042 01:36:24.333520 CBT Training : PASS
2043 01:36:24.333572 Write leveling : PASS
2044 01:36:24.333625 RX DQS gating : PASS
2045 01:36:24.333678 RX DQ/DQS(RDDQC) : PASS
2046 01:36:24.333730 TX DQ/DQS : PASS
2047 01:36:24.333782 RX DATLAT : PASS
2048 01:36:24.333835 RX DQ/DQS(Engine): PASS
2049 01:36:24.333888 TX OE : NO K
2050 01:36:24.333940 All Pass.
2051 01:36:24.333993
2052 01:36:24.334045 CH 1, Rank 0
2053 01:36:24.334098 SW Impedance : PASS
2054 01:36:24.334151 DUTY Scan : NO K
2055 01:36:24.334203 ZQ Calibration : PASS
2056 01:36:24.334255 Jitter Meter : NO K
2057 01:36:24.334308 CBT Training : PASS
2058 01:36:24.334360 Write leveling : PASS
2059 01:36:24.334413 RX DQS gating : PASS
2060 01:36:24.334466 RX DQ/DQS(RDDQC) : PASS
2061 01:36:24.334518 TX DQ/DQS : PASS
2062 01:36:24.334571 RX DATLAT : PASS
2063 01:36:24.334623 RX DQ/DQS(Engine): PASS
2064 01:36:24.334675 TX OE : NO K
2065 01:36:24.334728 All Pass.
2066 01:36:24.334780
2067 01:36:24.334832 CH 1, Rank 1
2068 01:36:24.334884 SW Impedance : PASS
2069 01:36:24.334936 DUTY Scan : NO K
2070 01:36:24.334989 ZQ Calibration : PASS
2071 01:36:24.335041 Jitter Meter : NO K
2072 01:36:24.335094 CBT Training : PASS
2073 01:36:24.335146 Write leveling : PASS
2074 01:36:24.335199 RX DQS gating : PASS
2075 01:36:24.335251 RX DQ/DQS(RDDQC) : PASS
2076 01:36:24.335303 TX DQ/DQS : PASS
2077 01:36:24.335355 RX DATLAT : PASS
2078 01:36:24.335408 RX DQ/DQS(Engine): PASS
2079 01:36:24.335460 TX OE : NO K
2080 01:36:24.335512 All Pass.
2081 01:36:24.335564
2082 01:36:24.335617 DramC Write-DBI off
2083 01:36:24.335674 PER_BANK_REFRESH: Hybrid Mode
2084 01:36:24.335930 TX_TRACKING: ON
2085 01:36:24.336062 [GetDramInforAfterCalByMRR] Vendor 6.
2086 01:36:24.336191 [GetDramInforAfterCalByMRR] Revision 606.
2087 01:36:24.336320 [GetDramInforAfterCalByMRR] Revision 2 0.
2088 01:36:24.336450 MR0 0x3b3b
2089 01:36:24.336522 MR8 0x5151
2090 01:36:24.336578 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2091 01:36:24.336632
2092 01:36:24.336684 MR0 0x3b3b
2093 01:36:24.336737 MR8 0x5151
2094 01:36:24.336790 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 01:36:24.336843
2096 01:36:24.336895 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2097 01:36:24.336950 [FAST_K] Save calibration result to emmc
2098 01:36:24.337004 [FAST_K] Save calibration result to emmc
2099 01:36:24.337057 dram_init: config_dvfs: 1
2100 01:36:24.337110 dramc_set_vcore_voltage set vcore to 662500
2101 01:36:24.337163 Read voltage for 1200, 2
2102 01:36:24.337217 Vio18 = 0
2103 01:36:24.337293 Vcore = 662500
2104 01:36:24.337360 Vdram = 0
2105 01:36:24.337412 Vddq = 0
2106 01:36:24.337464 Vmddr = 0
2107 01:36:24.337517 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2108 01:36:24.337570 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2109 01:36:24.337623 MEM_TYPE=3, freq_sel=15
2110 01:36:24.337675 sv_algorithm_assistance_LP4_1600
2111 01:36:24.337728 ============ PULL DRAM RESETB DOWN ============
2112 01:36:24.337782 ========== PULL DRAM RESETB DOWN end =========
2113 01:36:24.337834 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2114 01:36:24.337887 ===================================
2115 01:36:24.337940 LPDDR4 DRAM CONFIGURATION
2116 01:36:24.337993 ===================================
2117 01:36:24.338045 EX_ROW_EN[0] = 0x0
2118 01:36:24.338098 EX_ROW_EN[1] = 0x0
2119 01:36:24.338151 LP4Y_EN = 0x0
2120 01:36:24.338203 WORK_FSP = 0x0
2121 01:36:24.338255 WL = 0x4
2122 01:36:24.338308 RL = 0x4
2123 01:36:24.338360 BL = 0x2
2124 01:36:24.338413 RPST = 0x0
2125 01:36:24.338465 RD_PRE = 0x0
2126 01:36:24.338517 WR_PRE = 0x1
2127 01:36:24.338569 WR_PST = 0x0
2128 01:36:24.338622 DBI_WR = 0x0
2129 01:36:24.338674 DBI_RD = 0x0
2130 01:36:24.338726 OTF = 0x1
2131 01:36:24.338778 ===================================
2132 01:36:24.338831 ===================================
2133 01:36:24.338884 ANA top config
2134 01:36:24.338936 ===================================
2135 01:36:24.338988 DLL_ASYNC_EN = 0
2136 01:36:24.339041 ALL_SLAVE_EN = 0
2137 01:36:24.339094 NEW_RANK_MODE = 1
2138 01:36:24.339148 DLL_IDLE_MODE = 1
2139 01:36:24.339200 LP45_APHY_COMB_EN = 1
2140 01:36:24.339252 TX_ODT_DIS = 1
2141 01:36:24.339305 NEW_8X_MODE = 1
2142 01:36:24.339358 ===================================
2143 01:36:24.339410 ===================================
2144 01:36:24.339463 data_rate = 2400
2145 01:36:24.339515 CKR = 1
2146 01:36:24.339568 DQ_P2S_RATIO = 8
2147 01:36:24.339619 ===================================
2148 01:36:24.339672 CA_P2S_RATIO = 8
2149 01:36:24.339724 DQ_CA_OPEN = 0
2150 01:36:24.339777 DQ_SEMI_OPEN = 0
2151 01:36:24.339830 CA_SEMI_OPEN = 0
2152 01:36:24.339882 CA_FULL_RATE = 0
2153 01:36:24.339934 DQ_CKDIV4_EN = 0
2154 01:36:24.339987 CA_CKDIV4_EN = 0
2155 01:36:24.340039 CA_PREDIV_EN = 0
2156 01:36:24.340092 PH8_DLY = 17
2157 01:36:24.340144 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2158 01:36:24.340197 DQ_AAMCK_DIV = 4
2159 01:36:24.340249 CA_AAMCK_DIV = 4
2160 01:36:24.340301 CA_ADMCK_DIV = 4
2161 01:36:24.340354 DQ_TRACK_CA_EN = 0
2162 01:36:24.340406 CA_PICK = 1200
2163 01:36:24.340458 CA_MCKIO = 1200
2164 01:36:24.340510 MCKIO_SEMI = 0
2165 01:36:24.340563 PLL_FREQ = 2366
2166 01:36:24.340615 DQ_UI_PI_RATIO = 32
2167 01:36:24.340668 CA_UI_PI_RATIO = 0
2168 01:36:24.340721 ===================================
2169 01:36:24.340774 ===================================
2170 01:36:24.340827 memory_type:LPDDR4
2171 01:36:24.340879 GP_NUM : 10
2172 01:36:24.340932 SRAM_EN : 1
2173 01:36:24.340984 MD32_EN : 0
2174 01:36:24.341037 ===================================
2175 01:36:24.341090 [ANA_INIT] >>>>>>>>>>>>>>
2176 01:36:24.341143 <<<<<< [CONFIGURE PHASE]: ANA_TX
2177 01:36:24.341196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2178 01:36:24.341249 ===================================
2179 01:36:24.341338 data_rate = 2400,PCW = 0X5b00
2180 01:36:24.341390 ===================================
2181 01:36:24.341443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2182 01:36:24.341496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2183 01:36:24.341549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 01:36:24.341602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2185 01:36:24.341655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2186 01:36:24.341708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2187 01:36:24.341761 [ANA_INIT] flow start
2188 01:36:24.341813 [ANA_INIT] PLL >>>>>>>>
2189 01:36:24.341865 [ANA_INIT] PLL <<<<<<<<
2190 01:36:24.341917 [ANA_INIT] MIDPI >>>>>>>>
2191 01:36:24.341970 [ANA_INIT] MIDPI <<<<<<<<
2192 01:36:24.342022 [ANA_INIT] DLL >>>>>>>>
2193 01:36:24.342075 [ANA_INIT] DLL <<<<<<<<
2194 01:36:24.342127 [ANA_INIT] flow end
2195 01:36:24.342179 ============ LP4 DIFF to SE enter ============
2196 01:36:24.342233 ============ LP4 DIFF to SE exit ============
2197 01:36:24.342285 [ANA_INIT] <<<<<<<<<<<<<
2198 01:36:24.342338 [Flow] Enable top DCM control >>>>>
2199 01:36:24.342391 [Flow] Enable top DCM control <<<<<
2200 01:36:24.342444 Enable DLL master slave shuffle
2201 01:36:24.342497 ==============================================================
2202 01:36:24.342550 Gating Mode config
2203 01:36:24.342602 ==============================================================
2204 01:36:24.342655 Config description:
2205 01:36:24.342708 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2206 01:36:24.342761 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2207 01:36:24.343010 SELPH_MODE 0: By rank 1: By Phase
2208 01:36:24.343143 ==============================================================
2209 01:36:24.343273 GAT_TRACK_EN = 1
2210 01:36:24.343401 RX_GATING_MODE = 2
2211 01:36:24.343529 RX_GATING_TRACK_MODE = 2
2212 01:36:24.343631 SELPH_MODE = 1
2213 01:36:24.343688 PICG_EARLY_EN = 1
2214 01:36:24.343742 VALID_LAT_VALUE = 1
2215 01:36:24.343796 ==============================================================
2216 01:36:24.343850 Enter into Gating configuration >>>>
2217 01:36:24.343904 Exit from Gating configuration <<<<
2218 01:36:24.343957 Enter into DVFS_PRE_config >>>>>
2219 01:36:24.344010 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2220 01:36:24.344065 Exit from DVFS_PRE_config <<<<<
2221 01:36:24.344118 Enter into PICG configuration >>>>
2222 01:36:24.344171 Exit from PICG configuration <<<<
2223 01:36:24.344224 [RX_INPUT] configuration >>>>>
2224 01:36:24.344278 [RX_INPUT] configuration <<<<<
2225 01:36:24.344331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2226 01:36:24.344385 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2227 01:36:24.344438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2228 01:36:24.344491 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2229 01:36:24.344545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 01:36:24.344598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 01:36:24.344651 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2232 01:36:24.344704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2233 01:36:24.344757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2234 01:36:24.344810 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2235 01:36:24.344862 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2236 01:36:24.344915 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2237 01:36:24.344968 ===================================
2238 01:36:24.345021 LPDDR4 DRAM CONFIGURATION
2239 01:36:24.345074 ===================================
2240 01:36:24.345126 EX_ROW_EN[0] = 0x0
2241 01:36:24.345179 EX_ROW_EN[1] = 0x0
2242 01:36:24.345230 LP4Y_EN = 0x0
2243 01:36:24.345323 WORK_FSP = 0x0
2244 01:36:24.345376 WL = 0x4
2245 01:36:24.345428 RL = 0x4
2246 01:36:24.345480 BL = 0x2
2247 01:36:24.345532 RPST = 0x0
2248 01:36:24.345585 RD_PRE = 0x0
2249 01:36:24.345637 WR_PRE = 0x1
2250 01:36:24.345689 WR_PST = 0x0
2251 01:36:24.345742 DBI_WR = 0x0
2252 01:36:24.345794 DBI_RD = 0x0
2253 01:36:24.345846 OTF = 0x1
2254 01:36:24.345899 ===================================
2255 01:36:24.345952 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2256 01:36:24.346004 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2257 01:36:24.346057 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 01:36:24.346110 ===================================
2259 01:36:24.346163 LPDDR4 DRAM CONFIGURATION
2260 01:36:24.346215 ===================================
2261 01:36:24.346268 EX_ROW_EN[0] = 0x10
2262 01:36:24.346320 EX_ROW_EN[1] = 0x0
2263 01:36:24.346372 LP4Y_EN = 0x0
2264 01:36:24.346425 WORK_FSP = 0x0
2265 01:36:24.346478 WL = 0x4
2266 01:36:24.346530 RL = 0x4
2267 01:36:24.346581 BL = 0x2
2268 01:36:24.346634 RPST = 0x0
2269 01:36:24.346686 RD_PRE = 0x0
2270 01:36:24.346738 WR_PRE = 0x1
2271 01:36:24.346790 WR_PST = 0x0
2272 01:36:24.346842 DBI_WR = 0x0
2273 01:36:24.346894 DBI_RD = 0x0
2274 01:36:24.346946 OTF = 0x1
2275 01:36:24.346999 ===================================
2276 01:36:24.347052 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2277 01:36:24.347105 ==
2278 01:36:24.347158 Dram Type= 6, Freq= 0, CH_0, rank 0
2279 01:36:24.347211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2280 01:36:24.347264 ==
2281 01:36:24.347317 [Duty_Offset_Calibration]
2282 01:36:24.347370 B0:2 B1:0 CA:4
2283 01:36:24.347423
2284 01:36:24.347475 [DutyScan_Calibration_Flow] k_type=0
2285 01:36:24.347527
2286 01:36:24.347580 ==CLK 0==
2287 01:36:24.347632 Final CLK duty delay cell = -4
2288 01:36:24.347685 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2289 01:36:24.347738 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2290 01:36:24.347791 [-4] AVG Duty = 4937%(X100)
2291 01:36:24.347843
2292 01:36:24.347895 CH0 CLK Duty spec in!! Max-Min= 187%
2293 01:36:24.347947 [DutyScan_Calibration_Flow] ====Done====
2294 01:36:24.347999
2295 01:36:24.348051 [DutyScan_Calibration_Flow] k_type=1
2296 01:36:24.348103
2297 01:36:24.348154 ==DQS 0 ==
2298 01:36:24.348206 Final DQS duty delay cell = 0
2299 01:36:24.348258 [0] MAX Duty = 5156%(X100), DQS PI = 18
2300 01:36:24.348311 [0] MIN Duty = 5093%(X100), DQS PI = 0
2301 01:36:24.348363 [0] AVG Duty = 5124%(X100)
2302 01:36:24.348415
2303 01:36:24.348467 ==DQS 1 ==
2304 01:36:24.348518 Final DQS duty delay cell = 0
2305 01:36:24.348570 [0] MAX Duty = 5125%(X100), DQS PI = 52
2306 01:36:24.348622 [0] MIN Duty = 4969%(X100), DQS PI = 16
2307 01:36:24.348674 [0] AVG Duty = 5047%(X100)
2308 01:36:24.348726
2309 01:36:24.348777 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2310 01:36:24.348828
2311 01:36:24.348880 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2312 01:36:24.348932 [DutyScan_Calibration_Flow] ====Done====
2313 01:36:24.348984
2314 01:36:24.349036 [DutyScan_Calibration_Flow] k_type=3
2315 01:36:24.349088
2316 01:36:24.349140 ==DQM 0 ==
2317 01:36:24.349192 Final DQM duty delay cell = 0
2318 01:36:24.349244 [0] MAX Duty = 5125%(X100), DQS PI = 20
2319 01:36:24.349332 [0] MIN Duty = 4844%(X100), DQS PI = 50
2320 01:36:24.349385 [0] AVG Duty = 4984%(X100)
2321 01:36:24.349437
2322 01:36:24.349488 ==DQM 1 ==
2323 01:36:24.349540 Final DQM duty delay cell = 0
2324 01:36:24.349592 [0] MAX Duty = 4969%(X100), DQS PI = 2
2325 01:36:24.349644 [0] MIN Duty = 4875%(X100), DQS PI = 20
2326 01:36:24.349696 [0] AVG Duty = 4922%(X100)
2327 01:36:24.349747
2328 01:36:24.349799 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2329 01:36:24.349851
2330 01:36:24.349903 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2331 01:36:24.349955 [DutyScan_Calibration_Flow] ====Done====
2332 01:36:24.350006
2333 01:36:24.350057 [DutyScan_Calibration_Flow] k_type=2
2334 01:36:24.350109
2335 01:36:24.350161 ==DQ 0 ==
2336 01:36:24.350213 Final DQ duty delay cell = 0
2337 01:36:24.350266 [0] MAX Duty = 5125%(X100), DQS PI = 18
2338 01:36:24.350318 [0] MIN Duty = 4938%(X100), DQS PI = 58
2339 01:36:24.350565 [0] AVG Duty = 5031%(X100)
2340 01:36:24.350695
2341 01:36:24.350823 ==DQ 1 ==
2342 01:36:24.350950 Final DQ duty delay cell = 0
2343 01:36:24.351079 [0] MAX Duty = 5156%(X100), DQS PI = 6
2344 01:36:24.351142 [0] MIN Duty = 4938%(X100), DQS PI = 14
2345 01:36:24.351197 [0] AVG Duty = 5047%(X100)
2346 01:36:24.351250
2347 01:36:24.351304 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2348 01:36:24.351357
2349 01:36:24.351409 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2350 01:36:24.351462 [DutyScan_Calibration_Flow] ====Done====
2351 01:36:24.351515 ==
2352 01:36:24.351568 Dram Type= 6, Freq= 0, CH_1, rank 0
2353 01:36:24.351620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 01:36:24.351674 ==
2355 01:36:24.351726 [Duty_Offset_Calibration]
2356 01:36:24.351778 B0:0 B1:-1 CA:3
2357 01:36:24.351830
2358 01:36:24.351883 [DutyScan_Calibration_Flow] k_type=0
2359 01:36:24.351935
2360 01:36:24.351986 ==CLK 0==
2361 01:36:24.352039 Final CLK duty delay cell = -4
2362 01:36:24.352091 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2363 01:36:24.352144 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2364 01:36:24.352197 [-4] AVG Duty = 4938%(X100)
2365 01:36:24.352249
2366 01:36:24.352300 CH1 CLK Duty spec in!! Max-Min= 124%
2367 01:36:24.352353 [DutyScan_Calibration_Flow] ====Done====
2368 01:36:24.352405
2369 01:36:24.352457 [DutyScan_Calibration_Flow] k_type=1
2370 01:36:24.352510
2371 01:36:24.352580 ==DQS 0 ==
2372 01:36:24.352635 Final DQS duty delay cell = 0
2373 01:36:24.352688 [0] MAX Duty = 5156%(X100), DQS PI = 18
2374 01:36:24.352741 [0] MIN Duty = 4907%(X100), DQS PI = 38
2375 01:36:24.352794 [0] AVG Duty = 5031%(X100)
2376 01:36:24.352847
2377 01:36:24.352899 ==DQS 1 ==
2378 01:36:24.352952 Final DQS duty delay cell = -4
2379 01:36:24.353005 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2380 01:36:24.353058 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2381 01:36:24.353111 [-4] AVG Duty = 4937%(X100)
2382 01:36:24.353164
2383 01:36:24.353215 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2384 01:36:24.353292
2385 01:36:24.353360 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2386 01:36:24.353413 [DutyScan_Calibration_Flow] ====Done====
2387 01:36:24.353465
2388 01:36:24.353517 [DutyScan_Calibration_Flow] k_type=3
2389 01:36:24.353569
2390 01:36:24.353621 ==DQM 0 ==
2391 01:36:24.353674 Final DQM duty delay cell = 0
2392 01:36:24.353726 [0] MAX Duty = 5031%(X100), DQS PI = 28
2393 01:36:24.353778 [0] MIN Duty = 4813%(X100), DQS PI = 38
2394 01:36:24.353831 [0] AVG Duty = 4922%(X100)
2395 01:36:24.353883
2396 01:36:24.353934 ==DQM 1 ==
2397 01:36:24.353986 Final DQM duty delay cell = 4
2398 01:36:24.354038 [4] MAX Duty = 5187%(X100), DQS PI = 32
2399 01:36:24.354091 [4] MIN Duty = 5062%(X100), DQS PI = 2
2400 01:36:24.354142 [4] AVG Duty = 5124%(X100)
2401 01:36:24.354194
2402 01:36:24.354246 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2403 01:36:24.354298
2404 01:36:24.354350 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2405 01:36:24.354402 [DutyScan_Calibration_Flow] ====Done====
2406 01:36:24.354454
2407 01:36:24.354506 [DutyScan_Calibration_Flow] k_type=2
2408 01:36:24.354558
2409 01:36:24.354610 ==DQ 0 ==
2410 01:36:24.354662 Final DQ duty delay cell = -4
2411 01:36:24.354714 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2412 01:36:24.354766 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2413 01:36:24.354818 [-4] AVG Duty = 4937%(X100)
2414 01:36:24.354869
2415 01:36:24.354922 ==DQ 1 ==
2416 01:36:24.354973 Final DQ duty delay cell = 0
2417 01:36:24.355026 [0] MAX Duty = 5031%(X100), DQS PI = 32
2418 01:36:24.355078 [0] MIN Duty = 4844%(X100), DQS PI = 62
2419 01:36:24.355131 [0] AVG Duty = 4937%(X100)
2420 01:36:24.355183
2421 01:36:24.355235 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2422 01:36:24.355287
2423 01:36:24.355339 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2424 01:36:24.355392 [DutyScan_Calibration_Flow] ====Done====
2425 01:36:24.355444 nWR fixed to 30
2426 01:36:24.355497 [ModeRegInit_LP4] CH0 RK0
2427 01:36:24.355549 [ModeRegInit_LP4] CH0 RK1
2428 01:36:24.355601 [ModeRegInit_LP4] CH1 RK0
2429 01:36:24.355653 [ModeRegInit_LP4] CH1 RK1
2430 01:36:24.355705 match AC timing 7
2431 01:36:24.355756 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2432 01:36:24.355808 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2433 01:36:24.355861 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2434 01:36:24.355913 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2435 01:36:24.355966 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2436 01:36:24.356017 ==
2437 01:36:24.356069 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 01:36:24.356122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 01:36:24.356175 ==
2440 01:36:24.356227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2441 01:36:24.356281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2442 01:36:24.356334 [CA 0] Center 40 (10~70) winsize 61
2443 01:36:24.356387 [CA 1] Center 39 (9~70) winsize 62
2444 01:36:24.356439 [CA 2] Center 35 (5~66) winsize 62
2445 01:36:24.356492 [CA 3] Center 35 (5~66) winsize 62
2446 01:36:24.356544 [CA 4] Center 33 (3~64) winsize 62
2447 01:36:24.356597 [CA 5] Center 33 (3~63) winsize 61
2448 01:36:24.356649
2449 01:36:24.356701 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2450 01:36:24.356753
2451 01:36:24.356804 [CATrainingPosCal] consider 1 rank data
2452 01:36:24.356856 u2DelayCellTimex100 = 270/100 ps
2453 01:36:24.356908 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2454 01:36:24.356961 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2455 01:36:24.357013 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2456 01:36:24.357065 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2457 01:36:24.357118 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2458 01:36:24.357170 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2459 01:36:24.357223
2460 01:36:24.357279 CA PerBit enable=1, Macro0, CA PI delay=33
2461 01:36:24.357332
2462 01:36:24.357385 [CBTSetCACLKResult] CA Dly = 33
2463 01:36:24.357437 CS Dly: 7 (0~38)
2464 01:36:24.357489 ==
2465 01:36:24.357541 Dram Type= 6, Freq= 0, CH_0, rank 1
2466 01:36:24.357594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 01:36:24.357647 ==
2468 01:36:24.357700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 01:36:24.357753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 01:36:24.357805 [CA 0] Center 39 (9~70) winsize 62
2471 01:36:24.357857 [CA 1] Center 39 (9~70) winsize 62
2472 01:36:24.357909 [CA 2] Center 35 (5~66) winsize 62
2473 01:36:24.357961 [CA 3] Center 35 (5~66) winsize 62
2474 01:36:24.358013 [CA 4] Center 34 (4~65) winsize 62
2475 01:36:24.358065 [CA 5] Center 33 (3~64) winsize 62
2476 01:36:24.358117
2477 01:36:24.358170 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 01:36:24.358221
2479 01:36:24.358273 [CATrainingPosCal] consider 2 rank data
2480 01:36:24.358325 u2DelayCellTimex100 = 270/100 ps
2481 01:36:24.358378 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2482 01:36:24.358625 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 01:36:24.358688 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 01:36:24.358743 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 01:36:24.358795 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2486 01:36:24.358848 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2487 01:36:24.358901
2488 01:36:24.358954 CA PerBit enable=1, Macro0, CA PI delay=33
2489 01:36:24.359008
2490 01:36:24.359059 [CBTSetCACLKResult] CA Dly = 33
2491 01:36:24.359112 CS Dly: 8 (0~41)
2492 01:36:24.359164
2493 01:36:24.359217 ----->DramcWriteLeveling(PI) begin...
2494 01:36:24.359270 ==
2495 01:36:24.359323 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 01:36:24.359376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 01:36:24.359429 ==
2498 01:36:24.359481 Write leveling (Byte 0): 33 => 33
2499 01:36:24.359533 Write leveling (Byte 1): 26 => 26
2500 01:36:24.359586 DramcWriteLeveling(PI) end<-----
2501 01:36:24.359639
2502 01:36:24.359690 ==
2503 01:36:24.359743 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 01:36:24.359795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 01:36:24.359847 ==
2506 01:36:24.359899 [Gating] SW mode calibration
2507 01:36:24.359951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2508 01:36:24.360005 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2509 01:36:24.360058 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2510 01:36:24.360111 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2511 01:36:24.360163 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 01:36:24.360216 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 01:36:24.360268 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 01:36:24.360321 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 01:36:24.360373 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2516 01:36:24.360425 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
2517 01:36:24.360477 1 0 0 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2518 01:36:24.360529 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 01:36:24.360581 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 01:36:24.360633 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 01:36:24.360686 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 01:36:24.360738 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 01:36:24.360790 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2524 01:36:24.360842 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2525 01:36:24.360895 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2526 01:36:24.360947 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2527 01:36:24.360999 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 01:36:24.361051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 01:36:24.361103 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 01:36:24.361155 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 01:36:24.361208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 01:36:24.361268 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2533 01:36:24.361323 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2534 01:36:24.361375 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2535 01:36:24.361428 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 01:36:24.361481 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 01:36:24.361534 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 01:36:24.361587 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 01:36:24.361639 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 01:36:24.361691 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 01:36:24.361743 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 01:36:24.361796 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 01:36:24.361848 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 01:36:24.361899 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 01:36:24.361951 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 01:36:24.362003 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 01:36:24.362056 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2548 01:36:24.362108 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2549 01:36:24.362160 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2550 01:36:24.362212 Total UI for P1: 0, mck2ui 16
2551 01:36:24.362265 best dqsien dly found for B0: ( 1, 3, 26)
2552 01:36:24.362317 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 01:36:24.362370 Total UI for P1: 0, mck2ui 16
2554 01:36:24.362423 best dqsien dly found for B1: ( 1, 4, 2)
2555 01:36:24.362476 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2556 01:36:24.362529 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2557 01:36:24.362582
2558 01:36:24.362634 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2559 01:36:24.362687 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2560 01:36:24.362739 [Gating] SW calibration Done
2561 01:36:24.362790 ==
2562 01:36:24.362842 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 01:36:24.362895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 01:36:24.362948 ==
2565 01:36:24.363001 RX Vref Scan: 0
2566 01:36:24.363053
2567 01:36:24.363105 RX Vref 0 -> 0, step: 1
2568 01:36:24.363157
2569 01:36:24.363209 RX Delay -40 -> 252, step: 8
2570 01:36:24.363261 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2571 01:36:24.363313 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2572 01:36:24.363365 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2573 01:36:24.363418 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2574 01:36:24.363471 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2575 01:36:24.363523 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2576 01:36:24.363575 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2577 01:36:24.363628 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2578 01:36:24.363695 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2579 01:36:24.363749 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2580 01:36:24.363802 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2581 01:36:24.363854 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2582 01:36:24.363906 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2583 01:36:24.364153 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2584 01:36:24.364286 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2585 01:36:24.364414 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2586 01:36:24.364540 ==
2587 01:36:24.364666 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 01:36:24.364794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 01:36:24.364923 ==
2590 01:36:24.365049 DQS Delay:
2591 01:36:24.365176 DQS0 = 0, DQS1 = 0
2592 01:36:24.365289 DQM Delay:
2593 01:36:24.365361 DQM0 = 118, DQM1 = 108
2594 01:36:24.365416 DQ Delay:
2595 01:36:24.365470 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =115
2596 01:36:24.365523 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2597 01:36:24.365577 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2598 01:36:24.365630 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2599 01:36:24.365682
2600 01:36:24.365735
2601 01:36:24.365787 ==
2602 01:36:24.365839 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 01:36:24.365891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 01:36:24.365945 ==
2605 01:36:24.365997
2606 01:36:24.366049
2607 01:36:24.366101 TX Vref Scan disable
2608 01:36:24.366153 == TX Byte 0 ==
2609 01:36:24.366206 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2610 01:36:24.366259 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2611 01:36:24.366312 == TX Byte 1 ==
2612 01:36:24.366365 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2613 01:36:24.366418 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2614 01:36:24.366471 ==
2615 01:36:24.366523 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 01:36:24.366576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 01:36:24.366628 ==
2618 01:36:24.366681 TX Vref=22, minBit 7, minWin=25, winSum=411
2619 01:36:24.366734 TX Vref=24, minBit 1, minWin=25, winSum=418
2620 01:36:24.366786 TX Vref=26, minBit 8, minWin=25, winSum=419
2621 01:36:24.366839 TX Vref=28, minBit 10, minWin=26, winSum=432
2622 01:36:24.366891 TX Vref=30, minBit 5, minWin=26, winSum=430
2623 01:36:24.366944 TX Vref=32, minBit 4, minWin=26, winSum=427
2624 01:36:24.366996 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 28
2625 01:36:24.367049
2626 01:36:24.367101 Final TX Range 1 Vref 28
2627 01:36:24.367153
2628 01:36:24.367205 ==
2629 01:36:24.367257 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 01:36:24.367309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 01:36:24.367362 ==
2632 01:36:24.367414
2633 01:36:24.367465
2634 01:36:24.367517 TX Vref Scan disable
2635 01:36:24.367569 == TX Byte 0 ==
2636 01:36:24.367622 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 01:36:24.367675 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 01:36:24.367728 == TX Byte 1 ==
2639 01:36:24.367780 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2640 01:36:24.367833 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2641 01:36:24.367885
2642 01:36:24.367936 [DATLAT]
2643 01:36:24.367988 Freq=1200, CH0 RK0
2644 01:36:24.368041
2645 01:36:24.368093 DATLAT Default: 0xd
2646 01:36:24.368145 0, 0xFFFF, sum = 0
2647 01:36:24.368199 1, 0xFFFF, sum = 0
2648 01:36:24.368253 2, 0xFFFF, sum = 0
2649 01:36:24.368306 3, 0xFFFF, sum = 0
2650 01:36:24.368359 4, 0xFFFF, sum = 0
2651 01:36:24.368412 5, 0xFFFF, sum = 0
2652 01:36:24.368465 6, 0xFFFF, sum = 0
2653 01:36:24.368518 7, 0xFFFF, sum = 0
2654 01:36:24.368571 8, 0xFFFF, sum = 0
2655 01:36:24.368625 9, 0xFFFF, sum = 0
2656 01:36:24.368678 10, 0xFFFF, sum = 0
2657 01:36:24.368731 11, 0xFFFF, sum = 0
2658 01:36:24.368784 12, 0x0, sum = 1
2659 01:36:24.368837 13, 0x0, sum = 2
2660 01:36:24.368890 14, 0x0, sum = 3
2661 01:36:24.368942 15, 0x0, sum = 4
2662 01:36:24.368994 best_step = 13
2663 01:36:24.369047
2664 01:36:24.369098 ==
2665 01:36:24.369150 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 01:36:24.369219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 01:36:24.369295 ==
2668 01:36:24.369349 RX Vref Scan: 1
2669 01:36:24.369402
2670 01:36:24.369454 Set Vref Range= 32 -> 127
2671 01:36:24.369506
2672 01:36:24.369559 RX Vref 32 -> 127, step: 1
2673 01:36:24.369611
2674 01:36:24.369663 RX Delay -21 -> 252, step: 4
2675 01:36:24.369715
2676 01:36:24.369767 Set Vref, RX VrefLevel [Byte0]: 32
2677 01:36:24.369820 [Byte1]: 32
2678 01:36:24.369873
2679 01:36:24.369925 Set Vref, RX VrefLevel [Byte0]: 33
2680 01:36:24.369977 [Byte1]: 33
2681 01:36:24.370030
2682 01:36:24.370081 Set Vref, RX VrefLevel [Byte0]: 34
2683 01:36:24.370133 [Byte1]: 34
2684 01:36:24.370185
2685 01:36:24.370237 Set Vref, RX VrefLevel [Byte0]: 35
2686 01:36:24.370289 [Byte1]: 35
2687 01:36:24.370341
2688 01:36:24.370393 Set Vref, RX VrefLevel [Byte0]: 36
2689 01:36:24.370445 [Byte1]: 36
2690 01:36:24.370497
2691 01:36:24.370549 Set Vref, RX VrefLevel [Byte0]: 37
2692 01:36:24.370602 [Byte1]: 37
2693 01:36:24.370654
2694 01:36:24.370706 Set Vref, RX VrefLevel [Byte0]: 38
2695 01:36:24.370759 [Byte1]: 38
2696 01:36:24.370812
2697 01:36:24.370864 Set Vref, RX VrefLevel [Byte0]: 39
2698 01:36:24.370916 [Byte1]: 39
2699 01:36:24.370970
2700 01:36:24.371022 Set Vref, RX VrefLevel [Byte0]: 40
2701 01:36:24.371074 [Byte1]: 40
2702 01:36:24.371127
2703 01:36:24.371179 Set Vref, RX VrefLevel [Byte0]: 41
2704 01:36:24.371231 [Byte1]: 41
2705 01:36:24.371283
2706 01:36:24.371334 Set Vref, RX VrefLevel [Byte0]: 42
2707 01:36:24.371387 [Byte1]: 42
2708 01:36:24.371439
2709 01:36:24.371491 Set Vref, RX VrefLevel [Byte0]: 43
2710 01:36:24.371543 [Byte1]: 43
2711 01:36:24.371595
2712 01:36:24.371647 Set Vref, RX VrefLevel [Byte0]: 44
2713 01:36:24.371722 [Byte1]: 44
2714 01:36:24.371790
2715 01:36:24.371843 Set Vref, RX VrefLevel [Byte0]: 45
2716 01:36:24.371895 [Byte1]: 45
2717 01:36:24.371947
2718 01:36:24.371999 Set Vref, RX VrefLevel [Byte0]: 46
2719 01:36:24.372051 [Byte1]: 46
2720 01:36:24.372104
2721 01:36:24.372155 Set Vref, RX VrefLevel [Byte0]: 47
2722 01:36:24.372207 [Byte1]: 47
2723 01:36:24.372259
2724 01:36:24.372311 Set Vref, RX VrefLevel [Byte0]: 48
2725 01:36:24.372363 [Byte1]: 48
2726 01:36:24.372416
2727 01:36:24.372468 Set Vref, RX VrefLevel [Byte0]: 49
2728 01:36:24.372521 [Byte1]: 49
2729 01:36:24.372573
2730 01:36:24.372625 Set Vref, RX VrefLevel [Byte0]: 50
2731 01:36:24.372677 [Byte1]: 50
2732 01:36:24.372729
2733 01:36:24.372781 Set Vref, RX VrefLevel [Byte0]: 51
2734 01:36:24.372834 [Byte1]: 51
2735 01:36:24.372886
2736 01:36:24.372938 Set Vref, RX VrefLevel [Byte0]: 52
2737 01:36:24.372989 [Byte1]: 52
2738 01:36:24.373042
2739 01:36:24.373093 Set Vref, RX VrefLevel [Byte0]: 53
2740 01:36:24.373146 [Byte1]: 53
2741 01:36:24.373199
2742 01:36:24.373251 Set Vref, RX VrefLevel [Byte0]: 54
2743 01:36:24.373345 [Byte1]: 54
2744 01:36:24.373397
2745 01:36:24.373449 Set Vref, RX VrefLevel [Byte0]: 55
2746 01:36:24.373501 [Byte1]: 55
2747 01:36:24.373553
2748 01:36:24.373605 Set Vref, RX VrefLevel [Byte0]: 56
2749 01:36:24.373658 [Byte1]: 56
2750 01:36:24.373710
2751 01:36:24.373954 Set Vref, RX VrefLevel [Byte0]: 57
2752 01:36:24.374014 [Byte1]: 57
2753 01:36:24.374068
2754 01:36:24.374121 Set Vref, RX VrefLevel [Byte0]: 58
2755 01:36:24.374174 [Byte1]: 58
2756 01:36:24.374226
2757 01:36:24.374279 Set Vref, RX VrefLevel [Byte0]: 59
2758 01:36:24.374332 [Byte1]: 59
2759 01:36:24.374384
2760 01:36:24.374436 Set Vref, RX VrefLevel [Byte0]: 60
2761 01:36:24.374489 [Byte1]: 60
2762 01:36:24.374541
2763 01:36:24.374594 Set Vref, RX VrefLevel [Byte0]: 61
2764 01:36:24.374646 [Byte1]: 61
2765 01:36:24.374699
2766 01:36:24.374751 Set Vref, RX VrefLevel [Byte0]: 62
2767 01:36:24.374803 [Byte1]: 62
2768 01:36:24.374856
2769 01:36:24.374908 Set Vref, RX VrefLevel [Byte0]: 63
2770 01:36:24.374961 [Byte1]: 63
2771 01:36:24.375013
2772 01:36:24.375065 Set Vref, RX VrefLevel [Byte0]: 64
2773 01:36:24.375117 [Byte1]: 64
2774 01:36:24.375170
2775 01:36:24.375223 Set Vref, RX VrefLevel [Byte0]: 65
2776 01:36:24.375276 [Byte1]: 65
2777 01:36:24.375328
2778 01:36:24.375381 Set Vref, RX VrefLevel [Byte0]: 66
2779 01:36:24.375433 [Byte1]: 66
2780 01:36:24.375486
2781 01:36:24.375538 Set Vref, RX VrefLevel [Byte0]: 67
2782 01:36:24.375590 [Byte1]: 67
2783 01:36:24.375643
2784 01:36:24.375695 Set Vref, RX VrefLevel [Byte0]: 68
2785 01:36:24.375748 [Byte1]: 68
2786 01:36:24.375801
2787 01:36:24.375853 Final RX Vref Byte 0 = 53 to rank0
2788 01:36:24.375907 Final RX Vref Byte 1 = 50 to rank0
2789 01:36:24.375960 Final RX Vref Byte 0 = 53 to rank1
2790 01:36:24.376013 Final RX Vref Byte 1 = 50 to rank1==
2791 01:36:24.376065 Dram Type= 6, Freq= 0, CH_0, rank 0
2792 01:36:24.376117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2793 01:36:24.376170 ==
2794 01:36:24.376223 DQS Delay:
2795 01:36:24.376275 DQS0 = 0, DQS1 = 0
2796 01:36:24.376327 DQM Delay:
2797 01:36:24.376379 DQM0 = 116, DQM1 = 104
2798 01:36:24.376432 DQ Delay:
2799 01:36:24.376485 DQ0 =118, DQ1 =116, DQ2 =112, DQ3 =114
2800 01:36:24.376538 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2801 01:36:24.376590 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2802 01:36:24.376642 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
2803 01:36:24.376695
2804 01:36:24.376747
2805 01:36:24.376799 [DQSOSCAuto] RK0, (LSB)MR18= 0xfef9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2806 01:36:24.376853 CH0 RK0: MR19=303, MR18=FEF9
2807 01:36:24.376906 CH0_RK0: MR19=0x303, MR18=0xFEF9, DQSOSC=410, MR23=63, INC=39, DEC=26
2808 01:36:24.376959
2809 01:36:24.377011 ----->DramcWriteLeveling(PI) begin...
2810 01:36:24.377064 ==
2811 01:36:24.377117 Dram Type= 6, Freq= 0, CH_0, rank 1
2812 01:36:24.377169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 01:36:24.377221 ==
2814 01:36:24.377318 Write leveling (Byte 0): 30 => 30
2815 01:36:24.377374 Write leveling (Byte 1): 26 => 26
2816 01:36:24.377427 DramcWriteLeveling(PI) end<-----
2817 01:36:24.377479
2818 01:36:24.377532 ==
2819 01:36:24.377585 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 01:36:24.377638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 01:36:24.377691 ==
2822 01:36:24.377743 [Gating] SW mode calibration
2823 01:36:24.377797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2824 01:36:24.377851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2825 01:36:24.377904 0 15 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2826 01:36:24.377957 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2827 01:36:24.378010 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2828 01:36:24.378062 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2829 01:36:24.378115 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 01:36:24.378167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 01:36:24.378220 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2832 01:36:24.378272 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2833 01:36:24.378325 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2834 01:36:24.378377 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2835 01:36:24.378430 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2836 01:36:24.378482 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2837 01:36:24.378534 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 01:36:24.378587 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 01:36:24.378639 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2840 01:36:24.378692 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2841 01:36:24.378744 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
2842 01:36:24.378796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2843 01:36:24.378848 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2844 01:36:24.378901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 01:36:24.378954 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 01:36:24.379006 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 01:36:24.379058 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 01:36:24.379110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2849 01:36:24.379162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2850 01:36:24.379215 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 01:36:24.379267 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 01:36:24.379319 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 01:36:24.379371 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 01:36:24.379423 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 01:36:24.379475 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 01:36:24.379528 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 01:36:24.379581 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 01:36:24.379633 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 01:36:24.379684 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 01:36:24.379736 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 01:36:24.379788 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 01:36:24.379841 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 01:36:24.379893 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 01:36:24.380138 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2865 01:36:24.380269 Total UI for P1: 0, mck2ui 16
2866 01:36:24.380397 best dqsien dly found for B0: ( 1, 3, 26)
2867 01:36:24.380525 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2868 01:36:24.380653 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 01:36:24.380781 Total UI for P1: 0, mck2ui 16
2870 01:36:24.380907 best dqsien dly found for B1: ( 1, 4, 0)
2871 01:36:24.381034 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2872 01:36:24.381187 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2873 01:36:24.381317
2874 01:36:24.381376 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2875 01:36:24.381430 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2876 01:36:24.381484 [Gating] SW calibration Done
2877 01:36:24.381537 ==
2878 01:36:24.381590 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 01:36:24.381643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 01:36:24.381697 ==
2881 01:36:24.381750 RX Vref Scan: 0
2882 01:36:24.381802
2883 01:36:24.381854 RX Vref 0 -> 0, step: 1
2884 01:36:24.381907
2885 01:36:24.381959 RX Delay -40 -> 252, step: 8
2886 01:36:24.382011 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2887 01:36:24.382064 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2888 01:36:24.382116 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2889 01:36:24.382168 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2890 01:36:24.382221 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2891 01:36:24.382273 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2892 01:36:24.382324 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2893 01:36:24.382377 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2894 01:36:24.382429 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2895 01:36:24.382482 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2896 01:36:24.382535 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2897 01:36:24.382587 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2898 01:36:24.382640 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2899 01:36:24.382692 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2900 01:36:24.382744 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2901 01:36:24.382796 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2902 01:36:24.382848 ==
2903 01:36:24.382900 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 01:36:24.382953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 01:36:24.383005 ==
2906 01:36:24.383058 DQS Delay:
2907 01:36:24.383109 DQS0 = 0, DQS1 = 0
2908 01:36:24.383161 DQM Delay:
2909 01:36:24.383213 DQM0 = 116, DQM1 = 106
2910 01:36:24.383265 DQ Delay:
2911 01:36:24.383317 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2912 01:36:24.383370 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2913 01:36:24.383422 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2914 01:36:24.383475 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2915 01:36:24.383527
2916 01:36:24.383579
2917 01:36:24.383631 ==
2918 01:36:24.383683 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 01:36:24.383736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 01:36:24.383789 ==
2921 01:36:24.383841
2922 01:36:24.383892
2923 01:36:24.383944 TX Vref Scan disable
2924 01:36:24.383996 == TX Byte 0 ==
2925 01:36:24.384048 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2926 01:36:24.384101 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2927 01:36:24.384154 == TX Byte 1 ==
2928 01:36:24.384206 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2929 01:36:24.384259 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2930 01:36:24.384311 ==
2931 01:36:24.384363 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 01:36:24.384416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 01:36:24.384468 ==
2934 01:36:24.384520 TX Vref=22, minBit 0, minWin=25, winSum=410
2935 01:36:24.606781 TX Vref=24, minBit 0, minWin=25, winSum=412
2936 01:36:24.606903 TX Vref=26, minBit 0, minWin=26, winSum=418
2937 01:36:24.606970 TX Vref=28, minBit 13, minWin=25, winSum=426
2938 01:36:24.607031 TX Vref=30, minBit 0, minWin=26, winSum=419
2939 01:36:24.607090 TX Vref=32, minBit 5, minWin=25, winSum=418
2940 01:36:24.607146 [TxChooseVref] Worse bit 0, Min win 26, Win sum 419, Final Vref 30
2941 01:36:24.607203
2942 01:36:24.607258 Final TX Range 1 Vref 30
2943 01:36:24.607313
2944 01:36:24.607367 ==
2945 01:36:24.607421 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 01:36:24.607475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 01:36:24.607529 ==
2948 01:36:24.607583
2949 01:36:24.607636
2950 01:36:24.607688 TX Vref Scan disable
2951 01:36:24.607742 == TX Byte 0 ==
2952 01:36:24.607795 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2953 01:36:24.607849 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2954 01:36:24.607902 == TX Byte 1 ==
2955 01:36:24.607954 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2956 01:36:24.608007 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2957 01:36:24.608060
2958 01:36:24.608113 [DATLAT]
2959 01:36:24.608165 Freq=1200, CH0 RK1
2960 01:36:24.608218
2961 01:36:24.608271 DATLAT Default: 0xd
2962 01:36:24.608323 0, 0xFFFF, sum = 0
2963 01:36:24.608377 1, 0xFFFF, sum = 0
2964 01:36:24.608431 2, 0xFFFF, sum = 0
2965 01:36:24.608485 3, 0xFFFF, sum = 0
2966 01:36:24.608539 4, 0xFFFF, sum = 0
2967 01:36:24.608593 5, 0xFFFF, sum = 0
2968 01:36:24.608646 6, 0xFFFF, sum = 0
2969 01:36:24.608699 7, 0xFFFF, sum = 0
2970 01:36:24.608752 8, 0xFFFF, sum = 0
2971 01:36:24.608806 9, 0xFFFF, sum = 0
2972 01:36:24.608859 10, 0xFFFF, sum = 0
2973 01:36:24.608912 11, 0xFFFF, sum = 0
2974 01:36:24.608965 12, 0x0, sum = 1
2975 01:36:24.609018 13, 0x0, sum = 2
2976 01:36:24.609071 14, 0x0, sum = 3
2977 01:36:24.609124 15, 0x0, sum = 4
2978 01:36:24.609178 best_step = 13
2979 01:36:24.609230
2980 01:36:24.609325 ==
2981 01:36:24.609394 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 01:36:24.609446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 01:36:24.609500 ==
2984 01:36:24.609552 RX Vref Scan: 0
2985 01:36:24.609605
2986 01:36:24.609656 RX Vref 0 -> 0, step: 1
2987 01:36:24.609709
2988 01:36:24.609761 RX Delay -21 -> 252, step: 4
2989 01:36:24.609814 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
2990 01:36:24.609867 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2991 01:36:24.609920 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
2992 01:36:24.609971 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
2993 01:36:24.610023 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
2994 01:36:24.610076 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
2995 01:36:24.610128 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2996 01:36:24.610185 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
2997 01:36:24.610239 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
2998 01:36:24.610296 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
2999 01:36:24.610348 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3000 01:36:24.610401 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3001 01:36:24.610453 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3002 01:36:24.610712 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3003 01:36:24.610782 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3004 01:36:24.610837 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3005 01:36:24.610891 ==
3006 01:36:24.610944 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 01:36:24.610998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 01:36:24.611051 ==
3009 01:36:24.611105 DQS Delay:
3010 01:36:24.611158 DQS0 = 0, DQS1 = 0
3011 01:36:24.611211 DQM Delay:
3012 01:36:24.611263 DQM0 = 115, DQM1 = 105
3013 01:36:24.611315 DQ Delay:
3014 01:36:24.611368 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3015 01:36:24.611420 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3016 01:36:24.611472 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3017 01:36:24.611525 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3018 01:36:24.611578
3019 01:36:24.611630
3020 01:36:24.611682 [DQSOSCAuto] RK1, (LSB)MR18= 0xfcfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3021 01:36:24.611736 CH0 RK1: MR19=303, MR18=FCFA
3022 01:36:24.611788 CH0_RK1: MR19=0x303, MR18=0xFCFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3023 01:36:24.611842 [RxdqsGatingPostProcess] freq 1200
3024 01:36:24.611894 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3025 01:36:24.611947 best DQS0 dly(2T, 0.5T) = (0, 11)
3026 01:36:24.611999 best DQS1 dly(2T, 0.5T) = (0, 12)
3027 01:36:24.612052 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3028 01:36:24.612104 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3029 01:36:24.612157 best DQS0 dly(2T, 0.5T) = (0, 11)
3030 01:36:24.612209 best DQS1 dly(2T, 0.5T) = (0, 12)
3031 01:36:24.612262 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3032 01:36:24.612314 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3033 01:36:24.612366 Pre-setting of DQS Precalculation
3034 01:36:24.612419 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3035 01:36:24.612471 ==
3036 01:36:24.612524 Dram Type= 6, Freq= 0, CH_1, rank 0
3037 01:36:24.612577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 01:36:24.612629 ==
3039 01:36:24.612681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3040 01:36:24.612734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3041 01:36:24.612787 [CA 0] Center 38 (8~68) winsize 61
3042 01:36:24.612838 [CA 1] Center 38 (8~68) winsize 61
3043 01:36:24.612890 [CA 2] Center 35 (5~65) winsize 61
3044 01:36:24.612943 [CA 3] Center 34 (4~64) winsize 61
3045 01:36:24.612995 [CA 4] Center 34 (4~65) winsize 62
3046 01:36:24.613047 [CA 5] Center 33 (4~63) winsize 60
3047 01:36:24.613099
3048 01:36:24.613152 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3049 01:36:24.613203
3050 01:36:24.613255 [CATrainingPosCal] consider 1 rank data
3051 01:36:24.613346 u2DelayCellTimex100 = 270/100 ps
3052 01:36:24.613399 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3053 01:36:24.613452 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3054 01:36:24.613505 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3055 01:36:24.613557 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3056 01:36:24.613610 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3057 01:36:24.613662 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3058 01:36:24.613714
3059 01:36:24.613766 CA PerBit enable=1, Macro0, CA PI delay=33
3060 01:36:24.613818
3061 01:36:24.613870 [CBTSetCACLKResult] CA Dly = 33
3062 01:36:24.613922 CS Dly: 5 (0~36)
3063 01:36:24.613974 ==
3064 01:36:24.614026 Dram Type= 6, Freq= 0, CH_1, rank 1
3065 01:36:24.614078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 01:36:24.614132 ==
3067 01:36:24.614184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3068 01:36:24.614237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3069 01:36:24.614289 [CA 0] Center 37 (7~68) winsize 62
3070 01:36:24.614342 [CA 1] Center 38 (8~68) winsize 61
3071 01:36:24.614395 [CA 2] Center 35 (5~65) winsize 61
3072 01:36:24.614447 [CA 3] Center 33 (3~64) winsize 62
3073 01:36:24.614499 [CA 4] Center 34 (4~64) winsize 61
3074 01:36:24.614551 [CA 5] Center 33 (3~64) winsize 62
3075 01:36:24.614603
3076 01:36:24.614655 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3077 01:36:24.614707
3078 01:36:24.614759 [CATrainingPosCal] consider 2 rank data
3079 01:36:24.614811 u2DelayCellTimex100 = 270/100 ps
3080 01:36:24.614863 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3081 01:36:24.614916 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3082 01:36:24.614968 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3083 01:36:24.615020 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 01:36:24.615073 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 01:36:24.615124 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3086 01:36:24.615176
3087 01:36:24.615228 CA PerBit enable=1, Macro0, CA PI delay=33
3088 01:36:24.615280
3089 01:36:24.615332 [CBTSetCACLKResult] CA Dly = 33
3090 01:36:24.615383 CS Dly: 6 (0~38)
3091 01:36:24.615435
3092 01:36:24.615487 ----->DramcWriteLeveling(PI) begin...
3093 01:36:24.615540 ==
3094 01:36:24.615593 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 01:36:24.615645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 01:36:24.615698 ==
3097 01:36:24.615751 Write leveling (Byte 0): 26 => 26
3098 01:36:24.615803 Write leveling (Byte 1): 27 => 27
3099 01:36:24.615855 DramcWriteLeveling(PI) end<-----
3100 01:36:24.615908
3101 01:36:24.615960 ==
3102 01:36:24.616013 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 01:36:24.616065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 01:36:24.616138 ==
3105 01:36:24.616205 [Gating] SW mode calibration
3106 01:36:24.616257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3107 01:36:24.616310 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3108 01:36:24.616363 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3109 01:36:24.616415 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3110 01:36:24.616467 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3111 01:36:24.616519 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 01:36:24.616571 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 01:36:24.616623 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 01:36:24.616676 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 01:36:24.616728 0 15 28 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
3116 01:36:24.616780 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3117 01:36:24.616832 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3118 01:36:24.616884 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 01:36:24.616936 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 01:36:24.617181 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 01:36:24.617241 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 01:36:24.617335 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
3123 01:36:24.617389 1 0 28 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (1 1)
3124 01:36:24.617442 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3125 01:36:24.617495 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3126 01:36:24.617549 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 01:36:24.617601 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 01:36:24.617654 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 01:36:24.617707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 01:36:24.617760 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3131 01:36:24.617812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3132 01:36:24.617865 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3133 01:36:24.617917 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 01:36:24.617970 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 01:36:24.618022 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 01:36:24.618075 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 01:36:24.618128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 01:36:24.618181 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 01:36:24.618233 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 01:36:24.618287 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 01:36:24.618340 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 01:36:24.618394 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 01:36:24.618447 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 01:36:24.618500 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 01:36:24.618552 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 01:36:24.618605 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3147 01:36:24.618658 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3148 01:36:24.618711 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 01:36:24.618764 Total UI for P1: 0, mck2ui 16
3150 01:36:24.618817 best dqsien dly found for B0: ( 1, 3, 26)
3151 01:36:24.618871 Total UI for P1: 0, mck2ui 16
3152 01:36:24.618924 best dqsien dly found for B1: ( 1, 3, 28)
3153 01:36:24.618977 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3154 01:36:24.619031 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3155 01:36:24.619083
3156 01:36:24.619135 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3157 01:36:24.619189 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3158 01:36:24.619242 [Gating] SW calibration Done
3159 01:36:24.619294 ==
3160 01:36:24.619346 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 01:36:24.619399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 01:36:24.619452 ==
3163 01:36:24.619504 RX Vref Scan: 0
3164 01:36:24.619556
3165 01:36:24.619609 RX Vref 0 -> 0, step: 1
3166 01:36:24.619662
3167 01:36:24.619714 RX Delay -40 -> 252, step: 8
3168 01:36:24.619767 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3169 01:36:24.619820 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3170 01:36:24.619873 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3171 01:36:24.619926 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3172 01:36:24.619979 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3173 01:36:24.620031 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3174 01:36:24.620084 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3175 01:36:24.620136 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3176 01:36:24.620188 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3177 01:36:24.620241 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3178 01:36:24.620294 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3179 01:36:24.620347 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3180 01:36:24.620400 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3181 01:36:24.620453 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3182 01:36:24.620505 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3183 01:36:24.620558 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3184 01:36:24.620610 ==
3185 01:36:24.620663 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 01:36:24.620715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 01:36:24.620769 ==
3188 01:36:24.620821 DQS Delay:
3189 01:36:24.620874 DQS0 = 0, DQS1 = 0
3190 01:36:24.620927 DQM Delay:
3191 01:36:24.620980 DQM0 = 115, DQM1 = 112
3192 01:36:24.621032 DQ Delay:
3193 01:36:24.621084 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3194 01:36:24.621137 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3195 01:36:24.621190 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3196 01:36:24.621243 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3197 01:36:24.621336
3198 01:36:24.621388
3199 01:36:24.621440 ==
3200 01:36:24.621493 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 01:36:24.621546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 01:36:24.621598 ==
3203 01:36:24.621650
3204 01:36:24.621703
3205 01:36:24.621755 TX Vref Scan disable
3206 01:36:24.621807 == TX Byte 0 ==
3207 01:36:24.621860 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3208 01:36:24.621913 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3209 01:36:24.621965 == TX Byte 1 ==
3210 01:36:24.622018 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3211 01:36:24.622071 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3212 01:36:24.622123 ==
3213 01:36:24.622176 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 01:36:24.622228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 01:36:24.622281 ==
3216 01:36:24.622334 TX Vref=22, minBit 9, minWin=24, winSum=406
3217 01:36:24.622387 TX Vref=24, minBit 8, minWin=24, winSum=412
3218 01:36:24.622441 TX Vref=26, minBit 3, minWin=25, winSum=419
3219 01:36:24.622494 TX Vref=28, minBit 3, minWin=25, winSum=422
3220 01:36:24.622547 TX Vref=30, minBit 3, minWin=26, winSum=424
3221 01:36:24.622600 TX Vref=32, minBit 8, minWin=25, winSum=423
3222 01:36:24.622652 [TxChooseVref] Worse bit 3, Min win 26, Win sum 424, Final Vref 30
3223 01:36:24.622706
3224 01:36:24.622758 Final TX Range 1 Vref 30
3225 01:36:24.622843
3226 01:36:24.622933 ==
3227 01:36:24.622985 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 01:36:24.623038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 01:36:24.623091 ==
3230 01:36:24.623143
3231 01:36:24.623195
3232 01:36:24.623247 TX Vref Scan disable
3233 01:36:24.623299 == TX Byte 0 ==
3234 01:36:24.623352 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3235 01:36:24.623594 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3236 01:36:24.623682 == TX Byte 1 ==
3237 01:36:24.623790 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3238 01:36:24.623895 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3239 01:36:24.623986
3240 01:36:24.624070 [DATLAT]
3241 01:36:24.624153 Freq=1200, CH1 RK0
3242 01:36:24.624235
3243 01:36:24.624317 DATLAT Default: 0xd
3244 01:36:24.624399 0, 0xFFFF, sum = 0
3245 01:36:24.624484 1, 0xFFFF, sum = 0
3246 01:36:24.624568 2, 0xFFFF, sum = 0
3247 01:36:24.624651 3, 0xFFFF, sum = 0
3248 01:36:24.624735 4, 0xFFFF, sum = 0
3249 01:36:24.624819 5, 0xFFFF, sum = 0
3250 01:36:24.624903 6, 0xFFFF, sum = 0
3251 01:36:24.624986 7, 0xFFFF, sum = 0
3252 01:36:24.625069 8, 0xFFFF, sum = 0
3253 01:36:24.625153 9, 0xFFFF, sum = 0
3254 01:36:24.625236 10, 0xFFFF, sum = 0
3255 01:36:24.625363 11, 0xFFFF, sum = 0
3256 01:36:24.625448 12, 0x0, sum = 1
3257 01:36:24.625532 13, 0x0, sum = 2
3258 01:36:24.625614 14, 0x0, sum = 3
3259 01:36:24.625675 15, 0x0, sum = 4
3260 01:36:24.625731 best_step = 13
3261 01:36:24.625784
3262 01:36:24.625837 ==
3263 01:36:24.625890 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 01:36:24.625943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 01:36:24.625996 ==
3266 01:36:24.626049 RX Vref Scan: 1
3267 01:36:24.626112
3268 01:36:24.626166 Set Vref Range= 32 -> 127
3269 01:36:24.626219
3270 01:36:24.626271 RX Vref 32 -> 127, step: 1
3271 01:36:24.626324
3272 01:36:24.626376 RX Delay -13 -> 252, step: 4
3273 01:36:24.626429
3274 01:36:24.626482 Set Vref, RX VrefLevel [Byte0]: 32
3275 01:36:24.626535 [Byte1]: 32
3276 01:36:24.626587
3277 01:36:24.626644 Set Vref, RX VrefLevel [Byte0]: 33
3278 01:36:24.626702 [Byte1]: 33
3279 01:36:24.626757
3280 01:36:24.626810 Set Vref, RX VrefLevel [Byte0]: 34
3281 01:36:24.626863 [Byte1]: 34
3282 01:36:24.626915
3283 01:36:24.626968 Set Vref, RX VrefLevel [Byte0]: 35
3284 01:36:24.627021 [Byte1]: 35
3285 01:36:24.627074
3286 01:36:24.627126 Set Vref, RX VrefLevel [Byte0]: 36
3287 01:36:24.627179 [Byte1]: 36
3288 01:36:24.627232
3289 01:36:24.627285 Set Vref, RX VrefLevel [Byte0]: 37
3290 01:36:24.627338 [Byte1]: 37
3291 01:36:24.627391
3292 01:36:24.627443 Set Vref, RX VrefLevel [Byte0]: 38
3293 01:36:24.627495 [Byte1]: 38
3294 01:36:24.627548
3295 01:36:24.627600 Set Vref, RX VrefLevel [Byte0]: 39
3296 01:36:24.627653 [Byte1]: 39
3297 01:36:24.627705
3298 01:36:24.627757 Set Vref, RX VrefLevel [Byte0]: 40
3299 01:36:24.627809 [Byte1]: 40
3300 01:36:24.627862
3301 01:36:24.627914 Set Vref, RX VrefLevel [Byte0]: 41
3302 01:36:24.627965 [Byte1]: 41
3303 01:36:24.628017
3304 01:36:24.628093 Set Vref, RX VrefLevel [Byte0]: 42
3305 01:36:24.628158 [Byte1]: 42
3306 01:36:24.628210
3307 01:36:24.628262 Set Vref, RX VrefLevel [Byte0]: 43
3308 01:36:24.628315 [Byte1]: 43
3309 01:36:24.628367
3310 01:36:24.628418 Set Vref, RX VrefLevel [Byte0]: 44
3311 01:36:24.628469 [Byte1]: 44
3312 01:36:24.628522
3313 01:36:24.628581 Set Vref, RX VrefLevel [Byte0]: 45
3314 01:36:24.628636 [Byte1]: 45
3315 01:36:24.628688
3316 01:36:24.628740 Set Vref, RX VrefLevel [Byte0]: 46
3317 01:36:24.628792 [Byte1]: 46
3318 01:36:24.628844
3319 01:36:24.628896 Set Vref, RX VrefLevel [Byte0]: 47
3320 01:36:24.628948 [Byte1]: 47
3321 01:36:24.629000
3322 01:36:24.629051 Set Vref, RX VrefLevel [Byte0]: 48
3323 01:36:24.629103 [Byte1]: 48
3324 01:36:24.629155
3325 01:36:24.629207 Set Vref, RX VrefLevel [Byte0]: 49
3326 01:36:24.629264 [Byte1]: 49
3327 01:36:24.629351
3328 01:36:24.629403 Set Vref, RX VrefLevel [Byte0]: 50
3329 01:36:24.629455 [Byte1]: 50
3330 01:36:24.629507
3331 01:36:24.629559 Set Vref, RX VrefLevel [Byte0]: 51
3332 01:36:24.629611 [Byte1]: 51
3333 01:36:24.629663
3334 01:36:24.629715 Set Vref, RX VrefLevel [Byte0]: 52
3335 01:36:24.629767 [Byte1]: 52
3336 01:36:24.629821
3337 01:36:24.629872 Set Vref, RX VrefLevel [Byte0]: 53
3338 01:36:24.629924 [Byte1]: 53
3339 01:36:24.629977
3340 01:36:24.630028 Set Vref, RX VrefLevel [Byte0]: 54
3341 01:36:24.630080 [Byte1]: 54
3342 01:36:24.630135
3343 01:36:24.630189 Set Vref, RX VrefLevel [Byte0]: 55
3344 01:36:24.630246 [Byte1]: 55
3345 01:36:24.630299
3346 01:36:24.630350 Set Vref, RX VrefLevel [Byte0]: 56
3347 01:36:24.630403 [Byte1]: 56
3348 01:36:24.630455
3349 01:36:24.630507 Set Vref, RX VrefLevel [Byte0]: 57
3350 01:36:24.630559 [Byte1]: 57
3351 01:36:24.630611
3352 01:36:24.630663 Set Vref, RX VrefLevel [Byte0]: 58
3353 01:36:24.630715 [Byte1]: 58
3354 01:36:24.630767
3355 01:36:24.630818 Set Vref, RX VrefLevel [Byte0]: 59
3356 01:36:24.630871 [Byte1]: 59
3357 01:36:24.630923
3358 01:36:24.630974 Set Vref, RX VrefLevel [Byte0]: 60
3359 01:36:24.631026 [Byte1]: 60
3360 01:36:24.631078
3361 01:36:24.631130 Set Vref, RX VrefLevel [Byte0]: 61
3362 01:36:24.631182 [Byte1]: 61
3363 01:36:24.631234
3364 01:36:24.631285 Set Vref, RX VrefLevel [Byte0]: 62
3365 01:36:24.631338 [Byte1]: 62
3366 01:36:24.631390
3367 01:36:24.631442 Set Vref, RX VrefLevel [Byte0]: 63
3368 01:36:24.631494 [Byte1]: 63
3369 01:36:24.631546
3370 01:36:24.631598 Set Vref, RX VrefLevel [Byte0]: 64
3371 01:36:24.631649 [Byte1]: 64
3372 01:36:24.631701
3373 01:36:24.631752 Set Vref, RX VrefLevel [Byte0]: 65
3374 01:36:24.631805 [Byte1]: 65
3375 01:36:24.631857
3376 01:36:24.631908 Final RX Vref Byte 0 = 53 to rank0
3377 01:36:24.631968 Final RX Vref Byte 1 = 54 to rank0
3378 01:36:24.632024 Final RX Vref Byte 0 = 53 to rank1
3379 01:36:24.632114 Final RX Vref Byte 1 = 54 to rank1==
3380 01:36:24.632167 Dram Type= 6, Freq= 0, CH_1, rank 0
3381 01:36:24.632220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3382 01:36:24.632272 ==
3383 01:36:24.632325 DQS Delay:
3384 01:36:24.632377 DQS0 = 0, DQS1 = 0
3385 01:36:24.632429 DQM Delay:
3386 01:36:24.632481 DQM0 = 114, DQM1 = 113
3387 01:36:24.632534 DQ Delay:
3388 01:36:24.632586 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3389 01:36:24.632638 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3390 01:36:24.632690 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3391 01:36:24.632743 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3392 01:36:24.632795
3393 01:36:24.632847
3394 01:36:24.632898 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3395 01:36:24.632952 CH1 RK0: MR19=303, MR18=F1FD
3396 01:36:24.633004 CH1_RK0: MR19=0x303, MR18=0xF1FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3397 01:36:24.633057
3398 01:36:24.633108 ----->DramcWriteLeveling(PI) begin...
3399 01:36:24.633162 ==
3400 01:36:24.633214 Dram Type= 6, Freq= 0, CH_1, rank 1
3401 01:36:24.633484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 01:36:24.633544 ==
3403 01:36:24.633598 Write leveling (Byte 0): 25 => 25
3404 01:36:24.633651 Write leveling (Byte 1): 30 => 30
3405 01:36:24.633704 DramcWriteLeveling(PI) end<-----
3406 01:36:24.633756
3407 01:36:24.633809 ==
3408 01:36:24.633861 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 01:36:24.633914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 01:36:24.633966 ==
3411 01:36:24.634019 [Gating] SW mode calibration
3412 01:36:24.634119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3413 01:36:24.634174 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3414 01:36:24.634227 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3415 01:36:24.634281 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3416 01:36:24.634333 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3417 01:36:24.634390 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3418 01:36:24.634444 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3419 01:36:24.634502 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3420 01:36:24.634555 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
3421 01:36:24.634607 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3422 01:36:24.634658 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3423 01:36:24.634710 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3424 01:36:24.634762 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 01:36:24.634814 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3426 01:36:24.634866 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 01:36:24.634918 1 0 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3428 01:36:24.634971 1 0 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3429 01:36:24.635023 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3430 01:36:24.635075 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3431 01:36:24.635127 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3432 01:36:24.635179 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 01:36:24.635232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3434 01:36:24.635284 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 01:36:24.635340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 01:36:24.635398 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3437 01:36:24.635451 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3438 01:36:24.635503 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3439 01:36:24.635555 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3440 01:36:24.635607 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 01:36:24.635660 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 01:36:24.635712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 01:36:24.635764 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 01:36:24.635816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 01:36:24.635868 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 01:36:24.635921 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 01:36:24.635973 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 01:36:24.636025 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 01:36:24.636086 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 01:36:24.636142 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 01:36:24.636194 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3452 01:36:24.636246 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3453 01:36:24.636299 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3454 01:36:24.636351 Total UI for P1: 0, mck2ui 16
3455 01:36:24.636404 best dqsien dly found for B0: ( 1, 3, 22)
3456 01:36:24.636456 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 01:36:24.636509 Total UI for P1: 0, mck2ui 16
3458 01:36:24.636561 best dqsien dly found for B1: ( 1, 3, 26)
3459 01:36:24.636616 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3460 01:36:24.636669 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3461 01:36:24.636721
3462 01:36:24.636773 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3463 01:36:24.636825 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3464 01:36:24.636877 [Gating] SW calibration Done
3465 01:36:24.636930 ==
3466 01:36:24.636982 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 01:36:24.637034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 01:36:24.637087 ==
3469 01:36:24.637139 RX Vref Scan: 0
3470 01:36:24.637191
3471 01:36:24.637242 RX Vref 0 -> 0, step: 1
3472 01:36:24.637336
3473 01:36:24.637389 RX Delay -40 -> 252, step: 8
3474 01:36:24.637442 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3475 01:36:24.637495 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3476 01:36:24.637548 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3477 01:36:24.637601 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3478 01:36:24.637653 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3479 01:36:24.637706 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3480 01:36:24.637757 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3481 01:36:24.637809 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3482 01:36:24.637860 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3483 01:36:24.637912 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3484 01:36:24.637964 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3485 01:36:24.638016 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3486 01:36:24.638101 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3487 01:36:24.638153 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3488 01:36:24.638206 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3489 01:36:24.638258 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3490 01:36:24.638310 ==
3491 01:36:24.638362 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 01:36:24.638420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 01:36:24.638477 ==
3494 01:36:24.638530 DQS Delay:
3495 01:36:24.638582 DQS0 = 0, DQS1 = 0
3496 01:36:24.638637 DQM Delay:
3497 01:36:24.638694 DQM0 = 115, DQM1 = 112
3498 01:36:24.638747 DQ Delay:
3499 01:36:24.638799 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3500 01:36:24.638851 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3501 01:36:24.638903 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3502 01:36:24.639157 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3503 01:36:24.639222
3504 01:36:24.639276
3505 01:36:24.639329 ==
3506 01:36:24.639382 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 01:36:24.639435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 01:36:24.639488 ==
3509 01:36:24.639540
3510 01:36:24.639592
3511 01:36:24.639644 TX Vref Scan disable
3512 01:36:24.639696 == TX Byte 0 ==
3513 01:36:24.639748 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3514 01:36:24.639800 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3515 01:36:24.639853 == TX Byte 1 ==
3516 01:36:24.639905 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3517 01:36:24.639957 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3518 01:36:24.640010 ==
3519 01:36:24.640081 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 01:36:24.640168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 01:36:24.640259 ==
3522 01:36:24.640315 TX Vref=22, minBit 3, minWin=25, winSum=418
3523 01:36:24.640370 TX Vref=24, minBit 0, minWin=26, winSum=426
3524 01:36:24.640423 TX Vref=26, minBit 1, minWin=26, winSum=426
3525 01:36:24.640476 TX Vref=28, minBit 1, minWin=26, winSum=430
3526 01:36:24.640529 TX Vref=30, minBit 3, minWin=26, winSum=430
3527 01:36:24.640582 TX Vref=32, minBit 15, minWin=25, winSum=431
3528 01:36:24.640636 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3529 01:36:24.640690
3530 01:36:24.640742 Final TX Range 1 Vref 28
3531 01:36:24.640795
3532 01:36:24.640847 ==
3533 01:36:24.640898 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 01:36:24.640951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 01:36:24.641004 ==
3536 01:36:24.641056
3537 01:36:24.641108
3538 01:36:24.641160 TX Vref Scan disable
3539 01:36:24.641212 == TX Byte 0 ==
3540 01:36:24.641272 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3541 01:36:24.641359 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3542 01:36:24.641411 == TX Byte 1 ==
3543 01:36:24.641463 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3544 01:36:24.641516 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3545 01:36:24.641568
3546 01:36:24.641620 [DATLAT]
3547 01:36:24.641672 Freq=1200, CH1 RK1
3548 01:36:24.641725
3549 01:36:24.641784 DATLAT Default: 0xd
3550 01:36:24.641869 0, 0xFFFF, sum = 0
3551 01:36:24.641953 1, 0xFFFF, sum = 0
3552 01:36:24.642042 2, 0xFFFF, sum = 0
3553 01:36:24.642120 3, 0xFFFF, sum = 0
3554 01:36:24.642197 4, 0xFFFF, sum = 0
3555 01:36:24.642252 5, 0xFFFF, sum = 0
3556 01:36:24.642306 6, 0xFFFF, sum = 0
3557 01:36:24.642360 7, 0xFFFF, sum = 0
3558 01:36:24.642413 8, 0xFFFF, sum = 0
3559 01:36:24.642467 9, 0xFFFF, sum = 0
3560 01:36:24.642524 10, 0xFFFF, sum = 0
3561 01:36:24.642583 11, 0xFFFF, sum = 0
3562 01:36:24.642637 12, 0x0, sum = 1
3563 01:36:24.642690 13, 0x0, sum = 2
3564 01:36:24.642743 14, 0x0, sum = 3
3565 01:36:24.642796 15, 0x0, sum = 4
3566 01:36:24.642849 best_step = 13
3567 01:36:24.642901
3568 01:36:24.642953 ==
3569 01:36:24.643005 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 01:36:24.643058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 01:36:24.643111 ==
3572 01:36:24.643163 RX Vref Scan: 0
3573 01:36:24.643216
3574 01:36:24.643268 RX Vref 0 -> 0, step: 1
3575 01:36:24.643320
3576 01:36:24.643371 RX Delay -13 -> 252, step: 4
3577 01:36:24.643423 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3578 01:36:24.643476 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3579 01:36:24.643528 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3580 01:36:24.643580 iDelay=191, Bit 3, Center 114 (47 ~ 182) 136
3581 01:36:24.643632 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3582 01:36:24.643684 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3583 01:36:24.643736 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3584 01:36:24.643789 iDelay=191, Bit 7, Center 114 (47 ~ 182) 136
3585 01:36:24.643841 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3586 01:36:24.643893 iDelay=191, Bit 9, Center 104 (43 ~ 166) 124
3587 01:36:24.643946 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3588 01:36:24.643999 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3589 01:36:24.644051 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3590 01:36:24.644103 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3591 01:36:24.644156 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3592 01:36:24.644208 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3593 01:36:24.644260 ==
3594 01:36:24.644312 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 01:36:24.644365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 01:36:24.644418 ==
3597 01:36:24.644470 DQS Delay:
3598 01:36:24.644521 DQS0 = 0, DQS1 = 0
3599 01:36:24.644573 DQM Delay:
3600 01:36:24.644625 DQM0 = 115, DQM1 = 112
3601 01:36:24.644677 DQ Delay:
3602 01:36:24.644729 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =114
3603 01:36:24.644781 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =114
3604 01:36:24.644834 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3605 01:36:24.644885 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3606 01:36:24.644938
3607 01:36:24.644989
3608 01:36:24.645042 [DQSOSCAuto] RK1, (LSB)MR18= 0xf608, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3609 01:36:24.645095 CH1 RK1: MR19=304, MR18=F608
3610 01:36:24.645148 CH1_RK1: MR19=0x304, MR18=0xF608, DQSOSC=406, MR23=63, INC=39, DEC=26
3611 01:36:24.645206 [RxdqsGatingPostProcess] freq 1200
3612 01:36:24.645316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3613 01:36:24.645387 best DQS0 dly(2T, 0.5T) = (0, 11)
3614 01:36:24.645440 best DQS1 dly(2T, 0.5T) = (0, 11)
3615 01:36:24.645492 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3616 01:36:24.645545 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3617 01:36:24.645598 best DQS0 dly(2T, 0.5T) = (0, 11)
3618 01:36:24.645650 best DQS1 dly(2T, 0.5T) = (0, 11)
3619 01:36:24.645702 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3620 01:36:24.645754 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3621 01:36:24.645806 Pre-setting of DQS Precalculation
3622 01:36:24.645859 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3623 01:36:24.645912 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3624 01:36:24.645965 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3625 01:36:24.646018
3626 01:36:24.646071
3627 01:36:24.646154 [Calibration Summary] 2400 Mbps
3628 01:36:24.646207 CH 0, Rank 0
3629 01:36:24.646265 SW Impedance : PASS
3630 01:36:24.646322 DUTY Scan : NO K
3631 01:36:24.646376 ZQ Calibration : PASS
3632 01:36:24.646428 Jitter Meter : NO K
3633 01:36:24.646480 CBT Training : PASS
3634 01:36:24.646532 Write leveling : PASS
3635 01:36:24.646585 RX DQS gating : PASS
3636 01:36:24.646637 RX DQ/DQS(RDDQC) : PASS
3637 01:36:24.646689 TX DQ/DQS : PASS
3638 01:36:24.646742 RX DATLAT : PASS
3639 01:36:24.646794 RX DQ/DQS(Engine): PASS
3640 01:36:24.646846 TX OE : NO K
3641 01:36:24.646897 All Pass.
3642 01:36:24.646949
3643 01:36:24.647001 CH 0, Rank 1
3644 01:36:24.647053 SW Impedance : PASS
3645 01:36:24.647299 DUTY Scan : NO K
3646 01:36:24.647359 ZQ Calibration : PASS
3647 01:36:24.647413 Jitter Meter : NO K
3648 01:36:24.647467 CBT Training : PASS
3649 01:36:24.647519 Write leveling : PASS
3650 01:36:24.647572 RX DQS gating : PASS
3651 01:36:24.647625 RX DQ/DQS(RDDQC) : PASS
3652 01:36:24.647678 TX DQ/DQS : PASS
3653 01:36:24.647730 RX DATLAT : PASS
3654 01:36:24.647783 RX DQ/DQS(Engine): PASS
3655 01:36:24.647835 TX OE : NO K
3656 01:36:24.647888 All Pass.
3657 01:36:24.647940
3658 01:36:24.647993 CH 1, Rank 0
3659 01:36:24.648049 SW Impedance : PASS
3660 01:36:24.648145 DUTY Scan : NO K
3661 01:36:24.648199 ZQ Calibration : PASS
3662 01:36:24.648251 Jitter Meter : NO K
3663 01:36:24.648304 CBT Training : PASS
3664 01:36:24.648356 Write leveling : PASS
3665 01:36:24.648409 RX DQS gating : PASS
3666 01:36:24.648461 RX DQ/DQS(RDDQC) : PASS
3667 01:36:24.648513 TX DQ/DQS : PASS
3668 01:36:24.648566 RX DATLAT : PASS
3669 01:36:24.648619 RX DQ/DQS(Engine): PASS
3670 01:36:24.648670 TX OE : NO K
3671 01:36:24.648723 All Pass.
3672 01:36:24.648775
3673 01:36:24.648827 CH 1, Rank 1
3674 01:36:24.648879 SW Impedance : PASS
3675 01:36:24.648931 DUTY Scan : NO K
3676 01:36:24.648983 ZQ Calibration : PASS
3677 01:36:24.649035 Jitter Meter : NO K
3678 01:36:24.649088 CBT Training : PASS
3679 01:36:24.649139 Write leveling : PASS
3680 01:36:24.649192 RX DQS gating : PASS
3681 01:36:24.649244 RX DQ/DQS(RDDQC) : PASS
3682 01:36:24.649339 TX DQ/DQS : PASS
3683 01:36:24.649392 RX DATLAT : PASS
3684 01:36:24.649445 RX DQ/DQS(Engine): PASS
3685 01:36:24.649497 TX OE : NO K
3686 01:36:24.649549 All Pass.
3687 01:36:24.649601
3688 01:36:24.649653 DramC Write-DBI off
3689 01:36:24.649705 PER_BANK_REFRESH: Hybrid Mode
3690 01:36:24.649757 TX_TRACKING: ON
3691 01:36:24.649810 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3692 01:36:24.649863 [FAST_K] Save calibration result to emmc
3693 01:36:24.649916 dramc_set_vcore_voltage set vcore to 650000
3694 01:36:24.649968 Read voltage for 600, 5
3695 01:36:24.650021 Vio18 = 0
3696 01:36:24.650098 Vcore = 650000
3697 01:36:24.650163 Vdram = 0
3698 01:36:24.650215 Vddq = 0
3699 01:36:24.650268 Vmddr = 0
3700 01:36:24.650320 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3701 01:36:24.650373 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3702 01:36:24.650431 MEM_TYPE=3, freq_sel=19
3703 01:36:24.650488 sv_algorithm_assistance_LP4_1600
3704 01:36:24.650542 ============ PULL DRAM RESETB DOWN ============
3705 01:36:24.650595 ========== PULL DRAM RESETB DOWN end =========
3706 01:36:24.650647 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3707 01:36:24.650699 ===================================
3708 01:36:24.650752 LPDDR4 DRAM CONFIGURATION
3709 01:36:24.650804 ===================================
3710 01:36:24.650856 EX_ROW_EN[0] = 0x0
3711 01:36:24.650908 EX_ROW_EN[1] = 0x0
3712 01:36:24.650960 LP4Y_EN = 0x0
3713 01:36:24.651011 WORK_FSP = 0x0
3714 01:36:24.651063 WL = 0x2
3715 01:36:24.651115 RL = 0x2
3716 01:36:24.651167 BL = 0x2
3717 01:36:24.651219 RPST = 0x0
3718 01:36:24.651271 RD_PRE = 0x0
3719 01:36:24.651326 WR_PRE = 0x1
3720 01:36:24.651382 WR_PST = 0x0
3721 01:36:24.651435 DBI_WR = 0x0
3722 01:36:24.651486 DBI_RD = 0x0
3723 01:36:24.651538 OTF = 0x1
3724 01:36:24.651591 ===================================
3725 01:36:24.651643 ===================================
3726 01:36:24.651695 ANA top config
3727 01:36:24.651747 ===================================
3728 01:36:24.651800 DLL_ASYNC_EN = 0
3729 01:36:24.651852 ALL_SLAVE_EN = 1
3730 01:36:24.651904 NEW_RANK_MODE = 1
3731 01:36:24.651957 DLL_IDLE_MODE = 1
3732 01:36:24.652010 LP45_APHY_COMB_EN = 1
3733 01:36:24.652062 TX_ODT_DIS = 1
3734 01:36:24.652114 NEW_8X_MODE = 1
3735 01:36:24.652166 ===================================
3736 01:36:24.652219 ===================================
3737 01:36:24.652272 data_rate = 1200
3738 01:36:24.652324 CKR = 1
3739 01:36:24.652376 DQ_P2S_RATIO = 8
3740 01:36:24.652428 ===================================
3741 01:36:24.652481 CA_P2S_RATIO = 8
3742 01:36:24.652533 DQ_CA_OPEN = 0
3743 01:36:24.652585 DQ_SEMI_OPEN = 0
3744 01:36:24.652637 CA_SEMI_OPEN = 0
3745 01:36:24.652690 CA_FULL_RATE = 0
3746 01:36:24.652741 DQ_CKDIV4_EN = 1
3747 01:36:24.652794 CA_CKDIV4_EN = 1
3748 01:36:24.652845 CA_PREDIV_EN = 0
3749 01:36:24.652897 PH8_DLY = 0
3750 01:36:24.652968 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3751 01:36:24.653022 DQ_AAMCK_DIV = 4
3752 01:36:24.653074 CA_AAMCK_DIV = 4
3753 01:36:24.653127 CA_ADMCK_DIV = 4
3754 01:36:24.653179 DQ_TRACK_CA_EN = 0
3755 01:36:24.653231 CA_PICK = 600
3756 01:36:24.653310 CA_MCKIO = 600
3757 01:36:24.653377 MCKIO_SEMI = 0
3758 01:36:24.653429 PLL_FREQ = 2288
3759 01:36:24.653481 DQ_UI_PI_RATIO = 32
3760 01:36:24.653533 CA_UI_PI_RATIO = 0
3761 01:36:24.653585 ===================================
3762 01:36:24.653637 ===================================
3763 01:36:24.653690 memory_type:LPDDR4
3764 01:36:24.653742 GP_NUM : 10
3765 01:36:24.653794 SRAM_EN : 1
3766 01:36:24.653846 MD32_EN : 0
3767 01:36:24.653898 ===================================
3768 01:36:24.653950 [ANA_INIT] >>>>>>>>>>>>>>
3769 01:36:24.654002 <<<<<< [CONFIGURE PHASE]: ANA_TX
3770 01:36:24.654055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3771 01:36:24.654108 ===================================
3772 01:36:24.654165 data_rate = 1200,PCW = 0X5800
3773 01:36:24.654225 ===================================
3774 01:36:24.654279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3775 01:36:24.654333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3776 01:36:24.654386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3777 01:36:24.654439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3778 01:36:24.654492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3779 01:36:24.654545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3780 01:36:24.654597 [ANA_INIT] flow start
3781 01:36:24.654649 [ANA_INIT] PLL >>>>>>>>
3782 01:36:24.654701 [ANA_INIT] PLL <<<<<<<<
3783 01:36:24.654754 [ANA_INIT] MIDPI >>>>>>>>
3784 01:36:24.654806 [ANA_INIT] MIDPI <<<<<<<<
3785 01:36:24.654858 [ANA_INIT] DLL >>>>>>>>
3786 01:36:24.654910 [ANA_INIT] flow end
3787 01:36:24.655154 ============ LP4 DIFF to SE enter ============
3788 01:36:24.655214 ============ LP4 DIFF to SE exit ============
3789 01:36:24.655269 [ANA_INIT] <<<<<<<<<<<<<
3790 01:36:24.655322 [Flow] Enable top DCM control >>>>>
3791 01:36:24.655376 [Flow] Enable top DCM control <<<<<
3792 01:36:24.655429 Enable DLL master slave shuffle
3793 01:36:24.655482 ==============================================================
3794 01:36:24.655535 Gating Mode config
3795 01:36:24.655588 ==============================================================
3796 01:36:24.655641 Config description:
3797 01:36:24.655693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3798 01:36:24.655747 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3799 01:36:24.655800 SELPH_MODE 0: By rank 1: By Phase
3800 01:36:24.655853 ==============================================================
3801 01:36:24.655906 GAT_TRACK_EN = 1
3802 01:36:24.655958 RX_GATING_MODE = 2
3803 01:36:24.656010 RX_GATING_TRACK_MODE = 2
3804 01:36:24.656062 SELPH_MODE = 1
3805 01:36:24.656115 PICG_EARLY_EN = 1
3806 01:36:24.656167 VALID_LAT_VALUE = 1
3807 01:36:24.656220 ==============================================================
3808 01:36:24.656272 Enter into Gating configuration >>>>
3809 01:36:24.656325 Exit from Gating configuration <<<<
3810 01:36:24.656377 Enter into DVFS_PRE_config >>>>>
3811 01:36:24.656431 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3812 01:36:24.656484 Exit from DVFS_PRE_config <<<<<
3813 01:36:24.656537 Enter into PICG configuration >>>>
3814 01:36:24.656589 Exit from PICG configuration <<<<
3815 01:36:24.656641 [RX_INPUT] configuration >>>>>
3816 01:36:24.656693 [RX_INPUT] configuration <<<<<
3817 01:36:24.656746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3818 01:36:24.656798 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3819 01:36:24.656851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3820 01:36:24.656904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3821 01:36:24.656956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3822 01:36:24.657008 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3823 01:36:24.657061 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3824 01:36:24.657113 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3825 01:36:24.657165 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3826 01:36:24.657217 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3827 01:36:24.657296 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3828 01:36:24.657364 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3829 01:36:24.657417 ===================================
3830 01:36:24.657469 LPDDR4 DRAM CONFIGURATION
3831 01:36:24.657521 ===================================
3832 01:36:24.657573 EX_ROW_EN[0] = 0x0
3833 01:36:24.657625 EX_ROW_EN[1] = 0x0
3834 01:36:24.657678 LP4Y_EN = 0x0
3835 01:36:24.657729 WORK_FSP = 0x0
3836 01:36:24.657782 WL = 0x2
3837 01:36:24.657833 RL = 0x2
3838 01:36:24.657886 BL = 0x2
3839 01:36:24.657937 RPST = 0x0
3840 01:36:24.658180 RD_PRE = 0x0
3841 01:36:24.658242 WR_PRE = 0x1
3842 01:36:24.661117 WR_PST = 0x0
3843 01:36:24.661225 DBI_WR = 0x0
3844 01:36:24.664644 DBI_RD = 0x0
3845 01:36:24.664725 OTF = 0x1
3846 01:36:24.668242 ===================================
3847 01:36:24.674598 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3848 01:36:24.677961 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3849 01:36:24.681476 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 01:36:24.684111 ===================================
3851 01:36:24.688244 LPDDR4 DRAM CONFIGURATION
3852 01:36:24.690942 ===================================
3853 01:36:24.694221 EX_ROW_EN[0] = 0x10
3854 01:36:24.694303 EX_ROW_EN[1] = 0x0
3855 01:36:24.697497 LP4Y_EN = 0x0
3856 01:36:24.697578 WORK_FSP = 0x0
3857 01:36:24.700681 WL = 0x2
3858 01:36:24.700762 RL = 0x2
3859 01:36:24.704223 BL = 0x2
3860 01:36:24.704304 RPST = 0x0
3861 01:36:24.707518 RD_PRE = 0x0
3862 01:36:24.707599 WR_PRE = 0x1
3863 01:36:24.710368 WR_PST = 0x0
3864 01:36:24.710450 DBI_WR = 0x0
3865 01:36:24.714350 DBI_RD = 0x0
3866 01:36:24.714431 OTF = 0x1
3867 01:36:24.716861 ===================================
3868 01:36:24.723486 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3869 01:36:24.728431 nWR fixed to 30
3870 01:36:24.731941 [ModeRegInit_LP4] CH0 RK0
3871 01:36:24.732022 [ModeRegInit_LP4] CH0 RK1
3872 01:36:24.735163 [ModeRegInit_LP4] CH1 RK0
3873 01:36:24.738531 [ModeRegInit_LP4] CH1 RK1
3874 01:36:24.738613 match AC timing 17
3875 01:36:24.745144 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3876 01:36:24.748453 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3877 01:36:24.751716 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3878 01:36:24.758511 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3879 01:36:24.761704 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3880 01:36:24.761786 ==
3881 01:36:24.764902 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 01:36:24.767940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3883 01:36:24.768025 ==
3884 01:36:24.774441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3885 01:36:24.781192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3886 01:36:24.784310 [CA 0] Center 36 (6~67) winsize 62
3887 01:36:24.787828 [CA 1] Center 36 (5~67) winsize 63
3888 01:36:24.791188 [CA 2] Center 34 (4~65) winsize 62
3889 01:36:24.794218 [CA 3] Center 34 (3~65) winsize 63
3890 01:36:24.797514 [CA 4] Center 33 (3~64) winsize 62
3891 01:36:24.801031 [CA 5] Center 33 (3~64) winsize 62
3892 01:36:24.801112
3893 01:36:24.804431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3894 01:36:24.804513
3895 01:36:24.807632 [CATrainingPosCal] consider 1 rank data
3896 01:36:24.810884 u2DelayCellTimex100 = 270/100 ps
3897 01:36:24.814195 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3898 01:36:24.817255 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3899 01:36:24.824064 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3900 01:36:24.827320 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3901 01:36:24.830572 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3902 01:36:24.833849 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3903 01:36:24.833931
3904 01:36:24.837151 CA PerBit enable=1, Macro0, CA PI delay=33
3905 01:36:24.837233
3906 01:36:24.840567 [CBTSetCACLKResult] CA Dly = 33
3907 01:36:24.840650 CS Dly: 5 (0~36)
3908 01:36:24.840715 ==
3909 01:36:24.843918 Dram Type= 6, Freq= 0, CH_0, rank 1
3910 01:36:24.850547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 01:36:24.850630 ==
3912 01:36:24.853893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 01:36:24.860501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3914 01:36:24.864025 [CA 0] Center 36 (6~67) winsize 62
3915 01:36:24.867392 [CA 1] Center 36 (6~67) winsize 62
3916 01:36:24.870355 [CA 2] Center 34 (4~65) winsize 62
3917 01:36:24.874429 [CA 3] Center 34 (4~65) winsize 62
3918 01:36:24.877712 [CA 4] Center 34 (3~65) winsize 63
3919 01:36:24.880539 [CA 5] Center 34 (3~65) winsize 63
3920 01:36:24.880621
3921 01:36:24.883907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3922 01:36:24.883989
3923 01:36:24.886946 [CATrainingPosCal] consider 2 rank data
3924 01:36:24.890684 u2DelayCellTimex100 = 270/100 ps
3925 01:36:24.893655 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 01:36:24.900021 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 01:36:24.903405 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 01:36:24.906803 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 01:36:24.909823 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 01:36:24.913612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 01:36:24.913694
3932 01:36:24.916515 CA PerBit enable=1, Macro0, CA PI delay=33
3933 01:36:24.916597
3934 01:36:24.920237 [CBTSetCACLKResult] CA Dly = 33
3935 01:36:24.923083 CS Dly: 6 (0~38)
3936 01:36:24.923165
3937 01:36:24.926269 ----->DramcWriteLeveling(PI) begin...
3938 01:36:24.926353 ==
3939 01:36:24.929574 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 01:36:24.933135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 01:36:24.933217 ==
3942 01:36:24.936358 Write leveling (Byte 0): 33 => 33
3943 01:36:24.939780 Write leveling (Byte 1): 32 => 32
3944 01:36:24.942737 DramcWriteLeveling(PI) end<-----
3945 01:36:24.942819
3946 01:36:24.942884 ==
3947 01:36:24.946054 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 01:36:24.949152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 01:36:24.949234 ==
3950 01:36:24.952785 [Gating] SW mode calibration
3951 01:36:24.959432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3952 01:36:24.965478 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3953 01:36:24.968676 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3954 01:36:24.975554 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3955 01:36:24.978744 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3956 01:36:24.982141 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
3957 01:36:24.988799 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
3958 01:36:24.991974 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3959 01:36:24.995586 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3960 01:36:25.001813 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 01:36:25.005484 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 01:36:25.008605 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 01:36:25.014943 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 01:36:25.018303 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3965 01:36:25.021753 0 10 16 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
3966 01:36:25.028278 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3967 01:36:25.031650 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3968 01:36:25.034548 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 01:36:25.041435 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 01:36:25.044530 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 01:36:25.048363 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 01:36:25.054226 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 01:36:25.057741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3974 01:36:25.060848 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 01:36:25.067799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 01:36:25.071272 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 01:36:25.074192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 01:36:25.080706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 01:36:25.083920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 01:36:25.087423 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 01:36:25.093656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 01:36:25.097492 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 01:36:25.100787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 01:36:25.106804 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 01:36:25.110267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 01:36:25.113966 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 01:36:25.120393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3988 01:36:25.123651 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3989 01:36:25.126729 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3990 01:36:25.129871 Total UI for P1: 0, mck2ui 16
3991 01:36:25.133248 best dqsien dly found for B0: ( 0, 13, 10)
3992 01:36:25.140444 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 01:36:25.140528 Total UI for P1: 0, mck2ui 16
3994 01:36:25.146454 best dqsien dly found for B1: ( 0, 13, 16)
3995 01:36:25.149667 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
3996 01:36:25.152986 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
3997 01:36:25.153070
3998 01:36:25.156313 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
3999 01:36:25.159709 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4000 01:36:25.162829 [Gating] SW calibration Done
4001 01:36:25.162911 ==
4002 01:36:25.166056 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 01:36:25.169911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 01:36:25.169995 ==
4005 01:36:25.172971 RX Vref Scan: 0
4006 01:36:25.173053
4007 01:36:25.176011 RX Vref 0 -> 0, step: 1
4008 01:36:25.176094
4009 01:36:25.176158 RX Delay -230 -> 252, step: 16
4010 01:36:25.182957 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4011 01:36:25.186309 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4012 01:36:25.189064 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4013 01:36:25.193312 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4014 01:36:25.199257 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4015 01:36:25.202778 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4016 01:36:25.205723 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4017 01:36:25.209115 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4018 01:36:25.216108 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4019 01:36:25.219031 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4020 01:36:25.222330 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4021 01:36:25.225493 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4022 01:36:25.232194 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4023 01:36:25.235437 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4024 01:36:25.238907 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4025 01:36:25.242316 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4026 01:36:25.242398 ==
4027 01:36:25.245558 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 01:36:25.252076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 01:36:25.252159 ==
4030 01:36:25.252224 DQS Delay:
4031 01:36:25.255661 DQS0 = 0, DQS1 = 0
4032 01:36:25.255743 DQM Delay:
4033 01:36:25.255809 DQM0 = 47, DQM1 = 37
4034 01:36:25.258361 DQ Delay:
4035 01:36:25.261528 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4036 01:36:25.264925 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4037 01:36:25.268142 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4038 01:36:25.271681 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4039 01:36:25.271763
4040 01:36:25.271827
4041 01:36:25.271887 ==
4042 01:36:25.274660 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 01:36:25.278073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 01:36:25.278156 ==
4045 01:36:25.278222
4046 01:36:25.278282
4047 01:36:25.281209 TX Vref Scan disable
4048 01:36:25.284651 == TX Byte 0 ==
4049 01:36:25.288398 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4050 01:36:25.291230 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4051 01:36:25.294676 == TX Byte 1 ==
4052 01:36:25.297916 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4053 01:36:25.301261 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4054 01:36:25.301343 ==
4055 01:36:25.304519 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 01:36:25.310740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 01:36:25.310824 ==
4058 01:36:25.310888
4059 01:36:25.310971
4060 01:36:25.311043 TX Vref Scan disable
4061 01:36:25.315564 == TX Byte 0 ==
4062 01:36:25.318750 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4063 01:36:25.325212 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4064 01:36:25.325320 == TX Byte 1 ==
4065 01:36:25.328980 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4066 01:36:25.335190 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4067 01:36:25.335276
4068 01:36:25.335340 [DATLAT]
4069 01:36:25.335400 Freq=600, CH0 RK0
4070 01:36:25.335459
4071 01:36:25.338271 DATLAT Default: 0x9
4072 01:36:25.338352 0, 0xFFFF, sum = 0
4073 01:36:25.341903 1, 0xFFFF, sum = 0
4074 01:36:25.344771 2, 0xFFFF, sum = 0
4075 01:36:25.344853 3, 0xFFFF, sum = 0
4076 01:36:25.348073 4, 0xFFFF, sum = 0
4077 01:36:25.348156 5, 0xFFFF, sum = 0
4078 01:36:25.351925 6, 0xFFFF, sum = 0
4079 01:36:25.352008 7, 0xFFFF, sum = 0
4080 01:36:25.355119 8, 0x0, sum = 1
4081 01:36:25.355203 9, 0x0, sum = 2
4082 01:36:25.358455 10, 0x0, sum = 3
4083 01:36:25.358538 11, 0x0, sum = 4
4084 01:36:25.358604 best_step = 9
4085 01:36:25.358664
4086 01:36:25.361732 ==
4087 01:36:25.361814 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 01:36:25.367851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 01:36:25.367933 ==
4090 01:36:25.367998 RX Vref Scan: 1
4091 01:36:25.368057
4092 01:36:25.371329 RX Vref 0 -> 0, step: 1
4093 01:36:25.371411
4094 01:36:25.374584 RX Delay -195 -> 252, step: 8
4095 01:36:25.374667
4096 01:36:25.378165 Set Vref, RX VrefLevel [Byte0]: 53
4097 01:36:25.381582 [Byte1]: 50
4098 01:36:25.381665
4099 01:36:25.384364 Final RX Vref Byte 0 = 53 to rank0
4100 01:36:25.387875 Final RX Vref Byte 1 = 50 to rank0
4101 01:36:25.391157 Final RX Vref Byte 0 = 53 to rank1
4102 01:36:25.394547 Final RX Vref Byte 1 = 50 to rank1==
4103 01:36:25.397436 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 01:36:25.400847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 01:36:25.404491 ==
4106 01:36:25.404573 DQS Delay:
4107 01:36:25.404637 DQS0 = 0, DQS1 = 0
4108 01:36:25.407553 DQM Delay:
4109 01:36:25.407635 DQM0 = 41, DQM1 = 33
4110 01:36:25.411118 DQ Delay:
4111 01:36:25.414246 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4112 01:36:25.414328 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4113 01:36:25.417370 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4114 01:36:25.423859 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4115 01:36:25.423942
4116 01:36:25.424006
4117 01:36:25.430724 [DQSOSCAuto] RK0, (LSB)MR18= 0x4840, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4118 01:36:25.433880 CH0 RK0: MR19=808, MR18=4840
4119 01:36:25.440426 CH0_RK0: MR19=0x808, MR18=0x4840, DQSOSC=396, MR23=63, INC=167, DEC=111
4120 01:36:25.440510
4121 01:36:25.443590 ----->DramcWriteLeveling(PI) begin...
4122 01:36:25.443673 ==
4123 01:36:25.447081 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 01:36:25.450235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 01:36:25.450319 ==
4126 01:36:25.453396 Write leveling (Byte 0): 36 => 36
4127 01:36:25.457098 Write leveling (Byte 1): 29 => 29
4128 01:36:25.459998 DramcWriteLeveling(PI) end<-----
4129 01:36:25.460079
4130 01:36:25.460143 ==
4131 01:36:25.463407 Dram Type= 6, Freq= 0, CH_0, rank 1
4132 01:36:25.466970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 01:36:25.470229 ==
4134 01:36:25.470311 [Gating] SW mode calibration
4135 01:36:25.479936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4136 01:36:25.483139 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4137 01:36:25.486390 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4138 01:36:25.493090 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4139 01:36:25.496756 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4140 01:36:25.499771 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
4141 01:36:25.505943 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
4142 01:36:25.509760 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4143 01:36:25.512526 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4144 01:36:25.519205 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 01:36:25.522989 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 01:36:25.525972 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 01:36:25.532806 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 01:36:25.536025 0 10 12 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4149 01:36:25.538970 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4150 01:36:25.545802 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4151 01:36:25.548771 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4152 01:36:25.552245 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 01:36:25.558584 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 01:36:25.562038 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 01:36:25.565218 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4156 01:36:25.571722 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4157 01:36:25.575568 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4158 01:36:25.578632 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4159 01:36:25.585131 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 01:36:25.588825 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 01:36:25.591696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 01:36:25.598150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 01:36:25.601449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 01:36:25.604698 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 01:36:25.611489 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 01:36:25.614498 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 01:36:25.618900 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 01:36:25.624393 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 01:36:25.627725 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 01:36:25.634268 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 01:36:25.637441 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 01:36:25.641001 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4173 01:36:25.647720 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4174 01:36:25.647803 Total UI for P1: 0, mck2ui 16
4175 01:36:25.650646 best dqsien dly found for B0: ( 0, 13, 12)
4176 01:36:25.657287 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 01:36:25.660639 Total UI for P1: 0, mck2ui 16
4178 01:36:25.663921 best dqsien dly found for B1: ( 0, 13, 14)
4179 01:36:25.667274 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4180 01:36:25.670488 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4181 01:36:25.670570
4182 01:36:25.673806 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4183 01:36:25.677265 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4184 01:36:25.680095 [Gating] SW calibration Done
4185 01:36:25.680178 ==
4186 01:36:25.683509 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 01:36:25.687043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 01:36:25.690017 ==
4189 01:36:25.690099 RX Vref Scan: 0
4190 01:36:25.690163
4191 01:36:25.693411 RX Vref 0 -> 0, step: 1
4192 01:36:25.693493
4193 01:36:25.697063 RX Delay -230 -> 252, step: 16
4194 01:36:25.700260 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4195 01:36:25.703872 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4196 01:36:25.707111 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4197 01:36:25.713126 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4198 01:36:25.716521 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4199 01:36:25.719575 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4200 01:36:25.723221 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4201 01:36:25.729593 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4202 01:36:25.733378 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4203 01:36:25.735852 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4204 01:36:25.739400 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4205 01:36:25.746035 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4206 01:36:25.749203 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4207 01:36:25.752431 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4208 01:36:25.755624 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4209 01:36:25.762665 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4210 01:36:25.762748 ==
4211 01:36:25.765951 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 01:36:25.768995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 01:36:25.769078 ==
4214 01:36:25.769142 DQS Delay:
4215 01:36:25.772317 DQS0 = 0, DQS1 = 0
4216 01:36:25.772399 DQM Delay:
4217 01:36:25.775759 DQM0 = 41, DQM1 = 34
4218 01:36:25.775845 DQ Delay:
4219 01:36:25.778949 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4220 01:36:25.782008 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4221 01:36:25.785590 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4222 01:36:25.788789 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4223 01:36:25.788871
4224 01:36:25.788936
4225 01:36:25.788995 ==
4226 01:36:25.792107 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 01:36:25.795326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 01:36:25.798282 ==
4229 01:36:25.798364
4230 01:36:25.798428
4231 01:36:25.798488 TX Vref Scan disable
4232 01:36:25.801995 == TX Byte 0 ==
4233 01:36:25.804996 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4234 01:36:25.808110 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4235 01:36:25.811819 == TX Byte 1 ==
4236 01:36:25.815371 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4237 01:36:25.822072 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4238 01:36:25.822155 ==
4239 01:36:25.824892 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 01:36:25.828370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 01:36:25.828452 ==
4242 01:36:25.828516
4243 01:36:25.828576
4244 01:36:25.831560 TX Vref Scan disable
4245 01:36:25.835810 == TX Byte 0 ==
4246 01:36:25.837986 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4247 01:36:25.841319 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4248 01:36:25.844848 == TX Byte 1 ==
4249 01:36:25.848105 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4250 01:36:25.851525 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4251 01:36:25.851608
4252 01:36:25.851672 [DATLAT]
4253 01:36:25.854778 Freq=600, CH0 RK1
4254 01:36:25.854861
4255 01:36:25.858233 DATLAT Default: 0x9
4256 01:36:25.858316 0, 0xFFFF, sum = 0
4257 01:36:25.861321 1, 0xFFFF, sum = 0
4258 01:36:25.861405 2, 0xFFFF, sum = 0
4259 01:36:25.864914 3, 0xFFFF, sum = 0
4260 01:36:25.864997 4, 0xFFFF, sum = 0
4261 01:36:25.867863 5, 0xFFFF, sum = 0
4262 01:36:25.867947 6, 0xFFFF, sum = 0
4263 01:36:25.871210 7, 0xFFFF, sum = 0
4264 01:36:25.871293 8, 0x0, sum = 1
4265 01:36:25.874444 9, 0x0, sum = 2
4266 01:36:25.874527 10, 0x0, sum = 3
4267 01:36:25.877755 11, 0x0, sum = 4
4268 01:36:25.877838 best_step = 9
4269 01:36:25.877904
4270 01:36:25.877963 ==
4271 01:36:25.880920 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 01:36:25.884786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 01:36:25.884869 ==
4274 01:36:25.887828 RX Vref Scan: 0
4275 01:36:25.887910
4276 01:36:25.890926 RX Vref 0 -> 0, step: 1
4277 01:36:25.891008
4278 01:36:25.891073 RX Delay -179 -> 252, step: 8
4279 01:36:25.898926 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4280 01:36:25.902069 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4281 01:36:25.905268 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4282 01:36:25.908348 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4283 01:36:25.915025 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4284 01:36:25.919339 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4285 01:36:25.921616 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4286 01:36:25.925625 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4287 01:36:25.931998 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4288 01:36:25.935191 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4289 01:36:25.938267 iDelay=197, Bit 10, Center 32 (-123 ~ 188) 312
4290 01:36:25.941519 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4291 01:36:25.948164 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4292 01:36:25.951303 iDelay=197, Bit 13, Center 36 (-115 ~ 188) 304
4293 01:36:25.954703 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4294 01:36:25.958392 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4295 01:36:25.958475 ==
4296 01:36:25.961281 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 01:36:25.968122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 01:36:25.968204 ==
4299 01:36:25.968269 DQS Delay:
4300 01:36:25.970986 DQS0 = 0, DQS1 = 0
4301 01:36:25.971067 DQM Delay:
4302 01:36:25.971132 DQM0 = 41, DQM1 = 33
4303 01:36:25.974777 DQ Delay:
4304 01:36:25.977673 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4305 01:36:25.981197 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4306 01:36:25.984079 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4307 01:36:25.987593 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4308 01:36:25.987675
4309 01:36:25.987739
4310 01:36:25.994163 [DQSOSCAuto] RK1, (LSB)MR18= 0x4440, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4311 01:36:25.997451 CH0 RK1: MR19=808, MR18=4440
4312 01:36:26.003908 CH0_RK1: MR19=0x808, MR18=0x4440, DQSOSC=396, MR23=63, INC=167, DEC=111
4313 01:36:26.007107 [RxdqsGatingPostProcess] freq 600
4314 01:36:26.013781 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4315 01:36:26.013869 Pre-setting of DQS Precalculation
4316 01:36:26.020632 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4317 01:36:26.020713 ==
4318 01:36:26.023699 Dram Type= 6, Freq= 0, CH_1, rank 0
4319 01:36:26.026776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 01:36:26.026859 ==
4321 01:36:26.033481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4322 01:36:26.040409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4323 01:36:26.043723 [CA 0] Center 36 (6~66) winsize 61
4324 01:36:26.046679 [CA 1] Center 35 (5~66) winsize 62
4325 01:36:26.050059 [CA 2] Center 34 (4~65) winsize 62
4326 01:36:26.053557 [CA 3] Center 34 (3~65) winsize 63
4327 01:36:26.056809 [CA 4] Center 34 (4~65) winsize 62
4328 01:36:26.060526 [CA 5] Center 33 (3~64) winsize 62
4329 01:36:26.060608
4330 01:36:26.063473 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4331 01:36:26.063554
4332 01:36:26.066997 [CATrainingPosCal] consider 1 rank data
4333 01:36:26.070030 u2DelayCellTimex100 = 270/100 ps
4334 01:36:26.073078 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4335 01:36:26.076697 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4336 01:36:26.080116 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4337 01:36:26.083531 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4338 01:36:26.086700 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4339 01:36:26.093015 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4340 01:36:26.093096
4341 01:36:26.096499 CA PerBit enable=1, Macro0, CA PI delay=33
4342 01:36:26.096581
4343 01:36:26.099700 [CBTSetCACLKResult] CA Dly = 33
4344 01:36:26.099782 CS Dly: 5 (0~36)
4345 01:36:26.099847 ==
4346 01:36:26.103024 Dram Type= 6, Freq= 0, CH_1, rank 1
4347 01:36:26.106136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 01:36:26.109723 ==
4349 01:36:26.112969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 01:36:26.119276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4351 01:36:26.122848 [CA 0] Center 35 (5~66) winsize 62
4352 01:36:26.126061 [CA 1] Center 36 (6~66) winsize 61
4353 01:36:26.129587 [CA 2] Center 34 (4~65) winsize 62
4354 01:36:26.132795 [CA 3] Center 34 (3~65) winsize 63
4355 01:36:26.135891 [CA 4] Center 34 (4~65) winsize 62
4356 01:36:26.139467 [CA 5] Center 34 (3~65) winsize 63
4357 01:36:26.139549
4358 01:36:26.142735 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4359 01:36:26.142817
4360 01:36:26.145664 [CATrainingPosCal] consider 2 rank data
4361 01:36:26.149264 u2DelayCellTimex100 = 270/100 ps
4362 01:36:26.152622 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4363 01:36:26.155495 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4364 01:36:26.162649 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 01:36:26.165408 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4366 01:36:26.168675 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4367 01:36:26.172314 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 01:36:26.172397
4369 01:36:26.175572 CA PerBit enable=1, Macro0, CA PI delay=33
4370 01:36:26.175654
4371 01:36:26.178896 [CBTSetCACLKResult] CA Dly = 33
4372 01:36:26.178978 CS Dly: 5 (0~36)
4373 01:36:26.181948
4374 01:36:26.185602 ----->DramcWriteLeveling(PI) begin...
4375 01:36:26.185686 ==
4376 01:36:26.188733 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 01:36:26.191770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 01:36:26.191853 ==
4379 01:36:26.195222 Write leveling (Byte 0): 29 => 29
4380 01:36:26.198584 Write leveling (Byte 1): 29 => 29
4381 01:36:26.201837 DramcWriteLeveling(PI) end<-----
4382 01:36:26.201919
4383 01:36:26.201983 ==
4384 01:36:26.205247 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 01:36:26.208360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 01:36:26.208452 ==
4387 01:36:26.211450 [Gating] SW mode calibration
4388 01:36:26.218136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4389 01:36:26.224540 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4390 01:36:26.228254 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4391 01:36:26.231593 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4392 01:36:26.237755 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4393 01:36:26.241361 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4394 01:36:26.244453 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4395 01:36:26.251531 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 01:36:26.254980 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 01:36:26.258099 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 01:36:26.264186 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 01:36:26.267682 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 01:36:26.271099 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 01:36:26.277573 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
4402 01:36:26.280559 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 01:36:26.283984 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 01:36:26.290878 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 01:36:26.294079 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 01:36:26.297061 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 01:36:26.303964 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 01:36:26.306868 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 01:36:26.310610 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4410 01:36:26.316728 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 01:36:26.320219 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 01:36:26.324269 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 01:36:26.330605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 01:36:26.333400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 01:36:26.336710 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 01:36:26.343237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 01:36:26.346651 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 01:36:26.349789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 01:36:26.356474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 01:36:26.359749 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 01:36:26.363148 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 01:36:26.369540 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 01:36:26.373576 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 01:36:26.375863 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 01:36:26.382518 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 01:36:26.386309 Total UI for P1: 0, mck2ui 16
4427 01:36:26.389144 best dqsien dly found for B0: ( 0, 13, 10)
4428 01:36:26.392263 Total UI for P1: 0, mck2ui 16
4429 01:36:26.395799 best dqsien dly found for B1: ( 0, 13, 10)
4430 01:36:26.399222 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4431 01:36:26.402318 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4432 01:36:26.402400
4433 01:36:26.406332 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4434 01:36:26.408703 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4435 01:36:26.412333 [Gating] SW calibration Done
4436 01:36:26.412415 ==
4437 01:36:26.415507 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 01:36:26.418859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 01:36:26.422239 ==
4440 01:36:26.422321 RX Vref Scan: 0
4441 01:36:26.422386
4442 01:36:26.425712 RX Vref 0 -> 0, step: 1
4443 01:36:26.425794
4444 01:36:26.428544 RX Delay -230 -> 252, step: 16
4445 01:36:26.431781 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4446 01:36:26.434950 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4447 01:36:26.438716 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4448 01:36:26.444945 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4449 01:36:26.448605 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4450 01:36:26.451619 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4451 01:36:26.455134 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4452 01:36:26.458707 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4453 01:36:26.465145 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4454 01:36:26.468145 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4455 01:36:26.471959 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4456 01:36:26.474651 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4457 01:36:26.481514 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4458 01:36:26.484713 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4459 01:36:26.487848 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4460 01:36:26.490964 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4461 01:36:26.494532 ==
4462 01:36:26.497882 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 01:36:26.500904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 01:36:26.500986 ==
4465 01:36:26.501051 DQS Delay:
4466 01:36:26.504549 DQS0 = 0, DQS1 = 0
4467 01:36:26.504631 DQM Delay:
4468 01:36:26.507870 DQM0 = 41, DQM1 = 39
4469 01:36:26.507953 DQ Delay:
4470 01:36:26.510841 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4471 01:36:26.514117 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4472 01:36:26.517686 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4473 01:36:26.520899 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4474 01:36:26.520981
4475 01:36:26.521046
4476 01:36:26.521105 ==
4477 01:36:26.524232 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 01:36:26.527477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 01:36:26.527572 ==
4480 01:36:26.527641
4481 01:36:26.527702
4482 01:36:26.530627 TX Vref Scan disable
4483 01:36:26.533945 == TX Byte 0 ==
4484 01:36:26.537461 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4485 01:36:26.540737 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4486 01:36:26.544080 == TX Byte 1 ==
4487 01:36:26.547462 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4488 01:36:26.550742 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4489 01:36:26.550854 ==
4490 01:36:26.553796 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 01:36:26.561019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 01:36:26.561156 ==
4493 01:36:26.561287
4494 01:36:26.561392
4495 01:36:26.561489 TX Vref Scan disable
4496 01:36:26.564705 == TX Byte 0 ==
4497 01:36:26.568505 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4498 01:36:26.575136 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4499 01:36:26.575341 == TX Byte 1 ==
4500 01:36:26.578203 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4501 01:36:26.584986 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4502 01:36:26.585312
4503 01:36:26.585553 [DATLAT]
4504 01:36:26.585775 Freq=600, CH1 RK0
4505 01:36:26.585995
4506 01:36:26.588404 DATLAT Default: 0x9
4507 01:36:26.591344 0, 0xFFFF, sum = 0
4508 01:36:26.591744 1, 0xFFFF, sum = 0
4509 01:36:26.595365 2, 0xFFFF, sum = 0
4510 01:36:26.595792 3, 0xFFFF, sum = 0
4511 01:36:26.598069 4, 0xFFFF, sum = 0
4512 01:36:26.598499 5, 0xFFFF, sum = 0
4513 01:36:26.601726 6, 0xFFFF, sum = 0
4514 01:36:26.602156 7, 0xFFFF, sum = 0
4515 01:36:26.604576 8, 0x0, sum = 1
4516 01:36:26.605004 9, 0x0, sum = 2
4517 01:36:26.605385 10, 0x0, sum = 3
4518 01:36:26.608110 11, 0x0, sum = 4
4519 01:36:26.608550 best_step = 9
4520 01:36:26.608882
4521 01:36:26.611365 ==
4522 01:36:26.611819 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 01:36:26.618202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 01:36:26.618749 ==
4525 01:36:26.619099 RX Vref Scan: 1
4526 01:36:26.619416
4527 01:36:26.621362 RX Vref 0 -> 0, step: 1
4528 01:36:26.621789
4529 01:36:26.624665 RX Delay -179 -> 252, step: 8
4530 01:36:26.625096
4531 01:36:26.627982 Set Vref, RX VrefLevel [Byte0]: 53
4532 01:36:26.631125 [Byte1]: 54
4533 01:36:26.631557
4534 01:36:26.634334 Final RX Vref Byte 0 = 53 to rank0
4535 01:36:26.637577 Final RX Vref Byte 1 = 54 to rank0
4536 01:36:26.641118 Final RX Vref Byte 0 = 53 to rank1
4537 01:36:26.645209 Final RX Vref Byte 1 = 54 to rank1==
4538 01:36:26.647423 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 01:36:26.650519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 01:36:26.653956 ==
4541 01:36:26.654039 DQS Delay:
4542 01:36:26.654104 DQS0 = 0, DQS1 = 0
4543 01:36:26.657631 DQM Delay:
4544 01:36:26.657733 DQM0 = 41, DQM1 = 33
4545 01:36:26.660792 DQ Delay:
4546 01:36:26.660874 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4547 01:36:26.663989 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4548 01:36:26.667162 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4549 01:36:26.670388 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4550 01:36:26.673720
4551 01:36:26.673803
4552 01:36:26.679914 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4553 01:36:26.683693 CH1 RK0: MR19=808, MR18=2E48
4554 01:36:26.690246 CH1_RK0: MR19=0x808, MR18=0x2E48, DQSOSC=396, MR23=63, INC=167, DEC=111
4555 01:36:26.690329
4556 01:36:26.693473 ----->DramcWriteLeveling(PI) begin...
4557 01:36:26.693557 ==
4558 01:36:26.696712 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 01:36:26.700141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 01:36:26.700224 ==
4561 01:36:26.703447 Write leveling (Byte 0): 30 => 30
4562 01:36:26.706445 Write leveling (Byte 1): 30 => 30
4563 01:36:26.709736 DramcWriteLeveling(PI) end<-----
4564 01:36:26.709819
4565 01:36:26.709884 ==
4566 01:36:26.713058 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 01:36:26.716476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 01:36:26.716560 ==
4569 01:36:26.719610 [Gating] SW mode calibration
4570 01:36:26.726237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4571 01:36:26.732785 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4572 01:36:26.735937 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4573 01:36:26.742531 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4574 01:36:26.745931 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4575 01:36:26.749253 0 9 12 | B1->B0 | 3131 2727 | 0 0 | (0 0) (1 0)
4576 01:36:26.756106 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4577 01:36:26.759087 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4578 01:36:26.762595 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4579 01:36:26.769148 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 01:36:26.772881 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 01:36:26.775361 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 01:36:26.782154 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4583 01:36:26.785964 0 10 12 | B1->B0 | 2b2b 3d3d | 1 0 | (0 0) (0 0)
4584 01:36:26.788934 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4585 01:36:26.795413 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4586 01:36:26.798593 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4587 01:36:26.802303 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4588 01:36:26.808429 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 01:36:26.812117 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 01:36:26.814895 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 01:36:26.821770 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4592 01:36:26.824927 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4593 01:36:26.828543 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 01:36:26.834908 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 01:36:26.838709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 01:36:26.841248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 01:36:26.847992 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 01:36:26.851326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 01:36:26.854864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 01:36:26.861286 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 01:36:26.864786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 01:36:26.867685 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 01:36:26.874244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 01:36:26.877702 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 01:36:26.880856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 01:36:26.887220 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 01:36:26.890719 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4608 01:36:26.894091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 01:36:26.897158 Total UI for P1: 0, mck2ui 16
4610 01:36:26.900782 best dqsien dly found for B0: ( 0, 13, 12)
4611 01:36:26.904062 Total UI for P1: 0, mck2ui 16
4612 01:36:26.906995 best dqsien dly found for B1: ( 0, 13, 12)
4613 01:36:26.910421 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4614 01:36:26.916876 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4615 01:36:26.916959
4616 01:36:26.920974 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4617 01:36:26.923691 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4618 01:36:26.927172 [Gating] SW calibration Done
4619 01:36:26.927288 ==
4620 01:36:26.930690 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 01:36:26.933746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 01:36:26.933830 ==
4623 01:36:26.936575 RX Vref Scan: 0
4624 01:36:26.936657
4625 01:36:26.936723 RX Vref 0 -> 0, step: 1
4626 01:36:26.936784
4627 01:36:26.940096 RX Delay -230 -> 252, step: 16
4628 01:36:26.943724 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4629 01:36:26.949673 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4630 01:36:26.953238 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4631 01:36:26.956693 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4632 01:36:26.959732 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4633 01:36:26.966838 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4634 01:36:26.969977 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4635 01:36:26.972998 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4636 01:36:26.976355 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4637 01:36:26.982722 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4638 01:36:26.985955 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4639 01:36:26.989816 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4640 01:36:26.992643 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4641 01:36:26.999486 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4642 01:36:27.003014 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4643 01:36:27.006101 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4644 01:36:27.006184 ==
4645 01:36:27.009182 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 01:36:27.012408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 01:36:27.012491 ==
4648 01:36:27.015722 DQS Delay:
4649 01:36:27.015805 DQS0 = 0, DQS1 = 0
4650 01:36:27.019107 DQM Delay:
4651 01:36:27.019189 DQM0 = 41, DQM1 = 38
4652 01:36:27.019259 DQ Delay:
4653 01:36:27.022703 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4654 01:36:27.025639 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4655 01:36:27.028838 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4656 01:36:27.031956 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4657 01:36:27.032039
4658 01:36:27.035547
4659 01:36:27.035630 ==
4660 01:36:27.039342 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 01:36:27.042234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 01:36:27.042343 ==
4663 01:36:27.042437
4664 01:36:27.042526
4665 01:36:27.045403 TX Vref Scan disable
4666 01:36:27.045486 == TX Byte 0 ==
4667 01:36:27.052030 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4668 01:36:27.055669 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4669 01:36:27.055753 == TX Byte 1 ==
4670 01:36:27.061879 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4671 01:36:27.065277 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4672 01:36:27.065362 ==
4673 01:36:27.068603 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 01:36:27.071633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 01:36:27.071717 ==
4676 01:36:27.071783
4677 01:36:27.071844
4678 01:36:27.075086 TX Vref Scan disable
4679 01:36:27.078334 == TX Byte 0 ==
4680 01:36:27.081572 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4681 01:36:27.085210 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4682 01:36:27.087902 == TX Byte 1 ==
4683 01:36:27.091439 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4684 01:36:27.098028 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4685 01:36:27.098111
4686 01:36:27.098176 [DATLAT]
4687 01:36:27.098237 Freq=600, CH1 RK1
4688 01:36:27.098297
4689 01:36:27.101421 DATLAT Default: 0x9
4690 01:36:27.101504 0, 0xFFFF, sum = 0
4691 01:36:27.104763 1, 0xFFFF, sum = 0
4692 01:36:27.108070 2, 0xFFFF, sum = 0
4693 01:36:27.108154 3, 0xFFFF, sum = 0
4694 01:36:27.111538 4, 0xFFFF, sum = 0
4695 01:36:27.111622 5, 0xFFFF, sum = 0
4696 01:36:27.114625 6, 0xFFFF, sum = 0
4697 01:36:27.114709 7, 0xFFFF, sum = 0
4698 01:36:27.117805 8, 0x0, sum = 1
4699 01:36:27.117890 9, 0x0, sum = 2
4700 01:36:27.117956 10, 0x0, sum = 3
4701 01:36:27.121307 11, 0x0, sum = 4
4702 01:36:27.121391 best_step = 9
4703 01:36:27.121457
4704 01:36:27.121518 ==
4705 01:36:27.124528 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 01:36:27.131257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 01:36:27.131341 ==
4708 01:36:27.131407 RX Vref Scan: 0
4709 01:36:27.131468
4710 01:36:27.134269 RX Vref 0 -> 0, step: 1
4711 01:36:27.134351
4712 01:36:27.137577 RX Delay -179 -> 252, step: 8
4713 01:36:27.144496 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4714 01:36:27.147475 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4715 01:36:27.150702 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4716 01:36:27.154166 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4717 01:36:27.157180 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4718 01:36:27.163615 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4719 01:36:27.167569 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4720 01:36:27.170538 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4721 01:36:27.173668 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4722 01:36:27.181170 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4723 01:36:27.183634 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4724 01:36:27.186763 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4725 01:36:27.190156 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4726 01:36:27.197546 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4727 01:36:27.200142 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4728 01:36:27.203876 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4729 01:36:27.203960 ==
4730 01:36:27.207172 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 01:36:27.210262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 01:36:27.213599 ==
4733 01:36:27.213682 DQS Delay:
4734 01:36:27.213747 DQS0 = 0, DQS1 = 0
4735 01:36:27.216854 DQM Delay:
4736 01:36:27.216936 DQM0 = 37, DQM1 = 35
4737 01:36:27.219673 DQ Delay:
4738 01:36:27.223088 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4739 01:36:27.223171 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4740 01:36:27.226520 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4741 01:36:27.232881 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4742 01:36:27.232964
4743 01:36:27.233029
4744 01:36:27.239760 [DQSOSCAuto] RK1, (LSB)MR18= 0x375c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4745 01:36:27.242981 CH1 RK1: MR19=808, MR18=375C
4746 01:36:27.249887 CH1_RK1: MR19=0x808, MR18=0x375C, DQSOSC=392, MR23=63, INC=170, DEC=113
4747 01:36:27.252940 [RxdqsGatingPostProcess] freq 600
4748 01:36:27.256164 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4749 01:36:27.259468 Pre-setting of DQS Precalculation
4750 01:36:27.265806 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4751 01:36:27.272584 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4752 01:36:27.279076 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4753 01:36:27.279160
4754 01:36:27.279225
4755 01:36:27.283002 [Calibration Summary] 1200 Mbps
4756 01:36:27.283085 CH 0, Rank 0
4757 01:36:27.285825 SW Impedance : PASS
4758 01:36:27.289461 DUTY Scan : NO K
4759 01:36:27.289545 ZQ Calibration : PASS
4760 01:36:27.292356 Jitter Meter : NO K
4761 01:36:27.295536 CBT Training : PASS
4762 01:36:27.295619 Write leveling : PASS
4763 01:36:27.298876 RX DQS gating : PASS
4764 01:36:27.301953 RX DQ/DQS(RDDQC) : PASS
4765 01:36:27.302036 TX DQ/DQS : PASS
4766 01:36:27.305436 RX DATLAT : PASS
4767 01:36:27.309145 RX DQ/DQS(Engine): PASS
4768 01:36:27.309227 TX OE : NO K
4769 01:36:27.312177 All Pass.
4770 01:36:27.312260
4771 01:36:27.312326 CH 0, Rank 1
4772 01:36:27.315631 SW Impedance : PASS
4773 01:36:27.315714 DUTY Scan : NO K
4774 01:36:27.318602 ZQ Calibration : PASS
4775 01:36:27.321848 Jitter Meter : NO K
4776 01:36:27.321931 CBT Training : PASS
4777 01:36:27.325440 Write leveling : PASS
4778 01:36:27.328552 RX DQS gating : PASS
4779 01:36:27.328643 RX DQ/DQS(RDDQC) : PASS
4780 01:36:27.331408 TX DQ/DQS : PASS
4781 01:36:27.334929 RX DATLAT : PASS
4782 01:36:27.335012 RX DQ/DQS(Engine): PASS
4783 01:36:27.338365 TX OE : NO K
4784 01:36:27.338448 All Pass.
4785 01:36:27.338512
4786 01:36:27.341479 CH 1, Rank 0
4787 01:36:27.341562 SW Impedance : PASS
4788 01:36:27.345230 DUTY Scan : NO K
4789 01:36:27.347963 ZQ Calibration : PASS
4790 01:36:27.348045 Jitter Meter : NO K
4791 01:36:27.351107 CBT Training : PASS
4792 01:36:27.354920 Write leveling : PASS
4793 01:36:27.355003 RX DQS gating : PASS
4794 01:36:27.357962 RX DQ/DQS(RDDQC) : PASS
4795 01:36:27.358045 TX DQ/DQS : PASS
4796 01:36:27.361092 RX DATLAT : PASS
4797 01:36:27.364709 RX DQ/DQS(Engine): PASS
4798 01:36:27.364798 TX OE : NO K
4799 01:36:27.367805 All Pass.
4800 01:36:27.367886
4801 01:36:27.367951 CH 1, Rank 1
4802 01:36:27.371084 SW Impedance : PASS
4803 01:36:27.371167 DUTY Scan : NO K
4804 01:36:27.374255 ZQ Calibration : PASS
4805 01:36:27.377844 Jitter Meter : NO K
4806 01:36:27.377927 CBT Training : PASS
4807 01:36:27.380889 Write leveling : PASS
4808 01:36:27.384065 RX DQS gating : PASS
4809 01:36:27.384149 RX DQ/DQS(RDDQC) : PASS
4810 01:36:27.387424 TX DQ/DQS : PASS
4811 01:36:27.390851 RX DATLAT : PASS
4812 01:36:27.390934 RX DQ/DQS(Engine): PASS
4813 01:36:27.394132 TX OE : NO K
4814 01:36:27.394215 All Pass.
4815 01:36:27.394280
4816 01:36:27.397267 DramC Write-DBI off
4817 01:36:27.400504 PER_BANK_REFRESH: Hybrid Mode
4818 01:36:27.400587 TX_TRACKING: ON
4819 01:36:27.410967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4820 01:36:27.413737 [FAST_K] Save calibration result to emmc
4821 01:36:27.417201 dramc_set_vcore_voltage set vcore to 662500
4822 01:36:27.420812 Read voltage for 933, 3
4823 01:36:27.420895 Vio18 = 0
4824 01:36:27.420961 Vcore = 662500
4825 01:36:27.423889 Vdram = 0
4826 01:36:27.423972 Vddq = 0
4827 01:36:27.424037 Vmddr = 0
4828 01:36:27.430379 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4829 01:36:27.433473 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4830 01:36:27.437025 MEM_TYPE=3, freq_sel=17
4831 01:36:27.440153 sv_algorithm_assistance_LP4_1600
4832 01:36:27.443553 ============ PULL DRAM RESETB DOWN ============
4833 01:36:27.450341 ========== PULL DRAM RESETB DOWN end =========
4834 01:36:27.453375 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4835 01:36:27.456462 ===================================
4836 01:36:27.459676 LPDDR4 DRAM CONFIGURATION
4837 01:36:27.463609 ===================================
4838 01:36:27.463692 EX_ROW_EN[0] = 0x0
4839 01:36:27.466655 EX_ROW_EN[1] = 0x0
4840 01:36:27.466738 LP4Y_EN = 0x0
4841 01:36:27.469797 WORK_FSP = 0x0
4842 01:36:27.469881 WL = 0x3
4843 01:36:27.473094 RL = 0x3
4844 01:36:27.476316 BL = 0x2
4845 01:36:27.476399 RPST = 0x0
4846 01:36:27.479655 RD_PRE = 0x0
4847 01:36:27.479737 WR_PRE = 0x1
4848 01:36:27.483388 WR_PST = 0x0
4849 01:36:27.483471 DBI_WR = 0x0
4850 01:36:27.486082 DBI_RD = 0x0
4851 01:36:27.486165 OTF = 0x1
4852 01:36:27.489673 ===================================
4853 01:36:27.492807 ===================================
4854 01:36:27.496311 ANA top config
4855 01:36:27.499307 ===================================
4856 01:36:27.499390 DLL_ASYNC_EN = 0
4857 01:36:27.502702 ALL_SLAVE_EN = 1
4858 01:36:27.506170 NEW_RANK_MODE = 1
4859 01:36:27.509524 DLL_IDLE_MODE = 1
4860 01:36:27.509606 LP45_APHY_COMB_EN = 1
4861 01:36:27.512710 TX_ODT_DIS = 1
4862 01:36:27.515956 NEW_8X_MODE = 1
4863 01:36:27.519258 ===================================
4864 01:36:27.522957 ===================================
4865 01:36:27.525851 data_rate = 1866
4866 01:36:27.529164 CKR = 1
4867 01:36:27.532169 DQ_P2S_RATIO = 8
4868 01:36:27.535911 ===================================
4869 01:36:27.535994 CA_P2S_RATIO = 8
4870 01:36:27.539224 DQ_CA_OPEN = 0
4871 01:36:27.542479 DQ_SEMI_OPEN = 0
4872 01:36:27.545543 CA_SEMI_OPEN = 0
4873 01:36:27.548761 CA_FULL_RATE = 0
4874 01:36:27.552377 DQ_CKDIV4_EN = 1
4875 01:36:27.555768 CA_CKDIV4_EN = 1
4876 01:36:27.555851 CA_PREDIV_EN = 0
4877 01:36:27.558805 PH8_DLY = 0
4878 01:36:27.561786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4879 01:36:27.565566 DQ_AAMCK_DIV = 4
4880 01:36:27.568695 CA_AAMCK_DIV = 4
4881 01:36:27.571736 CA_ADMCK_DIV = 4
4882 01:36:27.571824 DQ_TRACK_CA_EN = 0
4883 01:36:27.575119 CA_PICK = 933
4884 01:36:27.578652 CA_MCKIO = 933
4885 01:36:27.582134 MCKIO_SEMI = 0
4886 01:36:27.585219 PLL_FREQ = 3732
4887 01:36:27.588483 DQ_UI_PI_RATIO = 32
4888 01:36:27.591483 CA_UI_PI_RATIO = 0
4889 01:36:27.594970 ===================================
4890 01:36:27.598462 ===================================
4891 01:36:27.598545 memory_type:LPDDR4
4892 01:36:27.601534 GP_NUM : 10
4893 01:36:27.604573 SRAM_EN : 1
4894 01:36:27.604655 MD32_EN : 0
4895 01:36:27.608039 ===================================
4896 01:36:27.611578 [ANA_INIT] >>>>>>>>>>>>>>
4897 01:36:27.614623 <<<<<< [CONFIGURE PHASE]: ANA_TX
4898 01:36:27.617943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4899 01:36:27.621362 ===================================
4900 01:36:27.624749 data_rate = 1866,PCW = 0X8f00
4901 01:36:27.627968 ===================================
4902 01:36:27.631261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4903 01:36:27.634517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4904 01:36:27.641010 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4905 01:36:27.644232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4906 01:36:27.650846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4907 01:36:27.654105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4908 01:36:27.654189 [ANA_INIT] flow start
4909 01:36:27.657602 [ANA_INIT] PLL >>>>>>>>
4910 01:36:27.660711 [ANA_INIT] PLL <<<<<<<<
4911 01:36:27.660794 [ANA_INIT] MIDPI >>>>>>>>
4912 01:36:27.664134 [ANA_INIT] MIDPI <<<<<<<<
4913 01:36:27.667347 [ANA_INIT] DLL >>>>>>>>
4914 01:36:27.667430 [ANA_INIT] flow end
4915 01:36:27.673959 ============ LP4 DIFF to SE enter ============
4916 01:36:27.676803 ============ LP4 DIFF to SE exit ============
4917 01:36:27.680072 [ANA_INIT] <<<<<<<<<<<<<
4918 01:36:27.684225 [Flow] Enable top DCM control >>>>>
4919 01:36:27.686815 [Flow] Enable top DCM control <<<<<
4920 01:36:27.686900 Enable DLL master slave shuffle
4921 01:36:27.693142 ==============================================================
4922 01:36:27.696684 Gating Mode config
4923 01:36:27.699879 ==============================================================
4924 01:36:27.703510 Config description:
4925 01:36:27.712953 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4926 01:36:27.719504 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4927 01:36:27.723004 SELPH_MODE 0: By rank 1: By Phase
4928 01:36:27.729569 ==============================================================
4929 01:36:27.733317 GAT_TRACK_EN = 1
4930 01:36:27.736078 RX_GATING_MODE = 2
4931 01:36:27.739494 RX_GATING_TRACK_MODE = 2
4932 01:36:27.743365 SELPH_MODE = 1
4933 01:36:27.746234 PICG_EARLY_EN = 1
4934 01:36:27.746316 VALID_LAT_VALUE = 1
4935 01:36:27.752961 ==============================================================
4936 01:36:27.756281 Enter into Gating configuration >>>>
4937 01:36:27.759846 Exit from Gating configuration <<<<
4938 01:36:27.762322 Enter into DVFS_PRE_config >>>>>
4939 01:36:27.775367 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4940 01:36:27.775469 Exit from DVFS_PRE_config <<<<<
4941 01:36:27.778786 Enter into PICG configuration >>>>
4942 01:36:27.782175 Exit from PICG configuration <<<<
4943 01:36:27.785685 [RX_INPUT] configuration >>>>>
4944 01:36:27.788659 [RX_INPUT] configuration <<<<<
4945 01:36:27.795491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4946 01:36:27.798766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4947 01:36:27.805177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4948 01:36:27.811556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4949 01:36:27.818173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4950 01:36:27.824867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4951 01:36:27.828357 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4952 01:36:27.831780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4953 01:36:27.834956 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4954 01:36:27.841383 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4955 01:36:27.844559 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4956 01:36:27.848212 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4957 01:36:27.851360 ===================================
4958 01:36:27.854581 LPDDR4 DRAM CONFIGURATION
4959 01:36:27.857752 ===================================
4960 01:36:27.860794 EX_ROW_EN[0] = 0x0
4961 01:36:27.860877 EX_ROW_EN[1] = 0x0
4962 01:36:27.864302 LP4Y_EN = 0x0
4963 01:36:27.864412 WORK_FSP = 0x0
4964 01:36:27.867747 WL = 0x3
4965 01:36:27.867830 RL = 0x3
4966 01:36:27.871010 BL = 0x2
4967 01:36:27.871093 RPST = 0x0
4968 01:36:27.873957 RD_PRE = 0x0
4969 01:36:27.877462 WR_PRE = 0x1
4970 01:36:27.877545 WR_PST = 0x0
4971 01:36:27.880854 DBI_WR = 0x0
4972 01:36:27.880936 DBI_RD = 0x0
4973 01:36:27.883948 OTF = 0x1
4974 01:36:27.887634 ===================================
4975 01:36:27.890554 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4976 01:36:27.893830 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4977 01:36:27.896980 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 01:36:27.900380 ===================================
4979 01:36:27.903737 LPDDR4 DRAM CONFIGURATION
4980 01:36:27.907172 ===================================
4981 01:36:27.910432 EX_ROW_EN[0] = 0x10
4982 01:36:27.910515 EX_ROW_EN[1] = 0x0
4983 01:36:27.913377 LP4Y_EN = 0x0
4984 01:36:27.913460 WORK_FSP = 0x0
4985 01:36:27.916644 WL = 0x3
4986 01:36:27.920143 RL = 0x3
4987 01:36:27.920227 BL = 0x2
4988 01:36:27.923440 RPST = 0x0
4989 01:36:27.923524 RD_PRE = 0x0
4990 01:36:27.926814 WR_PRE = 0x1
4991 01:36:27.926897 WR_PST = 0x0
4992 01:36:27.929989 DBI_WR = 0x0
4993 01:36:27.930073 DBI_RD = 0x0
4994 01:36:27.933438 OTF = 0x1
4995 01:36:27.936799 ===================================
4996 01:36:27.943012 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4997 01:36:27.946158 nWR fixed to 30
4998 01:36:27.946247 [ModeRegInit_LP4] CH0 RK0
4999 01:36:27.949443 [ModeRegInit_LP4] CH0 RK1
5000 01:36:27.953153 [ModeRegInit_LP4] CH1 RK0
5001 01:36:27.956246 [ModeRegInit_LP4] CH1 RK1
5002 01:36:27.956328 match AC timing 9
5003 01:36:27.959418 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5004 01:36:27.965831 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5005 01:36:27.969182 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5006 01:36:27.975809 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5007 01:36:27.979056 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5008 01:36:27.979139 ==
5009 01:36:27.982331 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 01:36:27.985735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5011 01:36:27.985820 ==
5012 01:36:27.992455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5013 01:36:27.998941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5014 01:36:28.002068 [CA 0] Center 37 (7~68) winsize 62
5015 01:36:28.006017 [CA 1] Center 37 (7~68) winsize 62
5016 01:36:28.009141 [CA 2] Center 34 (4~65) winsize 62
5017 01:36:28.012657 [CA 3] Center 34 (4~65) winsize 62
5018 01:36:28.015132 [CA 4] Center 32 (2~63) winsize 62
5019 01:36:28.018471 [CA 5] Center 32 (2~63) winsize 62
5020 01:36:28.018553
5021 01:36:28.022406 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5022 01:36:28.022504
5023 01:36:28.025413 [CATrainingPosCal] consider 1 rank data
5024 01:36:28.028562 u2DelayCellTimex100 = 270/100 ps
5025 01:36:28.031866 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5026 01:36:28.035356 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5027 01:36:28.038713 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5028 01:36:28.041469 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5029 01:36:28.048186 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5030 01:36:28.051704 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5031 01:36:28.051788
5032 01:36:28.055063 CA PerBit enable=1, Macro0, CA PI delay=32
5033 01:36:28.055146
5034 01:36:28.058080 [CBTSetCACLKResult] CA Dly = 32
5035 01:36:28.058163 CS Dly: 5 (0~36)
5036 01:36:28.058229 ==
5037 01:36:28.061384 Dram Type= 6, Freq= 0, CH_0, rank 1
5038 01:36:28.068180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 01:36:28.068263 ==
5040 01:36:28.071267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 01:36:28.078131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5042 01:36:28.081061 [CA 0] Center 37 (7~68) winsize 62
5043 01:36:28.084540 [CA 1] Center 37 (7~68) winsize 62
5044 01:36:28.087904 [CA 2] Center 34 (4~65) winsize 62
5045 01:36:28.091388 [CA 3] Center 34 (4~65) winsize 62
5046 01:36:28.094595 [CA 4] Center 33 (3~64) winsize 62
5047 01:36:28.097603 [CA 5] Center 32 (2~63) winsize 62
5048 01:36:28.097686
5049 01:36:28.101252 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5050 01:36:28.101357
5051 01:36:28.104300 [CATrainingPosCal] consider 2 rank data
5052 01:36:28.107597 u2DelayCellTimex100 = 270/100 ps
5053 01:36:28.111091 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5054 01:36:28.114304 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5055 01:36:28.120696 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5056 01:36:28.124538 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5057 01:36:28.128671 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5058 01:36:28.130337 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5059 01:36:28.130413
5060 01:36:28.133758 CA PerBit enable=1, Macro0, CA PI delay=32
5061 01:36:28.133836
5062 01:36:28.137849 [CBTSetCACLKResult] CA Dly = 32
5063 01:36:28.137929 CS Dly: 6 (0~38)
5064 01:36:28.140549
5065 01:36:28.143875 ----->DramcWriteLeveling(PI) begin...
5066 01:36:28.143961 ==
5067 01:36:28.146936 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 01:36:28.150591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 01:36:28.150674 ==
5070 01:36:28.153806 Write leveling (Byte 0): 32 => 32
5071 01:36:28.156921 Write leveling (Byte 1): 30 => 30
5072 01:36:28.160560 DramcWriteLeveling(PI) end<-----
5073 01:36:28.160643
5074 01:36:28.160708 ==
5075 01:36:28.163772 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 01:36:28.166910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 01:36:28.166994 ==
5078 01:36:28.170189 [Gating] SW mode calibration
5079 01:36:28.176838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5080 01:36:28.183671 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5081 01:36:28.186908 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5082 01:36:28.190252 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5083 01:36:28.196434 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5084 01:36:28.199572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5085 01:36:28.203095 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 01:36:28.209387 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 01:36:28.212867 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5088 01:36:28.216279 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5089 01:36:28.222709 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5090 01:36:28.226131 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5091 01:36:28.229242 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5092 01:36:28.235785 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 01:36:28.239055 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 01:36:28.242587 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 01:36:28.249516 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 01:36:28.252352 0 15 28 | B1->B0 | 2424 3939 | 0 0 | (1 1) (0 0)
5097 01:36:28.255362 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5098 01:36:28.262069 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5099 01:36:28.265353 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5100 01:36:28.271853 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 01:36:28.275075 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 01:36:28.278688 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 01:36:28.285457 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5104 01:36:28.288123 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5105 01:36:28.291773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5106 01:36:28.298033 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5107 01:36:28.301428 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 01:36:28.304850 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 01:36:28.311249 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 01:36:28.314838 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 01:36:28.317977 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 01:36:28.324997 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 01:36:28.327761 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 01:36:28.331312 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 01:36:28.334371 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 01:36:28.340929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 01:36:28.344297 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 01:36:28.351516 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 01:36:28.354510 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 01:36:28.358034 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5121 01:36:28.364139 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5122 01:36:28.364244 Total UI for P1: 0, mck2ui 16
5123 01:36:28.370836 best dqsien dly found for B0: ( 1, 2, 28)
5124 01:36:28.374197 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 01:36:28.377086 Total UI for P1: 0, mck2ui 16
5126 01:36:28.381107 best dqsien dly found for B1: ( 1, 3, 0)
5127 01:36:28.383754 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5128 01:36:28.387584 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5129 01:36:28.387684
5130 01:36:28.390270 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5131 01:36:28.393960 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5132 01:36:28.398123 [Gating] SW calibration Done
5133 01:36:28.398223 ==
5134 01:36:28.400118 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 01:36:28.403883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 01:36:28.403960 ==
5137 01:36:28.406817 RX Vref Scan: 0
5138 01:36:28.406889
5139 01:36:28.410387 RX Vref 0 -> 0, step: 1
5140 01:36:28.410487
5141 01:36:28.410577 RX Delay -80 -> 252, step: 8
5142 01:36:28.416726 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5143 01:36:28.420323 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5144 01:36:28.423367 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5145 01:36:28.427094 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5146 01:36:28.429928 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5147 01:36:28.433051 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5148 01:36:28.439559 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5149 01:36:28.443207 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5150 01:36:28.446472 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5151 01:36:28.449686 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5152 01:36:28.456371 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5153 01:36:28.459271 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5154 01:36:28.462596 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5155 01:36:28.465791 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5156 01:36:28.469503 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5157 01:36:28.472617 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5158 01:36:28.476148 ==
5159 01:36:28.479836 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 01:36:28.482364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 01:36:28.482443 ==
5162 01:36:28.482506 DQS Delay:
5163 01:36:28.486158 DQS0 = 0, DQS1 = 0
5164 01:36:28.486230 DQM Delay:
5165 01:36:28.489510 DQM0 = 100, DQM1 = 89
5166 01:36:28.489605 DQ Delay:
5167 01:36:28.492220 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5168 01:36:28.495526 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =111
5169 01:36:28.499193 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5170 01:36:28.502243 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5171 01:36:28.502318
5172 01:36:28.502379
5173 01:36:28.502443 ==
5174 01:36:28.505324 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 01:36:28.509015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 01:36:28.509112 ==
5177 01:36:28.511905
5178 01:36:28.511977
5179 01:36:28.512036 TX Vref Scan disable
5180 01:36:28.515606 == TX Byte 0 ==
5181 01:36:28.518515 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5182 01:36:28.521931 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5183 01:36:28.525217 == TX Byte 1 ==
5184 01:36:28.528336 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5185 01:36:28.531930 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5186 01:36:28.535202 ==
5187 01:36:28.535276 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 01:36:28.541661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 01:36:28.541761 ==
5190 01:36:28.541851
5191 01:36:28.541940
5192 01:36:28.545443 TX Vref Scan disable
5193 01:36:28.545539 == TX Byte 0 ==
5194 01:36:28.551507 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5195 01:36:28.554921 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5196 01:36:28.554995 == TX Byte 1 ==
5197 01:36:28.561507 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5198 01:36:28.565088 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5199 01:36:28.565172
5200 01:36:28.565237 [DATLAT]
5201 01:36:28.567948 Freq=933, CH0 RK0
5202 01:36:28.568031
5203 01:36:28.568096 DATLAT Default: 0xd
5204 01:36:28.571153 0, 0xFFFF, sum = 0
5205 01:36:28.571237 1, 0xFFFF, sum = 0
5206 01:36:28.574494 2, 0xFFFF, sum = 0
5207 01:36:28.574578 3, 0xFFFF, sum = 0
5208 01:36:28.578108 4, 0xFFFF, sum = 0
5209 01:36:28.578192 5, 0xFFFF, sum = 0
5210 01:36:28.581406 6, 0xFFFF, sum = 0
5211 01:36:28.584874 7, 0xFFFF, sum = 0
5212 01:36:28.584958 8, 0xFFFF, sum = 0
5213 01:36:28.587760 9, 0xFFFF, sum = 0
5214 01:36:28.587843 10, 0x0, sum = 1
5215 01:36:28.587909 11, 0x0, sum = 2
5216 01:36:28.591398 12, 0x0, sum = 3
5217 01:36:28.591482 13, 0x0, sum = 4
5218 01:36:28.594380 best_step = 11
5219 01:36:28.594463
5220 01:36:28.594527 ==
5221 01:36:28.598086 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 01:36:28.601365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 01:36:28.601448 ==
5224 01:36:28.604764 RX Vref Scan: 1
5225 01:36:28.604847
5226 01:36:28.604911 RX Vref 0 -> 0, step: 1
5227 01:36:28.607750
5228 01:36:28.607831 RX Delay -61 -> 252, step: 4
5229 01:36:28.607897
5230 01:36:28.610690 Set Vref, RX VrefLevel [Byte0]: 53
5231 01:36:28.614273 [Byte1]: 50
5232 01:36:28.618600
5233 01:36:28.618681 Final RX Vref Byte 0 = 53 to rank0
5234 01:36:28.621903 Final RX Vref Byte 1 = 50 to rank0
5235 01:36:28.625167 Final RX Vref Byte 0 = 53 to rank1
5236 01:36:28.628885 Final RX Vref Byte 1 = 50 to rank1==
5237 01:36:28.631932 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 01:36:28.638466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 01:36:28.638549 ==
5240 01:36:28.638614 DQS Delay:
5241 01:36:28.641843 DQS0 = 0, DQS1 = 0
5242 01:36:28.641925 DQM Delay:
5243 01:36:28.641990 DQM0 = 99, DQM1 = 87
5244 01:36:28.645246 DQ Delay:
5245 01:36:28.648220 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5246 01:36:28.651739 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5247 01:36:28.655201 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5248 01:36:28.658545 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =96
5249 01:36:28.658628
5250 01:36:28.658694
5251 01:36:28.664985 [DQSOSCAuto] RK0, (LSB)MR18= 0x1913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5252 01:36:28.667841 CH0 RK0: MR19=505, MR18=1913
5253 01:36:28.674821 CH0_RK0: MR19=0x505, MR18=0x1913, DQSOSC=413, MR23=63, INC=63, DEC=42
5254 01:36:28.674904
5255 01:36:28.678263 ----->DramcWriteLeveling(PI) begin...
5256 01:36:28.678347 ==
5257 01:36:28.681096 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 01:36:28.684332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 01:36:28.687523 ==
5260 01:36:28.687605 Write leveling (Byte 0): 33 => 33
5261 01:36:28.691269 Write leveling (Byte 1): 28 => 28
5262 01:36:28.694030 DramcWriteLeveling(PI) end<-----
5263 01:36:28.694112
5264 01:36:28.694177 ==
5265 01:36:28.697500 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 01:36:28.704062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 01:36:28.704146 ==
5268 01:36:28.707347 [Gating] SW mode calibration
5269 01:36:28.713867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5270 01:36:28.717393 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5271 01:36:28.723781 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5272 01:36:28.727170 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5273 01:36:28.730381 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5274 01:36:28.736927 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 01:36:28.740249 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 01:36:28.743726 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 01:36:28.750556 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 01:36:28.753234 0 14 28 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 1)
5279 01:36:28.756919 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5280 01:36:28.763503 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5281 01:36:28.767106 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5282 01:36:28.769838 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 01:36:28.776234 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 01:36:28.779631 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 01:36:28.783390 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5286 01:36:28.789849 0 15 28 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)
5287 01:36:28.792649 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5288 01:36:28.796168 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5289 01:36:28.802879 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5290 01:36:28.805784 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 01:36:28.809218 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 01:36:28.816198 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 01:36:28.819051 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 01:36:28.822714 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5295 01:36:28.829209 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5296 01:36:28.832375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5297 01:36:28.835356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 01:36:28.842241 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 01:36:28.845156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 01:36:28.848475 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 01:36:28.855053 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 01:36:28.858564 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 01:36:28.862239 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 01:36:28.868144 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 01:36:28.872042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 01:36:28.874760 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 01:36:28.881638 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 01:36:28.884635 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 01:36:28.888157 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5310 01:36:28.894677 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5311 01:36:28.898073 Total UI for P1: 0, mck2ui 16
5312 01:36:28.900966 best dqsien dly found for B0: ( 1, 2, 24)
5313 01:36:28.904866 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5314 01:36:28.907597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 01:36:28.911000 Total UI for P1: 0, mck2ui 16
5316 01:36:28.914616 best dqsien dly found for B1: ( 1, 3, 0)
5317 01:36:28.918112 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5318 01:36:28.924384 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5319 01:36:28.924467
5320 01:36:28.927831 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5321 01:36:28.930718 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5322 01:36:28.933724 [Gating] SW calibration Done
5323 01:36:28.933806 ==
5324 01:36:28.937241 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 01:36:28.940773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 01:36:28.940856 ==
5327 01:36:28.944028 RX Vref Scan: 0
5328 01:36:28.944110
5329 01:36:28.944174 RX Vref 0 -> 0, step: 1
5330 01:36:28.944236
5331 01:36:28.947117 RX Delay -80 -> 252, step: 8
5332 01:36:28.950172 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5333 01:36:28.953826 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5334 01:36:28.960656 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5335 01:36:28.963478 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5336 01:36:28.967099 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5337 01:36:28.970328 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5338 01:36:28.973222 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5339 01:36:28.976743 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5340 01:36:28.983153 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5341 01:36:28.986711 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5342 01:36:28.989829 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5343 01:36:28.993428 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5344 01:36:28.996874 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5345 01:36:29.003028 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5346 01:36:29.006589 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5347 01:36:29.009817 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5348 01:36:29.009900 ==
5349 01:36:29.012766 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 01:36:29.016449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 01:36:29.016532 ==
5352 01:36:29.019208 DQS Delay:
5353 01:36:29.019333 DQS0 = 0, DQS1 = 0
5354 01:36:29.022947 DQM Delay:
5355 01:36:29.023028 DQM0 = 97, DQM1 = 89
5356 01:36:29.023092 DQ Delay:
5357 01:36:29.026325 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5358 01:36:29.029733 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5359 01:36:29.033248 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5360 01:36:29.035965 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5361 01:36:29.036047
5362 01:36:29.036111
5363 01:36:29.039629 ==
5364 01:36:29.042528 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 01:36:29.045977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 01:36:29.046060 ==
5367 01:36:29.046124
5368 01:36:29.046183
5369 01:36:29.049222 TX Vref Scan disable
5370 01:36:29.049328 == TX Byte 0 ==
5371 01:36:29.055853 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5372 01:36:29.059136 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5373 01:36:29.059219 == TX Byte 1 ==
5374 01:36:29.065483 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5375 01:36:29.068937 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5376 01:36:29.069019 ==
5377 01:36:29.072132 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 01:36:29.075186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 01:36:29.075269 ==
5380 01:36:29.075333
5381 01:36:29.075392
5382 01:36:29.078365 TX Vref Scan disable
5383 01:36:29.081836 == TX Byte 0 ==
5384 01:36:29.085600 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5385 01:36:29.088519 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5386 01:36:29.091816 == TX Byte 1 ==
5387 01:36:29.094958 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5388 01:36:29.098308 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5389 01:36:29.098391
5390 01:36:29.101635 [DATLAT]
5391 01:36:29.101718 Freq=933, CH0 RK1
5392 01:36:29.101783
5393 01:36:29.104808 DATLAT Default: 0xb
5394 01:36:29.104890 0, 0xFFFF, sum = 0
5395 01:36:29.108043 1, 0xFFFF, sum = 0
5396 01:36:29.108127 2, 0xFFFF, sum = 0
5397 01:36:29.111379 3, 0xFFFF, sum = 0
5398 01:36:29.111463 4, 0xFFFF, sum = 0
5399 01:36:29.114746 5, 0xFFFF, sum = 0
5400 01:36:29.118002 6, 0xFFFF, sum = 0
5401 01:36:29.118100 7, 0xFFFF, sum = 0
5402 01:36:29.121005 8, 0xFFFF, sum = 0
5403 01:36:29.121109 9, 0xFFFF, sum = 0
5404 01:36:29.124599 10, 0x0, sum = 1
5405 01:36:29.124677 11, 0x0, sum = 2
5406 01:36:29.127777 12, 0x0, sum = 3
5407 01:36:29.127875 13, 0x0, sum = 4
5408 01:36:29.127969 best_step = 11
5409 01:36:29.128055
5410 01:36:29.131557 ==
5411 01:36:29.134374 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 01:36:29.137718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 01:36:29.137794 ==
5414 01:36:29.137857 RX Vref Scan: 0
5415 01:36:29.137919
5416 01:36:29.141415 RX Vref 0 -> 0, step: 1
5417 01:36:29.141513
5418 01:36:29.144206 RX Delay -53 -> 252, step: 4
5419 01:36:29.150627 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5420 01:36:29.153876 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5421 01:36:29.157452 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5422 01:36:29.160584 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5423 01:36:29.164126 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5424 01:36:29.167540 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5425 01:36:29.173849 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5426 01:36:29.176973 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5427 01:36:29.180673 iDelay=195, Bit 8, Center 78 (-9 ~ 166) 176
5428 01:36:29.183655 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5429 01:36:29.186904 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5430 01:36:29.193550 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5431 01:36:29.197084 iDelay=195, Bit 12, Center 90 (-1 ~ 182) 184
5432 01:36:29.200488 iDelay=195, Bit 13, Center 90 (3 ~ 178) 176
5433 01:36:29.203567 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5434 01:36:29.206760 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5435 01:36:29.206862 ==
5436 01:36:29.209998 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 01:36:29.216667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 01:36:29.216775 ==
5439 01:36:29.216880 DQS Delay:
5440 01:36:29.219961 DQS0 = 0, DQS1 = 0
5441 01:36:29.220101 DQM Delay:
5442 01:36:29.220203 DQM0 = 96, DQM1 = 87
5443 01:36:29.223048 DQ Delay:
5444 01:36:29.227151 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =94
5445 01:36:29.229880 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5446 01:36:29.233383 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5447 01:36:29.236343 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =94
5448 01:36:29.236442
5449 01:36:29.236539
5450 01:36:29.242923 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5451 01:36:29.246323 CH0 RK1: MR19=505, MR18=1310
5452 01:36:29.252854 CH0_RK1: MR19=0x505, MR18=0x1310, DQSOSC=415, MR23=63, INC=62, DEC=41
5453 01:36:29.255735 [RxdqsGatingPostProcess] freq 933
5454 01:36:29.262490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5455 01:36:29.265744 best DQS0 dly(2T, 0.5T) = (0, 10)
5456 01:36:29.265821 best DQS1 dly(2T, 0.5T) = (0, 11)
5457 01:36:29.269236 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5458 01:36:29.272432 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5459 01:36:29.275708 best DQS0 dly(2T, 0.5T) = (0, 10)
5460 01:36:29.279107 best DQS1 dly(2T, 0.5T) = (0, 11)
5461 01:36:29.282391 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5462 01:36:29.285439 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5463 01:36:29.288723 Pre-setting of DQS Precalculation
5464 01:36:29.295560 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5465 01:36:29.295664 ==
5466 01:36:29.298558 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 01:36:29.301740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 01:36:29.301813 ==
5469 01:36:29.308721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5470 01:36:29.315504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5471 01:36:29.318730 [CA 0] Center 36 (6~67) winsize 62
5472 01:36:29.321930 [CA 1] Center 36 (6~67) winsize 62
5473 01:36:29.325412 [CA 2] Center 34 (4~65) winsize 62
5474 01:36:29.328338 [CA 3] Center 34 (3~65) winsize 63
5475 01:36:29.331523 [CA 4] Center 34 (3~65) winsize 63
5476 01:36:29.335034 [CA 5] Center 33 (3~64) winsize 62
5477 01:36:29.335110
5478 01:36:29.338228 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5479 01:36:29.338302
5480 01:36:29.341375 [CATrainingPosCal] consider 1 rank data
5481 01:36:29.344986 u2DelayCellTimex100 = 270/100 ps
5482 01:36:29.348188 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5483 01:36:29.351412 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5484 01:36:29.354900 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5485 01:36:29.357939 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5486 01:36:29.361212 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5487 01:36:29.364386 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5488 01:36:29.364468
5489 01:36:29.371027 CA PerBit enable=1, Macro0, CA PI delay=33
5490 01:36:29.371111
5491 01:36:29.374573 [CBTSetCACLKResult] CA Dly = 33
5492 01:36:29.374656 CS Dly: 5 (0~36)
5493 01:36:29.374721 ==
5494 01:36:29.377434 Dram Type= 6, Freq= 0, CH_1, rank 1
5495 01:36:29.380747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 01:36:29.380856 ==
5497 01:36:29.387598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 01:36:29.394340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5499 01:36:29.397761 [CA 0] Center 36 (5~67) winsize 63
5500 01:36:29.400928 [CA 1] Center 36 (6~67) winsize 62
5501 01:36:29.404309 [CA 2] Center 34 (4~65) winsize 62
5502 01:36:29.407008 [CA 3] Center 33 (3~64) winsize 62
5503 01:36:29.410456 [CA 4] Center 33 (3~64) winsize 62
5504 01:36:29.413627 [CA 5] Center 33 (3~64) winsize 62
5505 01:36:29.413710
5506 01:36:29.417128 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5507 01:36:29.417236
5508 01:36:29.420385 [CATrainingPosCal] consider 2 rank data
5509 01:36:29.423684 u2DelayCellTimex100 = 270/100 ps
5510 01:36:29.427277 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 01:36:29.430057 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5512 01:36:29.433216 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5513 01:36:29.440346 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5514 01:36:29.443436 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5515 01:36:29.446557 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 01:36:29.446641
5517 01:36:29.449815 CA PerBit enable=1, Macro0, CA PI delay=33
5518 01:36:29.449897
5519 01:36:29.452960 [CBTSetCACLKResult] CA Dly = 33
5520 01:36:29.453068 CS Dly: 6 (0~38)
5521 01:36:29.453160
5522 01:36:29.456543 ----->DramcWriteLeveling(PI) begin...
5523 01:36:29.459851 ==
5524 01:36:29.462869 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 01:36:29.466337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 01:36:29.466420 ==
5527 01:36:29.469546 Write leveling (Byte 0): 30 => 30
5528 01:36:29.472978 Write leveling (Byte 1): 32 => 32
5529 01:36:29.476272 DramcWriteLeveling(PI) end<-----
5530 01:36:29.476355
5531 01:36:29.476419 ==
5532 01:36:29.479441 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 01:36:29.482851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 01:36:29.482934 ==
5535 01:36:29.486224 [Gating] SW mode calibration
5536 01:36:29.492739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 01:36:29.498999 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5538 01:36:29.502388 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 01:36:29.505790 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 01:36:29.512402 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 01:36:29.516240 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 01:36:29.518939 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 01:36:29.525468 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 01:36:29.528908 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5545 01:36:29.532342 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (1 0)
5546 01:36:29.538832 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 01:36:29.541932 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 01:36:29.545568 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 01:36:29.552179 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 01:36:29.555087 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 01:36:29.558517 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 01:36:29.565238 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5553 01:36:29.568158 0 15 28 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
5554 01:36:29.571549 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 01:36:29.578069 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 01:36:29.581337 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 01:36:29.585330 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 01:36:29.591783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 01:36:29.594604 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 01:36:29.597698 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 01:36:29.604696 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5562 01:36:29.607787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5563 01:36:29.610943 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 01:36:29.617891 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 01:36:29.620968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 01:36:29.624150 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 01:36:29.630763 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 01:36:29.634477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 01:36:29.637188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 01:36:29.644183 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 01:36:29.647060 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 01:36:29.650369 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 01:36:29.657068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 01:36:29.660385 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 01:36:29.663511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 01:36:29.670162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 01:36:29.673230 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 01:36:29.676812 Total UI for P1: 0, mck2ui 16
5579 01:36:29.679893 best dqsien dly found for B0: ( 1, 2, 26)
5580 01:36:29.683362 Total UI for P1: 0, mck2ui 16
5581 01:36:29.686895 best dqsien dly found for B1: ( 1, 2, 26)
5582 01:36:29.690226 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5583 01:36:29.693053 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5584 01:36:29.693152
5585 01:36:29.696612 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5586 01:36:29.703013 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5587 01:36:29.703116 [Gating] SW calibration Done
5588 01:36:29.703211 ==
5589 01:36:29.706079 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 01:36:29.712728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 01:36:29.712831 ==
5592 01:36:29.712929 RX Vref Scan: 0
5593 01:36:29.713019
5594 01:36:29.716154 RX Vref 0 -> 0, step: 1
5595 01:36:29.716259
5596 01:36:29.719492 RX Delay -80 -> 252, step: 8
5597 01:36:29.723043 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5598 01:36:29.726078 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5599 01:36:29.729549 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5600 01:36:29.732645 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5601 01:36:29.739259 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5602 01:36:29.742566 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5603 01:36:29.746073 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5604 01:36:29.749170 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5605 01:36:29.752593 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5606 01:36:29.758810 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5607 01:36:29.762424 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5608 01:36:29.765722 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5609 01:36:29.768816 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5610 01:36:29.772697 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5611 01:36:29.778611 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5612 01:36:29.782030 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5613 01:36:29.782107 ==
5614 01:36:29.785192 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 01:36:29.789073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 01:36:29.789172 ==
5617 01:36:29.789267 DQS Delay:
5618 01:36:29.791890 DQS0 = 0, DQS1 = 0
5619 01:36:29.791962 DQM Delay:
5620 01:36:29.795083 DQM0 = 99, DQM1 = 95
5621 01:36:29.795154 DQ Delay:
5622 01:36:29.798578 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5623 01:36:29.801674 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5624 01:36:29.805089 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5625 01:36:29.808575 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5626 01:36:29.808682
5627 01:36:29.808773
5628 01:36:29.811866 ==
5629 01:36:29.811960 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 01:36:29.817913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 01:36:29.817992 ==
5632 01:36:29.818056
5633 01:36:29.818115
5634 01:36:29.821601 TX Vref Scan disable
5635 01:36:29.821679 == TX Byte 0 ==
5636 01:36:29.824957 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5637 01:36:29.831505 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5638 01:36:29.831609 == TX Byte 1 ==
5639 01:36:29.837743 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5640 01:36:29.841189 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5641 01:36:29.841316 ==
5642 01:36:29.844401 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 01:36:29.847668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 01:36:29.847751 ==
5645 01:36:29.847816
5646 01:36:29.847876
5647 01:36:29.850901 TX Vref Scan disable
5648 01:36:29.854286 == TX Byte 0 ==
5649 01:36:29.858207 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5650 01:36:29.861181 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5651 01:36:29.864127 == TX Byte 1 ==
5652 01:36:29.867279 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5653 01:36:29.871019 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5654 01:36:29.871102
5655 01:36:29.874326 [DATLAT]
5656 01:36:29.874408 Freq=933, CH1 RK0
5657 01:36:29.874473
5658 01:36:29.877471 DATLAT Default: 0xd
5659 01:36:29.877552 0, 0xFFFF, sum = 0
5660 01:36:29.880844 1, 0xFFFF, sum = 0
5661 01:36:29.880927 2, 0xFFFF, sum = 0
5662 01:36:29.883855 3, 0xFFFF, sum = 0
5663 01:36:29.883939 4, 0xFFFF, sum = 0
5664 01:36:29.887133 5, 0xFFFF, sum = 0
5665 01:36:29.887217 6, 0xFFFF, sum = 0
5666 01:36:29.890368 7, 0xFFFF, sum = 0
5667 01:36:29.890452 8, 0xFFFF, sum = 0
5668 01:36:29.893982 9, 0xFFFF, sum = 0
5669 01:36:29.894066 10, 0x0, sum = 1
5670 01:36:29.897563 11, 0x0, sum = 2
5671 01:36:29.897646 12, 0x0, sum = 3
5672 01:36:29.900587 13, 0x0, sum = 4
5673 01:36:29.900671 best_step = 11
5674 01:36:29.900736
5675 01:36:29.900795 ==
5676 01:36:29.903536 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 01:36:29.910364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 01:36:29.910490 ==
5679 01:36:29.910556 RX Vref Scan: 1
5680 01:36:29.910616
5681 01:36:29.913686 RX Vref 0 -> 0, step: 1
5682 01:36:29.913768
5683 01:36:29.917203 RX Delay -53 -> 252, step: 4
5684 01:36:29.917286
5685 01:36:29.920092 Set Vref, RX VrefLevel [Byte0]: 53
5686 01:36:29.923629 [Byte1]: 54
5687 01:36:29.923711
5688 01:36:29.926685 Final RX Vref Byte 0 = 53 to rank0
5689 01:36:29.930012 Final RX Vref Byte 1 = 54 to rank0
5690 01:36:29.933419 Final RX Vref Byte 0 = 53 to rank1
5691 01:36:29.936863 Final RX Vref Byte 1 = 54 to rank1==
5692 01:36:29.940217 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 01:36:29.942954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 01:36:29.946061 ==
5695 01:36:29.946143 DQS Delay:
5696 01:36:29.946207 DQS0 = 0, DQS1 = 0
5697 01:36:29.950155 DQM Delay:
5698 01:36:29.950237 DQM0 = 98, DQM1 = 95
5699 01:36:29.953115 DQ Delay:
5700 01:36:29.953198 DQ0 =106, DQ1 =94, DQ2 =86, DQ3 =96
5701 01:36:29.956479 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5702 01:36:29.959580 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =90
5703 01:36:29.966065 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5704 01:36:29.966148
5705 01:36:29.966213
5706 01:36:29.972639 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5707 01:36:29.975860 CH1 RK0: MR19=505, MR18=818
5708 01:36:29.982481 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5709 01:36:29.982565
5710 01:36:29.985779 ----->DramcWriteLeveling(PI) begin...
5711 01:36:29.985863 ==
5712 01:36:29.989324 Dram Type= 6, Freq= 0, CH_1, rank 1
5713 01:36:29.992170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 01:36:29.992252 ==
5715 01:36:29.996164 Write leveling (Byte 0): 24 => 24
5716 01:36:29.999164 Write leveling (Byte 1): 28 => 28
5717 01:36:30.002413 DramcWriteLeveling(PI) end<-----
5718 01:36:30.002495
5719 01:36:30.002559 ==
5720 01:36:30.005642 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 01:36:30.009081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 01:36:30.009164 ==
5723 01:36:30.012128 [Gating] SW mode calibration
5724 01:36:30.018962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5725 01:36:30.025175 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5726 01:36:30.028714 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5727 01:36:30.035500 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5728 01:36:30.038482 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5729 01:36:30.041955 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 01:36:30.048682 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 01:36:30.051660 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 01:36:30.054645 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5733 01:36:30.061768 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5734 01:36:30.064791 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5735 01:36:30.068095 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5736 01:36:30.074480 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5737 01:36:30.078057 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 01:36:30.081340 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 01:36:30.087650 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 01:36:30.090799 0 15 24 | B1->B0 | 2726 3131 | 1 0 | (0 0) (0 0)
5741 01:36:30.094102 0 15 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5742 01:36:30.101043 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5743 01:36:30.104149 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5744 01:36:30.107593 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5745 01:36:30.114234 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 01:36:30.117107 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 01:36:30.120637 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 01:36:30.126997 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5749 01:36:30.130508 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5750 01:36:30.133848 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5751 01:36:30.140255 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5752 01:36:30.143732 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 01:36:30.149762 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 01:36:30.153465 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 01:36:30.156481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 01:36:30.163154 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 01:36:30.166787 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 01:36:30.169760 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 01:36:30.176202 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 01:36:30.179848 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 01:36:30.183008 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 01:36:30.189661 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 01:36:30.192849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 01:36:30.195908 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5765 01:36:30.202813 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5766 01:36:30.202896 Total UI for P1: 0, mck2ui 16
5767 01:36:30.209426 best dqsien dly found for B0: ( 1, 2, 24)
5768 01:36:30.212660 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 01:36:30.215844 Total UI for P1: 0, mck2ui 16
5770 01:36:30.219278 best dqsien dly found for B1: ( 1, 2, 28)
5771 01:36:30.222641 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5772 01:36:30.225620 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5773 01:36:30.225703
5774 01:36:30.229287 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5775 01:36:30.232861 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5776 01:36:30.235941 [Gating] SW calibration Done
5777 01:36:30.236024 ==
5778 01:36:30.239204 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 01:36:30.242558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 01:36:30.242660 ==
5781 01:36:30.245610 RX Vref Scan: 0
5782 01:36:30.245684
5783 01:36:30.248920 RX Vref 0 -> 0, step: 1
5784 01:36:30.249003
5785 01:36:30.249068 RX Delay -80 -> 252, step: 8
5786 01:36:30.255383 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5787 01:36:30.258781 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5788 01:36:30.262104 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5789 01:36:30.265842 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5790 01:36:30.269032 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5791 01:36:30.275054 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5792 01:36:30.278697 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5793 01:36:30.281823 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5794 01:36:30.285439 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5795 01:36:30.288422 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5796 01:36:30.291590 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5797 01:36:30.298176 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5798 01:36:30.301675 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5799 01:36:30.305178 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5800 01:36:30.308148 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5801 01:36:30.311280 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5802 01:36:30.315205 ==
5803 01:36:30.315288 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 01:36:30.321450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 01:36:30.321534 ==
5806 01:36:30.321600 DQS Delay:
5807 01:36:30.324722 DQS0 = 0, DQS1 = 0
5808 01:36:30.324804 DQM Delay:
5809 01:36:30.327626 DQM0 = 97, DQM1 = 94
5810 01:36:30.327709 DQ Delay:
5811 01:36:30.330885 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5812 01:36:30.334574 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5813 01:36:30.337905 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5814 01:36:30.341352 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5815 01:36:30.341435
5816 01:36:30.341501
5817 01:36:30.341560 ==
5818 01:36:30.344189 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 01:36:30.347999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 01:36:30.348082 ==
5821 01:36:30.351327
5822 01:36:30.351409
5823 01:36:30.351474 TX Vref Scan disable
5824 01:36:30.354123 == TX Byte 0 ==
5825 01:36:30.357673 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5826 01:36:30.361009 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5827 01:36:30.364528 == TX Byte 1 ==
5828 01:36:30.367537 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5829 01:36:30.370536 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5830 01:36:30.374146 ==
5831 01:36:30.374229 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 01:36:30.380484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 01:36:30.380569 ==
5834 01:36:30.380634
5835 01:36:30.380694
5836 01:36:30.383914 TX Vref Scan disable
5837 01:36:30.383996 == TX Byte 0 ==
5838 01:36:30.390786 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5839 01:36:30.393671 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5840 01:36:30.393754 == TX Byte 1 ==
5841 01:36:30.400330 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5842 01:36:30.403414 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5843 01:36:30.403497
5844 01:36:30.403562 [DATLAT]
5845 01:36:30.406637 Freq=933, CH1 RK1
5846 01:36:30.406720
5847 01:36:30.406785 DATLAT Default: 0xb
5848 01:36:30.409977 0, 0xFFFF, sum = 0
5849 01:36:30.410061 1, 0xFFFF, sum = 0
5850 01:36:30.413456 2, 0xFFFF, sum = 0
5851 01:36:30.416665 3, 0xFFFF, sum = 0
5852 01:36:30.416749 4, 0xFFFF, sum = 0
5853 01:36:30.420093 5, 0xFFFF, sum = 0
5854 01:36:30.420176 6, 0xFFFF, sum = 0
5855 01:36:30.423160 7, 0xFFFF, sum = 0
5856 01:36:30.423244 8, 0xFFFF, sum = 0
5857 01:36:30.426905 9, 0xFFFF, sum = 0
5858 01:36:30.426989 10, 0x0, sum = 1
5859 01:36:30.430069 11, 0x0, sum = 2
5860 01:36:30.430152 12, 0x0, sum = 3
5861 01:36:30.433127 13, 0x0, sum = 4
5862 01:36:30.433238 best_step = 11
5863 01:36:30.433355
5864 01:36:30.433418 ==
5865 01:36:30.436525 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 01:36:30.439670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 01:36:30.439753 ==
5868 01:36:30.442740 RX Vref Scan: 0
5869 01:36:30.442823
5870 01:36:30.446048 RX Vref 0 -> 0, step: 1
5871 01:36:30.446130
5872 01:36:30.446195 RX Delay -53 -> 252, step: 4
5873 01:36:30.453961 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5874 01:36:30.457355 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5875 01:36:30.460613 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5876 01:36:30.464264 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5877 01:36:30.467234 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5878 01:36:30.473974 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5879 01:36:30.477115 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5880 01:36:30.480247 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5881 01:36:30.483655 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5882 01:36:30.486957 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5883 01:36:30.494047 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5884 01:36:30.497044 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5885 01:36:30.500066 iDelay=199, Bit 12, Center 104 (15 ~ 194) 180
5886 01:36:30.503475 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5887 01:36:30.506752 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5888 01:36:30.513765 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5889 01:36:30.513848 ==
5890 01:36:30.516799 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 01:36:30.520311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 01:36:30.520393 ==
5893 01:36:30.520458 DQS Delay:
5894 01:36:30.523659 DQS0 = 0, DQS1 = 0
5895 01:36:30.523741 DQM Delay:
5896 01:36:30.526414 DQM0 = 97, DQM1 = 93
5897 01:36:30.526497 DQ Delay:
5898 01:36:30.530298 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5899 01:36:30.533648 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =96
5900 01:36:30.537208 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5901 01:36:30.539876 DQ12 =104, DQ13 =100, DQ14 =98, DQ15 =102
5902 01:36:30.539988
5903 01:36:30.540080
5904 01:36:30.549655 [DQSOSCAuto] RK1, (LSB)MR18= 0xe25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5905 01:36:30.549739 CH1 RK1: MR19=505, MR18=E25
5906 01:36:30.556319 CH1_RK1: MR19=0x505, MR18=0xE25, DQSOSC=410, MR23=63, INC=64, DEC=42
5907 01:36:30.559474 [RxdqsGatingPostProcess] freq 933
5908 01:36:30.566076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5909 01:36:30.569598 best DQS0 dly(2T, 0.5T) = (0, 10)
5910 01:36:30.572831 best DQS1 dly(2T, 0.5T) = (0, 10)
5911 01:36:30.576016 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5912 01:36:30.579050 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5913 01:36:30.582400 best DQS0 dly(2T, 0.5T) = (0, 10)
5914 01:36:30.582472 best DQS1 dly(2T, 0.5T) = (0, 10)
5915 01:36:30.586264 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5916 01:36:30.589179 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5917 01:36:30.592580 Pre-setting of DQS Precalculation
5918 01:36:30.599154 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5919 01:36:30.605826 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5920 01:36:30.612117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5921 01:36:30.612200
5922 01:36:30.612264
5923 01:36:30.615273 [Calibration Summary] 1866 Mbps
5924 01:36:30.618812 CH 0, Rank 0
5925 01:36:30.618895 SW Impedance : PASS
5926 01:36:30.621866 DUTY Scan : NO K
5927 01:36:30.625302 ZQ Calibration : PASS
5928 01:36:30.625385 Jitter Meter : NO K
5929 01:36:30.628768 CBT Training : PASS
5930 01:36:30.631657 Write leveling : PASS
5931 01:36:30.631740 RX DQS gating : PASS
5932 01:36:30.634897 RX DQ/DQS(RDDQC) : PASS
5933 01:36:30.638593 TX DQ/DQS : PASS
5934 01:36:30.638676 RX DATLAT : PASS
5935 01:36:30.641666 RX DQ/DQS(Engine): PASS
5936 01:36:30.641752 TX OE : NO K
5937 01:36:30.644721 All Pass.
5938 01:36:30.644820
5939 01:36:30.644912 CH 0, Rank 1
5940 01:36:30.648684 SW Impedance : PASS
5941 01:36:30.648757 DUTY Scan : NO K
5942 01:36:30.652002 ZQ Calibration : PASS
5943 01:36:30.654908 Jitter Meter : NO K
5944 01:36:30.654987 CBT Training : PASS
5945 01:36:30.658160 Write leveling : PASS
5946 01:36:30.661400 RX DQS gating : PASS
5947 01:36:30.661482 RX DQ/DQS(RDDQC) : PASS
5948 01:36:30.664839 TX DQ/DQS : PASS
5949 01:36:30.668071 RX DATLAT : PASS
5950 01:36:30.668141 RX DQ/DQS(Engine): PASS
5951 01:36:30.671444 TX OE : NO K
5952 01:36:30.671542 All Pass.
5953 01:36:30.671630
5954 01:36:30.674996 CH 1, Rank 0
5955 01:36:30.675092 SW Impedance : PASS
5956 01:36:30.677896 DUTY Scan : NO K
5957 01:36:30.681266 ZQ Calibration : PASS
5958 01:36:30.681393 Jitter Meter : NO K
5959 01:36:30.684463 CBT Training : PASS
5960 01:36:30.687755 Write leveling : PASS
5961 01:36:30.687824 RX DQS gating : PASS
5962 01:36:30.691095 RX DQ/DQS(RDDQC) : PASS
5963 01:36:30.694503 TX DQ/DQS : PASS
5964 01:36:30.694588 RX DATLAT : PASS
5965 01:36:30.698070 RX DQ/DQS(Engine): PASS
5966 01:36:30.700871 TX OE : NO K
5967 01:36:30.700966 All Pass.
5968 01:36:30.701061
5969 01:36:30.701148 CH 1, Rank 1
5970 01:36:30.704213 SW Impedance : PASS
5971 01:36:30.707835 DUTY Scan : NO K
5972 01:36:30.707917 ZQ Calibration : PASS
5973 01:36:30.710953 Jitter Meter : NO K
5974 01:36:30.714161 CBT Training : PASS
5975 01:36:30.714260 Write leveling : PASS
5976 01:36:30.717521 RX DQS gating : PASS
5977 01:36:30.720555 RX DQ/DQS(RDDQC) : PASS
5978 01:36:30.720653 TX DQ/DQS : PASS
5979 01:36:30.724000 RX DATLAT : PASS
5980 01:36:30.727074 RX DQ/DQS(Engine): PASS
5981 01:36:30.727171 TX OE : NO K
5982 01:36:30.727261 All Pass.
5983 01:36:30.730360
5984 01:36:30.730456 DramC Write-DBI off
5985 01:36:30.733764 PER_BANK_REFRESH: Hybrid Mode
5986 01:36:30.733852 TX_TRACKING: ON
5987 01:36:30.743748 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5988 01:36:30.746723 [FAST_K] Save calibration result to emmc
5989 01:36:30.750084 dramc_set_vcore_voltage set vcore to 650000
5990 01:36:30.753607 Read voltage for 400, 6
5991 01:36:30.753678 Vio18 = 0
5992 01:36:30.756967 Vcore = 650000
5993 01:36:30.757072 Vdram = 0
5994 01:36:30.757161 Vddq = 0
5995 01:36:30.760369 Vmddr = 0
5996 01:36:30.763721 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5997 01:36:30.770014 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5998 01:36:30.770105 MEM_TYPE=3, freq_sel=20
5999 01:36:30.773163 sv_algorithm_assistance_LP4_800
6000 01:36:30.779789 ============ PULL DRAM RESETB DOWN ============
6001 01:36:30.783631 ========== PULL DRAM RESETB DOWN end =========
6002 01:36:30.786556 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6003 01:36:30.789804 ===================================
6004 01:36:30.793172 LPDDR4 DRAM CONFIGURATION
6005 01:36:30.795988 ===================================
6006 01:36:30.799714 EX_ROW_EN[0] = 0x0
6007 01:36:30.799821 EX_ROW_EN[1] = 0x0
6008 01:36:30.803131 LP4Y_EN = 0x0
6009 01:36:30.803203 WORK_FSP = 0x0
6010 01:36:30.806017 WL = 0x2
6011 01:36:30.806100 RL = 0x2
6012 01:36:30.809370 BL = 0x2
6013 01:36:30.809441 RPST = 0x0
6014 01:36:30.813180 RD_PRE = 0x0
6015 01:36:30.813269 WR_PRE = 0x1
6016 01:36:30.816086 WR_PST = 0x0
6017 01:36:30.816168 DBI_WR = 0x0
6018 01:36:30.819698 DBI_RD = 0x0
6019 01:36:30.819780 OTF = 0x1
6020 01:36:30.822649 ===================================
6021 01:36:30.825630 ===================================
6022 01:36:30.828919 ANA top config
6023 01:36:30.832226 ===================================
6024 01:36:30.835919 DLL_ASYNC_EN = 0
6025 01:36:30.836003 ALL_SLAVE_EN = 1
6026 01:36:30.838686 NEW_RANK_MODE = 1
6027 01:36:30.842005 DLL_IDLE_MODE = 1
6028 01:36:30.845528 LP45_APHY_COMB_EN = 1
6029 01:36:30.849023 TX_ODT_DIS = 1
6030 01:36:30.849105 NEW_8X_MODE = 1
6031 01:36:30.852117 ===================================
6032 01:36:30.855363 ===================================
6033 01:36:30.858890 data_rate = 800
6034 01:36:30.861888 CKR = 1
6035 01:36:30.864978 DQ_P2S_RATIO = 4
6036 01:36:30.868707 ===================================
6037 01:36:30.871639 CA_P2S_RATIO = 4
6038 01:36:30.875031 DQ_CA_OPEN = 0
6039 01:36:30.875114 DQ_SEMI_OPEN = 1
6040 01:36:30.878395 CA_SEMI_OPEN = 1
6041 01:36:30.882250 CA_FULL_RATE = 0
6042 01:36:30.884699 DQ_CKDIV4_EN = 0
6043 01:36:30.888128 CA_CKDIV4_EN = 1
6044 01:36:30.891703 CA_PREDIV_EN = 0
6045 01:36:30.891785 PH8_DLY = 0
6046 01:36:30.894746 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6047 01:36:30.898256 DQ_AAMCK_DIV = 0
6048 01:36:30.901540 CA_AAMCK_DIV = 0
6049 01:36:30.904541 CA_ADMCK_DIV = 4
6050 01:36:30.908684 DQ_TRACK_CA_EN = 0
6051 01:36:30.911174 CA_PICK = 800
6052 01:36:30.911256 CA_MCKIO = 400
6053 01:36:30.914693 MCKIO_SEMI = 400
6054 01:36:30.917631 PLL_FREQ = 3016
6055 01:36:30.921013 DQ_UI_PI_RATIO = 32
6056 01:36:30.924409 CA_UI_PI_RATIO = 32
6057 01:36:30.927527 ===================================
6058 01:36:30.930786 ===================================
6059 01:36:30.934444 memory_type:LPDDR4
6060 01:36:30.934526 GP_NUM : 10
6061 01:36:30.937440 SRAM_EN : 1
6062 01:36:30.941146 MD32_EN : 0
6063 01:36:30.944502 ===================================
6064 01:36:30.944585 [ANA_INIT] >>>>>>>>>>>>>>
6065 01:36:30.947143 <<<<<< [CONFIGURE PHASE]: ANA_TX
6066 01:36:30.950486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6067 01:36:30.954140 ===================================
6068 01:36:30.957211 data_rate = 800,PCW = 0X7400
6069 01:36:30.960784 ===================================
6070 01:36:30.963876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6071 01:36:30.970688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6072 01:36:30.980513 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6073 01:36:30.987383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6074 01:36:30.990329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6075 01:36:30.993802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6076 01:36:30.993885 [ANA_INIT] flow start
6077 01:36:30.996780 [ANA_INIT] PLL >>>>>>>>
6078 01:36:31.000481 [ANA_INIT] PLL <<<<<<<<
6079 01:36:31.000563 [ANA_INIT] MIDPI >>>>>>>>
6080 01:36:31.003514 [ANA_INIT] MIDPI <<<<<<<<
6081 01:36:31.006438 [ANA_INIT] DLL >>>>>>>>
6082 01:36:31.006520 [ANA_INIT] flow end
6083 01:36:31.013138 ============ LP4 DIFF to SE enter ============
6084 01:36:31.016546 ============ LP4 DIFF to SE exit ============
6085 01:36:31.020106 [ANA_INIT] <<<<<<<<<<<<<
6086 01:36:31.022940 [Flow] Enable top DCM control >>>>>
6087 01:36:31.026165 [Flow] Enable top DCM control <<<<<
6088 01:36:31.029818 Enable DLL master slave shuffle
6089 01:36:31.032843 ==============================================================
6090 01:36:31.036314 Gating Mode config
6091 01:36:31.039474 ==============================================================
6092 01:36:31.042941 Config description:
6093 01:36:31.052599 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6094 01:36:31.059237 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6095 01:36:31.062736 SELPH_MODE 0: By rank 1: By Phase
6096 01:36:31.069193 ==============================================================
6097 01:36:31.072973 GAT_TRACK_EN = 0
6098 01:36:31.075563 RX_GATING_MODE = 2
6099 01:36:31.078860 RX_GATING_TRACK_MODE = 2
6100 01:36:31.082257 SELPH_MODE = 1
6101 01:36:31.085439 PICG_EARLY_EN = 1
6102 01:36:31.088863 VALID_LAT_VALUE = 1
6103 01:36:31.091955 ==============================================================
6104 01:36:31.095691 Enter into Gating configuration >>>>
6105 01:36:31.098631 Exit from Gating configuration <<<<
6106 01:36:31.102710 Enter into DVFS_PRE_config >>>>>
6107 01:36:31.115210 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6108 01:36:31.118122 Exit from DVFS_PRE_config <<<<<
6109 01:36:31.121989 Enter into PICG configuration >>>>
6110 01:36:31.122107 Exit from PICG configuration <<<<
6111 01:36:31.124847 [RX_INPUT] configuration >>>>>
6112 01:36:31.128483 [RX_INPUT] configuration <<<<<
6113 01:36:31.134892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6114 01:36:31.138316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6115 01:36:31.145004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6116 01:36:31.151412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6117 01:36:31.157896 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6118 01:36:31.164872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6119 01:36:31.167927 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6120 01:36:31.171211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6121 01:36:31.177841 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6122 01:36:31.181309 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6123 01:36:31.184921 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6124 01:36:31.187975 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6125 01:36:31.191691 ===================================
6126 01:36:31.194175 LPDDR4 DRAM CONFIGURATION
6127 01:36:31.197581 ===================================
6128 01:36:31.201203 EX_ROW_EN[0] = 0x0
6129 01:36:31.201770 EX_ROW_EN[1] = 0x0
6130 01:36:31.204893 LP4Y_EN = 0x0
6131 01:36:31.205458 WORK_FSP = 0x0
6132 01:36:31.207693 WL = 0x2
6133 01:36:31.210760 RL = 0x2
6134 01:36:31.211179 BL = 0x2
6135 01:36:31.214500 RPST = 0x0
6136 01:36:31.215032 RD_PRE = 0x0
6137 01:36:31.217191 WR_PRE = 0x1
6138 01:36:31.217655 WR_PST = 0x0
6139 01:36:31.220537 DBI_WR = 0x0
6140 01:36:31.220961 DBI_RD = 0x0
6141 01:36:31.223690 OTF = 0x1
6142 01:36:31.227235 ===================================
6143 01:36:31.230584 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6144 01:36:31.233923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6145 01:36:31.240383 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 01:36:31.243280 ===================================
6147 01:36:31.243838 LPDDR4 DRAM CONFIGURATION
6148 01:36:31.247584 ===================================
6149 01:36:31.250042 EX_ROW_EN[0] = 0x10
6150 01:36:31.253568 EX_ROW_EN[1] = 0x0
6151 01:36:31.253988 LP4Y_EN = 0x0
6152 01:36:31.256607 WORK_FSP = 0x0
6153 01:36:31.257023 WL = 0x2
6154 01:36:31.259882 RL = 0x2
6155 01:36:31.260295 BL = 0x2
6156 01:36:31.263443 RPST = 0x0
6157 01:36:31.264005 RD_PRE = 0x0
6158 01:36:31.266314 WR_PRE = 0x1
6159 01:36:31.266731 WR_PST = 0x0
6160 01:36:31.269768 DBI_WR = 0x0
6161 01:36:31.270183 DBI_RD = 0x0
6162 01:36:31.272894 OTF = 0x1
6163 01:36:31.276096 ===================================
6164 01:36:31.283560 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6165 01:36:31.286143 nWR fixed to 30
6166 01:36:31.286563 [ModeRegInit_LP4] CH0 RK0
6167 01:36:31.289631 [ModeRegInit_LP4] CH0 RK1
6168 01:36:31.292795 [ModeRegInit_LP4] CH1 RK0
6169 01:36:31.296633 [ModeRegInit_LP4] CH1 RK1
6170 01:36:31.297061 match AC timing 19
6171 01:36:31.302657 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6172 01:36:31.306109 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6173 01:36:31.309582 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6174 01:36:31.316131 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6175 01:36:31.319319 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6176 01:36:31.319743 ==
6177 01:36:31.322600 Dram Type= 6, Freq= 0, CH_0, rank 0
6178 01:36:31.326026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6179 01:36:31.326448 ==
6180 01:36:31.332605 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6181 01:36:31.339177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6182 01:36:31.342377 [CA 0] Center 36 (8~64) winsize 57
6183 01:36:31.345614 [CA 1] Center 36 (8~64) winsize 57
6184 01:36:31.348723 [CA 2] Center 36 (8~64) winsize 57
6185 01:36:31.349183 [CA 3] Center 36 (8~64) winsize 57
6186 01:36:31.352353 [CA 4] Center 36 (8~64) winsize 57
6187 01:36:31.355830 [CA 5] Center 36 (8~64) winsize 57
6188 01:36:31.356350
6189 01:36:31.362452 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6190 01:36:31.362872
6191 01:36:31.365539 [CATrainingPosCal] consider 1 rank data
6192 01:36:31.368497 u2DelayCellTimex100 = 270/100 ps
6193 01:36:31.372323 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6194 01:36:31.375322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6195 01:36:31.378791 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 01:36:31.382105 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 01:36:31.385139 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 01:36:31.388433 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 01:36:31.388947
6200 01:36:31.392117 CA PerBit enable=1, Macro0, CA PI delay=36
6201 01:36:31.392740
6202 01:36:31.395126 [CBTSetCACLKResult] CA Dly = 36
6203 01:36:31.398126 CS Dly: 1 (0~32)
6204 01:36:31.398590 ==
6205 01:36:31.402186 Dram Type= 6, Freq= 0, CH_0, rank 1
6206 01:36:31.404957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 01:36:31.405564 ==
6208 01:36:31.411437 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 01:36:31.418333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6210 01:36:31.421083 [CA 0] Center 36 (8~64) winsize 57
6211 01:36:31.425475 [CA 1] Center 36 (8~64) winsize 57
6212 01:36:31.426036 [CA 2] Center 36 (8~64) winsize 57
6213 01:36:31.428145 [CA 3] Center 36 (8~64) winsize 57
6214 01:36:31.430898 [CA 4] Center 36 (8~64) winsize 57
6215 01:36:31.434449 [CA 5] Center 36 (8~64) winsize 57
6216 01:36:31.434914
6217 01:36:31.441184 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6218 01:36:31.441791
6219 01:36:31.444516 [CATrainingPosCal] consider 2 rank data
6220 01:36:31.447441 u2DelayCellTimex100 = 270/100 ps
6221 01:36:31.450761 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 01:36:31.454226 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 01:36:31.457848 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 01:36:31.460782 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 01:36:31.464000 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 01:36:31.467271 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 01:36:31.467990
6228 01:36:31.470882 CA PerBit enable=1, Macro0, CA PI delay=36
6229 01:36:31.471601
6230 01:36:31.474216 [CBTSetCACLKResult] CA Dly = 36
6231 01:36:31.477074 CS Dly: 1 (0~32)
6232 01:36:31.477590
6233 01:36:31.480605 ----->DramcWriteLeveling(PI) begin...
6234 01:36:31.481188 ==
6235 01:36:31.484186 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 01:36:31.486914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 01:36:31.487360 ==
6238 01:36:31.490293 Write leveling (Byte 0): 40 => 8
6239 01:36:31.493602 Write leveling (Byte 1): 40 => 8
6240 01:36:31.496980 DramcWriteLeveling(PI) end<-----
6241 01:36:31.497456
6242 01:36:31.497861 ==
6243 01:36:31.500580 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 01:36:31.503356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 01:36:31.503784 ==
6246 01:36:31.507136 [Gating] SW mode calibration
6247 01:36:31.513381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6248 01:36:31.519746 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6249 01:36:31.523361 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6250 01:36:31.529837 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6251 01:36:31.533071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6252 01:36:31.536034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6253 01:36:31.543257 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6254 01:36:31.546108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6255 01:36:31.550008 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 01:36:31.555929 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 01:36:31.559113 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6258 01:36:31.562472 Total UI for P1: 0, mck2ui 16
6259 01:36:31.566024 best dqsien dly found for B0: ( 0, 14, 24)
6260 01:36:31.569223 Total UI for P1: 0, mck2ui 16
6261 01:36:31.572534 best dqsien dly found for B1: ( 0, 14, 24)
6262 01:36:31.575503 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6263 01:36:31.579140 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6264 01:36:31.579567
6265 01:36:31.582395 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6266 01:36:31.585477 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6267 01:36:31.588831 [Gating] SW calibration Done
6268 01:36:31.589425 ==
6269 01:36:31.592398 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 01:36:31.598928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 01:36:31.599354 ==
6272 01:36:31.599690 RX Vref Scan: 0
6273 01:36:31.599999
6274 01:36:31.601964 RX Vref 0 -> 0, step: 1
6275 01:36:31.602389
6276 01:36:31.605054 RX Delay -410 -> 252, step: 16
6277 01:36:31.609449 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6278 01:36:31.612095 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6279 01:36:31.618496 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6280 01:36:31.621497 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6281 01:36:31.625390 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6282 01:36:31.628500 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6283 01:36:31.634995 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6284 01:36:31.638716 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6285 01:36:31.642103 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6286 01:36:31.645034 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6287 01:36:31.651758 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6288 01:36:31.655074 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6289 01:36:31.657968 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6290 01:36:31.661623 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6291 01:36:31.668818 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6292 01:36:31.671456 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6293 01:36:31.672018 ==
6294 01:36:31.674454 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 01:36:31.677717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 01:36:31.678189 ==
6297 01:36:31.681492 DQS Delay:
6298 01:36:31.681955 DQS0 = 35, DQS1 = 51
6299 01:36:31.684554 DQM Delay:
6300 01:36:31.684971 DQM0 = 4, DQM1 = 10
6301 01:36:31.687781 DQ Delay:
6302 01:36:31.688201 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6303 01:36:31.691438 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6304 01:36:31.694011 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6305 01:36:31.697360 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6306 01:36:31.697804
6307 01:36:31.698164
6308 01:36:31.698486 ==
6309 01:36:31.700821 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 01:36:31.707573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 01:36:31.708084 ==
6312 01:36:31.708417
6313 01:36:31.708720
6314 01:36:31.709069 TX Vref Scan disable
6315 01:36:31.710576 == TX Byte 0 ==
6316 01:36:31.714009 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6317 01:36:31.717293 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6318 01:36:31.720531 == TX Byte 1 ==
6319 01:36:31.724369 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6320 01:36:31.727271 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6321 01:36:31.730511 ==
6322 01:36:31.734009 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 01:36:31.737183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 01:36:31.737640 ==
6325 01:36:31.737968
6326 01:36:31.738273
6327 01:36:31.740564 TX Vref Scan disable
6328 01:36:31.741075 == TX Byte 0 ==
6329 01:36:31.743946 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6330 01:36:31.750347 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6331 01:36:31.750861 == TX Byte 1 ==
6332 01:36:31.753864 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 01:36:31.760328 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 01:36:31.760842
6335 01:36:31.761173 [DATLAT]
6336 01:36:31.761533 Freq=400, CH0 RK0
6337 01:36:31.761839
6338 01:36:31.763561 DATLAT Default: 0xf
6339 01:36:31.764071 0, 0xFFFF, sum = 0
6340 01:36:31.766814 1, 0xFFFF, sum = 0
6341 01:36:31.770016 2, 0xFFFF, sum = 0
6342 01:36:31.770554 3, 0xFFFF, sum = 0
6343 01:36:31.773363 4, 0xFFFF, sum = 0
6344 01:36:31.773790 5, 0xFFFF, sum = 0
6345 01:36:31.777055 6, 0xFFFF, sum = 0
6346 01:36:31.777621 7, 0xFFFF, sum = 0
6347 01:36:31.780185 8, 0xFFFF, sum = 0
6348 01:36:31.780698 9, 0xFFFF, sum = 0
6349 01:36:31.783474 10, 0xFFFF, sum = 0
6350 01:36:31.783997 11, 0xFFFF, sum = 0
6351 01:36:31.786542 12, 0xFFFF, sum = 0
6352 01:36:31.787059 13, 0x0, sum = 1
6353 01:36:31.789994 14, 0x0, sum = 2
6354 01:36:31.790524 15, 0x0, sum = 3
6355 01:36:31.793211 16, 0x0, sum = 4
6356 01:36:31.793774 best_step = 14
6357 01:36:31.794106
6358 01:36:31.794410 ==
6359 01:36:31.796941 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 01:36:31.803231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 01:36:31.803745 ==
6362 01:36:31.804078 RX Vref Scan: 1
6363 01:36:31.804390
6364 01:36:31.806270 RX Vref 0 -> 0, step: 1
6365 01:36:31.806766
6366 01:36:31.809596 RX Delay -343 -> 252, step: 8
6367 01:36:31.810111
6368 01:36:31.812871 Set Vref, RX VrefLevel [Byte0]: 53
6369 01:36:31.816588 [Byte1]: 50
6370 01:36:31.817097
6371 01:36:31.819198 Final RX Vref Byte 0 = 53 to rank0
6372 01:36:31.822487 Final RX Vref Byte 1 = 50 to rank0
6373 01:36:31.825921 Final RX Vref Byte 0 = 53 to rank1
6374 01:36:31.829401 Final RX Vref Byte 1 = 50 to rank1==
6375 01:36:31.832308 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 01:36:31.836013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 01:36:31.839424 ==
6378 01:36:31.839952 DQS Delay:
6379 01:36:31.840316 DQS0 = 44, DQS1 = 56
6380 01:36:31.842569 DQM Delay:
6381 01:36:31.842991 DQM0 = 10, DQM1 = 14
6382 01:36:31.845503 DQ Delay:
6383 01:36:31.849469 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6384 01:36:31.850018 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6385 01:36:31.852572 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6386 01:36:31.855606 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6387 01:36:31.856163
6388 01:36:31.859083
6389 01:36:31.865686 [DQSOSCAuto] RK0, (LSB)MR18= 0x978a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6390 01:36:31.869165 CH0 RK0: MR19=C0C, MR18=978A
6391 01:36:31.875478 CH0_RK0: MR19=0xC0C, MR18=0x978A, DQSOSC=390, MR23=63, INC=388, DEC=258
6392 01:36:31.876023 ==
6393 01:36:31.879022 Dram Type= 6, Freq= 0, CH_0, rank 1
6394 01:36:31.882304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 01:36:31.882869 ==
6396 01:36:31.886139 [Gating] SW mode calibration
6397 01:36:31.891799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6398 01:36:31.898430 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6399 01:36:31.901847 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6400 01:36:31.905510 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 01:36:31.912078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6402 01:36:31.915304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 01:36:31.918343 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6404 01:36:31.925121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 01:36:31.928198 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 01:36:31.931867 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 01:36:31.938022 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6408 01:36:31.938487 Total UI for P1: 0, mck2ui 16
6409 01:36:31.944820 best dqsien dly found for B0: ( 0, 14, 24)
6410 01:36:31.945417 Total UI for P1: 0, mck2ui 16
6411 01:36:31.951428 best dqsien dly found for B1: ( 0, 14, 24)
6412 01:36:31.954866 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6413 01:36:31.957960 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6414 01:36:31.958425
6415 01:36:31.960889 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6416 01:36:31.964652 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 01:36:31.967542 [Gating] SW calibration Done
6418 01:36:31.968010 ==
6419 01:36:31.970976 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 01:36:31.974265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 01:36:31.974734 ==
6422 01:36:31.977878 RX Vref Scan: 0
6423 01:36:31.978391
6424 01:36:31.981173 RX Vref 0 -> 0, step: 1
6425 01:36:31.981801
6426 01:36:31.982181 RX Delay -410 -> 252, step: 16
6427 01:36:31.987758 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6428 01:36:31.991576 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6429 01:36:31.994273 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6430 01:36:32.000820 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6431 01:36:32.003955 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6432 01:36:32.006789 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6433 01:36:32.010210 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6434 01:36:32.017070 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6435 01:36:32.020615 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6436 01:36:32.023131 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6437 01:36:32.027307 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6438 01:36:32.033489 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6439 01:36:32.036627 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6440 01:36:32.040162 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6441 01:36:32.046323 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6442 01:36:32.049712 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6443 01:36:32.050273 ==
6444 01:36:32.053117 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 01:36:32.056508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 01:36:32.057071 ==
6447 01:36:32.059635 DQS Delay:
6448 01:36:32.060093 DQS0 = 35, DQS1 = 59
6449 01:36:32.060457 DQM Delay:
6450 01:36:32.062640 DQM0 = 6, DQM1 = 17
6451 01:36:32.063102 DQ Delay:
6452 01:36:32.065934 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6453 01:36:32.069352 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6454 01:36:32.072649 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6455 01:36:32.076164 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6456 01:36:32.076725
6457 01:36:32.077093
6458 01:36:32.077500 ==
6459 01:36:32.079374 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 01:36:32.082875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 01:36:32.085861 ==
6462 01:36:32.086277
6463 01:36:32.086603
6464 01:36:32.086905 TX Vref Scan disable
6465 01:36:32.089353 == TX Byte 0 ==
6466 01:36:32.092525 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6467 01:36:32.095821 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6468 01:36:32.099743 == TX Byte 1 ==
6469 01:36:32.103065 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6470 01:36:32.105747 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6471 01:36:32.106170 ==
6472 01:36:32.109119 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 01:36:32.115283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 01:36:32.115709 ==
6475 01:36:32.116037
6476 01:36:32.116342
6477 01:36:32.116637 TX Vref Scan disable
6478 01:36:32.119013 == TX Byte 0 ==
6479 01:36:32.121840 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6480 01:36:32.124970 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6481 01:36:32.128834 == TX Byte 1 ==
6482 01:36:32.132239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6483 01:36:32.135598 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6484 01:36:32.136020
6485 01:36:32.138164 [DATLAT]
6486 01:36:32.138584 Freq=400, CH0 RK1
6487 01:36:32.138917
6488 01:36:32.141726 DATLAT Default: 0xe
6489 01:36:32.142242 0, 0xFFFF, sum = 0
6490 01:36:32.145175 1, 0xFFFF, sum = 0
6491 01:36:32.145760 2, 0xFFFF, sum = 0
6492 01:36:32.148219 3, 0xFFFF, sum = 0
6493 01:36:32.148753 4, 0xFFFF, sum = 0
6494 01:36:32.151660 5, 0xFFFF, sum = 0
6495 01:36:32.152181 6, 0xFFFF, sum = 0
6496 01:36:32.155036 7, 0xFFFF, sum = 0
6497 01:36:32.155555 8, 0xFFFF, sum = 0
6498 01:36:32.158767 9, 0xFFFF, sum = 0
6499 01:36:32.161993 10, 0xFFFF, sum = 0
6500 01:36:32.162422 11, 0xFFFF, sum = 0
6501 01:36:32.164642 12, 0xFFFF, sum = 0
6502 01:36:32.165070 13, 0x0, sum = 1
6503 01:36:32.168369 14, 0x0, sum = 2
6504 01:36:32.168889 15, 0x0, sum = 3
6505 01:36:32.171501 16, 0x0, sum = 4
6506 01:36:32.171929 best_step = 14
6507 01:36:32.172264
6508 01:36:32.172573 ==
6509 01:36:32.174562 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 01:36:32.178239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 01:36:32.178757 ==
6512 01:36:32.181829 RX Vref Scan: 0
6513 01:36:32.182348
6514 01:36:32.185055 RX Vref 0 -> 0, step: 1
6515 01:36:32.185523
6516 01:36:32.185861 RX Delay -359 -> 252, step: 8
6517 01:36:32.193421 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6518 01:36:32.196714 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6519 01:36:32.199975 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6520 01:36:32.206309 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6521 01:36:32.209625 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6522 01:36:32.213084 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6523 01:36:32.216899 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6524 01:36:32.222803 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6525 01:36:32.225947 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6526 01:36:32.230210 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6527 01:36:32.232869 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6528 01:36:32.239502 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6529 01:36:32.242770 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6530 01:36:32.245711 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6531 01:36:32.252427 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6532 01:36:32.255880 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6533 01:36:32.256438 ==
6534 01:36:32.258936 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 01:36:32.262567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 01:36:32.263036 ==
6537 01:36:32.265580 DQS Delay:
6538 01:36:32.266040 DQS0 = 44, DQS1 = 60
6539 01:36:32.266404 DQM Delay:
6540 01:36:32.269173 DQM0 = 9, DQM1 = 14
6541 01:36:32.269766 DQ Delay:
6542 01:36:32.272868 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6543 01:36:32.275660 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6544 01:36:32.279219 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6545 01:36:32.282167 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6546 01:36:32.282637
6547 01:36:32.283001
6548 01:36:32.291990 [DQSOSCAuto] RK1, (LSB)MR18= 0x8782, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6549 01:36:32.292569 CH0 RK1: MR19=C0C, MR18=8782
6550 01:36:32.298427 CH0_RK1: MR19=0xC0C, MR18=0x8782, DQSOSC=392, MR23=63, INC=384, DEC=256
6551 01:36:32.301783 [RxdqsGatingPostProcess] freq 400
6552 01:36:32.308762 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6553 01:36:32.311794 best DQS0 dly(2T, 0.5T) = (0, 10)
6554 01:36:32.314884 best DQS1 dly(2T, 0.5T) = (0, 10)
6555 01:36:32.318263 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6556 01:36:32.321890 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6557 01:36:32.324708 best DQS0 dly(2T, 0.5T) = (0, 10)
6558 01:36:32.325166 best DQS1 dly(2T, 0.5T) = (0, 10)
6559 01:36:32.328418 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6560 01:36:32.331713 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6561 01:36:32.334978 Pre-setting of DQS Precalculation
6562 01:36:32.341132 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6563 01:36:32.341792 ==
6564 01:36:32.345986 Dram Type= 6, Freq= 0, CH_1, rank 0
6565 01:36:32.347837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 01:36:32.348237 ==
6567 01:36:32.354558 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6568 01:36:32.361028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6569 01:36:32.364221 [CA 0] Center 36 (8~64) winsize 57
6570 01:36:32.367587 [CA 1] Center 36 (8~64) winsize 57
6571 01:36:32.370723 [CA 2] Center 36 (8~64) winsize 57
6572 01:36:32.374262 [CA 3] Center 36 (8~64) winsize 57
6573 01:36:32.374490 [CA 4] Center 36 (8~64) winsize 57
6574 01:36:32.377677 [CA 5] Center 36 (8~64) winsize 57
6575 01:36:32.377905
6576 01:36:32.383725 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6577 01:36:32.383952
6578 01:36:32.387775 [CATrainingPosCal] consider 1 rank data
6579 01:36:32.390303 u2DelayCellTimex100 = 270/100 ps
6580 01:36:32.393607 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6581 01:36:32.397358 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6582 01:36:32.400168 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 01:36:32.403316 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 01:36:32.407141 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 01:36:32.410317 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 01:36:32.410741
6587 01:36:32.413234 CA PerBit enable=1, Macro0, CA PI delay=36
6588 01:36:32.417326
6589 01:36:32.417742 [CBTSetCACLKResult] CA Dly = 36
6590 01:36:32.420324 CS Dly: 1 (0~32)
6591 01:36:32.420741 ==
6592 01:36:32.423176 Dram Type= 6, Freq= 0, CH_1, rank 1
6593 01:36:32.426789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 01:36:32.427327 ==
6595 01:36:32.433321 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 01:36:32.439695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6597 01:36:32.443479 [CA 0] Center 36 (8~64) winsize 57
6598 01:36:32.446464 [CA 1] Center 36 (8~64) winsize 57
6599 01:36:32.450094 [CA 2] Center 36 (8~64) winsize 57
6600 01:36:32.450538 [CA 3] Center 36 (8~64) winsize 57
6601 01:36:32.453328 [CA 4] Center 36 (8~64) winsize 57
6602 01:36:32.456314 [CA 5] Center 36 (8~64) winsize 57
6603 01:36:32.456741
6604 01:36:32.463045 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6605 01:36:32.463518
6606 01:36:32.466402 [CATrainingPosCal] consider 2 rank data
6607 01:36:32.469448 u2DelayCellTimex100 = 270/100 ps
6608 01:36:32.472700 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 01:36:32.476204 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 01:36:32.479675 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 01:36:32.483045 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 01:36:32.486506 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 01:36:32.489345 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 01:36:32.489775
6615 01:36:32.492772 CA PerBit enable=1, Macro0, CA PI delay=36
6616 01:36:32.493199
6617 01:36:32.495963 [CBTSetCACLKResult] CA Dly = 36
6618 01:36:32.499249 CS Dly: 1 (0~32)
6619 01:36:32.499730
6620 01:36:32.502667 ----->DramcWriteLeveling(PI) begin...
6621 01:36:32.503133 ==
6622 01:36:32.506101 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 01:36:32.509591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 01:36:32.510116 ==
6625 01:36:32.512493 Write leveling (Byte 0): 40 => 8
6626 01:36:32.515679 Write leveling (Byte 1): 40 => 8
6627 01:36:32.519138 DramcWriteLeveling(PI) end<-----
6628 01:36:32.519561
6629 01:36:32.519894 ==
6630 01:36:32.522311 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 01:36:32.526005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 01:36:32.526628 ==
6633 01:36:32.529099 [Gating] SW mode calibration
6634 01:36:32.535774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6635 01:36:32.542324 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6636 01:36:32.545774 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6637 01:36:32.552399 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6638 01:36:32.555712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6639 01:36:32.558943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6640 01:36:32.566116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6641 01:36:32.568453 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6642 01:36:32.572291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 01:36:32.579012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 01:36:32.581998 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 01:36:32.584831 Total UI for P1: 0, mck2ui 16
6646 01:36:32.588750 best dqsien dly found for B0: ( 0, 14, 24)
6647 01:36:32.592201 Total UI for P1: 0, mck2ui 16
6648 01:36:32.595025 best dqsien dly found for B1: ( 0, 14, 24)
6649 01:36:32.598289 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6650 01:36:32.601974 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6651 01:36:32.602531
6652 01:36:32.605304 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6653 01:36:32.608516 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6654 01:36:32.611772 [Gating] SW calibration Done
6655 01:36:32.612332 ==
6656 01:36:32.615071 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 01:36:32.618684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 01:36:32.621480 ==
6659 01:36:32.622038 RX Vref Scan: 0
6660 01:36:32.622405
6661 01:36:32.624436 RX Vref 0 -> 0, step: 1
6662 01:36:32.624942
6663 01:36:32.628010 RX Delay -410 -> 252, step: 16
6664 01:36:32.631035 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6665 01:36:32.634405 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6666 01:36:32.640844 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6667 01:36:32.643971 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6668 01:36:32.647634 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6669 01:36:32.650933 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6670 01:36:32.657238 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6671 01:36:32.660253 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6672 01:36:32.664130 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6673 01:36:32.667273 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6674 01:36:32.674033 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6675 01:36:32.677243 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6676 01:36:32.680429 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6677 01:36:32.683692 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6678 01:36:32.690955 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6679 01:36:32.693730 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6680 01:36:32.694155 ==
6681 01:36:32.696785 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 01:36:32.700186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 01:36:32.700610 ==
6684 01:36:32.703829 DQS Delay:
6685 01:36:32.704346 DQS0 = 35, DQS1 = 51
6686 01:36:32.706787 DQM Delay:
6687 01:36:32.707302 DQM0 = 6, DQM1 = 13
6688 01:36:32.707634 DQ Delay:
6689 01:36:32.710513 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6690 01:36:32.712999 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6691 01:36:32.716642 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6692 01:36:32.719524 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6693 01:36:32.719946
6694 01:36:32.720281
6695 01:36:32.720591 ==
6696 01:36:32.723201 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 01:36:32.729595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 01:36:32.730026 ==
6699 01:36:32.730356
6700 01:36:32.730664
6701 01:36:32.730965 TX Vref Scan disable
6702 01:36:32.733025 == TX Byte 0 ==
6703 01:36:32.736610 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6704 01:36:32.739776 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6705 01:36:32.743339 == TX Byte 1 ==
6706 01:36:32.746104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6707 01:36:32.749907 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6708 01:36:32.752853 ==
6709 01:36:32.755884 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 01:36:32.758964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 01:36:32.759393 ==
6712 01:36:32.759727
6713 01:36:32.760036
6714 01:36:32.762599 TX Vref Scan disable
6715 01:36:32.763043 == TX Byte 0 ==
6716 01:36:32.765646 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6717 01:36:32.772512 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6718 01:36:32.772940 == TX Byte 1 ==
6719 01:36:32.775778 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 01:36:32.781985 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 01:36:32.782411
6722 01:36:32.782744 [DATLAT]
6723 01:36:32.783055 Freq=400, CH1 RK0
6724 01:36:32.785702
6725 01:36:32.786220 DATLAT Default: 0xf
6726 01:36:32.788639 0, 0xFFFF, sum = 0
6727 01:36:32.789072 1, 0xFFFF, sum = 0
6728 01:36:32.791854 2, 0xFFFF, sum = 0
6729 01:36:32.792283 3, 0xFFFF, sum = 0
6730 01:36:32.795143 4, 0xFFFF, sum = 0
6731 01:36:32.795694 5, 0xFFFF, sum = 0
6732 01:36:32.798565 6, 0xFFFF, sum = 0
6733 01:36:32.798995 7, 0xFFFF, sum = 0
6734 01:36:32.801660 8, 0xFFFF, sum = 0
6735 01:36:32.802090 9, 0xFFFF, sum = 0
6736 01:36:32.805359 10, 0xFFFF, sum = 0
6737 01:36:32.805795 11, 0xFFFF, sum = 0
6738 01:36:32.808110 12, 0xFFFF, sum = 0
6739 01:36:32.808811 13, 0x0, sum = 1
6740 01:36:32.811707 14, 0x0, sum = 2
6741 01:36:32.812288 15, 0x0, sum = 3
6742 01:36:32.815155 16, 0x0, sum = 4
6743 01:36:32.815669 best_step = 14
6744 01:36:32.816008
6745 01:36:32.816316 ==
6746 01:36:32.818568 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 01:36:32.825201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 01:36:32.825750 ==
6749 01:36:32.826088 RX Vref Scan: 1
6750 01:36:32.826399
6751 01:36:32.828375 RX Vref 0 -> 0, step: 1
6752 01:36:32.828799
6753 01:36:32.831312 RX Delay -343 -> 252, step: 8
6754 01:36:32.831735
6755 01:36:32.835140 Set Vref, RX VrefLevel [Byte0]: 53
6756 01:36:32.838126 [Byte1]: 54
6757 01:36:32.841449
6758 01:36:32.841869 Final RX Vref Byte 0 = 53 to rank0
6759 01:36:32.844980 Final RX Vref Byte 1 = 54 to rank0
6760 01:36:32.847865 Final RX Vref Byte 0 = 53 to rank1
6761 01:36:32.851297 Final RX Vref Byte 1 = 54 to rank1==
6762 01:36:32.855076 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 01:36:32.860912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 01:36:32.861382 ==
6765 01:36:32.861724 DQS Delay:
6766 01:36:32.864665 DQS0 = 44, DQS1 = 52
6767 01:36:32.865089 DQM Delay:
6768 01:36:32.865464 DQM0 = 11, DQM1 = 10
6769 01:36:32.867621 DQ Delay:
6770 01:36:32.871042 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6771 01:36:32.874657 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6772 01:36:32.875080 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6773 01:36:32.880718 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6774 01:36:32.881241
6775 01:36:32.881629
6776 01:36:32.888020 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6777 01:36:32.890885 CH1 RK0: MR19=C0C, MR18=6A91
6778 01:36:32.897366 CH1_RK0: MR19=0xC0C, MR18=0x6A91, DQSOSC=391, MR23=63, INC=386, DEC=257
6779 01:36:32.897890 ==
6780 01:36:32.901418 Dram Type= 6, Freq= 0, CH_1, rank 1
6781 01:36:32.903922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 01:36:32.904493 ==
6783 01:36:32.908369 [Gating] SW mode calibration
6784 01:36:32.913651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6785 01:36:32.920736 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6786 01:36:32.923606 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6787 01:36:32.927465 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 01:36:32.933486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6789 01:36:32.936811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 01:36:32.940411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6791 01:36:32.946463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 01:36:32.950150 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 01:36:32.953151 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 01:36:32.960477 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6795 01:36:32.962911 Total UI for P1: 0, mck2ui 16
6796 01:36:32.966917 best dqsien dly found for B0: ( 0, 14, 24)
6797 01:36:32.969626 Total UI for P1: 0, mck2ui 16
6798 01:36:32.973417 best dqsien dly found for B1: ( 0, 14, 24)
6799 01:36:32.976494 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6800 01:36:32.979786 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6801 01:36:32.980343
6802 01:36:32.982913 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6803 01:36:32.986897 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 01:36:32.989425 [Gating] SW calibration Done
6805 01:36:32.989980 ==
6806 01:36:32.993204 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 01:36:32.996579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 01:36:32.997142 ==
6809 01:36:32.999379 RX Vref Scan: 0
6810 01:36:32.999847
6811 01:36:33.003605 RX Vref 0 -> 0, step: 1
6812 01:36:33.004154
6813 01:36:33.004522 RX Delay -410 -> 252, step: 16
6814 01:36:33.009392 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6815 01:36:33.012869 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6816 01:36:33.016507 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6817 01:36:33.019836 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6818 01:36:33.025981 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6819 01:36:33.029080 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6820 01:36:33.032494 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6821 01:36:33.039107 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6822 01:36:33.042466 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6823 01:36:33.045863 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6824 01:36:33.049419 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6825 01:36:33.055786 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6826 01:36:33.059200 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6827 01:36:33.062260 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6828 01:36:33.065733 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6829 01:36:33.072137 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6830 01:36:33.072685 ==
6831 01:36:33.075607 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 01:36:33.078905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 01:36:33.079472 ==
6834 01:36:33.079845 DQS Delay:
6835 01:36:33.081819 DQS0 = 43, DQS1 = 51
6836 01:36:33.082292 DQM Delay:
6837 01:36:33.085245 DQM0 = 9, DQM1 = 13
6838 01:36:33.085837 DQ Delay:
6839 01:36:33.088600 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6840 01:36:33.091859 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6841 01:36:33.095402 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6842 01:36:33.098108 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6843 01:36:33.098578
6844 01:36:33.098941
6845 01:36:33.099279 ==
6846 01:36:33.102196 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 01:36:33.105469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 01:36:33.105948 ==
6849 01:36:33.108722
6850 01:36:33.109308
6851 01:36:33.109690 TX Vref Scan disable
6852 01:36:33.111725 == TX Byte 0 ==
6853 01:36:33.115482 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 01:36:33.118213 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 01:36:33.121789 == TX Byte 1 ==
6856 01:36:33.125108 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6857 01:36:33.128494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6858 01:36:33.128977 ==
6859 01:36:33.131189 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 01:36:33.134460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 01:36:33.137939 ==
6862 01:36:33.138410
6863 01:36:33.138773
6864 01:36:33.139109 TX Vref Scan disable
6865 01:36:33.141201 == TX Byte 0 ==
6866 01:36:33.145216 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6867 01:36:33.148062 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6868 01:36:33.150866 == TX Byte 1 ==
6869 01:36:33.154526 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6870 01:36:33.157576 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6871 01:36:33.158003
6872 01:36:33.161067 [DATLAT]
6873 01:36:33.161684 Freq=400, CH1 RK1
6874 01:36:33.162057
6875 01:36:33.164196 DATLAT Default: 0xe
6876 01:36:33.164679 0, 0xFFFF, sum = 0
6877 01:36:33.167676 1, 0xFFFF, sum = 0
6878 01:36:33.168110 2, 0xFFFF, sum = 0
6879 01:36:33.170678 3, 0xFFFF, sum = 0
6880 01:36:33.171108 4, 0xFFFF, sum = 0
6881 01:36:33.173786 5, 0xFFFF, sum = 0
6882 01:36:33.174219 6, 0xFFFF, sum = 0
6883 01:36:33.177405 7, 0xFFFF, sum = 0
6884 01:36:33.177944 8, 0xFFFF, sum = 0
6885 01:36:33.180732 9, 0xFFFF, sum = 0
6886 01:36:33.181249 10, 0xFFFF, sum = 0
6887 01:36:33.184529 11, 0xFFFF, sum = 0
6888 01:36:33.187230 12, 0xFFFF, sum = 0
6889 01:36:33.187661 13, 0x0, sum = 1
6890 01:36:33.191136 14, 0x0, sum = 2
6891 01:36:33.191655 15, 0x0, sum = 3
6892 01:36:33.191997 16, 0x0, sum = 4
6893 01:36:33.193680 best_step = 14
6894 01:36:33.194107
6895 01:36:33.194442 ==
6896 01:36:33.197216 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 01:36:33.200324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 01:36:33.200760 ==
6899 01:36:33.204264 RX Vref Scan: 0
6900 01:36:33.204778
6901 01:36:33.206820 RX Vref 0 -> 0, step: 1
6902 01:36:33.207246
6903 01:36:33.207579 RX Delay -343 -> 252, step: 8
6904 01:36:33.215596 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6905 01:36:33.218740 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6906 01:36:33.222152 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6907 01:36:33.228706 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6908 01:36:33.232081 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6909 01:36:33.235939 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6910 01:36:33.238376 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6911 01:36:33.245121 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6912 01:36:33.248766 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6913 01:36:33.251547 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6914 01:36:33.255319 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6915 01:36:33.261506 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6916 01:36:33.264986 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6917 01:36:33.268415 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6918 01:36:33.272273 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6919 01:36:33.278346 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6920 01:36:33.278863 ==
6921 01:36:33.281408 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 01:36:33.285020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 01:36:33.285569 ==
6924 01:36:33.288056 DQS Delay:
6925 01:36:33.288569 DQS0 = 44, DQS1 = 52
6926 01:36:33.288906 DQM Delay:
6927 01:36:33.291163 DQM0 = 7, DQM1 = 9
6928 01:36:33.291675 DQ Delay:
6929 01:36:33.294119 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =4
6930 01:36:33.298531 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6931 01:36:33.300791 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6932 01:36:33.304397 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6933 01:36:33.304916
6934 01:36:33.305287
6935 01:36:33.314065 [DQSOSCAuto] RK1, (LSB)MR18= 0x70a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6936 01:36:33.314613 CH1 RK1: MR19=C0C, MR18=70A9
6937 01:36:33.320985 CH1_RK1: MR19=0xC0C, MR18=0x70A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6938 01:36:33.324003 [RxdqsGatingPostProcess] freq 400
6939 01:36:33.330473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6940 01:36:33.334410 best DQS0 dly(2T, 0.5T) = (0, 10)
6941 01:36:33.337297 best DQS1 dly(2T, 0.5T) = (0, 10)
6942 01:36:33.340609 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6943 01:36:33.344122 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6944 01:36:33.347378 best DQS0 dly(2T, 0.5T) = (0, 10)
6945 01:36:33.347891 best DQS1 dly(2T, 0.5T) = (0, 10)
6946 01:36:33.350289 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6947 01:36:33.353715 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6948 01:36:33.357107 Pre-setting of DQS Precalculation
6949 01:36:33.363444 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6950 01:36:33.369904 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6951 01:36:33.376398 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6952 01:36:33.376912
6953 01:36:33.377249
6954 01:36:33.379738 [Calibration Summary] 800 Mbps
6955 01:36:33.383723 CH 0, Rank 0
6956 01:36:33.384234 SW Impedance : PASS
6957 01:36:33.386405 DUTY Scan : NO K
6958 01:36:33.389834 ZQ Calibration : PASS
6959 01:36:33.390345 Jitter Meter : NO K
6960 01:36:33.393005 CBT Training : PASS
6961 01:36:33.396007 Write leveling : PASS
6962 01:36:33.396436 RX DQS gating : PASS
6963 01:36:33.399566 RX DQ/DQS(RDDQC) : PASS
6964 01:36:33.403229 TX DQ/DQS : PASS
6965 01:36:33.403742 RX DATLAT : PASS
6966 01:36:33.406079 RX DQ/DQS(Engine): PASS
6967 01:36:33.409224 TX OE : NO K
6968 01:36:33.409781 All Pass.
6969 01:36:33.410119
6970 01:36:33.410431 CH 0, Rank 1
6971 01:36:33.412353 SW Impedance : PASS
6972 01:36:33.415717 DUTY Scan : NO K
6973 01:36:33.416225 ZQ Calibration : PASS
6974 01:36:33.419416 Jitter Meter : NO K
6975 01:36:33.422267 CBT Training : PASS
6976 01:36:33.422775 Write leveling : NO K
6977 01:36:33.425738 RX DQS gating : PASS
6978 01:36:33.428997 RX DQ/DQS(RDDQC) : PASS
6979 01:36:33.429454 TX DQ/DQS : PASS
6980 01:36:33.432126 RX DATLAT : PASS
6981 01:36:33.432650 RX DQ/DQS(Engine): PASS
6982 01:36:33.435569 TX OE : NO K
6983 01:36:33.435998 All Pass.
6984 01:36:33.436333
6985 01:36:33.438799 CH 1, Rank 0
6986 01:36:33.439225 SW Impedance : PASS
6987 01:36:33.442003 DUTY Scan : NO K
6988 01:36:33.444974 ZQ Calibration : PASS
6989 01:36:33.445435 Jitter Meter : NO K
6990 01:36:33.448366 CBT Training : PASS
6991 01:36:33.451704 Write leveling : PASS
6992 01:36:33.452217 RX DQS gating : PASS
6993 01:36:33.455074 RX DQ/DQS(RDDQC) : PASS
6994 01:36:33.458375 TX DQ/DQS : PASS
6995 01:36:33.458893 RX DATLAT : PASS
6996 01:36:33.461761 RX DQ/DQS(Engine): PASS
6997 01:36:33.465360 TX OE : NO K
6998 01:36:33.465755 All Pass.
6999 01:36:33.466149
7000 01:36:33.466469 CH 1, Rank 1
7001 01:36:33.468353 SW Impedance : PASS
7002 01:36:33.472166 DUTY Scan : NO K
7003 01:36:33.472683 ZQ Calibration : PASS
7004 01:36:33.475149 Jitter Meter : NO K
7005 01:36:33.478259 CBT Training : PASS
7006 01:36:33.478686 Write leveling : NO K
7007 01:36:33.481627 RX DQS gating : PASS
7008 01:36:33.484948 RX DQ/DQS(RDDQC) : PASS
7009 01:36:33.485497 TX DQ/DQS : PASS
7010 01:36:33.488041 RX DATLAT : PASS
7011 01:36:33.491739 RX DQ/DQS(Engine): PASS
7012 01:36:33.492257 TX OE : NO K
7013 01:36:33.495030 All Pass.
7014 01:36:33.495548
7015 01:36:33.495884 DramC Write-DBI off
7016 01:36:33.497926 PER_BANK_REFRESH: Hybrid Mode
7017 01:36:33.498353 TX_TRACKING: ON
7018 01:36:33.508190 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7019 01:36:33.511342 [FAST_K] Save calibration result to emmc
7020 01:36:33.514168 dramc_set_vcore_voltage set vcore to 725000
7021 01:36:33.517992 Read voltage for 1600, 0
7022 01:36:33.518585 Vio18 = 0
7023 01:36:33.521176 Vcore = 725000
7024 01:36:33.521727 Vdram = 0
7025 01:36:33.522064 Vddq = 0
7026 01:36:33.525047 Vmddr = 0
7027 01:36:33.527149 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7028 01:36:33.534385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7029 01:36:33.534890 MEM_TYPE=3, freq_sel=13
7030 01:36:33.537554 sv_algorithm_assistance_LP4_3733
7031 01:36:33.543760 ============ PULL DRAM RESETB DOWN ============
7032 01:36:33.547456 ========== PULL DRAM RESETB DOWN end =========
7033 01:36:33.550836 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7034 01:36:33.553637 ===================================
7035 01:36:33.557432 LPDDR4 DRAM CONFIGURATION
7036 01:36:33.560377 ===================================
7037 01:36:33.563894 EX_ROW_EN[0] = 0x0
7038 01:36:33.564316 EX_ROW_EN[1] = 0x0
7039 01:36:33.567101 LP4Y_EN = 0x0
7040 01:36:33.567529 WORK_FSP = 0x1
7041 01:36:33.570493 WL = 0x5
7042 01:36:33.571012 RL = 0x5
7043 01:36:33.574311 BL = 0x2
7044 01:36:33.574735 RPST = 0x0
7045 01:36:33.577333 RD_PRE = 0x0
7046 01:36:33.577851 WR_PRE = 0x1
7047 01:36:33.580657 WR_PST = 0x1
7048 01:36:33.581174 DBI_WR = 0x0
7049 01:36:33.584343 DBI_RD = 0x0
7050 01:36:33.584854 OTF = 0x1
7051 01:36:33.587532 ===================================
7052 01:36:33.591033 ===================================
7053 01:36:33.593519 ANA top config
7054 01:36:33.597345 ===================================
7055 01:36:33.600405 DLL_ASYNC_EN = 0
7056 01:36:33.600926 ALL_SLAVE_EN = 0
7057 01:36:33.603206 NEW_RANK_MODE = 1
7058 01:36:33.606908 DLL_IDLE_MODE = 1
7059 01:36:33.609983 LP45_APHY_COMB_EN = 1
7060 01:36:33.613639 TX_ODT_DIS = 0
7061 01:36:33.614159 NEW_8X_MODE = 1
7062 01:36:33.616766 ===================================
7063 01:36:33.620092 ===================================
7064 01:36:33.623205 data_rate = 3200
7065 01:36:33.626887 CKR = 1
7066 01:36:33.630220 DQ_P2S_RATIO = 8
7067 01:36:33.633336 ===================================
7068 01:36:33.636307 CA_P2S_RATIO = 8
7069 01:36:33.639542 DQ_CA_OPEN = 0
7070 01:36:33.639970 DQ_SEMI_OPEN = 0
7071 01:36:33.642491 CA_SEMI_OPEN = 0
7072 01:36:33.646243 CA_FULL_RATE = 0
7073 01:36:33.649314 DQ_CKDIV4_EN = 0
7074 01:36:33.652638 CA_CKDIV4_EN = 0
7075 01:36:33.655881 CA_PREDIV_EN = 0
7076 01:36:33.659541 PH8_DLY = 12
7077 01:36:33.660058 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7078 01:36:33.662658 DQ_AAMCK_DIV = 4
7079 01:36:33.665756 CA_AAMCK_DIV = 4
7080 01:36:33.669503 CA_ADMCK_DIV = 4
7081 01:36:33.672685 DQ_TRACK_CA_EN = 0
7082 01:36:33.675975 CA_PICK = 1600
7083 01:36:33.679601 CA_MCKIO = 1600
7084 01:36:33.680029 MCKIO_SEMI = 0
7085 01:36:33.682652 PLL_FREQ = 3068
7086 01:36:33.685396 DQ_UI_PI_RATIO = 32
7087 01:36:33.689145 CA_UI_PI_RATIO = 0
7088 01:36:33.692334 ===================================
7089 01:36:33.695462 ===================================
7090 01:36:33.698970 memory_type:LPDDR4
7091 01:36:33.699540 GP_NUM : 10
7092 01:36:33.701809 SRAM_EN : 1
7093 01:36:33.705764 MD32_EN : 0
7094 01:36:33.709051 ===================================
7095 01:36:33.709661 [ANA_INIT] >>>>>>>>>>>>>>
7096 01:36:33.711970 <<<<<< [CONFIGURE PHASE]: ANA_TX
7097 01:36:33.714937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7098 01:36:33.718607 ===================================
7099 01:36:33.721960 data_rate = 3200,PCW = 0X7600
7100 01:36:33.725370 ===================================
7101 01:36:33.728218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7102 01:36:33.734570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7103 01:36:33.737983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7104 01:36:33.744980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7105 01:36:33.748149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7106 01:36:33.751353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7107 01:36:33.754571 [ANA_INIT] flow start
7108 01:36:33.755035 [ANA_INIT] PLL >>>>>>>>
7109 01:36:33.758768 [ANA_INIT] PLL <<<<<<<<
7110 01:36:33.761255 [ANA_INIT] MIDPI >>>>>>>>
7111 01:36:33.761905 [ANA_INIT] MIDPI <<<<<<<<
7112 01:36:33.764460 [ANA_INIT] DLL >>>>>>>>
7113 01:36:33.767968 [ANA_INIT] DLL <<<<<<<<
7114 01:36:33.768433 [ANA_INIT] flow end
7115 01:36:33.774501 ============ LP4 DIFF to SE enter ============
7116 01:36:33.777669 ============ LP4 DIFF to SE exit ============
7117 01:36:33.781076 [ANA_INIT] <<<<<<<<<<<<<
7118 01:36:33.784414 [Flow] Enable top DCM control >>>>>
7119 01:36:33.787956 [Flow] Enable top DCM control <<<<<
7120 01:36:33.788547 Enable DLL master slave shuffle
7121 01:36:33.793951 ==============================================================
7122 01:36:33.797765 Gating Mode config
7123 01:36:33.800792 ==============================================================
7124 01:36:33.804117 Config description:
7125 01:36:33.813732 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7126 01:36:33.820958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7127 01:36:33.823734 SELPH_MODE 0: By rank 1: By Phase
7128 01:36:33.830678 ==============================================================
7129 01:36:33.833635 GAT_TRACK_EN = 1
7130 01:36:33.836755 RX_GATING_MODE = 2
7131 01:36:33.839971 RX_GATING_TRACK_MODE = 2
7132 01:36:33.844409 SELPH_MODE = 1
7133 01:36:33.846523 PICG_EARLY_EN = 1
7134 01:36:33.846948 VALID_LAT_VALUE = 1
7135 01:36:33.853875 ==============================================================
7136 01:36:33.856702 Enter into Gating configuration >>>>
7137 01:36:33.859896 Exit from Gating configuration <<<<
7138 01:36:33.863289 Enter into DVFS_PRE_config >>>>>
7139 01:36:33.876110 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7140 01:36:33.876680 Exit from DVFS_PRE_config <<<<<
7141 01:36:33.879506 Enter into PICG configuration >>>>
7142 01:36:33.882797 Exit from PICG configuration <<<<
7143 01:36:33.886690 [RX_INPUT] configuration >>>>>
7144 01:36:33.889544 [RX_INPUT] configuration <<<<<
7145 01:36:33.896197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7146 01:36:33.899612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7147 01:36:33.905539 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7148 01:36:33.912096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7149 01:36:33.919241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7150 01:36:33.925537 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7151 01:36:33.928816 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7152 01:36:33.932127 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7153 01:36:33.938512 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7154 01:36:33.941581 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7155 01:36:33.945006 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7156 01:36:33.948597 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7157 01:36:33.951798 ===================================
7158 01:36:33.954866 LPDDR4 DRAM CONFIGURATION
7159 01:36:33.959130 ===================================
7160 01:36:33.962129 EX_ROW_EN[0] = 0x0
7161 01:36:33.962572 EX_ROW_EN[1] = 0x0
7162 01:36:33.964783 LP4Y_EN = 0x0
7163 01:36:33.965207 WORK_FSP = 0x1
7164 01:36:33.968126 WL = 0x5
7165 01:36:33.968590 RL = 0x5
7166 01:36:33.972110 BL = 0x2
7167 01:36:33.972571 RPST = 0x0
7168 01:36:33.974647 RD_PRE = 0x0
7169 01:36:33.977906 WR_PRE = 0x1
7170 01:36:33.978468 WR_PST = 0x1
7171 01:36:33.981293 DBI_WR = 0x0
7172 01:36:33.981723 DBI_RD = 0x0
7173 01:36:33.984435 OTF = 0x1
7174 01:36:33.988187 ===================================
7175 01:36:33.991649 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7176 01:36:33.994327 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7177 01:36:33.997746 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 01:36:34.004844 ===================================
7179 01:36:34.005397 LPDDR4 DRAM CONFIGURATION
7180 01:36:34.007532 ===================================
7181 01:36:34.011413 EX_ROW_EN[0] = 0x10
7182 01:36:34.011953 EX_ROW_EN[1] = 0x0
7183 01:36:34.014052 LP4Y_EN = 0x0
7184 01:36:34.014479 WORK_FSP = 0x1
7185 01:36:34.017604 WL = 0x5
7186 01:36:34.020867 RL = 0x5
7187 01:36:34.021349 BL = 0x2
7188 01:36:34.024361 RPST = 0x0
7189 01:36:34.024887 RD_PRE = 0x0
7190 01:36:34.027677 WR_PRE = 0x1
7191 01:36:34.028206 WR_PST = 0x1
7192 01:36:34.031042 DBI_WR = 0x0
7193 01:36:34.031672 DBI_RD = 0x0
7194 01:36:34.034174 OTF = 0x1
7195 01:36:34.036892 ===================================
7196 01:36:34.043581 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7197 01:36:34.044007 ==
7198 01:36:34.046750 Dram Type= 6, Freq= 0, CH_0, rank 0
7199 01:36:34.050465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7200 01:36:34.050962 ==
7201 01:36:34.053478 [Duty_Offset_Calibration]
7202 01:36:34.053903 B0:2 B1:0 CA:4
7203 01:36:34.054334
7204 01:36:34.057084 [DutyScan_Calibration_Flow] k_type=0
7205 01:36:34.066836
7206 01:36:34.067260 ==CLK 0==
7207 01:36:34.069632 Final CLK duty delay cell = -4
7208 01:36:34.073604 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7209 01:36:34.076274 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7210 01:36:34.079640 [-4] AVG Duty = 4922%(X100)
7211 01:36:34.080067
7212 01:36:34.083205 CH0 CLK Duty spec in!! Max-Min= 218%
7213 01:36:34.086359 [DutyScan_Calibration_Flow] ====Done====
7214 01:36:34.086781
7215 01:36:34.089825 [DutyScan_Calibration_Flow] k_type=1
7216 01:36:34.106669
7217 01:36:34.107103 ==DQS 0 ==
7218 01:36:34.110484 Final DQS duty delay cell = 0
7219 01:36:34.113448 [0] MAX Duty = 5218%(X100), DQS PI = 38
7220 01:36:34.116541 [0] MIN Duty = 5093%(X100), DQS PI = 6
7221 01:36:34.120100 [0] AVG Duty = 5155%(X100)
7222 01:36:34.120537
7223 01:36:34.120889 ==DQS 1 ==
7224 01:36:34.123217 Final DQS duty delay cell = 0
7225 01:36:34.126656 [0] MAX Duty = 5156%(X100), DQS PI = 2
7226 01:36:34.129606 [0] MIN Duty = 4969%(X100), DQS PI = 10
7227 01:36:34.133132 [0] AVG Duty = 5062%(X100)
7228 01:36:34.133592
7229 01:36:34.136509 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7230 01:36:34.136932
7231 01:36:34.140071 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7232 01:36:34.142820 [DutyScan_Calibration_Flow] ====Done====
7233 01:36:34.143247
7234 01:36:34.145856 [DutyScan_Calibration_Flow] k_type=3
7235 01:36:34.164127
7236 01:36:34.164559 ==DQM 0 ==
7237 01:36:34.167196 Final DQM duty delay cell = 0
7238 01:36:34.170368 [0] MAX Duty = 5124%(X100), DQS PI = 22
7239 01:36:34.173696 [0] MIN Duty = 4844%(X100), DQS PI = 58
7240 01:36:34.177418 [0] AVG Duty = 4984%(X100)
7241 01:36:34.177860
7242 01:36:34.178197 ==DQM 1 ==
7243 01:36:34.180755 Final DQM duty delay cell = 0
7244 01:36:34.184167 [0] MAX Duty = 4969%(X100), DQS PI = 2
7245 01:36:34.187350 [0] MIN Duty = 4813%(X100), DQS PI = 16
7246 01:36:34.190695 [0] AVG Duty = 4891%(X100)
7247 01:36:34.191245
7248 01:36:34.193520 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7249 01:36:34.193973
7250 01:36:34.196981 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7251 01:36:34.200096 [DutyScan_Calibration_Flow] ====Done====
7252 01:36:34.200535
7253 01:36:34.203140 [DutyScan_Calibration_Flow] k_type=2
7254 01:36:34.220826
7255 01:36:34.221251 ==DQ 0 ==
7256 01:36:34.224500 Final DQ duty delay cell = 0
7257 01:36:34.228012 [0] MAX Duty = 5156%(X100), DQS PI = 26
7258 01:36:34.230897 [0] MIN Duty = 4938%(X100), DQS PI = 12
7259 01:36:34.233782 [0] AVG Duty = 5047%(X100)
7260 01:36:34.234520
7261 01:36:34.235128 ==DQ 1 ==
7262 01:36:34.237066 Final DQ duty delay cell = 0
7263 01:36:34.240344 [0] MAX Duty = 5187%(X100), DQS PI = 2
7264 01:36:34.243642 [0] MIN Duty = 4938%(X100), DQS PI = 12
7265 01:36:34.247029 [0] AVG Duty = 5062%(X100)
7266 01:36:34.247456
7267 01:36:34.250422 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7268 01:36:34.250848
7269 01:36:34.253359 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7270 01:36:34.257035 [DutyScan_Calibration_Flow] ====Done====
7271 01:36:34.257509 ==
7272 01:36:34.260978 Dram Type= 6, Freq= 0, CH_1, rank 0
7273 01:36:34.263749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7274 01:36:34.264176 ==
7275 01:36:34.266876 [Duty_Offset_Calibration]
7276 01:36:34.267300 B0:0 B1:-1 CA:3
7277 01:36:34.267634
7278 01:36:34.270107 [DutyScan_Calibration_Flow] k_type=0
7279 01:36:34.281419
7280 01:36:34.281931 ==CLK 0==
7281 01:36:34.284538 Final CLK duty delay cell = 0
7282 01:36:34.288483 [0] MAX Duty = 5218%(X100), DQS PI = 34
7283 01:36:34.291416 [0] MIN Duty = 5000%(X100), DQS PI = 6
7284 01:36:34.291842 [0] AVG Duty = 5109%(X100)
7285 01:36:34.294784
7286 01:36:34.297991 CH1 CLK Duty spec in!! Max-Min= 218%
7287 01:36:34.301499 [DutyScan_Calibration_Flow] ====Done====
7288 01:36:34.302032
7289 01:36:34.304606 [DutyScan_Calibration_Flow] k_type=1
7290 01:36:34.320394
7291 01:36:34.320953 ==DQS 0 ==
7292 01:36:34.323880 Final DQS duty delay cell = 0
7293 01:36:34.326852 [0] MAX Duty = 5156%(X100), DQS PI = 0
7294 01:36:34.330197 [0] MIN Duty = 4938%(X100), DQS PI = 8
7295 01:36:34.330663 [0] AVG Duty = 5047%(X100)
7296 01:36:34.333550
7297 01:36:34.333971 ==DQS 1 ==
7298 01:36:34.336558 Final DQS duty delay cell = -4
7299 01:36:34.339602 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7300 01:36:34.342979 [-4] MIN Duty = 4813%(X100), DQS PI = 52
7301 01:36:34.346666 [-4] AVG Duty = 4922%(X100)
7302 01:36:34.347092
7303 01:36:34.349711 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7304 01:36:34.350138
7305 01:36:34.353287 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7306 01:36:34.355973 [DutyScan_Calibration_Flow] ====Done====
7307 01:36:34.356398
7308 01:36:34.359807 [DutyScan_Calibration_Flow] k_type=3
7309 01:36:34.377397
7310 01:36:34.377881 ==DQM 0 ==
7311 01:36:34.380739 Final DQM duty delay cell = 0
7312 01:36:34.384010 [0] MAX Duty = 5031%(X100), DQS PI = 38
7313 01:36:34.386948 [0] MIN Duty = 4782%(X100), DQS PI = 6
7314 01:36:34.390755 [0] AVG Duty = 4906%(X100)
7315 01:36:34.391269
7316 01:36:34.391604 ==DQM 1 ==
7317 01:36:34.393884 Final DQM duty delay cell = 0
7318 01:36:34.396793 [0] MAX Duty = 4969%(X100), DQS PI = 0
7319 01:36:34.400464 [0] MIN Duty = 4813%(X100), DQS PI = 30
7320 01:36:34.403517 [0] AVG Duty = 4891%(X100)
7321 01:36:34.403938
7322 01:36:34.407352 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7323 01:36:34.407869
7324 01:36:34.410016 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7325 01:36:34.413739 [DutyScan_Calibration_Flow] ====Done====
7326 01:36:34.414226
7327 01:36:34.416270 [DutyScan_Calibration_Flow] k_type=2
7328 01:36:34.434468
7329 01:36:34.434989 ==DQ 0 ==
7330 01:36:34.437012 Final DQ duty delay cell = 0
7331 01:36:34.440510 [0] MAX Duty = 5187%(X100), DQS PI = 0
7332 01:36:34.444089 [0] MIN Duty = 5031%(X100), DQS PI = 6
7333 01:36:34.444608 [0] AVG Duty = 5109%(X100)
7334 01:36:34.444943
7335 01:36:34.447197 ==DQ 1 ==
7336 01:36:34.450241 Final DQ duty delay cell = 0
7337 01:36:34.453788 [0] MAX Duty = 5031%(X100), DQS PI = 0
7338 01:36:34.456785 [0] MIN Duty = 4844%(X100), DQS PI = 28
7339 01:36:34.457206 [0] AVG Duty = 4937%(X100)
7340 01:36:34.457587
7341 01:36:34.464471 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7342 01:36:34.464993
7343 01:36:34.467171 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7344 01:36:34.470463 [DutyScan_Calibration_Flow] ====Done====
7345 01:36:34.473438 nWR fixed to 30
7346 01:36:34.473968 [ModeRegInit_LP4] CH0 RK0
7347 01:36:34.477365 [ModeRegInit_LP4] CH0 RK1
7348 01:36:34.480429 [ModeRegInit_LP4] CH1 RK0
7349 01:36:34.483269 [ModeRegInit_LP4] CH1 RK1
7350 01:36:34.483824 match AC timing 5
7351 01:36:34.490045 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7352 01:36:34.493812 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7353 01:36:34.496733 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7354 01:36:34.503045 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7355 01:36:34.506608 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7356 01:36:34.507138 [MiockJmeterHQA]
7357 01:36:34.507520
7358 01:36:34.509651 [DramcMiockJmeter] u1RxGatingPI = 0
7359 01:36:34.513031 0 : 4364, 4137
7360 01:36:34.513551 4 : 4252, 4027
7361 01:36:34.516501 8 : 4363, 4137
7362 01:36:34.517086 12 : 4257, 4029
7363 01:36:34.517528 16 : 4258, 4029
7364 01:36:34.519604 20 : 4363, 4138
7365 01:36:34.520036 24 : 4361, 4138
7366 01:36:34.522901 28 : 4252, 4026
7367 01:36:34.523333 32 : 4250, 4027
7368 01:36:34.526118 36 : 4253, 4027
7369 01:36:34.526784 40 : 4360, 4137
7370 01:36:34.529413 44 : 4252, 4030
7371 01:36:34.529858 48 : 4361, 4138
7372 01:36:34.530197 52 : 4253, 4027
7373 01:36:34.532490 56 : 4250, 4026
7374 01:36:34.533049 60 : 4250, 4027
7375 01:36:34.536352 64 : 4250, 4027
7376 01:36:34.536786 68 : 4361, 4137
7377 01:36:34.539383 72 : 4250, 4027
7378 01:36:34.539874 76 : 4361, 4137
7379 01:36:34.542516 80 : 4250, 4027
7380 01:36:34.542948 84 : 4250, 4027
7381 01:36:34.546393 88 : 4250, 4027
7382 01:36:34.546918 92 : 4360, 4137
7383 01:36:34.547261 96 : 4250, 2592
7384 01:36:34.549321 100 : 4361, 0
7385 01:36:34.549847 104 : 4360, 0
7386 01:36:34.552702 108 : 4250, 0
7387 01:36:34.553136 112 : 4250, 0
7388 01:36:34.553521 116 : 4250, 0
7389 01:36:34.556441 120 : 4250, 0
7390 01:36:34.556872 124 : 4250, 0
7391 01:36:34.559182 128 : 4250, 0
7392 01:36:34.559706 132 : 4250, 0
7393 01:36:34.560048 136 : 4360, 0
7394 01:36:34.562052 140 : 4361, 0
7395 01:36:34.562486 144 : 4248, 0
7396 01:36:34.565659 148 : 4361, 0
7397 01:36:34.566090 152 : 4361, 0
7398 01:36:34.566429 156 : 4361, 0
7399 01:36:34.568881 160 : 4250, 0
7400 01:36:34.569338 164 : 4250, 0
7401 01:36:34.569686 168 : 4250, 0
7402 01:36:34.572410 172 : 4250, 0
7403 01:36:34.572840 176 : 4250, 0
7404 01:36:34.575732 180 : 4250, 0
7405 01:36:34.576163 184 : 4253, 0
7406 01:36:34.576501 188 : 4250, 0
7407 01:36:34.578975 192 : 4361, 0
7408 01:36:34.579405 196 : 4250, 0
7409 01:36:34.581900 200 : 4361, 0
7410 01:36:34.582327 204 : 4361, 0
7411 01:36:34.582664 208 : 4363, 0
7412 01:36:34.585421 212 : 4250, 0
7413 01:36:34.585851 216 : 4250, 0
7414 01:36:34.588495 220 : 4250, 742
7415 01:36:34.588924 224 : 4250, 4015
7416 01:36:34.592129 228 : 4250, 4027
7417 01:36:34.592559 232 : 4252, 4029
7418 01:36:34.595798 236 : 4250, 4027
7419 01:36:34.596331 240 : 4250, 4027
7420 01:36:34.596675 244 : 4250, 4026
7421 01:36:34.598620 248 : 4250, 4027
7422 01:36:34.599051 252 : 4250, 4026
7423 01:36:34.601690 256 : 4361, 4137
7424 01:36:34.602123 260 : 4360, 4137
7425 01:36:34.605176 264 : 4247, 4024
7426 01:36:34.605652 268 : 4360, 4137
7427 01:36:34.608468 272 : 4361, 4138
7428 01:36:34.608899 276 : 4250, 4027
7429 01:36:34.611594 280 : 4250, 4026
7430 01:36:34.612047 284 : 4250, 4027
7431 01:36:34.615108 288 : 4250, 4027
7432 01:36:34.615538 292 : 4250, 4027
7433 01:36:34.618140 296 : 4250, 4026
7434 01:36:34.618569 300 : 4250, 4027
7435 01:36:34.622132 304 : 4250, 4027
7436 01:36:34.622627 308 : 4361, 4137
7437 01:36:34.622968 312 : 4360, 4137
7438 01:36:34.624857 316 : 4248, 4024
7439 01:36:34.625368 320 : 4361, 4137
7440 01:36:34.627954 324 : 4361, 4137
7441 01:36:34.628501 328 : 4250, 4027
7442 01:36:34.631456 332 : 4250, 3846
7443 01:36:34.631984 336 : 4250, 1582
7444 01:36:34.632326
7445 01:36:34.634777 MIOCK jitter meter ch=0
7446 01:36:34.635272
7447 01:36:34.637768 1T = (336-100) = 236 dly cells
7448 01:36:34.644997 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7449 01:36:34.645569 ==
7450 01:36:34.647802 Dram Type= 6, Freq= 0, CH_0, rank 0
7451 01:36:34.651246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7452 01:36:34.651672 ==
7453 01:36:34.657856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7454 01:36:34.660964 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7455 01:36:34.664318 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7456 01:36:34.670962 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7457 01:36:34.680353 [CA 0] Center 44 (14~74) winsize 61
7458 01:36:34.683257 [CA 1] Center 43 (13~74) winsize 62
7459 01:36:34.687067 [CA 2] Center 39 (10~68) winsize 59
7460 01:36:34.689967 [CA 3] Center 38 (9~68) winsize 60
7461 01:36:34.693080 [CA 4] Center 36 (7~66) winsize 60
7462 01:36:34.696966 [CA 5] Center 36 (6~66) winsize 61
7463 01:36:34.697621
7464 01:36:34.700230 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7465 01:36:34.700909
7466 01:36:34.706150 [CATrainingPosCal] consider 1 rank data
7467 01:36:34.706582 u2DelayCellTimex100 = 275/100 ps
7468 01:36:34.713054 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7469 01:36:34.716458 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7470 01:36:34.719601 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7471 01:36:34.722977 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7472 01:36:34.725814 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7473 01:36:34.729361 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7474 01:36:34.729793
7475 01:36:34.732719 CA PerBit enable=1, Macro0, CA PI delay=36
7476 01:36:34.733145
7477 01:36:34.736210 [CBTSetCACLKResult] CA Dly = 36
7478 01:36:34.739322 CS Dly: 10 (0~41)
7479 01:36:34.742337 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7480 01:36:34.746258 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7481 01:36:34.746681 ==
7482 01:36:34.749048 Dram Type= 6, Freq= 0, CH_0, rank 1
7483 01:36:34.756326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7484 01:36:34.756861 ==
7485 01:36:34.759122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7486 01:36:34.766037 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7487 01:36:34.769292 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7488 01:36:34.775696 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7489 01:36:34.783765 [CA 0] Center 43 (13~74) winsize 62
7490 01:36:34.787015 [CA 1] Center 43 (13~74) winsize 62
7491 01:36:34.790384 [CA 2] Center 38 (9~68) winsize 60
7492 01:36:34.793499 [CA 3] Center 38 (9~68) winsize 60
7493 01:36:34.796931 [CA 4] Center 36 (6~67) winsize 62
7494 01:36:34.800312 [CA 5] Center 36 (6~66) winsize 61
7495 01:36:34.800738
7496 01:36:34.803229 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7497 01:36:34.803770
7498 01:36:34.809885 [CATrainingPosCal] consider 2 rank data
7499 01:36:34.810519 u2DelayCellTimex100 = 275/100 ps
7500 01:36:34.816647 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7501 01:36:34.820304 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7502 01:36:34.822937 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7503 01:36:34.826696 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7504 01:36:34.830002 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7505 01:36:34.832998 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7506 01:36:34.833726
7507 01:36:34.836384 CA PerBit enable=1, Macro0, CA PI delay=36
7508 01:36:34.836807
7509 01:36:34.839747 [CBTSetCACLKResult] CA Dly = 36
7510 01:36:34.842749 CS Dly: 11 (0~43)
7511 01:36:34.846199 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7512 01:36:34.849349 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7513 01:36:34.849778
7514 01:36:34.852809 ----->DramcWriteLeveling(PI) begin...
7515 01:36:34.855991 ==
7516 01:36:34.856415 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 01:36:34.862830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 01:36:34.863257 ==
7519 01:36:34.865753 Write leveling (Byte 0): 35 => 35
7520 01:36:34.869096 Write leveling (Byte 1): 22 => 22
7521 01:36:34.872895 DramcWriteLeveling(PI) end<-----
7522 01:36:34.873368
7523 01:36:34.873713 ==
7524 01:36:34.876052 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 01:36:34.879032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 01:36:34.879459 ==
7527 01:36:34.882455 [Gating] SW mode calibration
7528 01:36:34.889042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7529 01:36:34.895560 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7530 01:36:34.898981 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7531 01:36:34.902212 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7532 01:36:34.908986 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7533 01:36:34.912120 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7534 01:36:34.915444 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7535 01:36:34.922309 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7536 01:36:34.925363 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7537 01:36:34.928821 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7538 01:36:34.934991 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 01:36:34.938323 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 01:36:34.941495 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
7541 01:36:34.948825 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7542 01:36:34.951498 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7543 01:36:34.954817 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
7544 01:36:34.961826 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 01:36:34.965011 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 01:36:34.968088 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 01:36:34.974470 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 01:36:34.978046 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7549 01:36:34.981091 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7550 01:36:34.987971 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7551 01:36:34.991038 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7552 01:36:34.994468 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7553 01:36:35.001244 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7554 01:36:35.004121 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 01:36:35.007475 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 01:36:35.014012 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 01:36:35.017359 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7558 01:36:35.021369 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7559 01:36:35.027301 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7560 01:36:35.030581 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7561 01:36:35.034568 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7562 01:36:35.040426 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 01:36:35.043623 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 01:36:35.047074 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 01:36:35.053435 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 01:36:35.057164 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 01:36:35.060114 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 01:36:35.066950 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 01:36:35.070201 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 01:36:35.073449 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 01:36:35.080261 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 01:36:35.083403 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7573 01:36:35.087129 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7574 01:36:35.089749 Total UI for P1: 0, mck2ui 16
7575 01:36:35.093721 best dqsien dly found for B0: ( 1, 9, 8)
7576 01:36:35.099990 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7577 01:36:35.102974 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7578 01:36:35.106719 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7579 01:36:35.112923 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 01:36:35.113387 Total UI for P1: 0, mck2ui 16
7581 01:36:35.119749 best dqsien dly found for B1: ( 1, 9, 22)
7582 01:36:35.122655 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7583 01:36:35.126146 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7584 01:36:35.126666
7585 01:36:35.129520 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7586 01:36:35.133314 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7587 01:36:35.136157 [Gating] SW calibration Done
7588 01:36:35.136599 ==
7589 01:36:35.139558 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 01:36:35.142522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 01:36:35.142949 ==
7592 01:36:35.145713 RX Vref Scan: 0
7593 01:36:35.146134
7594 01:36:35.146463 RX Vref 0 -> 0, step: 1
7595 01:36:35.146771
7596 01:36:35.149208 RX Delay 0 -> 252, step: 8
7597 01:36:35.152419 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7598 01:36:35.159218 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7599 01:36:35.162255 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7600 01:36:35.165516 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7601 01:36:35.168897 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7602 01:36:35.172414 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7603 01:36:35.178641 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7604 01:36:35.182041 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7605 01:36:35.185853 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7606 01:36:35.188875 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7607 01:36:35.192175 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7608 01:36:35.198391 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7609 01:36:35.201722 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7610 01:36:35.204976 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7611 01:36:35.208496 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7612 01:36:35.214756 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7613 01:36:35.215245 ==
7614 01:36:35.218204 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 01:36:35.221364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 01:36:35.221812 ==
7617 01:36:35.222149 DQS Delay:
7618 01:36:35.224940 DQS0 = 0, DQS1 = 0
7619 01:36:35.225473 DQM Delay:
7620 01:36:35.227978 DQM0 = 132, DQM1 = 126
7621 01:36:35.228403 DQ Delay:
7622 01:36:35.231843 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7623 01:36:35.234627 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7624 01:36:35.237717 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7625 01:36:35.244364 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7626 01:36:35.244791
7627 01:36:35.245125
7628 01:36:35.245469 ==
7629 01:36:35.247548 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 01:36:35.251146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 01:36:35.251574 ==
7632 01:36:35.251994
7633 01:36:35.252573
7634 01:36:35.254352 TX Vref Scan disable
7635 01:36:35.254774 == TX Byte 0 ==
7636 01:36:35.261565 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7637 01:36:35.264161 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7638 01:36:35.264716 == TX Byte 1 ==
7639 01:36:35.270997 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7640 01:36:35.274124 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7641 01:36:35.274563 ==
7642 01:36:35.277492 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 01:36:35.280621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 01:36:35.281057 ==
7645 01:36:35.297362
7646 01:36:35.300622 TX Vref early break, caculate TX vref
7647 01:36:35.303833 TX Vref=16, minBit 4, minWin=22, winSum=367
7648 01:36:35.307026 TX Vref=18, minBit 6, minWin=22, winSum=377
7649 01:36:35.310354 TX Vref=20, minBit 7, minWin=22, winSum=385
7650 01:36:35.314019 TX Vref=22, minBit 0, minWin=24, winSum=396
7651 01:36:35.316882 TX Vref=24, minBit 8, minWin=24, winSum=405
7652 01:36:35.323547 TX Vref=26, minBit 1, minWin=25, winSum=411
7653 01:36:35.326864 TX Vref=28, minBit 7, minWin=25, winSum=418
7654 01:36:35.330316 TX Vref=30, minBit 0, minWin=25, winSum=414
7655 01:36:35.333372 TX Vref=32, minBit 1, minWin=25, winSum=406
7656 01:36:35.336615 TX Vref=34, minBit 1, minWin=24, winSum=398
7657 01:36:35.343515 TX Vref=36, minBit 2, minWin=23, winSum=384
7658 01:36:35.346393 [TxChooseVref] Worse bit 7, Min win 25, Win sum 418, Final Vref 28
7659 01:36:35.346820
7660 01:36:35.349566 Final TX Range 0 Vref 28
7661 01:36:35.349990
7662 01:36:35.350325 ==
7663 01:36:35.353069 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 01:36:35.356604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 01:36:35.359357 ==
7666 01:36:35.359781
7667 01:36:35.360113
7668 01:36:35.360421 TX Vref Scan disable
7669 01:36:35.366760 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7670 01:36:35.367199 == TX Byte 0 ==
7671 01:36:35.370110 u2DelayCellOfst[0]=14 cells (4 PI)
7672 01:36:35.373350 u2DelayCellOfst[1]=17 cells (5 PI)
7673 01:36:35.376910 u2DelayCellOfst[2]=14 cells (4 PI)
7674 01:36:35.379907 u2DelayCellOfst[3]=10 cells (3 PI)
7675 01:36:35.383398 u2DelayCellOfst[4]=10 cells (3 PI)
7676 01:36:35.386197 u2DelayCellOfst[5]=0 cells (0 PI)
7677 01:36:35.389597 u2DelayCellOfst[6]=21 cells (6 PI)
7678 01:36:35.393025 u2DelayCellOfst[7]=21 cells (6 PI)
7679 01:36:35.396278 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7680 01:36:35.402884 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7681 01:36:35.403311 == TX Byte 1 ==
7682 01:36:35.406481 u2DelayCellOfst[8]=0 cells (0 PI)
7683 01:36:35.409343 u2DelayCellOfst[9]=0 cells (0 PI)
7684 01:36:35.412882 u2DelayCellOfst[10]=3 cells (1 PI)
7685 01:36:35.416237 u2DelayCellOfst[11]=0 cells (0 PI)
7686 01:36:35.419050 u2DelayCellOfst[12]=7 cells (2 PI)
7687 01:36:35.422652 u2DelayCellOfst[13]=7 cells (2 PI)
7688 01:36:35.425924 u2DelayCellOfst[14]=14 cells (4 PI)
7689 01:36:35.426352 u2DelayCellOfst[15]=7 cells (2 PI)
7690 01:36:35.432667 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7691 01:36:35.436430 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7692 01:36:35.439064 DramC Write-DBI on
7693 01:36:35.439503 ==
7694 01:36:35.441984 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 01:36:35.445585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 01:36:35.446017 ==
7697 01:36:35.446352
7698 01:36:35.446664
7699 01:36:35.448934 TX Vref Scan disable
7700 01:36:35.452144 == TX Byte 0 ==
7701 01:36:35.455573 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7702 01:36:35.455995 == TX Byte 1 ==
7703 01:36:35.461766 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
7704 01:36:35.462195 DramC Write-DBI off
7705 01:36:35.462529
7706 01:36:35.462841 [DATLAT]
7707 01:36:35.464975 Freq=1600, CH0 RK0
7708 01:36:35.465523
7709 01:36:35.468471 DATLAT Default: 0xf
7710 01:36:35.468893 0, 0xFFFF, sum = 0
7711 01:36:35.472077 1, 0xFFFF, sum = 0
7712 01:36:35.472508 2, 0xFFFF, sum = 0
7713 01:36:35.475328 3, 0xFFFF, sum = 0
7714 01:36:35.475756 4, 0xFFFF, sum = 0
7715 01:36:35.478303 5, 0xFFFF, sum = 0
7716 01:36:35.478747 6, 0xFFFF, sum = 0
7717 01:36:35.481828 7, 0xFFFF, sum = 0
7718 01:36:35.482257 8, 0xFFFF, sum = 0
7719 01:36:35.484720 9, 0xFFFF, sum = 0
7720 01:36:35.485328 10, 0xFFFF, sum = 0
7721 01:36:35.488302 11, 0xFFFF, sum = 0
7722 01:36:35.491703 12, 0xFFFF, sum = 0
7723 01:36:35.492198 13, 0xFFFF, sum = 0
7724 01:36:35.495618 14, 0x0, sum = 1
7725 01:36:35.496134 15, 0x0, sum = 2
7726 01:36:35.496478 16, 0x0, sum = 3
7727 01:36:35.498044 17, 0x0, sum = 4
7728 01:36:35.498556 best_step = 15
7729 01:36:35.498910
7730 01:36:35.501134 ==
7731 01:36:35.501589 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 01:36:35.508114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 01:36:35.508646 ==
7734 01:36:35.508988 RX Vref Scan: 1
7735 01:36:35.509333
7736 01:36:35.511529 Set Vref Range= 24 -> 127
7737 01:36:35.511972
7738 01:36:35.514235 RX Vref 24 -> 127, step: 1
7739 01:36:35.514660
7740 01:36:35.517745 RX Delay 11 -> 252, step: 4
7741 01:36:35.518187
7742 01:36:35.521614 Set Vref, RX VrefLevel [Byte0]: 24
7743 01:36:35.524285 [Byte1]: 24
7744 01:36:35.524713
7745 01:36:35.527430 Set Vref, RX VrefLevel [Byte0]: 25
7746 01:36:35.530897 [Byte1]: 25
7747 01:36:35.531327
7748 01:36:35.534526 Set Vref, RX VrefLevel [Byte0]: 26
7749 01:36:35.537622 [Byte1]: 26
7750 01:36:35.541081
7751 01:36:35.541708 Set Vref, RX VrefLevel [Byte0]: 27
7752 01:36:35.544730 [Byte1]: 27
7753 01:36:35.548821
7754 01:36:35.549250 Set Vref, RX VrefLevel [Byte0]: 28
7755 01:36:35.551873 [Byte1]: 28
7756 01:36:35.556510
7757 01:36:35.556933 Set Vref, RX VrefLevel [Byte0]: 29
7758 01:36:35.559606 [Byte1]: 29
7759 01:36:35.563878
7760 01:36:35.564306 Set Vref, RX VrefLevel [Byte0]: 30
7761 01:36:35.567055 [Byte1]: 30
7762 01:36:35.571543
7763 01:36:35.571977 Set Vref, RX VrefLevel [Byte0]: 31
7764 01:36:35.574949 [Byte1]: 31
7765 01:36:35.579130
7766 01:36:35.579554 Set Vref, RX VrefLevel [Byte0]: 32
7767 01:36:35.582353 [Byte1]: 32
7768 01:36:35.586828
7769 01:36:35.587250 Set Vref, RX VrefLevel [Byte0]: 33
7770 01:36:35.590006 [Byte1]: 33
7771 01:36:35.594908
7772 01:36:35.595421 Set Vref, RX VrefLevel [Byte0]: 34
7773 01:36:35.597681 [Byte1]: 34
7774 01:36:35.602172
7775 01:36:35.602593 Set Vref, RX VrefLevel [Byte0]: 35
7776 01:36:35.605805 [Byte1]: 35
7777 01:36:35.609556
7778 01:36:35.609977 Set Vref, RX VrefLevel [Byte0]: 36
7779 01:36:35.612912 [Byte1]: 36
7780 01:36:35.617026
7781 01:36:35.617478 Set Vref, RX VrefLevel [Byte0]: 37
7782 01:36:35.620401 [Byte1]: 37
7783 01:36:35.625087
7784 01:36:35.625627 Set Vref, RX VrefLevel [Byte0]: 38
7785 01:36:35.628179 [Byte1]: 38
7786 01:36:35.632929
7787 01:36:35.633476 Set Vref, RX VrefLevel [Byte0]: 39
7788 01:36:35.635499 [Byte1]: 39
7789 01:36:35.640480
7790 01:36:35.640984 Set Vref, RX VrefLevel [Byte0]: 40
7791 01:36:35.643294 [Byte1]: 40
7792 01:36:35.647844
7793 01:36:35.648263 Set Vref, RX VrefLevel [Byte0]: 41
7794 01:36:35.651275 [Byte1]: 41
7795 01:36:35.655364
7796 01:36:35.655786 Set Vref, RX VrefLevel [Byte0]: 42
7797 01:36:35.658689 [Byte1]: 42
7798 01:36:35.662985
7799 01:36:35.663403 Set Vref, RX VrefLevel [Byte0]: 43
7800 01:36:35.666427 [Byte1]: 43
7801 01:36:35.670643
7802 01:36:35.671063 Set Vref, RX VrefLevel [Byte0]: 44
7803 01:36:35.673764 [Byte1]: 44
7804 01:36:35.678068
7805 01:36:35.678591 Set Vref, RX VrefLevel [Byte0]: 45
7806 01:36:35.681574 [Byte1]: 45
7807 01:36:35.685969
7808 01:36:35.686481 Set Vref, RX VrefLevel [Byte0]: 46
7809 01:36:35.689176 [Byte1]: 46
7810 01:36:35.693294
7811 01:36:35.693804 Set Vref, RX VrefLevel [Byte0]: 47
7812 01:36:35.696524 [Byte1]: 47
7813 01:36:35.701309
7814 01:36:35.701815 Set Vref, RX VrefLevel [Byte0]: 48
7815 01:36:35.704523 [Byte1]: 48
7816 01:36:35.709208
7817 01:36:35.709781 Set Vref, RX VrefLevel [Byte0]: 49
7818 01:36:35.712501 [Byte1]: 49
7819 01:36:35.716124
7820 01:36:35.716574 Set Vref, RX VrefLevel [Byte0]: 50
7821 01:36:35.719581 [Byte1]: 50
7822 01:36:35.724934
7823 01:36:35.725479 Set Vref, RX VrefLevel [Byte0]: 51
7824 01:36:35.727642 [Byte1]: 51
7825 01:36:35.731306
7826 01:36:35.731722 Set Vref, RX VrefLevel [Byte0]: 52
7827 01:36:35.735333 [Byte1]: 52
7828 01:36:35.739167
7829 01:36:35.739602 Set Vref, RX VrefLevel [Byte0]: 53
7830 01:36:35.742804 [Byte1]: 53
7831 01:36:35.747086
7832 01:36:35.747619 Set Vref, RX VrefLevel [Byte0]: 54
7833 01:36:35.749903 [Byte1]: 54
7834 01:36:35.754131
7835 01:36:35.754549 Set Vref, RX VrefLevel [Byte0]: 55
7836 01:36:35.757409 [Byte1]: 55
7837 01:36:35.762052
7838 01:36:35.762582 Set Vref, RX VrefLevel [Byte0]: 56
7839 01:36:35.765173 [Byte1]: 56
7840 01:36:35.769251
7841 01:36:35.769720 Set Vref, RX VrefLevel [Byte0]: 57
7842 01:36:35.772656 [Byte1]: 57
7843 01:36:35.776946
7844 01:36:35.777472 Set Vref, RX VrefLevel [Byte0]: 58
7845 01:36:35.780121 [Byte1]: 58
7846 01:36:35.784928
7847 01:36:35.785486 Set Vref, RX VrefLevel [Byte0]: 59
7848 01:36:35.787782 [Byte1]: 59
7849 01:36:35.792348
7850 01:36:35.792976 Set Vref, RX VrefLevel [Byte0]: 60
7851 01:36:35.795746 [Byte1]: 60
7852 01:36:35.799745
7853 01:36:35.800209 Set Vref, RX VrefLevel [Byte0]: 61
7854 01:36:35.803367 [Byte1]: 61
7855 01:36:35.807341
7856 01:36:35.807757 Set Vref, RX VrefLevel [Byte0]: 62
7857 01:36:35.810762 [Byte1]: 62
7858 01:36:35.815293
7859 01:36:35.815815 Set Vref, RX VrefLevel [Byte0]: 63
7860 01:36:35.818415 [Byte1]: 63
7861 01:36:35.823130
7862 01:36:35.823637 Set Vref, RX VrefLevel [Byte0]: 64
7863 01:36:35.826188 [Byte1]: 64
7864 01:36:35.830700
7865 01:36:35.831225 Set Vref, RX VrefLevel [Byte0]: 65
7866 01:36:35.833857 [Byte1]: 65
7867 01:36:35.838242
7868 01:36:35.838805 Set Vref, RX VrefLevel [Byte0]: 66
7869 01:36:35.841309 [Byte1]: 66
7870 01:36:35.846240
7871 01:36:35.846698 Set Vref, RX VrefLevel [Byte0]: 67
7872 01:36:35.848987 [Byte1]: 67
7873 01:36:35.853081
7874 01:36:35.853544 Set Vref, RX VrefLevel [Byte0]: 68
7875 01:36:35.856438 [Byte1]: 68
7876 01:36:35.860752
7877 01:36:35.861406 Set Vref, RX VrefLevel [Byte0]: 69
7878 01:36:35.864433 [Byte1]: 69
7879 01:36:35.868555
7880 01:36:35.869076 Set Vref, RX VrefLevel [Byte0]: 70
7881 01:36:35.872019 [Byte1]: 70
7882 01:36:35.876177
7883 01:36:35.876689 Set Vref, RX VrefLevel [Byte0]: 71
7884 01:36:35.879429 [Byte1]: 71
7885 01:36:35.883890
7886 01:36:35.884404 Set Vref, RX VrefLevel [Byte0]: 72
7887 01:36:35.887208 [Byte1]: 72
7888 01:36:35.891567
7889 01:36:35.892081 Set Vref, RX VrefLevel [Byte0]: 73
7890 01:36:35.894487 [Byte1]: 73
7891 01:36:35.899029
7892 01:36:35.899512 Set Vref, RX VrefLevel [Byte0]: 74
7893 01:36:35.902117 [Byte1]: 74
7894 01:36:35.906297
7895 01:36:35.909702 Set Vref, RX VrefLevel [Byte0]: 75
7896 01:36:35.912935 [Byte1]: 75
7897 01:36:35.913414
7898 01:36:35.916826 Final RX Vref Byte 0 = 57 to rank0
7899 01:36:35.919805 Final RX Vref Byte 1 = 57 to rank0
7900 01:36:35.923154 Final RX Vref Byte 0 = 57 to rank1
7901 01:36:35.925994 Final RX Vref Byte 1 = 57 to rank1==
7902 01:36:35.929626 Dram Type= 6, Freq= 0, CH_0, rank 0
7903 01:36:35.932530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7904 01:36:35.933047 ==
7905 01:36:35.933510 DQS Delay:
7906 01:36:35.935889 DQS0 = 0, DQS1 = 0
7907 01:36:35.936404 DQM Delay:
7908 01:36:35.939029 DQM0 = 129, DQM1 = 123
7909 01:36:35.939463 DQ Delay:
7910 01:36:35.942710 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7911 01:36:35.945561 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
7912 01:36:35.949032 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7913 01:36:35.955644 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
7914 01:36:35.956320
7915 01:36:35.956668
7916 01:36:35.956976
7917 01:36:35.957350 [DramC_TX_OE_Calibration] TA2
7918 01:36:35.958670 Original DQ_B0 (3 6) =30, OEN = 27
7919 01:36:35.962264 Original DQ_B1 (3 6) =30, OEN = 27
7920 01:36:35.966116 24, 0x0, End_B0=24 End_B1=24
7921 01:36:35.968937 25, 0x0, End_B0=25 End_B1=25
7922 01:36:35.971926 26, 0x0, End_B0=26 End_B1=26
7923 01:36:35.974912 27, 0x0, End_B0=27 End_B1=27
7924 01:36:35.975383 28, 0x0, End_B0=28 End_B1=28
7925 01:36:35.978594 29, 0x0, End_B0=29 End_B1=29
7926 01:36:35.981544 30, 0x0, End_B0=30 End_B1=30
7927 01:36:35.985107 31, 0x4141, End_B0=30 End_B1=30
7928 01:36:35.988145 Byte0 end_step=30 best_step=27
7929 01:36:35.991573 Byte1 end_step=30 best_step=27
7930 01:36:35.992312 Byte0 TX OE(2T, 0.5T) = (3, 3)
7931 01:36:35.994878 Byte1 TX OE(2T, 0.5T) = (3, 3)
7932 01:36:35.995581
7933 01:36:35.996116
7934 01:36:36.004979 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7935 01:36:36.008300 CH0 RK0: MR19=303, MR18=1815
7936 01:36:36.011266 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7937 01:36:36.011689
7938 01:36:36.014899 ----->DramcWriteLeveling(PI) begin...
7939 01:36:36.017950 ==
7940 01:36:36.021354 Dram Type= 6, Freq= 0, CH_0, rank 1
7941 01:36:36.024736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7942 01:36:36.025463 ==
7943 01:36:36.027751 Write leveling (Byte 0): 36 => 36
7944 01:36:36.031018 Write leveling (Byte 1): 27 => 27
7945 01:36:36.034556 DramcWriteLeveling(PI) end<-----
7946 01:36:36.035225
7947 01:36:36.035754 ==
7948 01:36:36.037523 Dram Type= 6, Freq= 0, CH_0, rank 1
7949 01:36:36.040625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 01:36:36.041075 ==
7951 01:36:36.043906 [Gating] SW mode calibration
7952 01:36:36.050860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7953 01:36:36.057229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7954 01:36:36.060754 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7955 01:36:36.063991 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7956 01:36:36.070284 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7957 01:36:36.073407 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7958 01:36:36.077240 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7959 01:36:36.083260 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
7960 01:36:36.086618 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 01:36:36.090041 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7962 01:36:36.096488 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7963 01:36:36.100580 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7964 01:36:36.103011 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7965 01:36:36.109785 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7966 01:36:36.112970 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7967 01:36:36.116485 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7968 01:36:36.123108 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7969 01:36:36.126527 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 01:36:36.129113 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 01:36:36.135887 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7972 01:36:36.139118 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
7973 01:36:36.142412 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7974 01:36:36.149206 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
7975 01:36:36.152280 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7976 01:36:36.159079 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 01:36:36.162200 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 01:36:36.165761 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 01:36:36.168685 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7980 01:36:36.175652 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7981 01:36:36.178760 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7982 01:36:36.182474 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7983 01:36:36.188680 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7984 01:36:36.191803 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 01:36:36.198584 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 01:36:36.201732 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 01:36:36.204847 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 01:36:36.208328 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 01:36:36.215056 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 01:36:36.218254 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 01:36:36.221853 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 01:36:36.228659 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 01:36:36.231572 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 01:36:36.238094 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 01:36:36.241591 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 01:36:36.244245 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7997 01:36:36.248066 Total UI for P1: 0, mck2ui 16
7998 01:36:36.251052 best dqsien dly found for B0: ( 1, 9, 6)
7999 01:36:36.257677 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8000 01:36:36.261794 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8001 01:36:36.264501 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8002 01:36:36.270645 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 01:36:36.271238 Total UI for P1: 0, mck2ui 16
8004 01:36:36.277880 best dqsien dly found for B1: ( 1, 9, 20)
8005 01:36:36.280638 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8006 01:36:36.283522 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8007 01:36:36.283991
8008 01:36:36.287395 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8009 01:36:36.290369 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8010 01:36:36.293466 [Gating] SW calibration Done
8011 01:36:36.294030 ==
8012 01:36:36.297310 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 01:36:36.301141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 01:36:36.301760 ==
8015 01:36:36.303563 RX Vref Scan: 0
8016 01:36:36.304025
8017 01:36:36.304398 RX Vref 0 -> 0, step: 1
8018 01:36:36.304755
8019 01:36:36.306664 RX Delay 0 -> 252, step: 8
8020 01:36:36.309902 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8021 01:36:36.316648 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8022 01:36:36.319602 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8023 01:36:36.323467 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8024 01:36:36.326452 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8025 01:36:36.329538 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8026 01:36:36.336634 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8027 01:36:36.339818 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8028 01:36:36.343248 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8029 01:36:36.346120 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8030 01:36:36.352762 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8031 01:36:36.356185 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8032 01:36:36.359671 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8033 01:36:36.363056 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8034 01:36:36.366269 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8035 01:36:36.372693 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8036 01:36:36.373176 ==
8037 01:36:36.375747 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 01:36:36.379643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 01:36:36.380064 ==
8040 01:36:36.380391 DQS Delay:
8041 01:36:36.382614 DQS0 = 0, DQS1 = 0
8042 01:36:36.383032 DQM Delay:
8043 01:36:36.385583 DQM0 = 130, DQM1 = 127
8044 01:36:36.386000 DQ Delay:
8045 01:36:36.389056 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
8046 01:36:36.392036 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8047 01:36:36.395691 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8048 01:36:36.402629 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8049 01:36:36.403141
8050 01:36:36.403472
8051 01:36:36.403777 ==
8052 01:36:36.405721 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 01:36:36.408809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 01:36:36.409367 ==
8055 01:36:36.409709
8056 01:36:36.410017
8057 01:36:36.412553 TX Vref Scan disable
8058 01:36:36.413066 == TX Byte 0 ==
8059 01:36:36.418562 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8060 01:36:36.422080 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8061 01:36:36.422506 == TX Byte 1 ==
8062 01:36:36.428674 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8063 01:36:36.431851 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8064 01:36:36.432355 ==
8065 01:36:36.435000 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 01:36:36.438467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 01:36:36.438891 ==
8068 01:36:36.453218
8069 01:36:36.456280 TX Vref early break, caculate TX vref
8070 01:36:36.460298 TX Vref=16, minBit 2, minWin=23, winSum=382
8071 01:36:36.462900 TX Vref=18, minBit 0, minWin=24, winSum=390
8072 01:36:36.466503 TX Vref=20, minBit 1, minWin=24, winSum=400
8073 01:36:36.469413 TX Vref=22, minBit 4, minWin=24, winSum=404
8074 01:36:36.472782 TX Vref=24, minBit 8, minWin=24, winSum=414
8075 01:36:36.479554 TX Vref=26, minBit 4, minWin=25, winSum=421
8076 01:36:36.483083 TX Vref=28, minBit 0, minWin=26, winSum=421
8077 01:36:36.486488 TX Vref=30, minBit 2, minWin=25, winSum=418
8078 01:36:36.489321 TX Vref=32, minBit 1, minWin=24, winSum=410
8079 01:36:36.492456 TX Vref=34, minBit 0, minWin=24, winSum=398
8080 01:36:36.499537 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
8081 01:36:36.500031
8082 01:36:36.503239 Final TX Range 0 Vref 28
8083 01:36:36.503780
8084 01:36:36.504135 ==
8085 01:36:36.505695 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 01:36:36.509209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 01:36:36.509669 ==
8088 01:36:36.509999
8089 01:36:36.510304
8090 01:36:36.512758 TX Vref Scan disable
8091 01:36:36.518781 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8092 01:36:36.519208 == TX Byte 0 ==
8093 01:36:36.522345 u2DelayCellOfst[0]=10 cells (3 PI)
8094 01:36:36.525751 u2DelayCellOfst[1]=14 cells (4 PI)
8095 01:36:36.528778 u2DelayCellOfst[2]=7 cells (2 PI)
8096 01:36:36.532001 u2DelayCellOfst[3]=10 cells (3 PI)
8097 01:36:36.535295 u2DelayCellOfst[4]=7 cells (2 PI)
8098 01:36:36.538784 u2DelayCellOfst[5]=0 cells (0 PI)
8099 01:36:36.542085 u2DelayCellOfst[6]=14 cells (4 PI)
8100 01:36:36.545181 u2DelayCellOfst[7]=17 cells (5 PI)
8101 01:36:36.548896 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8102 01:36:36.551829 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8103 01:36:36.555206 == TX Byte 1 ==
8104 01:36:36.558192 u2DelayCellOfst[8]=0 cells (0 PI)
8105 01:36:36.561880 u2DelayCellOfst[9]=0 cells (0 PI)
8106 01:36:36.565219 u2DelayCellOfst[10]=3 cells (1 PI)
8107 01:36:36.568302 u2DelayCellOfst[11]=0 cells (0 PI)
8108 01:36:36.571615 u2DelayCellOfst[12]=10 cells (3 PI)
8109 01:36:36.572078 u2DelayCellOfst[13]=10 cells (3 PI)
8110 01:36:36.575017 u2DelayCellOfst[14]=14 cells (4 PI)
8111 01:36:36.578197 u2DelayCellOfst[15]=10 cells (3 PI)
8112 01:36:36.584731 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8113 01:36:36.588020 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8114 01:36:36.591631 DramC Write-DBI on
8115 01:36:36.592050 ==
8116 01:36:36.594611 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 01:36:36.597737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 01:36:36.598159 ==
8119 01:36:36.598492
8120 01:36:36.598793
8121 01:36:36.601655 TX Vref Scan disable
8122 01:36:36.602172 == TX Byte 0 ==
8123 01:36:36.608072 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8124 01:36:36.608494 == TX Byte 1 ==
8125 01:36:36.611458 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8126 01:36:36.614791 DramC Write-DBI off
8127 01:36:36.615298
8128 01:36:36.615630 [DATLAT]
8129 01:36:36.617628 Freq=1600, CH0 RK1
8130 01:36:36.618045
8131 01:36:36.618385 DATLAT Default: 0xf
8132 01:36:36.620846 0, 0xFFFF, sum = 0
8133 01:36:36.624578 1, 0xFFFF, sum = 0
8134 01:36:36.625136 2, 0xFFFF, sum = 0
8135 01:36:36.627577 3, 0xFFFF, sum = 0
8136 01:36:36.628086 4, 0xFFFF, sum = 0
8137 01:36:36.631017 5, 0xFFFF, sum = 0
8138 01:36:36.631592 6, 0xFFFF, sum = 0
8139 01:36:36.634358 7, 0xFFFF, sum = 0
8140 01:36:36.634808 8, 0xFFFF, sum = 0
8141 01:36:36.637254 9, 0xFFFF, sum = 0
8142 01:36:36.637794 10, 0xFFFF, sum = 0
8143 01:36:36.641117 11, 0xFFFF, sum = 0
8144 01:36:36.641713 12, 0xFFFF, sum = 0
8145 01:36:36.644188 13, 0xFFFF, sum = 0
8146 01:36:36.644704 14, 0x0, sum = 1
8147 01:36:36.647884 15, 0x0, sum = 2
8148 01:36:36.648395 16, 0x0, sum = 3
8149 01:36:36.650911 17, 0x0, sum = 4
8150 01:36:36.651349 best_step = 15
8151 01:36:36.651678
8152 01:36:36.651984 ==
8153 01:36:36.654208 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 01:36:36.660885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 01:36:36.661344 ==
8156 01:36:36.661683 RX Vref Scan: 0
8157 01:36:36.661991
8158 01:36:36.664248 RX Vref 0 -> 0, step: 1
8159 01:36:36.664764
8160 01:36:36.667778 RX Delay 11 -> 252, step: 4
8161 01:36:36.670538 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8162 01:36:36.673751 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8163 01:36:36.676988 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8164 01:36:36.683541 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8165 01:36:36.686971 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8166 01:36:36.690344 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8167 01:36:36.693700 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8168 01:36:36.696697 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8169 01:36:36.703482 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8170 01:36:36.706882 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8171 01:36:36.710534 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8172 01:36:36.713222 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8173 01:36:36.720513 iDelay=191, Bit 12, Center 126 (71 ~ 182) 112
8174 01:36:36.722869 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8175 01:36:36.726923 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8176 01:36:36.730023 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8177 01:36:36.730445 ==
8178 01:36:36.733205 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 01:36:36.740342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 01:36:36.740766 ==
8181 01:36:36.741098 DQS Delay:
8182 01:36:36.742825 DQS0 = 0, DQS1 = 0
8183 01:36:36.743274 DQM Delay:
8184 01:36:36.743604 DQM0 = 128, DQM1 = 123
8185 01:36:36.746557 DQ Delay:
8186 01:36:36.749833 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8187 01:36:36.752605 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8188 01:36:36.756012 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =118
8189 01:36:36.759324 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =130
8190 01:36:36.759749
8191 01:36:36.760080
8192 01:36:36.760383
8193 01:36:36.762483 [DramC_TX_OE_Calibration] TA2
8194 01:36:36.766169 Original DQ_B0 (3 6) =30, OEN = 27
8195 01:36:36.769393 Original DQ_B1 (3 6) =30, OEN = 27
8196 01:36:36.772618 24, 0x0, End_B0=24 End_B1=24
8197 01:36:36.776573 25, 0x0, End_B0=25 End_B1=25
8198 01:36:36.776998 26, 0x0, End_B0=26 End_B1=26
8199 01:36:36.779710 27, 0x0, End_B0=27 End_B1=27
8200 01:36:36.782268 28, 0x0, End_B0=28 End_B1=28
8201 01:36:36.785691 29, 0x0, End_B0=29 End_B1=29
8202 01:36:36.786118 30, 0x0, End_B0=30 End_B1=30
8203 01:36:36.789091 31, 0x4141, End_B0=30 End_B1=30
8204 01:36:36.792673 Byte0 end_step=30 best_step=27
8205 01:36:36.795965 Byte1 end_step=30 best_step=27
8206 01:36:36.798967 Byte0 TX OE(2T, 0.5T) = (3, 3)
8207 01:36:36.802540 Byte1 TX OE(2T, 0.5T) = (3, 3)
8208 01:36:36.803053
8209 01:36:36.803387
8210 01:36:36.808903 [DQSOSCAuto] RK1, (LSB)MR18= 0x100f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8211 01:36:36.812493 CH0 RK1: MR19=303, MR18=100F
8212 01:36:36.818683 CH0_RK1: MR19=0x303, MR18=0x100F, DQSOSC=401, MR23=63, INC=22, DEC=15
8213 01:36:36.821748 [RxdqsGatingPostProcess] freq 1600
8214 01:36:36.828719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8215 01:36:36.829200 best DQS0 dly(2T, 0.5T) = (1, 1)
8216 01:36:36.831821 best DQS1 dly(2T, 0.5T) = (1, 1)
8217 01:36:36.834969 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8218 01:36:36.838337 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8219 01:36:36.841807 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 01:36:36.845161 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 01:36:36.848203 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 01:36:36.851503 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 01:36:36.854779 Pre-setting of DQS Precalculation
8224 01:36:36.858099 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8225 01:36:36.861664 ==
8226 01:36:36.862090 Dram Type= 6, Freq= 0, CH_1, rank 0
8227 01:36:36.868172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 01:36:36.868712 ==
8229 01:36:36.871320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8230 01:36:36.878058 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8231 01:36:36.881530 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8232 01:36:36.887967 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8233 01:36:36.896288 [CA 0] Center 42 (12~72) winsize 61
8234 01:36:36.899418 [CA 1] Center 42 (12~72) winsize 61
8235 01:36:36.902562 [CA 2] Center 38 (9~68) winsize 60
8236 01:36:36.905913 [CA 3] Center 37 (8~66) winsize 59
8237 01:36:36.909412 [CA 4] Center 38 (8~68) winsize 61
8238 01:36:36.912198 [CA 5] Center 36 (7~66) winsize 60
8239 01:36:36.912661
8240 01:36:36.915893 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8241 01:36:36.916451
8242 01:36:36.922548 [CATrainingPosCal] consider 1 rank data
8243 01:36:36.923013 u2DelayCellTimex100 = 275/100 ps
8244 01:36:36.929099 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8245 01:36:36.932201 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8246 01:36:36.935834 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8247 01:36:36.938819 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8248 01:36:36.942222 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8249 01:36:36.945310 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8250 01:36:36.945782
8251 01:36:36.949342 CA PerBit enable=1, Macro0, CA PI delay=36
8252 01:36:36.949900
8253 01:36:36.952393 [CBTSetCACLKResult] CA Dly = 36
8254 01:36:36.955278 CS Dly: 8 (0~39)
8255 01:36:36.958518 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8256 01:36:36.961894 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8257 01:36:36.962356 ==
8258 01:36:36.965609 Dram Type= 6, Freq= 0, CH_1, rank 1
8259 01:36:36.971809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 01:36:36.972372 ==
8261 01:36:36.974921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 01:36:36.981674 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 01:36:36.984897 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 01:36:36.991733 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 01:36:36.999114 [CA 0] Center 42 (12~72) winsize 61
8266 01:36:37.003009 [CA 1] Center 43 (14~72) winsize 59
8267 01:36:37.005730 [CA 2] Center 38 (9~68) winsize 60
8268 01:36:37.009193 [CA 3] Center 37 (8~67) winsize 60
8269 01:36:37.012363 [CA 4] Center 38 (8~68) winsize 61
8270 01:36:37.015657 [CA 5] Center 37 (8~67) winsize 60
8271 01:36:37.016122
8272 01:36:37.019060 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8273 01:36:37.019522
8274 01:36:37.025517 [CATrainingPosCal] consider 2 rank data
8275 01:36:37.026085 u2DelayCellTimex100 = 275/100 ps
8276 01:36:37.032258 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8277 01:36:37.035429 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8278 01:36:37.038754 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8279 01:36:37.041863 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8280 01:36:37.045368 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8281 01:36:37.048454 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8282 01:36:37.048897
8283 01:36:37.051758 CA PerBit enable=1, Macro0, CA PI delay=37
8284 01:36:37.052177
8285 01:36:37.054817 [CBTSetCACLKResult] CA Dly = 37
8286 01:36:37.058289 CS Dly: 9 (0~42)
8287 01:36:37.061341 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 01:36:37.065334 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 01:36:37.065854
8290 01:36:37.068222 ----->DramcWriteLeveling(PI) begin...
8291 01:36:37.068738 ==
8292 01:36:37.071806 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 01:36:37.077592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 01:36:37.078013 ==
8295 01:36:37.081195 Write leveling (Byte 0): 25 => 25
8296 01:36:37.084609 Write leveling (Byte 1): 26 => 26
8297 01:36:37.087788 DramcWriteLeveling(PI) end<-----
8298 01:36:37.088199
8299 01:36:37.088519 ==
8300 01:36:37.091215 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 01:36:37.094090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 01:36:37.094504 ==
8303 01:36:37.097435 [Gating] SW mode calibration
8304 01:36:37.104468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8305 01:36:37.110710 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8306 01:36:37.114000 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 01:36:37.117488 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 01:36:37.124015 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8309 01:36:37.127341 1 4 12 | B1->B0 | 2424 3131 | 1 1 | (1 1) (1 1)
8310 01:36:37.130718 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 01:36:37.136965 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 01:36:37.140632 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 01:36:37.143765 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 01:36:37.150788 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 01:36:37.153354 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 01:36:37.156709 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8317 01:36:37.163298 1 5 12 | B1->B0 | 3434 2b2b | 0 0 | (1 0) (1 0)
8318 01:36:37.166785 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 01:36:37.170220 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 01:36:37.176649 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 01:36:37.179977 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 01:36:37.183461 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 01:36:37.189674 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 01:36:37.193025 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8325 01:36:37.196325 1 6 12 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
8326 01:36:37.203157 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 01:36:37.206605 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 01:36:37.209074 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 01:36:37.216106 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 01:36:37.219794 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 01:36:37.222710 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 01:36:37.229879 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8333 01:36:37.232578 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8334 01:36:37.235975 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8335 01:36:37.242610 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 01:36:37.245933 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 01:36:37.249157 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 01:36:37.255546 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 01:36:37.258778 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 01:36:37.262025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 01:36:37.268726 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 01:36:37.271722 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 01:36:37.274979 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 01:36:37.281598 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 01:36:37.284821 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 01:36:37.288150 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 01:36:37.295243 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 01:36:37.298221 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 01:36:37.301709 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8350 01:36:37.308251 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 01:36:37.308681 Total UI for P1: 0, mck2ui 16
8352 01:36:37.314893 best dqsien dly found for B0: ( 1, 9, 12)
8353 01:36:37.315316 Total UI for P1: 0, mck2ui 16
8354 01:36:37.321455 best dqsien dly found for B1: ( 1, 9, 12)
8355 01:36:37.324772 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8356 01:36:37.328294 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8357 01:36:37.328811
8358 01:36:37.331476 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8359 01:36:37.334888 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8360 01:36:37.337985 [Gating] SW calibration Done
8361 01:36:37.338406 ==
8362 01:36:37.341056 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 01:36:37.344379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 01:36:37.344814 ==
8365 01:36:37.347509 RX Vref Scan: 0
8366 01:36:37.348036
8367 01:36:37.350840 RX Vref 0 -> 0, step: 1
8368 01:36:37.351258
8369 01:36:37.351585 RX Delay 0 -> 252, step: 8
8370 01:36:37.357431 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8371 01:36:37.361116 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8372 01:36:37.363911 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8373 01:36:37.367578 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8374 01:36:37.370704 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8375 01:36:37.377040 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8376 01:36:37.381149 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8377 01:36:37.383804 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8378 01:36:37.387429 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8379 01:36:37.390875 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8380 01:36:37.397211 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8381 01:36:37.400404 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8382 01:36:37.403855 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8383 01:36:37.406995 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8384 01:36:37.413532 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8385 01:36:37.417116 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8386 01:36:37.417723 ==
8387 01:36:37.419974 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 01:36:37.423669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 01:36:37.424240 ==
8390 01:36:37.426674 DQS Delay:
8391 01:36:37.427240 DQS0 = 0, DQS1 = 0
8392 01:36:37.427611 DQM Delay:
8393 01:36:37.429993 DQM0 = 135, DQM1 = 130
8394 01:36:37.430452 DQ Delay:
8395 01:36:37.433610 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8396 01:36:37.436385 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8397 01:36:37.440121 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8398 01:36:37.446522 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8399 01:36:37.447070
8400 01:36:37.447431
8401 01:36:37.447773 ==
8402 01:36:37.450004 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 01:36:37.452987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 01:36:37.453476 ==
8405 01:36:37.453838
8406 01:36:37.454169
8407 01:36:37.456135 TX Vref Scan disable
8408 01:36:37.456597 == TX Byte 0 ==
8409 01:36:37.463058 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8410 01:36:37.465928 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8411 01:36:37.469424 == TX Byte 1 ==
8412 01:36:37.472603 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8413 01:36:37.476007 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8414 01:36:37.476570 ==
8415 01:36:37.479187 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 01:36:37.482617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 01:36:37.485616 ==
8418 01:36:37.496746
8419 01:36:37.500102 TX Vref early break, caculate TX vref
8420 01:36:37.503332 TX Vref=16, minBit 8, minWin=21, winSum=370
8421 01:36:37.506546 TX Vref=18, minBit 8, minWin=22, winSum=379
8422 01:36:37.509833 TX Vref=20, minBit 8, minWin=23, winSum=390
8423 01:36:37.513134 TX Vref=22, minBit 8, minWin=23, winSum=395
8424 01:36:37.516659 TX Vref=24, minBit 8, minWin=23, winSum=405
8425 01:36:37.522961 TX Vref=26, minBit 0, minWin=25, winSum=415
8426 01:36:37.526505 TX Vref=28, minBit 9, minWin=25, winSum=421
8427 01:36:37.529774 TX Vref=30, minBit 9, minWin=24, winSum=413
8428 01:36:37.533229 TX Vref=32, minBit 0, minWin=24, winSum=402
8429 01:36:37.536693 TX Vref=34, minBit 0, minWin=24, winSum=396
8430 01:36:37.542822 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8431 01:36:37.543376
8432 01:36:37.546423 Final TX Range 0 Vref 28
8433 01:36:37.546889
8434 01:36:37.547251 ==
8435 01:36:37.549336 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 01:36:37.552929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 01:36:37.553454 ==
8438 01:36:37.553826
8439 01:36:37.554164
8440 01:36:37.556239 TX Vref Scan disable
8441 01:36:37.562708 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8442 01:36:37.563268 == TX Byte 0 ==
8443 01:36:37.566550 u2DelayCellOfst[0]=17 cells (5 PI)
8444 01:36:37.569498 u2DelayCellOfst[1]=10 cells (3 PI)
8445 01:36:37.572828 u2DelayCellOfst[2]=0 cells (0 PI)
8446 01:36:37.576209 u2DelayCellOfst[3]=10 cells (3 PI)
8447 01:36:37.579318 u2DelayCellOfst[4]=10 cells (3 PI)
8448 01:36:37.582837 u2DelayCellOfst[5]=17 cells (5 PI)
8449 01:36:37.585902 u2DelayCellOfst[6]=17 cells (5 PI)
8450 01:36:37.589137 u2DelayCellOfst[7]=7 cells (2 PI)
8451 01:36:37.593038 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8452 01:36:37.595502 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8453 01:36:37.599252 == TX Byte 1 ==
8454 01:36:37.602110 u2DelayCellOfst[8]=0 cells (0 PI)
8455 01:36:37.605332 u2DelayCellOfst[9]=7 cells (2 PI)
8456 01:36:37.605795 u2DelayCellOfst[10]=10 cells (3 PI)
8457 01:36:37.608951 u2DelayCellOfst[11]=3 cells (1 PI)
8458 01:36:37.612512 u2DelayCellOfst[12]=14 cells (4 PI)
8459 01:36:37.615767 u2DelayCellOfst[13]=14 cells (4 PI)
8460 01:36:37.618839 u2DelayCellOfst[14]=17 cells (5 PI)
8461 01:36:37.622099 u2DelayCellOfst[15]=17 cells (5 PI)
8462 01:36:37.628915 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8463 01:36:37.632063 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 01:36:37.632657 DramC Write-DBI on
8465 01:36:37.633034 ==
8466 01:36:37.635420 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 01:36:37.642070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 01:36:37.642653 ==
8469 01:36:37.643024
8470 01:36:37.643359
8471 01:36:37.644715 TX Vref Scan disable
8472 01:36:37.645236 == TX Byte 0 ==
8473 01:36:37.651501 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8474 01:36:37.651966 == TX Byte 1 ==
8475 01:36:37.654962 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8476 01:36:37.658066 DramC Write-DBI off
8477 01:36:37.658532
8478 01:36:37.658892 [DATLAT]
8479 01:36:37.661431 Freq=1600, CH1 RK0
8480 01:36:37.661902
8481 01:36:37.662247 DATLAT Default: 0xf
8482 01:36:37.664685 0, 0xFFFF, sum = 0
8483 01:36:37.665302 1, 0xFFFF, sum = 0
8484 01:36:37.667811 2, 0xFFFF, sum = 0
8485 01:36:37.668229 3, 0xFFFF, sum = 0
8486 01:36:37.671175 4, 0xFFFF, sum = 0
8487 01:36:37.671596 5, 0xFFFF, sum = 0
8488 01:36:37.674377 6, 0xFFFF, sum = 0
8489 01:36:37.674799 7, 0xFFFF, sum = 0
8490 01:36:37.677779 8, 0xFFFF, sum = 0
8491 01:36:37.680830 9, 0xFFFF, sum = 0
8492 01:36:37.681249 10, 0xFFFF, sum = 0
8493 01:36:37.684489 11, 0xFFFF, sum = 0
8494 01:36:37.684908 12, 0xFFFF, sum = 0
8495 01:36:37.687890 13, 0xFFFF, sum = 0
8496 01:36:37.688572 14, 0x0, sum = 1
8497 01:36:37.691107 15, 0x0, sum = 2
8498 01:36:37.691531 16, 0x0, sum = 3
8499 01:36:37.694960 17, 0x0, sum = 4
8500 01:36:37.695483 best_step = 15
8501 01:36:37.695810
8502 01:36:37.696110 ==
8503 01:36:37.697822 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 01:36:37.700716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 01:36:37.704107 ==
8506 01:36:37.704626 RX Vref Scan: 1
8507 01:36:37.704962
8508 01:36:37.707573 Set Vref Range= 24 -> 127
8509 01:36:37.708005
8510 01:36:37.710955 RX Vref 24 -> 127, step: 1
8511 01:36:37.711369
8512 01:36:37.711694 RX Delay 19 -> 252, step: 4
8513 01:36:37.711994
8514 01:36:37.713836 Set Vref, RX VrefLevel [Byte0]: 24
8515 01:36:37.717458 [Byte1]: 24
8516 01:36:37.721364
8517 01:36:37.722034 Set Vref, RX VrefLevel [Byte0]: 25
8518 01:36:37.724465 [Byte1]: 25
8519 01:36:37.728727
8520 01:36:37.729413 Set Vref, RX VrefLevel [Byte0]: 26
8521 01:36:37.731811 [Byte1]: 26
8522 01:36:37.736093
8523 01:36:37.736607 Set Vref, RX VrefLevel [Byte0]: 27
8524 01:36:37.739988 [Byte1]: 27
8525 01:36:37.744220
8526 01:36:37.744735 Set Vref, RX VrefLevel [Byte0]: 28
8527 01:36:37.749823 [Byte1]: 28
8528 01:36:37.750309
8529 01:36:37.753538 Set Vref, RX VrefLevel [Byte0]: 29
8530 01:36:37.756913 [Byte1]: 29
8531 01:36:37.757387
8532 01:36:37.760123 Set Vref, RX VrefLevel [Byte0]: 30
8533 01:36:37.763248 [Byte1]: 30
8534 01:36:37.763673
8535 01:36:37.766809 Set Vref, RX VrefLevel [Byte0]: 31
8536 01:36:37.770174 [Byte1]: 31
8537 01:36:37.773805
8538 01:36:37.774222 Set Vref, RX VrefLevel [Byte0]: 32
8539 01:36:37.777471 [Byte1]: 32
8540 01:36:37.781882
8541 01:36:37.782301 Set Vref, RX VrefLevel [Byte0]: 33
8542 01:36:37.784907 [Byte1]: 33
8543 01:36:37.789324
8544 01:36:37.789749 Set Vref, RX VrefLevel [Byte0]: 34
8545 01:36:37.792352 [Byte1]: 34
8546 01:36:37.796779
8547 01:36:37.797371 Set Vref, RX VrefLevel [Byte0]: 35
8548 01:36:37.799827 [Byte1]: 35
8549 01:36:37.804643
8550 01:36:37.805061 Set Vref, RX VrefLevel [Byte0]: 36
8551 01:36:37.807352 [Byte1]: 36
8552 01:36:37.811895
8553 01:36:37.812372 Set Vref, RX VrefLevel [Byte0]: 37
8554 01:36:37.815378 [Byte1]: 37
8555 01:36:37.819953
8556 01:36:37.820497 Set Vref, RX VrefLevel [Byte0]: 38
8557 01:36:37.822809 [Byte1]: 38
8558 01:36:37.827097
8559 01:36:37.827513 Set Vref, RX VrefLevel [Byte0]: 39
8560 01:36:37.830540 [Byte1]: 39
8561 01:36:37.835238
8562 01:36:37.835751 Set Vref, RX VrefLevel [Byte0]: 40
8563 01:36:37.837630 [Byte1]: 40
8564 01:36:37.842191
8565 01:36:37.842706 Set Vref, RX VrefLevel [Byte0]: 41
8566 01:36:37.845841 [Byte1]: 41
8567 01:36:37.849658
8568 01:36:37.850080 Set Vref, RX VrefLevel [Byte0]: 42
8569 01:36:37.853133 [Byte1]: 42
8570 01:36:37.857080
8571 01:36:37.857536 Set Vref, RX VrefLevel [Byte0]: 43
8572 01:36:37.860651 [Byte1]: 43
8573 01:36:37.864943
8574 01:36:37.865398 Set Vref, RX VrefLevel [Byte0]: 44
8575 01:36:37.868729 [Byte1]: 44
8576 01:36:37.872600
8577 01:36:37.873172 Set Vref, RX VrefLevel [Byte0]: 45
8578 01:36:37.876116 [Byte1]: 45
8579 01:36:37.880831
8580 01:36:37.881435 Set Vref, RX VrefLevel [Byte0]: 46
8581 01:36:37.884017 [Byte1]: 46
8582 01:36:37.887971
8583 01:36:37.888705 Set Vref, RX VrefLevel [Byte0]: 47
8584 01:36:37.890884 [Byte1]: 47
8585 01:36:37.895922
8586 01:36:37.896473 Set Vref, RX VrefLevel [Byte0]: 48
8587 01:36:37.898579 [Byte1]: 48
8588 01:36:37.902704
8589 01:36:37.903259 Set Vref, RX VrefLevel [Byte0]: 49
8590 01:36:37.906661 [Byte1]: 49
8591 01:36:37.910324
8592 01:36:37.910927 Set Vref, RX VrefLevel [Byte0]: 50
8593 01:36:37.914025 [Byte1]: 50
8594 01:36:37.918165
8595 01:36:37.918675 Set Vref, RX VrefLevel [Byte0]: 51
8596 01:36:37.921324 [Byte1]: 51
8597 01:36:37.925451
8598 01:36:37.925999 Set Vref, RX VrefLevel [Byte0]: 52
8599 01:36:37.929033 [Byte1]: 52
8600 01:36:37.933692
8601 01:36:37.934379 Set Vref, RX VrefLevel [Byte0]: 53
8602 01:36:37.936763 [Byte1]: 53
8603 01:36:37.941204
8604 01:36:37.941793 Set Vref, RX VrefLevel [Byte0]: 54
8605 01:36:37.944205 [Byte1]: 54
8606 01:36:37.948505
8607 01:36:37.948971 Set Vref, RX VrefLevel [Byte0]: 55
8608 01:36:37.951557 [Byte1]: 55
8609 01:36:37.956197
8610 01:36:37.956735 Set Vref, RX VrefLevel [Byte0]: 56
8611 01:36:37.959237 [Byte1]: 56
8612 01:36:37.963558
8613 01:36:37.964120 Set Vref, RX VrefLevel [Byte0]: 57
8614 01:36:37.966820 [Byte1]: 57
8615 01:36:37.971383
8616 01:36:37.971945 Set Vref, RX VrefLevel [Byte0]: 58
8617 01:36:37.974511 [Byte1]: 58
8618 01:36:37.978613
8619 01:36:37.979214 Set Vref, RX VrefLevel [Byte0]: 59
8620 01:36:37.981914 [Byte1]: 59
8621 01:36:37.986009
8622 01:36:37.986607 Set Vref, RX VrefLevel [Byte0]: 60
8623 01:36:37.989568 [Byte1]: 60
8624 01:36:37.994340
8625 01:36:37.994893 Set Vref, RX VrefLevel [Byte0]: 61
8626 01:36:37.996882 [Byte1]: 61
8627 01:36:38.001251
8628 01:36:38.001850 Set Vref, RX VrefLevel [Byte0]: 62
8629 01:36:38.005066 [Byte1]: 62
8630 01:36:38.009207
8631 01:36:38.009805 Set Vref, RX VrefLevel [Byte0]: 63
8632 01:36:38.012143 [Byte1]: 63
8633 01:36:38.016740
8634 01:36:38.017337 Set Vref, RX VrefLevel [Byte0]: 64
8635 01:36:38.019893 [Byte1]: 64
8636 01:36:38.023979
8637 01:36:38.024530 Set Vref, RX VrefLevel [Byte0]: 65
8638 01:36:38.028120 [Byte1]: 65
8639 01:36:38.031331
8640 01:36:38.031787 Set Vref, RX VrefLevel [Byte0]: 66
8641 01:36:38.034855 [Byte1]: 66
8642 01:36:38.039528
8643 01:36:38.040076 Set Vref, RX VrefLevel [Byte0]: 67
8644 01:36:38.045827 [Byte1]: 67
8645 01:36:38.046390
8646 01:36:38.049028 Set Vref, RX VrefLevel [Byte0]: 68
8647 01:36:38.052361 [Byte1]: 68
8648 01:36:38.052824
8649 01:36:38.055988 Set Vref, RX VrefLevel [Byte0]: 69
8650 01:36:38.059065 [Byte1]: 69
8651 01:36:38.059628
8652 01:36:38.061808 Set Vref, RX VrefLevel [Byte0]: 70
8653 01:36:38.065509 [Byte1]: 70
8654 01:36:38.069466
8655 01:36:38.069925 Set Vref, RX VrefLevel [Byte0]: 71
8656 01:36:38.072708 [Byte1]: 71
8657 01:36:38.077317
8658 01:36:38.077896 Final RX Vref Byte 0 = 56 to rank0
8659 01:36:38.080471 Final RX Vref Byte 1 = 59 to rank0
8660 01:36:38.083836 Final RX Vref Byte 0 = 56 to rank1
8661 01:36:38.086824 Final RX Vref Byte 1 = 59 to rank1==
8662 01:36:38.090106 Dram Type= 6, Freq= 0, CH_1, rank 0
8663 01:36:38.096975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8664 01:36:38.097591 ==
8665 01:36:38.097965 DQS Delay:
8666 01:36:38.100261 DQS0 = 0, DQS1 = 0
8667 01:36:38.100819 DQM Delay:
8668 01:36:38.101184 DQM0 = 132, DQM1 = 127
8669 01:36:38.104009 DQ Delay:
8670 01:36:38.106605 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =132
8671 01:36:38.109944 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8672 01:36:38.113752 DQ8 =110, DQ9 =116, DQ10 =128, DQ11 =120
8673 01:36:38.116377 DQ12 =140, DQ13 =138, DQ14 =134, DQ15 =136
8674 01:36:38.116930
8675 01:36:38.117335
8676 01:36:38.117690
8677 01:36:38.119795 [DramC_TX_OE_Calibration] TA2
8678 01:36:38.123120 Original DQ_B0 (3 6) =30, OEN = 27
8679 01:36:38.126332 Original DQ_B1 (3 6) =30, OEN = 27
8680 01:36:38.129776 24, 0x0, End_B0=24 End_B1=24
8681 01:36:38.132968 25, 0x0, End_B0=25 End_B1=25
8682 01:36:38.133574 26, 0x0, End_B0=26 End_B1=26
8683 01:36:38.136405 27, 0x0, End_B0=27 End_B1=27
8684 01:36:38.140061 28, 0x0, End_B0=28 End_B1=28
8685 01:36:38.142985 29, 0x0, End_B0=29 End_B1=29
8686 01:36:38.143541 30, 0x0, End_B0=30 End_B1=30
8687 01:36:38.145986 31, 0x4141, End_B0=30 End_B1=30
8688 01:36:38.149454 Byte0 end_step=30 best_step=27
8689 01:36:38.152714 Byte1 end_step=30 best_step=27
8690 01:36:38.156051 Byte0 TX OE(2T, 0.5T) = (3, 3)
8691 01:36:38.159714 Byte1 TX OE(2T, 0.5T) = (3, 3)
8692 01:36:38.160274
8693 01:36:38.160687
8694 01:36:38.165834 [DQSOSCAuto] RK0, (LSB)MR18= 0x913, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8695 01:36:38.169335 CH1 RK0: MR19=303, MR18=913
8696 01:36:38.175986 CH1_RK0: MR19=0x303, MR18=0x913, DQSOSC=400, MR23=63, INC=23, DEC=15
8697 01:36:38.176555
8698 01:36:38.179460 ----->DramcWriteLeveling(PI) begin...
8699 01:36:38.179931 ==
8700 01:36:38.182525 Dram Type= 6, Freq= 0, CH_1, rank 1
8701 01:36:38.185805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 01:36:38.186309 ==
8703 01:36:38.188899 Write leveling (Byte 0): 23 => 23
8704 01:36:38.191944 Write leveling (Byte 1): 26 => 26
8705 01:36:38.195737 DramcWriteLeveling(PI) end<-----
8706 01:36:38.196253
8707 01:36:38.196587 ==
8708 01:36:38.198563 Dram Type= 6, Freq= 0, CH_1, rank 1
8709 01:36:38.202242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 01:36:38.205435 ==
8711 01:36:38.205946 [Gating] SW mode calibration
8712 01:36:38.215243 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8713 01:36:38.218487 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8714 01:36:38.221951 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8715 01:36:38.228911 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8716 01:36:38.231366 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8717 01:36:38.234932 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8718 01:36:38.241725 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8719 01:36:38.244941 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8720 01:36:38.248098 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8721 01:36:38.254485 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8722 01:36:38.257827 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8723 01:36:38.261738 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8724 01:36:38.268095 1 5 8 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
8725 01:36:38.271004 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8726 01:36:38.274506 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 01:36:38.281153 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 01:36:38.284845 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 01:36:38.287838 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 01:36:38.294256 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 01:36:38.297300 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8732 01:36:38.301412 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8733 01:36:38.307342 1 6 12 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8734 01:36:38.310567 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8735 01:36:38.314464 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 01:36:38.320648 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8737 01:36:38.324146 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8738 01:36:38.327470 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8739 01:36:38.334118 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8740 01:36:38.337481 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8741 01:36:38.340241 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8742 01:36:38.347242 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8743 01:36:38.349974 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 01:36:38.353646 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 01:36:38.360484 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 01:36:38.363780 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 01:36:38.369993 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 01:36:38.373347 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 01:36:38.376850 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 01:36:38.383072 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 01:36:38.386192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 01:36:38.389586 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 01:36:38.396021 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 01:36:38.399319 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 01:36:38.402495 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8756 01:36:38.409386 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8757 01:36:38.413022 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8758 01:36:38.416140 Total UI for P1: 0, mck2ui 16
8759 01:36:38.419530 best dqsien dly found for B0: ( 1, 9, 6)
8760 01:36:38.422427 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 01:36:38.425882 Total UI for P1: 0, mck2ui 16
8762 01:36:38.428967 best dqsien dly found for B1: ( 1, 9, 10)
8763 01:36:38.432360 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8764 01:36:38.435717 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8765 01:36:38.436244
8766 01:36:38.439054 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8767 01:36:38.446093 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8768 01:36:38.446661 [Gating] SW calibration Done
8769 01:36:38.449474 ==
8770 01:36:38.449936 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 01:36:38.455877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 01:36:38.456426 ==
8773 01:36:38.456794 RX Vref Scan: 0
8774 01:36:38.457246
8775 01:36:38.458612 RX Vref 0 -> 0, step: 1
8776 01:36:38.459077
8777 01:36:38.461998 RX Delay 0 -> 252, step: 8
8778 01:36:38.465059 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8779 01:36:38.468481 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8780 01:36:38.471725 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8781 01:36:38.478459 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8782 01:36:38.481587 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8783 01:36:38.485180 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8784 01:36:38.488165 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8785 01:36:38.491341 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8786 01:36:38.498367 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8787 01:36:38.501391 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8788 01:36:38.504800 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8789 01:36:38.508120 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8790 01:36:38.514901 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8791 01:36:38.518256 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8792 01:36:38.521157 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8793 01:36:38.524220 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8794 01:36:38.524719 ==
8795 01:36:38.527465 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 01:36:38.534097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 01:36:38.534521 ==
8798 01:36:38.534901 DQS Delay:
8799 01:36:38.537864 DQS0 = 0, DQS1 = 0
8800 01:36:38.538284 DQM Delay:
8801 01:36:38.538615 DQM0 = 133, DQM1 = 130
8802 01:36:38.540605 DQ Delay:
8803 01:36:38.544733 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =135
8804 01:36:38.547878 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8805 01:36:38.551083 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8806 01:36:38.554349 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8807 01:36:38.555059
8808 01:36:38.555450
8809 01:36:38.555789 ==
8810 01:36:38.557734 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 01:36:38.564119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 01:36:38.564682 ==
8813 01:36:38.565052
8814 01:36:38.565444
8815 01:36:38.565775 TX Vref Scan disable
8816 01:36:38.567265 == TX Byte 0 ==
8817 01:36:38.570634 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8818 01:36:38.577246 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8819 01:36:38.577696 == TX Byte 1 ==
8820 01:36:38.580398 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8821 01:36:38.587129 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8822 01:36:38.587635 ==
8823 01:36:38.590269 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 01:36:38.594327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 01:36:38.594841 ==
8826 01:36:38.606281
8827 01:36:38.609966 TX Vref early break, caculate TX vref
8828 01:36:38.612576 TX Vref=16, minBit 9, minWin=21, winSum=378
8829 01:36:38.616236 TX Vref=18, minBit 9, minWin=22, winSum=385
8830 01:36:38.619816 TX Vref=20, minBit 9, minWin=22, winSum=395
8831 01:36:38.622717 TX Vref=22, minBit 9, minWin=23, winSum=402
8832 01:36:38.626089 TX Vref=24, minBit 9, minWin=23, winSum=411
8833 01:36:38.632670 TX Vref=26, minBit 9, minWin=24, winSum=419
8834 01:36:38.635502 TX Vref=28, minBit 9, minWin=25, winSum=424
8835 01:36:38.639294 TX Vref=30, minBit 0, minWin=25, winSum=414
8836 01:36:38.643194 TX Vref=32, minBit 8, minWin=24, winSum=408
8837 01:36:38.645770 TX Vref=34, minBit 0, minWin=23, winSum=399
8838 01:36:38.652486 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
8839 01:36:38.653040
8840 01:36:38.655405 Final TX Range 0 Vref 28
8841 01:36:38.655870
8842 01:36:38.656234 ==
8843 01:36:38.659010 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 01:36:38.662162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 01:36:38.662722 ==
8846 01:36:38.663093
8847 01:36:38.663431
8848 01:36:38.665296 TX Vref Scan disable
8849 01:36:38.672312 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8850 01:36:38.672856 == TX Byte 0 ==
8851 01:36:38.674871 u2DelayCellOfst[0]=14 cells (4 PI)
8852 01:36:38.678848 u2DelayCellOfst[1]=10 cells (3 PI)
8853 01:36:38.681792 u2DelayCellOfst[2]=0 cells (0 PI)
8854 01:36:38.684963 u2DelayCellOfst[3]=7 cells (2 PI)
8855 01:36:38.688033 u2DelayCellOfst[4]=7 cells (2 PI)
8856 01:36:38.691925 u2DelayCellOfst[5]=17 cells (5 PI)
8857 01:36:38.695616 u2DelayCellOfst[6]=17 cells (5 PI)
8858 01:36:38.698005 u2DelayCellOfst[7]=7 cells (2 PI)
8859 01:36:38.701457 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8860 01:36:38.705008 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8861 01:36:38.708665 == TX Byte 1 ==
8862 01:36:38.711250 u2DelayCellOfst[8]=0 cells (0 PI)
8863 01:36:38.714640 u2DelayCellOfst[9]=3 cells (1 PI)
8864 01:36:38.717978 u2DelayCellOfst[10]=10 cells (3 PI)
8865 01:36:38.718446 u2DelayCellOfst[11]=3 cells (1 PI)
8866 01:36:38.721420 u2DelayCellOfst[12]=14 cells (4 PI)
8867 01:36:38.724586 u2DelayCellOfst[13]=14 cells (4 PI)
8868 01:36:38.727787 u2DelayCellOfst[14]=17 cells (5 PI)
8869 01:36:38.731457 u2DelayCellOfst[15]=17 cells (5 PI)
8870 01:36:38.737915 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8871 01:36:38.741354 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8872 01:36:38.741911 DramC Write-DBI on
8873 01:36:38.745117 ==
8874 01:36:38.747909 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 01:36:38.751186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 01:36:38.751655 ==
8877 01:36:38.752022
8878 01:36:38.752355
8879 01:36:38.754158 TX Vref Scan disable
8880 01:36:38.754619 == TX Byte 0 ==
8881 01:36:38.760865 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8882 01:36:38.761492 == TX Byte 1 ==
8883 01:36:38.764627 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8884 01:36:38.767775 DramC Write-DBI off
8885 01:36:38.768330
8886 01:36:38.768695 [DATLAT]
8887 01:36:38.771208 Freq=1600, CH1 RK1
8888 01:36:38.771673
8889 01:36:38.772036 DATLAT Default: 0xf
8890 01:36:38.773881 0, 0xFFFF, sum = 0
8891 01:36:38.774355 1, 0xFFFF, sum = 0
8892 01:36:38.777426 2, 0xFFFF, sum = 0
8893 01:36:38.777989 3, 0xFFFF, sum = 0
8894 01:36:38.780734 4, 0xFFFF, sum = 0
8895 01:36:38.781203 5, 0xFFFF, sum = 0
8896 01:36:38.783736 6, 0xFFFF, sum = 0
8897 01:36:38.786886 7, 0xFFFF, sum = 0
8898 01:36:38.787358 8, 0xFFFF, sum = 0
8899 01:36:38.790832 9, 0xFFFF, sum = 0
8900 01:36:38.791392 10, 0xFFFF, sum = 0
8901 01:36:38.793873 11, 0xFFFF, sum = 0
8902 01:36:38.794439 12, 0xFFFF, sum = 0
8903 01:36:38.797250 13, 0xFFFF, sum = 0
8904 01:36:38.797846 14, 0x0, sum = 1
8905 01:36:38.800190 15, 0x0, sum = 2
8906 01:36:38.800668 16, 0x0, sum = 3
8907 01:36:38.803874 17, 0x0, sum = 4
8908 01:36:38.804483 best_step = 15
8909 01:36:38.804856
8910 01:36:38.805194 ==
8911 01:36:38.806868 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 01:36:38.809972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 01:36:38.813662 ==
8914 01:36:38.814221 RX Vref Scan: 0
8915 01:36:38.814588
8916 01:36:38.816721 RX Vref 0 -> 0, step: 1
8917 01:36:38.817311
8918 01:36:38.820071 RX Delay 11 -> 252, step: 4
8919 01:36:38.823478 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8920 01:36:38.826289 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8921 01:36:38.830032 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8922 01:36:38.836698 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8923 01:36:38.839569 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8924 01:36:38.843056 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8925 01:36:38.846235 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8926 01:36:38.849423 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8927 01:36:38.855891 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8928 01:36:38.859299 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8929 01:36:38.862640 iDelay=195, Bit 10, Center 132 (79 ~ 186) 108
8930 01:36:38.865914 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8931 01:36:38.872411 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8932 01:36:38.876109 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8933 01:36:38.879445 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8934 01:36:38.882970 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8935 01:36:38.883390 ==
8936 01:36:38.885763 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 01:36:38.892652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 01:36:38.893171 ==
8939 01:36:38.893564 DQS Delay:
8940 01:36:38.895743 DQS0 = 0, DQS1 = 0
8941 01:36:38.896282 DQM Delay:
8942 01:36:38.896620 DQM0 = 130, DQM1 = 128
8943 01:36:38.898512 DQ Delay:
8944 01:36:38.902021 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
8945 01:36:38.905300 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
8946 01:36:38.908400 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8947 01:36:38.912166 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =136
8948 01:36:38.912588
8949 01:36:38.912920
8950 01:36:38.913227
8951 01:36:38.915337 [DramC_TX_OE_Calibration] TA2
8952 01:36:38.918488 Original DQ_B0 (3 6) =30, OEN = 27
8953 01:36:38.921967 Original DQ_B1 (3 6) =30, OEN = 27
8954 01:36:38.925218 24, 0x0, End_B0=24 End_B1=24
8955 01:36:38.928619 25, 0x0, End_B0=25 End_B1=25
8956 01:36:38.929137 26, 0x0, End_B0=26 End_B1=26
8957 01:36:38.932235 27, 0x0, End_B0=27 End_B1=27
8958 01:36:38.935484 28, 0x0, End_B0=28 End_B1=28
8959 01:36:38.938189 29, 0x0, End_B0=29 End_B1=29
8960 01:36:38.938615 30, 0x0, End_B0=30 End_B1=30
8961 01:36:38.941720 31, 0x4545, End_B0=30 End_B1=30
8962 01:36:38.945049 Byte0 end_step=30 best_step=27
8963 01:36:38.948787 Byte1 end_step=30 best_step=27
8964 01:36:38.951583 Byte0 TX OE(2T, 0.5T) = (3, 3)
8965 01:36:38.954992 Byte1 TX OE(2T, 0.5T) = (3, 3)
8966 01:36:38.955416
8967 01:36:38.955749
8968 01:36:38.961748 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8969 01:36:38.964860 CH1 RK1: MR19=303, MR18=101E
8970 01:36:38.971693 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
8971 01:36:38.974835 [RxdqsGatingPostProcess] freq 1600
8972 01:36:38.977848 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8973 01:36:38.981084 best DQS0 dly(2T, 0.5T) = (1, 1)
8974 01:36:38.984775 best DQS1 dly(2T, 0.5T) = (1, 1)
8975 01:36:38.987733 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8976 01:36:38.991376 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8977 01:36:38.994375 best DQS0 dly(2T, 0.5T) = (1, 1)
8978 01:36:38.997894 best DQS1 dly(2T, 0.5T) = (1, 1)
8979 01:36:39.001161 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8980 01:36:39.004035 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8981 01:36:39.007210 Pre-setting of DQS Precalculation
8982 01:36:39.010782 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8983 01:36:39.020414 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8984 01:36:39.027696 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8985 01:36:39.028135
8986 01:36:39.028465
8987 01:36:39.030951 [Calibration Summary] 3200 Mbps
8988 01:36:39.031479 CH 0, Rank 0
8989 01:36:39.033890 SW Impedance : PASS
8990 01:36:39.034312 DUTY Scan : NO K
8991 01:36:39.037093 ZQ Calibration : PASS
8992 01:36:39.040398 Jitter Meter : NO K
8993 01:36:39.040927 CBT Training : PASS
8994 01:36:39.043347 Write leveling : PASS
8995 01:36:39.046745 RX DQS gating : PASS
8996 01:36:39.047131 RX DQ/DQS(RDDQC) : PASS
8997 01:36:39.049978 TX DQ/DQS : PASS
8998 01:36:39.053739 RX DATLAT : PASS
8999 01:36:39.054159 RX DQ/DQS(Engine): PASS
9000 01:36:39.056508 TX OE : PASS
9001 01:36:39.057131 All Pass.
9002 01:36:39.057559
9003 01:36:39.060159 CH 0, Rank 1
9004 01:36:39.060577 SW Impedance : PASS
9005 01:36:39.063330 DUTY Scan : NO K
9006 01:36:39.067632 ZQ Calibration : PASS
9007 01:36:39.068147 Jitter Meter : NO K
9008 01:36:39.069924 CBT Training : PASS
9009 01:36:39.073255 Write leveling : PASS
9010 01:36:39.073704 RX DQS gating : PASS
9011 01:36:39.076510 RX DQ/DQS(RDDQC) : PASS
9012 01:36:39.079583 TX DQ/DQS : PASS
9013 01:36:39.080022 RX DATLAT : PASS
9014 01:36:39.083347 RX DQ/DQS(Engine): PASS
9015 01:36:39.086692 TX OE : PASS
9016 01:36:39.087174 All Pass.
9017 01:36:39.087565
9018 01:36:39.087875 CH 1, Rank 0
9019 01:36:39.089850 SW Impedance : PASS
9020 01:36:39.093116 DUTY Scan : NO K
9021 01:36:39.093577 ZQ Calibration : PASS
9022 01:36:39.097033 Jitter Meter : NO K
9023 01:36:39.099371 CBT Training : PASS
9024 01:36:39.099792 Write leveling : PASS
9025 01:36:39.103595 RX DQS gating : PASS
9026 01:36:39.106510 RX DQ/DQS(RDDQC) : PASS
9027 01:36:39.107049 TX DQ/DQS : PASS
9028 01:36:39.109394 RX DATLAT : PASS
9029 01:36:39.109812 RX DQ/DQS(Engine): PASS
9030 01:36:39.112841 TX OE : PASS
9031 01:36:39.113315 All Pass.
9032 01:36:39.113652
9033 01:36:39.116425 CH 1, Rank 1
9034 01:36:39.116947 SW Impedance : PASS
9035 01:36:39.119477 DUTY Scan : NO K
9036 01:36:39.122854 ZQ Calibration : PASS
9037 01:36:39.123295 Jitter Meter : NO K
9038 01:36:39.126035 CBT Training : PASS
9039 01:36:39.129093 Write leveling : PASS
9040 01:36:39.129655 RX DQS gating : PASS
9041 01:36:39.132386 RX DQ/DQS(RDDQC) : PASS
9042 01:36:39.135832 TX DQ/DQS : PASS
9043 01:36:39.136357 RX DATLAT : PASS
9044 01:36:39.138727 RX DQ/DQS(Engine): PASS
9045 01:36:39.142875 TX OE : PASS
9046 01:36:39.143439 All Pass.
9047 01:36:39.143788
9048 01:36:39.145978 DramC Write-DBI on
9049 01:36:39.146400 PER_BANK_REFRESH: Hybrid Mode
9050 01:36:39.148861 TX_TRACKING: ON
9051 01:36:39.158768 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9052 01:36:39.165977 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9053 01:36:39.171801 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 01:36:39.175452 [FAST_K] Save calibration result to emmc
9055 01:36:39.178842 sync common calibartion params.
9056 01:36:39.181568 sync cbt_mode0:1, 1:1
9057 01:36:39.181989 dram_init: ddr_geometry: 2
9058 01:36:39.185446 dram_init: ddr_geometry: 2
9059 01:36:39.188393 dram_init: ddr_geometry: 2
9060 01:36:39.191581 0:dram_rank_size:100000000
9061 01:36:39.192097 1:dram_rank_size:100000000
9062 01:36:39.198366 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9063 01:36:39.201790 DFS_SHUFFLE_HW_MODE: ON
9064 01:36:39.205330 dramc_set_vcore_voltage set vcore to 725000
9065 01:36:39.208333 Read voltage for 1600, 0
9066 01:36:39.208905 Vio18 = 0
9067 01:36:39.209248 Vcore = 725000
9068 01:36:39.211384 Vdram = 0
9069 01:36:39.211834 Vddq = 0
9070 01:36:39.212159 Vmddr = 0
9071 01:36:39.214773 switch to 3200 Mbps bootup
9072 01:36:39.215189 [DramcRunTimeConfig]
9073 01:36:39.218448 PHYPLL
9074 01:36:39.218867 DPM_CONTROL_AFTERK: ON
9075 01:36:39.221042 PER_BANK_REFRESH: ON
9076 01:36:39.224829 REFRESH_OVERHEAD_REDUCTION: ON
9077 01:36:39.225381 CMD_PICG_NEW_MODE: OFF
9078 01:36:39.227957 XRTWTW_NEW_MODE: ON
9079 01:36:39.228596 XRTRTR_NEW_MODE: ON
9080 01:36:39.231566 TX_TRACKING: ON
9081 01:36:39.231990 RDSEL_TRACKING: OFF
9082 01:36:39.235108 DQS Precalculation for DVFS: ON
9083 01:36:39.237733 RX_TRACKING: OFF
9084 01:36:39.238149 HW_GATING DBG: ON
9085 01:36:39.241099 ZQCS_ENABLE_LP4: ON
9086 01:36:39.241543 RX_PICG_NEW_MODE: ON
9087 01:36:39.244632 TX_PICG_NEW_MODE: ON
9088 01:36:39.247896 ENABLE_RX_DCM_DPHY: ON
9089 01:36:39.250876 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9090 01:36:39.251298 DUMMY_READ_FOR_TRACKING: OFF
9091 01:36:39.254581 !!! SPM_CONTROL_AFTERK: OFF
9092 01:36:39.257394 !!! SPM could not control APHY
9093 01:36:39.260533 IMPEDANCE_TRACKING: ON
9094 01:36:39.260952 TEMP_SENSOR: ON
9095 01:36:39.263852 HW_SAVE_FOR_SR: OFF
9096 01:36:39.264275 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9097 01:36:39.271039 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9098 01:36:39.271550 Read ODT Tracking: ON
9099 01:36:39.273857 Refresh Rate DeBounce: ON
9100 01:36:39.277403 DFS_NO_QUEUE_FLUSH: ON
9101 01:36:39.280922 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9102 01:36:39.281581 ENABLE_DFS_RUNTIME_MRW: OFF
9103 01:36:39.284174 DDR_RESERVE_NEW_MODE: ON
9104 01:36:39.286840 MR_CBT_SWITCH_FREQ: ON
9105 01:36:39.287260 =========================
9106 01:36:39.306872 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9107 01:36:39.310383 dram_init: ddr_geometry: 2
9108 01:36:39.329215 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9109 01:36:39.332140 dram_init: dram init end (result: 0)
9110 01:36:39.338560 DRAM-K: Full calibration passed in 24400 msecs
9111 01:36:39.342146 MRC: failed to locate region type 0.
9112 01:36:39.342704 DRAM rank0 size:0x100000000,
9113 01:36:39.345047 DRAM rank1 size=0x100000000
9114 01:36:39.354748 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9115 01:36:39.360890 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9116 01:36:39.371298 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9117 01:36:39.377862 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9118 01:36:39.378430 DRAM rank0 size:0x100000000,
9119 01:36:39.380982 DRAM rank1 size=0x100000000
9120 01:36:39.381489 CBMEM:
9121 01:36:39.384522 IMD: root @ 0xfffff000 254 entries.
9122 01:36:39.387678 IMD: root @ 0xffffec00 62 entries.
9123 01:36:39.394146 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9124 01:36:39.397888 WARNING: RO_VPD is uninitialized or empty.
9125 01:36:39.400561 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9126 01:36:39.408920 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9127 01:36:39.421898 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9128 01:36:39.432935 BS: romstage times (exec / console): total (unknown) / 23930 ms
9129 01:36:39.433541
9130 01:36:39.433903
9131 01:36:39.442501 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9132 01:36:39.446123 ARM64: Exception handlers installed.
9133 01:36:39.449337 ARM64: Testing exception
9134 01:36:39.452317 ARM64: Done test exception
9135 01:36:39.452779 Enumerating buses...
9136 01:36:39.455816 Show all devs... Before device enumeration.
9137 01:36:39.458583 Root Device: enabled 1
9138 01:36:39.461986 CPU_CLUSTER: 0: enabled 1
9139 01:36:39.462463 CPU: 00: enabled 1
9140 01:36:39.465536 Compare with tree...
9141 01:36:39.466088 Root Device: enabled 1
9142 01:36:39.468685 CPU_CLUSTER: 0: enabled 1
9143 01:36:39.472275 CPU: 00: enabled 1
9144 01:36:39.472832 Root Device scanning...
9145 01:36:39.475052 scan_static_bus for Root Device
9146 01:36:39.478785 CPU_CLUSTER: 0 enabled
9147 01:36:39.481724 scan_static_bus for Root Device done
9148 01:36:39.485421 scan_bus: bus Root Device finished in 8 msecs
9149 01:36:39.485887 done
9150 01:36:39.492151 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9151 01:36:39.495441 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9152 01:36:39.501986 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9153 01:36:39.508760 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9154 01:36:39.509356 Allocating resources...
9155 01:36:39.511815 Reading resources...
9156 01:36:39.514644 Root Device read_resources bus 0 link: 0
9157 01:36:39.518956 DRAM rank0 size:0x100000000,
9158 01:36:39.519513 DRAM rank1 size=0x100000000
9159 01:36:39.525042 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9160 01:36:39.525625 CPU: 00 missing read_resources
9161 01:36:39.531732 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9162 01:36:39.534853 Root Device read_resources bus 0 link: 0 done
9163 01:36:39.538574 Done reading resources.
9164 01:36:39.541658 Show resources in subtree (Root Device)...After reading.
9165 01:36:39.544974 Root Device child on link 0 CPU_CLUSTER: 0
9166 01:36:39.548127 CPU_CLUSTER: 0 child on link 0 CPU: 00
9167 01:36:39.557899 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9168 01:36:39.558480 CPU: 00
9169 01:36:39.564294 Root Device assign_resources, bus 0 link: 0
9170 01:36:39.568254 CPU_CLUSTER: 0 missing set_resources
9171 01:36:39.571240 Root Device assign_resources, bus 0 link: 0 done
9172 01:36:39.574667 Done setting resources.
9173 01:36:39.577453 Show resources in subtree (Root Device)...After assigning values.
9174 01:36:39.580821 Root Device child on link 0 CPU_CLUSTER: 0
9175 01:36:39.587563 CPU_CLUSTER: 0 child on link 0 CPU: 00
9176 01:36:39.594008 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9177 01:36:39.597316 CPU: 00
9178 01:36:39.597874 Done allocating resources.
9179 01:36:39.604520 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9180 01:36:39.605093 Enabling resources...
9181 01:36:39.607242 done.
9182 01:36:39.610486 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9183 01:36:39.613770 Initializing devices...
9184 01:36:39.614237 Root Device init
9185 01:36:39.617361 init hardware done!
9186 01:36:39.617943 0x00000018: ctrlr->caps
9187 01:36:39.620968 52.000 MHz: ctrlr->f_max
9188 01:36:39.624000 0.400 MHz: ctrlr->f_min
9189 01:36:39.626960 0x40ff8080: ctrlr->voltages
9190 01:36:39.627432 sclk: 390625
9191 01:36:39.627795 Bus Width = 1
9192 01:36:39.630636 sclk: 390625
9193 01:36:39.631197 Bus Width = 1
9194 01:36:39.633874 Early init status = 3
9195 01:36:39.636884 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9196 01:36:39.640806 in-header: 03 fc 00 00 01 00 00 00
9197 01:36:39.643978 in-data: 00
9198 01:36:39.647293 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9199 01:36:39.652370 in-header: 03 fd 00 00 00 00 00 00
9200 01:36:39.655934 in-data:
9201 01:36:39.658817 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9202 01:36:39.663624 in-header: 03 fc 00 00 01 00 00 00
9203 01:36:39.666810 in-data: 00
9204 01:36:39.670052 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9205 01:36:39.675938 in-header: 03 fd 00 00 00 00 00 00
9206 01:36:39.679113 in-data:
9207 01:36:39.682174 [SSUSB] Setting up USB HOST controller...
9208 01:36:39.685574 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9209 01:36:39.689021 [SSUSB] phy power-on done.
9210 01:36:39.692420 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9211 01:36:39.698876 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9212 01:36:39.702264 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9213 01:36:39.708608 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9214 01:36:39.714855 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9215 01:36:39.721757 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9216 01:36:39.728277 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9217 01:36:39.734916 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9218 01:36:39.738103 SPM: binary array size = 0x9dc
9219 01:36:39.744619 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9220 01:36:39.748114 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9221 01:36:39.757666 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9222 01:36:39.760830 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9223 01:36:39.764337 configure_display: Starting display init
9224 01:36:39.799234 anx7625_power_on_init: Init interface.
9225 01:36:39.802101 anx7625_disable_pd_protocol: Disabled PD feature.
9226 01:36:39.805758 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9227 01:36:39.833536 anx7625_start_dp_work: Secure OCM version=00
9228 01:36:39.837631 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9229 01:36:39.851760 sp_tx_get_edid_block: EDID Block = 1
9230 01:36:39.953942 Extracted contents:
9231 01:36:39.957255 header: 00 ff ff ff ff ff ff 00
9232 01:36:39.960768 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9233 01:36:39.963824 version: 01 04
9234 01:36:39.966975 basic params: 95 1f 11 78 0a
9235 01:36:39.970494 chroma info: 76 90 94 55 54 90 27 21 50 54
9236 01:36:39.973473 established: 00 00 00
9237 01:36:39.980658 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9238 01:36:39.986742 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9239 01:36:39.990044 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9240 01:36:39.997069 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9241 01:36:40.002927 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9242 01:36:40.006711 extensions: 00
9243 01:36:40.007172 checksum: fb
9244 01:36:40.007535
9245 01:36:40.012886 Manufacturer: IVO Model 57d Serial Number 0
9246 01:36:40.013348 Made week 0 of 2020
9247 01:36:40.016418 EDID version: 1.4
9248 01:36:40.016931 Digital display
9249 01:36:40.019449 6 bits per primary color channel
9250 01:36:40.022903 DisplayPort interface
9251 01:36:40.023416 Maximum image size: 31 cm x 17 cm
9252 01:36:40.026322 Gamma: 220%
9253 01:36:40.026882 Check DPMS levels
9254 01:36:40.033239 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9255 01:36:40.036598 First detailed timing is preferred timing
9256 01:36:40.039617 Established timings supported:
9257 01:36:40.040172 Standard timings supported:
9258 01:36:40.042940 Detailed timings
9259 01:36:40.046648 Hex of detail: 383680a07038204018303c0035ae10000019
9260 01:36:40.053364 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9261 01:36:40.055978 0780 0798 07c8 0820 hborder 0
9262 01:36:40.059532 0438 043b 0447 0458 vborder 0
9263 01:36:40.062544 -hsync -vsync
9264 01:36:40.063008 Did detailed timing
9265 01:36:40.069632 Hex of detail: 000000000000000000000000000000000000
9266 01:36:40.072857 Manufacturer-specified data, tag 0
9267 01:36:40.076326 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9268 01:36:40.079248 ASCII string: InfoVision
9269 01:36:40.082523 Hex of detail: 000000fe00523134304e574635205248200a
9270 01:36:40.085715 ASCII string: R140NWF5 RH
9271 01:36:40.086135 Checksum
9272 01:36:40.089339 Checksum: 0xfb (valid)
9273 01:36:40.092821 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9274 01:36:40.096043 DSI data_rate: 832800000 bps
9275 01:36:40.102582 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9276 01:36:40.105863 anx7625_parse_edid: pixelclock(138800).
9277 01:36:40.109098 hactive(1920), hsync(48), hfp(24), hbp(88)
9278 01:36:40.112598 vactive(1080), vsync(12), vfp(3), vbp(17)
9279 01:36:40.115364 anx7625_dsi_config: config dsi.
9280 01:36:40.122200 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9281 01:36:40.136111 anx7625_dsi_config: success to config DSI
9282 01:36:40.139455 anx7625_dp_start: MIPI phy setup OK.
9283 01:36:40.142819 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9284 01:36:40.145750 mtk_ddp_mode_set invalid vrefresh 60
9285 01:36:40.149506 main_disp_path_setup
9286 01:36:40.150061 ovl_layer_smi_id_en
9287 01:36:40.152517 ovl_layer_smi_id_en
9288 01:36:40.153125 ccorr_config
9289 01:36:40.153548 aal_config
9290 01:36:40.155737 gamma_config
9291 01:36:40.156293 postmask_config
9292 01:36:40.158722 dither_config
9293 01:36:40.161862 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9294 01:36:40.168938 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9295 01:36:40.171990 Root Device init finished in 554 msecs
9296 01:36:40.175185 CPU_CLUSTER: 0 init
9297 01:36:40.182071 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9298 01:36:40.189061 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9299 01:36:40.189698 APU_MBOX 0x190000b0 = 0x10001
9300 01:36:40.192538 APU_MBOX 0x190001b0 = 0x10001
9301 01:36:40.195642 APU_MBOX 0x190005b0 = 0x10001
9302 01:36:40.198733 APU_MBOX 0x190006b0 = 0x10001
9303 01:36:40.205379 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9304 01:36:40.214669 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9305 01:36:40.227875 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9306 01:36:40.233570 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9307 01:36:40.245382 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9308 01:36:40.254599 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9309 01:36:40.258335 CPU_CLUSTER: 0 init finished in 81 msecs
9310 01:36:40.261200 Devices initialized
9311 01:36:40.264637 Show all devs... After init.
9312 01:36:40.265363 Root Device: enabled 1
9313 01:36:40.267800 CPU_CLUSTER: 0: enabled 1
9314 01:36:40.271308 CPU: 00: enabled 1
9315 01:36:40.274847 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9316 01:36:40.277666 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9317 01:36:40.280823 ELOG: NV offset 0x57f000 size 0x1000
9318 01:36:40.287590 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9319 01:36:40.294444 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9320 01:36:40.297910 ELOG: Event(17) added with size 13 at 2024-06-05 01:36:40 UTC
9321 01:36:40.304499 out: cmd=0x121: 03 db 21 01 00 00 00 00
9322 01:36:40.307722 in-header: 03 e8 00 00 2c 00 00 00
9323 01:36:40.317627 in-data: 55 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 01:36:40.324425 ELOG: Event(A1) added with size 10 at 2024-06-05 01:36:40 UTC
9325 01:36:40.330639 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9326 01:36:40.337412 ELOG: Event(A0) added with size 9 at 2024-06-05 01:36:40 UTC
9327 01:36:40.340488 elog_add_boot_reason: Logged dev mode boot
9328 01:36:40.347871 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9329 01:36:40.348390 Finalize devices...
9330 01:36:40.350634 Devices finalized
9331 01:36:40.353670 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9332 01:36:40.357107 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9333 01:36:40.360670 in-header: 03 07 00 00 08 00 00 00
9334 01:36:40.363947 in-data: aa e4 47 04 13 02 00 00
9335 01:36:40.366977 Chrome EC: UHEPI supported
9336 01:36:40.373906 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9337 01:36:40.376904 in-header: 03 a9 00 00 08 00 00 00
9338 01:36:40.380490 in-data: 84 60 60 08 00 00 00 00
9339 01:36:40.386712 ELOG: Event(91) added with size 10 at 2024-06-05 01:36:40 UTC
9340 01:36:40.389891 Chrome EC: clear events_b mask to 0x0000000020004000
9341 01:36:40.396586 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9342 01:36:40.400380 in-header: 03 fd 00 00 00 00 00 00
9343 01:36:40.404531 in-data:
9344 01:36:40.407276 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9345 01:36:40.410350 Writing coreboot table at 0xffe64000
9346 01:36:40.417121 0. 000000000010a000-0000000000113fff: RAMSTAGE
9347 01:36:40.420291 1. 0000000040000000-00000000400fffff: RAM
9348 01:36:40.423654 2. 0000000040100000-000000004032afff: RAMSTAGE
9349 01:36:40.426944 3. 000000004032b000-00000000545fffff: RAM
9350 01:36:40.430548 4. 0000000054600000-000000005465ffff: BL31
9351 01:36:40.433496 5. 0000000054660000-00000000ffe63fff: RAM
9352 01:36:40.440701 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9353 01:36:40.443417 7. 0000000100000000-000000023fffffff: RAM
9354 01:36:40.446820 Passing 5 GPIOs to payload:
9355 01:36:40.450124 NAME | PORT | POLARITY | VALUE
9356 01:36:40.456591 EC in RW | 0x000000aa | low | undefined
9357 01:36:40.460190 EC interrupt | 0x00000005 | low | undefined
9358 01:36:40.466365 TPM interrupt | 0x000000ab | high | undefined
9359 01:36:40.469585 SD card detect | 0x00000011 | high | undefined
9360 01:36:40.472824 speaker enable | 0x00000093 | high | undefined
9361 01:36:40.479179 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9362 01:36:40.482913 in-header: 03 f9 00 00 02 00 00 00
9363 01:36:40.483466 in-data: 02 00
9364 01:36:40.486231 ADC[4]: Raw value=902955 ID=7
9365 01:36:40.489324 ADC[3]: Raw value=213916 ID=1
9366 01:36:40.489797 RAM Code: 0x71
9367 01:36:40.492750 ADC[6]: Raw value=75000 ID=0
9368 01:36:40.496204 ADC[5]: Raw value=213546 ID=1
9369 01:36:40.496720 SKU Code: 0x1
9370 01:36:40.502717 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8a58
9371 01:36:40.506057 coreboot table: 964 bytes.
9372 01:36:40.509512 IMD ROOT 0. 0xfffff000 0x00001000
9373 01:36:40.512946 IMD SMALL 1. 0xffffe000 0x00001000
9374 01:36:40.515791 RO MCACHE 2. 0xffffc000 0x00001104
9375 01:36:40.519874 CONSOLE 3. 0xfff7c000 0x00080000
9376 01:36:40.522217 FMAP 4. 0xfff7b000 0x00000452
9377 01:36:40.526259 TIME STAMP 5. 0xfff7a000 0x00000910
9378 01:36:40.529086 VBOOT WORK 6. 0xfff66000 0x00014000
9379 01:36:40.532350 RAMOOPS 7. 0xffe66000 0x00100000
9380 01:36:40.535185 COREBOOT 8. 0xffe64000 0x00002000
9381 01:36:40.535658 IMD small region:
9382 01:36:40.539244 IMD ROOT 0. 0xffffec00 0x00000400
9383 01:36:40.542789 VPD 1. 0xffffeb80 0x0000006c
9384 01:36:40.545317 MMC STATUS 2. 0xffffeb60 0x00000004
9385 01:36:40.552398 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9386 01:36:40.558401 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9387 01:36:40.597375 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9388 01:36:40.600592 Checking segment from ROM address 0x40100000
9389 01:36:40.604071 Checking segment from ROM address 0x4010001c
9390 01:36:40.610485 Loading segment from ROM address 0x40100000
9391 01:36:40.610915 code (compression=0)
9392 01:36:40.620653 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9393 01:36:40.627460 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9394 01:36:40.627968 it's not compressed!
9395 01:36:40.634032 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9396 01:36:40.640373 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9397 01:36:40.658175 Loading segment from ROM address 0x4010001c
9398 01:36:40.658691 Entry Point 0x80000000
9399 01:36:40.661126 Loaded segments
9400 01:36:40.664653 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9401 01:36:40.671007 Jumping to boot code at 0x80000000(0xffe64000)
9402 01:36:40.677375 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9403 01:36:40.684347 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9404 01:36:40.692184 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9405 01:36:40.696066 Checking segment from ROM address 0x40100000
9406 01:36:40.699132 Checking segment from ROM address 0x4010001c
9407 01:36:40.705753 Loading segment from ROM address 0x40100000
9408 01:36:40.706304 code (compression=1)
9409 01:36:40.712247 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9410 01:36:40.722055 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9411 01:36:40.722603 using LZMA
9412 01:36:40.730880 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9413 01:36:40.737549 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9414 01:36:40.741459 Loading segment from ROM address 0x4010001c
9415 01:36:40.744406 Entry Point 0x54601000
9416 01:36:40.744965 Loaded segments
9417 01:36:40.747572 NOTICE: MT8192 bl31_setup
9418 01:36:40.754301 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9419 01:36:40.758006 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9420 01:36:40.760838 WARNING: region 0:
9421 01:36:40.764365 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9422 01:36:40.764928 WARNING: region 1:
9423 01:36:40.770622 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9424 01:36:40.774717 WARNING: region 2:
9425 01:36:40.777833 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9426 01:36:40.780841 WARNING: region 3:
9427 01:36:40.787455 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9428 01:36:40.788019 WARNING: region 4:
9429 01:36:40.793893 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9430 01:36:40.794456 WARNING: region 5:
9431 01:36:40.797314 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 01:36:40.800410 WARNING: region 6:
9433 01:36:40.804348 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 01:36:40.807003 WARNING: region 7:
9435 01:36:40.810549 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9436 01:36:40.817122 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9437 01:36:40.820627 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9438 01:36:40.827174 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9439 01:36:40.830130 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9440 01:36:40.833536 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9441 01:36:40.839972 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9442 01:36:40.843320 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9443 01:36:40.846641 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9444 01:36:40.853346 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9445 01:36:40.856508 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9446 01:36:40.863261 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9447 01:36:40.866423 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9448 01:36:40.869995 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9449 01:36:40.877105 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9450 01:36:40.879535 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9451 01:36:40.886699 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9452 01:36:40.889362 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9453 01:36:40.892747 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9454 01:36:40.899257 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9455 01:36:40.902930 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9456 01:36:40.909431 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9457 01:36:40.912609 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9458 01:36:40.915897 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9459 01:36:40.922540 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9460 01:36:40.925783 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9461 01:36:40.932285 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9462 01:36:40.935506 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9463 01:36:40.939005 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9464 01:36:40.945702 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9465 01:36:40.948816 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9466 01:36:40.955038 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9467 01:36:40.958584 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9468 01:36:40.961658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9469 01:36:40.968113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9470 01:36:40.971434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9471 01:36:40.975052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9472 01:36:40.978366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9473 01:36:40.985396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9474 01:36:40.988452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9475 01:36:40.991784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9476 01:36:40.994688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9477 01:36:41.001419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9478 01:36:41.004673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9479 01:36:41.007962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9480 01:36:41.014306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9481 01:36:41.017382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9482 01:36:41.021011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9483 01:36:41.024560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9484 01:36:41.030667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9485 01:36:41.034285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9486 01:36:41.040351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9487 01:36:41.044418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9488 01:36:41.050568 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9489 01:36:41.053709 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9490 01:36:41.060200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9491 01:36:41.063371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9492 01:36:41.066776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9493 01:36:41.073243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9494 01:36:41.077297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9495 01:36:41.083344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9496 01:36:41.086808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9497 01:36:41.093342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9498 01:36:41.096566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9499 01:36:41.103850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9500 01:36:41.106428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9501 01:36:41.109882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9502 01:36:41.116319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9503 01:36:41.119664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9504 01:36:41.126228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9505 01:36:41.129727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9506 01:36:41.136360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9507 01:36:41.139557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9508 01:36:41.145958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9509 01:36:41.149657 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9510 01:36:41.152850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9511 01:36:41.159431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9512 01:36:41.162467 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9513 01:36:41.169203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9514 01:36:41.172384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9515 01:36:41.179184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9516 01:36:41.182443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9517 01:36:41.189162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9518 01:36:41.192358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9519 01:36:41.195639 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9520 01:36:41.201975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9521 01:36:41.205615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9522 01:36:41.212043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9523 01:36:41.215091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9524 01:36:41.222211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9525 01:36:41.224918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9526 01:36:41.231962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9527 01:36:41.235050 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9528 01:36:41.241556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9529 01:36:41.244923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9530 01:36:41.248473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9531 01:36:41.254704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9532 01:36:41.258180 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9533 01:36:41.260959 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9534 01:36:41.267874 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9535 01:36:41.271034 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9536 01:36:41.274215 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9537 01:36:41.280827 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9538 01:36:41.284407 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9539 01:36:41.290804 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9540 01:36:41.294241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9541 01:36:41.297960 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9542 01:36:41.304354 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9543 01:36:41.308345 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9544 01:36:41.313797 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9545 01:36:41.317083 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9546 01:36:41.320787 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9547 01:36:41.326965 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9548 01:36:41.330298 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9549 01:36:41.337335 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9550 01:36:41.340370 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9551 01:36:41.344398 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9552 01:36:41.350286 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9553 01:36:41.353938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9554 01:36:41.356870 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9555 01:36:41.363167 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9556 01:36:41.366885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9557 01:36:41.369957 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9558 01:36:41.373379 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9559 01:36:41.379946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9560 01:36:41.383051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9561 01:36:41.389478 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9562 01:36:41.392805 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9563 01:36:41.396932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9564 01:36:41.402727 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9565 01:36:41.406348 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9566 01:36:41.412966 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9567 01:36:41.415881 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9568 01:36:41.419018 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9569 01:36:41.425888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9570 01:36:41.428765 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9571 01:36:41.435950 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9572 01:36:41.438866 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9573 01:36:41.442179 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9574 01:36:41.448644 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9575 01:36:41.451740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9576 01:36:41.458632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9577 01:36:41.461884 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9578 01:36:41.465166 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9579 01:36:41.471714 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9580 01:36:41.475296 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9581 01:36:41.481637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9582 01:36:41.485765 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9583 01:36:41.488121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9584 01:36:41.495282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9585 01:36:41.498344 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9586 01:36:41.504724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9587 01:36:41.507905 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9588 01:36:41.511492 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9589 01:36:41.517559 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9590 01:36:41.521319 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9591 01:36:41.527451 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9592 01:36:41.530677 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9593 01:36:41.534679 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9594 01:36:41.540735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9595 01:36:41.544623 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9596 01:36:41.550762 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9597 01:36:41.554348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9598 01:36:41.557577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9599 01:36:41.564118 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9600 01:36:41.567097 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9601 01:36:41.573777 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9602 01:36:41.576711 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9603 01:36:41.580764 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9604 01:36:41.586686 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9605 01:36:41.590239 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9606 01:36:41.596740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9607 01:36:41.600156 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9608 01:36:41.602930 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9609 01:36:41.610604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9610 01:36:41.613526 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9611 01:36:41.620302 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9612 01:36:41.623242 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9613 01:36:41.627165 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9614 01:36:41.633292 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9615 01:36:41.636274 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9616 01:36:41.643132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9617 01:36:41.645991 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9618 01:36:41.649805 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9619 01:36:41.656253 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9620 01:36:41.659451 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9621 01:36:41.665721 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9622 01:36:41.669235 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9623 01:36:41.672669 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9624 01:36:41.679426 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9625 01:36:41.682808 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9626 01:36:41.689114 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9627 01:36:41.692619 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9628 01:36:41.699192 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9629 01:36:41.702446 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9630 01:36:41.705709 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9631 01:36:41.712586 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9632 01:36:41.715888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9633 01:36:41.722722 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9634 01:36:41.725492 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9635 01:36:41.731879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9636 01:36:41.735340 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9637 01:36:41.738475 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9638 01:36:41.745380 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9639 01:36:41.748468 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9640 01:36:41.754799 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9641 01:36:41.758524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9642 01:36:41.764952 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9643 01:36:41.768459 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9644 01:36:41.771887 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9645 01:36:41.777784 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9646 01:36:41.781371 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9647 01:36:41.787791 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9648 01:36:41.791139 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9649 01:36:41.797806 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9650 01:36:41.801159 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9651 01:36:41.804367 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9652 01:36:41.811306 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9653 01:36:41.813936 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9654 01:36:41.820699 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9655 01:36:41.823874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9656 01:36:41.830383 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9657 01:36:41.833917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9658 01:36:41.836884 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9659 01:36:41.844313 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9660 01:36:41.846746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9661 01:36:41.853413 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9662 01:36:41.857064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9663 01:36:41.863545 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9664 01:36:41.866649 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9665 01:36:41.870118 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9666 01:36:41.876873 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9667 01:36:41.880000 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9668 01:36:41.883629 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9669 01:36:41.886810 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9670 01:36:41.893459 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9671 01:36:41.896247 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9672 01:36:41.899628 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9673 01:36:41.906266 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9674 01:36:41.909889 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9675 01:36:41.912934 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9676 01:36:41.919296 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9677 01:36:41.923079 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9678 01:36:41.929951 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9679 01:36:41.933291 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9680 01:36:41.936214 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9681 01:36:41.942567 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9682 01:36:41.945807 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9683 01:36:41.952861 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9684 01:36:41.956155 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9685 01:36:41.959294 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9686 01:36:41.965837 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9687 01:36:41.969053 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9688 01:36:41.972274 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9689 01:36:41.978730 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9690 01:36:41.982279 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9691 01:36:41.988346 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9692 01:36:41.992801 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9693 01:36:41.995506 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9694 01:36:42.001699 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9695 01:36:42.005596 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9696 01:36:42.008126 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9697 01:36:42.015360 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9698 01:36:42.018170 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9699 01:36:42.021504 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9700 01:36:42.028546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9701 01:36:42.031799 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9702 01:36:42.038647 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9703 01:36:42.041458 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9704 01:36:42.044830 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9705 01:36:42.051266 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9706 01:36:42.054891 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9707 01:36:42.057639 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9708 01:36:42.061385 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9709 01:36:42.064353 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9710 01:36:42.070785 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9711 01:36:42.074073 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9712 01:36:42.077024 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9713 01:36:42.083653 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9714 01:36:42.087012 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9715 01:36:42.090649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9716 01:36:42.097373 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9717 01:36:42.101019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9718 01:36:42.103836 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9719 01:36:42.110961 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9720 01:36:42.114077 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9721 01:36:42.119660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9722 01:36:42.123533 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9723 01:36:42.126529 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9724 01:36:42.133071 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9725 01:36:42.136742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9726 01:36:42.143071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9727 01:36:42.146570 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9728 01:36:42.153391 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9729 01:36:42.156442 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9730 01:36:42.159691 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9731 01:36:42.166596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9732 01:36:42.169418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9733 01:36:42.175883 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9734 01:36:42.179528 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9735 01:36:42.182637 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9736 01:36:42.189052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9737 01:36:42.192484 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9738 01:36:42.199002 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9739 01:36:42.202675 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9740 01:36:42.208573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9741 01:36:42.212575 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9742 01:36:42.215650 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9743 01:36:42.222164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9744 01:36:42.225610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9745 01:36:42.232083 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9746 01:36:42.235455 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9747 01:36:42.242232 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9748 01:36:42.244950 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9749 01:36:42.248363 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9750 01:36:42.254826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9751 01:36:42.258126 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9752 01:36:42.265218 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9753 01:36:42.268336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9754 01:36:42.274401 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9755 01:36:42.278438 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9756 01:36:42.281565 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9757 01:36:42.288115 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9758 01:36:42.291327 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9759 01:36:42.297420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9760 01:36:42.301316 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9761 01:36:42.304125 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9762 01:36:42.310920 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9763 01:36:42.314220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9764 01:36:42.320431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9765 01:36:42.324122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9766 01:36:42.327368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9767 01:36:42.334340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9768 01:36:42.337123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9769 01:36:42.343662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9770 01:36:42.347478 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9771 01:36:42.353668 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9772 01:36:42.357364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9773 01:36:42.360237 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9774 01:36:42.366604 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9775 01:36:42.370038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9776 01:36:42.376302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9777 01:36:42.379695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9778 01:36:42.386296 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9779 01:36:42.389581 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9780 01:36:42.392554 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9781 01:36:42.399406 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9782 01:36:42.402728 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9783 01:36:42.409189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9784 01:36:42.412754 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9785 01:36:42.419272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9786 01:36:42.422713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9787 01:36:42.425881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9788 01:36:42.432789 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9789 01:36:42.435597 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9790 01:36:42.442838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9791 01:36:42.446078 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9792 01:36:42.449177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9793 01:36:42.455683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9794 01:36:42.458774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9795 01:36:42.465588 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9796 01:36:42.469067 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9797 01:36:42.475489 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9798 01:36:42.478620 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9799 01:36:42.484946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9800 01:36:42.488616 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9801 01:36:42.495046 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9802 01:36:42.498452 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9803 01:36:42.502443 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9804 01:36:42.508287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9805 01:36:42.511925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9806 01:36:42.518170 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9807 01:36:42.521469 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9808 01:36:42.528382 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9809 01:36:42.531487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9810 01:36:42.535017 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9811 01:36:42.541754 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9812 01:36:42.544822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9813 01:36:42.551721 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9814 01:36:42.554822 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9815 01:36:42.561716 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9816 01:36:42.564471 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9817 01:36:42.571038 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9818 01:36:42.574496 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9819 01:36:42.577725 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9820 01:36:42.584647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9821 01:36:42.588230 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9822 01:36:42.594259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9823 01:36:42.598036 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9824 01:36:42.604533 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9825 01:36:42.607697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9826 01:36:42.614029 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9827 01:36:42.617182 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9828 01:36:42.620801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9829 01:36:42.627628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9830 01:36:42.630785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9831 01:36:42.637468 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9832 01:36:42.640597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9833 01:36:42.647068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9834 01:36:42.650188 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9835 01:36:42.657205 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9836 01:36:42.659880 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9837 01:36:42.663817 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9838 01:36:42.669940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9839 01:36:42.673416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9840 01:36:42.680545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9841 01:36:42.683298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9842 01:36:42.690112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9843 01:36:42.693220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9844 01:36:42.699624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9845 01:36:42.703250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9846 01:36:42.709474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9847 01:36:42.713223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9848 01:36:42.719621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9849 01:36:42.722614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9850 01:36:42.728892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9851 01:36:42.732577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9852 01:36:42.738973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9853 01:36:42.742269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9854 01:36:42.748802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9855 01:36:42.752114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9856 01:36:42.759058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9857 01:36:42.761947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9858 01:36:42.768616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9859 01:36:42.772012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9860 01:36:42.778518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9861 01:36:42.781800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9862 01:36:42.788408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9863 01:36:42.791441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9864 01:36:42.798045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9865 01:36:42.801248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9866 01:36:42.808119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9867 01:36:42.811201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9868 01:36:42.817991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9869 01:36:42.821318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9870 01:36:42.827665 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9871 01:36:42.828091 INFO: [APUAPC] vio 0
9872 01:36:42.834733 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9873 01:36:42.837837 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9874 01:36:42.840904 INFO: [APUAPC] D0_APC_0: 0x400510
9875 01:36:42.844427 INFO: [APUAPC] D0_APC_1: 0x0
9876 01:36:42.847573 INFO: [APUAPC] D0_APC_2: 0x1540
9877 01:36:42.850742 INFO: [APUAPC] D0_APC_3: 0x0
9878 01:36:42.854819 INFO: [APUAPC] D1_APC_0: 0xffffffff
9879 01:36:42.857210 INFO: [APUAPC] D1_APC_1: 0xffffffff
9880 01:36:42.860450 INFO: [APUAPC] D1_APC_2: 0x3fffff
9881 01:36:42.864788 INFO: [APUAPC] D1_APC_3: 0x0
9882 01:36:42.867124 INFO: [APUAPC] D2_APC_0: 0xffffffff
9883 01:36:42.870197 INFO: [APUAPC] D2_APC_1: 0xffffffff
9884 01:36:42.874076 INFO: [APUAPC] D2_APC_2: 0x3fffff
9885 01:36:42.877411 INFO: [APUAPC] D2_APC_3: 0x0
9886 01:36:42.880594 INFO: [APUAPC] D3_APC_0: 0xffffffff
9887 01:36:42.883648 INFO: [APUAPC] D3_APC_1: 0xffffffff
9888 01:36:42.887467 INFO: [APUAPC] D3_APC_2: 0x3fffff
9889 01:36:42.890353 INFO: [APUAPC] D3_APC_3: 0x0
9890 01:36:42.893374 INFO: [APUAPC] D4_APC_0: 0xffffffff
9891 01:36:42.896867 INFO: [APUAPC] D4_APC_1: 0xffffffff
9892 01:36:42.900262 INFO: [APUAPC] D4_APC_2: 0x3fffff
9893 01:36:42.903496 INFO: [APUAPC] D4_APC_3: 0x0
9894 01:36:42.907213 INFO: [APUAPC] D5_APC_0: 0xffffffff
9895 01:36:42.909776 INFO: [APUAPC] D5_APC_1: 0xffffffff
9896 01:36:42.913883 INFO: [APUAPC] D5_APC_2: 0x3fffff
9897 01:36:42.916937 INFO: [APUAPC] D5_APC_3: 0x0
9898 01:36:42.920219 INFO: [APUAPC] D6_APC_0: 0xffffffff
9899 01:36:42.923267 INFO: [APUAPC] D6_APC_1: 0xffffffff
9900 01:36:42.926780 INFO: [APUAPC] D6_APC_2: 0x3fffff
9901 01:36:42.929671 INFO: [APUAPC] D6_APC_3: 0x0
9902 01:36:42.933701 INFO: [APUAPC] D7_APC_0: 0xffffffff
9903 01:36:42.936339 INFO: [APUAPC] D7_APC_1: 0xffffffff
9904 01:36:42.939616 INFO: [APUAPC] D7_APC_2: 0x3fffff
9905 01:36:42.940136 INFO: [APUAPC] D7_APC_3: 0x0
9906 01:36:42.946267 INFO: [APUAPC] D8_APC_0: 0xffffffff
9907 01:36:42.949717 INFO: [APUAPC] D8_APC_1: 0xffffffff
9908 01:36:42.953040 INFO: [APUAPC] D8_APC_2: 0x3fffff
9909 01:36:42.953674 INFO: [APUAPC] D8_APC_3: 0x0
9910 01:36:42.956129 INFO: [APUAPC] D9_APC_0: 0xffffffff
9911 01:36:42.962722 INFO: [APUAPC] D9_APC_1: 0xffffffff
9912 01:36:42.966239 INFO: [APUAPC] D9_APC_2: 0x3fffff
9913 01:36:42.966668 INFO: [APUAPC] D9_APC_3: 0x0
9914 01:36:42.969187 INFO: [APUAPC] D10_APC_0: 0xffffffff
9915 01:36:42.976333 INFO: [APUAPC] D10_APC_1: 0xffffffff
9916 01:36:42.979247 INFO: [APUAPC] D10_APC_2: 0x3fffff
9917 01:36:42.979676 INFO: [APUAPC] D10_APC_3: 0x0
9918 01:36:42.986057 INFO: [APUAPC] D11_APC_0: 0xffffffff
9919 01:36:42.989574 INFO: [APUAPC] D11_APC_1: 0xffffffff
9920 01:36:42.992283 INFO: [APUAPC] D11_APC_2: 0x3fffff
9921 01:36:42.992806 INFO: [APUAPC] D11_APC_3: 0x0
9922 01:36:42.999348 INFO: [APUAPC] D12_APC_0: 0xffffffff
9923 01:36:43.002326 INFO: [APUAPC] D12_APC_1: 0xffffffff
9924 01:36:43.005783 INFO: [APUAPC] D12_APC_2: 0x3fffff
9925 01:36:43.008664 INFO: [APUAPC] D12_APC_3: 0x0
9926 01:36:43.012288 INFO: [APUAPC] D13_APC_0: 0xffffffff
9927 01:36:43.015779 INFO: [APUAPC] D13_APC_1: 0xffffffff
9928 01:36:43.018425 INFO: [APUAPC] D13_APC_2: 0x3fffff
9929 01:36:43.021963 INFO: [APUAPC] D13_APC_3: 0x0
9930 01:36:43.025161 INFO: [APUAPC] D14_APC_0: 0xffffffff
9931 01:36:43.028741 INFO: [APUAPC] D14_APC_1: 0xffffffff
9932 01:36:43.032194 INFO: [APUAPC] D14_APC_2: 0x3fffff
9933 01:36:43.034995 INFO: [APUAPC] D14_APC_3: 0x0
9934 01:36:43.039414 INFO: [APUAPC] D15_APC_0: 0xffffffff
9935 01:36:43.042135 INFO: [APUAPC] D15_APC_1: 0xffffffff
9936 01:36:43.045816 INFO: [APUAPC] D15_APC_2: 0x3fffff
9937 01:36:43.048234 INFO: [APUAPC] D15_APC_3: 0x0
9938 01:36:43.051745 INFO: [APUAPC] APC_CON: 0x4
9939 01:36:43.052264 INFO: [NOCDAPC] D0_APC_0: 0x0
9940 01:36:43.055322 INFO: [NOCDAPC] D0_APC_1: 0x0
9941 01:36:43.058207 INFO: [NOCDAPC] D1_APC_0: 0x0
9942 01:36:43.061714 INFO: [NOCDAPC] D1_APC_1: 0xfff
9943 01:36:43.065319 INFO: [NOCDAPC] D2_APC_0: 0x0
9944 01:36:43.067740 INFO: [NOCDAPC] D2_APC_1: 0xfff
9945 01:36:43.071169 INFO: [NOCDAPC] D3_APC_0: 0x0
9946 01:36:43.074674 INFO: [NOCDAPC] D3_APC_1: 0xfff
9947 01:36:43.077921 INFO: [NOCDAPC] D4_APC_0: 0x0
9948 01:36:43.081156 INFO: [NOCDAPC] D4_APC_1: 0xfff
9949 01:36:43.084695 INFO: [NOCDAPC] D5_APC_0: 0x0
9950 01:36:43.087709 INFO: [NOCDAPC] D5_APC_1: 0xfff
9951 01:36:43.088138 INFO: [NOCDAPC] D6_APC_0: 0x0
9952 01:36:43.091124 INFO: [NOCDAPC] D6_APC_1: 0xfff
9953 01:36:43.094566 INFO: [NOCDAPC] D7_APC_0: 0x0
9954 01:36:43.097615 INFO: [NOCDAPC] D7_APC_1: 0xfff
9955 01:36:43.100667 INFO: [NOCDAPC] D8_APC_0: 0x0
9956 01:36:43.104211 INFO: [NOCDAPC] D8_APC_1: 0xfff
9957 01:36:43.107630 INFO: [NOCDAPC] D9_APC_0: 0x0
9958 01:36:43.110433 INFO: [NOCDAPC] D9_APC_1: 0xfff
9959 01:36:43.114110 INFO: [NOCDAPC] D10_APC_0: 0x0
9960 01:36:43.116977 INFO: [NOCDAPC] D10_APC_1: 0xfff
9961 01:36:43.120621 INFO: [NOCDAPC] D11_APC_0: 0x0
9962 01:36:43.124215 INFO: [NOCDAPC] D11_APC_1: 0xfff
9963 01:36:43.127176 INFO: [NOCDAPC] D12_APC_0: 0x0
9964 01:36:43.131000 INFO: [NOCDAPC] D12_APC_1: 0xfff
9965 01:36:43.131515 INFO: [NOCDAPC] D13_APC_0: 0x0
9966 01:36:43.133978 INFO: [NOCDAPC] D13_APC_1: 0xfff
9967 01:36:43.137530 INFO: [NOCDAPC] D14_APC_0: 0x0
9968 01:36:43.140591 INFO: [NOCDAPC] D14_APC_1: 0xfff
9969 01:36:43.144022 INFO: [NOCDAPC] D15_APC_0: 0x0
9970 01:36:43.146995 INFO: [NOCDAPC] D15_APC_1: 0xfff
9971 01:36:43.150502 INFO: [NOCDAPC] APC_CON: 0x4
9972 01:36:43.154071 INFO: [APUAPC] set_apusys_apc done
9973 01:36:43.156924 INFO: [DEVAPC] devapc_init done
9974 01:36:43.160007 INFO: GICv3 without legacy support detected.
9975 01:36:43.166741 INFO: ARM GICv3 driver initialized in EL3
9976 01:36:43.170032 INFO: Maximum SPI INTID supported: 639
9977 01:36:43.173440 INFO: BL31: Initializing runtime services
9978 01:36:43.179747 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9979 01:36:43.180318 INFO: SPM: enable CPC mode
9980 01:36:43.186473 INFO: mcdi ready for mcusys-off-idle and system suspend
9981 01:36:43.190216 INFO: BL31: Preparing for EL3 exit to normal world
9982 01:36:43.196690 INFO: Entry point address = 0x80000000
9983 01:36:43.197250 INFO: SPSR = 0x8
9984 01:36:43.202678
9985 01:36:43.203236
9986 01:36:43.203612
9987 01:36:43.205915 Starting depthcharge on Spherion...
9988 01:36:43.206384
9989 01:36:43.206924 Wipe memory regions:
9990 01:36:43.207346
9991 01:36:43.209730 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
9992 01:36:43.210258 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
9993 01:36:43.210698 Setting prompt string to ['asurada:']
9994 01:36:43.211133 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
9995 01:36:43.211851 [0x00000040000000, 0x00000054600000)
9996 01:36:43.331626
9997 01:36:43.332185 [0x00000054660000, 0x00000080000000)
9998 01:36:43.591472
9999 01:36:43.592026 [0x000000821a7280, 0x000000ffe64000)
10000 01:36:44.335857
10001 01:36:44.336415 [0x00000100000000, 0x00000240000000)
10002 01:36:46.224080
10003 01:36:46.227314 Initializing XHCI USB controller at 0x11200000.
10004 01:36:47.265754
10005 01:36:47.268705 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10006 01:36:47.269170
10007 01:36:47.269591
10008 01:36:47.270397 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10010 01:36:47.371745 asurada: tftpboot 192.168.201.1 14173516/tftp-deploy-pbvb5vjh/kernel/image.itb 14173516/tftp-deploy-pbvb5vjh/kernel/cmdline
10011 01:36:47.372502 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10012 01:36:47.372954 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10013 01:36:47.377483 tftpboot 192.168.201.1 14173516/tftp-deploy-pbvb5vjh/kernel/image.ittp-deploy-pbvb5vjh/kernel/cmdline
10014 01:36:47.377988
10015 01:36:47.378359 Waiting for link
10016 01:36:47.535998
10017 01:36:47.536560 R8152: Initializing
10018 01:36:47.536933
10019 01:36:47.539297 Version 6 (ocp_data = 5c30)
10020 01:36:47.539872
10021 01:36:47.542693 R8152: Done initializing
10022 01:36:47.543256
10023 01:36:47.543624 Adding net device
10024 01:36:49.412376
10025 01:36:49.412924 done.
10026 01:36:49.413351
10027 01:36:49.413706 MAC: 00:24:32:30:7c:7b
10028 01:36:49.414040
10029 01:36:49.415489 Sending DHCP discover... done.
10030 01:36:49.416164
10031 01:36:59.894954 Waiting for reply... R8152: Bulk read error 0xffffffbf
10032 01:36:59.895605
10033 01:36:59.898209 Receive failed.
10034 01:36:59.898693
10035 01:36:59.899064 done.
10036 01:36:59.899404
10037 01:36:59.901697 Sending DHCP request... done.
10038 01:36:59.902157
10039 01:36:59.908552 Waiting for reply... done.
10040 01:36:59.909114
10041 01:36:59.909559 My ip is 192.168.201.14
10042 01:36:59.909910
10043 01:36:59.912182 The DHCP server ip is 192.168.201.1
10044 01:36:59.912739
10045 01:36:59.918748 TFTP server IP predefined by user: 192.168.201.1
10046 01:36:59.919354
10047 01:36:59.925923 Bootfile predefined by user: 14173516/tftp-deploy-pbvb5vjh/kernel/image.itb
10048 01:36:59.926488
10049 01:36:59.928333 Sending tftp read request... done.
10050 01:36:59.928793
10051 01:36:59.935694 Waiting for the transfer...
10052 01:36:59.936361
10053 01:37:00.624026 00000000 ################################################################
10054 01:37:00.624563
10055 01:37:01.353811 00080000 ################################################################
10056 01:37:01.354345
10057 01:37:02.052566 00100000 ################################################################
10058 01:37:02.053079
10059 01:37:02.733827 00180000 ################################################################
10060 01:37:02.734338
10061 01:37:03.407247 00200000 ################################################################
10062 01:37:03.407765
10063 01:37:04.071050 00280000 ################################################################
10064 01:37:04.071632
10065 01:37:04.757127 00300000 ################################################################
10066 01:37:04.757687
10067 01:37:05.440515 00380000 ################################################################
10068 01:37:05.441196
10069 01:37:06.136856 00400000 ################################################################
10070 01:37:06.137558
10071 01:37:06.839478 00480000 ################################################################
10072 01:37:06.840025
10073 01:37:07.560025 00500000 ################################################################
10074 01:37:07.560566
10075 01:37:08.256572 00580000 ################################################################
10076 01:37:08.256959
10077 01:37:08.873558 00600000 ################################################################
10078 01:37:08.873796
10079 01:37:09.566962 00680000 ################################################################
10080 01:37:09.567658
10081 01:37:10.256100 00700000 ################################################################
10082 01:37:10.256649
10083 01:37:10.924283 00780000 ################################################################
10084 01:37:10.924433
10085 01:37:11.488331 00800000 ################################################################
10086 01:37:11.488481
10087 01:37:12.101581 00880000 ################################################################
10088 01:37:12.102092
10089 01:37:12.798289 00900000 ################################################################
10090 01:37:12.798805
10091 01:37:13.499182 00980000 ################################################################
10092 01:37:13.499795
10093 01:37:14.204869 00a00000 ################################################################
10094 01:37:14.205426
10095 01:37:14.904576 00a80000 ################################################################
10096 01:37:14.905091
10097 01:37:15.586460 00b00000 ################################################################
10098 01:37:15.586987
10099 01:37:16.265942 00b80000 ################################################################
10100 01:37:16.266477
10101 01:37:16.949378 00c00000 ################################################################
10102 01:37:16.949887
10103 01:37:17.657674 00c80000 ################################################################
10104 01:37:17.658184
10105 01:37:18.355594 00d00000 ################################################################
10106 01:37:18.356108
10107 01:37:19.061839 00d80000 ################################################################
10108 01:37:19.062352
10109 01:37:19.770682 00e00000 ################################################################
10110 01:37:19.771202
10111 01:37:20.467086 00e80000 ################################################################
10112 01:37:20.467637
10113 01:37:21.160876 00f00000 ################################################################
10114 01:37:21.161427
10115 01:37:21.842292 00f80000 ################################################################
10116 01:37:21.842829
10117 01:37:22.520348 01000000 ################################################################
10118 01:37:22.520864
10119 01:37:23.192746 01080000 ################################################################
10120 01:37:23.193294
10121 01:37:23.902223 01100000 ################################################################
10122 01:37:23.902765
10123 01:37:24.577220 01180000 ################################################################
10124 01:37:24.577769
10125 01:37:25.253139 01200000 ################################################################
10126 01:37:25.253706
10127 01:37:25.934477 01280000 ################################################################
10128 01:37:25.935015
10129 01:37:26.638022 01300000 ################################################################
10130 01:37:26.638557
10131 01:37:27.325775 01380000 ################################################################
10132 01:37:27.326396
10133 01:37:28.025006 01400000 ################################################################
10134 01:37:28.025668
10135 01:37:28.679601 01480000 ################################################################
10136 01:37:28.679746
10137 01:37:29.349881 01500000 ################################################################
10138 01:37:29.350607
10139 01:37:30.013530 01580000 ################################################################
10140 01:37:30.013671
10141 01:37:30.647273 01600000 ################################################################
10142 01:37:30.647896
10143 01:37:31.335434 01680000 ################################################################
10144 01:37:31.335986
10145 01:37:32.025051 01700000 ################################################################
10146 01:37:32.025628
10147 01:37:32.719418 01780000 ################################################################
10148 01:37:32.719958
10149 01:37:33.402621 01800000 ################################################################
10150 01:37:33.403213
10151 01:37:34.092848 01880000 ################################################################
10152 01:37:34.093425
10153 01:37:34.786479 01900000 ################################################################
10154 01:37:34.787002
10155 01:37:35.474234 01980000 ################################################################
10156 01:37:35.474748
10157 01:37:36.158041 01a00000 ################################################################
10158 01:37:36.158563
10159 01:37:36.833130 01a80000 ################################################################
10160 01:37:36.833807
10161 01:37:37.535680 01b00000 ################################################################
10162 01:37:37.536428
10163 01:37:38.228834 01b80000 ################################################################
10164 01:37:38.229380
10165 01:37:38.910923 01c00000 ################################################################
10166 01:37:38.911437
10167 01:37:39.617153 01c80000 ################################################################
10168 01:37:39.617761
10169 01:37:40.344158 01d00000 ################################################################
10170 01:37:40.344716
10171 01:37:41.036161 01d80000 ################################################################
10172 01:37:41.036765
10173 01:37:41.724699 01e00000 ################################################################
10174 01:37:41.725254
10175 01:37:42.412428 01e80000 ################################################################
10176 01:37:42.412975
10177 01:37:43.115950 01f00000 ################################################################
10178 01:37:43.116494
10179 01:37:43.820959 01f80000 ################################################################
10180 01:37:43.821523
10181 01:37:44.532723 02000000 ################################################################
10182 01:37:44.533245
10183 01:37:45.252151 02080000 ################################################################
10184 01:37:45.252699
10185 01:37:45.952431 02100000 ################################################################
10186 01:37:45.952959
10187 01:37:46.676653 02180000 ################################################################
10188 01:37:46.677233
10189 01:37:47.357793 02200000 ################################################################
10190 01:37:47.358303
10191 01:37:48.040617 02280000 ################################################################
10192 01:37:48.041476
10193 01:37:48.736725 02300000 ################################################################
10194 01:37:48.737241
10195 01:37:49.401730 02380000 ################################################################
10196 01:37:49.401950
10197 01:37:50.079832 02400000 ################################################################
10198 01:37:50.080348
10199 01:37:50.765303 02480000 ################################################################
10200 01:37:50.765823
10201 01:37:51.484709 02500000 ################################################################
10202 01:37:51.485242
10203 01:37:52.179657 02580000 ################################################################
10204 01:37:52.180263
10205 01:37:52.897186 02600000 ################################################################
10206 01:37:52.897841
10207 01:37:53.600828 02680000 ################################################################
10208 01:37:53.601375
10209 01:37:54.327618 02700000 ################################################################
10210 01:37:54.328169
10211 01:37:55.041563 02780000 ################################################################
10212 01:37:55.042123
10213 01:37:55.715461 02800000 ################################################################
10214 01:37:55.716162
10215 01:37:56.399024 02880000 ################################################################
10216 01:37:56.399572
10217 01:37:57.103409 02900000 ################################################################
10218 01:37:57.103945
10219 01:37:57.814201 02980000 ################################################################
10220 01:37:57.814721
10221 01:37:58.545199 02a00000 ################################################################
10222 01:37:58.545805
10223 01:37:59.257334 02a80000 ################################################################
10224 01:37:59.257901
10225 01:37:59.947152 02b00000 ################################################################
10226 01:37:59.947670
10227 01:38:00.629620 02b80000 ################################################################
10228 01:38:00.630133
10229 01:38:01.329399 02c00000 ################################################################
10230 01:38:01.329933
10231 01:38:02.028016 02c80000 ################################################################
10232 01:38:02.028549
10233 01:38:02.720084 02d00000 ################################################################
10234 01:38:02.720622
10235 01:38:03.411134 02d80000 ################################################################
10236 01:38:03.411712
10237 01:38:04.117673 02e00000 ################################################################
10238 01:38:04.118200
10239 01:38:04.810149 02e80000 ################################################################
10240 01:38:04.810691
10241 01:38:05.494088 02f00000 ################################################################
10242 01:38:05.494601
10243 01:38:06.189764 02f80000 ################################################################
10244 01:38:06.190274
10245 01:38:06.899942 03000000 ################################################################
10246 01:38:06.900454
10247 01:38:07.612129 03080000 ################################################################
10248 01:38:07.612655
10249 01:38:08.289942 03100000 ################################################################
10250 01:38:08.290090
10251 01:38:08.891583 03180000 ################################################################
10252 01:38:08.891738
10253 01:38:09.481022 03200000 ################################################################
10254 01:38:09.481178
10255 01:38:10.054258 03280000 ################################################################
10256 01:38:10.054419
10257 01:38:10.627977 03300000 ################################################################
10258 01:38:10.628135
10259 01:38:10.965470 03380000 ####################################### done.
10260 01:38:10.965625
10261 01:38:10.968427 The bootfile was 54313290 bytes long.
10262 01:38:10.968524
10263 01:38:10.971910 Sending tftp read request... done.
10264 01:38:10.972012
10265 01:38:10.972079 Waiting for the transfer...
10266 01:38:10.972140
10267 01:38:10.975450 00000000 # done.
10268 01:38:10.975546
10269 01:38:10.981891 Command line loaded dynamically from TFTP file: 14173516/tftp-deploy-pbvb5vjh/kernel/cmdline
10270 01:38:10.982005
10271 01:38:10.994901 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10272 01:38:10.995049
10273 01:38:10.998216 Loading FIT.
10274 01:38:10.998306
10275 01:38:11.001589 Image ramdisk-1 has 41204080 bytes.
10276 01:38:11.001683
10277 01:38:11.004930 Image fdt-1 has 47258 bytes.
10278 01:38:11.005022
10279 01:38:11.005087 Image kernel-1 has 13059919 bytes.
10280 01:38:11.008461
10281 01:38:11.014838 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10282 01:38:11.014956
10283 01:38:11.031181 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10284 01:38:11.034779
10285 01:38:11.037704 Choosing best match conf-1 for compat google,spherion-rev2.
10286 01:38:11.042706
10287 01:38:11.084518 Connected to device vid:did:rid of 1ae0:0028:00
10288 01:38:11.095865
10289 01:38:11.098134 tpm_get_response: command 0x17b, return code 0x0
10290 01:38:11.098226
10291 01:38:11.101376 ec_init: CrosEC protocol v3 supported (256, 248)
10292 01:38:11.105170
10293 01:38:11.108477 tpm_cleanup: add release locality here.
10294 01:38:11.108563
10295 01:38:11.108628 Shutting down all USB controllers.
10296 01:38:11.112213
10297 01:38:11.112300 Removing current net device
10298 01:38:11.112366
10299 01:38:11.118659 Exiting depthcharge with code 4 at timestamp: 117131929
10300 01:38:11.118751
10301 01:38:11.121883 LZMA decompressing kernel-1 to 0x821a6718
10302 01:38:11.121970
10303 01:38:11.125144 LZMA decompressing kernel-1 to 0x40000000
10304 01:38:12.734537
10305 01:38:12.734687 jumping to kernel
10306 01:38:12.735199 end: 2.2.4 bootloader-commands (duration 00:01:30) [common]
10307 01:38:12.735299 start: 2.2.5 auto-login-action (timeout 00:02:57) [common]
10308 01:38:12.735377 Setting prompt string to ['Linux version [0-9]']
10309 01:38:12.735446 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10310 01:38:12.735515 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10311 01:38:12.816672
10312 01:38:12.820188 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10313 01:38:12.824339 start: 2.2.5.1 login-action (timeout 00:02:57) [common]
10314 01:38:12.824436 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10315 01:38:12.824508 Setting prompt string to []
10316 01:38:12.824584 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10317 01:38:12.824658 Using line separator: #'\n'#
10318 01:38:12.824718 No login prompt set.
10319 01:38:12.824778 Parsing kernel messages
10320 01:38:12.824833 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10321 01:38:12.824935 [login-action] Waiting for messages, (timeout 00:02:57)
10322 01:38:12.825001 Waiting using forced prompt support (timeout 00:01:28)
10323 01:38:12.843467 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10324 01:38:12.846449 [ 0.000000] random: crng init done
10325 01:38:12.852946 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10326 01:38:12.856280 [ 0.000000] efi: UEFI not found.
10327 01:38:12.862666 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10328 01:38:12.872868 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10329 01:38:12.882717 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10330 01:38:12.889543 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10331 01:38:12.896573 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10332 01:38:12.902989 [ 0.000000] printk: bootconsole [mtk8250] enabled
10333 01:38:12.908992 [ 0.000000] NUMA: No NUMA configuration found
10334 01:38:12.915675 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10335 01:38:12.922754 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10336 01:38:12.922838 [ 0.000000] Zone ranges:
10337 01:38:12.929091 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10338 01:38:12.932282 [ 0.000000] DMA32 empty
10339 01:38:12.938809 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10340 01:38:12.942418 [ 0.000000] Movable zone start for each node
10341 01:38:12.945270 [ 0.000000] Early memory node ranges
10342 01:38:12.952828 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10343 01:38:12.958702 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10344 01:38:12.965825 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10345 01:38:12.971992 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10346 01:38:12.978413 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10347 01:38:12.985168 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10348 01:38:13.041606 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10349 01:38:13.047987 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10350 01:38:13.054912 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10351 01:38:13.058300 [ 0.000000] psci: probing for conduit method from DT.
10352 01:38:13.064728 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10353 01:38:13.068133 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10354 01:38:13.074513 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10355 01:38:13.077749 [ 0.000000] psci: SMC Calling Convention v1.2
10356 01:38:13.084353 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10357 01:38:13.087762 [ 0.000000] Detected VIPT I-cache on CPU0
10358 01:38:13.094272 [ 0.000000] CPU features: detected: GIC system register CPU interface
10359 01:38:13.101414 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10360 01:38:13.107467 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10361 01:38:13.114261 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10362 01:38:13.123927 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10363 01:38:13.130738 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10364 01:38:13.135385 [ 0.000000] alternatives: applying boot alternatives
10365 01:38:13.140725 [ 0.000000] Fallback order for Node 0: 0
10366 01:38:13.147976 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10367 01:38:13.150497 [ 0.000000] Policy zone: Normal
10368 01:38:13.163527 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10369 01:38:13.173640 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10370 01:38:13.185972 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10371 01:38:13.195944 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10372 01:38:13.202707 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10373 01:38:13.205950 <6>[ 0.000000] software IO TLB: area num 8.
10374 01:38:13.262933 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10375 01:38:13.412911 <6>[ 0.000000] Memory: 7923952K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428816K reserved, 32768K cma-reserved)
10376 01:38:13.419596 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10377 01:38:13.425827 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10378 01:38:13.429297 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10379 01:38:13.435744 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10380 01:38:13.442345 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10381 01:38:13.445900 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10382 01:38:13.455906 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10383 01:38:13.462224 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10384 01:38:13.469154 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10385 01:38:13.475540 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10386 01:38:13.478575 <6>[ 0.000000] GICv3: 608 SPIs implemented
10387 01:38:13.482207 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10388 01:38:13.488563 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10389 01:38:13.492568 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10390 01:38:13.498569 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10391 01:38:13.511707 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10392 01:38:13.524928 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10393 01:38:13.531848 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10394 01:38:13.539699 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10395 01:38:13.552694 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10396 01:38:13.559577 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10397 01:38:13.566302 <6>[ 0.009227] Console: colour dummy device 80x25
10398 01:38:13.576142 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10399 01:38:13.582432 <6>[ 0.024469] pid_max: default: 32768 minimum: 301
10400 01:38:13.586502 <6>[ 0.029342] LSM: Security Framework initializing
10401 01:38:13.592757 <6>[ 0.034280] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 01:38:13.602572 <6>[ 0.042094] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 01:38:13.609250 <6>[ 0.051499] cblist_init_generic: Setting adjustable number of callback queues.
10404 01:38:13.615819 <6>[ 0.058942] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 01:38:13.625150 <6>[ 0.065280] cblist_init_generic: Setting adjustable number of callback queues.
10406 01:38:13.632041 <6>[ 0.072753] cblist_init_generic: Setting shift to 3 and lim to 1.
10407 01:38:13.635690 <6>[ 0.079190] rcu: Hierarchical SRCU implementation.
10408 01:38:13.642275 <6>[ 0.079192] rcu: Max phase no-delay instances is 1000.
10409 01:38:13.648631 <6>[ 0.079215] printk: bootconsole [mtk8250] printing thread started
10410 01:38:13.655142 <6>[ 0.097499] EFI services will not be available.
10411 01:38:13.658465 <6>[ 0.097675] smp: Bringing up secondary CPUs ...
10412 01:38:13.665152 <6>[ 0.097953] Detected VIPT I-cache on CPU1
10413 01:38:13.671625 <6>[ 0.098020] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10414 01:38:13.678870 <6>[ 0.098054] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10415 01:38:13.687782 <6>[ 0.125921] Detected VIPT I-cache on CPU2
10416 01:38:13.694581 <6>[ 0.125975] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10417 01:38:13.704362 <6>[ 0.125993] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10418 01:38:13.708098 <6>[ 0.126249] Detected VIPT I-cache on CPU3
10419 01:38:13.714435 <6>[ 0.126298] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10420 01:38:13.720945 <6>[ 0.126313] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10421 01:38:13.724431 <6>[ 0.126622] CPU features: detected: Spectre-v4
10422 01:38:13.731133 <6>[ 0.126628] CPU features: detected: Spectre-BHB
10423 01:38:13.734571 <6>[ 0.126633] Detected PIPT I-cache on CPU4
10424 01:38:13.740896 <6>[ 0.126691] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10425 01:38:13.747590 <6>[ 0.126706] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10426 01:38:13.754180 <6>[ 0.126996] Detected PIPT I-cache on CPU5
10427 01:38:13.760983 <6>[ 0.127057] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10428 01:38:13.767079 <6>[ 0.127073] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10429 01:38:13.770871 <6>[ 0.127357] Detected PIPT I-cache on CPU6
10430 01:38:13.776842 <6>[ 0.127423] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10431 01:38:13.787867 <6>[ 0.127439] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10432 01:38:13.791432 <6>[ 0.127722] Detected PIPT I-cache on CPU7
10433 01:38:13.798233 <6>[ 0.127787] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10434 01:38:13.804954 <6>[ 0.127803] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10435 01:38:13.807555 <6>[ 0.127850] smp: Brought up 1 node, 8 CPUs
10436 01:38:13.814423 <6>[ 0.127855] SMP: Total of 8 processors activated.
10437 01:38:13.818419 <6>[ 0.127858] CPU features: detected: 32-bit EL0 Support
10438 01:38:13.827965 <6>[ 0.127860] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10439 01:38:13.834265 <6>[ 0.127862] CPU features: detected: Common not Private translations
10440 01:38:13.840887 <6>[ 0.127864] CPU features: detected: CRC32 instructions
10441 01:38:13.847711 <6>[ 0.127867] CPU features: detected: RCpc load-acquire (LDAPR)
10442 01:38:13.850828 <6>[ 0.127869] CPU features: detected: LSE atomic instructions
10443 01:38:13.857602 <6>[ 0.127870] CPU features: detected: Privileged Access Never
10444 01:38:13.864095 <6>[ 0.127872] CPU features: detected: RAS Extension Support
10445 01:38:13.870636 <6>[ 0.127875] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10446 01:38:13.873928 <6>[ 0.127941] CPU: All CPU(s) started at EL2
10447 01:38:13.880184 <6>[ 0.127942] alternatives: applying system-wide alternatives
10448 01:38:13.883836 <6>[ 0.141180] devtmpfs: initialized
10449 01:38:13.893581 <6>[ 0.147495] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10450 01:38:13.900467 <6>[ 0.147509] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10451 01:38:13.926487 <6>[ 0.369561] printk: console [tty<S0] printing thread started
10452 01:38:13.932852 6>[ 0.148196] pinctrl core: initialized pinctrl subsystem
10453 01:38:13.941911 <6>[ 0.369567] printk: console [ttyS0] enabled
10454 01:38:13.945017 <6>[ 0.369571] printk: bootconsole [mtk8250] disabled
10455 01:38:13.951312 <6>[ 0.380890] printk: bootconsole [mtk8250] printing thread stopped
10456 01:38:13.958063 <6>[ 0.382264] SuperH (H)SCI(F) driver initialized
10457 01:38:13.961677 <6>[ 0.382736] msm_serial: driver initialized
10458 01:38:13.970983 <6>[ 0.387331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10459 01:38:13.977776 <6>[ 0.387360] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10460 01:38:13.988809 <6>[ 0.387389] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10461 01:38:13.995106 <6>[ 0.387418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10462 01:38:14.005244 <6>[ 0.387441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10463 01:38:14.017236 <6>[ 0.387471] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10464 01:38:14.029986 <6>[ 0.387498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10465 01:38:14.034236 <6>[ 0.387620] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10466 01:38:14.039246 <6>[ 0.387649] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10467 01:38:14.044340 <6>[ 0.398090] loop: module loaded
10468 01:38:14.049224 <6>[ 0.400564] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10469 01:38:14.056215 <4>[ 0.417776] mtk-pmic-keys: Failed to locate of_node [id: -1]
10470 01:38:14.059622 <6>[ 0.418819] megasas: 07.719.03.00-rc1
10471 01:38:14.062449 <6>[ 0.428185] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10472 01:38:14.069125 <6>[ 0.436184] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10473 01:38:14.075833 <6>[ 0.448357] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10474 01:38:14.089114 <6>[ 0.501979] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10475 01:38:15.549380 <6>[ 1.990976] Freeing initrd memory: 40232K
10476 01:38:15.557471 <6>[ 1.998211] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10477 01:38:15.563759 <6>[ 2.003006] tun: Universal TUN/TAP device driver, 1.6
10478 01:38:15.567248 <6>[ 2.003770] thunder_xcv, ver 1.0
10479 01:38:15.570716 <6>[ 2.003790] thunder_bgx, ver 1.0
10480 01:38:15.574188 <6>[ 2.003803] nicpf, ver 1.0
10481 01:38:15.580524 <6>[ 2.004880] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10482 01:38:15.587484 <6>[ 2.004883] hns3: Copyright (c) 2017 Huawei Corporation.
10483 01:38:15.590517 <6>[ 2.004909] hclge is initializing
10484 01:38:15.597197 <6>[ 2.004927] e1000: Intel(R) PRO/1000 Network Driver
10485 01:38:15.601118 <6>[ 2.004929] e1000: Copyright (c) 1999-2006 Intel Corporation.
10486 01:38:15.608479 <6>[ 2.004948] e1000e: Intel(R) PRO/1000 Network Driver
10487 01:38:15.611840 <6>[ 2.004949] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10488 01:38:15.618869 <6>[ 2.004967] igb: Intel(R) Gigabit Ethernet Network Driver
10489 01:38:15.625536 <6>[ 2.004969] igb: Copyright (c) 2007-2014 Intel Corporation.
10490 01:38:15.632711 <6>[ 2.004983] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10491 01:38:15.635823 <6>[ 2.004985] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10492 01:38:15.642577 <6>[ 2.005276] sky2: driver version 1.30
10493 01:38:15.649062 <6>[ 2.006275] usbcore: registered new device driver r8152-cfgselector
10494 01:38:15.652918 <6>[ 2.006291] usbcore: registered new interface driver r8152
10495 01:38:15.658576 <6>[ 2.006370] VFIO - User Level meta-driver version: 0.3
10496 01:38:15.665716 <6>[ 2.009215] usbcore: registered new interface driver usb-storage
10497 01:38:15.671923 <6>[ 2.009399] usbcore: registered new device driver onboard-usb-hub
10498 01:38:15.675385 <6>[ 2.012192] mt6397-rtc mt6359-rtc: registered as rtc0
10499 01:38:15.685447 <6>[ 2.012341] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T01:38:15 UTC (1717551495)
10500 01:38:15.688630 <6>[ 2.012965] i2c_dev: i2c /dev entries driver
10501 01:38:15.698839 <6>[ 2.020142] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10502 01:38:15.705035 <4>[ 2.020879] cpu cpu0: supply cpu not found, using dummy regulator
10503 01:38:15.711531 <4>[ 2.020957] cpu cpu1: supply cpu not found, using dummy regulator
10504 01:38:15.717906 <4>[ 2.021014] cpu cpu2: supply cpu not found, using dummy regulator
10505 01:38:15.724609 <4>[ 2.021072] cpu cpu3: supply cpu not found, using dummy regulator
10506 01:38:15.728438 <4>[ 2.021123] cpu cpu4: supply cpu not found, using dummy regulator
10507 01:38:15.735220 <4>[ 2.021193] cpu cpu5: supply cpu not found, using dummy regulator
10508 01:38:15.741059 <4>[ 2.021242] cpu cpu6: supply cpu not found, using dummy regulator
10509 01:38:15.747978 <4>[ 2.021290] cpu cpu7: supply cpu not found, using dummy regulator
10510 01:38:15.754869 <6>[ 2.035906] cpu cpu0: EM: created perf domain
10511 01:38:15.757912 <6>[ 2.036238] cpu cpu4: EM: created perf domain
10512 01:38:15.764385 <6>[ 2.039017] sdhci: Secure Digital Host Controller Interface driver
10513 01:38:15.767656 <6>[ 2.039019] sdhci: Copyright(c) Pierre Ossman
10514 01:38:15.774466 <6>[ 2.039390] Synopsys Designware Multimedia Card Interface Driver
10515 01:38:15.780689 <6>[ 2.039773] sdhci-pltfm: SDHCI platform and OF driver helper
10516 01:38:15.787372 <6>[ 2.043980] ledtrig-cpu: registered to indicate activity on CPUs
10517 01:38:15.790628 <6>[ 2.044703] mmc0: CQHCI version 5.10
10518 01:38:15.797526 <6>[ 2.044807] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10519 01:38:15.804243 <6>[ 2.045102] usbcore: registered new interface driver usbhid
10520 01:38:15.807557 <6>[ 2.045104] usbhid: USB HID core driver
10521 01:38:15.814264 <6>[ 2.045214] spi_master spi0: will run message pump with realtime priority
10522 01:38:15.827743 <6>[ 2.077655] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10523 01:38:15.840624 <6>[ 2.079576] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10524 01:38:15.847289 <6>[ 2.080675] cros-ec-spi spi0.0: Chrome EC device registered
10525 01:38:15.856965 <6>[ 2.098608] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10526 01:38:15.860378 <6>[ 2.101120] NET: Registered PF_PACKET protocol family
10527 01:38:15.866612 <6>[ 2.101239] 9pnet: Installing 9P2000 support
10528 01:38:15.869990 <5>[ 2.101279] Key type dns_resolver registered
10529 01:38:15.874064 <6>[ 2.101724] registered taskstats version 1
10530 01:38:15.880314 <5>[ 2.101757] Loading compiled-in X.509 certificates
10531 01:38:15.889663 <4>[ 2.125534] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 01:38:15.899717 <4>[ 2.125696] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 01:38:15.906702 <6>[ 2.135597] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10534 01:38:15.912922 <6>[ 2.136265] xhci-mtk 11200000.usb: xHCI Host Controller
10535 01:38:15.919788 <6>[ 2.136277] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10536 01:38:15.929472 <6>[ 2.136468] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10537 01:38:15.935885 <6>[ 2.136499] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10538 01:38:15.939407 <6>[ 2.136576] xhci-mtk 11200000.usb: xHCI Host Controller
10539 01:38:15.949436 <6>[ 2.136579] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10540 01:38:15.956166 <6>[ 2.136586] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10541 01:38:15.962219 <6>[ 2.136679] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10542 01:38:15.966081 <6>[ 2.136897] hub 1-0:1.0: USB hub found
10543 01:38:15.969996 <6>[ 2.136907] hub 1-0:1.0: 1 port detected
10544 01:38:15.979615 <6>[ 2.137000] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10545 01:38:15.982255 <6>[ 2.137187] hub 2-0:1.0: USB hub found
10546 01:38:15.985704 <6>[ 2.137214] hub 2-0:1.0: 1 port detected
10547 01:38:15.992128 <6>[ 2.140293] mtk-msdc 11f70000.mmc: Got CD GPIO
10548 01:38:15.995456 <6>[ 2.146618] mmc0: Command Queue Engine enabled
10549 01:38:16.001907 <6>[ 2.146637] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10550 01:38:16.008567 <6>[ 2.147544] mmcblk0: mmc0:0001 DA4128 116 GiB
10551 01:38:16.015507 <6>[ 2.149407] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10552 01:38:16.021858 <6>[ 2.149416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10553 01:38:16.032717 <4>[ 2.149503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10554 01:38:16.038639 <6>[ 2.149999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10555 01:38:16.048267 <6>[ 2.150000] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10556 01:38:16.054612 <6>[ 2.150348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10557 01:38:16.064662 <6>[ 2.150364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10558 01:38:16.071401 <6>[ 2.150366] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10559 01:38:16.081371 <6>[ 2.150368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10560 01:38:16.088405 <6>[ 2.151769] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10561 01:38:16.097550 <6>[ 2.151782] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10562 01:38:16.104231 <6>[ 2.151785] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10563 01:38:16.114597 <6>[ 2.151788] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10564 01:38:16.120736 <6>[ 2.151791] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10565 01:38:16.131037 <6>[ 2.151794] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10566 01:38:16.137287 <6>[ 2.151797] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10567 01:38:16.147256 <6>[ 2.151799] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10568 01:38:16.157162 <6>[ 2.151804] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10569 01:38:16.164494 <6>[ 2.151808] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10570 01:38:16.173456 <6>[ 2.151811] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10571 01:38:16.180477 <6>[ 2.151814] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10572 01:38:16.190171 <6>[ 2.151816] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10573 01:38:16.196643 <6>[ 2.151820] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10574 01:38:16.206646 <6>[ 2.151823] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10575 01:38:16.213127 <6>[ 2.152349] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10576 01:38:16.216663 <6>[ 2.152889] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10577 01:38:16.223334 <6>[ 2.153469] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10578 01:38:16.229978 <6>[ 2.154105] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10579 01:38:16.236300 <6>[ 2.154510] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10580 01:38:16.242805 <6>[ 2.154737] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10581 01:38:16.249559 <6>[ 2.155242] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10582 01:38:16.259178 <6>[ 2.155497] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10583 01:38:16.269413 <6>[ 2.155515] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10584 01:38:16.275818 <6>[ 2.155519] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10585 01:38:16.285676 <6>[ 2.155524] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10586 01:38:16.295745 <6>[ 2.155528] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10587 01:38:16.305685 <6>[ 2.155533] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10588 01:38:16.315522 <6>[ 2.155537] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10589 01:38:16.325180 <6>[ 2.155540] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10590 01:38:16.332113 <6>[ 2.155544] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10591 01:38:16.341647 <6>[ 2.155550] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10592 01:38:16.355054 <6>[ 2.155554] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10593 01:38:16.358525 <6>[ 2.155571] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10594 01:38:16.368414 <6>[ 2.156225] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10595 01:38:16.374275 <6>[ 2.156415] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10596 01:38:16.381149 <6>[ 2.556908] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10597 01:38:16.384526 <6>[ 2.708500] hub 1-1:1.0: USB hub found
10598 01:38:16.387824 <6>[ 2.708843] hub 1-1:1.0: 4 ports detected
10599 01:38:16.391275 <6>[ 2.711615] hub 1-1:1.0: USB hub found
10600 01:38:16.397798 <6>[ 2.711875] hub 1-1:1.0: 4 ports detected
10601 01:38:16.404651 <6>[ 2.837178] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10602 01:38:16.421469 <6>[ 2.862352] hub 2-1:1.0: USB hub found
10603 01:38:16.424528 <6>[ 2.862770] hub 2-1:1.0: 3 ports detected
10604 01:38:16.427505 <6>[ 2.865940] hub 2-1:1.0: USB hub found
10605 01:38:16.431031 <6>[ 2.866354] hub 2-1:1.0: 3 ports detected
10606 01:38:16.588900 <6>[ 3.025050] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10607 01:38:16.713494 <6>[ 3.152975] hub 1-1.4:1.0: USB hub found
10608 01:38:16.716562 <6>[ 3.153434] hub 1-1.4:1.0: 2 ports detected
10609 01:38:16.719734 <6>[ 3.157112] hub 1-1.4:1.0: USB hub found
10610 01:38:16.726495 <6>[ 3.157459] hub 1-1.4:1.0: 2 ports detected
10611 01:38:16.793096 <6>[ 3.229152] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10612 01:38:16.896479 <6>[ 3.333597] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10613 01:38:16.920989 <4>[ 3.360609] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10614 01:38:16.930457 <4>[ 3.360628] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10615 01:38:16.953055 <6>[ 3.394437] r8152 2-1.3:1.0 eth0: v1.12.13
10616 01:38:17.008560 <6>[ 3.445049] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10617 01:38:17.192851 <6>[ 3.629063] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10618 01:38:18.545390 <6>[ 4.987140] r8152 2-1.3:1.0 eth0: carrier on
10619 01:38:21.056889 <5>[ 5.017014] Sending DHCP requests .., OK
10620 01:38:21.064130 <6>[ 7.497104] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10621 01:38:21.067415 <6>[ 7.497125] IP-Config: Complete:
10622 01:38:21.080695 <6>[ 7.497128] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10623 01:38:21.086602 <6>[ 7.497141] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10624 01:38:21.093518 <6>[ 7.497146] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10625 01:38:21.100225 <6>[ 7.497154] nameserver0=192.168.201.1
10626 01:38:21.103603 <6>[ 7.497474] clk: Disabling unused clocks
10627 01:38:21.106342 <6>[ 7.498535] ALSA device list:
10628 01:38:21.110216 <6>[ 7.498548] No soundcards found.
10629 01:38:21.116220 <6>[ 7.502969] Freeing unused kernel memory: 8512K
10630 01:38:21.119693 <6>[ 7.503148] Run /init as init process
10631 01:38:21.133209 <6>[ 7.573075] NET: Registered PF_INET6 protocol family
10632 01:38:21.136165 <6>[ 7.574480] Segment Routing with IPv6
10633 01:38:21.142708 <6>[ 7.574492] In-situ OAM (IOAM) with IPv6
10634 01:38:21.142834
10635 01:38:21.178708 Welcome to [1mDebian GNU/Linu<30>[ 7.590447] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10636 01:38:21.182236 <30>[ 7.590470] systemd[1]: Detected architecture arm64.
10637 01:38:21.185286 x 12 (bookworm)[0m!
10638 01:38:21.185402
10639 01:38:21.205462 <30>[ 7.645175] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10640 01:38:21.372090 <30>[ 7.812058] systemd[1]: Queued start job for default target graphical.target.
10641 01:38:21.402343 [[0;32m OK [0m] Created slic<30>[ 7.839003] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10642 01:38:21.404765 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10643 01:38:21.428748 [[0;32m OK [0m] Created slic<30>[ 7.866158] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10644 01:38:21.432409 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10645 01:38:21.459350 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 7.893661] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10646 01:38:21.463417 m-seria…[0m - Slice /system/serial-getty.
10647 01:38:21.485121 [[0;32m OK [0m] Created slic<30>[ 7.922332] systemd[1]: Created slice user.slice - User and Session Slice.
10648 01:38:21.488200 e [0;1;39muser.slice[0m - User and Session Slice.
10649 01:38:21.516028 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 7.949889] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10650 01:38:21.519252 -passwo…quests to Console Directory Watch.
10651 01:38:21.543687 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 7.977794] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10652 01:38:21.547183 -passwo… Requests to Wall Directory Watch.
10653 01:38:21.581397 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 8.005526] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10654 01:38:21.588092 <30>[ 8.005689] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10655 01:38:21.591710 ice[0m - /dev/ttyS0...
10656 01:38:21.611691 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 8.049130] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10657 01:38:21.614742 tsetup.…get[0m - Local Encrypted Volumes.
10658 01:38:21.639247 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 8.073122] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10659 01:38:21.642359 grityse…Local Integrity Protected Volumes.
10660 01:38:21.664510 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 8.101590] systemd[1]: Reached target paths.target - Path Units.
10661 01:38:21.664655 s.target[0m - Path Units.
10662 01:38:21.688338 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 8.125405] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10663 01:38:21.691639 te-fs.target[0m - Remote File Systems.
10664 01:38:21.712352 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 8.149097] systemd[1]: Reached target slices.target - Slice Units.
10665 01:38:21.715076 es.target[0m - Slice Units.
10666 01:38:21.736969 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 8.173501] systemd[1]: Reached target swap.target - Swaps.
10667 01:38:21.737114 .target[0m - Swaps.
10668 01:38:21.759503 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 8.196940] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10669 01:38:21.766438 tysetup… - Local Verity Protected Volumes.
10670 01:38:21.788787 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.225515] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10671 01:38:21.794935 d-initc… initctl Compatibility Named Pipe.
10672 01:38:21.817974 [[0;32m OK [0m] Listening on<30>[ 8.254921] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10673 01:38:21.824135 [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10674 01:38:21.847282 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.281649] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10675 01:38:21.850613 d-journ…t[0m - Journal Socket (/dev/log).
10676 01:38:21.872465 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.309646] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10677 01:38:21.875772 d-journald.socket[0m - Journal Socket.
10678 01:38:21.896834 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.333745] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10679 01:38:21.903068 d-netwo… - Network Service Netlink Socket.
10680 01:38:21.925163 [[0;32m OK [0m] Listening on<30>[ 8.362438] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10681 01:38:21.931768 [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10682 01:38:21.953399 [[0;32m OK [0m] Listening on<30>[ 8.390157] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10683 01:38:21.956224 [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10684 01:38:22.004113 Mounting [0;1;39mdev-hugepages.mount[<30>[ 8.441153] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10685 01:38:22.006819 0m - Huge Pages File System...
10686 01:38:22.020181 Mountin<30>[ 8.460513] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10687 01:38:22.026408 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10688 01:38:22.051786 Mounting [0;1;39msys-kernel-debug.…<30>[ 8.489252] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10689 01:38:22.054956 [0m - Kernel Debug File System...
10690 01:38:22.083012 <30>[ 8.513501] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10691 01:38:22.092253 <30>[ 8.518396] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10692 01:38:22.099183 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10693 01:38:22.120032 <30>[ 8.560653] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10694 01:38:22.126993 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10695 01:38:22.152720 Starting [0;1;39mmodpr<30>[ 8.590009] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10696 01:38:22.165702 obe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 8.602367] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10697 01:38:22.165833 .
10698 01:38:22.192538 Starting [0;1;39mmodprobe@drm.service<30>[ 8.629835] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10699 01:38:22.195882 [0m - Load Kernel Module drm...
10700 01:38:22.224876 Starting [0;1;39mmodpr<30>[ 8.662085] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10701 01:38:22.227903 obe@efi_psto…- Load Kernel Module efi_pstore...
10702 01:38:22.256643 Starting [0;1;39mmodpr<30>[ 8.694140] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10703 01:38:22.260055 obe@loop.ser…e[0m - Load Kernel Module loop...
10704 01:38:22.292554 Starting [0;1;39msystemd-journald.serv<30>[ 8.729558] systemd[1]: Starting systemd-journald.service - Journal Service...
10705 01:38:22.295374 ice[0m - Journal Service...
10706 01:38:22.314929 Startin<30>[ 8.755766] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10707 01:38:22.321717 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10708 01:38:22.352088 Starting [0;1;39msyste<30>[ 8.786023] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10709 01:38:22.355228 md-network-g… units from Kernel command line...
10710 01:38:22.387781 Starting [0;1;39msystemd-remount-f…n<30>[ 8.821963] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10711 01:38:22.391038 t Root and Kernel File Systems...
10712 01:38:22.412317 <30>[ 8.852604] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10713 01:38:22.418568 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10714 01:38:22.448060 [[0;32m OK [<30>[ 8.888376] systemd[1]: Started systemd-journald.service - Journal Service.
10715 01:38:22.454483 0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10716 01:38:22.476630 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10717 01:38:22.493740 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10718 01:38:22.512955 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10719 01:38:22.532537 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10720 01:38:22.553791 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10721 01:38:22.579597 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10722 01:38:22.603795 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10723 01:38:22.623175 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10724 01:38:22.644197 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10725 01:38:22.662375 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10726 01:38:22.681711 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10727 01:38:22.702851 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10728 01:38:22.709709 See 'systemctl status systemd-remount-fs.service' for details.
10729 01:38:22.719216 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10730 01:38:22.738777 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10731 01:38:22.784706 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10732 01:38:22.806780 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10733 01:38:22.823919 <46>[ 9.262708] systemd-journald[199]: Received client request to flush runtime journal.
10734 01:38:22.835618 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10735 01:38:22.860251 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10736 01:38:22.885282 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10737 01:38:22.914836 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10738 01:38:22.933712 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10739 01:38:22.953566 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10740 01:38:22.973453 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10741 01:38:22.993791 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10742 01:38:23.049423 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10743 01:38:23.074932 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10744 01:38:23.093247 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10745 01:38:23.112567 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10746 01:38:23.156923 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10747 01:38:23.181215 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10748 01:38:23.204555 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10749 01:38:23.251226 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10750 01:38:23.274536 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10751 01:38:23.294674 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10752 01:38:23.341950 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10753 01:38:23.366565 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10754 01:38:23.397385 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10755 01:38:23.501251 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10756 01:38:23.525685 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10757 01:38:23.545401 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10758 01:38:23.565592 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10759 01:38:23.585727 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10760 01:38:23.603104 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10761 01:38:23.620185 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10762 01:38:23.627047 <6>[ 10.065748] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10763 01:38:23.659891 <3>[ 10.098350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 01:38:23.666100 <3>[ 10.098373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 01:38:23.676254 <3>[ 10.098376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 01:38:23.679934 <6>[ 10.105428] remoteproc remoteproc0: scp is available
10767 01:38:23.686376 <6>[ 10.105534] remoteproc remoteproc0: powering up scp
10768 01:38:23.696119 <6>[ 10.105543] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10769 01:38:23.699481 <6>[ 10.105569] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10770 01:38:23.709665 <3>[ 10.133985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 01:38:23.715788 <3>[ 10.134008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 01:38:23.726521 <3>[ 10.134016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 01:38:23.732589 <3>[ 10.134026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 01:38:23.739231 <3>[ 10.134033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 01:38:23.749166 <6>[ 10.135909] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10776 01:38:23.755902 <6>[ 10.135968] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10777 01:38:23.765480 <6>[ 10.135980] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10778 01:38:23.772096 <3>[ 10.168320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 01:38:23.778510 <6>[ 10.197690] mc: Linux media interface: v0.10
10780 01:38:23.785398 <3>[ 10.199300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 01:38:23.795283 <3>[ 10.199321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 01:38:23.802019 <3>[ 10.199324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 01:38:23.809400 <6>[ 10.211923] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10784 01:38:23.819234 <3>[ 10.217125] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 01:38:23.826047 <3>[ 10.217175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 01:38:23.835530 <3>[ 10.217187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 01:38:23.842708 <3>[ 10.217204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 01:38:23.849586 <3>[ 10.217213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 01:38:23.855851 <6>[ 10.227555] videodev: Linux video capture interface: v2.00
10790 01:38:23.866169 <6>[ 10.231011] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10791 01:38:23.872526 <6>[ 10.231011] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10792 01:38:23.879034 <6>[ 10.231036] remoteproc remoteproc0: remote processor scp is now up
10793 01:38:23.886025 <3>[ 10.235633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 01:38:23.895960 <4>[ 10.238817] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10795 01:38:23.899841 <4>[ 10.238817] Fallback method does not support PEC.
10796 01:38:23.912867 Starting [0;1;39msystemd-networkd.…i<4>[ 10.247586] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10797 01:38:23.919435 ce[0m - Network<4>[ 10.255583] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10798 01:38:23.929388 Configuration..<3>[ 10.256119] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10799 01:38:23.936378 <6>[ 10.278685] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10800 01:38:23.943673 <6>[ 10.278713] pci_bus 0000:00: root bus resource [bus 00-ff]
10801 01:38:23.949963 <6>[ 10.278724] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10802 01:38:23.950079 .
10803 01:38:23.960402 <6>[ 10.278729] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10804 01:38:23.966815 <6>[ 10.278810] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10805 01:38:23.973656 <6>[ 10.278829] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10806 01:38:23.981102 [[0;32m OK [0m] Reached targ<6>[ 10.278933] pci 0000:00:00.0: supports D1 D2
10807 01:38:23.990993 et [0;1;39mbasi<6>[ 10.278937] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10808 01:38:24.001010 c.target[0m - B<3>[ 10.304973] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10809 01:38:24.001142 asic System.
10810 01:38:24.011242 <3>[ 10.305813] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10811 01:38:24.017928 <6>[ 10.314578] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10812 01:38:24.024696 <6>[ 10.326272] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10813 01:38:24.031981 <6>[ 10.326313] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10814 01:38:24.037988 <6>[ 10.326335] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10815 01:38:24.045173 <6>[ 10.326350] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10816 01:38:24.051677 <6>[ 10.326500] pci 0000:01:00.0: supports D1 D2
10817 01:38:24.058649 Startin<6>[ 10.326505] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10818 01:38:24.068560 g [0;1;39mdbus.<6>[ 10.337736] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10819 01:38:24.075475 <6>[ 10.340158] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10820 01:38:24.085226 service[0m - D-<6>[ 10.341139] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10821 01:38:24.091942 <6>[ 10.341174] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10822 01:38:24.102863 Bus System Messa<6>[ 10.341177] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10823 01:38:24.102998 ge Bus...
10824 01:38:24.112953 <6>[ 10.341185] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10825 01:38:24.119514 <6>[ 10.341198] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10826 01:38:24.126644 <6>[ 10.341211] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10827 01:38:24.132936 <6>[ 10.341222] pci 0000:00:00.0: PCI bridge to [bus 01]
10828 01:38:24.140008 <6>[ 10.341227] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10829 01:38:24.147318 <6>[ 10.341364] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10830 01:38:24.156738 Starting [0;1;39msystemd-logind.se…i<6>[ 10.341820] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10831 01:38:24.163629 ce[0m - User Lo<6>[ 10.341972] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10832 01:38:24.177337 gin Management..<6>[ 10.361216] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10833 01:38:24.177475 .
10834 01:38:24.184841 <6>[ 10.361623] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10835 01:38:24.194733 <6>[ 10.364792] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10836 01:38:24.204659 <5>[ 10.389695] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10837 01:38:24.210928 <3>[ 10.399731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 01:38:24.220549 <6>[ 10.401381] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10839 01:38:24.227422 <3>[ 10.402209] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10840 01:38:24.234098 <5>[ 10.403384] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10841 01:38:24.240544 <5>[ 10.403700] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10842 01:38:24.250696 <4>[ 10.404901] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10843 01:38:24.257651 <6>[ 10.404910] cfg80211: failed to load regulatory.db
10844 01:38:24.263804 <3>[ 10.410597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10845 01:38:24.277088 <6>[ 10.411791] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10846 01:38:24.283575 <6>[ 10.412053] usbcore: registered new interface driver uvcvideo
10847 01:38:24.286752 <6>[ 10.429938] Bluetooth: Core ver 2.22
10848 01:38:24.293362 <6>[ 10.430012] NET: Registered PF_BLUETOOTH protocol family
10849 01:38:24.300188 <6>[ 10.430014] Bluetooth: HCI device and connection manager initialized
10850 01:38:24.303127 <6>[ 10.430026] Bluetooth: HCI socket layer initialized
10851 01:38:24.310030 <6>[ 10.430031] Bluetooth: L2CAP socket layer initialized
10852 01:38:24.313227 <6>[ 10.430037] Bluetooth: SCO socket layer initialized
10853 01:38:24.323040 <3>[ 10.440414] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 01:38:24.330038 <6>[ 10.443579] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10855 01:38:24.340191 <3>[ 10.469671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 01:38:24.346183 <3>[ 10.493342] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 01:38:24.353191 <6>[ 10.496482] usbcore: registered new interface driver btusb
10858 01:38:24.362529 <4>[ 10.498213] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10859 01:38:24.369557 <3>[ 10.498244] Bluetooth: hci0: Failed to load firmware file (-2)
10860 01:38:24.376657 <3>[ 10.498249] Bluetooth: hci0: Failed to set up firmware (-2)
10861 01:38:24.385809 <4>[ 10.498253] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10862 01:38:24.395810 <3>[ 10.515484] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 01:38:24.402662 <6>[ 10.523566] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10864 01:38:24.409542 <6>[ 10.523669] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10865 01:38:24.415445 <6>[ 10.540770] mt7921e 0000:01:00.0: ASIC revision: 79610010
10866 01:38:24.428686 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Conf<6>[ 10.643427] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10867 01:38:24.431880 <6>[ 10.643427]
10868 01:38:24.431983 iguration.
10869 01:38:24.453407 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10870 01:38:24.464566 <6>[ 10.903481] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10871 01:38:24.481598 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10872 01:38:24.503594 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10873 01:38:24.521154 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10874 01:38:24.534229 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10875 01:38:24.553195 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10876 01:38:24.590352 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10877 01:38:24.614912 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10878 01:38:24.637239 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10879 01:38:24.658661 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10880 01:38:24.721189 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10881 01:38:24.738712 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10882 01:38:24.755149 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10883 01:38:24.771060 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10884 01:38:24.791149 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10885 01:38:24.835910 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10886 01:38:24.860604 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10887 01:38:24.884897 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10888 01:38:24.928610 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10889 01:38:24.966756
10890 01:38:24.969726 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10891 01:38:24.969825
10892 01:38:24.972816 debian-bookworm-arm64 login: root (automatic login)
10893 01:38:24.972901
10894 01:38:24.985972 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10895 01:38:24.986107
10896 01:38:24.992373 The programs included with the Debian GNU/Linux system are free software;
10897 01:38:24.999011 the exact distribution terms for each program are described in the
10898 01:38:25.002456 individual files in /usr/share/doc/*/copyright.
10899 01:38:25.002552
10900 01:38:25.009201 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10901 01:38:25.012116 permitted by applicable law.
10902 01:38:25.012510 Matched prompt #10: / #
10904 01:38:25.012716 Setting prompt string to ['/ #']
10905 01:38:25.012809 end: 2.2.5.1 login-action (duration 00:00:12) [common]
10907 01:38:25.013001 end: 2.2.5 auto-login-action (duration 00:00:12) [common]
10908 01:38:25.013087 start: 2.2.6 expect-shell-connection (timeout 00:02:45) [common]
10909 01:38:25.013158 Setting prompt string to ['/ #']
10910 01:38:25.013219 Forcing a shell prompt, looking for ['/ #']
10912 01:38:25.063532 / #
10913 01:38:25.063737 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10914 01:38:25.063832 Waiting using forced prompt support (timeout 00:02:30)
10915 01:38:25.069005
10916 01:38:25.069331 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10917 01:38:25.069431 start: 2.2.7 export-device-env (timeout 00:02:45) [common]
10918 01:38:25.069520 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10919 01:38:25.069604 end: 2.2 depthcharge-retry (duration 00:02:15) [common]
10920 01:38:25.069685 end: 2 depthcharge-action (duration 00:02:15) [common]
10921 01:38:25.069772 start: 3 lava-test-retry (timeout 00:07:24) [common]
10922 01:38:25.069855 start: 3.1 lava-test-shell (timeout 00:07:24) [common]
10923 01:38:25.069928 Using namespace: common
10925 01:38:25.170310 / # #
10926 01:38:25.170519 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10927 01:38:25.175968 #
10928 01:38:25.176251 Using /lava-14173516
10930 01:38:25.276671 / # export SHELL=/bin/sh
10931 01:38:25.282025 export SHELL=/bin/sh
10933 01:38:25.385721 / # . /lava-14173516/environment
10934 01:38:25.385946 <6>[ 11.783764] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10935 01:38:25.391630 . /lava-14173516/environment
10937 01:38:25.492236 / # /lava-14173516/bin/lava-test-runner /lava-14173516/0
10938 01:38:25.492425 Test shell timeout: 10s (minimum of the action and connection timeout)
10939 01:38:25.497769 /lava-14173516/bin/lava-test-runner /lava-14173516/0
10940 01:38:25.521389 + export TESTRUN_ID=0_v4l2-compliance-uvc
10941 01:38:25.525147 + cd /lava-14173516/0/tests/0_v4l2-compliance-uvc
10942 01:38:25.525253 + cat uuid
10943 01:38:25.528163 + UUID=14173516_1.5.2.3.1
10944 01:38:25.528250 + set +x
10945 01:38:25.534996 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14173516_1.5.2.3.1>
10946 01:38:25.535279 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14173516_1.5.2.3.1
10947 01:38:25.535358 Starting test lava.0_v4l2-compliance-uvc (14173516_1.5.2.3.1)
10948 01:38:25.535443 Skipping test definition patterns.
10949 01:38:25.538226 + /usr/bin/v4l2-parser.sh -d uvcvideo
10950 01:38:25.544436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10951 01:38:25.544535 device: /dev/video0
10952 01:38:25.544776 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10954 01:38:32.007322 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
10955 01:38:32.020120 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
10956 01:38:32.027977
10957 01:38:32.045233 Compliance test for uvcvideo device /dev/video0:
10958 01:38:32.058488
10959 01:38:32.070416 Driver Info:
10960 01:38:32.084939 Driver name : uvcvideo
10961 01:38:32.097522 Card type : HD User Facing: HD User Facing
10962 01:38:32.113164 Bus info : usb-11200000.usb-1.4.1
10963 01:38:32.119803 Driver version : 6.1.92
10964 01:38:32.131632 Capabilities : 0x84a00001
10965 01:38:32.148294 Metadata Capture
10966 01:38:32.159968 Streaming
10967 01:38:32.171627 Extended Pix Format
10968 01:38:32.182424 Device Capabilities
10969 01:38:32.195194 Device Caps : 0x04200001
10970 01:38:32.209746 Streaming
10971 01:38:32.224511 Extended Pix Format
10972 01:38:32.236644 Media Driver Info:
10973 01:38:32.251237 Driver name : uvcvideo
10974 01:38:32.264879 Model : HD User Facing: HD User Facing
10975 01:38:32.272218 Serial : 200901010001
10976 01:38:32.285329 Bus info : usb-11200000.usb-1.4.1
10977 01:38:32.292992 Media version : 6.1.92
10978 01:38:32.306461 Hardware revision: 0x00009758 (38744)
10979 01:38:32.313520 Driver version : 6.1.92
10980 01:38:32.329543 Interface Info:
10981 01:38:32.344916 <LAVA_SIGNAL_TESTSET START Interface-Info>
10982 01:38:32.345016 ID : 0x03000002
10983 01:38:32.345266 Received signal: <TESTSET> START Interface-Info
10984 01:38:32.345344 Starting test_set Interface-Info
10985 01:38:32.353953 Type : V4L Video
10986 01:38:32.366610 Entity Info:
10987 01:38:32.376190 <LAVA_SIGNAL_TESTSET STOP>
10988 01:38:32.376450 Received signal: <TESTSET> STOP
10989 01:38:32.376525 Closing test_set Interface-Info
10990 01:38:32.386296 <LAVA_SIGNAL_TESTSET START Entity-Info>
10991 01:38:32.386553 Received signal: <TESTSET> START Entity-Info
10992 01:38:32.386623 Starting test_set Entity-Info
10993 01:38:32.389447 ID : 0x00000001 (1)
10994 01:38:32.402126 Name : HD User Facing: HD User Facing
10995 01:38:32.412784 Function : V4L2 I/O
10996 01:38:32.422724 Flags : default
10997 01:38:32.435895 Pad 0x01000007 : 0: Sink
10998 01:38:32.456293 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
10999 01:38:32.456393
11000 01:38:32.469548 Required ioctls:
11001 01:38:32.476326 <LAVA_SIGNAL_TESTSET STOP>
11002 01:38:32.476589 Received signal: <TESTSET> STOP
11003 01:38:32.476660 Closing test_set Entity-Info
11004 01:38:32.485296 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11005 01:38:32.485553 Received signal: <TESTSET> START Required-ioctls
11006 01:38:32.485625 Starting test_set Required-ioctls
11007 01:38:32.488699 test MC information (see 'Media Driver Info' above): OK
11008 01:38:32.513768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11009 01:38:32.514053 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11011 01:38:32.516609 test VIDIOC_QUERYCAP: OK
11012 01:38:32.534484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11013 01:38:32.534775 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11015 01:38:32.538369 test invalid ioctls: OK
11016 01:38:32.557401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11017 01:38:32.557494
11018 01:38:32.557749 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11020 01:38:32.569280 Allow for multiple opens:
11021 01:38:32.575612 <LAVA_SIGNAL_TESTSET STOP>
11022 01:38:32.575867 Received signal: <TESTSET> STOP
11023 01:38:32.575937 Closing test_set Required-ioctls
11024 01:38:32.586282 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11025 01:38:32.586538 Received signal: <TESTSET> START Allow-for-multiple-opens
11026 01:38:32.586609 Starting test_set Allow-for-multiple-opens
11027 01:38:32.589938 test second /dev/video0 open: OK
11028 01:38:32.612258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11029 01:38:32.612518 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11031 01:38:32.615643 test VIDIOC_QUERYCAP: OK
11032 01:38:32.639981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11033 01:38:32.640259 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11035 01:38:32.643452 test VIDIOC_G/S_PRIORITY: OK
11036 01:38:32.664284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11037 01:38:32.664548 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11039 01:38:32.667538 test for unlimited opens: OK
11040 01:38:32.689718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11041 01:38:32.689816
11042 01:38:32.690054 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11044 01:38:32.700501 Debug ioctls:
11045 01:38:32.707424 <LAVA_SIGNAL_TESTSET STOP>
11046 01:38:32.707677 Received signal: <TESTSET> STOP
11047 01:38:32.707746 Closing test_set Allow-for-multiple-opens
11048 01:38:32.716948 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11049 01:38:32.717204 Received signal: <TESTSET> START Debug-ioctls
11050 01:38:32.717309 Starting test_set Debug-ioctls
11051 01:38:32.720322 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11052 01:38:32.745342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11053 01:38:32.745634 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11055 01:38:32.751787 test VIDIOC_LOG_STATUS: OK (Not Supported)
11056 01:38:32.769455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11057 01:38:32.769549
11058 01:38:32.769788 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11060 01:38:32.780198 Input ioctls:
11061 01:38:32.788162 <LAVA_SIGNAL_TESTSET STOP>
11062 01:38:32.788422 Received signal: <TESTSET> STOP
11063 01:38:32.788495 Closing test_set Debug-ioctls
11064 01:38:32.799545 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11065 01:38:32.799803 Received signal: <TESTSET> START Input-ioctls
11066 01:38:32.799875 Starting test_set Input-ioctls
11067 01:38:32.802895 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11068 01:38:32.827770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11069 01:38:32.828060 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11071 01:38:32.830435 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11072 01:38:32.848525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11073 01:38:32.848787 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11075 01:38:32.854414 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11076 01:38:32.876506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11077 01:38:32.876776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11079 01:38:32.883411 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11080 01:38:32.901082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11081 01:38:32.901388 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11083 01:38:32.904254 test VIDIOC_G/S/ENUMINPUT: OK
11084 01:38:32.927576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11085 01:38:32.927870 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11087 01:38:32.933773 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11088 01:38:32.951921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11089 01:38:32.952195 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11091 01:38:32.955677 Inputs: 1 Audio Inputs: 0 Tuners: 0
11092 01:38:32.963864
11093 01:38:32.980794 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11094 01:38:33.002169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11095 01:38:33.002458 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11097 01:38:33.008596 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11098 01:38:33.030017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11099 01:38:33.030307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11101 01:38:33.036847 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11102 01:38:33.053894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11103 01:38:33.054171 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11105 01:38:33.060185 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11106 01:38:33.078845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11107 01:38:33.079129 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11109 01:38:33.085790 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11110 01:38:33.108264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11111 01:38:33.108369
11112 01:38:33.108607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11114 01:38:33.126879 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11115 01:38:33.153845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11116 01:38:33.154157 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11118 01:38:33.160436 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11119 01:38:33.182251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11120 01:38:33.182549 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11122 01:38:33.185962 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11123 01:38:33.203270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11124 01:38:33.203552 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11126 01:38:33.206784 test VIDIOC_G/S_EDID: OK (Not Supported)
11127 01:38:33.232767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11128 01:38:33.232897
11129 01:38:33.233141 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11131 01:38:33.243440 Control ioctls (Input 0):
11132 01:38:33.250242 <LAVA_SIGNAL_TESTSET STOP>
11133 01:38:33.250543 Received signal: <TESTSET> STOP
11134 01:38:33.250646 Closing test_set Input-ioctls
11135 01:38:33.260276 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11136 01:38:33.260554 Received signal: <TESTSET> START Control-ioctls-Input-0
11137 01:38:33.260648 Starting test_set Control-ioctls-Input-0
11138 01:38:33.263573 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11139 01:38:33.288559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11140 01:38:33.288691 test VIDIOC_QUERYCTRL: OK
11141 01:38:33.288951 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11143 01:38:33.310705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11144 01:38:33.310989 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11146 01:38:33.313673 test VIDIOC_G/S_CTRL: OK
11147 01:38:33.336199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11148 01:38:33.336492 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11150 01:38:33.339204 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11151 01:38:33.365789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11152 01:38:33.366081 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11154 01:38:33.372479 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11155 01:38:33.394901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11156 01:38:33.395316 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11158 01:38:33.397821 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11159 01:38:33.419975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11160 01:38:33.420256 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11162 01:38:33.423847 Standard Controls: 16 Private Controls: 0
11163 01:38:33.433700
11164 01:38:33.446549 Format ioctls (Input 0):
11165 01:38:33.453634 <LAVA_SIGNAL_TESTSET STOP>
11166 01:38:33.453893 Received signal: <TESTSET> STOP
11167 01:38:33.453963 Closing test_set Control-ioctls-Input-0
11168 01:38:33.463267 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11169 01:38:33.463523 Received signal: <TESTSET> START Format-ioctls-Input-0
11170 01:38:33.463594 Starting test_set Format-ioctls-Input-0
11171 01:38:33.466469 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11172 01:38:33.493758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11173 01:38:33.494047 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11175 01:38:33.497269 test VIDIOC_G/S_PARM: OK
11176 01:38:33.521397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11177 01:38:33.521687 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11179 01:38:33.524810 test VIDIOC_G_FBUF: OK (Not Supported)
11180 01:38:33.547554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11181 01:38:33.547845 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11183 01:38:33.551096 test VIDIOC_G_FMT: OK
11184 01:38:33.574110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11185 01:38:33.574389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11187 01:38:33.577141 test VIDIOC_TRY_FMT: OK
11188 01:38:33.598629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11189 01:38:33.598900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11191 01:38:33.604607 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11192 01:38:33.610339 test VIDIOC_S_FMT: OK
11193 01:38:33.635502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11194 01:38:33.635785 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11196 01:38:33.638755 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11197 01:38:33.660296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11198 01:38:33.660576 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11200 01:38:33.663452 test Cropping: OK (Not Supported)
11201 01:38:33.682454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11202 01:38:33.682720 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11204 01:38:33.685916 test Composing: OK (Not Supported)
11205 01:38:33.713611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11206 01:38:33.713910 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11208 01:38:33.717198 test Scaling: OK (Not Supported)
11209 01:38:33.738387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11210 01:38:33.738484
11211 01:38:33.738723 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11213 01:38:33.750407 Codec ioctls (Input 0):
11214 01:38:33.757342 <LAVA_SIGNAL_TESTSET STOP>
11215 01:38:33.757599 Received signal: <TESTSET> STOP
11216 01:38:33.757670 Closing test_set Format-ioctls-Input-0
11217 01:38:33.765992 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11218 01:38:33.766246 Received signal: <TESTSET> START Codec-ioctls-Input-0
11219 01:38:33.766314 Starting test_set Codec-ioctls-Input-0
11220 01:38:33.769440 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11221 01:38:33.791574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11222 01:38:33.791848 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11224 01:38:33.798303 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11225 01:38:33.816415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11226 01:38:33.816685 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11228 01:38:33.822390 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11229 01:38:33.839890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11230 01:38:33.840000
11231 01:38:33.840251 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11233 01:38:33.850071 Buffer ioctls (Input 0):
11234 01:38:33.856885 <LAVA_SIGNAL_TESTSET STOP>
11235 01:38:33.857139 Received signal: <TESTSET> STOP
11236 01:38:33.857207 Closing test_set Codec-ioctls-Input-0
11237 01:38:33.866911 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11238 01:38:33.867181 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11239 01:38:33.867268 Starting test_set Buffer-ioctls-Input-0
11240 01:38:33.870420 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11241 01:38:33.894966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11242 01:38:33.895244 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11244 01:38:33.898949 test CREATE_BUFS maximum buffers: OK
11245 01:38:33.918306 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11247 01:38:33.921550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11248 01:38:33.921633 test VIDIOC_EXPBUF: OK
11249 01:38:33.942156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11250 01:38:33.942428 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11252 01:38:33.945161 test Requests: OK (Not Supported)
11253 01:38:33.973208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11254 01:38:33.973394
11255 01:38:33.973651 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11257 01:38:33.989064 Test input 0:
11258 01:38:33.997828
11259 01:38:34.007333 Streaming ioctls:
11260 01:38:34.014063 <LAVA_SIGNAL_TESTSET STOP>
11261 01:38:34.014330 Received signal: <TESTSET> STOP
11262 01:38:34.014415 Closing test_set Buffer-ioctls-Input-0
11263 01:38:34.022950 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11264 01:38:34.023215 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11265 01:38:34.023288 Starting test_set Streaming-ioctls_Test-input-0
11266 01:38:34.026320 test read/write: OK (Not Supported)
11267 01:38:34.056260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11268 01:38:34.056560 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11270 01:38:34.059969 test blocking wait: OK
11271 01:38:34.080040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11272 01:38:34.080319 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11274 01:38:34.086375 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11275 01:38:34.089734 test MMAP (no poll): FAIL
11276 01:38:34.117193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11277 01:38:34.117544 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11279 01:38:34.124018 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11280 01:38:34.128315 test MMAP (select): FAIL
11281 01:38:34.156494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11282 01:38:34.156802 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11284 01:38:34.163075 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11285 01:38:34.166433 test MMAP (epoll): FAIL
11286 01:38:34.192373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11287 01:38:34.192493
11288 01:38:34.192733 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11290 01:38:34.205449
11291 01:38:34.394737
11292 01:38:34.399656 test USERPTR (no poll): OK
11293 01:38:34.425233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11294 01:38:34.425358
11295 01:38:34.425597 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11297 01:38:34.440161
11298 01:38:34.622918
11299 01:38:34.631749 test USERPTR (select): OK
11300 01:38:34.656032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11301 01:38:34.656312 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11303 01:38:34.662556 test DMABUF: Cannot test, specify --expbuf-device
11304 01:38:34.669953
11305 01:38:34.687716 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11306 01:38:34.693894 <LAVA_TEST_RUNNER EXIT>
11307 01:38:34.694156 ok: lava_test_shell seems to have completed
11308 01:38:34.694233 Marking unfinished test run as failed
11310 01:38:34.695191 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11311 01:38:34.695318 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11312 01:38:34.695406 end: 3 lava-test-retry (duration 00:00:10) [common]
11313 01:38:34.695492 start: 4 finalize (timeout 00:07:15) [common]
11314 01:38:34.695585 start: 4.1 power-off (timeout 00:00:30) [common]
11315 01:38:34.695734 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11316 01:38:34.895249 >> Command sent successfully.
11317 01:38:34.897705 Returned 0 in 0 seconds
11318 01:38:34.998196 end: 4.1 power-off (duration 00:00:00) [common]
11320 01:38:34.998601 start: 4.2 read-feedback (timeout 00:07:14) [common]
11321 01:38:34.998911 Listened to connection for namespace 'common' for up to 1s
11322 01:38:36.000007 Finalising connection for namespace 'common'
11323 01:38:36.000652 Disconnecting from shell: Finalise
11324 01:38:36.001019 / #
11325 01:38:36.102149 end: 4.2 read-feedback (duration 00:00:01) [common]
11326 01:38:36.102932 end: 4 finalize (duration 00:00:01) [common]
11327 01:38:36.103552 Cleaning after the job
11328 01:38:36.104183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/ramdisk
11329 01:38:36.123869 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/kernel
11330 01:38:36.153311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/dtb
11331 01:38:36.153613 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173516/tftp-deploy-pbvb5vjh/modules
11332 01:38:36.160898 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173516
11333 01:38:36.222670 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173516
11334 01:38:36.222852 Job finished correctly