Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
1 01:35:03.167883 lava-dispatcher, installed at version: 2024.03
2 01:35:03.168086 start: 0 validate
3 01:35:03.168217 Start time: 2024-06-05 01:35:03.168209+00:00 (UTC)
4 01:35:03.168339 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:35:03.168466 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:35:03.439893 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:35:03.440643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:35:03.695401 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:35:03.696180 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:35:03.951256 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:35:03.951954 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:35:04.212013 validate duration: 1.04
14 01:35:04.213435 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:35:04.214074 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:35:04.214642 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:35:04.215309 Not decompressing ramdisk as can be used compressed.
18 01:35:04.215800 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:35:04.216168 saving as /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/ramdisk/rootfs.cpio.gz
20 01:35:04.216526 total size: 47897469 (45 MB)
21 01:35:04.221715 progress 0 % (0 MB)
22 01:35:04.262470 progress 5 % (2 MB)
23 01:35:04.278749 progress 10 % (4 MB)
24 01:35:04.291367 progress 15 % (6 MB)
25 01:35:04.303484 progress 20 % (9 MB)
26 01:35:04.315613 progress 25 % (11 MB)
27 01:35:04.327666 progress 30 % (13 MB)
28 01:35:04.339693 progress 35 % (16 MB)
29 01:35:04.351666 progress 40 % (18 MB)
30 01:35:04.363930 progress 45 % (20 MB)
31 01:35:04.375993 progress 50 % (22 MB)
32 01:35:04.388275 progress 55 % (25 MB)
33 01:35:04.401117 progress 60 % (27 MB)
34 01:35:04.413633 progress 65 % (29 MB)
35 01:35:04.427120 progress 70 % (32 MB)
36 01:35:04.439538 progress 75 % (34 MB)
37 01:35:04.451971 progress 80 % (36 MB)
38 01:35:04.464578 progress 85 % (38 MB)
39 01:35:04.476873 progress 90 % (41 MB)
40 01:35:04.489121 progress 95 % (43 MB)
41 01:35:04.500957 progress 100 % (45 MB)
42 01:35:04.501216 45 MB downloaded in 0.28 s (160.44 MB/s)
43 01:35:04.501375 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:35:04.501794 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:35:04.501883 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:35:04.501967 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:35:04.502101 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:35:04.502171 saving as /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/kernel/Image
50 01:35:04.502232 total size: 54682112 (52 MB)
51 01:35:04.502294 No compression specified
52 01:35:04.503508 progress 0 % (0 MB)
53 01:35:04.518335 progress 5 % (2 MB)
54 01:35:04.532365 progress 10 % (5 MB)
55 01:35:04.546387 progress 15 % (7 MB)
56 01:35:04.560240 progress 20 % (10 MB)
57 01:35:04.574204 progress 25 % (13 MB)
58 01:35:04.588105 progress 30 % (15 MB)
59 01:35:04.602125 progress 35 % (18 MB)
60 01:35:04.615899 progress 40 % (20 MB)
61 01:35:04.629673 progress 45 % (23 MB)
62 01:35:04.643576 progress 50 % (26 MB)
63 01:35:04.657242 progress 55 % (28 MB)
64 01:35:04.671253 progress 60 % (31 MB)
65 01:35:04.685186 progress 65 % (33 MB)
66 01:35:04.699159 progress 70 % (36 MB)
67 01:35:04.712983 progress 75 % (39 MB)
68 01:35:04.726894 progress 80 % (41 MB)
69 01:35:04.740533 progress 85 % (44 MB)
70 01:35:04.754211 progress 90 % (46 MB)
71 01:35:04.767986 progress 95 % (49 MB)
72 01:35:04.781400 progress 100 % (52 MB)
73 01:35:04.781623 52 MB downloaded in 0.28 s (186.65 MB/s)
74 01:35:04.781771 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:35:04.782004 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:35:04.782090 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:35:04.782197 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:35:04.782346 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:35:04.782435 saving as /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/dtb/mt8192-asurada-spherion-r0.dtb
81 01:35:04.782510 total size: 47258 (0 MB)
82 01:35:04.782570 No compression specified
83 01:35:04.783635 progress 69 % (0 MB)
84 01:35:04.783897 progress 100 % (0 MB)
85 01:35:04.784048 0 MB downloaded in 0.00 s (29.35 MB/s)
86 01:35:04.784166 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:35:04.784384 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:35:04.784466 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:35:04.784548 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:35:04.784655 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:35:04.784723 saving as /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/modules/modules.tar
93 01:35:04.784782 total size: 8605984 (8 MB)
94 01:35:04.784842 Using unxz to decompress xz
95 01:35:04.788953 progress 0 % (0 MB)
96 01:35:04.807749 progress 5 % (0 MB)
97 01:35:04.834054 progress 10 % (0 MB)
98 01:35:04.863274 progress 15 % (1 MB)
99 01:35:04.886732 progress 20 % (1 MB)
100 01:35:04.910198 progress 25 % (2 MB)
101 01:35:04.933367 progress 30 % (2 MB)
102 01:35:04.957218 progress 35 % (2 MB)
103 01:35:04.983666 progress 40 % (3 MB)
104 01:35:05.006246 progress 45 % (3 MB)
105 01:35:05.029750 progress 50 % (4 MB)
106 01:35:05.054080 progress 55 % (4 MB)
107 01:35:05.078347 progress 60 % (4 MB)
108 01:35:05.102287 progress 65 % (5 MB)
109 01:35:05.126763 progress 70 % (5 MB)
110 01:35:05.150124 progress 75 % (6 MB)
111 01:35:05.177663 progress 80 % (6 MB)
112 01:35:05.201963 progress 85 % (7 MB)
113 01:35:05.226831 progress 90 % (7 MB)
114 01:35:05.251514 progress 95 % (7 MB)
115 01:35:05.276373 progress 100 % (8 MB)
116 01:35:05.281758 8 MB downloaded in 0.50 s (16.51 MB/s)
117 01:35:05.281993 end: 1.4.1 http-download (duration 00:00:00) [common]
119 01:35:05.282262 end: 1.4 download-retry (duration 00:00:00) [common]
120 01:35:05.282357 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:35:05.282455 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:35:05.282538 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:35:05.282627 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:35:05.282856 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph
125 01:35:05.282990 makedir: /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin
126 01:35:05.283095 makedir: /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/tests
127 01:35:05.283195 makedir: /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/results
128 01:35:05.283315 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-add-keys
129 01:35:05.283473 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-add-sources
130 01:35:05.283607 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-background-process-start
131 01:35:05.283739 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-background-process-stop
132 01:35:05.283865 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-common-functions
133 01:35:05.283989 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-echo-ipv4
134 01:35:05.284114 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-install-packages
135 01:35:05.284239 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-installed-packages
136 01:35:05.284362 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-os-build
137 01:35:05.284488 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-probe-channel
138 01:35:05.284612 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-probe-ip
139 01:35:05.284735 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-target-ip
140 01:35:05.284858 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-target-mac
141 01:35:05.284991 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-target-storage
142 01:35:05.285159 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-case
143 01:35:05.285284 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-event
144 01:35:05.285440 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-feedback
145 01:35:05.285588 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-raise
146 01:35:05.285716 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-reference
147 01:35:05.285841 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-runner
148 01:35:05.285965 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-set
149 01:35:05.286091 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-test-shell
150 01:35:05.286219 Updating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-install-packages (oe)
151 01:35:05.286371 Updating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/bin/lava-installed-packages (oe)
152 01:35:05.286495 Creating /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/environment
153 01:35:05.286596 LAVA metadata
154 01:35:05.286669 - LAVA_JOB_ID=14173506
155 01:35:05.286733 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:35:05.286833 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:35:05.286903 skipped lava-vland-overlay
158 01:35:05.286977 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:35:05.287062 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:35:05.287127 skipped lava-multinode-overlay
161 01:35:05.287199 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:35:05.287293 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:35:05.287386 Loading test definitions
164 01:35:05.287479 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:35:05.287555 Using /lava-14173506 at stage 0
166 01:35:05.287867 uuid=14173506_1.5.2.3.1 testdef=None
167 01:35:05.287959 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:35:05.288047 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:35:05.288564 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:35:05.288790 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:35:05.289456 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:35:05.289686 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:35:05.290268 runner path: /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/0/tests/0_igt-kms-mediatek test_uuid 14173506_1.5.2.3.1
176 01:35:05.290435 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:35:05.290641 Creating lava-test-runner.conf files
179 01:35:05.290705 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173506/lava-overlay-p06a6iph/lava-14173506/0 for stage 0
180 01:35:05.290794 - 0_igt-kms-mediatek
181 01:35:05.290893 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:35:05.290981 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:35:05.298210 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:35:05.298313 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:35:05.298399 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:35:05.298486 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:35:05.298572 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:35:07.024622 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 01:35:07.025018 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 01:35:07.025135 extracting modules file /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173506/extract-overlay-ramdisk-r25i_i3a/ramdisk
191 01:35:07.241543 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:35:07.241712 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 01:35:07.241804 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173506/compress-overlay-9cped2qw/overlay-1.5.2.4.tar.gz to ramdisk
194 01:35:07.241878 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173506/compress-overlay-9cped2qw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173506/extract-overlay-ramdisk-r25i_i3a/ramdisk
195 01:35:07.248205 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:35:07.248376 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 01:35:07.248530 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:35:07.248661 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 01:35:07.248745 Building ramdisk /var/lib/lava/dispatcher/tmp/14173506/extract-overlay-ramdisk-r25i_i3a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173506/extract-overlay-ramdisk-r25i_i3a/ramdisk
200 01:35:08.404288 >> 465932 blocks
201 01:35:14.585139 rename /var/lib/lava/dispatcher/tmp/14173506/extract-overlay-ramdisk-r25i_i3a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/ramdisk/ramdisk.cpio.gz
202 01:35:14.585582 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 01:35:14.585702 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 01:35:14.585824 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 01:35:14.585930 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/kernel/Image']
206 01:35:27.430968 Returned 0 in 12 seconds
207 01:35:27.532068 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/kernel/image.itb
208 01:35:28.405975 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:35:28.406343 output: Created: Wed Jun 5 02:35:28 2024
210 01:35:28.406445 output: Image 0 (kernel-1)
211 01:35:28.406508 output: Description:
212 01:35:28.406566 output: Created: Wed Jun 5 02:35:28 2024
213 01:35:28.406628 output: Type: Kernel Image
214 01:35:28.406688 output: Compression: lzma compressed
215 01:35:28.406745 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
216 01:35:28.406804 output: Architecture: AArch64
217 01:35:28.406861 output: OS: Linux
218 01:35:28.406919 output: Load Address: 0x00000000
219 01:35:28.406976 output: Entry Point: 0x00000000
220 01:35:28.407033 output: Hash algo: crc32
221 01:35:28.407101 output: Hash value: 4c96ec19
222 01:35:28.407158 output: Image 1 (fdt-1)
223 01:35:28.407211 output: Description: mt8192-asurada-spherion-r0
224 01:35:28.407263 output: Created: Wed Jun 5 02:35:28 2024
225 01:35:28.407314 output: Type: Flat Device Tree
226 01:35:28.407366 output: Compression: uncompressed
227 01:35:28.407417 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 01:35:28.407525 output: Architecture: AArch64
229 01:35:28.407582 output: Hash algo: crc32
230 01:35:28.407644 output: Hash value: 0f8e4d2e
231 01:35:28.407695 output: Image 2 (ramdisk-1)
232 01:35:28.407768 output: Description: unavailable
233 01:35:28.407832 output: Created: Wed Jun 5 02:35:28 2024
234 01:35:28.407883 output: Type: RAMDisk Image
235 01:35:28.407935 output: Compression: Unknown Compression
236 01:35:28.407985 output: Data Size: 60993338 Bytes = 59563.81 KiB = 58.17 MiB
237 01:35:28.408037 output: Architecture: AArch64
238 01:35:28.408088 output: OS: Linux
239 01:35:28.408139 output: Load Address: unavailable
240 01:35:28.408190 output: Entry Point: unavailable
241 01:35:28.408241 output: Hash algo: crc32
242 01:35:28.408291 output: Hash value: 59d4398b
243 01:35:28.408341 output: Default Configuration: 'conf-1'
244 01:35:28.408392 output: Configuration 0 (conf-1)
245 01:35:28.408442 output: Description: mt8192-asurada-spherion-r0
246 01:35:28.408493 output: Kernel: kernel-1
247 01:35:28.408543 output: Init Ramdisk: ramdisk-1
248 01:35:28.408593 output: FDT: fdt-1
249 01:35:28.408644 output: Loadables: kernel-1
250 01:35:28.408694 output:
251 01:35:28.408892 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:35:28.408993 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:35:28.409134 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 01:35:28.409223 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 01:35:28.409301 No LXC device requested
256 01:35:28.409379 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:35:28.409464 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 01:35:28.409541 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:35:28.409609 Checking files for TFTP limit of 4294967296 bytes.
260 01:35:28.410114 end: 1 tftp-deploy (duration 00:00:24) [common]
261 01:35:28.410213 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:35:28.410305 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:35:28.410420 substitutions:
264 01:35:28.410484 - {DTB}: 14173506/tftp-deploy-nsa4wev3/dtb/mt8192-asurada-spherion-r0.dtb
265 01:35:28.410548 - {INITRD}: 14173506/tftp-deploy-nsa4wev3/ramdisk/ramdisk.cpio.gz
266 01:35:28.410606 - {KERNEL}: 14173506/tftp-deploy-nsa4wev3/kernel/Image
267 01:35:28.410661 - {LAVA_MAC}: None
268 01:35:28.410715 - {PRESEED_CONFIG}: None
269 01:35:28.410768 - {PRESEED_LOCAL}: None
270 01:35:28.410821 - {RAMDISK}: 14173506/tftp-deploy-nsa4wev3/ramdisk/ramdisk.cpio.gz
271 01:35:28.410874 - {ROOT_PART}: None
272 01:35:28.410927 - {ROOT}: None
273 01:35:28.410979 - {SERVER_IP}: 192.168.201.1
274 01:35:28.411031 - {TEE}: None
275 01:35:28.411084 Parsed boot commands:
276 01:35:28.411138 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:35:28.411307 Parsed boot commands: tftpboot 192.168.201.1 14173506/tftp-deploy-nsa4wev3/kernel/image.itb 14173506/tftp-deploy-nsa4wev3/kernel/cmdline
278 01:35:28.411394 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:35:28.411478 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:35:28.411567 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:35:28.411649 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:35:28.411717 Not connected, no need to disconnect.
283 01:35:28.411788 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:35:28.411867 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:35:28.411933 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 01:35:28.415532 Setting prompt string to ['lava-test: # ']
287 01:35:28.415882 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:35:28.415983 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:35:28.416082 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:35:28.416217 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:35:28.416462 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 01:35:33.565400 >> Command sent successfully.
293 01:35:33.575862 Returned 0 in 5 seconds
294 01:35:33.677149 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:35:33.678772 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:35:33.679298 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:35:33.679802 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:35:33.680178 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:35:33.680603 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:35:33.682609 [Enter `^Ec?' for help]
302 01:35:33.842191
303 01:35:33.842760
304 01:35:33.843161 F0: 102B 0000
305 01:35:33.843533
306 01:35:33.843882 F3: 1001 0000 [0200]
307 01:35:33.845107
308 01:35:33.845602 F3: 1001 0000
309 01:35:33.846033
310 01:35:33.846392 F7: 102D 0000
311 01:35:33.846734
312 01:35:33.848297 F1: 0000 0000
313 01:35:33.848769
314 01:35:33.849245 V0: 0000 0000 [0001]
315 01:35:33.849614
316 01:35:33.852289 00: 0007 8000
317 01:35:33.852739
318 01:35:33.853125 01: 0000 0000
319 01:35:33.853460
320 01:35:33.854943 BP: 0C00 0209 [0000]
321 01:35:33.855363
322 01:35:33.855741 G0: 1182 0000
323 01:35:33.856308
324 01:35:33.858649 EC: 0000 0021 [4000]
325 01:35:33.859214
326 01:35:33.859717 S7: 0000 0000 [0000]
327 01:35:33.860185
328 01:35:33.862405 CC: 0000 0000 [0001]
329 01:35:33.862826
330 01:35:33.863164 T0: 0000 0040 [010F]
331 01:35:33.863482
332 01:35:33.863789 Jump to BL
333 01:35:33.864090
334 01:35:33.888757
335 01:35:33.889334
336 01:35:33.896241 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 01:35:33.899913 ARM64: Exception handlers installed.
338 01:35:33.903492 ARM64: Testing exception
339 01:35:33.906974 ARM64: Done test exception
340 01:35:33.913435 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 01:35:33.923523 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 01:35:33.930214 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 01:35:33.940623 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 01:35:33.947717 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 01:35:33.954101 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 01:35:33.965323 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 01:35:33.972405 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 01:35:33.991241 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 01:35:33.994639 WDT: Last reset was cold boot
350 01:35:33.998584 SPI1(PAD0) initialized at 2873684 Hz
351 01:35:34.001583 SPI5(PAD0) initialized at 992727 Hz
352 01:35:34.004932 VBOOT: Loading verstage.
353 01:35:34.011504 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 01:35:34.014754 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 01:35:34.018067 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 01:35:34.021231 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 01:35:34.029351 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 01:35:34.035930 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 01:35:34.048472 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
360 01:35:34.049089
361 01:35:34.049478
362 01:35:34.057286 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 01:35:34.061407 ARM64: Exception handlers installed.
364 01:35:34.063562 ARM64: Testing exception
365 01:35:34.064160 ARM64: Done test exception
366 01:35:34.070816 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 01:35:34.075255 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 01:35:34.087892 Probing TPM: . done!
369 01:35:34.088510 TPM ready after 0 ms
370 01:35:34.092965 Connected to device vid:did:rid of 1ae0:0028:00
371 01:35:34.103871 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 01:35:34.160406 Initialized TPM device CR50 revision 0
373 01:35:34.171949 tlcl_send_startup: Startup return code is 0
374 01:35:34.172409 TPM: setup succeeded
375 01:35:34.183626 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 01:35:34.192379 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 01:35:34.204272 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 01:35:34.215293 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 01:35:34.217931 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 01:35:34.222693 in-header: 03 07 00 00 08 00 00 00
381 01:35:34.227719 in-data: aa e4 47 04 13 02 00 00
382 01:35:34.230235 Chrome EC: UHEPI supported
383 01:35:34.237287 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 01:35:34.241288 in-header: 03 ad 00 00 08 00 00 00
385 01:35:34.244748 in-data: 00 20 20 08 00 00 00 00
386 01:35:34.245285 Phase 1
387 01:35:34.249144 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 01:35:34.256013 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 01:35:34.259592 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 01:35:34.263121 Recovery requested (1009000e)
391 01:35:34.273058 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 01:35:34.277659 tlcl_extend: response is 0
393 01:35:34.287092 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 01:35:34.292251 tlcl_extend: response is 0
395 01:35:34.299310 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 01:35:34.319549 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
397 01:35:34.326908 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 01:35:34.327484
399 01:35:34.327865
400 01:35:34.336655 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 01:35:34.341228 ARM64: Exception handlers installed.
402 01:35:34.341805 ARM64: Testing exception
403 01:35:34.344019 ARM64: Done test exception
404 01:35:34.364490 pmic_efuse_setting: Set efuses in 11 msecs
405 01:35:34.368159 pmwrap_interface_init: Select PMIF_VLD_RDY
406 01:35:34.375639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 01:35:34.378792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 01:35:34.383145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 01:35:34.389308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 01:35:34.393867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 01:35:34.397818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 01:35:34.404760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 01:35:34.408566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 01:35:34.412611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 01:35:34.415742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 01:35:34.423270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 01:35:34.427509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 01:35:34.430956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 01:35:34.439042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 01:35:34.442923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 01:35:34.449958 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 01:35:34.453200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 01:35:34.461076 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 01:35:34.464154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 01:35:34.472926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 01:35:34.475971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 01:35:34.483366 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 01:35:34.487799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 01:35:34.494493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 01:35:34.497992 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 01:35:34.506903 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 01:35:34.509770 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 01:35:34.513347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 01:35:34.520829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 01:35:34.523839 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 01:35:34.528377 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 01:35:34.535193 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 01:35:34.539358 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 01:35:34.542696 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 01:35:34.549505 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 01:35:34.553727 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 01:35:34.557719 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 01:35:34.565170 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 01:35:34.568356 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 01:35:34.572859 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 01:35:34.576463 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 01:35:34.582799 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 01:35:34.587886 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 01:35:34.591059 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 01:35:34.594764 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 01:35:34.597798 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 01:35:34.602271 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 01:35:34.609585 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 01:35:34.613076 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 01:35:34.617241 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 01:35:34.620494 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 01:35:34.628762 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 01:35:34.635392 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 01:35:34.638855 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 01:35:34.649817 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 01:35:34.658310 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 01:35:34.661740 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 01:35:34.664767 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 01:35:34.673292 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:35:34.676429 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
466 01:35:34.684211 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 01:35:34.687340 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 01:35:34.691315 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 01:35:34.702540 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 01:35:34.711879 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 01:35:34.723131 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 01:35:34.731083 [RTC]rtc_get_frequency_meter,154: input=17, output=838
473 01:35:34.740270 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 01:35:34.749968 [RTC]rtc_get_frequency_meter,154: input=15, output=789
475 01:35:34.760435 [RTC]rtc_get_frequency_meter,154: input=16, output=813
476 01:35:34.763553 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 01:35:34.767704 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 01:35:34.771157 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 01:35:34.779447 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 01:35:34.781959 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 01:35:34.785924 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 01:35:34.790201 ADC[4]: Raw value=901328 ID=7
483 01:35:34.790767 ADC[3]: Raw value=213336 ID=1
484 01:35:34.794594 RAM Code: 0x71
485 01:35:34.798513 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 01:35:34.801119 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 01:35:34.813332 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 01:35:34.815976 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 01:35:34.818899 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 01:35:34.823201 in-header: 03 07 00 00 08 00 00 00
491 01:35:34.826795 in-data: aa e4 47 04 13 02 00 00
492 01:35:34.830766 Chrome EC: UHEPI supported
493 01:35:34.837980 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 01:35:34.841916 in-header: 03 ed 00 00 08 00 00 00
495 01:35:34.842410 in-data: 80 20 60 08 00 00 00 00
496 01:35:34.845258 MRC: failed to locate region type 0.
497 01:35:34.852685 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 01:35:34.856740 DRAM-K: Running full calibration
499 01:35:34.860707 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 01:35:34.864693 header.status = 0x0
501 01:35:34.868027 header.version = 0x6 (expected: 0x6)
502 01:35:34.871609 header.size = 0xd00 (expected: 0xd00)
503 01:35:34.872162 header.flags = 0x0
504 01:35:34.878763 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 01:35:34.898161 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
506 01:35:34.904469 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 01:35:34.905091 dram_init: ddr_geometry: 2
508 01:35:34.908209 [EMI] MDL number = 2
509 01:35:34.911599 [EMI] Get MDL freq = 0
510 01:35:34.912077 dram_init: ddr_type: 0
511 01:35:34.915646 is_discrete_lpddr4: 1
512 01:35:34.918525 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 01:35:34.919010
514 01:35:34.919391
515 01:35:34.919749 [Bian_co] ETT version 0.0.0.1
516 01:35:34.926371 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 01:35:34.926970
518 01:35:34.929452 dramc_set_vcore_voltage set vcore to 650000
519 01:35:34.932575 Read voltage for 800, 4
520 01:35:34.933092 Vio18 = 0
521 01:35:34.933481 Vcore = 650000
522 01:35:34.935822 Vdram = 0
523 01:35:34.936303 Vddq = 0
524 01:35:34.936684 Vmddr = 0
525 01:35:34.939416 dram_init: config_dvfs: 1
526 01:35:34.942522 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 01:35:34.949442 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 01:35:34.953078 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 01:35:34.956541 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 01:35:34.959006 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 01:35:34.962478 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 01:35:34.966654 MEM_TYPE=3, freq_sel=18
533 01:35:34.969176 sv_algorithm_assistance_LP4_1600
534 01:35:34.972675 ============ PULL DRAM RESETB DOWN ============
535 01:35:34.976385 ========== PULL DRAM RESETB DOWN end =========
536 01:35:34.982934 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 01:35:34.986392 ===================================
538 01:35:34.989806 LPDDR4 DRAM CONFIGURATION
539 01:35:34.993092 ===================================
540 01:35:34.993681 EX_ROW_EN[0] = 0x0
541 01:35:34.996128 EX_ROW_EN[1] = 0x0
542 01:35:34.996609 LP4Y_EN = 0x0
543 01:35:35.001014 WORK_FSP = 0x0
544 01:35:35.001607 WL = 0x2
545 01:35:35.003304 RL = 0x2
546 01:35:35.003783 BL = 0x2
547 01:35:35.006889 RPST = 0x0
548 01:35:35.007474 RD_PRE = 0x0
549 01:35:35.009752 WR_PRE = 0x1
550 01:35:35.010229 WR_PST = 0x0
551 01:35:35.012741 DBI_WR = 0x0
552 01:35:35.013274 DBI_RD = 0x0
553 01:35:35.016456 OTF = 0x1
554 01:35:35.019775 ===================================
555 01:35:35.022875 ===================================
556 01:35:35.023469 ANA top config
557 01:35:35.026360 ===================================
558 01:35:35.031082 DLL_ASYNC_EN = 0
559 01:35:35.033275 ALL_SLAVE_EN = 1
560 01:35:35.036774 NEW_RANK_MODE = 1
561 01:35:35.037293 DLL_IDLE_MODE = 1
562 01:35:35.039690 LP45_APHY_COMB_EN = 1
563 01:35:35.043926 TX_ODT_DIS = 1
564 01:35:35.046476 NEW_8X_MODE = 1
565 01:35:35.049687 ===================================
566 01:35:35.053291 ===================================
567 01:35:35.053771 data_rate = 1600
568 01:35:35.056770 CKR = 1
569 01:35:35.059829 DQ_P2S_RATIO = 8
570 01:35:35.063549 ===================================
571 01:35:35.067353 CA_P2S_RATIO = 8
572 01:35:35.069875 DQ_CA_OPEN = 0
573 01:35:35.073279 DQ_SEMI_OPEN = 0
574 01:35:35.073771 CA_SEMI_OPEN = 0
575 01:35:35.076793 CA_FULL_RATE = 0
576 01:35:35.080390 DQ_CKDIV4_EN = 1
577 01:35:35.083903 CA_CKDIV4_EN = 1
578 01:35:35.086826 CA_PREDIV_EN = 0
579 01:35:35.087367 PH8_DLY = 0
580 01:35:35.090456 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 01:35:35.093474 DQ_AAMCK_DIV = 4
582 01:35:35.096970 CA_AAMCK_DIV = 4
583 01:35:35.100385 CA_ADMCK_DIV = 4
584 01:35:35.103993 DQ_TRACK_CA_EN = 0
585 01:35:35.104538 CA_PICK = 800
586 01:35:35.107558 CA_MCKIO = 800
587 01:35:35.109976 MCKIO_SEMI = 0
588 01:35:35.113923 PLL_FREQ = 3068
589 01:35:35.118000 DQ_UI_PI_RATIO = 32
590 01:35:35.121447 CA_UI_PI_RATIO = 0
591 01:35:35.122149 ===================================
592 01:35:35.124961 ===================================
593 01:35:35.129160 memory_type:LPDDR4
594 01:35:35.132376 GP_NUM : 10
595 01:35:35.132972 SRAM_EN : 1
596 01:35:35.135819 MD32_EN : 0
597 01:35:35.139609 ===================================
598 01:35:35.140090 [ANA_INIT] >>>>>>>>>>>>>>
599 01:35:35.144381 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 01:35:35.147047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 01:35:35.150619 ===================================
602 01:35:35.155042 data_rate = 1600,PCW = 0X7600
603 01:35:35.155523 ===================================
604 01:35:35.161284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 01:35:35.164179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 01:35:35.171870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:35:35.174468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 01:35:35.177683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 01:35:35.182108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:35:35.185272 [ANA_INIT] flow start
611 01:35:35.185860 [ANA_INIT] PLL >>>>>>>>
612 01:35:35.187639 [ANA_INIT] PLL <<<<<<<<
613 01:35:35.191768 [ANA_INIT] MIDPI >>>>>>>>
614 01:35:35.194248 [ANA_INIT] MIDPI <<<<<<<<
615 01:35:35.194743 [ANA_INIT] DLL >>>>>>>>
616 01:35:35.198522 [ANA_INIT] flow end
617 01:35:35.201369 ============ LP4 DIFF to SE enter ============
618 01:35:35.204503 ============ LP4 DIFF to SE exit ============
619 01:35:35.208577 [ANA_INIT] <<<<<<<<<<<<<
620 01:35:35.211524 [Flow] Enable top DCM control >>>>>
621 01:35:35.214610 [Flow] Enable top DCM control <<<<<
622 01:35:35.218357 Enable DLL master slave shuffle
623 01:35:35.221621 ==============================================================
624 01:35:35.225769 Gating Mode config
625 01:35:35.232081 ==============================================================
626 01:35:35.232679 Config description:
627 01:35:35.242990 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 01:35:35.248202 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 01:35:35.251790 SELPH_MODE 0: By rank 1: By Phase
630 01:35:35.258393 ==============================================================
631 01:35:35.261803 GAT_TRACK_EN = 1
632 01:35:35.265424 RX_GATING_MODE = 2
633 01:35:35.268478 RX_GATING_TRACK_MODE = 2
634 01:35:35.271576 SELPH_MODE = 1
635 01:35:35.275052 PICG_EARLY_EN = 1
636 01:35:35.275533 VALID_LAT_VALUE = 1
637 01:35:35.282272 ==============================================================
638 01:35:35.285755 Enter into Gating configuration >>>>
639 01:35:35.288514 Exit from Gating configuration <<<<
640 01:35:35.291775 Enter into DVFS_PRE_config >>>>>
641 01:35:35.301920 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 01:35:35.305184 Exit from DVFS_PRE_config <<<<<
643 01:35:35.309337 Enter into PICG configuration >>>>
644 01:35:35.312004 Exit from PICG configuration <<<<
645 01:35:35.315258 [RX_INPUT] configuration >>>>>
646 01:35:35.318556 [RX_INPUT] configuration <<<<<
647 01:35:35.321794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 01:35:35.328769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 01:35:35.336070 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 01:35:35.340420 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 01:35:35.346741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 01:35:35.353043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 01:35:35.356037 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 01:35:35.359230 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 01:35:35.366223 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 01:35:35.369662 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 01:35:35.372733 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 01:35:35.379760 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 01:35:35.384697 ===================================
660 01:35:35.385290 LPDDR4 DRAM CONFIGURATION
661 01:35:35.386465 ===================================
662 01:35:35.389835 EX_ROW_EN[0] = 0x0
663 01:35:35.390281 EX_ROW_EN[1] = 0x0
664 01:35:35.392846 LP4Y_EN = 0x0
665 01:35:35.393404 WORK_FSP = 0x0
666 01:35:35.396237 WL = 0x2
667 01:35:35.396781 RL = 0x2
668 01:35:35.400071 BL = 0x2
669 01:35:35.400513 RPST = 0x0
670 01:35:35.408548 RD_PRE = 0x0
671 01:35:35.409256 WR_PRE = 0x1
672 01:35:35.409815 WR_PST = 0x0
673 01:35:35.410580 DBI_WR = 0x0
674 01:35:35.410977 DBI_RD = 0x0
675 01:35:35.413603 OTF = 0x1
676 01:35:35.418530 ===================================
677 01:35:35.420262 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 01:35:35.423601 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 01:35:35.426937 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 01:35:35.429672 ===================================
681 01:35:35.433282 LPDDR4 DRAM CONFIGURATION
682 01:35:35.436599 ===================================
683 01:35:35.439961 EX_ROW_EN[0] = 0x10
684 01:35:35.440403 EX_ROW_EN[1] = 0x0
685 01:35:35.443313 LP4Y_EN = 0x0
686 01:35:35.443783 WORK_FSP = 0x0
687 01:35:35.447672 WL = 0x2
688 01:35:35.448118 RL = 0x2
689 01:35:35.450535 BL = 0x2
690 01:35:35.451087 RPST = 0x0
691 01:35:35.454012 RD_PRE = 0x0
692 01:35:35.454465 WR_PRE = 0x1
693 01:35:35.456875 WR_PST = 0x0
694 01:35:35.457371 DBI_WR = 0x0
695 01:35:35.460620 DBI_RD = 0x0
696 01:35:35.461298 OTF = 0x1
697 01:35:35.463310 ===================================
698 01:35:35.470169 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 01:35:35.475423 nWR fixed to 40
700 01:35:35.478502 [ModeRegInit_LP4] CH0 RK0
701 01:35:35.478949 [ModeRegInit_LP4] CH0 RK1
702 01:35:35.481132 [ModeRegInit_LP4] CH1 RK0
703 01:35:35.484721 [ModeRegInit_LP4] CH1 RK1
704 01:35:35.485298 match AC timing 13
705 01:35:35.491670 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 01:35:35.494790 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 01:35:35.498442 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 01:35:35.504848 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 01:35:35.508162 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 01:35:35.508733 [EMI DOE] emi_dcm 0
711 01:35:35.515772 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 01:35:35.516350 ==
713 01:35:35.518544 Dram Type= 6, Freq= 0, CH_0, rank 0
714 01:35:35.521665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 01:35:35.522242 ==
716 01:35:35.528165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 01:35:35.531988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 01:35:35.542241 [CA 0] Center 37 (6~68) winsize 63
719 01:35:35.545367 [CA 1] Center 37 (6~68) winsize 63
720 01:35:35.549023 [CA 2] Center 35 (4~66) winsize 63
721 01:35:35.552847 [CA 3] Center 34 (4~65) winsize 62
722 01:35:35.555291 [CA 4] Center 34 (4~65) winsize 62
723 01:35:35.558868 [CA 5] Center 34 (4~64) winsize 61
724 01:35:35.559351
725 01:35:35.561927 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 01:35:35.562404
727 01:35:35.566511 [CATrainingPosCal] consider 1 rank data
728 01:35:35.568782 u2DelayCellTimex100 = 270/100 ps
729 01:35:35.573574 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
730 01:35:35.575499 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
731 01:35:35.579136 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
732 01:35:35.585574 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
733 01:35:35.588945 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 01:35:35.593048 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
735 01:35:35.593765
736 01:35:35.595946 CA PerBit enable=1, Macro0, CA PI delay=34
737 01:35:35.596520
738 01:35:35.599591 [CBTSetCACLKResult] CA Dly = 34
739 01:35:35.600164 CS Dly: 5 (0~36)
740 01:35:35.600550 ==
741 01:35:35.602473 Dram Type= 6, Freq= 0, CH_0, rank 1
742 01:35:35.609584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 01:35:35.610152 ==
744 01:35:35.613034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 01:35:35.619903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 01:35:35.628848 [CA 0] Center 37 (6~68) winsize 63
747 01:35:35.631698 [CA 1] Center 37 (6~68) winsize 63
748 01:35:35.635153 [CA 2] Center 35 (5~66) winsize 62
749 01:35:35.639465 [CA 3] Center 35 (4~66) winsize 63
750 01:35:35.641703 [CA 4] Center 34 (4~65) winsize 62
751 01:35:35.645585 [CA 5] Center 33 (3~64) winsize 62
752 01:35:35.646173
753 01:35:35.648472 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 01:35:35.648962
755 01:35:35.652834 [CATrainingPosCal] consider 2 rank data
756 01:35:35.655081 u2DelayCellTimex100 = 270/100 ps
757 01:35:35.658830 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
758 01:35:35.661722 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
759 01:35:35.665468 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 01:35:35.672238 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
761 01:35:35.675617 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
762 01:35:35.678259 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
763 01:35:35.678756
764 01:35:35.681949 CA PerBit enable=1, Macro0, CA PI delay=34
765 01:35:35.682552
766 01:35:35.685864 [CBTSetCACLKResult] CA Dly = 34
767 01:35:35.686355 CS Dly: 5 (0~37)
768 01:35:35.686851
769 01:35:35.688384 ----->DramcWriteLeveling(PI) begin...
770 01:35:35.688898 ==
771 01:35:35.692131 Dram Type= 6, Freq= 0, CH_0, rank 0
772 01:35:35.699368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 01:35:35.700027 ==
774 01:35:35.700540 Write leveling (Byte 0): 29 => 29
775 01:35:35.703137 Write leveling (Byte 1): 29 => 29
776 01:35:35.706108 DramcWriteLeveling(PI) end<-----
777 01:35:35.706600
778 01:35:35.707092 ==
779 01:35:35.709991 Dram Type= 6, Freq= 0, CH_0, rank 0
780 01:35:35.713862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 01:35:35.714473 ==
782 01:35:35.717952 [Gating] SW mode calibration
783 01:35:35.724508 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 01:35:35.731561 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 01:35:35.734237 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 01:35:35.737903 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 01:35:35.741578 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 01:35:35.747847 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 01:35:35.751629 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:35:35.754767 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:35:35.761666 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:35:35.765094 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:35:35.768126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:35:35.774739 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:35:35.778967 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:35:35.781517 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:35:35.787922 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:35:35.791747 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:35:35.795590 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:35:35.801827 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:35:35.805312 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:35:35.808536 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:35:35.811505 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 01:35:35.818581 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
805 01:35:35.821608 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:35:35.824937 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:35:35.831831 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:35:35.837296 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:35:35.838576 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:35:35.845417 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 01:35:35.848353 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
812 01:35:35.852409 0 9 12 | B1->B0 | 2626 3333 | 0 1 | (0 0) (1 1)
813 01:35:35.859260 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 01:35:35.861983 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 01:35:35.865250 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 01:35:35.869050 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 01:35:35.875475 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 01:35:35.879062 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 01:35:35.883021 0 10 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
820 01:35:35.889409 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
821 01:35:35.892041 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 01:35:35.895589 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:35:35.901904 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:35:35.905736 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:35:35.909137 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:35:35.915475 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:35:35.919096 0 11 8 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (0 0)
828 01:35:35.921865 0 11 12 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
829 01:35:35.929836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 01:35:35.932371 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 01:35:35.936207 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 01:35:35.940218 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 01:35:35.946604 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 01:35:35.949321 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 01:35:35.952772 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 01:35:35.959894 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 01:35:35.962549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:35:35.966114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:35:35.973088 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:35:35.976323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:35:35.979554 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:35:35.982699 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:35:35.989472 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:35:35.993539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:35:35.997406 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:35:36.002920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:35:36.006408 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:35:36.009970 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:35:36.016552 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:35:36.020091 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:35:36.023361 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 01:35:36.030522 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 01:35:36.031113 Total UI for P1: 0, mck2ui 16
854 01:35:36.036562 best dqsien dly found for B0: ( 0, 14, 8)
855 01:35:36.037210 Total UI for P1: 0, mck2ui 16
856 01:35:36.040006 best dqsien dly found for B1: ( 0, 14, 8)
857 01:35:36.043387 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 01:35:36.050235 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 01:35:36.050818
860 01:35:36.053842 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 01:35:36.057128 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 01:35:36.060693 [Gating] SW calibration Done
863 01:35:36.061325 ==
864 01:35:36.063962 Dram Type= 6, Freq= 0, CH_0, rank 0
865 01:35:36.067520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 01:35:36.068131 ==
867 01:35:36.068519 RX Vref Scan: 0
868 01:35:36.068874
869 01:35:36.070854 RX Vref 0 -> 0, step: 1
870 01:35:36.071436
871 01:35:36.073649 RX Delay -130 -> 252, step: 16
872 01:35:36.077273 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
873 01:35:36.080718 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
874 01:35:36.084013 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
875 01:35:36.090764 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
876 01:35:36.093877 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
877 01:35:36.097062 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
878 01:35:36.101188 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
879 01:35:36.104202 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
880 01:35:36.110734 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
881 01:35:36.114251 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
882 01:35:36.117457 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
883 01:35:36.120586 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
884 01:35:36.123531 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
885 01:35:36.130450 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
886 01:35:36.133681 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
887 01:35:36.137152 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
888 01:35:36.137728 ==
889 01:35:36.140599 Dram Type= 6, Freq= 0, CH_0, rank 0
890 01:35:36.143888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 01:35:36.144474 ==
892 01:35:36.147300 DQS Delay:
893 01:35:36.147779 DQS0 = 0, DQS1 = 0
894 01:35:36.150800 DQM Delay:
895 01:35:36.151383 DQM0 = 83, DQM1 = 77
896 01:35:36.151767 DQ Delay:
897 01:35:36.154010 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 01:35:36.157098 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
899 01:35:36.160727 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
900 01:35:36.164043 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
901 01:35:36.164623
902 01:35:36.165060
903 01:35:36.165428 ==
904 01:35:36.167545 Dram Type= 6, Freq= 0, CH_0, rank 0
905 01:35:36.174115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 01:35:36.174692 ==
907 01:35:36.175070
908 01:35:36.175419
909 01:35:36.175753 TX Vref Scan disable
910 01:35:36.177677 == TX Byte 0 ==
911 01:35:36.182363 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 01:35:36.184425 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 01:35:36.188129 == TX Byte 1 ==
914 01:35:36.191211 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
915 01:35:36.195070 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
916 01:35:36.197616 ==
917 01:35:36.201366 Dram Type= 6, Freq= 0, CH_0, rank 0
918 01:35:36.204638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 01:35:36.205269 ==
920 01:35:36.217272 TX Vref=22, minBit 0, minWin=27, winSum=441
921 01:35:36.221769 TX Vref=24, minBit 5, minWin=27, winSum=444
922 01:35:36.223666 TX Vref=26, minBit 3, minWin=27, winSum=447
923 01:35:36.226988 TX Vref=28, minBit 12, minWin=27, winSum=450
924 01:35:36.231489 TX Vref=30, minBit 12, minWin=27, winSum=453
925 01:35:36.233943 TX Vref=32, minBit 1, minWin=28, winSum=452
926 01:35:36.240309 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 32
927 01:35:36.240881
928 01:35:36.244182 Final TX Range 1 Vref 32
929 01:35:36.244763
930 01:35:36.245210 ==
931 01:35:36.247143 Dram Type= 6, Freq= 0, CH_0, rank 0
932 01:35:36.250711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 01:35:36.251297 ==
934 01:35:36.251682
935 01:35:36.252036
936 01:35:36.253707 TX Vref Scan disable
937 01:35:36.257276 == TX Byte 0 ==
938 01:35:36.260619 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
939 01:35:36.264224 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
940 01:35:36.267004 == TX Byte 1 ==
941 01:35:36.271398 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 01:35:36.274362 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 01:35:36.274994
944 01:35:36.277552 [DATLAT]
945 01:35:36.278028 Freq=800, CH0 RK0
946 01:35:36.278405
947 01:35:36.280999 DATLAT Default: 0xa
948 01:35:36.281487 0, 0xFFFF, sum = 0
949 01:35:36.284579 1, 0xFFFF, sum = 0
950 01:35:36.285226 2, 0xFFFF, sum = 0
951 01:35:36.288022 3, 0xFFFF, sum = 0
952 01:35:36.288629 4, 0xFFFF, sum = 0
953 01:35:36.290747 5, 0xFFFF, sum = 0
954 01:35:36.291330 6, 0xFFFF, sum = 0
955 01:35:36.294914 7, 0xFFFF, sum = 0
956 01:35:36.295502 8, 0xFFFF, sum = 0
957 01:35:36.297930 9, 0x0, sum = 1
958 01:35:36.298520 10, 0x0, sum = 2
959 01:35:36.300794 11, 0x0, sum = 3
960 01:35:36.301318 12, 0x0, sum = 4
961 01:35:36.304721 best_step = 10
962 01:35:36.305350
963 01:35:36.305733 ==
964 01:35:36.307551 Dram Type= 6, Freq= 0, CH_0, rank 0
965 01:35:36.311249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 01:35:36.311732 ==
967 01:35:36.314720 RX Vref Scan: 1
968 01:35:36.315295
969 01:35:36.315677 Set Vref Range= 32 -> 127
970 01:35:36.316027
971 01:35:36.318200 RX Vref 32 -> 127, step: 1
972 01:35:36.318784
973 01:35:36.321555 RX Delay -95 -> 252, step: 8
974 01:35:36.322030
975 01:35:36.324355 Set Vref, RX VrefLevel [Byte0]: 32
976 01:35:36.327709 [Byte1]: 32
977 01:35:36.328288
978 01:35:36.331217 Set Vref, RX VrefLevel [Byte0]: 33
979 01:35:36.334256 [Byte1]: 33
980 01:35:36.334734
981 01:35:36.338486 Set Vref, RX VrefLevel [Byte0]: 34
982 01:35:36.341524 [Byte1]: 34
983 01:35:36.345053
984 01:35:36.345529 Set Vref, RX VrefLevel [Byte0]: 35
985 01:35:36.348721 [Byte1]: 35
986 01:35:36.353598
987 01:35:36.354178 Set Vref, RX VrefLevel [Byte0]: 36
988 01:35:36.355634 [Byte1]: 36
989 01:35:36.360319
990 01:35:36.360899 Set Vref, RX VrefLevel [Byte0]: 37
991 01:35:36.363912 [Byte1]: 37
992 01:35:36.368232
993 01:35:36.368710 Set Vref, RX VrefLevel [Byte0]: 38
994 01:35:36.371683 [Byte1]: 38
995 01:35:36.375596
996 01:35:36.376066 Set Vref, RX VrefLevel [Byte0]: 39
997 01:35:36.379600 [Byte1]: 39
998 01:35:36.383491
999 01:35:36.384064 Set Vref, RX VrefLevel [Byte0]: 40
1000 01:35:36.386514 [Byte1]: 40
1001 01:35:36.390759
1002 01:35:36.391229 Set Vref, RX VrefLevel [Byte0]: 41
1003 01:35:36.395094 [Byte1]: 41
1004 01:35:36.398346
1005 01:35:36.398814 Set Vref, RX VrefLevel [Byte0]: 42
1006 01:35:36.402111 [Byte1]: 42
1007 01:35:36.406539
1008 01:35:36.407108 Set Vref, RX VrefLevel [Byte0]: 43
1009 01:35:36.408919 [Byte1]: 43
1010 01:35:36.413155
1011 01:35:36.413713 Set Vref, RX VrefLevel [Byte0]: 44
1012 01:35:36.417519 [Byte1]: 44
1013 01:35:36.420831
1014 01:35:36.421485 Set Vref, RX VrefLevel [Byte0]: 45
1015 01:35:36.424174 [Byte1]: 45
1016 01:35:36.429179
1017 01:35:36.429745 Set Vref, RX VrefLevel [Byte0]: 46
1018 01:35:36.431909 [Byte1]: 46
1019 01:35:36.435993
1020 01:35:36.436559 Set Vref, RX VrefLevel [Byte0]: 47
1021 01:35:36.439800 [Byte1]: 47
1022 01:35:36.443794
1023 01:35:36.444361 Set Vref, RX VrefLevel [Byte0]: 48
1024 01:35:36.447165 [Byte1]: 48
1025 01:35:36.451565
1026 01:35:36.452142 Set Vref, RX VrefLevel [Byte0]: 49
1027 01:35:36.454905 [Byte1]: 49
1028 01:35:36.459791
1029 01:35:36.460346 Set Vref, RX VrefLevel [Byte0]: 50
1030 01:35:36.462158 [Byte1]: 50
1031 01:35:36.467629
1032 01:35:36.468089 Set Vref, RX VrefLevel [Byte0]: 51
1033 01:35:36.470042 [Byte1]: 51
1034 01:35:36.474789
1035 01:35:36.475356 Set Vref, RX VrefLevel [Byte0]: 52
1036 01:35:36.477439 [Byte1]: 52
1037 01:35:36.481420
1038 01:35:36.481884 Set Vref, RX VrefLevel [Byte0]: 53
1039 01:35:36.489304 [Byte1]: 53
1040 01:35:36.489886
1041 01:35:36.491557 Set Vref, RX VrefLevel [Byte0]: 54
1042 01:35:36.495000 [Byte1]: 54
1043 01:35:36.495463
1044 01:35:36.497823 Set Vref, RX VrefLevel [Byte0]: 55
1045 01:35:36.501103 [Byte1]: 55
1046 01:35:36.501596
1047 01:35:36.504685 Set Vref, RX VrefLevel [Byte0]: 56
1048 01:35:36.508645 [Byte1]: 56
1049 01:35:36.512442
1050 01:35:36.512906 Set Vref, RX VrefLevel [Byte0]: 57
1051 01:35:36.515045 [Byte1]: 57
1052 01:35:36.520156
1053 01:35:36.520715 Set Vref, RX VrefLevel [Byte0]: 58
1054 01:35:36.522744 [Byte1]: 58
1055 01:35:36.527154
1056 01:35:36.527571 Set Vref, RX VrefLevel [Byte0]: 59
1057 01:35:36.531313 [Byte1]: 59
1058 01:35:36.534809
1059 01:35:36.535358 Set Vref, RX VrefLevel [Byte0]: 60
1060 01:35:36.537995 [Byte1]: 60
1061 01:35:36.543186
1062 01:35:36.543739 Set Vref, RX VrefLevel [Byte0]: 61
1063 01:35:36.545478 [Byte1]: 61
1064 01:35:36.549828
1065 01:35:36.550339 Set Vref, RX VrefLevel [Byte0]: 62
1066 01:35:36.553004 [Byte1]: 62
1067 01:35:36.557807
1068 01:35:36.558265 Set Vref, RX VrefLevel [Byte0]: 63
1069 01:35:36.560407 [Byte1]: 63
1070 01:35:36.565067
1071 01:35:36.565653 Set Vref, RX VrefLevel [Byte0]: 64
1072 01:35:36.568224 [Byte1]: 64
1073 01:35:36.572600
1074 01:35:36.573055 Set Vref, RX VrefLevel [Byte0]: 65
1075 01:35:36.575759 [Byte1]: 65
1076 01:35:36.580446
1077 01:35:36.580955 Set Vref, RX VrefLevel [Byte0]: 66
1078 01:35:36.583737 [Byte1]: 66
1079 01:35:36.588292
1080 01:35:36.588713 Set Vref, RX VrefLevel [Byte0]: 67
1081 01:35:36.590896 [Byte1]: 67
1082 01:35:36.595404
1083 01:35:36.595920 Set Vref, RX VrefLevel [Byte0]: 68
1084 01:35:36.599028 [Byte1]: 68
1085 01:35:36.603181
1086 01:35:36.603723 Set Vref, RX VrefLevel [Byte0]: 69
1087 01:35:36.606409 [Byte1]: 69
1088 01:35:36.610589
1089 01:35:36.611063 Set Vref, RX VrefLevel [Byte0]: 70
1090 01:35:36.614637 [Byte1]: 70
1091 01:35:36.618672
1092 01:35:36.619091 Set Vref, RX VrefLevel [Byte0]: 71
1093 01:35:36.621266 [Byte1]: 71
1094 01:35:36.625697
1095 01:35:36.626118 Set Vref, RX VrefLevel [Byte0]: 72
1096 01:35:36.629407 [Byte1]: 72
1097 01:35:36.634354
1098 01:35:36.634883 Set Vref, RX VrefLevel [Byte0]: 73
1099 01:35:36.637038 [Byte1]: 73
1100 01:35:36.641310
1101 01:35:36.641870 Set Vref, RX VrefLevel [Byte0]: 74
1102 01:35:36.644701 [Byte1]: 74
1103 01:35:36.648958
1104 01:35:36.649433 Set Vref, RX VrefLevel [Byte0]: 75
1105 01:35:36.652332 [Byte1]: 75
1106 01:35:36.656734
1107 01:35:36.657296 Set Vref, RX VrefLevel [Byte0]: 76
1108 01:35:36.659588 [Byte1]: 76
1109 01:35:36.664518
1110 01:35:36.665092 Final RX Vref Byte 0 = 60 to rank0
1111 01:35:36.667715 Final RX Vref Byte 1 = 58 to rank0
1112 01:35:36.670415 Final RX Vref Byte 0 = 60 to rank1
1113 01:35:36.674002 Final RX Vref Byte 1 = 58 to rank1==
1114 01:35:36.677376 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 01:35:36.680455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 01:35:36.684235 ==
1117 01:35:36.684787 DQS Delay:
1118 01:35:36.685223 DQS0 = 0, DQS1 = 0
1119 01:35:36.687287 DQM Delay:
1120 01:35:36.687846 DQM0 = 86, DQM1 = 79
1121 01:35:36.690602 DQ Delay:
1122 01:35:36.691323 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1123 01:35:36.694292 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1124 01:35:36.697332 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1125 01:35:36.701799 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1126 01:35:36.702465
1127 01:35:36.702862
1128 01:35:36.711321 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1129 01:35:36.714295 CH0 RK0: MR19=606, MR18=2A11
1130 01:35:36.719209 CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61
1131 01:35:36.721285
1132 01:35:36.724205 ----->DramcWriteLeveling(PI) begin...
1133 01:35:36.724756 ==
1134 01:35:36.728098 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 01:35:36.731643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 01:35:36.732206 ==
1137 01:35:36.734523 Write leveling (Byte 0): 31 => 31
1138 01:35:36.737801 Write leveling (Byte 1): 27 => 27
1139 01:35:36.741269 DramcWriteLeveling(PI) end<-----
1140 01:35:36.741740
1141 01:35:36.742105 ==
1142 01:35:36.745315 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 01:35:36.748203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 01:35:36.748763 ==
1145 01:35:36.751535 [Gating] SW mode calibration
1146 01:35:36.757666 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 01:35:36.761386 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 01:35:36.768286 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 01:35:36.772340 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 01:35:36.774922 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1151 01:35:36.818941 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 01:35:36.819574 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:35:36.820434 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:35:36.821021 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:35:36.821391 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:35:36.821729 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:35:36.822141 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:35:36.822472 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:35:36.822858 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:35:36.823196 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:35:36.845131 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:35:36.845785 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:35:36.846777 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:35:36.847191 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1165 01:35:36.847548 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1166 01:35:36.848532 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1167 01:35:36.851900 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:35:36.855727 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:35:36.859122 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:35:36.862498 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:35:36.869010 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:35:36.872213 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:35:36.876079 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:35:36.882905 0 9 8 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
1175 01:35:36.885612 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1176 01:35:36.889280 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 01:35:36.895848 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 01:35:36.899489 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 01:35:36.903084 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 01:35:36.909899 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:35:36.912564 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1182 01:35:36.916001 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (1 0) (1 1)
1183 01:35:36.922958 0 10 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
1184 01:35:36.926287 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 01:35:36.929040 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 01:35:36.933181 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 01:35:36.942327 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:35:36.943315 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:35:36.946146 0 11 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1190 01:35:36.954833 0 11 8 | B1->B0 | 2525 3939 | 0 1 | (0 0) (0 0)
1191 01:35:36.958371 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1192 01:35:36.960795 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 01:35:36.964163 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 01:35:36.971010 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 01:35:36.974443 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:35:36.979032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:35:36.982607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1198 01:35:36.990257 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1199 01:35:36.991894 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 01:35:36.995814 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:35:36.999868 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:35:37.006284 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:35:37.008646 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:35:37.012244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:35:37.019080 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:35:37.021564 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:35:37.025151 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:35:37.032270 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:35:37.035891 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:35:37.039066 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:35:37.046228 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:35:37.048933 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:35:37.052249 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 01:35:37.058467 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1215 01:35:37.058931 Total UI for P1: 0, mck2ui 16
1216 01:35:37.062226 best dqsien dly found for B0: ( 0, 14, 4)
1217 01:35:37.068860 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 01:35:37.072356 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 01:35:37.075555 Total UI for P1: 0, mck2ui 16
1220 01:35:37.078942 best dqsien dly found for B1: ( 0, 14, 10)
1221 01:35:37.082669 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 01:35:37.085519 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1223 01:35:37.085985
1224 01:35:37.088891 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 01:35:37.092433 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1226 01:35:37.095702 [Gating] SW calibration Done
1227 01:35:37.096164 ==
1228 01:35:37.099565 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 01:35:37.103076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 01:35:37.107478 ==
1231 01:35:37.108032 RX Vref Scan: 0
1232 01:35:37.108403
1233 01:35:37.109132 RX Vref 0 -> 0, step: 1
1234 01:35:37.109503
1235 01:35:37.112863 RX Delay -130 -> 252, step: 16
1236 01:35:37.116100 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1237 01:35:37.119289 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 01:35:37.122412 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 01:35:37.125685 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 01:35:37.132946 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 01:35:37.136517 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 01:35:37.140514 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 01:35:37.143267 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1244 01:35:37.146174 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 01:35:37.150273 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 01:35:37.156913 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 01:35:37.159511 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 01:35:37.163213 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 01:35:37.167154 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 01:35:37.169915 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 01:35:37.176752 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 01:35:37.177288 ==
1253 01:35:37.179535 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 01:35:37.183305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 01:35:37.183864 ==
1256 01:35:37.184240 DQS Delay:
1257 01:35:37.186064 DQS0 = 0, DQS1 = 0
1258 01:35:37.186526 DQM Delay:
1259 01:35:37.189294 DQM0 = 90, DQM1 = 79
1260 01:35:37.189755 DQ Delay:
1261 01:35:37.193175 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1262 01:35:37.196470 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
1263 01:35:37.199767 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1264 01:35:37.203241 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1265 01:35:37.203795
1266 01:35:37.204167
1267 01:35:37.204504 ==
1268 01:35:37.206317 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 01:35:37.209612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 01:35:37.210082 ==
1271 01:35:37.213164
1272 01:35:37.213621
1273 01:35:37.213985 TX Vref Scan disable
1274 01:35:37.218428 == TX Byte 0 ==
1275 01:35:37.219722 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1276 01:35:37.223478 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1277 01:35:37.226241 == TX Byte 1 ==
1278 01:35:37.230251 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1279 01:35:37.233783 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1280 01:35:37.234340 ==
1281 01:35:37.236566 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 01:35:37.243690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 01:35:37.244251 ==
1284 01:35:37.255718 TX Vref=22, minBit 12, minWin=26, winSum=440
1285 01:35:37.260008 TX Vref=24, minBit 3, minWin=27, winSum=442
1286 01:35:37.262356 TX Vref=26, minBit 9, minWin=26, winSum=448
1287 01:35:37.265335 TX Vref=28, minBit 9, minWin=26, winSum=445
1288 01:35:37.268644 TX Vref=30, minBit 8, minWin=27, winSum=453
1289 01:35:37.272470 TX Vref=32, minBit 8, minWin=27, winSum=449
1290 01:35:37.279361 [TxChooseVref] Worse bit 8, Min win 27, Win sum 453, Final Vref 30
1291 01:35:37.279908
1292 01:35:37.282222 Final TX Range 1 Vref 30
1293 01:35:37.282684
1294 01:35:37.283042 ==
1295 01:35:37.285981 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 01:35:37.288912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 01:35:37.289420 ==
1298 01:35:37.289787
1299 01:35:37.290126
1300 01:35:37.293192 TX Vref Scan disable
1301 01:35:37.296475 == TX Byte 0 ==
1302 01:35:37.298693 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1303 01:35:37.302216 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1304 01:35:37.305755 == TX Byte 1 ==
1305 01:35:37.308666 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1306 01:35:37.313280 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1307 01:35:37.313688
1308 01:35:37.315760 [DATLAT]
1309 01:35:37.316053 Freq=800, CH0 RK1
1310 01:35:37.316286
1311 01:35:37.319603 DATLAT Default: 0xa
1312 01:35:37.319997 0, 0xFFFF, sum = 0
1313 01:35:37.322420 1, 0xFFFF, sum = 0
1314 01:35:37.322719 2, 0xFFFF, sum = 0
1315 01:35:37.325693 3, 0xFFFF, sum = 0
1316 01:35:37.326055 4, 0xFFFF, sum = 0
1317 01:35:37.329049 5, 0xFFFF, sum = 0
1318 01:35:37.329434 6, 0xFFFF, sum = 0
1319 01:35:37.332514 7, 0xFFFF, sum = 0
1320 01:35:37.332907 8, 0xFFFF, sum = 0
1321 01:35:37.336656 9, 0x0, sum = 1
1322 01:35:37.337083 10, 0x0, sum = 2
1323 01:35:37.339328 11, 0x0, sum = 3
1324 01:35:37.339718 12, 0x0, sum = 4
1325 01:35:37.344014 best_step = 10
1326 01:35:37.344401
1327 01:35:37.344639 ==
1328 01:35:37.346148 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 01:35:37.349620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 01:35:37.350010 ==
1331 01:35:37.352441 RX Vref Scan: 0
1332 01:35:37.352826
1333 01:35:37.353088 RX Vref 0 -> 0, step: 1
1334 01:35:37.353310
1335 01:35:37.356551 RX Delay -95 -> 252, step: 8
1336 01:35:37.363255 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 01:35:37.365555 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 01:35:37.369660 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 01:35:37.372688 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 01:35:37.375960 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 01:35:37.379224 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 01:35:37.386485 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 01:35:37.389527 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 01:35:37.393358 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 01:35:37.396097 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 01:35:37.399889 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 01:35:37.407143 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 01:35:37.409543 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 01:35:37.413443 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1350 01:35:37.416400 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 01:35:37.420068 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 01:35:37.422696 ==
1353 01:35:37.423154 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 01:35:37.429988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 01:35:37.430539 ==
1356 01:35:37.430906 DQS Delay:
1357 01:35:37.433903 DQS0 = 0, DQS1 = 0
1358 01:35:37.434456 DQM Delay:
1359 01:35:37.436357 DQM0 = 87, DQM1 = 77
1360 01:35:37.436904 DQ Delay:
1361 01:35:37.440091 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 01:35:37.443268 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 01:35:37.446366 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 01:35:37.449855 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1365 01:35:37.450404
1366 01:35:37.450768
1367 01:35:37.457081 [DQSOSCAuto] RK1, (LSB)MR18= 0x301b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1368 01:35:37.460346 CH0 RK1: MR19=606, MR18=301B
1369 01:35:37.466673 CH0_RK1: MR19=0x606, MR18=0x301B, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 01:35:37.470356 [RxdqsGatingPostProcess] freq 800
1371 01:35:37.473983 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 01:35:37.478054 Pre-setting of DQS Precalculation
1373 01:35:37.483661 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 01:35:37.484214 ==
1375 01:35:37.486552 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 01:35:37.490252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 01:35:37.490816 ==
1378 01:35:37.496486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 01:35:37.500788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 01:35:37.510418 [CA 0] Center 36 (6~66) winsize 61
1381 01:35:37.516676 [CA 1] Center 36 (6~67) winsize 62
1382 01:35:37.517617 [CA 2] Center 35 (5~65) winsize 61
1383 01:35:37.521087 [CA 3] Center 34 (3~65) winsize 63
1384 01:35:37.524114 [CA 4] Center 34 (4~65) winsize 62
1385 01:35:37.527421 [CA 5] Center 33 (3~64) winsize 62
1386 01:35:37.527886
1387 01:35:37.531969 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 01:35:37.532524
1389 01:35:37.533861 [CATrainingPosCal] consider 1 rank data
1390 01:35:37.537895 u2DelayCellTimex100 = 270/100 ps
1391 01:35:37.540749 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 01:35:37.543942 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 01:35:37.550667 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1394 01:35:37.554044 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1395 01:35:37.557053 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 01:35:37.561324 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 01:35:37.561882
1398 01:35:37.564152 CA PerBit enable=1, Macro0, CA PI delay=33
1399 01:35:37.564615
1400 01:35:37.567591 [CBTSetCACLKResult] CA Dly = 33
1401 01:35:37.568159 CS Dly: 5 (0~36)
1402 01:35:37.568607 ==
1403 01:35:37.573143 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 01:35:37.577806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 01:35:37.578272 ==
1406 01:35:37.580781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 01:35:37.588047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 01:35:37.597116 [CA 0] Center 36 (6~67) winsize 62
1409 01:35:37.600424 [CA 1] Center 36 (6~67) winsize 62
1410 01:35:37.603870 [CA 2] Center 34 (4~65) winsize 62
1411 01:35:37.607041 [CA 3] Center 33 (3~64) winsize 62
1412 01:35:37.610338 [CA 4] Center 34 (3~65) winsize 63
1413 01:35:37.613884 [CA 5] Center 33 (3~64) winsize 62
1414 01:35:37.614465
1415 01:35:37.617690 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 01:35:37.618153
1417 01:35:37.621224 [CATrainingPosCal] consider 2 rank data
1418 01:35:37.624704 u2DelayCellTimex100 = 270/100 ps
1419 01:35:37.628623 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 01:35:37.632384 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 01:35:37.635995 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1422 01:35:37.640717 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 01:35:37.642889 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 01:35:37.647270 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 01:35:37.647729
1426 01:35:37.650354 CA PerBit enable=1, Macro0, CA PI delay=33
1427 01:35:37.650906
1428 01:35:37.653753 [CBTSetCACLKResult] CA Dly = 33
1429 01:35:37.654216 CS Dly: 5 (0~37)
1430 01:35:37.654595
1431 01:35:37.657125 ----->DramcWriteLeveling(PI) begin...
1432 01:35:37.657594 ==
1433 01:35:37.660279 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 01:35:37.668778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 01:35:37.669382 ==
1436 01:35:37.671556 Write leveling (Byte 0): 29 => 29
1437 01:35:37.672032 Write leveling (Byte 1): 29 => 29
1438 01:35:37.674128 DramcWriteLeveling(PI) end<-----
1439 01:35:37.674652
1440 01:35:37.675020 ==
1441 01:35:37.677571 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 01:35:37.684138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 01:35:37.684682 ==
1444 01:35:37.688350 [Gating] SW mode calibration
1445 01:35:37.694098 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 01:35:37.697849 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 01:35:37.700758 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1448 01:35:37.708351 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1449 01:35:37.710734 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1450 01:35:37.714478 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 01:35:37.721078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 01:35:37.724224 0 6 20 | B1->B0 | 0 2323 | 1 0 | (0 0) (0 0)
1453 01:35:37.727392 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:35:37.734797 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:35:37.737922 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:35:37.741642 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:35:37.744886 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:35:37.751903 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:35:37.755186 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:35:37.757679 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:35:37.764790 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 01:35:37.768638 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:35:37.771051 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 01:35:37.778527 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 01:35:37.781046 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1466 01:35:37.784571 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:35:37.792015 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:35:37.794678 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:35:37.798638 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:35:37.806399 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:35:37.807987 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:35:37.811736 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:35:37.818967 0 9 8 | B1->B0 | 2424 2626 | 1 0 | (1 1) (0 0)
1474 01:35:37.821657 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 01:35:37.825139 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 01:35:37.827653 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 01:35:37.835394 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 01:35:37.838548 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 01:35:37.842176 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 01:35:37.849135 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1481 01:35:37.851572 0 10 8 | B1->B0 | 2e2e 2e2e | 1 0 | (1 0) (1 0)
1482 01:35:37.855521 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 01:35:37.862173 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 01:35:37.865846 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 01:35:37.868127 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 01:35:37.876153 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 01:35:37.877950 0 11 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1488 01:35:37.882903 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:35:37.888372 0 11 8 | B1->B0 | 3333 3232 | 0 1 | (0 0) (0 0)
1490 01:35:37.892163 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 01:35:37.895711 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 01:35:37.899253 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 01:35:37.905400 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:35:37.908156 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 01:35:37.911687 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 01:35:37.918727 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:35:37.921673 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 01:35:37.925632 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:35:37.932026 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:35:37.935197 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:35:37.938891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:35:37.946186 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:35:37.949084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:35:37.954743 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:35:37.959300 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:35:37.964330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:35:37.966090 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:35:37.968595 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:35:37.975799 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:35:37.978701 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:35:37.984002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:35:37.990396 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:35:37.992728 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1514 01:35:37.995856 Total UI for P1: 0, mck2ui 16
1515 01:35:37.999470 best dqsien dly found for B1: ( 0, 14, 6)
1516 01:35:38.002494 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 01:35:38.005775 Total UI for P1: 0, mck2ui 16
1518 01:35:38.010152 best dqsien dly found for B0: ( 0, 14, 8)
1519 01:35:38.012827 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 01:35:38.016812 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 01:35:38.017323
1522 01:35:38.019521 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 01:35:38.025839 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 01:35:38.026307 [Gating] SW calibration Done
1525 01:35:38.026684 ==
1526 01:35:38.029182 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 01:35:38.035992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 01:35:38.036552 ==
1529 01:35:38.036923 RX Vref Scan: 0
1530 01:35:38.037325
1531 01:35:38.039405 RX Vref 0 -> 0, step: 1
1532 01:35:38.039867
1533 01:35:38.043022 RX Delay -130 -> 252, step: 16
1534 01:35:38.046104 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1535 01:35:38.049106 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1536 01:35:38.052716 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1537 01:35:38.056215 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 01:35:38.063063 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1539 01:35:38.067549 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1540 01:35:38.070762 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 01:35:38.073085 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1542 01:35:38.076454 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1543 01:35:38.080145 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1544 01:35:38.087163 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1545 01:35:38.089601 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 01:35:38.094355 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 01:35:38.096461 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 01:35:38.100140 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 01:35:38.106818 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1550 01:35:38.107363 ==
1551 01:35:38.109913 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 01:35:38.113784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 01:35:38.114348 ==
1554 01:35:38.114721 DQS Delay:
1555 01:35:38.116459 DQS0 = 0, DQS1 = 0
1556 01:35:38.116920 DQM Delay:
1557 01:35:38.120416 DQM0 = 83, DQM1 = 76
1558 01:35:38.120876 DQ Delay:
1559 01:35:38.124019 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1560 01:35:38.126965 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1561 01:35:38.130443 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1562 01:35:38.134847 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 01:35:38.135407
1564 01:35:38.135775
1565 01:35:38.136116 ==
1566 01:35:38.136957 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 01:35:38.140597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 01:35:38.141220 ==
1569 01:35:38.141716
1570 01:35:38.142174
1571 01:35:38.143818 TX Vref Scan disable
1572 01:35:38.146976 == TX Byte 0 ==
1573 01:35:38.150729 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1574 01:35:38.153803 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1575 01:35:38.157206 == TX Byte 1 ==
1576 01:35:38.160452 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 01:35:38.163917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 01:35:38.164491 ==
1579 01:35:38.167068 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 01:35:38.171159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 01:35:38.173624 ==
1582 01:35:38.185069 TX Vref=22, minBit 11, minWin=26, winSum=437
1583 01:35:38.189690 TX Vref=24, minBit 1, minWin=27, winSum=444
1584 01:35:38.192310 TX Vref=26, minBit 7, minWin=27, winSum=446
1585 01:35:38.195587 TX Vref=28, minBit 9, minWin=27, winSum=449
1586 01:35:38.199467 TX Vref=30, minBit 0, minWin=28, winSum=452
1587 01:35:38.202463 TX Vref=32, minBit 0, minWin=28, winSum=455
1588 01:35:38.209595 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
1589 01:35:38.210153
1590 01:35:38.213366 Final TX Range 1 Vref 32
1591 01:35:38.213924
1592 01:35:38.214293 ==
1593 01:35:38.216267 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 01:35:38.219602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 01:35:38.220161 ==
1596 01:35:38.220530
1597 01:35:38.220866
1598 01:35:38.222789 TX Vref Scan disable
1599 01:35:38.225915 == TX Byte 0 ==
1600 01:35:38.229492 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1601 01:35:38.233139 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1602 01:35:38.235934 == TX Byte 1 ==
1603 01:35:38.239629 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 01:35:38.243424 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 01:35:38.243980
1606 01:35:38.244351 [DATLAT]
1607 01:35:38.246180 Freq=800, CH1 RK0
1608 01:35:38.246734
1609 01:35:38.249472 DATLAT Default: 0xa
1610 01:35:38.250100 0, 0xFFFF, sum = 0
1611 01:35:38.253193 1, 0xFFFF, sum = 0
1612 01:35:38.253668 2, 0xFFFF, sum = 0
1613 01:35:38.256217 3, 0xFFFF, sum = 0
1614 01:35:38.256798 4, 0xFFFF, sum = 0
1615 01:35:38.259515 5, 0xFFFF, sum = 0
1616 01:35:38.260077 6, 0xFFFF, sum = 0
1617 01:35:38.263124 7, 0xFFFF, sum = 0
1618 01:35:38.263690 8, 0xFFFF, sum = 0
1619 01:35:38.267208 9, 0x0, sum = 1
1620 01:35:38.267794 10, 0x0, sum = 2
1621 01:35:38.268176 11, 0x0, sum = 3
1622 01:35:38.269649 12, 0x0, sum = 4
1623 01:35:38.270195 best_step = 10
1624 01:35:38.270575
1625 01:35:38.273531 ==
1626 01:35:38.273995 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 01:35:38.279698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 01:35:38.280164 ==
1629 01:35:38.280532 RX Vref Scan: 1
1630 01:35:38.280878
1631 01:35:38.283137 Set Vref Range= 32 -> 127
1632 01:35:38.283612
1633 01:35:38.286603 RX Vref 32 -> 127, step: 1
1634 01:35:38.287161
1635 01:35:38.289597 RX Delay -95 -> 252, step: 8
1636 01:35:38.290062
1637 01:35:38.293639 Set Vref, RX VrefLevel [Byte0]: 32
1638 01:35:38.296147 [Byte1]: 32
1639 01:35:38.296610
1640 01:35:38.299787 Set Vref, RX VrefLevel [Byte0]: 33
1641 01:35:38.303333 [Byte1]: 33
1642 01:35:38.303812
1643 01:35:38.306987 Set Vref, RX VrefLevel [Byte0]: 34
1644 01:35:38.309699 [Byte1]: 34
1645 01:35:38.310160
1646 01:35:38.313601 Set Vref, RX VrefLevel [Byte0]: 35
1647 01:35:38.317800 [Byte1]: 35
1648 01:35:38.320404
1649 01:35:38.320859 Set Vref, RX VrefLevel [Byte0]: 36
1650 01:35:38.324724 [Byte1]: 36
1651 01:35:38.328007
1652 01:35:38.328498 Set Vref, RX VrefLevel [Byte0]: 37
1653 01:35:38.331765 [Byte1]: 37
1654 01:35:38.335826
1655 01:35:38.336380 Set Vref, RX VrefLevel [Byte0]: 38
1656 01:35:38.339930 [Byte1]: 38
1657 01:35:38.343537
1658 01:35:38.344105 Set Vref, RX VrefLevel [Byte0]: 39
1659 01:35:38.346505 [Byte1]: 39
1660 01:35:38.351106
1661 01:35:38.351655 Set Vref, RX VrefLevel [Byte0]: 40
1662 01:35:38.353868 [Byte1]: 40
1663 01:35:38.358853
1664 01:35:38.359410 Set Vref, RX VrefLevel [Byte0]: 41
1665 01:35:38.362085 [Byte1]: 41
1666 01:35:38.367183
1667 01:35:38.367737 Set Vref, RX VrefLevel [Byte0]: 42
1668 01:35:38.369541 [Byte1]: 42
1669 01:35:38.374371
1670 01:35:38.374924 Set Vref, RX VrefLevel [Byte0]: 43
1671 01:35:38.377966 [Byte1]: 43
1672 01:35:38.382707
1673 01:35:38.383298 Set Vref, RX VrefLevel [Byte0]: 44
1674 01:35:38.384762 [Byte1]: 44
1675 01:35:38.389416
1676 01:35:38.389974 Set Vref, RX VrefLevel [Byte0]: 45
1677 01:35:38.392351 [Byte1]: 45
1678 01:35:38.396709
1679 01:35:38.397313 Set Vref, RX VrefLevel [Byte0]: 46
1680 01:35:38.400175 [Byte1]: 46
1681 01:35:38.404126
1682 01:35:38.404720 Set Vref, RX VrefLevel [Byte0]: 47
1683 01:35:38.407151 [Byte1]: 47
1684 01:35:38.411630
1685 01:35:38.412203 Set Vref, RX VrefLevel [Byte0]: 48
1686 01:35:38.414825 [Byte1]: 48
1687 01:35:38.419746
1688 01:35:38.420309 Set Vref, RX VrefLevel [Byte0]: 49
1689 01:35:38.422314 [Byte1]: 49
1690 01:35:38.427151
1691 01:35:38.427613 Set Vref, RX VrefLevel [Byte0]: 50
1692 01:35:38.430247 [Byte1]: 50
1693 01:35:38.434607
1694 01:35:38.435083 Set Vref, RX VrefLevel [Byte0]: 51
1695 01:35:38.438981 [Byte1]: 51
1696 01:35:38.442615
1697 01:35:38.443180 Set Vref, RX VrefLevel [Byte0]: 52
1698 01:35:38.445355 [Byte1]: 52
1699 01:35:38.449965
1700 01:35:38.450560 Set Vref, RX VrefLevel [Byte0]: 53
1701 01:35:38.453338 [Byte1]: 53
1702 01:35:38.457606
1703 01:35:38.458165 Set Vref, RX VrefLevel [Byte0]: 54
1704 01:35:38.460800 [Byte1]: 54
1705 01:35:38.465120
1706 01:35:38.465544 Set Vref, RX VrefLevel [Byte0]: 55
1707 01:35:38.468013 [Byte1]: 55
1708 01:35:38.473470
1709 01:35:38.474028 Set Vref, RX VrefLevel [Byte0]: 56
1710 01:35:38.476324 [Byte1]: 56
1711 01:35:38.480057
1712 01:35:38.480614 Set Vref, RX VrefLevel [Byte0]: 57
1713 01:35:38.483198 [Byte1]: 57
1714 01:35:38.487549
1715 01:35:38.488101 Set Vref, RX VrefLevel [Byte0]: 58
1716 01:35:38.492099 [Byte1]: 58
1717 01:35:38.495841
1718 01:35:38.496394 Set Vref, RX VrefLevel [Byte0]: 59
1719 01:35:38.499349 [Byte1]: 59
1720 01:35:38.502438
1721 01:35:38.502913 Set Vref, RX VrefLevel [Byte0]: 60
1722 01:35:38.506114 [Byte1]: 60
1723 01:35:38.511341
1724 01:35:38.511896 Set Vref, RX VrefLevel [Byte0]: 61
1725 01:35:38.514518 [Byte1]: 61
1726 01:35:38.518140
1727 01:35:38.518602 Set Vref, RX VrefLevel [Byte0]: 62
1728 01:35:38.523037 [Byte1]: 62
1729 01:35:38.525441
1730 01:35:38.525906 Set Vref, RX VrefLevel [Byte0]: 63
1731 01:35:38.528513 [Byte1]: 63
1732 01:35:38.533193
1733 01:35:38.536957 Set Vref, RX VrefLevel [Byte0]: 64
1734 01:35:38.537572 [Byte1]: 64
1735 01:35:38.541260
1736 01:35:38.541810 Set Vref, RX VrefLevel [Byte0]: 65
1737 01:35:38.544459 [Byte1]: 65
1738 01:35:38.549582
1739 01:35:38.550157 Set Vref, RX VrefLevel [Byte0]: 66
1740 01:35:38.552595 [Byte1]: 66
1741 01:35:38.556214
1742 01:35:38.556768 Set Vref, RX VrefLevel [Byte0]: 67
1743 01:35:38.560386 [Byte1]: 67
1744 01:35:38.564306
1745 01:35:38.564862 Set Vref, RX VrefLevel [Byte0]: 68
1746 01:35:38.566592 [Byte1]: 68
1747 01:35:38.570752
1748 01:35:38.571218 Set Vref, RX VrefLevel [Byte0]: 69
1749 01:35:38.574813 [Byte1]: 69
1750 01:35:38.578880
1751 01:35:38.579435 Set Vref, RX VrefLevel [Byte0]: 70
1752 01:35:38.583069 [Byte1]: 70
1753 01:35:38.587787
1754 01:35:38.588343 Set Vref, RX VrefLevel [Byte0]: 71
1755 01:35:38.589471 [Byte1]: 71
1756 01:35:38.594024
1757 01:35:38.594581 Set Vref, RX VrefLevel [Byte0]: 72
1758 01:35:38.597628 [Byte1]: 72
1759 01:35:38.601973
1760 01:35:38.602530 Set Vref, RX VrefLevel [Byte0]: 73
1761 01:35:38.605269 [Byte1]: 73
1762 01:35:38.609934
1763 01:35:38.610493 Set Vref, RX VrefLevel [Byte0]: 74
1764 01:35:38.612113 [Byte1]: 74
1765 01:35:38.617252
1766 01:35:38.617806 Set Vref, RX VrefLevel [Byte0]: 75
1767 01:35:38.619911 [Byte1]: 75
1768 01:35:38.624306
1769 01:35:38.624862 Set Vref, RX VrefLevel [Byte0]: 76
1770 01:35:38.627813 [Byte1]: 76
1771 01:35:38.632403
1772 01:35:38.632959 Set Vref, RX VrefLevel [Byte0]: 77
1773 01:35:38.635618 [Byte1]: 77
1774 01:35:38.640549
1775 01:35:38.641140 Set Vref, RX VrefLevel [Byte0]: 78
1776 01:35:38.642565 [Byte1]: 78
1777 01:35:38.647379
1778 01:35:38.647932 Set Vref, RX VrefLevel [Byte0]: 79
1779 01:35:38.650442 [Byte1]: 79
1780 01:35:38.655322
1781 01:35:38.655921 Set Vref, RX VrefLevel [Byte0]: 80
1782 01:35:38.658344 [Byte1]: 80
1783 01:35:38.662298
1784 01:35:38.662773 Final RX Vref Byte 0 = 60 to rank0
1785 01:35:38.666146 Final RX Vref Byte 1 = 58 to rank0
1786 01:35:38.669291 Final RX Vref Byte 0 = 60 to rank1
1787 01:35:38.672284 Final RX Vref Byte 1 = 58 to rank1==
1788 01:35:38.675548 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 01:35:38.678778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 01:35:38.682267 ==
1791 01:35:38.682765 DQS Delay:
1792 01:35:38.683133 DQS0 = 0, DQS1 = 0
1793 01:35:38.685892 DQM Delay:
1794 01:35:38.686436 DQM0 = 84, DQM1 = 73
1795 01:35:38.690316 DQ Delay:
1796 01:35:38.690867 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1797 01:35:38.692110 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1798 01:35:38.695873 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =72
1799 01:35:38.699392 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1800 01:35:38.699957
1801 01:35:38.702700
1802 01:35:38.709819 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1803 01:35:38.712545 CH1 RK0: MR19=605, MR18=28FD
1804 01:35:38.719575 CH1_RK0: MR19=0x605, MR18=0x28FD, DQSOSC=399, MR23=63, INC=92, DEC=61
1805 01:35:38.720132
1806 01:35:38.722941 ----->DramcWriteLeveling(PI) begin...
1807 01:35:38.723506 ==
1808 01:35:38.726356 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 01:35:38.729169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 01:35:38.729643 ==
1811 01:35:38.733267 Write leveling (Byte 0): 27 => 27
1812 01:35:38.736688 Write leveling (Byte 1): 29 => 29
1813 01:35:38.739684 DramcWriteLeveling(PI) end<-----
1814 01:35:38.740243
1815 01:35:38.740619 ==
1816 01:35:38.743381 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 01:35:38.746652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 01:35:38.747263 ==
1819 01:35:38.749526 [Gating] SW mode calibration
1820 01:35:38.756133 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 01:35:38.763386 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 01:35:38.766043 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1823 01:35:38.769150 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1824 01:35:38.773285 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1825 01:35:38.780214 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:35:38.783794 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:35:38.786905 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:35:38.792661 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 01:35:38.796582 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 01:35:38.799586 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:35:38.807086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:35:38.809798 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:35:38.813211 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1834 01:35:38.820355 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1835 01:35:38.823348 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1836 01:35:38.826663 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:35:38.834279 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1838 01:35:38.836533 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 01:35:38.840079 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1840 01:35:38.844537 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 01:35:38.850326 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 01:35:38.853205 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 01:35:38.856857 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 01:35:38.864048 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 01:35:38.867517 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 01:35:38.870743 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 01:35:38.877600 0 9 4 | B1->B0 | 2323 2525 | 1 0 | (1 1) (0 0)
1848 01:35:38.880854 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1849 01:35:38.884429 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 01:35:38.890573 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 01:35:38.894400 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1852 01:35:38.896882 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 01:35:38.900153 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 01:35:38.907702 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 01:35:38.910094 0 10 4 | B1->B0 | 3131 2c2c | 0 0 | (0 1) (1 1)
1856 01:35:38.913680 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1857 01:35:38.920007 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 01:35:38.923947 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 01:35:38.926816 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 01:35:38.933613 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 01:35:38.937969 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1862 01:35:38.940857 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 01:35:38.947149 0 11 4 | B1->B0 | 2c2c 3e3e | 0 0 | (1 1) (0 0)
1864 01:35:38.950440 0 11 8 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
1865 01:35:38.953576 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 01:35:38.957487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 01:35:38.964398 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 01:35:38.967483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 01:35:38.971110 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 01:35:38.977481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1871 01:35:38.980904 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1872 01:35:38.984454 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 01:35:38.991271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 01:35:38.994522 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 01:35:38.998491 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 01:35:39.004379 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 01:35:39.007627 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 01:35:39.011566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 01:35:39.014436 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 01:35:39.020831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 01:35:39.024247 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 01:35:39.027886 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 01:35:39.034393 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 01:35:39.037852 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 01:35:39.040970 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 01:35:39.047776 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 01:35:39.051092 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1888 01:35:39.054574 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 01:35:39.058090 Total UI for P1: 0, mck2ui 16
1890 01:35:39.061490 best dqsien dly found for B0: ( 0, 14, 4)
1891 01:35:39.064929 Total UI for P1: 0, mck2ui 16
1892 01:35:39.068267 best dqsien dly found for B1: ( 0, 14, 4)
1893 01:35:39.071179 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1894 01:35:39.075002 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 01:35:39.075471
1896 01:35:39.078808 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 01:35:39.081590 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 01:35:39.085410 [Gating] SW calibration Done
1899 01:35:39.085948 ==
1900 01:35:39.089121 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 01:35:39.091553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 01:35:39.096295 ==
1903 01:35:39.096719 RX Vref Scan: 0
1904 01:35:39.097088
1905 01:35:39.098754 RX Vref 0 -> 0, step: 1
1906 01:35:39.099176
1907 01:35:39.101744 RX Delay -130 -> 252, step: 16
1908 01:35:39.105689 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 01:35:39.108549 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1910 01:35:39.111949 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 01:35:39.116269 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1912 01:35:39.122310 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1913 01:35:39.125962 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1914 01:35:39.128711 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1915 01:35:39.132152 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1916 01:35:39.135306 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1917 01:35:39.139417 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1918 01:35:39.146159 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1919 01:35:39.148913 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1920 01:35:39.151799 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1921 01:35:39.155322 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1922 01:35:39.161582 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1923 01:35:39.165089 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1924 01:35:39.165550 ==
1925 01:35:39.168560 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 01:35:39.172086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 01:35:39.172547 ==
1928 01:35:39.172967 DQS Delay:
1929 01:35:39.175493 DQS0 = 0, DQS1 = 0
1930 01:35:39.175951 DQM Delay:
1931 01:35:39.178920 DQM0 = 80, DQM1 = 75
1932 01:35:39.179341 DQ Delay:
1933 01:35:39.182015 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1934 01:35:39.185392 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1935 01:35:39.189767 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1936 01:35:39.192039 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 01:35:39.192472
1938 01:35:39.192839
1939 01:35:39.193204 ==
1940 01:35:39.195847 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 01:35:39.198766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 01:35:39.199179 ==
1943 01:35:39.199508
1944 01:35:39.202277
1945 01:35:39.202691 TX Vref Scan disable
1946 01:35:39.205826 == TX Byte 0 ==
1947 01:35:39.209414 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1948 01:35:39.212300 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1949 01:35:39.216471 == TX Byte 1 ==
1950 01:35:39.219502 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1951 01:35:39.222893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1952 01:35:39.223406 ==
1953 01:35:39.225884 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 01:35:39.232727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 01:35:39.233196 ==
1956 01:35:39.244250 TX Vref=22, minBit 1, minWin=27, winSum=443
1957 01:35:39.247200 TX Vref=24, minBit 9, minWin=27, winSum=447
1958 01:35:39.250747 TX Vref=26, minBit 10, minWin=27, winSum=449
1959 01:35:39.254243 TX Vref=28, minBit 0, minWin=28, winSum=454
1960 01:35:39.258139 TX Vref=30, minBit 0, minWin=28, winSum=452
1961 01:35:39.261074 TX Vref=32, minBit 0, minWin=28, winSum=456
1962 01:35:39.268434 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 32
1963 01:35:39.268860
1964 01:35:39.271041 Final TX Range 1 Vref 32
1965 01:35:39.271464
1966 01:35:39.271800 ==
1967 01:35:39.274455 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 01:35:39.277652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 01:35:39.278077 ==
1970 01:35:39.278414
1971 01:35:39.278728
1972 01:35:39.280895 TX Vref Scan disable
1973 01:35:39.284462 == TX Byte 0 ==
1974 01:35:39.287546 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 01:35:39.290586 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 01:35:39.294323 == TX Byte 1 ==
1977 01:35:39.297563 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1978 01:35:39.300815 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1979 01:35:39.301401
1980 01:35:39.304368 [DATLAT]
1981 01:35:39.304880 Freq=800, CH1 RK1
1982 01:35:39.305252
1983 01:35:39.307745 DATLAT Default: 0xa
1984 01:35:39.308283 0, 0xFFFF, sum = 0
1985 01:35:39.311173 1, 0xFFFF, sum = 0
1986 01:35:39.311684 2, 0xFFFF, sum = 0
1987 01:35:39.314796 3, 0xFFFF, sum = 0
1988 01:35:39.315411 4, 0xFFFF, sum = 0
1989 01:35:39.318056 5, 0xFFFF, sum = 0
1990 01:35:39.318519 6, 0xFFFF, sum = 0
1991 01:35:39.321548 7, 0xFFFF, sum = 0
1992 01:35:39.321996 8, 0xFFFF, sum = 0
1993 01:35:39.324951 9, 0x0, sum = 1
1994 01:35:39.325407 10, 0x0, sum = 2
1995 01:35:39.327893 11, 0x0, sum = 3
1996 01:35:39.328316 12, 0x0, sum = 4
1997 01:35:39.331321 best_step = 10
1998 01:35:39.331739
1999 01:35:39.332069 ==
2000 01:35:39.334501 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 01:35:39.338165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 01:35:39.338690 ==
2003 01:35:39.341754 RX Vref Scan: 0
2004 01:35:39.342276
2005 01:35:39.342612 RX Vref 0 -> 0, step: 1
2006 01:35:39.342973
2007 01:35:39.344205 RX Delay -111 -> 252, step: 8
2008 01:35:39.351863 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2009 01:35:39.354490 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2010 01:35:39.358319 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2011 01:35:39.361599 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2012 01:35:39.364805 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2013 01:35:39.368230 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2014 01:35:39.375354 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2015 01:35:39.378196 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2016 01:35:39.381952 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2017 01:35:39.385069 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2018 01:35:39.388351 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2019 01:35:39.394715 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2020 01:35:39.398124 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2021 01:35:39.401609 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2022 01:35:39.405701 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2023 01:35:39.408167 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2024 01:35:39.412116 ==
2025 01:35:39.415052 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 01:35:39.418319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 01:35:39.418928 ==
2028 01:35:39.419307 DQS Delay:
2029 01:35:39.421735 DQS0 = 0, DQS1 = 0
2030 01:35:39.422203 DQM Delay:
2031 01:35:39.425603 DQM0 = 80, DQM1 = 75
2032 01:35:39.426170 DQ Delay:
2033 01:35:39.428485 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2034 01:35:39.431363 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2035 01:35:39.435103 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2036 01:35:39.438651 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2037 01:35:39.439223
2038 01:35:39.439586
2039 01:35:39.445564 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2040 01:35:39.448127 CH1 RK1: MR19=606, MR18=1C28
2041 01:35:39.455390 CH1_RK1: MR19=0x606, MR18=0x1C28, DQSOSC=399, MR23=63, INC=92, DEC=61
2042 01:35:39.458666 [RxdqsGatingPostProcess] freq 800
2043 01:35:39.462139 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 01:35:39.465441 Pre-setting of DQS Precalculation
2045 01:35:39.471498 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 01:35:39.478620 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 01:35:39.485170 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 01:35:39.485744
2049 01:35:39.486114
2050 01:35:39.488581 [Calibration Summary] 1600 Mbps
2051 01:35:39.489175 CH 0, Rank 0
2052 01:35:39.492299 SW Impedance : PASS
2053 01:35:39.495748 DUTY Scan : NO K
2054 01:35:39.496304 ZQ Calibration : PASS
2055 01:35:39.498719 Jitter Meter : NO K
2056 01:35:39.502458 CBT Training : PASS
2057 01:35:39.503015 Write leveling : PASS
2058 01:35:39.505346 RX DQS gating : PASS
2059 01:35:39.509033 RX DQ/DQS(RDDQC) : PASS
2060 01:35:39.509608 TX DQ/DQS : PASS
2061 01:35:39.512494 RX DATLAT : PASS
2062 01:35:39.512964 RX DQ/DQS(Engine): PASS
2063 01:35:39.516251 TX OE : NO K
2064 01:35:39.516809 All Pass.
2065 01:35:39.517245
2066 01:35:39.519440 CH 0, Rank 1
2067 01:35:39.519898 SW Impedance : PASS
2068 01:35:39.521782 DUTY Scan : NO K
2069 01:35:39.525581 ZQ Calibration : PASS
2070 01:35:39.526132 Jitter Meter : NO K
2071 01:35:39.528962 CBT Training : PASS
2072 01:35:39.532364 Write leveling : PASS
2073 01:35:39.532822 RX DQS gating : PASS
2074 01:35:39.535706 RX DQ/DQS(RDDQC) : PASS
2075 01:35:39.539280 TX DQ/DQS : PASS
2076 01:35:39.539834 RX DATLAT : PASS
2077 01:35:39.542570 RX DQ/DQS(Engine): PASS
2078 01:35:39.543141 TX OE : NO K
2079 01:35:39.545607 All Pass.
2080 01:35:39.546067
2081 01:35:39.546431 CH 1, Rank 0
2082 01:35:39.548890 SW Impedance : PASS
2083 01:35:39.549425 DUTY Scan : NO K
2084 01:35:39.552257 ZQ Calibration : PASS
2085 01:35:39.556284 Jitter Meter : NO K
2086 01:35:39.556968 CBT Training : PASS
2087 01:35:39.559349 Write leveling : PASS
2088 01:35:39.562530 RX DQS gating : PASS
2089 01:35:39.563108 RX DQ/DQS(RDDQC) : PASS
2090 01:35:39.565800 TX DQ/DQS : PASS
2091 01:35:39.568677 RX DATLAT : PASS
2092 01:35:39.569258 RX DQ/DQS(Engine): PASS
2093 01:35:39.572273 TX OE : NO K
2094 01:35:39.572736 All Pass.
2095 01:35:39.573160
2096 01:35:39.575543 CH 1, Rank 1
2097 01:35:39.576027 SW Impedance : PASS
2098 01:35:39.580107 DUTY Scan : NO K
2099 01:35:39.583401 ZQ Calibration : PASS
2100 01:35:39.583955 Jitter Meter : NO K
2101 01:35:39.585674 CBT Training : PASS
2102 01:35:39.589662 Write leveling : PASS
2103 01:35:39.590118 RX DQS gating : PASS
2104 01:35:39.593130 RX DQ/DQS(RDDQC) : PASS
2105 01:35:39.593689 TX DQ/DQS : PASS
2106 01:35:39.595746 RX DATLAT : PASS
2107 01:35:39.601009 RX DQ/DQS(Engine): PASS
2108 01:35:39.601594 TX OE : NO K
2109 01:35:39.602317 All Pass.
2110 01:35:39.602702
2111 01:35:39.603039 DramC Write-DBI off
2112 01:35:39.605839 PER_BANK_REFRESH: Hybrid Mode
2113 01:35:39.606324 TX_TRACKING: ON
2114 01:35:39.609103 [GetDramInforAfterCalByMRR] Vendor 6.
2115 01:35:39.617575 [GetDramInforAfterCalByMRR] Revision 606.
2116 01:35:39.619390 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 01:35:39.619846 MR0 0x3b3b
2118 01:35:39.620204 MR8 0x5151
2119 01:35:39.623230 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 01:35:39.623780
2121 01:35:39.626420 MR0 0x3b3b
2122 01:35:39.626971 MR8 0x5151
2123 01:35:39.629564 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 01:35:39.630027
2125 01:35:39.639561 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 01:35:39.642810 [FAST_K] Save calibration result to emmc
2127 01:35:39.646674 [FAST_K] Save calibration result to emmc
2128 01:35:39.649773 dram_init: config_dvfs: 1
2129 01:35:39.653680 dramc_set_vcore_voltage set vcore to 662500
2130 01:35:39.655931 Read voltage for 1200, 2
2131 01:35:39.656540 Vio18 = 0
2132 01:35:39.657232 Vcore = 662500
2133 01:35:39.657657 Vdram = 0
2134 01:35:39.659598 Vddq = 0
2135 01:35:39.660154 Vmddr = 0
2136 01:35:39.665916 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 01:35:39.669340 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 01:35:39.672740 MEM_TYPE=3, freq_sel=15
2139 01:35:39.676272 sv_algorithm_assistance_LP4_1600
2140 01:35:39.679444 ============ PULL DRAM RESETB DOWN ============
2141 01:35:39.683141 ========== PULL DRAM RESETB DOWN end =========
2142 01:35:39.689530 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 01:35:39.692834 ===================================
2144 01:35:39.693448 LPDDR4 DRAM CONFIGURATION
2145 01:35:39.696870 ===================================
2146 01:35:39.699831 EX_ROW_EN[0] = 0x0
2147 01:35:39.700361 EX_ROW_EN[1] = 0x0
2148 01:35:39.703348 LP4Y_EN = 0x0
2149 01:35:39.703804 WORK_FSP = 0x0
2150 01:35:39.706419 WL = 0x4
2151 01:35:39.706872 RL = 0x4
2152 01:35:39.709460 BL = 0x2
2153 01:35:39.709918 RPST = 0x0
2154 01:35:39.713335 RD_PRE = 0x0
2155 01:35:39.716320 WR_PRE = 0x1
2156 01:35:39.716831 WR_PST = 0x0
2157 01:35:39.719914 DBI_WR = 0x0
2158 01:35:39.720323 DBI_RD = 0x0
2159 01:35:39.723138 OTF = 0x1
2160 01:35:39.726494 ===================================
2161 01:35:39.730128 ===================================
2162 01:35:39.730782 ANA top config
2163 01:35:39.733166 ===================================
2164 01:35:39.736590 DLL_ASYNC_EN = 0
2165 01:35:39.737045 ALL_SLAVE_EN = 0
2166 01:35:39.740401 NEW_RANK_MODE = 1
2167 01:35:39.743198 DLL_IDLE_MODE = 1
2168 01:35:39.747321 LP45_APHY_COMB_EN = 1
2169 01:35:39.749888 TX_ODT_DIS = 1
2170 01:35:39.750406 NEW_8X_MODE = 1
2171 01:35:39.753616 ===================================
2172 01:35:39.757105 ===================================
2173 01:35:39.760629 data_rate = 2400
2174 01:35:39.763227 CKR = 1
2175 01:35:39.766865 DQ_P2S_RATIO = 8
2176 01:35:39.770940 ===================================
2177 01:35:39.774111 CA_P2S_RATIO = 8
2178 01:35:39.774532 DQ_CA_OPEN = 0
2179 01:35:39.777347 DQ_SEMI_OPEN = 0
2180 01:35:39.780877 CA_SEMI_OPEN = 0
2181 01:35:39.784183 CA_FULL_RATE = 0
2182 01:35:39.786724 DQ_CKDIV4_EN = 0
2183 01:35:39.790056 CA_CKDIV4_EN = 0
2184 01:35:39.790522 CA_PREDIV_EN = 0
2185 01:35:39.794197 PH8_DLY = 17
2186 01:35:39.797773 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 01:35:39.800772 DQ_AAMCK_DIV = 4
2188 01:35:39.804507 CA_AAMCK_DIV = 4
2189 01:35:39.805155 CA_ADMCK_DIV = 4
2190 01:35:39.807192 DQ_TRACK_CA_EN = 0
2191 01:35:39.811403 CA_PICK = 1200
2192 01:35:39.814169 CA_MCKIO = 1200
2193 01:35:39.817378 MCKIO_SEMI = 0
2194 01:35:39.821559 PLL_FREQ = 2366
2195 01:35:39.823723 DQ_UI_PI_RATIO = 32
2196 01:35:39.824189 CA_UI_PI_RATIO = 0
2197 01:35:39.827766 ===================================
2198 01:35:39.831812 ===================================
2199 01:35:39.834627 memory_type:LPDDR4
2200 01:35:39.837591 GP_NUM : 10
2201 01:35:39.838160 SRAM_EN : 1
2202 01:35:39.842363 MD32_EN : 0
2203 01:35:39.843636 ===================================
2204 01:35:39.847655 [ANA_INIT] >>>>>>>>>>>>>>
2205 01:35:39.851051 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 01:35:39.854034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 01:35:39.857626 ===================================
2208 01:35:39.858311 data_rate = 2400,PCW = 0X5b00
2209 01:35:39.860932 ===================================
2210 01:35:39.864765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 01:35:39.870737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 01:35:39.877565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 01:35:39.881008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 01:35:39.884272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 01:35:39.888071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 01:35:39.890867 [ANA_INIT] flow start
2217 01:35:39.891333 [ANA_INIT] PLL >>>>>>>>
2218 01:35:39.894717 [ANA_INIT] PLL <<<<<<<<
2219 01:35:39.899173 [ANA_INIT] MIDPI >>>>>>>>
2220 01:35:39.899744 [ANA_INIT] MIDPI <<<<<<<<
2221 01:35:39.901632 [ANA_INIT] DLL >>>>>>>>
2222 01:35:39.904296 [ANA_INIT] DLL <<<<<<<<
2223 01:35:39.904860 [ANA_INIT] flow end
2224 01:35:39.911196 ============ LP4 DIFF to SE enter ============
2225 01:35:39.914540 ============ LP4 DIFF to SE exit ============
2226 01:35:39.917718 [ANA_INIT] <<<<<<<<<<<<<
2227 01:35:39.921321 [Flow] Enable top DCM control >>>>>
2228 01:35:39.925578 [Flow] Enable top DCM control <<<<<
2229 01:35:39.926137 Enable DLL master slave shuffle
2230 01:35:39.930768 ==============================================================
2231 01:35:39.934663 Gating Mode config
2232 01:35:39.938359 ==============================================================
2233 01:35:39.942592 Config description:
2234 01:35:39.951361 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 01:35:39.957990 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 01:35:39.961678 SELPH_MODE 0: By rank 1: By Phase
2237 01:35:39.968440 ==============================================================
2238 01:35:39.972048 GAT_TRACK_EN = 1
2239 01:35:39.974701 RX_GATING_MODE = 2
2240 01:35:39.975161 RX_GATING_TRACK_MODE = 2
2241 01:35:39.977973 SELPH_MODE = 1
2242 01:35:39.981112 PICG_EARLY_EN = 1
2243 01:35:39.984858 VALID_LAT_VALUE = 1
2244 01:35:39.991158 ==============================================================
2245 01:35:39.994607 Enter into Gating configuration >>>>
2246 01:35:39.998405 Exit from Gating configuration <<<<
2247 01:35:40.001426 Enter into DVFS_PRE_config >>>>>
2248 01:35:40.012740 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 01:35:40.014488 Exit from DVFS_PRE_config <<<<<
2250 01:35:40.018931 Enter into PICG configuration >>>>
2251 01:35:40.022180 Exit from PICG configuration <<<<
2252 01:35:40.024523 [RX_INPUT] configuration >>>>>
2253 01:35:40.025023 [RX_INPUT] configuration <<<<<
2254 01:35:40.031781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 01:35:40.037901 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 01:35:40.041615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 01:35:40.048392 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 01:35:40.055800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 01:35:40.062336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 01:35:40.064959 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 01:35:40.068832 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 01:35:40.075911 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 01:35:40.078100 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 01:35:40.081682 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 01:35:40.084841 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 01:35:40.089134 ===================================
2267 01:35:40.092257 LPDDR4 DRAM CONFIGURATION
2268 01:35:40.095714 ===================================
2269 01:35:40.098417 EX_ROW_EN[0] = 0x0
2270 01:35:40.099131 EX_ROW_EN[1] = 0x0
2271 01:35:40.101658 LP4Y_EN = 0x0
2272 01:35:40.102121 WORK_FSP = 0x0
2273 01:35:40.105658 WL = 0x4
2274 01:35:40.106218 RL = 0x4
2275 01:35:40.108882 BL = 0x2
2276 01:35:40.109420 RPST = 0x0
2277 01:35:40.112962 RD_PRE = 0x0
2278 01:35:40.113575 WR_PRE = 0x1
2279 01:35:40.115282 WR_PST = 0x0
2280 01:35:40.115749 DBI_WR = 0x0
2281 01:35:40.119205 DBI_RD = 0x0
2282 01:35:40.119767 OTF = 0x1
2283 01:35:40.121670 ===================================
2284 01:35:40.129330 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 01:35:40.131632 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 01:35:40.135776 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 01:35:40.138762 ===================================
2288 01:35:40.141888 LPDDR4 DRAM CONFIGURATION
2289 01:35:40.145845 ===================================
2290 01:35:40.146432 EX_ROW_EN[0] = 0x10
2291 01:35:40.149040 EX_ROW_EN[1] = 0x0
2292 01:35:40.151771 LP4Y_EN = 0x0
2293 01:35:40.152320 WORK_FSP = 0x0
2294 01:35:40.155809 WL = 0x4
2295 01:35:40.156338 RL = 0x4
2296 01:35:40.158428 BL = 0x2
2297 01:35:40.158881 RPST = 0x0
2298 01:35:40.162634 RD_PRE = 0x0
2299 01:35:40.163129 WR_PRE = 0x1
2300 01:35:40.165368 WR_PST = 0x0
2301 01:35:40.165838 DBI_WR = 0x0
2302 01:35:40.169011 DBI_RD = 0x0
2303 01:35:40.169492 OTF = 0x1
2304 01:35:40.172477 ===================================
2305 01:35:40.179039 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 01:35:40.179474 ==
2307 01:35:40.182105 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 01:35:40.185855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 01:35:40.186275 ==
2310 01:35:40.188671 [Duty_Offset_Calibration]
2311 01:35:40.192216 B0:2 B1:-1 CA:1
2312 01:35:40.192531
2313 01:35:40.195415 [DutyScan_Calibration_Flow] k_type=0
2314 01:35:40.202477
2315 01:35:40.202885 ==CLK 0==
2316 01:35:40.206618 Final CLK duty delay cell = -4
2317 01:35:40.209375 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2318 01:35:40.213107 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2319 01:35:40.216415 [-4] AVG Duty = 4953%(X100)
2320 01:35:40.216737
2321 01:35:40.220144 CH0 CLK Duty spec in!! Max-Min= 156%
2322 01:35:40.223042 [DutyScan_Calibration_Flow] ====Done====
2323 01:35:40.223459
2324 01:35:40.226093 [DutyScan_Calibration_Flow] k_type=1
2325 01:35:40.241816
2326 01:35:40.242364 ==DQS 0 ==
2327 01:35:40.244450 Final DQS duty delay cell = -4
2328 01:35:40.249092 [-4] MAX Duty = 5031%(X100), DQS PI = 54
2329 01:35:40.251504 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2330 01:35:40.253999 [-4] AVG Duty = 4953%(X100)
2331 01:35:40.254563
2332 01:35:40.254970 ==DQS 1 ==
2333 01:35:40.257640 Final DQS duty delay cell = -4
2334 01:35:40.260436 [-4] MAX Duty = 5093%(X100), DQS PI = 16
2335 01:35:40.264768 [-4] MIN Duty = 5000%(X100), DQS PI = 42
2336 01:35:40.267748 [-4] AVG Duty = 5046%(X100)
2337 01:35:40.268308
2338 01:35:40.270642 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2339 01:35:40.271105
2340 01:35:40.274236 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2341 01:35:40.277789 [DutyScan_Calibration_Flow] ====Done====
2342 01:35:40.278250
2343 01:35:40.280997 [DutyScan_Calibration_Flow] k_type=3
2344 01:35:40.298536
2345 01:35:40.299093 ==DQM 0 ==
2346 01:35:40.301995 Final DQM duty delay cell = 0
2347 01:35:40.304957 [0] MAX Duty = 5000%(X100), DQS PI = 54
2348 01:35:40.308316 [0] MIN Duty = 4907%(X100), DQS PI = 2
2349 01:35:40.308875 [0] AVG Duty = 4953%(X100)
2350 01:35:40.311194
2351 01:35:40.311650 ==DQM 1 ==
2352 01:35:40.314942 Final DQM duty delay cell = 0
2353 01:35:40.318240 [0] MAX Duty = 5124%(X100), DQS PI = 30
2354 01:35:40.321373 [0] MIN Duty = 4969%(X100), DQS PI = 8
2355 01:35:40.321839 [0] AVG Duty = 5046%(X100)
2356 01:35:40.322206
2357 01:35:40.324723 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2358 01:35:40.328242
2359 01:35:40.332057 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2360 01:35:40.335099 [DutyScan_Calibration_Flow] ====Done====
2361 01:35:40.335586
2362 01:35:40.338302 [DutyScan_Calibration_Flow] k_type=2
2363 01:35:40.354567
2364 01:35:40.355173 ==DQ 0 ==
2365 01:35:40.357168 Final DQ duty delay cell = -4
2366 01:35:40.360154 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2367 01:35:40.363618 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2368 01:35:40.367347 [-4] AVG Duty = 4937%(X100)
2369 01:35:40.367752
2370 01:35:40.368075 ==DQ 1 ==
2371 01:35:40.370806 Final DQ duty delay cell = 0
2372 01:35:40.373725 [0] MAX Duty = 5031%(X100), DQS PI = 18
2373 01:35:40.377253 [0] MIN Duty = 4907%(X100), DQS PI = 46
2374 01:35:40.377897 [0] AVG Duty = 4969%(X100)
2375 01:35:40.380360
2376 01:35:40.384063 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2377 01:35:40.384716
2378 01:35:40.387422 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2379 01:35:40.390566 [DutyScan_Calibration_Flow] ====Done====
2380 01:35:40.391021 ==
2381 01:35:40.393652 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 01:35:40.397196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 01:35:40.397936 ==
2384 01:35:40.400371 [Duty_Offset_Calibration]
2385 01:35:40.400829 B0:1 B1:1 CA:2
2386 01:35:40.401395
2387 01:35:40.403613 [DutyScan_Calibration_Flow] k_type=0
2388 01:35:40.414475
2389 01:35:40.415029 ==CLK 0==
2390 01:35:40.417367 Final CLK duty delay cell = 0
2391 01:35:40.420875 [0] MAX Duty = 5156%(X100), DQS PI = 24
2392 01:35:40.424104 [0] MIN Duty = 4938%(X100), DQS PI = 48
2393 01:35:40.424564 [0] AVG Duty = 5047%(X100)
2394 01:35:40.424921
2395 01:35:40.427288 CH1 CLK Duty spec in!! Max-Min= 218%
2396 01:35:40.434608 [DutyScan_Calibration_Flow] ====Done====
2397 01:35:40.435063
2398 01:35:40.437434 [DutyScan_Calibration_Flow] k_type=1
2399 01:35:40.453202
2400 01:35:40.453701 ==DQS 0 ==
2401 01:35:40.456526 Final DQS duty delay cell = 0
2402 01:35:40.459808 [0] MAX Duty = 5031%(X100), DQS PI = 18
2403 01:35:40.464036 [0] MIN Duty = 4844%(X100), DQS PI = 48
2404 01:35:40.467116 [0] AVG Duty = 4937%(X100)
2405 01:35:40.467625
2406 01:35:40.467954 ==DQS 1 ==
2407 01:35:40.470090 Final DQS duty delay cell = 0
2408 01:35:40.473321 [0] MAX Duty = 5031%(X100), DQS PI = 36
2409 01:35:40.476640 [0] MIN Duty = 4906%(X100), DQS PI = 14
2410 01:35:40.477101 [0] AVG Duty = 4968%(X100)
2411 01:35:40.480860
2412 01:35:40.483884 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2413 01:35:40.484397
2414 01:35:40.487321 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2415 01:35:40.489963 [DutyScan_Calibration_Flow] ====Done====
2416 01:35:40.490499
2417 01:35:40.493014 [DutyScan_Calibration_Flow] k_type=3
2418 01:35:40.509697
2419 01:35:40.510258 ==DQM 0 ==
2420 01:35:40.513713 Final DQM duty delay cell = 0
2421 01:35:40.516661 [0] MAX Duty = 5093%(X100), DQS PI = 16
2422 01:35:40.519938 [0] MIN Duty = 4875%(X100), DQS PI = 48
2423 01:35:40.520408 [0] AVG Duty = 4984%(X100)
2424 01:35:40.523508
2425 01:35:40.523971 ==DQM 1 ==
2426 01:35:40.527384 Final DQM duty delay cell = 0
2427 01:35:40.530717 [0] MAX Duty = 5156%(X100), DQS PI = 62
2428 01:35:40.533028 [0] MIN Duty = 4938%(X100), DQS PI = 22
2429 01:35:40.533520 [0] AVG Duty = 5047%(X100)
2430 01:35:40.537123
2431 01:35:40.540260 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2432 01:35:40.540820
2433 01:35:40.545670 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2434 01:35:40.546898 [DutyScan_Calibration_Flow] ====Done====
2435 01:35:40.547364
2436 01:35:40.550275 [DutyScan_Calibration_Flow] k_type=2
2437 01:35:40.566616
2438 01:35:40.567171 ==DQ 0 ==
2439 01:35:40.570120 Final DQ duty delay cell = 0
2440 01:35:40.573675 [0] MAX Duty = 5093%(X100), DQS PI = 18
2441 01:35:40.577649 [0] MIN Duty = 4907%(X100), DQS PI = 50
2442 01:35:40.578113 [0] AVG Duty = 5000%(X100)
2443 01:35:40.578476
2444 01:35:40.579732 ==DQ 1 ==
2445 01:35:40.583427 Final DQ duty delay cell = 0
2446 01:35:40.587046 [0] MAX Duty = 5093%(X100), DQS PI = 10
2447 01:35:40.590359 [0] MIN Duty = 5000%(X100), DQS PI = 50
2448 01:35:40.590927 [0] AVG Duty = 5046%(X100)
2449 01:35:40.591297
2450 01:35:40.593560 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2451 01:35:40.594018
2452 01:35:40.596708 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2453 01:35:40.603587 [DutyScan_Calibration_Flow] ====Done====
2454 01:35:40.607115 nWR fixed to 30
2455 01:35:40.607672 [ModeRegInit_LP4] CH0 RK0
2456 01:35:40.610507 [ModeRegInit_LP4] CH0 RK1
2457 01:35:40.613096 [ModeRegInit_LP4] CH1 RK0
2458 01:35:40.613555 [ModeRegInit_LP4] CH1 RK1
2459 01:35:40.616676 match AC timing 7
2460 01:35:40.620081 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 01:35:40.623428 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 01:35:40.630097 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 01:35:40.633188 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 01:35:40.640325 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 01:35:40.640891 ==
2466 01:35:40.644033 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 01:35:40.647330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 01:35:40.647926 ==
2469 01:35:40.653832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 01:35:40.657162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 01:35:40.667236 [CA 0] Center 40 (10~71) winsize 62
2472 01:35:40.669663 [CA 1] Center 39 (9~70) winsize 62
2473 01:35:40.673374 [CA 2] Center 36 (6~67) winsize 62
2474 01:35:40.676791 [CA 3] Center 36 (5~67) winsize 63
2475 01:35:40.679749 [CA 4] Center 35 (5~65) winsize 61
2476 01:35:40.683298 [CA 5] Center 34 (4~64) winsize 61
2477 01:35:40.683867
2478 01:35:40.687121 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2479 01:35:40.687690
2480 01:35:40.690014 [CATrainingPosCal] consider 1 rank data
2481 01:35:40.693186 u2DelayCellTimex100 = 270/100 ps
2482 01:35:40.697052 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2483 01:35:40.700640 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2484 01:35:40.706824 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2485 01:35:40.710033 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2486 01:35:40.713530 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2487 01:35:40.717339 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2488 01:35:40.717905
2489 01:35:40.720052 CA PerBit enable=1, Macro0, CA PI delay=34
2490 01:35:40.720520
2491 01:35:40.723461 [CBTSetCACLKResult] CA Dly = 34
2492 01:35:40.723926 CS Dly: 7 (0~38)
2493 01:35:40.724299 ==
2494 01:35:40.727447 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 01:35:40.734643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 01:35:40.735203 ==
2497 01:35:40.737010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 01:35:40.743395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2499 01:35:40.752560 [CA 0] Center 39 (9~70) winsize 62
2500 01:35:40.755988 [CA 1] Center 39 (9~70) winsize 62
2501 01:35:40.759609 [CA 2] Center 36 (6~67) winsize 62
2502 01:35:40.762233 [CA 3] Center 36 (5~67) winsize 63
2503 01:35:40.765921 [CA 4] Center 34 (4~65) winsize 62
2504 01:35:40.769149 [CA 5] Center 34 (4~64) winsize 61
2505 01:35:40.769616
2506 01:35:40.772674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 01:35:40.773183
2508 01:35:40.775745 [CATrainingPosCal] consider 2 rank data
2509 01:35:40.778930 u2DelayCellTimex100 = 270/100 ps
2510 01:35:40.783080 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 01:35:40.785550 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2512 01:35:40.789536 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2513 01:35:40.796205 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2514 01:35:40.800074 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2515 01:35:40.803378 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2516 01:35:40.803941
2517 01:35:40.805819 CA PerBit enable=1, Macro0, CA PI delay=34
2518 01:35:40.806279
2519 01:35:40.809605 [CBTSetCACLKResult] CA Dly = 34
2520 01:35:40.810164 CS Dly: 8 (0~41)
2521 01:35:40.810534
2522 01:35:40.813786 ----->DramcWriteLeveling(PI) begin...
2523 01:35:40.814351 ==
2524 01:35:40.816473 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 01:35:40.822875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 01:35:40.823381 ==
2527 01:35:40.826524 Write leveling (Byte 0): 32 => 32
2528 01:35:40.829926 Write leveling (Byte 1): 29 => 29
2529 01:35:40.830484 DramcWriteLeveling(PI) end<-----
2530 01:35:40.830851
2531 01:35:40.833258 ==
2532 01:35:40.833718 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 01:35:40.840045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 01:35:40.840604 ==
2535 01:35:40.843013 [Gating] SW mode calibration
2536 01:35:40.849637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 01:35:40.853733 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 01:35:40.860689 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 01:35:40.863810 0 15 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2540 01:35:40.866466 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2541 01:35:40.870581 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 01:35:40.876557 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 01:35:40.880855 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 01:35:40.883452 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 01:35:40.891284 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 01:35:40.894011 1 0 0 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2547 01:35:40.896668 1 0 4 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2548 01:35:40.903476 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 01:35:40.906422 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 01:35:40.910626 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 01:35:40.917619 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 01:35:40.920111 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 01:35:40.923413 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 01:35:40.930922 1 1 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 01:35:40.933750 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
2556 01:35:40.937082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 01:35:40.943725 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 01:35:40.946767 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 01:35:40.950426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 01:35:40.953328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 01:35:40.960595 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 01:35:40.964399 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 01:35:40.966861 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 01:35:40.973644 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 01:35:40.976857 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 01:35:40.980596 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 01:35:40.986901 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 01:35:40.990233 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 01:35:40.993739 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 01:35:41.000724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 01:35:41.003759 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 01:35:41.007373 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 01:35:41.014360 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 01:35:41.018416 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 01:35:41.020330 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 01:35:41.023650 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 01:35:41.030911 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 01:35:41.034383 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2579 01:35:41.037259 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 01:35:41.040894 Total UI for P1: 0, mck2ui 16
2581 01:35:41.044466 best dqsien dly found for B0: ( 1, 4, 0)
2582 01:35:41.051418 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 01:35:41.051996 Total UI for P1: 0, mck2ui 16
2584 01:35:41.057392 best dqsien dly found for B1: ( 1, 4, 4)
2585 01:35:41.061581 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2586 01:35:41.064644 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2587 01:35:41.065166
2588 01:35:41.067107 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 01:35:41.071490 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2590 01:35:41.074023 [Gating] SW calibration Done
2591 01:35:41.074497 ==
2592 01:35:41.077795 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 01:35:41.080499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 01:35:41.080932 ==
2595 01:35:41.081425 RX Vref Scan: 0
2596 01:35:41.084104
2597 01:35:41.084636 RX Vref 0 -> 0, step: 1
2598 01:35:41.085172
2599 01:35:41.087673 RX Delay -40 -> 252, step: 8
2600 01:35:41.091579 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2601 01:35:41.094055 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2602 01:35:41.101218 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2603 01:35:41.104639 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2604 01:35:41.107668 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2605 01:35:41.110942 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2606 01:35:41.115450 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2607 01:35:41.117486 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2608 01:35:41.124531 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2609 01:35:41.127840 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2610 01:35:41.131446 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2611 01:35:41.134757 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2612 01:35:41.138655 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2613 01:35:41.144908 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2614 01:35:41.148059 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2615 01:35:41.151778 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2616 01:35:41.152422 ==
2617 01:35:41.154643 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 01:35:41.157846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 01:35:41.158373 ==
2620 01:35:41.162315 DQS Delay:
2621 01:35:41.162831 DQS0 = 0, DQS1 = 0
2622 01:35:41.164544 DQM Delay:
2623 01:35:41.165334 DQM0 = 115, DQM1 = 107
2624 01:35:41.165699 DQ Delay:
2625 01:35:41.167713 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2626 01:35:41.176153 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2627 01:35:41.177868 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2628 01:35:41.181941 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2629 01:35:41.182355
2630 01:35:41.182689
2631 01:35:41.182996 ==
2632 01:35:41.184862 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 01:35:41.187914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 01:35:41.188429 ==
2635 01:35:41.188769
2636 01:35:41.189132
2637 01:35:41.190967 TX Vref Scan disable
2638 01:35:41.191380 == TX Byte 0 ==
2639 01:35:41.198004 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2640 01:35:41.201836 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2641 01:35:41.202371 == TX Byte 1 ==
2642 01:35:41.208039 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2643 01:35:41.211262 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2644 01:35:41.211780 ==
2645 01:35:41.214705 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 01:35:41.217777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 01:35:41.218197 ==
2648 01:35:41.231612 TX Vref=22, minBit 1, minWin=24, winSum=413
2649 01:35:41.234606 TX Vref=24, minBit 0, minWin=25, winSum=418
2650 01:35:41.238419 TX Vref=26, minBit 3, minWin=25, winSum=421
2651 01:35:41.241541 TX Vref=28, minBit 0, minWin=26, winSum=429
2652 01:35:41.245298 TX Vref=30, minBit 1, minWin=26, winSum=432
2653 01:35:41.248271 TX Vref=32, minBit 0, minWin=26, winSum=429
2654 01:35:41.254311 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
2655 01:35:41.254856
2656 01:35:41.257835 Final TX Range 1 Vref 30
2657 01:35:41.258467
2658 01:35:41.258856 ==
2659 01:35:41.261088 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 01:35:41.264670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 01:35:41.265348 ==
2662 01:35:41.265934
2663 01:35:41.266296
2664 01:35:41.268415 TX Vref Scan disable
2665 01:35:41.271185 == TX Byte 0 ==
2666 01:35:41.275909 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2667 01:35:41.279056 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2668 01:35:41.281369 == TX Byte 1 ==
2669 01:35:41.284739 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2670 01:35:41.288119 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2671 01:35:41.288681
2672 01:35:41.291597 [DATLAT]
2673 01:35:41.292171 Freq=1200, CH0 RK0
2674 01:35:41.292542
2675 01:35:41.294409 DATLAT Default: 0xd
2676 01:35:41.295020 0, 0xFFFF, sum = 0
2677 01:35:41.298124 1, 0xFFFF, sum = 0
2678 01:35:41.298590 2, 0xFFFF, sum = 0
2679 01:35:41.301083 3, 0xFFFF, sum = 0
2680 01:35:41.301550 4, 0xFFFF, sum = 0
2681 01:35:41.304612 5, 0xFFFF, sum = 0
2682 01:35:41.305075 6, 0xFFFF, sum = 0
2683 01:35:41.308524 7, 0xFFFF, sum = 0
2684 01:35:41.309088 8, 0xFFFF, sum = 0
2685 01:35:41.311377 9, 0xFFFF, sum = 0
2686 01:35:41.311795 10, 0xFFFF, sum = 0
2687 01:35:41.315319 11, 0xFFFF, sum = 0
2688 01:35:41.315922 12, 0x0, sum = 1
2689 01:35:41.318392 13, 0x0, sum = 2
2690 01:35:41.318916 14, 0x0, sum = 3
2691 01:35:41.321657 15, 0x0, sum = 4
2692 01:35:41.322101 best_step = 13
2693 01:35:41.322437
2694 01:35:41.322748 ==
2695 01:35:41.324790 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 01:35:41.332024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 01:35:41.332538 ==
2698 01:35:41.332877 RX Vref Scan: 1
2699 01:35:41.333244
2700 01:35:41.334961 Set Vref Range= 32 -> 127
2701 01:35:41.335378
2702 01:35:41.338797 RX Vref 32 -> 127, step: 1
2703 01:35:41.339311
2704 01:35:41.339649 RX Delay -21 -> 252, step: 4
2705 01:35:41.339965
2706 01:35:41.341589 Set Vref, RX VrefLevel [Byte0]: 32
2707 01:35:41.344754 [Byte1]: 32
2708 01:35:41.349867
2709 01:35:41.350379 Set Vref, RX VrefLevel [Byte0]: 33
2710 01:35:41.352777 [Byte1]: 33
2711 01:35:41.357157
2712 01:35:41.357667 Set Vref, RX VrefLevel [Byte0]: 34
2713 01:35:41.360628 [Byte1]: 34
2714 01:35:41.365436
2715 01:35:41.366109 Set Vref, RX VrefLevel [Byte0]: 35
2716 01:35:41.368427 [Byte1]: 35
2717 01:35:41.373452
2718 01:35:41.374001 Set Vref, RX VrefLevel [Byte0]: 36
2719 01:35:41.376181 [Byte1]: 36
2720 01:35:41.381197
2721 01:35:41.381667 Set Vref, RX VrefLevel [Byte0]: 37
2722 01:35:41.384094 [Byte1]: 37
2723 01:35:41.389178
2724 01:35:41.389726 Set Vref, RX VrefLevel [Byte0]: 38
2725 01:35:41.393178 [Byte1]: 38
2726 01:35:41.397463
2727 01:35:41.397918 Set Vref, RX VrefLevel [Byte0]: 39
2728 01:35:41.399952 [Byte1]: 39
2729 01:35:41.405125
2730 01:35:41.405825 Set Vref, RX VrefLevel [Byte0]: 40
2731 01:35:41.407857 [Byte1]: 40
2732 01:35:41.413042
2733 01:35:41.413614 Set Vref, RX VrefLevel [Byte0]: 41
2734 01:35:41.415867 [Byte1]: 41
2735 01:35:41.420808
2736 01:35:41.421283 Set Vref, RX VrefLevel [Byte0]: 42
2737 01:35:41.423728 [Byte1]: 42
2738 01:35:41.428770
2739 01:35:41.429395 Set Vref, RX VrefLevel [Byte0]: 43
2740 01:35:41.432745 [Byte1]: 43
2741 01:35:41.436590
2742 01:35:41.437146 Set Vref, RX VrefLevel [Byte0]: 44
2743 01:35:41.440099 [Byte1]: 44
2744 01:35:41.444838
2745 01:35:41.445401 Set Vref, RX VrefLevel [Byte0]: 45
2746 01:35:41.447852 [Byte1]: 45
2747 01:35:41.453219
2748 01:35:41.453726 Set Vref, RX VrefLevel [Byte0]: 46
2749 01:35:41.455920 [Byte1]: 46
2750 01:35:41.460430
2751 01:35:41.461071 Set Vref, RX VrefLevel [Byte0]: 47
2752 01:35:41.465189 [Byte1]: 47
2753 01:35:41.468458
2754 01:35:41.469034 Set Vref, RX VrefLevel [Byte0]: 48
2755 01:35:41.471716 [Byte1]: 48
2756 01:35:41.475871
2757 01:35:41.476381 Set Vref, RX VrefLevel [Byte0]: 49
2758 01:35:41.479366 [Byte1]: 49
2759 01:35:41.484250
2760 01:35:41.484761 Set Vref, RX VrefLevel [Byte0]: 50
2761 01:35:41.487664 [Byte1]: 50
2762 01:35:41.492071
2763 01:35:41.492576 Set Vref, RX VrefLevel [Byte0]: 51
2764 01:35:41.495259 [Byte1]: 51
2765 01:35:41.500065
2766 01:35:41.500477 Set Vref, RX VrefLevel [Byte0]: 52
2767 01:35:41.503775 [Byte1]: 52
2768 01:35:41.507764
2769 01:35:41.508264 Set Vref, RX VrefLevel [Byte0]: 53
2770 01:35:41.511108 [Byte1]: 53
2771 01:35:41.515581
2772 01:35:41.516262 Set Vref, RX VrefLevel [Byte0]: 54
2773 01:35:41.518897 [Byte1]: 54
2774 01:35:41.523544
2775 01:35:41.524125 Set Vref, RX VrefLevel [Byte0]: 55
2776 01:35:41.526928 [Byte1]: 55
2777 01:35:41.531527
2778 01:35:41.531937 Set Vref, RX VrefLevel [Byte0]: 56
2779 01:35:41.534973 [Byte1]: 56
2780 01:35:41.540131
2781 01:35:41.540751 Set Vref, RX VrefLevel [Byte0]: 57
2782 01:35:41.543496 [Byte1]: 57
2783 01:35:41.548043
2784 01:35:41.548461 Set Vref, RX VrefLevel [Byte0]: 58
2785 01:35:41.550468 [Byte1]: 58
2786 01:35:41.555424
2787 01:35:41.555836 Set Vref, RX VrefLevel [Byte0]: 59
2788 01:35:41.558523 [Byte1]: 59
2789 01:35:41.563446
2790 01:35:41.563961 Set Vref, RX VrefLevel [Byte0]: 60
2791 01:35:41.567182 [Byte1]: 60
2792 01:35:41.571095
2793 01:35:41.571508 Set Vref, RX VrefLevel [Byte0]: 61
2794 01:35:41.574259 [Byte1]: 61
2795 01:35:41.579046
2796 01:35:41.579462 Set Vref, RX VrefLevel [Byte0]: 62
2797 01:35:41.582597 [Byte1]: 62
2798 01:35:41.587570
2799 01:35:41.588084 Set Vref, RX VrefLevel [Byte0]: 63
2800 01:35:41.590406 [Byte1]: 63
2801 01:35:41.595235
2802 01:35:41.595665 Set Vref, RX VrefLevel [Byte0]: 64
2803 01:35:41.597973 [Byte1]: 64
2804 01:35:41.602867
2805 01:35:41.603403 Set Vref, RX VrefLevel [Byte0]: 65
2806 01:35:41.606688 [Byte1]: 65
2807 01:35:41.610963
2808 01:35:41.611392 Set Vref, RX VrefLevel [Byte0]: 66
2809 01:35:41.613886 [Byte1]: 66
2810 01:35:41.618576
2811 01:35:41.619118 Set Vref, RX VrefLevel [Byte0]: 67
2812 01:35:41.622213 [Byte1]: 67
2813 01:35:41.626969
2814 01:35:41.627400 Set Vref, RX VrefLevel [Byte0]: 68
2815 01:35:41.630820 [Byte1]: 68
2816 01:35:41.634342
2817 01:35:41.634775 Final RX Vref Byte 0 = 52 to rank0
2818 01:35:41.637739 Final RX Vref Byte 1 = 52 to rank0
2819 01:35:41.641780 Final RX Vref Byte 0 = 52 to rank1
2820 01:35:41.644558 Final RX Vref Byte 1 = 52 to rank1==
2821 01:35:41.647850 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 01:35:41.654963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 01:35:41.655498 ==
2824 01:35:41.655944 DQS Delay:
2825 01:35:41.656355 DQS0 = 0, DQS1 = 0
2826 01:35:41.658000 DQM Delay:
2827 01:35:41.658426 DQM0 = 115, DQM1 = 104
2828 01:35:41.661365 DQ Delay:
2829 01:35:41.664528 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =112
2830 01:35:41.668646 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2831 01:35:41.671803 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2832 01:35:41.674573 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2833 01:35:41.675100
2834 01:35:41.675441
2835 01:35:41.681586 [DQSOSCAuto] RK0, (LSB)MR18= 0xfceb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2836 01:35:41.685322 CH0 RK0: MR19=303, MR18=FCEB
2837 01:35:41.691479 CH0_RK0: MR19=0x303, MR18=0xFCEB, DQSOSC=411, MR23=63, INC=38, DEC=25
2838 01:35:41.692042
2839 01:35:41.694813 ----->DramcWriteLeveling(PI) begin...
2840 01:35:41.695279 ==
2841 01:35:41.699181 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 01:35:41.701588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 01:35:41.702052 ==
2844 01:35:41.704826 Write leveling (Byte 0): 35 => 35
2845 01:35:41.708540 Write leveling (Byte 1): 28 => 28
2846 01:35:41.711412 DramcWriteLeveling(PI) end<-----
2847 01:35:41.711873
2848 01:35:41.712256 ==
2849 01:35:41.714924 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 01:35:41.718520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 01:35:41.719051 ==
2852 01:35:41.721507 [Gating] SW mode calibration
2853 01:35:41.728291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 01:35:41.735027 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 01:35:41.738567 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 01:35:41.745088 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2857 01:35:41.748748 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 01:35:41.751734 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 01:35:41.758522 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 01:35:41.762384 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2861 01:35:41.765547 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 01:35:41.769250 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
2863 01:35:41.776615 1 0 0 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
2864 01:35:41.779242 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 01:35:41.782658 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 01:35:41.789078 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 01:35:41.792913 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 01:35:41.795786 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 01:35:41.804100 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2870 01:35:41.805535 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2871 01:35:41.808841 1 1 0 | B1->B0 | 3636 3f3f | 0 0 | (1 1) (0 0)
2872 01:35:41.815683 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2873 01:35:41.819253 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 01:35:41.822053 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 01:35:41.825747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 01:35:41.832709 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 01:35:41.836638 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 01:35:41.839378 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 01:35:41.845893 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2880 01:35:41.849169 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 01:35:41.853133 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 01:35:41.859553 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 01:35:41.862966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 01:35:41.866407 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 01:35:41.872763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 01:35:41.875991 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 01:35:41.879224 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 01:35:41.886229 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 01:35:41.890044 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 01:35:41.892581 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 01:35:41.896209 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 01:35:41.902448 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 01:35:41.905977 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 01:35:41.909901 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2895 01:35:41.916023 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2896 01:35:41.919284 Total UI for P1: 0, mck2ui 16
2897 01:35:41.922868 best dqsien dly found for B0: ( 1, 3, 26)
2898 01:35:41.925908 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 01:35:41.929892 Total UI for P1: 0, mck2ui 16
2900 01:35:41.933207 best dqsien dly found for B1: ( 1, 4, 0)
2901 01:35:41.936117 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2902 01:35:41.939294 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2903 01:35:41.939751
2904 01:35:41.942819 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2905 01:35:41.947456 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2906 01:35:41.949556 [Gating] SW calibration Done
2907 01:35:41.950012 ==
2908 01:35:41.953322 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 01:35:41.956580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 01:35:41.957181 ==
2911 01:35:41.960348 RX Vref Scan: 0
2912 01:35:41.960900
2913 01:35:41.963195 RX Vref 0 -> 0, step: 1
2914 01:35:41.963766
2915 01:35:41.964143 RX Delay -40 -> 252, step: 8
2916 01:35:41.969583 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2917 01:35:41.974276 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2918 01:35:41.976281 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2919 01:35:41.979821 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2920 01:35:41.983480 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2921 01:35:41.986967 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2922 01:35:41.993594 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2923 01:35:41.996410 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2924 01:35:41.999835 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2925 01:35:42.003821 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 01:35:42.006431 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2927 01:35:42.013911 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2928 01:35:42.017164 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2929 01:35:42.020661 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2930 01:35:42.023791 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 01:35:42.026571 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2932 01:35:42.029878 ==
2933 01:35:42.030438 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 01:35:42.037819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 01:35:42.038369 ==
2936 01:35:42.038738 DQS Delay:
2937 01:35:42.040609 DQS0 = 0, DQS1 = 0
2938 01:35:42.041201 DQM Delay:
2939 01:35:42.043688 DQM0 = 115, DQM1 = 106
2940 01:35:42.044246 DQ Delay:
2941 01:35:42.046724 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2942 01:35:42.050557 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2943 01:35:42.053775 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2944 01:35:42.056877 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2945 01:35:42.057486
2946 01:35:42.057858
2947 01:35:42.058195 ==
2948 01:35:42.060253 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 01:35:42.063630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 01:35:42.067178 ==
2951 01:35:42.067744
2952 01:35:42.068109
2953 01:35:42.068449 TX Vref Scan disable
2954 01:35:42.070309 == TX Byte 0 ==
2955 01:35:42.073646 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2956 01:35:42.077321 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2957 01:35:42.080324 == TX Byte 1 ==
2958 01:35:42.084007 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2959 01:35:42.087031 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2960 01:35:42.087498 ==
2961 01:35:42.090409 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 01:35:42.097907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 01:35:42.098481 ==
2964 01:35:42.109135 TX Vref=22, minBit 1, minWin=25, winSum=419
2965 01:35:42.112021 TX Vref=24, minBit 1, minWin=25, winSum=426
2966 01:35:42.116253 TX Vref=26, minBit 1, minWin=26, winSum=432
2967 01:35:42.119200 TX Vref=28, minBit 1, minWin=26, winSum=434
2968 01:35:42.122166 TX Vref=30, minBit 3, minWin=26, winSum=435
2969 01:35:42.125558 TX Vref=32, minBit 1, minWin=26, winSum=436
2970 01:35:42.131770 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 32
2971 01:35:42.132333
2972 01:35:42.135733 Final TX Range 1 Vref 32
2973 01:35:42.136209
2974 01:35:42.136693 ==
2975 01:35:42.139930 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 01:35:42.142185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 01:35:42.142761 ==
2978 01:35:42.143251
2979 01:35:42.143697
2980 01:35:42.146656 TX Vref Scan disable
2981 01:35:42.148500 == TX Byte 0 ==
2982 01:35:42.151916 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2983 01:35:42.155400 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2984 01:35:42.158830 == TX Byte 1 ==
2985 01:35:42.161723 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2986 01:35:42.165355 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2987 01:35:42.165924
2988 01:35:42.168431 [DATLAT]
2989 01:35:42.169039 Freq=1200, CH0 RK1
2990 01:35:42.169532
2991 01:35:42.171508 DATLAT Default: 0xd
2992 01:35:42.171964 0, 0xFFFF, sum = 0
2993 01:35:42.175695 1, 0xFFFF, sum = 0
2994 01:35:42.176354 2, 0xFFFF, sum = 0
2995 01:35:42.178656 3, 0xFFFF, sum = 0
2996 01:35:42.179123 4, 0xFFFF, sum = 0
2997 01:35:42.182233 5, 0xFFFF, sum = 0
2998 01:35:42.182701 6, 0xFFFF, sum = 0
2999 01:35:42.185702 7, 0xFFFF, sum = 0
3000 01:35:42.186285 8, 0xFFFF, sum = 0
3001 01:35:42.188411 9, 0xFFFF, sum = 0
3002 01:35:42.189015 10, 0xFFFF, sum = 0
3003 01:35:42.191990 11, 0xFFFF, sum = 0
3004 01:35:42.192459 12, 0x0, sum = 1
3005 01:35:42.195468 13, 0x0, sum = 2
3006 01:35:42.196033 14, 0x0, sum = 3
3007 01:35:42.200535 15, 0x0, sum = 4
3008 01:35:42.201044 best_step = 13
3009 01:35:42.201420
3010 01:35:42.201760 ==
3011 01:35:42.202429 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 01:35:42.208906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 01:35:42.209398 ==
3014 01:35:42.209763 RX Vref Scan: 0
3015 01:35:42.210108
3016 01:35:42.212011 RX Vref 0 -> 0, step: 1
3017 01:35:42.212493
3018 01:35:42.215484 RX Delay -21 -> 252, step: 4
3019 01:35:42.219569 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3020 01:35:42.222373 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3021 01:35:42.225950 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3022 01:35:42.232500 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3023 01:35:42.235761 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3024 01:35:42.238984 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3025 01:35:42.243108 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3026 01:35:42.245764 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3027 01:35:42.252769 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3028 01:35:42.256284 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3029 01:35:42.259090 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3030 01:35:42.263002 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3031 01:35:42.266932 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3032 01:35:42.269416 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3033 01:35:42.276689 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3034 01:35:42.279703 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3035 01:35:42.280264 ==
3036 01:35:42.282705 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 01:35:42.286281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 01:35:42.286842 ==
3039 01:35:42.289452 DQS Delay:
3040 01:35:42.290009 DQS0 = 0, DQS1 = 0
3041 01:35:42.290381 DQM Delay:
3042 01:35:42.292865 DQM0 = 114, DQM1 = 105
3043 01:35:42.293515 DQ Delay:
3044 01:35:42.296204 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3045 01:35:42.299711 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3046 01:35:42.303201 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3047 01:35:42.309626 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3048 01:35:42.310091
3049 01:35:42.310456
3050 01:35:42.316153 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3051 01:35:42.319880 CH0 RK1: MR19=303, MR18=FEF0
3052 01:35:42.326695 CH0_RK1: MR19=0x303, MR18=0xFEF0, DQSOSC=410, MR23=63, INC=39, DEC=26
3053 01:35:42.329548 [RxdqsGatingPostProcess] freq 1200
3054 01:35:42.332837 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 01:35:42.336181 best DQS0 dly(2T, 0.5T) = (0, 12)
3056 01:35:42.340836 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 01:35:42.343395 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3058 01:35:42.346354 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 01:35:42.349539 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 01:35:42.353398 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 01:35:42.356821 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 01:35:42.359959 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 01:35:42.363119 Pre-setting of DQS Precalculation
3064 01:35:42.367164 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 01:35:42.367724 ==
3066 01:35:42.369994 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 01:35:42.373542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 01:35:42.374012 ==
3069 01:35:42.380154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 01:35:42.386888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 01:35:42.395801 [CA 0] Center 38 (9~68) winsize 60
3072 01:35:42.397778 [CA 1] Center 38 (8~68) winsize 61
3073 01:35:42.401158 [CA 2] Center 35 (5~65) winsize 61
3074 01:35:42.404106 [CA 3] Center 34 (4~65) winsize 62
3075 01:35:42.408373 [CA 4] Center 34 (4~65) winsize 62
3076 01:35:42.410580 [CA 5] Center 34 (4~64) winsize 61
3077 01:35:42.411043
3078 01:35:42.413702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3079 01:35:42.414170
3080 01:35:42.417473 [CATrainingPosCal] consider 1 rank data
3081 01:35:42.421115 u2DelayCellTimex100 = 270/100 ps
3082 01:35:42.424068 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3083 01:35:42.427354 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3084 01:35:42.434740 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3085 01:35:42.440007 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3086 01:35:42.440939 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3087 01:35:42.444774 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3088 01:35:42.445530
3089 01:35:42.447644 CA PerBit enable=1, Macro0, CA PI delay=34
3090 01:35:42.448229
3091 01:35:42.450851 [CBTSetCACLKResult] CA Dly = 34
3092 01:35:42.451426 CS Dly: 6 (0~37)
3093 01:35:42.451924 ==
3094 01:35:42.454113 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 01:35:42.462375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 01:35:42.462940 ==
3097 01:35:42.464376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 01:35:42.471763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 01:35:42.480898 [CA 0] Center 38 (8~68) winsize 61
3100 01:35:42.484891 [CA 1] Center 38 (9~68) winsize 60
3101 01:35:42.486541 [CA 2] Center 34 (4~65) winsize 62
3102 01:35:42.490297 [CA 3] Center 34 (3~65) winsize 63
3103 01:35:42.493266 [CA 4] Center 34 (4~65) winsize 62
3104 01:35:42.496645 [CA 5] Center 33 (3~64) winsize 62
3105 01:35:42.497254
3106 01:35:42.500260 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 01:35:42.500842
3108 01:35:42.503773 [CATrainingPosCal] consider 2 rank data
3109 01:35:42.506932 u2DelayCellTimex100 = 270/100 ps
3110 01:35:42.510226 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3111 01:35:42.513235 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3112 01:35:42.517461 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3113 01:35:42.523484 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3114 01:35:42.526210 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3115 01:35:42.529455 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3116 01:35:42.529919
3117 01:35:42.533342 CA PerBit enable=1, Macro0, CA PI delay=34
3118 01:35:42.533923
3119 01:35:42.536642 [CBTSetCACLKResult] CA Dly = 34
3120 01:35:42.537318 CS Dly: 7 (0~40)
3121 01:35:42.537862
3122 01:35:42.539719 ----->DramcWriteLeveling(PI) begin...
3123 01:35:42.540278 ==
3124 01:35:42.544131 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 01:35:42.551365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 01:35:42.551946 ==
3127 01:35:42.554288 Write leveling (Byte 0): 26 => 26
3128 01:35:42.557439 Write leveling (Byte 1): 28 => 28
3129 01:35:42.557995 DramcWriteLeveling(PI) end<-----
3130 01:35:42.558365
3131 01:35:42.561246 ==
3132 01:35:42.561707 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 01:35:42.567053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 01:35:42.567749 ==
3135 01:35:42.571184 [Gating] SW mode calibration
3136 01:35:42.577548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 01:35:42.580869 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 01:35:42.587842 0 15 0 | B1->B0 | 2929 2323 | 1 1 | (1 1) (1 1)
3139 01:35:42.590479 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3140 01:35:42.594034 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 01:35:42.597228 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3142 01:35:42.604464 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 01:35:42.606834 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3144 01:35:42.610874 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 01:35:42.616827 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3146 01:35:42.620905 1 0 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3147 01:35:42.623873 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 01:35:42.631089 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 01:35:42.633935 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3150 01:35:42.637371 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 01:35:42.644281 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 01:35:42.648102 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 01:35:42.650698 1 0 28 | B1->B0 | 2626 2626 | 1 0 | (0 0) (0 0)
3154 01:35:42.657819 1 1 0 | B1->B0 | 4444 3a3a | 0 0 | (0 0) (0 0)
3155 01:35:42.660535 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 01:35:42.664796 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 01:35:42.670875 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 01:35:42.674593 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 01:35:42.677309 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 01:35:42.680790 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 01:35:42.688031 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3162 01:35:42.691136 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 01:35:42.694167 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 01:35:42.701883 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 01:35:42.704402 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 01:35:42.707868 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 01:35:42.714037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 01:35:42.718362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 01:35:42.721009 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 01:35:42.728383 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 01:35:42.730989 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 01:35:42.733988 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 01:35:42.738013 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 01:35:42.744188 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 01:35:42.747854 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 01:35:42.750649 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 01:35:42.758146 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3178 01:35:42.761178 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3179 01:35:42.764368 Total UI for P1: 0, mck2ui 16
3180 01:35:42.767802 best dqsien dly found for B0: ( 1, 3, 28)
3181 01:35:42.770796 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 01:35:42.774394 Total UI for P1: 0, mck2ui 16
3183 01:35:42.777552 best dqsien dly found for B1: ( 1, 3, 30)
3184 01:35:42.780862 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3185 01:35:42.784389 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3186 01:35:42.784803
3187 01:35:42.791539 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 01:35:42.794433 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3189 01:35:42.794853 [Gating] SW calibration Done
3190 01:35:42.797715 ==
3191 01:35:42.798134 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 01:35:42.804500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 01:35:42.805130 ==
3194 01:35:42.805487 RX Vref Scan: 0
3195 01:35:42.805807
3196 01:35:42.808000 RX Vref 0 -> 0, step: 1
3197 01:35:42.808418
3198 01:35:42.811763 RX Delay -40 -> 252, step: 8
3199 01:35:42.815351 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3200 01:35:42.818636 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3201 01:35:42.821833 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3202 01:35:42.828005 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3203 01:35:42.831635 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3204 01:35:42.834858 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3205 01:35:42.838160 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3206 01:35:42.841273 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3207 01:35:42.848074 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 01:35:42.851111 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3209 01:35:42.855326 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3210 01:35:42.857596 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 01:35:42.861727 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3212 01:35:42.868306 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
3213 01:35:42.871842 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3214 01:35:42.874498 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3215 01:35:42.875256 ==
3216 01:35:42.877695 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 01:35:42.880946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 01:35:42.881409 ==
3219 01:35:42.886035 DQS Delay:
3220 01:35:42.886466 DQS0 = 0, DQS1 = 0
3221 01:35:42.886800 DQM Delay:
3222 01:35:42.887996 DQM0 = 116, DQM1 = 110
3223 01:35:42.888410 DQ Delay:
3224 01:35:42.891393 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3225 01:35:42.894877 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3226 01:35:42.899428 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3227 01:35:42.906567 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =115
3228 01:35:42.907118
3229 01:35:42.907656
3230 01:35:42.908125 ==
3231 01:35:42.909081 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 01:35:42.911451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 01:35:42.911866 ==
3234 01:35:42.912195
3235 01:35:42.912548
3236 01:35:42.914895 TX Vref Scan disable
3237 01:35:42.915308 == TX Byte 0 ==
3238 01:35:42.921359 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3239 01:35:42.925200 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3240 01:35:42.925832 == TX Byte 1 ==
3241 01:35:42.932046 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3242 01:35:42.935677 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3243 01:35:42.936284 ==
3244 01:35:42.938814 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 01:35:42.941933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 01:35:42.942504 ==
3247 01:35:42.954095 TX Vref=22, minBit 0, minWin=25, winSum=410
3248 01:35:42.957686 TX Vref=24, minBit 1, minWin=25, winSum=417
3249 01:35:42.961633 TX Vref=26, minBit 1, minWin=25, winSum=421
3250 01:35:42.964683 TX Vref=28, minBit 1, minWin=25, winSum=427
3251 01:35:42.968952 TX Vref=30, minBit 0, minWin=26, winSum=427
3252 01:35:42.971476 TX Vref=32, minBit 3, minWin=25, winSum=427
3253 01:35:42.978095 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
3254 01:35:42.978670
3255 01:35:42.981116 Final TX Range 1 Vref 30
3256 01:35:42.981583
3257 01:35:42.981951 ==
3258 01:35:42.985147 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 01:35:42.987894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 01:35:42.988463 ==
3261 01:35:42.988836
3262 01:35:42.989251
3263 01:35:42.991235 TX Vref Scan disable
3264 01:35:42.994504 == TX Byte 0 ==
3265 01:35:42.997568 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3266 01:35:43.000880 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3267 01:35:43.004349 == TX Byte 1 ==
3268 01:35:43.007691 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3269 01:35:43.010872 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3270 01:35:43.011502
3271 01:35:43.014314 [DATLAT]
3272 01:35:43.014775 Freq=1200, CH1 RK0
3273 01:35:43.015145
3274 01:35:43.018283 DATLAT Default: 0xd
3275 01:35:43.018746 0, 0xFFFF, sum = 0
3276 01:35:43.020801 1, 0xFFFF, sum = 0
3277 01:35:43.021295 2, 0xFFFF, sum = 0
3278 01:35:43.024584 3, 0xFFFF, sum = 0
3279 01:35:43.025213 4, 0xFFFF, sum = 0
3280 01:35:43.027929 5, 0xFFFF, sum = 0
3281 01:35:43.028394 6, 0xFFFF, sum = 0
3282 01:35:43.031343 7, 0xFFFF, sum = 0
3283 01:35:43.031907 8, 0xFFFF, sum = 0
3284 01:35:43.034829 9, 0xFFFF, sum = 0
3285 01:35:43.035405 10, 0xFFFF, sum = 0
3286 01:35:43.038007 11, 0xFFFF, sum = 0
3287 01:35:43.038474 12, 0x0, sum = 1
3288 01:35:43.041137 13, 0x0, sum = 2
3289 01:35:43.041625 14, 0x0, sum = 3
3290 01:35:43.044404 15, 0x0, sum = 4
3291 01:35:43.045031 best_step = 13
3292 01:35:43.045418
3293 01:35:43.045759 ==
3294 01:35:43.048119 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 01:35:43.054393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 01:35:43.054858 ==
3297 01:35:43.055222 RX Vref Scan: 1
3298 01:35:43.055563
3299 01:35:43.057559 Set Vref Range= 32 -> 127
3300 01:35:43.057974
3301 01:35:43.061528 RX Vref 32 -> 127, step: 1
3302 01:35:43.061955
3303 01:35:43.062417 RX Delay -21 -> 252, step: 4
3304 01:35:43.064732
3305 01:35:43.065180 Set Vref, RX VrefLevel [Byte0]: 32
3306 01:35:43.067890 [Byte1]: 32
3307 01:35:43.073733
3308 01:35:43.074127 Set Vref, RX VrefLevel [Byte0]: 33
3309 01:35:43.075353 [Byte1]: 33
3310 01:35:43.080864
3311 01:35:43.081287 Set Vref, RX VrefLevel [Byte0]: 34
3312 01:35:43.083406 [Byte1]: 34
3313 01:35:43.089090
3314 01:35:43.089474 Set Vref, RX VrefLevel [Byte0]: 35
3315 01:35:43.091595 [Byte1]: 35
3316 01:35:43.096455
3317 01:35:43.096939 Set Vref, RX VrefLevel [Byte0]: 36
3318 01:35:43.099702 [Byte1]: 36
3319 01:35:43.104150
3320 01:35:43.104771 Set Vref, RX VrefLevel [Byte0]: 37
3321 01:35:43.107047 [Byte1]: 37
3322 01:35:43.112361
3323 01:35:43.112918 Set Vref, RX VrefLevel [Byte0]: 38
3324 01:35:43.115497 [Byte1]: 38
3325 01:35:43.119706
3326 01:35:43.120166 Set Vref, RX VrefLevel [Byte0]: 39
3327 01:35:43.123191 [Byte1]: 39
3328 01:35:43.128346
3329 01:35:43.128906 Set Vref, RX VrefLevel [Byte0]: 40
3330 01:35:43.131596 [Byte1]: 40
3331 01:35:43.135900
3332 01:35:43.136450 Set Vref, RX VrefLevel [Byte0]: 41
3333 01:35:43.138882 [Byte1]: 41
3334 01:35:43.143343
3335 01:35:43.143803 Set Vref, RX VrefLevel [Byte0]: 42
3336 01:35:43.146640 [Byte1]: 42
3337 01:35:43.151776
3338 01:35:43.152329 Set Vref, RX VrefLevel [Byte0]: 43
3339 01:35:43.154966 [Byte1]: 43
3340 01:35:43.159714
3341 01:35:43.160267 Set Vref, RX VrefLevel [Byte0]: 44
3342 01:35:43.162861 [Byte1]: 44
3343 01:35:43.167572
3344 01:35:43.168122 Set Vref, RX VrefLevel [Byte0]: 45
3345 01:35:43.170914 [Byte1]: 45
3346 01:35:43.175329
3347 01:35:43.175839 Set Vref, RX VrefLevel [Byte0]: 46
3348 01:35:43.178891 [Byte1]: 46
3349 01:35:43.183447
3350 01:35:43.183916 Set Vref, RX VrefLevel [Byte0]: 47
3351 01:35:43.187879 [Byte1]: 47
3352 01:35:43.192286
3353 01:35:43.192834 Set Vref, RX VrefLevel [Byte0]: 48
3354 01:35:43.194747 [Byte1]: 48
3355 01:35:43.199890
3356 01:35:43.200444 Set Vref, RX VrefLevel [Byte0]: 49
3357 01:35:43.203033 [Byte1]: 49
3358 01:35:43.207250
3359 01:35:43.207799 Set Vref, RX VrefLevel [Byte0]: 50
3360 01:35:43.210222 [Byte1]: 50
3361 01:35:43.215676
3362 01:35:43.216229 Set Vref, RX VrefLevel [Byte0]: 51
3363 01:35:43.218441 [Byte1]: 51
3364 01:35:43.223192
3365 01:35:43.223746 Set Vref, RX VrefLevel [Byte0]: 52
3366 01:35:43.226025 [Byte1]: 52
3367 01:35:43.231036
3368 01:35:43.231589 Set Vref, RX VrefLevel [Byte0]: 53
3369 01:35:43.234230 [Byte1]: 53
3370 01:35:43.239963
3371 01:35:43.240461 Set Vref, RX VrefLevel [Byte0]: 54
3372 01:35:43.243259 [Byte1]: 54
3373 01:35:43.246928
3374 01:35:43.247488 Set Vref, RX VrefLevel [Byte0]: 55
3375 01:35:43.250177 [Byte1]: 55
3376 01:35:43.254447
3377 01:35:43.255008 Set Vref, RX VrefLevel [Byte0]: 56
3378 01:35:43.258547 [Byte1]: 56
3379 01:35:43.262392
3380 01:35:43.262979 Set Vref, RX VrefLevel [Byte0]: 57
3381 01:35:43.268951 [Byte1]: 57
3382 01:35:43.269582
3383 01:35:43.271874 Set Vref, RX VrefLevel [Byte0]: 58
3384 01:35:43.275413 [Byte1]: 58
3385 01:35:43.276008
3386 01:35:43.278839 Set Vref, RX VrefLevel [Byte0]: 59
3387 01:35:43.282108 [Byte1]: 59
3388 01:35:43.286390
3389 01:35:43.286953 Set Vref, RX VrefLevel [Byte0]: 60
3390 01:35:43.289757 [Byte1]: 60
3391 01:35:43.293927
3392 01:35:43.294480 Set Vref, RX VrefLevel [Byte0]: 61
3393 01:35:43.299170 [Byte1]: 61
3394 01:35:43.303448
3395 01:35:43.304002 Set Vref, RX VrefLevel [Byte0]: 62
3396 01:35:43.305965 [Byte1]: 62
3397 01:35:43.309835
3398 01:35:43.310386 Set Vref, RX VrefLevel [Byte0]: 63
3399 01:35:43.313301 [Byte1]: 63
3400 01:35:43.318239
3401 01:35:43.318794 Set Vref, RX VrefLevel [Byte0]: 64
3402 01:35:43.322273 [Byte1]: 64
3403 01:35:43.325845
3404 01:35:43.326400 Set Vref, RX VrefLevel [Byte0]: 65
3405 01:35:43.329018 [Byte1]: 65
3406 01:35:43.333969
3407 01:35:43.334537 Set Vref, RX VrefLevel [Byte0]: 66
3408 01:35:43.336962 [Byte1]: 66
3409 01:35:43.342189
3410 01:35:43.342742 Set Vref, RX VrefLevel [Byte0]: 67
3411 01:35:43.344780 [Byte1]: 67
3412 01:35:43.350241
3413 01:35:43.350799 Set Vref, RX VrefLevel [Byte0]: 68
3414 01:35:43.353330 [Byte1]: 68
3415 01:35:43.358372
3416 01:35:43.358937 Set Vref, RX VrefLevel [Byte0]: 69
3417 01:35:43.360946 [Byte1]: 69
3418 01:35:43.366335
3419 01:35:43.366889 Set Vref, RX VrefLevel [Byte0]: 70
3420 01:35:43.369508 [Byte1]: 70
3421 01:35:43.373164
3422 01:35:43.373628 Final RX Vref Byte 0 = 56 to rank0
3423 01:35:43.376877 Final RX Vref Byte 1 = 48 to rank0
3424 01:35:43.380294 Final RX Vref Byte 0 = 56 to rank1
3425 01:35:43.383084 Final RX Vref Byte 1 = 48 to rank1==
3426 01:35:43.387352 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 01:35:43.390110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 01:35:43.393742 ==
3429 01:35:43.394297 DQS Delay:
3430 01:35:43.394668 DQS0 = 0, DQS1 = 0
3431 01:35:43.397354 DQM Delay:
3432 01:35:43.397913 DQM0 = 116, DQM1 = 108
3433 01:35:43.400602 DQ Delay:
3434 01:35:43.403606 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3435 01:35:43.407050 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3436 01:35:43.410456 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3437 01:35:43.413556 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =112
3438 01:35:43.414031
3439 01:35:43.414603
3440 01:35:43.420322 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3441 01:35:43.423589 CH1 RK0: MR19=303, MR18=FFE4
3442 01:35:43.430453 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3443 01:35:43.431002
3444 01:35:43.434308 ----->DramcWriteLeveling(PI) begin...
3445 01:35:43.434783 ==
3446 01:35:43.436714 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 01:35:43.439957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 01:35:43.440465 ==
3449 01:35:43.443632 Write leveling (Byte 0): 28 => 28
3450 01:35:43.447086 Write leveling (Byte 1): 28 => 28
3451 01:35:43.451377 DramcWriteLeveling(PI) end<-----
3452 01:35:43.451931
3453 01:35:43.452301 ==
3454 01:35:43.454263 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 01:35:43.458042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 01:35:43.461085 ==
3457 01:35:43.461554 [Gating] SW mode calibration
3458 01:35:43.467441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 01:35:43.473563 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 01:35:43.477590 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 01:35:43.483749 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3462 01:35:43.487379 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 01:35:43.491009 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 01:35:43.497612 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 01:35:43.502255 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 01:35:43.503656 0 15 24 | B1->B0 | 3535 2828 | 0 0 | (0 0) (0 0)
3467 01:35:43.507570 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3468 01:35:43.513836 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3469 01:35:43.517056 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 01:35:43.521201 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 01:35:43.527245 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 01:35:43.530408 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 01:35:43.533460 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3474 01:35:43.540344 1 0 24 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
3475 01:35:43.543908 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3476 01:35:43.547978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 01:35:43.554100 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 01:35:43.557592 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 01:35:43.560563 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 01:35:43.569067 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 01:35:43.570861 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 01:35:43.576290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3483 01:35:43.581789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3484 01:35:43.583964 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 01:35:43.587711 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 01:35:43.591110 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 01:35:43.598340 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 01:35:43.601179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 01:35:43.604612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 01:35:43.611959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 01:35:43.615155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 01:35:43.617639 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 01:35:43.624523 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 01:35:43.628086 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 01:35:43.631002 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 01:35:43.637629 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 01:35:43.640785 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3498 01:35:43.644372 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 01:35:43.651649 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3500 01:35:43.652340 Total UI for P1: 0, mck2ui 16
3501 01:35:43.654817 best dqsien dly found for B0: ( 1, 3, 22)
3502 01:35:43.661145 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 01:35:43.664269 Total UI for P1: 0, mck2ui 16
3504 01:35:43.667938 best dqsien dly found for B1: ( 1, 3, 28)
3505 01:35:43.671046 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3506 01:35:43.674162 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3507 01:35:43.674632
3508 01:35:43.677735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3509 01:35:43.681108 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3510 01:35:43.684268 [Gating] SW calibration Done
3511 01:35:43.684734 ==
3512 01:35:43.688522 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 01:35:43.693915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 01:35:43.694477 ==
3515 01:35:43.695197 RX Vref Scan: 0
3516 01:35:43.695776
3517 01:35:43.696162 RX Vref 0 -> 0, step: 1
3518 01:35:43.697540
3519 01:35:43.698002 RX Delay -40 -> 252, step: 8
3520 01:35:43.704128 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3521 01:35:43.707787 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3522 01:35:43.711758 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3523 01:35:43.714941 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3524 01:35:43.717619 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3525 01:35:43.721557 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3526 01:35:43.728330 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3527 01:35:43.732054 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3528 01:35:43.735037 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3529 01:35:43.737569 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3530 01:35:43.740749 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3531 01:35:43.747750 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3532 01:35:43.751403 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3533 01:35:43.754809 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3534 01:35:43.757628 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3535 01:35:43.761264 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3536 01:35:43.764626 ==
3537 01:35:43.768630 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 01:35:43.771684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 01:35:43.772154 ==
3540 01:35:43.772532 DQS Delay:
3541 01:35:43.774398 DQS0 = 0, DQS1 = 0
3542 01:35:43.774861 DQM Delay:
3543 01:35:43.777422 DQM0 = 113, DQM1 = 108
3544 01:35:43.777887 DQ Delay:
3545 01:35:43.781219 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3546 01:35:43.784514 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3547 01:35:43.788038 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3548 01:35:43.791370 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3549 01:35:43.791938
3550 01:35:43.792308
3551 01:35:43.792652 ==
3552 01:35:43.794426 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 01:35:43.801275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 01:35:43.801872 ==
3555 01:35:43.802266
3556 01:35:43.802617
3557 01:35:43.802947 TX Vref Scan disable
3558 01:35:43.804576 == TX Byte 0 ==
3559 01:35:43.807342 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3560 01:35:43.811079 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3561 01:35:43.814165 == TX Byte 1 ==
3562 01:35:43.818221 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3563 01:35:43.822376 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3564 01:35:43.824084 ==
3565 01:35:43.827146 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 01:35:43.830889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 01:35:43.831355 ==
3568 01:35:43.841805 TX Vref=22, minBit 7, minWin=25, winSum=422
3569 01:35:43.845221 TX Vref=24, minBit 1, minWin=26, winSum=427
3570 01:35:43.849656 TX Vref=26, minBit 2, minWin=26, winSum=429
3571 01:35:43.852170 TX Vref=28, minBit 2, minWin=26, winSum=434
3572 01:35:43.855237 TX Vref=30, minBit 2, minWin=26, winSum=435
3573 01:35:43.858943 TX Vref=32, minBit 3, minWin=26, winSum=434
3574 01:35:43.865506 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 30
3575 01:35:43.866068
3576 01:35:43.869188 Final TX Range 1 Vref 30
3577 01:35:43.869746
3578 01:35:43.870112 ==
3579 01:35:43.872106 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 01:35:43.874900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 01:35:43.875368 ==
3582 01:35:43.875737
3583 01:35:43.879444
3584 01:35:43.880109 TX Vref Scan disable
3585 01:35:43.882053 == TX Byte 0 ==
3586 01:35:43.885363 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3587 01:35:43.888916 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3588 01:35:43.892182 == TX Byte 1 ==
3589 01:35:43.895389 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3590 01:35:43.898957 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3591 01:35:43.899530
3592 01:35:43.901819 [DATLAT]
3593 01:35:43.902284 Freq=1200, CH1 RK1
3594 01:35:43.902651
3595 01:35:43.905337 DATLAT Default: 0xd
3596 01:35:43.905802 0, 0xFFFF, sum = 0
3597 01:35:43.908673 1, 0xFFFF, sum = 0
3598 01:35:43.909242 2, 0xFFFF, sum = 0
3599 01:35:43.912123 3, 0xFFFF, sum = 0
3600 01:35:43.912592 4, 0xFFFF, sum = 0
3601 01:35:43.916324 5, 0xFFFF, sum = 0
3602 01:35:43.916895 6, 0xFFFF, sum = 0
3603 01:35:43.919506 7, 0xFFFF, sum = 0
3604 01:35:43.920084 8, 0xFFFF, sum = 0
3605 01:35:43.922813 9, 0xFFFF, sum = 0
3606 01:35:43.925267 10, 0xFFFF, sum = 0
3607 01:35:43.925757 11, 0xFFFF, sum = 0
3608 01:35:43.930462 12, 0x0, sum = 1
3609 01:35:43.931039 13, 0x0, sum = 2
3610 01:35:43.931534 14, 0x0, sum = 3
3611 01:35:43.932752 15, 0x0, sum = 4
3612 01:35:43.933270 best_step = 13
3613 01:35:43.933754
3614 01:35:43.934208 ==
3615 01:35:43.935834 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 01:35:43.941854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 01:35:43.942322 ==
3618 01:35:43.942698 RX Vref Scan: 0
3619 01:35:43.943046
3620 01:35:43.945157 RX Vref 0 -> 0, step: 1
3621 01:35:43.945883
3622 01:35:43.948338 RX Delay -21 -> 252, step: 4
3623 01:35:43.952144 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3624 01:35:43.955394 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3625 01:35:43.962958 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3626 01:35:43.965303 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3627 01:35:43.968732 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3628 01:35:43.972306 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3629 01:35:43.975275 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3630 01:35:43.981705 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3631 01:35:43.985313 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3632 01:35:43.988847 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3633 01:35:43.992248 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3634 01:35:43.995330 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3635 01:35:43.999301 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3636 01:35:44.006057 iDelay=191, Bit 13, Center 118 (51 ~ 186) 136
3637 01:35:44.009060 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3638 01:35:44.012155 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3639 01:35:44.012620 ==
3640 01:35:44.015809 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 01:35:44.018833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 01:35:44.022249 ==
3643 01:35:44.022882 DQS Delay:
3644 01:35:44.023314 DQS0 = 0, DQS1 = 0
3645 01:35:44.025327 DQM Delay:
3646 01:35:44.025994 DQM0 = 113, DQM1 = 108
3647 01:35:44.029095 DQ Delay:
3648 01:35:44.032014 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3649 01:35:44.035543 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3650 01:35:44.038468 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3651 01:35:44.042451 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =116
3652 01:35:44.042875
3653 01:35:44.043210
3654 01:35:44.048632 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 414 ps
3655 01:35:44.051762 CH1 RK1: MR19=303, MR18=F6FE
3656 01:35:44.058851 CH1_RK1: MR19=0x303, MR18=0xF6FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3657 01:35:44.062196 [RxdqsGatingPostProcess] freq 1200
3658 01:35:44.069311 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3659 01:35:44.069738 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 01:35:44.072291 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 01:35:44.075518 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 01:35:44.078786 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 01:35:44.082356 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 01:35:44.086010 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 01:35:44.089003 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 01:35:44.092213 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 01:35:44.095177 Pre-setting of DQS Precalculation
3668 01:35:44.102249 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3669 01:35:44.109072 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3670 01:35:44.116026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3671 01:35:44.116547
3672 01:35:44.116883
3673 01:35:44.119148 [Calibration Summary] 2400 Mbps
3674 01:35:44.119677 CH 0, Rank 0
3675 01:35:44.122395 SW Impedance : PASS
3676 01:35:44.122916 DUTY Scan : NO K
3677 01:35:44.125584 ZQ Calibration : PASS
3678 01:35:44.128584 Jitter Meter : NO K
3679 01:35:44.129165 CBT Training : PASS
3680 01:35:44.131748 Write leveling : PASS
3681 01:35:44.135507 RX DQS gating : PASS
3682 01:35:44.136065 RX DQ/DQS(RDDQC) : PASS
3683 01:35:44.138469 TX DQ/DQS : PASS
3684 01:35:44.142894 RX DATLAT : PASS
3685 01:35:44.143321 RX DQ/DQS(Engine): PASS
3686 01:35:44.146129 TX OE : NO K
3687 01:35:44.146830 All Pass.
3688 01:35:44.147332
3689 01:35:44.148938 CH 0, Rank 1
3690 01:35:44.149417 SW Impedance : PASS
3691 01:35:44.152652 DUTY Scan : NO K
3692 01:35:44.155556 ZQ Calibration : PASS
3693 01:35:44.156098 Jitter Meter : NO K
3694 01:35:44.159181 CBT Training : PASS
3695 01:35:44.163136 Write leveling : PASS
3696 01:35:44.163558 RX DQS gating : PASS
3697 01:35:44.166142 RX DQ/DQS(RDDQC) : PASS
3698 01:35:44.166656 TX DQ/DQS : PASS
3699 01:35:44.168849 RX DATLAT : PASS
3700 01:35:44.171964 RX DQ/DQS(Engine): PASS
3701 01:35:44.172666 TX OE : NO K
3702 01:35:44.175487 All Pass.
3703 01:35:44.175907
3704 01:35:44.176242 CH 1, Rank 0
3705 01:35:44.178736 SW Impedance : PASS
3706 01:35:44.179161 DUTY Scan : NO K
3707 01:35:44.182218 ZQ Calibration : PASS
3708 01:35:44.185131 Jitter Meter : NO K
3709 01:35:44.185553 CBT Training : PASS
3710 01:35:44.188883 Write leveling : PASS
3711 01:35:44.192504 RX DQS gating : PASS
3712 01:35:44.192925 RX DQ/DQS(RDDQC) : PASS
3713 01:35:44.196146 TX DQ/DQS : PASS
3714 01:35:44.198965 RX DATLAT : PASS
3715 01:35:44.199392 RX DQ/DQS(Engine): PASS
3716 01:35:44.202451 TX OE : NO K
3717 01:35:44.203095 All Pass.
3718 01:35:44.203449
3719 01:35:44.205453 CH 1, Rank 1
3720 01:35:44.205873 SW Impedance : PASS
3721 01:35:44.208528 DUTY Scan : NO K
3722 01:35:44.208948 ZQ Calibration : PASS
3723 01:35:44.213175 Jitter Meter : NO K
3724 01:35:44.215571 CBT Training : PASS
3725 01:35:44.216039 Write leveling : PASS
3726 01:35:44.218956 RX DQS gating : PASS
3727 01:35:44.222601 RX DQ/DQS(RDDQC) : PASS
3728 01:35:44.223114 TX DQ/DQS : PASS
3729 01:35:44.225606 RX DATLAT : PASS
3730 01:35:44.229496 RX DQ/DQS(Engine): PASS
3731 01:35:44.229920 TX OE : NO K
3732 01:35:44.232490 All Pass.
3733 01:35:44.232908
3734 01:35:44.233302 DramC Write-DBI off
3735 01:35:44.236030 PER_BANK_REFRESH: Hybrid Mode
3736 01:35:44.236452 TX_TRACKING: ON
3737 01:35:44.245564 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3738 01:35:44.248723 [FAST_K] Save calibration result to emmc
3739 01:35:44.252045 dramc_set_vcore_voltage set vcore to 650000
3740 01:35:44.255149 Read voltage for 600, 5
3741 01:35:44.255671 Vio18 = 0
3742 01:35:44.258477 Vcore = 650000
3743 01:35:44.258901 Vdram = 0
3744 01:35:44.259237 Vddq = 0
3745 01:35:44.259553 Vmddr = 0
3746 01:35:44.265505 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3747 01:35:44.272622 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3748 01:35:44.273261 MEM_TYPE=3, freq_sel=19
3749 01:35:44.276093 sv_algorithm_assistance_LP4_1600
3750 01:35:44.278674 ============ PULL DRAM RESETB DOWN ============
3751 01:35:44.285562 ========== PULL DRAM RESETB DOWN end =========
3752 01:35:44.288574 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 01:35:44.291946 ===================================
3754 01:35:44.295566 LPDDR4 DRAM CONFIGURATION
3755 01:35:44.298907 ===================================
3756 01:35:44.299423 EX_ROW_EN[0] = 0x0
3757 01:35:44.302268 EX_ROW_EN[1] = 0x0
3758 01:35:44.302783 LP4Y_EN = 0x0
3759 01:35:44.306181 WORK_FSP = 0x0
3760 01:35:44.308519 WL = 0x2
3761 01:35:44.309300 RL = 0x2
3762 01:35:44.312067 BL = 0x2
3763 01:35:44.312491 RPST = 0x0
3764 01:35:44.315219 RD_PRE = 0x0
3765 01:35:44.315642 WR_PRE = 0x1
3766 01:35:44.318644 WR_PST = 0x0
3767 01:35:44.319064 DBI_WR = 0x0
3768 01:35:44.321886 DBI_RD = 0x0
3769 01:35:44.322464 OTF = 0x1
3770 01:35:44.326766 ===================================
3771 01:35:44.329048 ===================================
3772 01:35:44.332382 ANA top config
3773 01:35:44.335377 ===================================
3774 01:35:44.335803 DLL_ASYNC_EN = 0
3775 01:35:44.339060 ALL_SLAVE_EN = 1
3776 01:35:44.342159 NEW_RANK_MODE = 1
3777 01:35:44.345364 DLL_IDLE_MODE = 1
3778 01:35:44.345788 LP45_APHY_COMB_EN = 1
3779 01:35:44.348671 TX_ODT_DIS = 1
3780 01:35:44.352325 NEW_8X_MODE = 1
3781 01:35:44.355880 ===================================
3782 01:35:44.359338 ===================================
3783 01:35:44.362129 data_rate = 1200
3784 01:35:44.365633 CKR = 1
3785 01:35:44.366151 DQ_P2S_RATIO = 8
3786 01:35:44.368796 ===================================
3787 01:35:44.372849 CA_P2S_RATIO = 8
3788 01:35:44.376243 DQ_CA_OPEN = 0
3789 01:35:44.380180 DQ_SEMI_OPEN = 0
3790 01:35:44.382138 CA_SEMI_OPEN = 0
3791 01:35:44.385637 CA_FULL_RATE = 0
3792 01:35:44.386060 DQ_CKDIV4_EN = 1
3793 01:35:44.389368 CA_CKDIV4_EN = 1
3794 01:35:44.392182 CA_PREDIV_EN = 0
3795 01:35:44.395561 PH8_DLY = 0
3796 01:35:44.399515 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3797 01:35:44.400031 DQ_AAMCK_DIV = 4
3798 01:35:44.402253 CA_AAMCK_DIV = 4
3799 01:35:44.406141 CA_ADMCK_DIV = 4
3800 01:35:44.409368 DQ_TRACK_CA_EN = 0
3801 01:35:44.412390 CA_PICK = 600
3802 01:35:44.416060 CA_MCKIO = 600
3803 01:35:44.418904 MCKIO_SEMI = 0
3804 01:35:44.419417 PLL_FREQ = 2288
3805 01:35:44.422925 DQ_UI_PI_RATIO = 32
3806 01:35:44.426198 CA_UI_PI_RATIO = 0
3807 01:35:44.429378 ===================================
3808 01:35:44.432225 ===================================
3809 01:35:44.435669 memory_type:LPDDR4
3810 01:35:44.436208 GP_NUM : 10
3811 01:35:44.439670 SRAM_EN : 1
3812 01:35:44.442287 MD32_EN : 0
3813 01:35:44.445804 ===================================
3814 01:35:44.446327 [ANA_INIT] >>>>>>>>>>>>>>
3815 01:35:44.449559 <<<<<< [CONFIGURE PHASE]: ANA_TX
3816 01:35:44.452312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3817 01:35:44.455859 ===================================
3818 01:35:44.459723 data_rate = 1200,PCW = 0X5800
3819 01:35:44.463491 ===================================
3820 01:35:44.465597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3821 01:35:44.472947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 01:35:44.476116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 01:35:44.483015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3824 01:35:44.487580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3825 01:35:44.489676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3826 01:35:44.490104 [ANA_INIT] flow start
3827 01:35:44.493695 [ANA_INIT] PLL >>>>>>>>
3828 01:35:44.495933 [ANA_INIT] PLL <<<<<<<<
3829 01:35:44.496355 [ANA_INIT] MIDPI >>>>>>>>
3830 01:35:44.498917 [ANA_INIT] MIDPI <<<<<<<<
3831 01:35:44.502631 [ANA_INIT] DLL >>>>>>>>
3832 01:35:44.503148 [ANA_INIT] flow end
3833 01:35:44.509119 ============ LP4 DIFF to SE enter ============
3834 01:35:44.512602 ============ LP4 DIFF to SE exit ============
3835 01:35:44.515865 [ANA_INIT] <<<<<<<<<<<<<
3836 01:35:44.519286 [Flow] Enable top DCM control >>>>>
3837 01:35:44.522159 [Flow] Enable top DCM control <<<<<
3838 01:35:44.526274 Enable DLL master slave shuffle
3839 01:35:44.528886 ==============================================================
3840 01:35:44.533037 Gating Mode config
3841 01:35:44.535376 ==============================================================
3842 01:35:44.539691 Config description:
3843 01:35:44.549070 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3844 01:35:44.556160 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3845 01:35:44.559297 SELPH_MODE 0: By rank 1: By Phase
3846 01:35:44.565726 ==============================================================
3847 01:35:44.569130 GAT_TRACK_EN = 1
3848 01:35:44.572473 RX_GATING_MODE = 2
3849 01:35:44.575941 RX_GATING_TRACK_MODE = 2
3850 01:35:44.580191 SELPH_MODE = 1
3851 01:35:44.580711 PICG_EARLY_EN = 1
3852 01:35:44.582599 VALID_LAT_VALUE = 1
3853 01:35:44.589354 ==============================================================
3854 01:35:44.592265 Enter into Gating configuration >>>>
3855 01:35:44.595750 Exit from Gating configuration <<<<
3856 01:35:44.599498 Enter into DVFS_PRE_config >>>>>
3857 01:35:44.608805 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3858 01:35:44.611767 Exit from DVFS_PRE_config <<<<<
3859 01:35:44.615435 Enter into PICG configuration >>>>
3860 01:35:44.618808 Exit from PICG configuration <<<<
3861 01:35:44.622443 [RX_INPUT] configuration >>>>>
3862 01:35:44.625226 [RX_INPUT] configuration <<<<<
3863 01:35:44.629949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3864 01:35:44.635737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3865 01:35:44.642191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 01:35:44.649344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 01:35:44.655957 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 01:35:44.659180 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 01:35:44.665926 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3870 01:35:44.669431 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3871 01:35:44.672479 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3872 01:35:44.675935 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3873 01:35:44.678929 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3874 01:35:44.686398 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 01:35:44.688843 ===================================
3876 01:35:44.692876 LPDDR4 DRAM CONFIGURATION
3877 01:35:44.693476 ===================================
3878 01:35:44.695572 EX_ROW_EN[0] = 0x0
3879 01:35:44.699104 EX_ROW_EN[1] = 0x0
3880 01:35:44.699660 LP4Y_EN = 0x0
3881 01:35:44.702247 WORK_FSP = 0x0
3882 01:35:44.702713 WL = 0x2
3883 01:35:44.706314 RL = 0x2
3884 01:35:44.706874 BL = 0x2
3885 01:35:44.709489 RPST = 0x0
3886 01:35:44.710115 RD_PRE = 0x0
3887 01:35:44.712588 WR_PRE = 0x1
3888 01:35:44.713117 WR_PST = 0x0
3889 01:35:44.716042 DBI_WR = 0x0
3890 01:35:44.716595 DBI_RD = 0x0
3891 01:35:44.718655 OTF = 0x1
3892 01:35:44.722873 ===================================
3893 01:35:44.726442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3894 01:35:44.728664 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3895 01:35:44.736154 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 01:35:44.739853 ===================================
3897 01:35:44.740515 LPDDR4 DRAM CONFIGURATION
3898 01:35:44.742496 ===================================
3899 01:35:44.745580 EX_ROW_EN[0] = 0x10
3900 01:35:44.749290 EX_ROW_EN[1] = 0x0
3901 01:35:44.750038 LP4Y_EN = 0x0
3902 01:35:44.751993 WORK_FSP = 0x0
3903 01:35:44.752456 WL = 0x2
3904 01:35:44.755485 RL = 0x2
3905 01:35:44.755951 BL = 0x2
3906 01:35:44.759472 RPST = 0x0
3907 01:35:44.760033 RD_PRE = 0x0
3908 01:35:44.762899 WR_PRE = 0x1
3909 01:35:44.763454 WR_PST = 0x0
3910 01:35:44.765969 DBI_WR = 0x0
3911 01:35:44.766435 DBI_RD = 0x0
3912 01:35:44.768947 OTF = 0x1
3913 01:35:44.773577 ===================================
3914 01:35:44.779217 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3915 01:35:44.782937 nWR fixed to 30
3916 01:35:44.783410 [ModeRegInit_LP4] CH0 RK0
3917 01:35:44.785992 [ModeRegInit_LP4] CH0 RK1
3918 01:35:44.789078 [ModeRegInit_LP4] CH1 RK0
3919 01:35:44.789630 [ModeRegInit_LP4] CH1 RK1
3920 01:35:44.792369 match AC timing 17
3921 01:35:44.795586 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3922 01:35:44.799307 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3923 01:35:44.806159 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3924 01:35:44.809019 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3925 01:35:44.816054 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3926 01:35:44.816615 ==
3927 01:35:44.819172 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 01:35:44.822305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 01:35:44.822868 ==
3930 01:35:44.828943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 01:35:44.832589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3932 01:35:44.837024 [CA 0] Center 36 (6~67) winsize 62
3933 01:35:44.840578 [CA 1] Center 36 (6~66) winsize 61
3934 01:35:44.843002 [CA 2] Center 34 (4~65) winsize 62
3935 01:35:44.846803 [CA 3] Center 34 (4~65) winsize 62
3936 01:35:44.850746 [CA 4] Center 33 (3~64) winsize 62
3937 01:35:44.853233 [CA 5] Center 33 (3~64) winsize 62
3938 01:35:44.853787
3939 01:35:44.856804 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3940 01:35:44.857415
3941 01:35:44.860037 [CATrainingPosCal] consider 1 rank data
3942 01:35:44.863219 u2DelayCellTimex100 = 270/100 ps
3943 01:35:44.866593 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3944 01:35:44.870505 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3945 01:35:44.876718 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 01:35:44.879872 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 01:35:44.883434 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 01:35:44.886618 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 01:35:44.887086
3950 01:35:44.889930 CA PerBit enable=1, Macro0, CA PI delay=33
3951 01:35:44.890486
3952 01:35:44.893508 [CBTSetCACLKResult] CA Dly = 33
3953 01:35:44.893972 CS Dly: 6 (0~37)
3954 01:35:44.897438 ==
3955 01:35:44.897999 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 01:35:44.903328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 01:35:44.903886 ==
3958 01:35:44.906733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 01:35:44.913425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3960 01:35:44.917621 [CA 0] Center 36 (6~67) winsize 62
3961 01:35:44.920010 [CA 1] Center 36 (6~66) winsize 61
3962 01:35:44.923739 [CA 2] Center 34 (4~65) winsize 62
3963 01:35:44.926848 [CA 3] Center 34 (4~64) winsize 61
3964 01:35:44.930687 [CA 4] Center 33 (3~64) winsize 62
3965 01:35:44.933704 [CA 5] Center 33 (3~64) winsize 62
3966 01:35:44.934173
3967 01:35:44.936791 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3968 01:35:44.937401
3969 01:35:44.940794 [CATrainingPosCal] consider 2 rank data
3970 01:35:44.943141 u2DelayCellTimex100 = 270/100 ps
3971 01:35:44.947148 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3972 01:35:44.950230 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3973 01:35:44.956783 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3974 01:35:44.960191 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3975 01:35:44.963992 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 01:35:44.966231 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 01:35:44.966699
3978 01:35:44.969826 CA PerBit enable=1, Macro0, CA PI delay=33
3979 01:35:44.970387
3980 01:35:44.973519 [CBTSetCACLKResult] CA Dly = 33
3981 01:35:44.974081 CS Dly: 5 (0~36)
3982 01:35:44.974458
3983 01:35:44.976683 ----->DramcWriteLeveling(PI) begin...
3984 01:35:44.979741 ==
3985 01:35:44.983227 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 01:35:44.986636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 01:35:44.987106 ==
3988 01:35:44.990203 Write leveling (Byte 0): 35 => 35
3989 01:35:44.993486 Write leveling (Byte 1): 31 => 31
3990 01:35:44.996846 DramcWriteLeveling(PI) end<-----
3991 01:35:44.997367
3992 01:35:44.997742 ==
3993 01:35:44.999760 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 01:35:45.003663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 01:35:45.004225 ==
3996 01:35:45.006539 [Gating] SW mode calibration
3997 01:35:45.013516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3998 01:35:45.016778 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3999 01:35:45.024229 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 01:35:45.026623 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 01:35:45.031445 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 01:35:45.037058 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4003 01:35:45.040075 0 9 16 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 1)
4004 01:35:45.043333 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4005 01:35:45.049959 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 01:35:45.054683 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 01:35:45.057341 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 01:35:45.063910 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 01:35:45.066406 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 01:35:45.070539 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4011 01:35:45.077128 0 10 16 | B1->B0 | 2f2f 4242 | 0 0 | (0 0) (0 0)
4012 01:35:45.080113 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 01:35:45.083220 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 01:35:45.089908 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 01:35:45.093629 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 01:35:45.096359 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 01:35:45.100045 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 01:35:45.106693 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 01:35:45.110303 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4020 01:35:45.113196 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4021 01:35:45.119859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 01:35:45.123726 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 01:35:45.127503 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 01:35:45.133636 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 01:35:45.137510 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 01:35:45.141210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 01:35:45.146943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 01:35:45.150581 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 01:35:45.153689 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 01:35:45.160421 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 01:35:45.163472 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 01:35:45.166923 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 01:35:45.174303 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 01:35:45.176534 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 01:35:45.180079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4036 01:35:45.186674 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 01:35:45.187175 Total UI for P1: 0, mck2ui 16
4038 01:35:45.189981 best dqsien dly found for B0: ( 0, 13, 16)
4039 01:35:45.193351 Total UI for P1: 0, mck2ui 16
4040 01:35:45.196771 best dqsien dly found for B1: ( 0, 13, 16)
4041 01:35:45.200174 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4042 01:35:45.207012 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4043 01:35:45.207589
4044 01:35:45.209719 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4045 01:35:45.213164 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4046 01:35:45.216327 [Gating] SW calibration Done
4047 01:35:45.216854 ==
4048 01:35:45.220078 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 01:35:45.223488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 01:35:45.224063 ==
4051 01:35:45.224439 RX Vref Scan: 0
4052 01:35:45.226758
4053 01:35:45.227497 RX Vref 0 -> 0, step: 1
4054 01:35:45.227895
4055 01:35:45.230054 RX Delay -230 -> 252, step: 16
4056 01:35:45.233270 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4057 01:35:45.240242 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4058 01:35:45.243926 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4059 01:35:45.247820 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4060 01:35:45.251041 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4061 01:35:45.254298 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4062 01:35:45.260606 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4063 01:35:45.263870 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4064 01:35:45.267910 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4065 01:35:45.270349 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4066 01:35:45.273945 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4067 01:35:45.281654 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4068 01:35:45.285289 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4069 01:35:45.287123 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4070 01:35:45.289975 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4071 01:35:45.296661 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4072 01:35:45.297287 ==
4073 01:35:45.300207 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 01:35:45.303364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 01:35:45.303938 ==
4076 01:35:45.304319 DQS Delay:
4077 01:35:45.306669 DQS0 = 0, DQS1 = 0
4078 01:35:45.307241 DQM Delay:
4079 01:35:45.310907 DQM0 = 42, DQM1 = 33
4080 01:35:45.311481 DQ Delay:
4081 01:35:45.313581 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4082 01:35:45.316723 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4083 01:35:45.320375 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4084 01:35:45.323161 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4085 01:35:45.323629
4086 01:35:45.324003
4087 01:35:45.324343 ==
4088 01:35:45.327185 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 01:35:45.330179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 01:35:45.330748 ==
4091 01:35:45.333211
4092 01:35:45.333701
4093 01:35:45.334135 TX Vref Scan disable
4094 01:35:45.336440 == TX Byte 0 ==
4095 01:35:45.340087 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4096 01:35:45.344229 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4097 01:35:45.346823 == TX Byte 1 ==
4098 01:35:45.350978 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4099 01:35:45.353503 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4100 01:35:45.356618 ==
4101 01:35:45.357236 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 01:35:45.363874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 01:35:45.364343 ==
4104 01:35:45.364714
4105 01:35:45.365112
4106 01:35:45.366460 TX Vref Scan disable
4107 01:35:45.367000 == TX Byte 0 ==
4108 01:35:45.373202 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4109 01:35:45.376572 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4110 01:35:45.377078 == TX Byte 1 ==
4111 01:35:45.383323 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4112 01:35:45.386580 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4113 01:35:45.387060
4114 01:35:45.387452 [DATLAT]
4115 01:35:45.390255 Freq=600, CH0 RK0
4116 01:35:45.390800
4117 01:35:45.391174 DATLAT Default: 0x9
4118 01:35:45.393581 0, 0xFFFF, sum = 0
4119 01:35:45.394143 1, 0xFFFF, sum = 0
4120 01:35:45.396909 2, 0xFFFF, sum = 0
4121 01:35:45.397380 3, 0xFFFF, sum = 0
4122 01:35:45.399833 4, 0xFFFF, sum = 0
4123 01:35:45.402926 5, 0xFFFF, sum = 0
4124 01:35:45.403356 6, 0xFFFF, sum = 0
4125 01:35:45.406701 7, 0xFFFF, sum = 0
4126 01:35:45.407132 8, 0x0, sum = 1
4127 01:35:45.407479 9, 0x0, sum = 2
4128 01:35:45.409770 10, 0x0, sum = 3
4129 01:35:45.410218 11, 0x0, sum = 4
4130 01:35:45.412967 best_step = 9
4131 01:35:45.413419
4132 01:35:45.413753 ==
4133 01:35:45.416346 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 01:35:45.419281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 01:35:45.419707 ==
4136 01:35:45.422847 RX Vref Scan: 1
4137 01:35:45.423267
4138 01:35:45.423601 RX Vref 0 -> 0, step: 1
4139 01:35:45.423915
4140 01:35:45.426806 RX Delay -179 -> 252, step: 8
4141 01:35:45.427333
4142 01:35:45.429497 Set Vref, RX VrefLevel [Byte0]: 52
4143 01:35:45.432725 [Byte1]: 52
4144 01:35:45.436765
4145 01:35:45.437295 Final RX Vref Byte 0 = 52 to rank0
4146 01:35:45.440150 Final RX Vref Byte 1 = 52 to rank0
4147 01:35:45.443600 Final RX Vref Byte 0 = 52 to rank1
4148 01:35:45.446710 Final RX Vref Byte 1 = 52 to rank1==
4149 01:35:45.450710 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 01:35:45.457228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 01:35:45.457736 ==
4152 01:35:45.458075 DQS Delay:
4153 01:35:45.458390 DQS0 = 0, DQS1 = 0
4154 01:35:45.461414 DQM Delay:
4155 01:35:45.462032 DQM0 = 42, DQM1 = 33
4156 01:35:45.465224 DQ Delay:
4157 01:35:45.466680 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4158 01:35:45.471419 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4159 01:35:45.472170 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4160 01:35:45.477630 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4161 01:35:45.478056
4162 01:35:45.478384
4163 01:35:45.484077 [DQSOSCAuto] RK0, (LSB)MR18= 0x4423, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4164 01:35:45.486829 CH0 RK0: MR19=808, MR18=4423
4165 01:35:45.493630 CH0_RK0: MR19=0x808, MR18=0x4423, DQSOSC=396, MR23=63, INC=167, DEC=111
4166 01:35:45.494052
4167 01:35:45.497367 ----->DramcWriteLeveling(PI) begin...
4168 01:35:45.498033 ==
4169 01:35:45.499931 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 01:35:45.503807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 01:35:45.504240 ==
4172 01:35:45.506947 Write leveling (Byte 0): 31 => 31
4173 01:35:45.510354 Write leveling (Byte 1): 31 => 31
4174 01:35:45.513571 DramcWriteLeveling(PI) end<-----
4175 01:35:45.514237
4176 01:35:45.514718 ==
4177 01:35:45.516723 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 01:35:45.520366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 01:35:45.520791 ==
4180 01:35:45.523712 [Gating] SW mode calibration
4181 01:35:45.530647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4182 01:35:45.537396 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4183 01:35:45.540053 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 01:35:45.543272 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 01:35:45.549907 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4186 01:35:45.553309 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
4187 01:35:45.557011 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
4188 01:35:45.563380 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 01:35:45.566660 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 01:35:45.569801 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 01:35:45.577440 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 01:35:45.583268 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 01:35:45.584297 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 01:35:45.590640 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4195 01:35:45.593461 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
4196 01:35:45.597354 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 01:35:45.603411 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 01:35:45.607050 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 01:35:45.611353 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 01:35:45.614616 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 01:35:45.620241 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 01:35:45.624708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4203 01:35:45.626729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4204 01:35:45.633348 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 01:35:45.637135 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 01:35:45.640098 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 01:35:45.646990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 01:35:45.650326 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 01:35:45.653573 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 01:35:45.660484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 01:35:45.663852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 01:35:45.666952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 01:35:45.674013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 01:35:45.677097 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 01:35:45.680565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 01:35:45.687176 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 01:35:45.690954 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 01:35:45.695080 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4219 01:35:45.699315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4220 01:35:45.700511 Total UI for P1: 0, mck2ui 16
4221 01:35:45.703692 best dqsien dly found for B0: ( 0, 13, 12)
4222 01:35:45.710965 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 01:35:45.713912 Total UI for P1: 0, mck2ui 16
4224 01:35:45.717018 best dqsien dly found for B1: ( 0, 13, 16)
4225 01:35:45.720235 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4226 01:35:45.723946 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4227 01:35:45.724513
4228 01:35:45.727889 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4229 01:35:45.731060 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4230 01:35:45.734067 [Gating] SW calibration Done
4231 01:35:45.734535 ==
4232 01:35:45.737078 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 01:35:45.741665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 01:35:45.742150 ==
4235 01:35:45.744361 RX Vref Scan: 0
4236 01:35:45.744877
4237 01:35:45.747190 RX Vref 0 -> 0, step: 1
4238 01:35:45.747743
4239 01:35:45.748116 RX Delay -230 -> 252, step: 16
4240 01:35:45.754402 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4241 01:35:45.756876 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4242 01:35:45.760417 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4243 01:35:45.764272 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4244 01:35:45.767909 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4245 01:35:45.774051 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4246 01:35:45.777350 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4247 01:35:45.781162 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4248 01:35:45.784214 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4249 01:35:45.791792 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4250 01:35:45.793595 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4251 01:35:45.797309 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4252 01:35:45.800915 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4253 01:35:45.803557 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4254 01:35:45.812291 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4255 01:35:45.814730 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4256 01:35:45.815289 ==
4257 01:35:45.817587 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 01:35:45.820506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 01:35:45.821105 ==
4260 01:35:45.823868 DQS Delay:
4261 01:35:45.824423 DQS0 = 0, DQS1 = 0
4262 01:35:45.827543 DQM Delay:
4263 01:35:45.828100 DQM0 = 42, DQM1 = 34
4264 01:35:45.828476 DQ Delay:
4265 01:35:45.831727 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4266 01:35:45.833746 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4267 01:35:45.837581 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4268 01:35:45.840597 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4269 01:35:45.841190
4270 01:35:45.841571
4271 01:35:45.841989 ==
4272 01:35:45.843544 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 01:35:45.850231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 01:35:45.850779 ==
4275 01:35:45.851155
4276 01:35:45.851497
4277 01:35:45.851824 TX Vref Scan disable
4278 01:35:45.854524 == TX Byte 0 ==
4279 01:35:45.858569 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4280 01:35:45.864517 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4281 01:35:45.865133 == TX Byte 1 ==
4282 01:35:45.867534 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4283 01:35:45.874829 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4284 01:35:45.875388 ==
4285 01:35:45.877292 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 01:35:45.881352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 01:35:45.881822 ==
4288 01:35:45.882194
4289 01:35:45.882534
4290 01:35:45.884417 TX Vref Scan disable
4291 01:35:45.884881 == TX Byte 0 ==
4292 01:35:45.890656 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4293 01:35:45.894027 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4294 01:35:45.894510 == TX Byte 1 ==
4295 01:35:45.900734 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4296 01:35:45.903995 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4297 01:35:45.904416
4298 01:35:45.904745 [DATLAT]
4299 01:35:45.907543 Freq=600, CH0 RK1
4300 01:35:45.907964
4301 01:35:45.908296 DATLAT Default: 0x9
4302 01:35:45.910914 0, 0xFFFF, sum = 0
4303 01:35:45.911220 1, 0xFFFF, sum = 0
4304 01:35:45.916140 2, 0xFFFF, sum = 0
4305 01:35:45.917786 3, 0xFFFF, sum = 0
4306 01:35:45.918098 4, 0xFFFF, sum = 0
4307 01:35:45.921085 5, 0xFFFF, sum = 0
4308 01:35:45.921389 6, 0xFFFF, sum = 0
4309 01:35:45.924012 7, 0xFFFF, sum = 0
4310 01:35:45.924353 8, 0x0, sum = 1
4311 01:35:45.924605 9, 0x0, sum = 2
4312 01:35:45.927259 10, 0x0, sum = 3
4313 01:35:45.927648 11, 0x0, sum = 4
4314 01:35:45.930658 best_step = 9
4315 01:35:45.931047
4316 01:35:45.931290 ==
4317 01:35:45.934228 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 01:35:45.937344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 01:35:45.937649 ==
4320 01:35:45.941179 RX Vref Scan: 0
4321 01:35:45.941563
4322 01:35:45.941868 RX Vref 0 -> 0, step: 1
4323 01:35:45.942208
4324 01:35:45.943778 RX Delay -195 -> 252, step: 8
4325 01:35:45.952414 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4326 01:35:45.955012 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4327 01:35:45.958186 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4328 01:35:45.961492 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4329 01:35:45.968128 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4330 01:35:45.971564 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4331 01:35:45.974974 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4332 01:35:45.978548 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4333 01:35:45.981655 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4334 01:35:45.988773 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4335 01:35:45.992020 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4336 01:35:45.995897 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4337 01:35:45.999039 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4338 01:35:46.002044 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4339 01:35:46.009115 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4340 01:35:46.011937 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4341 01:35:46.012490 ==
4342 01:35:46.015516 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 01:35:46.018559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 01:35:46.019062 ==
4345 01:35:46.021941 DQS Delay:
4346 01:35:46.022400 DQS0 = 0, DQS1 = 0
4347 01:35:46.025406 DQM Delay:
4348 01:35:46.025956 DQM0 = 40, DQM1 = 33
4349 01:35:46.026323 DQ Delay:
4350 01:35:46.028820 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4351 01:35:46.033479 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4352 01:35:46.035903 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4353 01:35:46.038280 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4354 01:35:46.038837
4355 01:35:46.039291
4356 01:35:46.048689 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4357 01:35:46.052166 CH0 RK1: MR19=808, MR18=4729
4358 01:35:46.055344 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4359 01:35:46.058504 [RxdqsGatingPostProcess] freq 600
4360 01:35:46.065070 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4361 01:35:46.068436 Pre-setting of DQS Precalculation
4362 01:35:46.071716 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4363 01:35:46.072271 ==
4364 01:35:46.075705 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 01:35:46.082191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 01:35:46.082749 ==
4367 01:35:46.085024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 01:35:46.092271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4369 01:35:46.096204 [CA 0] Center 35 (5~66) winsize 62
4370 01:35:46.098766 [CA 1] Center 35 (5~66) winsize 62
4371 01:35:46.101776 [CA 2] Center 34 (4~65) winsize 62
4372 01:35:46.105854 [CA 3] Center 33 (3~64) winsize 62
4373 01:35:46.108415 [CA 4] Center 34 (3~65) winsize 63
4374 01:35:46.112293 [CA 5] Center 33 (3~64) winsize 62
4375 01:35:46.112851
4376 01:35:46.115313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4377 01:35:46.115890
4378 01:35:46.118145 [CATrainingPosCal] consider 1 rank data
4379 01:35:46.121545 u2DelayCellTimex100 = 270/100 ps
4380 01:35:46.125040 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 01:35:46.128829 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 01:35:46.135047 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 01:35:46.138927 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 01:35:46.141746 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4385 01:35:46.145489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 01:35:46.146018
4387 01:35:46.148444 CA PerBit enable=1, Macro0, CA PI delay=33
4388 01:35:46.148928
4389 01:35:46.151990 [CBTSetCACLKResult] CA Dly = 33
4390 01:35:46.152560 CS Dly: 5 (0~36)
4391 01:35:46.152930 ==
4392 01:35:46.155379 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 01:35:46.161435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 01:35:46.161909 ==
4395 01:35:46.164900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 01:35:46.171808 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4397 01:35:46.175628 [CA 0] Center 35 (5~66) winsize 62
4398 01:35:46.178576 [CA 1] Center 35 (5~66) winsize 62
4399 01:35:46.181659 [CA 2] Center 34 (3~65) winsize 63
4400 01:35:46.184883 [CA 3] Center 34 (3~65) winsize 63
4401 01:35:46.188429 [CA 4] Center 34 (4~65) winsize 62
4402 01:35:46.192065 [CA 5] Center 33 (3~64) winsize 62
4403 01:35:46.192630
4404 01:35:46.195337 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4405 01:35:46.195912
4406 01:35:46.198579 [CATrainingPosCal] consider 2 rank data
4407 01:35:46.202634 u2DelayCellTimex100 = 270/100 ps
4408 01:35:46.205171 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4409 01:35:46.209059 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4410 01:35:46.215223 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 01:35:46.218444 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 01:35:46.222035 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 01:35:46.224705 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 01:35:46.225211
4415 01:35:46.228073 CA PerBit enable=1, Macro0, CA PI delay=33
4416 01:35:46.228542
4417 01:35:46.231816 [CBTSetCACLKResult] CA Dly = 33
4418 01:35:46.232376 CS Dly: 5 (0~37)
4419 01:35:46.232753
4420 01:35:46.234974 ----->DramcWriteLeveling(PI) begin...
4421 01:35:46.238393 ==
4422 01:35:46.238974 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 01:35:46.245480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 01:35:46.246004 ==
4425 01:35:46.249156 Write leveling (Byte 0): 29 => 29
4426 01:35:46.252147 Write leveling (Byte 1): 29 => 29
4427 01:35:46.255890 DramcWriteLeveling(PI) end<-----
4428 01:35:46.256447
4429 01:35:46.256819 ==
4430 01:35:46.258705 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 01:35:46.262244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 01:35:46.262735 ==
4433 01:35:46.264721 [Gating] SW mode calibration
4434 01:35:46.272000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4435 01:35:46.275486 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4436 01:35:46.282141 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 01:35:46.285385 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 01:35:46.288434 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 01:35:46.295154 0 9 12 | B1->B0 | 3333 3333 | 1 0 | (1 0) (0 0)
4440 01:35:46.298584 0 9 16 | B1->B0 | 2d2d 2828 | 0 0 | (1 1) (0 0)
4441 01:35:46.301651 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 01:35:46.308464 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 01:35:46.311980 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 01:35:46.314800 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 01:35:46.321248 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 01:35:46.324642 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 01:35:46.328235 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4448 01:35:46.335041 0 10 16 | B1->B0 | 3838 3d3d | 1 0 | (0 0) (1 1)
4449 01:35:46.337663 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 01:35:46.341675 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 01:35:46.348251 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 01:35:46.351056 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 01:35:46.355533 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 01:35:46.361981 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 01:35:46.365286 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4456 01:35:46.367959 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 01:35:46.374957 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 01:35:46.378429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 01:35:46.381393 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 01:35:46.390173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 01:35:46.391551 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 01:35:46.394867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 01:35:46.398171 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 01:35:46.404665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 01:35:46.408306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 01:35:46.412371 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 01:35:46.418902 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 01:35:46.421744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 01:35:46.425496 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 01:35:46.432057 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 01:35:46.434852 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 01:35:46.438320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4473 01:35:46.441864 Total UI for P1: 0, mck2ui 16
4474 01:35:46.444539 best dqsien dly found for B1: ( 0, 13, 14)
4475 01:35:46.451648 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 01:35:46.452247 Total UI for P1: 0, mck2ui 16
4477 01:35:46.455048 best dqsien dly found for B0: ( 0, 13, 16)
4478 01:35:46.462031 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4479 01:35:46.464497 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4480 01:35:46.464969
4481 01:35:46.468891 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4482 01:35:46.471810 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4483 01:35:46.475009 [Gating] SW calibration Done
4484 01:35:46.475564 ==
4485 01:35:46.477993 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 01:35:46.481285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 01:35:46.481753 ==
4488 01:35:46.485240 RX Vref Scan: 0
4489 01:35:46.485792
4490 01:35:46.486167 RX Vref 0 -> 0, step: 1
4491 01:35:46.486514
4492 01:35:46.488710 RX Delay -230 -> 252, step: 16
4493 01:35:46.491987 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4494 01:35:46.498307 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4495 01:35:46.501338 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4496 01:35:46.504949 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4497 01:35:46.508674 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4498 01:35:46.515086 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4499 01:35:46.518277 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4500 01:35:46.521517 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4501 01:35:46.525160 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4502 01:35:46.528281 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4503 01:35:46.534665 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4504 01:35:46.537808 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4505 01:35:46.541356 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4506 01:35:46.544514 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4507 01:35:46.551221 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4508 01:35:46.554631 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4509 01:35:46.555207 ==
4510 01:35:46.558891 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 01:35:46.561055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 01:35:46.561527 ==
4513 01:35:46.564817 DQS Delay:
4514 01:35:46.565329 DQS0 = 0, DQS1 = 0
4515 01:35:46.565706 DQM Delay:
4516 01:35:46.567615 DQM0 = 43, DQM1 = 34
4517 01:35:46.568078 DQ Delay:
4518 01:35:46.571678 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4519 01:35:46.575169 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4520 01:35:46.578461 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4521 01:35:46.582250 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =33
4522 01:35:46.582808
4523 01:35:46.583181
4524 01:35:46.583576 ==
4525 01:35:46.584281 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 01:35:46.590931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 01:35:46.591398 ==
4528 01:35:46.591766
4529 01:35:46.592106
4530 01:35:46.592433 TX Vref Scan disable
4531 01:35:46.594299 == TX Byte 0 ==
4532 01:35:46.597931 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 01:35:46.605184 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 01:35:46.605651 == TX Byte 1 ==
4535 01:35:46.608142 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 01:35:46.611843 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 01:35:46.614494 ==
4538 01:35:46.618155 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 01:35:46.621691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 01:35:46.622202 ==
4541 01:35:46.622787
4542 01:35:46.623279
4543 01:35:46.624560 TX Vref Scan disable
4544 01:35:46.625011 == TX Byte 0 ==
4545 01:35:46.633160 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 01:35:46.635677 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 01:35:46.636193 == TX Byte 1 ==
4548 01:35:46.641698 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4549 01:35:46.645144 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4550 01:35:46.645615
4551 01:35:46.645986 [DATLAT]
4552 01:35:46.647911 Freq=600, CH1 RK0
4553 01:35:46.648471
4554 01:35:46.648846 DATLAT Default: 0x9
4555 01:35:46.651453 0, 0xFFFF, sum = 0
4556 01:35:46.652020 1, 0xFFFF, sum = 0
4557 01:35:46.654788 2, 0xFFFF, sum = 0
4558 01:35:46.655259 3, 0xFFFF, sum = 0
4559 01:35:46.657952 4, 0xFFFF, sum = 0
4560 01:35:46.661346 5, 0xFFFF, sum = 0
4561 01:35:46.661966 6, 0xFFFF, sum = 0
4562 01:35:46.665302 7, 0xFFFF, sum = 0
4563 01:35:46.665793 8, 0x0, sum = 1
4564 01:35:46.666170 9, 0x0, sum = 2
4565 01:35:46.668273 10, 0x0, sum = 3
4566 01:35:46.668746 11, 0x0, sum = 4
4567 01:35:46.671267 best_step = 9
4568 01:35:46.671728
4569 01:35:46.672097 ==
4570 01:35:46.674607 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 01:35:46.678442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 01:35:46.678980 ==
4573 01:35:46.681525 RX Vref Scan: 1
4574 01:35:46.681990
4575 01:35:46.682368 RX Vref 0 -> 0, step: 1
4576 01:35:46.682718
4577 01:35:46.685013 RX Delay -195 -> 252, step: 8
4578 01:35:46.685576
4579 01:35:46.688863 Set Vref, RX VrefLevel [Byte0]: 56
4580 01:35:46.691587 [Byte1]: 48
4581 01:35:46.695351
4582 01:35:46.695771 Final RX Vref Byte 0 = 56 to rank0
4583 01:35:46.698872 Final RX Vref Byte 1 = 48 to rank0
4584 01:35:46.701780 Final RX Vref Byte 0 = 56 to rank1
4585 01:35:46.705155 Final RX Vref Byte 1 = 48 to rank1==
4586 01:35:46.708522 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 01:35:46.715391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 01:35:46.715934 ==
4589 01:35:46.716316 DQS Delay:
4590 01:35:46.716650 DQS0 = 0, DQS1 = 0
4591 01:35:46.718797 DQM Delay:
4592 01:35:46.719395 DQM0 = 39, DQM1 = 33
4593 01:35:46.722330 DQ Delay:
4594 01:35:46.725390 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4595 01:35:46.725817 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4596 01:35:46.729503 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4597 01:35:46.735921 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4598 01:35:46.736431
4599 01:35:46.736828
4600 01:35:46.741806 [DQSOSCAuto] RK0, (LSB)MR18= 0x450c, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4601 01:35:46.745429 CH1 RK0: MR19=808, MR18=450C
4602 01:35:46.751761 CH1_RK0: MR19=0x808, MR18=0x450C, DQSOSC=396, MR23=63, INC=167, DEC=111
4603 01:35:46.752231
4604 01:35:46.755005 ----->DramcWriteLeveling(PI) begin...
4605 01:35:46.755536 ==
4606 01:35:46.758933 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 01:35:46.762613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 01:35:46.763152 ==
4609 01:35:46.765546 Write leveling (Byte 0): 32 => 32
4610 01:35:46.768580 Write leveling (Byte 1): 32 => 32
4611 01:35:46.771883 DramcWriteLeveling(PI) end<-----
4612 01:35:46.772495
4613 01:35:46.772876 ==
4614 01:35:46.775596 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 01:35:46.778644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 01:35:46.779152 ==
4617 01:35:46.782763 [Gating] SW mode calibration
4618 01:35:46.788524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4619 01:35:46.795120 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4620 01:35:46.798458 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 01:35:46.802546 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 01:35:46.808615 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
4623 01:35:46.811695 0 9 12 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (1 0)
4624 01:35:46.815357 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4625 01:35:46.821565 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 01:35:46.824772 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 01:35:46.828768 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 01:35:46.835066 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 01:35:46.839373 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4630 01:35:46.841646 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
4631 01:35:46.848286 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
4632 01:35:46.851931 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4633 01:35:46.855588 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 01:35:46.861654 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 01:35:46.865093 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 01:35:46.868422 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 01:35:46.874512 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 01:35:46.879048 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 01:35:46.881736 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4640 01:35:46.885041 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 01:35:46.891791 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 01:35:46.895151 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 01:35:46.898418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 01:35:46.904855 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 01:35:46.908237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 01:35:46.912858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 01:35:46.918096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 01:35:46.921980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 01:35:46.925180 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 01:35:46.931920 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 01:35:46.934552 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 01:35:46.938332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 01:35:46.944828 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 01:35:46.948161 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4655 01:35:46.951624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4656 01:35:46.955231 Total UI for P1: 0, mck2ui 16
4657 01:35:46.958586 best dqsien dly found for B0: ( 0, 13, 8)
4658 01:35:46.965123 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 01:35:46.965679 Total UI for P1: 0, mck2ui 16
4660 01:35:46.968220 best dqsien dly found for B1: ( 0, 13, 14)
4661 01:35:46.976073 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4662 01:35:46.977972 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4663 01:35:46.978437
4664 01:35:46.982011 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4665 01:35:46.985419 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4666 01:35:46.987921 [Gating] SW calibration Done
4667 01:35:46.988475 ==
4668 01:35:46.991042 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 01:35:46.996017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 01:35:46.996578 ==
4671 01:35:46.997924 RX Vref Scan: 0
4672 01:35:46.998391
4673 01:35:46.998757 RX Vref 0 -> 0, step: 1
4674 01:35:46.999104
4675 01:35:47.001169 RX Delay -230 -> 252, step: 16
4676 01:35:47.005125 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4677 01:35:47.011635 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4678 01:35:47.015159 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4679 01:35:47.018403 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4680 01:35:47.021190 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4681 01:35:47.028030 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4682 01:35:47.031281 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4683 01:35:47.034674 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4684 01:35:47.038048 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4685 01:35:47.041395 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4686 01:35:47.048878 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4687 01:35:47.052766 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4688 01:35:47.055116 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4689 01:35:47.057659 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4690 01:35:47.064808 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4691 01:35:47.067825 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4692 01:35:47.068297 ==
4693 01:35:47.071433 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 01:35:47.074735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 01:35:47.075310 ==
4696 01:35:47.078662 DQS Delay:
4697 01:35:47.079233 DQS0 = 0, DQS1 = 0
4698 01:35:47.079608 DQM Delay:
4699 01:35:47.081852 DQM0 = 40, DQM1 = 35
4700 01:35:47.082326 DQ Delay:
4701 01:35:47.084735 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4702 01:35:47.088364 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4703 01:35:47.093702 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4704 01:35:47.095151 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4705 01:35:47.095618
4706 01:35:47.095987
4707 01:35:47.096328 ==
4708 01:35:47.097856 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 01:35:47.101368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 01:35:47.104828 ==
4711 01:35:47.105327
4712 01:35:47.105690
4713 01:35:47.106032 TX Vref Scan disable
4714 01:35:47.108449 == TX Byte 0 ==
4715 01:35:47.112248 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4716 01:35:47.115636 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4717 01:35:47.118441 == TX Byte 1 ==
4718 01:35:47.121964 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4719 01:35:47.124821 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4720 01:35:47.128287 ==
4721 01:35:47.128855 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 01:35:47.135877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 01:35:47.136452 ==
4724 01:35:47.136833
4725 01:35:47.137229
4726 01:35:47.138365 TX Vref Scan disable
4727 01:35:47.138856 == TX Byte 0 ==
4728 01:35:47.144888 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4729 01:35:47.148328 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4730 01:35:47.148794 == TX Byte 1 ==
4731 01:35:47.155373 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4732 01:35:47.158214 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4733 01:35:47.158791
4734 01:35:47.159166 [DATLAT]
4735 01:35:47.161347 Freq=600, CH1 RK1
4736 01:35:47.161815
4737 01:35:47.162184 DATLAT Default: 0x9
4738 01:35:47.164900 0, 0xFFFF, sum = 0
4739 01:35:47.165415 1, 0xFFFF, sum = 0
4740 01:35:47.168888 2, 0xFFFF, sum = 0
4741 01:35:47.169412 3, 0xFFFF, sum = 0
4742 01:35:47.171896 4, 0xFFFF, sum = 0
4743 01:35:47.172368 5, 0xFFFF, sum = 0
4744 01:35:47.174981 6, 0xFFFF, sum = 0
4745 01:35:47.175547 7, 0xFFFF, sum = 0
4746 01:35:47.178398 8, 0x0, sum = 1
4747 01:35:47.178873 9, 0x0, sum = 2
4748 01:35:47.181530 10, 0x0, sum = 3
4749 01:35:47.182007 11, 0x0, sum = 4
4750 01:35:47.185021 best_step = 9
4751 01:35:47.185492
4752 01:35:47.185858 ==
4753 01:35:47.188189 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 01:35:47.191189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 01:35:47.191675 ==
4756 01:35:47.195027 RX Vref Scan: 0
4757 01:35:47.195582
4758 01:35:47.195955 RX Vref 0 -> 0, step: 1
4759 01:35:47.196317
4760 01:35:47.199412 RX Delay -195 -> 252, step: 8
4761 01:35:47.205822 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4762 01:35:47.208087 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4763 01:35:47.211781 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4764 01:35:47.215239 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4765 01:35:47.221867 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4766 01:35:47.225039 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4767 01:35:47.228612 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4768 01:35:47.231916 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4769 01:35:47.236511 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4770 01:35:47.241769 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4771 01:35:47.245042 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4772 01:35:47.249887 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4773 01:35:47.252096 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4774 01:35:47.258588 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4775 01:35:47.261833 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4776 01:35:47.265558 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4777 01:35:47.266125 ==
4778 01:35:47.268298 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 01:35:47.271722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 01:35:47.275357 ==
4781 01:35:47.275915 DQS Delay:
4782 01:35:47.276287 DQS0 = 0, DQS1 = 0
4783 01:35:47.278089 DQM Delay:
4784 01:35:47.278554 DQM0 = 38, DQM1 = 33
4785 01:35:47.278926 DQ Delay:
4786 01:35:47.281821 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4787 01:35:47.284689 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4788 01:35:47.288526 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4789 01:35:47.292024 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4790 01:35:47.292491
4791 01:35:47.292860
4792 01:35:47.301328 [DQSOSCAuto] RK1, (LSB)MR18= 0x3544, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4793 01:35:47.306388 CH1 RK1: MR19=808, MR18=3544
4794 01:35:47.311663 CH1_RK1: MR19=0x808, MR18=0x3544, DQSOSC=396, MR23=63, INC=167, DEC=111
4795 01:35:47.312220 [RxdqsGatingPostProcess] freq 600
4796 01:35:47.318340 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4797 01:35:47.321862 Pre-setting of DQS Precalculation
4798 01:35:47.325240 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4799 01:35:47.334846 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4800 01:35:47.341731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4801 01:35:47.342204
4802 01:35:47.342577
4803 01:35:47.344669 [Calibration Summary] 1200 Mbps
4804 01:35:47.345271 CH 0, Rank 0
4805 01:35:47.348456 SW Impedance : PASS
4806 01:35:47.349062 DUTY Scan : NO K
4807 01:35:47.351769 ZQ Calibration : PASS
4808 01:35:47.355255 Jitter Meter : NO K
4809 01:35:47.355813 CBT Training : PASS
4810 01:35:47.359421 Write leveling : PASS
4811 01:35:47.362238 RX DQS gating : PASS
4812 01:35:47.362797 RX DQ/DQS(RDDQC) : PASS
4813 01:35:47.365092 TX DQ/DQS : PASS
4814 01:35:47.369286 RX DATLAT : PASS
4815 01:35:47.370108 RX DQ/DQS(Engine): PASS
4816 01:35:47.371531 TX OE : NO K
4817 01:35:47.371999 All Pass.
4818 01:35:47.372366
4819 01:35:47.374967 CH 0, Rank 1
4820 01:35:47.375525 SW Impedance : PASS
4821 01:35:47.378712 DUTY Scan : NO K
4822 01:35:47.379270 ZQ Calibration : PASS
4823 01:35:47.381498 Jitter Meter : NO K
4824 01:35:47.385414 CBT Training : PASS
4825 01:35:47.385881 Write leveling : PASS
4826 01:35:47.388376 RX DQS gating : PASS
4827 01:35:47.392179 RX DQ/DQS(RDDQC) : PASS
4828 01:35:47.392647 TX DQ/DQS : PASS
4829 01:35:47.395877 RX DATLAT : PASS
4830 01:35:47.399780 RX DQ/DQS(Engine): PASS
4831 01:35:47.400340 TX OE : NO K
4832 01:35:47.402106 All Pass.
4833 01:35:47.402668
4834 01:35:47.403038 CH 1, Rank 0
4835 01:35:47.405450 SW Impedance : PASS
4836 01:35:47.406007 DUTY Scan : NO K
4837 01:35:47.408531 ZQ Calibration : PASS
4838 01:35:47.411882 Jitter Meter : NO K
4839 01:35:47.412440 CBT Training : PASS
4840 01:35:47.415381 Write leveling : PASS
4841 01:35:47.415938 RX DQS gating : PASS
4842 01:35:47.418799 RX DQ/DQS(RDDQC) : PASS
4843 01:35:47.421889 TX DQ/DQS : PASS
4844 01:35:47.422359 RX DATLAT : PASS
4845 01:35:47.425533 RX DQ/DQS(Engine): PASS
4846 01:35:47.428418 TX OE : NO K
4847 01:35:47.428882 All Pass.
4848 01:35:47.429290
4849 01:35:47.429633 CH 1, Rank 1
4850 01:35:47.432001 SW Impedance : PASS
4851 01:35:47.436377 DUTY Scan : NO K
4852 01:35:47.436937 ZQ Calibration : PASS
4853 01:35:47.438781 Jitter Meter : NO K
4854 01:35:47.441714 CBT Training : PASS
4855 01:35:47.442181 Write leveling : PASS
4856 01:35:47.445543 RX DQS gating : PASS
4857 01:35:47.448950 RX DQ/DQS(RDDQC) : PASS
4858 01:35:47.449551 TX DQ/DQS : PASS
4859 01:35:47.452176 RX DATLAT : PASS
4860 01:35:47.452732 RX DQ/DQS(Engine): PASS
4861 01:35:47.455549 TX OE : NO K
4862 01:35:47.456107 All Pass.
4863 01:35:47.456481
4864 01:35:47.458831 DramC Write-DBI off
4865 01:35:47.463498 PER_BANK_REFRESH: Hybrid Mode
4866 01:35:47.464065 TX_TRACKING: ON
4867 01:35:47.471715 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4868 01:35:47.476054 [FAST_K] Save calibration result to emmc
4869 01:35:47.479014 dramc_set_vcore_voltage set vcore to 662500
4870 01:35:47.481949 Read voltage for 933, 3
4871 01:35:47.482477 Vio18 = 0
4872 01:35:47.482849 Vcore = 662500
4873 01:35:47.485867 Vdram = 0
4874 01:35:47.486466 Vddq = 0
4875 01:35:47.486848 Vmddr = 0
4876 01:35:47.492973 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4877 01:35:47.495211 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4878 01:35:47.498373 MEM_TYPE=3, freq_sel=17
4879 01:35:47.502484 sv_algorithm_assistance_LP4_1600
4880 01:35:47.505380 ============ PULL DRAM RESETB DOWN ============
4881 01:35:47.509129 ========== PULL DRAM RESETB DOWN end =========
4882 01:35:47.515459 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4883 01:35:47.518858 ===================================
4884 01:35:47.521903 LPDDR4 DRAM CONFIGURATION
4885 01:35:47.525701 ===================================
4886 01:35:47.526263 EX_ROW_EN[0] = 0x0
4887 01:35:47.528548 EX_ROW_EN[1] = 0x0
4888 01:35:47.529039 LP4Y_EN = 0x0
4889 01:35:47.532510 WORK_FSP = 0x0
4890 01:35:47.533113 WL = 0x3
4891 01:35:47.535394 RL = 0x3
4892 01:35:47.535951 BL = 0x2
4893 01:35:47.538520 RPST = 0x0
4894 01:35:47.538987 RD_PRE = 0x0
4895 01:35:47.542668 WR_PRE = 0x1
4896 01:35:47.543223 WR_PST = 0x0
4897 01:35:47.545419 DBI_WR = 0x0
4898 01:35:47.545883 DBI_RD = 0x0
4899 01:35:47.548614 OTF = 0x1
4900 01:35:47.552674 ===================================
4901 01:35:47.555404 ===================================
4902 01:35:47.555869 ANA top config
4903 01:35:47.558901 ===================================
4904 01:35:47.562190 DLL_ASYNC_EN = 0
4905 01:35:47.565342 ALL_SLAVE_EN = 1
4906 01:35:47.569689 NEW_RANK_MODE = 1
4907 01:35:47.570255 DLL_IDLE_MODE = 1
4908 01:35:47.572073 LP45_APHY_COMB_EN = 1
4909 01:35:47.575883 TX_ODT_DIS = 1
4910 01:35:47.579612 NEW_8X_MODE = 1
4911 01:35:47.582169 ===================================
4912 01:35:47.585506 ===================================
4913 01:35:47.588883 data_rate = 1866
4914 01:35:47.589476 CKR = 1
4915 01:35:47.591864 DQ_P2S_RATIO = 8
4916 01:35:47.595618 ===================================
4917 01:35:47.598196 CA_P2S_RATIO = 8
4918 01:35:47.601528 DQ_CA_OPEN = 0
4919 01:35:47.606474 DQ_SEMI_OPEN = 0
4920 01:35:47.608874 CA_SEMI_OPEN = 0
4921 01:35:47.609466 CA_FULL_RATE = 0
4922 01:35:47.612223 DQ_CKDIV4_EN = 1
4923 01:35:47.615001 CA_CKDIV4_EN = 1
4924 01:35:47.618475 CA_PREDIV_EN = 0
4925 01:35:47.621613 PH8_DLY = 0
4926 01:35:47.625731 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4927 01:35:47.626293 DQ_AAMCK_DIV = 4
4928 01:35:47.629347 CA_AAMCK_DIV = 4
4929 01:35:47.632517 CA_ADMCK_DIV = 4
4930 01:35:47.634989 DQ_TRACK_CA_EN = 0
4931 01:35:47.638741 CA_PICK = 933
4932 01:35:47.642172 CA_MCKIO = 933
4933 01:35:47.642732 MCKIO_SEMI = 0
4934 01:35:47.645108 PLL_FREQ = 3732
4935 01:35:47.648184 DQ_UI_PI_RATIO = 32
4936 01:35:47.652013 CA_UI_PI_RATIO = 0
4937 01:35:47.655525 ===================================
4938 01:35:47.659120 ===================================
4939 01:35:47.662408 memory_type:LPDDR4
4940 01:35:47.662963 GP_NUM : 10
4941 01:35:47.665631 SRAM_EN : 1
4942 01:35:47.668105 MD32_EN : 0
4943 01:35:47.671908 ===================================
4944 01:35:47.672398 [ANA_INIT] >>>>>>>>>>>>>>
4945 01:35:47.675618 <<<<<< [CONFIGURE PHASE]: ANA_TX
4946 01:35:47.679904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4947 01:35:47.683025 ===================================
4948 01:35:47.684950 data_rate = 1866,PCW = 0X8f00
4949 01:35:47.688856 ===================================
4950 01:35:47.692269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4951 01:35:47.698504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 01:35:47.701550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 01:35:47.709371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4954 01:35:47.711462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4955 01:35:47.715140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4956 01:35:47.715703 [ANA_INIT] flow start
4957 01:35:47.718452 [ANA_INIT] PLL >>>>>>>>
4958 01:35:47.721858 [ANA_INIT] PLL <<<<<<<<
4959 01:35:47.722416 [ANA_INIT] MIDPI >>>>>>>>
4960 01:35:47.724490 [ANA_INIT] MIDPI <<<<<<<<
4961 01:35:47.728005 [ANA_INIT] DLL >>>>>>>>
4962 01:35:47.728755 [ANA_INIT] flow end
4963 01:35:47.734390 ============ LP4 DIFF to SE enter ============
4964 01:35:47.737751 ============ LP4 DIFF to SE exit ============
4965 01:35:47.741266 [ANA_INIT] <<<<<<<<<<<<<
4966 01:35:47.744897 [Flow] Enable top DCM control >>>>>
4967 01:35:47.748761 [Flow] Enable top DCM control <<<<<
4968 01:35:47.751130 Enable DLL master slave shuffle
4969 01:35:47.754888 ==============================================================
4970 01:35:47.758213 Gating Mode config
4971 01:35:47.761459 ==============================================================
4972 01:35:47.764634 Config description:
4973 01:35:47.774796 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4974 01:35:47.781436 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4975 01:35:47.785598 SELPH_MODE 0: By rank 1: By Phase
4976 01:35:47.791214 ==============================================================
4977 01:35:47.794441 GAT_TRACK_EN = 1
4978 01:35:47.797659 RX_GATING_MODE = 2
4979 01:35:47.801464 RX_GATING_TRACK_MODE = 2
4980 01:35:47.804706 SELPH_MODE = 1
4981 01:35:47.805306 PICG_EARLY_EN = 1
4982 01:35:47.807775 VALID_LAT_VALUE = 1
4983 01:35:47.814671 ==============================================================
4984 01:35:47.818524 Enter into Gating configuration >>>>
4985 01:35:47.821603 Exit from Gating configuration <<<<
4986 01:35:47.824448 Enter into DVFS_PRE_config >>>>>
4987 01:35:47.834857 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4988 01:35:47.838763 Exit from DVFS_PRE_config <<<<<
4989 01:35:47.841004 Enter into PICG configuration >>>>
4990 01:35:47.844460 Exit from PICG configuration <<<<
4991 01:35:47.847920 [RX_INPUT] configuration >>>>>
4992 01:35:47.851298 [RX_INPUT] configuration <<<<<
4993 01:35:47.854229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4994 01:35:47.861006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4995 01:35:47.868211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 01:35:47.874764 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 01:35:47.877866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 01:35:47.884619 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 01:35:47.888391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5000 01:35:47.895044 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5001 01:35:47.898264 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5002 01:35:47.901765 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5003 01:35:47.904566 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5004 01:35:47.911566 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 01:35:47.914672 ===================================
5006 01:35:47.915090 LPDDR4 DRAM CONFIGURATION
5007 01:35:47.918422 ===================================
5008 01:35:47.921648 EX_ROW_EN[0] = 0x0
5009 01:35:47.924564 EX_ROW_EN[1] = 0x0
5010 01:35:47.925075 LP4Y_EN = 0x0
5011 01:35:47.928833 WORK_FSP = 0x0
5012 01:35:47.929505 WL = 0x3
5013 01:35:47.932506 RL = 0x3
5014 01:35:47.933072 BL = 0x2
5015 01:35:47.935378 RPST = 0x0
5016 01:35:47.935915 RD_PRE = 0x0
5017 01:35:47.938413 WR_PRE = 0x1
5018 01:35:47.938829 WR_PST = 0x0
5019 01:35:47.941106 DBI_WR = 0x0
5020 01:35:47.941528 DBI_RD = 0x0
5021 01:35:47.944760 OTF = 0x1
5022 01:35:47.948586 ===================================
5023 01:35:47.952168 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5024 01:35:47.955054 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5025 01:35:47.961954 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 01:35:47.964511 ===================================
5027 01:35:47.965010 LPDDR4 DRAM CONFIGURATION
5028 01:35:47.967780 ===================================
5029 01:35:47.971184 EX_ROW_EN[0] = 0x10
5030 01:35:47.974356 EX_ROW_EN[1] = 0x0
5031 01:35:47.975089 LP4Y_EN = 0x0
5032 01:35:47.978373 WORK_FSP = 0x0
5033 01:35:47.978926 WL = 0x3
5034 01:35:47.981396 RL = 0x3
5035 01:35:47.981862 BL = 0x2
5036 01:35:47.984900 RPST = 0x0
5037 01:35:47.985518 RD_PRE = 0x0
5038 01:35:47.988443 WR_PRE = 0x1
5039 01:35:47.989046 WR_PST = 0x0
5040 01:35:47.991359 DBI_WR = 0x0
5041 01:35:47.991841 DBI_RD = 0x0
5042 01:35:47.994496 OTF = 0x1
5043 01:35:47.998936 ===================================
5044 01:35:48.004593 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5045 01:35:48.008060 nWR fixed to 30
5046 01:35:48.008640 [ModeRegInit_LP4] CH0 RK0
5047 01:35:48.011880 [ModeRegInit_LP4] CH0 RK1
5048 01:35:48.014728 [ModeRegInit_LP4] CH1 RK0
5049 01:35:48.015286 [ModeRegInit_LP4] CH1 RK1
5050 01:35:48.018129 match AC timing 9
5051 01:35:48.021058 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5052 01:35:48.024615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5053 01:35:48.032659 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5054 01:35:48.034774 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5055 01:35:48.041029 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5056 01:35:48.041504 ==
5057 01:35:48.044946 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 01:35:48.049154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 01:35:48.049624 ==
5060 01:35:48.055316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 01:35:48.057903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5062 01:35:48.062578 [CA 0] Center 38 (8~69) winsize 62
5063 01:35:48.066450 [CA 1] Center 37 (7~68) winsize 62
5064 01:35:48.069353 [CA 2] Center 35 (5~66) winsize 62
5065 01:35:48.072425 [CA 3] Center 35 (5~66) winsize 62
5066 01:35:48.075276 [CA 4] Center 34 (4~64) winsize 61
5067 01:35:48.078883 [CA 5] Center 34 (4~64) winsize 61
5068 01:35:48.079445
5069 01:35:48.082219 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5070 01:35:48.082800
5071 01:35:48.086272 [CATrainingPosCal] consider 1 rank data
5072 01:35:48.088809 u2DelayCellTimex100 = 270/100 ps
5073 01:35:48.092286 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5074 01:35:48.095869 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5075 01:35:48.101858 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5076 01:35:48.105538 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5077 01:35:48.109229 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5078 01:35:48.112399 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5079 01:35:48.112867
5080 01:35:48.115599 CA PerBit enable=1, Macro0, CA PI delay=34
5081 01:35:48.116153
5082 01:35:48.119093 [CBTSetCACLKResult] CA Dly = 34
5083 01:35:48.119652 CS Dly: 6 (0~37)
5084 01:35:48.122226 ==
5085 01:35:48.122804 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 01:35:48.128490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 01:35:48.129097 ==
5088 01:35:48.131846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 01:35:48.139105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5090 01:35:48.143491 [CA 0] Center 38 (8~69) winsize 62
5091 01:35:48.145203 [CA 1] Center 38 (7~69) winsize 63
5092 01:35:48.149164 [CA 2] Center 35 (5~66) winsize 62
5093 01:35:48.151881 [CA 3] Center 35 (5~66) winsize 62
5094 01:35:48.155085 [CA 4] Center 34 (4~64) winsize 61
5095 01:35:48.158883 [CA 5] Center 33 (3~64) winsize 62
5096 01:35:48.159446
5097 01:35:48.163110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5098 01:35:48.163666
5099 01:35:48.166164 [CATrainingPosCal] consider 2 rank data
5100 01:35:48.168749 u2DelayCellTimex100 = 270/100 ps
5101 01:35:48.171805 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5102 01:35:48.178724 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5103 01:35:48.182634 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5104 01:35:48.185102 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5105 01:35:48.188430 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5106 01:35:48.191667 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5107 01:35:48.192230
5108 01:35:48.196026 CA PerBit enable=1, Macro0, CA PI delay=34
5109 01:35:48.196584
5110 01:35:48.198570 [CBTSetCACLKResult] CA Dly = 34
5111 01:35:48.199126 CS Dly: 7 (0~40)
5112 01:35:48.199555
5113 01:35:48.201770 ----->DramcWriteLeveling(PI) begin...
5114 01:35:48.204953 ==
5115 01:35:48.208522 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 01:35:48.212268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 01:35:48.212826 ==
5118 01:35:48.216448 Write leveling (Byte 0): 31 => 31
5119 01:35:48.219520 Write leveling (Byte 1): 29 => 29
5120 01:35:48.222695 DramcWriteLeveling(PI) end<-----
5121 01:35:48.223163
5122 01:35:48.223529 ==
5123 01:35:48.225272 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 01:35:48.228944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 01:35:48.229540 ==
5126 01:35:48.231778 [Gating] SW mode calibration
5127 01:35:48.239253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5128 01:35:48.242456 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5129 01:35:48.249052 0 14 0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
5130 01:35:48.252608 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5131 01:35:48.256567 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 01:35:48.262438 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 01:35:48.267141 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 01:35:48.268597 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 01:35:48.275288 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 01:35:48.279287 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
5137 01:35:48.282893 0 15 0 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)
5138 01:35:48.289680 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5139 01:35:48.292152 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 01:35:48.295526 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 01:35:48.302313 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 01:35:48.305578 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 01:35:48.308871 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 01:35:48.316044 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5145 01:35:48.319293 1 0 0 | B1->B0 | 2d2d 3b3b | 0 1 | (1 1) (0 0)
5146 01:35:48.322407 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5147 01:35:48.325513 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 01:35:48.332593 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 01:35:48.336483 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 01:35:48.339617 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 01:35:48.345473 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 01:35:48.348691 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 01:35:48.351919 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5154 01:35:48.359152 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5155 01:35:48.362445 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 01:35:48.366336 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 01:35:48.372745 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 01:35:48.375994 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 01:35:48.379385 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 01:35:48.385932 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 01:35:48.389098 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 01:35:48.392419 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 01:35:48.399225 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 01:35:48.402413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 01:35:48.407187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 01:35:48.412341 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 01:35:48.416487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 01:35:48.418686 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 01:35:48.423018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 01:35:48.429031 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 01:35:48.431907 Total UI for P1: 0, mck2ui 16
5172 01:35:48.435616 best dqsien dly found for B0: ( 1, 3, 2)
5173 01:35:48.438951 Total UI for P1: 0, mck2ui 16
5174 01:35:48.441923 best dqsien dly found for B1: ( 1, 3, 2)
5175 01:35:48.446072 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5176 01:35:48.448959 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5177 01:35:48.449499
5178 01:35:48.452132 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5179 01:35:48.455494 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5180 01:35:48.458759 [Gating] SW calibration Done
5181 01:35:48.459321 ==
5182 01:35:48.462136 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 01:35:48.465379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 01:35:48.465946 ==
5185 01:35:48.468925 RX Vref Scan: 0
5186 01:35:48.469533
5187 01:35:48.469957 RX Vref 0 -> 0, step: 1
5188 01:35:48.470342
5189 01:35:48.471759 RX Delay -80 -> 252, step: 8
5190 01:35:48.475315 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5191 01:35:48.482201 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5192 01:35:48.485462 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5193 01:35:48.488955 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5194 01:35:48.492400 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5195 01:35:48.495587 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5196 01:35:48.499090 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5197 01:35:48.505715 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5198 01:35:48.508828 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5199 01:35:48.512058 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5200 01:35:48.515469 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5201 01:35:48.520001 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5202 01:35:48.525760 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5203 01:35:48.528750 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5204 01:35:48.532827 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5205 01:35:48.536115 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5206 01:35:48.536670 ==
5207 01:35:48.539717 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 01:35:48.542420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 01:35:48.542889 ==
5210 01:35:48.545596 DQS Delay:
5211 01:35:48.546060 DQS0 = 0, DQS1 = 0
5212 01:35:48.548560 DQM Delay:
5213 01:35:48.549206 DQM0 = 98, DQM1 = 86
5214 01:35:48.549597 DQ Delay:
5215 01:35:48.551889 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5216 01:35:48.555524 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5217 01:35:48.559281 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5218 01:35:48.562211 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5219 01:35:48.562772
5220 01:35:48.566419
5221 01:35:48.566974 ==
5222 01:35:48.568904 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 01:35:48.572781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 01:35:48.573445 ==
5225 01:35:48.573828
5226 01:35:48.574173
5227 01:35:48.575187 TX Vref Scan disable
5228 01:35:48.575652 == TX Byte 0 ==
5229 01:35:48.582047 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5230 01:35:48.585064 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5231 01:35:48.585533 == TX Byte 1 ==
5232 01:35:48.588748 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5233 01:35:48.595100 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5234 01:35:48.595743 ==
5235 01:35:48.598438 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 01:35:48.602771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 01:35:48.603328 ==
5238 01:35:48.603705
5239 01:35:48.604046
5240 01:35:48.605147 TX Vref Scan disable
5241 01:35:48.608908 == TX Byte 0 ==
5242 01:35:48.612499 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5243 01:35:48.615539 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5244 01:35:48.618910 == TX Byte 1 ==
5245 01:35:48.621764 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5246 01:35:48.625529 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5247 01:35:48.625996
5248 01:35:48.626365 [DATLAT]
5249 01:35:48.629069 Freq=933, CH0 RK0
5250 01:35:48.629625
5251 01:35:48.632046 DATLAT Default: 0xd
5252 01:35:48.632509 0, 0xFFFF, sum = 0
5253 01:35:48.636340 1, 0xFFFF, sum = 0
5254 01:35:48.636895 2, 0xFFFF, sum = 0
5255 01:35:48.638795 3, 0xFFFF, sum = 0
5256 01:35:48.639353 4, 0xFFFF, sum = 0
5257 01:35:48.642416 5, 0xFFFF, sum = 0
5258 01:35:48.642890 6, 0xFFFF, sum = 0
5259 01:35:48.646368 7, 0xFFFF, sum = 0
5260 01:35:48.646843 8, 0xFFFF, sum = 0
5261 01:35:48.648472 9, 0xFFFF, sum = 0
5262 01:35:48.648943 10, 0x0, sum = 1
5263 01:35:48.652102 11, 0x0, sum = 2
5264 01:35:48.652575 12, 0x0, sum = 3
5265 01:35:48.655795 13, 0x0, sum = 4
5266 01:35:48.656358 best_step = 11
5267 01:35:48.656728
5268 01:35:48.657107 ==
5269 01:35:48.659099 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 01:35:48.661775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 01:35:48.662340 ==
5272 01:35:48.665286 RX Vref Scan: 1
5273 01:35:48.665751
5274 01:35:48.668139 RX Vref 0 -> 0, step: 1
5275 01:35:48.668602
5276 01:35:48.668972 RX Delay -69 -> 252, step: 4
5277 01:35:48.671824
5278 01:35:48.672285 Set Vref, RX VrefLevel [Byte0]: 52
5279 01:35:48.675056 [Byte1]: 52
5280 01:35:48.680818
5281 01:35:48.681406 Final RX Vref Byte 0 = 52 to rank0
5282 01:35:48.683498 Final RX Vref Byte 1 = 52 to rank0
5283 01:35:48.687318 Final RX Vref Byte 0 = 52 to rank1
5284 01:35:48.691034 Final RX Vref Byte 1 = 52 to rank1==
5285 01:35:48.694007 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 01:35:48.697201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 01:35:48.700904 ==
5288 01:35:48.701522 DQS Delay:
5289 01:35:48.701906 DQS0 = 0, DQS1 = 0
5290 01:35:48.704077 DQM Delay:
5291 01:35:48.704540 DQM0 = 97, DQM1 = 88
5292 01:35:48.707003 DQ Delay:
5293 01:35:48.710500 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5294 01:35:48.713344 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5295 01:35:48.716674 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =80
5296 01:35:48.719977 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5297 01:35:48.720462
5298 01:35:48.720822
5299 01:35:48.726843 [DQSOSCAuto] RK0, (LSB)MR18= 0x1500, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5300 01:35:48.730319 CH0 RK0: MR19=505, MR18=1500
5301 01:35:48.737067 CH0_RK0: MR19=0x505, MR18=0x1500, DQSOSC=415, MR23=63, INC=62, DEC=41
5302 01:35:48.737476
5303 01:35:48.740372 ----->DramcWriteLeveling(PI) begin...
5304 01:35:48.740780 ==
5305 01:35:48.743958 Dram Type= 6, Freq= 0, CH_0, rank 1
5306 01:35:48.747405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 01:35:48.747702 ==
5308 01:35:48.750107 Write leveling (Byte 0): 32 => 32
5309 01:35:48.754151 Write leveling (Byte 1): 32 => 32
5310 01:35:48.757743 DramcWriteLeveling(PI) end<-----
5311 01:35:48.758133
5312 01:35:48.758371 ==
5313 01:35:48.761448 Dram Type= 6, Freq= 0, CH_0, rank 1
5314 01:35:48.764848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 01:35:48.765372 ==
5316 01:35:48.767645 [Gating] SW mode calibration
5317 01:35:48.773673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5318 01:35:48.780286 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5319 01:35:48.784255 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5320 01:35:48.787216 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5321 01:35:48.793639 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 01:35:48.797094 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 01:35:48.800695 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 01:35:48.808898 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 01:35:48.811496 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5326 01:35:48.814643 0 14 28 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 0)
5327 01:35:48.821547 0 15 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
5328 01:35:48.823498 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 01:35:48.827392 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 01:35:48.833790 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 01:35:48.837379 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 01:35:48.840107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 01:35:48.843302 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5334 01:35:48.850552 0 15 28 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
5335 01:35:48.853908 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5336 01:35:48.857164 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 01:35:48.864653 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 01:35:48.866952 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 01:35:48.870593 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 01:35:48.877614 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 01:35:48.880622 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 01:35:48.883992 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5343 01:35:48.891085 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 01:35:48.893773 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5345 01:35:48.897120 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 01:35:48.903466 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 01:35:48.907028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 01:35:48.910328 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 01:35:48.917301 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 01:35:48.920135 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 01:35:48.924223 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 01:35:48.930398 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 01:35:48.934120 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 01:35:48.937237 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 01:35:48.940523 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 01:35:48.946626 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 01:35:48.950573 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5358 01:35:48.953992 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5359 01:35:48.957703 Total UI for P1: 0, mck2ui 16
5360 01:35:48.960339 best dqsien dly found for B0: ( 1, 2, 24)
5361 01:35:48.967482 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5362 01:35:48.970357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5363 01:35:48.973783 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 01:35:48.977521 Total UI for P1: 0, mck2ui 16
5365 01:35:48.980715 best dqsien dly found for B1: ( 1, 3, 4)
5366 01:35:48.983885 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5367 01:35:48.986932 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5368 01:35:48.987390
5369 01:35:48.993391 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5370 01:35:48.997237 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5371 01:35:48.997707 [Gating] SW calibration Done
5372 01:35:49.000300 ==
5373 01:35:49.003889 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 01:35:49.007116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 01:35:49.007578 ==
5376 01:35:49.007943 RX Vref Scan: 0
5377 01:35:49.008280
5378 01:35:49.010143 RX Vref 0 -> 0, step: 1
5379 01:35:49.010599
5380 01:35:49.013869 RX Delay -80 -> 252, step: 8
5381 01:35:49.017458 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5382 01:35:49.020216 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5383 01:35:49.023401 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5384 01:35:49.031354 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5385 01:35:49.034032 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5386 01:35:49.036881 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5387 01:35:49.040197 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5388 01:35:49.043411 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5389 01:35:49.047447 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5390 01:35:49.053534 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5391 01:35:49.056724 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5392 01:35:49.059870 iDelay=208, Bit 11, Center 79 (-8 ~ 167) 176
5393 01:35:49.063534 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5394 01:35:49.067242 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5395 01:35:49.070000 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5396 01:35:49.076778 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5397 01:35:49.077320 ==
5398 01:35:49.079782 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 01:35:49.083483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 01:35:49.083921 ==
5401 01:35:49.084572 DQS Delay:
5402 01:35:49.086677 DQS0 = 0, DQS1 = 0
5403 01:35:49.087138 DQM Delay:
5404 01:35:49.091225 DQM0 = 96, DQM1 = 86
5405 01:35:49.091657 DQ Delay:
5406 01:35:49.093548 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5407 01:35:49.096924 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =103
5408 01:35:49.099778 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5409 01:35:49.104716 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5410 01:35:49.105282
5411 01:35:49.105725
5412 01:35:49.106132 ==
5413 01:35:49.106912 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 01:35:49.110913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 01:35:49.111344 ==
5416 01:35:49.113706
5417 01:35:49.114131
5418 01:35:49.114558 TX Vref Scan disable
5419 01:35:49.116765 == TX Byte 0 ==
5420 01:35:49.120331 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5421 01:35:49.123565 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5422 01:35:49.127846 == TX Byte 1 ==
5423 01:35:49.130189 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5424 01:35:49.133565 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5425 01:35:49.134202 ==
5426 01:35:49.136904 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 01:35:49.143867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 01:35:49.144498 ==
5429 01:35:49.145129
5430 01:35:49.145498
5431 01:35:49.145914 TX Vref Scan disable
5432 01:35:49.147899 == TX Byte 0 ==
5433 01:35:49.150947 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5434 01:35:49.157537 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5435 01:35:49.157962 == TX Byte 1 ==
5436 01:35:49.160919 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5437 01:35:49.167368 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5438 01:35:49.167790
5439 01:35:49.168123 [DATLAT]
5440 01:35:49.168437 Freq=933, CH0 RK1
5441 01:35:49.168741
5442 01:35:49.171200 DATLAT Default: 0xb
5443 01:35:49.171621 0, 0xFFFF, sum = 0
5444 01:35:49.174360 1, 0xFFFF, sum = 0
5445 01:35:49.174791 2, 0xFFFF, sum = 0
5446 01:35:49.177300 3, 0xFFFF, sum = 0
5447 01:35:49.180401 4, 0xFFFF, sum = 0
5448 01:35:49.180827 5, 0xFFFF, sum = 0
5449 01:35:49.184309 6, 0xFFFF, sum = 0
5450 01:35:49.184740 7, 0xFFFF, sum = 0
5451 01:35:49.187686 8, 0xFFFF, sum = 0
5452 01:35:49.188144 9, 0xFFFF, sum = 0
5453 01:35:49.190373 10, 0x0, sum = 1
5454 01:35:49.190800 11, 0x0, sum = 2
5455 01:35:49.193944 12, 0x0, sum = 3
5456 01:35:49.194383 13, 0x0, sum = 4
5457 01:35:49.194730 best_step = 11
5458 01:35:49.195040
5459 01:35:49.197324 ==
5460 01:35:49.200520 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 01:35:49.204607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 01:35:49.205092 ==
5463 01:35:49.205526 RX Vref Scan: 0
5464 01:35:49.205936
5465 01:35:49.207384 RX Vref 0 -> 0, step: 1
5466 01:35:49.207815
5467 01:35:49.210915 RX Delay -61 -> 252, step: 4
5468 01:35:49.214322 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5469 01:35:49.221607 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5470 01:35:49.223827 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5471 01:35:49.227488 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5472 01:35:49.230365 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5473 01:35:49.234163 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5474 01:35:49.237425 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5475 01:35:49.243878 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5476 01:35:49.247260 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5477 01:35:49.250343 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5478 01:35:49.253969 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5479 01:35:49.257546 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5480 01:35:49.261193 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5481 01:35:49.267308 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5482 01:35:49.271609 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5483 01:35:49.274024 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5484 01:35:49.274445 ==
5485 01:35:49.277001 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 01:35:49.280896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 01:35:49.281527 ==
5488 01:35:49.285098 DQS Delay:
5489 01:35:49.285524 DQS0 = 0, DQS1 = 0
5490 01:35:49.285857 DQM Delay:
5491 01:35:49.287322 DQM0 = 95, DQM1 = 87
5492 01:35:49.287743 DQ Delay:
5493 01:35:49.290723 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5494 01:35:49.293875 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5495 01:35:49.297577 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5496 01:35:49.300952 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5497 01:35:49.301561
5498 01:35:49.301925
5499 01:35:49.310837 [DQSOSCAuto] RK1, (LSB)MR18= 0x1603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5500 01:35:49.311314 CH0 RK1: MR19=505, MR18=1603
5501 01:35:49.317909 CH0_RK1: MR19=0x505, MR18=0x1603, DQSOSC=414, MR23=63, INC=63, DEC=42
5502 01:35:49.321028 [RxdqsGatingPostProcess] freq 933
5503 01:35:49.327984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 01:35:49.330834 best DQS0 dly(2T, 0.5T) = (0, 11)
5505 01:35:49.334841 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 01:35:49.337307 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5507 01:35:49.341143 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 01:35:49.344954 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 01:35:49.345455 best DQS1 dly(2T, 0.5T) = (0, 11)
5510 01:35:49.347837 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 01:35:49.351077 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5512 01:35:49.354640 Pre-setting of DQS Precalculation
5513 01:35:49.360851 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 01:35:49.361480 ==
5515 01:35:49.364219 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 01:35:49.367612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 01:35:49.368324 ==
5518 01:35:49.373928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 01:35:49.380712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 01:35:49.384014 [CA 0] Center 36 (6~67) winsize 62
5521 01:35:49.388475 [CA 1] Center 36 (6~67) winsize 62
5522 01:35:49.390988 [CA 2] Center 34 (4~64) winsize 61
5523 01:35:49.393973 [CA 3] Center 33 (3~64) winsize 62
5524 01:35:49.397753 [CA 4] Center 34 (4~64) winsize 61
5525 01:35:49.398167 [CA 5] Center 33 (3~64) winsize 62
5526 01:35:49.400915
5527 01:35:49.405339 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 01:35:49.405851
5529 01:35:49.407503 [CATrainingPosCal] consider 1 rank data
5530 01:35:49.411054 u2DelayCellTimex100 = 270/100 ps
5531 01:35:49.414681 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 01:35:49.417964 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 01:35:49.421050 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 01:35:49.424219 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 01:35:49.427361 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5536 01:35:49.431130 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 01:35:49.431669
5538 01:35:49.434143 CA PerBit enable=1, Macro0, CA PI delay=33
5539 01:35:49.434653
5540 01:35:49.437747 [CBTSetCACLKResult] CA Dly = 33
5541 01:35:49.441793 CS Dly: 4 (0~35)
5542 01:35:49.442207 ==
5543 01:35:49.444949 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 01:35:49.447511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 01:35:49.447928 ==
5546 01:35:49.454488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 01:35:49.461488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5548 01:35:49.464010 [CA 0] Center 36 (6~67) winsize 62
5549 01:35:49.467679 [CA 1] Center 36 (6~67) winsize 62
5550 01:35:49.471335 [CA 2] Center 33 (3~64) winsize 62
5551 01:35:49.474557 [CA 3] Center 33 (3~64) winsize 62
5552 01:35:49.475084 [CA 4] Center 34 (4~64) winsize 61
5553 01:35:49.477756 [CA 5] Center 33 (2~64) winsize 63
5554 01:35:49.478171
5555 01:35:49.485059 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5556 01:35:49.485607
5557 01:35:49.488007 [CATrainingPosCal] consider 2 rank data
5558 01:35:49.491149 u2DelayCellTimex100 = 270/100 ps
5559 01:35:49.494908 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 01:35:49.497688 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 01:35:49.501201 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5562 01:35:49.505948 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 01:35:49.508081 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 01:35:49.511017 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5565 01:35:49.511461
5566 01:35:49.514638 CA PerBit enable=1, Macro0, CA PI delay=33
5567 01:35:49.515168
5568 01:35:49.518137 [CBTSetCACLKResult] CA Dly = 33
5569 01:35:49.521722 CS Dly: 5 (0~37)
5570 01:35:49.522358
5571 01:35:49.524757 ----->DramcWriteLeveling(PI) begin...
5572 01:35:49.525328 ==
5573 01:35:49.528536 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 01:35:49.532331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 01:35:49.532854 ==
5576 01:35:49.534809 Write leveling (Byte 0): 24 => 24
5577 01:35:49.537956 Write leveling (Byte 1): 31 => 31
5578 01:35:49.540933 DramcWriteLeveling(PI) end<-----
5579 01:35:49.541379
5580 01:35:49.541706 ==
5581 01:35:49.544271 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 01:35:49.547672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 01:35:49.548205 ==
5584 01:35:49.551074 [Gating] SW mode calibration
5585 01:35:49.557378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 01:35:49.564971 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 01:35:49.567708 0 14 0 | B1->B0 | 3232 3232 | 1 1 | (1 1) (0 0)
5588 01:35:49.571606 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 01:35:49.578718 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 01:35:49.581666 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 01:35:49.584198 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 01:35:49.590880 0 14 20 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5593 01:35:49.594063 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
5594 01:35:49.597312 0 14 28 | B1->B0 | 2f2f 3030 | 0 1 | (0 1) (0 0)
5595 01:35:49.604933 0 15 0 | B1->B0 | 2b2b 2a2a | 0 0 | (1 1) (0 0)
5596 01:35:49.607742 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 01:35:49.610770 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5598 01:35:49.617323 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 01:35:49.620638 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 01:35:49.624642 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 01:35:49.630419 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 01:35:49.634130 0 15 28 | B1->B0 | 3232 2a2a | 0 0 | (1 1) (0 0)
5603 01:35:49.637247 1 0 0 | B1->B0 | 4242 3e3e | 0 0 | (0 0) (0 0)
5604 01:35:49.643996 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 01:35:49.647306 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 01:35:49.650301 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 01:35:49.657393 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 01:35:49.660698 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 01:35:49.663854 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 01:35:49.671150 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 01:35:49.673621 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 01:35:49.677479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 01:35:49.683968 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 01:35:49.686741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 01:35:49.690479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 01:35:49.697625 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 01:35:49.700360 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 01:35:49.703937 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 01:35:49.710204 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 01:35:49.713840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 01:35:49.717116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 01:35:49.720578 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 01:35:49.728046 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 01:35:49.730744 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 01:35:49.735039 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 01:35:49.740248 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5627 01:35:49.743432 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 01:35:49.747399 Total UI for P1: 0, mck2ui 16
5629 01:35:49.749873 best dqsien dly found for B0: ( 1, 2, 28)
5630 01:35:49.753627 Total UI for P1: 0, mck2ui 16
5631 01:35:49.757021 best dqsien dly found for B1: ( 1, 2, 28)
5632 01:35:49.760142 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5633 01:35:49.764731 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5634 01:35:49.765311
5635 01:35:49.767408 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5636 01:35:49.770762 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5637 01:35:49.773823 [Gating] SW calibration Done
5638 01:35:49.774330 ==
5639 01:35:49.777375 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 01:35:49.780694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 01:35:49.783731 ==
5642 01:35:49.784257 RX Vref Scan: 0
5643 01:35:49.784594
5644 01:35:49.787191 RX Vref 0 -> 0, step: 1
5645 01:35:49.787721
5646 01:35:49.790117 RX Delay -80 -> 252, step: 8
5647 01:35:49.794945 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5648 01:35:49.796780 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5649 01:35:49.800213 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5650 01:35:49.804560 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5651 01:35:49.807704 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5652 01:35:49.813349 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5653 01:35:49.816616 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5654 01:35:49.820451 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5655 01:35:49.823914 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5656 01:35:49.827666 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5657 01:35:49.830417 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5658 01:35:49.837029 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5659 01:35:49.840927 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5660 01:35:49.844487 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5661 01:35:49.846853 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5662 01:35:49.850336 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5663 01:35:49.850750 ==
5664 01:35:49.853322 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 01:35:49.860034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 01:35:49.860451 ==
5667 01:35:49.860787 DQS Delay:
5668 01:35:49.861143 DQS0 = 0, DQS1 = 0
5669 01:35:49.864222 DQM Delay:
5670 01:35:49.864731 DQM0 = 95, DQM1 = 89
5671 01:35:49.866710 DQ Delay:
5672 01:35:49.870235 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5673 01:35:49.873418 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5674 01:35:49.877126 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5675 01:35:49.880205 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5676 01:35:49.880719
5677 01:35:49.881112
5678 01:35:49.881430 ==
5679 01:35:49.884088 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 01:35:49.887534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 01:35:49.888071 ==
5682 01:35:49.888476
5683 01:35:49.888793
5684 01:35:49.890287 TX Vref Scan disable
5685 01:35:49.890703 == TX Byte 0 ==
5686 01:35:49.897273 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5687 01:35:49.900234 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5688 01:35:49.900770 == TX Byte 1 ==
5689 01:35:49.907748 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5690 01:35:49.910188 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5691 01:35:49.910609 ==
5692 01:35:49.913407 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 01:35:49.917268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 01:35:49.917777 ==
5695 01:35:49.918117
5696 01:35:49.918455
5697 01:35:49.920179 TX Vref Scan disable
5698 01:35:49.923495 == TX Byte 0 ==
5699 01:35:49.926941 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5700 01:35:49.930684 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5701 01:35:49.933539 == TX Byte 1 ==
5702 01:35:49.937005 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5703 01:35:49.940355 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5704 01:35:49.940778
5705 01:35:49.943863 [DATLAT]
5706 01:35:49.944427 Freq=933, CH1 RK0
5707 01:35:49.944768
5708 01:35:49.947982 DATLAT Default: 0xd
5709 01:35:49.948498 0, 0xFFFF, sum = 0
5710 01:35:49.950122 1, 0xFFFF, sum = 0
5711 01:35:49.950545 2, 0xFFFF, sum = 0
5712 01:35:49.953498 3, 0xFFFF, sum = 0
5713 01:35:49.954110 4, 0xFFFF, sum = 0
5714 01:35:49.957355 5, 0xFFFF, sum = 0
5715 01:35:49.957939 6, 0xFFFF, sum = 0
5716 01:35:49.960732 7, 0xFFFF, sum = 0
5717 01:35:49.961292 8, 0xFFFF, sum = 0
5718 01:35:49.963823 9, 0xFFFF, sum = 0
5719 01:35:49.964444 10, 0x0, sum = 1
5720 01:35:49.966776 11, 0x0, sum = 2
5721 01:35:49.967199 12, 0x0, sum = 3
5722 01:35:49.970581 13, 0x0, sum = 4
5723 01:35:49.971000 best_step = 11
5724 01:35:49.971325
5725 01:35:49.971630 ==
5726 01:35:49.973294 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 01:35:49.980459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 01:35:49.981005 ==
5729 01:35:49.981346 RX Vref Scan: 1
5730 01:35:49.981655
5731 01:35:49.984104 RX Vref 0 -> 0, step: 1
5732 01:35:49.984613
5733 01:35:49.986891 RX Delay -61 -> 252, step: 4
5734 01:35:49.987307
5735 01:35:49.991007 Set Vref, RX VrefLevel [Byte0]: 56
5736 01:35:49.993508 [Byte1]: 48
5737 01:35:49.994032
5738 01:35:49.997591 Final RX Vref Byte 0 = 56 to rank0
5739 01:35:50.000243 Final RX Vref Byte 1 = 48 to rank0
5740 01:35:50.004126 Final RX Vref Byte 0 = 56 to rank1
5741 01:35:50.007252 Final RX Vref Byte 1 = 48 to rank1==
5742 01:35:50.011189 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 01:35:50.013393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 01:35:50.013818 ==
5745 01:35:50.016678 DQS Delay:
5746 01:35:50.017280 DQS0 = 0, DQS1 = 0
5747 01:35:50.017619 DQM Delay:
5748 01:35:50.020865 DQM0 = 97, DQM1 = 90
5749 01:35:50.021334 DQ Delay:
5750 01:35:50.023490 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5751 01:35:50.027072 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5752 01:35:50.030000 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5753 01:35:50.033548 DQ12 =100, DQ13 =94, DQ14 =100, DQ15 =94
5754 01:35:50.033963
5755 01:35:50.034291
5756 01:35:50.043686 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5757 01:35:50.048936 CH1 RK0: MR19=504, MR18=13F0
5758 01:35:50.051502 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5759 01:35:50.052018
5760 01:35:50.053320 ----->DramcWriteLeveling(PI) begin...
5761 01:35:50.057028 ==
5762 01:35:50.061222 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 01:35:50.063833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 01:35:50.064349 ==
5765 01:35:50.066993 Write leveling (Byte 0): 25 => 25
5766 01:35:50.070876 Write leveling (Byte 1): 25 => 25
5767 01:35:50.073641 DramcWriteLeveling(PI) end<-----
5768 01:35:50.074054
5769 01:35:50.074380 ==
5770 01:35:50.076787 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 01:35:50.080057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 01:35:50.080573 ==
5773 01:35:50.083949 [Gating] SW mode calibration
5774 01:35:50.090230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5775 01:35:50.096672 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5776 01:35:50.100292 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 01:35:50.103657 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 01:35:50.107334 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 01:35:50.113767 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 01:35:50.116762 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 01:35:50.120068 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 01:35:50.127710 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5783 01:35:50.129915 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5784 01:35:50.133355 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 01:35:50.140005 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 01:35:50.143406 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5787 01:35:50.147408 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 01:35:50.152920 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 01:35:50.156841 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5790 01:35:50.161165 0 15 24 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
5791 01:35:50.166727 0 15 28 | B1->B0 | 3535 4545 | 0 0 | (1 1) (0 0)
5792 01:35:50.169674 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 01:35:50.173689 1 0 4 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
5794 01:35:50.179888 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 01:35:50.183532 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 01:35:50.186490 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 01:35:50.193510 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5798 01:35:50.197023 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5799 01:35:50.200476 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5800 01:35:50.206521 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5801 01:35:50.209772 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 01:35:50.213839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 01:35:50.220387 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 01:35:50.224082 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 01:35:50.227252 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 01:35:50.230165 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 01:35:50.237095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 01:35:50.241189 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 01:35:50.243973 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 01:35:50.250439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 01:35:50.254634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 01:35:50.256502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 01:35:50.263984 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 01:35:50.267042 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5815 01:35:50.269721 Total UI for P1: 0, mck2ui 16
5816 01:35:50.273535 best dqsien dly found for B0: ( 1, 2, 22)
5817 01:35:50.277099 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 01:35:50.280132 Total UI for P1: 0, mck2ui 16
5819 01:35:50.283610 best dqsien dly found for B1: ( 1, 2, 24)
5820 01:35:50.286930 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5821 01:35:50.290524 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5822 01:35:50.291103
5823 01:35:50.293514 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5824 01:35:50.300524 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5825 01:35:50.301168 [Gating] SW calibration Done
5826 01:35:50.301659 ==
5827 01:35:50.303752 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 01:35:50.310464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 01:35:50.310928 ==
5830 01:35:50.311296 RX Vref Scan: 0
5831 01:35:50.311642
5832 01:35:50.313671 RX Vref 0 -> 0, step: 1
5833 01:35:50.314126
5834 01:35:50.316676 RX Delay -80 -> 252, step: 8
5835 01:35:50.320257 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5836 01:35:50.323689 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5837 01:35:50.326771 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5838 01:35:50.330163 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5839 01:35:50.337133 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5840 01:35:50.340756 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5841 01:35:50.344063 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5842 01:35:50.347231 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5843 01:35:50.349586 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5844 01:35:50.353068 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5845 01:35:50.360201 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5846 01:35:50.363279 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5847 01:35:50.366369 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5848 01:35:50.370284 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5849 01:35:50.374482 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5850 01:35:50.378271 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5851 01:35:50.380542 ==
5852 01:35:50.383478 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 01:35:50.387583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 01:35:50.388145 ==
5855 01:35:50.388519 DQS Delay:
5856 01:35:50.390227 DQS0 = 0, DQS1 = 0
5857 01:35:50.390682 DQM Delay:
5858 01:35:50.393761 DQM0 = 93, DQM1 = 88
5859 01:35:50.394218 DQ Delay:
5860 01:35:50.396765 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5861 01:35:50.400079 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5862 01:35:50.403333 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5863 01:35:50.407142 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5864 01:35:50.407798
5865 01:35:50.408176
5866 01:35:50.408518 ==
5867 01:35:50.410301 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 01:35:50.413111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 01:35:50.413594 ==
5870 01:35:50.413967
5871 01:35:50.414303
5872 01:35:50.417984 TX Vref Scan disable
5873 01:35:50.421074 == TX Byte 0 ==
5874 01:35:50.423627 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5875 01:35:50.427341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5876 01:35:50.430709 == TX Byte 1 ==
5877 01:35:50.433908 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5878 01:35:50.437316 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5879 01:35:50.437910 ==
5880 01:35:50.440443 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 01:35:50.443443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 01:35:50.446900 ==
5883 01:35:50.447359
5884 01:35:50.447717
5885 01:35:50.448081 TX Vref Scan disable
5886 01:35:50.451369 == TX Byte 0 ==
5887 01:35:50.453751 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5888 01:35:50.458239 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5889 01:35:50.460673 == TX Byte 1 ==
5890 01:35:50.464114 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5891 01:35:50.467201 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5892 01:35:50.470347
5893 01:35:50.470904 [DATLAT]
5894 01:35:50.471272 Freq=933, CH1 RK1
5895 01:35:50.471618
5896 01:35:50.473721 DATLAT Default: 0xb
5897 01:35:50.474181 0, 0xFFFF, sum = 0
5898 01:35:50.477048 1, 0xFFFF, sum = 0
5899 01:35:50.477514 2, 0xFFFF, sum = 0
5900 01:35:50.481026 3, 0xFFFF, sum = 0
5901 01:35:50.481448 4, 0xFFFF, sum = 0
5902 01:35:50.483596 5, 0xFFFF, sum = 0
5903 01:35:50.484034 6, 0xFFFF, sum = 0
5904 01:35:50.486863 7, 0xFFFF, sum = 0
5905 01:35:50.491684 8, 0xFFFF, sum = 0
5906 01:35:50.492250 9, 0xFFFF, sum = 0
5907 01:35:50.492627 10, 0x0, sum = 1
5908 01:35:50.494541 11, 0x0, sum = 2
5909 01:35:50.495007 12, 0x0, sum = 3
5910 01:35:50.497983 13, 0x0, sum = 4
5911 01:35:50.498406 best_step = 11
5912 01:35:50.498764
5913 01:35:50.499101 ==
5914 01:35:50.501022 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 01:35:50.507983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 01:35:50.508527 ==
5917 01:35:50.508892 RX Vref Scan: 0
5918 01:35:50.509358
5919 01:35:50.510177 RX Vref 0 -> 0, step: 1
5920 01:35:50.510630
5921 01:35:50.513503 RX Delay -61 -> 252, step: 4
5922 01:35:50.516867 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5923 01:35:50.523715 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5924 01:35:50.527170 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5925 01:35:50.530756 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5926 01:35:50.533643 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5927 01:35:50.538039 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5928 01:35:50.540545 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5929 01:35:50.544189 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5930 01:35:50.550438 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5931 01:35:50.553253 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5932 01:35:50.556680 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5933 01:35:50.560513 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5934 01:35:50.564086 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5935 01:35:50.567182 iDelay=199, Bit 13, Center 96 (3 ~ 190) 188
5936 01:35:50.573774 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5937 01:35:50.577222 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5938 01:35:50.577637 ==
5939 01:35:50.580169 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 01:35:50.583648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 01:35:50.584171 ==
5942 01:35:50.587425 DQS Delay:
5943 01:35:50.587942 DQS0 = 0, DQS1 = 0
5944 01:35:50.588275 DQM Delay:
5945 01:35:50.591012 DQM0 = 95, DQM1 = 89
5946 01:35:50.591542 DQ Delay:
5947 01:35:50.593829 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =94
5948 01:35:50.597441 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5949 01:35:50.600836 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =82
5950 01:35:50.603555 DQ12 =94, DQ13 =96, DQ14 =96, DQ15 =98
5951 01:35:50.603971
5952 01:35:50.604297
5953 01:35:50.614566 [DQSOSCAuto] RK1, (LSB)MR18= 0xf18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5954 01:35:50.615241 CH1 RK1: MR19=505, MR18=F18
5955 01:35:50.620411 CH1_RK1: MR19=0x505, MR18=0xF18, DQSOSC=414, MR23=63, INC=63, DEC=42
5956 01:35:50.626392 [RxdqsGatingPostProcess] freq 933
5957 01:35:50.630469 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5958 01:35:50.633339 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 01:35:50.637139 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 01:35:50.640170 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 01:35:50.643677 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 01:35:50.644419 best DQS0 dly(2T, 0.5T) = (0, 10)
5963 01:35:50.646652 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 01:35:50.650118 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5965 01:35:50.653473 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 01:35:50.656903 Pre-setting of DQS Precalculation
5967 01:35:50.664851 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5968 01:35:50.670373 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5969 01:35:50.677427 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5970 01:35:50.677888
5971 01:35:50.678251
5972 01:35:50.681687 [Calibration Summary] 1866 Mbps
5973 01:35:50.682240 CH 0, Rank 0
5974 01:35:50.684385 SW Impedance : PASS
5975 01:35:50.687644 DUTY Scan : NO K
5976 01:35:50.688201 ZQ Calibration : PASS
5977 01:35:50.690633 Jitter Meter : NO K
5978 01:35:50.694136 CBT Training : PASS
5979 01:35:50.694698 Write leveling : PASS
5980 01:35:50.697600 RX DQS gating : PASS
5981 01:35:50.700305 RX DQ/DQS(RDDQC) : PASS
5982 01:35:50.700861 TX DQ/DQS : PASS
5983 01:35:50.704590 RX DATLAT : PASS
5984 01:35:50.705237 RX DQ/DQS(Engine): PASS
5985 01:35:50.707120 TX OE : NO K
5986 01:35:50.707681 All Pass.
5987 01:35:50.708052
5988 01:35:50.709985 CH 0, Rank 1
5989 01:35:50.710440 SW Impedance : PASS
5990 01:35:50.713890 DUTY Scan : NO K
5991 01:35:50.717452 ZQ Calibration : PASS
5992 01:35:50.717908 Jitter Meter : NO K
5993 01:35:50.721125 CBT Training : PASS
5994 01:35:50.723583 Write leveling : PASS
5995 01:35:50.724141 RX DQS gating : PASS
5996 01:35:50.727071 RX DQ/DQS(RDDQC) : PASS
5997 01:35:50.730549 TX DQ/DQS : PASS
5998 01:35:50.731107 RX DATLAT : PASS
5999 01:35:50.735020 RX DQ/DQS(Engine): PASS
6000 01:35:50.737420 TX OE : NO K
6001 01:35:50.737929 All Pass.
6002 01:35:50.738300
6003 01:35:50.738641 CH 1, Rank 0
6004 01:35:50.740384 SW Impedance : PASS
6005 01:35:50.743581 DUTY Scan : NO K
6006 01:35:50.744044 ZQ Calibration : PASS
6007 01:35:50.747493 Jitter Meter : NO K
6008 01:35:50.747948 CBT Training : PASS
6009 01:35:50.750891 Write leveling : PASS
6010 01:35:50.753586 RX DQS gating : PASS
6011 01:35:50.754047 RX DQ/DQS(RDDQC) : PASS
6012 01:35:50.757058 TX DQ/DQS : PASS
6013 01:35:50.760680 RX DATLAT : PASS
6014 01:35:50.761304 RX DQ/DQS(Engine): PASS
6015 01:35:50.763759 TX OE : NO K
6016 01:35:50.764314 All Pass.
6017 01:35:50.764682
6018 01:35:50.767337 CH 1, Rank 1
6019 01:35:50.767791 SW Impedance : PASS
6020 01:35:50.770613 DUTY Scan : NO K
6021 01:35:50.774691 ZQ Calibration : PASS
6022 01:35:50.775253 Jitter Meter : NO K
6023 01:35:50.777244 CBT Training : PASS
6024 01:35:50.780514 Write leveling : PASS
6025 01:35:50.781129 RX DQS gating : PASS
6026 01:35:50.783981 RX DQ/DQS(RDDQC) : PASS
6027 01:35:50.787886 TX DQ/DQS : PASS
6028 01:35:50.788445 RX DATLAT : PASS
6029 01:35:50.790159 RX DQ/DQS(Engine): PASS
6030 01:35:50.790739 TX OE : NO K
6031 01:35:50.794595 All Pass.
6032 01:35:50.795052
6033 01:35:50.795413 DramC Write-DBI off
6034 01:35:50.796870 PER_BANK_REFRESH: Hybrid Mode
6035 01:35:50.800335 TX_TRACKING: ON
6036 01:35:50.807282 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6037 01:35:50.810171 [FAST_K] Save calibration result to emmc
6038 01:35:50.813773 dramc_set_vcore_voltage set vcore to 650000
6039 01:35:50.817327 Read voltage for 400, 6
6040 01:35:50.817787 Vio18 = 0
6041 01:35:50.820404 Vcore = 650000
6042 01:35:50.820949 Vdram = 0
6043 01:35:50.821366 Vddq = 0
6044 01:35:50.824168 Vmddr = 0
6045 01:35:50.827943 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6046 01:35:50.833587 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6047 01:35:50.834134 MEM_TYPE=3, freq_sel=20
6048 01:35:50.837301 sv_algorithm_assistance_LP4_800
6049 01:35:50.844095 ============ PULL DRAM RESETB DOWN ============
6050 01:35:50.847015 ========== PULL DRAM RESETB DOWN end =========
6051 01:35:50.850245 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6052 01:35:50.853328 ===================================
6053 01:35:50.858267 LPDDR4 DRAM CONFIGURATION
6054 01:35:50.861661 ===================================
6055 01:35:50.863775 EX_ROW_EN[0] = 0x0
6056 01:35:50.864322 EX_ROW_EN[1] = 0x0
6057 01:35:50.867739 LP4Y_EN = 0x0
6058 01:35:50.868286 WORK_FSP = 0x0
6059 01:35:50.870858 WL = 0x2
6060 01:35:50.871486 RL = 0x2
6061 01:35:50.873700 BL = 0x2
6062 01:35:50.874251 RPST = 0x0
6063 01:35:50.876571 RD_PRE = 0x0
6064 01:35:50.877067 WR_PRE = 0x1
6065 01:35:50.880785 WR_PST = 0x0
6066 01:35:50.881336 DBI_WR = 0x0
6067 01:35:50.883896 DBI_RD = 0x0
6068 01:35:50.884444 OTF = 0x1
6069 01:35:50.887080 ===================================
6070 01:35:50.890431 ===================================
6071 01:35:50.893767 ANA top config
6072 01:35:50.896431 ===================================
6073 01:35:50.896891 DLL_ASYNC_EN = 0
6074 01:35:50.900329 ALL_SLAVE_EN = 1
6075 01:35:50.904040 NEW_RANK_MODE = 1
6076 01:35:50.906961 DLL_IDLE_MODE = 1
6077 01:35:50.910624 LP45_APHY_COMB_EN = 1
6078 01:35:50.911084 TX_ODT_DIS = 1
6079 01:35:50.913497 NEW_8X_MODE = 1
6080 01:35:50.917078 ===================================
6081 01:35:50.920022 ===================================
6082 01:35:50.923512 data_rate = 800
6083 01:35:50.926900 CKR = 1
6084 01:35:50.930329 DQ_P2S_RATIO = 4
6085 01:35:50.934845 ===================================
6086 01:35:50.935405 CA_P2S_RATIO = 4
6087 01:35:50.937534 DQ_CA_OPEN = 0
6088 01:35:50.940445 DQ_SEMI_OPEN = 1
6089 01:35:50.944190 CA_SEMI_OPEN = 1
6090 01:35:50.947155 CA_FULL_RATE = 0
6091 01:35:50.950954 DQ_CKDIV4_EN = 0
6092 01:35:50.951515 CA_CKDIV4_EN = 1
6093 01:35:50.953517 CA_PREDIV_EN = 0
6094 01:35:50.957900 PH8_DLY = 0
6095 01:35:50.960735 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6096 01:35:50.963891 DQ_AAMCK_DIV = 0
6097 01:35:50.967084 CA_AAMCK_DIV = 0
6098 01:35:50.967630 CA_ADMCK_DIV = 4
6099 01:35:50.970528 DQ_TRACK_CA_EN = 0
6100 01:35:50.973769 CA_PICK = 800
6101 01:35:50.976850 CA_MCKIO = 400
6102 01:35:50.980180 MCKIO_SEMI = 400
6103 01:35:50.983932 PLL_FREQ = 3016
6104 01:35:50.987176 DQ_UI_PI_RATIO = 32
6105 01:35:50.987638 CA_UI_PI_RATIO = 32
6106 01:35:50.990761 ===================================
6107 01:35:50.994079 ===================================
6108 01:35:50.996888 memory_type:LPDDR4
6109 01:35:51.000748 GP_NUM : 10
6110 01:35:51.001357 SRAM_EN : 1
6111 01:35:51.003742 MD32_EN : 0
6112 01:35:51.007305 ===================================
6113 01:35:51.010176 [ANA_INIT] >>>>>>>>>>>>>>
6114 01:35:51.013984 <<<<<< [CONFIGURE PHASE]: ANA_TX
6115 01:35:51.017299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6116 01:35:51.017780 ===================================
6117 01:35:51.020458 data_rate = 800,PCW = 0X7400
6118 01:35:51.024119 ===================================
6119 01:35:51.027214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6120 01:35:51.033825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 01:35:51.044679 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 01:35:51.050658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6123 01:35:51.055285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6124 01:35:51.057592 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6125 01:35:51.058057 [ANA_INIT] flow start
6126 01:35:51.060916 [ANA_INIT] PLL >>>>>>>>
6127 01:35:51.064187 [ANA_INIT] PLL <<<<<<<<
6128 01:35:51.064780 [ANA_INIT] MIDPI >>>>>>>>
6129 01:35:51.067684 [ANA_INIT] MIDPI <<<<<<<<
6130 01:35:51.071008 [ANA_INIT] DLL >>>>>>>>
6131 01:35:51.071590 [ANA_INIT] flow end
6132 01:35:51.077439 ============ LP4 DIFF to SE enter ============
6133 01:35:51.080522 ============ LP4 DIFF to SE exit ============
6134 01:35:51.084211 [ANA_INIT] <<<<<<<<<<<<<
6135 01:35:51.087114 [Flow] Enable top DCM control >>>>>
6136 01:35:51.091154 [Flow] Enable top DCM control <<<<<
6137 01:35:51.091714 Enable DLL master slave shuffle
6138 01:35:51.097267 ==============================================================
6139 01:35:51.100747 Gating Mode config
6140 01:35:51.105093 ==============================================================
6141 01:35:51.107537 Config description:
6142 01:35:51.117364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6143 01:35:51.124109 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6144 01:35:51.127791 SELPH_MODE 0: By rank 1: By Phase
6145 01:35:51.134006 ==============================================================
6146 01:35:51.138470 GAT_TRACK_EN = 0
6147 01:35:51.141384 RX_GATING_MODE = 2
6148 01:35:51.144434 RX_GATING_TRACK_MODE = 2
6149 01:35:51.145015 SELPH_MODE = 1
6150 01:35:51.147186 PICG_EARLY_EN = 1
6151 01:35:51.151072 VALID_LAT_VALUE = 1
6152 01:35:51.157618 ==============================================================
6153 01:35:51.161148 Enter into Gating configuration >>>>
6154 01:35:51.164835 Exit from Gating configuration <<<<
6155 01:35:51.167435 Enter into DVFS_PRE_config >>>>>
6156 01:35:51.177722 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6157 01:35:51.181041 Exit from DVFS_PRE_config <<<<<
6158 01:35:51.183905 Enter into PICG configuration >>>>
6159 01:35:51.187796 Exit from PICG configuration <<<<
6160 01:35:51.190956 [RX_INPUT] configuration >>>>>
6161 01:35:51.194860 [RX_INPUT] configuration <<<<<
6162 01:35:51.197412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6163 01:35:51.204602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6164 01:35:51.211132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 01:35:51.217194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 01:35:51.220840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 01:35:51.227987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 01:35:51.231673 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6169 01:35:51.237535 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6170 01:35:51.240853 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6171 01:35:51.244059 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6172 01:35:51.247418 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6173 01:35:51.254524 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 01:35:51.257960 ===================================
6175 01:35:51.258525 LPDDR4 DRAM CONFIGURATION
6176 01:35:51.260967 ===================================
6177 01:35:51.264211 EX_ROW_EN[0] = 0x0
6178 01:35:51.267507 EX_ROW_EN[1] = 0x0
6179 01:35:51.268069 LP4Y_EN = 0x0
6180 01:35:51.271660 WORK_FSP = 0x0
6181 01:35:51.272223 WL = 0x2
6182 01:35:51.274484 RL = 0x2
6183 01:35:51.275046 BL = 0x2
6184 01:35:51.277669 RPST = 0x0
6185 01:35:51.278245 RD_PRE = 0x0
6186 01:35:51.280554 WR_PRE = 0x1
6187 01:35:51.281140 WR_PST = 0x0
6188 01:35:51.284920 DBI_WR = 0x0
6189 01:35:51.285524 DBI_RD = 0x0
6190 01:35:51.287933 OTF = 0x1
6191 01:35:51.291064 ===================================
6192 01:35:51.293887 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6193 01:35:51.297717 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6194 01:35:51.304108 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 01:35:51.304656 ===================================
6196 01:35:51.308559 LPDDR4 DRAM CONFIGURATION
6197 01:35:51.310646 ===================================
6198 01:35:51.314128 EX_ROW_EN[0] = 0x10
6199 01:35:51.314595 EX_ROW_EN[1] = 0x0
6200 01:35:51.317572 LP4Y_EN = 0x0
6201 01:35:51.318133 WORK_FSP = 0x0
6202 01:35:51.321096 WL = 0x2
6203 01:35:51.321561 RL = 0x2
6204 01:35:51.324282 BL = 0x2
6205 01:35:51.324850 RPST = 0x0
6206 01:35:51.327821 RD_PRE = 0x0
6207 01:35:51.331201 WR_PRE = 0x1
6208 01:35:51.331771 WR_PST = 0x0
6209 01:35:51.334167 DBI_WR = 0x0
6210 01:35:51.334634 DBI_RD = 0x0
6211 01:35:51.337744 OTF = 0x1
6212 01:35:51.341489 ===================================
6213 01:35:51.344117 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6214 01:35:51.350070 nWR fixed to 30
6215 01:35:51.352667 [ModeRegInit_LP4] CH0 RK0
6216 01:35:51.353200 [ModeRegInit_LP4] CH0 RK1
6217 01:35:51.356236 [ModeRegInit_LP4] CH1 RK0
6218 01:35:51.359892 [ModeRegInit_LP4] CH1 RK1
6219 01:35:51.360461 match AC timing 19
6220 01:35:51.366956 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6221 01:35:51.369918 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6222 01:35:51.373385 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6223 01:35:51.380052 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6224 01:35:51.383481 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6225 01:35:51.384053 ==
6226 01:35:51.386764 Dram Type= 6, Freq= 0, CH_0, rank 0
6227 01:35:51.389705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 01:35:51.390275 ==
6229 01:35:51.396580 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 01:35:51.403557 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6231 01:35:51.406274 [CA 0] Center 36 (8~64) winsize 57
6232 01:35:51.409909 [CA 1] Center 36 (8~64) winsize 57
6233 01:35:51.410478 [CA 2] Center 36 (8~64) winsize 57
6234 01:35:51.412603 [CA 3] Center 36 (8~64) winsize 57
6235 01:35:51.416464 [CA 4] Center 36 (8~64) winsize 57
6236 01:35:51.419739 [CA 5] Center 36 (8~64) winsize 57
6237 01:35:51.420208
6238 01:35:51.422999 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6239 01:35:51.423610
6240 01:35:51.429831 [CATrainingPosCal] consider 1 rank data
6241 01:35:51.430390 u2DelayCellTimex100 = 270/100 ps
6242 01:35:51.433699 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 01:35:51.439790 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 01:35:51.442858 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 01:35:51.446503 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 01:35:51.450165 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 01:35:51.453499 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 01:35:51.454086
6249 01:35:51.456371 CA PerBit enable=1, Macro0, CA PI delay=36
6250 01:35:51.456837
6251 01:35:51.459981 [CBTSetCACLKResult] CA Dly = 36
6252 01:35:51.460447 CS Dly: 1 (0~32)
6253 01:35:51.462627 ==
6254 01:35:51.467576 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 01:35:51.469560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 01:35:51.470032 ==
6257 01:35:51.472821 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 01:35:51.479404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6259 01:35:51.483113 [CA 0] Center 36 (8~64) winsize 57
6260 01:35:51.486550 [CA 1] Center 36 (8~64) winsize 57
6261 01:35:51.489940 [CA 2] Center 36 (8~64) winsize 57
6262 01:35:51.493733 [CA 3] Center 36 (8~64) winsize 57
6263 01:35:51.496637 [CA 4] Center 36 (8~64) winsize 57
6264 01:35:51.499679 [CA 5] Center 36 (8~64) winsize 57
6265 01:35:51.500274
6266 01:35:51.503366 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6267 01:35:51.503950
6268 01:35:51.506453 [CATrainingPosCal] consider 2 rank data
6269 01:35:51.509965 u2DelayCellTimex100 = 270/100 ps
6270 01:35:51.512739 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 01:35:51.516178 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 01:35:51.519521 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 01:35:51.524315 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 01:35:51.526243 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 01:35:51.532535 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 01:35:51.533153
6277 01:35:51.536260 CA PerBit enable=1, Macro0, CA PI delay=36
6278 01:35:51.536835
6279 01:35:51.539214 [CBTSetCACLKResult] CA Dly = 36
6280 01:35:51.539806 CS Dly: 1 (0~32)
6281 01:35:51.540193
6282 01:35:51.542559 ----->DramcWriteLeveling(PI) begin...
6283 01:35:51.543033 ==
6284 01:35:51.546163 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 01:35:51.549100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 01:35:51.552788 ==
6287 01:35:51.553291 Write leveling (Byte 0): 40 => 8
6288 01:35:51.556388 Write leveling (Byte 1): 32 => 0
6289 01:35:51.559264 DramcWriteLeveling(PI) end<-----
6290 01:35:51.559825
6291 01:35:51.560191 ==
6292 01:35:51.562399 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 01:35:51.569030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 01:35:51.569494 ==
6295 01:35:51.573046 [Gating] SW mode calibration
6296 01:35:51.579502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6297 01:35:51.582796 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6298 01:35:51.588855 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 01:35:51.592801 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 01:35:51.596080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 01:35:51.599266 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 01:35:51.606633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 01:35:51.609624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 01:35:51.613160 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 01:35:51.619644 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 01:35:51.622684 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 01:35:51.626157 Total UI for P1: 0, mck2ui 16
6308 01:35:51.629120 best dqsien dly found for B0: ( 0, 14, 24)
6309 01:35:51.632417 Total UI for P1: 0, mck2ui 16
6310 01:35:51.636815 best dqsien dly found for B1: ( 0, 14, 24)
6311 01:35:51.639178 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6312 01:35:51.642694 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6313 01:35:51.643389
6314 01:35:51.645825 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 01:35:51.649240 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 01:35:51.652403 [Gating] SW calibration Done
6317 01:35:51.653175 ==
6318 01:35:51.655581 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 01:35:51.662875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 01:35:51.663452 ==
6321 01:35:51.663921 RX Vref Scan: 0
6322 01:35:51.664270
6323 01:35:51.666038 RX Vref 0 -> 0, step: 1
6324 01:35:51.666491
6325 01:35:51.668864 RX Delay -410 -> 252, step: 16
6326 01:35:51.672434 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6327 01:35:51.676025 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6328 01:35:51.679027 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6329 01:35:51.686337 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6330 01:35:51.689232 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6331 01:35:51.692280 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6332 01:35:51.696014 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6333 01:35:51.703396 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6334 01:35:51.706080 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6335 01:35:51.710267 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6336 01:35:51.712890 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6337 01:35:51.719396 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6338 01:35:51.722792 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6339 01:35:51.726280 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6340 01:35:51.730286 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6341 01:35:51.735947 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6342 01:35:51.736497 ==
6343 01:35:51.739633 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 01:35:51.743731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 01:35:51.744198 ==
6346 01:35:51.744566 DQS Delay:
6347 01:35:51.746403 DQS0 = 43, DQS1 = 51
6348 01:35:51.746972 DQM Delay:
6349 01:35:51.749903 DQM0 = 14, DQM1 = 10
6350 01:35:51.750481 DQ Delay:
6351 01:35:51.752651 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6352 01:35:51.756216 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6353 01:35:51.759192 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6354 01:35:51.762991 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6355 01:35:51.763456
6356 01:35:51.763823
6357 01:35:51.764161 ==
6358 01:35:51.766154 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 01:35:51.769370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 01:35:51.769842 ==
6361 01:35:51.770255
6362 01:35:51.770596
6363 01:35:51.772791 TX Vref Scan disable
6364 01:35:51.776630 == TX Byte 0 ==
6365 01:35:51.779470 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 01:35:51.782664 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 01:35:51.786337 == TX Byte 1 ==
6368 01:35:51.789388 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6369 01:35:51.792536 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6370 01:35:51.792961 ==
6371 01:35:51.796308 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 01:35:51.799378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 01:35:51.799799 ==
6374 01:35:51.802193
6375 01:35:51.802607
6376 01:35:51.802941 TX Vref Scan disable
6377 01:35:51.805569 == TX Byte 0 ==
6378 01:35:51.809564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 01:35:51.812367 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 01:35:51.815570 == TX Byte 1 ==
6381 01:35:51.819506 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 01:35:51.822821 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 01:35:51.823351
6384 01:35:51.823691 [DATLAT]
6385 01:35:51.826061 Freq=400, CH0 RK0
6386 01:35:51.826596
6387 01:35:51.828918 DATLAT Default: 0xf
6388 01:35:51.829378 0, 0xFFFF, sum = 0
6389 01:35:51.832760 1, 0xFFFF, sum = 0
6390 01:35:51.833345 2, 0xFFFF, sum = 0
6391 01:35:51.835866 3, 0xFFFF, sum = 0
6392 01:35:51.836399 4, 0xFFFF, sum = 0
6393 01:35:51.839349 5, 0xFFFF, sum = 0
6394 01:35:51.839878 6, 0xFFFF, sum = 0
6395 01:35:51.843444 7, 0xFFFF, sum = 0
6396 01:35:51.843974 8, 0xFFFF, sum = 0
6397 01:35:51.846339 9, 0xFFFF, sum = 0
6398 01:35:51.846867 10, 0xFFFF, sum = 0
6399 01:35:51.849284 11, 0xFFFF, sum = 0
6400 01:35:51.849881 12, 0xFFFF, sum = 0
6401 01:35:51.852600 13, 0x0, sum = 1
6402 01:35:51.853091 14, 0x0, sum = 2
6403 01:35:51.855971 15, 0x0, sum = 3
6404 01:35:51.856538 16, 0x0, sum = 4
6405 01:35:51.859628 best_step = 14
6406 01:35:51.860131
6407 01:35:51.860575 ==
6408 01:35:51.862387 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 01:35:51.865874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 01:35:51.866408 ==
6411 01:35:51.866751 RX Vref Scan: 1
6412 01:35:51.869468
6413 01:35:51.869995 RX Vref 0 -> 0, step: 1
6414 01:35:51.870338
6415 01:35:51.872889 RX Delay -343 -> 252, step: 8
6416 01:35:51.873455
6417 01:35:51.876162 Set Vref, RX VrefLevel [Byte0]: 52
6418 01:35:51.879281 [Byte1]: 52
6419 01:35:51.883938
6420 01:35:51.884463 Final RX Vref Byte 0 = 52 to rank0
6421 01:35:51.886907 Final RX Vref Byte 1 = 52 to rank0
6422 01:35:51.890003 Final RX Vref Byte 0 = 52 to rank1
6423 01:35:51.893893 Final RX Vref Byte 1 = 52 to rank1==
6424 01:35:51.896588 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 01:35:51.903277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 01:35:51.903704 ==
6427 01:35:51.904040 DQS Delay:
6428 01:35:51.906733 DQS0 = 44, DQS1 = 60
6429 01:35:51.907256 DQM Delay:
6430 01:35:51.907633 DQM0 = 10, DQM1 = 14
6431 01:35:51.910313 DQ Delay:
6432 01:35:51.913111 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6433 01:35:51.913539 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6434 01:35:51.917222 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6435 01:35:51.920285 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6436 01:35:51.923838
6437 01:35:51.924353
6438 01:35:51.930725 [DQSOSCAuto] RK0, (LSB)MR18= 0x7c4a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
6439 01:35:51.933470 CH0 RK0: MR19=C0C, MR18=7C4A
6440 01:35:51.940141 CH0_RK0: MR19=0xC0C, MR18=0x7C4A, DQSOSC=394, MR23=63, INC=380, DEC=253
6441 01:35:51.940688 ==
6442 01:35:51.943174 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 01:35:51.946762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 01:35:51.947520 ==
6445 01:35:51.949839 [Gating] SW mode calibration
6446 01:35:51.956862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6447 01:35:51.960199 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6448 01:35:51.966777 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 01:35:51.970394 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 01:35:51.973767 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 01:35:51.979908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 01:35:51.983788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 01:35:51.986481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 01:35:51.993466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 01:35:51.997334 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 01:35:52.000491 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 01:35:52.004025 Total UI for P1: 0, mck2ui 16
6458 01:35:52.008639 best dqsien dly found for B0: ( 0, 14, 24)
6459 01:35:52.010221 Total UI for P1: 0, mck2ui 16
6460 01:35:52.013735 best dqsien dly found for B1: ( 0, 14, 24)
6461 01:35:52.017053 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6462 01:35:52.020876 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6463 01:35:52.021486
6464 01:35:52.027751 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 01:35:52.031013 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 01:35:52.031574 [Gating] SW calibration Done
6467 01:35:52.033829 ==
6468 01:35:52.037843 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 01:35:52.041256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 01:35:52.041727 ==
6471 01:35:52.042097 RX Vref Scan: 0
6472 01:35:52.042434
6473 01:35:52.043538 RX Vref 0 -> 0, step: 1
6474 01:35:52.043997
6475 01:35:52.047038 RX Delay -410 -> 252, step: 16
6476 01:35:52.050504 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6477 01:35:52.053367 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6478 01:35:52.060397 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6479 01:35:52.064310 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6480 01:35:52.067711 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6481 01:35:52.070289 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6482 01:35:52.076940 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6483 01:35:52.080801 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6484 01:35:52.084478 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6485 01:35:52.087457 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6486 01:35:52.094116 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6487 01:35:52.097099 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6488 01:35:52.100749 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6489 01:35:52.103992 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6490 01:35:52.110012 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6491 01:35:52.113619 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6492 01:35:52.114187 ==
6493 01:35:52.117080 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 01:35:52.120371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 01:35:52.121042 ==
6496 01:35:52.124149 DQS Delay:
6497 01:35:52.124721 DQS0 = 43, DQS1 = 51
6498 01:35:52.127656 DQM Delay:
6499 01:35:52.128220 DQM0 = 11, DQM1 = 10
6500 01:35:52.128594 DQ Delay:
6501 01:35:52.130617 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6502 01:35:52.133385 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6503 01:35:52.137126 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6504 01:35:52.141125 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6505 01:35:52.141687
6506 01:35:52.142062
6507 01:35:52.142404 ==
6508 01:35:52.144262 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 01:35:52.146761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 01:35:52.150251 ==
6511 01:35:52.150790
6512 01:35:52.151165
6513 01:35:52.151511 TX Vref Scan disable
6514 01:35:52.153505 == TX Byte 0 ==
6515 01:35:52.157138 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6516 01:35:52.160654 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6517 01:35:52.163758 == TX Byte 1 ==
6518 01:35:52.167333 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6519 01:35:52.170228 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6520 01:35:52.170785 ==
6521 01:35:52.174296 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 01:35:52.176584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 01:35:52.180615 ==
6524 01:35:52.181214
6525 01:35:52.181592
6526 01:35:52.181939 TX Vref Scan disable
6527 01:35:52.183923 == TX Byte 0 ==
6528 01:35:52.187446 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6529 01:35:52.189779 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6530 01:35:52.193637 == TX Byte 1 ==
6531 01:35:52.196769 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6532 01:35:52.200871 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6533 01:35:52.201518
6534 01:35:52.204216 [DATLAT]
6535 01:35:52.204796 Freq=400, CH0 RK1
6536 01:35:52.205227
6537 01:35:52.206863 DATLAT Default: 0xe
6538 01:35:52.207389 0, 0xFFFF, sum = 0
6539 01:35:52.210004 1, 0xFFFF, sum = 0
6540 01:35:52.210577 2, 0xFFFF, sum = 0
6541 01:35:52.214151 3, 0xFFFF, sum = 0
6542 01:35:52.214726 4, 0xFFFF, sum = 0
6543 01:35:52.216578 5, 0xFFFF, sum = 0
6544 01:35:52.217071 6, 0xFFFF, sum = 0
6545 01:35:52.220418 7, 0xFFFF, sum = 0
6546 01:35:52.221029 8, 0xFFFF, sum = 0
6547 01:35:52.223768 9, 0xFFFF, sum = 0
6548 01:35:52.224241 10, 0xFFFF, sum = 0
6549 01:35:52.227068 11, 0xFFFF, sum = 0
6550 01:35:52.227647 12, 0xFFFF, sum = 0
6551 01:35:52.230581 13, 0x0, sum = 1
6552 01:35:52.231155 14, 0x0, sum = 2
6553 01:35:52.234010 15, 0x0, sum = 3
6554 01:35:52.234581 16, 0x0, sum = 4
6555 01:35:52.237195 best_step = 14
6556 01:35:52.237756
6557 01:35:52.238127 ==
6558 01:35:52.240488 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 01:35:52.244050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 01:35:52.244620 ==
6561 01:35:52.246642 RX Vref Scan: 0
6562 01:35:52.247105
6563 01:35:52.247494 RX Vref 0 -> 0, step: 1
6564 01:35:52.247895
6565 01:35:52.249883 RX Delay -343 -> 252, step: 8
6566 01:35:52.257915 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6567 01:35:52.262145 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6568 01:35:52.264607 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6569 01:35:52.268407 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6570 01:35:52.274517 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6571 01:35:52.278296 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6572 01:35:52.281790 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6573 01:35:52.284688 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6574 01:35:52.290885 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6575 01:35:52.295410 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6576 01:35:52.298255 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6577 01:35:52.301569 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6578 01:35:52.307799 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6579 01:35:52.311416 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6580 01:35:52.314563 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6581 01:35:52.317676 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6582 01:35:52.321524 ==
6583 01:35:52.325355 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 01:35:52.327971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 01:35:52.328542 ==
6586 01:35:52.328918 DQS Delay:
6587 01:35:52.331336 DQS0 = 48, DQS1 = 56
6588 01:35:52.331901 DQM Delay:
6589 01:35:52.334907 DQM0 = 12, DQM1 = 10
6590 01:35:52.335482 DQ Delay:
6591 01:35:52.337982 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6592 01:35:52.342016 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6593 01:35:52.345149 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =0
6594 01:35:52.348232 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6595 01:35:52.348806
6596 01:35:52.349221
6597 01:35:52.354377 [DQSOSCAuto] RK1, (LSB)MR18= 0x9468, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6598 01:35:52.358113 CH0 RK1: MR19=C0C, MR18=9468
6599 01:35:52.365064 CH0_RK1: MR19=0xC0C, MR18=0x9468, DQSOSC=391, MR23=63, INC=386, DEC=257
6600 01:35:52.369675 [RxdqsGatingPostProcess] freq 400
6601 01:35:52.371639 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6602 01:35:52.375048 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 01:35:52.377859 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 01:35:52.381882 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 01:35:52.385556 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 01:35:52.387963 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 01:35:52.391579 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 01:35:52.394964 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 01:35:52.398005 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 01:35:52.401139 Pre-setting of DQS Precalculation
6611 01:35:52.404822 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6612 01:35:52.405433 ==
6613 01:35:52.408409 Dram Type= 6, Freq= 0, CH_1, rank 0
6614 01:35:52.416281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 01:35:52.416850 ==
6616 01:35:52.417688 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 01:35:52.424437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 01:35:52.427991 [CA 0] Center 36 (8~64) winsize 57
6619 01:35:52.432118 [CA 1] Center 36 (8~64) winsize 57
6620 01:35:52.435193 [CA 2] Center 36 (8~64) winsize 57
6621 01:35:52.438326 [CA 3] Center 36 (8~64) winsize 57
6622 01:35:52.441141 [CA 4] Center 36 (8~64) winsize 57
6623 01:35:52.444967 [CA 5] Center 36 (8~64) winsize 57
6624 01:35:52.445582
6625 01:35:52.448408 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 01:35:52.449017
6627 01:35:52.451042 [CATrainingPosCal] consider 1 rank data
6628 01:35:52.454506 u2DelayCellTimex100 = 270/100 ps
6629 01:35:52.458102 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 01:35:52.462325 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 01:35:52.464814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 01:35:52.468491 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 01:35:52.471788 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 01:35:52.475099 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 01:35:52.475568
6636 01:35:52.481784 CA PerBit enable=1, Macro0, CA PI delay=36
6637 01:35:52.482353
6638 01:35:52.485472 [CBTSetCACLKResult] CA Dly = 36
6639 01:35:52.486044 CS Dly: 1 (0~32)
6640 01:35:52.486424 ==
6641 01:35:52.488672 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 01:35:52.491785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 01:35:52.492350 ==
6644 01:35:52.498164 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 01:35:52.505501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6646 01:35:52.508736 [CA 0] Center 36 (8~64) winsize 57
6647 01:35:52.511521 [CA 1] Center 36 (8~64) winsize 57
6648 01:35:52.514419 [CA 2] Center 36 (8~64) winsize 57
6649 01:35:52.518209 [CA 3] Center 36 (8~64) winsize 57
6650 01:35:52.518768 [CA 4] Center 36 (8~64) winsize 57
6651 01:35:52.520943 [CA 5] Center 36 (8~64) winsize 57
6652 01:35:52.521464
6653 01:35:52.528079 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6654 01:35:52.528669
6655 01:35:52.531643 [CATrainingPosCal] consider 2 rank data
6656 01:35:52.534690 u2DelayCellTimex100 = 270/100 ps
6657 01:35:52.537671 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 01:35:52.541693 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 01:35:52.545329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 01:35:52.547946 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 01:35:52.551120 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 01:35:52.554693 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 01:35:52.555235
6664 01:35:52.557878 CA PerBit enable=1, Macro0, CA PI delay=36
6665 01:35:52.558396
6666 01:35:52.561137 [CBTSetCACLKResult] CA Dly = 36
6667 01:35:52.564681 CS Dly: 1 (0~32)
6668 01:35:52.565286
6669 01:35:52.568070 ----->DramcWriteLeveling(PI) begin...
6670 01:35:52.568634 ==
6671 01:35:52.571410 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 01:35:52.574604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 01:35:52.575164 ==
6674 01:35:52.577826 Write leveling (Byte 0): 40 => 8
6675 01:35:52.581148 Write leveling (Byte 1): 40 => 8
6676 01:35:52.584819 DramcWriteLeveling(PI) end<-----
6677 01:35:52.585438
6678 01:35:52.585815 ==
6679 01:35:52.587527 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 01:35:52.592136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 01:35:52.592707 ==
6682 01:35:52.595796 [Gating] SW mode calibration
6683 01:35:52.601720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6684 01:35:52.608338 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6685 01:35:52.611621 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 01:35:52.614452 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6687 01:35:52.621636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 01:35:52.624520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 01:35:52.628278 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 01:35:52.634900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 01:35:52.637839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 01:35:52.641912 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 01:35:52.648168 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 01:35:52.648728 Total UI for P1: 0, mck2ui 16
6695 01:35:52.651151 best dqsien dly found for B0: ( 0, 14, 24)
6696 01:35:52.654838 Total UI for P1: 0, mck2ui 16
6697 01:35:52.659060 best dqsien dly found for B1: ( 0, 14, 24)
6698 01:35:52.660900 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6699 01:35:52.667819 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6700 01:35:52.668438
6701 01:35:52.671306 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 01:35:52.674718 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 01:35:52.678692 [Gating] SW calibration Done
6704 01:35:52.679261 ==
6705 01:35:52.681128 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 01:35:52.685534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 01:35:52.686109 ==
6708 01:35:52.686485 RX Vref Scan: 0
6709 01:35:52.688018
6710 01:35:52.688631 RX Vref 0 -> 0, step: 1
6711 01:35:52.689221
6712 01:35:52.691231 RX Delay -410 -> 252, step: 16
6713 01:35:52.694463 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6714 01:35:52.702131 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6715 01:35:52.705099 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6716 01:35:52.708622 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6717 01:35:52.711772 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6718 01:35:52.718852 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6719 01:35:52.721478 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6720 01:35:52.724664 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6721 01:35:52.728282 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6722 01:35:52.734595 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6723 01:35:52.738133 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6724 01:35:52.741059 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6725 01:35:52.744660 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6726 01:35:52.751029 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6727 01:35:52.754864 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6728 01:35:52.757620 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6729 01:35:52.758090 ==
6730 01:35:52.761291 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 01:35:52.765429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 01:35:52.768452 ==
6733 01:35:52.769065 DQS Delay:
6734 01:35:52.769448 DQS0 = 51, DQS1 = 59
6735 01:35:52.771900 DQM Delay:
6736 01:35:52.772466 DQM0 = 19, DQM1 = 16
6737 01:35:52.774626 DQ Delay:
6738 01:35:52.775195 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6739 01:35:52.777798 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6740 01:35:52.781083 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6741 01:35:52.785083 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6742 01:35:52.785644
6743 01:35:52.786018
6744 01:35:52.789397 ==
6745 01:35:52.789969 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 01:35:52.795072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 01:35:52.795640 ==
6748 01:35:52.796012
6749 01:35:52.796354
6750 01:35:52.797875 TX Vref Scan disable
6751 01:35:52.798341 == TX Byte 0 ==
6752 01:35:52.801096 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 01:35:52.808814 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 01:35:52.809477 == TX Byte 1 ==
6755 01:35:52.812086 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 01:35:52.814479 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 01:35:52.818388 ==
6758 01:35:52.821563 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 01:35:52.824475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 01:35:52.824946 ==
6761 01:35:52.825355
6762 01:35:52.825702
6763 01:35:52.828496 TX Vref Scan disable
6764 01:35:52.828960 == TX Byte 0 ==
6765 01:35:52.831475 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 01:35:52.838159 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 01:35:52.838583 == TX Byte 1 ==
6768 01:35:52.841070 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 01:35:52.845369 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 01:35:52.848376
6771 01:35:52.848795 [DATLAT]
6772 01:35:52.849154 Freq=400, CH1 RK0
6773 01:35:52.849472
6774 01:35:52.851306 DATLAT Default: 0xf
6775 01:35:52.851729 0, 0xFFFF, sum = 0
6776 01:35:52.854554 1, 0xFFFF, sum = 0
6777 01:35:52.855107 2, 0xFFFF, sum = 0
6778 01:35:52.858534 3, 0xFFFF, sum = 0
6779 01:35:52.858963 4, 0xFFFF, sum = 0
6780 01:35:52.861517 5, 0xFFFF, sum = 0
6781 01:35:52.861949 6, 0xFFFF, sum = 0
6782 01:35:52.864708 7, 0xFFFF, sum = 0
6783 01:35:52.868292 8, 0xFFFF, sum = 0
6784 01:35:52.868826 9, 0xFFFF, sum = 0
6785 01:35:52.872576 10, 0xFFFF, sum = 0
6786 01:35:52.873153 11, 0xFFFF, sum = 0
6787 01:35:52.874944 12, 0xFFFF, sum = 0
6788 01:35:52.875476 13, 0x0, sum = 1
6789 01:35:52.878785 14, 0x0, sum = 2
6790 01:35:52.879319 15, 0x0, sum = 3
6791 01:35:52.882341 16, 0x0, sum = 4
6792 01:35:52.882771 best_step = 14
6793 01:35:52.883110
6794 01:35:52.883425 ==
6795 01:35:52.884855 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 01:35:52.888739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 01:35:52.889341 ==
6798 01:35:52.891698 RX Vref Scan: 1
6799 01:35:52.892117
6800 01:35:52.892452 RX Vref 0 -> 0, step: 1
6801 01:35:52.895108
6802 01:35:52.895527 RX Delay -359 -> 252, step: 8
6803 01:35:52.895865
6804 01:35:52.898560 Set Vref, RX VrefLevel [Byte0]: 56
6805 01:35:52.901271 [Byte1]: 48
6806 01:35:52.907264
6807 01:35:52.907801 Final RX Vref Byte 0 = 56 to rank0
6808 01:35:52.910301 Final RX Vref Byte 1 = 48 to rank0
6809 01:35:52.913716 Final RX Vref Byte 0 = 56 to rank1
6810 01:35:52.917037 Final RX Vref Byte 1 = 48 to rank1==
6811 01:35:52.920365 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 01:35:52.927259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 01:35:52.927689 ==
6814 01:35:52.928027 DQS Delay:
6815 01:35:52.929799 DQS0 = 48, DQS1 = 64
6816 01:35:52.930223 DQM Delay:
6817 01:35:52.930560 DQM0 = 12, DQM1 = 16
6818 01:35:52.933583 DQ Delay:
6819 01:35:52.937373 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6820 01:35:52.937903 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6821 01:35:52.940463 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6822 01:35:52.943763 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6823 01:35:52.944304
6824 01:35:52.947233
6825 01:35:52.953552 [DQSOSCAuto] RK0, (LSB)MR18= 0x8831, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6826 01:35:52.957325 CH1 RK0: MR19=C0C, MR18=8831
6827 01:35:52.963265 CH1_RK0: MR19=0xC0C, MR18=0x8831, DQSOSC=392, MR23=63, INC=384, DEC=256
6828 01:35:52.963693 ==
6829 01:35:52.966561 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 01:35:52.970180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 01:35:52.970713 ==
6832 01:35:52.973341 [Gating] SW mode calibration
6833 01:35:52.979943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6834 01:35:52.983198 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6835 01:35:52.990558 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 01:35:52.994610 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 01:35:52.997213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 01:35:53.003854 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 01:35:53.006725 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 01:35:53.010017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 01:35:53.016730 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 01:35:53.020563 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 01:35:53.023499 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 01:35:53.026446 Total UI for P1: 0, mck2ui 16
6845 01:35:53.030400 best dqsien dly found for B0: ( 0, 14, 24)
6846 01:35:53.033590 Total UI for P1: 0, mck2ui 16
6847 01:35:53.037746 best dqsien dly found for B1: ( 0, 14, 24)
6848 01:35:53.040157 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6849 01:35:53.043390 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6850 01:35:53.043964
6851 01:35:53.050590 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 01:35:53.053130 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 01:35:53.056579 [Gating] SW calibration Done
6854 01:35:53.057115 ==
6855 01:35:53.060132 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 01:35:53.063083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 01:35:53.063618 ==
6858 01:35:53.063991 RX Vref Scan: 0
6859 01:35:53.064339
6860 01:35:53.066849 RX Vref 0 -> 0, step: 1
6861 01:35:53.067419
6862 01:35:53.070545 RX Delay -410 -> 252, step: 16
6863 01:35:53.074886 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6864 01:35:53.080017 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6865 01:35:53.083059 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6866 01:35:53.087639 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6867 01:35:53.089997 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6868 01:35:53.096942 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6869 01:35:53.100018 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6870 01:35:53.103777 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6871 01:35:53.106499 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6872 01:35:53.109783 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6873 01:35:53.117232 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6874 01:35:53.119983 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6875 01:35:53.122967 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6876 01:35:53.129918 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6877 01:35:53.133569 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6878 01:35:53.136376 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6879 01:35:53.136841 ==
6880 01:35:53.139706 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 01:35:53.144371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 01:35:53.144942 ==
6883 01:35:53.147200 DQS Delay:
6884 01:35:53.147782 DQS0 = 43, DQS1 = 51
6885 01:35:53.150203 DQM Delay:
6886 01:35:53.150772 DQM0 = 10, DQM1 = 10
6887 01:35:53.152969 DQ Delay:
6888 01:35:53.153478 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6889 01:35:53.156492 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6890 01:35:53.159771 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6891 01:35:53.163192 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6892 01:35:53.163656
6893 01:35:53.164022
6894 01:35:53.164479 ==
6895 01:35:53.166856 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 01:35:53.173806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 01:35:53.174382 ==
6898 01:35:53.174758
6899 01:35:53.175102
6900 01:35:53.175432 TX Vref Scan disable
6901 01:35:53.176469 == TX Byte 0 ==
6902 01:35:53.180586 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6903 01:35:53.183165 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6904 01:35:53.186768 == TX Byte 1 ==
6905 01:35:53.190146 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6906 01:35:53.193818 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6907 01:35:53.194380 ==
6908 01:35:53.197371 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 01:35:53.200548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 01:35:53.203616 ==
6911 01:35:53.204083
6912 01:35:53.204448
6913 01:35:53.204790 TX Vref Scan disable
6914 01:35:53.207217 == TX Byte 0 ==
6915 01:35:53.209869 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6916 01:35:53.213386 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6917 01:35:53.217575 == TX Byte 1 ==
6918 01:35:53.221578 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6919 01:35:53.223848 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6920 01:35:53.224410
6921 01:35:53.224781 [DATLAT]
6922 01:35:53.227514 Freq=400, CH1 RK1
6923 01:35:53.228074
6924 01:35:53.230355 DATLAT Default: 0xe
6925 01:35:53.230913 0, 0xFFFF, sum = 0
6926 01:35:53.233623 1, 0xFFFF, sum = 0
6927 01:35:53.234195 2, 0xFFFF, sum = 0
6928 01:35:53.237682 3, 0xFFFF, sum = 0
6929 01:35:53.238235 4, 0xFFFF, sum = 0
6930 01:35:53.240490 5, 0xFFFF, sum = 0
6931 01:35:53.241107 6, 0xFFFF, sum = 0
6932 01:35:53.243967 7, 0xFFFF, sum = 0
6933 01:35:53.244645 8, 0xFFFF, sum = 0
6934 01:35:53.247104 9, 0xFFFF, sum = 0
6935 01:35:53.247673 10, 0xFFFF, sum = 0
6936 01:35:53.250349 11, 0xFFFF, sum = 0
6937 01:35:53.250912 12, 0xFFFF, sum = 0
6938 01:35:53.253382 13, 0x0, sum = 1
6939 01:35:53.253853 14, 0x0, sum = 2
6940 01:35:53.256689 15, 0x0, sum = 3
6941 01:35:53.257198 16, 0x0, sum = 4
6942 01:35:53.259696 best_step = 14
6943 01:35:53.260223
6944 01:35:53.260598 ==
6945 01:35:53.263081 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 01:35:53.266507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 01:35:53.267083 ==
6948 01:35:53.269895 RX Vref Scan: 0
6949 01:35:53.270357
6950 01:35:53.270730 RX Vref 0 -> 0, step: 1
6951 01:35:53.271077
6952 01:35:53.273745 RX Delay -343 -> 252, step: 8
6953 01:35:53.281189 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6954 01:35:53.285998 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6955 01:35:53.287993 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6956 01:35:53.292414 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6957 01:35:53.298278 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6958 01:35:53.301447 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6959 01:35:53.304385 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6960 01:35:53.308818 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6961 01:35:53.314803 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6962 01:35:53.318055 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6963 01:35:53.321191 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6964 01:35:53.324917 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6965 01:35:53.331300 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6966 01:35:53.334673 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6967 01:35:53.337578 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6968 01:35:53.344625 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6969 01:35:53.345215 ==
6970 01:35:53.347635 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 01:35:53.351209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 01:35:53.351769 ==
6973 01:35:53.352312 DQS Delay:
6974 01:35:53.354935 DQS0 = 52, DQS1 = 60
6975 01:35:53.355400 DQM Delay:
6976 01:35:53.357542 DQM0 = 14, DQM1 = 13
6977 01:35:53.358088 DQ Delay:
6978 01:35:53.361780 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6979 01:35:53.365545 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6980 01:35:53.367502 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6981 01:35:53.371232 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6982 01:35:53.371697
6983 01:35:53.372066
6984 01:35:53.377758 [DQSOSCAuto] RK1, (LSB)MR18= 0x758a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6985 01:35:53.381912 CH1 RK1: MR19=C0C, MR18=758A
6986 01:35:53.388517 CH1_RK1: MR19=0xC0C, MR18=0x758A, DQSOSC=392, MR23=63, INC=384, DEC=256
6987 01:35:53.391417 [RxdqsGatingPostProcess] freq 400
6988 01:35:53.394536 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6989 01:35:53.398522 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 01:35:53.401457 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 01:35:53.404248 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 01:35:53.408491 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 01:35:53.411883 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 01:35:53.415356 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 01:35:53.418395 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 01:35:53.421565 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 01:35:53.425023 Pre-setting of DQS Precalculation
6998 01:35:53.428049 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6999 01:35:53.438696 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7000 01:35:53.444543 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7001 01:35:53.445140
7002 01:35:53.445510
7003 01:35:53.448407 [Calibration Summary] 800 Mbps
7004 01:35:53.448963 CH 0, Rank 0
7005 01:35:53.451557 SW Impedance : PASS
7006 01:35:53.452115 DUTY Scan : NO K
7007 01:35:53.454858 ZQ Calibration : PASS
7008 01:35:53.458088 Jitter Meter : NO K
7009 01:35:53.458550 CBT Training : PASS
7010 01:35:53.460938 Write leveling : PASS
7011 01:35:53.464616 RX DQS gating : PASS
7012 01:35:53.465108 RX DQ/DQS(RDDQC) : PASS
7013 01:35:53.467946 TX DQ/DQS : PASS
7014 01:35:53.468525 RX DATLAT : PASS
7015 01:35:53.471564 RX DQ/DQS(Engine): PASS
7016 01:35:53.474980 TX OE : NO K
7017 01:35:53.475540 All Pass.
7018 01:35:53.475912
7019 01:35:53.476257 CH 0, Rank 1
7020 01:35:53.478167 SW Impedance : PASS
7021 01:35:53.481248 DUTY Scan : NO K
7022 01:35:53.481707 ZQ Calibration : PASS
7023 01:35:53.484390 Jitter Meter : NO K
7024 01:35:53.488622 CBT Training : PASS
7025 01:35:53.489249 Write leveling : NO K
7026 01:35:53.491637 RX DQS gating : PASS
7027 01:35:53.494967 RX DQ/DQS(RDDQC) : PASS
7028 01:35:53.495521 TX DQ/DQS : PASS
7029 01:35:53.497895 RX DATLAT : PASS
7030 01:35:53.502512 RX DQ/DQS(Engine): PASS
7031 01:35:53.503071 TX OE : NO K
7032 01:35:53.503444 All Pass.
7033 01:35:53.505084
7034 01:35:53.505548 CH 1, Rank 0
7035 01:35:53.508750 SW Impedance : PASS
7036 01:35:53.509348 DUTY Scan : NO K
7037 01:35:53.511460 ZQ Calibration : PASS
7038 01:35:53.512014 Jitter Meter : NO K
7039 01:35:53.514811 CBT Training : PASS
7040 01:35:53.518246 Write leveling : PASS
7041 01:35:53.518802 RX DQS gating : PASS
7042 01:35:53.521207 RX DQ/DQS(RDDQC) : PASS
7043 01:35:53.524643 TX DQ/DQS : PASS
7044 01:35:53.525250 RX DATLAT : PASS
7045 01:35:53.528112 RX DQ/DQS(Engine): PASS
7046 01:35:53.531299 TX OE : NO K
7047 01:35:53.531763 All Pass.
7048 01:35:53.532129
7049 01:35:53.532471 CH 1, Rank 1
7050 01:35:53.534794 SW Impedance : PASS
7051 01:35:53.537788 DUTY Scan : NO K
7052 01:35:53.538250 ZQ Calibration : PASS
7053 01:35:53.541359 Jitter Meter : NO K
7054 01:35:53.544665 CBT Training : PASS
7055 01:35:53.545393 Write leveling : NO K
7056 01:35:53.548570 RX DQS gating : PASS
7057 01:35:53.551532 RX DQ/DQS(RDDQC) : PASS
7058 01:35:53.552099 TX DQ/DQS : PASS
7059 01:35:53.554750 RX DATLAT : PASS
7060 01:35:53.555213 RX DQ/DQS(Engine): PASS
7061 01:35:53.557534 TX OE : NO K
7062 01:35:53.557996 All Pass.
7063 01:35:53.558363
7064 01:35:53.561210 DramC Write-DBI off
7065 01:35:53.564826 PER_BANK_REFRESH: Hybrid Mode
7066 01:35:53.565321 TX_TRACKING: ON
7067 01:35:53.574614 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7068 01:35:53.577946 [FAST_K] Save calibration result to emmc
7069 01:35:53.581122 dramc_set_vcore_voltage set vcore to 725000
7070 01:35:53.584902 Read voltage for 1600, 0
7071 01:35:53.585395 Vio18 = 0
7072 01:35:53.588242 Vcore = 725000
7073 01:35:53.588800 Vdram = 0
7074 01:35:53.589210 Vddq = 0
7075 01:35:53.589592 Vmddr = 0
7076 01:35:53.595400 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7077 01:35:53.597601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7078 01:35:53.601029 MEM_TYPE=3, freq_sel=13
7079 01:35:53.604325 sv_algorithm_assistance_LP4_3733
7080 01:35:53.608486 ============ PULL DRAM RESETB DOWN ============
7081 01:35:53.614700 ========== PULL DRAM RESETB DOWN end =========
7082 01:35:53.617453 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7083 01:35:53.621567 ===================================
7084 01:35:53.624590 LPDDR4 DRAM CONFIGURATION
7085 01:35:53.628087 ===================================
7086 01:35:53.628647 EX_ROW_EN[0] = 0x0
7087 01:35:53.631112 EX_ROW_EN[1] = 0x0
7088 01:35:53.631572 LP4Y_EN = 0x0
7089 01:35:53.635053 WORK_FSP = 0x1
7090 01:35:53.635609 WL = 0x5
7091 01:35:53.637689 RL = 0x5
7092 01:35:53.638150 BL = 0x2
7093 01:35:53.641278 RPST = 0x0
7094 01:35:53.641831 RD_PRE = 0x0
7095 01:35:53.644518 WR_PRE = 0x1
7096 01:35:53.645113 WR_PST = 0x1
7097 01:35:53.648065 DBI_WR = 0x0
7098 01:35:53.651171 DBI_RD = 0x0
7099 01:35:53.651635 OTF = 0x1
7100 01:35:53.654315 ===================================
7101 01:35:53.658360 ===================================
7102 01:35:53.658974 ANA top config
7103 01:35:53.660835 ===================================
7104 01:35:53.664780 DLL_ASYNC_EN = 0
7105 01:35:53.669327 ALL_SLAVE_EN = 0
7106 01:35:53.671767 NEW_RANK_MODE = 1
7107 01:35:53.672333 DLL_IDLE_MODE = 1
7108 01:35:53.674415 LP45_APHY_COMB_EN = 1
7109 01:35:53.677562 TX_ODT_DIS = 0
7110 01:35:53.681642 NEW_8X_MODE = 1
7111 01:35:53.684471 ===================================
7112 01:35:53.688402 ===================================
7113 01:35:53.691113 data_rate = 3200
7114 01:35:53.691682 CKR = 1
7115 01:35:53.695416 DQ_P2S_RATIO = 8
7116 01:35:53.698206 ===================================
7117 01:35:53.701559 CA_P2S_RATIO = 8
7118 01:35:53.705408 DQ_CA_OPEN = 0
7119 01:35:53.708127 DQ_SEMI_OPEN = 0
7120 01:35:53.711775 CA_SEMI_OPEN = 0
7121 01:35:53.712350 CA_FULL_RATE = 0
7122 01:35:53.714627 DQ_CKDIV4_EN = 0
7123 01:35:53.717942 CA_CKDIV4_EN = 0
7124 01:35:53.721610 CA_PREDIV_EN = 0
7125 01:35:53.725058 PH8_DLY = 12
7126 01:35:53.728065 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7127 01:35:53.728633 DQ_AAMCK_DIV = 4
7128 01:35:53.731925 CA_AAMCK_DIV = 4
7129 01:35:53.734660 CA_ADMCK_DIV = 4
7130 01:35:53.737966 DQ_TRACK_CA_EN = 0
7131 01:35:53.742041 CA_PICK = 1600
7132 01:35:53.745114 CA_MCKIO = 1600
7133 01:35:53.745675 MCKIO_SEMI = 0
7134 01:35:53.748287 PLL_FREQ = 3068
7135 01:35:53.751452 DQ_UI_PI_RATIO = 32
7136 01:35:53.754834 CA_UI_PI_RATIO = 0
7137 01:35:53.757866 ===================================
7138 01:35:53.761546 ===================================
7139 01:35:53.764673 memory_type:LPDDR4
7140 01:35:53.765229 GP_NUM : 10
7141 01:35:53.768597 SRAM_EN : 1
7142 01:35:53.772270 MD32_EN : 0
7143 01:35:53.774587 ===================================
7144 01:35:53.775163 [ANA_INIT] >>>>>>>>>>>>>>
7145 01:35:53.777993 <<<<<< [CONFIGURE PHASE]: ANA_TX
7146 01:35:53.781132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7147 01:35:53.784768 ===================================
7148 01:35:53.788734 data_rate = 3200,PCW = 0X7600
7149 01:35:53.791464 ===================================
7150 01:35:53.795457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7151 01:35:53.801531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 01:35:53.805044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 01:35:53.812077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7154 01:35:53.815001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7155 01:35:53.818089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7156 01:35:53.818554 [ANA_INIT] flow start
7157 01:35:53.821717 [ANA_INIT] PLL >>>>>>>>
7158 01:35:53.825106 [ANA_INIT] PLL <<<<<<<<
7159 01:35:53.825684 [ANA_INIT] MIDPI >>>>>>>>
7160 01:35:53.828091 [ANA_INIT] MIDPI <<<<<<<<
7161 01:35:53.831859 [ANA_INIT] DLL >>>>>>>>
7162 01:35:53.832453 [ANA_INIT] DLL <<<<<<<<
7163 01:35:53.835462 [ANA_INIT] flow end
7164 01:35:53.838072 ============ LP4 DIFF to SE enter ============
7165 01:35:53.841750 ============ LP4 DIFF to SE exit ============
7166 01:35:53.845178 [ANA_INIT] <<<<<<<<<<<<<
7167 01:35:53.848771 [Flow] Enable top DCM control >>>>>
7168 01:35:53.852156 [Flow] Enable top DCM control <<<<<
7169 01:35:53.855303 Enable DLL master slave shuffle
7170 01:35:53.861966 ==============================================================
7171 01:35:53.862538 Gating Mode config
7172 01:35:53.869197 ==============================================================
7173 01:35:53.869762 Config description:
7174 01:35:53.878636 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7175 01:35:53.884510 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7176 01:35:53.891165 SELPH_MODE 0: By rank 1: By Phase
7177 01:35:53.894844 ==============================================================
7178 01:35:53.898012 GAT_TRACK_EN = 1
7179 01:35:53.901455 RX_GATING_MODE = 2
7180 01:35:53.904904 RX_GATING_TRACK_MODE = 2
7181 01:35:53.908878 SELPH_MODE = 1
7182 01:35:53.911694 PICG_EARLY_EN = 1
7183 01:35:53.915288 VALID_LAT_VALUE = 1
7184 01:35:53.922166 ==============================================================
7185 01:35:53.925430 Enter into Gating configuration >>>>
7186 01:35:53.928239 Exit from Gating configuration <<<<
7187 01:35:53.931898 Enter into DVFS_PRE_config >>>>>
7188 01:35:53.941172 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7189 01:35:53.944609 Exit from DVFS_PRE_config <<<<<
7190 01:35:53.948119 Enter into PICG configuration >>>>
7191 01:35:53.951449 Exit from PICG configuration <<<<
7192 01:35:53.954895 [RX_INPUT] configuration >>>>>
7193 01:35:53.955396 [RX_INPUT] configuration <<<<<
7194 01:35:53.961749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7195 01:35:53.964488 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7196 01:35:53.971900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 01:35:53.977951 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 01:35:53.984472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 01:35:53.991697 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 01:35:53.994948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7201 01:35:53.999053 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7202 01:35:54.001350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7203 01:35:54.009461 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7204 01:35:54.011398 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7205 01:35:54.014831 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 01:35:54.018093 ===================================
7207 01:35:54.021345 LPDDR4 DRAM CONFIGURATION
7208 01:35:54.024595 ===================================
7209 01:35:54.028060 EX_ROW_EN[0] = 0x0
7210 01:35:54.028521 EX_ROW_EN[1] = 0x0
7211 01:35:54.031564 LP4Y_EN = 0x0
7212 01:35:54.032125 WORK_FSP = 0x1
7213 01:35:54.034734 WL = 0x5
7214 01:35:54.035196 RL = 0x5
7215 01:35:54.040333 BL = 0x2
7216 01:35:54.040893 RPST = 0x0
7217 01:35:54.041943 RD_PRE = 0x0
7218 01:35:54.042402 WR_PRE = 0x1
7219 01:35:54.045020 WR_PST = 0x1
7220 01:35:54.045582 DBI_WR = 0x0
7221 01:35:54.049314 DBI_RD = 0x0
7222 01:35:54.049867 OTF = 0x1
7223 01:35:54.051317 ===================================
7224 01:35:54.058750 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7225 01:35:54.062522 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7226 01:35:54.065166 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 01:35:54.068191 ===================================
7228 01:35:54.071489 LPDDR4 DRAM CONFIGURATION
7229 01:35:54.075256 ===================================
7230 01:35:54.075775 EX_ROW_EN[0] = 0x10
7231 01:35:54.078151 EX_ROW_EN[1] = 0x0
7232 01:35:54.081146 LP4Y_EN = 0x0
7233 01:35:54.081564 WORK_FSP = 0x1
7234 01:35:54.084678 WL = 0x5
7235 01:35:54.085139 RL = 0x5
7236 01:35:54.088061 BL = 0x2
7237 01:35:54.088588 RPST = 0x0
7238 01:35:54.091479 RD_PRE = 0x0
7239 01:35:54.091926 WR_PRE = 0x1
7240 01:35:54.094644 WR_PST = 0x1
7241 01:35:54.095157 DBI_WR = 0x0
7242 01:35:54.098238 DBI_RD = 0x0
7243 01:35:54.098751 OTF = 0x1
7244 01:35:54.102139 ===================================
7245 01:35:54.107905 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7246 01:35:54.108324 ==
7247 01:35:54.111662 Dram Type= 6, Freq= 0, CH_0, rank 0
7248 01:35:54.115132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7249 01:35:54.115650 ==
7250 01:35:54.118284 [Duty_Offset_Calibration]
7251 01:35:54.121379 B0:2 B1:-1 CA:1
7252 01:35:54.121797
7253 01:35:54.124580 [DutyScan_Calibration_Flow] k_type=0
7254 01:35:54.132701
7255 01:35:54.133462 ==CLK 0==
7256 01:35:54.136202 Final CLK duty delay cell = -4
7257 01:35:54.139234 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7258 01:35:54.142380 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7259 01:35:54.146174 [-4] AVG Duty = 4937%(X100)
7260 01:35:54.146598
7261 01:35:54.149600 CH0 CLK Duty spec in!! Max-Min= 187%
7262 01:35:54.153335 [DutyScan_Calibration_Flow] ====Done====
7263 01:35:54.153756
7264 01:35:54.156385 [DutyScan_Calibration_Flow] k_type=1
7265 01:35:54.171909
7266 01:35:54.172339 ==DQS 0 ==
7267 01:35:54.175183 Final DQS duty delay cell = 0
7268 01:35:54.178900 [0] MAX Duty = 5125%(X100), DQS PI = 56
7269 01:35:54.181733 [0] MIN Duty = 5000%(X100), DQS PI = 16
7270 01:35:54.185141 [0] AVG Duty = 5062%(X100)
7271 01:35:54.185731
7272 01:35:54.186088 ==DQS 1 ==
7273 01:35:54.188711 Final DQS duty delay cell = -4
7274 01:35:54.192437 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7275 01:35:54.195254 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7276 01:35:54.199744 [-4] AVG Duty = 5046%(X100)
7277 01:35:54.200164
7278 01:35:54.201872 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7279 01:35:54.202297
7280 01:35:54.205470 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7281 01:35:54.208961 [DutyScan_Calibration_Flow] ====Done====
7282 01:35:54.209511
7283 01:35:54.212105 [DutyScan_Calibration_Flow] k_type=3
7284 01:35:54.230432
7285 01:35:54.231003 ==DQM 0 ==
7286 01:35:54.233566 Final DQM duty delay cell = 0
7287 01:35:54.236700 [0] MAX Duty = 5000%(X100), DQS PI = 20
7288 01:35:54.239445 [0] MIN Duty = 4875%(X100), DQS PI = 4
7289 01:35:54.240040 [0] AVG Duty = 4937%(X100)
7290 01:35:54.243443
7291 01:35:54.243907 ==DQM 1 ==
7292 01:35:54.245872 Final DQM duty delay cell = 0
7293 01:35:54.249494 [0] MAX Duty = 5187%(X100), DQS PI = 58
7294 01:35:54.252624 [0] MIN Duty = 4969%(X100), DQS PI = 20
7295 01:35:54.253112 [0] AVG Duty = 5078%(X100)
7296 01:35:54.256056
7297 01:35:54.259855 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7298 01:35:54.260274
7299 01:35:54.262464 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7300 01:35:54.265859 [DutyScan_Calibration_Flow] ====Done====
7301 01:35:54.266281
7302 01:35:54.269253 [DutyScan_Calibration_Flow] k_type=2
7303 01:35:54.286233
7304 01:35:54.286738 ==DQ 0 ==
7305 01:35:54.289774 Final DQ duty delay cell = 0
7306 01:35:54.292741 [0] MAX Duty = 5156%(X100), DQS PI = 0
7307 01:35:54.296136 [0] MIN Duty = 5031%(X100), DQS PI = 10
7308 01:35:54.296551 [0] AVG Duty = 5093%(X100)
7309 01:35:54.296880
7310 01:35:54.299854 ==DQ 1 ==
7311 01:35:54.302985 Final DQ duty delay cell = 0
7312 01:35:54.306352 [0] MAX Duty = 5031%(X100), DQS PI = 30
7313 01:35:54.310315 [0] MIN Duty = 4907%(X100), DQS PI = 18
7314 01:35:54.310931 [0] AVG Duty = 4969%(X100)
7315 01:35:54.311292
7316 01:35:54.313078 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7317 01:35:54.316242
7318 01:35:54.319279 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7319 01:35:54.322791 [DutyScan_Calibration_Flow] ====Done====
7320 01:35:54.323210 ==
7321 01:35:54.326618 Dram Type= 6, Freq= 0, CH_1, rank 0
7322 01:35:54.329750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 01:35:54.330166 ==
7324 01:35:54.333070 [Duty_Offset_Calibration]
7325 01:35:54.333484 B0:1 B1:1 CA:2
7326 01:35:54.333818
7327 01:35:54.336323 [DutyScan_Calibration_Flow] k_type=0
7328 01:35:54.346571
7329 01:35:54.347282 ==CLK 0==
7330 01:35:54.350374 Final CLK duty delay cell = 0
7331 01:35:54.353134 [0] MAX Duty = 5156%(X100), DQS PI = 24
7332 01:35:54.356798 [0] MIN Duty = 4938%(X100), DQS PI = 50
7333 01:35:54.357257 [0] AVG Duty = 5047%(X100)
7334 01:35:54.360184
7335 01:35:54.362980 CH1 CLK Duty spec in!! Max-Min= 218%
7336 01:35:54.366355 [DutyScan_Calibration_Flow] ====Done====
7337 01:35:54.366771
7338 01:35:54.370336 [DutyScan_Calibration_Flow] k_type=1
7339 01:35:54.386421
7340 01:35:54.386976 ==DQS 0 ==
7341 01:35:54.390751 Final DQS duty delay cell = 0
7342 01:35:54.393512 [0] MAX Duty = 5031%(X100), DQS PI = 20
7343 01:35:54.396053 [0] MIN Duty = 4813%(X100), DQS PI = 50
7344 01:35:54.399555 [0] AVG Duty = 4922%(X100)
7345 01:35:54.399969
7346 01:35:54.400298 ==DQS 1 ==
7347 01:35:54.403335 Final DQS duty delay cell = 0
7348 01:35:54.405971 [0] MAX Duty = 5031%(X100), DQS PI = 56
7349 01:35:54.409871 [0] MIN Duty = 4938%(X100), DQS PI = 12
7350 01:35:54.412843 [0] AVG Duty = 4984%(X100)
7351 01:35:54.413294
7352 01:35:54.416838 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7353 01:35:54.417446
7354 01:35:54.419475 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7355 01:35:54.423434 [DutyScan_Calibration_Flow] ====Done====
7356 01:35:54.423945
7357 01:35:54.426445 [DutyScan_Calibration_Flow] k_type=3
7358 01:35:54.443766
7359 01:35:54.444323 ==DQM 0 ==
7360 01:35:54.447225 Final DQM duty delay cell = 0
7361 01:35:54.449558 [0] MAX Duty = 5156%(X100), DQS PI = 20
7362 01:35:54.453087 [0] MIN Duty = 4813%(X100), DQS PI = 50
7363 01:35:54.456260 [0] AVG Duty = 4984%(X100)
7364 01:35:54.456727
7365 01:35:54.457146 ==DQM 1 ==
7366 01:35:54.460086 Final DQM duty delay cell = 0
7367 01:35:54.463420 [0] MAX Duty = 5156%(X100), DQS PI = 60
7368 01:35:54.466435 [0] MIN Duty = 4875%(X100), DQS PI = 20
7369 01:35:54.469804 [0] AVG Duty = 5015%(X100)
7370 01:35:54.470355
7371 01:35:54.473829 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7372 01:35:54.474291
7373 01:35:54.476657 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7374 01:35:54.479727 [DutyScan_Calibration_Flow] ====Done====
7375 01:35:54.480285
7376 01:35:54.483113 [DutyScan_Calibration_Flow] k_type=2
7377 01:35:54.500327
7378 01:35:54.501118 ==DQ 0 ==
7379 01:35:54.504106 Final DQ duty delay cell = 0
7380 01:35:54.507015 [0] MAX Duty = 5156%(X100), DQS PI = 20
7381 01:35:54.510209 [0] MIN Duty = 4907%(X100), DQS PI = 52
7382 01:35:54.510766 [0] AVG Duty = 5031%(X100)
7383 01:35:54.513673
7384 01:35:54.514224 ==DQ 1 ==
7385 01:35:54.517519 Final DQ duty delay cell = 0
7386 01:35:54.519995 [0] MAX Duty = 5093%(X100), DQS PI = 8
7387 01:35:54.523280 [0] MIN Duty = 5031%(X100), DQS PI = 0
7388 01:35:54.523740 [0] AVG Duty = 5062%(X100)
7389 01:35:54.524117
7390 01:35:54.526425 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7391 01:35:54.526884
7392 01:35:54.530036 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7393 01:35:54.536300 [DutyScan_Calibration_Flow] ====Done====
7394 01:35:54.540281 nWR fixed to 30
7395 01:35:54.540858 [ModeRegInit_LP4] CH0 RK0
7396 01:35:54.543879 [ModeRegInit_LP4] CH0 RK1
7397 01:35:54.546522 [ModeRegInit_LP4] CH1 RK0
7398 01:35:54.546982 [ModeRegInit_LP4] CH1 RK1
7399 01:35:54.549581 match AC timing 5
7400 01:35:54.553929 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7401 01:35:54.556757 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7402 01:35:54.564272 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7403 01:35:54.566574 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7404 01:35:54.573234 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7405 01:35:54.573787 [MiockJmeterHQA]
7406 01:35:54.574178
7407 01:35:54.577146 [DramcMiockJmeter] u1RxGatingPI = 0
7408 01:35:54.579746 0 : 4368, 4140
7409 01:35:54.580299 4 : 4257, 4030
7410 01:35:54.580675 8 : 4260, 4032
7411 01:35:54.584076 12 : 4255, 4027
7412 01:35:54.584632 16 : 4255, 4029
7413 01:35:54.585925 20 : 4257, 4029
7414 01:35:54.586390 24 : 4368, 4140
7415 01:35:54.589692 28 : 4253, 4027
7416 01:35:54.590252 32 : 4366, 4139
7417 01:35:54.590625 36 : 4255, 4029
7418 01:35:54.593489 40 : 4255, 4030
7419 01:35:54.594054 44 : 4363, 4137
7420 01:35:54.596179 48 : 4253, 4026
7421 01:35:54.596643 52 : 4252, 4027
7422 01:35:54.600279 56 : 4252, 4027
7423 01:35:54.600848 60 : 4252, 4027
7424 01:35:54.603897 64 : 4360, 4137
7425 01:35:54.604657 68 : 4252, 4029
7426 01:35:54.605105 72 : 4361, 4137
7427 01:35:54.605858 76 : 4252, 4030
7428 01:35:54.606366 80 : 4360, 4138
7429 01:35:54.609666 84 : 4250, 4026
7430 01:35:54.610133 88 : 4250, 4027
7431 01:35:54.613214 92 : 4255, 4029
7432 01:35:54.613766 96 : 4361, 3589
7433 01:35:54.616240 100 : 4255, 0
7434 01:35:54.616802 104 : 4255, 0
7435 01:35:54.617216 108 : 4250, 0
7436 01:35:54.619653 112 : 4255, 0
7437 01:35:54.620215 116 : 4252, 0
7438 01:35:54.620587 120 : 4250, 0
7439 01:35:54.622890 124 : 4365, 0
7440 01:35:54.623357 128 : 4250, 0
7441 01:35:54.626656 132 : 4249, 0
7442 01:35:54.627215 136 : 4252, 0
7443 01:35:54.627588 140 : 4253, 0
7444 01:35:54.630464 144 : 4363, 0
7445 01:35:54.631028 148 : 4363, 0
7446 01:35:54.633472 152 : 4248, 0
7447 01:35:54.634036 156 : 4252, 0
7448 01:35:54.634408 160 : 4253, 0
7449 01:35:54.636079 164 : 4360, 0
7450 01:35:54.636728 168 : 4250, 0
7451 01:35:54.637275 172 : 4254, 0
7452 01:35:54.640181 176 : 4250, 0
7453 01:35:54.640747 180 : 4250, 0
7454 01:35:54.642803 184 : 4250, 0
7455 01:35:54.643377 188 : 4253, 0
7456 01:35:54.643750 192 : 4252, 0
7457 01:35:54.645871 196 : 4360, 0
7458 01:35:54.646337 200 : 4361, 0
7459 01:35:54.650470 204 : 4361, 0
7460 01:35:54.651075 208 : 4255, 0
7461 01:35:54.651471 212 : 4253, 23
7462 01:35:54.652754 216 : 4253, 3062
7463 01:35:54.653331 220 : 4253, 4029
7464 01:35:54.655613 224 : 4361, 4137
7465 01:35:54.656078 228 : 4252, 4029
7466 01:35:54.659101 232 : 4253, 4029
7467 01:35:54.659715 236 : 4363, 4140
7468 01:35:54.662480 240 : 4360, 4137
7469 01:35:54.662942 244 : 4250, 4026
7470 01:35:54.666459 248 : 4250, 4027
7471 01:35:54.667135 252 : 4252, 4029
7472 01:35:54.669545 256 : 4250, 4027
7473 01:35:54.670145 260 : 4361, 4137
7474 01:35:54.670525 264 : 4250, 4026
7475 01:35:54.673508 268 : 4250, 4027
7476 01:35:54.673929 272 : 4361, 4137
7477 01:35:54.676899 276 : 4250, 4027
7478 01:35:54.677457 280 : 4361, 4137
7479 01:35:54.679776 284 : 4252, 4029
7480 01:35:54.680298 288 : 4252, 4029
7481 01:35:54.683168 292 : 4365, 4139
7482 01:35:54.683587 296 : 4363, 4140
7483 01:35:54.685804 300 : 4255, 4029
7484 01:35:54.686227 304 : 4363, 4140
7485 01:35:54.689952 308 : 4250, 4027
7486 01:35:54.690473 312 : 4252, 4030
7487 01:35:54.690812 316 : 4360, 4137
7488 01:35:54.693692 320 : 4252, 4029
7489 01:35:54.694111 324 : 4250, 4027
7490 01:35:54.696758 328 : 4253, 4029
7491 01:35:54.697317 332 : 4252, 3306
7492 01:35:54.699389 336 : 4250, 221
7493 01:35:54.699936
7494 01:35:54.703026 MIOCK jitter meter ch=0
7495 01:35:54.703544
7496 01:35:54.703878 1T = (336-100) = 236 dly cells
7497 01:35:54.711018 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7498 01:35:54.711539 ==
7499 01:35:54.713168 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 01:35:54.716257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 01:35:54.716769 ==
7502 01:35:54.722853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 01:35:54.726103 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 01:35:54.732818 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 01:35:54.736638 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 01:35:54.746659 [CA 0] Center 45 (15~75) winsize 61
7507 01:35:54.750326 [CA 1] Center 44 (13~75) winsize 63
7508 01:35:54.753701 [CA 2] Center 40 (11~69) winsize 59
7509 01:35:54.756405 [CA 3] Center 39 (10~69) winsize 60
7510 01:35:54.760011 [CA 4] Center 37 (8~67) winsize 60
7511 01:35:54.763354 [CA 5] Center 37 (7~67) winsize 61
7512 01:35:54.763930
7513 01:35:54.766366 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 01:35:54.766826
7515 01:35:54.773330 [CATrainingPosCal] consider 1 rank data
7516 01:35:54.773893 u2DelayCellTimex100 = 275/100 ps
7517 01:35:54.779639 CA0 delay=45 (15~75),Diff = 8 PI (28 cell)
7518 01:35:54.783076 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7519 01:35:54.787038 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7520 01:35:54.789260 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7521 01:35:54.793095 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7522 01:35:54.796387 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7523 01:35:54.796944
7524 01:35:54.799781 CA PerBit enable=1, Macro0, CA PI delay=37
7525 01:35:54.800339
7526 01:35:54.803065 [CBTSetCACLKResult] CA Dly = 37
7527 01:35:54.806198 CS Dly: 11 (0~42)
7528 01:35:54.809434 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 01:35:54.813121 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 01:35:54.813690 ==
7531 01:35:54.816155 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 01:35:54.819851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 01:35:54.823552 ==
7534 01:35:54.826873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 01:35:54.830151 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 01:35:54.836386 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 01:35:54.842885 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 01:35:54.850716 [CA 0] Center 44 (14~75) winsize 62
7539 01:35:54.853984 [CA 1] Center 44 (14~75) winsize 62
7540 01:35:54.857680 [CA 2] Center 39 (10~69) winsize 60
7541 01:35:54.860562 [CA 3] Center 39 (10~69) winsize 60
7542 01:35:54.863820 [CA 4] Center 38 (8~68) winsize 61
7543 01:35:54.868224 [CA 5] Center 37 (7~67) winsize 61
7544 01:35:54.868777
7545 01:35:54.870545 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 01:35:54.871146
7547 01:35:54.873460 [CATrainingPosCal] consider 2 rank data
7548 01:35:54.877605 u2DelayCellTimex100 = 275/100 ps
7549 01:35:54.881051 CA0 delay=45 (15~75),Diff = 8 PI (28 cell)
7550 01:35:54.886899 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7551 01:35:54.891271 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7552 01:35:54.893549 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7553 01:35:54.897781 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7554 01:35:54.900615 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7555 01:35:54.901247
7556 01:35:54.903544 CA PerBit enable=1, Macro0, CA PI delay=37
7557 01:35:54.903971
7558 01:35:54.907041 [CBTSetCACLKResult] CA Dly = 37
7559 01:35:54.910474 CS Dly: 12 (0~44)
7560 01:35:54.913999 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 01:35:54.916762 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 01:35:54.917255
7563 01:35:54.920463 ----->DramcWriteLeveling(PI) begin...
7564 01:35:54.920927 ==
7565 01:35:54.924388 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 01:35:54.931125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 01:35:54.931680 ==
7568 01:35:54.933548 Write leveling (Byte 0): 31 => 31
7569 01:35:54.934006 Write leveling (Byte 1): 27 => 27
7570 01:35:54.937264 DramcWriteLeveling(PI) end<-----
7571 01:35:54.937723
7572 01:35:54.938084 ==
7573 01:35:54.940105 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 01:35:54.947131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 01:35:54.947695 ==
7576 01:35:54.950710 [Gating] SW mode calibration
7577 01:35:54.957384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 01:35:54.960123 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 01:35:54.967650 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 01:35:54.970424 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 01:35:54.974594 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 01:35:54.979981 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 01:35:54.983656 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7584 01:35:54.986553 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7585 01:35:54.990801 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7586 01:35:54.996850 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 01:35:55.000833 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 01:35:55.003676 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 01:35:55.010615 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 01:35:55.014656 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 01:35:55.016798 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7592 01:35:55.024104 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7593 01:35:55.026819 1 5 24 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7594 01:35:55.030272 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 01:35:55.036808 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 01:35:55.041688 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 01:35:55.043486 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 01:35:55.051011 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 01:35:55.053838 1 6 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7600 01:35:55.057552 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7601 01:35:55.064258 1 6 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7602 01:35:55.067451 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 01:35:55.070272 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 01:35:55.074421 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 01:35:55.081635 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 01:35:55.084024 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 01:35:55.086958 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7608 01:35:55.093940 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7609 01:35:55.097267 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7610 01:35:55.100321 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 01:35:55.107487 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 01:35:55.111309 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 01:35:55.113899 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 01:35:55.120477 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 01:35:55.123735 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 01:35:55.127192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 01:35:55.135175 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 01:35:55.138451 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 01:35:55.140398 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 01:35:55.148518 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 01:35:55.151938 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 01:35:55.154212 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 01:35:55.157580 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7624 01:35:55.163742 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7625 01:35:55.168288 Total UI for P1: 0, mck2ui 16
7626 01:35:55.170878 best dqsien dly found for B0: ( 1, 9, 16)
7627 01:35:55.174336 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 01:35:55.177376 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 01:35:55.180214 Total UI for P1: 0, mck2ui 16
7630 01:35:55.184413 best dqsien dly found for B1: ( 1, 9, 20)
7631 01:35:55.187053 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7632 01:35:55.191437 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7633 01:35:55.192003
7634 01:35:55.197640 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7635 01:35:55.200913 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7636 01:35:55.203893 [Gating] SW calibration Done
7637 01:35:55.204354 ==
7638 01:35:55.207246 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 01:35:55.211023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 01:35:55.211609 ==
7641 01:35:55.211984 RX Vref Scan: 0
7642 01:35:55.212319
7643 01:35:55.214584 RX Vref 0 -> 0, step: 1
7644 01:35:55.215040
7645 01:35:55.217473 RX Delay 0 -> 252, step: 8
7646 01:35:55.221217 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7647 01:35:55.224769 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7648 01:35:55.227684 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7649 01:35:55.234249 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7650 01:35:55.237754 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7651 01:35:55.241328 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7652 01:35:55.244201 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7653 01:35:55.248326 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7654 01:35:55.251097 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7655 01:35:55.257868 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7656 01:35:55.261050 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7657 01:35:55.264709 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7658 01:35:55.268062 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7659 01:35:55.273927 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7660 01:35:55.277332 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7661 01:35:55.281044 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7662 01:35:55.281605 ==
7663 01:35:55.284481 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 01:35:55.287961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 01:35:55.288516 ==
7666 01:35:55.291189 DQS Delay:
7667 01:35:55.291736 DQS0 = 0, DQS1 = 0
7668 01:35:55.294592 DQM Delay:
7669 01:35:55.295043 DQM0 = 132, DQM1 = 125
7670 01:35:55.295406 DQ Delay:
7671 01:35:55.301918 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7672 01:35:55.304170 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7673 01:35:55.307522 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =123
7674 01:35:55.310658 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7675 01:35:55.311213
7676 01:35:55.311582
7677 01:35:55.311920 ==
7678 01:35:55.315200 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 01:35:55.317892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 01:35:55.318422 ==
7681 01:35:55.318793
7682 01:35:55.319133
7683 01:35:55.320574 TX Vref Scan disable
7684 01:35:55.323996 == TX Byte 0 ==
7685 01:35:55.328777 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7686 01:35:55.331094 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7687 01:35:55.334228 == TX Byte 1 ==
7688 01:35:55.337886 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7689 01:35:55.341124 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7690 01:35:55.341681 ==
7691 01:35:55.344312 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 01:35:55.347139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 01:35:55.350402 ==
7694 01:35:55.362433
7695 01:35:55.365661 TX Vref early break, caculate TX vref
7696 01:35:55.369102 TX Vref=16, minBit 0, minWin=22, winSum=359
7697 01:35:55.372377 TX Vref=18, minBit 0, minWin=22, winSum=370
7698 01:35:55.376306 TX Vref=20, minBit 0, minWin=22, winSum=379
7699 01:35:55.379000 TX Vref=22, minBit 7, minWin=22, winSum=387
7700 01:35:55.382442 TX Vref=24, minBit 1, minWin=24, winSum=404
7701 01:35:55.386151 TX Vref=26, minBit 1, minWin=25, winSum=412
7702 01:35:55.393186 TX Vref=28, minBit 1, minWin=26, winSum=422
7703 01:35:55.396165 TX Vref=30, minBit 3, minWin=25, winSum=419
7704 01:35:55.398943 TX Vref=32, minBit 3, minWin=24, winSum=407
7705 01:35:55.402866 TX Vref=34, minBit 3, minWin=24, winSum=397
7706 01:35:55.408804 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 28
7707 01:35:55.409386
7708 01:35:55.412680 Final TX Range 0 Vref 28
7709 01:35:55.413271
7710 01:35:55.413636 ==
7711 01:35:55.415955 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 01:35:55.419360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 01:35:55.419926 ==
7714 01:35:55.420300
7715 01:35:55.420642
7716 01:35:55.422372 TX Vref Scan disable
7717 01:35:55.428862 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7718 01:35:55.429455 == TX Byte 0 ==
7719 01:35:55.432879 u2DelayCellOfst[0]=14 cells (4 PI)
7720 01:35:55.435782 u2DelayCellOfst[1]=17 cells (5 PI)
7721 01:35:55.439117 u2DelayCellOfst[2]=10 cells (3 PI)
7722 01:35:55.443453 u2DelayCellOfst[3]=14 cells (4 PI)
7723 01:35:55.445513 u2DelayCellOfst[4]=7 cells (2 PI)
7724 01:35:55.448822 u2DelayCellOfst[5]=0 cells (0 PI)
7725 01:35:55.449380 u2DelayCellOfst[6]=21 cells (6 PI)
7726 01:35:55.452195 u2DelayCellOfst[7]=17 cells (5 PI)
7727 01:35:55.459320 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7728 01:35:55.461791 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7729 01:35:55.462269 == TX Byte 1 ==
7730 01:35:55.465679 u2DelayCellOfst[8]=0 cells (0 PI)
7731 01:35:55.468765 u2DelayCellOfst[9]=3 cells (1 PI)
7732 01:35:55.472530 u2DelayCellOfst[10]=7 cells (2 PI)
7733 01:35:55.475900 u2DelayCellOfst[11]=0 cells (0 PI)
7734 01:35:55.479428 u2DelayCellOfst[12]=14 cells (4 PI)
7735 01:35:55.482619 u2DelayCellOfst[13]=10 cells (3 PI)
7736 01:35:55.485582 u2DelayCellOfst[14]=14 cells (4 PI)
7737 01:35:55.489241 u2DelayCellOfst[15]=14 cells (4 PI)
7738 01:35:55.492198 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7739 01:35:55.495497 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7740 01:35:55.498713 DramC Write-DBI on
7741 01:35:55.499127 ==
7742 01:35:55.502910 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 01:35:55.505618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 01:35:55.506049 ==
7745 01:35:55.506487
7746 01:35:55.506927
7747 01:35:55.508968 TX Vref Scan disable
7748 01:35:55.512017 == TX Byte 0 ==
7749 01:35:55.515422 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7750 01:35:55.519306 == TX Byte 1 ==
7751 01:35:55.522453 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7752 01:35:55.522990 DramC Write-DBI off
7753 01:35:55.523429
7754 01:35:55.525902 [DATLAT]
7755 01:35:55.526330 Freq=1600, CH0 RK0
7756 01:35:55.526874
7757 01:35:55.529091 DATLAT Default: 0xf
7758 01:35:55.529677 0, 0xFFFF, sum = 0
7759 01:35:55.532170 1, 0xFFFF, sum = 0
7760 01:35:55.532636 2, 0xFFFF, sum = 0
7761 01:35:55.535501 3, 0xFFFF, sum = 0
7762 01:35:55.536017 4, 0xFFFF, sum = 0
7763 01:35:55.538905 5, 0xFFFF, sum = 0
7764 01:35:55.539367 6, 0xFFFF, sum = 0
7765 01:35:55.543349 7, 0xFFFF, sum = 0
7766 01:35:55.543772 8, 0xFFFF, sum = 0
7767 01:35:55.545892 9, 0xFFFF, sum = 0
7768 01:35:55.546312 10, 0xFFFF, sum = 0
7769 01:35:55.549068 11, 0xFFFF, sum = 0
7770 01:35:55.552276 12, 0xFFFF, sum = 0
7771 01:35:55.552763 13, 0xFFFF, sum = 0
7772 01:35:55.555574 14, 0x0, sum = 1
7773 01:35:55.555994 15, 0x0, sum = 2
7774 01:35:55.556324 16, 0x0, sum = 3
7775 01:35:55.558776 17, 0x0, sum = 4
7776 01:35:55.559382 best_step = 15
7777 01:35:55.559752
7778 01:35:55.560080 ==
7779 01:35:55.562508 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 01:35:55.569862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 01:35:55.570586 ==
7782 01:35:55.571065 RX Vref Scan: 1
7783 01:35:55.571389
7784 01:35:55.572230 Set Vref Range= 24 -> 127
7785 01:35:55.572642
7786 01:35:55.575891 RX Vref 24 -> 127, step: 1
7787 01:35:55.576303
7788 01:35:55.579497 RX Delay 11 -> 252, step: 4
7789 01:35:55.579915
7790 01:35:55.582441 Set Vref, RX VrefLevel [Byte0]: 24
7791 01:35:55.585594 [Byte1]: 24
7792 01:35:55.586008
7793 01:35:55.589379 Set Vref, RX VrefLevel [Byte0]: 25
7794 01:35:55.593236 [Byte1]: 25
7795 01:35:55.593686
7796 01:35:55.595452 Set Vref, RX VrefLevel [Byte0]: 26
7797 01:35:55.598821 [Byte1]: 26
7798 01:35:55.599235
7799 01:35:55.602450 Set Vref, RX VrefLevel [Byte0]: 27
7800 01:35:55.605430 [Byte1]: 27
7801 01:35:55.609917
7802 01:35:55.610329 Set Vref, RX VrefLevel [Byte0]: 28
7803 01:35:55.612852 [Byte1]: 28
7804 01:35:55.617713
7805 01:35:55.618125 Set Vref, RX VrefLevel [Byte0]: 29
7806 01:35:55.621153 [Byte1]: 29
7807 01:35:55.624863
7808 01:35:55.625310 Set Vref, RX VrefLevel [Byte0]: 30
7809 01:35:55.628195 [Byte1]: 30
7810 01:35:55.632558
7811 01:35:55.632971 Set Vref, RX VrefLevel [Byte0]: 31
7812 01:35:55.637533 [Byte1]: 31
7813 01:35:55.640550
7814 01:35:55.640960 Set Vref, RX VrefLevel [Byte0]: 32
7815 01:35:55.643407 [Byte1]: 32
7816 01:35:55.648058
7817 01:35:55.648473 Set Vref, RX VrefLevel [Byte0]: 33
7818 01:35:55.651022 [Byte1]: 33
7819 01:35:55.656084
7820 01:35:55.656504 Set Vref, RX VrefLevel [Byte0]: 34
7821 01:35:55.658370 [Byte1]: 34
7822 01:35:55.663020
7823 01:35:55.663452 Set Vref, RX VrefLevel [Byte0]: 35
7824 01:35:55.666764 [Byte1]: 35
7825 01:35:55.670485
7826 01:35:55.670907 Set Vref, RX VrefLevel [Byte0]: 36
7827 01:35:55.674881 [Byte1]: 36
7828 01:35:55.678403
7829 01:35:55.678854 Set Vref, RX VrefLevel [Byte0]: 37
7830 01:35:55.681363 [Byte1]: 37
7831 01:35:55.686042
7832 01:35:55.686560 Set Vref, RX VrefLevel [Byte0]: 38
7833 01:35:55.689762 [Byte1]: 38
7834 01:35:55.693262
7835 01:35:55.693676 Set Vref, RX VrefLevel [Byte0]: 39
7836 01:35:55.696776 [Byte1]: 39
7837 01:35:55.700826
7838 01:35:55.701296 Set Vref, RX VrefLevel [Byte0]: 40
7839 01:35:55.707695 [Byte1]: 40
7840 01:35:55.708152
7841 01:35:55.710897 Set Vref, RX VrefLevel [Byte0]: 41
7842 01:35:55.714058 [Byte1]: 41
7843 01:35:55.714478
7844 01:35:55.718213 Set Vref, RX VrefLevel [Byte0]: 42
7845 01:35:55.720861 [Byte1]: 42
7846 01:35:55.721361
7847 01:35:55.724432 Set Vref, RX VrefLevel [Byte0]: 43
7848 01:35:55.727303 [Byte1]: 43
7849 01:35:55.731369
7850 01:35:55.731780 Set Vref, RX VrefLevel [Byte0]: 44
7851 01:35:55.735025 [Byte1]: 44
7852 01:35:55.739297
7853 01:35:55.739710 Set Vref, RX VrefLevel [Byte0]: 45
7854 01:35:55.742399 [Byte1]: 45
7855 01:35:55.746821
7856 01:35:55.747233 Set Vref, RX VrefLevel [Byte0]: 46
7857 01:35:55.749625 [Byte1]: 46
7858 01:35:55.754595
7859 01:35:55.755119 Set Vref, RX VrefLevel [Byte0]: 47
7860 01:35:55.757835 [Byte1]: 47
7861 01:35:55.762084
7862 01:35:55.762497 Set Vref, RX VrefLevel [Byte0]: 48
7863 01:35:55.765764 [Byte1]: 48
7864 01:35:55.769656
7865 01:35:55.770209 Set Vref, RX VrefLevel [Byte0]: 49
7866 01:35:55.773442 [Byte1]: 49
7867 01:35:55.777031
7868 01:35:55.777488 Set Vref, RX VrefLevel [Byte0]: 50
7869 01:35:55.780305 [Byte1]: 50
7870 01:35:55.784482
7871 01:35:55.784895 Set Vref, RX VrefLevel [Byte0]: 51
7872 01:35:55.788371 [Byte1]: 51
7873 01:35:55.792231
7874 01:35:55.792646 Set Vref, RX VrefLevel [Byte0]: 52
7875 01:35:55.796333 [Byte1]: 52
7876 01:35:55.800453
7877 01:35:55.800971 Set Vref, RX VrefLevel [Byte0]: 53
7878 01:35:55.803226 [Byte1]: 53
7879 01:35:55.807366
7880 01:35:55.807877 Set Vref, RX VrefLevel [Byte0]: 54
7881 01:35:55.811883 [Byte1]: 54
7882 01:35:55.815036
7883 01:35:55.815463 Set Vref, RX VrefLevel [Byte0]: 55
7884 01:35:55.819110 [Byte1]: 55
7885 01:35:55.822935
7886 01:35:55.823354 Set Vref, RX VrefLevel [Byte0]: 56
7887 01:35:55.825887 [Byte1]: 56
7888 01:35:55.831078
7889 01:35:55.831592 Set Vref, RX VrefLevel [Byte0]: 57
7890 01:35:55.833895 [Byte1]: 57
7891 01:35:55.838700
7892 01:35:55.839110 Set Vref, RX VrefLevel [Byte0]: 58
7893 01:35:55.841769 [Byte1]: 58
7894 01:35:55.845516
7895 01:35:55.845930 Set Vref, RX VrefLevel [Byte0]: 59
7896 01:35:55.848709 [Byte1]: 59
7897 01:35:55.853163
7898 01:35:55.853572 Set Vref, RX VrefLevel [Byte0]: 60
7899 01:35:55.856915 [Byte1]: 60
7900 01:35:55.861106
7901 01:35:55.861690 Set Vref, RX VrefLevel [Byte0]: 61
7902 01:35:55.864530 [Byte1]: 61
7903 01:35:55.868653
7904 01:35:55.869144 Set Vref, RX VrefLevel [Byte0]: 62
7905 01:35:55.872149 [Byte1]: 62
7906 01:35:55.876125
7907 01:35:55.876623 Set Vref, RX VrefLevel [Byte0]: 63
7908 01:35:55.879975 [Byte1]: 63
7909 01:35:55.884274
7910 01:35:55.884828 Set Vref, RX VrefLevel [Byte0]: 64
7911 01:35:55.888919 [Byte1]: 64
7912 01:35:55.891865
7913 01:35:55.892457 Set Vref, RX VrefLevel [Byte0]: 65
7914 01:35:55.894623 [Byte1]: 65
7915 01:35:55.898879
7916 01:35:55.899531 Set Vref, RX VrefLevel [Byte0]: 66
7917 01:35:55.902428 [Byte1]: 66
7918 01:35:55.906704
7919 01:35:55.907156 Set Vref, RX VrefLevel [Byte0]: 67
7920 01:35:55.909731 [Byte1]: 67
7921 01:35:55.914100
7922 01:35:55.914511 Set Vref, RX VrefLevel [Byte0]: 68
7923 01:35:55.917479 [Byte1]: 68
7924 01:35:55.921722
7925 01:35:55.922137 Set Vref, RX VrefLevel [Byte0]: 69
7926 01:35:55.925090 [Byte1]: 69
7927 01:35:55.929279
7928 01:35:55.929690 Set Vref, RX VrefLevel [Byte0]: 70
7929 01:35:55.933324 [Byte1]: 70
7930 01:35:55.937272
7931 01:35:55.937824 Set Vref, RX VrefLevel [Byte0]: 71
7932 01:35:55.940416 [Byte1]: 71
7933 01:35:55.944548
7934 01:35:55.945224 Set Vref, RX VrefLevel [Byte0]: 72
7935 01:35:55.948057 [Byte1]: 72
7936 01:35:55.951916
7937 01:35:55.952371 Set Vref, RX VrefLevel [Byte0]: 73
7938 01:35:55.955899 [Byte1]: 73
7939 01:35:55.959871
7940 01:35:55.960342 Set Vref, RX VrefLevel [Byte0]: 74
7941 01:35:55.964161 [Byte1]: 74
7942 01:35:55.967377
7943 01:35:55.967884 Set Vref, RX VrefLevel [Byte0]: 75
7944 01:35:55.971206 [Byte1]: 75
7945 01:35:55.975059
7946 01:35:55.975618 Final RX Vref Byte 0 = 57 to rank0
7947 01:35:55.978462 Final RX Vref Byte 1 = 63 to rank0
7948 01:35:55.981782 Final RX Vref Byte 0 = 57 to rank1
7949 01:35:55.984886 Final RX Vref Byte 1 = 63 to rank1==
7950 01:35:55.988379 Dram Type= 6, Freq= 0, CH_0, rank 0
7951 01:35:55.995178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 01:35:55.995595 ==
7953 01:35:55.995926 DQS Delay:
7954 01:35:55.996232 DQS0 = 0, DQS1 = 0
7955 01:35:55.998279 DQM Delay:
7956 01:35:55.998691 DQM0 = 129, DQM1 = 122
7957 01:35:56.001505 DQ Delay:
7958 01:35:56.004950 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
7959 01:35:56.008497 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =136
7960 01:35:56.011802 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7961 01:35:56.015818 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =134
7962 01:35:56.016361
7963 01:35:56.016702
7964 01:35:56.017023
7965 01:35:56.018147 [DramC_TX_OE_Calibration] TA2
7966 01:35:56.021808 Original DQ_B0 (3 6) =30, OEN = 27
7967 01:35:56.025278 Original DQ_B1 (3 6) =30, OEN = 27
7968 01:35:56.028265 24, 0x0, End_B0=24 End_B1=24
7969 01:35:56.028809 25, 0x0, End_B0=25 End_B1=25
7970 01:35:56.032440 26, 0x0, End_B0=26 End_B1=26
7971 01:35:56.035213 27, 0x0, End_B0=27 End_B1=27
7972 01:35:56.039248 28, 0x0, End_B0=28 End_B1=28
7973 01:35:56.039774 29, 0x0, End_B0=29 End_B1=29
7974 01:35:56.041546 30, 0x0, End_B0=30 End_B1=30
7975 01:35:56.045239 31, 0x4141, End_B0=30 End_B1=30
7976 01:35:56.048687 Byte0 end_step=30 best_step=27
7977 01:35:56.052352 Byte1 end_step=30 best_step=27
7978 01:35:56.055325 Byte0 TX OE(2T, 0.5T) = (3, 3)
7979 01:35:56.055880 Byte1 TX OE(2T, 0.5T) = (3, 3)
7980 01:35:56.058522
7981 01:35:56.059087
7982 01:35:56.065018 [DQSOSCAuto] RK0, (LSB)MR18= 0x1207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7983 01:35:56.068089 CH0 RK0: MR19=303, MR18=1207
7984 01:35:56.074718 CH0_RK0: MR19=0x303, MR18=0x1207, DQSOSC=400, MR23=63, INC=23, DEC=15
7985 01:35:56.075218
7986 01:35:56.078579 ----->DramcWriteLeveling(PI) begin...
7987 01:35:56.079240 ==
7988 01:35:56.081641 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 01:35:56.085114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 01:35:56.085537 ==
7991 01:35:56.088366 Write leveling (Byte 0): 35 => 35
7992 01:35:56.091692 Write leveling (Byte 1): 25 => 25
7993 01:35:56.095050 DramcWriteLeveling(PI) end<-----
7994 01:35:56.095605
7995 01:35:56.095972 ==
7996 01:35:56.098408 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 01:35:56.101743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 01:35:56.102329 ==
7999 01:35:56.104782 [Gating] SW mode calibration
8000 01:35:56.112136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8001 01:35:56.118857 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8002 01:35:56.121722 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 01:35:56.125847 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 01:35:56.131741 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 01:35:56.134617 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8006 01:35:56.138286 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8007 01:35:56.144648 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8008 01:35:56.148600 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8009 01:35:56.151988 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 01:35:56.158286 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 01:35:56.162042 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8012 01:35:56.165024 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8013 01:35:56.171495 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8014 01:35:56.174704 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8015 01:35:56.178102 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8016 01:35:56.185904 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8017 01:35:56.188796 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 01:35:56.192012 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 01:35:56.195384 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 01:35:56.201897 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8021 01:35:56.205135 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8022 01:35:56.208611 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8023 01:35:56.214855 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
8024 01:35:56.218624 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 01:35:56.221782 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 01:35:56.229083 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 01:35:56.231855 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 01:35:56.235419 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 01:35:56.241611 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8030 01:35:56.245195 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8031 01:35:56.248291 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8032 01:35:56.255512 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 01:35:56.259787 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 01:35:56.261420 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 01:35:56.268278 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 01:35:56.271696 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 01:35:56.274566 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 01:35:56.278244 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 01:35:56.286008 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 01:35:56.288650 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 01:35:56.291888 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 01:35:56.298276 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 01:35:56.302045 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 01:35:56.304964 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 01:35:56.311560 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 01:35:56.315216 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8047 01:35:56.318950 Total UI for P1: 0, mck2ui 16
8048 01:35:56.321987 best dqsien dly found for B0: ( 1, 9, 10)
8049 01:35:56.325780 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 01:35:56.331619 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 01:35:56.332178 Total UI for P1: 0, mck2ui 16
8052 01:35:56.338153 best dqsien dly found for B1: ( 1, 9, 20)
8053 01:35:56.341641 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8054 01:35:56.345052 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8055 01:35:56.345633
8056 01:35:56.347975 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8057 01:35:56.351634 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8058 01:35:56.354269 [Gating] SW calibration Done
8059 01:35:56.354695 ==
8060 01:35:56.358227 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 01:35:56.361477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 01:35:56.362089 ==
8063 01:35:56.364849 RX Vref Scan: 0
8064 01:35:56.365486
8065 01:35:56.365977 RX Vref 0 -> 0, step: 1
8066 01:35:56.366433
8067 01:35:56.368178 RX Delay 0 -> 252, step: 8
8068 01:35:56.371938 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8069 01:35:56.377979 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8070 01:35:56.381349 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8071 01:35:56.385413 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8072 01:35:56.388080 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8073 01:35:56.391447 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8074 01:35:56.398337 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8075 01:35:56.401802 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8076 01:35:56.405104 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8077 01:35:56.408445 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8078 01:35:56.410922 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8079 01:35:56.417873 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8080 01:35:56.421351 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8081 01:35:56.425561 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8082 01:35:56.427999 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8083 01:35:56.431832 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8084 01:35:56.434672 ==
8085 01:35:56.437811 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 01:35:56.441626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 01:35:56.442196 ==
8088 01:35:56.442569 DQS Delay:
8089 01:35:56.444432 DQS0 = 0, DQS1 = 0
8090 01:35:56.445016 DQM Delay:
8091 01:35:56.448496 DQM0 = 131, DQM1 = 126
8092 01:35:56.449115 DQ Delay:
8093 01:35:56.451275 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8094 01:35:56.454464 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8095 01:35:56.458377 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8096 01:35:56.461220 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
8097 01:35:56.461773
8098 01:35:56.462338
8099 01:35:56.462793 ==
8100 01:35:56.466627 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 01:35:56.468004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 01:35:56.471397 ==
8103 01:35:56.471892
8104 01:35:56.472370
8105 01:35:56.472832 TX Vref Scan disable
8106 01:35:56.474923 == TX Byte 0 ==
8107 01:35:56.478166 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8108 01:35:56.481512 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8109 01:35:56.484842 == TX Byte 1 ==
8110 01:35:56.489824 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8111 01:35:56.492919 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8112 01:35:56.495655 ==
8113 01:35:56.496210 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 01:35:56.502352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 01:35:56.502914 ==
8116 01:35:56.516383
8117 01:35:56.520051 TX Vref early break, caculate TX vref
8118 01:35:56.522707 TX Vref=16, minBit 9, minWin=22, winSum=378
8119 01:35:56.526744 TX Vref=18, minBit 8, minWin=22, winSum=382
8120 01:35:56.529664 TX Vref=20, minBit 9, minWin=23, winSum=394
8121 01:35:56.533175 TX Vref=22, minBit 8, minWin=23, winSum=400
8122 01:35:56.536274 TX Vref=24, minBit 9, minWin=24, winSum=409
8123 01:35:56.543126 TX Vref=26, minBit 3, minWin=25, winSum=413
8124 01:35:56.545983 TX Vref=28, minBit 9, minWin=25, winSum=422
8125 01:35:56.549612 TX Vref=30, minBit 10, minWin=25, winSum=422
8126 01:35:56.553357 TX Vref=32, minBit 5, minWin=25, winSum=416
8127 01:35:56.556638 TX Vref=34, minBit 13, minWin=24, winSum=405
8128 01:35:56.559660 TX Vref=36, minBit 13, minWin=23, winSum=397
8129 01:35:56.566121 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
8130 01:35:56.566606
8131 01:35:56.569588 Final TX Range 0 Vref 28
8132 01:35:56.570055
8133 01:35:56.570420 ==
8134 01:35:56.572673 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 01:35:56.576174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 01:35:56.576643 ==
8137 01:35:56.577045
8138 01:35:56.577398
8139 01:35:56.579862 TX Vref Scan disable
8140 01:35:56.586133 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8141 01:35:56.586678 == TX Byte 0 ==
8142 01:35:56.589574 u2DelayCellOfst[0]=14 cells (4 PI)
8143 01:35:56.592856 u2DelayCellOfst[1]=21 cells (6 PI)
8144 01:35:56.596132 u2DelayCellOfst[2]=10 cells (3 PI)
8145 01:35:56.599678 u2DelayCellOfst[3]=14 cells (4 PI)
8146 01:35:56.602655 u2DelayCellOfst[4]=10 cells (3 PI)
8147 01:35:56.606217 u2DelayCellOfst[5]=0 cells (0 PI)
8148 01:35:56.609267 u2DelayCellOfst[6]=17 cells (5 PI)
8149 01:35:56.612442 u2DelayCellOfst[7]=17 cells (5 PI)
8150 01:35:56.616113 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8151 01:35:56.619814 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8152 01:35:56.622800 == TX Byte 1 ==
8153 01:35:56.626469 u2DelayCellOfst[8]=0 cells (0 PI)
8154 01:35:56.629483 u2DelayCellOfst[9]=0 cells (0 PI)
8155 01:35:56.632583 u2DelayCellOfst[10]=3 cells (1 PI)
8156 01:35:56.633086 u2DelayCellOfst[11]=0 cells (0 PI)
8157 01:35:56.636211 u2DelayCellOfst[12]=10 cells (3 PI)
8158 01:35:56.639226 u2DelayCellOfst[13]=10 cells (3 PI)
8159 01:35:56.642738 u2DelayCellOfst[14]=14 cells (4 PI)
8160 01:35:56.646307 u2DelayCellOfst[15]=10 cells (3 PI)
8161 01:35:56.652706 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8162 01:35:56.656003 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8163 01:35:56.656522 DramC Write-DBI on
8164 01:35:56.656858 ==
8165 01:35:56.659854 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 01:35:56.665780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 01:35:56.666210 ==
8168 01:35:56.666547
8169 01:35:56.666858
8170 01:35:56.667158 TX Vref Scan disable
8171 01:35:56.670045 == TX Byte 0 ==
8172 01:35:56.673686 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8173 01:35:56.677072 == TX Byte 1 ==
8174 01:35:56.679968 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8175 01:35:56.683596 DramC Write-DBI off
8176 01:35:56.684055
8177 01:35:56.684417 [DATLAT]
8178 01:35:56.684756 Freq=1600, CH0 RK1
8179 01:35:56.685117
8180 01:35:56.686484 DATLAT Default: 0xf
8181 01:35:56.686922 0, 0xFFFF, sum = 0
8182 01:35:56.690118 1, 0xFFFF, sum = 0
8183 01:35:56.690639 2, 0xFFFF, sum = 0
8184 01:35:56.693148 3, 0xFFFF, sum = 0
8185 01:35:56.696792 4, 0xFFFF, sum = 0
8186 01:35:56.697404 5, 0xFFFF, sum = 0
8187 01:35:56.699616 6, 0xFFFF, sum = 0
8188 01:35:56.700043 7, 0xFFFF, sum = 0
8189 01:35:56.703435 8, 0xFFFF, sum = 0
8190 01:35:56.704021 9, 0xFFFF, sum = 0
8191 01:35:56.706353 10, 0xFFFF, sum = 0
8192 01:35:56.706824 11, 0xFFFF, sum = 0
8193 01:35:56.709453 12, 0xFFFF, sum = 0
8194 01:35:56.709962 13, 0xFFFF, sum = 0
8195 01:35:56.712895 14, 0x0, sum = 1
8196 01:35:56.713427 15, 0x0, sum = 2
8197 01:35:56.717467 16, 0x0, sum = 3
8198 01:35:56.718067 17, 0x0, sum = 4
8199 01:35:56.719702 best_step = 15
8200 01:35:56.720173
8201 01:35:56.720654 ==
8202 01:35:56.723296 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 01:35:56.726837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 01:35:56.727442 ==
8205 01:35:56.730464 RX Vref Scan: 0
8206 01:35:56.731039
8207 01:35:56.731529 RX Vref 0 -> 0, step: 1
8208 01:35:56.731981
8209 01:35:56.733756 RX Delay 11 -> 252, step: 4
8210 01:35:56.736662 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8211 01:35:56.743193 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8212 01:35:56.746745 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8213 01:35:56.749963 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8214 01:35:56.753399 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8215 01:35:56.756574 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8216 01:35:56.763125 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8217 01:35:56.766875 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8218 01:35:56.769899 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8219 01:35:56.773444 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8220 01:35:56.776627 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8221 01:35:56.783447 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8222 01:35:56.786944 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8223 01:35:56.789576 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8224 01:35:56.793020 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8225 01:35:56.798440 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8226 01:35:56.799428 ==
8227 01:35:56.803011 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 01:35:56.806845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 01:35:56.807312 ==
8230 01:35:56.807677 DQS Delay:
8231 01:35:56.809675 DQS0 = 0, DQS1 = 0
8232 01:35:56.810149 DQM Delay:
8233 01:35:56.812881 DQM0 = 126, DQM1 = 122
8234 01:35:56.813380 DQ Delay:
8235 01:35:56.816804 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8236 01:35:56.820781 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8237 01:35:56.822946 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8238 01:35:56.826058 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8239 01:35:56.826616
8240 01:35:56.826989
8241 01:35:56.827332
8242 01:35:56.829744 [DramC_TX_OE_Calibration] TA2
8243 01:35:56.833091 Original DQ_B0 (3 6) =30, OEN = 27
8244 01:35:56.836703 Original DQ_B1 (3 6) =30, OEN = 27
8245 01:35:56.839369 24, 0x0, End_B0=24 End_B1=24
8246 01:35:56.843980 25, 0x0, End_B0=25 End_B1=25
8247 01:35:56.844564 26, 0x0, End_B0=26 End_B1=26
8248 01:35:56.846003 27, 0x0, End_B0=27 End_B1=27
8249 01:35:56.849767 28, 0x0, End_B0=28 End_B1=28
8250 01:35:56.853227 29, 0x0, End_B0=29 End_B1=29
8251 01:35:56.853809 30, 0x0, End_B0=30 End_B1=30
8252 01:35:56.856464 31, 0x4141, End_B0=30 End_B1=30
8253 01:35:56.859502 Byte0 end_step=30 best_step=27
8254 01:35:56.862752 Byte1 end_step=30 best_step=27
8255 01:35:56.867735 Byte0 TX OE(2T, 0.5T) = (3, 3)
8256 01:35:56.869576 Byte1 TX OE(2T, 0.5T) = (3, 3)
8257 01:35:56.870054
8258 01:35:56.870531
8259 01:35:56.877147 [DQSOSCAuto] RK1, (LSB)MR18= 0x150b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8260 01:35:56.879621 CH0 RK1: MR19=303, MR18=150B
8261 01:35:56.886125 CH0_RK1: MR19=0x303, MR18=0x150B, DQSOSC=399, MR23=63, INC=23, DEC=15
8262 01:35:56.889689 [RxdqsGatingPostProcess] freq 1600
8263 01:35:56.892772 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8264 01:35:56.896436 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 01:35:56.900177 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 01:35:56.903590 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 01:35:56.906085 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 01:35:56.909911 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 01:35:56.913854 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 01:35:56.916673 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 01:35:56.919353 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 01:35:56.922984 Pre-setting of DQS Precalculation
8273 01:35:56.926720 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8274 01:35:56.927194 ==
8275 01:35:56.929612 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 01:35:56.933583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 01:35:56.937389 ==
8278 01:35:56.939513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8279 01:35:56.943962 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8280 01:35:56.950397 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8281 01:35:56.952946 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8282 01:35:56.963040 [CA 0] Center 42 (14~71) winsize 58
8283 01:35:56.967181 [CA 1] Center 42 (13~71) winsize 59
8284 01:35:56.969807 [CA 2] Center 37 (8~66) winsize 59
8285 01:35:56.973657 [CA 3] Center 36 (7~65) winsize 59
8286 01:35:56.976734 [CA 4] Center 37 (8~67) winsize 60
8287 01:35:56.979835 [CA 5] Center 36 (7~66) winsize 60
8288 01:35:56.980411
8289 01:35:56.983425 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8290 01:35:56.984028
8291 01:35:56.986719 [CATrainingPosCal] consider 1 rank data
8292 01:35:56.989656 u2DelayCellTimex100 = 275/100 ps
8293 01:35:56.993231 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8294 01:35:57.000030 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8295 01:35:57.003213 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8296 01:35:57.006608 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8297 01:35:57.010150 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8298 01:35:57.013192 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8299 01:35:57.013513
8300 01:35:57.016178 CA PerBit enable=1, Macro0, CA PI delay=36
8301 01:35:57.016416
8302 01:35:57.019292 [CBTSetCACLKResult] CA Dly = 36
8303 01:35:57.019624 CS Dly: 9 (0~40)
8304 01:35:57.026008 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8305 01:35:57.029581 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8306 01:35:57.030015 ==
8307 01:35:57.033252 Dram Type= 6, Freq= 0, CH_1, rank 1
8308 01:35:57.036290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 01:35:57.036624 ==
8310 01:35:57.044413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 01:35:57.046517 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 01:35:57.052810 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 01:35:57.056285 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 01:35:57.066311 [CA 0] Center 43 (14~73) winsize 60
8315 01:35:57.069499 [CA 1] Center 43 (14~72) winsize 59
8316 01:35:57.072632 [CA 2] Center 38 (9~67) winsize 59
8317 01:35:57.076511 [CA 3] Center 37 (8~66) winsize 59
8318 01:35:57.080052 [CA 4] Center 38 (8~68) winsize 61
8319 01:35:57.082830 [CA 5] Center 36 (7~66) winsize 60
8320 01:35:57.083295
8321 01:35:57.086483 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8322 01:35:57.087037
8323 01:35:57.090556 [CATrainingPosCal] consider 2 rank data
8324 01:35:57.093065 u2DelayCellTimex100 = 275/100 ps
8325 01:35:57.096470 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8326 01:35:57.103232 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8327 01:35:57.106419 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8328 01:35:57.110000 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8329 01:35:57.113465 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8330 01:35:57.116469 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8331 01:35:57.117108
8332 01:35:57.120439 CA PerBit enable=1, Macro0, CA PI delay=36
8333 01:35:57.121046
8334 01:35:57.123636 [CBTSetCACLKResult] CA Dly = 36
8335 01:35:57.124218 CS Dly: 10 (0~43)
8336 01:35:57.129977 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 01:35:57.133741 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 01:35:57.134297
8339 01:35:57.137098 ----->DramcWriteLeveling(PI) begin...
8340 01:35:57.137664 ==
8341 01:35:57.140496 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 01:35:57.143252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 01:35:57.143812 ==
8344 01:35:57.147460 Write leveling (Byte 0): 24 => 24
8345 01:35:57.150158 Write leveling (Byte 1): 28 => 28
8346 01:35:57.154004 DramcWriteLeveling(PI) end<-----
8347 01:35:57.154556
8348 01:35:57.154920 ==
8349 01:35:57.156509 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 01:35:57.160157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 01:35:57.163359 ==
8352 01:35:57.163953 [Gating] SW mode calibration
8353 01:35:57.170703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8354 01:35:57.176386 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8355 01:35:57.180096 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 01:35:57.187252 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 01:35:57.190664 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 01:35:57.193967 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 01:35:57.199943 1 4 16 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
8360 01:35:57.204104 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8361 01:35:57.206736 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 01:35:57.213359 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 01:35:57.216923 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 01:35:57.221187 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 01:35:57.224075 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 01:35:57.229957 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 01:35:57.234744 1 5 16 | B1->B0 | 3232 3434 | 1 0 | (1 0) (0 1)
8368 01:35:57.236339 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8369 01:35:57.243672 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 01:35:57.246658 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 01:35:57.251019 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 01:35:57.258067 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 01:35:57.259817 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 01:35:57.263730 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 01:35:57.270011 1 6 16 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
8376 01:35:57.273740 1 6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8377 01:35:57.277070 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 01:35:57.283071 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 01:35:57.287224 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 01:35:57.289932 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 01:35:57.296530 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 01:35:57.300288 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 01:35:57.303621 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8384 01:35:57.310329 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 01:35:57.313262 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 01:35:57.317091 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 01:35:57.323368 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 01:35:57.326969 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 01:35:57.330167 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 01:35:57.334321 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 01:35:57.341287 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 01:35:57.343510 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 01:35:57.346530 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 01:35:57.353274 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 01:35:57.356622 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 01:35:57.360610 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 01:35:57.367683 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 01:35:57.371208 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 01:35:57.373572 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8400 01:35:57.377149 Total UI for P1: 0, mck2ui 16
8401 01:35:57.380463 best dqsien dly found for B0: ( 1, 9, 14)
8402 01:35:57.386999 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8403 01:35:57.387562 Total UI for P1: 0, mck2ui 16
8404 01:35:57.389809 best dqsien dly found for B1: ( 1, 9, 16)
8405 01:35:57.397048 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8406 01:35:57.400344 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8407 01:35:57.400923
8408 01:35:57.403376 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8409 01:35:57.406991 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8410 01:35:57.410212 [Gating] SW calibration Done
8411 01:35:57.410679 ==
8412 01:35:57.413068 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 01:35:57.416940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 01:35:57.417571 ==
8415 01:35:57.419749 RX Vref Scan: 0
8416 01:35:57.420231
8417 01:35:57.420600 RX Vref 0 -> 0, step: 1
8418 01:35:57.420943
8419 01:35:57.423248 RX Delay 0 -> 252, step: 8
8420 01:35:57.427216 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8421 01:35:57.433850 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8422 01:35:57.437145 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8423 01:35:57.439609 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8424 01:35:57.445624 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8425 01:35:57.447253 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8426 01:35:57.450645 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8427 01:35:57.456866 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8428 01:35:57.460809 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8429 01:35:57.463842 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8430 01:35:57.468405 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8431 01:35:57.470192 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8432 01:35:57.476878 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8433 01:35:57.480188 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8434 01:35:57.483486 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8435 01:35:57.486646 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8436 01:35:57.487212 ==
8437 01:35:57.490581 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 01:35:57.496708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 01:35:57.497314 ==
8440 01:35:57.497690 DQS Delay:
8441 01:35:57.498039 DQS0 = 0, DQS1 = 0
8442 01:35:57.500459 DQM Delay:
8443 01:35:57.501144 DQM0 = 134, DQM1 = 127
8444 01:35:57.503632 DQ Delay:
8445 01:35:57.506843 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8446 01:35:57.510119 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8447 01:35:57.513622 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8448 01:35:57.517059 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8449 01:35:57.517618
8450 01:35:57.517984
8451 01:35:57.518321 ==
8452 01:35:57.520139 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 01:35:57.524693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 01:35:57.526630 ==
8455 01:35:57.527102
8456 01:35:57.527468
8457 01:35:57.527804 TX Vref Scan disable
8458 01:35:57.530424 == TX Byte 0 ==
8459 01:35:57.533443 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8460 01:35:57.537254 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8461 01:35:57.539992 == TX Byte 1 ==
8462 01:35:57.543273 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8463 01:35:57.546393 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8464 01:35:57.546856 ==
8465 01:35:57.550431 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 01:35:57.557183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 01:35:57.557749 ==
8468 01:35:57.569827
8469 01:35:57.573090 TX Vref early break, caculate TX vref
8470 01:35:57.576656 TX Vref=16, minBit 8, minWin=21, winSum=365
8471 01:35:57.579944 TX Vref=18, minBit 8, minWin=21, winSum=374
8472 01:35:57.583048 TX Vref=20, minBit 8, minWin=21, winSum=387
8473 01:35:57.586542 TX Vref=22, minBit 8, minWin=22, winSum=395
8474 01:35:57.590569 TX Vref=24, minBit 8, minWin=23, winSum=404
8475 01:35:57.597097 TX Vref=26, minBit 0, minWin=25, winSum=411
8476 01:35:57.601582 TX Vref=28, minBit 5, minWin=25, winSum=419
8477 01:35:57.603247 TX Vref=30, minBit 1, minWin=25, winSum=418
8478 01:35:57.606313 TX Vref=32, minBit 0, minWin=24, winSum=409
8479 01:35:57.609579 TX Vref=34, minBit 8, minWin=23, winSum=401
8480 01:35:57.614279 TX Vref=36, minBit 9, minWin=22, winSum=387
8481 01:35:57.620038 [TxChooseVref] Worse bit 5, Min win 25, Win sum 419, Final Vref 28
8482 01:35:57.620664
8483 01:35:57.623195 Final TX Range 0 Vref 28
8484 01:35:57.623658
8485 01:35:57.624022 ==
8486 01:35:57.627213 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 01:35:57.630054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 01:35:57.630622 ==
8489 01:35:57.630990
8490 01:35:57.631326
8491 01:35:57.633152 TX Vref Scan disable
8492 01:35:57.640117 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8493 01:35:57.640685 == TX Byte 0 ==
8494 01:35:57.643973 u2DelayCellOfst[0]=17 cells (5 PI)
8495 01:35:57.646909 u2DelayCellOfst[1]=10 cells (3 PI)
8496 01:35:57.649681 u2DelayCellOfst[2]=0 cells (0 PI)
8497 01:35:57.653084 u2DelayCellOfst[3]=7 cells (2 PI)
8498 01:35:57.656437 u2DelayCellOfst[4]=7 cells (2 PI)
8499 01:35:57.660249 u2DelayCellOfst[5]=17 cells (5 PI)
8500 01:35:57.663010 u2DelayCellOfst[6]=17 cells (5 PI)
8501 01:35:57.663475 u2DelayCellOfst[7]=3 cells (1 PI)
8502 01:35:57.670761 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8503 01:35:57.673544 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8504 01:35:57.674010 == TX Byte 1 ==
8505 01:35:57.676365 u2DelayCellOfst[8]=0 cells (0 PI)
8506 01:35:57.680120 u2DelayCellOfst[9]=3 cells (1 PI)
8507 01:35:57.683157 u2DelayCellOfst[10]=10 cells (3 PI)
8508 01:35:57.686226 u2DelayCellOfst[11]=7 cells (2 PI)
8509 01:35:57.689697 u2DelayCellOfst[12]=14 cells (4 PI)
8510 01:35:57.693444 u2DelayCellOfst[13]=17 cells (5 PI)
8511 01:35:57.697081 u2DelayCellOfst[14]=17 cells (5 PI)
8512 01:35:57.699844 u2DelayCellOfst[15]=17 cells (5 PI)
8513 01:35:57.703462 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8514 01:35:57.710044 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8515 01:35:57.710511 DramC Write-DBI on
8516 01:35:57.710879 ==
8517 01:35:57.713061 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 01:35:57.716233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 01:35:57.716809 ==
8520 01:35:57.720289
8521 01:35:57.720910
8522 01:35:57.721334 TX Vref Scan disable
8523 01:35:57.723497 == TX Byte 0 ==
8524 01:35:57.726989 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8525 01:35:57.730406 == TX Byte 1 ==
8526 01:35:57.733937 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8527 01:35:57.734504 DramC Write-DBI off
8528 01:35:57.734872
8529 01:35:57.737167 [DATLAT]
8530 01:35:57.737723 Freq=1600, CH1 RK0
8531 01:35:57.738122
8532 01:35:57.740664 DATLAT Default: 0xf
8533 01:35:57.741305 0, 0xFFFF, sum = 0
8534 01:35:57.743696 1, 0xFFFF, sum = 0
8535 01:35:57.744271 2, 0xFFFF, sum = 0
8536 01:35:57.746484 3, 0xFFFF, sum = 0
8537 01:35:57.746949 4, 0xFFFF, sum = 0
8538 01:35:57.750396 5, 0xFFFF, sum = 0
8539 01:35:57.750963 6, 0xFFFF, sum = 0
8540 01:35:57.753351 7, 0xFFFF, sum = 0
8541 01:35:57.753819 8, 0xFFFF, sum = 0
8542 01:35:57.757066 9, 0xFFFF, sum = 0
8543 01:35:57.757633 10, 0xFFFF, sum = 0
8544 01:35:57.760157 11, 0xFFFF, sum = 0
8545 01:35:57.763282 12, 0xFFFF, sum = 0
8546 01:35:57.763750 13, 0xFFFF, sum = 0
8547 01:35:57.766631 14, 0x0, sum = 1
8548 01:35:57.767101 15, 0x0, sum = 2
8549 01:35:57.767470 16, 0x0, sum = 3
8550 01:35:57.770265 17, 0x0, sum = 4
8551 01:35:57.770733 best_step = 15
8552 01:35:57.771096
8553 01:35:57.774467 ==
8554 01:35:57.775037 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 01:35:57.780308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 01:35:57.780871 ==
8557 01:35:57.781307 RX Vref Scan: 1
8558 01:35:57.781686
8559 01:35:57.783493 Set Vref Range= 24 -> 127
8560 01:35:57.783956
8561 01:35:57.786763 RX Vref 24 -> 127, step: 1
8562 01:35:57.787335
8563 01:35:57.789699 RX Delay 11 -> 252, step: 4
8564 01:35:57.790161
8565 01:35:57.793221 Set Vref, RX VrefLevel [Byte0]: 24
8566 01:35:57.796868 [Byte1]: 24
8567 01:35:57.797463
8568 01:35:57.799898 Set Vref, RX VrefLevel [Byte0]: 25
8569 01:35:57.803078 [Byte1]: 25
8570 01:35:57.803647
8571 01:35:57.807017 Set Vref, RX VrefLevel [Byte0]: 26
8572 01:35:57.809882 [Byte1]: 26
8573 01:35:57.813594
8574 01:35:57.814167 Set Vref, RX VrefLevel [Byte0]: 27
8575 01:35:57.816702 [Byte1]: 27
8576 01:35:57.821078
8577 01:35:57.821659 Set Vref, RX VrefLevel [Byte0]: 28
8578 01:35:57.825128 [Byte1]: 28
8579 01:35:57.829276
8580 01:35:57.829837 Set Vref, RX VrefLevel [Byte0]: 29
8581 01:35:57.831940 [Byte1]: 29
8582 01:35:57.835782
8583 01:35:57.836246 Set Vref, RX VrefLevel [Byte0]: 30
8584 01:35:57.839104 [Byte1]: 30
8585 01:35:57.844180
8586 01:35:57.844747 Set Vref, RX VrefLevel [Byte0]: 31
8587 01:35:57.847616 [Byte1]: 31
8588 01:35:57.851657
8589 01:35:57.852231 Set Vref, RX VrefLevel [Byte0]: 32
8590 01:35:57.857930 [Byte1]: 32
8591 01:35:57.858492
8592 01:35:57.861044 Set Vref, RX VrefLevel [Byte0]: 33
8593 01:35:57.864428 [Byte1]: 33
8594 01:35:57.865144
8595 01:35:57.867476 Set Vref, RX VrefLevel [Byte0]: 34
8596 01:35:57.870781 [Byte1]: 34
8597 01:35:57.871245
8598 01:35:57.874716 Set Vref, RX VrefLevel [Byte0]: 35
8599 01:35:57.877318 [Byte1]: 35
8600 01:35:57.881725
8601 01:35:57.882281 Set Vref, RX VrefLevel [Byte0]: 36
8602 01:35:57.885742 [Byte1]: 36
8603 01:35:57.889468
8604 01:35:57.889884 Set Vref, RX VrefLevel [Byte0]: 37
8605 01:35:57.892945 [Byte1]: 37
8606 01:35:57.898133
8607 01:35:57.898656 Set Vref, RX VrefLevel [Byte0]: 38
8608 01:35:57.900702 [Byte1]: 38
8609 01:35:57.904281
8610 01:35:57.904696 Set Vref, RX VrefLevel [Byte0]: 39
8611 01:35:57.907619 [Byte1]: 39
8612 01:35:57.912224
8613 01:35:57.912643 Set Vref, RX VrefLevel [Byte0]: 40
8614 01:35:57.915430 [Byte1]: 40
8615 01:35:57.920120
8616 01:35:57.920634 Set Vref, RX VrefLevel [Byte0]: 41
8617 01:35:57.923464 [Byte1]: 41
8618 01:35:57.926945
8619 01:35:57.927359 Set Vref, RX VrefLevel [Byte0]: 42
8620 01:35:57.930586 [Byte1]: 42
8621 01:35:57.936123
8622 01:35:57.936678 Set Vref, RX VrefLevel [Byte0]: 43
8623 01:35:57.938564 [Byte1]: 43
8624 01:35:57.942974
8625 01:35:57.943536 Set Vref, RX VrefLevel [Byte0]: 44
8626 01:35:57.945524 [Byte1]: 44
8627 01:35:57.950292
8628 01:35:57.950855 Set Vref, RX VrefLevel [Byte0]: 45
8629 01:35:57.956915 [Byte1]: 45
8630 01:35:57.957530
8631 01:35:57.960618 Set Vref, RX VrefLevel [Byte0]: 46
8632 01:35:57.963812 [Byte1]: 46
8633 01:35:57.964366
8634 01:35:57.967346 Set Vref, RX VrefLevel [Byte0]: 47
8635 01:35:57.969706 [Byte1]: 47
8636 01:35:57.970170
8637 01:35:57.972957 Set Vref, RX VrefLevel [Byte0]: 48
8638 01:35:57.976491 [Byte1]: 48
8639 01:35:57.980595
8640 01:35:57.981102 Set Vref, RX VrefLevel [Byte0]: 49
8641 01:35:57.983936 [Byte1]: 49
8642 01:35:57.989378
8643 01:35:57.989935 Set Vref, RX VrefLevel [Byte0]: 50
8644 01:35:57.992208 [Byte1]: 50
8645 01:35:57.996268
8646 01:35:57.996828 Set Vref, RX VrefLevel [Byte0]: 51
8647 01:35:57.999742 [Byte1]: 51
8648 01:35:58.004994
8649 01:35:58.005566 Set Vref, RX VrefLevel [Byte0]: 52
8650 01:35:58.007086 [Byte1]: 52
8651 01:35:58.011389
8652 01:35:58.011954 Set Vref, RX VrefLevel [Byte0]: 53
8653 01:35:58.014406 [Byte1]: 53
8654 01:35:58.019154
8655 01:35:58.019716 Set Vref, RX VrefLevel [Byte0]: 54
8656 01:35:58.021899 [Byte1]: 54
8657 01:35:58.026596
8658 01:35:58.027158 Set Vref, RX VrefLevel [Byte0]: 55
8659 01:35:58.029775 [Byte1]: 55
8660 01:35:58.034042
8661 01:35:58.034603 Set Vref, RX VrefLevel [Byte0]: 56
8662 01:35:58.037343 [Byte1]: 56
8663 01:35:58.041666
8664 01:35:58.042244 Set Vref, RX VrefLevel [Byte0]: 57
8665 01:35:58.044726 [Byte1]: 57
8666 01:35:58.049520
8667 01:35:58.049978 Set Vref, RX VrefLevel [Byte0]: 58
8668 01:35:58.052470 [Byte1]: 58
8669 01:35:58.056631
8670 01:35:58.057134 Set Vref, RX VrefLevel [Byte0]: 59
8671 01:35:58.060781 [Byte1]: 59
8672 01:35:58.065086
8673 01:35:58.065561 Set Vref, RX VrefLevel [Byte0]: 60
8674 01:35:58.067925 [Byte1]: 60
8675 01:35:58.071836
8676 01:35:58.072252 Set Vref, RX VrefLevel [Byte0]: 61
8677 01:35:58.076129 [Byte1]: 61
8678 01:35:58.079872
8679 01:35:58.080391 Set Vref, RX VrefLevel [Byte0]: 62
8680 01:35:58.083389 [Byte1]: 62
8681 01:35:58.087217
8682 01:35:58.087785 Set Vref, RX VrefLevel [Byte0]: 63
8683 01:35:58.090882 [Byte1]: 63
8684 01:35:58.095339
8685 01:35:58.095902 Set Vref, RX VrefLevel [Byte0]: 64
8686 01:35:58.098799 [Byte1]: 64
8687 01:35:58.103070
8688 01:35:58.103633 Set Vref, RX VrefLevel [Byte0]: 65
8689 01:35:58.107135 [Byte1]: 65
8690 01:35:58.110648
8691 01:35:58.111216 Set Vref, RX VrefLevel [Byte0]: 66
8692 01:35:58.114230 [Byte1]: 66
8693 01:35:58.118276
8694 01:35:58.118892 Set Vref, RX VrefLevel [Byte0]: 67
8695 01:35:58.121086 [Byte1]: 67
8696 01:35:58.125264
8697 01:35:58.125964 Set Vref, RX VrefLevel [Byte0]: 68
8698 01:35:58.129090 [Byte1]: 68
8699 01:35:58.133585
8700 01:35:58.134150 Set Vref, RX VrefLevel [Byte0]: 69
8701 01:35:58.136521 [Byte1]: 69
8702 01:35:58.141222
8703 01:35:58.141786 Set Vref, RX VrefLevel [Byte0]: 70
8704 01:35:58.144380 [Byte1]: 70
8705 01:35:58.147868
8706 01:35:58.148326 Set Vref, RX VrefLevel [Byte0]: 71
8707 01:35:58.151678 [Byte1]: 71
8708 01:35:58.156043
8709 01:35:58.156502 Set Vref, RX VrefLevel [Byte0]: 72
8710 01:35:58.159277 [Byte1]: 72
8711 01:35:58.163491
8712 01:35:58.163954 Set Vref, RX VrefLevel [Byte0]: 73
8713 01:35:58.166535 [Byte1]: 73
8714 01:35:58.171574
8715 01:35:58.172212 Set Vref, RX VrefLevel [Byte0]: 74
8716 01:35:58.174347 [Byte1]: 74
8717 01:35:58.178812
8718 01:35:58.179367 Set Vref, RX VrefLevel [Byte0]: 75
8719 01:35:58.181941 [Byte1]: 75
8720 01:35:58.186645
8721 01:35:58.187199 Set Vref, RX VrefLevel [Byte0]: 76
8722 01:35:58.189367 [Byte1]: 76
8723 01:35:58.193712
8724 01:35:58.194261 Final RX Vref Byte 0 = 58 to rank0
8725 01:35:58.198474 Final RX Vref Byte 1 = 52 to rank0
8726 01:35:58.200271 Final RX Vref Byte 0 = 58 to rank1
8727 01:35:58.203991 Final RX Vref Byte 1 = 52 to rank1==
8728 01:35:58.207323 Dram Type= 6, Freq= 0, CH_1, rank 0
8729 01:35:58.213713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 01:35:58.214273 ==
8731 01:35:58.214644 DQS Delay:
8732 01:35:58.214985 DQS0 = 0, DQS1 = 0
8733 01:35:58.216794 DQM Delay:
8734 01:35:58.217316 DQM0 = 131, DQM1 = 124
8735 01:35:58.220756 DQ Delay:
8736 01:35:58.225190 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =128
8737 01:35:58.227573 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8738 01:35:58.230824 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8739 01:35:58.233898 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8740 01:35:58.234587
8741 01:35:58.234965
8742 01:35:58.235309
8743 01:35:58.237618 [DramC_TX_OE_Calibration] TA2
8744 01:35:58.241397 Original DQ_B0 (3 6) =30, OEN = 27
8745 01:35:58.243800 Original DQ_B1 (3 6) =30, OEN = 27
8746 01:35:58.247764 24, 0x0, End_B0=24 End_B1=24
8747 01:35:58.248341 25, 0x0, End_B0=25 End_B1=25
8748 01:35:58.250639 26, 0x0, End_B0=26 End_B1=26
8749 01:35:58.253688 27, 0x0, End_B0=27 End_B1=27
8750 01:35:58.257273 28, 0x0, End_B0=28 End_B1=28
8751 01:35:58.257832 29, 0x0, End_B0=29 End_B1=29
8752 01:35:58.260520 30, 0x0, End_B0=30 End_B1=30
8753 01:35:58.265414 31, 0x4141, End_B0=30 End_B1=30
8754 01:35:58.267699 Byte0 end_step=30 best_step=27
8755 01:35:58.271792 Byte1 end_step=30 best_step=27
8756 01:35:58.274201 Byte0 TX OE(2T, 0.5T) = (3, 3)
8757 01:35:58.274664 Byte1 TX OE(2T, 0.5T) = (3, 3)
8758 01:35:58.275031
8759 01:35:58.277012
8760 01:35:58.283784 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8761 01:35:58.287660 CH1 RK0: MR19=302, MR18=13FD
8762 01:35:58.295482 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8763 01:35:58.296037
8764 01:35:58.297030 ----->DramcWriteLeveling(PI) begin...
8765 01:35:58.297505 ==
8766 01:35:58.301030 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 01:35:58.303988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 01:35:58.304548 ==
8769 01:35:58.307489 Write leveling (Byte 0): 26 => 26
8770 01:35:58.310729 Write leveling (Byte 1): 28 => 28
8771 01:35:58.313427 DramcWriteLeveling(PI) end<-----
8772 01:35:58.313889
8773 01:35:58.314256 ==
8774 01:35:58.317578 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 01:35:58.320945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 01:35:58.321566 ==
8777 01:35:58.323560 [Gating] SW mode calibration
8778 01:35:58.330146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8779 01:35:58.337141 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8780 01:35:58.341706 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 01:35:58.343817 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 01:35:58.350197 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8783 01:35:58.353952 1 4 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
8784 01:35:58.356894 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 01:35:58.363751 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 01:35:58.366767 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 01:35:58.370664 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 01:35:58.376721 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 01:35:58.380484 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8790 01:35:58.384113 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8791 01:35:58.390400 1 5 12 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
8792 01:35:58.393322 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8793 01:35:58.396740 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 01:35:58.403438 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 01:35:58.406911 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 01:35:58.410179 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 01:35:58.416710 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 01:35:58.419818 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8799 01:35:58.423246 1 6 12 | B1->B0 | 3636 4646 | 1 0 | (1 1) (0 0)
8800 01:35:58.430184 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 01:35:58.433916 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 01:35:58.436971 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 01:35:58.440170 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 01:35:58.446601 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 01:35:58.449668 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 01:35:58.452837 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8807 01:35:58.459901 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8808 01:35:58.463732 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 01:35:58.466428 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 01:35:58.473880 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 01:35:58.477362 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 01:35:58.480677 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 01:35:58.486646 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 01:35:58.489792 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 01:35:58.493437 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 01:35:58.500366 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 01:35:58.503264 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 01:35:58.506569 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 01:35:58.513344 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 01:35:58.516600 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 01:35:58.520387 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 01:35:58.526473 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8823 01:35:58.529629 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 01:35:58.533173 Total UI for P1: 0, mck2ui 16
8825 01:35:58.536892 best dqsien dly found for B0: ( 1, 9, 6)
8826 01:35:58.540717 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 01:35:58.543647 Total UI for P1: 0, mck2ui 16
8828 01:35:58.546200 best dqsien dly found for B1: ( 1, 9, 12)
8829 01:35:58.550139 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8830 01:35:58.552831 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8831 01:35:58.553476
8832 01:35:58.556952 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8833 01:35:58.563146 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8834 01:35:58.563847 [Gating] SW calibration Done
8835 01:35:58.564229 ==
8836 01:35:58.566372 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 01:35:58.573072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 01:35:58.573683 ==
8839 01:35:58.574063 RX Vref Scan: 0
8840 01:35:58.574411
8841 01:35:58.576623 RX Vref 0 -> 0, step: 1
8842 01:35:58.577216
8843 01:35:58.579556 RX Delay 0 -> 252, step: 8
8844 01:35:58.583699 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8845 01:35:58.586509 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8846 01:35:58.589699 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8847 01:35:58.593574 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8848 01:35:58.599788 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8849 01:35:58.602900 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8850 01:35:58.606859 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8851 01:35:58.610448 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8852 01:35:58.613039 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8853 01:35:58.620500 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8854 01:35:58.623530 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8855 01:35:58.626582 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8856 01:35:58.629928 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8857 01:35:58.633671 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8858 01:35:58.641406 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8859 01:35:58.643412 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8860 01:35:58.644001 ==
8861 01:35:58.646323 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 01:35:58.649633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 01:35:58.650106 ==
8864 01:35:58.652957 DQS Delay:
8865 01:35:58.653445 DQS0 = 0, DQS1 = 0
8866 01:35:58.653812 DQM Delay:
8867 01:35:58.655915 DQM0 = 132, DQM1 = 127
8868 01:35:58.656378 DQ Delay:
8869 01:35:58.659637 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8870 01:35:58.662996 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8871 01:35:58.666641 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8872 01:35:58.673099 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8873 01:35:58.673773
8874 01:35:58.674152
8875 01:35:58.674497 ==
8876 01:35:58.676510 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 01:35:58.679596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 01:35:58.680060 ==
8879 01:35:58.680423
8880 01:35:58.680763
8881 01:35:58.683126 TX Vref Scan disable
8882 01:35:58.683686 == TX Byte 0 ==
8883 01:35:58.689612 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8884 01:35:58.693988 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8885 01:35:58.694556 == TX Byte 1 ==
8886 01:35:58.699583 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8887 01:35:58.702850 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8888 01:35:58.703334 ==
8889 01:35:58.706118 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 01:35:58.709094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 01:35:58.709561 ==
8892 01:35:58.724964
8893 01:35:58.727791 TX Vref early break, caculate TX vref
8894 01:35:58.731089 TX Vref=16, minBit 8, minWin=21, winSum=374
8895 01:35:58.734779 TX Vref=18, minBit 8, minWin=22, winSum=380
8896 01:35:58.737444 TX Vref=20, minBit 8, minWin=22, winSum=389
8897 01:35:58.740670 TX Vref=22, minBit 9, minWin=24, winSum=404
8898 01:35:58.744063 TX Vref=24, minBit 8, minWin=24, winSum=407
8899 01:35:58.750873 TX Vref=26, minBit 11, minWin=25, winSum=417
8900 01:35:58.754504 TX Vref=28, minBit 8, minWin=25, winSum=419
8901 01:35:58.758690 TX Vref=30, minBit 9, minWin=25, winSum=418
8902 01:35:58.761380 TX Vref=32, minBit 0, minWin=24, winSum=410
8903 01:35:58.764347 TX Vref=34, minBit 0, minWin=24, winSum=400
8904 01:35:58.768180 TX Vref=36, minBit 0, minWin=23, winSum=393
8905 01:35:58.775296 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8906 01:35:58.775720
8907 01:35:58.777618 Final TX Range 0 Vref 28
8908 01:35:58.778037
8909 01:35:58.778367 ==
8910 01:35:58.781018 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 01:35:58.784150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 01:35:58.784686 ==
8913 01:35:58.785073
8914 01:35:58.785392
8915 01:35:58.788017 TX Vref Scan disable
8916 01:35:58.794459 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8917 01:35:58.794990 == TX Byte 0 ==
8918 01:35:58.797496 u2DelayCellOfst[0]=17 cells (5 PI)
8919 01:35:58.800587 u2DelayCellOfst[1]=10 cells (3 PI)
8920 01:35:58.804651 u2DelayCellOfst[2]=0 cells (0 PI)
8921 01:35:58.808617 u2DelayCellOfst[3]=7 cells (2 PI)
8922 01:35:58.810710 u2DelayCellOfst[4]=10 cells (3 PI)
8923 01:35:58.814311 u2DelayCellOfst[5]=17 cells (5 PI)
8924 01:35:58.817769 u2DelayCellOfst[6]=17 cells (5 PI)
8925 01:35:58.821568 u2DelayCellOfst[7]=7 cells (2 PI)
8926 01:35:58.824115 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8927 01:35:58.827991 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8928 01:35:58.831570 == TX Byte 1 ==
8929 01:35:58.832086 u2DelayCellOfst[8]=0 cells (0 PI)
8930 01:35:58.834386 u2DelayCellOfst[9]=7 cells (2 PI)
8931 01:35:58.837647 u2DelayCellOfst[10]=10 cells (3 PI)
8932 01:35:58.841132 u2DelayCellOfst[11]=7 cells (2 PI)
8933 01:35:58.844142 u2DelayCellOfst[12]=14 cells (4 PI)
8934 01:35:58.847311 u2DelayCellOfst[13]=14 cells (4 PI)
8935 01:35:58.851305 u2DelayCellOfst[14]=17 cells (5 PI)
8936 01:35:58.854250 u2DelayCellOfst[15]=17 cells (5 PI)
8937 01:35:58.857550 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8938 01:35:58.864628 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8939 01:35:58.865195 DramC Write-DBI on
8940 01:35:58.865541 ==
8941 01:35:58.867765 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 01:35:58.870578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 01:35:58.874209 ==
8944 01:35:58.874628
8945 01:35:58.874957
8946 01:35:58.875267 TX Vref Scan disable
8947 01:35:58.877629 == TX Byte 0 ==
8948 01:35:58.881258 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8949 01:35:58.884610 == TX Byte 1 ==
8950 01:35:58.888245 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8951 01:35:58.890796 DramC Write-DBI off
8952 01:35:58.891352
8953 01:35:58.891701 [DATLAT]
8954 01:35:58.892014 Freq=1600, CH1 RK1
8955 01:35:58.892318
8956 01:35:58.894823 DATLAT Default: 0xf
8957 01:35:58.895242 0, 0xFFFF, sum = 0
8958 01:35:58.897662 1, 0xFFFF, sum = 0
8959 01:35:58.898189 2, 0xFFFF, sum = 0
8960 01:35:58.900605 3, 0xFFFF, sum = 0
8961 01:35:58.904313 4, 0xFFFF, sum = 0
8962 01:35:58.904843 5, 0xFFFF, sum = 0
8963 01:35:58.908325 6, 0xFFFF, sum = 0
8964 01:35:58.908855 7, 0xFFFF, sum = 0
8965 01:35:58.911137 8, 0xFFFF, sum = 0
8966 01:35:58.911559 9, 0xFFFF, sum = 0
8967 01:35:58.914074 10, 0xFFFF, sum = 0
8968 01:35:58.914609 11, 0xFFFF, sum = 0
8969 01:35:58.918267 12, 0xFFFF, sum = 0
8970 01:35:58.918693 13, 0xFFFF, sum = 0
8971 01:35:58.920875 14, 0x0, sum = 1
8972 01:35:58.921335 15, 0x0, sum = 2
8973 01:35:58.923867 16, 0x0, sum = 3
8974 01:35:58.924287 17, 0x0, sum = 4
8975 01:35:58.927835 best_step = 15
8976 01:35:58.928252
8977 01:35:58.928580 ==
8978 01:35:58.931717 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 01:35:58.934473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 01:35:58.934997 ==
8981 01:35:58.935333 RX Vref Scan: 0
8982 01:35:58.937298
8983 01:35:58.937716 RX Vref 0 -> 0, step: 1
8984 01:35:58.938053
8985 01:35:58.940453 RX Delay 11 -> 252, step: 4
8986 01:35:58.944798 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8987 01:35:58.950912 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8988 01:35:58.954454 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8989 01:35:58.957589 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8990 01:35:58.960599 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8991 01:35:58.964495 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8992 01:35:58.971079 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8993 01:35:58.973784 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8994 01:35:58.977737 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8995 01:35:58.981125 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8996 01:35:58.984320 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8997 01:35:58.987519 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8998 01:35:58.993983 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8999 01:35:58.997856 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9000 01:35:59.000678 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9001 01:35:59.004770 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9002 01:35:59.005389 ==
9003 01:35:59.007826 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 01:35:59.015733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 01:35:59.016158 ==
9006 01:35:59.016492 DQS Delay:
9007 01:35:59.018505 DQS0 = 0, DQS1 = 0
9008 01:35:59.018920 DQM Delay:
9009 01:35:59.019248 DQM0 = 129, DQM1 = 126
9010 01:35:59.021064 DQ Delay:
9011 01:35:59.023948 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9012 01:35:59.028361 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9013 01:35:59.030631 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9014 01:35:59.034518 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9015 01:35:59.035040
9016 01:35:59.035381
9017 01:35:59.035688
9018 01:35:59.037587 [DramC_TX_OE_Calibration] TA2
9019 01:35:59.041111 Original DQ_B0 (3 6) =30, OEN = 27
9020 01:35:59.044467 Original DQ_B1 (3 6) =30, OEN = 27
9021 01:35:59.048655 24, 0x0, End_B0=24 End_B1=24
9022 01:35:59.049123 25, 0x0, End_B0=25 End_B1=25
9023 01:35:59.051110 26, 0x0, End_B0=26 End_B1=26
9024 01:35:59.054300 27, 0x0, End_B0=27 End_B1=27
9025 01:35:59.058427 28, 0x0, End_B0=28 End_B1=28
9026 01:35:59.058956 29, 0x0, End_B0=29 End_B1=29
9027 01:35:59.061338 30, 0x0, End_B0=30 End_B1=30
9028 01:35:59.064644 31, 0x4141, End_B0=30 End_B1=30
9029 01:35:59.068706 Byte0 end_step=30 best_step=27
9030 01:35:59.071051 Byte1 end_step=30 best_step=27
9031 01:35:59.075326 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 01:35:59.075743 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 01:35:59.076074
9034 01:35:59.078500
9035 01:35:59.084597 [DQSOSCAuto] RK1, (LSB)MR18= 0xe14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9036 01:35:59.087822 CH1 RK1: MR19=303, MR18=E14
9037 01:35:59.095099 CH1_RK1: MR19=0x303, MR18=0xE14, DQSOSC=399, MR23=63, INC=23, DEC=15
9038 01:35:59.095625 [RxdqsGatingPostProcess] freq 1600
9039 01:35:59.101076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 01:35:59.104489 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 01:35:59.108032 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 01:35:59.110620 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 01:35:59.115421 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 01:35:59.117813 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 01:35:59.121290 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 01:35:59.124897 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 01:35:59.127744 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 01:35:59.128206 Pre-setting of DQS Precalculation
9049 01:35:59.134717 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 01:35:59.141070 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 01:35:59.147844 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 01:35:59.148421
9053 01:35:59.148791
9054 01:35:59.150360 [Calibration Summary] 3200 Mbps
9055 01:35:59.153710 CH 0, Rank 0
9056 01:35:59.154171 SW Impedance : PASS
9057 01:35:59.156945 DUTY Scan : NO K
9058 01:35:59.160629 ZQ Calibration : PASS
9059 01:35:59.161238 Jitter Meter : NO K
9060 01:35:59.163778 CBT Training : PASS
9061 01:35:59.166883 Write leveling : PASS
9062 01:35:59.167566 RX DQS gating : PASS
9063 01:35:59.171842 RX DQ/DQS(RDDQC) : PASS
9064 01:35:59.173729 TX DQ/DQS : PASS
9065 01:35:59.174148 RX DATLAT : PASS
9066 01:35:59.176776 RX DQ/DQS(Engine): PASS
9067 01:35:59.182822 TX OE : PASS
9068 01:35:59.183240 All Pass.
9069 01:35:59.183570
9070 01:35:59.183994 CH 0, Rank 1
9071 01:35:59.184914 SW Impedance : PASS
9072 01:35:59.187201 DUTY Scan : NO K
9073 01:35:59.187786 ZQ Calibration : PASS
9074 01:35:59.190807 Jitter Meter : NO K
9075 01:35:59.191228 CBT Training : PASS
9076 01:35:59.193599 Write leveling : PASS
9077 01:35:59.196723 RX DQS gating : PASS
9078 01:35:59.197181 RX DQ/DQS(RDDQC) : PASS
9079 01:35:59.200502 TX DQ/DQS : PASS
9080 01:35:59.203845 RX DATLAT : PASS
9081 01:35:59.204377 RX DQ/DQS(Engine): PASS
9082 01:35:59.207168 TX OE : PASS
9083 01:35:59.207693 All Pass.
9084 01:35:59.208032
9085 01:35:59.210961 CH 1, Rank 0
9086 01:35:59.211380 SW Impedance : PASS
9087 01:35:59.213536 DUTY Scan : NO K
9088 01:35:59.216846 ZQ Calibration : PASS
9089 01:35:59.217306 Jitter Meter : NO K
9090 01:35:59.220542 CBT Training : PASS
9091 01:35:59.223812 Write leveling : PASS
9092 01:35:59.224229 RX DQS gating : PASS
9093 01:35:59.228401 RX DQ/DQS(RDDQC) : PASS
9094 01:35:59.230340 TX DQ/DQS : PASS
9095 01:35:59.230763 RX DATLAT : PASS
9096 01:35:59.233843 RX DQ/DQS(Engine): PASS
9097 01:35:59.234367 TX OE : PASS
9098 01:35:59.236807 All Pass.
9099 01:35:59.237274
9100 01:35:59.237620 CH 1, Rank 1
9101 01:35:59.241295 SW Impedance : PASS
9102 01:35:59.241713 DUTY Scan : NO K
9103 01:35:59.243767 ZQ Calibration : PASS
9104 01:35:59.246938 Jitter Meter : NO K
9105 01:35:59.247472 CBT Training : PASS
9106 01:35:59.250646 Write leveling : PASS
9107 01:35:59.253636 RX DQS gating : PASS
9108 01:35:59.254147 RX DQ/DQS(RDDQC) : PASS
9109 01:35:59.257038 TX DQ/DQS : PASS
9110 01:35:59.260292 RX DATLAT : PASS
9111 01:35:59.260852 RX DQ/DQS(Engine): PASS
9112 01:35:59.263520 TX OE : PASS
9113 01:35:59.263938 All Pass.
9114 01:35:59.264270
9115 01:35:59.267862 DramC Write-DBI on
9116 01:35:59.270120 PER_BANK_REFRESH: Hybrid Mode
9117 01:35:59.270642 TX_TRACKING: ON
9118 01:35:59.280528 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 01:35:59.287044 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 01:35:59.293873 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 01:35:59.297292 [FAST_K] Save calibration result to emmc
9122 01:35:59.301121 sync common calibartion params.
9123 01:35:59.304620 sync cbt_mode0:1, 1:1
9124 01:35:59.307169 dram_init: ddr_geometry: 2
9125 01:35:59.307685 dram_init: ddr_geometry: 2
9126 01:35:59.311896 dram_init: ddr_geometry: 2
9127 01:35:59.314146 0:dram_rank_size:100000000
9128 01:35:59.314572 1:dram_rank_size:100000000
9129 01:35:59.320043 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 01:35:59.323390 DFS_SHUFFLE_HW_MODE: ON
9131 01:35:59.327477 dramc_set_vcore_voltage set vcore to 725000
9132 01:35:59.331234 Read voltage for 1600, 0
9133 01:35:59.331651 Vio18 = 0
9134 01:35:59.332066 Vcore = 725000
9135 01:35:59.333884 Vdram = 0
9136 01:35:59.334301 Vddq = 0
9137 01:35:59.334630 Vmddr = 0
9138 01:35:59.337051 switch to 3200 Mbps bootup
9139 01:35:59.337471 [DramcRunTimeConfig]
9140 01:35:59.340324 PHYPLL
9141 01:35:59.340776 DPM_CONTROL_AFTERK: ON
9142 01:35:59.343660 PER_BANK_REFRESH: ON
9143 01:35:59.346815 REFRESH_OVERHEAD_REDUCTION: ON
9144 01:35:59.347237 CMD_PICG_NEW_MODE: OFF
9145 01:35:59.350444 XRTWTW_NEW_MODE: ON
9146 01:35:59.350887 XRTRTR_NEW_MODE: ON
9147 01:35:59.353595 TX_TRACKING: ON
9148 01:35:59.354016 RDSEL_TRACKING: OFF
9149 01:35:59.356718 DQS Precalculation for DVFS: ON
9150 01:35:59.360626 RX_TRACKING: OFF
9151 01:35:59.361419 HW_GATING DBG: ON
9152 01:35:59.363836 ZQCS_ENABLE_LP4: ON
9153 01:35:59.364255 RX_PICG_NEW_MODE: ON
9154 01:35:59.366992 TX_PICG_NEW_MODE: ON
9155 01:35:59.367451 ENABLE_RX_DCM_DPHY: ON
9156 01:35:59.370738 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 01:35:59.374848 DUMMY_READ_FOR_TRACKING: OFF
9158 01:35:59.376960 !!! SPM_CONTROL_AFTERK: OFF
9159 01:35:59.380466 !!! SPM could not control APHY
9160 01:35:59.381096 IMPEDANCE_TRACKING: ON
9161 01:35:59.383806 TEMP_SENSOR: ON
9162 01:35:59.384270 HW_SAVE_FOR_SR: OFF
9163 01:35:59.387309 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 01:35:59.389999 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 01:35:59.393940 Read ODT Tracking: ON
9166 01:35:59.397054 Refresh Rate DeBounce: ON
9167 01:35:59.397523 DFS_NO_QUEUE_FLUSH: ON
9168 01:35:59.400546 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 01:35:59.404543 ENABLE_DFS_RUNTIME_MRW: OFF
9170 01:35:59.407043 DDR_RESERVE_NEW_MODE: ON
9171 01:35:59.407607 MR_CBT_SWITCH_FREQ: ON
9172 01:35:59.411296 =========================
9173 01:35:59.429696 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 01:35:59.432400 dram_init: ddr_geometry: 2
9175 01:35:59.450766 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 01:35:59.453496 dram_init: dram init end (result: 0)
9177 01:35:59.460218 DRAM-K: Full calibration passed in 24592 msecs
9178 01:35:59.463496 MRC: failed to locate region type 0.
9179 01:35:59.464215 DRAM rank0 size:0x100000000,
9180 01:35:59.467111 DRAM rank1 size=0x100000000
9181 01:35:59.476963 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 01:35:59.483542 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 01:35:59.490157 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 01:35:59.496921 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 01:35:59.500258 DRAM rank0 size:0x100000000,
9186 01:35:59.503736 DRAM rank1 size=0x100000000
9187 01:35:59.503893 CBMEM:
9188 01:35:59.507529 IMD: root @ 0xfffff000 254 entries.
9189 01:35:59.510579 IMD: root @ 0xffffec00 62 entries.
9190 01:35:59.513303 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 01:35:59.517045 WARNING: RO_VPD is uninitialized or empty.
9192 01:35:59.523736 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 01:35:59.530683 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 01:35:59.543944 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9195 01:35:59.554760 BS: romstage times (exec / console): total (unknown) / 24095 ms
9196 01:35:59.555328
9197 01:35:59.555697
9198 01:35:59.564544 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 01:35:59.567690 ARM64: Exception handlers installed.
9200 01:35:59.571948 ARM64: Testing exception
9201 01:35:59.574930 ARM64: Done test exception
9202 01:35:59.575493 Enumerating buses...
9203 01:35:59.578465 Show all devs... Before device enumeration.
9204 01:35:59.581005 Root Device: enabled 1
9205 01:35:59.585118 CPU_CLUSTER: 0: enabled 1
9206 01:35:59.585706 CPU: 00: enabled 1
9207 01:35:59.589140 Compare with tree...
9208 01:35:59.589706 Root Device: enabled 1
9209 01:35:59.591176 CPU_CLUSTER: 0: enabled 1
9210 01:35:59.594736 CPU: 00: enabled 1
9211 01:35:59.595217 Root Device scanning...
9212 01:35:59.597741 scan_static_bus for Root Device
9213 01:35:59.601512 CPU_CLUSTER: 0 enabled
9214 01:35:59.605648 scan_static_bus for Root Device done
9215 01:35:59.607646 scan_bus: bus Root Device finished in 8 msecs
9216 01:35:59.608115 done
9217 01:35:59.614748 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 01:35:59.618559 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 01:35:59.624867 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 01:35:59.628630 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 01:35:59.631542 Allocating resources...
9222 01:35:59.632102 Reading resources...
9223 01:35:59.638970 Root Device read_resources bus 0 link: 0
9224 01:35:59.639528 DRAM rank0 size:0x100000000,
9225 01:35:59.641004 DRAM rank1 size=0x100000000
9226 01:35:59.645576 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 01:35:59.648788 CPU: 00 missing read_resources
9228 01:35:59.651341 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 01:35:59.657785 Root Device read_resources bus 0 link: 0 done
9230 01:35:59.658656 Done reading resources.
9231 01:35:59.664465 Show resources in subtree (Root Device)...After reading.
9232 01:35:59.667870 Root Device child on link 0 CPU_CLUSTER: 0
9233 01:35:59.671484 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 01:35:59.681047 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 01:35:59.681611 CPU: 00
9236 01:35:59.685144 Root Device assign_resources, bus 0 link: 0
9237 01:35:59.688298 CPU_CLUSTER: 0 missing set_resources
9238 01:35:59.691445 Root Device assign_resources, bus 0 link: 0 done
9239 01:35:59.694818 Done setting resources.
9240 01:35:59.701459 Show resources in subtree (Root Device)...After assigning values.
9241 01:35:59.704686 Root Device child on link 0 CPU_CLUSTER: 0
9242 01:35:59.707733 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 01:35:59.718073 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 01:35:59.718667 CPU: 00
9245 01:35:59.721697 Done allocating resources.
9246 01:35:59.725041 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 01:35:59.728105 Enabling resources...
9248 01:35:59.728664 done.
9249 01:35:59.731006 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 01:35:59.734562 Initializing devices...
9251 01:35:59.737981 Root Device init
9252 01:35:59.738548 init hardware done!
9253 01:35:59.741268 0x00000018: ctrlr->caps
9254 01:35:59.741842 52.000 MHz: ctrlr->f_max
9255 01:35:59.744643 0.400 MHz: ctrlr->f_min
9256 01:35:59.748165 0x40ff8080: ctrlr->voltages
9257 01:35:59.748738 sclk: 390625
9258 01:35:59.751123 Bus Width = 1
9259 01:35:59.751588 sclk: 390625
9260 01:35:59.751975 Bus Width = 1
9261 01:35:59.755165 Early init status = 3
9262 01:35:59.758091 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 01:35:59.764621 in-header: 03 fc 00 00 01 00 00 00
9264 01:35:59.766339 in-data: 00
9265 01:35:59.769970 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 01:35:59.775341 in-header: 03 fd 00 00 00 00 00 00
9267 01:35:59.779076 in-data:
9268 01:35:59.781582 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 01:35:59.786410 in-header: 03 fc 00 00 01 00 00 00
9270 01:35:59.789576 in-data: 00
9271 01:35:59.792753 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 01:35:59.799086 in-header: 03 fd 00 00 00 00 00 00
9273 01:35:59.801917 in-data:
9274 01:35:59.805813 [SSUSB] Setting up USB HOST controller...
9275 01:35:59.809629 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 01:35:59.812663 [SSUSB] phy power-on done.
9277 01:35:59.816068 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 01:35:59.822897 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 01:35:59.826069 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 01:35:59.833158 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 01:35:59.839859 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 01:35:59.845937 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 01:35:59.853138 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 01:35:59.859815 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9285 01:35:59.860390 SPM: binary array size = 0x9dc
9286 01:35:59.865509 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 01:35:59.872595 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 01:35:59.879389 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 01:35:59.882290 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 01:35:59.885862 configure_display: Starting display init
9291 01:35:59.922032 anx7625_power_on_init: Init interface.
9292 01:35:59.925524 anx7625_disable_pd_protocol: Disabled PD feature.
9293 01:35:59.929046 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 01:35:59.957677 anx7625_start_dp_work: Secure OCM version=00
9295 01:35:59.960542 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 01:35:59.974777 sp_tx_get_edid_block: EDID Block = 1
9297 01:36:00.077815 Extracted contents:
9298 01:36:00.082293 header: 00 ff ff ff ff ff ff 00
9299 01:36:00.084294 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 01:36:00.087970 version: 01 04
9301 01:36:00.090691 basic params: 95 1f 11 78 0a
9302 01:36:00.093728 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 01:36:00.097116 established: 00 00 00
9304 01:36:00.104047 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 01:36:00.106852 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 01:36:00.113835 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 01:36:00.120711 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 01:36:00.127008 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 01:36:00.130854 extensions: 00
9310 01:36:00.131409 checksum: fb
9311 01:36:00.131776
9312 01:36:00.133956 Manufacturer: IVO Model 57d Serial Number 0
9313 01:36:00.137379 Made week 0 of 2020
9314 01:36:00.137931 EDID version: 1.4
9315 01:36:00.140735 Digital display
9316 01:36:00.143572 6 bits per primary color channel
9317 01:36:00.144130 DisplayPort interface
9318 01:36:00.147967 Maximum image size: 31 cm x 17 cm
9319 01:36:00.150185 Gamma: 220%
9320 01:36:00.150741 Check DPMS levels
9321 01:36:00.153761 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 01:36:00.157624 First detailed timing is preferred timing
9323 01:36:00.160290 Established timings supported:
9324 01:36:00.163989 Standard timings supported:
9325 01:36:00.164542 Detailed timings
9326 01:36:00.170418 Hex of detail: 383680a07038204018303c0035ae10000019
9327 01:36:00.173583 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 01:36:00.180201 0780 0798 07c8 0820 hborder 0
9329 01:36:00.183638 0438 043b 0447 0458 vborder 0
9330 01:36:00.184227 -hsync -vsync
9331 01:36:00.186876 Did detailed timing
9332 01:36:00.190327 Hex of detail: 000000000000000000000000000000000000
9333 01:36:00.193972 Manufacturer-specified data, tag 0
9334 01:36:00.201547 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 01:36:00.202100 ASCII string: InfoVision
9336 01:36:00.206703 Hex of detail: 000000fe00523134304e574635205248200a
9337 01:36:00.207249 ASCII string: R140NWF5 RH
9338 01:36:00.210989 Checksum
9339 01:36:00.211671 Checksum: 0xfb (valid)
9340 01:36:00.218122 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 01:36:00.219990 DSI data_rate: 832800000 bps
9342 01:36:00.224075 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 01:36:00.227080 anx7625_parse_edid: pixelclock(138800).
9344 01:36:00.234226 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 01:36:00.237486 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 01:36:00.240433 anx7625_dsi_config: config dsi.
9347 01:36:00.247554 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 01:36:00.259606 anx7625_dsi_config: success to config DSI
9349 01:36:00.262826 anx7625_dp_start: MIPI phy setup OK.
9350 01:36:00.265743 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 01:36:00.269730 mtk_ddp_mode_set invalid vrefresh 60
9352 01:36:00.273281 main_disp_path_setup
9353 01:36:00.273844 ovl_layer_smi_id_en
9354 01:36:00.276086 ovl_layer_smi_id_en
9355 01:36:00.276657 ccorr_config
9356 01:36:00.277085 aal_config
9357 01:36:00.279608 gamma_config
9358 01:36:00.280175 postmask_config
9359 01:36:00.283479 dither_config
9360 01:36:00.286676 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 01:36:00.292956 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 01:36:00.296665 Root Device init finished in 555 msecs
9363 01:36:00.297233 CPU_CLUSTER: 0 init
9364 01:36:00.308360 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 01:36:00.310059 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 01:36:00.313023 APU_MBOX 0x190000b0 = 0x10001
9367 01:36:00.316451 APU_MBOX 0x190001b0 = 0x10001
9368 01:36:00.320081 APU_MBOX 0x190005b0 = 0x10001
9369 01:36:00.322812 APU_MBOX 0x190006b0 = 0x10001
9370 01:36:00.326292 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 01:36:00.338628 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9372 01:36:00.350926 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 01:36:00.357445 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 01:36:00.369298 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9375 01:36:00.378701 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 01:36:00.381332 CPU_CLUSTER: 0 init finished in 81 msecs
9377 01:36:00.385136 Devices initialized
9378 01:36:00.388292 Show all devs... After init.
9379 01:36:00.388904 Root Device: enabled 1
9380 01:36:00.391467 CPU_CLUSTER: 0: enabled 1
9381 01:36:00.394997 CPU: 00: enabled 1
9382 01:36:00.398476 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9383 01:36:00.401381 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 01:36:00.404800 ELOG: NV offset 0x57f000 size 0x1000
9385 01:36:00.411468 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 01:36:00.417845 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 01:36:00.421160 ELOG: Event(17) added with size 13 at 2024-06-05 01:36:00 UTC
9388 01:36:00.424840 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 01:36:00.428572 in-header: 03 c2 00 00 2c 00 00 00
9390 01:36:00.441548 in-data: 9d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 01:36:00.448400 ELOG: Event(A1) added with size 10 at 2024-06-05 01:36:00 UTC
9392 01:36:00.455629 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 01:36:00.461617 ELOG: Event(A0) added with size 9 at 2024-06-05 01:36:00 UTC
9394 01:36:00.465095 elog_add_boot_reason: Logged dev mode boot
9395 01:36:00.468449 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9396 01:36:00.471540 Finalize devices...
9397 01:36:00.472065 Devices finalized
9398 01:36:00.478547 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 01:36:00.481756 Writing coreboot table at 0xffe64000
9400 01:36:00.485182 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 01:36:00.488291 1. 0000000040000000-00000000400fffff: RAM
9402 01:36:00.492390 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 01:36:00.499322 3. 000000004032b000-00000000545fffff: RAM
9404 01:36:00.502030 4. 0000000054600000-000000005465ffff: BL31
9405 01:36:00.505909 5. 0000000054660000-00000000ffe63fff: RAM
9406 01:36:00.508519 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 01:36:00.515159 7. 0000000100000000-000000023fffffff: RAM
9408 01:36:00.515681 Passing 5 GPIOs to payload:
9409 01:36:00.522455 NAME | PORT | POLARITY | VALUE
9410 01:36:00.525728 EC in RW | 0x000000aa | low | undefined
9411 01:36:00.532318 EC interrupt | 0x00000005 | low | undefined
9412 01:36:00.535617 TPM interrupt | 0x000000ab | high | undefined
9413 01:36:00.538401 SD card detect | 0x00000011 | high | undefined
9414 01:36:00.545320 speaker enable | 0x00000093 | high | undefined
9415 01:36:00.550009 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 01:36:00.551600 in-header: 03 f9 00 00 02 00 00 00
9417 01:36:00.552068 in-data: 02 00
9418 01:36:00.555533 ADC[4]: Raw value=899852 ID=7
9419 01:36:00.558169 ADC[3]: Raw value=213336 ID=1
9420 01:36:00.558774 RAM Code: 0x71
9421 01:36:00.561461 ADC[6]: Raw value=74557 ID=0
9422 01:36:00.565956 ADC[5]: Raw value=212229 ID=1
9423 01:36:00.566456 SKU Code: 0x1
9424 01:36:00.571554 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 634c
9425 01:36:00.575466 coreboot table: 964 bytes.
9426 01:36:00.578320 IMD ROOT 0. 0xfffff000 0x00001000
9427 01:36:00.582009 IMD SMALL 1. 0xffffe000 0x00001000
9428 01:36:00.584972 RO MCACHE 2. 0xffffc000 0x00001104
9429 01:36:00.588041 CONSOLE 3. 0xfff7c000 0x00080000
9430 01:36:00.592402 FMAP 4. 0xfff7b000 0x00000452
9431 01:36:00.596101 TIME STAMP 5. 0xfff7a000 0x00000910
9432 01:36:00.598405 VBOOT WORK 6. 0xfff66000 0x00014000
9433 01:36:00.602081 RAMOOPS 7. 0xffe66000 0x00100000
9434 01:36:00.605065 COREBOOT 8. 0xffe64000 0x00002000
9435 01:36:00.605584 IMD small region:
9436 01:36:00.609280 IMD ROOT 0. 0xffffec00 0x00000400
9437 01:36:00.611868 VPD 1. 0xffffeb80 0x0000006c
9438 01:36:00.614952 MMC STATUS 2. 0xffffeb60 0x00000004
9439 01:36:00.622843 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 01:36:00.623476 Probing TPM: done!
9441 01:36:00.628379 Connected to device vid:did:rid of 1ae0:0028:00
9442 01:36:00.635435 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9443 01:36:00.638514 Initialized TPM device CR50 revision 0
9444 01:36:00.642721 Checking cr50 for pending updates
9445 01:36:00.649888 Reading cr50 TPM mode
9446 01:36:00.657474 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 01:36:00.663692 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 01:36:00.703486 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9449 01:36:00.707881 Checking segment from ROM address 0x40100000
9450 01:36:00.710471 Checking segment from ROM address 0x4010001c
9451 01:36:00.717176 Loading segment from ROM address 0x40100000
9452 01:36:00.717727 code (compression=0)
9453 01:36:00.723949 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 01:36:00.733963 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 01:36:00.734529 it's not compressed!
9456 01:36:00.740276 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 01:36:00.743649 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 01:36:00.763386 Loading segment from ROM address 0x4010001c
9459 01:36:00.763932 Entry Point 0x80000000
9460 01:36:00.767639 Loaded segments
9461 01:36:00.770368 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 01:36:00.777399 Jumping to boot code at 0x80000000(0xffe64000)
9463 01:36:00.784520 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 01:36:00.791255 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 01:36:00.798194 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9466 01:36:00.801591 Checking segment from ROM address 0x40100000
9467 01:36:00.805360 Checking segment from ROM address 0x4010001c
9468 01:36:00.809432 Loading segment from ROM address 0x40100000
9469 01:36:00.811457 code (compression=1)
9470 01:36:00.818380 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 01:36:00.828290 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 01:36:00.828891 using LZMA
9473 01:36:00.837100 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 01:36:00.843791 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 01:36:00.846776 Loading segment from ROM address 0x4010001c
9476 01:36:00.847336 Entry Point 0x54601000
9477 01:36:00.850277 Loaded segments
9478 01:36:00.853443 NOTICE: MT8192 bl31_setup
9479 01:36:00.860390 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 01:36:00.863937 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 01:36:00.866769 WARNING: region 0:
9482 01:36:00.870401 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 01:36:00.870920 WARNING: region 1:
9484 01:36:00.877625 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 01:36:00.878188 WARNING: region 2:
9486 01:36:00.884356 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 01:36:00.887161 WARNING: region 3:
9488 01:36:00.890640 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 01:36:00.894526 WARNING: region 4:
9490 01:36:00.897067 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 01:36:00.900808 WARNING: region 5:
9492 01:36:00.903666 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 01:36:00.907412 WARNING: region 6:
9494 01:36:00.910612 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 01:36:00.911176 WARNING: region 7:
9496 01:36:00.917178 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 01:36:00.924216 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 01:36:00.928541 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 01:36:00.931377 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 01:36:00.933887 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 01:36:00.940882 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 01:36:00.944504 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 01:36:00.951105 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 01:36:00.954264 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 01:36:00.957654 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 01:36:00.964569 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 01:36:00.967381 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 01:36:00.971058 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 01:36:00.977959 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 01:36:00.981182 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 01:36:00.987422 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 01:36:00.993563 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 01:36:00.994813 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 01:36:01.001533 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 01:36:01.004951 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 01:36:01.007753 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 01:36:01.014345 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 01:36:01.018550 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 01:36:01.024279 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 01:36:01.027823 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 01:36:01.031300 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 01:36:01.037807 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 01:36:01.041601 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 01:36:01.045517 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 01:36:01.051574 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 01:36:01.054529 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 01:36:01.061437 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 01:36:01.065402 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 01:36:01.068365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 01:36:01.071865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 01:36:01.078183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 01:36:01.083091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 01:36:01.085922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 01:36:01.088047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 01:36:01.095702 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 01:36:01.098687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 01:36:01.101383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 01:36:01.107492 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 01:36:01.108760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 01:36:01.115932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 01:36:01.118639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 01:36:01.121684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 01:36:01.128392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 01:36:01.131858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 01:36:01.135411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 01:36:01.141967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 01:36:01.145229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 01:36:01.152776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 01:36:01.155048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 01:36:01.158533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 01:36:01.165152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 01:36:01.169293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 01:36:01.175466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 01:36:01.178969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 01:36:01.182663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 01:36:01.188743 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 01:36:01.192692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 01:36:01.198836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 01:36:01.202016 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 01:36:01.209229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 01:36:01.212727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 01:36:01.222272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 01:36:01.223192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 01:36:01.225336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 01:36:01.232204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 01:36:01.235383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 01:36:01.242581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 01:36:01.245938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 01:36:01.248923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 01:36:01.255408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 01:36:01.258683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 01:36:01.265661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 01:36:01.269927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 01:36:01.276091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 01:36:01.279275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 01:36:01.282683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 01:36:01.289206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 01:36:01.292227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 01:36:01.299533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 01:36:01.302120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 01:36:01.308918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 01:36:01.313040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 01:36:01.315517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 01:36:01.323819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 01:36:01.326357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 01:36:01.332667 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 01:36:01.335929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 01:36:01.339337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 01:36:01.347260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 01:36:01.349723 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 01:36:01.356517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 01:36:01.360755 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 01:36:01.363422 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 01:36:01.369624 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 01:36:01.373284 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 01:36:01.376537 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 01:36:01.379595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 01:36:01.386635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 01:36:01.389511 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 01:36:01.398695 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 01:36:01.399921 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 01:36:01.404150 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 01:36:01.410057 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 01:36:01.413370 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 01:36:01.420038 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 01:36:01.423732 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 01:36:01.426618 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 01:36:01.433882 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 01:36:01.437073 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 01:36:01.440452 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 01:36:01.447153 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 01:36:01.451022 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 01:36:01.454521 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 01:36:01.461607 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 01:36:01.464112 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 01:36:01.467204 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 01:36:01.471971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 01:36:01.477046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 01:36:01.480888 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 01:36:01.483831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 01:36:01.490289 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 01:36:01.494052 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 01:36:01.497273 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 01:36:01.504070 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 01:36:01.507239 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 01:36:01.514591 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 01:36:01.516820 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 01:36:01.521439 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 01:36:01.527711 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 01:36:01.530767 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 01:36:01.533527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 01:36:01.540933 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 01:36:01.544621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 01:36:01.547180 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 01:36:01.555078 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 01:36:01.557547 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 01:36:01.564438 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 01:36:01.568881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 01:36:01.570816 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 01:36:01.578065 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 01:36:01.580933 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 01:36:01.584302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 01:36:01.591439 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 01:36:01.594714 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 01:36:01.601130 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 01:36:01.605195 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 01:36:01.607647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 01:36:01.614355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 01:36:01.618061 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 01:36:01.621613 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 01:36:01.628166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 01:36:01.631334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 01:36:01.638311 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 01:36:01.641726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 01:36:01.644816 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 01:36:01.651716 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 01:36:01.655180 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 01:36:01.658187 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 01:36:01.665017 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 01:36:01.668534 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 01:36:01.675772 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 01:36:01.678645 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 01:36:01.681584 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 01:36:01.688804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 01:36:01.691505 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 01:36:01.695324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 01:36:01.702815 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 01:36:01.705094 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 01:36:01.712273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 01:36:01.715388 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 01:36:01.718854 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 01:36:01.725283 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 01:36:01.729150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 01:36:01.737040 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 01:36:01.738886 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 01:36:01.742101 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 01:36:01.748933 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 01:36:01.752007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 01:36:01.755541 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 01:36:01.761908 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 01:36:01.765341 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 01:36:01.772145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 01:36:01.775552 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 01:36:01.778416 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 01:36:01.785814 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 01:36:01.789085 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 01:36:01.795989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 01:36:01.798605 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 01:36:01.804948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 01:36:01.808267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 01:36:01.812093 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 01:36:01.818632 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 01:36:01.822004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 01:36:01.829620 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 01:36:01.832108 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 01:36:01.835542 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 01:36:01.842664 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 01:36:01.845088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 01:36:01.852119 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 01:36:01.855483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 01:36:01.859806 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 01:36:01.865929 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 01:36:01.869071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 01:36:01.875245 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 01:36:01.878786 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 01:36:01.882552 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 01:36:01.888609 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 01:36:01.893536 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 01:36:01.898904 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 01:36:01.901984 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 01:36:01.905443 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 01:36:01.913469 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 01:36:01.915632 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 01:36:01.921977 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 01:36:01.925214 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 01:36:01.932076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 01:36:01.935614 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 01:36:01.939530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 01:36:01.945528 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 01:36:01.949384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 01:36:01.956068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 01:36:01.958943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 01:36:01.962150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 01:36:01.969069 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 01:36:01.972217 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 01:36:01.976970 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 01:36:01.982264 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 01:36:01.985554 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 01:36:01.989032 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 01:36:01.992827 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 01:36:01.999546 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 01:36:02.003598 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 01:36:02.005683 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 01:36:02.011895 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 01:36:02.015206 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 01:36:02.019002 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 01:36:02.025905 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 01:36:02.029405 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 01:36:02.035636 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 01:36:02.039219 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 01:36:02.041994 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 01:36:02.048769 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 01:36:02.053095 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 01:36:02.055108 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 01:36:02.062183 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 01:36:02.065275 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 01:36:02.069274 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 01:36:02.075677 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 01:36:02.078957 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 01:36:02.082154 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 01:36:02.089093 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 01:36:02.091859 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 01:36:02.099286 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 01:36:02.102464 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 01:36:02.105429 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 01:36:02.111941 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 01:36:02.114968 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 01:36:02.121973 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 01:36:02.125042 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 01:36:02.128410 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 01:36:02.135684 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 01:36:02.138754 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 01:36:02.141753 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 01:36:02.148452 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 01:36:02.152079 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 01:36:02.156019 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 01:36:02.158627 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 01:36:02.165370 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 01:36:02.168858 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 01:36:02.172485 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 01:36:02.176038 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 01:36:02.179186 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 01:36:02.185888 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 01:36:02.188944 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 01:36:02.191982 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 01:36:02.195569 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 01:36:02.202417 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 01:36:02.205684 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 01:36:02.208816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 01:36:02.215742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 01:36:02.218875 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 01:36:02.225815 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 01:36:02.229186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 01:36:02.235677 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 01:36:02.238881 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 01:36:02.241860 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 01:36:02.248493 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 01:36:02.252003 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 01:36:02.258271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 01:36:02.262528 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 01:36:02.265836 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 01:36:02.272034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 01:36:02.274879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 01:36:02.281711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 01:36:02.284763 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 01:36:02.288699 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 01:36:02.295197 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 01:36:02.298573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 01:36:02.305227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 01:36:02.308591 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 01:36:02.311574 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 01:36:02.318336 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 01:36:02.322599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 01:36:02.328625 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 01:36:02.331793 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 01:36:02.334964 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 01:36:02.342186 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 01:36:02.345226 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 01:36:02.351909 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 01:36:02.355903 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 01:36:02.358435 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 01:36:02.365332 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 01:36:02.368800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 01:36:02.374912 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 01:36:02.379309 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 01:36:02.385093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 01:36:02.388870 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 01:36:02.392205 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 01:36:02.398311 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 01:36:02.401736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 01:36:02.405230 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 01:36:02.412007 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 01:36:02.415171 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 01:36:02.422149 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 01:36:02.425443 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 01:36:02.429415 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 01:36:02.435408 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 01:36:02.438162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 01:36:02.445147 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 01:36:02.449260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 01:36:02.455379 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 01:36:02.458497 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 01:36:02.462046 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 01:36:02.468569 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 01:36:02.471759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 01:36:02.475039 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 01:36:02.481386 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 01:36:02.484676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 01:36:02.491648 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 01:36:02.495358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 01:36:02.501465 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 01:36:02.505148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 01:36:02.508902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 01:36:02.515792 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 01:36:02.518863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 01:36:02.521706 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 01:36:02.529953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 01:36:02.532017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 01:36:02.538549 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 01:36:02.542255 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 01:36:02.545614 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 01:36:02.552341 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 01:36:02.555952 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 01:36:02.562032 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 01:36:02.565886 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 01:36:02.572824 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 01:36:02.575265 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 01:36:02.579444 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 01:36:02.584876 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 01:36:02.588437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 01:36:02.595588 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 01:36:02.598559 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 01:36:02.604954 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 01:36:02.608834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 01:36:02.614874 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 01:36:02.618136 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 01:36:02.621823 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 01:36:02.628726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 01:36:02.631998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 01:36:02.639568 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 01:36:02.642769 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 01:36:02.648518 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 01:36:02.653616 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 01:36:02.654866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 01:36:02.662062 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 01:36:02.665907 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 01:36:02.672150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 01:36:02.675408 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 01:36:02.681935 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 01:36:02.685860 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 01:36:02.688528 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 01:36:02.695658 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 01:36:02.699371 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 01:36:02.705156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 01:36:02.708569 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 01:36:02.711903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 01:36:02.718369 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 01:36:02.722102 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 01:36:02.729522 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 01:36:02.731877 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 01:36:02.739192 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 01:36:02.741923 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 01:36:02.745712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 01:36:02.752360 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 01:36:02.755693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 01:36:02.762753 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 01:36:02.765559 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 01:36:02.772248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 01:36:02.776275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 01:36:02.778360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 01:36:02.785341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 01:36:02.788856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 01:36:02.795266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 01:36:02.799131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 01:36:02.805155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 01:36:02.808469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 01:36:02.815584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 01:36:02.818577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 01:36:02.825048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 01:36:02.828256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 01:36:02.835611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 01:36:02.838755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 01:36:02.845260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 01:36:02.848630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 01:36:02.852120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 01:36:02.858324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 01:36:02.861894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 01:36:02.868689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 01:36:02.872090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 01:36:02.878813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 01:36:02.881715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 01:36:02.888254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 01:36:02.891525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 01:36:02.898184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 01:36:02.901328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 01:36:02.907955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 01:36:02.911928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 01:36:02.918483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 01:36:02.921817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 01:36:02.928664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 01:36:02.931673 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 01:36:02.935540 INFO: [APUAPC] vio 0
9933 01:36:02.938304 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 01:36:02.945122 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 01:36:02.948430 INFO: [APUAPC] D0_APC_0: 0x400510
9936 01:36:02.948855 INFO: [APUAPC] D0_APC_1: 0x0
9937 01:36:02.951922 INFO: [APUAPC] D0_APC_2: 0x1540
9938 01:36:02.955213 INFO: [APUAPC] D0_APC_3: 0x0
9939 01:36:02.958903 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 01:36:02.962035 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 01:36:02.965336 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 01:36:02.969262 INFO: [APUAPC] D1_APC_3: 0x0
9943 01:36:02.971713 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 01:36:02.975359 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 01:36:02.979346 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 01:36:02.981792 INFO: [APUAPC] D2_APC_3: 0x0
9947 01:36:02.985393 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 01:36:02.988208 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 01:36:02.991870 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 01:36:02.995145 INFO: [APUAPC] D3_APC_3: 0x0
9951 01:36:02.998344 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 01:36:03.001358 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 01:36:03.004691 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 01:36:03.008229 INFO: [APUAPC] D4_APC_3: 0x0
9955 01:36:03.011459 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 01:36:03.014791 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 01:36:03.018343 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 01:36:03.021406 INFO: [APUAPC] D5_APC_3: 0x0
9959 01:36:03.024697 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 01:36:03.028824 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 01:36:03.031929 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 01:36:03.034857 INFO: [APUAPC] D6_APC_3: 0x0
9963 01:36:03.038563 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 01:36:03.041420 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 01:36:03.045107 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 01:36:03.048522 INFO: [APUAPC] D7_APC_3: 0x0
9967 01:36:03.051395 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 01:36:03.055307 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 01:36:03.059487 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 01:36:03.062049 INFO: [APUAPC] D8_APC_3: 0x0
9971 01:36:03.065362 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 01:36:03.068418 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 01:36:03.071932 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 01:36:03.072493 INFO: [APUAPC] D9_APC_3: 0x0
9975 01:36:03.078217 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 01:36:03.081388 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 01:36:03.084378 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 01:36:03.088257 INFO: [APUAPC] D10_APC_3: 0x0
9979 01:36:03.092130 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 01:36:03.094994 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 01:36:03.099281 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 01:36:03.099840 INFO: [APUAPC] D11_APC_3: 0x0
9983 01:36:03.105545 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 01:36:03.108620 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 01:36:03.111510 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 01:36:03.111975 INFO: [APUAPC] D12_APC_3: 0x0
9987 01:36:03.117882 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 01:36:03.121609 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 01:36:03.125593 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 01:36:03.128421 INFO: [APUAPC] D13_APC_3: 0x0
9991 01:36:03.131346 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 01:36:03.134864 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 01:36:03.138077 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 01:36:03.141506 INFO: [APUAPC] D14_APC_3: 0x0
9995 01:36:03.144426 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 01:36:03.148125 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 01:36:03.151223 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 01:36:03.154489 INFO: [APUAPC] D15_APC_3: 0x0
9999 01:36:03.155048 INFO: [APUAPC] APC_CON: 0x4
10000 01:36:03.157971 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 01:36:03.161298 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 01:36:03.164830 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 01:36:03.168260 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 01:36:03.172270 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 01:36:03.174924 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 01:36:03.177833 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 01:36:03.181581 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 01:36:03.184335 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 01:36:03.184800 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 01:36:03.188420 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 01:36:03.191492 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 01:36:03.194875 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 01:36:03.198144 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 01:36:03.201375 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 01:36:03.204470 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 01:36:03.208245 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 01:36:03.212385 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 01:36:03.214369 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 01:36:03.217888 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 01:36:03.218349 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 01:36:03.221163 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 01:36:03.224842 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 01:36:03.228231 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 01:36:03.230891 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 01:36:03.234471 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 01:36:03.237787 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 01:36:03.241052 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 01:36:03.244955 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 01:36:03.247959 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 01:36:03.251130 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 01:36:03.254053 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 01:36:03.258294 INFO: [NOCDAPC] APC_CON: 0x4
10033 01:36:03.260915 INFO: [APUAPC] set_apusys_apc done
10034 01:36:03.261588 INFO: [DEVAPC] devapc_init done
10035 01:36:03.268056 INFO: GICv3 without legacy support detected.
10036 01:36:03.271194 INFO: ARM GICv3 driver initialized in EL3
10037 01:36:03.274561 INFO: Maximum SPI INTID supported: 639
10038 01:36:03.278545 INFO: BL31: Initializing runtime services
10039 01:36:03.284563 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 01:36:03.288798 INFO: SPM: enable CPC mode
10041 01:36:03.291622 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 01:36:03.298610 INFO: BL31: Preparing for EL3 exit to normal world
10043 01:36:03.301106 INFO: Entry point address = 0x80000000
10044 01:36:03.301582 INFO: SPSR = 0x8
10045 01:36:03.308604
10046 01:36:03.309216
10047 01:36:03.309589
10048 01:36:03.311740 Starting depthcharge on Spherion...
10049 01:36:03.312319
10050 01:36:03.312688 Wipe memory regions:
10051 01:36:03.313076
10052 01:36:03.315796 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10053 01:36:03.316350 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 01:36:03.316799 Setting prompt string to ['asurada:']
10055 01:36:03.317321 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 01:36:03.318040 [0x00000040000000, 0x00000054600000)
10057 01:36:03.437359
10058 01:36:03.437907 [0x00000054660000, 0x00000080000000)
10059 01:36:03.697879
10060 01:36:03.698436 [0x000000821a7280, 0x000000ffe64000)
10061 01:36:04.442976
10062 01:36:04.443527 [0x00000100000000, 0x00000240000000)
10063 01:36:06.332019
10064 01:36:06.335653 Initializing XHCI USB controller at 0x11200000.
10065 01:36:07.374640
10066 01:36:07.377366 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 01:36:07.377929
10068 01:36:07.378299
10069 01:36:07.379102 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 01:36:07.480521 asurada: tftpboot 192.168.201.1 14173506/tftp-deploy-nsa4wev3/kernel/image.itb 14173506/tftp-deploy-nsa4wev3/kernel/cmdline
10072 01:36:07.481219 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 01:36:07.481696 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 01:36:07.486148 tftpboot 192.168.201.1 14173506/tftp-deploy-nsa4wev3/kernel/image.itbtp-deploy-nsa4wev3/kernel/cmdline
10075 01:36:07.486758
10076 01:36:07.487136 Waiting for link
10077 01:36:07.646854
10078 01:36:07.647408 R8152: Initializing
10079 01:36:07.647781
10080 01:36:07.649943 Version 6 (ocp_data = 5c30)
10081 01:36:07.650458
10082 01:36:07.653403 R8152: Done initializing
10083 01:36:07.653957
10084 01:36:07.654535 Adding net device
10085 01:36:09.614555
10086 01:36:09.615101 done.
10087 01:36:09.615595
10088 01:36:09.616286 MAC: 00:24:32:30:78:52
10089 01:36:09.616929
10090 01:36:09.617792 Sending DHCP discover... done.
10091 01:36:09.618167
10092 01:36:09.621491 Waiting for reply... done.
10093 01:36:09.622044
10094 01:36:09.625143 Sending DHCP request... done.
10095 01:36:09.625604
10096 01:36:09.630837 Waiting for reply... done.
10097 01:36:09.631394
10098 01:36:09.631763 My ip is 192.168.201.14
10099 01:36:09.632104
10100 01:36:09.633389 The DHCP server ip is 192.168.201.1
10101 01:36:09.633792
10102 01:36:09.640720 TFTP server IP predefined by user: 192.168.201.1
10103 01:36:09.641341
10104 01:36:09.646707 Bootfile predefined by user: 14173506/tftp-deploy-nsa4wev3/kernel/image.itb
10105 01:36:09.647193
10106 01:36:09.647597 Sending tftp read request... done.
10107 01:36:09.651031
10108 01:36:09.657174 Waiting for the transfer...
10109 01:36:09.657652
10110 01:36:10.345584 00000000 ################################################################
10111 01:36:10.346116
10112 01:36:11.045936 00080000 ################################################################
10113 01:36:11.046458
10114 01:36:11.733848 00100000 ################################################################
10115 01:36:11.734383
10116 01:36:12.453600 00180000 ################################################################
10117 01:36:12.454195
10118 01:36:13.160874 00200000 ################################################################
10119 01:36:13.161456
10120 01:36:13.884722 00280000 ################################################################
10121 01:36:13.885312
10122 01:36:14.587525 00300000 ################################################################
10123 01:36:14.588097
10124 01:36:15.315265 00380000 ################################################################
10125 01:36:15.315784
10126 01:36:16.011215 00400000 ################################################################
10127 01:36:16.011759
10128 01:36:16.703591 00480000 ################################################################
10129 01:36:16.704112
10130 01:36:17.425097 00500000 ################################################################
10131 01:36:17.425719
10132 01:36:18.131621 00580000 ################################################################
10133 01:36:18.132138
10134 01:36:18.827673 00600000 ################################################################
10135 01:36:18.828206
10136 01:36:19.535149 00680000 ################################################################
10137 01:36:19.535711
10138 01:36:20.260785 00700000 ################################################################
10139 01:36:20.261323
10140 01:36:20.977552 00780000 ################################################################
10141 01:36:20.978168
10142 01:36:21.692382 00800000 ################################################################
10143 01:36:21.692912
10144 01:36:22.406909 00880000 ################################################################
10145 01:36:22.407423
10146 01:36:23.089865 00900000 ################################################################
10147 01:36:23.090371
10148 01:36:23.816805 00980000 ################################################################
10149 01:36:23.817547
10150 01:36:24.520146 00a00000 ################################################################
10151 01:36:24.520659
10152 01:36:25.239830 00a80000 ################################################################
10153 01:36:25.240399
10154 01:36:25.957274 00b00000 ################################################################
10155 01:36:25.957866
10156 01:36:26.673751 00b80000 ################################################################
10157 01:36:26.674260
10158 01:36:27.404859 00c00000 ################################################################
10159 01:36:27.405493
10160 01:36:28.121395 00c80000 ################################################################
10161 01:36:28.121976
10162 01:36:28.851373 00d00000 ################################################################
10163 01:36:28.851975
10164 01:36:29.561909 00d80000 ################################################################
10165 01:36:29.562429
10166 01:36:30.291315 00e00000 ################################################################
10167 01:36:30.291827
10168 01:36:31.025909 00e80000 ################################################################
10169 01:36:31.026514
10170 01:36:31.736109 00f00000 ################################################################
10171 01:36:31.736641
10172 01:36:32.442942 00f80000 ################################################################
10173 01:36:32.443545
10174 01:36:33.158441 01000000 ################################################################
10175 01:36:33.159000
10176 01:36:33.885080 01080000 ################################################################
10177 01:36:33.885598
10178 01:36:34.598689 01100000 ################################################################
10179 01:36:34.599273
10180 01:36:35.317980 01180000 ################################################################
10181 01:36:35.318501
10182 01:36:36.030672 01200000 ################################################################
10183 01:36:36.031188
10184 01:36:36.717321 01280000 ################################################################
10185 01:36:36.717918
10186 01:36:37.406814 01300000 ################################################################
10187 01:36:37.407340
10188 01:36:38.087446 01380000 ################################################################
10189 01:36:38.087971
10190 01:36:38.776084 01400000 ################################################################
10191 01:36:38.776597
10192 01:36:39.464217 01480000 ################################################################
10193 01:36:39.465018
10194 01:36:40.172589 01500000 ################################################################
10195 01:36:40.173144
10196 01:36:40.879749 01580000 ################################################################
10197 01:36:40.880367
10198 01:36:41.612443 01600000 ################################################################
10199 01:36:41.613025
10200 01:36:42.323751 01680000 ################################################################
10201 01:36:42.324255
10202 01:36:43.029131 01700000 ################################################################
10203 01:36:43.029769
10204 01:36:43.721488 01780000 ################################################################
10205 01:36:43.721998
10206 01:36:44.400900 01800000 ################################################################
10207 01:36:44.401466
10208 01:36:45.080883 01880000 ################################################################
10209 01:36:45.081429
10210 01:36:45.752305 01900000 ################################################################
10211 01:36:45.752810
10212 01:36:46.479793 01980000 ################################################################
10213 01:36:46.480315
10214 01:36:47.196133 01a00000 ################################################################
10215 01:36:47.196658
10216 01:36:47.907997 01a80000 ################################################################
10217 01:36:47.908552
10218 01:36:48.630450 01b00000 ################################################################
10219 01:36:48.630987
10220 01:36:49.339343 01b80000 ################################################################
10221 01:36:49.339858
10222 01:36:50.074755 01c00000 ################################################################
10223 01:36:50.075297
10224 01:36:50.791774 01c80000 ################################################################
10225 01:36:50.792352
10226 01:36:51.526844 01d00000 ################################################################
10227 01:36:51.527398
10228 01:36:52.221776 01d80000 ################################################################
10229 01:36:52.222395
10230 01:36:52.904116 01e00000 ################################################################
10231 01:36:52.904660
10232 01:36:53.606269 01e80000 ################################################################
10233 01:36:53.606810
10234 01:36:54.310479 01f00000 ################################################################
10235 01:36:54.310999
10236 01:36:55.022999 01f80000 ################################################################
10237 01:36:55.023579
10238 01:36:55.721915 02000000 ################################################################
10239 01:36:55.722440
10240 01:36:56.396495 02080000 ################################################################
10241 01:36:56.397059
10242 01:36:57.089423 02100000 ################################################################
10243 01:36:57.089941
10244 01:36:57.794743 02180000 ################################################################
10245 01:36:57.795260
10246 01:36:58.513106 02200000 ################################################################
10247 01:36:58.513648
10248 01:36:59.194128 02280000 ################################################################
10249 01:36:59.194649
10250 01:36:59.910047 02300000 ################################################################
10251 01:36:59.910590
10252 01:37:00.624199 02380000 ################################################################
10253 01:37:00.624719
10254 01:37:01.320511 02400000 ################################################################
10255 01:37:01.321088
10256 01:37:02.008802 02480000 ################################################################
10257 01:37:02.009405
10258 01:37:02.718038 02500000 ################################################################
10259 01:37:02.718563
10260 01:37:03.434869 02580000 ################################################################
10261 01:37:03.435457
10262 01:37:04.145475 02600000 ################################################################
10263 01:37:04.145997
10264 01:37:04.849814 02680000 ################################################################
10265 01:37:04.850334
10266 01:37:05.556064 02700000 ################################################################
10267 01:37:05.556571
10268 01:37:06.262503 02780000 ################################################################
10269 01:37:06.263035
10270 01:37:06.951234 02800000 ################################################################
10271 01:37:06.951784
10272 01:37:07.674061 02880000 ################################################################
10273 01:37:07.674580
10274 01:37:08.395923 02900000 ################################################################
10275 01:37:08.396502
10276 01:37:09.112477 02980000 ################################################################
10277 01:37:09.113197
10278 01:37:09.833270 02a00000 ################################################################
10279 01:37:09.833819
10280 01:37:10.552598 02a80000 ################################################################
10281 01:37:10.553156
10282 01:37:11.289219 02b00000 ################################################################
10283 01:37:11.290049
10284 01:37:12.023760 02b80000 ################################################################
10285 01:37:12.024342
10286 01:37:12.734255 02c00000 ################################################################
10287 01:37:12.734767
10288 01:37:13.424637 02c80000 ################################################################
10289 01:37:13.425324
10290 01:37:14.120143 02d00000 ################################################################
10291 01:37:14.120662
10292 01:37:14.842313 02d80000 ################################################################
10293 01:37:14.842842
10294 01:37:15.539616 02e00000 ################################################################
10295 01:37:15.540184
10296 01:37:16.253627 02e80000 ################################################################
10297 01:37:16.254190
10298 01:37:16.957618 02f00000 ################################################################
10299 01:37:16.958148
10300 01:37:17.673087 02f80000 ################################################################
10301 01:37:17.673605
10302 01:37:18.377701 03000000 ################################################################
10303 01:37:18.378281
10304 01:37:19.075015 03080000 ################################################################
10305 01:37:19.075532
10306 01:37:19.768844 03100000 ################################################################
10307 01:37:19.769431
10308 01:37:20.479090 03180000 ################################################################
10309 01:37:20.479609
10310 01:37:21.177509 03200000 ################################################################
10311 01:37:21.178037
10312 01:37:21.867786 03280000 ################################################################
10313 01:37:21.868322
10314 01:37:22.583127 03300000 ################################################################
10315 01:37:22.583653
10316 01:37:23.287326 03380000 ################################################################
10317 01:37:23.287875
10318 01:37:23.993119 03400000 ################################################################
10319 01:37:23.993638
10320 01:37:24.702566 03480000 ################################################################
10321 01:37:24.703111
10322 01:37:25.434179 03500000 ################################################################
10323 01:37:25.434757
10324 01:37:26.118310 03580000 ################################################################
10325 01:37:26.118833
10326 01:37:26.795587 03600000 ################################################################
10327 01:37:26.796110
10328 01:37:27.524735 03680000 ################################################################
10329 01:37:27.525303
10330 01:37:28.221586 03700000 ################################################################
10331 01:37:28.222124
10332 01:37:28.918495 03780000 ################################################################
10333 01:37:28.919026
10334 01:37:29.606867 03800000 ################################################################
10335 01:37:29.607421
10336 01:37:30.311341 03880000 ################################################################
10337 01:37:30.311915
10338 01:37:31.002030 03900000 ################################################################
10339 01:37:31.002606
10340 01:37:31.681437 03980000 ################################################################
10341 01:37:31.681957
10342 01:37:32.395725 03a00000 ################################################################
10343 01:37:32.396377
10344 01:37:33.095543 03a80000 ################################################################
10345 01:37:33.096064
10346 01:37:33.784243 03b00000 ################################################################
10347 01:37:33.784792
10348 01:37:34.494403 03b80000 ################################################################
10349 01:37:34.494923
10350 01:37:35.173610 03c00000 ################################################################
10351 01:37:35.174123
10352 01:37:35.871006 03c80000 ################################################################
10353 01:37:35.871531
10354 01:37:36.585074 03d00000 ################################################################
10355 01:37:36.585653
10356 01:37:37.296964 03d80000 ################################################################
10357 01:37:37.297603
10358 01:37:38.008117 03e00000 ################################################################
10359 01:37:38.008650
10360 01:37:38.700420 03e80000 ################################################################
10361 01:37:38.701009
10362 01:37:39.412352 03f00000 ################################################################
10363 01:37:39.412859
10364 01:37:40.112692 03f80000 ################################################################
10365 01:37:40.113232
10366 01:37:40.815374 04000000 ################################################################
10367 01:37:40.815907
10368 01:37:41.532905 04080000 ################################################################
10369 01:37:41.533463
10370 01:37:42.235995 04100000 ################################################################
10371 01:37:42.236563
10372 01:37:42.927599 04180000 ################################################################
10373 01:37:42.928145
10374 01:37:43.633880 04200000 ################################################################
10375 01:37:43.634410
10376 01:37:44.359536 04280000 ################################################################
10377 01:37:44.360083
10378 01:37:45.044715 04300000 ################################################################
10379 01:37:45.045368
10380 01:37:45.759274 04380000 ################################################################
10381 01:37:45.759793
10382 01:37:46.458683 04400000 ################################################################
10383 01:37:46.459226
10384 01:37:47.171005 04480000 ################################################################
10385 01:37:47.171594
10386 01:37:47.888715 04500000 ################################################################
10387 01:37:47.889348
10388 01:37:48.583119 04580000 ################################################################
10389 01:37:48.583697
10390 01:37:49.291084 04600000 ################################################################
10391 01:37:49.291668
10392 01:37:49.528926 04680000 ###################### done.
10393 01:37:49.529485
10394 01:37:49.533260 The bootfile was 74102550 bytes long.
10395 01:37:49.533688
10396 01:37:49.535268 Sending tftp read request... done.
10397 01:37:49.535691
10398 01:37:49.540965 Waiting for the transfer...
10399 01:37:49.541423
10400 01:37:49.541760 00000000 # done.
10401 01:37:49.542084
10402 01:37:49.545862 Command line loaded dynamically from TFTP file: 14173506/tftp-deploy-nsa4wev3/kernel/cmdline
10403 01:37:49.546285
10404 01:37:49.558701 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10405 01:37:49.559238
10406 01:37:49.562701 Loading FIT.
10407 01:37:49.563222
10408 01:37:49.565475 Image ramdisk-1 has 60993338 bytes.
10409 01:37:49.565894
10410 01:37:49.569165 Image fdt-1 has 47258 bytes.
10411 01:37:49.569606
10412 01:37:49.569950 Image kernel-1 has 13059919 bytes.
10413 01:37:49.572891
10414 01:37:49.579999 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10415 01:37:49.580523
10416 01:37:49.596066 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10417 01:37:49.596627
10418 01:37:49.603033 Choosing best match conf-1 for compat google,spherion-rev2.
10419 01:37:49.607458
10420 01:37:49.611716 Connected to device vid:did:rid of 1ae0:0028:00
10421 01:37:49.619760
10422 01:37:49.623251 tpm_get_response: command 0x17b, return code 0x0
10423 01:37:49.623717
10424 01:37:49.626758 ec_init: CrosEC protocol v3 supported (256, 248)
10425 01:37:49.630097
10426 01:37:49.633688 tpm_cleanup: add release locality here.
10427 01:37:49.634179
10428 01:37:49.636145 Shutting down all USB controllers.
10429 01:37:49.636608
10430 01:37:49.640124 Removing current net device
10431 01:37:49.640586
10432 01:37:49.643054 Exiting depthcharge with code 4 at timestamp: 135752857
10433 01:37:49.643518
10434 01:37:49.646872 LZMA decompressing kernel-1 to 0x821a6718
10435 01:37:49.647443
10436 01:37:49.649746 LZMA decompressing kernel-1 to 0x40000000
10437 01:37:51.261902
10438 01:37:51.262463 jumping to kernel
10439 01:37:51.264601 end: 2.2.4 bootloader-commands (duration 00:01:48) [common]
10440 01:37:51.265167 start: 2.2.5 auto-login-action (timeout 00:02:37) [common]
10441 01:37:51.265590 Setting prompt string to ['Linux version [0-9]']
10442 01:37:51.265970 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10443 01:37:51.266349 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10444 01:37:51.343698
10445 01:37:51.347317 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10446 01:37:51.350620 start: 2.2.5.1 login-action (timeout 00:02:37) [common]
10447 01:37:51.351235 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10448 01:37:51.351687 Setting prompt string to []
10449 01:37:51.352138 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10450 01:37:51.352544 Using line separator: #'\n'#
10451 01:37:51.352886 No login prompt set.
10452 01:37:51.353257 Parsing kernel messages
10453 01:37:51.353583 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10454 01:37:51.354149 [login-action] Waiting for messages, (timeout 00:02:37)
10455 01:37:51.354525 Waiting using forced prompt support (timeout 00:01:19)
10456 01:37:51.369503 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10457 01:37:51.372792 [ 0.000000] random: crng init done
10458 01:37:51.380259 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10459 01:37:51.383548 [ 0.000000] efi: UEFI not found.
10460 01:37:51.389371 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10461 01:37:51.396402 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10462 01:37:51.406309 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10463 01:37:51.416591 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10464 01:37:51.423040 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10465 01:37:51.429527 [ 0.000000] printk: bootconsole [mtk8250] enabled
10466 01:37:51.436943 [ 0.000000] NUMA: No NUMA configuration found
10467 01:37:51.443117 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10468 01:37:51.446460 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10469 01:37:51.449848 [ 0.000000] Zone ranges:
10470 01:37:51.457634 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10471 01:37:51.459726 [ 0.000000] DMA32 empty
10472 01:37:51.466821 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10473 01:37:51.470274 [ 0.000000] Movable zone start for each node
10474 01:37:51.475047 [ 0.000000] Early memory node ranges
10475 01:37:51.480518 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10476 01:37:51.486576 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10477 01:37:51.493361 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10478 01:37:51.497790 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10479 01:37:51.503253 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10480 01:37:51.510508 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10481 01:37:51.569043 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10482 01:37:51.575185 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10483 01:37:51.581333 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10484 01:37:51.585457 [ 0.000000] psci: probing for conduit method from DT.
10485 01:37:51.592441 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10486 01:37:51.595386 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10487 01:37:51.602040 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10488 01:37:51.606012 [ 0.000000] psci: SMC Calling Convention v1.2
10489 01:37:51.612029 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10490 01:37:51.615094 [ 0.000000] Detected VIPT I-cache on CPU0
10491 01:37:51.621806 [ 0.000000] CPU features: detected: GIC system register CPU interface
10492 01:37:51.628239 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10493 01:37:51.635236 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10494 01:37:51.641482 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10495 01:37:51.648223 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10496 01:37:51.654758 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10497 01:37:51.661723 [ 0.000000] alternatives: applying boot alternatives
10498 01:37:51.665559 [ 0.000000] Fallback order for Node 0: 0
10499 01:37:51.671638 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10500 01:37:51.674989 [ 0.000000] Policy zone: Normal
10501 01:37:51.691436 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10502 01:37:51.702097 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10503 01:37:51.711769 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10504 01:37:51.722767 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10505 01:37:51.728621 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10506 01:37:51.732313 <6>[ 0.000000] software IO TLB: area num 8.
10507 01:37:51.788486 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10508 01:37:51.937137 <6>[ 0.000000] Memory: 7904624K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448144K reserved, 32768K cma-reserved)
10509 01:37:51.944810 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10510 01:37:51.950953 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10511 01:37:51.954307 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10512 01:37:51.960794 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10513 01:37:51.967246 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10514 01:37:51.971661 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10515 01:37:51.981665 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10516 01:37:51.987389 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10517 01:37:51.990538 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10518 01:37:51.998272 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10519 01:37:52.001353 <6>[ 0.000000] GICv3: 608 SPIs implemented
10520 01:37:52.008535 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10521 01:37:52.011806 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10522 01:37:52.015285 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10523 01:37:52.025595 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10524 01:37:52.034690 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10525 01:37:52.048559 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10526 01:37:52.054914 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10527 01:37:52.063533 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10528 01:37:52.077064 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10529 01:37:52.083486 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10530 01:37:52.089891 <6>[ 0.009181] Console: colour dummy device 80x25
10531 01:37:52.100007 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10532 01:37:52.107020 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10533 01:37:52.110775 <6>[ 0.029287] LSM: Security Framework initializing
10534 01:37:52.116872 <6>[ 0.034224] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10535 01:37:52.126287 <6>[ 0.042039] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10536 01:37:52.133377 <6>[ 0.051446] cblist_init_generic: Setting adjustable number of callback queues.
10537 01:37:52.140736 <6>[ 0.058890] cblist_init_generic: Setting shift to 3 and lim to 1.
10538 01:37:52.149947 <6>[ 0.065267] cblist_init_generic: Setting adjustable number of callback queues.
10539 01:37:52.153521 <6>[ 0.072694] cblist_init_generic: Setting shift to 3 and lim to 1.
10540 01:37:52.160062 <6>[ 0.079120] rcu: Hierarchical SRCU implementation.
10541 01:37:52.167388 <6>[ 0.079122] rcu: Max phase no-delay instances is 1000.
10542 01:37:52.170261 <6>[ 0.079145] printk: bootconsole [mtk8250] printing thread started
10543 01:37:52.178859 <6>[ 0.097456] EFI services will not be available.
10544 01:37:52.181797 <6>[ 0.097658] smp: Bringing up secondary CPUs ...
10545 01:37:52.189672 <6>[ 0.097967] Detected VIPT I-cache on CPU1
10546 01:37:52.195239 <6>[ 0.098036] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10547 01:37:52.201819 <6>[ 0.098068] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10548 01:37:52.212872 <6>[ 0.125895] Detected VIPT I-cache on CPU2
10549 01:37:52.219291 <6>[ 0.125948] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10550 01:37:52.228083 <6>[ 0.125967] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10551 01:37:52.231656 <6>[ 0.126225] Detected VIPT I-cache on CPU3
10552 01:37:52.239040 <6>[ 0.126274] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10553 01:37:52.246151 <6>[ 0.126288] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10554 01:37:52.248185 <6>[ 0.126597] CPU features: detected: Spectre-v4
10555 01:37:52.256223 <6>[ 0.126602] CPU features: detected: Spectre-BHB
10556 01:37:52.258153 <6>[ 0.126608] Detected PIPT I-cache on CPU4
10557 01:37:52.264826 <6>[ 0.126667] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10558 01:37:52.271826 <6>[ 0.126683] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10559 01:37:52.278487 <6>[ 0.126968] Detected PIPT I-cache on CPU5
10560 01:37:52.285149 <6>[ 0.127030] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10561 01:37:52.292128 <6>[ 0.127046] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10562 01:37:52.295260 <6>[ 0.127318] Detected PIPT I-cache on CPU6
10563 01:37:52.301312 <6>[ 0.127382] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10564 01:37:52.312238 <6>[ 0.127398] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10565 01:37:52.315836 <6>[ 0.127685] Detected PIPT I-cache on CPU7
10566 01:37:52.321667 <6>[ 0.127749] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10567 01:37:52.329133 <6>[ 0.127764] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10568 01:37:52.332744 <6>[ 0.127811] smp: Brought up 1 node, 8 CPUs
10569 01:37:52.338803 <6>[ 0.127816] SMP: Total of 8 processors activated.
10570 01:37:52.341836 <6>[ 0.127818] CPU features: detected: 32-bit EL0 Support
10571 01:37:52.352123 <6>[ 0.127821] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10572 01:37:52.358867 <6>[ 0.127823] CPU features: detected: Common not Private translations
10573 01:37:52.365967 <6>[ 0.127825] CPU features: detected: CRC32 instructions
10574 01:37:52.370475 <6>[ 0.127828] CPU features: detected: RCpc load-acquire (LDAPR)
10575 01:37:52.375377 <6>[ 0.127829] CPU features: detected: LSE atomic instructions
10576 01:37:52.382331 <6>[ 0.127831] CPU features: detected: Privileged Access Never
10577 01:37:52.389848 <6>[ 0.127832] CPU features: detected: RAS Extension Support
10578 01:37:52.395518 <6>[ 0.127835] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10579 01:37:52.399176 <6>[ 0.127903] CPU: All CPU(s) started at EL2
10580 01:37:52.405739 <6>[ 0.127905] alternatives: applying system-wide alternatives
10581 01:37:52.408972 <6>[ 0.141127] devtmpfs: initialized
10582 01:37:52.418640 <6>[ 0.147410] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10583 01:37:52.425237 <6>[ 0.147424] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10584 01:37:52.431431 <6>[ 0.148286] pinctrl core: initialized pinctrl subsystem
10585 01:37:52.455794 <6>[ 0.374930] prin<tk: console [ttyS0] printing thread started
10586 01:37:52.459525 6>[ 0.149458] DMI not present or invalid.
10587 01:37:52.470797 <6>[ 0.374933] printk: console [ttyS0] enabled
10588 01:37:52.473338 <6>[ 0.374938] printk: bootconsole [mtk8250] disabled
10589 01:37:52.480182 <6>[ 0.384866] printk: bootconsole [mtk8250] printing thread stopped
10590 01:37:52.486241 <6>[ 0.386239] SuperH (H)SCI(F) driver initialized
10591 01:37:52.489590 <6>[ 0.386729] msm_serial: driver initialized
10592 01:37:52.499792 <6>[ 0.391349] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10593 01:37:52.505763 <6>[ 0.391377] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10594 01:37:52.519345 <6>[ 0.391406] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10595 01:37:52.529623 <6>[ 0.391435] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10596 01:37:52.537786 <6>[ 0.391456] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10597 01:37:52.543912 <6>[ 0.391484] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10598 01:37:52.556293 <6>[ 0.391512] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10599 01:37:52.560192 <6>[ 0.391645] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10600 01:37:52.569223 <6>[ 0.391675] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10601 01:37:52.569797 <6>[ 0.402056] loop: module loaded
10602 01:37:52.578697 <6>[ 0.404569] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10603 01:37:52.582191 <4>[ 0.422024] mtk-pmic-keys: Failed to locate of_node [id: -1]
10604 01:37:52.586224 <6>[ 0.423240] megasas: 07.719.03.00-rc1
10605 01:37:52.591838 <6>[ 0.432032] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10606 01:37:52.598547 <6>[ 0.436148] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10607 01:37:52.605418 <6>[ 0.448406] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10608 01:37:52.615500 <6>[ 0.502372] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10609 01:37:55.049079 <6>[ 2.966685] Freeing initrd memory: 59560K
10610 01:37:55.057053 <6>[ 2.974293] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10611 01:37:55.064102 <6>[ 2.979083] tun: Universal TUN/TAP device driver, 1.6
10612 01:37:55.067061 <6>[ 2.979860] thunder_xcv, ver 1.0
10613 01:37:55.070607 <6>[ 2.979879] thunder_bgx, ver 1.0
10614 01:37:55.074195 <6>[ 2.979894] nicpf, ver 1.0
10615 01:37:55.081271 <6>[ 2.980980] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10616 01:37:55.087339 <6>[ 2.980983] hns3: Copyright (c) 2017 Huawei Corporation.
10617 01:37:55.090275 <6>[ 2.981016] hclge is initializing
10618 01:37:55.097505 <6>[ 2.981028] e1000: Intel(R) PRO/1000 Network Driver
10619 01:37:55.101556 <6>[ 2.981030] e1000: Copyright (c) 1999-2006 Intel Corporation.
10620 01:37:55.107660 <6>[ 2.981050] e1000e: Intel(R) PRO/1000 Network Driver
10621 01:37:55.111562 <6>[ 2.981051] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10622 01:37:55.118752 <6>[ 2.981068] igb: Intel(R) Gigabit Ethernet Network Driver
10623 01:37:55.125758 <6>[ 2.981070] igb: Copyright (c) 2007-2014 Intel Corporation.
10624 01:37:55.132180 <6>[ 2.981084] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10625 01:37:55.135727 <6>[ 2.981087] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10626 01:37:55.142421 <6>[ 2.981393] sky2: driver version 1.30
10627 01:37:55.145975 <6>[ 2.982400] usbcore: registered new device driver r8152-cfgselector
10628 01:37:55.152057 <6>[ 2.982419] usbcore: registered new interface driver r8152
10629 01:37:55.159070 <6>[ 2.982496] VFIO - User Level meta-driver version: 0.3
10630 01:37:55.165743 <6>[ 2.985360] usbcore: registered new interface driver usb-storage
10631 01:37:55.172220 <6>[ 2.985546] usbcore: registered new device driver onboard-usb-hub
10632 01:37:55.175931 <6>[ 2.988325] mt6397-rtc mt6359-rtc: registered as rtc0
10633 01:37:55.185302 <6>[ 2.988474] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T01:37:55 UTC (1717551475)
10634 01:37:55.188866 <6>[ 2.989099] i2c_dev: i2c /dev entries driver
10635 01:37:55.198894 <6>[ 2.996254] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10636 01:37:55.205844 <4>[ 2.996990] cpu cpu0: supply cpu not found, using dummy regulator
10637 01:37:55.209139 <4>[ 2.997078] cpu cpu1: supply cpu not found, using dummy regulator
10638 01:37:55.215741 <4>[ 2.997134] cpu cpu2: supply cpu not found, using dummy regulator
10639 01:37:55.222606 <4>[ 2.997187] cpu cpu3: supply cpu not found, using dummy regulator
10640 01:37:55.229288 <4>[ 2.997236] cpu cpu4: supply cpu not found, using dummy regulator
10641 01:37:55.235655 <4>[ 2.997292] cpu cpu5: supply cpu not found, using dummy regulator
10642 01:37:55.241973 <4>[ 2.997360] cpu cpu6: supply cpu not found, using dummy regulator
10643 01:37:55.249361 <4>[ 2.997414] cpu cpu7: supply cpu not found, using dummy regulator
10644 01:37:55.252415 <6>[ 3.011682] cpu cpu0: EM: created perf domain
10645 01:37:55.258742 <6>[ 3.011916] cpu cpu4: EM: created perf domain
10646 01:37:55.265239 <6>[ 3.015023] sdhci: Secure Digital Host Controller Interface driver
10647 01:37:55.268341 <6>[ 3.015025] sdhci: Copyright(c) Pierre Ossman
10648 01:37:55.275573 <6>[ 3.015393] Synopsys Designware Multimedia Card Interface Driver
10649 01:37:55.281828 <6>[ 3.015777] sdhci-pltfm: SDHCI platform and OF driver helper
10650 01:37:55.288737 <6>[ 3.019956] ledtrig-cpu: registered to indicate activity on CPUs
10651 01:37:55.292080 <6>[ 3.020636] mmc0: CQHCI version 5.10
10652 01:37:55.298770 <6>[ 3.020775] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10653 01:37:55.302049 <6>[ 3.021064] usbcore: registered new interface driver usbhid
10654 01:37:55.308456 <6>[ 3.021066] usbhid: USB HID core driver
10655 01:37:55.315326 <6>[ 3.021186] spi_master spi0: will run message pump with realtime priority
10656 01:37:55.329032 <6>[ 3.053273] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10657 01:37:55.341884 <6>[ 3.056138] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10658 01:37:55.345245 <6>[ 3.057055] cros-ec-spi spi0.0: Chrome EC device registered
10659 01:37:55.357663 <6>[ 3.070955] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10660 01:37:55.361954 <6>[ 3.073268] NET: Registered PF_PACKET protocol family
10661 01:37:55.365341 <6>[ 3.073367] 9pnet: Installing 9P2000 support
10662 01:37:55.368827 <5>[ 3.073403] Key type dns_resolver registered
10663 01:37:55.375174 <6>[ 3.073695] registered taskstats version 1
10664 01:37:55.378559 <5>[ 3.073711] Loading compiled-in X.509 certificates
10665 01:37:55.388623 <4>[ 3.088357] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 01:37:55.402171 <4>[ 3.088514] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10667 01:37:55.404912 <6>[ 3.098113] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10668 01:37:55.411590 <6>[ 3.098789] xhci-mtk 11200000.usb: xHCI Host Controller
10669 01:37:55.418306 <6>[ 3.098818] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10670 01:37:55.428611 <6>[ 3.099091] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10671 01:37:55.435820 <6>[ 3.099181] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10672 01:37:55.441443 <6>[ 3.099281] xhci-mtk 11200000.usb: xHCI Host Controller
10673 01:37:55.448399 <6>[ 3.099298] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10674 01:37:55.455205 <6>[ 3.099309] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10675 01:37:55.458201 <6>[ 3.099855] hub 1-0:1.0: USB hub found
10676 01:37:55.464623 <6>[ 3.099875] hub 1-0:1.0: 1 port detected
10677 01:37:55.471242 <6>[ 3.100079] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10678 01:37:55.475162 <6>[ 3.100326] hub 2-0:1.0: USB hub found
10679 01:37:55.481566 <6>[ 3.100340] hub 2-0:1.0: 1 port detected
10680 01:37:55.484903 <6>[ 3.103565] mtk-msdc 11f70000.mmc: Got CD GPIO
10681 01:37:55.491561 <3>[ 3.112269] mtk-msdc 11f60000.mmc: phase error: [map:0]
10682 01:37:55.498562 <3>[ 3.112276] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10683 01:37:55.501367 <3>[ 3.112278] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10684 01:37:55.507938 <3>[ 3.112286] mmc0: error -5 whilst initialising MMC card
10685 01:37:55.514467 <6>[ 3.118871] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10686 01:37:55.524552 <6>[ 3.118879] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10687 01:37:55.534563 <4>[ 3.119027] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10688 01:37:55.540937 <6>[ 3.119662] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10689 01:37:55.547512 <6>[ 3.119666] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10690 01:37:55.557683 <6>[ 3.119782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10691 01:37:55.567152 <6>[ 3.119793] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10692 01:37:55.574181 <6>[ 3.119797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10693 01:37:55.581064 <6>[ 3.119802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10694 01:37:55.590480 <6>[ 3.121323] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10695 01:37:55.597234 <6>[ 3.121342] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10696 01:37:55.607235 <6>[ 3.121348] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10697 01:37:55.613546 <6>[ 3.121354] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10698 01:37:55.623599 <6>[ 3.121359] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10699 01:37:55.630121 <6>[ 3.121365] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10700 01:37:55.639785 <6>[ 3.121370] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10701 01:37:55.649704 <6>[ 3.121376] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10702 01:37:55.656448 <6>[ 3.121382] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10703 01:37:55.666899 <6>[ 3.121388] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10704 01:37:55.673054 <6>[ 3.121394] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10705 01:37:55.683561 <6>[ 3.121400] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10706 01:37:55.689876 <6>[ 3.121406] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10707 01:37:55.700656 <6>[ 3.121415] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10708 01:37:55.706941 <6>[ 3.121420] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10709 01:37:55.712954 <6>[ 3.121991] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10710 01:37:55.720279 <6>[ 3.122896] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10711 01:37:55.726491 <6>[ 3.123466] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10712 01:37:55.733081 <6>[ 3.124100] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10713 01:37:55.739230 <6>[ 3.124824] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10714 01:37:55.749307 <6>[ 3.125051] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10715 01:37:55.759420 <6>[ 3.125069] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10716 01:37:55.765758 <6>[ 3.125075] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10717 01:37:55.775780 <6>[ 3.125081] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10718 01:37:55.787516 <6>[ 3.125087] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10719 01:37:55.795828 <6>[ 3.125094] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10720 01:37:55.805395 <6>[ 3.125100] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10721 01:37:55.812002 <6>[ 3.125106] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10722 01:37:55.822487 <6>[ 3.125112] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10723 01:37:55.832501 <6>[ 3.125119] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10724 01:37:55.842935 <6>[ 3.125124] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10725 01:37:55.852695 <6>[ 3.126082] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10726 01:37:55.859151 <3>[ 3.206893] mtk-msdc 11f60000.mmc: phase error: [map:0]
10727 01:37:55.861843 <3>[ 3.206899] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10728 01:37:55.869707 <3>[ 3.206901] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10729 01:37:55.875141 <3>[ 3.206909] mmc0: error -5 whilst initialising MMC card
10730 01:37:55.882563 <6>[ 3.516889] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10731 01:37:55.888878 <6>[ 3.637714] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10732 01:37:55.892261 <6>[ 3.644352] mmc0: Command Queue Engine enabled
10733 01:37:55.898463 <6>[ 3.644368] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10734 01:37:55.906162 <6>[ 3.645221] mmcblk0: mmc0:0001 DA4128 116 GiB
10735 01:37:55.908182 <6>[ 3.648523] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10736 01:37:55.914569 <6>[ 3.649524] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10737 01:37:55.921544 <6>[ 3.650181] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10738 01:37:55.927708 <6>[ 3.650766] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10739 01:37:55.931582 <6>[ 3.669506] hub 1-1:1.0: USB hub found
10740 01:37:55.934694 <6>[ 3.669888] hub 1-1:1.0: 4 ports detected
10741 01:37:55.938191 <6>[ 3.673700] hub 1-1:1.0: USB hub found
10742 01:37:55.946828 <6>[ 3.674023] hub 1-1:1.0: 4 ports detected
10743 01:37:55.951209 <6>[ 3.793061] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10744 01:37:55.955517 <6>[ 3.821613] hub 2-1:1.0: USB hub found
10745 01:37:55.957438 <6>[ 3.822005] hub 2-1:1.0: 3 ports detected
10746 01:37:55.961188 <6>[ 3.825202] hub 2-1:1.0: USB hub found
10747 01:37:55.968097 <6>[ 3.825589] hub 2-1:1.0: 3 ports detected
10748 01:37:56.080673 <6>[ 3.993008] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10749 01:37:56.205401 <6>[ 4.120869] hub 1-1.4:1.0: USB hub found
10750 01:37:56.208876 <6>[ 4.121330] hub 1-1.4:1.0: 2 ports detected
10751 01:37:56.212683 <6>[ 4.125385] hub 1-1.4:1.0: USB hub found
10752 01:37:56.218420 <6>[ 4.125749] hub 1-1.4:1.0: 2 ports detected
10753 01:37:56.284541 <6>[ 4.197153] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10754 01:37:56.388779 <6>[ 4.301560] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10755 01:37:56.412762 <4>[ 4.328442] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10756 01:37:56.422886 <4>[ 4.328461] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10757 01:37:56.445028 <6>[ 4.362353] r8152 2-1.3:1.0 eth0: v1.12.13
10758 01:37:56.500769 <6>[ 4.413025] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10759 01:37:56.685172 <6>[ 4.597022] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10760 01:37:58.065904 <6>[ 5.981429] r8152 2-1.3:1.0 eth0: carrier on
10761 01:38:00.137606 <5>[ 6.012853] Sending DHCP requests .., OK
10762 01:38:00.144452 <6>[ 8.052927] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10763 01:38:00.146786 <6>[ 8.052945] IP-Config: Complete:
10764 01:38:00.160271 <6>[ 8.052947] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10765 01:38:00.166866 <6>[ 8.052958] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10766 01:38:00.174246 <6>[ 8.052962] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10767 01:38:00.180574 <6>[ 8.052968] nameserver0=192.168.201.1
10768 01:38:00.183135 <6>[ 8.053226] clk: Disabling unused clocks
10769 01:38:00.186776 <6>[ 8.054274] ALSA device list:
10770 01:38:00.189837 <6>[ 8.054287] No soundcards found.
10771 01:38:00.193828 <6>[ 8.058653] Freeing unused kernel memory: 8512K
10772 01:38:00.200608 <6>[ 8.058843] Run /init as init process
10773 01:38:00.213464 <6>[ 8.129445] NET: Registered PF_INET6 protocol family
10774 01:38:00.216755 <6>[ 8.130979] Segment Routing with IPv6
10775 01:38:00.222398 <6>[ 8.131010] In-situ OAM (IOAM) with IPv6
10776 01:38:00.222946
10777 01:38:00.259245 Welcome to [1mDebian GNU/Linu<30>[ 8.146728] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10778 01:38:00.262703 <30>[ 8.146750] systemd[1]: Detected architecture arm64.
10779 01:38:00.265711 x 12 (bookworm)[0m!
10780 01:38:00.266268
10781 01:38:00.285361 <30>[ 8.200951] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10782 01:38:00.436486 <30>[ 8.352004] systemd[1]: Queued start job for default target graphical.target.
10783 01:38:00.477596 [[0;32m OK [0m] Created slic<30>[ 8.390671] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10784 01:38:00.480810 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10785 01:38:00.504676 [[0;32m OK [0m] Created slic<30>[ 8.417923] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10786 01:38:00.507850 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10787 01:38:00.534220 [[0;32m OK [0m] Created slic<30>[ 8.447255] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10788 01:38:00.541200 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10789 01:38:00.561918 [[0;32m OK [0m] Created slic<30>[ 8.475013] systemd[1]: Created slice user.slice - User and Session Slice.
10790 01:38:00.565833 e [0;1;39muser.slice[0m - User and Session Slice.
10791 01:38:00.591834 [[0;32m OK [0m] Started [0;<30>[ 8.501860] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10792 01:38:00.595403 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10793 01:38:00.619173 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 8.529183] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10794 01:38:00.624004 -passwo… Requests to Wall Directory Watch.
10795 01:38:00.657483 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 8.557545] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10796 01:38:00.664263 <30>[ 8.557728] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10797 01:38:00.667344 ice[0m - /dev/ttyS0...
10798 01:38:00.688728 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 8.601424] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10799 01:38:00.691690 tsetup.…get[0m - Local Encrypted Volumes.
10800 01:38:00.719189 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 8.629124] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10801 01:38:00.722327 grityse…Local Integrity Protected Volumes.
10802 01:38:00.745148 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 8.657544] systemd[1]: Reached target paths.target - Path Units.
10803 01:38:00.745715 s.target[0m - Path Units.
10804 01:38:00.768051 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 8.681448] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10805 01:38:00.771679 te-fs.target[0m - Remote File Systems.
10806 01:38:00.791578 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 8.705034] systemd[1]: Reached target slices.target - Slice Units.
10807 01:38:00.794873 es.target[0m - Slice Units.
10808 01:38:00.816211 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 8.729483] systemd[1]: Reached target swap.target - Swaps.
10809 01:38:00.816776 .target[0m - Swaps.
10810 01:38:00.842247 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 8.753561] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10811 01:38:00.847502 tysetup… - Local Verity Protected Volumes.
10812 01:38:00.868570 [[0;32m OK [0m] Listening on<30>[ 8.781972] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10813 01:38:00.875797 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10814 01:38:00.898484 [[0;32m OK [<30>[ 8.811260] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10815 01:38:00.905085 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10816 01:38:00.928629 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.837801] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10817 01:38:00.930662 d-journ…t[0m - Journal Socket (/dev/log).
10818 01:38:00.956409 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.869732] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10819 01:38:00.960266 d-journald.socket[0m - Journal Socket.
10820 01:38:00.980333 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 8.893672] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10821 01:38:00.987375 d-udevd….socket[0m - udev Control Socket.
10822 01:38:01.009161 [[0;32m OK [0m] Listening on<30>[ 8.922182] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10823 01:38:01.012254 [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10824 01:38:01.060700 Mounting [0;1;39mdev-hugepages.mount[<30>[ 8.973201] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10825 01:38:01.063129 0m - Huge Pages File System...
10826 01:38:01.086155 Mounting [0;1;39mdev-m<30>[ 8.999137] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10827 01:38:01.089730 queue.mount…POSIX Message Queue File System...
10828 01:38:01.111616 Mountin<30>[ 9.028040] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10829 01:38:01.118236 g [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10830 01:38:01.146848 <30>[ 9.053457] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10831 01:38:01.156957 <30>[ 9.058742] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10832 01:38:01.164212 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10833 01:38:01.189116 Starting [0;1;39mmodpr<30>[ 9.102126] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10834 01:38:01.192113 obe@configfs…m - Load Kernel Module configfs...
10835 01:38:01.221791 Starting [0;1;39mmodpr<30>[ 9.134236] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10836 01:38:01.234361 obe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 9.146736] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10837 01:38:01.234927 .
10838 01:38:01.261525 Starting [0;1;39mmodpr<30>[ 9.174354] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10839 01:38:01.265592 obe@drm.service[0m - Load Kernel Module drm...
10840 01:38:01.293454 Starting [0;1;39mmodpr<30>[ 9.206301] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10841 01:38:01.296490 obe@efi_psto…- Load Kernel Module efi_pstore...
10842 01:38:01.325215 Starting [0;1;39mmodpr<30>[ 9.237920] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10843 01:38:01.329083 obe@loop.ser…e[0m - Load Kernel Module loop...
10844 01:38:01.361158 Starting [0;1;39msystemd-journald.serv<30>[ 9.273798] systemd[1]: Starting systemd-journald.service - Journal Service...
10845 01:38:01.363891 ice[0m - Journal Service...
10846 01:38:01.383178 Startin<30>[ 9.299663] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10847 01:38:01.389551 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10848 01:38:01.416420 Startin<30>[ 9.328151] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10849 01:38:01.422338 g [0;1;39msystemd-network-g… units from Kernel command line...
10850 01:38:01.449655 Starting [0;1;39msyste<30>[ 9.361887] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10851 01:38:01.455935 md-remount-f…nt Root and Kernel File Systems...
10852 01:38:01.478749 Startin<30>[ 9.392058] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10853 01:38:01.481994 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10854 01:38:01.510392 [[0;32m OK [0m] Started [0;<30>[ 9.422839] systemd[1]: Started systemd-journald.service - Journal Service.
10855 01:38:01.512630 1;39msystemd-journald.service[0m - Journal Service.
10856 01:38:01.536462 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10857 01:38:01.552922 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10858 01:38:01.573146 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10859 01:38:01.593563 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10860 01:38:01.614313 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10861 01:38:01.639116 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10862 01:38:01.658581 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10863 01:38:01.678534 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10864 01:38:01.698756 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10865 01:38:01.722198 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10866 01:38:01.741746 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10867 01:38:01.762768 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10868 01:38:01.768726 See 'systemctl status systemd-remount-fs.service' for details.
10869 01:38:01.779223 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10870 01:38:01.799214 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10871 01:38:01.837604 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10872 01:38:01.859218 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10873 01:38:01.871864 <46>[ 9.786839] systemd-journald[195]: Received client request to flush runtime journal.
10874 01:38:01.887481 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10875 01:38:01.914114 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10876 01:38:01.936476 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10877 01:38:01.966933 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10878 01:38:01.989153 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10879 01:38:02.009854 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10880 01:38:02.029666 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10881 01:38:02.049723 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10882 01:38:02.092533 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10883 01:38:02.115217 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10884 01:38:02.133470 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10885 01:38:02.152160 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10886 01:38:02.200252 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10887 01:38:02.220101 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10888 01:38:02.245873 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10889 01:38:02.293563 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10890 01:38:02.323038 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10891 01:38:02.344871 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10892 01:38:02.390268 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10893 01:38:02.424375 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10894 01:38:02.432742 <46>[ 10.351682] systemd-journald[195]: Time jumped backwards, rotating.
10895 01:38:02.469165 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10896 01:38:02.586318 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10897 01:38:02.605935 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10898 01:38:02.625977 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10899 01:38:02.645596 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10900 01:38:02.665593 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10901 01:38:02.672221 <3>[ 10.586111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 01:38:02.682284 <3>[ 10.586156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 01:38:02.688808 <3>[ 10.586166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 01:38:02.694608 <3>[ 10.611501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 01:38:02.705075 <3>[ 10.611526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 01:38:02.711862 <3>[ 10.611531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 01:38:02.721514 [[0;32m OK [<3>[ 10.611538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 01:38:02.731957 0m] Listening on<3>[ 10.611543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10909 01:38:02.741376 [0;1;39mdbus.s<6>[ 10.628091] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10910 01:38:02.752659 ocket[…- D-Bu<3>[ 10.634829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 01:38:02.754496 <6>[ 10.644445] remoteproc remoteproc0: scp is available
10912 01:38:02.761313 s System Message<6>[ 10.644592] remoteproc remoteproc0: powering up scp
10913 01:38:02.771601 <6>[ 10.644602] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10914 01:38:02.774921 <6>[ 10.644641] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10915 01:38:02.784846 <3>[ 10.645108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 01:38:02.785504 Bus Socket.
10917 01:38:02.794770 <3>[ 10.645119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 01:38:02.801036 <3>[ 10.645122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 01:38:02.808612 <3>[ 10.655918] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 01:38:02.818407 <3>[ 10.655973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 01:38:02.825018 <3>[ 10.655986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 01:38:02.834431 <3>[ 10.656004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 01:38:02.840955 <3>[ 10.656014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 01:38:02.851782 [[0;32m OK [<3>[ 10.657542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 01:38:02.857901 <6>[ 10.660045] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10926 01:38:02.868009 <6>[ 10.660076] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10927 01:38:02.878115 0m] Reached targ<6>[ 10.660084] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10928 01:38:02.881481 et [0;1;39msock<6>[ 10.722371] mc: Linux media interface: v0.10
10929 01:38:02.889303 <6>[ 10.743384] videodev: Linux video capture interface: v2.00
10930 01:38:02.896353 <6>[ 10.746403] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10931 01:38:02.903278 <4>[ 10.747759] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10932 01:38:02.909656 <4>[ 10.748757] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10933 01:38:02.920321 ets.target[0m -<6>[ 10.765788] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10934 01:38:02.926753 <6>[ 10.765793] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10935 01:38:02.933548 <6>[ 10.765806] remoteproc remoteproc0: remote processor scp is now up
10936 01:38:02.936836 Socket Units.
10937 01:38:02.945381 <4>[ 10.770832] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10938 01:38:02.951054 <4>[ 10.770832] Fallback method does not support PEC.
10939 01:38:02.959361 <6>[ 10.784959] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10940 01:38:02.959927
10941 01:38:02.964173 <6>[ 10.784977] pci_bus 0000:00: root bus resource [bus 00-ff]
10942 01:38:02.972110 <6>[ 10.784988] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10943 01:38:02.978787 <6>[ 10.784993] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10944 01:38:02.984570 <6>[ 10.785030] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10945 01:38:02.994361 [[0;32m OK [0m] Reached targ<6>[ 10.785045] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10946 01:38:03.001377 et [0;1;39mbasi<6>[ 10.785121] pci 0000:00:00.0: supports D1 D2
10947 01:38:03.010989 c.target[0m - B<6>[ 10.785123] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10948 01:38:03.011558 asic System.
10949 01:38:03.021588 <3>[ 10.787624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 01:38:03.028245 <6>[ 10.802737] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10951 01:38:03.035289 <6>[ 10.806624] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10952 01:38:03.045702 <6>[ 10.806665] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10953 01:38:03.051924 <6>[ 10.806685] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10954 01:38:03.059553 <6>[ 10.806700] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10955 01:38:03.062287 <6>[ 10.806831] pci 0000:01:00.0: supports D1 D2
10956 01:38:03.069645 <6>[ 10.806834] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10957 01:38:03.076892 <3>[ 10.817810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 01:38:03.083700 <6>[ 10.828873] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10959 01:38:03.094206 <6>[ 10.828934] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10960 01:38:03.099935 <6>[ 10.828940] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10961 01:38:03.110283 <6>[ 10.828953] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10962 01:38:03.116719 <6>[ 10.828969] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10963 01:38:03.123422 <6>[ 10.828985] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10964 01:38:03.131498 <6>[ 10.829018] pci 0000:00:00.0: PCI bridge to [bus 01]
10965 01:38:03.137735 <6>[ 10.829026] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10966 01:38:03.143778 <6>[ 10.829240] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10967 01:38:03.150566 <6>[ 10.830278] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10968 01:38:03.157177 <6>[ 10.830553] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10969 01:38:03.164599 <6>[ 10.838046] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10970 01:38:03.174426 <6>[ 10.839703] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10971 01:38:03.181564 <3>[ 10.841600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 01:38:03.191748 <6>[ 10.852961] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10973 01:38:03.202194 Startin<3>[ 10.868244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 01:38:03.212526 g [0;1;39mdbus.<6>[ 10.890751] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10975 01:38:03.221748 service[0m - D-<6>[ 10.891099] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10976 01:38:03.232822 Bus System Messa<3>[ 10.906255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 01:38:03.236823 ge Bus...
10978 01:38:03.243547 <5>[ 10.915283] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10979 01:38:03.246467 <6>[ 10.929583] Bluetooth: Core ver 2.22
10980 01:38:03.253185 <6>[ 10.929816] NET: Registered PF_BLUETOOTH protocol family
10981 01:38:03.260068 <6>[ 10.929832] Bluetooth: HCI device and connection manager initialized
10982 01:38:03.263536 <6>[ 10.929888] Bluetooth: HCI socket layer initialized
10983 01:38:03.269465 <6>[ 10.929899] Bluetooth: L2CAP socket layer initialized
10984 01:38:03.273784 <6>[ 10.929919] Bluetooth: SCO socket layer initialized
10985 01:38:03.280445 <6>[ 10.935994] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10986 01:38:03.287361 <6>[ 10.937643] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10987 01:38:03.304963 Starting [0;1;39msystemd-logind.se…i<6>[ 10.941466] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10988 01:38:03.311529 ce[0m - User Lo<6>[ 10.941828] usbcore: registered new interface driver uvcvideo
10989 01:38:03.320948 gin Management..<5>[ 10.955953] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10990 01:38:03.327850 <5>[ 10.956190] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10991 01:38:03.328285 .
10992 01:38:03.338799 <4>[ 10.956252] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10993 01:38:03.341363 <6>[ 10.956260] cfg80211: failed to load regulatory.db
10994 01:38:03.351809 <3>[ 10.984468] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10995 01:38:03.358497 <6>[ 10.995992] usbcore: registered new interface driver btusb
10996 01:38:03.368090 <4>[ 10.996644] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10997 01:38:03.378297 Starting [0;1;39msystemd-user-sess…v<3>[ 10.996656] Bluetooth: hci0: Failed to load firmware file (-2)
10998 01:38:03.384578 ice[0m - Permit<3>[ 10.996659] Bluetooth: hci0: Failed to set up firmware (-2)
10999 01:38:03.394966 <4>[ 10.996661] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11000 01:38:03.404523 <3>[ 10.997396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 01:38:03.415120 User Sessions..<3>[ 11.055804] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 01:38:03.424849 <3>[ 11.057438] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11003 01:38:03.431839 <6>[ 11.069485] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11004 01:38:03.437689 <6>[ 11.069581] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11005 01:38:03.438163 .
11006 01:38:03.444517 <6>[ 11.090479] mt7921e 0000:01:00.0: ASIC revision: 79610010
11007 01:38:03.454334 <3>[ 11.116988] power_supply sbs-5-000b: driver failed to report `constant_charge_voltage_max' property: -6
11008 01:38:03.466241 <6>[ 11.184402] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11009 01:38:03.466768 <6>[ 11.184402]
11010 01:38:03.470884 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11011 01:38:03.499334 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11012 01:38:03.529260 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Man<6>[ 11.443087] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11013 01:38:03.532765 agement.
11014 01:38:03.550829 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11015 01:38:03.572698 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11016 01:38:03.593119 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11017 01:38:03.657789 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11018 01:38:03.681590 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11019 01:38:03.705372 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11020 01:38:03.725612 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11021 01:38:03.745497 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11022 01:38:03.798244 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11023 01:38:03.823025 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11024 01:38:03.848417 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11025 01:38:03.902347 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11026 01:38:03.921828 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11027 01:38:03.948350 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11028 01:38:04.009512
11029 01:38:04.012482 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11030 01:38:04.013085
11031 01:38:04.015054 debian-bookworm-arm64 login: root (automatic login)
11032 01:38:04.015539
11033 01:38:04.030992 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
11034 01:38:04.031602
11035 01:38:04.037114 The programs included with the Debian GNU/Linux system are free software;
11036 01:38:04.044309 the exact distribution terms for each program are described in the
11037 01:38:04.047652 individual files in /usr/share/doc/*/copyright.
11038 01:38:04.048291
11039 01:38:04.055089 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11040 01:38:04.057394 permitted by applicable law.
11041 01:38:04.058930 Matched prompt #10: / #
11043 01:38:04.060022 Setting prompt string to ['/ #']
11044 01:38:04.060507 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11046 01:38:04.061659 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
11047 01:38:04.062146 start: 2.2.6 expect-shell-connection (timeout 00:02:24) [common]
11048 01:38:04.062541 Setting prompt string to ['/ #']
11049 01:38:04.062882 Forcing a shell prompt, looking for ['/ #']
11051 01:38:04.113752 / #
11052 01:38:04.114416 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11053 01:38:04.114872 Waiting using forced prompt support (timeout 00:02:30)
11054 01:38:04.120390
11055 01:38:04.121324 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11056 01:38:04.121848 start: 2.2.7 export-device-env (timeout 00:02:24) [common]
11057 01:38:04.122351 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11058 01:38:04.122840 end: 2.2 depthcharge-retry (duration 00:02:36) [common]
11059 01:38:04.123294 end: 2 depthcharge-action (duration 00:02:36) [common]
11060 01:38:04.123780 start: 3 lava-test-retry (timeout 00:07:00) [common]
11061 01:38:04.124242 start: 3.1 lava-test-shell (timeout 00:07:00) [common]
11062 01:38:04.124653 Using namespace: common
11064 01:38:04.225825 / # #
11065 01:38:04.226507 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11066 01:38:04.232520 #
11067 01:38:04.233450 Using /lava-14173506
11069 01:38:04.334847 / # export SHELL=/bin/sh
11070 01:38:04.341256 export SHELL=/bin/sh
11072 01:38:04.442953 / # . /lava-14173506/environment
11073 01:38:04.443743 <6>[ 12.313251] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11074 01:38:04.449640 . /lava-14173506/environment
11076 01:38:04.551401 / # /lava-14173506/bin/lava-test-runner /lava-14173506/0
11077 01:38:04.552032 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 01:38:04.557558 /lava-14173506/bin/lava-test-runner /lava-14173506/0
11079 01:38:04.581499 + export TESTRUN_ID=0_igt-kms-mediatek
11080 01:38:04.588139 + cd /la<8>[ 12.504110] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14173506_1.5.2.3.1>
11081 01:38:04.589027 Received signal: <STARTRUN> 0_igt-kms-mediatek 14173506_1.5.2.3.1
11082 01:38:04.589451 Starting test lava.0_igt-kms-mediatek (14173506_1.5.2.3.1)
11083 01:38:04.589893 Skipping test definition patterns.
11084 01:38:04.592404 va-14173506/0/tests/0_igt-kms-mediatek
11085 01:38:04.592910 + cat uuid
11086 01:38:04.595352 + UUID=14173506_1.5.2.3.1
11087 01:38:04.595825 + set +x
11088 01:38:04.604487 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core<8>[ 12.522626] <LAVA_SIGNAL_TESTSET START core_auth>
11089 01:38:04.605351 Received signal: <TESTSET> START core_auth
11090 01:38:04.605785 Starting test_set core_auth
11091 01:38:04.614645 _auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_re<14>[ 12.535570] [IGT] core_auth: executing
11092 01:38:04.624170 ad kms_addfb_bas<14>[ 12.535819] [IGT] core_auth: starting subtest getclient-simple
11093 01:38:04.631333 ic kms_atomic km<14>[ 12.535974] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11094 01:38:04.639234 s_flip_event_lea<14>[ 12.536031] [IGT] core_auth: exiting, ret=0
11095 01:38:04.647774 k kms_prop_blob <8>[ 12.540614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11096 01:38:04.648632 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11098 01:38:04.650830 kms_setmode kms_<14>[ 12.572339] [IGT] core_auth: executing
11099 01:38:04.654031 vblank
11100 01:38:04.661019 IGT-Vers<14>[ 12.572672] [IGT] core_auth: starting subtest getclient-master-drop
11101 01:38:04.670998 ion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip2<14>[ 12.586034] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11102 01:38:04.674126 2-rt12 aarch64)
11103 01:38:04.677665 <14>[ 12.586135] [IGT] core_auth: exiting, ret=0
11104 01:38:04.678231
11105 01:38:04.687500 Using IGT_SRAND<8>[ 12.591724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11106 01:38:04.688348 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11108 01:38:04.691076 OM=1717551484 for randomisation
11109 01:38:04.697263 Starting subtest: getclient-sim<14>[ 12.614231] [IGT] core_auth: executing
11110 01:38:04.697825 ple
11111 01:38:04.704017 Opened devi<14>[ 12.614649] [IGT] core_auth: starting subtest basic-auth
11112 01:38:04.710636 ce: /dev/dri/car<14>[ 12.614842] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11113 01:38:04.711110 d0
11114 01:38:04.717171 [1mSubtest <14>[ 12.614902] [IGT] core_auth: exiting, ret=0
11115 01:38:04.724259 getclient-simple<8>[ 12.620768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11116 01:38:04.725120 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11118 01:38:04.727293 : SUCCESS (0.000s)[0m
11119 01:38:04.735280 IGT-Vers<14>[ 12.651158] [IGT] core_auth: executing
11120 01:38:04.737287 <14>[ 12.651486] [IGT] core_auth: starting subtest many-magics
11121 01:38:04.746929 ion: 1.28-ga44eb<14>[ 12.663763] [IGT] core_auth: finished subtest many-magics, SUCCESS
11122 01:38:04.750760 <14>[ 12.663819] [IGT] core_auth: exiting, ret=0
11123 01:38:04.757232 <8>[ 12.668300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11124 01:38:04.758087 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11126 01:38:04.760340 <8>[ 12.670343] <LAVA_SIGNAL_TESTSET STOP>
11127 01:38:04.761093 Received signal: <TESTSET> STOP
11128 01:38:04.761504 Closing test_set core_auth
11129 01:38:04.766809 fe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11130 01:38:04.770034 Using IGT_SRANDOM=1717551484 for randomisation
11131 01:38:04.773871 Starting subtest: getclient-master-drop
11132 01:38:04.776681 Opened device: /dev/dri/card0
11133 01:38:04.780113 [1mSub<14>[ 12.697135] [IGT] core_getclient: executing
11134 01:38:04.787276 test getclient-m<14>[ 12.697483] [IGT] core_getclient: exiting, ret=0
11135 01:38:04.793576 <8>[ 12.702184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11136 01:38:04.794427 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11138 01:38:04.797080 aster-drop: SUCCESS (0.013s)[0m
11139 01:38:04.803369 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11140 01:38:04.806913 Using IGT_SRANDOM=1717551484 for randomisation
11141 01:38:04.809767 Opened device: /dev/dri/card0
11142 01:38:04.813489 Starting subtest: basic-auth
11143 01:38:04.816934 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11144 01:38:04.823420 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11145 01:38:04.827147 Using IGT_SRANDOM=1717551484 for randomisation
11146 01:38:04.833617 O<14>[ 12.748929] [IGT] core_getstats: executing
11147 01:38:04.836423 <14>[ 12.749287] [IGT] core_getstats: exiting, ret=0
11148 01:38:04.843408 <8>[ 12.755973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11149 01:38:04.844270 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11151 01:38:04.846629 pened device: /dev/dri/card0
11152 01:38:04.849896 Starting subtest: many-magics
11153 01:38:04.853247 Reopening device failed after 1020 opens
11154 01:38:04.856860 [1mSubtest many-magics: SUCCESS (0.008s)[0m
11155 01:38:04.863257 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11156 01:38:04.866786 Using IGT_SRANDOM=1717551484 for randomisation
11157 01:38:04.869564 Opened device: /dev/dri/card0
11158 01:38:04.873267 SUCCESS (0.000s)
11159 01:38:04.879855 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.797660] [IGT] core_getversion: executing
11160 01:38:04.886190 <14>[ 12.797996] [IGT] core_getversion: exiting, ret=0
11161 01:38:04.893671 <8>[ 12.804543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11162 01:38:04.894519 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11164 01:38:04.896220 .92-cip22-rt12 aarch64)
11165 01:38:04.900223 Using IGT_SRANDOM=1717551484 for randomisation
11166 01:38:04.903044 Opened device: /dev/dri/card0
11167 01:38:04.903611 SUCCESS (0.000s)
11168 01:38:04.912885 IGT-Version: 1.28-ga44ebfe (aarch64) (<14>[ 12.832583] [IGT] core_setmaster_vs_auth: executing
11169 01:38:04.916897 Linux: 6.1.92-cip22-rt12 aarch64)
11170 01:38:04.922705 Using IGT_SRA<14>[ 12.838385] [IGT] core_setmaster_vs_auth: exiting, ret=0
11171 01:38:04.929607 <8>[ 12.844077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11172 01:38:04.930467 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11174 01:38:04.932921 NDOM=1717551484 for randomisation
11175 01:38:04.939748 Opened device: /dev/dri/card0<8>[ 12.860545] <LAVA_SIGNAL_TESTSET START drm_read>
11176 01:38:04.940319
11177 01:38:04.940964 Received signal: <TESTSET> START drm_read
11178 01:38:04.941441 Starting test_set drm_read
11179 01:38:04.942606 SUCCESS (0.000s)
11180 01:38:04.949644 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11181 01:38:04.953168 Using IGT_SRANDOM=1717551484 for randomisation
11182 01:38:04.956215 Opened device: /dev/dri/card0
11183 01:38:04.956778 SUCCESS (0.005s)
11184 01:38:04.969977 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 12.887116] [IGT] drm_read: executing
11185 01:38:04.973703 <14>[ 12.887793] [IGT] drm_read: exiting, ret=77
11186 01:38:04.980323 <8>[ 12.893741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11187 01:38:04.981167 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11189 01:38:04.983891 h64) (Linux: 6.1.92-cip22-rt12 aarch64)
11190 01:38:04.990847 Using I<14>[ 12.908011] [IGT] drm_read: executing
11191 01:38:04.993116 <14>[ 12.908478] [IGT] drm_read: exiting, ret=77
11192 01:38:05.000553 <8>[ 12.914998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11193 01:38:05.001439 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11195 01:38:05.004372 GT_SRANDOM=1717551484 for randomisation
11196 01:38:05.006248 Opened <14>[ 12.927846] [IGT] drm_read: executing
11197 01:38:05.013837 <14>[ 12.928282] [IGT] drm_read: exiting, ret=77
11198 01:38:05.019575 <8>[ 12.932939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11199 01:38:05.020415 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11201 01:38:05.023746 device: /dev/dri/card0
11202 01:38:05.026699 No KMS driver or no outp<14>[ 12.946422] [IGT] drm_read: executing
11203 01:38:05.033459 uts, pipes: 16, <14>[ 12.946924] [IGT] drm_read: exiting, ret=77
11204 01:38:05.034033 outputs: 0
11205 01:38:05.043678 [1m<8>[ 12.951652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11206 01:38:05.044519 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11208 01:38:05.046024 Subtest invalid-buffer: SKIP (0.000s)[0m
11209 01:38:05.056731 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch6<14>[ 12.976249] [IGT] drm_read: executing
11210 01:38:05.057349 4)
11211 01:38:05.063051 Using IGT_SRANDOM=1717551484 for randomisati<14>[ 12.981581] [IGT] drm_read: exiting, ret=77
11212 01:38:05.073012 <8>[ 12.986922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11213 01:38:05.073580 on
11214 01:38:05.074231 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11216 01:38:05.075913 Opened device: /dev/dri/card0
11217 01:38:05.079508 No KMS driver<14>[ 13.000038] [IGT] drm_read: executing
11218 01:38:05.086693 <14>[ 13.000491] [IGT] drm_read: exiting, ret=77
11219 01:38:05.092680 <8>[ 13.006220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11220 01:38:05.093527 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11222 01:38:05.099500 or no outputs, pipes: 16, outpu<14>[ 13.019263] [IGT] drm_read: executing
11223 01:38:05.100066 ts: 0
11224 01:38:05.106600 [1mSubte<14>[ 13.019727] [IGT] drm_read: exiting, ret=77
11225 01:38:05.113439 <8>[ 13.024087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11226 01:38:05.114280 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11228 01:38:05.116250 <8>[ 13.026215] <LAVA_SIGNAL_TESTSET STOP>
11229 01:38:05.116973 Received signal: <TESTSET> STOP
11230 01:38:05.117409 Closing test_set drm_read
11231 01:38:05.119792 st fault-buffer: SKIP (0.000s)[0m
11232 01:38:05.125840 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11233 01:38:05.129148 Using IGT_SRANDOM=1717551484 for randomisation
11234 01:38:05.133375 Opened device: /dev/dri/card0
11235 01:38:05.143068 No KMS driver or no outputs, pipes: <8>[ 13.057178] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11236 01:38:05.143546 16, outputs: 0
11237 01:38:05.144195 Received signal: <TESTSET> START kms_addfb_basic
11238 01:38:05.144578 Starting test_set kms_addfb_basic
11239 01:38:05.146010 [1mSubtest empty-block: SKIP (0.000s)[0m
11240 01:38:05.152640 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11241 01:38:05.159529 Using IGT_SRANDOM=171755148<14>[ 13.079789] [IGT] kms_addfb_basic: executing
11242 01:38:05.165975 <14>[ 13.084433] [IGT] kms_addfb_basic: starting subtest unused-handle
11243 01:38:05.175890 5 for randomisat<14>[ 13.092711] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11244 01:38:05.176452 ion
11245 01:38:05.178713 Opened device: /dev/dri/card0
11246 01:38:05.185642 No KMS drive<14>[ 13.101771] [IGT] kms_addfb_basic: exiting, ret=0
11247 01:38:05.192129 <8>[ 13.106800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11248 01:38:05.193048 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11250 01:38:05.196129 r or no outputs, pipes: 16, outputs: 0
11251 01:38:05.198868 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11252 01:38:05.205642 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11253 01:38:05.211809 Using IGT_SRANDOM=1717551485 for<14>[ 13.130995] [IGT] kms_addfb_basic: executing
11254 01:38:05.218850 <14>[ 13.135865] [IGT] kms_addfb_basic: starting subtest unused-pitches
11255 01:38:05.223003 randomisation
11256 01:38:05.223558 Opened device: /dev/dri/card0
11257 01:38:05.231857 N<14>[ 13.145397] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11258 01:38:05.242238 o KMS driver or no outputs, pipes: 16, outputs: <14>[ 13.157288] [IGT] kms_addfb_basic: exiting, ret=0
11259 01:38:05.248722 <8>[ 13.163341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11260 01:38:05.249310 0
11261 01:38:05.249996 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11263 01:38:05.253346 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11264 01:38:05.261791 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<14>[ 13.177141] [IGT] kms_addfb_basic: executing
11265 01:38:05.269077 <14>[ 13.181616] [IGT] kms_addfb_basic: starting subtest unused-offsets
11266 01:38:05.269645 x: 6.1.92-cip22-rt12 aarch64)
11267 01:38:05.278802 Using IGT_SRANDOM<14>[ 13.192823] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11268 01:38:05.285277 =1717551485 for <14>[ 13.204590] [IGT] kms_addfb_basic: exiting, ret=0
11269 01:38:05.291947 <8>[ 13.210130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11270 01:38:05.292511 randomisation
11271 01:38:05.293174 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11273 01:38:05.295598 Opened device: /dev/dri/card0
11274 01:38:05.305557 No KMS driver or no outputs, pipes<14>[ 13.224138] [IGT] kms_addfb_basic: executing
11275 01:38:05.311446 <14>[ 13.228515] [IGT] kms_addfb_basic: starting subtest unused-modifier
11276 01:38:05.318905 : 16, outputs: 0<14>[ 13.236348] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11277 01:38:05.319653
11278 01:38:05.329252 [1mSubtest short-buffer-nonblock: SKIP (0.000<14>[ 13.245370] [IGT] kms_addfb_basic: exiting, ret=0
11279 01:38:05.335566 <8>[ 13.251277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11280 01:38:05.336040 s)[0m
11281 01:38:05.336680 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11283 01:38:05.344905 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<14>[ 13.263689] [IGT] kms_addfb_basic: executing
11284 01:38:05.352179 <14>[ 13.268058] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11285 01:38:05.354995 nux: 6.1.92-cip22-rt12 aarch64)
11286 01:38:05.365516 Using IGT_SRAND<14>[ 13.277492] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11287 01:38:05.366081 OM=1717551485 for randomisation
11288 01:38:05.371977 Opened device: <14>[ 13.289417] [IGT] kms_addfb_basic: exiting, ret=77
11289 01:38:05.381982 <8>[ 13.295346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11290 01:38:05.382548 /dev/dri/card0
11291 01:38:05.383204 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11293 01:38:05.388018 No KMS driver or no outputs, pip<14>[ 13.308286] [IGT] kms_addfb_basic: executing
11294 01:38:05.398206 <14>[ 13.312659] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11295 01:38:05.398772 es: 16, outputs: 0
11296 01:38:05.408258 [1mSubtest <14>[ 13.322746] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11297 01:38:05.412133 short-buffer-wakeup: SKIP (0.000s)[0m
11298 01:38:05.418387 IGT-Vers<14>[ 13.333961] [IGT] kms_addfb_basic: exiting, ret=77
11299 01:38:05.428459 ion: 1.28-ga44eb<8>[ 13.338600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11300 01:38:05.429344 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11302 01:38:05.430953 fe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11303 01:38:05.434905 Using IGT_SRANDOM=1717551485 for randomisation
11304 01:38:05.437887 Opened device: /dev/dri/card0
11305 01:38:05.445349 Starting subtest<14>[ 13.362905] [IGT] kms_addfb_basic: executing
11306 01:38:05.451530 <14>[ 13.367600] [IGT] kms_addfb_basic: starting subtest legacy-format
11307 01:38:05.452095 : unused-handle
11308 01:38:05.454722 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11309 01:38:05.468018 Test requirement not met in function igt_requi<14>[ 13.382455] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11310 01:38:05.471475 re_intel, file ../lib/drmtest.c:880:
11311 01:38:05.478227 Test requi<14>[ 13.393387] [IGT] kms_addfb_basic: exiting, ret=0
11312 01:38:05.484793 <8>[ 13.398912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11313 01:38:05.485678 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11315 01:38:05.487499 rement: is_intel_device(fd)
11316 01:38:05.491353 Test requirement no<14>[ 13.410690] [IGT] kms_addfb_basic: executing
11317 01:38:05.498102 <14>[ 13.417238] [IGT] kms_addfb_basic: starting subtest no-handle
11318 01:38:05.507359 t met in functio<14>[ 13.424383] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11319 01:38:05.511031 n igt_require_intel, file ../lib/drmtest.c:880:
11320 01:38:05.514344 Test requirement: is_intel_device(fd)
11321 01:38:05.517704 No KMS driver or no outputs, pipes: 16, outputs: 0
11322 01:38:05.524612 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11323 01:38:05.531361 Using IGT_SRANDOM=1717551485 for randomisation
11324 01:38:05.531986 Opened device: /dev/dri/card0
11325 01:38:05.534289 Starting subtest: unused-pitches
11326 01:38:05.541367 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11327 01:38:05.547907 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11328 01:38:05.550822 Test requirement: is_intel_device(fd)
11329 01:38:05.557550 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11330 01:38:05.560667 Test requirement: is_intel_device(fd)
11331 01:38:05.564954 No KMS driver or no outputs, pipes: 16, outputs: 0
11332 01:38:05.571184 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11333 01:38:05.577726 Using IGT_SRANDOM=1717551485 for randomisation
11334 01:38:05.578302 Opened device: /dev/dri/card0
11335 01:38:05.581156 Starting subtest: unused-offsets
11336 01:38:05.587709 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11337 01:38:05.594558 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11338 01:38:05.598311 Test requirement: is_intel_device(fd)
11339 01:38:05.604679 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11340 01:38:05.607949 Test requirement: is_intel_device(fd)
11341 01:38:05.610952 No KMS driver or no outputs, pipes: 16, outputs: 0
11342 01:38:05.617051 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11343 01:38:05.623669 Using IGT_SRANDOM=1717551485 for randomisation
11344 01:38:05.624241 Opened device: /dev/dri/card0
11345 01:38:05.626836 Starting subtest: unused-modifier
11346 01:38:05.634048 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11347 01:38:05.639896 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11348 01:38:05.643382 Test requirement: is_intel_device(fd)
11349 01:38:05.650994 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11350 01:38:05.654729 Test requirement: is_intel_device(fd)
11351 01:38:05.657207 No KMS driver or no outputs, pipes: 16, outputs: 0
11352 01:38:05.664271 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11353 01:38:05.670749 Using IGT_SRANDOM=1717551485 for randomisation
11354 01:38:05.671308 Opened device: /dev/dri/card0
11355 01:38:05.673033 Starting subtest: clobberred-modifier
11356 01:38:05.684565 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:885:
11357 01:38:05.686429 Test requirement: is_i915_device(fd)
11358 01:38:05.689865 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11359 01:38:05.696579 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11360 01:38:05.699884 Test requirement: is_intel_device(fd)
11361 01:38:05.706753 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11362 01:38:05.710251 Test requirement: is_intel_device(fd)
11363 01:38:05.716714 No KMS driver or no outputs, pipes: 16, outputs: 0
11364 01:38:05.723865 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11365 01:38:05.726946 Using IGT_SRANDOM=1717551485 for randomisation
11366 01:38:05.729878 Opened device: /dev/dri/card0
11367 01:38:05.732892 Starting subtest: invalid-smem-bo-on-discrete
11368 01:38:05.739515 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11369 01:38:05.743602 Test requirement: is_intel_device(fd)
11370 01:38:05.750076 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11371 01:38:05.755909 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11372 01:38:05.759678 Test requirement: is_intel_device(fd)
11373 01:38:05.766489 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11374 01:38:05.770230 Test requirement: is_intel_device(fd)
11375 01:38:05.776918 No KMS driver or no outputs, pipes: 16, outputs: 0
11376 01:38:05.783240 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11377 01:38:05.786419 Using IGT_SRANDOM=1717551485 for randomisation
11378 01:38:05.789320 Opened device: /dev/dri/card0
11379 01:38:05.789790 Starting subtest: legacy-format
11380 01:38:05.796344 Successfully fuzzed 10000 {bpp, depth} variations
11381 01:38:05.799912 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11382 01:38:05.805901 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11383 01:38:05.809131 Test requirement: is_intel_device(fd)
11384 01:38:05.816126 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11385 01:38:05.819810 Test requirement: is_intel_device(fd)
11386 01:38:05.826596 No KMS driver or no outputs, pipes: 16, outputs: 0
11387 01:38:05.832702 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11388 01:38:05.835943 Using IGT_SRANDOM=1717551485 for randomisation
11389 01:38:05.839281 Opened device: /dev/dri/card0
11390 01:38:05.842623 Starting subtest: no-handle
11391 01:38:05.848922 [1mSubtest no-handle: SUCCESS (0.000s<14>[ 13.766516] [IGT] kms_addfb_basic: exiting, ret=0
11392 01:38:05.856150 <8>[ 13.773069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11393 01:38:05.856707 )[0m
11394 01:38:05.857445 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11396 01:38:05.869510 Test requirement not met in function igt_require_intel, file ../lib/drmte<14>[ 13.784819] [IGT] kms_addfb_basic: executing
11397 01:38:05.870084 st.c:880:
11398 01:38:05.875310 Test <14>[ 13.791328] [IGT] kms_addfb_basic: starting subtest basic
11399 01:38:05.879028 requirement: is_intel_device(fd)
11400 01:38:05.887127 Test requireme<14>[ 13.800857] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11401 01:38:05.892173 nt not met in fu<14>[ 13.811870] [IGT] kms_addfb_basic: exiting, ret=0
11402 01:38:05.899299 <8>[ 13.817259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11403 01:38:05.900146 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11405 01:38:05.901791 nction igt_require_intel, file ../lib/drmtest.c:880:
11406 01:38:05.906594 Test requirement: is_intel_device(fd)
11407 01:38:05.913513 No KMS driver or no<14>[ 13.829771] [IGT] kms_addfb_basic: executing
11408 01:38:05.918886 <14>[ 13.836439] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11409 01:38:05.921935 outputs, pipes: 16, outputs: 0
11410 01:38:05.932854 IGT-Version: 1.<14>[ 13.845188] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11411 01:38:05.934987 28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11412 01:38:05.941937 Using <14>[ 13.856905] [IGT] kms_addfb_basic: exiting, ret=0
11413 01:38:05.949449 <8>[ 13.862452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11414 01:38:05.950290 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11416 01:38:05.951699 IGT_SRANDOM=1717551485 for randomisation
11417 01:38:05.958367 Opened<14>[ 13.876511] [IGT] kms_addfb_basic: executing
11418 01:38:05.958926 device: /dev/dri/card0
11419 01:38:05.961721 Starting subtest: basic
11420 01:38:05.965386 [1mSubtest basic: SUCCESS (0.000s)[0m
11421 01:38:05.975226 Test requirement not met in function <14>[ 13.889029] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11422 01:38:05.981842 <14>[ 13.889123] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11423 01:38:05.988085 igt_require_intel, file ../lib/d<14>[ 13.907731] [IGT] kms_addfb_basic: exiting, ret=0
11424 01:38:05.996125 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11426 01:38:05.997840 <8>[ 13.913393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11427 01:38:05.998313 rmtest.c:880:
11428 01:38:06.003065 Test requirement: is_intel_device(fd)
11429 01:38:06.008826 Test requirement not met i<14>[ 13.926373] [IGT] kms_addfb_basic: executing
11430 01:38:06.015060 <14>[ 13.932989] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11431 01:38:06.025096 n function igt_r<14>[ 13.940391] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11432 01:38:06.027745 equire_intel, file ../lib/drmtest.c:880:
11433 01:38:06.031077 Test r<14>[ 13.949216] [IGT] kms_addfb_basic: exiting, ret=0
11434 01:38:06.038607 <8>[ 13.954940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11435 01:38:06.039503 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11437 01:38:06.041364 equirement: is_intel_device(fd)
11438 01:38:06.048004 No KMS driver o<14>[ 13.967390] [IGT] kms_addfb_basic: executing
11439 01:38:06.055045 <14>[ 13.973898] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11440 01:38:06.064653 r no outputs, pi<14>[ 13.980552] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11441 01:38:06.065252 pes: 16, outputs: 0
11442 01:38:06.074383 IGT-Version: 1.28-ga44ebfe <14>[ 13.989398] [IGT] kms_addfb_basic: exiting, ret=0
11443 01:38:06.080918 <8>[ 13.995074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11444 01:38:06.081806 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11446 01:38:06.084451 (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11447 01:38:06.088067 Us<14>[ 14.007409] [IGT] kms_addfb_basic: executing
11448 01:38:06.094726 <14>[ 14.013897] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11449 01:38:06.100849 <14>[ 14.020747] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11450 01:38:06.107373 ing IGT_SRANDOM=<14>[ 14.028242] [IGT] kms_addfb_basic: exiting, ret=0
11451 01:38:06.114024 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11453 01:38:06.118122 <8>[ 14.033578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11454 01:38:06.118684 1717551485 for randomisation
11455 01:38:06.121137 Opened device: /dev/dri/card0
11456 01:38:06.123918 Starting subtest: bad-pitch-0
11457 01:38:06.127632 [1m<14>[ 14.045149] [IGT] kms_addfb_basic: executing
11458 01:38:06.134322 <14>[ 14.051505] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11459 01:38:06.140531 Subtest bad-pitch-0: SUCCESS (0.000s)[0m
11460 01:38:06.147441 Test <14>[ 14.061045] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11461 01:38:06.157670 requirement not met in function igt_require_intel, file ../lib/d<14>[ 14.072899] [IGT] kms_addfb_basic: exiting, ret=0
11462 01:38:06.163922 <8>[ 14.078511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11463 01:38:06.164659 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11465 01:38:06.167454 rmtest.c:880:
11466 01:38:06.173899 Test requirement:<14>[ 14.090477] [IGT] kms_addfb_basic: executing
11467 01:38:06.176640 <14>[ 14.096913] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11468 01:38:06.187103 is_intel_device<14>[ 14.104370] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11469 01:38:06.187673 (fd)
11470 01:38:06.197799 Test requirement not met in function igt_r<14>[ 14.113294] [IGT] kms_addfb_basic: exiting, ret=0
11471 01:38:06.203627 <8>[ 14.118750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11472 01:38:06.204469 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11474 01:38:06.206753 equire_intel, file ../lib/drmtest.c:880:
11475 01:38:06.213460 Test r<14>[ 14.130187] [IGT] kms_addfb_basic: executing
11476 01:38:06.220254 <14>[ 14.136557] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11477 01:38:06.223393 equirement: is_intel_device(fd)
11478 01:38:06.230155 No KMS driver o<14>[ 14.144982] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11479 01:38:06.233452 r no outputs, pipes: 16, outputs: 0
11480 01:38:06.240365 IGT-Version: 1.28-ga44ebfe <14>[ 14.156730] [IGT] kms_addfb_basic: exiting, ret=0
11481 01:38:06.247279 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11483 01:38:06.250287 <8>[ 14.162255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11484 01:38:06.256534 (aarch64) (Linux: 6.1.92-cip22-r<14>[ 14.174412] [IGT] kms_addfb_basic: executing
11485 01:38:06.257105 t12 aarch64)
11486 01:38:06.267880 Using IGT_SRANDOM=1717551485 for r<14>[ 14.182727] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11487 01:38:06.276738 <14>[ 14.182820] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11488 01:38:06.277467 andomisation
11489 01:38:06.280673 Opened device: /dev/dri/card0
11490 01:38:06.283548 Starting subtest: bad-pitch-32
11491 01:38:06.286744 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11492 01:38:06.293740 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11493 01:38:06.296179 Test requirement: is_intel_device(fd)
11494 01:38:06.303245 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11495 01:38:06.306072 Test requirement: is_intel_device(fd)
11496 01:38:06.313076 No KMS driver or no outputs, pipes: 16, outputs: 0
11497 01:38:06.319438 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11498 01:38:06.323247 Using IGT_SRANDOM=1717551485 for randomisation
11499 01:38:06.326504 Opened device: /dev/dri/card0
11500 01:38:06.327016 Starting subtest: bad-pitch-63
11501 01:38:06.333042 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11502 01:38:06.339849 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11503 01:38:06.342760 Test requirement: is_intel_device(fd)
11504 01:38:06.349642 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11505 01:38:06.352765 Test requirement: is_intel_device(fd)
11506 01:38:06.359689 No KMS driver or no outputs, pipes: 16, outputs: 0
11507 01:38:06.362849 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11508 01:38:06.369644 Using IGT_SRANDOM=1717551486 for randomisation
11509 01:38:06.372460 Opened device: /dev/dri/card0
11510 01:38:06.372883 Starting subtest: bad-pitch-128
11511 01:38:06.379872 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11512 01:38:06.386265 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11513 01:38:06.391002 Test requirement: is_intel_device(fd)
11514 01:38:06.396072 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11515 01:38:06.400961 Test requirement: is_intel_device(fd)
11516 01:38:06.403074 No KMS driver or no outputs, pipes: 16, outputs: 0
11517 01:38:06.409996 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11518 01:38:06.415982 Using IGT_SRANDOM=1717551486 for randomisation
11519 01:38:06.416500 Opened device: /dev/dri/card0
11520 01:38:06.419996 Starting subtest: bad-pitch-256
11521 01:38:06.425628 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11522 01:38:06.432422 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11523 01:38:06.435698 Test requirement: is_intel_device(fd)
11524 01:38:06.443590 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11525 01:38:06.445533 Test requirement: is_intel_device(fd)
11526 01:38:06.449453 No KMS driver or no outputs, pipes: 16, outputs: 0
11527 01:38:06.456066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11528 01:38:06.462298 Using IGT_SRANDOM=1717551486 for randomisation
11529 01:38:06.462817 Opened device: /dev/dri/card0
11530 01:38:06.466322 Starting subtest: bad-pitch-1024
11531 01:38:06.472766 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11532 01:38:06.478996 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11533 01:38:06.482179 Test requirement: is_intel_device(fd)
11534 01:38:06.489182 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11535 01:38:06.492082 Test requirement: is_intel_device(fd)
11536 01:38:06.495793 No KMS driver or no outputs, pipes: 16, outputs: 0
11537 01:38:06.503031 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11538 01:38:06.506429 Using IGT_SRANDOM=1717551486 for randomisation
11539 01:38:06.508943 Opened device: /dev/dri/card0
11540 01:38:06.512053 Starting subtest: bad-pitch-999
11541 01:38:06.515797 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11542 01:38:06.525500 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11543 01:38:06.529136 Test requirement: is_intel_device(fd)
11544 01:38:06.535146 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11545 01:38:06.539261 Test requirement: is_intel_device(fd)
11546 01:38:06.541780 No KMS driver or no outputs, pipes: 16, outputs: 0
11547 01:38:06.550120 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11548 01:38:06.551694 Using IGT_SRANDOM=1717551486 for randomisation
11549 01:38:06.555447 Opened device: /dev/dri/card0
11550 01:38:06.559057 Starting subtest: bad-pitch-65536
11551 01:38:06.562312 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11552 01:38:06.572180 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11553 01:38:06.575384 Test requirement: is_intel_device(fd)
11554 01:38:06.581551 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11555 01:38:06.585786 Test requirement: is_intel_device(fd)
11556 01:38:06.588250 No KMS driver or no outputs, pipes: 16, outputs: 0
11557 01:38:06.595817 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11558 01:38:06.598666 Using IGT_SRANDOM=1717551486 for randomisation
11559 01:38:06.601227 Opened device: /dev/dri/card0
11560 01:38:06.605056 Starting subtest: invalid-get-prop-any
11561 01:38:06.611541 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11562 01:38:06.615028 Test <14>[ 14.533274] [IGT] kms_addfb_basic: exiting, ret=0
11563 01:38:06.625283 <8>[ 14.539706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11564 01:38:06.626150 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11566 01:38:06.632382 requirement not met in function igt_require_inte<14>[ 14.551543] [IGT] kms_addfb_basic: executing
11567 01:38:06.636066 l, file ../lib/drmtest.c:880:
11568 01:38:06.641821 T<14>[ 14.559991] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11569 01:38:06.648109 <14>[ 14.560104] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11570 01:38:06.655197 est requirement:<14>[ 14.575882] [IGT] kms_addfb_basic: exiting, ret=0
11571 01:38:06.661814 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11573 01:38:06.665227 <8>[ 14.581182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11574 01:38:06.665794 is_intel_device(fd)
11575 01:38:06.674927 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 14.593647] [IGT] kms_addfb_basic: executing
11576 01:38:06.684932 <14>[ 14.602149] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11577 01:38:06.685550 t.c:880:
11578 01:38:06.689156 Test requirement: is_intel_device(fd)
11579 01:38:06.695076 <14>[ 14.609597] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11580 01:38:06.695638
11581 01:38:06.705072 No KMS driver or no outputs, pipes: 16, outputs<14>[ 14.621782] [IGT] kms_addfb_basic: exiting, ret=0
11582 01:38:06.711623 <8>[ 14.627751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11583 01:38:06.712113 : 0
11584 01:38:06.712877 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11586 01:38:06.718554 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11587 01:38:06.725647 Us<14>[ 14.641107] [IGT] kms_addfb_basic: executing
11588 01:38:06.732012 <14>[ 14.649659] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11589 01:38:06.734643 ing IGT_SRANDOM=1717551486 for randomisation
11590 01:38:06.741953 Op<14>[ 14.656858] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11591 01:38:06.744949 ened device: /dev/dri/card0
11592 01:38:06.748024 Starting subtest: invalid-get-prop
11593 01:38:06.755525 <14>[ 14.668803] [IGT] kms_addfb_basic: exiting, ret=0
11594 01:38:06.762168 <8>[ 14.674573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11595 01:38:06.762730
11596 01:38:06.763376 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11598 01:38:06.768061 [1mSubtest invalid-get-prop: S<14>[ 14.687279] [IGT] kms_addfb_basic: executing
11599 01:38:06.771343 UCCESS (0.000s)[0m
11600 01:38:06.781813 Test requirement not met in function igt_require_intel, fil<14>[ 14.697824] [IGT] kms_addfb_basic: starting subtest master-rmfb
11601 01:38:06.788530 <14>[ 14.698020] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11602 01:38:06.795195 <14>[ 14.700217] [IGT] kms_addfb_basic: exiting, ret=0
11603 01:38:06.801352 <8>[ 14.705936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11604 01:38:06.802203 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11606 01:38:06.805857 <14>[ 14.719470] [IGT] kms_addfb_basic: executing
11607 01:38:06.808042 e ../lib/drmtest.c:880:
11608 01:38:06.811673 Test requirement: is_intel_device(fd)
11609 01:38:06.818462 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11610 01:38:06.828231 Test requirement: is_intel_d<14>[ 14.742777] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11611 01:38:06.834557 <14>[ 14.742872] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11612 01:38:06.841782 <14>[ 14.743107] [IGT] kms_addfb_basic: exiting, ret=0
11613 01:38:06.848105 <8>[ 14.748326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11614 01:38:06.849159 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11616 01:38:06.851025 evice(fd)
11617 01:38:06.857643 No KMS driver or no o<14>[ 14.774998] [IGT] kms_addfb_basic: executing
11618 01:38:06.858222 utputs, pipes: 16, outputs: 0
11619 01:38:06.871073 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 14.787168] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11620 01:38:06.874556 92-cip22-rt12 aarch64)
11621 01:38:06.884620 Using IGT_SRANDOM=1717551486 for randomi<14>[ 14.799496] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11622 01:38:06.885245 sation
11623 01:38:06.888364 Opened device: /dev/dri/card0
11624 01:38:06.890594 Starting subtest: invalid-set-prop-any
11625 01:38:06.894286 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11626 01:38:06.904212 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11627 01:38:06.907467 Test requirement: is_intel_device(fd)
11628 01:38:06.914476 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11629 01:38:06.917396 Test requirement: is_intel_device(fd)
11630 01:38:06.920219 No KMS driver or no outputs, pipes: 16, outputs: 0
11631 01:38:06.927086 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11632 01:38:06.930154 Using IGT_SRANDOM=1717551486 for randomisation
11633 01:38:06.933704 Opened device: /dev/dri/card0
11634 01:38:06.937949 Starting subtest: invalid-set-prop
11635 01:38:06.943888 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11636 01:38:06.950859 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11637 01:38:06.953946 Test requirement: is_intel_device(fd)
11638 01:38:06.960183 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11639 01:38:06.963897 Test requirement: is_intel_device(fd)
11640 01:38:06.967141 No KMS driver or no outputs, pipes: 16, outputs: 0
11641 01:38:06.973819 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11642 01:38:06.980131 Using IGT_SRANDOM=1717551486 for randomisation
11643 01:38:06.980560 Opened device: /dev/dri/card0
11644 01:38:06.983635 Starting subtest: master-rmfb
11645 01:38:06.987260 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11646 01:38:06.996519 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11647 01:38:07.000185 Test requirement: is_intel_device(fd)
11648 01:38:07.007235 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11649 01:38:07.010376 Test requirement: is_intel_device(fd)
11650 01:38:07.013195 No KMS driver or no outputs, pipes: 16, outputs: 0
11651 01:38:07.019935 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11652 01:38:07.023276 Using IGT_SRANDOM=1717551486 for randomisation
11653 01:38:07.026754 Opened device: /dev/dri/card0
11654 01:38:07.029662 Starting subtest: addfb25-modifier-no-flag
11655 01:38:07.036794 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11656 01:38:07.043255 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11657 01:38:07.046553 Test requirement: is_intel_device(fd)
11658 01:38:07.052935 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11659 01:38:07.056614 Test requirement: is_intel_device(fd)
11660 01:38:07.063626 No KMS driver or no outputs, pipes: 16, outputs: 0
11661 01:38:07.069923 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11662 01:38:07.072933 Using IGT_SRANDOM=1717551486 for randomisation
11663 01:38:07.075979 Opened device: /dev/dri/card0
11664 01:38:07.079459 Starting subtest: addfb25-bad-modifier
11665 01:38:07.089287 (kms_addfb_basic:444) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11666 01:38:07.105869 (kms_addfb_basic:444) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11667 01:38:07.109899 (kms_addfb_basic:444) CRITICAL: error: 0 != -1
11668 01:38:07.113360 Stack trace:
11669 01:38:07.115986 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11670 01:38:07.119613 #1 [<unknown>+0xcc434358]
11671 01:38:07.122385 #2 [<unknown>+0xcc435fbc]
11672 01:38:07.122972 #3 [<unknown>+0xcc43156c]
11673 01:38:07.125861 #4 [__libc_init_first+0x80]
11674 01:38:07.128692 #5 [__libc_start_main+0x98]
11675 01:38:07.132260 #6 [<unknown>+0xcc4315b0]
11676 01:38:07.135620 Subtest addfb25-bad-modifier failed.
11677 01:38:07.136058 **** DEBUG ****
11678 01:38:07.145797 (kms_addfb_basic:444) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11679 01:38:07.155334 (kms_addfb_basic:444) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11680 01:38:07.172065 (kms_addfb_basic:444) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11681 01:38:07.178961 (kms_addfb_basic:444) CRITICAL: error: 0 != -1
11682 01:38:07.182080 (kms_addfb_basic:444) igt_core-INFO: Stack trace:
11683 01:38:07.188810 (kms_addfb_basic:444) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11684 01:38:07.195835 (kms_addfb_basic:444) igt_core-INFO: #1 [<unknown>+0xcc434358]
11685 01:38:07.201605 (kms_addfb_basic:444) igt_core-INFO: #2 [<unknown>+0xcc435fbc]
11686 01:38:07.205417 (kms_addfb_basic:444) igt_core-INFO: #3 [<unknown>+0xcc43156c]
11687 01:38:07.212476 (kms_addfb_basic:444) igt_core-INFO: #4 [__libc_init_first+0x80]
11688 01:38:07.218775 (kms_addfb_basic:444) igt_core-INFO: #5 [__libc_start_main+0x98]
11689 01:38:07.225581 (kms_addfb_basic:444) i<14>[ 15.140979] [IGT] kms_addfb_basic: exiting, ret=98
11690 01:38:07.231757 <8>[ 15.147593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11691 01:38:07.232511 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11693 01:38:07.241896 gt_core-INFO: #6 [<unknown>+0x<14>[ 15.159433] [IGT] kms_addfb_basic: executing
11694 01:38:07.242325 cc4315b0]
11695 01:38:07.242748 **** END ****
11696 01:38:07.248268 [1mSubtest addfb25-bad-modifier: FAIL (0.012s)[0m
11697 01:38:07.251626 <14>[ 15.172045] [IGT] kms_addfb_basic: exiting, ret=77
11698 01:38:07.262320 <8>[ 15.177480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11699 01:38:07.262750
11700 01:38:07.263345 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11702 01:38:07.271819 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 15.189928] [IGT] kms_addfb_basic: executing
11703 01:38:07.272360 80:
11704 01:38:07.275051 Test requirement: is_intel_device(fd)
11705 01:38:07.284570 Test requirement not met in function<14>[ 15.202720] [IGT] kms_addfb_basic: exiting, ret=77
11706 01:38:07.291501 <8>[ 15.208453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11707 01:38:07.292330 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11709 01:38:07.298928 igt_require_intel, file ../lib/drmtest.c:880:
11710 01:38:07.304666 Test requirement: is_intel_devic<14>[ 15.222167] [IGT] kms_addfb_basic: executing
11711 01:38:07.305255 e(fd)
11712 01:38:07.308253 No KMS driver or no outputs, pipes: 16, outputs: 0
11713 01:38:07.317837 IGT-Version: 1.28-ga4<14>[ 15.234972] [IGT] kms_addfb_basic: exiting, ret=77
11714 01:38:07.324619 <8>[ 15.240601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11715 01:38:07.325538 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11717 01:38:07.331052 4ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11718 01:38:07.337851 Using IGT_SRANDOM=1717551487<14>[ 15.254538] [IGT] kms_addfb_basic: executing
11719 01:38:07.338489 for randomisation
11720 01:38:07.341379 Opened device: /dev/dri/card0
11721 01:38:07.348201 Test requirement not met in f<14>[ 15.267390] [IGT] kms_addfb_basic: exiting, ret=77
11722 01:38:07.358720 <8>[ 15.273476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11723 01:38:07.359603 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11725 01:38:07.361437 unction igt_require_intel, file ../lib/drmtest.c:880:
11726 01:38:07.369124 Test requirement: is_inte<14>[ 15.287939] [IGT] kms_addfb_basic: executing
11727 01:38:07.370738 l_device(fd)
11728 01:38:07.373994 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11729 01:38:07.380875 Te<14>[ 15.300698] [IGT] kms_addfb_basic: exiting, ret=77
11730 01:38:07.394291 st requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<8>[ 15.311977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11731 01:38:07.395178 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11733 01:38:07.397237
11734 01:38:07.401195 Test requirement: is_intel_device(fd)
11735 01:38:07.404583 No KMS <14>[ 15.324022] [IGT] kms_addfb_basic: executing
11736 01:38:07.407804 driver or no outputs, pipes: 16, outputs: 0
11737 01:38:07.414188 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11738 01:38:07.421259 Using IGT_<14>[ 15.336820] [IGT] kms_addfb_basic: exiting, ret=77
11739 01:38:07.427827 <8>[ 15.342722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11740 01:38:07.428705 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11742 01:38:07.437200 SRANDOM=1717551487 for randomisa<14>[ 15.356440] [IGT] kms_addfb_basic: executing
11743 01:38:07.437774 tion
11744 01:38:07.441049 Opened device: /dev/dri/card0
11745 01:38:07.447356 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11746 01:38:07.454231 Test requirement: is_in<14>[ 15.369427] [IGT] kms_addfb_basic: exiting, ret=77
11747 01:38:07.454801 tel_device(fd)
11748 01:38:07.463623 <8>[ 15.375079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11749 01:38:07.464478 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11751 01:38:07.467002 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11752 01:38:07.475240 Test requ<14>[ 15.389142] [IGT] kms_addfb_basic: executing
11753 01:38:07.480514 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11754 01:38:07.483842 Test <14>[ 15.402103] [IGT] kms_addfb_basic: exiting, ret=77
11755 01:38:07.490466 <8>[ 15.407849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11756 01:38:07.491343 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11758 01:38:07.493668 requirement: is_intel_device(fd)
11759 01:38:07.500416 No KMS driver <14>[ 15.420374] [IGT] kms_addfb_basic: executing
11760 01:38:07.503487 or no outputs, pipes: 16, outputs: 0
11761 01:38:07.510442 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11762 01:38:07.516645 Using IGT_SRANDOM<14>[ 15.433222] [IGT] kms_addfb_basic: exiting, ret=77
11763 01:38:07.523859 <8>[ 15.438909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11764 01:38:07.524701 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11766 01:38:07.526809 =1717551487 for randomisation
11767 01:38:07.533897 Opened device: /d<14>[ 15.452277] [IGT] kms_addfb_basic: executing
11768 01:38:07.534463 ev/dri/card0
11769 01:38:07.540191 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11770 01:38:07.549975 Test requirement: is_intel_dev<14>[ 15.465311] [IGT] kms_addfb_basic: exiting, ret=77
11771 01:38:07.556628 <8>[ 15.470951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11772 01:38:07.557248 ice(fd)
11773 01:38:07.557905 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11775 01:38:07.563452 [1mSubtest addfb25-framebuffer-vs-set-<14>[ 15.484291] [IGT] kms_addfb_basic: executing
11776 01:38:07.566550 tiling: SKIP (0.000s)[0m
11777 01:38:07.573844 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11778 01:38:07.576782 Test requirement: is_intel_device(fd)
11779 01:38:07.583524 No KMS driver or no outputs, pipes: 16, outputs: 0
11780 01:38:07.589755 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11781 01:38:07.592958 Using IGT_SRANDOM=1717551487 for randomisation
11782 01:38:07.596616 Opened device: /dev/dri/card0
11783 01:38:07.602745 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11784 01:38:07.606270 Test requirement: is_intel_device(fd)
11785 01:38:07.613057 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11786 01:38:07.616493 Test requirement: is_intel_device(fd)
11787 01:38:07.622940 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11788 01:38:07.627402 No KMS driver or no outputs, pipes: 16, outputs: 0
11789 01:38:07.633974 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11790 01:38:07.636097 Using IGT_SRANDOM=1717551487 for randomisation
11791 01:38:07.639433 Opened device: /dev/dri/card0
11792 01:38:07.645917 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11793 01:38:07.649827 Test requirement: is_intel_device(fd)
11794 01:38:07.655936 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11795 01:38:07.659707 Test requirement: is_intel_device(fd)
11796 01:38:07.665808 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11797 01:38:07.669235 No KMS driver or no outputs, pipes: 16, outputs: 0
11798 01:38:07.675927 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11799 01:38:07.679276 Using IGT_SRANDOM=1717551487 for randomisation
11800 01:38:07.684117 Opened device: /dev/dri/card0
11801 01:38:07.689043 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11802 01:38:07.692216 Test requirement: is_intel_device(fd)
11803 01:38:07.702525 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11804 01:38:07.705692 Test requirement: is_intel_device(fd)
11805 01:38:07.708890 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11806 01:38:07.712022 No KMS driver or no outputs, pipes: 16, outputs: 0
11807 01:38:07.719204 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11808 01:38:07.722854 Using IGT_SRANDOM=1717551487 for randomisation
11809 01:38:07.726235 Opened device: /dev/dri/card0
11810 01:38:07.735353 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11811 01:38:07.738984 Test requirement: is_intel_device(fd)
11812 01:38:07.745870 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11813 01:38:07.749098 Test requirement: is_intel_device(fd)
11814 01:38:07.752247 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11815 01:38:07.755634 No KMS driver or no outputs, pipes: 16, outputs: 0
11816 01:38:07.762532 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11817 01:38:07.768483 Using IGT_SRANDOM=1717551487 for randomisation
11818 01:38:07.769082 Opened device: /dev/dri/card0
11819 01:38:07.778431 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11820 01:38:07.781919 Test requirement: is_intel_device(fd)
11821 01:38:07.788515 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11822 01:38:07.792019 Test requirement: is_intel_device(fd)
11823 01:38:07.797796 No KMS driver or no outputs, pipes: 16, outputs: 0
11824 01:38:07.798758 [1mSubtest size-max: SKIP (0.000s)[0m
11825 01:38:07.805176 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11826 01:38:07.811613 Using IGT_SRANDOM=1717551487 for randomisation
11827 01:38:07.812161 Opened device: /dev/dri/card0
11828 01:38:07.821933 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11829 01:38:07.825216 Test requirement: is_intel_device(fd)
11830 01:38:07.832336 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11831 01:38:07.834804 Test requirement: is_intel_device(fd)
11832 01:38:07.838284 No KMS driver or no outputs, pipes: 16, outputs: 0
11833 01:38:07.841282 [1mSubtest too-wide: SKIP (0.000s)[0m
11834 01:38:07.848326 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11835 01:38:07.851429 Using IGT_SRANDOM=1717551487 for randomisation
11836 01:38:07.855348 Opened device: /dev/dri/card0
11837 01:38:07.861379 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11838 01:38:07.865049 Test requirement: is_intel_device(fd)
11839 01:38:07.874945 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11840 01:38:07.878113 Test requirement: is_intel_device(fd)
11841 01:38:07.881292 No KMS driver or no outputs, pipes: 16, outputs: 0
11842 01:38:07.884808 [1mSubtest too-high: SKIP (0.000s)[0m
11843 01:38:07.891428 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11844 01:38:07.894588 Using IGT_SRANDOM=1717551487 for randomisation
11845 01:38:07.897584 Opened device: /dev/dri/card0
11846 01:38:07.904747 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11847 01:38:07.913542 Test requirement: is_inte<14>[ 15.829692] [IGT] kms_addfb_basic: exiting, ret=77
11848 01:38:07.918298 <8>[ 15.836604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11849 01:38:07.919207 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11851 01:38:07.921515 l_device(fd)
11852 01:38:07.928094 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11853 01:38:07.931200 Test requirement: is_intel_device(fd)
11854 01:38:07.934581 No KMS driver or no outputs, pipes: 16, outputs: 0
11855 01:38:07.941999 [1<14>[ 15.860767] [IGT] kms_addfb_basic: executing
11856 01:38:07.945075 mSubtest bo-too-small: SKIP (0.000s)[0m
11857 01:38:07.951439 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11858 01:38:07.955145 Using IGT_SRANDOM=1717551487 for randomisation
11859 01:38:07.957771 Opened device: /dev/dri/card0
11860 01:38:07.964844 Test requirement not met in fu<14>[ 15.880732] [IGT] kms_addfb_basic: exiting, ret=77
11861 01:38:07.971107 <8>[ 15.888267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11862 01:38:07.971982 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11864 01:38:07.977865 nction igt_require_intel, file ../lib/drmtest.c:880:
11865 01:38:07.984318 Test requirement: is_intel<14>[ 15.904378] [IGT] kms_addfb_basic: executing
11866 01:38:07.984907 _device(fd)
11867 01:38:07.991840 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11868 01:38:07.995705 Test requirement: is_intel_device(fd)
11869 01:38:08.001055 No KMS d<14>[ 15.917301] [IGT] kms_addfb_basic: exiting, ret=77
11870 01:38:08.011580 <8>[ 15.923436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11871 01:38:08.012510 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11873 01:38:08.013908 river or no outputs, pipes: 16, outputs: 0
11874 01:38:08.020458 [1mSubtest small-bo<14>[ 15.939098] [IGT] kms_addfb_basic: executing
11875 01:38:08.021103 : SKIP (0.000s)[0m
11876 01:38:08.030305 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-r<14>[ 15.951942] [IGT] kms_addfb_basic: exiting, ret=77
11877 01:38:08.040426 <8>[ 15.957630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11878 01:38:08.041038 t12 aarch64)
11879 01:38:08.041817 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11881 01:38:08.043907 Using IGT_SRANDOM=1717551487 for randomisation
11882 01:38:08.047718 Opened device: /dev/dri/card0
11883 01:38:08.054982 Tes<14>[ 15.970011] [IGT] kms_addfb_basic: executing
11884 01:38:08.060952 t requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11885 01:38:08.063801 <14>[ 15.982781] [IGT] kms_addfb_basic: exiting, ret=77
11886 01:38:08.074651 <8>[ 15.988508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11887 01:38:08.075224
11888 01:38:08.075998 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11890 01:38:08.077407 Test requirement: is_intel_device(fd)
11891 01:38:08.083636 Test requirement not met in function igt<14>[ 16.002470] [IGT] kms_addfb_basic: executing
11892 01:38:08.090894 _require_intel, file ../lib/drmtest.c:880:
11893 01:38:08.097173 Test requirement: is_intel_device(fd<14>[ 16.015201] [IGT] kms_addfb_basic: exiting, ret=77
11894 01:38:08.103661 <8>[ 16.020590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11895 01:38:08.104539 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11897 01:38:08.107444 )
11898 01:38:08.110513 No KMS driver or no outputs, pipes: 16, outputs: 0
11899 01:38:08.117457 [1mSubtest bo-too-small-<14>[ 16.033249] [IGT] kms_addfb_basic: executing
11900 01:38:08.120837 due-to-tiling: SKIP (0.000s)[0m
11901 01:38:08.130136 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<14>[ 16.046014] [IGT] kms_addfb_basic: exiting, ret=77
11902 01:38:08.136576 <8>[ 16.051821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11903 01:38:08.137513 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11905 01:38:08.140106 <8>[ 16.053284] <LAVA_SIGNAL_TESTSET STOP>
11906 01:38:08.140854 Received signal: <TESTSET> STOP
11907 01:38:08.141311 Closing test_set kms_addfb_basic
11908 01:38:08.143236 .1.92-cip22-rt12 aarch64)
11909 01:38:08.146654 Using IGT_SRANDOM=1717551488 for randomisation
11910 01:38:08.153938 Opene<8>[ 16.070971] <LAVA_SIGNAL_TESTSET START kms_atomic>
11911 01:38:08.154510 d device: /dev/dri/card0
11912 01:38:08.155157 Received signal: <TESTSET> START kms_atomic
11913 01:38:08.155539 Starting test_set kms_atomic
11914 01:38:08.163560 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11915 01:38:08.167169 Test requirement: <14>[ 16.085071] [IGT] kms_atomic: executing
11916 01:38:08.173379 <14>[ 16.085564] [IGT] kms_atomic: exiting, ret=77
11917 01:38:08.180348 <8>[ 16.090840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11918 01:38:08.181235 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11920 01:38:08.183551 is_intel_device(fd)
11921 01:38:08.190530 Test requirement not met in<14>[ 16.106203] [IGT] kms_atomic: executing
11922 01:38:08.193940 <14>[ 16.106683] [IGT] kms_atomic: exiting, ret=77
11923 01:38:08.201254 <8>[ 16.112195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11924 01:38:08.202093 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11926 01:38:08.206707 function igt_require_intel, fil<14>[ 16.126958] [IGT] kms_atomic: executing
11927 01:38:08.214012 <14>[ 16.127407] [IGT] kms_atomic: exiting, ret=77
11928 01:38:08.220549 <8>[ 16.134148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11929 01:38:08.221449 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11931 01:38:08.223147 e ../lib/drmtest.c:880:
11932 01:38:08.230194 Test re<14>[ 16.147550] [IGT] kms_atomic: executing
11933 01:38:08.233923 <14>[ 16.147985] [IGT] kms_atomic: exiting, ret=77
11934 01:38:08.240682 <8>[ 16.154368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11935 01:38:08.241572 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11937 01:38:08.243041 quirement: is_intel_device(fd)
11938 01:38:08.246817 <14>[ 16.167192] [IGT] kms_atomic: executing
11939 01:38:08.253193 <14>[ 16.167606] [IGT] kms_atomic: exiting, ret=77
11940 01:38:08.259732 <8>[ 16.172693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11941 01:38:08.260623 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11943 01:38:08.266066 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 16.185501] [IGT] kms_atomic: executing
11944 01:38:08.273194 <14>[ 16.185938] [IGT] kms_atomic: exiting, ret=77
11945 01:38:08.279562 <8>[ 16.190956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11946 01:38:08.280155 0
11947 01:38:08.281015 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11949 01:38:08.289483 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.<14>[ 16.206048] [IGT] kms_atomic: executing
11950 01:38:08.293512 <14>[ 16.206475] [IGT] kms_atomic: exiting, ret=77
11951 01:38:08.299797 <8>[ 16.212489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11952 01:38:08.300476 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11954 01:38:08.302882 000s)[0m
11955 01:38:08.305946 IGT-Version: 1.28-ga4<14>[ 16.226825] [IGT] kms_atomic: executing
11956 01:38:08.313165 <14>[ 16.227259] [IGT] kms_atomic: exiting, ret=77
11957 01:38:08.320221 <8>[ 16.231301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11958 01:38:08.320898 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11960 01:38:08.326401 4ebfe (aarch64) (Linux: 6.1.92-c<14>[ 16.246720] [IGT] kms_atomic: executing
11961 01:38:08.332391 <14>[ 16.247145] [IGT] kms_atomic: exiting, ret=77
11962 01:38:08.339272 <8>[ 16.252163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11963 01:38:08.340095 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11965 01:38:08.342761 ip22-rt12 aarch64)
11966 01:38:08.349439 Using IGT_SRANDOM=1717551488<14>[ 16.266001] [IGT] kms_atomic: executing
11967 01:38:08.352257 <14>[ 16.266401] [IGT] kms_atomic: exiting, ret=77
11968 01:38:08.362658 <8>[ 16.272685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11969 01:38:08.363244 for randomisation
11970 01:38:08.363989 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11972 01:38:08.365844 Opened device: /dev/dri/card0
11973 01:38:08.372529 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11974 01:38:08.379274 Test requirement: is_inte<14>[ 16.299417] [IGT] kms_atomic: executing
11975 01:38:08.382188 <14>[ 16.300021] [IGT] kms_atomic: exiting, ret=77
11976 01:38:08.392502 <8>[ 16.305212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11977 01:38:08.392933 l_device(fd)
11978 01:38:08.393572 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11980 01:38:08.398591 Test requirement not met in functi<14>[ 16.317752] [IGT] kms_atomic: executing
11981 01:38:08.405734 on igt_require_intel, file ../lib/drmtest.c:880:
11982 01:38:08.408865 Test requirement: is_intel_device(fd)
11983 01:38:08.412083 No KMS driver or no outputs, pipes: 16, outputs: 0
11984 01:38:08.418764 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11985 01:38:08.422266 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11986 01:38:08.429086 Using IGT_SRANDOM=1717551488 for randomisation
11987 01:38:08.432123 Opened device: /dev/dri/card0
11988 01:38:08.438273 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11989 01:38:08.441778 Test requirement: is_intel_device(fd)
11990 01:38:08.449498 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11991 01:38:08.452024 Test requirement: is_intel_device(fd)
11992 01:38:08.455435 No KMS driver or no outputs, pipes: 16, outputs: 0
11993 01:38:08.461711 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11994 01:38:08.469084 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
11995 01:38:08.472282 Using IGT_SRANDOM=1717551488 for randomisation
11996 01:38:08.474820 Opened device: /dev/dri/card0
11997 01:38:08.481609 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11998 01:38:08.484675 Test requirement: is_intel_device(fd)
11999 01:38:08.492408 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12000 01:38:08.495642 Test requirement: is_intel_device(fd)
12001 01:38:08.501548 No KMS driver or no outputs, pipes: 16, outputs: 0
12002 01:38:08.505080 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12003 01:38:08.512039 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12004 01:38:08.515032 Using IGT_SRANDOM=1717551488 for randomisation
12005 01:38:08.517416 Opened device: /dev/dri/card0
12006 01:38:08.521143 No KMS driver or no outputs, pipes: 16, outputs: 0
12007 01:38:08.527792 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12008 01:38:08.534376 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12009 01:38:08.537632 Using IGT_SRANDOM=1717551488 for randomisation
12010 01:38:08.540753 Opened device: /dev/dri/card0
12011 01:38:08.544684 No KMS driver or no outputs, pipes: 16, outputs: 0
12012 01:38:08.551009 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12013 01:38:08.554125 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12014 01:38:08.561216 Using IGT_SRANDOM=1717551488 for randomisation
12015 01:38:08.561770 Opened device: /dev/dri/card0
12016 01:38:08.567678 No KMS driver or no outputs, pipes: 16, outputs: 0
12017 01:38:08.574249 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12018 01:38:08.580713 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12019 01:38:08.584378 Using IGT_SRANDOM=1717551488 for randomisation
12020 01:38:08.587036 Opened device: /dev/dri/card0
12021 01:38:08.591435 No KMS driver or no outputs, pipes: 16, outputs: 0
12022 01:38:08.593508 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12023 01:38:08.601277 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12024 01:38:08.607568 Using IGT_SRANDOM=1717551488 for randomisation
12025 01:38:08.608198 Opened device: /dev/dri/card0
12026 01:38:08.613774 No KMS driver or no outputs, pipes: 16, outputs: 0
12027 01:38:08.617196 [1mSubtest test-only: SKIP (0.000s)[0m
12028 01:38:08.624792 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12029 01:38:08.627591 Using IGT_SRANDOM=1717551488 for randomisation
12030 01:38:08.630966 Opened device: /dev/dri/card0
12031 01:38:08.634311 No KMS driver or no outputs, pipes: 16, outputs: 0
12032 01:38:08.640219 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12033 01:38:08.644232 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12034 01:38:08.650914 Using IGT_SRANDOM=1717551488 for randomisation
12035 01:38:08.651465 Opened device: /dev/dri/card0
12036 01:38:08.656961 No KMS driver or no outputs, pipes: 16, outputs: 0
12037 01:38:08.660105 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12038 01:38:08.667022 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12039 01:38:08.670271 Using IGT_SRANDOM=1717551488 for randomisation
12040 01:38:08.674033 Opened device: /dev/dri/card0
12041 01:38:08.680181 No KMS driver or no outputs, pipes: 16, outputs: 0
12042 01:38:08.683461 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12043 01:38:08.690502 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12044 01:38:08.693337 Using IGT_SRANDOM=1717551488 for randomisation
12045 01:38:08.696573 Opened device: /dev/dri/card0
12046 01:38:08.700166 No KMS driver or no outputs, pipes: 16, outputs: 0
12047 01:38:08.707810 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12048 01:38:08.712888 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12049 01:38:08.717081 Using IGT_SRANDOM=1717551488 for randomisation
12050 01:38:08.720362 Opened device: /dev/dri/card0
12051 01:38:08.723474 No KMS driver or no outputs, pipes: 16, outputs: 0
12052 01:38:08.729705 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12053 01:38:08.736736 IGT-Version: 1.28-ga44ebfe (aarch64)<14>[ 16.656001] [IGT] kms_atomic: exiting, ret=77
12054 01:38:08.743781 <8>[ 16.662360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12055 01:38:08.744543 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12057 01:38:08.749549 <8>[ 16.663600] <LAVA_SIGNAL_TESTSET STOP>
12058 01:38:08.750398 Received signal: <TESTSET> STOP
12059 01:38:08.750790 Closing test_set kms_atomic
12060 01:38:08.753229 (Linux: 6.1.92-cip22-rt12 aarch64)
12061 01:38:08.759418 Using IGT_SRANDOM=1717551488 for randomisat<8>[ 16.679546] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12062 01:38:08.760250 Received signal: <TESTSET> START kms_flip_event_leak
12063 01:38:08.760643 Starting test_set kms_flip_event_leak
12064 01:38:08.763473 ion
12065 01:38:08.764028 Opened device: /dev/dri/card0
12066 01:38:08.769277 No KMS driver or no outputs, pipes: 16, outputs: 0
12067 01:38:08.776428 [1mSubtest atomic-invalid-params: SKIP <14>[ 16.693887] [IGT] kms_flip_event_leak: executing
12068 01:38:08.783137 <14>[ 16.694341] [IGT] kms_flip_event_leak: exiting, ret=77
12069 01:38:08.789125 <8>[ 16.698767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12070 01:38:08.789967 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12072 01:38:08.792411 <8>[ 16.701604] <LAVA_SIGNAL_TESTSET STOP>
12073 01:38:08.793292 Received signal: <TESTSET> STOP
12074 01:38:08.793696 Closing test_set kms_flip_event_leak
12075 01:38:08.799849 <8>[ 16.718394] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12076 01:38:08.800420 (0.000s)[0m
12077 01:38:08.801100 Received signal: <TESTSET> START kms_prop_blob
12078 01:38:08.801484 Starting test_set kms_prop_blob
12079 01:38:08.806389 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12080 01:38:08.812338 Using IGT<14>[ 16.730717] [IGT] kms_prop_blob: executing
12081 01:38:08.815826 <14>[ 16.731033] [IGT] kms_prop_blob: starting subtest basic
12082 01:38:08.822936 <14>[ 16.731087] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12083 01:38:08.829238 <14>[ 16.731169] [IGT] kms_prop_blob: exiting, ret=0
12084 01:38:08.836333 <8>[ 16.737338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12085 01:38:08.837170 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12087 01:38:08.839093 <14>[ 16.754190] [IGT] kms_prop_blob: executing
12088 01:38:08.842174 _SRANDOM=1717551488 for randomisation
12089 01:38:08.849708 Opened de<14>[ 16.765173] [IGT] kms_prop_blob: starting subtest blob-prop-core
12090 01:38:08.856000 <14>[ 16.765225] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12091 01:38:08.862485 <14>[ 16.765296] [IGT] kms_prop_blob: exiting, ret=0
12092 01:38:08.869529 <8>[ 16.770741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12093 01:38:08.870083 vice: /dev/dri/card0
12094 01:38:08.870731 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12096 01:38:08.875898 No KMS dri<14>[ 16.794690] [IGT] kms_prop_blob: executing
12097 01:38:08.882586 <14>[ 16.794989] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12098 01:38:08.889907 <14>[ 16.795090] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12099 01:38:08.895766 <14>[ 16.795162] [IGT] kms_prop_blob: exiting, ret=0
12100 01:38:08.902780 <8>[ 16.800420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12101 01:38:08.903627 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12103 01:38:08.909085 ver or no output<14>[ 16.828531] [IGT] kms_prop_blob: executing
12104 01:38:08.909659 s, pipes: 16, outputs: 0
12105 01:38:08.919850 [1mSu<14>[ 16.834664] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12106 01:38:08.925533 <14>[ 16.834778] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12107 01:38:08.929298 <14>[ 16.834826] [IGT] kms_prop_blob: exiting, ret=0
12108 01:38:08.939839 <8>[ 16.840854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12109 01:38:08.940683 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12111 01:38:08.942718 <14>[ 16.856211] [IGT] kms_prop_blob: executing
12112 01:38:08.948953 btest atomic-pla<14>[ 16.868316] [IGT] kms_prop_blob: starting subtest blob-multiple
12113 01:38:08.955518 <14>[ 16.868467] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12114 01:38:08.962562 <14>[ 16.868517] [IGT] kms_prop_blob: exiting, ret=0
12115 01:38:08.969097 <8>[ 16.873648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12116 01:38:08.969958 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12118 01:38:08.971946 <14>[ 16.887726] [IGT] kms_prop_blob: executing
12119 01:38:08.975873 ne-damage: SKIP (0.000s)[0m
12120 01:38:08.983889 IG<14>[ 16.899405] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12121 01:38:08.992378 <14>[ 16.899452] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12122 01:38:08.995579 <14>[ 16.899530] [IGT] kms_prop_blob: exiting, ret=0
12123 01:38:09.002236 <8>[ 16.904389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12124 01:38:09.003076 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12126 01:38:09.011925 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.9<14>[ 16.929097] [IGT] kms_prop_blob: executing
12127 01:38:09.018019 <14>[ 16.929441] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12128 01:38:09.024916 <14>[ 16.929489] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12129 01:38:09.032501 <14>[ 16.929558] [IGT] kms_prop_blob: exiting, ret=0
12130 01:38:09.038300 <8>[ 16.935412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12131 01:38:09.039144 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12133 01:38:09.041960 <14>[ 16.951576] [IGT] kms_prop_blob: executing
12134 01:38:09.052056 2-cip22-rt12 aar<14>[ 16.968376] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12135 01:38:09.058096 <14>[ 16.968423] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12136 01:38:09.064656 <14>[ 16.968493] [IGT] kms_prop_blob: exiting, ret=0
12137 01:38:09.071359 <8>[ 16.973565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12138 01:38:09.071925 ch64)
12139 01:38:09.072574 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12141 01:38:09.075003 Using IGT<14>[ 16.996674] [IGT] kms_prop_blob: executing
12142 01:38:09.084583 _SRANDOM=1717551488 for randomis<14>[ 17.002569] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12143 01:38:09.091408 <14>[ 17.002648] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12144 01:38:09.098363 <14>[ 17.002718] [IGT] kms_prop_blob: exiting, ret=0
12145 01:38:09.104772 <8>[ 17.007780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12146 01:38:09.105668 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12148 01:38:09.108086 <8>[ 17.009777] <LAVA_SIGNAL_TESTSET STOP>
12149 01:38:09.108924 Received signal: <TESTSET> STOP
12150 01:38:09.109362 Closing test_set kms_prop_blob
12151 01:38:09.114540 <8>[ 17.025237] <LAVA_SIGNAL_TESTSET START kms_setmode>
12152 01:38:09.115117 ation
12153 01:38:09.115764 Received signal: <TESTSET> START kms_setmode
12154 01:38:09.116149 Starting test_set kms_setmode
12155 01:38:09.117787 Opened device: /dev/dri/card0
12156 01:38:09.121440 No KMS driver or no outputs, pipes: 16, outputs: 0
12157 01:38:09.125781 [1mSubtest basic: SKIP (0.000s)[0m
12158 01:38:09.135239 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 a<14>[ 17.053469] [IGT] kms_setmode: executing
12159 01:38:09.141679 <14>[ 17.053977] [IGT] kms_setmode: starting subtest basic
12160 01:38:09.148705 <14>[ 17.054053] [IGT] kms_setmode: finished subtest basic, SKIP
12161 01:38:09.151652 <14>[ 17.054151] [IGT] kms_setmode: exiting, ret=77
12162 01:38:09.157539 <8>[ 17.059529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12163 01:38:09.158102 arch64)
12164 01:38:09.158757 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12166 01:38:09.164454 Using IGT_SRANDOM=1717551488 for randomisation
12167 01:38:09.167901 Opened <14>[ 17.088085] [IGT] kms_setmode: executing
12168 01:38:09.175215 <14>[ 17.088588] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12169 01:38:09.184439 device: /dev/dri<14>[ 17.088663] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12170 01:38:09.185268 /card0
12171 01:38:09.191327 Starting<14>[ 17.089462] [IGT] kms_setmode: exiting, ret=77
12172 01:38:09.197968 <8>[ 17.105290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12173 01:38:09.198537 subtest: basic
12174 01:38:09.199189 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12176 01:38:09.204449 [1mSubtest basic: SUCCESS (0.000s)[0m
12177 01:38:09.210866 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<14>[ 17.130773] [IGT] kms_setmode: executing
12178 01:38:09.217158 <14>[ 17.131327] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12179 01:38:09.227559 <14>[ 17.131415] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12180 01:38:09.231045 <14>[ 17.131536] [IGT] kms_setmode: exiting, ret=77
12181 01:38:09.237639 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12183 01:38:09.240902 <8>[ 17.136535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12184 01:38:09.244165 <14>[ 17.157247] [IGT] kms_setmode: executing
12185 01:38:09.244726 p22-rt12 aarch64)
12186 01:38:09.254612 Using IGT_SRANDOM=1717551488 <14>[ 17.169833] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12187 01:38:09.264691 <14>[ 17.169875] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12188 01:38:09.267038 <14>[ 17.169930] [IGT] kms_setmode: exiting, ret=77
12189 01:38:09.277071 <8>[ 17.175264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12190 01:38:09.277663 for randomisation
12191 01:38:09.278313 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12193 01:38:09.284006 Opened device<14>[ 17.202297] [IGT] kms_setmode: executing
12194 01:38:09.290472 <14>[ 17.202637] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12195 01:38:09.296722 <14>[ 17.202677] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12196 01:38:09.297306 : /dev/dri/card0
12197 01:38:09.303813 Starting subte<14>[ 17.202733] [IGT] kms_setmode: exiting, ret=77
12198 01:38:09.314491 <8>[ 17.207826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12199 01:38:09.315383 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12201 01:38:09.316775 <14>[ 17.223314] [IGT] kms_setmode: executing
12202 01:38:09.323932 <14>[ 17.223668] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12203 01:38:09.333566 <14>[ 17.223716] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12204 01:38:09.337379 <14>[ 17.223784] [IGT] kms_setmode: exiting, ret=77
12205 01:38:09.346853 <8>[ 17.229662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12206 01:38:09.347675 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12208 01:38:09.350838 <8>[ 17.231040] <LAVA_SIGNAL_TESTSET STOP>
12209 01:38:09.351678 Received signal: <TESTSET> STOP
12210 01:38:09.352071 Closing test_set kms_setmode
12211 01:38:09.356736 <8>[ 17.261595] <LAVA_SIGNAL_TESTSET START kms_vblank>
12212 01:38:09.357232 st: blob-prop-core
12213 01:38:09.357860 Received signal: <TESTSET> START kms_vblank
12214 01:38:09.358253 Starting test_set kms_vblank
12215 01:38:09.364110 [1mSubtest blob-prop-core: <14>[ 17.281834] [IGT] kms_vblank: executing
12216 01:38:09.370206 <14>[ 17.282238] [IGT] kms_vblank: exiting, ret=77
12217 01:38:09.374484 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12219 01:38:09.376544 <8>[ 17.287498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12220 01:38:09.377032 SUCCESS (0.000s)[0m
12221 01:38:09.383769 IGT-Version: 1.28-ga44ebfe<14>[ 17.301470] [IGT] kms_vblank: executing
12222 01:38:09.386778 <14>[ 17.301894] [IGT] kms_vblank: exiting, ret=77
12223 01:38:09.393329 <8>[ 17.307580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12224 01:38:09.394165 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12226 01:38:09.400361 (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12227 01:38:09.403793 U<14>[ 17.321093] [IGT] kms_vblank: executing
12228 01:38:09.406560 <14>[ 17.321514] [IGT] kms_vblank: exiting, ret=77
12229 01:38:09.413397 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12231 01:38:09.416952 <8>[ 17.327414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12232 01:38:09.419730 sing IGT_SRANDOM=1717551488 for randomisation
12233 01:38:09.424669 O<14>[ 17.341256] [IGT] kms_vblank: executing
12234 01:38:09.426805 pened device: /dev/dri/card0
12235 01:38:09.430684 Starting subtest: blob-prop-validate
12236 01:38:09.433361 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12237 01:38:09.439878 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12238 01:38:09.443229 Using IGT_SRANDOM=1717551488 for randomisation
12239 01:38:09.447464 Opened device: /dev/dri/card0
12240 01:38:09.450204 Starting subtest: blob-prop-lifetime
12241 01:38:09.456572 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12242 01:38:09.460028 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12243 01:38:09.466600 Using IGT_SRANDOM=1717551488 for randomisation
12244 01:38:09.470019 Opened device: /dev/dri/card0
12245 01:38:09.470580 Starting subtest: blob-multiple
12246 01:38:09.476267 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12247 01:38:09.483058 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12248 01:38:09.487318 Using IGT_SRANDOM=1717551488 for randomisation
12249 01:38:09.489700 Opened device: /dev/dri/card0
12250 01:38:09.492733 Starting subtest: invalid-get-prop-any
12251 01:38:09.496459 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12252 01:38:09.503115 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12253 01:38:09.506259 Using IGT_SRANDOM=1717551489 for randomisation
12254 01:38:09.509533 Opened device: /dev/dri/card0
12255 01:38:09.512906 Starting subtest: invalid-get-prop
12256 01:38:09.516564 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12257 01:38:09.522996 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12258 01:38:09.529591 Using IGT_SRANDOM=1717551489 for randomisation
12259 01:38:09.530144 Opened device: /dev/dri/card0
12260 01:38:09.532636 Starting subtest: invalid-set-prop-any
12261 01:38:09.540184 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12262 01:38:09.546686 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12263 01:38:09.549245 Using IGT_SRANDOM=1717551489 for randomisation
12264 01:38:09.552627 Opened device: /dev/dri/card0
12265 01:38:09.556020 Starting subtest: invalid-set-prop
12266 01:38:09.559866 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12267 01:38:09.565779 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12268 01:38:09.569515 Using IGT_SRANDOM=1717551489 for randomisation
12269 01:38:09.572740 Opened device: /dev/dri/card0
12270 01:38:09.576123 Starting subtest: basic
12271 01:38:09.579588 No dynamic tests executed.
12272 01:38:09.582901 [1mSubtest basic: SKIP (0.000s)[0m
12273 01:38:09.589095 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12274 01:38:09.592315 Using IGT_SRANDOM=1717551489 for randomisation
12275 01:38:09.595998 Opened device: /dev/dri/card0
12276 01:38:09.599460 Starting subtest: basic-clone-single-crtc
12277 01:38:09.600026 No dynamic tests executed.
12278 01:38:09.605512 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12279 01:38:09.612263 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12280 01:38:09.616147 Using IGT_SRANDOM=1717551489 for randomisation
12281 01:38:09.619425 Opened device: /dev/dri/card0
12282 01:38:09.622537 Starting subtest: invalid-clone-single-crtc
12283 01:38:09.627088 No dynamic tests executed.
12284 01:38:09.629854 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12285 01:38:09.635510 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12286 01:38:09.639014 Using IGT_SRANDOM=1717551489 for randomisation
12287 01:38:09.642379 Opened device: /dev/dri/card0
12288 01:38:09.646490 Starting subtest: invalid-clone-exclusive-crtc
12289 01:38:09.649190 No dynamic tests executed.
12290 01:38:09.656080 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12291 01:38:09.662377 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12292 01:38:09.666272 Using IGT_SRANDOM=1717551489 for randomisation
12293 01:38:09.669044 Opened device: /dev/dri/card0
12294 01:38:09.672051 Starting subtest: clone-exclusive-crtc
12295 01:38:09.675825 No dynamic tests executed.
12296 01:38:09.678800 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12297 01:38:09.685922 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12298 01:38:09.688904 Using IGT_SRANDOM=1717551489 for randomisation
12299 01:38:09.692371 Opened device: /dev/dri/card0
12300 01:38:09.695968 Starting subtest: invalid-clone-single-crtc-stealing
12301 01:38:09.699035 No dynamic tests executed.
12302 01:38:09.705670 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12303 01:38:09.712232 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12304 01:38:09.715835 Using IGT_SRANDOM=1717551489 for randomisation
12305 01:38:09.719479 Opened device: /dev/dri/card0
12306 01:38:09.722450 No KMS driver or no outputs, pipes: 16, outputs: 0
12307 01:38:09.725238 [1mSubtest invalid: SKIP (0.000s)[0m
12308 01:38:09.731927 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12309 01:38:09.735694 Using IGT_SRANDOM=1717551489 for randomisation
12310 01:38:09.738457 Opened device: /dev/dri/card0
12311 01:38:09.745231 No KMS driver or no outputs, pipes: 16, outputs: 0
12312 01:38:09.748888 [1mSubtest crtc-id: SKIP (0.000s)[0m
12313 01:38:09.755378 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12314 01:38:09.758395 Using IGT_SRANDOM=1<14>[ 17.679608] [IGT] kms_vblank: exiting, ret=77
12315 01:38:09.761569 717551489 for randomisation
12316 01:38:09.769423 Ope<8>[ 17.688580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12317 01:38:09.770277 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12319 01:38:09.772364 ned device: /dev/dri/card0
12320 01:38:09.776715 No KMS driver or no outputs, pipes: 16, outputs: 0
12321 01:38:09.785440 [1mSubtest accuracy-idle: SKIP <14>[ 17.702912] [IGT] kms_vblank: executing
12322 01:38:09.790384 <14>[ 17.703375] [IGT] kms_vblank: exiting, ret=77
12323 01:38:09.794943 <8>[ 17.709768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12324 01:38:09.795790 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12326 01:38:09.798426 (0.000s)[0m
12327 01:38:09.805406 IGT-Version: 1.28-ga44ebfe (aarch6<14>[ 17.722742] [IGT] kms_vblank: executing
12328 01:38:09.808659 <14>[ 17.723198] [IGT] kms_vblank: exiting, ret=77
12329 01:38:09.815652 <8>[ 17.731534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12330 01:38:09.816493 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12332 01:38:09.818252 4) (Linux: 6.1.92-cip22-rt12 aarch64)
12333 01:38:09.825890 Using IGT_SRANDOM=1717551489 for randomisation
12334 01:38:09.828506 Opened de<14>[ 17.744964] [IGT] kms_vblank: executing
12335 01:38:09.831660 <14>[ 17.745438] [IGT] kms_vblank: exiting, ret=77
12336 01:38:09.842459 <8>[ 17.751043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12337 01:38:09.843027 vice: /dev/dri/card0
12338 01:38:09.843679 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12340 01:38:09.848478 No KMS driver or no outputs, pipes: 16, outputs: 0
12341 01:38:09.851513 [1mSubtest query-idle: SKIP (0.000s)[0m
12342 01:38:09.854784 IGT-Version<14>[ 17.775205] [IGT] kms_vblank: executing
12343 01:38:09.861433 <14>[ 17.775885] [IGT] kms_vblank: exiting, ret=77
12344 01:38:09.867739 <8>[ 17.781897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12345 01:38:09.868561 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12347 01:38:09.870752 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12348 01:38:09.877733 Using IGT_SRANDOM=1717551489 for randomisation
12349 01:38:09.881297 Opened device: /dev/dri/card0
12350 01:38:09.884455 No <14>[ 17.803593] [IGT] kms_vblank: executing
12351 01:38:09.888375 <14>[ 17.804213] [IGT] kms_vblank: exiting, ret=77
12352 01:38:09.895417 <8>[ 17.810196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12353 01:38:09.896263 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12355 01:38:09.901865 KMS driver or no outputs, pipes: 16, outputs: 0
12356 01:38:09.904574 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12357 01:38:09.911097 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12358 01:38:09.914974 Using <14>[ 17.834013] [IGT] kms_vblank: executing
12359 01:38:09.921178 <14>[ 17.834687] [IGT] kms_vblank: exiting, ret=77
12360 01:38:09.927622 <8>[ 17.840335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12361 01:38:09.928362 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12363 01:38:09.930500 IGT_SRANDOM=1717551489 for randomisation
12364 01:38:09.933941 Opened device: /dev/dri/card0
12365 01:38:09.937543 No KMS driver or no outputs, pipes: 16, outputs: 0
12366 01:38:09.943690 [1mSubtest query-f<14>[ 17.861891] [IGT] kms_vblank: executing
12367 01:38:09.947439 <14>[ 17.862500] [IGT] kms_vblank: exiting, ret=77
12368 01:38:09.957581 <8>[ 17.867727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12369 01:38:09.958154 orked: SKIP (0.000s)[0m
12370 01:38:09.958812 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12372 01:38:09.963645 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12373 01:38:09.970430 Using IGT_SRANDOM=1717551489 <14>[ 17.889914] [IGT] kms_vblank: executing
12374 01:38:09.977353 <14>[ 17.890552] [IGT] kms_vblank: exiting, ret=77
12375 01:38:09.983671 <8>[ 17.896458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12376 01:38:09.984237 for randomisation
12377 01:38:09.984888 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12379 01:38:09.990942 Opened device: /dev/dri/card0<14>[ 17.910315] [IGT] kms_vblank: executing
12380 01:38:09.996926 <14>[ 17.910768] [IGT] kms_vblank: exiting, ret=77
12381 01:38:10.003580 <8>[ 17.915444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12382 01:38:10.004147
12383 01:38:10.004794 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12385 01:38:10.007828 No KMS driver or no outputs, pipes: 16, outputs: 0
12386 01:38:10.013391 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12387 01:38:10.020126 IGT-Version: 1.28-ga44eb<14>[ 17.940137] [IGT] kms_vblank: executing
12388 01:38:10.023537 fe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12389 01:38:10.026931 <14>[ 17.945277] [IGT] kms_vblank: exiting, ret=77
12390 01:38:10.033155 <8>[ 17.950262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12391 01:38:10.033721
12392 01:38:10.034371 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12394 01:38:10.040125 Using IGT_SRANDOM=1717551489 for randomisation
12395 01:38:10.043586 <14>[ 17.962435] [IGT] kms_vblank: executing
12396 01:38:10.046643 <14>[ 17.962865] [IGT] kms_vblank: exiting, ret=77
12397 01:38:10.047222
12398 01:38:10.057661 Opened device: <8>[ 17.968421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12399 01:38:10.058227 /dev/dri/card0
12400 01:38:10.058873 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12402 01:38:10.064858 No KMS driver or no outputs, pipes: 16, outputs: 0
12403 01:38:10.067206 [1mSubtest query-busy: SKIP (0.000s)[0m
12404 01:38:10.070632 IGT-Version: 1.28<14>[ 17.992628] [IGT] kms_vblank: executing
12405 01:38:10.080249 -ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aa<14>[ 17.998399] [IGT] kms_vblank: exiting, ret=77
12406 01:38:10.087354 <8>[ 18.002980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12407 01:38:10.087918 rch64)
12408 01:38:10.088567 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12410 01:38:10.093635 Using IGT_SRANDOM=1717551489 for randomisation
12411 01:38:10.094195 Opened device: /dev/dri/card0
12412 01:38:10.100569 No KMS driver or no outputs, pipes: 16, outputs: 0
12413 01:38:10.103780 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12414 01:38:10.110524 IGT-Version: 1.28-ga44ebfe (aarch64) <14>[ 18.032441] [IGT] kms_vblank: executing
12415 01:38:10.112883 (Linux: 6.1.92-cip22-rt12 aarch64)
12416 01:38:10.119791 Using IGT_SR<14>[ 18.037722] [IGT] kms_vblank: exiting, ret=77
12417 01:38:10.127722 <8>[ 18.044749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12418 01:38:10.128568 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12420 01:38:10.129775 ANDOM=1717551489 for randomisation
12421 01:38:10.136783 Opened devic<14>[ 18.056345] [IGT] kms_vblank: executing
12422 01:38:10.140029 <14>[ 18.056806] [IGT] kms_vblank: exiting, ret=77
12423 01:38:10.147356 <8>[ 18.063441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12424 01:38:10.148101 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12426 01:38:10.150031 e: /dev/dri/card0
12427 01:38:10.157007 No KMS driver or no outputs, <14>[ 18.076456] [IGT] kms_vblank: executing
12428 01:38:10.157543 pipes: 16, outputs: 0
12429 01:38:10.163385 [1mSubtest query-forked-<14>[ 18.082168] [IGT] kms_vblank: exiting, ret=77
12430 01:38:10.173379 <8>[ 18.088805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12431 01:38:10.173950 busy: SKIP (0.000s)[0m
12432 01:38:10.174605 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12434 01:38:10.180335 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12435 01:38:10.186501 Using IGT_SRANDOM=1717551489 for randomisation
12436 01:38:10.187191 Opened device: /dev/dri/card0
12437 01:38:10.196551 No KMS driver or no outputs, pipes: 16, outputs<14>[ 18.113182] [IGT] kms_vblank: executing
12438 01:38:10.199733 <14>[ 18.113816] [IGT] kms_vblank: exiting, ret=77
12439 01:38:10.209768 <8>[ 18.119944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12440 01:38:10.210358 : 0
12441 01:38:10.211014 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12443 01:38:10.216910 [1mSubtest query-forked-bu<14>[ 18.134831] [IGT] kms_vblank: executing
12444 01:38:10.219832 <14>[ 18.135278] [IGT] kms_vblank: exiting, ret=77
12445 01:38:10.229737 <8>[ 18.141662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12446 01:38:10.230299 sy-hang: SKIP (0.000s)[0m
12447 01:38:10.230951 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12449 01:38:10.236294 IGT-<14>[ 18.155044] [IGT] kms_vblank: executing
12450 01:38:10.239613 <14>[ 18.155479] [IGT] kms_vblank: exiting, ret=77
12451 01:38:10.249390 <8>[ 18.161855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12452 01:38:10.250214 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12454 01:38:10.256251 Version: 1.28-ga44ebfe (aarch64)<14>[ 18.174422] [IGT] kms_vblank: executing
12455 01:38:10.259710 <14>[ 18.174835] [IGT] kms_vblank: exiting, ret=77
12456 01:38:10.269459 <8>[ 18.180184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12457 01:38:10.270301 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12459 01:38:10.272609 (Linux: 6.1.92-cip22-rt12 aarch64)
12460 01:38:10.276299 Using IGT_SRANDOM=1717551489 for randomisation
12461 01:38:10.279539 Opened device: /dev/dri/card0
12462 01:38:10.283283 No KMS drive<14>[ 18.204222] [IGT] kms_vblank: executing
12463 01:38:10.286157 r or no outputs, pipes: 16, outputs: 0
12464 01:38:10.293012 [1mSubt<14>[ 18.209935] [IGT] kms_vblank: exiting, ret=77
12465 01:38:10.299671 <8>[ 18.218536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12466 01:38:10.300516 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12468 01:38:10.302654 est wait-idle: SKIP (0.000s)[0m
12469 01:38:10.313009 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<14>[ 18.230866] [IGT] kms_vblank: executing
12470 01:38:10.315675 <14>[ 18.231298] [IGT] kms_vblank: exiting, ret=77
12471 01:38:10.322407 <8>[ 18.236257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12472 01:38:10.323258 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12474 01:38:10.325641 .1.92-cip22-rt12 aarch64)
12475 01:38:10.329574 Using IGT_SRANDOM=1717551489 for randomisation
12476 01:38:10.332622 Opened device: /dev/dri/card0
12477 01:38:10.339472 No KMS driver or no outputs, pipes: 16, outputs: 0
12478 01:38:10.342281 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12479 01:38:10.349208 IGT-Version: 1.28-g<14>[ 18.266782] [IGT] kms_vblank: executing
12480 01:38:10.352630 <14>[ 18.267418] [IGT] kms_vblank: exiting, ret=77
12481 01:38:10.359834 <8>[ 18.273108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12482 01:38:10.360705 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12484 01:38:10.368968 a44ebfe (aarch64) (Linux: 6.1.92<14>[ 18.287055] [IGT] kms_vblank: executing
12485 01:38:10.372388 <14>[ 18.287469] [IGT] kms_vblank: exiting, ret=77
12486 01:38:10.380353 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12488 01:38:10.382045 <8>[ 18.292862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12489 01:38:10.386124 <8>[ 18.294853] <LAVA_SIGNAL_TESTSET STOP>
12490 01:38:10.386682 -cip22-rt12 aarch64)
12491 01:38:10.387366 Received signal: <TESTSET> STOP
12492 01:38:10.387754 Closing test_set kms_vblank
12493 01:38:10.395859 Using IGT_<8>[ 18.311058] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14173506_1.5.2.3.1>
12494 01:38:10.396536 Received signal: <ENDRUN> 0_igt-kms-mediatek 14173506_1.5.2.3.1
12495 01:38:10.396934 Ending use of test pattern.
12496 01:38:10.397304 Ending test lava.0_igt-kms-mediatek (14173506_1.5.2.3.1), duration 5.81
12498 01:38:10.399609 SRANDOM=1717551490 for randomisation
12499 01:38:10.400028 Opened device: /dev/dri/card0
12500 01:38:10.405808 No KMS driver or no outputs, pipes: 16, outputs: 0
12501 01:38:10.408794 [1mSubtest wait-forked: SKIP (0.000s)[0m
12502 01:38:10.415308 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12503 01:38:10.418747 Using IGT_SRANDOM=1717551490 for randomisation
12504 01:38:10.422342 Opened device: /dev/dri/card0
12505 01:38:10.425748 No KMS driver or no outputs, pipes: 16, outputs: 0
12506 01:38:10.431924 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12507 01:38:10.435473 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12508 01:38:10.442704 Using IGT_SRANDOM=1717551490 for randomisation
12509 01:38:10.445521 Opened device: /dev/dri/card0
12510 01:38:10.448307 No KMS driver or no outputs, pipes: 16, outputs: 0
12511 01:38:10.451744 [1mSubtest wait-busy: SKIP (0.000s)[0m
12512 01:38:10.458476 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12513 01:38:10.461844 Using IGT_SRANDOM=1717551490 for randomisation
12514 01:38:10.465079 Opened device: /dev/dri/card0
12515 01:38:10.468696 No KMS driver or no outputs, pipes: 16, outputs: 0
12516 01:38:10.475160 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12517 01:38:10.478633 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12518 01:38:10.485198 Using IGT_SRANDOM=1717551490 for randomisation
12519 01:38:10.488034 Opened device: /dev/dri/card0
12520 01:38:10.491445 No KMS driver or no outputs, pipes: 16, outputs: 0
12521 01:38:10.496605 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12522 01:38:10.501909 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12523 01:38:10.505395 Using IGT_SRANDOM=1717551490 for randomisation
12524 01:38:10.508490 Opened device: /dev/dri/card0
12525 01:38:10.515028 No KMS driver or no outputs, pipes: 16, outputs: 0
12526 01:38:10.518189 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12527 01:38:10.524671 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12528 01:38:10.528707 Using IGT_SRANDOM=1717551490 for randomisation
12529 01:38:10.531605 Opened device: /dev/dri/card0
12530 01:38:10.534863 No KMS driver or no outputs, pipes: 16, outputs: 0
12531 01:38:10.541375 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12532 01:38:10.548405 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12533 01:38:10.551663 Using IGT_SRANDOM=1717551490 for randomisation
12534 01:38:10.555645 Opened device: /dev/dri/card0
12535 01:38:10.558168 No KMS driver or no outputs, pipes: 16, outputs: 0
12536 01:38:10.565228 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12537 01:38:10.568467 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12538 01:38:10.575909 Using IGT_SRANDOM=1717551490 for randomisation
12539 01:38:10.576464 Opened device: /dev/dri/card0
12540 01:38:10.581627 No KMS driver or no outputs, pipes: 16, outputs: 0
12541 01:38:10.584950 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12542 01:38:10.591218 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12543 01:38:10.598829 Using IGT_SRANDOM=1717551490 for randomisation
12544 01:38:10.599399 Opened device: /dev/dri/card0
12545 01:38:10.605375 No KMS driver or no outputs, pipes: 16, outputs: 0
12546 01:38:10.607853 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12547 01:38:10.615213 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12548 01:38:10.618011 Using IGT_SRANDOM=1717551490 for randomisation
12549 01:38:10.621557 Opened device: /dev/dri/card0
12550 01:38:10.628516 No KMS driver or no outputs, pipes: 16, outputs: 0
12551 01:38:10.631185 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12552 01:38:10.638395 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12553 01:38:10.640589 Using IGT_SRANDOM=1717551490 for randomisation
12554 01:38:10.644560 Opened device: /dev/dri/card0
12555 01:38:10.648223 No KMS driver or no outputs, pipes: 16, outputs: 0
12556 01:38:10.654595 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12557 01:38:10.661244 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12558 01:38:10.665067 Using IGT_SRANDOM=1717551490 for randomisation
12559 01:38:10.668127 Opened device: /dev/dri/card0
12560 01:38:10.670701 No KMS driver or no outputs, pipes: 16, outputs: 0
12561 01:38:10.677069 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12562 01:38:10.684451 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22-rt12 aarch64)
12563 01:38:10.687281 Using IGT_SRANDOM=1717551490 for randomisation
12564 01:38:10.691284 Opened device: /dev/dri/card0
12565 01:38:10.694963 No KMS driver or no outputs, pipes: 16, outputs: 0
12566 01:38:10.700616 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12567 01:38:10.701382 + set +x
12568 01:38:10.704077 <LAVA_TEST_RUNNER EXIT>
12569 01:38:10.705040 ok: lava_test_shell seems to have completed
12570 01:38:10.719672 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12571 01:38:10.720423 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12572 01:38:10.720894 end: 3 lava-test-retry (duration 00:00:07) [common]
12573 01:38:10.721409 start: 4 finalize (timeout 00:06:53) [common]
12574 01:38:10.721876 start: 4.1 power-off (timeout 00:00:30) [common]
12575 01:38:10.722639 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
12576 01:38:10.828931 >> Command sent successfully.
12577 01:38:10.833850 Returned 0 in 0 seconds
12578 01:38:10.934826 end: 4.1 power-off (duration 00:00:00) [common]
12580 01:38:10.936409 start: 4.2 read-feedback (timeout 00:06:53) [common]
12581 01:38:10.937784 Listened to connection for namespace 'common' for up to 1s
12582 01:38:11.938322 Finalising connection for namespace 'common'
12583 01:38:11.938985 Disconnecting from shell: Finalise
12584 01:38:11.939450 / #
12585 01:38:12.040382 end: 4.2 read-feedback (duration 00:00:01) [common]
12586 01:38:12.041122 end: 4 finalize (duration 00:00:01) [common]
12587 01:38:12.042041 Cleaning after the job
12588 01:38:12.042852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/ramdisk
12589 01:38:12.070399 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/kernel
12590 01:38:12.097041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/dtb
12591 01:38:12.097340 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173506/tftp-deploy-nsa4wev3/modules
12592 01:38:12.103985 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173506
12593 01:38:12.219311 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173506
12594 01:38:12.219613 Job finished correctly