Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 01:32:09.959355 lava-dispatcher, installed at version: 2024.03
2 01:32:09.959563 start: 0 validate
3 01:32:09.959693 Start time: 2024-06-05 01:32:09.959685+00:00 (UTC)
4 01:32:09.959809 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:32:09.959935 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:32:10.238624 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:32:10.239367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:32:10.494332 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:32:10.495047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:32:10.750263 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:32:10.750943 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:32:11.004328 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:32:11.005121 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:32:11.267784 validate duration: 1.31
16 01:32:11.269143 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:32:11.269773 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:32:11.270404 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:32:11.271035 Not decompressing ramdisk as can be used compressed.
20 01:32:11.271502 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:32:11.271969 saving as /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/ramdisk/initrd.cpio.gz
22 01:32:11.272344 total size: 5628169 (5 MB)
23 01:32:11.277666 progress 0 % (0 MB)
24 01:32:11.287787 progress 5 % (0 MB)
25 01:32:11.294523 progress 10 % (0 MB)
26 01:32:11.298542 progress 15 % (0 MB)
27 01:32:11.302299 progress 20 % (1 MB)
28 01:32:11.305371 progress 25 % (1 MB)
29 01:32:11.308379 progress 30 % (1 MB)
30 01:32:11.311090 progress 35 % (1 MB)
31 01:32:11.313323 progress 40 % (2 MB)
32 01:32:11.315718 progress 45 % (2 MB)
33 01:32:11.317671 progress 50 % (2 MB)
34 01:32:11.319874 progress 55 % (2 MB)
35 01:32:11.321807 progress 60 % (3 MB)
36 01:32:11.323566 progress 65 % (3 MB)
37 01:32:11.325431 progress 70 % (3 MB)
38 01:32:11.327056 progress 75 % (4 MB)
39 01:32:11.328811 progress 80 % (4 MB)
40 01:32:11.330311 progress 85 % (4 MB)
41 01:32:11.331929 progress 90 % (4 MB)
42 01:32:11.333541 progress 95 % (5 MB)
43 01:32:11.334988 progress 100 % (5 MB)
44 01:32:11.335196 5 MB downloaded in 0.06 s (85.36 MB/s)
45 01:32:11.335348 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:32:11.335585 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:32:11.335671 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:32:11.335754 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:32:11.335886 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:32:11.335955 saving as /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/kernel/Image
52 01:32:11.336016 total size: 54682112 (52 MB)
53 01:32:11.336077 No compression specified
54 01:32:11.337287 progress 0 % (0 MB)
55 01:32:11.351326 progress 5 % (2 MB)
56 01:32:11.365118 progress 10 % (5 MB)
57 01:32:11.379053 progress 15 % (7 MB)
58 01:32:11.393056 progress 20 % (10 MB)
59 01:32:11.407092 progress 25 % (13 MB)
60 01:32:11.421012 progress 30 % (15 MB)
61 01:32:11.435107 progress 35 % (18 MB)
62 01:32:11.448857 progress 40 % (20 MB)
63 01:32:11.462636 progress 45 % (23 MB)
64 01:32:11.476741 progress 50 % (26 MB)
65 01:32:11.490829 progress 55 % (28 MB)
66 01:32:11.504707 progress 60 % (31 MB)
67 01:32:11.518565 progress 65 % (33 MB)
68 01:32:11.532710 progress 70 % (36 MB)
69 01:32:11.546553 progress 75 % (39 MB)
70 01:32:11.560508 progress 80 % (41 MB)
71 01:32:11.574479 progress 85 % (44 MB)
72 01:32:11.588449 progress 90 % (46 MB)
73 01:32:11.602332 progress 95 % (49 MB)
74 01:32:11.615749 progress 100 % (52 MB)
75 01:32:11.615974 52 MB downloaded in 0.28 s (186.28 MB/s)
76 01:32:11.616124 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:32:11.616362 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:32:11.616449 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:32:11.616533 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:32:11.616665 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:32:11.616739 saving as /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/dtb/mt8192-asurada-spherion-r0.dtb
83 01:32:11.616800 total size: 47258 (0 MB)
84 01:32:11.616860 No compression specified
85 01:32:11.617933 progress 69 % (0 MB)
86 01:32:11.618234 progress 100 % (0 MB)
87 01:32:11.618390 0 MB downloaded in 0.00 s (28.38 MB/s)
88 01:32:11.618510 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:32:11.618731 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:32:11.618816 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:32:11.618898 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:32:11.619007 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:32:11.619075 saving as /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/nfsrootfs/full.rootfs.tar
95 01:32:11.619134 total size: 120894716 (115 MB)
96 01:32:11.619194 Using unxz to decompress xz
97 01:32:11.623293 progress 0 % (0 MB)
98 01:32:11.963478 progress 5 % (5 MB)
99 01:32:12.312307 progress 10 % (11 MB)
100 01:32:12.656621 progress 15 % (17 MB)
101 01:32:12.979966 progress 20 % (23 MB)
102 01:32:13.270336 progress 25 % (28 MB)
103 01:32:13.626983 progress 30 % (34 MB)
104 01:32:13.959117 progress 35 % (40 MB)
105 01:32:14.121897 progress 40 % (46 MB)
106 01:32:14.297592 progress 45 % (51 MB)
107 01:32:14.602773 progress 50 % (57 MB)
108 01:32:14.969863 progress 55 % (63 MB)
109 01:32:15.308063 progress 60 % (69 MB)
110 01:32:15.644787 progress 65 % (74 MB)
111 01:32:15.985128 progress 70 % (80 MB)
112 01:32:16.336428 progress 75 % (86 MB)
113 01:32:16.674222 progress 80 % (92 MB)
114 01:32:17.011663 progress 85 % (98 MB)
115 01:32:17.361671 progress 90 % (103 MB)
116 01:32:17.683146 progress 95 % (109 MB)
117 01:32:18.035258 progress 100 % (115 MB)
118 01:32:18.040565 115 MB downloaded in 6.42 s (17.95 MB/s)
119 01:32:18.040869 end: 1.4.1 http-download (duration 00:00:06) [common]
121 01:32:18.041266 end: 1.4 download-retry (duration 00:00:06) [common]
122 01:32:18.041388 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:32:18.041498 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:32:18.041647 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:32:18.041719 saving as /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/modules/modules.tar
126 01:32:18.041779 total size: 8605984 (8 MB)
127 01:32:18.041841 Using unxz to decompress xz
128 01:32:18.046365 progress 0 % (0 MB)
129 01:32:18.065047 progress 5 % (0 MB)
130 01:32:18.092025 progress 10 % (0 MB)
131 01:32:18.121990 progress 15 % (1 MB)
132 01:32:18.145543 progress 20 % (1 MB)
133 01:32:18.169256 progress 25 % (2 MB)
134 01:32:18.192815 progress 30 % (2 MB)
135 01:32:18.217256 progress 35 % (2 MB)
136 01:32:18.244154 progress 40 % (3 MB)
137 01:32:18.266517 progress 45 % (3 MB)
138 01:32:18.290406 progress 50 % (4 MB)
139 01:32:18.315324 progress 55 % (4 MB)
140 01:32:18.339735 progress 60 % (4 MB)
141 01:32:18.363551 progress 65 % (5 MB)
142 01:32:18.388331 progress 70 % (5 MB)
143 01:32:18.412086 progress 75 % (6 MB)
144 01:32:18.439779 progress 80 % (6 MB)
145 01:32:18.464055 progress 85 % (7 MB)
146 01:32:18.489381 progress 90 % (7 MB)
147 01:32:18.514624 progress 95 % (7 MB)
148 01:32:18.539724 progress 100 % (8 MB)
149 01:32:18.545028 8 MB downloaded in 0.50 s (16.31 MB/s)
150 01:32:18.545272 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:32:18.545540 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:32:18.545639 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:32:18.545733 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:32:21.961694 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj
156 01:32:21.961900 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 01:32:21.962002 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:32:21.962182 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o
159 01:32:21.962315 makedir: /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin
160 01:32:21.962416 makedir: /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/tests
161 01:32:21.962515 makedir: /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/results
162 01:32:21.962613 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-add-keys
163 01:32:21.962752 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-add-sources
164 01:32:21.962879 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-background-process-start
165 01:32:21.963018 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-background-process-stop
166 01:32:21.963148 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-common-functions
167 01:32:21.963273 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-echo-ipv4
168 01:32:21.963398 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-install-packages
169 01:32:21.963521 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-installed-packages
170 01:32:21.963648 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-os-build
171 01:32:21.963775 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-probe-channel
172 01:32:21.963898 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-probe-ip
173 01:32:21.964022 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-target-ip
174 01:32:21.964144 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-target-mac
175 01:32:21.964266 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-target-storage
176 01:32:21.964391 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-case
177 01:32:21.964515 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-event
178 01:32:21.964636 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-feedback
179 01:32:21.964758 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-raise
180 01:32:21.964880 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-reference
181 01:32:21.965003 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-runner
182 01:32:21.965124 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-set
183 01:32:21.965247 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-test-shell
184 01:32:21.965371 Updating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-add-keys (debian)
185 01:32:21.965521 Updating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-add-sources (debian)
186 01:32:21.965658 Updating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-install-packages (debian)
187 01:32:21.965793 Updating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-installed-packages (debian)
188 01:32:21.965927 Updating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/bin/lava-os-build (debian)
189 01:32:21.966045 Creating /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/environment
190 01:32:21.966140 LAVA metadata
191 01:32:21.966216 - LAVA_JOB_ID=14173494
192 01:32:21.966280 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:32:21.966381 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:32:21.966446 skipped lava-vland-overlay
195 01:32:21.966520 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:32:21.966597 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:32:21.966657 skipped lava-multinode-overlay
198 01:32:21.966726 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:32:21.966802 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:32:21.966873 Loading test definitions
201 01:32:21.966957 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:32:21.967026 Using /lava-14173494 at stage 0
203 01:32:21.967306 uuid=14173494_1.6.2.3.1 testdef=None
204 01:32:21.967393 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:32:21.967477 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:32:21.967926 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:32:21.968143 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:32:21.968698 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:32:21.968926 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:32:21.969456 runner path: /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/0/tests/0_timesync-off test_uuid 14173494_1.6.2.3.1
213 01:32:21.969612 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:32:21.969836 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:32:21.969907 Using /lava-14173494 at stage 0
217 01:32:21.970002 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:32:21.970087 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/0/tests/1_kselftest-arm64'
219 01:32:24.499055 Running '/usr/bin/git checkout kernelci.org
220 01:32:24.645804 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 01:32:24.646588 uuid=14173494_1.6.2.3.5 testdef=None
222 01:32:24.646755 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 01:32:24.647002 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 01:32:24.647756 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:32:24.647987 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 01:32:24.648991 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:32:24.649236 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 01:32:24.650175 runner path: /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/0/tests/1_kselftest-arm64 test_uuid 14173494_1.6.2.3.5
232 01:32:24.650305 BOARD='mt8192-asurada-spherion-r0'
233 01:32:24.650369 BRANCH='cip-gitlab'
234 01:32:24.650429 SKIPFILE='/dev/null'
235 01:32:24.650487 SKIP_INSTALL='True'
236 01:32:24.650543 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:32:24.650600 TST_CASENAME=''
238 01:32:24.650656 TST_CMDFILES='arm64'
239 01:32:24.650797 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:32:24.651004 Creating lava-test-runner.conf files
242 01:32:24.651068 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173494/lava-overlay-gcmp206o/lava-14173494/0 for stage 0
243 01:32:24.651160 - 0_timesync-off
244 01:32:24.651229 - 1_kselftest-arm64
245 01:32:24.651323 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 01:32:24.651413 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 01:32:32.083419 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 01:32:32.083569 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 01:32:32.083661 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:32:32.083760 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 01:32:32.083850 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 01:32:32.247375 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:32:32.247766 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 01:32:32.247885 extracting modules file /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj
255 01:32:32.463375 extracting modules file /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173494/extract-overlay-ramdisk-fow01l4i/ramdisk
256 01:32:32.687073 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:32:32.687236 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 01:32:32.687334 [common] Applying overlay to NFS
259 01:32:32.687407 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173494/compress-overlay-m3hp9hlt/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj
260 01:32:33.604719 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:32:33.604884 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 01:32:33.604985 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:32:33.605075 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 01:32:33.605160 Building ramdisk /var/lib/lava/dispatcher/tmp/14173494/extract-overlay-ramdisk-fow01l4i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173494/extract-overlay-ramdisk-fow01l4i/ramdisk
265 01:32:33.946967 >> 130348 blocks
266 01:32:35.983863 rename /var/lib/lava/dispatcher/tmp/14173494/extract-overlay-ramdisk-fow01l4i/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/ramdisk/ramdisk.cpio.gz
267 01:32:35.984310 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:32:35.984442 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 01:32:35.984543 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 01:32:35.984652 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/kernel/Image']
271 01:32:48.922340 Returned 0 in 12 seconds
272 01:32:49.023312 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/kernel/image.itb
273 01:32:49.408257 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:32:49.408636 output: Created: Wed Jun 5 02:32:49 2024
275 01:32:49.408712 output: Image 0 (kernel-1)
276 01:32:49.408779 output: Description:
277 01:32:49.408844 output: Created: Wed Jun 5 02:32:49 2024
278 01:32:49.408909 output: Type: Kernel Image
279 01:32:49.408971 output: Compression: lzma compressed
280 01:32:49.409033 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
281 01:32:49.409094 output: Architecture: AArch64
282 01:32:49.409154 output: OS: Linux
283 01:32:49.409212 output: Load Address: 0x00000000
284 01:32:49.409291 output: Entry Point: 0x00000000
285 01:32:49.409349 output: Hash algo: crc32
286 01:32:49.409406 output: Hash value: 4c96ec19
287 01:32:49.409462 output: Image 1 (fdt-1)
288 01:32:49.409518 output: Description: mt8192-asurada-spherion-r0
289 01:32:49.409574 output: Created: Wed Jun 5 02:32:49 2024
290 01:32:49.409630 output: Type: Flat Device Tree
291 01:32:49.409683 output: Compression: uncompressed
292 01:32:49.409737 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 01:32:49.409791 output: Architecture: AArch64
294 01:32:49.409845 output: Hash algo: crc32
295 01:32:49.409898 output: Hash value: 0f8e4d2e
296 01:32:49.409951 output: Image 2 (ramdisk-1)
297 01:32:49.410004 output: Description: unavailable
298 01:32:49.410057 output: Created: Wed Jun 5 02:32:49 2024
299 01:32:49.410111 output: Type: RAMDisk Image
300 01:32:49.410170 output: Compression: Unknown Compression
301 01:32:49.410262 output: Data Size: 18734352 Bytes = 18295.27 KiB = 17.87 MiB
302 01:32:49.410316 output: Architecture: AArch64
303 01:32:49.410369 output: OS: Linux
304 01:32:49.410422 output: Load Address: unavailable
305 01:32:49.410474 output: Entry Point: unavailable
306 01:32:49.410527 output: Hash algo: crc32
307 01:32:49.410579 output: Hash value: bcd21e18
308 01:32:49.410632 output: Default Configuration: 'conf-1'
309 01:32:49.410685 output: Configuration 0 (conf-1)
310 01:32:49.410738 output: Description: mt8192-asurada-spherion-r0
311 01:32:49.410791 output: Kernel: kernel-1
312 01:32:49.410844 output: Init Ramdisk: ramdisk-1
313 01:32:49.410897 output: FDT: fdt-1
314 01:32:49.410949 output: Loadables: kernel-1
315 01:32:49.411001 output:
316 01:32:49.411208 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:32:49.411333 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:32:49.411445 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 01:32:49.411536 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 01:32:49.411613 No LXC device requested
321 01:32:49.411692 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:32:49.411782 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 01:32:49.411861 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:32:49.411931 Checking files for TFTP limit of 4294967296 bytes.
325 01:32:49.412434 end: 1 tftp-deploy (duration 00:00:38) [common]
326 01:32:49.412541 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:32:49.412635 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:32:49.412765 substitutions:
329 01:32:49.412833 - {DTB}: 14173494/tftp-deploy-s3airdeb/dtb/mt8192-asurada-spherion-r0.dtb
330 01:32:49.412896 - {INITRD}: 14173494/tftp-deploy-s3airdeb/ramdisk/ramdisk.cpio.gz
331 01:32:49.412956 - {KERNEL}: 14173494/tftp-deploy-s3airdeb/kernel/Image
332 01:32:49.413013 - {LAVA_MAC}: None
333 01:32:49.413070 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj
334 01:32:49.413126 - {NFS_SERVER_IP}: 192.168.201.1
335 01:32:49.413181 - {PRESEED_CONFIG}: None
336 01:32:49.413235 - {PRESEED_LOCAL}: None
337 01:32:49.413323 - {RAMDISK}: 14173494/tftp-deploy-s3airdeb/ramdisk/ramdisk.cpio.gz
338 01:32:49.413410 - {ROOT_PART}: None
339 01:32:49.413471 - {ROOT}: None
340 01:32:49.413526 - {SERVER_IP}: 192.168.201.1
341 01:32:49.413580 - {TEE}: None
342 01:32:49.413635 Parsed boot commands:
343 01:32:49.413688 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:32:49.413871 Parsed boot commands: tftpboot 192.168.201.1 14173494/tftp-deploy-s3airdeb/kernel/image.itb 14173494/tftp-deploy-s3airdeb/kernel/cmdline
345 01:32:49.413959 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:32:49.414045 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:32:49.414137 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:32:49.414275 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:32:49.414349 Not connected, no need to disconnect.
350 01:32:49.414422 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:32:49.414508 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:32:49.414579 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 01:32:49.418328 Setting prompt string to ['lava-test: # ']
354 01:32:49.418697 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:32:49.418809 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:32:49.418904 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:32:49.418997 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:32:49.419172 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 01:33:03.344310 Returned 0 in 13 seconds
360 01:33:03.445500 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 01:33:03.447298 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 01:33:03.447954 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 01:33:03.448530 Setting prompt string to 'Starting depthcharge on Spherion...'
365 01:33:03.448989 Changing prompt to 'Starting depthcharge on Spherion...'
366 01:33:03.449476 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 01:33:03.451709 [Enter `^Ec?' for help]
368 01:33:03.452189
369 01:33:03.452697
370 01:33:03.453268 F0: 102B 0000
371 01:33:03.453738
372 01:33:03.454274 F3: 1001 0000 [0200]
373 01:33:03.454690
374 01:33:03.455103 F3: 1001 0000
375 01:33:03.455518
376 01:33:03.455906 F7: 102D 0000
377 01:33:03.456291
378 01:33:03.456674 F1: 0000 0000
379 01:33:03.457161
380 01:33:03.457573 V0: 0000 0000 [0001]
381 01:33:03.458090
382 01:33:03.458571 00: 0007 8000
383 01:33:03.459121
384 01:33:03.459613 01: 0000 0000
385 01:33:03.460069
386 01:33:03.460500 BP: 0C00 0209 [0000]
387 01:33:03.460927
388 01:33:03.461356 G0: 1182 0000
389 01:33:03.461782
390 01:33:03.462231 EC: 0000 0021 [4000]
391 01:33:03.462645
392 01:33:03.462951 S7: 0000 0000 [0000]
393 01:33:03.463231
394 01:33:03.463506 CC: 0000 0000 [0001]
395 01:33:03.463795
396 01:33:03.464099 T0: 0000 0040 [010F]
397 01:33:03.464380
398 01:33:03.464669 Jump to BL
399 01:33:03.464973
400 01:33:03.465251
401 01:33:03.465524
402 01:33:03.465797 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 01:33:03.466096 ARM64: Exception handlers installed.
404 01:33:03.466397 ARM64: Testing exception
405 01:33:03.466674 ARM64: Done test exception
406 01:33:03.466947 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 01:33:03.467223 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 01:33:03.467503 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 01:33:03.467781 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 01:33:03.468056 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 01:33:03.468329 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 01:33:03.468601 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 01:33:03.468912 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 01:33:03.469194 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 01:33:03.469469 WDT: Last reset was cold boot
416 01:33:03.469741 SPI1(PAD0) initialized at 2873684 Hz
417 01:33:03.470009 SPI5(PAD0) initialized at 992727 Hz
418 01:33:03.470323 VBOOT: Loading verstage.
419 01:33:03.470619 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 01:33:03.471091 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 01:33:03.471513 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 01:33:03.471857 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 01:33:03.472142 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 01:33:03.472423 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 01:33:03.472676 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 01:33:03.472872
427 01:33:03.473065
428 01:33:03.473260 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 01:33:03.473459 ARM64: Exception handlers installed.
430 01:33:03.473653 ARM64: Testing exception
431 01:33:03.473847 ARM64: Done test exception
432 01:33:03.474151 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 01:33:03.474382 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 01:33:03.474584 Probing TPM: . done!
435 01:33:03.474777 TPM ready after 0 ms
436 01:33:03.474972 Connected to device vid:did:rid of 1ae0:0028:00
437 01:33:03.475167 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 01:33:03.475369 Initialized TPM device CR50 revision 0
439 01:33:03.475564 tlcl_send_startup: Startup return code is 0
440 01:33:03.475759 TPM: setup succeeded
441 01:33:03.475954 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 01:33:03.476150 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 01:33:03.476346 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 01:33:03.476543 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:33:03.476739 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 01:33:03.476934 in-header: 03 07 00 00 08 00 00 00
447 01:33:03.477128 in-data: aa e4 47 04 13 02 00 00
448 01:33:03.477323 Chrome EC: UHEPI supported
449 01:33:03.477518 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 01:33:03.477685 in-header: 03 a9 00 00 08 00 00 00
451 01:33:03.477832 in-data: 84 60 60 08 00 00 00 00
452 01:33:03.477976 Phase 1
453 01:33:03.478121 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 01:33:03.478282 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 01:33:03.478429 VB2:vb2_check_recovery() Recovery was requested manually
456 01:33:03.478577 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 01:33:03.478723 Recovery requested (1009000e)
458 01:33:03.478870 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 01:33:03.479016 tlcl_extend: response is 0
460 01:33:03.479172 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 01:33:03.479327 tlcl_extend: response is 0
462 01:33:03.479477 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 01:33:03.479624 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 01:33:03.479790 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 01:33:03.479953
466 01:33:03.480100
467 01:33:03.480244 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 01:33:03.480393 ARM64: Exception handlers installed.
469 01:33:03.480539 ARM64: Testing exception
470 01:33:03.480686 ARM64: Done test exception
471 01:33:03.480831 pmic_efuse_setting: Set efuses in 11 msecs
472 01:33:03.480978 pmwrap_interface_init: Select PMIF_VLD_RDY
473 01:33:03.481124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 01:33:03.481270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 01:33:03.481675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 01:33:03.481854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 01:33:03.482013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 01:33:03.482178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 01:33:03.482331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 01:33:03.482488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 01:33:03.482649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 01:33:03.482777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 01:33:03.482906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 01:33:03.483025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 01:33:03.483156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 01:33:03.483367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 01:33:03.483565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 01:33:03.483752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 01:33:03.483937 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 01:33:03.484122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 01:33:03.484306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 01:33:03.484490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 01:33:03.484673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 01:33:03.484857 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 01:33:03.485041 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 01:33:03.485233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 01:33:03.485392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 01:33:03.485582 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 01:33:03.485767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 01:33:03.485953 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 01:33:03.486156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 01:33:03.486314 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 01:33:03.486434 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 01:33:03.486559 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 01:33:03.486683 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 01:33:03.486801 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 01:33:03.486933 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 01:33:03.487061 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 01:33:03.487188 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 01:33:03.487309 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 01:33:03.487427 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 01:33:03.487546 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 01:33:03.487659 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 01:33:03.487757 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 01:33:03.487855 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 01:33:03.487952 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 01:33:03.488048 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 01:33:03.488146 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 01:33:03.488243 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 01:33:03.488341 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 01:33:03.488437 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 01:33:03.488535 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 01:33:03.488632 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 01:33:03.488730 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 01:33:03.488845 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 01:33:03.488946 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 01:33:03.489045 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 01:33:03.489144 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 01:33:03.489244 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 01:33:03.489342 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 01:33:03.489440 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:33:03.489537 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6c, sec=0x32
533 01:33:03.489636 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
534 01:33:03.489734 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 01:33:03.489831 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 01:33:03.489935 [RTC]rtc_get_frequency_meter,154: input=15, output=834
537 01:33:03.490035 [RTC]rtc_get_frequency_meter,154: input=7, output=707
538 01:33:03.490134 [RTC]rtc_get_frequency_meter,154: input=11, output=771
539 01:33:03.490249 [RTC]rtc_get_frequency_meter,154: input=13, output=803
540 01:33:03.490348 [RTC]rtc_get_frequency_meter,154: input=12, output=786
541 01:33:03.490446 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 01:33:03.490544 [RTC]rtc_get_frequency_meter,154: input=13, output=803
543 01:33:03.490641 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 01:33:03.490740 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 01:33:03.491102 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 01:33:03.491229 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 01:33:03.491335 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 01:33:03.491439 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 01:33:03.491539 ADC[4]: Raw value=902291 ID=7
550 01:33:03.491643 ADC[3]: Raw value=213652 ID=1
551 01:33:03.491742 RAM Code: 0x71
552 01:33:03.491841 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 01:33:03.491940 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 01:33:03.492040 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 01:33:03.492140 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 01:33:03.492245 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 01:33:03.492387 in-header: 03 07 00 00 08 00 00 00
558 01:33:03.492527 in-data: aa e4 47 04 13 02 00 00
559 01:33:03.492663 Chrome EC: UHEPI supported
560 01:33:03.492809 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 01:33:03.492957 in-header: 03 a9 00 00 08 00 00 00
562 01:33:03.493075 in-data: 84 60 60 08 00 00 00 00
563 01:33:03.493220 MRC: failed to locate region type 0.
564 01:33:03.493335 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 01:33:03.493482 DRAM-K: Running full calibration
566 01:33:03.493599 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 01:33:03.493716 header.status = 0x0
568 01:33:03.493833 header.version = 0x6 (expected: 0x6)
569 01:33:03.493980 header.size = 0xd00 (expected: 0xd00)
570 01:33:03.494127 header.flags = 0x0
571 01:33:03.494253 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 01:33:03.494401 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 01:33:03.494518 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 01:33:03.494666 dram_init: ddr_geometry: 2
575 01:33:03.494782 [EMI] MDL number = 2
576 01:33:03.494899 [EMI] Get MDL freq = 0
577 01:33:03.495016 dram_init: ddr_type: 0
578 01:33:03.495162 is_discrete_lpddr4: 1
579 01:33:03.495309 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 01:33:03.495425
581 01:33:03.495572
582 01:33:03.495719 [Bian_co] ETT version 0.0.0.1
583 01:33:03.495866 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 01:33:03.496013
585 01:33:03.496159 dramc_set_vcore_voltage set vcore to 650000
586 01:33:03.496307 Read voltage for 800, 4
587 01:33:03.496454 Vio18 = 0
588 01:33:03.496601 Vcore = 650000
589 01:33:03.496748 Vdram = 0
590 01:33:03.496894 Vddq = 0
591 01:33:03.497039 Vmddr = 0
592 01:33:03.497184 dram_init: config_dvfs: 1
593 01:33:03.497330 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 01:33:03.497476 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 01:33:03.497631 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
596 01:33:03.497759 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
597 01:33:03.497888 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 01:33:03.498016 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 01:33:03.498145 MEM_TYPE=3, freq_sel=18
600 01:33:03.498279 sv_algorithm_assistance_LP4_1600
601 01:33:03.498407 ============ PULL DRAM RESETB DOWN ============
602 01:33:03.498539 ========== PULL DRAM RESETB DOWN end =========
603 01:33:03.498668 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 01:33:03.498796 ===================================
605 01:33:03.498924 LPDDR4 DRAM CONFIGURATION
606 01:33:03.499052 ===================================
607 01:33:03.499180 EX_ROW_EN[0] = 0x0
608 01:33:03.499308 EX_ROW_EN[1] = 0x0
609 01:33:03.499436 LP4Y_EN = 0x0
610 01:33:03.499565 WORK_FSP = 0x0
611 01:33:03.499693 WL = 0x2
612 01:33:03.499820 RL = 0x2
613 01:33:03.499947 BL = 0x2
614 01:33:03.500075 RPST = 0x0
615 01:33:03.500202 RD_PRE = 0x0
616 01:33:03.500329 WR_PRE = 0x1
617 01:33:03.500456 WR_PST = 0x0
618 01:33:03.500584 DBI_WR = 0x0
619 01:33:03.500711 DBI_RD = 0x0
620 01:33:03.500838 OTF = 0x1
621 01:33:03.500966 ===================================
622 01:33:03.501096 ===================================
623 01:33:03.501224 ANA top config
624 01:33:03.501352 ===================================
625 01:33:03.501480 DLL_ASYNC_EN = 0
626 01:33:03.501608 ALL_SLAVE_EN = 1
627 01:33:03.501735 NEW_RANK_MODE = 1
628 01:33:03.501865 DLL_IDLE_MODE = 1
629 01:33:03.501993 LP45_APHY_COMB_EN = 1
630 01:33:03.502121 TX_ODT_DIS = 1
631 01:33:03.502260 NEW_8X_MODE = 1
632 01:33:03.502390 ===================================
633 01:33:03.502522 ===================================
634 01:33:03.502631 data_rate = 1600
635 01:33:03.502723 CKR = 1
636 01:33:03.502814 DQ_P2S_RATIO = 8
637 01:33:03.502928 ===================================
638 01:33:03.503043 CA_P2S_RATIO = 8
639 01:33:03.503158 DQ_CA_OPEN = 0
640 01:33:03.503271 DQ_SEMI_OPEN = 0
641 01:33:03.503362 CA_SEMI_OPEN = 0
642 01:33:03.503453 CA_FULL_RATE = 0
643 01:33:03.503567 DQ_CKDIV4_EN = 1
644 01:33:03.503680 CA_CKDIV4_EN = 1
645 01:33:03.503794 CA_PREDIV_EN = 0
646 01:33:03.503908 PH8_DLY = 0
647 01:33:03.504022 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 01:33:03.504136 DQ_AAMCK_DIV = 4
649 01:33:03.504250 CA_AAMCK_DIV = 4
650 01:33:03.504368 CA_ADMCK_DIV = 4
651 01:33:03.504483 DQ_TRACK_CA_EN = 0
652 01:33:03.504598 CA_PICK = 800
653 01:33:03.504713 CA_MCKIO = 800
654 01:33:03.504826 MCKIO_SEMI = 0
655 01:33:03.504940 PLL_FREQ = 3068
656 01:33:03.505054 DQ_UI_PI_RATIO = 32
657 01:33:03.505168 CA_UI_PI_RATIO = 0
658 01:33:03.505281 ===================================
659 01:33:03.505395 ===================================
660 01:33:03.505509 memory_type:LPDDR4
661 01:33:03.505622 GP_NUM : 10
662 01:33:03.505735 SRAM_EN : 1
663 01:33:03.505849 MD32_EN : 0
664 01:33:03.506203 ===================================
665 01:33:03.506322 [ANA_INIT] >>>>>>>>>>>>>>
666 01:33:03.506440 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 01:33:03.506560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 01:33:03.506678 ===================================
669 01:33:03.506795 data_rate = 1600,PCW = 0X7600
670 01:33:03.506912 ===================================
671 01:33:03.507027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 01:33:03.507143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 01:33:03.507258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:33:03.507374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 01:33:03.507489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 01:33:03.507613 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:33:03.507716 [ANA_INIT] flow start
678 01:33:03.507819 [ANA_INIT] PLL >>>>>>>>
679 01:33:03.507922 [ANA_INIT] PLL <<<<<<<<
680 01:33:03.508026 [ANA_INIT] MIDPI >>>>>>>>
681 01:33:03.508128 [ANA_INIT] MIDPI <<<<<<<<
682 01:33:03.508231 [ANA_INIT] DLL >>>>>>>>
683 01:33:03.508333 [ANA_INIT] flow end
684 01:33:03.508436 ============ LP4 DIFF to SE enter ============
685 01:33:03.508539 ============ LP4 DIFF to SE exit ============
686 01:33:03.508643 [ANA_INIT] <<<<<<<<<<<<<
687 01:33:03.508745 [Flow] Enable top DCM control >>>>>
688 01:33:03.508849 [Flow] Enable top DCM control <<<<<
689 01:33:03.508952 Enable DLL master slave shuffle
690 01:33:03.509054 ==============================================================
691 01:33:03.509158 Gating Mode config
692 01:33:03.509261 ==============================================================
693 01:33:03.509365 Config description:
694 01:33:03.509471 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 01:33:03.509577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 01:33:03.509682 SELPH_MODE 0: By rank 1: By Phase
697 01:33:03.509786 ==============================================================
698 01:33:03.509891 GAT_TRACK_EN = 1
699 01:33:03.509994 RX_GATING_MODE = 2
700 01:33:03.510097 RX_GATING_TRACK_MODE = 2
701 01:33:03.510209 SELPH_MODE = 1
702 01:33:03.510313 PICG_EARLY_EN = 1
703 01:33:03.510416 VALID_LAT_VALUE = 1
704 01:33:03.510519 ==============================================================
705 01:33:03.510623 Enter into Gating configuration >>>>
706 01:33:03.510726 Exit from Gating configuration <<<<
707 01:33:03.510829 Enter into DVFS_PRE_config >>>>>
708 01:33:03.510932 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 01:33:03.511039 Exit from DVFS_PRE_config <<<<<
710 01:33:03.511142 Enter into PICG configuration >>>>
711 01:33:03.511244 Exit from PICG configuration <<<<
712 01:33:03.511346 [RX_INPUT] configuration >>>>>
713 01:33:03.511449 [RX_INPUT] configuration <<<<<
714 01:33:03.511553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 01:33:03.511658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 01:33:03.511763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 01:33:03.511867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 01:33:03.511972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 01:33:03.512078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 01:33:03.512181 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 01:33:03.512286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 01:33:03.512390 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 01:33:03.512500 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 01:33:03.512617 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 01:33:03.512713 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 01:33:03.512807 ===================================
727 01:33:03.512902 LPDDR4 DRAM CONFIGURATION
728 01:33:03.512996 ===================================
729 01:33:03.513091 EX_ROW_EN[0] = 0x0
730 01:33:03.513185 EX_ROW_EN[1] = 0x0
731 01:33:03.513278 LP4Y_EN = 0x0
732 01:33:03.513372 WORK_FSP = 0x0
733 01:33:03.513465 WL = 0x2
734 01:33:03.513559 RL = 0x2
735 01:33:03.513652 BL = 0x2
736 01:33:03.513744 RPST = 0x0
737 01:33:03.513837 RD_PRE = 0x0
738 01:33:03.513930 WR_PRE = 0x1
739 01:33:03.514023 WR_PST = 0x0
740 01:33:03.514117 DBI_WR = 0x0
741 01:33:03.514216 DBI_RD = 0x0
742 01:33:03.514310 OTF = 0x1
743 01:33:03.514405 ===================================
744 01:33:03.514499 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 01:33:03.514593 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 01:33:03.514688 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 01:33:03.514781 ===================================
748 01:33:03.514876 LPDDR4 DRAM CONFIGURATION
749 01:33:03.514970 ===================================
750 01:33:03.515064 EX_ROW_EN[0] = 0x10
751 01:33:03.515157 EX_ROW_EN[1] = 0x0
752 01:33:03.515251 LP4Y_EN = 0x0
753 01:33:03.515344 WORK_FSP = 0x0
754 01:33:03.515440 WL = 0x2
755 01:33:03.515535 RL = 0x2
756 01:33:03.515629 BL = 0x2
757 01:33:03.515721 RPST = 0x0
758 01:33:03.515814 RD_PRE = 0x0
759 01:33:03.515907 WR_PRE = 0x1
760 01:33:03.516000 WR_PST = 0x0
761 01:33:03.516093 DBI_WR = 0x0
762 01:33:03.516186 DBI_RD = 0x0
763 01:33:03.516281 OTF = 0x1
764 01:33:03.516376 ===================================
765 01:33:03.516469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 01:33:03.516563 nWR fixed to 40
767 01:33:03.516657 [ModeRegInit_LP4] CH0 RK0
768 01:33:03.516751 [ModeRegInit_LP4] CH0 RK1
769 01:33:03.516844 [ModeRegInit_LP4] CH1 RK0
770 01:33:03.516937 [ModeRegInit_LP4] CH1 RK1
771 01:33:03.517030 match AC timing 13
772 01:33:03.517123 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 01:33:03.517426 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 01:33:03.517524 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 01:33:03.517636 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 01:33:03.517731 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 01:33:03.517829 [EMI DOE] emi_dcm 0
778 01:33:03.517926 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 01:33:03.518022 ==
780 01:33:03.518116 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:33:03.518249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 01:33:03.518343 ==
783 01:33:03.518437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 01:33:03.518531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 01:33:03.518627 [CA 0] Center 37 (7~68) winsize 62
786 01:33:03.518720 [CA 1] Center 37 (6~68) winsize 63
787 01:33:03.518812 [CA 2] Center 34 (4~65) winsize 62
788 01:33:03.518906 [CA 3] Center 34 (4~65) winsize 62
789 01:33:03.518999 [CA 4] Center 33 (3~64) winsize 62
790 01:33:03.519092 [CA 5] Center 33 (3~64) winsize 62
791 01:33:03.519183
792 01:33:03.519275 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 01:33:03.519367
794 01:33:03.519459 [CATrainingPosCal] consider 1 rank data
795 01:33:03.519551 u2DelayCellTimex100 = 270/100 ps
796 01:33:03.519642 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 01:33:03.519735 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 01:33:03.519827 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 01:33:03.519919 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 01:33:03.520011 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 01:33:03.520102 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 01:33:03.520193
803 01:33:03.520284 CA PerBit enable=1, Macro0, CA PI delay=33
804 01:33:03.520376
805 01:33:03.520467 [CBTSetCACLKResult] CA Dly = 33
806 01:33:03.520567 CS Dly: 6 (0~37)
807 01:33:03.520709 ==
808 01:33:03.520803 Dram Type= 6, Freq= 0, CH_0, rank 1
809 01:33:03.520899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 01:33:03.520988 ==
811 01:33:03.521073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 01:33:03.521163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 01:33:03.521251 [CA 0] Center 37 (6~68) winsize 63
814 01:33:03.521340 [CA 1] Center 37 (7~68) winsize 62
815 01:33:03.521429 [CA 2] Center 34 (4~65) winsize 62
816 01:33:03.521516 [CA 3] Center 34 (4~65) winsize 62
817 01:33:03.521599 [CA 4] Center 33 (3~64) winsize 62
818 01:33:03.521682 [CA 5] Center 33 (3~64) winsize 62
819 01:33:03.521763
820 01:33:03.521846 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 01:33:03.521928
822 01:33:03.522010 [CATrainingPosCal] consider 2 rank data
823 01:33:03.522093 u2DelayCellTimex100 = 270/100 ps
824 01:33:03.522178 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 01:33:03.522272 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 01:33:03.522326 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 01:33:03.522379 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 01:33:03.522432 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 01:33:03.522484 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 01:33:03.522537
831 01:33:03.522589 CA PerBit enable=1, Macro0, CA PI delay=33
832 01:33:03.522642
833 01:33:03.522694 [CBTSetCACLKResult] CA Dly = 33
834 01:33:03.522747 CS Dly: 7 (0~39)
835 01:33:03.522799
836 01:33:03.522852 ----->DramcWriteLeveling(PI) begin...
837 01:33:03.522907 ==
838 01:33:03.522961 Dram Type= 6, Freq= 0, CH_0, rank 0
839 01:33:03.523014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 01:33:03.523067 ==
841 01:33:03.523120 Write leveling (Byte 0): 32 => 32
842 01:33:03.523173 Write leveling (Byte 1): 29 => 29
843 01:33:03.523225 DramcWriteLeveling(PI) end<-----
844 01:33:03.523278
845 01:33:03.523330 ==
846 01:33:03.523382 Dram Type= 6, Freq= 0, CH_0, rank 0
847 01:33:03.523435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 01:33:03.523488 ==
849 01:33:03.523541 [Gating] SW mode calibration
850 01:33:03.523593 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 01:33:03.523647 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 01:33:03.523700 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 01:33:03.523752 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 01:33:03.523805 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 01:33:03.523858 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 01:33:03.523910 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:33:03.523962 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:33:03.524015 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:33:03.524067 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:33:03.524119 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:33:03.524171 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:33:03.524224 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:33:03.524276 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:33:03.524329 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:33:03.524381 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 01:33:03.524433 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:33:03.524486 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:33:03.524538 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:33:03.524591 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 01:33:03.524644 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 01:33:03.524695 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 01:33:03.524748 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 01:33:03.524800 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 01:33:03.524852 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 01:33:03.524904 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:33:03.524956 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:33:03.525008 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
878 01:33:03.525061 0 9 8 | B1->B0 | 2322 2b2b | 1 0 | (0 0) (0 0)
879 01:33:03.525113 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
880 01:33:03.525166 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 01:33:03.525411 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 01:33:03.525471 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 01:33:03.525525 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 01:33:03.525578 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 01:33:03.525631 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
886 01:33:03.525684 0 10 8 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (1 1)
887 01:33:03.525738 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
888 01:33:03.525791 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 01:33:03.525844 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 01:33:03.525897 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 01:33:03.525949 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 01:33:03.526002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 01:33:03.526053 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 01:33:03.526106 0 11 8 | B1->B0 | 2525 3a3a | 0 1 | (0 0) (0 0)
895 01:33:03.526159 0 11 12 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
896 01:33:03.526258 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 01:33:03.526311 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 01:33:03.526364 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 01:33:03.526416 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 01:33:03.526468 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 01:33:03.526520 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 01:33:03.526573 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 01:33:03.526625 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 01:33:03.526677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 01:33:03.526730 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:33:03.526782 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:33:03.526835 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:33:03.526888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:33:03.526940 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:33:03.526993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:33:03.527045 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:33:03.527101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 01:33:03.527154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 01:33:03.527206 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 01:33:03.527258 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 01:33:03.527310 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 01:33:03.527363 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 01:33:03.527415 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 01:33:03.527467 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 01:33:03.527519 Total UI for P1: 0, mck2ui 16
921 01:33:03.527572 best dqsien dly found for B0: ( 0, 14, 8)
922 01:33:03.527625 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 01:33:03.527677 Total UI for P1: 0, mck2ui 16
924 01:33:03.527739 best dqsien dly found for B1: ( 0, 14, 12)
925 01:33:03.527797 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 01:33:03.527856 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
927 01:33:03.527919
928 01:33:03.527974 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 01:33:03.528028 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
930 01:33:03.528080 [Gating] SW calibration Done
931 01:33:03.528132 ==
932 01:33:03.528185 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:33:03.528238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:33:03.528299 ==
935 01:33:03.528365 RX Vref Scan: 0
936 01:33:03.528419
937 01:33:03.528472 RX Vref 0 -> 0, step: 1
938 01:33:03.528525
939 01:33:03.528578 RX Delay -130 -> 252, step: 16
940 01:33:03.528630 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 01:33:03.528683 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 01:33:03.528736 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 01:33:03.528789 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 01:33:03.528841 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 01:33:03.528893 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 01:33:03.528945 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 01:33:03.528998 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 01:33:03.529050 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 01:33:03.529102 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 01:33:03.529155 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 01:33:03.529207 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 01:33:03.529259 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 01:33:03.529311 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 01:33:03.529364 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 01:33:03.529416 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 01:33:03.529468 ==
957 01:33:03.529520 Dram Type= 6, Freq= 0, CH_0, rank 0
958 01:33:03.529573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 01:33:03.529653 ==
960 01:33:03.529740 DQS Delay:
961 01:33:03.529829 DQS0 = 0, DQS1 = 0
962 01:33:03.529927 DQM Delay:
963 01:33:03.530024 DQM0 = 86, DQM1 = 74
964 01:33:03.530120 DQ Delay:
965 01:33:03.530227 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 01:33:03.530318 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
967 01:33:03.530407 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 01:33:03.530490 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
969 01:33:03.530571
970 01:33:03.530652
971 01:33:03.530734 ==
972 01:33:03.530816 Dram Type= 6, Freq= 0, CH_0, rank 0
973 01:33:03.530899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 01:33:03.530981 ==
975 01:33:03.531062
976 01:33:03.531143
977 01:33:03.531225 TX Vref Scan disable
978 01:33:03.531326 == TX Byte 0 ==
979 01:33:03.531425 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 01:33:03.531509 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 01:33:03.531591 == TX Byte 1 ==
982 01:33:03.531673 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 01:33:03.531755 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 01:33:03.531837 ==
985 01:33:03.531919 Dram Type= 6, Freq= 0, CH_0, rank 0
986 01:33:03.532002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 01:33:03.532084 ==
988 01:33:03.532166 TX Vref=22, minBit 4, minWin=27, winSum=443
989 01:33:03.532446 TX Vref=24, minBit 8, minWin=27, winSum=445
990 01:33:03.532537 TX Vref=26, minBit 8, minWin=27, winSum=448
991 01:33:03.532620 TX Vref=28, minBit 8, minWin=27, winSum=448
992 01:33:03.532703 TX Vref=30, minBit 8, minWin=27, winSum=448
993 01:33:03.532786 TX Vref=32, minBit 11, minWin=26, winSum=444
994 01:33:03.532869 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 26
995 01:33:03.532951
996 01:33:03.533033 Final TX Range 1 Vref 26
997 01:33:03.533115
998 01:33:03.533196 ==
999 01:33:03.533278 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 01:33:03.533361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 01:33:03.533443 ==
1002 01:33:03.533524
1003 01:33:03.533605
1004 01:33:03.533686 TX Vref Scan disable
1005 01:33:03.533768 == TX Byte 0 ==
1006 01:33:03.533850 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 01:33:03.533932 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 01:33:03.534015 == TX Byte 1 ==
1009 01:33:03.534097 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 01:33:03.534204 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 01:33:03.534301
1012 01:33:03.534384 [DATLAT]
1013 01:33:03.534466 Freq=800, CH0 RK0
1014 01:33:03.534548
1015 01:33:03.534629 DATLAT Default: 0xa
1016 01:33:03.534711 0, 0xFFFF, sum = 0
1017 01:33:03.534795 1, 0xFFFF, sum = 0
1018 01:33:03.534879 2, 0xFFFF, sum = 0
1019 01:33:03.534962 3, 0xFFFF, sum = 0
1020 01:33:03.535046 4, 0xFFFF, sum = 0
1021 01:33:03.535129 5, 0xFFFF, sum = 0
1022 01:33:03.535212 6, 0xFFFF, sum = 0
1023 01:33:03.535296 7, 0xFFFF, sum = 0
1024 01:33:03.535380 8, 0xFFFF, sum = 0
1025 01:33:03.535456 9, 0x0, sum = 1
1026 01:33:03.535518 10, 0x0, sum = 2
1027 01:33:03.535574 11, 0x0, sum = 3
1028 01:33:03.535644 12, 0x0, sum = 4
1029 01:33:03.535706 best_step = 10
1030 01:33:03.535771
1031 01:33:03.535827 ==
1032 01:33:03.535882 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 01:33:03.535938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 01:33:03.535992 ==
1035 01:33:03.536046 RX Vref Scan: 1
1036 01:33:03.536100
1037 01:33:03.536160 Set Vref Range= 32 -> 127
1038 01:33:03.536224
1039 01:33:03.536279 RX Vref 32 -> 127, step: 1
1040 01:33:03.536333
1041 01:33:03.536385 RX Delay -111 -> 252, step: 8
1042 01:33:03.536438
1043 01:33:03.536491 Set Vref, RX VrefLevel [Byte0]: 32
1044 01:33:03.536544 [Byte1]: 32
1045 01:33:03.536597
1046 01:33:03.536650 Set Vref, RX VrefLevel [Byte0]: 33
1047 01:33:03.536703 [Byte1]: 33
1048 01:33:03.536755
1049 01:33:03.536808 Set Vref, RX VrefLevel [Byte0]: 34
1050 01:33:03.536861 [Byte1]: 34
1051 01:33:03.536913
1052 01:33:03.536966 Set Vref, RX VrefLevel [Byte0]: 35
1053 01:33:03.537050 [Byte1]: 35
1054 01:33:03.537102
1055 01:33:03.537154 Set Vref, RX VrefLevel [Byte0]: 36
1056 01:33:03.537207 [Byte1]: 36
1057 01:33:03.537259
1058 01:33:03.537311 Set Vref, RX VrefLevel [Byte0]: 37
1059 01:33:03.537364 [Byte1]: 37
1060 01:33:03.537417
1061 01:33:03.537496 Set Vref, RX VrefLevel [Byte0]: 38
1062 01:33:03.537584 [Byte1]: 38
1063 01:33:03.537666
1064 01:33:03.537747 Set Vref, RX VrefLevel [Byte0]: 39
1065 01:33:03.537829 [Byte1]: 39
1066 01:33:03.537910
1067 01:33:03.537992 Set Vref, RX VrefLevel [Byte0]: 40
1068 01:33:03.538073 [Byte1]: 40
1069 01:33:03.538154
1070 01:33:03.538246 Set Vref, RX VrefLevel [Byte0]: 41
1071 01:33:03.538300 [Byte1]: 41
1072 01:33:03.538354
1073 01:33:03.538406 Set Vref, RX VrefLevel [Byte0]: 42
1074 01:33:03.538459 [Byte1]: 42
1075 01:33:03.538512
1076 01:33:03.538565 Set Vref, RX VrefLevel [Byte0]: 43
1077 01:33:03.538618 [Byte1]: 43
1078 01:33:03.538671
1079 01:33:03.538723 Set Vref, RX VrefLevel [Byte0]: 44
1080 01:33:03.538776 [Byte1]: 44
1081 01:33:03.538829
1082 01:33:03.538881 Set Vref, RX VrefLevel [Byte0]: 45
1083 01:33:03.538933 [Byte1]: 45
1084 01:33:03.538986
1085 01:33:03.539039 Set Vref, RX VrefLevel [Byte0]: 46
1086 01:33:03.539107 [Byte1]: 46
1087 01:33:03.539161
1088 01:33:03.539219 Set Vref, RX VrefLevel [Byte0]: 47
1089 01:33:03.539283 [Byte1]: 47
1090 01:33:03.539336
1091 01:33:03.539389 Set Vref, RX VrefLevel [Byte0]: 48
1092 01:33:03.539472 [Byte1]: 48
1093 01:33:03.539575
1094 01:33:03.539634 Set Vref, RX VrefLevel [Byte0]: 49
1095 01:33:03.539701 [Byte1]: 49
1096 01:33:03.539758
1097 01:33:03.539811 Set Vref, RX VrefLevel [Byte0]: 50
1098 01:33:03.539865 [Byte1]: 50
1099 01:33:03.539918
1100 01:33:03.539971 Set Vref, RX VrefLevel [Byte0]: 51
1101 01:33:03.540024 [Byte1]: 51
1102 01:33:03.540076
1103 01:33:03.540129 Set Vref, RX VrefLevel [Byte0]: 52
1104 01:33:03.540182 [Byte1]: 52
1105 01:33:03.540234
1106 01:33:03.540286 Set Vref, RX VrefLevel [Byte0]: 53
1107 01:33:03.540339 [Byte1]: 53
1108 01:33:03.540391
1109 01:33:03.540445 Set Vref, RX VrefLevel [Byte0]: 54
1110 01:33:03.540497 [Byte1]: 54
1111 01:33:03.540549
1112 01:33:03.540602 Set Vref, RX VrefLevel [Byte0]: 55
1113 01:33:03.540655 [Byte1]: 55
1114 01:33:03.540708
1115 01:33:03.540760 Set Vref, RX VrefLevel [Byte0]: 56
1116 01:33:03.540813 [Byte1]: 56
1117 01:33:03.540866
1118 01:33:03.540918 Set Vref, RX VrefLevel [Byte0]: 57
1119 01:33:03.540971 [Byte1]: 57
1120 01:33:03.541024
1121 01:33:03.541076 Set Vref, RX VrefLevel [Byte0]: 58
1122 01:33:03.541129 [Byte1]: 58
1123 01:33:03.541181
1124 01:33:03.541234 Set Vref, RX VrefLevel [Byte0]: 59
1125 01:33:03.541287 [Byte1]: 59
1126 01:33:03.541339
1127 01:33:03.541392 Set Vref, RX VrefLevel [Byte0]: 60
1128 01:33:03.541444 [Byte1]: 60
1129 01:33:03.541497
1130 01:33:03.541550 Set Vref, RX VrefLevel [Byte0]: 61
1131 01:33:03.541603 [Byte1]: 61
1132 01:33:03.541655
1133 01:33:03.541707 Set Vref, RX VrefLevel [Byte0]: 62
1134 01:33:03.541760 [Byte1]: 62
1135 01:33:03.541813
1136 01:33:03.541865 Set Vref, RX VrefLevel [Byte0]: 63
1137 01:33:03.541917 [Byte1]: 63
1138 01:33:03.541970
1139 01:33:03.542022 Set Vref, RX VrefLevel [Byte0]: 64
1140 01:33:03.542075 [Byte1]: 64
1141 01:33:03.542127
1142 01:33:03.542210 Set Vref, RX VrefLevel [Byte0]: 65
1143 01:33:03.542278 [Byte1]: 65
1144 01:33:03.542331
1145 01:33:03.542383 Set Vref, RX VrefLevel [Byte0]: 66
1146 01:33:03.542436 [Byte1]: 66
1147 01:33:03.542489
1148 01:33:03.542541 Set Vref, RX VrefLevel [Byte0]: 67
1149 01:33:03.542594 [Byte1]: 67
1150 01:33:03.542647
1151 01:33:03.542699 Set Vref, RX VrefLevel [Byte0]: 68
1152 01:33:03.542751 [Byte1]: 68
1153 01:33:03.542804
1154 01:33:03.542857 Set Vref, RX VrefLevel [Byte0]: 69
1155 01:33:03.542910 [Byte1]: 69
1156 01:33:03.542962
1157 01:33:03.543207 Set Vref, RX VrefLevel [Byte0]: 70
1158 01:33:03.543269 [Byte1]: 70
1159 01:33:03.543324
1160 01:33:03.543377 Set Vref, RX VrefLevel [Byte0]: 71
1161 01:33:03.543430 [Byte1]: 71
1162 01:33:03.543482
1163 01:33:03.543535 Set Vref, RX VrefLevel [Byte0]: 72
1164 01:33:03.543588 [Byte1]: 72
1165 01:33:03.543640
1166 01:33:03.543693 Set Vref, RX VrefLevel [Byte0]: 73
1167 01:33:03.543746 [Byte1]: 73
1168 01:33:03.543799
1169 01:33:03.543851 Set Vref, RX VrefLevel [Byte0]: 74
1170 01:33:03.543904 [Byte1]: 74
1171 01:33:03.543956
1172 01:33:03.544009 Set Vref, RX VrefLevel [Byte0]: 75
1173 01:33:03.544062 [Byte1]: 75
1174 01:33:03.544114
1175 01:33:03.544167 Set Vref, RX VrefLevel [Byte0]: 76
1176 01:33:03.544220 [Byte1]: 76
1177 01:33:03.544272
1178 01:33:03.544325 Set Vref, RX VrefLevel [Byte0]: 77
1179 01:33:03.544378 [Byte1]: 77
1180 01:33:03.544431
1181 01:33:03.544483 Set Vref, RX VrefLevel [Byte0]: 78
1182 01:33:03.544535 [Byte1]: 78
1183 01:33:03.544588
1184 01:33:03.544640 Set Vref, RX VrefLevel [Byte0]: 79
1185 01:33:03.544693 [Byte1]: 79
1186 01:33:03.544745
1187 01:33:03.544797 Set Vref, RX VrefLevel [Byte0]: 80
1188 01:33:03.544850 [Byte1]: 80
1189 01:33:03.544903
1190 01:33:03.544955 Set Vref, RX VrefLevel [Byte0]: 81
1191 01:33:03.545008 [Byte1]: 81
1192 01:33:03.545060
1193 01:33:03.545113 Set Vref, RX VrefLevel [Byte0]: 82
1194 01:33:03.545165 [Byte1]: 82
1195 01:33:03.545218
1196 01:33:03.545271 Set Vref, RX VrefLevel [Byte0]: 83
1197 01:33:03.545324 [Byte1]: 83
1198 01:33:03.545376
1199 01:33:03.545429 Final RX Vref Byte 0 = 61 to rank0
1200 01:33:03.545482 Final RX Vref Byte 1 = 52 to rank0
1201 01:33:03.545535 Final RX Vref Byte 0 = 61 to rank1
1202 01:33:03.545588 Final RX Vref Byte 1 = 52 to rank1==
1203 01:33:03.545641 Dram Type= 6, Freq= 0, CH_0, rank 0
1204 01:33:03.545693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 01:33:03.545746 ==
1206 01:33:03.545798 DQS Delay:
1207 01:33:03.545851 DQS0 = 0, DQS1 = 0
1208 01:33:03.545903 DQM Delay:
1209 01:33:03.545956 DQM0 = 87, DQM1 = 76
1210 01:33:03.546008 DQ Delay:
1211 01:33:03.546061 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1212 01:33:03.546114 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1213 01:33:03.546200 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1214 01:33:03.546271 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1215 01:33:03.546324
1216 01:33:03.546377
1217 01:33:03.546429 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 394 ps
1218 01:33:03.546483 CH0 RK0: MR19=606, MR18=3E1F
1219 01:33:03.546536 CH0_RK0: MR19=0x606, MR18=0x3E1F, DQSOSC=394, MR23=63, INC=95, DEC=63
1220 01:33:03.546589
1221 01:33:03.546642 ----->DramcWriteLeveling(PI) begin...
1222 01:33:03.546696 ==
1223 01:33:03.546749 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 01:33:03.546801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 01:33:03.546855 ==
1226 01:33:03.546907 Write leveling (Byte 0): 33 => 33
1227 01:33:03.546960 Write leveling (Byte 1): 31 => 31
1228 01:33:03.547012 DramcWriteLeveling(PI) end<-----
1229 01:33:03.547064
1230 01:33:03.547117 ==
1231 01:33:03.547169 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 01:33:03.547222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 01:33:03.547275 ==
1234 01:33:03.547327 [Gating] SW mode calibration
1235 01:33:03.547380 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1236 01:33:03.547434 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1237 01:33:03.547487 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1238 01:33:03.547540 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1239 01:33:03.547592 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1240 01:33:03.547645 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 01:33:03.547697 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 01:33:03.547750 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 01:33:03.547802 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 01:33:03.547854 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 01:33:03.547907 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 01:33:03.547959 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 01:33:03.548011 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 01:33:03.548064 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 01:33:03.548116 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 01:33:03.548169 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 01:33:03.548221 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 01:33:03.548274 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 01:33:03.548326 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 01:33:03.548379 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 01:33:03.548432 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1256 01:33:03.548484 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1257 01:33:03.548537 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 01:33:03.548589 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 01:33:03.548642 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 01:33:03.548694 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 01:33:03.548747 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 01:33:03.548799 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 01:33:03.548851 0 9 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1264 01:33:03.548904 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 01:33:03.548956 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 01:33:03.549009 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 01:33:03.549061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 01:33:03.549113 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 01:33:03.549166 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 01:33:03.549218 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1271 01:33:03.549271 0 10 8 | B1->B0 | 3030 2a2a | 1 0 | (1 0) (0 0)
1272 01:33:03.549323 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1273 01:33:03.549569 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 01:33:03.549627 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 01:33:03.549719 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 01:33:03.549772 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 01:33:03.549825 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 01:33:03.549878 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1279 01:33:03.549931 0 11 8 | B1->B0 | 2929 3e3e | 0 0 | (1 1) (0 0)
1280 01:33:03.549984 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1281 01:33:03.550052 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 01:33:03.550106 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 01:33:03.550165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 01:33:03.550223 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 01:33:03.550277 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 01:33:03.550331 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 01:33:03.550426 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1288 01:33:03.550478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 01:33:03.550531 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 01:33:03.550583 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 01:33:03.550635 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 01:33:03.550687 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 01:33:03.550739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 01:33:03.550791 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 01:33:03.550843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 01:33:03.550895 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 01:33:03.550947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 01:33:03.550999 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 01:33:03.551052 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 01:33:03.551105 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 01:33:03.551157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 01:33:03.551210 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1303 01:33:03.551262 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1304 01:33:03.551314 Total UI for P1: 0, mck2ui 16
1305 01:33:03.551367 best dqsien dly found for B0: ( 0, 14, 4)
1306 01:33:03.551420 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1307 01:33:03.551473 Total UI for P1: 0, mck2ui 16
1308 01:33:03.551526 best dqsien dly found for B1: ( 0, 14, 6)
1309 01:33:03.551579 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1310 01:33:03.551632 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1311 01:33:03.551685
1312 01:33:03.551737 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1313 01:33:03.551790 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1314 01:33:03.551843 [Gating] SW calibration Done
1315 01:33:03.551895 ==
1316 01:33:03.551948 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 01:33:03.552001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 01:33:03.552054 ==
1319 01:33:03.552106 RX Vref Scan: 0
1320 01:33:03.552159
1321 01:33:03.552211 RX Vref 0 -> 0, step: 1
1322 01:33:03.552263
1323 01:33:03.552316 RX Delay -130 -> 252, step: 16
1324 01:33:03.552369 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1325 01:33:03.552422 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1326 01:33:03.552474 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1327 01:33:03.552526 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1328 01:33:03.552578 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1329 01:33:03.552629 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1330 01:33:03.552682 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1331 01:33:03.552734 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1332 01:33:03.552787 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1333 01:33:03.552839 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1334 01:33:03.552891 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1335 01:33:03.552943 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1336 01:33:03.552995 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1337 01:33:03.553048 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1338 01:33:03.553100 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1339 01:33:03.553152 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1340 01:33:03.553205 ==
1341 01:33:03.553257 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 01:33:03.553310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 01:33:03.553362 ==
1344 01:33:03.553414 DQS Delay:
1345 01:33:03.553482 DQS0 = 0, DQS1 = 0
1346 01:33:03.553548 DQM Delay:
1347 01:33:03.553599 DQM0 = 84, DQM1 = 77
1348 01:33:03.553652 DQ Delay:
1349 01:33:03.553705 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1350 01:33:03.553757 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1351 01:33:03.553810 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1352 01:33:03.553862 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1353 01:33:03.553915
1354 01:33:03.553967
1355 01:33:03.554019 ==
1356 01:33:03.554072 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 01:33:03.554125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 01:33:03.554212 ==
1359 01:33:03.554266
1360 01:33:03.554318
1361 01:33:03.554369 TX Vref Scan disable
1362 01:33:03.554421 == TX Byte 0 ==
1363 01:33:03.554473 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1364 01:33:03.554525 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1365 01:33:03.554578 == TX Byte 1 ==
1366 01:33:03.554630 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1367 01:33:03.554682 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1368 01:33:03.554734 ==
1369 01:33:03.554786 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 01:33:03.554839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 01:33:03.554891 ==
1372 01:33:03.554943 TX Vref=22, minBit 3, minWin=27, winSum=442
1373 01:33:03.554996 TX Vref=24, minBit 8, minWin=27, winSum=445
1374 01:33:03.555048 TX Vref=26, minBit 9, minWin=27, winSum=448
1375 01:33:03.555100 TX Vref=28, minBit 8, minWin=27, winSum=449
1376 01:33:03.555152 TX Vref=30, minBit 9, minWin=27, winSum=449
1377 01:33:03.555204 TX Vref=32, minBit 9, minWin=27, winSum=447
1378 01:33:03.555257 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 28
1379 01:33:03.555309
1380 01:33:03.555361 Final TX Range 1 Vref 28
1381 01:33:03.555414
1382 01:33:03.555465 ==
1383 01:33:03.555518 Dram Type= 6, Freq= 0, CH_0, rank 1
1384 01:33:03.555570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 01:33:03.555815 ==
1386 01:33:03.555874
1387 01:33:03.555927
1388 01:33:03.555979 TX Vref Scan disable
1389 01:33:03.556032 == TX Byte 0 ==
1390 01:33:03.556084 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1391 01:33:03.556137 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1392 01:33:03.556189 == TX Byte 1 ==
1393 01:33:03.556241 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1394 01:33:03.556294 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1395 01:33:03.556346
1396 01:33:03.556397 [DATLAT]
1397 01:33:03.556449 Freq=800, CH0 RK1
1398 01:33:03.556502
1399 01:33:03.556554 DATLAT Default: 0xa
1400 01:33:03.556605 0, 0xFFFF, sum = 0
1401 01:33:03.556658 1, 0xFFFF, sum = 0
1402 01:33:03.556712 2, 0xFFFF, sum = 0
1403 01:33:03.556765 3, 0xFFFF, sum = 0
1404 01:33:03.556817 4, 0xFFFF, sum = 0
1405 01:33:03.556870 5, 0xFFFF, sum = 0
1406 01:33:03.556922 6, 0xFFFF, sum = 0
1407 01:33:03.556974 7, 0xFFFF, sum = 0
1408 01:33:03.557027 8, 0xFFFF, sum = 0
1409 01:33:03.557080 9, 0x0, sum = 1
1410 01:33:03.557132 10, 0x0, sum = 2
1411 01:33:03.557185 11, 0x0, sum = 3
1412 01:33:03.557237 12, 0x0, sum = 4
1413 01:33:03.557290 best_step = 10
1414 01:33:03.557342
1415 01:33:03.557393 ==
1416 01:33:03.557445 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 01:33:03.557497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 01:33:03.557551 ==
1419 01:33:03.557603 RX Vref Scan: 0
1420 01:33:03.557654
1421 01:33:03.557706 RX Vref 0 -> 0, step: 1
1422 01:33:03.557758
1423 01:33:03.557810 RX Delay -111 -> 252, step: 8
1424 01:33:03.557862 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1425 01:33:03.557915 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1426 01:33:03.557967 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1427 01:33:03.558019 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1428 01:33:03.558074 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1429 01:33:03.558168 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1430 01:33:03.558262 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1431 01:33:03.558316 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1432 01:33:03.558368 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1433 01:33:03.558421 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1434 01:33:03.558473 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1435 01:33:03.558525 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1436 01:33:03.558577 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1437 01:33:03.558628 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1438 01:33:03.558680 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1439 01:33:03.558732 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1440 01:33:03.558784 ==
1441 01:33:03.558837 Dram Type= 6, Freq= 0, CH_0, rank 1
1442 01:33:03.558890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 01:33:03.558944 ==
1444 01:33:03.558996 DQS Delay:
1445 01:33:03.559048 DQS0 = 0, DQS1 = 0
1446 01:33:03.559100 DQM Delay:
1447 01:33:03.559152 DQM0 = 86, DQM1 = 77
1448 01:33:03.559204 DQ Delay:
1449 01:33:03.559256 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1450 01:33:03.559308 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1451 01:33:03.559359 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1452 01:33:03.559412 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1453 01:33:03.559463
1454 01:33:03.559515
1455 01:33:03.559566 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e06, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
1456 01:33:03.559619 CH0 RK1: MR19=606, MR18=3E06
1457 01:33:03.559671 CH0_RK1: MR19=0x606, MR18=0x3E06, DQSOSC=394, MR23=63, INC=95, DEC=63
1458 01:33:03.559724 [RxdqsGatingPostProcess] freq 800
1459 01:33:03.559776 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1460 01:33:03.559829 Pre-setting of DQS Precalculation
1461 01:33:03.559880 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1462 01:33:03.559933 ==
1463 01:33:03.559985 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 01:33:03.560037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 01:33:03.560090 ==
1466 01:33:03.560142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 01:33:03.560195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 01:33:03.560247 [CA 0] Center 36 (6~67) winsize 62
1469 01:33:03.560300 [CA 1] Center 36 (6~67) winsize 62
1470 01:33:03.560352 [CA 2] Center 34 (4~65) winsize 62
1471 01:33:03.560404 [CA 3] Center 34 (3~65) winsize 63
1472 01:33:03.560456 [CA 4] Center 34 (4~65) winsize 62
1473 01:33:03.560508 [CA 5] Center 33 (3~64) winsize 62
1474 01:33:03.560560
1475 01:33:03.560612 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1476 01:33:03.560664
1477 01:33:03.560716 [CATrainingPosCal] consider 1 rank data
1478 01:33:03.560768 u2DelayCellTimex100 = 270/100 ps
1479 01:33:03.560820 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1480 01:33:03.560873 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1481 01:33:03.560925 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1482 01:33:03.560978 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1483 01:33:03.561031 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1484 01:33:03.561083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1485 01:33:03.561134
1486 01:33:03.561187 CA PerBit enable=1, Macro0, CA PI delay=33
1487 01:33:03.561239
1488 01:33:03.561291 [CBTSetCACLKResult] CA Dly = 33
1489 01:33:03.561343 CS Dly: 5 (0~36)
1490 01:33:03.561395 ==
1491 01:33:03.561448 Dram Type= 6, Freq= 0, CH_1, rank 1
1492 01:33:03.561500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 01:33:03.561553 ==
1494 01:33:03.561605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1495 01:33:03.561657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1496 01:33:03.561709 [CA 0] Center 36 (6~67) winsize 62
1497 01:33:03.561760 [CA 1] Center 37 (6~68) winsize 63
1498 01:33:03.561812 [CA 2] Center 34 (4~65) winsize 62
1499 01:33:03.561864 [CA 3] Center 34 (3~65) winsize 63
1500 01:33:03.561916 [CA 4] Center 34 (4~65) winsize 62
1501 01:33:03.561968 [CA 5] Center 34 (4~64) winsize 61
1502 01:33:03.562019
1503 01:33:03.562071 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1504 01:33:03.562123
1505 01:33:03.562203 [CATrainingPosCal] consider 2 rank data
1506 01:33:03.562272 u2DelayCellTimex100 = 270/100 ps
1507 01:33:03.562324 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1508 01:33:03.562376 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1509 01:33:03.562428 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1510 01:33:03.562480 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1511 01:33:03.562532 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1512 01:33:03.562583 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1513 01:33:03.562635
1514 01:33:03.562687 CA PerBit enable=1, Macro0, CA PI delay=34
1515 01:33:03.562739
1516 01:33:03.562791 [CBTSetCACLKResult] CA Dly = 34
1517 01:33:03.562842 CS Dly: 6 (0~38)
1518 01:33:03.562893
1519 01:33:03.562945 ----->DramcWriteLeveling(PI) begin...
1520 01:33:03.562998 ==
1521 01:33:03.563244 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 01:33:03.563308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 01:33:03.563394 ==
1524 01:33:03.563447 Write leveling (Byte 0): 25 => 25
1525 01:33:03.563500 Write leveling (Byte 1): 29 => 29
1526 01:33:03.563552 DramcWriteLeveling(PI) end<-----
1527 01:33:03.563604
1528 01:33:03.563656 ==
1529 01:33:03.563708 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 01:33:03.563761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 01:33:03.563813 ==
1532 01:33:03.563865 [Gating] SW mode calibration
1533 01:33:03.563918 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1534 01:33:03.563971 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1535 01:33:03.564023 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1536 01:33:03.564075 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1537 01:33:03.564127 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 01:33:03.564179 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:33:03.564231 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:33:03.564283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 01:33:03.564334 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 01:33:03.564386 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 01:33:03.564438 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 01:33:03.564489 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 01:33:03.564540 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 01:33:03.564592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 01:33:03.564644 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 01:33:03.564696 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 01:33:03.564747 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 01:33:03.564799 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 01:33:03.564850 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1552 01:33:03.564902 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1553 01:33:03.564953 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 01:33:03.565004 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 01:33:03.565056 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 01:33:03.565107 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 01:33:03.565159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 01:33:03.565211 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 01:33:03.565264 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 01:33:03.565315 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 01:33:03.565367 0 9 8 | B1->B0 | 2a2a 3232 | 1 1 | (0 0) (1 1)
1562 01:33:03.565419 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 01:33:03.565471 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 01:33:03.565523 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 01:33:03.565574 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 01:33:03.565626 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 01:33:03.565678 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 01:33:03.565729 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
1569 01:33:03.565780 0 10 8 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
1570 01:33:03.565832 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 01:33:03.565883 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 01:33:03.565935 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 01:33:03.565987 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 01:33:03.566038 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 01:33:03.566090 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 01:33:03.566142 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 1)
1577 01:33:03.566243 0 11 8 | B1->B0 | 3939 3e3e | 0 0 | (1 1) (0 0)
1578 01:33:03.566296 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 01:33:03.566348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 01:33:03.566400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 01:33:03.566452 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 01:33:03.566504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 01:33:03.566556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 01:33:03.566608 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1585 01:33:03.566660 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1586 01:33:03.566712 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 01:33:03.566764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 01:33:03.566815 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 01:33:03.566867 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 01:33:03.566920 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 01:33:03.566972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 01:33:03.567024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 01:33:03.567076 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 01:33:03.567127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 01:33:03.567179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 01:33:03.567231 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 01:33:03.567283 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 01:33:03.567334 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 01:33:03.567386 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 01:33:03.567438 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1601 01:33:03.567490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1602 01:33:03.567542 Total UI for P1: 0, mck2ui 16
1603 01:33:03.567594 best dqsien dly found for B0: ( 0, 14, 4)
1604 01:33:03.567647 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1605 01:33:03.567699 Total UI for P1: 0, mck2ui 16
1606 01:33:03.567752 best dqsien dly found for B1: ( 0, 14, 8)
1607 01:33:03.567993 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1608 01:33:03.568053 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1609 01:33:03.568107
1610 01:33:03.568159 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1611 01:33:03.568213 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1612 01:33:03.568265 [Gating] SW calibration Done
1613 01:33:03.568318 ==
1614 01:33:03.568370 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 01:33:03.568422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 01:33:03.568476 ==
1617 01:33:03.568529 RX Vref Scan: 0
1618 01:33:03.568580
1619 01:33:03.568633 RX Vref 0 -> 0, step: 1
1620 01:33:03.568685
1621 01:33:03.568737 RX Delay -130 -> 252, step: 16
1622 01:33:03.568789 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1623 01:33:03.568842 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1624 01:33:03.568894 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1625 01:33:03.568946 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1626 01:33:03.568998 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1627 01:33:03.569050 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1628 01:33:03.569102 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1629 01:33:03.569155 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1630 01:33:03.569207 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1631 01:33:03.569258 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1632 01:33:03.569309 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1633 01:33:03.569361 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1634 01:33:03.569413 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1635 01:33:03.569465 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1636 01:33:03.569517 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1637 01:33:03.569569 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1638 01:33:03.569621 ==
1639 01:33:03.569673 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 01:33:03.569725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 01:33:03.569778 ==
1642 01:33:03.569831 DQS Delay:
1643 01:33:03.569883 DQS0 = 0, DQS1 = 0
1644 01:33:03.569935 DQM Delay:
1645 01:33:03.569986 DQM0 = 89, DQM1 = 78
1646 01:33:03.570038 DQ Delay:
1647 01:33:03.570090 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1648 01:33:03.570142 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1649 01:33:03.570224 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1650 01:33:03.570290 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1651 01:33:03.570342
1652 01:33:03.570393
1653 01:33:03.570445 ==
1654 01:33:03.570497 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 01:33:03.570550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 01:33:03.570602 ==
1657 01:33:03.570654
1658 01:33:03.570705
1659 01:33:03.570757 TX Vref Scan disable
1660 01:33:03.570809 == TX Byte 0 ==
1661 01:33:03.570861 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1662 01:33:03.570913 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1663 01:33:03.570965 == TX Byte 1 ==
1664 01:33:03.571017 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1665 01:33:03.571069 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1666 01:33:03.571121 ==
1667 01:33:03.571173 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 01:33:03.571225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 01:33:03.571278 ==
1670 01:33:03.571330 TX Vref=22, minBit 8, minWin=26, winSum=438
1671 01:33:03.571384 TX Vref=24, minBit 3, minWin=27, winSum=445
1672 01:33:03.571436 TX Vref=26, minBit 10, minWin=27, winSum=449
1673 01:33:03.571489 TX Vref=28, minBit 8, minWin=27, winSum=446
1674 01:33:03.571541 TX Vref=30, minBit 10, minWin=27, winSum=447
1675 01:33:03.571593 TX Vref=32, minBit 0, minWin=27, winSum=444
1676 01:33:03.571646 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 26
1677 01:33:03.571699
1678 01:33:03.571750 Final TX Range 1 Vref 26
1679 01:33:03.571803
1680 01:33:03.571855 ==
1681 01:33:03.571907 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 01:33:03.571959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 01:33:03.572012 ==
1684 01:33:03.572064
1685 01:33:03.572115
1686 01:33:03.572166 TX Vref Scan disable
1687 01:33:03.572218 == TX Byte 0 ==
1688 01:33:03.572270 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1689 01:33:03.572322 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1690 01:33:03.572374 == TX Byte 1 ==
1691 01:33:03.572426 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1692 01:33:03.572478 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1693 01:33:03.572530
1694 01:33:03.572581 [DATLAT]
1695 01:33:03.572633 Freq=800, CH1 RK0
1696 01:33:03.572685
1697 01:33:03.572736 DATLAT Default: 0xa
1698 01:33:03.572788 0, 0xFFFF, sum = 0
1699 01:33:03.572841 1, 0xFFFF, sum = 0
1700 01:33:03.572893 2, 0xFFFF, sum = 0
1701 01:33:03.572945 3, 0xFFFF, sum = 0
1702 01:33:03.572998 4, 0xFFFF, sum = 0
1703 01:33:03.573050 5, 0xFFFF, sum = 0
1704 01:33:03.573103 6, 0xFFFF, sum = 0
1705 01:33:03.573155 7, 0xFFFF, sum = 0
1706 01:33:03.573214 8, 0xFFFF, sum = 0
1707 01:33:03.573269 9, 0x0, sum = 1
1708 01:33:03.573322 10, 0x0, sum = 2
1709 01:33:03.573374 11, 0x0, sum = 3
1710 01:33:03.573428 12, 0x0, sum = 4
1711 01:33:03.573481 best_step = 10
1712 01:33:03.573533
1713 01:33:03.573585 ==
1714 01:33:03.573637 Dram Type= 6, Freq= 0, CH_1, rank 0
1715 01:33:03.573689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1716 01:33:03.573742 ==
1717 01:33:03.573794 RX Vref Scan: 1
1718 01:33:03.573846
1719 01:33:03.573897 Set Vref Range= 32 -> 127
1720 01:33:03.573949
1721 01:33:03.574001 RX Vref 32 -> 127, step: 1
1722 01:33:03.574053
1723 01:33:03.574104 RX Delay -95 -> 252, step: 8
1724 01:33:03.574156
1725 01:33:03.574245 Set Vref, RX VrefLevel [Byte0]: 32
1726 01:33:03.574298 [Byte1]: 32
1727 01:33:03.574350
1728 01:33:03.574401 Set Vref, RX VrefLevel [Byte0]: 33
1729 01:33:03.574454 [Byte1]: 33
1730 01:33:03.574506
1731 01:33:03.574558 Set Vref, RX VrefLevel [Byte0]: 34
1732 01:33:03.574609 [Byte1]: 34
1733 01:33:03.574661
1734 01:33:03.574713 Set Vref, RX VrefLevel [Byte0]: 35
1735 01:33:03.574765 [Byte1]: 35
1736 01:33:03.574817
1737 01:33:03.574869 Set Vref, RX VrefLevel [Byte0]: 36
1738 01:33:03.574920 [Byte1]: 36
1739 01:33:03.574972
1740 01:33:03.575024 Set Vref, RX VrefLevel [Byte0]: 37
1741 01:33:03.575076 [Byte1]: 37
1742 01:33:03.575128
1743 01:33:03.575179 Set Vref, RX VrefLevel [Byte0]: 38
1744 01:33:03.575231 [Byte1]: 38
1745 01:33:03.575283
1746 01:33:03.575335 Set Vref, RX VrefLevel [Byte0]: 39
1747 01:33:03.575387 [Byte1]: 39
1748 01:33:03.575439
1749 01:33:03.575491 Set Vref, RX VrefLevel [Byte0]: 40
1750 01:33:03.575543 [Byte1]: 40
1751 01:33:03.575595
1752 01:33:03.575646 Set Vref, RX VrefLevel [Byte0]: 41
1753 01:33:03.575698 [Byte1]: 41
1754 01:33:03.575750
1755 01:33:03.575803 Set Vref, RX VrefLevel [Byte0]: 42
1756 01:33:03.575855 [Byte1]: 42
1757 01:33:03.575906
1758 01:33:03.575958 Set Vref, RX VrefLevel [Byte0]: 43
1759 01:33:03.576010 [Byte1]: 43
1760 01:33:03.576062
1761 01:33:03.576114 Set Vref, RX VrefLevel [Byte0]: 44
1762 01:33:03.576354 [Byte1]: 44
1763 01:33:03.576412
1764 01:33:03.576465 Set Vref, RX VrefLevel [Byte0]: 45
1765 01:33:03.576519 [Byte1]: 45
1766 01:33:03.576579
1767 01:33:03.576639 Set Vref, RX VrefLevel [Byte0]: 46
1768 01:33:03.576692 [Byte1]: 46
1769 01:33:03.576744
1770 01:33:03.576797 Set Vref, RX VrefLevel [Byte0]: 47
1771 01:33:03.576849 [Byte1]: 47
1772 01:33:03.576901
1773 01:33:03.576953 Set Vref, RX VrefLevel [Byte0]: 48
1774 01:33:03.577005 [Byte1]: 48
1775 01:33:03.577057
1776 01:33:03.577109 Set Vref, RX VrefLevel [Byte0]: 49
1777 01:33:03.577162 [Byte1]: 49
1778 01:33:03.577225
1779 01:33:03.577297 Set Vref, RX VrefLevel [Byte0]: 50
1780 01:33:03.577378 [Byte1]: 50
1781 01:33:03.577434
1782 01:33:03.577487 Set Vref, RX VrefLevel [Byte0]: 51
1783 01:33:03.577541 [Byte1]: 51
1784 01:33:03.577593
1785 01:33:03.577646 Set Vref, RX VrefLevel [Byte0]: 52
1786 01:33:03.577699 [Byte1]: 52
1787 01:33:03.577751
1788 01:33:03.577804 Set Vref, RX VrefLevel [Byte0]: 53
1789 01:33:03.577856 [Byte1]: 53
1790 01:33:03.577909
1791 01:33:03.577961 Set Vref, RX VrefLevel [Byte0]: 54
1792 01:33:03.578013 [Byte1]: 54
1793 01:33:03.578066
1794 01:33:03.578117 Set Vref, RX VrefLevel [Byte0]: 55
1795 01:33:03.578177 [Byte1]: 55
1796 01:33:03.578271
1797 01:33:03.578323 Set Vref, RX VrefLevel [Byte0]: 56
1798 01:33:03.578375 [Byte1]: 56
1799 01:33:03.578427
1800 01:33:03.578479 Set Vref, RX VrefLevel [Byte0]: 57
1801 01:33:03.578530 [Byte1]: 57
1802 01:33:03.578582
1803 01:33:03.578635 Set Vref, RX VrefLevel [Byte0]: 58
1804 01:33:03.578687 [Byte1]: 58
1805 01:33:03.578739
1806 01:33:03.578792 Set Vref, RX VrefLevel [Byte0]: 59
1807 01:33:03.578844 [Byte1]: 59
1808 01:33:03.578896
1809 01:33:03.578948 Set Vref, RX VrefLevel [Byte0]: 60
1810 01:33:03.579000 [Byte1]: 60
1811 01:33:03.579053
1812 01:33:03.579104 Set Vref, RX VrefLevel [Byte0]: 61
1813 01:33:03.579157 [Byte1]: 61
1814 01:33:03.579208
1815 01:33:03.579260 Set Vref, RX VrefLevel [Byte0]: 62
1816 01:33:03.579312 [Byte1]: 62
1817 01:33:03.579364
1818 01:33:03.579416 Set Vref, RX VrefLevel [Byte0]: 63
1819 01:33:03.579468 [Byte1]: 63
1820 01:33:03.579519
1821 01:33:03.579571 Set Vref, RX VrefLevel [Byte0]: 64
1822 01:33:03.579624 [Byte1]: 64
1823 01:33:03.579675
1824 01:33:03.579728 Set Vref, RX VrefLevel [Byte0]: 65
1825 01:33:03.579780 [Byte1]: 65
1826 01:33:03.579831
1827 01:33:03.579883 Set Vref, RX VrefLevel [Byte0]: 66
1828 01:33:03.579935 [Byte1]: 66
1829 01:33:03.579987
1830 01:33:03.580039 Set Vref, RX VrefLevel [Byte0]: 67
1831 01:33:03.580091 [Byte1]: 67
1832 01:33:03.580142
1833 01:33:03.580194 Set Vref, RX VrefLevel [Byte0]: 68
1834 01:33:03.580246 [Byte1]: 68
1835 01:33:03.580298
1836 01:33:03.580350 Set Vref, RX VrefLevel [Byte0]: 69
1837 01:33:03.580401 [Byte1]: 69
1838 01:33:03.580454
1839 01:33:03.580506 Set Vref, RX VrefLevel [Byte0]: 70
1840 01:33:03.580558 [Byte1]: 70
1841 01:33:03.580610
1842 01:33:03.580661 Set Vref, RX VrefLevel [Byte0]: 71
1843 01:33:03.580713 [Byte1]: 71
1844 01:33:03.580765
1845 01:33:03.580816 Set Vref, RX VrefLevel [Byte0]: 72
1846 01:33:03.580868 [Byte1]: 72
1847 01:33:03.580920
1848 01:33:03.580971 Set Vref, RX VrefLevel [Byte0]: 73
1849 01:33:03.581023 [Byte1]: 73
1850 01:33:03.581075
1851 01:33:03.581127 Set Vref, RX VrefLevel [Byte0]: 74
1852 01:33:03.581179 [Byte1]: 74
1853 01:33:03.581231
1854 01:33:03.581283 Set Vref, RX VrefLevel [Byte0]: 75
1855 01:33:03.581334 [Byte1]: 75
1856 01:33:03.581386
1857 01:33:03.581438 Set Vref, RX VrefLevel [Byte0]: 76
1858 01:33:03.581490 [Byte1]: 76
1859 01:33:03.581542
1860 01:33:03.581594 Set Vref, RX VrefLevel [Byte0]: 77
1861 01:33:03.581646 [Byte1]: 77
1862 01:33:03.581698
1863 01:33:03.581750 Final RX Vref Byte 0 = 55 to rank0
1864 01:33:03.581802 Final RX Vref Byte 1 = 67 to rank0
1865 01:33:03.581854 Final RX Vref Byte 0 = 55 to rank1
1866 01:33:03.581905 Final RX Vref Byte 1 = 67 to rank1==
1867 01:33:03.581957 Dram Type= 6, Freq= 0, CH_1, rank 0
1868 01:33:03.582009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 01:33:03.582062 ==
1870 01:33:03.582114 DQS Delay:
1871 01:33:03.582169 DQS0 = 0, DQS1 = 0
1872 01:33:03.582222 DQM Delay:
1873 01:33:03.582274 DQM0 = 86, DQM1 = 78
1874 01:33:03.582326 DQ Delay:
1875 01:33:03.582378 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1876 01:33:03.582431 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1877 01:33:03.582482 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1878 01:33:03.582534 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1879 01:33:03.582586
1880 01:33:03.582639
1881 01:33:03.582691 [DQSOSCAuto] RK0, (LSB)MR18= 0x321f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1882 01:33:03.582743 CH1 RK0: MR19=606, MR18=321F
1883 01:33:03.582796 CH1_RK0: MR19=0x606, MR18=0x321F, DQSOSC=397, MR23=63, INC=93, DEC=62
1884 01:33:03.582848
1885 01:33:03.582900 ----->DramcWriteLeveling(PI) begin...
1886 01:33:03.582953 ==
1887 01:33:03.583005 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 01:33:03.583057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 01:33:03.583110 ==
1890 01:33:03.583162 Write leveling (Byte 0): 28 => 28
1891 01:33:03.583214 Write leveling (Byte 1): 28 => 28
1892 01:33:03.583266 DramcWriteLeveling(PI) end<-----
1893 01:33:03.583318
1894 01:33:03.583370 ==
1895 01:33:03.583421 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 01:33:03.583474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 01:33:03.583526 ==
1898 01:33:03.583577 [Gating] SW mode calibration
1899 01:33:03.583630 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1900 01:33:03.583683 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1901 01:33:03.583736 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1902 01:33:03.583789 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1903 01:33:03.583841 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 01:33:03.583893 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 01:33:03.583944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 01:33:03.583996 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 01:33:03.584048 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 01:33:03.584100 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 01:33:03.584347 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 01:33:03.584408 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 01:33:03.584463 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 01:33:03.584515 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 01:33:03.584568 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 01:33:03.584620 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 01:33:03.584672 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 01:33:03.584724 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 01:33:03.584777 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 01:33:03.584829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1919 01:33:03.584882 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1920 01:33:03.584933 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 01:33:03.584985 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 01:33:03.585036 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 01:33:03.585088 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 01:33:03.585140 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 01:33:03.585192 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 01:33:03.585244 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1927 01:33:03.585295 0 9 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1928 01:33:03.585347 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 01:33:03.585399 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 01:33:03.585451 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1931 01:33:03.585503 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1932 01:33:03.585555 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1933 01:33:03.585606 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1934 01:33:03.585658 0 10 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1935 01:33:03.585710 0 10 8 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (1 1)
1936 01:33:03.585762 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1937 01:33:03.585814 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 01:33:03.585866 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 01:33:03.585918 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1940 01:33:03.585970 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1941 01:33:03.586021 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1942 01:33:03.586073 0 11 4 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (1 1)
1943 01:33:03.586125 0 11 8 | B1->B0 | 4343 3939 | 0 0 | (0 0) (0 0)
1944 01:33:03.586211 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 01:33:03.586277 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 01:33:03.586330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 01:33:03.586382 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 01:33:03.586434 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 01:33:03.586486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1950 01:33:03.586538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1951 01:33:03.586590 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1952 01:33:03.586643 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 01:33:03.586694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 01:33:03.586746 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 01:33:03.586798 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 01:33:03.586850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 01:33:03.586902 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 01:33:03.586954 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 01:33:03.587006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 01:33:03.587058 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 01:33:03.587110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 01:33:03.587161 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 01:33:03.587213 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 01:33:03.587264 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1965 01:33:03.587316 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1966 01:33:03.587369 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1967 01:33:03.587420 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1968 01:33:03.587472 Total UI for P1: 0, mck2ui 16
1969 01:33:03.587525 best dqsien dly found for B1: ( 0, 14, 6)
1970 01:33:03.587578 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1971 01:33:03.587630 Total UI for P1: 0, mck2ui 16
1972 01:33:03.587682 best dqsien dly found for B0: ( 0, 14, 8)
1973 01:33:03.587735 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1974 01:33:03.587787 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1975 01:33:03.587839
1976 01:33:03.587892 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1977 01:33:03.587944 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1978 01:33:03.587996 [Gating] SW calibration Done
1979 01:33:03.588049 ==
1980 01:33:03.588102 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 01:33:03.588154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 01:33:03.588207 ==
1983 01:33:03.588259 RX Vref Scan: 0
1984 01:33:03.588311
1985 01:33:03.588363 RX Vref 0 -> 0, step: 1
1986 01:33:03.740048
1987 01:33:03.740573 RX Delay -130 -> 252, step: 16
1988 01:33:03.740945 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1989 01:33:03.741292 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1990 01:33:03.741621 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1991 01:33:03.741935 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1992 01:33:03.742301 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1993 01:33:03.742619 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1994 01:33:03.742925 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1995 01:33:03.743231 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1996 01:33:03.743533 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1997 01:33:03.743837 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1998 01:33:03.744138 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1999 01:33:03.744842 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
2000 01:33:03.745190 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
2001 01:33:03.745695 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
2002 01:33:03.746400 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2003 01:33:03.747077 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2004 01:33:03.747606 ==
2005 01:33:03.748089 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 01:33:03.748598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 01:33:03.749071 ==
2008 01:33:03.749539 DQS Delay:
2009 01:33:03.750004 DQS0 = 0, DQS1 = 0
2010 01:33:03.750486 DQM Delay:
2011 01:33:03.750831 DQM0 = 87, DQM1 = 79
2012 01:33:03.751140 DQ Delay:
2013 01:33:03.751444 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
2014 01:33:03.751749 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2015 01:33:03.752051 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
2016 01:33:03.752352 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2017 01:33:03.752650
2018 01:33:03.752946
2019 01:33:03.753243 ==
2020 01:33:03.753540 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 01:33:03.753845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 01:33:03.754148 ==
2023 01:33:03.754692
2024 01:33:03.755070
2025 01:33:03.755375 TX Vref Scan disable
2026 01:33:03.755686 == TX Byte 0 ==
2027 01:33:03.755987 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2028 01:33:03.756290 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2029 01:33:03.756594 == TX Byte 1 ==
2030 01:33:03.756892 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2031 01:33:03.757190 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2032 01:33:03.757523 ==
2033 01:33:03.757830 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 01:33:03.758131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 01:33:03.758655 ==
2036 01:33:03.759004 TX Vref=22, minBit 1, minWin=27, winSum=444
2037 01:33:03.759313 TX Vref=24, minBit 0, minWin=27, winSum=446
2038 01:33:03.759615 TX Vref=26, minBit 13, minWin=27, winSum=452
2039 01:33:03.759951 TX Vref=28, minBit 8, minWin=27, winSum=449
2040 01:33:03.760258 TX Vref=30, minBit 8, minWin=27, winSum=449
2041 01:33:03.760558 TX Vref=32, minBit 8, minWin=27, winSum=448
2042 01:33:03.760881 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 26
2043 01:33:03.761187
2044 01:33:03.761485 Final TX Range 1 Vref 26
2045 01:33:03.761786
2046 01:33:03.762081 ==
2047 01:33:03.762426 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 01:33:03.762732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 01:33:03.763037 ==
2050 01:33:03.763333
2051 01:33:03.763635
2052 01:33:03.763913 TX Vref Scan disable
2053 01:33:03.764197 == TX Byte 0 ==
2054 01:33:03.764464 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2055 01:33:03.764736 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2056 01:33:03.765008 == TX Byte 1 ==
2057 01:33:03.765275 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2058 01:33:03.765545 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2059 01:33:03.765814
2060 01:33:03.766084 [DATLAT]
2061 01:33:03.766393 Freq=800, CH1 RK1
2062 01:33:03.766669
2063 01:33:03.766934 DATLAT Default: 0xa
2064 01:33:03.767230 0, 0xFFFF, sum = 0
2065 01:33:03.767511 1, 0xFFFF, sum = 0
2066 01:33:03.767731 2, 0xFFFF, sum = 0
2067 01:33:03.767925 3, 0xFFFF, sum = 0
2068 01:33:03.768119 4, 0xFFFF, sum = 0
2069 01:33:03.768316 5, 0xFFFF, sum = 0
2070 01:33:03.768511 6, 0xFFFF, sum = 0
2071 01:33:03.768705 7, 0xFFFF, sum = 0
2072 01:33:03.768898 8, 0xFFFF, sum = 0
2073 01:33:03.769095 9, 0x0, sum = 1
2074 01:33:03.769290 10, 0x0, sum = 2
2075 01:33:03.769486 11, 0x0, sum = 3
2076 01:33:03.769679 12, 0x0, sum = 4
2077 01:33:03.769873 best_step = 10
2078 01:33:03.770061
2079 01:33:03.770284 ==
2080 01:33:03.770481 Dram Type= 6, Freq= 0, CH_1, rank 1
2081 01:33:03.770695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2082 01:33:03.770890 ==
2083 01:33:03.771085 RX Vref Scan: 0
2084 01:33:03.771277
2085 01:33:03.771471 RX Vref 0 -> 0, step: 1
2086 01:33:03.771666
2087 01:33:03.771857 RX Delay -95 -> 252, step: 8
2088 01:33:03.772051 iDelay=217, Bit 0, Center 92 (-15 ~ 200) 216
2089 01:33:03.772247 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2090 01:33:03.772440 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2091 01:33:03.772630 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2092 01:33:03.772776 iDelay=217, Bit 4, Center 88 (-23 ~ 200) 224
2093 01:33:03.772923 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2094 01:33:03.773069 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2095 01:33:03.773215 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2096 01:33:03.773360 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
2097 01:33:03.773505 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2098 01:33:03.773650 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
2099 01:33:03.773796 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2100 01:33:03.773941 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2101 01:33:03.774100 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2102 01:33:03.774271 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2103 01:33:03.774420 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
2104 01:33:03.774567 ==
2105 01:33:03.774715 Dram Type= 6, Freq= 0, CH_1, rank 1
2106 01:33:03.774863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2107 01:33:03.775010 ==
2108 01:33:03.775157 DQS Delay:
2109 01:33:03.775304 DQS0 = 0, DQS1 = 0
2110 01:33:03.775451 DQM Delay:
2111 01:33:03.775596 DQM0 = 88, DQM1 = 76
2112 01:33:03.775741 DQ Delay:
2113 01:33:03.775888 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2114 01:33:03.776035 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
2115 01:33:03.776182 DQ8 =64, DQ9 =68, DQ10 =76, DQ11 =68
2116 01:33:03.776327 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2117 01:33:03.776474
2118 01:33:03.776620
2119 01:33:03.776766 [DQSOSCAuto] RK1, (LSB)MR18= 0x1811, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2120 01:33:03.776957 CH1 RK1: MR19=606, MR18=1811
2121 01:33:03.777130 CH1_RK1: MR19=0x606, MR18=0x1811, DQSOSC=403, MR23=63, INC=90, DEC=60
2122 01:33:03.777281 [RxdqsGatingPostProcess] freq 800
2123 01:33:03.777430 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2124 01:33:03.777586 Pre-setting of DQS Precalculation
2125 01:33:03.777704 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2126 01:33:03.777823 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2127 01:33:03.777943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2128 01:33:03.778060
2129 01:33:03.778187
2130 01:33:03.778305 [Calibration Summary] 1600 Mbps
2131 01:33:03.778425 CH 0, Rank 0
2132 01:33:03.778542 SW Impedance : PASS
2133 01:33:03.778660 DUTY Scan : NO K
2134 01:33:03.778778 ZQ Calibration : PASS
2135 01:33:03.778896 Jitter Meter : NO K
2136 01:33:03.779012 CBT Training : PASS
2137 01:33:03.779129 Write leveling : PASS
2138 01:33:03.779246 RX DQS gating : PASS
2139 01:33:03.779363 RX DQ/DQS(RDDQC) : PASS
2140 01:33:03.779729 TX DQ/DQS : PASS
2141 01:33:03.779935 RX DATLAT : PASS
2142 01:33:03.780120 RX DQ/DQS(Engine): PASS
2143 01:33:03.780301 TX OE : NO K
2144 01:33:03.780482 All Pass.
2145 01:33:03.780662
2146 01:33:03.780842 CH 0, Rank 1
2147 01:33:03.781022 SW Impedance : PASS
2148 01:33:03.781202 DUTY Scan : NO K
2149 01:33:03.781383 ZQ Calibration : PASS
2150 01:33:03.781563 Jitter Meter : NO K
2151 01:33:03.781742 CBT Training : PASS
2152 01:33:03.781921 Write leveling : PASS
2153 01:33:03.782101 RX DQS gating : PASS
2154 01:33:03.782303 RX DQ/DQS(RDDQC) : PASS
2155 01:33:03.782485 TX DQ/DQS : PASS
2156 01:33:03.782655 RX DATLAT : PASS
2157 01:33:03.782805 RX DQ/DQS(Engine): PASS
2158 01:33:03.782956 TX OE : NO K
2159 01:33:03.783106 All Pass.
2160 01:33:03.783257
2161 01:33:03.783407 CH 1, Rank 0
2162 01:33:03.783557 SW Impedance : PASS
2163 01:33:03.783708 DUTY Scan : NO K
2164 01:33:03.783858 ZQ Calibration : PASS
2165 01:33:03.784009 Jitter Meter : NO K
2166 01:33:03.784159 CBT Training : PASS
2167 01:33:03.784310 Write leveling : PASS
2168 01:33:03.784460 RX DQS gating : PASS
2169 01:33:03.784611 RX DQ/DQS(RDDQC) : PASS
2170 01:33:03.784761 TX DQ/DQS : PASS
2171 01:33:03.784911 RX DATLAT : PASS
2172 01:33:03.785061 RX DQ/DQS(Engine): PASS
2173 01:33:03.785211 TX OE : NO K
2174 01:33:03.785361 All Pass.
2175 01:33:03.785511
2176 01:33:03.785661 CH 1, Rank 1
2177 01:33:03.785811 SW Impedance : PASS
2178 01:33:03.785961 DUTY Scan : NO K
2179 01:33:03.786111 ZQ Calibration : PASS
2180 01:33:03.786272 Jitter Meter : NO K
2181 01:33:03.786416 CBT Training : PASS
2182 01:33:03.786518 Write leveling : PASS
2183 01:33:03.786616 RX DQS gating : PASS
2184 01:33:03.786713 RX DQ/DQS(RDDQC) : PASS
2185 01:33:03.786812 TX DQ/DQS : PASS
2186 01:33:03.786910 RX DATLAT : PASS
2187 01:33:03.787009 RX DQ/DQS(Engine): PASS
2188 01:33:03.787106 TX OE : NO K
2189 01:33:03.787204 All Pass.
2190 01:33:03.787303
2191 01:33:03.787400 DramC Write-DBI off
2192 01:33:03.787497 PER_BANK_REFRESH: Hybrid Mode
2193 01:33:03.787603 TX_TRACKING: ON
2194 01:33:03.787687 [GetDramInforAfterCalByMRR] Vendor 6.
2195 01:33:03.787772 [GetDramInforAfterCalByMRR] Revision 606.
2196 01:33:03.787856 [GetDramInforAfterCalByMRR] Revision 2 0.
2197 01:33:03.787940 MR0 0x3b3b
2198 01:33:03.788025 MR8 0x5151
2199 01:33:03.788110 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2200 01:33:03.788195
2201 01:33:03.788278 MR0 0x3b3b
2202 01:33:03.788378 MR8 0x5151
2203 01:33:03.788500 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2204 01:33:03.788624
2205 01:33:03.788712 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2206 01:33:03.788799 [FAST_K] Save calibration result to emmc
2207 01:33:03.788885 [FAST_K] Save calibration result to emmc
2208 01:33:03.788970 dram_init: config_dvfs: 1
2209 01:33:03.789055 dramc_set_vcore_voltage set vcore to 662500
2210 01:33:03.789140 Read voltage for 1200, 2
2211 01:33:03.789224 Vio18 = 0
2212 01:33:03.789309 Vcore = 662500
2213 01:33:03.789394 Vdram = 0
2214 01:33:03.789479 Vddq = 0
2215 01:33:03.789562 Vmddr = 0
2216 01:33:03.789646 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2217 01:33:03.789731 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2218 01:33:03.789815 MEM_TYPE=3, freq_sel=15
2219 01:33:03.789899 sv_algorithm_assistance_LP4_1600
2220 01:33:03.789984 ============ PULL DRAM RESETB DOWN ============
2221 01:33:03.790068 ========== PULL DRAM RESETB DOWN end =========
2222 01:33:03.790153 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2223 01:33:03.790265 ===================================
2224 01:33:03.790354 LPDDR4 DRAM CONFIGURATION
2225 01:33:03.790443 ===================================
2226 01:33:03.790528 EX_ROW_EN[0] = 0x0
2227 01:33:03.790613 EX_ROW_EN[1] = 0x0
2228 01:33:03.790696 LP4Y_EN = 0x0
2229 01:33:03.790780 WORK_FSP = 0x0
2230 01:33:03.790864 WL = 0x4
2231 01:33:03.790953 RL = 0x4
2232 01:33:03.791074 BL = 0x2
2233 01:33:03.791193 RPST = 0x0
2234 01:33:03.791310 RD_PRE = 0x0
2235 01:33:03.791426 WR_PRE = 0x1
2236 01:33:03.791571 WR_PST = 0x0
2237 01:33:03.791686 DBI_WR = 0x0
2238 01:33:03.791830 DBI_RD = 0x0
2239 01:33:03.791974 OTF = 0x1
2240 01:33:03.792120 ===================================
2241 01:33:03.792236 ===================================
2242 01:33:03.792353 ANA top config
2243 01:33:03.792469 ===================================
2244 01:33:03.792595 DLL_ASYNC_EN = 0
2245 01:33:03.792722 ALL_SLAVE_EN = 0
2246 01:33:03.792822 NEW_RANK_MODE = 1
2247 01:33:03.792949 DLL_IDLE_MODE = 1
2248 01:33:03.793077 LP45_APHY_COMB_EN = 1
2249 01:33:03.793204 TX_ODT_DIS = 1
2250 01:33:03.793331 NEW_8X_MODE = 1
2251 01:33:03.793459 ===================================
2252 01:33:03.793587 ===================================
2253 01:33:03.793717 data_rate = 2400
2254 01:33:03.793819 CKR = 1
2255 01:33:03.793947 DQ_P2S_RATIO = 8
2256 01:33:03.794074 ===================================
2257 01:33:03.794210 CA_P2S_RATIO = 8
2258 01:33:03.794338 DQ_CA_OPEN = 0
2259 01:33:03.794465 DQ_SEMI_OPEN = 0
2260 01:33:03.794592 CA_SEMI_OPEN = 0
2261 01:33:03.794719 CA_FULL_RATE = 0
2262 01:33:03.794846 DQ_CKDIV4_EN = 0
2263 01:33:03.794973 CA_CKDIV4_EN = 0
2264 01:33:03.795100 CA_PREDIV_EN = 0
2265 01:33:03.795226 PH8_DLY = 17
2266 01:33:03.795352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2267 01:33:03.795478 DQ_AAMCK_DIV = 4
2268 01:33:03.795605 CA_AAMCK_DIV = 4
2269 01:33:03.795732 CA_ADMCK_DIV = 4
2270 01:33:03.795858 DQ_TRACK_CA_EN = 0
2271 01:33:03.795985 CA_PICK = 1200
2272 01:33:03.796111 CA_MCKIO = 1200
2273 01:33:03.796237 MCKIO_SEMI = 0
2274 01:33:03.796364 PLL_FREQ = 2366
2275 01:33:03.796494 DQ_UI_PI_RATIO = 32
2276 01:33:03.796621 CA_UI_PI_RATIO = 0
2277 01:33:03.796748 ===================================
2278 01:33:03.796880 ===================================
2279 01:33:03.797008 memory_type:LPDDR4
2280 01:33:03.797137 GP_NUM : 10
2281 01:33:03.797264 SRAM_EN : 1
2282 01:33:03.797391 MD32_EN : 0
2283 01:33:03.797517 ===================================
2284 01:33:03.797648 [ANA_INIT] >>>>>>>>>>>>>>
2285 01:33:03.797760 <<<<<< [CONFIGURE PHASE]: ANA_TX
2286 01:33:03.797875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2287 01:33:03.797988 ===================================
2288 01:33:03.798102 data_rate = 2400,PCW = 0X5b00
2289 01:33:03.798446 ===================================
2290 01:33:03.798588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2291 01:33:03.798727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2292 01:33:03.798863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2293 01:33:03.798998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2294 01:33:03.799114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2295 01:33:03.799217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2296 01:33:03.799319 [ANA_INIT] flow start
2297 01:33:03.799421 [ANA_INIT] PLL >>>>>>>>
2298 01:33:03.799523 [ANA_INIT] PLL <<<<<<<<
2299 01:33:03.799625 [ANA_INIT] MIDPI >>>>>>>>
2300 01:33:03.799725 [ANA_INIT] MIDPI <<<<<<<<
2301 01:33:03.799826 [ANA_INIT] DLL >>>>>>>>
2302 01:33:03.799926 [ANA_INIT] DLL <<<<<<<<
2303 01:33:03.800027 [ANA_INIT] flow end
2304 01:33:03.800128 ============ LP4 DIFF to SE enter ============
2305 01:33:03.800231 ============ LP4 DIFF to SE exit ============
2306 01:33:03.800319 [ANA_INIT] <<<<<<<<<<<<<
2307 01:33:03.800386 [Flow] Enable top DCM control >>>>>
2308 01:33:03.800452 [Flow] Enable top DCM control <<<<<
2309 01:33:03.800518 Enable DLL master slave shuffle
2310 01:33:03.800584 ==============================================================
2311 01:33:03.800650 Gating Mode config
2312 01:33:03.800716 ==============================================================
2313 01:33:03.800781 Config description:
2314 01:33:03.800847 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2315 01:33:03.800913 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2316 01:33:03.800979 SELPH_MODE 0: By rank 1: By Phase
2317 01:33:03.801045 ==============================================================
2318 01:33:03.801111 GAT_TRACK_EN = 1
2319 01:33:03.801175 RX_GATING_MODE = 2
2320 01:33:03.801240 RX_GATING_TRACK_MODE = 2
2321 01:33:03.801305 SELPH_MODE = 1
2322 01:33:03.801370 PICG_EARLY_EN = 1
2323 01:33:03.801435 VALID_LAT_VALUE = 1
2324 01:33:03.801500 ==============================================================
2325 01:33:03.801566 Enter into Gating configuration >>>>
2326 01:33:03.801631 Exit from Gating configuration <<<<
2327 01:33:03.801696 Enter into DVFS_PRE_config >>>>>
2328 01:33:03.801761 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2329 01:33:03.801829 Exit from DVFS_PRE_config <<<<<
2330 01:33:03.801894 Enter into PICG configuration >>>>
2331 01:33:03.801959 Exit from PICG configuration <<<<
2332 01:33:03.802024 [RX_INPUT] configuration >>>>>
2333 01:33:03.802090 [RX_INPUT] configuration <<<<<
2334 01:33:03.802155 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2335 01:33:03.802232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2336 01:33:03.802299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2337 01:33:03.802365 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2338 01:33:03.802431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2339 01:33:03.802497 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2340 01:33:03.802563 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2341 01:33:03.802635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2342 01:33:03.802695 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2343 01:33:03.802754 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2344 01:33:03.802813 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2345 01:33:03.802871 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 01:33:03.802931 ===================================
2347 01:33:03.802990 LPDDR4 DRAM CONFIGURATION
2348 01:33:03.803049 ===================================
2349 01:33:03.803109 EX_ROW_EN[0] = 0x0
2350 01:33:03.803167 EX_ROW_EN[1] = 0x0
2351 01:33:03.803236 LP4Y_EN = 0x0
2352 01:33:03.803296 WORK_FSP = 0x0
2353 01:33:03.803355 WL = 0x4
2354 01:33:03.803419 RL = 0x4
2355 01:33:03.803479 BL = 0x2
2356 01:33:03.803538 RPST = 0x0
2357 01:33:03.803596 RD_PRE = 0x0
2358 01:33:03.803654 WR_PRE = 0x1
2359 01:33:03.803712 WR_PST = 0x0
2360 01:33:03.803771 DBI_WR = 0x0
2361 01:33:03.803828 DBI_RD = 0x0
2362 01:33:03.803885 OTF = 0x1
2363 01:33:03.803944 ===================================
2364 01:33:03.804002 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2365 01:33:03.804060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2366 01:33:03.804118 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2367 01:33:03.804176 ===================================
2368 01:33:03.804234 LPDDR4 DRAM CONFIGURATION
2369 01:33:03.804292 ===================================
2370 01:33:03.804349 EX_ROW_EN[0] = 0x10
2371 01:33:03.804408 EX_ROW_EN[1] = 0x0
2372 01:33:03.804465 LP4Y_EN = 0x0
2373 01:33:03.804523 WORK_FSP = 0x0
2374 01:33:03.804580 WL = 0x4
2375 01:33:03.804637 RL = 0x4
2376 01:33:03.804695 BL = 0x2
2377 01:33:03.804753 RPST = 0x0
2378 01:33:03.804810 RD_PRE = 0x0
2379 01:33:03.804868 WR_PRE = 0x1
2380 01:33:03.804925 WR_PST = 0x0
2381 01:33:03.804982 DBI_WR = 0x0
2382 01:33:03.805039 DBI_RD = 0x0
2383 01:33:03.805097 OTF = 0x1
2384 01:33:03.805155 ===================================
2385 01:33:03.805213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2386 01:33:03.805272 ==
2387 01:33:03.805331 Dram Type= 6, Freq= 0, CH_0, rank 0
2388 01:33:03.805390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2389 01:33:03.805449 ==
2390 01:33:03.805508 [Duty_Offset_Calibration]
2391 01:33:03.805566 B0:1 B1:-1 CA:0
2392 01:33:03.805624
2393 01:33:03.805683 [DutyScan_Calibration_Flow] k_type=0
2394 01:33:03.805741
2395 01:33:03.805799 ==CLK 0==
2396 01:33:03.805857 Final CLK duty delay cell = 0
2397 01:33:03.805916 [0] MAX Duty = 5094%(X100), DQS PI = 16
2398 01:33:03.805975 [0] MIN Duty = 4875%(X100), DQS PI = 8
2399 01:33:03.806033 [0] AVG Duty = 4984%(X100)
2400 01:33:03.806091
2401 01:33:03.806150 CH0 CLK Duty spec in!! Max-Min= 219%
2402 01:33:03.806417 [DutyScan_Calibration_Flow] ====Done====
2403 01:33:03.806514
2404 01:33:03.806633 [DutyScan_Calibration_Flow] k_type=1
2405 01:33:03.806749
2406 01:33:03.806867 ==DQS 0 ==
2407 01:33:03.806975 Final DQS duty delay cell = -4
2408 01:33:03.807077 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2409 01:33:03.807170 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2410 01:33:03.807262 [-4] AVG Duty = 4968%(X100)
2411 01:33:03.807352
2412 01:33:03.807443 ==DQS 1 ==
2413 01:33:03.807534 Final DQS duty delay cell = -4
2414 01:33:03.807629 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2415 01:33:03.807684 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2416 01:33:03.807738 [-4] AVG Duty = 4938%(X100)
2417 01:33:03.807795
2418 01:33:03.807850 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2419 01:33:03.807905
2420 01:33:03.807958 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2421 01:33:03.808012 [DutyScan_Calibration_Flow] ====Done====
2422 01:33:03.808065
2423 01:33:03.808119 [DutyScan_Calibration_Flow] k_type=3
2424 01:33:03.808172
2425 01:33:03.808227 ==DQM 0 ==
2426 01:33:03.808287 Final DQM duty delay cell = 0
2427 01:33:03.808341 [0] MAX Duty = 5031%(X100), DQS PI = 16
2428 01:33:03.808394 [0] MIN Duty = 4875%(X100), DQS PI = 6
2429 01:33:03.808448 [0] AVG Duty = 4953%(X100)
2430 01:33:03.808501
2431 01:33:03.808554 ==DQM 1 ==
2432 01:33:03.808608 Final DQM duty delay cell = 4
2433 01:33:03.808661 [4] MAX Duty = 5187%(X100), DQS PI = 14
2434 01:33:03.808715 [4] MIN Duty = 5000%(X100), DQS PI = 24
2435 01:33:03.808767 [4] AVG Duty = 5093%(X100)
2436 01:33:03.808820
2437 01:33:03.808873 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2438 01:33:03.808926
2439 01:33:03.808979 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2440 01:33:03.809032 [DutyScan_Calibration_Flow] ====Done====
2441 01:33:03.809085
2442 01:33:03.809138 [DutyScan_Calibration_Flow] k_type=2
2443 01:33:03.809192
2444 01:33:03.809245 ==DQ 0 ==
2445 01:33:03.809298 Final DQ duty delay cell = -4
2446 01:33:03.809353 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2447 01:33:03.809406 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2448 01:33:03.809460 [-4] AVG Duty = 4969%(X100)
2449 01:33:03.809513
2450 01:33:03.809565 ==DQ 1 ==
2451 01:33:03.809618 Final DQ duty delay cell = -4
2452 01:33:03.809672 [-4] MAX Duty = 4969%(X100), DQS PI = 54
2453 01:33:03.809725 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2454 01:33:03.809778 [-4] AVG Duty = 4922%(X100)
2455 01:33:03.809833
2456 01:33:03.809890 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2457 01:33:03.809943
2458 01:33:03.809996 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2459 01:33:03.810050 [DutyScan_Calibration_Flow] ====Done====
2460 01:33:03.810103 ==
2461 01:33:03.810156 Dram Type= 6, Freq= 0, CH_1, rank 0
2462 01:33:03.810220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 01:33:03.810299 ==
2464 01:33:03.810390 [Duty_Offset_Calibration]
2465 01:33:03.810448 B0:-1 B1:1 CA:1
2466 01:33:03.810502
2467 01:33:03.810556 [DutyScan_Calibration_Flow] k_type=0
2468 01:33:03.810610
2469 01:33:03.810664 ==CLK 0==
2470 01:33:03.810717 Final CLK duty delay cell = 0
2471 01:33:03.810771 [0] MAX Duty = 5156%(X100), DQS PI = 20
2472 01:33:03.810825 [0] MIN Duty = 4969%(X100), DQS PI = 60
2473 01:33:03.810879 [0] AVG Duty = 5062%(X100)
2474 01:33:03.810932
2475 01:33:03.810985 CH1 CLK Duty spec in!! Max-Min= 187%
2476 01:33:03.811039 [DutyScan_Calibration_Flow] ====Done====
2477 01:33:03.811092
2478 01:33:03.811145 [DutyScan_Calibration_Flow] k_type=1
2479 01:33:03.811198
2480 01:33:03.811251 ==DQS 0 ==
2481 01:33:03.811304 Final DQS duty delay cell = 0
2482 01:33:03.811358 [0] MAX Duty = 5125%(X100), DQS PI = 16
2483 01:33:03.811411 [0] MIN Duty = 4875%(X100), DQS PI = 6
2484 01:33:03.811464 [0] AVG Duty = 5000%(X100)
2485 01:33:03.811517
2486 01:33:03.811570 ==DQS 1 ==
2487 01:33:03.811623 Final DQS duty delay cell = 0
2488 01:33:03.811677 [0] MAX Duty = 5062%(X100), DQS PI = 10
2489 01:33:03.811731 [0] MIN Duty = 4969%(X100), DQS PI = 54
2490 01:33:03.811784 [0] AVG Duty = 5015%(X100)
2491 01:33:03.811837
2492 01:33:03.811890 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2493 01:33:03.811944
2494 01:33:03.811998 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2495 01:33:03.812051 [DutyScan_Calibration_Flow] ====Done====
2496 01:33:03.812104
2497 01:33:03.812157 [DutyScan_Calibration_Flow] k_type=3
2498 01:33:03.812210
2499 01:33:03.812263 ==DQM 0 ==
2500 01:33:03.812316 Final DQM duty delay cell = -4
2501 01:33:03.812369 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2502 01:33:03.812422 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2503 01:33:03.812475 [-4] AVG Duty = 4937%(X100)
2504 01:33:03.812528
2505 01:33:03.812593 ==DQM 1 ==
2506 01:33:03.812645 Final DQM duty delay cell = 0
2507 01:33:03.812698 [0] MAX Duty = 5156%(X100), DQS PI = 6
2508 01:33:03.812749 [0] MIN Duty = 4969%(X100), DQS PI = 28
2509 01:33:03.812801 [0] AVG Duty = 5062%(X100)
2510 01:33:03.812853
2511 01:33:03.812904 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2512 01:33:03.812956
2513 01:33:03.813008 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2514 01:33:03.813059 [DutyScan_Calibration_Flow] ====Done====
2515 01:33:03.813111
2516 01:33:03.813163 [DutyScan_Calibration_Flow] k_type=2
2517 01:33:03.813214
2518 01:33:03.813270 ==DQ 0 ==
2519 01:33:03.813323 Final DQ duty delay cell = 0
2520 01:33:03.813376 [0] MAX Duty = 5187%(X100), DQS PI = 30
2521 01:33:03.813429 [0] MIN Duty = 4907%(X100), DQS PI = 6
2522 01:33:03.813480 [0] AVG Duty = 5047%(X100)
2523 01:33:03.813533
2524 01:33:03.813585 ==DQ 1 ==
2525 01:33:03.813637 Final DQ duty delay cell = 0
2526 01:33:03.813690 [0] MAX Duty = 5124%(X100), DQS PI = 10
2527 01:33:03.813742 [0] MIN Duty = 4969%(X100), DQS PI = 34
2528 01:33:03.813794 [0] AVG Duty = 5046%(X100)
2529 01:33:03.813846
2530 01:33:03.813898 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2531 01:33:03.813951
2532 01:33:03.814003 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2533 01:33:03.814060 [DutyScan_Calibration_Flow] ====Done====
2534 01:33:03.814144 nWR fixed to 30
2535 01:33:03.814248 [ModeRegInit_LP4] CH0 RK0
2536 01:33:03.814301 [ModeRegInit_LP4] CH0 RK1
2537 01:33:03.814354 [ModeRegInit_LP4] CH1 RK0
2538 01:33:03.814405 [ModeRegInit_LP4] CH1 RK1
2539 01:33:03.814456 match AC timing 7
2540 01:33:03.814508 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2541 01:33:03.814560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2542 01:33:03.814612 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2543 01:33:03.814665 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2544 01:33:03.814717 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2545 01:33:03.814769 ==
2546 01:33:03.814822 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 01:33:03.814874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 01:33:03.814927 ==
2549 01:33:03.814979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2550 01:33:03.815032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2551 01:33:03.815084 [CA 0] Center 39 (9~70) winsize 62
2552 01:33:03.815136 [CA 1] Center 39 (9~70) winsize 62
2553 01:33:03.815188 [CA 2] Center 35 (5~66) winsize 62
2554 01:33:03.815240 [CA 3] Center 35 (5~66) winsize 62
2555 01:33:03.815486 [CA 4] Center 33 (4~63) winsize 60
2556 01:33:03.815575 [CA 5] Center 33 (3~63) winsize 61
2557 01:33:03.815680
2558 01:33:03.815784 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2559 01:33:03.815889
2560 01:33:03.815981 [CATrainingPosCal] consider 1 rank data
2561 01:33:03.816071 u2DelayCellTimex100 = 270/100 ps
2562 01:33:03.816128 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2563 01:33:03.816181 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2564 01:33:03.816234 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2565 01:33:03.816287 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 01:33:03.816340 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2567 01:33:03.816392 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2568 01:33:03.816443
2569 01:33:03.816496 CA PerBit enable=1, Macro0, CA PI delay=33
2570 01:33:03.816550
2571 01:33:03.816603 [CBTSetCACLKResult] CA Dly = 33
2572 01:33:03.816655 CS Dly: 8 (0~39)
2573 01:33:03.816707 ==
2574 01:33:03.816765 Dram Type= 6, Freq= 0, CH_0, rank 1
2575 01:33:03.816819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 01:33:03.816872 ==
2577 01:33:03.816924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2578 01:33:03.816977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2579 01:33:03.817030 [CA 0] Center 39 (8~70) winsize 63
2580 01:33:03.817082 [CA 1] Center 39 (9~70) winsize 62
2581 01:33:03.817134 [CA 2] Center 35 (5~66) winsize 62
2582 01:33:03.817186 [CA 3] Center 34 (4~65) winsize 62
2583 01:33:03.817238 [CA 4] Center 33 (3~64) winsize 62
2584 01:33:03.817290 [CA 5] Center 33 (3~63) winsize 61
2585 01:33:03.817341
2586 01:33:03.817393 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2587 01:33:03.817445
2588 01:33:03.817497 [CATrainingPosCal] consider 2 rank data
2589 01:33:03.817549 u2DelayCellTimex100 = 270/100 ps
2590 01:33:03.817601 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2591 01:33:03.817652 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2592 01:33:03.817705 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2593 01:33:03.817756 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2594 01:33:03.817808 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2595 01:33:03.817859 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2596 01:33:03.817911
2597 01:33:03.817962 CA PerBit enable=1, Macro0, CA PI delay=33
2598 01:33:03.818014
2599 01:33:03.818066 [CBTSetCACLKResult] CA Dly = 33
2600 01:33:03.818118 CS Dly: 9 (0~41)
2601 01:33:03.818177
2602 01:33:03.818230 ----->DramcWriteLeveling(PI) begin...
2603 01:33:03.818284 ==
2604 01:33:03.818336 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 01:33:03.818388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 01:33:03.818440 ==
2607 01:33:03.818493 Write leveling (Byte 0): 33 => 33
2608 01:33:03.818544 Write leveling (Byte 1): 28 => 28
2609 01:33:03.818597 DramcWriteLeveling(PI) end<-----
2610 01:33:03.818649
2611 01:33:03.818701 ==
2612 01:33:03.818753 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 01:33:03.818806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 01:33:03.818859 ==
2615 01:33:03.818911 [Gating] SW mode calibration
2616 01:33:03.818964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2617 01:33:03.819017 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2618 01:33:03.819069 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2619 01:33:03.819122 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2620 01:33:03.819174 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2621 01:33:03.819226 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2622 01:33:03.819278 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2623 01:33:03.819330 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2624 01:33:03.819381 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2625 01:33:03.819433 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
2626 01:33:03.819485 1 0 0 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2627 01:33:03.819537 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 01:33:03.819589 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2629 01:33:03.819640 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2630 01:33:03.819692 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2631 01:33:03.819744 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2632 01:33:03.819796 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2633 01:33:03.819847 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2634 01:33:03.819899 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2635 01:33:03.819951 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2636 01:33:03.820002 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 01:33:03.820060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 01:33:03.820113 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 01:33:03.820166 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 01:33:03.820218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2641 01:33:03.820270 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2642 01:33:03.820322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2643 01:33:03.820374 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 01:33:03.820426 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 01:33:03.820479 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 01:33:03.820531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 01:33:03.820582 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 01:33:03.820634 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 01:33:03.820685 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 01:33:03.820737 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 01:33:03.820789 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 01:33:03.820841 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 01:33:03.820893 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 01:33:03.820948 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2655 01:33:03.821000 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2656 01:33:03.821052 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2657 01:33:03.821104 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2658 01:33:03.821156 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2659 01:33:03.821208 Total UI for P1: 0, mck2ui 16
2660 01:33:03.821462 best dqsien dly found for B0: ( 1, 3, 28)
2661 01:33:03.821568 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2662 01:33:03.821634 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2663 01:33:03.821689 Total UI for P1: 0, mck2ui 16
2664 01:33:03.821744 best dqsien dly found for B1: ( 1, 4, 2)
2665 01:33:03.821797 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2666 01:33:03.821850 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2667 01:33:03.821902
2668 01:33:03.821955 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2669 01:33:03.822008 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2670 01:33:03.822060 [Gating] SW calibration Done
2671 01:33:03.822111 ==
2672 01:33:03.822171 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 01:33:03.822260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 01:33:03.822313 ==
2675 01:33:03.822365 RX Vref Scan: 0
2676 01:33:03.822418
2677 01:33:03.822470 RX Vref 0 -> 0, step: 1
2678 01:33:03.822522
2679 01:33:03.822574 RX Delay -40 -> 252, step: 8
2680 01:33:03.822627 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2681 01:33:03.822680 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2682 01:33:03.822733 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2683 01:33:03.822786 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2684 01:33:03.822838 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2685 01:33:03.822890 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2686 01:33:03.822941 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2687 01:33:03.822993 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2688 01:33:03.823045 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2689 01:33:03.823097 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2690 01:33:03.823150 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2691 01:33:03.823202 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2692 01:33:03.823254 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2693 01:33:03.823306 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2694 01:33:03.823358 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2695 01:33:03.823410 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2696 01:33:03.823462 ==
2697 01:33:03.823514 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 01:33:03.823566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 01:33:03.823618 ==
2700 01:33:03.823670 DQS Delay:
2701 01:33:03.823722 DQS0 = 0, DQS1 = 0
2702 01:33:03.823779 DQM Delay:
2703 01:33:03.823832 DQM0 = 119, DQM1 = 107
2704 01:33:03.823884 DQ Delay:
2705 01:33:03.823942 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2706 01:33:03.823996 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2707 01:33:03.824048 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2708 01:33:03.824101 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2709 01:33:03.824153
2710 01:33:03.824206
2711 01:33:03.824258 ==
2712 01:33:03.824309 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 01:33:03.824362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 01:33:03.824414 ==
2715 01:33:03.824466
2716 01:33:03.824518
2717 01:33:03.824569 TX Vref Scan disable
2718 01:33:03.824621 == TX Byte 0 ==
2719 01:33:03.824673 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2720 01:33:03.824726 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2721 01:33:03.824778 == TX Byte 1 ==
2722 01:33:03.824829 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2723 01:33:03.824882 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2724 01:33:03.824933 ==
2725 01:33:03.824985 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 01:33:03.825038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 01:33:03.825090 ==
2728 01:33:03.825142 TX Vref=22, minBit 5, minWin=25, winSum=414
2729 01:33:03.825195 TX Vref=24, minBit 3, minWin=26, winSum=423
2730 01:33:03.825247 TX Vref=26, minBit 1, minWin=26, winSum=425
2731 01:33:03.825299 TX Vref=28, minBit 5, minWin=26, winSum=430
2732 01:33:03.825351 TX Vref=30, minBit 10, minWin=26, winSum=431
2733 01:33:03.825403 TX Vref=32, minBit 5, minWin=26, winSum=431
2734 01:33:03.825455 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
2735 01:33:03.825508
2736 01:33:03.825559 Final TX Range 1 Vref 30
2737 01:33:03.825611
2738 01:33:03.825663 ==
2739 01:33:03.825714 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 01:33:03.825767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 01:33:03.825819 ==
2742 01:33:03.825871
2743 01:33:03.825922
2744 01:33:03.825973 TX Vref Scan disable
2745 01:33:03.826025 == TX Byte 0 ==
2746 01:33:03.826077 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2747 01:33:03.826129 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2748 01:33:03.826216 == TX Byte 1 ==
2749 01:33:03.826290 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2750 01:33:03.826343 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2751 01:33:03.826394
2752 01:33:03.826445 [DATLAT]
2753 01:33:03.826497 Freq=1200, CH0 RK0
2754 01:33:03.826549
2755 01:33:03.826600 DATLAT Default: 0xd
2756 01:33:03.826652 0, 0xFFFF, sum = 0
2757 01:33:03.826705 1, 0xFFFF, sum = 0
2758 01:33:03.826758 2, 0xFFFF, sum = 0
2759 01:33:03.826810 3, 0xFFFF, sum = 0
2760 01:33:03.826862 4, 0xFFFF, sum = 0
2761 01:33:03.826914 5, 0xFFFF, sum = 0
2762 01:33:03.826967 6, 0xFFFF, sum = 0
2763 01:33:03.827019 7, 0xFFFF, sum = 0
2764 01:33:03.827072 8, 0xFFFF, sum = 0
2765 01:33:03.827125 9, 0xFFFF, sum = 0
2766 01:33:03.827177 10, 0xFFFF, sum = 0
2767 01:33:03.827230 11, 0xFFFF, sum = 0
2768 01:33:03.827286 12, 0x0, sum = 1
2769 01:33:03.827340 13, 0x0, sum = 2
2770 01:33:03.827392 14, 0x0, sum = 3
2771 01:33:03.827447 15, 0x0, sum = 4
2772 01:33:03.827501 best_step = 13
2773 01:33:03.827552
2774 01:33:03.827604 ==
2775 01:33:03.827655 Dram Type= 6, Freq= 0, CH_0, rank 0
2776 01:33:03.827708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2777 01:33:03.827760 ==
2778 01:33:03.827812 RX Vref Scan: 1
2779 01:33:03.827864
2780 01:33:03.827916 Set Vref Range= 32 -> 127
2781 01:33:03.827967
2782 01:33:03.828019 RX Vref 32 -> 127, step: 1
2783 01:33:03.828071
2784 01:33:03.828123 RX Delay -21 -> 252, step: 4
2785 01:33:03.828175
2786 01:33:03.828227 Set Vref, RX VrefLevel [Byte0]: 32
2787 01:33:03.828279 [Byte1]: 32
2788 01:33:03.828331
2789 01:33:03.828383 Set Vref, RX VrefLevel [Byte0]: 33
2790 01:33:03.828435 [Byte1]: 33
2791 01:33:03.828487
2792 01:33:03.828538 Set Vref, RX VrefLevel [Byte0]: 34
2793 01:33:03.828590 [Byte1]: 34
2794 01:33:03.828642
2795 01:33:03.828694 Set Vref, RX VrefLevel [Byte0]: 35
2796 01:33:03.828746 [Byte1]: 35
2797 01:33:03.828797
2798 01:33:03.828848 Set Vref, RX VrefLevel [Byte0]: 36
2799 01:33:03.828900 [Byte1]: 36
2800 01:33:03.828952
2801 01:33:03.829003 Set Vref, RX VrefLevel [Byte0]: 37
2802 01:33:03.829054 [Byte1]: 37
2803 01:33:03.829106
2804 01:33:03.829158 Set Vref, RX VrefLevel [Byte0]: 38
2805 01:33:03.829209 [Byte1]: 38
2806 01:33:03.829261
2807 01:33:03.829312 Set Vref, RX VrefLevel [Byte0]: 39
2808 01:33:03.829365 [Byte1]: 39
2809 01:33:03.829416
2810 01:33:03.829467 Set Vref, RX VrefLevel [Byte0]: 40
2811 01:33:03.829519 [Byte1]: 40
2812 01:33:03.829570
2813 01:33:03.829819 Set Vref, RX VrefLevel [Byte0]: 41
2814 01:33:03.829912 [Byte1]: 41
2815 01:33:03.829994
2816 01:33:03.830077 Set Vref, RX VrefLevel [Byte0]: 42
2817 01:33:03.830191 [Byte1]: 42
2818 01:33:03.830310
2819 01:33:03.830444 Set Vref, RX VrefLevel [Byte0]: 43
2820 01:33:03.830539 [Byte1]: 43
2821 01:33:03.830628
2822 01:33:03.830687 Set Vref, RX VrefLevel [Byte0]: 44
2823 01:33:03.830741 [Byte1]: 44
2824 01:33:03.830794
2825 01:33:03.830847 Set Vref, RX VrefLevel [Byte0]: 45
2826 01:33:03.830900 [Byte1]: 45
2827 01:33:03.830952
2828 01:33:03.831004 Set Vref, RX VrefLevel [Byte0]: 46
2829 01:33:03.831057 [Byte1]: 46
2830 01:33:03.831109
2831 01:33:03.831161 Set Vref, RX VrefLevel [Byte0]: 47
2832 01:33:03.831213 [Byte1]: 47
2833 01:33:03.831265
2834 01:33:03.831317 Set Vref, RX VrefLevel [Byte0]: 48
2835 01:33:03.831369 [Byte1]: 48
2836 01:33:03.831420
2837 01:33:03.831472 Set Vref, RX VrefLevel [Byte0]: 49
2838 01:33:03.831525 [Byte1]: 49
2839 01:33:03.831577
2840 01:33:03.831628 Set Vref, RX VrefLevel [Byte0]: 50
2841 01:33:03.831681 [Byte1]: 50
2842 01:33:03.831733
2843 01:33:03.831785 Set Vref, RX VrefLevel [Byte0]: 51
2844 01:33:03.831837 [Byte1]: 51
2845 01:33:03.831889
2846 01:33:03.831941 Set Vref, RX VrefLevel [Byte0]: 52
2847 01:33:03.831992 [Byte1]: 52
2848 01:33:03.832044
2849 01:33:03.832096 Set Vref, RX VrefLevel [Byte0]: 53
2850 01:33:03.832149 [Byte1]: 53
2851 01:33:03.832201
2852 01:33:03.832253 Set Vref, RX VrefLevel [Byte0]: 54
2853 01:33:03.832305 [Byte1]: 54
2854 01:33:03.832358
2855 01:33:03.832410 Set Vref, RX VrefLevel [Byte0]: 55
2856 01:33:03.832462 [Byte1]: 55
2857 01:33:03.832514
2858 01:33:03.832565 Set Vref, RX VrefLevel [Byte0]: 56
2859 01:33:03.832617 [Byte1]: 56
2860 01:33:03.832669
2861 01:33:03.832721 Set Vref, RX VrefLevel [Byte0]: 57
2862 01:33:03.832772 [Byte1]: 57
2863 01:33:03.832824
2864 01:33:03.832875 Set Vref, RX VrefLevel [Byte0]: 58
2865 01:33:03.832927 [Byte1]: 58
2866 01:33:03.832979
2867 01:33:03.833034 Set Vref, RX VrefLevel [Byte0]: 59
2868 01:33:03.833087 [Byte1]: 59
2869 01:33:03.833139
2870 01:33:03.833191 Set Vref, RX VrefLevel [Byte0]: 60
2871 01:33:03.833242 [Byte1]: 60
2872 01:33:03.833294
2873 01:33:03.833346 Set Vref, RX VrefLevel [Byte0]: 61
2874 01:33:03.833399 [Byte1]: 61
2875 01:33:03.833450
2876 01:33:03.833503 Set Vref, RX VrefLevel [Byte0]: 62
2877 01:33:03.833555 [Byte1]: 62
2878 01:33:03.833607
2879 01:33:03.833659 Set Vref, RX VrefLevel [Byte0]: 63
2880 01:33:03.833711 [Byte1]: 63
2881 01:33:03.833762
2882 01:33:03.833815 Set Vref, RX VrefLevel [Byte0]: 64
2883 01:33:03.833866 [Byte1]: 64
2884 01:33:03.833918
2885 01:33:03.833970 Set Vref, RX VrefLevel [Byte0]: 65
2886 01:33:03.834022 [Byte1]: 65
2887 01:33:03.834074
2888 01:33:03.834125 Set Vref, RX VrefLevel [Byte0]: 66
2889 01:33:03.834210 [Byte1]: 66
2890 01:33:03.834277
2891 01:33:03.834329 Set Vref, RX VrefLevel [Byte0]: 67
2892 01:33:03.834382 [Byte1]: 67
2893 01:33:03.834434
2894 01:33:03.834486 Set Vref, RX VrefLevel [Byte0]: 68
2895 01:33:03.834539 [Byte1]: 68
2896 01:33:03.834591
2897 01:33:03.834643 Set Vref, RX VrefLevel [Byte0]: 69
2898 01:33:03.834695 [Byte1]: 69
2899 01:33:03.834747
2900 01:33:03.834799 Set Vref, RX VrefLevel [Byte0]: 70
2901 01:33:03.834851 [Byte1]: 70
2902 01:33:03.834903
2903 01:33:03.834955 Set Vref, RX VrefLevel [Byte0]: 71
2904 01:33:03.835007 [Byte1]: 71
2905 01:33:03.835058
2906 01:33:03.835110 Set Vref, RX VrefLevel [Byte0]: 72
2907 01:33:03.835162 [Byte1]: 72
2908 01:33:03.835214
2909 01:33:03.835266 Set Vref, RX VrefLevel [Byte0]: 73
2910 01:33:03.835318 [Byte1]: 73
2911 01:33:03.835370
2912 01:33:03.835426 Set Vref, RX VrefLevel [Byte0]: 74
2913 01:33:03.835480 [Byte1]: 74
2914 01:33:03.835532
2915 01:33:03.835584 Set Vref, RX VrefLevel [Byte0]: 75
2916 01:33:03.835645 [Byte1]: 75
2917 01:33:03.835698
2918 01:33:03.835750 Set Vref, RX VrefLevel [Byte0]: 76
2919 01:33:03.835803 [Byte1]: 76
2920 01:33:03.835854
2921 01:33:03.835907 Set Vref, RX VrefLevel [Byte0]: 77
2922 01:33:03.835959 [Byte1]: 77
2923 01:33:03.836011
2924 01:33:03.836067 Final RX Vref Byte 0 = 60 to rank0
2925 01:33:03.836120 Final RX Vref Byte 1 = 52 to rank0
2926 01:33:03.836172 Final RX Vref Byte 0 = 60 to rank1
2927 01:33:03.836224 Final RX Vref Byte 1 = 52 to rank1==
2928 01:33:03.836277 Dram Type= 6, Freq= 0, CH_0, rank 0
2929 01:33:03.836330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 01:33:03.836382 ==
2931 01:33:03.836435 DQS Delay:
2932 01:33:03.836487 DQS0 = 0, DQS1 = 0
2933 01:33:03.836539 DQM Delay:
2934 01:33:03.836592 DQM0 = 118, DQM1 = 107
2935 01:33:03.836644 DQ Delay:
2936 01:33:03.836696 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =116
2937 01:33:03.836748 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2938 01:33:03.836800 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2939 01:33:03.836852 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2940 01:33:03.836904
2941 01:33:03.836955
2942 01:33:03.837007 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2943 01:33:03.837060 CH0 RK0: MR19=403, MR18=10FC
2944 01:33:03.837112 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2945 01:33:03.837165
2946 01:33:03.837217 ----->DramcWriteLeveling(PI) begin...
2947 01:33:03.837270 ==
2948 01:33:03.837322 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 01:33:03.837375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 01:33:03.837427 ==
2951 01:33:03.837479 Write leveling (Byte 0): 33 => 33
2952 01:33:03.837532 Write leveling (Byte 1): 29 => 29
2953 01:33:03.837584 DramcWriteLeveling(PI) end<-----
2954 01:33:03.837636
2955 01:33:03.837688 ==
2956 01:33:03.837740 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 01:33:03.837793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 01:33:03.837846 ==
2959 01:33:03.837898 [Gating] SW mode calibration
2960 01:33:03.837951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2961 01:33:03.838003 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2962 01:33:03.838056 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2963 01:33:03.838109 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2964 01:33:03.838362 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 01:33:03.838460 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 01:33:03.838514 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 01:33:03.838566 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 01:33:03.838619 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 01:33:03.838671 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2970 01:33:03.838724 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
2971 01:33:03.838776 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2972 01:33:03.838830 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 01:33:03.838883 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 01:33:03.838936 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 01:33:03.838987 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 01:33:03.839040 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 01:33:03.839092 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2978 01:33:03.839144 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2979 01:33:03.839196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 01:33:03.839248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 01:33:03.839300 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 01:33:03.839352 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 01:33:03.839404 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 01:33:03.839456 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2985 01:33:03.839508 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2986 01:33:03.839560 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2987 01:33:03.839612 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 01:33:03.839664 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 01:33:03.839717 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 01:33:03.839769 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 01:33:03.839821 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 01:33:03.839873 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 01:33:03.839925 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 01:33:03.839976 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 01:33:03.840028 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 01:33:03.840080 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 01:33:03.840132 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 01:33:03.840184 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 01:33:03.840236 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 01:33:03.840287 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 01:33:03.840339 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3002 01:33:03.840392 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3003 01:33:03.840445 Total UI for P1: 0, mck2ui 16
3004 01:33:03.840497 best dqsien dly found for B0: ( 1, 3, 28)
3005 01:33:03.840550 Total UI for P1: 0, mck2ui 16
3006 01:33:04.092433 best dqsien dly found for B1: ( 1, 3, 30)
3007 01:33:04.092962 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3008 01:33:04.093328 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3009 01:33:04.093668
3010 01:33:04.093998 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3011 01:33:04.094354 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3012 01:33:04.094671 [Gating] SW calibration Done
3013 01:33:04.094982 ==
3014 01:33:04.095295 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 01:33:04.095604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 01:33:04.095911 ==
3017 01:33:04.096214 RX Vref Scan: 0
3018 01:33:04.096517
3019 01:33:04.096818 RX Vref 0 -> 0, step: 1
3020 01:33:04.097121
3021 01:33:04.097423 RX Delay -40 -> 252, step: 8
3022 01:33:04.097727 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3023 01:33:04.098030 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3024 01:33:04.098355 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3025 01:33:04.098658 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3026 01:33:04.098956 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3027 01:33:04.099251 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3028 01:33:04.099545 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3029 01:33:04.099842 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3030 01:33:04.100136 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3031 01:33:04.100432 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3032 01:33:04.100732 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3033 01:33:04.101029 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3034 01:33:04.101326 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3035 01:33:04.101622 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3036 01:33:04.101916 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3037 01:33:04.102233 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3038 01:33:04.102532 ==
3039 01:33:04.102830 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 01:33:04.103129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 01:33:04.103426 ==
3042 01:33:04.103726 DQS Delay:
3043 01:33:04.104021 DQS0 = 0, DQS1 = 0
3044 01:33:04.104319 DQM Delay:
3045 01:33:04.104617 DQM0 = 116, DQM1 = 108
3046 01:33:04.104914 DQ Delay:
3047 01:33:04.105206 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3048 01:33:04.105502 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3049 01:33:04.105798 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3050 01:33:04.106092 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3051 01:33:04.106413
3052 01:33:04.106710
3053 01:33:04.107004 ==
3054 01:33:04.107299 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 01:33:04.107597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 01:33:04.107895 ==
3057 01:33:04.108187
3058 01:33:04.108477
3059 01:33:04.108768 TX Vref Scan disable
3060 01:33:04.109067 == TX Byte 0 ==
3061 01:33:04.109363 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3062 01:33:04.109723 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3063 01:33:04.110025 == TX Byte 1 ==
3064 01:33:04.110345 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3065 01:33:04.110644 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3066 01:33:04.110942 ==
3067 01:33:04.111241 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 01:33:04.111541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 01:33:04.111841 ==
3070 01:33:04.112140 TX Vref=22, minBit 5, minWin=25, winSum=418
3071 01:33:04.112860 TX Vref=24, minBit 1, minWin=26, winSum=424
3072 01:33:04.113203 TX Vref=26, minBit 13, minWin=25, winSum=425
3073 01:33:04.113545 TX Vref=28, minBit 1, minWin=26, winSum=429
3074 01:33:04.113975 TX Vref=30, minBit 13, minWin=25, winSum=430
3075 01:33:04.114489 TX Vref=32, minBit 10, minWin=26, winSum=429
3076 01:33:04.114818 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3077 01:33:04.115129
3078 01:33:04.115436 Final TX Range 1 Vref 28
3079 01:33:04.115745
3080 01:33:04.116047 ==
3081 01:33:04.116347 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 01:33:04.116653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 01:33:04.116955 ==
3084 01:33:04.117256
3085 01:33:04.117551
3086 01:33:04.117781 TX Vref Scan disable
3087 01:33:04.117993 == TX Byte 0 ==
3088 01:33:04.118230 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3089 01:33:04.118451 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3090 01:33:04.118667 == TX Byte 1 ==
3091 01:33:04.118877 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3092 01:33:04.119088 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3093 01:33:04.119298
3094 01:33:04.119511 [DATLAT]
3095 01:33:04.119724 Freq=1200, CH0 RK1
3096 01:33:04.119937
3097 01:33:04.120146 DATLAT Default: 0xd
3098 01:33:04.120358 0, 0xFFFF, sum = 0
3099 01:33:04.120575 1, 0xFFFF, sum = 0
3100 01:33:04.120787 2, 0xFFFF, sum = 0
3101 01:33:04.121000 3, 0xFFFF, sum = 0
3102 01:33:04.121213 4, 0xFFFF, sum = 0
3103 01:33:04.121426 5, 0xFFFF, sum = 0
3104 01:33:04.121640 6, 0xFFFF, sum = 0
3105 01:33:04.121851 7, 0xFFFF, sum = 0
3106 01:33:04.122075 8, 0xFFFF, sum = 0
3107 01:33:04.122393 9, 0xFFFF, sum = 0
3108 01:33:04.122746 10, 0xFFFF, sum = 0
3109 01:33:04.122923 11, 0xFFFF, sum = 0
3110 01:33:04.123083 12, 0x0, sum = 1
3111 01:33:04.123241 13, 0x0, sum = 2
3112 01:33:04.123399 14, 0x0, sum = 3
3113 01:33:04.123555 15, 0x0, sum = 4
3114 01:33:04.123710 best_step = 13
3115 01:33:04.123863
3116 01:33:04.124018 ==
3117 01:33:04.124172 Dram Type= 6, Freq= 0, CH_0, rank 1
3118 01:33:04.124328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 01:33:04.124488 ==
3120 01:33:04.124645 RX Vref Scan: 0
3121 01:33:04.124800
3122 01:33:04.124955 RX Vref 0 -> 0, step: 1
3123 01:33:04.125110
3124 01:33:04.125265 RX Delay -21 -> 252, step: 4
3125 01:33:04.125421 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3126 01:33:04.125578 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3127 01:33:04.125734 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3128 01:33:04.125890 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3129 01:33:04.126047 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3130 01:33:04.126227 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3131 01:33:04.126389 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3132 01:33:04.126546 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3133 01:33:04.126703 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3134 01:33:04.126859 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3135 01:33:04.127015 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3136 01:33:04.127170 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3137 01:33:04.127326 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3138 01:33:04.127481 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3139 01:33:04.127632 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3140 01:33:04.127756 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3141 01:33:04.127878 ==
3142 01:33:04.128002 Dram Type= 6, Freq= 0, CH_0, rank 1
3143 01:33:04.128127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 01:33:04.128251 ==
3145 01:33:04.128375 DQS Delay:
3146 01:33:04.128499 DQS0 = 0, DQS1 = 0
3147 01:33:04.128622 DQM Delay:
3148 01:33:04.128744 DQM0 = 116, DQM1 = 108
3149 01:33:04.128868 DQ Delay:
3150 01:33:04.128991 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3151 01:33:04.129114 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3152 01:33:04.129238 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3153 01:33:04.129362 DQ12 =114, DQ13 =116, DQ14 =118, DQ15 =116
3154 01:33:04.129499
3155 01:33:04.129629
3156 01:33:04.129753 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3157 01:33:04.129879 CH0 RK1: MR19=403, MR18=9E5
3158 01:33:04.130003 CH0_RK1: MR19=0x403, MR18=0x9E5, DQSOSC=406, MR23=63, INC=39, DEC=26
3159 01:33:04.130128 [RxdqsGatingPostProcess] freq 1200
3160 01:33:04.130273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3161 01:33:04.130399 best DQS0 dly(2T, 0.5T) = (0, 11)
3162 01:33:04.130523 best DQS1 dly(2T, 0.5T) = (0, 12)
3163 01:33:04.130648 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3164 01:33:04.130771 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3165 01:33:04.130894 best DQS0 dly(2T, 0.5T) = (0, 11)
3166 01:33:04.131017 best DQS1 dly(2T, 0.5T) = (0, 11)
3167 01:33:04.131140 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3168 01:33:04.131263 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3169 01:33:04.131387 Pre-setting of DQS Precalculation
3170 01:33:04.131510 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3171 01:33:04.131633 ==
3172 01:33:04.131757 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 01:33:04.131881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 01:33:04.132005 ==
3175 01:33:04.132129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3176 01:33:04.132253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3177 01:33:04.132377 [CA 0] Center 37 (7~68) winsize 62
3178 01:33:04.132500 [CA 1] Center 38 (8~68) winsize 61
3179 01:33:04.132619 [CA 2] Center 34 (4~64) winsize 61
3180 01:33:04.132721 [CA 3] Center 33 (3~64) winsize 62
3181 01:33:04.132823 [CA 4] Center 34 (4~64) winsize 61
3182 01:33:04.132925 [CA 5] Center 33 (3~64) winsize 62
3183 01:33:04.133026
3184 01:33:04.133129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3185 01:33:04.133231
3186 01:33:04.133334 [CATrainingPosCal] consider 1 rank data
3187 01:33:04.133436 u2DelayCellTimex100 = 270/100 ps
3188 01:33:04.133566 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3189 01:33:04.133721 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3190 01:33:04.133851 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3191 01:33:04.133957 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3192 01:33:04.134060 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3193 01:33:04.134175 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3194 01:33:04.134283
3195 01:33:04.134386 CA PerBit enable=1, Macro0, CA PI delay=33
3196 01:33:04.134489
3197 01:33:04.134592 [CBTSetCACLKResult] CA Dly = 33
3198 01:33:04.134696 CS Dly: 6 (0~37)
3199 01:33:04.134799 ==
3200 01:33:04.134902 Dram Type= 6, Freq= 0, CH_1, rank 1
3201 01:33:04.135005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 01:33:04.135109 ==
3203 01:33:04.135212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3204 01:33:04.135554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3205 01:33:04.135674 [CA 0] Center 38 (8~68) winsize 61
3206 01:33:04.135781 [CA 1] Center 37 (7~68) winsize 62
3207 01:33:04.135885 [CA 2] Center 34 (4~65) winsize 62
3208 01:33:04.135988 [CA 3] Center 34 (3~65) winsize 63
3209 01:33:04.136090 [CA 4] Center 34 (4~64) winsize 61
3210 01:33:04.136194 [CA 5] Center 33 (3~64) winsize 62
3211 01:33:04.136295
3212 01:33:04.136401 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3213 01:33:04.136505
3214 01:33:04.136609 [CATrainingPosCal] consider 2 rank data
3215 01:33:04.136711 u2DelayCellTimex100 = 270/100 ps
3216 01:33:04.136814 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3217 01:33:04.136917 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3218 01:33:04.137020 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3219 01:33:04.137124 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3220 01:33:04.137227 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3221 01:33:04.137328 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3222 01:33:04.137431
3223 01:33:04.137534 CA PerBit enable=1, Macro0, CA PI delay=33
3224 01:33:04.137637
3225 01:33:04.137725 [CBTSetCACLKResult] CA Dly = 33
3226 01:33:04.137812 CS Dly: 7 (0~40)
3227 01:33:04.137900
3228 01:33:04.137987 ----->DramcWriteLeveling(PI) begin...
3229 01:33:04.138076 ==
3230 01:33:04.138175 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 01:33:04.138267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 01:33:04.138356 ==
3233 01:33:04.138444 Write leveling (Byte 0): 24 => 24
3234 01:33:04.138533 Write leveling (Byte 1): 26 => 26
3235 01:33:04.138620 DramcWriteLeveling(PI) end<-----
3236 01:33:04.138708
3237 01:33:04.138795 ==
3238 01:33:04.138882 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 01:33:04.138971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 01:33:04.139059 ==
3241 01:33:04.139147 [Gating] SW mode calibration
3242 01:33:04.139235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3243 01:33:04.139324 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3244 01:33:04.139412 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3245 01:33:04.139501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3246 01:33:04.139589 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3247 01:33:04.139677 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3248 01:33:04.139765 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3249 01:33:04.139852 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3250 01:33:04.139939 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3251 01:33:04.140027 0 15 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
3252 01:33:04.140114 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3253 01:33:04.140202 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3254 01:33:04.140289 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3255 01:33:04.140376 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3256 01:33:04.140464 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3257 01:33:04.140551 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3258 01:33:04.140639 1 0 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
3259 01:33:04.140727 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3260 01:33:04.140815 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 01:33:04.140902 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 01:33:04.140989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 01:33:04.141077 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 01:33:04.141164 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3265 01:33:04.141251 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3266 01:33:04.141338 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3267 01:33:04.141424 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3268 01:33:04.141513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3269 01:33:04.141600 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 01:33:04.141687 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 01:33:04.141774 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 01:33:04.141862 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 01:33:04.141949 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 01:33:04.142037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 01:33:04.142124 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 01:33:04.142226 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 01:33:04.142314 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 01:33:04.142401 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 01:33:04.142488 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 01:33:04.142584 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 01:33:04.142660 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 01:33:04.142736 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 01:33:04.142811 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3284 01:33:04.142887 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 01:33:04.142963 Total UI for P1: 0, mck2ui 16
3286 01:33:04.143040 best dqsien dly found for B0: ( 1, 3, 28)
3287 01:33:04.143118 Total UI for P1: 0, mck2ui 16
3288 01:33:04.143195 best dqsien dly found for B1: ( 1, 3, 28)
3289 01:33:04.143272 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3290 01:33:04.143349 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3291 01:33:04.143425
3292 01:33:04.143501 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3293 01:33:04.143577 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3294 01:33:04.143653 [Gating] SW calibration Done
3295 01:33:04.143729 ==
3296 01:33:04.143806 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 01:33:04.143882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 01:33:04.143959 ==
3299 01:33:04.144036 RX Vref Scan: 0
3300 01:33:04.144112
3301 01:33:04.144188 RX Vref 0 -> 0, step: 1
3302 01:33:04.144263
3303 01:33:04.144340 RX Delay -40 -> 252, step: 8
3304 01:33:04.144416 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3305 01:33:04.144493 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3306 01:33:04.144568 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3307 01:33:04.144643 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3308 01:33:04.144719 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3309 01:33:04.145006 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3310 01:33:04.145091 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3311 01:33:04.145168 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3312 01:33:04.145245 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3313 01:33:04.145322 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3314 01:33:04.145398 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3315 01:33:04.145475 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3316 01:33:04.145551 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3317 01:33:04.145628 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3318 01:33:04.145704 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3319 01:33:04.145780 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3320 01:33:04.145857 ==
3321 01:33:04.145933 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 01:33:04.146010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 01:33:04.146087 ==
3324 01:33:04.146176 DQS Delay:
3325 01:33:04.146257 DQS0 = 0, DQS1 = 0
3326 01:33:04.146334 DQM Delay:
3327 01:33:04.146410 DQM0 = 117, DQM1 = 110
3328 01:33:04.146487 DQ Delay:
3329 01:33:04.146564 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3330 01:33:04.146640 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3331 01:33:04.146716 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3332 01:33:04.146791 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3333 01:33:04.146868
3334 01:33:04.146944
3335 01:33:04.147020 ==
3336 01:33:04.147096 Dram Type= 6, Freq= 0, CH_1, rank 0
3337 01:33:04.147173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3338 01:33:04.147250 ==
3339 01:33:04.147326
3340 01:33:04.147401
3341 01:33:04.147476 TX Vref Scan disable
3342 01:33:04.147563 == TX Byte 0 ==
3343 01:33:04.147630 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3344 01:33:04.147699 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3345 01:33:04.147767 == TX Byte 1 ==
3346 01:33:04.147834 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3347 01:33:04.147901 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3348 01:33:04.147968 ==
3349 01:33:04.148037 Dram Type= 6, Freq= 0, CH_1, rank 0
3350 01:33:04.148105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3351 01:33:04.148173 ==
3352 01:33:04.148241 TX Vref=22, minBit 9, minWin=25, winSum=415
3353 01:33:04.148310 TX Vref=24, minBit 9, minWin=25, winSum=420
3354 01:33:04.148378 TX Vref=26, minBit 10, minWin=24, winSum=425
3355 01:33:04.148446 TX Vref=28, minBit 11, minWin=25, winSum=431
3356 01:33:04.148514 TX Vref=30, minBit 9, minWin=25, winSum=429
3357 01:33:04.148581 TX Vref=32, minBit 9, minWin=25, winSum=428
3358 01:33:04.148649 [TxChooseVref] Worse bit 11, Min win 25, Win sum 431, Final Vref 28
3359 01:33:04.148717
3360 01:33:04.148785 Final TX Range 1 Vref 28
3361 01:33:04.148852
3362 01:33:04.148918 ==
3363 01:33:04.148985 Dram Type= 6, Freq= 0, CH_1, rank 0
3364 01:33:04.149052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3365 01:33:04.149120 ==
3366 01:33:04.149188
3367 01:33:04.149254
3368 01:33:04.149320 TX Vref Scan disable
3369 01:33:04.149387 == TX Byte 0 ==
3370 01:33:04.149454 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3371 01:33:04.149521 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3372 01:33:04.149588 == TX Byte 1 ==
3373 01:33:04.149655 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3374 01:33:04.149722 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3375 01:33:04.149788
3376 01:33:04.149855 [DATLAT]
3377 01:33:04.149921 Freq=1200, CH1 RK0
3378 01:33:04.149990
3379 01:33:04.150056 DATLAT Default: 0xd
3380 01:33:04.150124 0, 0xFFFF, sum = 0
3381 01:33:04.150204 1, 0xFFFF, sum = 0
3382 01:33:04.150274 2, 0xFFFF, sum = 0
3383 01:33:04.150342 3, 0xFFFF, sum = 0
3384 01:33:04.150411 4, 0xFFFF, sum = 0
3385 01:33:04.150479 5, 0xFFFF, sum = 0
3386 01:33:04.150547 6, 0xFFFF, sum = 0
3387 01:33:04.150614 7, 0xFFFF, sum = 0
3388 01:33:04.150681 8, 0xFFFF, sum = 0
3389 01:33:04.150749 9, 0xFFFF, sum = 0
3390 01:33:04.150817 10, 0xFFFF, sum = 0
3391 01:33:04.150885 11, 0xFFFF, sum = 0
3392 01:33:04.150953 12, 0x0, sum = 1
3393 01:33:04.151021 13, 0x0, sum = 2
3394 01:33:04.151088 14, 0x0, sum = 3
3395 01:33:04.151156 15, 0x0, sum = 4
3396 01:33:04.151223 best_step = 13
3397 01:33:04.151289
3398 01:33:04.151357 ==
3399 01:33:04.151424 Dram Type= 6, Freq= 0, CH_1, rank 0
3400 01:33:04.151491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3401 01:33:04.151559 ==
3402 01:33:04.151626 RX Vref Scan: 1
3403 01:33:04.151693
3404 01:33:04.151760 Set Vref Range= 32 -> 127
3405 01:33:04.151826
3406 01:33:04.151895 RX Vref 32 -> 127, step: 1
3407 01:33:04.151962
3408 01:33:04.152029 RX Delay -21 -> 252, step: 4
3409 01:33:04.152095
3410 01:33:04.152163 Set Vref, RX VrefLevel [Byte0]: 32
3411 01:33:04.152230 [Byte1]: 32
3412 01:33:04.152297
3413 01:33:04.152363 Set Vref, RX VrefLevel [Byte0]: 33
3414 01:33:04.152430 [Byte1]: 33
3415 01:33:04.152496
3416 01:33:04.152573 Set Vref, RX VrefLevel [Byte0]: 34
3417 01:33:04.152632 [Byte1]: 34
3418 01:33:04.152692
3419 01:33:04.152751 Set Vref, RX VrefLevel [Byte0]: 35
3420 01:33:04.152812 [Byte1]: 35
3421 01:33:04.152871
3422 01:33:04.152931 Set Vref, RX VrefLevel [Byte0]: 36
3423 01:33:04.152991 [Byte1]: 36
3424 01:33:04.153051
3425 01:33:04.153111 Set Vref, RX VrefLevel [Byte0]: 37
3426 01:33:04.153171 [Byte1]: 37
3427 01:33:04.153231
3428 01:33:04.153291 Set Vref, RX VrefLevel [Byte0]: 38
3429 01:33:04.153352 [Byte1]: 38
3430 01:33:04.153411
3431 01:33:04.153471 Set Vref, RX VrefLevel [Byte0]: 39
3432 01:33:04.153531 [Byte1]: 39
3433 01:33:04.153590
3434 01:33:04.153650 Set Vref, RX VrefLevel [Byte0]: 40
3435 01:33:04.153709 [Byte1]: 40
3436 01:33:04.153769
3437 01:33:04.153829 Set Vref, RX VrefLevel [Byte0]: 41
3438 01:33:04.153889 [Byte1]: 41
3439 01:33:04.153949
3440 01:33:04.154009 Set Vref, RX VrefLevel [Byte0]: 42
3441 01:33:04.154070 [Byte1]: 42
3442 01:33:04.154129
3443 01:33:04.154199 Set Vref, RX VrefLevel [Byte0]: 43
3444 01:33:04.154261 [Byte1]: 43
3445 01:33:04.154321
3446 01:33:04.154381 Set Vref, RX VrefLevel [Byte0]: 44
3447 01:33:04.154441 [Byte1]: 44
3448 01:33:04.154501
3449 01:33:04.154563 Set Vref, RX VrefLevel [Byte0]: 45
3450 01:33:04.154623 [Byte1]: 45
3451 01:33:04.154684
3452 01:33:04.154743 Set Vref, RX VrefLevel [Byte0]: 46
3453 01:33:04.154804 [Byte1]: 46
3454 01:33:04.154864
3455 01:33:04.154923 Set Vref, RX VrefLevel [Byte0]: 47
3456 01:33:04.154983 [Byte1]: 47
3457 01:33:04.155043
3458 01:33:04.155103 Set Vref, RX VrefLevel [Byte0]: 48
3459 01:33:04.155164 [Byte1]: 48
3460 01:33:04.155223
3461 01:33:04.155283 Set Vref, RX VrefLevel [Byte0]: 49
3462 01:33:04.155343 [Byte1]: 49
3463 01:33:04.155403
3464 01:33:04.155463 Set Vref, RX VrefLevel [Byte0]: 50
3465 01:33:04.155523 [Byte1]: 50
3466 01:33:04.155583
3467 01:33:04.155643 Set Vref, RX VrefLevel [Byte0]: 51
3468 01:33:04.155704 [Byte1]: 51
3469 01:33:04.155962
3470 01:33:04.156028 Set Vref, RX VrefLevel [Byte0]: 52
3471 01:33:04.156090 [Byte1]: 52
3472 01:33:04.156151
3473 01:33:04.156212 Set Vref, RX VrefLevel [Byte0]: 53
3474 01:33:04.156273 [Byte1]: 53
3475 01:33:04.156333
3476 01:33:04.156393 Set Vref, RX VrefLevel [Byte0]: 54
3477 01:33:04.156453 [Byte1]: 54
3478 01:33:04.156513
3479 01:33:04.156573 Set Vref, RX VrefLevel [Byte0]: 55
3480 01:33:04.156634 [Byte1]: 55
3481 01:33:04.156694
3482 01:33:04.156754 Set Vref, RX VrefLevel [Byte0]: 56
3483 01:33:04.156814 [Byte1]: 56
3484 01:33:04.156874
3485 01:33:04.156934 Set Vref, RX VrefLevel [Byte0]: 57
3486 01:33:04.156994 [Byte1]: 57
3487 01:33:04.157053
3488 01:33:04.157114 Set Vref, RX VrefLevel [Byte0]: 58
3489 01:33:04.157173 [Byte1]: 58
3490 01:33:04.157233
3491 01:33:04.157294 Set Vref, RX VrefLevel [Byte0]: 59
3492 01:33:04.157354 [Byte1]: 59
3493 01:33:04.157415
3494 01:33:04.157474 Set Vref, RX VrefLevel [Byte0]: 60
3495 01:33:04.157535 [Byte1]: 60
3496 01:33:04.157602
3497 01:33:04.157657 Set Vref, RX VrefLevel [Byte0]: 61
3498 01:33:04.157711 [Byte1]: 61
3499 01:33:04.157766
3500 01:33:04.157820 Set Vref, RX VrefLevel [Byte0]: 62
3501 01:33:04.157875 [Byte1]: 62
3502 01:33:04.157929
3503 01:33:04.157984 Set Vref, RX VrefLevel [Byte0]: 63
3504 01:33:04.158038 [Byte1]: 63
3505 01:33:04.158093
3506 01:33:04.158147 Set Vref, RX VrefLevel [Byte0]: 64
3507 01:33:04.158212 [Byte1]: 64
3508 01:33:04.158267
3509 01:33:04.158322 Set Vref, RX VrefLevel [Byte0]: 65
3510 01:33:04.158377 [Byte1]: 65
3511 01:33:04.158432
3512 01:33:04.158486 Set Vref, RX VrefLevel [Byte0]: 66
3513 01:33:04.158540 [Byte1]: 66
3514 01:33:04.158595
3515 01:33:04.158649 Set Vref, RX VrefLevel [Byte0]: 67
3516 01:33:04.158703 [Byte1]: 67
3517 01:33:04.158758
3518 01:33:04.158812 Set Vref, RX VrefLevel [Byte0]: 68
3519 01:33:04.158866 [Byte1]: 68
3520 01:33:04.158920
3521 01:33:04.158974 Final RX Vref Byte 0 = 52 to rank0
3522 01:33:04.159030 Final RX Vref Byte 1 = 54 to rank0
3523 01:33:04.159085 Final RX Vref Byte 0 = 52 to rank1
3524 01:33:04.159140 Final RX Vref Byte 1 = 54 to rank1==
3525 01:33:04.159194 Dram Type= 6, Freq= 0, CH_1, rank 0
3526 01:33:04.159248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 01:33:04.159303 ==
3528 01:33:04.159358 DQS Delay:
3529 01:33:04.159420 DQS0 = 0, DQS1 = 0
3530 01:33:04.159485 DQM Delay:
3531 01:33:04.159540 DQM0 = 116, DQM1 = 110
3532 01:33:04.159596 DQ Delay:
3533 01:33:04.159650 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =112
3534 01:33:04.159706 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =112
3535 01:33:04.159761 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3536 01:33:04.159816 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3537 01:33:04.159870
3538 01:33:04.159924
3539 01:33:04.159979 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3540 01:33:04.160034 CH1 RK0: MR19=403, MR18=2F5
3541 01:33:04.160089 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3542 01:33:04.160145
3543 01:33:04.160200 ----->DramcWriteLeveling(PI) begin...
3544 01:33:04.160255 ==
3545 01:33:04.160310 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 01:33:04.160369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 01:33:04.160424 ==
3548 01:33:04.160479 Write leveling (Byte 0): 25 => 25
3549 01:33:04.160534 Write leveling (Byte 1): 27 => 27
3550 01:33:04.160589 DramcWriteLeveling(PI) end<-----
3551 01:33:04.160644
3552 01:33:04.160699 ==
3553 01:33:04.160753 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 01:33:04.160807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 01:33:04.160862 ==
3556 01:33:04.160917 [Gating] SW mode calibration
3557 01:33:04.160971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3558 01:33:04.161026 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3559 01:33:04.161081 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3560 01:33:04.161136 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 01:33:04.161190 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3562 01:33:04.161244 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3563 01:33:04.161299 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3564 01:33:04.161353 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3565 01:33:04.161407 0 15 24 | B1->B0 | 3030 3434 | 0 1 | (1 0) (1 0)
3566 01:33:04.161462 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (1 0)
3567 01:33:04.161517 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3568 01:33:04.161571 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 01:33:04.161626 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3570 01:33:04.161680 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3571 01:33:04.161736 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3572 01:33:04.161790 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3573 01:33:04.161845 1 0 24 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
3574 01:33:04.161899 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3575 01:33:04.161953 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 01:33:04.162008 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 01:33:04.162063 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 01:33:04.162117 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 01:33:04.162179 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3580 01:33:04.162235 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 01:33:04.162290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3582 01:33:04.162370 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3583 01:33:04.162427 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 01:33:04.162482 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 01:33:04.162537 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 01:33:04.162602 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 01:33:04.162654 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 01:33:04.162706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 01:33:04.162758 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 01:33:04.163001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 01:33:04.163059 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 01:33:04.163112 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 01:33:04.163165 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 01:33:04.163217 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 01:33:04.163269 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 01:33:04.163321 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3597 01:33:04.163373 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3598 01:33:04.163425 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3599 01:33:04.163478 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3600 01:33:04.163530 Total UI for P1: 0, mck2ui 16
3601 01:33:04.163582 best dqsien dly found for B0: ( 1, 3, 28)
3602 01:33:04.163635 Total UI for P1: 0, mck2ui 16
3603 01:33:04.163687 best dqsien dly found for B1: ( 1, 3, 26)
3604 01:33:04.163740 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3605 01:33:04.163793 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3606 01:33:04.163845
3607 01:33:04.163897 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3608 01:33:04.163949 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3609 01:33:04.164001 [Gating] SW calibration Done
3610 01:33:04.164053 ==
3611 01:33:04.164106 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 01:33:04.164159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 01:33:04.164211 ==
3614 01:33:04.164264 RX Vref Scan: 0
3615 01:33:04.164320
3616 01:33:04.164374 RX Vref 0 -> 0, step: 1
3617 01:33:04.164427
3618 01:33:04.164478 RX Delay -40 -> 252, step: 8
3619 01:33:04.164531 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3620 01:33:04.164583 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3621 01:33:04.164635 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3622 01:33:04.164687 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3623 01:33:04.164740 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3624 01:33:04.164792 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3625 01:33:04.164843 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3626 01:33:04.164895 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3627 01:33:04.164947 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3628 01:33:04.165000 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3629 01:33:04.165053 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3630 01:33:04.165105 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3631 01:33:04.165157 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3632 01:33:04.165209 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3633 01:33:04.165261 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3634 01:33:04.165313 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3635 01:33:04.165365 ==
3636 01:33:04.165417 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 01:33:04.165469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 01:33:04.165521 ==
3639 01:33:04.165574 DQS Delay:
3640 01:33:04.165626 DQS0 = 0, DQS1 = 0
3641 01:33:04.165678 DQM Delay:
3642 01:33:04.165730 DQM0 = 117, DQM1 = 110
3643 01:33:04.165782 DQ Delay:
3644 01:33:04.165834 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3645 01:33:04.165887 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3646 01:33:04.165940 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3647 01:33:04.165992 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3648 01:33:04.166044
3649 01:33:04.166096
3650 01:33:04.166147 ==
3651 01:33:04.166209 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 01:33:04.166263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 01:33:04.166318 ==
3654 01:33:04.166382
3655 01:33:04.166436
3656 01:33:04.166488 TX Vref Scan disable
3657 01:33:04.166541 == TX Byte 0 ==
3658 01:33:04.166593 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3659 01:33:04.166647 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3660 01:33:04.166699 == TX Byte 1 ==
3661 01:33:04.166751 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3662 01:33:04.166804 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3663 01:33:04.166856 ==
3664 01:33:04.166909 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 01:33:04.166961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 01:33:04.167014 ==
3667 01:33:04.167067 TX Vref=22, minBit 9, minWin=24, winSum=424
3668 01:33:04.167120 TX Vref=24, minBit 3, minWin=26, winSum=430
3669 01:33:04.167172 TX Vref=26, minBit 9, minWin=26, winSum=434
3670 01:33:04.167225 TX Vref=28, minBit 9, minWin=26, winSum=435
3671 01:33:04.167277 TX Vref=30, minBit 10, minWin=26, winSum=438
3672 01:33:04.167329 TX Vref=32, minBit 9, minWin=26, winSum=435
3673 01:33:04.167382 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
3674 01:33:04.167434
3675 01:33:04.167486 Final TX Range 1 Vref 30
3676 01:33:04.167539
3677 01:33:04.167590 ==
3678 01:33:04.167642 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 01:33:04.167695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 01:33:04.167749 ==
3681 01:33:04.167800
3682 01:33:04.167852
3683 01:33:04.167904 TX Vref Scan disable
3684 01:33:04.167956 == TX Byte 0 ==
3685 01:33:04.168008 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3686 01:33:04.168061 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3687 01:33:04.168114 == TX Byte 1 ==
3688 01:33:04.168166 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3689 01:33:04.168218 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3690 01:33:04.168270
3691 01:33:04.168322 [DATLAT]
3692 01:33:04.168373 Freq=1200, CH1 RK1
3693 01:33:04.168426
3694 01:33:04.168478 DATLAT Default: 0xd
3695 01:33:04.168530 0, 0xFFFF, sum = 0
3696 01:33:04.168583 1, 0xFFFF, sum = 0
3697 01:33:04.168636 2, 0xFFFF, sum = 0
3698 01:33:04.168689 3, 0xFFFF, sum = 0
3699 01:33:04.168742 4, 0xFFFF, sum = 0
3700 01:33:04.168795 5, 0xFFFF, sum = 0
3701 01:33:04.168848 6, 0xFFFF, sum = 0
3702 01:33:04.168900 7, 0xFFFF, sum = 0
3703 01:33:04.168953 8, 0xFFFF, sum = 0
3704 01:33:04.169005 9, 0xFFFF, sum = 0
3705 01:33:04.169058 10, 0xFFFF, sum = 0
3706 01:33:04.169110 11, 0xFFFF, sum = 0
3707 01:33:04.169163 12, 0x0, sum = 1
3708 01:33:04.169215 13, 0x0, sum = 2
3709 01:33:04.169268 14, 0x0, sum = 3
3710 01:33:04.169320 15, 0x0, sum = 4
3711 01:33:04.169373 best_step = 13
3712 01:33:04.169424
3713 01:33:04.169476 ==
3714 01:33:04.169528 Dram Type= 6, Freq= 0, CH_1, rank 1
3715 01:33:04.169581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3716 01:33:04.169634 ==
3717 01:33:04.169686 RX Vref Scan: 0
3718 01:33:04.169738
3719 01:33:04.169790 RX Vref 0 -> 0, step: 1
3720 01:33:04.169842
3721 01:33:04.169894 RX Delay -21 -> 252, step: 4
3722 01:33:04.169946 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3723 01:33:04.169999 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3724 01:33:04.170051 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3725 01:33:04.170103 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3726 01:33:04.170155 iDelay=199, Bit 4, Center 118 (51 ~ 186) 136
3727 01:33:04.170254 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3728 01:33:04.170503 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3729 01:33:04.170569 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3730 01:33:04.170624 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3731 01:33:04.170678 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3732 01:33:04.170731 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3733 01:33:04.170784 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3734 01:33:04.170837 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3735 01:33:04.170889 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3736 01:33:04.170941 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3737 01:33:04.170994 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3738 01:33:04.171046 ==
3739 01:33:04.171099 Dram Type= 6, Freq= 0, CH_1, rank 1
3740 01:33:04.171151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3741 01:33:04.171203 ==
3742 01:33:04.171256 DQS Delay:
3743 01:33:04.171308 DQS0 = 0, DQS1 = 0
3744 01:33:04.171361 DQM Delay:
3745 01:33:04.171412 DQM0 = 117, DQM1 = 110
3746 01:33:04.171465 DQ Delay:
3747 01:33:04.171517 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3748 01:33:04.171569 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116
3749 01:33:04.171621 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =100
3750 01:33:04.171680 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =118
3751 01:33:04.171733
3752 01:33:04.171786
3753 01:33:04.171844 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3754 01:33:04.171899 CH1 RK1: MR19=303, MR18=F2ED
3755 01:33:04.171952 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3756 01:33:04.172005 [RxdqsGatingPostProcess] freq 1200
3757 01:33:04.172057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3758 01:33:04.172109 best DQS0 dly(2T, 0.5T) = (0, 11)
3759 01:33:04.172161 best DQS1 dly(2T, 0.5T) = (0, 11)
3760 01:33:04.172222 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3761 01:33:04.172276 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3762 01:33:04.172328 best DQS0 dly(2T, 0.5T) = (0, 11)
3763 01:33:04.172381 best DQS1 dly(2T, 0.5T) = (0, 11)
3764 01:33:04.172433 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3765 01:33:04.172485 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3766 01:33:04.172537 Pre-setting of DQS Precalculation
3767 01:33:04.172590 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3768 01:33:04.172643 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3769 01:33:04.172696 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3770 01:33:04.172748
3771 01:33:04.172801
3772 01:33:04.172852 [Calibration Summary] 2400 Mbps
3773 01:33:04.172904 CH 0, Rank 0
3774 01:33:04.172957 SW Impedance : PASS
3775 01:33:04.173009 DUTY Scan : NO K
3776 01:33:04.173062 ZQ Calibration : PASS
3777 01:33:04.173114 Jitter Meter : NO K
3778 01:33:04.173165 CBT Training : PASS
3779 01:33:04.173218 Write leveling : PASS
3780 01:33:04.173270 RX DQS gating : PASS
3781 01:33:04.173322 RX DQ/DQS(RDDQC) : PASS
3782 01:33:04.173374 TX DQ/DQS : PASS
3783 01:33:04.173426 RX DATLAT : PASS
3784 01:33:04.173478 RX DQ/DQS(Engine): PASS
3785 01:33:04.173529 TX OE : NO K
3786 01:33:04.173581 All Pass.
3787 01:33:04.173633
3788 01:33:04.173685 CH 0, Rank 1
3789 01:33:04.173737 SW Impedance : PASS
3790 01:33:04.173790 DUTY Scan : NO K
3791 01:33:04.173842 ZQ Calibration : PASS
3792 01:33:04.173894 Jitter Meter : NO K
3793 01:33:04.173946 CBT Training : PASS
3794 01:33:04.173997 Write leveling : PASS
3795 01:33:04.174049 RX DQS gating : PASS
3796 01:33:04.174101 RX DQ/DQS(RDDQC) : PASS
3797 01:33:04.174153 TX DQ/DQS : PASS
3798 01:33:04.174214 RX DATLAT : PASS
3799 01:33:04.174267 RX DQ/DQS(Engine): PASS
3800 01:33:04.174318 TX OE : NO K
3801 01:33:04.174370 All Pass.
3802 01:33:04.174423
3803 01:33:04.174475 CH 1, Rank 0
3804 01:33:04.174527 SW Impedance : PASS
3805 01:33:04.174579 DUTY Scan : NO K
3806 01:33:04.174631 ZQ Calibration : PASS
3807 01:33:04.174683 Jitter Meter : NO K
3808 01:33:04.174734 CBT Training : PASS
3809 01:33:04.174787 Write leveling : PASS
3810 01:33:04.174839 RX DQS gating : PASS
3811 01:33:04.174891 RX DQ/DQS(RDDQC) : PASS
3812 01:33:04.174943 TX DQ/DQS : PASS
3813 01:33:04.174994 RX DATLAT : PASS
3814 01:33:04.175046 RX DQ/DQS(Engine): PASS
3815 01:33:04.175098 TX OE : NO K
3816 01:33:04.175150 All Pass.
3817 01:33:04.175202
3818 01:33:04.175253 CH 1, Rank 1
3819 01:33:04.175306 SW Impedance : PASS
3820 01:33:04.175358 DUTY Scan : NO K
3821 01:33:04.175410 ZQ Calibration : PASS
3822 01:33:04.175461 Jitter Meter : NO K
3823 01:33:04.175513 CBT Training : PASS
3824 01:33:04.175565 Write leveling : PASS
3825 01:33:04.175616 RX DQS gating : PASS
3826 01:33:04.175668 RX DQ/DQS(RDDQC) : PASS
3827 01:33:04.175720 TX DQ/DQS : PASS
3828 01:33:04.175779 RX DATLAT : PASS
3829 01:33:04.175832 RX DQ/DQS(Engine): PASS
3830 01:33:04.175884 TX OE : NO K
3831 01:33:04.175936 All Pass.
3832 01:33:04.175988
3833 01:33:04.176040 DramC Write-DBI off
3834 01:33:04.176092 PER_BANK_REFRESH: Hybrid Mode
3835 01:33:04.176144 TX_TRACKING: ON
3836 01:33:04.176197 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3837 01:33:04.176250 [FAST_K] Save calibration result to emmc
3838 01:33:04.176302 dramc_set_vcore_voltage set vcore to 650000
3839 01:33:04.176355 Read voltage for 600, 5
3840 01:33:04.176406 Vio18 = 0
3841 01:33:04.176459 Vcore = 650000
3842 01:33:04.176512 Vdram = 0
3843 01:33:04.176563 Vddq = 0
3844 01:33:04.176615 Vmddr = 0
3845 01:33:04.176667 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3846 01:33:04.176721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3847 01:33:04.176773 MEM_TYPE=3, freq_sel=19
3848 01:33:04.176825 sv_algorithm_assistance_LP4_1600
3849 01:33:04.176878 ============ PULL DRAM RESETB DOWN ============
3850 01:33:04.176930 ========== PULL DRAM RESETB DOWN end =========
3851 01:33:04.176983 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 01:33:04.177035 ===================================
3853 01:33:04.177088 LPDDR4 DRAM CONFIGURATION
3854 01:33:04.177140 ===================================
3855 01:33:04.177192 EX_ROW_EN[0] = 0x0
3856 01:33:04.177244 EX_ROW_EN[1] = 0x0
3857 01:33:04.177296 LP4Y_EN = 0x0
3858 01:33:04.177348 WORK_FSP = 0x0
3859 01:33:04.177400 WL = 0x2
3860 01:33:04.177451 RL = 0x2
3861 01:33:04.177508 BL = 0x2
3862 01:33:04.177570 RPST = 0x0
3863 01:33:04.177623 RD_PRE = 0x0
3864 01:33:04.177675 WR_PRE = 0x1
3865 01:33:04.177726 WR_PST = 0x0
3866 01:33:04.177777 DBI_WR = 0x0
3867 01:33:04.177829 DBI_RD = 0x0
3868 01:33:04.177880 OTF = 0x1
3869 01:33:04.177933 ===================================
3870 01:33:04.178186 ===================================
3871 01:33:04.178246 ANA top config
3872 01:33:04.178300 ===================================
3873 01:33:04.178353 DLL_ASYNC_EN = 0
3874 01:33:04.178405 ALL_SLAVE_EN = 1
3875 01:33:04.178458 NEW_RANK_MODE = 1
3876 01:33:04.178510 DLL_IDLE_MODE = 1
3877 01:33:04.178562 LP45_APHY_COMB_EN = 1
3878 01:33:04.178614 TX_ODT_DIS = 1
3879 01:33:04.178667 NEW_8X_MODE = 1
3880 01:33:04.178720 ===================================
3881 01:33:04.178772 ===================================
3882 01:33:04.178825 data_rate = 1200
3883 01:33:04.178878 CKR = 1
3884 01:33:04.178930 DQ_P2S_RATIO = 8
3885 01:33:04.178982 ===================================
3886 01:33:04.179035 CA_P2S_RATIO = 8
3887 01:33:04.179087 DQ_CA_OPEN = 0
3888 01:33:04.179147 DQ_SEMI_OPEN = 0
3889 01:33:04.179206 CA_SEMI_OPEN = 0
3890 01:33:04.179259 CA_FULL_RATE = 0
3891 01:33:04.179311 DQ_CKDIV4_EN = 1
3892 01:33:04.179365 CA_CKDIV4_EN = 1
3893 01:33:04.179417 CA_PREDIV_EN = 0
3894 01:33:04.179470 PH8_DLY = 0
3895 01:33:04.179522 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3896 01:33:04.179574 DQ_AAMCK_DIV = 4
3897 01:33:04.179626 CA_AAMCK_DIV = 4
3898 01:33:04.179678 CA_ADMCK_DIV = 4
3899 01:33:04.179730 DQ_TRACK_CA_EN = 0
3900 01:33:04.179782 CA_PICK = 600
3901 01:33:04.179833 CA_MCKIO = 600
3902 01:33:04.179886 MCKIO_SEMI = 0
3903 01:33:04.179938 PLL_FREQ = 2288
3904 01:33:04.179990 DQ_UI_PI_RATIO = 32
3905 01:33:04.180042 CA_UI_PI_RATIO = 0
3906 01:33:04.180094 ===================================
3907 01:33:04.180146 ===================================
3908 01:33:04.180198 memory_type:LPDDR4
3909 01:33:04.180251 GP_NUM : 10
3910 01:33:04.180303 SRAM_EN : 1
3911 01:33:04.180355 MD32_EN : 0
3912 01:33:04.180407 ===================================
3913 01:33:04.180460 [ANA_INIT] >>>>>>>>>>>>>>
3914 01:33:04.180512 <<<<<< [CONFIGURE PHASE]: ANA_TX
3915 01:33:04.180565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3916 01:33:04.180617 ===================================
3917 01:33:04.180669 data_rate = 1200,PCW = 0X5800
3918 01:33:04.180721 ===================================
3919 01:33:04.180774 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3920 01:33:04.180827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3921 01:33:04.180879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3922 01:33:04.180931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3923 01:33:04.180984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3924 01:33:04.181036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3925 01:33:04.181088 [ANA_INIT] flow start
3926 01:33:04.181139 [ANA_INIT] PLL >>>>>>>>
3927 01:33:04.181191 [ANA_INIT] PLL <<<<<<<<
3928 01:33:04.181243 [ANA_INIT] MIDPI >>>>>>>>
3929 01:33:04.181295 [ANA_INIT] MIDPI <<<<<<<<
3930 01:33:04.181347 [ANA_INIT] DLL >>>>>>>>
3931 01:33:04.181399 [ANA_INIT] flow end
3932 01:33:04.181451 ============ LP4 DIFF to SE enter ============
3933 01:33:04.181504 ============ LP4 DIFF to SE exit ============
3934 01:33:04.181557 [ANA_INIT] <<<<<<<<<<<<<
3935 01:33:04.181609 [Flow] Enable top DCM control >>>>>
3936 01:33:04.181661 [Flow] Enable top DCM control <<<<<
3937 01:33:04.181713 Enable DLL master slave shuffle
3938 01:33:04.181765 ==============================================================
3939 01:33:04.181817 Gating Mode config
3940 01:33:04.181877 ==============================================================
3941 01:33:04.181937 Config description:
3942 01:33:04.181989 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3943 01:33:04.182043 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3944 01:33:04.182096 SELPH_MODE 0: By rank 1: By Phase
3945 01:33:04.182166 ==============================================================
3946 01:33:04.182224 GAT_TRACK_EN = 1
3947 01:33:04.185391 RX_GATING_MODE = 2
3948 01:33:04.189286 RX_GATING_TRACK_MODE = 2
3949 01:33:04.192468 SELPH_MODE = 1
3950 01:33:04.192620 PICG_EARLY_EN = 1
3951 01:33:04.195840 VALID_LAT_VALUE = 1
3952 01:33:04.202447 ==============================================================
3953 01:33:04.205892 Enter into Gating configuration >>>>
3954 01:33:04.208669 Exit from Gating configuration <<<<
3955 01:33:04.211890 Enter into DVFS_PRE_config >>>>>
3956 01:33:04.222267 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3957 01:33:04.225625 Exit from DVFS_PRE_config <<<<<
3958 01:33:04.229040 Enter into PICG configuration >>>>
3959 01:33:04.232879 Exit from PICG configuration <<<<
3960 01:33:04.235684 [RX_INPUT] configuration >>>>>
3961 01:33:04.238658 [RX_INPUT] configuration <<<<<
3962 01:33:04.242200 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3963 01:33:04.249380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3964 01:33:04.255076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3965 01:33:04.262013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3966 01:33:04.268602 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3967 01:33:04.275084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3968 01:33:04.278130 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3969 01:33:04.281370 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3970 01:33:04.284783 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3971 01:33:04.291440 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3972 01:33:04.294875 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3973 01:33:04.298054 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3974 01:33:04.301269 ===================================
3975 01:33:04.304738 LPDDR4 DRAM CONFIGURATION
3976 01:33:04.308112 ===================================
3977 01:33:04.308628 EX_ROW_EN[0] = 0x0
3978 01:33:04.311191 EX_ROW_EN[1] = 0x0
3979 01:33:04.314192 LP4Y_EN = 0x0
3980 01:33:04.314493 WORK_FSP = 0x0
3981 01:33:04.317515 WL = 0x2
3982 01:33:04.317815 RL = 0x2
3983 01:33:04.321436 BL = 0x2
3984 01:33:04.321736 RPST = 0x0
3985 01:33:04.324098 RD_PRE = 0x0
3986 01:33:04.324425 WR_PRE = 0x1
3987 01:33:04.327330 WR_PST = 0x0
3988 01:33:04.327720 DBI_WR = 0x0
3989 01:33:04.330484 DBI_RD = 0x0
3990 01:33:04.330787 OTF = 0x1
3991 01:33:04.333819 ===================================
3992 01:33:04.340923 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3993 01:33:04.344160 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3994 01:33:04.347114 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3995 01:33:04.350320 ===================================
3996 01:33:04.353997 LPDDR4 DRAM CONFIGURATION
3997 01:33:04.356924 ===================================
3998 01:33:04.360171 EX_ROW_EN[0] = 0x10
3999 01:33:04.360640 EX_ROW_EN[1] = 0x0
4000 01:33:04.363643 LP4Y_EN = 0x0
4001 01:33:04.364112 WORK_FSP = 0x0
4002 01:33:04.366828 WL = 0x2
4003 01:33:04.367388 RL = 0x2
4004 01:33:04.370329 BL = 0x2
4005 01:33:04.370885 RPST = 0x0
4006 01:33:04.373190 RD_PRE = 0x0
4007 01:33:04.373652 WR_PRE = 0x1
4008 01:33:04.376549 WR_PST = 0x0
4009 01:33:04.377015 DBI_WR = 0x0
4010 01:33:04.380052 DBI_RD = 0x0
4011 01:33:04.380608 OTF = 0x1
4012 01:33:04.383506 ===================================
4013 01:33:04.389839 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4014 01:33:04.394706 nWR fixed to 30
4015 01:33:04.398527 [ModeRegInit_LP4] CH0 RK0
4016 01:33:04.399082 [ModeRegInit_LP4] CH0 RK1
4017 01:33:04.401392 [ModeRegInit_LP4] CH1 RK0
4018 01:33:04.404730 [ModeRegInit_LP4] CH1 RK1
4019 01:33:04.405277 match AC timing 17
4020 01:33:04.411300 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4021 01:33:04.414778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4022 01:33:04.418139 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4023 01:33:04.424461 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4024 01:33:04.428022 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4025 01:33:04.428592 ==
4026 01:33:04.430997 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 01:33:04.434428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 01:33:04.434984 ==
4029 01:33:04.440969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4030 01:33:04.447433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4031 01:33:04.450927 [CA 0] Center 36 (6~66) winsize 61
4032 01:33:04.453928 [CA 1] Center 36 (6~66) winsize 61
4033 01:33:04.457547 [CA 2] Center 34 (4~65) winsize 62
4034 01:33:04.460732 [CA 3] Center 34 (4~65) winsize 62
4035 01:33:04.463574 [CA 4] Center 33 (3~64) winsize 62
4036 01:33:04.467153 [CA 5] Center 33 (3~64) winsize 62
4037 01:33:04.467617
4038 01:33:04.470435 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4039 01:33:04.470898
4040 01:33:04.474054 [CATrainingPosCal] consider 1 rank data
4041 01:33:04.477731 u2DelayCellTimex100 = 270/100 ps
4042 01:33:04.481342 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4043 01:33:04.483671 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4044 01:33:04.487276 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4045 01:33:04.493700 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4046 01:33:04.497453 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4047 01:33:04.500441 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4048 01:33:04.500906
4049 01:33:04.503923 CA PerBit enable=1, Macro0, CA PI delay=33
4050 01:33:04.504479
4051 01:33:04.507068 [CBTSetCACLKResult] CA Dly = 33
4052 01:33:04.507585 CS Dly: 5 (0~36)
4053 01:33:04.507999 ==
4054 01:33:04.510430 Dram Type= 6, Freq= 0, CH_0, rank 1
4055 01:33:04.516813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 01:33:04.517371 ==
4057 01:33:04.520258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4058 01:33:04.526794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4059 01:33:04.530245 [CA 0] Center 36 (6~66) winsize 61
4060 01:33:04.533947 [CA 1] Center 36 (6~66) winsize 61
4061 01:33:04.537087 [CA 2] Center 34 (3~65) winsize 63
4062 01:33:04.540637 [CA 3] Center 33 (3~64) winsize 62
4063 01:33:04.543253 [CA 4] Center 33 (2~64) winsize 63
4064 01:33:04.546235 [CA 5] Center 33 (2~64) winsize 63
4065 01:33:04.546700
4066 01:33:04.550146 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4067 01:33:04.550763
4068 01:33:04.553093 [CATrainingPosCal] consider 2 rank data
4069 01:33:04.556442 u2DelayCellTimex100 = 270/100 ps
4070 01:33:04.559705 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4071 01:33:04.566441 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4072 01:33:04.569623 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4073 01:33:04.572697 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4074 01:33:04.576093 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4075 01:33:04.579300 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4076 01:33:04.579955
4077 01:33:04.582745 CA PerBit enable=1, Macro0, CA PI delay=33
4078 01:33:04.583208
4079 01:33:04.585858 [CBTSetCACLKResult] CA Dly = 33
4080 01:33:04.589180 CS Dly: 5 (0~36)
4081 01:33:04.589651
4082 01:33:04.592497 ----->DramcWriteLeveling(PI) begin...
4083 01:33:04.592925 ==
4084 01:33:04.596137 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 01:33:04.599677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 01:33:04.600198 ==
4087 01:33:04.602585 Write leveling (Byte 0): 35 => 35
4088 01:33:04.605488 Write leveling (Byte 1): 31 => 31
4089 01:33:04.609010 DramcWriteLeveling(PI) end<-----
4090 01:33:04.609482
4091 01:33:04.609856 ==
4092 01:33:04.612354 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 01:33:04.615684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 01:33:04.616152 ==
4095 01:33:04.618735 [Gating] SW mode calibration
4096 01:33:04.625413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4097 01:33:04.631769 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4098 01:33:04.635481 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4099 01:33:04.638522 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4100 01:33:04.645675 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4101 01:33:04.648452 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4102 01:33:04.652119 0 9 16 | B1->B0 | 3030 2727 | 0 0 | (0 0) (0 0)
4103 01:33:04.658430 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4104 01:33:04.661599 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 01:33:04.665101 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4106 01:33:04.671834 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4107 01:33:04.674871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4108 01:33:04.678259 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4109 01:33:04.685270 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4110 01:33:04.688566 0 10 16 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
4111 01:33:04.695021 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 01:33:04.698065 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 01:33:04.701427 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 01:33:04.707841 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 01:33:04.711096 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 01:33:04.714412 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4117 01:33:04.721167 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4118 01:33:04.724416 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4119 01:33:04.727555 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 01:33:04.730935 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 01:33:04.737717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 01:33:04.741367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 01:33:04.743949 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 01:33:04.750528 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 01:33:04.753930 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 01:33:04.757383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 01:33:04.764172 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 01:33:04.767577 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 01:33:04.770482 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 01:33:04.777657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 01:33:04.780331 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 01:33:04.784343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4133 01:33:04.790338 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4134 01:33:04.793725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4135 01:33:04.797151 Total UI for P1: 0, mck2ui 16
4136 01:33:04.800510 best dqsien dly found for B0: ( 0, 13, 14)
4137 01:33:04.804010 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4138 01:33:04.807084 Total UI for P1: 0, mck2ui 16
4139 01:33:04.810320 best dqsien dly found for B1: ( 0, 13, 16)
4140 01:33:04.813425 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4141 01:33:04.820484 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4142 01:33:04.821048
4143 01:33:04.824118 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4144 01:33:04.826591 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4145 01:33:04.830156 [Gating] SW calibration Done
4146 01:33:04.830776 ==
4147 01:33:04.833505 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 01:33:04.836565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 01:33:04.837034 ==
4150 01:33:04.839815 RX Vref Scan: 0
4151 01:33:04.840284
4152 01:33:04.840657 RX Vref 0 -> 0, step: 1
4153 01:33:04.841009
4154 01:33:04.843069 RX Delay -230 -> 252, step: 16
4155 01:33:04.846516 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4156 01:33:04.852779 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4157 01:33:04.856781 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4158 01:33:04.859575 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4159 01:33:04.862977 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4160 01:33:04.869679 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4161 01:33:04.872618 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4162 01:33:04.876020 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4163 01:33:04.879468 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4164 01:33:04.886297 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4165 01:33:04.889450 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4166 01:33:04.892689 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4167 01:33:04.895868 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4168 01:33:04.902608 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4169 01:33:04.905649 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4170 01:33:04.909256 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4171 01:33:04.909775 ==
4172 01:33:04.912390 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 01:33:04.915752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 01:33:04.916290 ==
4175 01:33:04.919454 DQS Delay:
4176 01:33:04.920013 DQS0 = 0, DQS1 = 0
4177 01:33:04.922227 DQM Delay:
4178 01:33:04.922697 DQM0 = 40, DQM1 = 30
4179 01:33:04.923070 DQ Delay:
4180 01:33:04.925800 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4181 01:33:04.928671 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4182 01:33:04.932404 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4183 01:33:04.935746 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4184 01:33:04.936213
4185 01:33:04.936584
4186 01:33:04.938909 ==
4187 01:33:04.942055 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 01:33:04.946132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 01:33:04.946935 ==
4190 01:33:04.947331
4191 01:33:04.947677
4192 01:33:04.948881 TX Vref Scan disable
4193 01:33:04.949344 == TX Byte 0 ==
4194 01:33:04.955752 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4195 01:33:04.958924 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4196 01:33:04.959483 == TX Byte 1 ==
4197 01:33:04.965345 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4198 01:33:04.969095 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4199 01:33:04.969656 ==
4200 01:33:04.971694 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 01:33:04.975418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 01:33:04.975885 ==
4203 01:33:04.976256
4204 01:33:04.976648
4205 01:33:04.978426 TX Vref Scan disable
4206 01:33:04.982028 == TX Byte 0 ==
4207 01:33:04.984993 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4208 01:33:04.991686 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4209 01:33:04.992231 == TX Byte 1 ==
4210 01:33:04.994639 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4211 01:33:05.001641 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4212 01:33:05.002225
4213 01:33:05.002611 [DATLAT]
4214 01:33:05.002960 Freq=600, CH0 RK0
4215 01:33:05.003294
4216 01:33:05.004599 DATLAT Default: 0x9
4217 01:33:05.008204 0, 0xFFFF, sum = 0
4218 01:33:05.008768 1, 0xFFFF, sum = 0
4219 01:33:05.011245 2, 0xFFFF, sum = 0
4220 01:33:05.011749 3, 0xFFFF, sum = 0
4221 01:33:05.014368 4, 0xFFFF, sum = 0
4222 01:33:05.014926 5, 0xFFFF, sum = 0
4223 01:33:05.017715 6, 0xFFFF, sum = 0
4224 01:33:05.018225 7, 0xFFFF, sum = 0
4225 01:33:05.020969 8, 0x0, sum = 1
4226 01:33:05.021441 9, 0x0, sum = 2
4227 01:33:05.024234 10, 0x0, sum = 3
4228 01:33:05.024711 11, 0x0, sum = 4
4229 01:33:05.025095 best_step = 9
4230 01:33:05.025474
4231 01:33:05.027446 ==
4232 01:33:05.030841 Dram Type= 6, Freq= 0, CH_0, rank 0
4233 01:33:05.034368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 01:33:05.034831 ==
4235 01:33:05.035196 RX Vref Scan: 1
4236 01:33:05.035532
4237 01:33:05.037210 RX Vref 0 -> 0, step: 1
4238 01:33:05.037667
4239 01:33:05.040879 RX Delay -195 -> 252, step: 8
4240 01:33:05.041292
4241 01:33:05.044078 Set Vref, RX VrefLevel [Byte0]: 60
4242 01:33:05.046961 [Byte1]: 52
4243 01:33:05.050193
4244 01:33:05.050613 Final RX Vref Byte 0 = 60 to rank0
4245 01:33:05.053530 Final RX Vref Byte 1 = 52 to rank0
4246 01:33:05.057122 Final RX Vref Byte 0 = 60 to rank1
4247 01:33:05.060223 Final RX Vref Byte 1 = 52 to rank1==
4248 01:33:05.064214 Dram Type= 6, Freq= 0, CH_0, rank 0
4249 01:33:05.070428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 01:33:05.070982 ==
4251 01:33:05.071354 DQS Delay:
4252 01:33:05.073490 DQS0 = 0, DQS1 = 0
4253 01:33:05.073948 DQM Delay:
4254 01:33:05.074361 DQM0 = 43, DQM1 = 32
4255 01:33:05.076823 DQ Delay:
4256 01:33:05.080201 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4257 01:33:05.083407 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4258 01:33:05.086865 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4259 01:33:05.090066 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4260 01:33:05.090609
4261 01:33:05.090941
4262 01:33:05.096701 [DQSOSCAuto] RK0, (LSB)MR18= 0x623a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4263 01:33:05.099941 CH0 RK0: MR19=808, MR18=623A
4264 01:33:05.106328 CH0_RK0: MR19=0x808, MR18=0x623A, DQSOSC=391, MR23=63, INC=171, DEC=114
4265 01:33:05.106817
4266 01:33:05.109936 ----->DramcWriteLeveling(PI) begin...
4267 01:33:05.110404 ==
4268 01:33:05.113366 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 01:33:05.116619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 01:33:05.117189 ==
4271 01:33:05.119637 Write leveling (Byte 0): 34 => 34
4272 01:33:05.122823 Write leveling (Byte 1): 30 => 30
4273 01:33:05.126139 DramcWriteLeveling(PI) end<-----
4274 01:33:05.126630
4275 01:33:05.126996 ==
4276 01:33:05.130090 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 01:33:05.132909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 01:33:05.136012 ==
4279 01:33:05.136477 [Gating] SW mode calibration
4280 01:33:05.146135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4281 01:33:05.149680 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4282 01:33:05.152479 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4283 01:33:05.159343 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4284 01:33:05.162428 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4285 01:33:05.165883 0 9 12 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
4286 01:33:05.173035 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
4287 01:33:05.175799 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 01:33:05.179076 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 01:33:05.185682 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 01:33:05.189066 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 01:33:05.192478 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 01:33:05.198568 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 01:33:05.202315 0 10 12 | B1->B0 | 2525 2626 | 0 0 | (0 0) (1 1)
4294 01:33:05.205520 0 10 16 | B1->B0 | 3b3b 3f3f | 1 0 | (0 0) (0 0)
4295 01:33:05.211632 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 01:33:05.215281 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 01:33:05.219094 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 01:33:05.225483 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 01:33:05.228211 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 01:33:05.231858 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 01:33:05.238254 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4302 01:33:05.241463 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4303 01:33:05.244549 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 01:33:05.251094 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 01:33:05.254709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 01:33:05.257532 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 01:33:05.264682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 01:33:05.267994 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 01:33:05.271156 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 01:33:05.277468 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 01:33:05.281055 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 01:33:05.284102 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 01:33:05.290797 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 01:33:05.293879 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 01:33:05.297685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 01:33:05.303806 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 01:33:05.307454 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4318 01:33:05.310230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4319 01:33:05.314211 Total UI for P1: 0, mck2ui 16
4320 01:33:05.317235 best dqsien dly found for B0: ( 0, 13, 12)
4321 01:33:05.320417 Total UI for P1: 0, mck2ui 16
4322 01:33:05.324023 best dqsien dly found for B1: ( 0, 13, 12)
4323 01:33:05.330198 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4324 01:33:05.333968 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4325 01:33:05.334487
4326 01:33:05.337004 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4327 01:33:05.340328 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4328 01:33:05.343228 [Gating] SW calibration Done
4329 01:33:05.343643 ==
4330 01:33:05.346668 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 01:33:05.350127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 01:33:05.350571 ==
4333 01:33:05.353351 RX Vref Scan: 0
4334 01:33:05.353763
4335 01:33:05.354090 RX Vref 0 -> 0, step: 1
4336 01:33:05.354519
4337 01:33:05.356822 RX Delay -230 -> 252, step: 16
4338 01:33:05.363366 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4339 01:33:05.366318 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4340 01:33:05.369659 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4341 01:33:05.372933 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4342 01:33:05.376060 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4343 01:33:05.383370 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4344 01:33:05.386781 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4345 01:33:05.389693 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4346 01:33:05.392852 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4347 01:33:05.399505 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4348 01:33:05.403045 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4349 01:33:05.406777 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4350 01:33:05.409269 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4351 01:33:05.415915 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4352 01:33:05.419351 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4353 01:33:05.422468 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4354 01:33:05.422885 ==
4355 01:33:05.426036 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 01:33:05.429207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 01:33:05.429830 ==
4358 01:33:05.432836 DQS Delay:
4359 01:33:05.433348 DQS0 = 0, DQS1 = 0
4360 01:33:05.435798 DQM Delay:
4361 01:33:05.436254 DQM0 = 41, DQM1 = 32
4362 01:33:05.436626 DQ Delay:
4363 01:33:05.439063 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4364 01:33:05.442388 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4365 01:33:05.445797 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4366 01:33:05.449169 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =33
4367 01:33:05.449584
4368 01:33:05.452144
4369 01:33:05.452702 ==
4370 01:33:05.455428 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 01:33:05.459094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 01:33:05.459531 ==
4373 01:33:05.459862
4374 01:33:05.460164
4375 01:33:05.462283 TX Vref Scan disable
4376 01:33:05.462715 == TX Byte 0 ==
4377 01:33:05.469401 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4378 01:33:05.472256 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4379 01:33:05.472823 == TX Byte 1 ==
4380 01:33:05.478797 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4381 01:33:05.482302 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4382 01:33:05.482855 ==
4383 01:33:05.485375 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 01:33:05.488877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 01:33:05.489411 ==
4386 01:33:05.489749
4387 01:33:05.490057
4388 01:33:05.492066 TX Vref Scan disable
4389 01:33:05.495305 == TX Byte 0 ==
4390 01:33:05.498730 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4391 01:33:05.505218 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4392 01:33:05.505767 == TX Byte 1 ==
4393 01:33:05.508318 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4394 01:33:05.515081 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4395 01:33:05.515600
4396 01:33:05.515949 [DATLAT]
4397 01:33:05.516257 Freq=600, CH0 RK1
4398 01:33:05.516559
4399 01:33:05.518285 DATLAT Default: 0x9
4400 01:33:05.518704 0, 0xFFFF, sum = 0
4401 01:33:05.521673 1, 0xFFFF, sum = 0
4402 01:33:05.524951 2, 0xFFFF, sum = 0
4403 01:33:05.525475 3, 0xFFFF, sum = 0
4404 01:33:05.528245 4, 0xFFFF, sum = 0
4405 01:33:05.528803 5, 0xFFFF, sum = 0
4406 01:33:05.531358 6, 0xFFFF, sum = 0
4407 01:33:05.531776 7, 0xFFFF, sum = 0
4408 01:33:05.534689 8, 0x0, sum = 1
4409 01:33:05.535111 9, 0x0, sum = 2
4410 01:33:05.538243 10, 0x0, sum = 3
4411 01:33:05.538756 11, 0x0, sum = 4
4412 01:33:05.539095 best_step = 9
4413 01:33:05.539402
4414 01:33:05.541588 ==
4415 01:33:05.544404 Dram Type= 6, Freq= 0, CH_0, rank 1
4416 01:33:05.548721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 01:33:05.549269 ==
4418 01:33:05.549635 RX Vref Scan: 0
4419 01:33:05.549974
4420 01:33:05.551358 RX Vref 0 -> 0, step: 1
4421 01:33:05.551812
4422 01:33:05.554555 RX Delay -195 -> 252, step: 8
4423 01:33:05.561003 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4424 01:33:05.564293 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4425 01:33:05.567842 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4426 01:33:05.571169 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4427 01:33:05.574268 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4428 01:33:05.581142 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4429 01:33:05.584139 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4430 01:33:05.587406 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4431 01:33:05.590852 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4432 01:33:05.597169 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4433 01:33:05.601161 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4434 01:33:05.604224 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4435 01:33:05.606971 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4436 01:33:05.613713 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4437 01:33:05.617254 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4438 01:33:05.620252 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4439 01:33:05.620673 ==
4440 01:33:05.623296 Dram Type= 6, Freq= 0, CH_0, rank 1
4441 01:33:05.627066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 01:33:05.630071 ==
4443 01:33:05.630729 DQS Delay:
4444 01:33:05.631257 DQS0 = 0, DQS1 = 0
4445 01:33:05.633510 DQM Delay:
4446 01:33:05.634022 DQM0 = 41, DQM1 = 36
4447 01:33:05.636722 DQ Delay:
4448 01:33:05.640381 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4449 01:33:05.643677 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4450 01:33:05.646994 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4451 01:33:05.649952 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4452 01:33:05.650494
4453 01:33:05.650959
4454 01:33:05.656860 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a0e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4455 01:33:05.659791 CH0 RK1: MR19=808, MR18=5A0E
4456 01:33:05.666681 CH0_RK1: MR19=0x808, MR18=0x5A0E, DQSOSC=392, MR23=63, INC=170, DEC=113
4457 01:33:05.669748 [RxdqsGatingPostProcess] freq 600
4458 01:33:05.673575 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4459 01:33:05.676528 Pre-setting of DQS Precalculation
4460 01:33:05.683200 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4461 01:33:05.683729 ==
4462 01:33:05.686599 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 01:33:05.689862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 01:33:05.690409 ==
4465 01:33:05.696096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4466 01:33:05.703143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4467 01:33:05.706148 [CA 0] Center 35 (5~66) winsize 62
4468 01:33:05.709674 [CA 1] Center 35 (5~66) winsize 62
4469 01:33:05.712740 [CA 2] Center 34 (4~65) winsize 62
4470 01:33:05.716134 [CA 3] Center 33 (3~64) winsize 62
4471 01:33:05.719302 [CA 4] Center 34 (4~64) winsize 61
4472 01:33:05.722757 [CA 5] Center 33 (3~64) winsize 62
4473 01:33:05.723221
4474 01:33:05.725848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4475 01:33:05.726447
4476 01:33:05.729021 [CATrainingPosCal] consider 1 rank data
4477 01:33:05.732069 u2DelayCellTimex100 = 270/100 ps
4478 01:33:05.735585 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4479 01:33:05.738899 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4480 01:33:05.742363 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4481 01:33:05.745652 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 01:33:05.748960 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4483 01:33:05.752287 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4484 01:33:05.752847
4485 01:33:05.759393 CA PerBit enable=1, Macro0, CA PI delay=33
4486 01:33:05.759956
4487 01:33:05.761750 [CBTSetCACLKResult] CA Dly = 33
4488 01:33:05.762257 CS Dly: 4 (0~35)
4489 01:33:05.762637 ==
4490 01:33:05.765622 Dram Type= 6, Freq= 0, CH_1, rank 1
4491 01:33:05.768446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 01:33:05.768911 ==
4493 01:33:05.775482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4494 01:33:05.781721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4495 01:33:05.785086 [CA 0] Center 35 (5~66) winsize 62
4496 01:33:05.788106 [CA 1] Center 36 (6~66) winsize 61
4497 01:33:05.791435 [CA 2] Center 34 (4~65) winsize 62
4498 01:33:05.794709 [CA 3] Center 34 (4~65) winsize 62
4499 01:33:05.797683 [CA 4] Center 34 (4~65) winsize 62
4500 01:33:05.801007 [CA 5] Center 34 (3~65) winsize 63
4501 01:33:05.801427
4502 01:33:05.804369 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4503 01:33:05.804788
4504 01:33:05.808191 [CATrainingPosCal] consider 2 rank data
4505 01:33:05.810848 u2DelayCellTimex100 = 270/100 ps
4506 01:33:05.814375 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4507 01:33:05.817885 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4508 01:33:05.820977 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4509 01:33:05.827641 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4510 01:33:05.830928 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4511 01:33:05.834155 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4512 01:33:05.834622
4513 01:33:05.837327 CA PerBit enable=1, Macro0, CA PI delay=33
4514 01:33:05.837752
4515 01:33:05.840587 [CBTSetCACLKResult] CA Dly = 33
4516 01:33:05.841007 CS Dly: 5 (0~37)
4517 01:33:05.841356
4518 01:33:05.844174 ----->DramcWriteLeveling(PI) begin...
4519 01:33:05.847586 ==
4520 01:33:05.850745 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 01:33:05.853935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 01:33:05.854464 ==
4523 01:33:05.857380 Write leveling (Byte 0): 28 => 28
4524 01:33:05.860894 Write leveling (Byte 1): 31 => 31
4525 01:33:05.864252 DramcWriteLeveling(PI) end<-----
4526 01:33:05.864783
4527 01:33:05.865218 ==
4528 01:33:05.867550 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 01:33:05.870825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 01:33:05.871251 ==
4531 01:33:05.873979 [Gating] SW mode calibration
4532 01:33:05.880926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4533 01:33:05.886794 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4534 01:33:05.890095 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4535 01:33:05.893654 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4536 01:33:05.899991 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4537 01:33:05.903559 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
4538 01:33:05.907424 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4539 01:33:05.913354 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4540 01:33:05.916818 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4541 01:33:05.920427 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4542 01:33:05.926355 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4543 01:33:05.930448 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4544 01:33:05.933567 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4545 01:33:05.939763 0 10 12 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (0 0)
4546 01:33:05.943169 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4547 01:33:05.946220 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 01:33:05.952982 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 01:33:05.956045 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 01:33:05.959382 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4551 01:33:05.966073 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 01:33:05.969418 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4553 01:33:05.972414 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4554 01:33:05.979012 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 01:33:05.982250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 01:33:05.985710 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 01:33:05.992739 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 01:33:05.995872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 01:33:05.999266 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 01:33:06.005877 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 01:33:06.009071 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 01:33:06.012693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 01:33:06.018842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 01:33:06.022219 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 01:33:06.025534 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 01:33:06.031797 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 01:33:06.035464 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 01:33:06.038799 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 01:33:06.045429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4570 01:33:06.049289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4571 01:33:06.052250 Total UI for P1: 0, mck2ui 16
4572 01:33:06.055053 best dqsien dly found for B0: ( 0, 13, 12)
4573 01:33:06.058956 Total UI for P1: 0, mck2ui 16
4574 01:33:06.061733 best dqsien dly found for B1: ( 0, 13, 12)
4575 01:33:06.064680 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4576 01:33:06.068592 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4577 01:33:06.069143
4578 01:33:06.071444 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4579 01:33:06.074878 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4580 01:33:06.077888 [Gating] SW calibration Done
4581 01:33:06.078345 ==
4582 01:33:06.080995 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 01:33:06.088088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 01:33:06.088605 ==
4585 01:33:06.088939 RX Vref Scan: 0
4586 01:33:06.089249
4587 01:33:06.091394 RX Vref 0 -> 0, step: 1
4588 01:33:06.091912
4589 01:33:06.094461 RX Delay -230 -> 252, step: 16
4590 01:33:06.097543 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4591 01:33:06.100913 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4592 01:33:06.104329 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4593 01:33:06.110822 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4594 01:33:06.113930 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4595 01:33:06.117879 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4596 01:33:06.121142 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4597 01:33:06.127755 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4598 01:33:06.130698 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4599 01:33:06.133839 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4600 01:33:06.137534 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4601 01:33:06.144486 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4602 01:33:06.147077 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4603 01:33:06.150863 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4604 01:33:06.153863 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4605 01:33:06.160528 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4606 01:33:06.161028 ==
4607 01:33:06.163969 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 01:33:06.167240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 01:33:06.167775 ==
4610 01:33:06.168112 DQS Delay:
4611 01:33:06.170561 DQS0 = 0, DQS1 = 0
4612 01:33:06.171077 DQM Delay:
4613 01:33:06.173721 DQM0 = 45, DQM1 = 33
4614 01:33:06.174137 DQ Delay:
4615 01:33:06.177142 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4616 01:33:06.180444 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =41
4617 01:33:06.183654 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4618 01:33:06.187578 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4619 01:33:06.188094
4620 01:33:06.188426
4621 01:33:06.188734 ==
4622 01:33:06.190231 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 01:33:06.193681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 01:33:06.194236 ==
4625 01:33:06.194589
4626 01:33:06.194903
4627 01:33:06.196823 TX Vref Scan disable
4628 01:33:06.199901 == TX Byte 0 ==
4629 01:33:06.203759 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4630 01:33:06.207022 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4631 01:33:06.210132 == TX Byte 1 ==
4632 01:33:06.213265 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4633 01:33:06.216505 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4634 01:33:06.216926 ==
4635 01:33:06.220060 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 01:33:06.227115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 01:33:06.227633 ==
4638 01:33:06.227967
4639 01:33:06.228275
4640 01:33:06.228568 TX Vref Scan disable
4641 01:33:06.231212 == TX Byte 0 ==
4642 01:33:06.234446 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4643 01:33:06.241380 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4644 01:33:06.241801 == TX Byte 1 ==
4645 01:33:06.244617 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4646 01:33:06.250856 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4647 01:33:06.251368
4648 01:33:06.251700 [DATLAT]
4649 01:33:06.252009 Freq=600, CH1 RK0
4650 01:33:06.252315
4651 01:33:06.254233 DATLAT Default: 0x9
4652 01:33:06.254655 0, 0xFFFF, sum = 0
4653 01:33:06.257580 1, 0xFFFF, sum = 0
4654 01:33:06.260925 2, 0xFFFF, sum = 0
4655 01:33:06.261352 3, 0xFFFF, sum = 0
4656 01:33:06.264277 4, 0xFFFF, sum = 0
4657 01:33:06.264746 5, 0xFFFF, sum = 0
4658 01:33:06.267209 6, 0xFFFF, sum = 0
4659 01:33:06.267637 7, 0xFFFF, sum = 0
4660 01:33:06.270738 8, 0x0, sum = 1
4661 01:33:06.271327 9, 0x0, sum = 2
4662 01:33:06.274107 10, 0x0, sum = 3
4663 01:33:06.274580 11, 0x0, sum = 4
4664 01:33:06.274923 best_step = 9
4665 01:33:06.275236
4666 01:33:06.277408 ==
4667 01:33:06.280803 Dram Type= 6, Freq= 0, CH_1, rank 0
4668 01:33:06.283656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 01:33:06.284082 ==
4670 01:33:06.284433 RX Vref Scan: 1
4671 01:33:06.284750
4672 01:33:06.286898 RX Vref 0 -> 0, step: 1
4673 01:33:06.287316
4674 01:33:06.290406 RX Delay -195 -> 252, step: 8
4675 01:33:06.290952
4676 01:33:06.293820 Set Vref, RX VrefLevel [Byte0]: 52
4677 01:33:06.296822 [Byte1]: 54
4678 01:33:06.297245
4679 01:33:06.300360 Final RX Vref Byte 0 = 52 to rank0
4680 01:33:06.303591 Final RX Vref Byte 1 = 54 to rank0
4681 01:33:06.306695 Final RX Vref Byte 0 = 52 to rank1
4682 01:33:06.309990 Final RX Vref Byte 1 = 54 to rank1==
4683 01:33:06.313348 Dram Type= 6, Freq= 0, CH_1, rank 0
4684 01:33:06.320372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 01:33:06.320934 ==
4686 01:33:06.321308 DQS Delay:
4687 01:33:06.321646 DQS0 = 0, DQS1 = 0
4688 01:33:06.323287 DQM Delay:
4689 01:33:06.323744 DQM0 = 45, DQM1 = 34
4690 01:33:06.326685 DQ Delay:
4691 01:33:06.330003 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4692 01:33:06.333109 DQ4 =40, DQ5 =56, DQ6 =56, DQ7 =40
4693 01:33:06.333531 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4694 01:33:06.340015 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4695 01:33:06.340434
4696 01:33:06.340769
4697 01:33:06.346370 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4698 01:33:06.349695 CH1 RK0: MR19=808, MR18=4A2F
4699 01:33:06.356289 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4700 01:33:06.356711
4701 01:33:06.360059 ----->DramcWriteLeveling(PI) begin...
4702 01:33:06.360581 ==
4703 01:33:06.363052 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 01:33:06.366728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 01:33:06.367249 ==
4706 01:33:06.369635 Write leveling (Byte 0): 29 => 29
4707 01:33:06.372892 Write leveling (Byte 1): 31 => 31
4708 01:33:06.376324 DramcWriteLeveling(PI) end<-----
4709 01:33:06.376860
4710 01:33:06.377199 ==
4711 01:33:06.379505 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 01:33:06.383149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 01:33:06.383669 ==
4714 01:33:06.386023 [Gating] SW mode calibration
4715 01:33:06.393004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4716 01:33:06.399171 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4717 01:33:06.402697 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4718 01:33:06.409586 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4719 01:33:06.412767 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4720 01:33:06.415688 0 9 12 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 1)
4721 01:33:06.422344 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4722 01:33:06.425902 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4723 01:33:06.429039 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4724 01:33:06.435382 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4725 01:33:06.438723 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4726 01:33:06.442438 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4727 01:33:06.448584 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4728 01:33:06.452336 0 10 12 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (0 0)
4729 01:33:06.455513 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 01:33:06.462141 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 01:33:06.465187 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 01:33:06.468139 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 01:33:06.474514 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 01:33:06.478070 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 01:33:06.481522 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4736 01:33:06.488641 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4737 01:33:06.491091 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 01:33:06.494563 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 01:33:06.501301 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 01:33:06.504768 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 01:33:06.508524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 01:33:06.514596 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 01:33:06.517607 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 01:33:06.521214 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 01:33:06.527524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 01:33:06.530895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 01:33:06.534062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 01:33:06.540620 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 01:33:06.544218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 01:33:06.546889 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 01:33:06.553995 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4752 01:33:06.556949 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4753 01:33:06.560345 Total UI for P1: 0, mck2ui 16
4754 01:33:06.563770 best dqsien dly found for B1: ( 0, 13, 10)
4755 01:33:06.567193 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4756 01:33:06.569934 Total UI for P1: 0, mck2ui 16
4757 01:33:06.574005 best dqsien dly found for B0: ( 0, 13, 10)
4758 01:33:06.576999 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4759 01:33:06.583031 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4760 01:33:06.583583
4761 01:33:06.586501 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4762 01:33:06.589945 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4763 01:33:06.593247 [Gating] SW calibration Done
4764 01:33:06.593816 ==
4765 01:33:06.596400 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 01:33:06.599598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 01:33:06.600069 ==
4768 01:33:06.602837 RX Vref Scan: 0
4769 01:33:06.603302
4770 01:33:06.603668 RX Vref 0 -> 0, step: 1
4771 01:33:06.604016
4772 01:33:06.606446 RX Delay -230 -> 252, step: 16
4773 01:33:06.612598 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4774 01:33:06.616405 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4775 01:33:06.619355 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4776 01:33:06.622856 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4777 01:33:06.625814 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4778 01:33:06.632511 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4779 01:33:06.636386 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4780 01:33:06.638975 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4781 01:33:06.642644 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4782 01:33:06.649371 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4783 01:33:06.652926 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4784 01:33:06.655524 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4785 01:33:06.659096 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4786 01:33:06.665563 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4787 01:33:06.669105 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4788 01:33:06.672299 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4789 01:33:06.672875 ==
4790 01:33:06.675427 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 01:33:06.678518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 01:33:06.681976 ==
4793 01:33:06.682466 DQS Delay:
4794 01:33:06.682842 DQS0 = 0, DQS1 = 0
4795 01:33:06.685148 DQM Delay:
4796 01:33:06.685609 DQM0 = 42, DQM1 = 37
4797 01:33:06.688625 DQ Delay:
4798 01:33:06.689216 DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =41
4799 01:33:06.691920 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4800 01:33:06.695026 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =33
4801 01:33:06.698771 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4802 01:33:06.701790
4803 01:33:06.702395
4804 01:33:06.702774 ==
4805 01:33:06.704952 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 01:33:06.708252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 01:33:06.708728 ==
4808 01:33:06.709096
4809 01:33:06.709436
4810 01:33:06.711625 TX Vref Scan disable
4811 01:33:06.712089 == TX Byte 0 ==
4812 01:33:06.718475 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4813 01:33:06.721572 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4814 01:33:06.722129 == TX Byte 1 ==
4815 01:33:06.728064 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4816 01:33:06.731377 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4817 01:33:06.731937 ==
4818 01:33:06.734979 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 01:33:06.738068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 01:33:06.738587 ==
4821 01:33:06.738957
4822 01:33:06.741265
4823 01:33:06.741726 TX Vref Scan disable
4824 01:33:06.744903 == TX Byte 0 ==
4825 01:33:06.747898 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4826 01:33:06.754403 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4827 01:33:06.754948 == TX Byte 1 ==
4828 01:33:06.758066 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4829 01:33:06.764494 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4830 01:33:06.765094
4831 01:33:06.765473 [DATLAT]
4832 01:33:06.765819 Freq=600, CH1 RK1
4833 01:33:06.766155
4834 01:33:06.768194 DATLAT Default: 0x9
4835 01:33:06.768761 0, 0xFFFF, sum = 0
4836 01:33:06.771050 1, 0xFFFF, sum = 0
4837 01:33:06.774597 2, 0xFFFF, sum = 0
4838 01:33:06.775175 3, 0xFFFF, sum = 0
4839 01:33:06.777861 4, 0xFFFF, sum = 0
4840 01:33:06.778496 5, 0xFFFF, sum = 0
4841 01:33:06.780991 6, 0xFFFF, sum = 0
4842 01:33:06.781588 7, 0xFFFF, sum = 0
4843 01:33:06.784484 8, 0x0, sum = 1
4844 01:33:06.785077 9, 0x0, sum = 2
4845 01:33:06.787850 10, 0x0, sum = 3
4846 01:33:06.788325 11, 0x0, sum = 4
4847 01:33:06.788699 best_step = 9
4848 01:33:06.789042
4849 01:33:06.791188 ==
4850 01:33:06.791650 Dram Type= 6, Freq= 0, CH_1, rank 1
4851 01:33:06.797253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4852 01:33:06.797722 ==
4853 01:33:06.798103 RX Vref Scan: 0
4854 01:33:06.798484
4855 01:33:06.800494 RX Vref 0 -> 0, step: 1
4856 01:33:06.800958
4857 01:33:06.804269 RX Delay -195 -> 252, step: 8
4858 01:33:06.810638 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4859 01:33:06.813878 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4860 01:33:06.817406 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4861 01:33:06.820649 iDelay=213, Bit 3, Center 36 (-115 ~ 188) 304
4862 01:33:06.826864 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4863 01:33:06.830558 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4864 01:33:06.833939 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4865 01:33:06.837344 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4866 01:33:06.840277 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4867 01:33:06.846828 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4868 01:33:06.849863 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4869 01:33:06.853330 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4870 01:33:06.856662 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4871 01:33:06.863993 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4872 01:33:06.866732 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4873 01:33:06.869923 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4874 01:33:06.870538 ==
4875 01:33:06.873154 Dram Type= 6, Freq= 0, CH_1, rank 1
4876 01:33:06.876363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4877 01:33:06.879782 ==
4878 01:33:06.880250 DQS Delay:
4879 01:33:06.880627 DQS0 = 0, DQS1 = 0
4880 01:33:06.882961 DQM Delay:
4881 01:33:06.883420 DQM0 = 41, DQM1 = 33
4882 01:33:06.886769 DQ Delay:
4883 01:33:06.890341 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4884 01:33:06.890899 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4885 01:33:06.893229 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4886 01:33:06.896267 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4887 01:33:06.899846
4888 01:33:06.900312
4889 01:33:06.906029 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4890 01:33:06.909958 CH1 RK1: MR19=808, MR18=2C21
4891 01:33:06.916177 CH1_RK1: MR19=0x808, MR18=0x2C21, DQSOSC=401, MR23=63, INC=163, DEC=108
4892 01:33:06.919568 [RxdqsGatingPostProcess] freq 600
4893 01:33:06.922748 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4894 01:33:06.925827 Pre-setting of DQS Precalculation
4895 01:33:06.932900 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4896 01:33:06.939228 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4897 01:33:06.945916 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4898 01:33:06.946441
4899 01:33:06.947015
4900 01:33:06.949054 [Calibration Summary] 1200 Mbps
4901 01:33:06.949515 CH 0, Rank 0
4902 01:33:06.952228 SW Impedance : PASS
4903 01:33:06.955778 DUTY Scan : NO K
4904 01:33:06.956199 ZQ Calibration : PASS
4905 01:33:06.958855 Jitter Meter : NO K
4906 01:33:06.962517 CBT Training : PASS
4907 01:33:06.963043 Write leveling : PASS
4908 01:33:06.965248 RX DQS gating : PASS
4909 01:33:06.968618 RX DQ/DQS(RDDQC) : PASS
4910 01:33:06.969043 TX DQ/DQS : PASS
4911 01:33:06.972402 RX DATLAT : PASS
4912 01:33:06.975692 RX DQ/DQS(Engine): PASS
4913 01:33:06.976131 TX OE : NO K
4914 01:33:06.978328 All Pass.
4915 01:33:06.978747
4916 01:33:06.979092 CH 0, Rank 1
4917 01:33:06.981956 SW Impedance : PASS
4918 01:33:06.982410 DUTY Scan : NO K
4919 01:33:06.985435 ZQ Calibration : PASS
4920 01:33:06.988320 Jitter Meter : NO K
4921 01:33:06.988964 CBT Training : PASS
4922 01:33:06.992490 Write leveling : PASS
4923 01:33:06.994824 RX DQS gating : PASS
4924 01:33:06.995247 RX DQ/DQS(RDDQC) : PASS
4925 01:33:06.998033 TX DQ/DQS : PASS
4926 01:33:06.998505 RX DATLAT : PASS
4927 01:33:07.001952 RX DQ/DQS(Engine): PASS
4928 01:33:07.005242 TX OE : NO K
4929 01:33:07.005760 All Pass.
4930 01:33:07.006100
4931 01:33:07.006452 CH 1, Rank 0
4932 01:33:07.008356 SW Impedance : PASS
4933 01:33:07.011443 DUTY Scan : NO K
4934 01:33:07.011866 ZQ Calibration : PASS
4935 01:33:07.014802 Jitter Meter : NO K
4936 01:33:07.018336 CBT Training : PASS
4937 01:33:07.018859 Write leveling : PASS
4938 01:33:07.021274 RX DQS gating : PASS
4939 01:33:07.024838 RX DQ/DQS(RDDQC) : PASS
4940 01:33:07.025257 TX DQ/DQS : PASS
4941 01:33:07.028063 RX DATLAT : PASS
4942 01:33:07.031220 RX DQ/DQS(Engine): PASS
4943 01:33:07.031638 TX OE : NO K
4944 01:33:07.034574 All Pass.
4945 01:33:07.034995
4946 01:33:07.035326 CH 1, Rank 1
4947 01:33:07.038129 SW Impedance : PASS
4948 01:33:07.038633 DUTY Scan : NO K
4949 01:33:07.041069 ZQ Calibration : PASS
4950 01:33:07.044561 Jitter Meter : NO K
4951 01:33:07.045090 CBT Training : PASS
4952 01:33:07.048083 Write leveling : PASS
4953 01:33:07.051495 RX DQS gating : PASS
4954 01:33:07.052060 RX DQ/DQS(RDDQC) : PASS
4955 01:33:07.054629 TX DQ/DQS : PASS
4956 01:33:07.057639 RX DATLAT : PASS
4957 01:33:07.058333 RX DQ/DQS(Engine): PASS
4958 01:33:07.061237 TX OE : NO K
4959 01:33:07.061932 All Pass.
4960 01:33:07.062380
4961 01:33:07.064173 DramC Write-DBI off
4962 01:33:07.067530 PER_BANK_REFRESH: Hybrid Mode
4963 01:33:07.067963 TX_TRACKING: ON
4964 01:33:07.077567 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4965 01:33:07.080809 [FAST_K] Save calibration result to emmc
4966 01:33:07.083942 dramc_set_vcore_voltage set vcore to 662500
4967 01:33:07.087613 Read voltage for 933, 3
4968 01:33:07.088031 Vio18 = 0
4969 01:33:07.088362 Vcore = 662500
4970 01:33:07.091227 Vdram = 0
4971 01:33:07.091763 Vddq = 0
4972 01:33:07.092126 Vmddr = 0
4973 01:33:07.097105 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4974 01:33:07.101085 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4975 01:33:07.104341 MEM_TYPE=3, freq_sel=17
4976 01:33:07.107001 sv_algorithm_assistance_LP4_1600
4977 01:33:07.110084 ============ PULL DRAM RESETB DOWN ============
4978 01:33:07.113613 ========== PULL DRAM RESETB DOWN end =========
4979 01:33:07.120032 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 01:33:07.123577 ===================================
4981 01:33:07.126676 LPDDR4 DRAM CONFIGURATION
4982 01:33:07.129993 ===================================
4983 01:33:07.130444 EX_ROW_EN[0] = 0x0
4984 01:33:07.133468 EX_ROW_EN[1] = 0x0
4985 01:33:07.134061 LP4Y_EN = 0x0
4986 01:33:07.136683 WORK_FSP = 0x0
4987 01:33:07.137101 WL = 0x3
4988 01:33:07.139933 RL = 0x3
4989 01:33:07.140481 BL = 0x2
4990 01:33:07.143040 RPST = 0x0
4991 01:33:07.143583 RD_PRE = 0x0
4992 01:33:07.146621 WR_PRE = 0x1
4993 01:33:07.147038 WR_PST = 0x0
4994 01:33:07.149878 DBI_WR = 0x0
4995 01:33:07.153007 DBI_RD = 0x0
4996 01:33:07.153511 OTF = 0x1
4997 01:33:07.156353 ===================================
4998 01:33:07.159543 ===================================
4999 01:33:07.159963 ANA top config
5000 01:33:07.162965 ===================================
5001 01:33:07.166076 DLL_ASYNC_EN = 0
5002 01:33:07.170109 ALL_SLAVE_EN = 1
5003 01:33:07.173238 NEW_RANK_MODE = 1
5004 01:33:07.176273 DLL_IDLE_MODE = 1
5005 01:33:07.176696 LP45_APHY_COMB_EN = 1
5006 01:33:07.179436 TX_ODT_DIS = 1
5007 01:33:07.182757 NEW_8X_MODE = 1
5008 01:33:07.185946 ===================================
5009 01:33:07.189386 ===================================
5010 01:33:07.192670 data_rate = 1866
5011 01:33:07.195911 CKR = 1
5012 01:33:07.199082 DQ_P2S_RATIO = 8
5013 01:33:07.202357 ===================================
5014 01:33:07.202781 CA_P2S_RATIO = 8
5015 01:33:07.205834 DQ_CA_OPEN = 0
5016 01:33:07.209031 DQ_SEMI_OPEN = 0
5017 01:33:07.212113 CA_SEMI_OPEN = 0
5018 01:33:07.215558 CA_FULL_RATE = 0
5019 01:33:07.218651 DQ_CKDIV4_EN = 1
5020 01:33:07.219067 CA_CKDIV4_EN = 1
5021 01:33:07.222255 CA_PREDIV_EN = 0
5022 01:33:07.225447 PH8_DLY = 0
5023 01:33:07.228783 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5024 01:33:07.232139 DQ_AAMCK_DIV = 4
5025 01:33:07.235017 CA_AAMCK_DIV = 4
5026 01:33:07.235455 CA_ADMCK_DIV = 4
5027 01:33:07.238611 DQ_TRACK_CA_EN = 0
5028 01:33:07.241770 CA_PICK = 933
5029 01:33:07.244940 CA_MCKIO = 933
5030 01:33:07.248213 MCKIO_SEMI = 0
5031 01:33:07.251712 PLL_FREQ = 3732
5032 01:33:07.254919 DQ_UI_PI_RATIO = 32
5033 01:33:07.258313 CA_UI_PI_RATIO = 0
5034 01:33:07.261642 ===================================
5035 01:33:07.265176 ===================================
5036 01:33:07.265596 memory_type:LPDDR4
5037 01:33:07.268229 GP_NUM : 10
5038 01:33:07.271371 SRAM_EN : 1
5039 01:33:07.271793 MD32_EN : 0
5040 01:33:07.275118 ===================================
5041 01:33:07.278419 [ANA_INIT] >>>>>>>>>>>>>>
5042 01:33:07.281117 <<<<<< [CONFIGURE PHASE]: ANA_TX
5043 01:33:07.284569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5044 01:33:07.287918 ===================================
5045 01:33:07.291557 data_rate = 1866,PCW = 0X8f00
5046 01:33:07.294571 ===================================
5047 01:33:07.297802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5048 01:33:07.301341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5049 01:33:07.308261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5050 01:33:07.311188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5051 01:33:07.314495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5052 01:33:07.317987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5053 01:33:07.320856 [ANA_INIT] flow start
5054 01:33:07.325497 [ANA_INIT] PLL >>>>>>>>
5055 01:33:07.326017 [ANA_INIT] PLL <<<<<<<<
5056 01:33:07.327528 [ANA_INIT] MIDPI >>>>>>>>
5057 01:33:07.331154 [ANA_INIT] MIDPI <<<<<<<<
5058 01:33:07.333892 [ANA_INIT] DLL >>>>>>>>
5059 01:33:07.334362 [ANA_INIT] flow end
5060 01:33:07.337059 ============ LP4 DIFF to SE enter ============
5061 01:33:07.343900 ============ LP4 DIFF to SE exit ============
5062 01:33:07.344327 [ANA_INIT] <<<<<<<<<<<<<
5063 01:33:07.347056 [Flow] Enable top DCM control >>>>>
5064 01:33:07.350633 [Flow] Enable top DCM control <<<<<
5065 01:33:07.354041 Enable DLL master slave shuffle
5066 01:33:07.360300 ==============================================================
5067 01:33:07.360724 Gating Mode config
5068 01:33:07.366781 ==============================================================
5069 01:33:07.370246 Config description:
5070 01:33:07.380481 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5071 01:33:07.387009 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5072 01:33:07.390055 SELPH_MODE 0: By rank 1: By Phase
5073 01:33:07.397233 ==============================================================
5074 01:33:07.399702 GAT_TRACK_EN = 1
5075 01:33:07.403501 RX_GATING_MODE = 2
5076 01:33:07.406582 RX_GATING_TRACK_MODE = 2
5077 01:33:07.407175 SELPH_MODE = 1
5078 01:33:07.409965 PICG_EARLY_EN = 1
5079 01:33:07.412953 VALID_LAT_VALUE = 1
5080 01:33:07.419679 ==============================================================
5081 01:33:07.422997 Enter into Gating configuration >>>>
5082 01:33:07.426074 Exit from Gating configuration <<<<
5083 01:33:07.429791 Enter into DVFS_PRE_config >>>>>
5084 01:33:07.439534 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5085 01:33:07.443407 Exit from DVFS_PRE_config <<<<<
5086 01:33:07.446364 Enter into PICG configuration >>>>
5087 01:33:07.449243 Exit from PICG configuration <<<<
5088 01:33:07.452725 [RX_INPUT] configuration >>>>>
5089 01:33:07.455894 [RX_INPUT] configuration <<<<<
5090 01:33:07.458989 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5091 01:33:07.465894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5092 01:33:07.472587 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5093 01:33:07.479255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5094 01:33:07.485413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5095 01:33:07.492597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5096 01:33:07.495683 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5097 01:33:07.498861 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5098 01:33:07.502318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5099 01:33:07.508648 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5100 01:33:07.511918 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5101 01:33:07.515534 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 01:33:07.518584 ===================================
5103 01:33:07.522257 LPDDR4 DRAM CONFIGURATION
5104 01:33:07.525429 ===================================
5105 01:33:07.526025 EX_ROW_EN[0] = 0x0
5106 01:33:07.528505 EX_ROW_EN[1] = 0x0
5107 01:33:07.531986 LP4Y_EN = 0x0
5108 01:33:07.532444 WORK_FSP = 0x0
5109 01:33:07.535325 WL = 0x3
5110 01:33:07.535907 RL = 0x3
5111 01:33:07.538127 BL = 0x2
5112 01:33:07.538612 RPST = 0x0
5113 01:33:07.541727 RD_PRE = 0x0
5114 01:33:07.542224 WR_PRE = 0x1
5115 01:33:07.545426 WR_PST = 0x0
5116 01:33:07.546021 DBI_WR = 0x0
5117 01:33:07.548427 DBI_RD = 0x0
5118 01:33:07.548987 OTF = 0x1
5119 01:33:07.551571 ===================================
5120 01:33:07.555457 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5121 01:33:07.561397 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5122 01:33:07.564953 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5123 01:33:07.568378 ===================================
5124 01:33:07.571179 LPDDR4 DRAM CONFIGURATION
5125 01:33:07.574492 ===================================
5126 01:33:07.574967 EX_ROW_EN[0] = 0x10
5127 01:33:07.577789 EX_ROW_EN[1] = 0x0
5128 01:33:07.581180 LP4Y_EN = 0x0
5129 01:33:07.581732 WORK_FSP = 0x0
5130 01:33:07.584415 WL = 0x3
5131 01:33:07.584978 RL = 0x3
5132 01:33:07.587874 BL = 0x2
5133 01:33:07.588333 RPST = 0x0
5134 01:33:07.590808 RD_PRE = 0x0
5135 01:33:07.591269 WR_PRE = 0x1
5136 01:33:07.594623 WR_PST = 0x0
5137 01:33:07.595083 DBI_WR = 0x0
5138 01:33:07.598275 DBI_RD = 0x0
5139 01:33:07.598904 OTF = 0x1
5140 01:33:07.600948 ===================================
5141 01:33:07.607589 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5142 01:33:07.612008 nWR fixed to 30
5143 01:33:07.615284 [ModeRegInit_LP4] CH0 RK0
5144 01:33:07.615748 [ModeRegInit_LP4] CH0 RK1
5145 01:33:07.618448 [ModeRegInit_LP4] CH1 RK0
5146 01:33:07.621877 [ModeRegInit_LP4] CH1 RK1
5147 01:33:07.622475 match AC timing 9
5148 01:33:07.628228 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5149 01:33:07.631643 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5150 01:33:07.635089 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5151 01:33:07.641653 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5152 01:33:07.645411 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5153 01:33:07.645964 ==
5154 01:33:07.648166 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 01:33:07.651670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 01:33:07.652235 ==
5157 01:33:07.657969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5158 01:33:07.664660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5159 01:33:07.667992 [CA 0] Center 37 (7~68) winsize 62
5160 01:33:07.670882 [CA 1] Center 37 (7~68) winsize 62
5161 01:33:07.674523 [CA 2] Center 34 (4~65) winsize 62
5162 01:33:07.677649 [CA 3] Center 34 (4~65) winsize 62
5163 01:33:07.681736 [CA 4] Center 33 (3~64) winsize 62
5164 01:33:07.684439 [CA 5] Center 33 (3~63) winsize 61
5165 01:33:07.685007
5166 01:33:07.687420 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5167 01:33:07.687883
5168 01:33:07.691124 [CATrainingPosCal] consider 1 rank data
5169 01:33:07.694117 u2DelayCellTimex100 = 270/100 ps
5170 01:33:07.697348 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5171 01:33:07.700678 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5172 01:33:07.707335 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5173 01:33:07.710637 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5174 01:33:07.713541 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5175 01:33:07.717388 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5176 01:33:07.717955
5177 01:33:07.720328 CA PerBit enable=1, Macro0, CA PI delay=33
5178 01:33:07.720790
5179 01:33:07.723604 [CBTSetCACLKResult] CA Dly = 33
5180 01:33:07.724064 CS Dly: 7 (0~38)
5181 01:33:07.726802 ==
5182 01:33:07.727262 Dram Type= 6, Freq= 0, CH_0, rank 1
5183 01:33:07.733517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 01:33:07.734067 ==
5185 01:33:07.736687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5186 01:33:07.743308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5187 01:33:07.747351 [CA 0] Center 37 (7~68) winsize 62
5188 01:33:07.750247 [CA 1] Center 37 (7~68) winsize 62
5189 01:33:07.753565 [CA 2] Center 34 (4~65) winsize 62
5190 01:33:07.756978 [CA 3] Center 34 (4~65) winsize 62
5191 01:33:07.760200 [CA 4] Center 33 (3~64) winsize 62
5192 01:33:07.763755 [CA 5] Center 33 (3~63) winsize 61
5193 01:33:07.764318
5194 01:33:07.766803 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5195 01:33:07.767269
5196 01:33:07.770426 [CATrainingPosCal] consider 2 rank data
5197 01:33:07.773686 u2DelayCellTimex100 = 270/100 ps
5198 01:33:07.776856 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5199 01:33:07.783376 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5200 01:33:07.786665 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5201 01:33:07.790109 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5202 01:33:07.793656 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5203 01:33:07.796962 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5204 01:33:07.797518
5205 01:33:07.800042 CA PerBit enable=1, Macro0, CA PI delay=33
5206 01:33:07.800523
5207 01:33:07.803177 [CBTSetCACLKResult] CA Dly = 33
5208 01:33:07.807091 CS Dly: 7 (0~39)
5209 01:33:07.807637
5210 01:33:07.810414 ----->DramcWriteLeveling(PI) begin...
5211 01:33:07.810968 ==
5212 01:33:07.813077 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 01:33:07.816540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 01:33:07.817107 ==
5215 01:33:07.819538 Write leveling (Byte 0): 31 => 31
5216 01:33:07.822877 Write leveling (Byte 1): 30 => 30
5217 01:33:07.826144 DramcWriteLeveling(PI) end<-----
5218 01:33:07.826637
5219 01:33:07.827032 ==
5220 01:33:07.829673 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 01:33:07.832839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 01:33:07.833379 ==
5223 01:33:07.835998 [Gating] SW mode calibration
5224 01:33:07.842429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5225 01:33:07.849453 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5226 01:33:07.852728 0 14 0 | B1->B0 | 2322 3232 | 1 0 | (0 0) (0 0)
5227 01:33:07.856039 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5228 01:33:07.862275 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5229 01:33:07.866007 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5230 01:33:07.869198 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5231 01:33:07.875792 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5232 01:33:07.878887 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5233 01:33:07.882381 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5234 01:33:07.889304 0 15 0 | B1->B0 | 3030 2424 | 0 0 | (1 0) (0 0)
5235 01:33:07.892131 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5236 01:33:07.896372 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5237 01:33:07.902056 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5238 01:33:07.905522 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5239 01:33:07.908685 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5240 01:33:07.915354 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5241 01:33:07.918619 0 15 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5242 01:33:07.922137 1 0 0 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
5243 01:33:07.928746 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 01:33:07.932577 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5245 01:33:07.935539 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5246 01:33:07.941898 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5247 01:33:07.944952 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5248 01:33:07.948529 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 01:33:07.954757 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5250 01:33:07.958278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5251 01:33:07.961136 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 01:33:07.967965 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 01:33:07.971197 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 01:33:07.974383 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 01:33:07.981241 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 01:33:07.984902 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 01:33:07.987686 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 01:33:07.994468 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 01:33:07.997620 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 01:33:08.001349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 01:33:08.007656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 01:33:08.011143 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 01:33:08.013971 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 01:33:08.021147 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 01:33:08.024194 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5266 01:33:08.027826 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5267 01:33:08.033986 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5268 01:33:08.037630 Total UI for P1: 0, mck2ui 16
5269 01:33:08.040277 best dqsien dly found for B0: ( 1, 2, 30)
5270 01:33:08.040739 Total UI for P1: 0, mck2ui 16
5271 01:33:08.047547 best dqsien dly found for B1: ( 1, 3, 2)
5272 01:33:08.050811 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5273 01:33:08.054024 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5274 01:33:08.054638
5275 01:33:08.057898 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5276 01:33:08.060165 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5277 01:33:08.063739 [Gating] SW calibration Done
5278 01:33:08.064304 ==
5279 01:33:08.067063 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 01:33:08.070372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 01:33:08.070843 ==
5282 01:33:08.073640 RX Vref Scan: 0
5283 01:33:08.074265
5284 01:33:08.074651 RX Vref 0 -> 0, step: 1
5285 01:33:08.074996
5286 01:33:08.076755 RX Delay -80 -> 252, step: 8
5287 01:33:08.083544 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5288 01:33:08.086711 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5289 01:33:08.089756 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5290 01:33:08.093140 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5291 01:33:08.096846 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5292 01:33:08.099573 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5293 01:33:08.106507 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5294 01:33:08.109878 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5295 01:33:08.113180 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5296 01:33:08.116083 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5297 01:33:08.119696 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5298 01:33:08.126449 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5299 01:33:08.130029 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5300 01:33:08.133095 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5301 01:33:08.136826 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5302 01:33:08.139563 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5303 01:33:08.140028 ==
5304 01:33:08.142689 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 01:33:08.149354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 01:33:08.149915 ==
5307 01:33:08.150341 DQS Delay:
5308 01:33:08.152682 DQS0 = 0, DQS1 = 0
5309 01:33:08.153244 DQM Delay:
5310 01:33:08.153611 DQM0 = 96, DQM1 = 86
5311 01:33:08.156077 DQ Delay:
5312 01:33:08.159493 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5313 01:33:08.162506 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5314 01:33:08.166079 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5315 01:33:08.169083 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5316 01:33:08.169545
5317 01:33:08.169909
5318 01:33:08.170296 ==
5319 01:33:08.172169 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 01:33:08.175546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 01:33:08.176112 ==
5322 01:33:08.176485
5323 01:33:08.176824
5324 01:33:08.178816 TX Vref Scan disable
5325 01:33:08.181947 == TX Byte 0 ==
5326 01:33:08.185565 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5327 01:33:08.188390 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5328 01:33:08.192001 == TX Byte 1 ==
5329 01:33:08.195009 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5330 01:33:08.198491 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5331 01:33:08.198960 ==
5332 01:33:08.201737 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 01:33:08.208349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 01:33:08.208902 ==
5335 01:33:08.209276
5336 01:33:08.209613
5337 01:33:08.209935 TX Vref Scan disable
5338 01:33:08.212382 == TX Byte 0 ==
5339 01:33:08.215806 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5340 01:33:08.222565 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5341 01:33:08.223119 == TX Byte 1 ==
5342 01:33:08.225776 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5343 01:33:08.232401 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5344 01:33:08.232961
5345 01:33:08.233331 [DATLAT]
5346 01:33:08.233670 Freq=933, CH0 RK0
5347 01:33:08.234003
5348 01:33:08.235254 DATLAT Default: 0xd
5349 01:33:08.235713 0, 0xFFFF, sum = 0
5350 01:33:08.239286 1, 0xFFFF, sum = 0
5351 01:33:08.242094 2, 0xFFFF, sum = 0
5352 01:33:08.242622 3, 0xFFFF, sum = 0
5353 01:33:08.245233 4, 0xFFFF, sum = 0
5354 01:33:08.245698 5, 0xFFFF, sum = 0
5355 01:33:08.249269 6, 0xFFFF, sum = 0
5356 01:33:08.249824 7, 0xFFFF, sum = 0
5357 01:33:08.252032 8, 0xFFFF, sum = 0
5358 01:33:08.252587 9, 0xFFFF, sum = 0
5359 01:33:08.255753 10, 0x0, sum = 1
5360 01:33:08.256332 11, 0x0, sum = 2
5361 01:33:08.258918 12, 0x0, sum = 3
5362 01:33:08.259383 13, 0x0, sum = 4
5363 01:33:08.259751 best_step = 11
5364 01:33:08.260082
5365 01:33:08.262004 ==
5366 01:33:08.265271 Dram Type= 6, Freq= 0, CH_0, rank 0
5367 01:33:08.268511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 01:33:08.268966 ==
5369 01:33:08.269328 RX Vref Scan: 1
5370 01:33:08.269664
5371 01:33:08.271812 RX Vref 0 -> 0, step: 1
5372 01:33:08.272267
5373 01:33:08.275068 RX Delay -61 -> 252, step: 4
5374 01:33:08.275481
5375 01:33:08.278139 Set Vref, RX VrefLevel [Byte0]: 60
5376 01:33:08.281694 [Byte1]: 52
5377 01:33:08.285108
5378 01:33:08.285534 Final RX Vref Byte 0 = 60 to rank0
5379 01:33:08.287904 Final RX Vref Byte 1 = 52 to rank0
5380 01:33:08.291426 Final RX Vref Byte 0 = 60 to rank1
5381 01:33:08.294701 Final RX Vref Byte 1 = 52 to rank1==
5382 01:33:08.297846 Dram Type= 6, Freq= 0, CH_0, rank 0
5383 01:33:08.304472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 01:33:08.304887 ==
5385 01:33:08.305148 DQS Delay:
5386 01:33:08.308022 DQS0 = 0, DQS1 = 0
5387 01:33:08.308435 DQM Delay:
5388 01:33:08.308691 DQM0 = 96, DQM1 = 85
5389 01:33:08.311009 DQ Delay:
5390 01:33:08.314480 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5391 01:33:08.317564 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5392 01:33:08.321137 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5393 01:33:08.324223 DQ12 =90, DQ13 =86, DQ14 =94, DQ15 =92
5394 01:33:08.324545
5395 01:33:08.324798
5396 01:33:08.330761 [DQSOSCAuto] RK0, (LSB)MR18= 0x260c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 409 ps
5397 01:33:08.334140 CH0 RK0: MR19=505, MR18=260C
5398 01:33:08.341036 CH0_RK0: MR19=0x505, MR18=0x260C, DQSOSC=409, MR23=63, INC=64, DEC=43
5399 01:33:08.341623
5400 01:33:08.344257 ----->DramcWriteLeveling(PI) begin...
5401 01:33:08.344957 ==
5402 01:33:08.347369 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 01:33:08.350755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 01:33:08.351220 ==
5405 01:33:08.354266 Write leveling (Byte 0): 33 => 33
5406 01:33:08.357229 Write leveling (Byte 1): 31 => 31
5407 01:33:08.360346 DramcWriteLeveling(PI) end<-----
5408 01:33:08.360821
5409 01:33:08.361524 ==
5410 01:33:08.363865 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 01:33:08.370241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 01:33:08.370710 ==
5413 01:33:08.371073 [Gating] SW mode calibration
5414 01:33:08.380339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5415 01:33:08.383974 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5416 01:33:08.386755 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5417 01:33:08.393435 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 01:33:08.397367 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 01:33:08.403246 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 01:33:08.406546 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5421 01:33:08.410077 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5422 01:33:08.416400 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 01:33:08.420274 0 14 28 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5424 01:33:08.423103 0 15 0 | B1->B0 | 2c2c 2828 | 1 1 | (1 0) (1 0)
5425 01:33:08.429748 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 01:33:08.432816 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 01:33:08.436112 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 01:33:08.442820 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5429 01:33:08.446352 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 01:33:08.450251 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 01:33:08.456073 0 15 28 | B1->B0 | 2525 3333 | 1 1 | (1 1) (0 0)
5432 01:33:08.459038 1 0 0 | B1->B0 | 3c3c 3f3f | 0 0 | (0 0) (0 0)
5433 01:33:08.462472 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 01:33:08.469019 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 01:33:08.472331 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 01:33:08.475626 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 01:33:08.482010 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 01:33:08.485599 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 01:33:08.488899 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 01:33:08.495353 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5441 01:33:08.498698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 01:33:08.502540 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 01:33:08.508611 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 01:33:08.512633 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 01:33:08.515618 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 01:33:08.521780 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 01:33:08.524887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 01:33:08.528405 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 01:33:08.534762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 01:33:08.538132 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 01:33:08.541435 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 01:33:08.547851 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 01:33:08.551497 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 01:33:08.554289 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 01:33:08.561736 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5456 01:33:08.564820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5457 01:33:08.567834 Total UI for P1: 0, mck2ui 16
5458 01:33:08.570960 best dqsien dly found for B0: ( 1, 2, 28)
5459 01:33:08.574385 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5460 01:33:08.577958 Total UI for P1: 0, mck2ui 16
5461 01:33:08.580533 best dqsien dly found for B1: ( 1, 3, 0)
5462 01:33:08.584053 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5463 01:33:08.587215 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5464 01:33:08.587636
5465 01:33:08.593939 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5466 01:33:08.596988 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5467 01:33:08.600525 [Gating] SW calibration Done
5468 01:33:08.600990 ==
5469 01:33:08.603759 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 01:33:08.607067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 01:33:08.607630 ==
5472 01:33:08.608001 RX Vref Scan: 0
5473 01:33:08.608345
5474 01:33:08.610242 RX Vref 0 -> 0, step: 1
5475 01:33:08.610760
5476 01:33:08.613390 RX Delay -80 -> 252, step: 8
5477 01:33:08.616528 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5478 01:33:08.619931 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5479 01:33:08.626393 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5480 01:33:08.629771 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5481 01:33:08.633057 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5482 01:33:08.636955 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5483 01:33:08.639653 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5484 01:33:08.643246 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5485 01:33:08.649343 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5486 01:33:08.652833 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5487 01:33:08.655829 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5488 01:33:08.659063 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5489 01:33:08.662499 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5490 01:33:08.669041 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5491 01:33:08.672624 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5492 01:33:08.675891 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5493 01:33:08.676105 ==
5494 01:33:08.679050 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 01:33:08.682124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 01:33:08.682318 ==
5497 01:33:08.685863 DQS Delay:
5498 01:33:08.686076 DQS0 = 0, DQS1 = 0
5499 01:33:08.688988 DQM Delay:
5500 01:33:08.689202 DQM0 = 96, DQM1 = 88
5501 01:33:08.692123 DQ Delay:
5502 01:33:08.692339 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5503 01:33:08.695285 DQ4 =95, DQ5 =91, DQ6 =107, DQ7 =107
5504 01:33:08.698523 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5505 01:33:08.701954 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5506 01:33:08.705619
5507 01:33:08.705850
5508 01:33:08.705980 ==
5509 01:33:08.708686 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 01:33:08.711862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 01:33:08.712116 ==
5512 01:33:08.712270
5513 01:33:08.712416
5514 01:33:08.715530 TX Vref Scan disable
5515 01:33:08.715736 == TX Byte 0 ==
5516 01:33:08.721586 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5517 01:33:08.725343 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5518 01:33:08.725743 == TX Byte 1 ==
5519 01:33:08.731930 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5520 01:33:08.734816 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5521 01:33:08.735272 ==
5522 01:33:08.738331 Dram Type= 6, Freq= 0, CH_0, rank 1
5523 01:33:08.741911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 01:33:08.742524 ==
5525 01:33:08.742899
5526 01:33:08.745071
5527 01:33:08.745571 TX Vref Scan disable
5528 01:33:08.748041 == TX Byte 0 ==
5529 01:33:08.751468 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5530 01:33:08.754717 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5531 01:33:08.758136 == TX Byte 1 ==
5532 01:33:08.761386 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5533 01:33:08.764868 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5534 01:33:08.768501
5535 01:33:08.769050 [DATLAT]
5536 01:33:08.769422 Freq=933, CH0 RK1
5537 01:33:08.769768
5538 01:33:08.771098 DATLAT Default: 0xb
5539 01:33:08.771560 0, 0xFFFF, sum = 0
5540 01:33:08.774842 1, 0xFFFF, sum = 0
5541 01:33:08.775310 2, 0xFFFF, sum = 0
5542 01:33:08.778098 3, 0xFFFF, sum = 0
5543 01:33:08.781903 4, 0xFFFF, sum = 0
5544 01:33:08.782521 5, 0xFFFF, sum = 0
5545 01:33:08.784852 6, 0xFFFF, sum = 0
5546 01:33:08.785411 7, 0xFFFF, sum = 0
5547 01:33:08.787579 8, 0xFFFF, sum = 0
5548 01:33:08.788045 9, 0xFFFF, sum = 0
5549 01:33:08.792097 10, 0x0, sum = 1
5550 01:33:08.792659 11, 0x0, sum = 2
5551 01:33:08.794529 12, 0x0, sum = 3
5552 01:33:08.795000 13, 0x0, sum = 4
5553 01:33:08.795374 best_step = 11
5554 01:33:08.795713
5555 01:33:08.797821 ==
5556 01:33:08.800984 Dram Type= 6, Freq= 0, CH_0, rank 1
5557 01:33:08.804397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 01:33:08.804963 ==
5559 01:33:08.805332 RX Vref Scan: 0
5560 01:33:08.805676
5561 01:33:08.807649 RX Vref 0 -> 0, step: 1
5562 01:33:08.808208
5563 01:33:08.811030 RX Delay -61 -> 252, step: 4
5564 01:33:08.817821 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5565 01:33:08.820921 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5566 01:33:08.824044 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5567 01:33:08.827202 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5568 01:33:08.831128 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5569 01:33:08.834204 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5570 01:33:08.840959 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5571 01:33:08.844324 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5572 01:33:08.847047 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5573 01:33:08.850460 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5574 01:33:08.854064 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5575 01:33:08.860487 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5576 01:33:08.863848 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5577 01:33:08.867038 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5578 01:33:08.870100 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5579 01:33:08.873442 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5580 01:33:08.873982 ==
5581 01:33:08.877227 Dram Type= 6, Freq= 0, CH_0, rank 1
5582 01:33:08.883476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 01:33:08.883952 ==
5584 01:33:08.884487 DQS Delay:
5585 01:33:08.886914 DQS0 = 0, DQS1 = 0
5586 01:33:08.887376 DQM Delay:
5587 01:33:08.890197 DQM0 = 95, DQM1 = 87
5588 01:33:08.890763 DQ Delay:
5589 01:33:08.893684 DQ0 =92, DQ1 =98, DQ2 =88, DQ3 =92
5590 01:33:08.896724 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5591 01:33:08.900226 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5592 01:33:08.903201 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5593 01:33:08.903664
5594 01:33:08.904029
5595 01:33:08.909995 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5596 01:33:08.913216 CH0 RK1: MR19=504, MR18=26F7
5597 01:33:08.920100 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5598 01:33:08.923159 [RxdqsGatingPostProcess] freq 933
5599 01:33:08.929816 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5600 01:33:08.933300 best DQS0 dly(2T, 0.5T) = (0, 10)
5601 01:33:08.933859 best DQS1 dly(2T, 0.5T) = (0, 11)
5602 01:33:08.936912 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5603 01:33:08.940294 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5604 01:33:08.942945 best DQS0 dly(2T, 0.5T) = (0, 10)
5605 01:33:08.946300 best DQS1 dly(2T, 0.5T) = (0, 11)
5606 01:33:08.949712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5607 01:33:08.952660 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5608 01:33:08.956329 Pre-setting of DQS Precalculation
5609 01:33:08.962793 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5610 01:33:08.963369 ==
5611 01:33:08.965994 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 01:33:08.969125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 01:33:08.969664 ==
5614 01:33:08.976199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5615 01:33:08.979633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5616 01:33:08.983651 [CA 0] Center 36 (6~67) winsize 62
5617 01:33:08.986766 [CA 1] Center 37 (6~68) winsize 63
5618 01:33:08.990418 [CA 2] Center 34 (4~65) winsize 62
5619 01:33:08.993454 [CA 3] Center 33 (3~64) winsize 62
5620 01:33:08.996776 [CA 4] Center 34 (4~64) winsize 61
5621 01:33:08.999887 [CA 5] Center 33 (3~64) winsize 62
5622 01:33:09.000353
5623 01:33:09.003617 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5624 01:33:09.004083
5625 01:33:09.007159 [CATrainingPosCal] consider 1 rank data
5626 01:33:09.010144 u2DelayCellTimex100 = 270/100 ps
5627 01:33:09.013115 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5628 01:33:09.020071 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5629 01:33:09.023264 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5630 01:33:09.026352 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5631 01:33:09.030099 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5632 01:33:09.032754 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5633 01:33:09.033217
5634 01:33:09.036260 CA PerBit enable=1, Macro0, CA PI delay=33
5635 01:33:09.036772
5636 01:33:09.039743 [CBTSetCACLKResult] CA Dly = 33
5637 01:33:09.043107 CS Dly: 6 (0~37)
5638 01:33:09.043654 ==
5639 01:33:09.046535 Dram Type= 6, Freq= 0, CH_1, rank 1
5640 01:33:09.049484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 01:33:09.049946 ==
5642 01:33:09.056434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5643 01:33:09.059339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5644 01:33:09.063752 [CA 0] Center 36 (6~67) winsize 62
5645 01:33:09.066650 [CA 1] Center 36 (6~67) winsize 62
5646 01:33:09.070043 [CA 2] Center 34 (4~65) winsize 62
5647 01:33:09.073389 [CA 3] Center 34 (3~65) winsize 63
5648 01:33:09.076577 [CA 4] Center 34 (4~65) winsize 62
5649 01:33:09.080025 [CA 5] Center 33 (3~64) winsize 62
5650 01:33:09.080488
5651 01:33:09.082992 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5652 01:33:09.083515
5653 01:33:09.086264 [CATrainingPosCal] consider 2 rank data
5654 01:33:09.089574 u2DelayCellTimex100 = 270/100 ps
5655 01:33:09.093254 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5656 01:33:09.099338 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5657 01:33:09.102726 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5658 01:33:09.106341 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5659 01:33:09.109780 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5660 01:33:09.112893 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5661 01:33:09.113443
5662 01:33:09.116165 CA PerBit enable=1, Macro0, CA PI delay=33
5663 01:33:09.116710
5664 01:33:09.119323 [CBTSetCACLKResult] CA Dly = 33
5665 01:33:09.122735 CS Dly: 7 (0~39)
5666 01:33:09.123212
5667 01:33:09.125769 ----->DramcWriteLeveling(PI) begin...
5668 01:33:09.126416 ==
5669 01:33:09.129152 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 01:33:09.132759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 01:33:09.133319 ==
5672 01:33:09.135704 Write leveling (Byte 0): 27 => 27
5673 01:33:09.139334 Write leveling (Byte 1): 29 => 29
5674 01:33:09.142800 DramcWriteLeveling(PI) end<-----
5675 01:33:09.143359
5676 01:33:09.143731 ==
5677 01:33:09.145896 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 01:33:09.149240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 01:33:09.149970 ==
5680 01:33:09.152091 [Gating] SW mode calibration
5681 01:33:09.158830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5682 01:33:09.165772 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5683 01:33:09.169521 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5684 01:33:09.175133 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5685 01:33:09.178552 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5686 01:33:09.181851 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5687 01:33:09.185123 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5688 01:33:09.191991 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5689 01:33:09.195138 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5690 01:33:09.198544 0 14 28 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
5691 01:33:09.205734 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5692 01:33:09.208429 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5693 01:33:09.211614 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5694 01:33:09.218427 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5695 01:33:09.221499 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5696 01:33:09.224765 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5697 01:33:09.231276 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5698 01:33:09.235315 0 15 28 | B1->B0 | 3535 3838 | 0 0 | (0 0) (1 1)
5699 01:33:09.238275 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5700 01:33:09.244387 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5701 01:33:09.247909 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 01:33:09.251297 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5703 01:33:09.258258 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5704 01:33:09.261158 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5705 01:33:09.264388 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5706 01:33:09.270974 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5707 01:33:09.274380 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5708 01:33:09.278004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 01:33:09.284118 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 01:33:09.287527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 01:33:09.290560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 01:33:09.297292 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 01:33:09.300796 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 01:33:09.304110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 01:33:09.310823 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 01:33:09.314233 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 01:33:09.317609 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 01:33:09.324035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 01:33:09.327072 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 01:33:09.330391 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 01:33:09.337288 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5722 01:33:09.340372 Total UI for P1: 0, mck2ui 16
5723 01:33:09.343373 best dqsien dly found for B0: ( 1, 2, 22)
5724 01:33:09.346729 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5725 01:33:09.349907 Total UI for P1: 0, mck2ui 16
5726 01:33:09.353145 best dqsien dly found for B1: ( 1, 2, 24)
5727 01:33:09.356676 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5728 01:33:09.360452 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5729 01:33:09.360997
5730 01:33:09.363259 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5731 01:33:09.370368 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5732 01:33:09.371023 [Gating] SW calibration Done
5733 01:33:09.371395 ==
5734 01:33:09.373197 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 01:33:09.379830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 01:33:09.380290 ==
5737 01:33:09.380651 RX Vref Scan: 0
5738 01:33:09.380985
5739 01:33:09.383241 RX Vref 0 -> 0, step: 1
5740 01:33:09.383836
5741 01:33:09.386216 RX Delay -80 -> 252, step: 8
5742 01:33:09.389631 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5743 01:33:09.393456 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5744 01:33:09.396156 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5745 01:33:09.402575 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5746 01:33:09.406387 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5747 01:33:09.409654 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5748 01:33:09.412412 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5749 01:33:09.415994 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5750 01:33:09.419112 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5751 01:33:09.425849 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5752 01:33:09.429034 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5753 01:33:09.432400 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5754 01:33:09.436173 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5755 01:33:09.439109 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5756 01:33:09.445692 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5757 01:33:09.449045 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5758 01:33:09.449592 ==
5759 01:33:09.451796 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 01:33:09.455482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 01:33:09.455964 ==
5762 01:33:09.458743 DQS Delay:
5763 01:33:09.459205 DQS0 = 0, DQS1 = 0
5764 01:33:09.459573 DQM Delay:
5765 01:33:09.461803 DQM0 = 101, DQM1 = 91
5766 01:33:09.462309 DQ Delay:
5767 01:33:09.465339 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =103
5768 01:33:09.468469 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5769 01:33:09.471783 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5770 01:33:09.475139 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5771 01:33:09.475559
5772 01:33:09.475889
5773 01:33:09.478560 ==
5774 01:33:09.478979 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 01:33:09.485575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 01:33:09.486091 ==
5777 01:33:09.486484
5778 01:33:09.486797
5779 01:33:09.488385 TX Vref Scan disable
5780 01:33:09.488806 == TX Byte 0 ==
5781 01:33:09.491468 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5782 01:33:09.498832 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5783 01:33:09.499353 == TX Byte 1 ==
5784 01:33:09.501418 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5785 01:33:09.508109 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5786 01:33:09.508620 ==
5787 01:33:09.511263 Dram Type= 6, Freq= 0, CH_1, rank 0
5788 01:33:09.514886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 01:33:09.515309 ==
5790 01:33:09.515734
5791 01:33:09.516098
5792 01:33:09.518204 TX Vref Scan disable
5793 01:33:09.521244 == TX Byte 0 ==
5794 01:33:09.524275 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5795 01:33:09.528181 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5796 01:33:09.531344 == TX Byte 1 ==
5797 01:33:09.534588 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5798 01:33:09.537784 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5799 01:33:09.538355
5800 01:33:09.540876 [DATLAT]
5801 01:33:09.541286 Freq=933, CH1 RK0
5802 01:33:09.541617
5803 01:33:09.544290 DATLAT Default: 0xd
5804 01:33:09.544701 0, 0xFFFF, sum = 0
5805 01:33:09.547743 1, 0xFFFF, sum = 0
5806 01:33:09.548259 2, 0xFFFF, sum = 0
5807 01:33:09.550831 3, 0xFFFF, sum = 0
5808 01:33:09.551424 4, 0xFFFF, sum = 0
5809 01:33:09.554100 5, 0xFFFF, sum = 0
5810 01:33:09.554609 6, 0xFFFF, sum = 0
5811 01:33:09.557351 7, 0xFFFF, sum = 0
5812 01:33:09.557802 8, 0xFFFF, sum = 0
5813 01:33:09.560589 9, 0xFFFF, sum = 0
5814 01:33:09.561027 10, 0x0, sum = 1
5815 01:33:09.564172 11, 0x0, sum = 2
5816 01:33:09.564641 12, 0x0, sum = 3
5817 01:33:09.567251 13, 0x0, sum = 4
5818 01:33:09.567694 best_step = 11
5819 01:33:09.568026
5820 01:33:09.568336 ==
5821 01:33:09.570342 Dram Type= 6, Freq= 0, CH_1, rank 0
5822 01:33:09.577102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 01:33:09.577524 ==
5824 01:33:09.577860 RX Vref Scan: 1
5825 01:33:09.578211
5826 01:33:09.580950 RX Vref 0 -> 0, step: 1
5827 01:33:09.581465
5828 01:33:09.583521 RX Delay -61 -> 252, step: 4
5829 01:33:09.583938
5830 01:33:09.586957 Set Vref, RX VrefLevel [Byte0]: 52
5831 01:33:09.590591 [Byte1]: 54
5832 01:33:09.591135
5833 01:33:09.593641 Final RX Vref Byte 0 = 52 to rank0
5834 01:33:09.596900 Final RX Vref Byte 1 = 54 to rank0
5835 01:33:09.600218 Final RX Vref Byte 0 = 52 to rank1
5836 01:33:09.603561 Final RX Vref Byte 1 = 54 to rank1==
5837 01:33:09.606811 Dram Type= 6, Freq= 0, CH_1, rank 0
5838 01:33:09.610127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 01:33:09.610576 ==
5840 01:33:09.613184 DQS Delay:
5841 01:33:09.613745 DQS0 = 0, DQS1 = 0
5842 01:33:09.616869 DQM Delay:
5843 01:33:09.617302 DQM0 = 100, DQM1 = 93
5844 01:33:09.620186 DQ Delay:
5845 01:33:09.620605 DQ0 =106, DQ1 =94, DQ2 =92, DQ3 =96
5846 01:33:09.623159 DQ4 =96, DQ5 =110, DQ6 =110, DQ7 =96
5847 01:33:09.626439 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
5848 01:33:09.633000 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =106
5849 01:33:09.633419
5850 01:33:09.633752
5851 01:33:09.639523 [DQSOSCAuto] RK0, (LSB)MR18= 0x1606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5852 01:33:09.642936 CH1 RK0: MR19=505, MR18=1606
5853 01:33:09.649397 CH1_RK0: MR19=0x505, MR18=0x1606, DQSOSC=414, MR23=63, INC=63, DEC=42
5854 01:33:09.649836
5855 01:33:09.652709 ----->DramcWriteLeveling(PI) begin...
5856 01:33:09.653164 ==
5857 01:33:09.656035 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 01:33:09.659465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 01:33:09.659888 ==
5860 01:33:09.662785 Write leveling (Byte 0): 25 => 25
5861 01:33:09.666037 Write leveling (Byte 1): 29 => 29
5862 01:33:09.669688 DramcWriteLeveling(PI) end<-----
5863 01:33:09.670116
5864 01:33:09.670507 ==
5865 01:33:09.672771 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 01:33:09.676096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 01:33:09.679185 ==
5868 01:33:09.679604 [Gating] SW mode calibration
5869 01:33:09.688972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5870 01:33:09.692385 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5871 01:33:09.696167 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
5872 01:33:09.702229 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5873 01:33:09.705363 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5874 01:33:09.708546 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5875 01:33:09.715249 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5876 01:33:09.718568 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5877 01:33:09.722014 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5878 01:33:09.728893 0 14 28 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 1)
5879 01:33:09.731855 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5880 01:33:09.735430 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5881 01:33:09.741843 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5882 01:33:09.745419 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5883 01:33:09.748484 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5884 01:33:09.754830 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5885 01:33:09.758241 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5886 01:33:09.761563 0 15 28 | B1->B0 | 3939 2d2d | 0 0 | (0 0) (0 0)
5887 01:33:09.768124 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 01:33:09.771578 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5889 01:33:09.774651 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5890 01:33:09.781301 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5891 01:33:09.784658 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5892 01:33:09.788306 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 01:33:09.794702 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5894 01:33:09.797899 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 01:33:09.801228 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5896 01:33:09.808086 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 01:33:09.811249 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 01:33:09.815766 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 01:33:09.821187 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 01:33:09.824957 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 01:33:09.827363 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 01:33:09.834432 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 01:33:09.837695 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 01:33:09.840450 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 01:33:09.846821 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 01:33:09.850446 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 01:33:09.854062 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 01:33:09.860645 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5909 01:33:09.864216 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5910 01:33:09.867012 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5911 01:33:09.873871 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5912 01:33:09.877007 Total UI for P1: 0, mck2ui 16
5913 01:33:09.880219 best dqsien dly found for B0: ( 1, 2, 28)
5914 01:33:09.883741 Total UI for P1: 0, mck2ui 16
5915 01:33:09.886518 best dqsien dly found for B1: ( 1, 2, 26)
5916 01:33:09.889986 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5917 01:33:09.893403 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5918 01:33:09.893863
5919 01:33:09.896920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5920 01:33:09.899972 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5921 01:33:09.903510 [Gating] SW calibration Done
5922 01:33:09.903972 ==
5923 01:33:09.906430 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 01:33:09.910374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 01:33:09.910925 ==
5926 01:33:09.913194 RX Vref Scan: 0
5927 01:33:09.913742
5928 01:33:09.916906 RX Vref 0 -> 0, step: 1
5929 01:33:09.917455
5930 01:33:09.917814 RX Delay -80 -> 252, step: 8
5931 01:33:09.923293 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5932 01:33:09.926265 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5933 01:33:09.929861 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5934 01:33:09.933072 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5935 01:33:09.936332 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5936 01:33:09.939417 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5937 01:33:09.946365 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5938 01:33:09.949416 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5939 01:33:09.952934 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5940 01:33:09.956165 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5941 01:33:09.959478 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5942 01:33:09.966029 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5943 01:33:09.969261 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5944 01:33:09.972535 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5945 01:33:09.975625 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5946 01:33:09.979116 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5947 01:33:09.979572 ==
5948 01:33:09.982474 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 01:33:09.988777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 01:33:09.989350 ==
5951 01:33:09.989718 DQS Delay:
5952 01:33:09.992331 DQS0 = 0, DQS1 = 0
5953 01:33:09.992903 DQM Delay:
5954 01:33:09.995485 DQM0 = 99, DQM1 = 90
5955 01:33:09.996001 DQ Delay:
5956 01:33:09.999036 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5957 01:33:10.001930 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5958 01:33:10.005759 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5959 01:33:10.008884 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5960 01:33:10.009455
5961 01:33:10.009827
5962 01:33:10.010195 ==
5963 01:33:10.011868 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 01:33:10.015281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 01:33:10.015837 ==
5966 01:33:10.016203
5967 01:33:10.016536
5968 01:33:10.019045 TX Vref Scan disable
5969 01:33:10.022192 == TX Byte 0 ==
5970 01:33:10.025486 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5971 01:33:10.028464 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5972 01:33:10.031596 == TX Byte 1 ==
5973 01:33:10.035066 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5974 01:33:10.039017 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5975 01:33:10.039571 ==
5976 01:33:10.041807 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 01:33:10.048114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 01:33:10.048686 ==
5979 01:33:10.049056
5980 01:33:10.049390
5981 01:33:10.049709 TX Vref Scan disable
5982 01:33:10.052561 == TX Byte 0 ==
5983 01:33:10.055682 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5984 01:33:10.062227 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5985 01:33:10.062689 == TX Byte 1 ==
5986 01:33:10.065543 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5987 01:33:10.071770 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5988 01:33:10.072313
5989 01:33:10.072680 [DATLAT]
5990 01:33:10.073057 Freq=933, CH1 RK1
5991 01:33:10.073400
5992 01:33:10.075359 DATLAT Default: 0xb
5993 01:33:10.078723 0, 0xFFFF, sum = 0
5994 01:33:10.079191 1, 0xFFFF, sum = 0
5995 01:33:10.081893 2, 0xFFFF, sum = 0
5996 01:33:10.082406 3, 0xFFFF, sum = 0
5997 01:33:10.085427 4, 0xFFFF, sum = 0
5998 01:33:10.085994 5, 0xFFFF, sum = 0
5999 01:33:10.088730 6, 0xFFFF, sum = 0
6000 01:33:10.089299 7, 0xFFFF, sum = 0
6001 01:33:10.091606 8, 0xFFFF, sum = 0
6002 01:33:10.092076 9, 0xFFFF, sum = 0
6003 01:33:10.094979 10, 0x0, sum = 1
6004 01:33:10.095448 11, 0x0, sum = 2
6005 01:33:10.098054 12, 0x0, sum = 3
6006 01:33:10.098500 13, 0x0, sum = 4
6007 01:33:10.101315 best_step = 11
6008 01:33:10.101732
6009 01:33:10.102064 ==
6010 01:33:10.104727 Dram Type= 6, Freq= 0, CH_1, rank 1
6011 01:33:10.108843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6012 01:33:10.109372 ==
6013 01:33:10.109711 RX Vref Scan: 0
6014 01:33:10.111348
6015 01:33:10.111764 RX Vref 0 -> 0, step: 1
6016 01:33:10.112099
6017 01:33:10.114797 RX Delay -61 -> 252, step: 4
6018 01:33:10.121886 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6019 01:33:10.124923 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6020 01:33:10.128421 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6021 01:33:10.131189 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
6022 01:33:10.134684 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6023 01:33:10.141154 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6024 01:33:10.144437 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6025 01:33:10.147922 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6026 01:33:10.151056 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6027 01:33:10.154662 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6028 01:33:10.158445 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6029 01:33:10.164441 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6030 01:33:10.168068 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6031 01:33:10.170703 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6032 01:33:10.174279 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6033 01:33:10.178093 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6034 01:33:10.180591 ==
6035 01:33:10.184282 Dram Type= 6, Freq= 0, CH_1, rank 1
6036 01:33:10.187449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6037 01:33:10.188011 ==
6038 01:33:10.188386 DQS Delay:
6039 01:33:10.190217 DQS0 = 0, DQS1 = 0
6040 01:33:10.190681 DQM Delay:
6041 01:33:10.194350 DQM0 = 100, DQM1 = 93
6042 01:33:10.194933 DQ Delay:
6043 01:33:10.197277 DQ0 =106, DQ1 =94, DQ2 =88, DQ3 =96
6044 01:33:10.200096 DQ4 =98, DQ5 =112, DQ6 =112, DQ7 =98
6045 01:33:10.203565 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =82
6046 01:33:10.207019 DQ12 =102, DQ13 =102, DQ14 =98, DQ15 =102
6047 01:33:10.207491
6048 01:33:10.208024
6049 01:33:10.217058 [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6050 01:33:10.217620 CH1 RK1: MR19=505, MR18=600
6051 01:33:10.223284 CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40
6052 01:33:10.226832 [RxdqsGatingPostProcess] freq 933
6053 01:33:10.233514 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6054 01:33:10.236857 best DQS0 dly(2T, 0.5T) = (0, 10)
6055 01:33:10.240327 best DQS1 dly(2T, 0.5T) = (0, 10)
6056 01:33:10.242963 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6057 01:33:10.246375 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6058 01:33:10.250914 best DQS0 dly(2T, 0.5T) = (0, 10)
6059 01:33:10.251490 best DQS1 dly(2T, 0.5T) = (0, 10)
6060 01:33:10.253150 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6061 01:33:10.256140 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6062 01:33:10.260043 Pre-setting of DQS Precalculation
6063 01:33:10.266584 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6064 01:33:10.272739 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6065 01:33:10.279683 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6066 01:33:10.280246
6067 01:33:10.280614
6068 01:33:10.282681 [Calibration Summary] 1866 Mbps
6069 01:33:10.286034 CH 0, Rank 0
6070 01:33:10.286574 SW Impedance : PASS
6071 01:33:10.289340 DUTY Scan : NO K
6072 01:33:10.292902 ZQ Calibration : PASS
6073 01:33:10.293463 Jitter Meter : NO K
6074 01:33:10.296158 CBT Training : PASS
6075 01:33:10.296722 Write leveling : PASS
6076 01:33:10.299204 RX DQS gating : PASS
6077 01:33:10.302710 RX DQ/DQS(RDDQC) : PASS
6078 01:33:10.303325 TX DQ/DQS : PASS
6079 01:33:10.305689 RX DATLAT : PASS
6080 01:33:10.309140 RX DQ/DQS(Engine): PASS
6081 01:33:10.309606 TX OE : NO K
6082 01:33:10.312710 All Pass.
6083 01:33:10.313286
6084 01:33:10.313703 CH 0, Rank 1
6085 01:33:10.315868 SW Impedance : PASS
6086 01:33:10.316430 DUTY Scan : NO K
6087 01:33:10.318998 ZQ Calibration : PASS
6088 01:33:10.322271 Jitter Meter : NO K
6089 01:33:10.322765 CBT Training : PASS
6090 01:33:10.325923 Write leveling : PASS
6091 01:33:10.328867 RX DQS gating : PASS
6092 01:33:10.329326 RX DQ/DQS(RDDQC) : PASS
6093 01:33:10.332521 TX DQ/DQS : PASS
6094 01:33:10.335461 RX DATLAT : PASS
6095 01:33:10.335922 RX DQ/DQS(Engine): PASS
6096 01:33:10.339054 TX OE : NO K
6097 01:33:10.339619 All Pass.
6098 01:33:10.339990
6099 01:33:10.342371 CH 1, Rank 0
6100 01:33:10.342922 SW Impedance : PASS
6101 01:33:10.345400 DUTY Scan : NO K
6102 01:33:10.349391 ZQ Calibration : PASS
6103 01:33:10.350077 Jitter Meter : NO K
6104 01:33:10.352402 CBT Training : PASS
6105 01:33:10.355541 Write leveling : PASS
6106 01:33:10.356294 RX DQS gating : PASS
6107 01:33:10.358883 RX DQ/DQS(RDDQC) : PASS
6108 01:33:10.359344 TX DQ/DQS : PASS
6109 01:33:10.362324 RX DATLAT : PASS
6110 01:33:10.365797 RX DQ/DQS(Engine): PASS
6111 01:33:10.366466 TX OE : NO K
6112 01:33:10.368621 All Pass.
6113 01:33:10.369168
6114 01:33:10.369538 CH 1, Rank 1
6115 01:33:10.371920 SW Impedance : PASS
6116 01:33:10.372473 DUTY Scan : NO K
6117 01:33:10.375372 ZQ Calibration : PASS
6118 01:33:10.378678 Jitter Meter : NO K
6119 01:33:10.379141 CBT Training : PASS
6120 01:33:10.381958 Write leveling : PASS
6121 01:33:10.385549 RX DQS gating : PASS
6122 01:33:10.386156 RX DQ/DQS(RDDQC) : PASS
6123 01:33:10.388888 TX DQ/DQS : PASS
6124 01:33:10.391825 RX DATLAT : PASS
6125 01:33:10.392382 RX DQ/DQS(Engine): PASS
6126 01:33:10.394982 TX OE : NO K
6127 01:33:10.395447 All Pass.
6128 01:33:10.395868
6129 01:33:10.398404 DramC Write-DBI off
6130 01:33:10.401865 PER_BANK_REFRESH: Hybrid Mode
6131 01:33:10.402468 TX_TRACKING: ON
6132 01:33:10.411985 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6133 01:33:10.414645 [FAST_K] Save calibration result to emmc
6134 01:33:10.418148 dramc_set_vcore_voltage set vcore to 650000
6135 01:33:10.421359 Read voltage for 400, 6
6136 01:33:10.421821 Vio18 = 0
6137 01:33:10.422230 Vcore = 650000
6138 01:33:10.424906 Vdram = 0
6139 01:33:10.425468 Vddq = 0
6140 01:33:10.425835 Vmddr = 0
6141 01:33:10.431191 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6142 01:33:10.434757 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6143 01:33:10.438201 MEM_TYPE=3, freq_sel=20
6144 01:33:10.441082 sv_algorithm_assistance_LP4_800
6145 01:33:10.444724 ============ PULL DRAM RESETB DOWN ============
6146 01:33:10.451305 ========== PULL DRAM RESETB DOWN end =========
6147 01:33:10.454233 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 01:33:10.457757 ===================================
6149 01:33:10.460872 LPDDR4 DRAM CONFIGURATION
6150 01:33:10.464334 ===================================
6151 01:33:10.464802 EX_ROW_EN[0] = 0x0
6152 01:33:10.467627 EX_ROW_EN[1] = 0x0
6153 01:33:10.468182 LP4Y_EN = 0x0
6154 01:33:10.470652 WORK_FSP = 0x0
6155 01:33:10.471138 WL = 0x2
6156 01:33:10.473849 RL = 0x2
6157 01:33:10.474382 BL = 0x2
6158 01:33:10.477025 RPST = 0x0
6159 01:33:10.480811 RD_PRE = 0x0
6160 01:33:10.481363 WR_PRE = 0x1
6161 01:33:10.484078 WR_PST = 0x0
6162 01:33:10.484580 DBI_WR = 0x0
6163 01:33:10.487423 DBI_RD = 0x0
6164 01:33:10.487891 OTF = 0x1
6165 01:33:10.490490 ===================================
6166 01:33:10.493939 ===================================
6167 01:33:10.497352 ANA top config
6168 01:33:10.500433 ===================================
6169 01:33:10.500984 DLL_ASYNC_EN = 0
6170 01:33:10.503937 ALL_SLAVE_EN = 1
6171 01:33:10.507119 NEW_RANK_MODE = 1
6172 01:33:10.510342 DLL_IDLE_MODE = 1
6173 01:33:10.510913 LP45_APHY_COMB_EN = 1
6174 01:33:10.513869 TX_ODT_DIS = 1
6175 01:33:10.516827 NEW_8X_MODE = 1
6176 01:33:10.520232 ===================================
6177 01:33:10.523654 ===================================
6178 01:33:10.527162 data_rate = 800
6179 01:33:10.530146 CKR = 1
6180 01:33:10.533536 DQ_P2S_RATIO = 4
6181 01:33:10.536702 ===================================
6182 01:33:10.537254 CA_P2S_RATIO = 4
6183 01:33:10.540393 DQ_CA_OPEN = 0
6184 01:33:10.543760 DQ_SEMI_OPEN = 1
6185 01:33:10.546518 CA_SEMI_OPEN = 1
6186 01:33:10.550100 CA_FULL_RATE = 0
6187 01:33:10.553821 DQ_CKDIV4_EN = 0
6188 01:33:10.554585 CA_CKDIV4_EN = 1
6189 01:33:10.556472 CA_PREDIV_EN = 0
6190 01:33:10.560131 PH8_DLY = 0
6191 01:33:10.563329 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6192 01:33:10.566473 DQ_AAMCK_DIV = 0
6193 01:33:10.570298 CA_AAMCK_DIV = 0
6194 01:33:10.570847 CA_ADMCK_DIV = 4
6195 01:33:10.573248 DQ_TRACK_CA_EN = 0
6196 01:33:10.576275 CA_PICK = 800
6197 01:33:10.580252 CA_MCKIO = 400
6198 01:33:10.582928 MCKIO_SEMI = 400
6199 01:33:10.586075 PLL_FREQ = 3016
6200 01:33:10.589557 DQ_UI_PI_RATIO = 32
6201 01:33:10.593019 CA_UI_PI_RATIO = 32
6202 01:33:10.596226 ===================================
6203 01:33:10.599421 ===================================
6204 01:33:10.599991 memory_type:LPDDR4
6205 01:33:10.602686 GP_NUM : 10
6206 01:33:10.605868 SRAM_EN : 1
6207 01:33:10.606359 MD32_EN : 0
6208 01:33:10.609323 ===================================
6209 01:33:10.612661 [ANA_INIT] >>>>>>>>>>>>>>
6210 01:33:10.615891 <<<<<< [CONFIGURE PHASE]: ANA_TX
6211 01:33:10.619194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6212 01:33:10.622199 ===================================
6213 01:33:10.626069 data_rate = 800,PCW = 0X7400
6214 01:33:10.628969 ===================================
6215 01:33:10.632357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6216 01:33:10.635847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6217 01:33:10.649214 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6218 01:33:10.652198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6219 01:33:10.655342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6220 01:33:10.658366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6221 01:33:10.662345 [ANA_INIT] flow start
6222 01:33:10.666087 [ANA_INIT] PLL >>>>>>>>
6223 01:33:10.666721 [ANA_INIT] PLL <<<<<<<<
6224 01:33:10.668400 [ANA_INIT] MIDPI >>>>>>>>
6225 01:33:10.671625 [ANA_INIT] MIDPI <<<<<<<<
6226 01:33:10.672090 [ANA_INIT] DLL >>>>>>>>
6227 01:33:10.675047 [ANA_INIT] flow end
6228 01:33:10.678044 ============ LP4 DIFF to SE enter ============
6229 01:33:10.684997 ============ LP4 DIFF to SE exit ============
6230 01:33:10.685546 [ANA_INIT] <<<<<<<<<<<<<
6231 01:33:10.688322 [Flow] Enable top DCM control >>>>>
6232 01:33:10.691299 [Flow] Enable top DCM control <<<<<
6233 01:33:10.694610 Enable DLL master slave shuffle
6234 01:33:10.701237 ==============================================================
6235 01:33:10.701781 Gating Mode config
6236 01:33:10.708268 ==============================================================
6237 01:33:10.711058 Config description:
6238 01:33:10.721720 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6239 01:33:10.727881 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6240 01:33:10.731055 SELPH_MODE 0: By rank 1: By Phase
6241 01:33:10.737537 ==============================================================
6242 01:33:10.740649 GAT_TRACK_EN = 0
6243 01:33:10.744355 RX_GATING_MODE = 2
6244 01:33:10.745007 RX_GATING_TRACK_MODE = 2
6245 01:33:10.747172 SELPH_MODE = 1
6246 01:33:10.750627 PICG_EARLY_EN = 1
6247 01:33:10.753886 VALID_LAT_VALUE = 1
6248 01:33:10.760346 ==============================================================
6249 01:33:10.763854 Enter into Gating configuration >>>>
6250 01:33:10.766913 Exit from Gating configuration <<<<
6251 01:33:10.770594 Enter into DVFS_PRE_config >>>>>
6252 01:33:10.779970 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6253 01:33:10.783403 Exit from DVFS_PRE_config <<<<<
6254 01:33:10.786730 Enter into PICG configuration >>>>
6255 01:33:10.789576 Exit from PICG configuration <<<<
6256 01:33:10.792845 [RX_INPUT] configuration >>>>>
6257 01:33:10.796436 [RX_INPUT] configuration <<<<<
6258 01:33:10.799839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6259 01:33:10.806270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6260 01:33:10.813047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6261 01:33:10.819349 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6262 01:33:10.825671 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6263 01:33:10.832790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6264 01:33:10.836081 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6265 01:33:10.839111 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6266 01:33:10.842653 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6267 01:33:10.849178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6268 01:33:10.852373 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6269 01:33:10.855541 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6270 01:33:10.858702 ===================================
6271 01:33:10.862459 LPDDR4 DRAM CONFIGURATION
6272 01:33:10.865738 ===================================
6273 01:33:10.866311 EX_ROW_EN[0] = 0x0
6274 01:33:10.868809 EX_ROW_EN[1] = 0x0
6275 01:33:10.872007 LP4Y_EN = 0x0
6276 01:33:10.872549 WORK_FSP = 0x0
6277 01:33:10.875146 WL = 0x2
6278 01:33:10.875564 RL = 0x2
6279 01:33:10.878507 BL = 0x2
6280 01:33:10.878924 RPST = 0x0
6281 01:33:10.881511 RD_PRE = 0x0
6282 01:33:10.881932 WR_PRE = 0x1
6283 01:33:10.885234 WR_PST = 0x0
6284 01:33:10.885754 DBI_WR = 0x0
6285 01:33:10.888256 DBI_RD = 0x0
6286 01:33:10.888674 OTF = 0x1
6287 01:33:10.891835 ===================================
6288 01:33:10.898284 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6289 01:33:10.901810 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6290 01:33:10.904907 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6291 01:33:10.908082 ===================================
6292 01:33:10.911434 LPDDR4 DRAM CONFIGURATION
6293 01:33:10.915081 ===================================
6294 01:33:10.918110 EX_ROW_EN[0] = 0x10
6295 01:33:10.918571 EX_ROW_EN[1] = 0x0
6296 01:33:10.921170 LP4Y_EN = 0x0
6297 01:33:10.921616 WORK_FSP = 0x0
6298 01:33:10.924679 WL = 0x2
6299 01:33:10.925100 RL = 0x2
6300 01:33:10.927613 BL = 0x2
6301 01:33:10.928031 RPST = 0x0
6302 01:33:10.931076 RD_PRE = 0x0
6303 01:33:10.931496 WR_PRE = 0x1
6304 01:33:10.934199 WR_PST = 0x0
6305 01:33:10.934624 DBI_WR = 0x0
6306 01:33:10.937879 DBI_RD = 0x0
6307 01:33:10.938447 OTF = 0x1
6308 01:33:10.941026 ===================================
6309 01:33:10.947300 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6310 01:33:10.952642 nWR fixed to 30
6311 01:33:10.956071 [ModeRegInit_LP4] CH0 RK0
6312 01:33:10.956493 [ModeRegInit_LP4] CH0 RK1
6313 01:33:10.958865 [ModeRegInit_LP4] CH1 RK0
6314 01:33:10.962077 [ModeRegInit_LP4] CH1 RK1
6315 01:33:10.962536 match AC timing 19
6316 01:33:10.968708 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6317 01:33:10.972408 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6318 01:33:10.975415 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6319 01:33:10.982267 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6320 01:33:10.986032 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6321 01:33:10.986638 ==
6322 01:33:10.988778 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 01:33:10.992328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 01:33:10.992845 ==
6325 01:33:10.998849 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6326 01:33:11.005051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6327 01:33:11.008957 [CA 0] Center 36 (8~64) winsize 57
6328 01:33:11.011665 [CA 1] Center 36 (8~64) winsize 57
6329 01:33:11.015019 [CA 2] Center 36 (8~64) winsize 57
6330 01:33:11.018503 [CA 3] Center 36 (8~64) winsize 57
6331 01:33:11.021981 [CA 4] Center 36 (8~64) winsize 57
6332 01:33:11.024956 [CA 5] Center 36 (8~64) winsize 57
6333 01:33:11.025479
6334 01:33:11.027926 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6335 01:33:11.028344
6336 01:33:11.031474 [CATrainingPosCal] consider 1 rank data
6337 01:33:11.034703 u2DelayCellTimex100 = 270/100 ps
6338 01:33:11.038024 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 01:33:11.041404 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 01:33:11.044316 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 01:33:11.047700 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 01:33:11.050975 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 01:33:11.054659 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 01:33:11.055187
6345 01:33:11.060696 CA PerBit enable=1, Macro0, CA PI delay=36
6346 01:33:11.061117
6347 01:33:11.063944 [CBTSetCACLKResult] CA Dly = 36
6348 01:33:11.064484 CS Dly: 1 (0~32)
6349 01:33:11.064821 ==
6350 01:33:11.068299 Dram Type= 6, Freq= 0, CH_0, rank 1
6351 01:33:11.070598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 01:33:11.071023 ==
6353 01:33:11.077457 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6354 01:33:11.083982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6355 01:33:11.087282 [CA 0] Center 36 (8~64) winsize 57
6356 01:33:11.090551 [CA 1] Center 36 (8~64) winsize 57
6357 01:33:11.094037 [CA 2] Center 36 (8~64) winsize 57
6358 01:33:11.097214 [CA 3] Center 36 (8~64) winsize 57
6359 01:33:11.100553 [CA 4] Center 36 (8~64) winsize 57
6360 01:33:11.103555 [CA 5] Center 36 (8~64) winsize 57
6361 01:33:11.103975
6362 01:33:11.106760 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6363 01:33:11.107178
6364 01:33:11.110405 [CATrainingPosCal] consider 2 rank data
6365 01:33:11.113313 u2DelayCellTimex100 = 270/100 ps
6366 01:33:11.116772 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 01:33:11.120395 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 01:33:11.123088 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 01:33:11.126715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 01:33:11.130154 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 01:33:11.133751 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 01:33:11.134468
6373 01:33:11.140192 CA PerBit enable=1, Macro0, CA PI delay=36
6374 01:33:11.140608
6375 01:33:11.140939 [CBTSetCACLKResult] CA Dly = 36
6376 01:33:11.143283 CS Dly: 1 (0~32)
6377 01:33:11.143697
6378 01:33:11.146414 ----->DramcWriteLeveling(PI) begin...
6379 01:33:11.146834 ==
6380 01:33:11.150053 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 01:33:11.153274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 01:33:11.153797 ==
6383 01:33:11.156260 Write leveling (Byte 0): 40 => 8
6384 01:33:11.159616 Write leveling (Byte 1): 32 => 0
6385 01:33:11.162933 DramcWriteLeveling(PI) end<-----
6386 01:33:11.163349
6387 01:33:11.163676 ==
6388 01:33:11.166281 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 01:33:11.169715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 01:33:11.173112 ==
6391 01:33:11.173527 [Gating] SW mode calibration
6392 01:33:11.182717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6393 01:33:11.186336 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6394 01:33:11.189374 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6395 01:33:11.195964 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6396 01:33:11.199096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6397 01:33:11.202713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6398 01:33:11.209690 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6399 01:33:11.213019 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6400 01:33:11.215821 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6401 01:33:11.222307 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6402 01:33:11.225912 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 01:33:11.229303 Total UI for P1: 0, mck2ui 16
6404 01:33:11.232405 best dqsien dly found for B0: ( 0, 14, 24)
6405 01:33:11.235515 Total UI for P1: 0, mck2ui 16
6406 01:33:11.238953 best dqsien dly found for B1: ( 0, 14, 24)
6407 01:33:11.242477 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6408 01:33:11.245475 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6409 01:33:11.245891
6410 01:33:11.248808 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6411 01:33:11.255289 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6412 01:33:11.255871 [Gating] SW calibration Done
6413 01:33:11.256209 ==
6414 01:33:11.259085 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 01:33:11.265319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 01:33:11.265848 ==
6417 01:33:11.266248 RX Vref Scan: 0
6418 01:33:11.266586
6419 01:33:11.268817 RX Vref 0 -> 0, step: 1
6420 01:33:11.269234
6421 01:33:11.271652 RX Delay -410 -> 252, step: 16
6422 01:33:11.275591 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6423 01:33:11.278524 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6424 01:33:11.285057 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6425 01:33:11.288044 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6426 01:33:11.292063 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6427 01:33:11.294764 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6428 01:33:11.301684 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6429 01:33:11.304686 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6430 01:33:11.308174 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6431 01:33:11.311240 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6432 01:33:11.318005 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6433 01:33:11.321195 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6434 01:33:11.324586 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6435 01:33:11.331343 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6436 01:33:11.334299 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6437 01:33:11.338290 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6438 01:33:11.338844 ==
6439 01:33:11.341084 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 01:33:11.344743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 01:33:11.347479 ==
6442 01:33:11.347943 DQS Delay:
6443 01:33:11.348310 DQS0 = 43, DQS1 = 59
6444 01:33:11.350854 DQM Delay:
6445 01:33:11.351318 DQM0 = 9, DQM1 = 12
6446 01:33:11.354328 DQ Delay:
6447 01:33:11.354875 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6448 01:33:11.357439 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6449 01:33:11.360755 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6450 01:33:11.364032 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6451 01:33:11.364497
6452 01:33:11.364859
6453 01:33:11.367175 ==
6454 01:33:11.367641 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 01:33:11.373770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 01:33:11.374406 ==
6457 01:33:11.374790
6458 01:33:11.375128
6459 01:33:11.376963 TX Vref Scan disable
6460 01:33:11.377423 == TX Byte 0 ==
6461 01:33:11.380553 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6462 01:33:11.387503 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6463 01:33:11.388103 == TX Byte 1 ==
6464 01:33:11.390631 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6465 01:33:11.397131 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6466 01:33:11.397687 ==
6467 01:33:11.400521 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 01:33:11.403857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 01:33:11.404325 ==
6470 01:33:11.404698
6471 01:33:11.405040
6472 01:33:11.406697 TX Vref Scan disable
6473 01:33:11.407162 == TX Byte 0 ==
6474 01:33:11.410793 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6475 01:33:11.416643 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6476 01:33:11.417191 == TX Byte 1 ==
6477 01:33:11.423496 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6478 01:33:11.426531 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6479 01:33:11.426997
6480 01:33:11.427364 [DATLAT]
6481 01:33:11.430263 Freq=400, CH0 RK0
6482 01:33:11.430970
6483 01:33:11.431456 DATLAT Default: 0xf
6484 01:33:11.433145 0, 0xFFFF, sum = 0
6485 01:33:11.433636 1, 0xFFFF, sum = 0
6486 01:33:11.436547 2, 0xFFFF, sum = 0
6487 01:33:11.437033 3, 0xFFFF, sum = 0
6488 01:33:11.439788 4, 0xFFFF, sum = 0
6489 01:33:11.440347 5, 0xFFFF, sum = 0
6490 01:33:11.442966 6, 0xFFFF, sum = 0
6491 01:33:11.443436 7, 0xFFFF, sum = 0
6492 01:33:11.446350 8, 0xFFFF, sum = 0
6493 01:33:11.446818 9, 0xFFFF, sum = 0
6494 01:33:11.449756 10, 0xFFFF, sum = 0
6495 01:33:11.452978 11, 0xFFFF, sum = 0
6496 01:33:11.453447 12, 0xFFFF, sum = 0
6497 01:33:11.455934 13, 0x0, sum = 1
6498 01:33:11.456403 14, 0x0, sum = 2
6499 01:33:11.459416 15, 0x0, sum = 3
6500 01:33:11.459980 16, 0x0, sum = 4
6501 01:33:11.460359 best_step = 14
6502 01:33:11.460705
6503 01:33:11.462924 ==
6504 01:33:11.465847 Dram Type= 6, Freq= 0, CH_0, rank 0
6505 01:33:11.469061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 01:33:11.469525 ==
6507 01:33:11.469895 RX Vref Scan: 1
6508 01:33:11.470291
6509 01:33:11.472589 RX Vref 0 -> 0, step: 1
6510 01:33:11.473182
6511 01:33:11.476109 RX Delay -359 -> 252, step: 8
6512 01:33:11.476723
6513 01:33:11.478804 Set Vref, RX VrefLevel [Byte0]: 60
6514 01:33:11.482683 [Byte1]: 52
6515 01:33:11.486263
6516 01:33:11.486886 Final RX Vref Byte 0 = 60 to rank0
6517 01:33:11.489435 Final RX Vref Byte 1 = 52 to rank0
6518 01:33:11.492791 Final RX Vref Byte 0 = 60 to rank1
6519 01:33:11.495998 Final RX Vref Byte 1 = 52 to rank1==
6520 01:33:11.499705 Dram Type= 6, Freq= 0, CH_0, rank 0
6521 01:33:11.505845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 01:33:11.506367 ==
6523 01:33:11.506744 DQS Delay:
6524 01:33:11.509662 DQS0 = 48, DQS1 = 64
6525 01:33:11.510269 DQM Delay:
6526 01:33:11.512687 DQM0 = 11, DQM1 = 15
6527 01:33:11.513208 DQ Delay:
6528 01:33:11.515859 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6529 01:33:11.518711 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6530 01:33:11.522801 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6531 01:33:11.525484 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6532 01:33:11.525945
6533 01:33:11.526361
6534 01:33:11.532052 [DQSOSCAuto] RK0, (LSB)MR18= 0xb67a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6535 01:33:11.535798 CH0 RK0: MR19=C0C, MR18=B67A
6536 01:33:11.542548 CH0_RK0: MR19=0xC0C, MR18=0xB67A, DQSOSC=387, MR23=63, INC=394, DEC=262
6537 01:33:11.543108 ==
6538 01:33:11.545402 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 01:33:11.548721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 01:33:11.549283 ==
6541 01:33:11.552405 [Gating] SW mode calibration
6542 01:33:11.559151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6543 01:33:11.564856 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6544 01:33:11.568461 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6545 01:33:11.574917 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6546 01:33:11.578139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6547 01:33:11.581729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6548 01:33:11.587965 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6549 01:33:11.591106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6550 01:33:11.594461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6551 01:33:11.601310 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6552 01:33:11.604210 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6553 01:33:11.607581 Total UI for P1: 0, mck2ui 16
6554 01:33:11.611405 best dqsien dly found for B0: ( 0, 14, 24)
6555 01:33:11.614579 Total UI for P1: 0, mck2ui 16
6556 01:33:11.617644 best dqsien dly found for B1: ( 0, 14, 24)
6557 01:33:11.621016 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6558 01:33:11.624124 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6559 01:33:11.624586
6560 01:33:11.627494 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6561 01:33:11.630929 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6562 01:33:11.634306 [Gating] SW calibration Done
6563 01:33:11.634865 ==
6564 01:33:11.637732 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 01:33:11.641040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 01:33:11.644695 ==
6567 01:33:11.645250 RX Vref Scan: 0
6568 01:33:11.645620
6569 01:33:11.647344 RX Vref 0 -> 0, step: 1
6570 01:33:11.647807
6571 01:33:11.650961 RX Delay -410 -> 252, step: 16
6572 01:33:11.654366 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6573 01:33:11.657156 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6574 01:33:11.660427 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6575 01:33:11.667356 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6576 01:33:11.670371 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6577 01:33:11.673993 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6578 01:33:11.677000 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6579 01:33:11.683930 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6580 01:33:11.686840 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6581 01:33:11.690601 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6582 01:33:11.696852 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6583 01:33:11.700194 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6584 01:33:11.703452 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6585 01:33:11.706489 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6586 01:33:11.713268 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6587 01:33:11.716887 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6588 01:33:11.717478 ==
6589 01:33:11.720211 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 01:33:11.723217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 01:33:11.723683 ==
6592 01:33:11.726419 DQS Delay:
6593 01:33:11.726876 DQS0 = 43, DQS1 = 59
6594 01:33:11.729912 DQM Delay:
6595 01:33:11.730510 DQM0 = 10, DQM1 = 16
6596 01:33:11.730931 DQ Delay:
6597 01:33:11.733449 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6598 01:33:11.736471 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6599 01:33:11.740196 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6600 01:33:11.743090 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6601 01:33:11.743637
6602 01:33:11.744003
6603 01:33:11.744340 ==
6604 01:33:11.746641 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 01:33:11.753129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 01:33:11.753690 ==
6607 01:33:11.754060
6608 01:33:11.754457
6609 01:33:11.754788 TX Vref Scan disable
6610 01:33:11.756398 == TX Byte 0 ==
6611 01:33:11.759394 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6612 01:33:11.762603 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6613 01:33:11.765861 == TX Byte 1 ==
6614 01:33:11.769130 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6615 01:33:11.772540 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6616 01:33:11.773059 ==
6617 01:33:11.776228 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 01:33:11.782400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 01:33:11.782884 ==
6620 01:33:11.783257
6621 01:33:11.783599
6622 01:33:11.783932 TX Vref Scan disable
6623 01:33:11.785627 == TX Byte 0 ==
6624 01:33:11.789037 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6625 01:33:11.792142 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6626 01:33:11.795919 == TX Byte 1 ==
6627 01:33:11.799191 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6628 01:33:11.802328 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6629 01:33:11.802883
6630 01:33:11.805836 [DATLAT]
6631 01:33:11.806526 Freq=400, CH0 RK1
6632 01:33:11.806903
6633 01:33:11.809166 DATLAT Default: 0xe
6634 01:33:11.809760 0, 0xFFFF, sum = 0
6635 01:33:11.812047 1, 0xFFFF, sum = 0
6636 01:33:11.812514 2, 0xFFFF, sum = 0
6637 01:33:11.815296 3, 0xFFFF, sum = 0
6638 01:33:11.815822 4, 0xFFFF, sum = 0
6639 01:33:11.818710 5, 0xFFFF, sum = 0
6640 01:33:11.819176 6, 0xFFFF, sum = 0
6641 01:33:11.822075 7, 0xFFFF, sum = 0
6642 01:33:11.825596 8, 0xFFFF, sum = 0
6643 01:33:11.826091 9, 0xFFFF, sum = 0
6644 01:33:11.828623 10, 0xFFFF, sum = 0
6645 01:33:11.829090 11, 0xFFFF, sum = 0
6646 01:33:11.831744 12, 0xFFFF, sum = 0
6647 01:33:11.832163 13, 0x0, sum = 1
6648 01:33:11.835181 14, 0x0, sum = 2
6649 01:33:11.835615 15, 0x0, sum = 3
6650 01:33:11.838346 16, 0x0, sum = 4
6651 01:33:11.838765 best_step = 14
6652 01:33:11.839095
6653 01:33:11.839401 ==
6654 01:33:11.841819 Dram Type= 6, Freq= 0, CH_0, rank 1
6655 01:33:11.845116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 01:33:11.848843 ==
6657 01:33:11.849356 RX Vref Scan: 0
6658 01:33:11.849692
6659 01:33:11.852429 RX Vref 0 -> 0, step: 1
6660 01:33:11.852939
6661 01:33:11.854722 RX Delay -359 -> 252, step: 8
6662 01:33:11.861470 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6663 01:33:11.864445 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6664 01:33:11.868093 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6665 01:33:11.871780 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6666 01:33:11.878261 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6667 01:33:11.881076 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6668 01:33:11.884064 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6669 01:33:11.887584 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6670 01:33:11.894333 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6671 01:33:11.897772 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6672 01:33:11.900905 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6673 01:33:11.904105 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6674 01:33:11.910468 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6675 01:33:11.914362 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6676 01:33:11.917267 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6677 01:33:11.923648 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6678 01:33:11.924214 ==
6679 01:33:11.926818 Dram Type= 6, Freq= 0, CH_0, rank 1
6680 01:33:11.930142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 01:33:11.930642 ==
6682 01:33:11.931012 DQS Delay:
6683 01:33:11.934102 DQS0 = 44, DQS1 = 60
6684 01:33:11.934610 DQM Delay:
6685 01:33:11.936854 DQM0 = 7, DQM1 = 14
6686 01:33:11.937314 DQ Delay:
6687 01:33:11.940264 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6688 01:33:11.943257 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6689 01:33:11.946620 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6690 01:33:11.949775 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6691 01:33:11.950227
6692 01:33:11.950594
6693 01:33:11.956778 [DQSOSCAuto] RK1, (LSB)MR18= 0xa836, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 388 ps
6694 01:33:11.959902 CH0 RK1: MR19=C0C, MR18=A836
6695 01:33:11.966226 CH0_RK1: MR19=0xC0C, MR18=0xA836, DQSOSC=388, MR23=63, INC=392, DEC=261
6696 01:33:11.970304 [RxdqsGatingPostProcess] freq 400
6697 01:33:11.976354 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6698 01:33:11.979473 best DQS0 dly(2T, 0.5T) = (0, 10)
6699 01:33:11.979894 best DQS1 dly(2T, 0.5T) = (0, 10)
6700 01:33:11.983156 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6701 01:33:11.986267 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6702 01:33:11.989408 best DQS0 dly(2T, 0.5T) = (0, 10)
6703 01:33:11.992625 best DQS1 dly(2T, 0.5T) = (0, 10)
6704 01:33:11.996097 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6705 01:33:11.999390 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6706 01:33:12.002680 Pre-setting of DQS Precalculation
6707 01:33:12.009042 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6708 01:33:12.009467 ==
6709 01:33:12.012637 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 01:33:12.015918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 01:33:12.016344 ==
6712 01:33:12.022713 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6713 01:33:12.028933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6714 01:33:12.032179 [CA 0] Center 36 (8~64) winsize 57
6715 01:33:12.032597 [CA 1] Center 36 (8~64) winsize 57
6716 01:33:12.035534 [CA 2] Center 36 (8~64) winsize 57
6717 01:33:12.039115 [CA 3] Center 36 (8~64) winsize 57
6718 01:33:12.042634 [CA 4] Center 36 (8~64) winsize 57
6719 01:33:12.045811 [CA 5] Center 36 (8~64) winsize 57
6720 01:33:12.046266
6721 01:33:12.049003 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6722 01:33:12.049509
6723 01:33:12.056088 [CATrainingPosCal] consider 1 rank data
6724 01:33:12.056613 u2DelayCellTimex100 = 270/100 ps
6725 01:33:12.061912 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 01:33:12.065322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 01:33:12.068331 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 01:33:12.071923 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 01:33:12.074945 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 01:33:12.078321 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 01:33:12.078747
6732 01:33:12.082437 CA PerBit enable=1, Macro0, CA PI delay=36
6733 01:33:12.082854
6734 01:33:12.085218 [CBTSetCACLKResult] CA Dly = 36
6735 01:33:12.088648 CS Dly: 1 (0~32)
6736 01:33:12.089066 ==
6737 01:33:12.091786 Dram Type= 6, Freq= 0, CH_1, rank 1
6738 01:33:12.094719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 01:33:12.095148 ==
6740 01:33:12.101396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6741 01:33:12.104839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6742 01:33:12.108492 [CA 0] Center 36 (8~64) winsize 57
6743 01:33:12.111581 [CA 1] Center 36 (8~64) winsize 57
6744 01:33:12.114696 [CA 2] Center 36 (8~64) winsize 57
6745 01:33:12.118082 [CA 3] Center 36 (8~64) winsize 57
6746 01:33:12.121217 [CA 4] Center 36 (8~64) winsize 57
6747 01:33:12.124540 [CA 5] Center 36 (8~64) winsize 57
6748 01:33:12.124962
6749 01:33:12.128019 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6750 01:33:12.128441
6751 01:33:12.131620 [CATrainingPosCal] consider 2 rank data
6752 01:33:12.134708 u2DelayCellTimex100 = 270/100 ps
6753 01:33:12.137890 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6754 01:33:12.141577 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6755 01:33:12.147994 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6756 01:33:12.151183 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6757 01:33:12.154272 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6758 01:33:12.157765 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6759 01:33:12.158222
6760 01:33:12.161052 CA PerBit enable=1, Macro0, CA PI delay=36
6761 01:33:12.161483
6762 01:33:12.164501 [CBTSetCACLKResult] CA Dly = 36
6763 01:33:12.164875 CS Dly: 1 (0~32)
6764 01:33:12.165223
6765 01:33:12.167574 ----->DramcWriteLeveling(PI) begin...
6766 01:33:12.171166 ==
6767 01:33:12.174379 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 01:33:12.177276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 01:33:12.177694 ==
6770 01:33:12.180938 Write leveling (Byte 0): 40 => 8
6771 01:33:12.184217 Write leveling (Byte 1): 32 => 0
6772 01:33:12.187371 DramcWriteLeveling(PI) end<-----
6773 01:33:12.187844
6774 01:33:12.188209 ==
6775 01:33:12.190965 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 01:33:12.193897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 01:33:12.194412 ==
6778 01:33:12.197535 [Gating] SW mode calibration
6779 01:33:12.203630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6780 01:33:12.210642 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6781 01:33:12.213724 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6782 01:33:12.217284 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6783 01:33:12.223634 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6784 01:33:12.226975 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6785 01:33:12.229896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6786 01:33:12.236709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6787 01:33:12.239758 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6788 01:33:12.242867 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6789 01:33:12.249633 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 01:33:12.250056 Total UI for P1: 0, mck2ui 16
6791 01:33:12.256542 best dqsien dly found for B0: ( 0, 14, 24)
6792 01:33:12.257157 Total UI for P1: 0, mck2ui 16
6793 01:33:12.262757 best dqsien dly found for B1: ( 0, 14, 24)
6794 01:33:12.266199 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6795 01:33:12.269701 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6796 01:33:12.270121
6797 01:33:12.272684 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6798 01:33:12.275883 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6799 01:33:12.279207 [Gating] SW calibration Done
6800 01:33:12.279645 ==
6801 01:33:12.282325 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 01:33:12.286620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 01:33:12.287039 ==
6804 01:33:12.289322 RX Vref Scan: 0
6805 01:33:12.289736
6806 01:33:12.292740 RX Vref 0 -> 0, step: 1
6807 01:33:12.293240
6808 01:33:12.293577 RX Delay -410 -> 252, step: 16
6809 01:33:12.299041 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6810 01:33:12.303001 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6811 01:33:12.305549 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6812 01:33:12.312548 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6813 01:33:12.315476 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6814 01:33:12.318969 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6815 01:33:12.322225 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6816 01:33:12.328960 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6817 01:33:12.332492 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6818 01:33:12.335274 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6819 01:33:12.338712 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6820 01:33:12.345368 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6821 01:33:12.348730 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6822 01:33:12.351733 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6823 01:33:12.355070 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6824 01:33:12.362009 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6825 01:33:12.362616 ==
6826 01:33:12.364790 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 01:33:12.368301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 01:33:12.368763 ==
6829 01:33:12.369124 DQS Delay:
6830 01:33:12.371660 DQS0 = 43, DQS1 = 51
6831 01:33:12.372121 DQM Delay:
6832 01:33:12.374861 DQM0 = 12, DQM1 = 14
6833 01:33:12.375321 DQ Delay:
6834 01:33:12.377983 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6835 01:33:12.381635 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6836 01:33:12.385132 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6837 01:33:12.388140 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6838 01:33:12.388555
6839 01:33:12.388884
6840 01:33:12.389186 ==
6841 01:33:12.391282 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 01:33:12.394685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 01:33:12.395201 ==
6844 01:33:12.398498
6845 01:33:12.399008
6846 01:33:12.399341 TX Vref Scan disable
6847 01:33:12.401507 == TX Byte 0 ==
6848 01:33:12.404804 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6849 01:33:12.407672 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6850 01:33:12.411315 == TX Byte 1 ==
6851 01:33:12.414659 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6852 01:33:12.417572 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6853 01:33:12.417990 ==
6854 01:33:12.421196 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 01:33:12.427345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 01:33:12.427763 ==
6857 01:33:12.428099
6858 01:33:12.428406
6859 01:33:12.428700 TX Vref Scan disable
6860 01:33:12.430892 == TX Byte 0 ==
6861 01:33:12.434201 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6862 01:33:12.437494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6863 01:33:12.440962 == TX Byte 1 ==
6864 01:33:12.444116 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6865 01:33:12.447773 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6866 01:33:12.448287
6867 01:33:12.450825 [DATLAT]
6868 01:33:12.451341 Freq=400, CH1 RK0
6869 01:33:12.451675
6870 01:33:12.454239 DATLAT Default: 0xf
6871 01:33:12.454745 0, 0xFFFF, sum = 0
6872 01:33:12.457421 1, 0xFFFF, sum = 0
6873 01:33:12.458071 2, 0xFFFF, sum = 0
6874 01:33:12.460508 3, 0xFFFF, sum = 0
6875 01:33:12.460926 4, 0xFFFF, sum = 0
6876 01:33:12.464252 5, 0xFFFF, sum = 0
6877 01:33:12.464673 6, 0xFFFF, sum = 0
6878 01:33:12.467162 7, 0xFFFF, sum = 0
6879 01:33:12.470425 8, 0xFFFF, sum = 0
6880 01:33:12.470847 9, 0xFFFF, sum = 0
6881 01:33:12.473642 10, 0xFFFF, sum = 0
6882 01:33:12.474062 11, 0xFFFF, sum = 0
6883 01:33:12.476926 12, 0xFFFF, sum = 0
6884 01:33:12.477432 13, 0x0, sum = 1
6885 01:33:12.480154 14, 0x0, sum = 2
6886 01:33:12.480578 15, 0x0, sum = 3
6887 01:33:12.483449 16, 0x0, sum = 4
6888 01:33:12.483904 best_step = 14
6889 01:33:12.484242
6890 01:33:12.484550 ==
6891 01:33:12.486862 Dram Type= 6, Freq= 0, CH_1, rank 0
6892 01:33:12.490212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 01:33:12.493506 ==
6894 01:33:12.494038 RX Vref Scan: 1
6895 01:33:12.494431
6896 01:33:12.497027 RX Vref 0 -> 0, step: 1
6897 01:33:12.497442
6898 01:33:12.500203 RX Delay -343 -> 252, step: 8
6899 01:33:12.500618
6900 01:33:12.503352 Set Vref, RX VrefLevel [Byte0]: 52
6901 01:33:12.506773 [Byte1]: 54
6902 01:33:12.507194
6903 01:33:12.510227 Final RX Vref Byte 0 = 52 to rank0
6904 01:33:12.513436 Final RX Vref Byte 1 = 54 to rank0
6905 01:33:12.516739 Final RX Vref Byte 0 = 52 to rank1
6906 01:33:12.520046 Final RX Vref Byte 1 = 54 to rank1==
6907 01:33:12.523154 Dram Type= 6, Freq= 0, CH_1, rank 0
6908 01:33:12.526187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 01:33:12.526607 ==
6910 01:33:12.529767 DQS Delay:
6911 01:33:12.530304 DQS0 = 44, DQS1 = 56
6912 01:33:12.532886 DQM Delay:
6913 01:33:12.533396 DQM0 = 7, DQM1 = 12
6914 01:33:12.536501 DQ Delay:
6915 01:33:12.536915 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6916 01:33:12.539610 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6917 01:33:12.542790 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6918 01:33:12.546615 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6919 01:33:12.547127
6920 01:33:12.547491
6921 01:33:12.556120 [DQSOSCAuto] RK0, (LSB)MR18= 0x9168, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6922 01:33:12.559044 CH1 RK0: MR19=C0C, MR18=9168
6923 01:33:12.565999 CH1_RK0: MR19=0xC0C, MR18=0x9168, DQSOSC=391, MR23=63, INC=386, DEC=257
6924 01:33:12.566695 ==
6925 01:33:12.569083 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 01:33:12.572349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 01:33:12.572816 ==
6928 01:33:12.575958 [Gating] SW mode calibration
6929 01:33:12.581961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6930 01:33:12.585713 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6931 01:33:12.592578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6932 01:33:12.596193 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6933 01:33:12.598745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6934 01:33:12.605490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6935 01:33:12.608881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6936 01:33:12.612199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6937 01:33:12.618862 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6938 01:33:12.622038 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6939 01:33:12.625287 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6940 01:33:12.628473 Total UI for P1: 0, mck2ui 16
6941 01:33:12.632187 best dqsien dly found for B0: ( 0, 14, 24)
6942 01:33:12.635282 Total UI for P1: 0, mck2ui 16
6943 01:33:12.638546 best dqsien dly found for B1: ( 0, 14, 24)
6944 01:33:12.641833 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6945 01:33:12.648164 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6946 01:33:12.648716
6947 01:33:12.652551 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6948 01:33:12.654774 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6949 01:33:12.658449 [Gating] SW calibration Done
6950 01:33:12.659013 ==
6951 01:33:12.662049 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 01:33:12.665320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 01:33:12.665879 ==
6954 01:33:12.668264 RX Vref Scan: 0
6955 01:33:12.668825
6956 01:33:12.669280 RX Vref 0 -> 0, step: 1
6957 01:33:12.669640
6958 01:33:12.671655 RX Delay -410 -> 252, step: 16
6959 01:33:12.674549 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6960 01:33:12.681204 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6961 01:33:12.684815 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6962 01:33:12.688005 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6963 01:33:12.691688 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6964 01:33:12.697845 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6965 01:33:12.701202 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6966 01:33:12.705128 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6967 01:33:12.708135 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6968 01:33:12.714235 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6969 01:33:12.717491 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6970 01:33:12.720761 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6971 01:33:12.727634 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6972 01:33:12.730750 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6973 01:33:12.734699 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6974 01:33:12.737119 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6975 01:33:12.740554 ==
6976 01:33:12.744160 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 01:33:12.747339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 01:33:12.747907 ==
6979 01:33:12.748356 DQS Delay:
6980 01:33:12.750382 DQS0 = 43, DQS1 = 51
6981 01:33:12.750837 DQM Delay:
6982 01:33:12.753840 DQM0 = 12, DQM1 = 14
6983 01:33:12.754321 DQ Delay:
6984 01:33:12.757688 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6985 01:33:12.760231 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6986 01:33:12.763903 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6987 01:33:12.766994 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6988 01:33:12.767494
6989 01:33:12.768062
6990 01:33:12.768421 ==
6991 01:33:12.770542 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 01:33:12.773566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 01:33:12.774028 ==
6994 01:33:12.774450
6995 01:33:12.774795
6996 01:33:12.777338 TX Vref Scan disable
6997 01:33:12.777810 == TX Byte 0 ==
6998 01:33:12.783822 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6999 01:33:12.786985 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7000 01:33:12.787451 == TX Byte 1 ==
7001 01:33:12.793615 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
7002 01:33:12.796790 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
7003 01:33:12.797273 ==
7004 01:33:12.800233 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 01:33:12.803338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 01:33:12.803898 ==
7007 01:33:12.804267
7008 01:33:12.804602
7009 01:33:12.806475 TX Vref Scan disable
7010 01:33:12.806935 == TX Byte 0 ==
7011 01:33:12.813508 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7012 01:33:12.816819 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7013 01:33:12.817434 == TX Byte 1 ==
7014 01:33:12.823431 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
7015 01:33:12.826444 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
7016 01:33:12.826910
7017 01:33:12.827272 [DATLAT]
7018 01:33:12.829726 Freq=400, CH1 RK1
7019 01:33:12.830215
7020 01:33:12.830585 DATLAT Default: 0xe
7021 01:33:12.832967 0, 0xFFFF, sum = 0
7022 01:33:12.833434 1, 0xFFFF, sum = 0
7023 01:33:12.836032 2, 0xFFFF, sum = 0
7024 01:33:12.836503 3, 0xFFFF, sum = 0
7025 01:33:12.839436 4, 0xFFFF, sum = 0
7026 01:33:12.840082 5, 0xFFFF, sum = 0
7027 01:33:12.842672 6, 0xFFFF, sum = 0
7028 01:33:12.845922 7, 0xFFFF, sum = 0
7029 01:33:12.846375 8, 0xFFFF, sum = 0
7030 01:33:12.849425 9, 0xFFFF, sum = 0
7031 01:33:12.850070 10, 0xFFFF, sum = 0
7032 01:33:12.852597 11, 0xFFFF, sum = 0
7033 01:33:12.853061 12, 0xFFFF, sum = 0
7034 01:33:12.856325 13, 0x0, sum = 1
7035 01:33:12.856890 14, 0x0, sum = 2
7036 01:33:12.859853 15, 0x0, sum = 3
7037 01:33:12.860419 16, 0x0, sum = 4
7038 01:33:12.862327 best_step = 14
7039 01:33:12.862787
7040 01:33:12.863151 ==
7041 01:33:12.866027 Dram Type= 6, Freq= 0, CH_1, rank 1
7042 01:33:12.869174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7043 01:33:12.869640 ==
7044 01:33:12.870008 RX Vref Scan: 0
7045 01:33:12.872294
7046 01:33:12.872748 RX Vref 0 -> 0, step: 1
7047 01:33:12.873112
7048 01:33:12.875881 RX Delay -343 -> 252, step: 8
7049 01:33:12.883436 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7050 01:33:12.886233 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7051 01:33:12.889472 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
7052 01:33:12.896315 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7053 01:33:12.899176 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7054 01:33:12.903113 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7055 01:33:12.906130 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7056 01:33:12.913181 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7057 01:33:12.916098 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7058 01:33:12.919305 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7059 01:33:12.922795 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7060 01:33:12.929413 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7061 01:33:12.932645 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7062 01:33:12.935774 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7063 01:33:12.942441 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7064 01:33:12.945649 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7065 01:33:12.946132 ==
7066 01:33:12.948980 Dram Type= 6, Freq= 0, CH_1, rank 1
7067 01:33:12.952511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7068 01:33:12.953082 ==
7069 01:33:12.955297 DQS Delay:
7070 01:33:12.955758 DQS0 = 48, DQS1 = 56
7071 01:33:12.956121 DQM Delay:
7072 01:33:12.959073 DQM0 = 11, DQM1 = 11
7073 01:33:12.959636 DQ Delay:
7074 01:33:12.962542 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7075 01:33:12.965590 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7076 01:33:12.968983 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7077 01:33:12.972694 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7078 01:33:12.973159
7079 01:33:12.973525
7080 01:33:12.982102 [DQSOSCAuto] RK1, (LSB)MR18= 0x6051, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7081 01:33:12.982716 CH1 RK1: MR19=C0C, MR18=6051
7082 01:33:12.988392 CH1_RK1: MR19=0xC0C, MR18=0x6051, DQSOSC=397, MR23=63, INC=374, DEC=249
7083 01:33:12.991799 [RxdqsGatingPostProcess] freq 400
7084 01:33:12.998516 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7085 01:33:13.002131 best DQS0 dly(2T, 0.5T) = (0, 10)
7086 01:33:13.005095 best DQS1 dly(2T, 0.5T) = (0, 10)
7087 01:33:13.008388 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7088 01:33:13.011579 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7089 01:33:13.014986 best DQS0 dly(2T, 0.5T) = (0, 10)
7090 01:33:13.015554 best DQS1 dly(2T, 0.5T) = (0, 10)
7091 01:33:13.018469 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7092 01:33:13.021394 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7093 01:33:13.024952 Pre-setting of DQS Precalculation
7094 01:33:13.031716 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7095 01:33:13.037716 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7096 01:33:13.044740 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7097 01:33:13.045361
7098 01:33:13.045736
7099 01:33:13.048114 [Calibration Summary] 800 Mbps
7100 01:33:13.051092 CH 0, Rank 0
7101 01:33:13.051719 SW Impedance : PASS
7102 01:33:13.054634 DUTY Scan : NO K
7103 01:33:13.057762 ZQ Calibration : PASS
7104 01:33:13.058358 Jitter Meter : NO K
7105 01:33:13.060923 CBT Training : PASS
7106 01:33:13.061385 Write leveling : PASS
7107 01:33:13.064460 RX DQS gating : PASS
7108 01:33:13.067996 RX DQ/DQS(RDDQC) : PASS
7109 01:33:13.068457 TX DQ/DQS : PASS
7110 01:33:13.070781 RX DATLAT : PASS
7111 01:33:13.073909 RX DQ/DQS(Engine): PASS
7112 01:33:13.074421 TX OE : NO K
7113 01:33:13.077721 All Pass.
7114 01:33:13.078352
7115 01:33:13.078738 CH 0, Rank 1
7116 01:33:13.080778 SW Impedance : PASS
7117 01:33:13.081237 DUTY Scan : NO K
7118 01:33:13.084249 ZQ Calibration : PASS
7119 01:33:13.087716 Jitter Meter : NO K
7120 01:33:13.088281 CBT Training : PASS
7121 01:33:13.090568 Write leveling : NO K
7122 01:33:13.094130 RX DQS gating : PASS
7123 01:33:13.094731 RX DQ/DQS(RDDQC) : PASS
7124 01:33:13.097546 TX DQ/DQS : PASS
7125 01:33:13.100739 RX DATLAT : PASS
7126 01:33:13.101297 RX DQ/DQS(Engine): PASS
7127 01:33:13.103801 TX OE : NO K
7128 01:33:13.104265 All Pass.
7129 01:33:13.104633
7130 01:33:13.107258 CH 1, Rank 0
7131 01:33:13.107732 SW Impedance : PASS
7132 01:33:13.110477 DUTY Scan : NO K
7133 01:33:13.114093 ZQ Calibration : PASS
7134 01:33:13.114596 Jitter Meter : NO K
7135 01:33:13.117236 CBT Training : PASS
7136 01:33:13.120291 Write leveling : PASS
7137 01:33:13.120752 RX DQS gating : PASS
7138 01:33:13.123711 RX DQ/DQS(RDDQC) : PASS
7139 01:33:13.126919 TX DQ/DQS : PASS
7140 01:33:13.127382 RX DATLAT : PASS
7141 01:33:13.130130 RX DQ/DQS(Engine): PASS
7142 01:33:13.134156 TX OE : NO K
7143 01:33:13.134727 All Pass.
7144 01:33:13.135062
7145 01:33:13.135414 CH 1, Rank 1
7146 01:33:13.136741 SW Impedance : PASS
7147 01:33:13.140026 DUTY Scan : NO K
7148 01:33:13.140447 ZQ Calibration : PASS
7149 01:33:13.143284 Jitter Meter : NO K
7150 01:33:13.143705 CBT Training : PASS
7151 01:33:13.146871 Write leveling : NO K
7152 01:33:13.150049 RX DQS gating : PASS
7153 01:33:13.150596 RX DQ/DQS(RDDQC) : PASS
7154 01:33:13.153192 TX DQ/DQS : PASS
7155 01:33:13.156469 RX DATLAT : PASS
7156 01:33:13.156987 RX DQ/DQS(Engine): PASS
7157 01:33:13.159756 TX OE : NO K
7158 01:33:13.160313 All Pass.
7159 01:33:13.160713
7160 01:33:13.162825 DramC Write-DBI off
7161 01:33:13.165908 PER_BANK_REFRESH: Hybrid Mode
7162 01:33:13.166370 TX_TRACKING: ON
7163 01:33:13.176273 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7164 01:33:13.179373 [FAST_K] Save calibration result to emmc
7165 01:33:13.182708 dramc_set_vcore_voltage set vcore to 725000
7166 01:33:13.186098 Read voltage for 1600, 0
7167 01:33:13.186657 Vio18 = 0
7168 01:33:13.189145 Vcore = 725000
7169 01:33:13.189565 Vdram = 0
7170 01:33:13.189931 Vddq = 0
7171 01:33:13.190391 Vmddr = 0
7172 01:33:13.195546 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7173 01:33:13.202423 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7174 01:33:13.202951 MEM_TYPE=3, freq_sel=13
7175 01:33:13.205517 sv_algorithm_assistance_LP4_3733
7176 01:33:13.212510 ============ PULL DRAM RESETB DOWN ============
7177 01:33:13.215711 ========== PULL DRAM RESETB DOWN end =========
7178 01:33:13.219024 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 01:33:13.222079 ===================================
7180 01:33:13.225458 LPDDR4 DRAM CONFIGURATION
7181 01:33:13.228947 ===================================
7182 01:33:13.229469 EX_ROW_EN[0] = 0x0
7183 01:33:13.232301 EX_ROW_EN[1] = 0x0
7184 01:33:13.235368 LP4Y_EN = 0x0
7185 01:33:13.235862 WORK_FSP = 0x1
7186 01:33:13.238752 WL = 0x5
7187 01:33:13.239251 RL = 0x5
7188 01:33:13.242220 BL = 0x2
7189 01:33:13.242641 RPST = 0x0
7190 01:33:13.245682 RD_PRE = 0x0
7191 01:33:13.246123 WR_PRE = 0x1
7192 01:33:13.248882 WR_PST = 0x1
7193 01:33:13.249299 DBI_WR = 0x0
7194 01:33:13.251848 DBI_RD = 0x0
7195 01:33:13.252265 OTF = 0x1
7196 01:33:13.255699 ===================================
7197 01:33:13.258408 ===================================
7198 01:33:13.261842 ANA top config
7199 01:33:13.265289 ===================================
7200 01:33:13.265751 DLL_ASYNC_EN = 0
7201 01:33:13.268546 ALL_SLAVE_EN = 0
7202 01:33:13.271563 NEW_RANK_MODE = 1
7203 01:33:13.274808 DLL_IDLE_MODE = 1
7204 01:33:13.278289 LP45_APHY_COMB_EN = 1
7205 01:33:13.278753 TX_ODT_DIS = 0
7206 01:33:13.281834 NEW_8X_MODE = 1
7207 01:33:13.284994 ===================================
7208 01:33:13.288450 ===================================
7209 01:33:13.291480 data_rate = 3200
7210 01:33:13.294872 CKR = 1
7211 01:33:13.298477 DQ_P2S_RATIO = 8
7212 01:33:13.301496 ===================================
7213 01:33:13.305105 CA_P2S_RATIO = 8
7214 01:33:13.305646 DQ_CA_OPEN = 0
7215 01:33:13.307976 DQ_SEMI_OPEN = 0
7216 01:33:13.311380 CA_SEMI_OPEN = 0
7217 01:33:13.314700 CA_FULL_RATE = 0
7218 01:33:13.317769 DQ_CKDIV4_EN = 0
7219 01:33:13.321186 CA_CKDIV4_EN = 0
7220 01:33:13.321732 CA_PREDIV_EN = 0
7221 01:33:13.324503 PH8_DLY = 12
7222 01:33:13.327551 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7223 01:33:13.330938 DQ_AAMCK_DIV = 4
7224 01:33:13.334621 CA_AAMCK_DIV = 4
7225 01:33:13.337558 CA_ADMCK_DIV = 4
7226 01:33:13.341264 DQ_TRACK_CA_EN = 0
7227 01:33:13.341882 CA_PICK = 1600
7228 01:33:13.344232 CA_MCKIO = 1600
7229 01:33:13.347311 MCKIO_SEMI = 0
7230 01:33:13.350607 PLL_FREQ = 3068
7231 01:33:13.353910 DQ_UI_PI_RATIO = 32
7232 01:33:13.357281 CA_UI_PI_RATIO = 0
7233 01:33:13.360589 ===================================
7234 01:33:13.363890 ===================================
7235 01:33:13.366992 memory_type:LPDDR4
7236 01:33:13.367451 GP_NUM : 10
7237 01:33:13.370440 SRAM_EN : 1
7238 01:33:13.370915 MD32_EN : 0
7239 01:33:13.373695 ===================================
7240 01:33:13.376981 [ANA_INIT] >>>>>>>>>>>>>>
7241 01:33:13.380379 <<<<<< [CONFIGURE PHASE]: ANA_TX
7242 01:33:13.383549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7243 01:33:13.386960 ===================================
7244 01:33:13.390054 data_rate = 3200,PCW = 0X7600
7245 01:33:13.393207 ===================================
7246 01:33:13.397177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7247 01:33:13.403033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7248 01:33:13.406542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7249 01:33:13.413400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7250 01:33:13.416985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7251 01:33:13.419879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7252 01:33:13.420450 [ANA_INIT] flow start
7253 01:33:13.423244 [ANA_INIT] PLL >>>>>>>>
7254 01:33:13.426531 [ANA_INIT] PLL <<<<<<<<
7255 01:33:13.426952 [ANA_INIT] MIDPI >>>>>>>>
7256 01:33:13.429563 [ANA_INIT] MIDPI <<<<<<<<
7257 01:33:13.432790 [ANA_INIT] DLL >>>>>>>>
7258 01:33:13.436224 [ANA_INIT] DLL <<<<<<<<
7259 01:33:13.436657 [ANA_INIT] flow end
7260 01:33:13.439392 ============ LP4 DIFF to SE enter ============
7261 01:33:13.446508 ============ LP4 DIFF to SE exit ============
7262 01:33:13.446946 [ANA_INIT] <<<<<<<<<<<<<
7263 01:33:13.449647 [Flow] Enable top DCM control >>>>>
7264 01:33:13.452949 [Flow] Enable top DCM control <<<<<
7265 01:33:13.455684 Enable DLL master slave shuffle
7266 01:33:13.462683 ==============================================================
7267 01:33:13.463118 Gating Mode config
7268 01:33:13.468972 ==============================================================
7269 01:33:13.472309 Config description:
7270 01:33:13.482411 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7271 01:33:13.488887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7272 01:33:13.492503 SELPH_MODE 0: By rank 1: By Phase
7273 01:33:13.499531 ==============================================================
7274 01:33:13.502290 GAT_TRACK_EN = 1
7275 01:33:13.505257 RX_GATING_MODE = 2
7276 01:33:13.508512 RX_GATING_TRACK_MODE = 2
7277 01:33:13.508931 SELPH_MODE = 1
7278 01:33:13.512165 PICG_EARLY_EN = 1
7279 01:33:13.515715 VALID_LAT_VALUE = 1
7280 01:33:13.521924 ==============================================================
7281 01:33:13.525097 Enter into Gating configuration >>>>
7282 01:33:13.529290 Exit from Gating configuration <<<<
7283 01:33:13.531764 Enter into DVFS_PRE_config >>>>>
7284 01:33:13.541354 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7285 01:33:13.545215 Exit from DVFS_PRE_config <<<<<
7286 01:33:13.548376 Enter into PICG configuration >>>>
7287 01:33:13.551615 Exit from PICG configuration <<<<
7288 01:33:13.555038 [RX_INPUT] configuration >>>>>
7289 01:33:13.558257 [RX_INPUT] configuration <<<<<
7290 01:33:13.561714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7291 01:33:13.568193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7292 01:33:13.574397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7293 01:33:13.581387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7294 01:33:13.587978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7295 01:33:13.594221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7296 01:33:13.597722 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7297 01:33:13.601280 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7298 01:33:13.604559 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7299 01:33:13.610914 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7300 01:33:13.614104 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7301 01:33:13.617528 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7302 01:33:13.620818 ===================================
7303 01:33:13.624052 LPDDR4 DRAM CONFIGURATION
7304 01:33:13.626907 ===================================
7305 01:33:13.627405 EX_ROW_EN[0] = 0x0
7306 01:33:13.630397 EX_ROW_EN[1] = 0x0
7307 01:33:13.634259 LP4Y_EN = 0x0
7308 01:33:13.634769 WORK_FSP = 0x1
7309 01:33:13.637335 WL = 0x5
7310 01:33:13.637857 RL = 0x5
7311 01:33:13.641218 BL = 0x2
7312 01:33:13.641728 RPST = 0x0
7313 01:33:13.643707 RD_PRE = 0x0
7314 01:33:13.644238 WR_PRE = 0x1
7315 01:33:13.647010 WR_PST = 0x1
7316 01:33:13.647545 DBI_WR = 0x0
7317 01:33:13.650293 DBI_RD = 0x0
7318 01:33:13.650802 OTF = 0x1
7319 01:33:13.653571 ===================================
7320 01:33:13.657216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7321 01:33:13.663495 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7322 01:33:13.667457 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7323 01:33:13.669901 ===================================
7324 01:33:13.673166 LPDDR4 DRAM CONFIGURATION
7325 01:33:13.676612 ===================================
7326 01:33:13.679704 EX_ROW_EN[0] = 0x10
7327 01:33:13.680124 EX_ROW_EN[1] = 0x0
7328 01:33:13.683297 LP4Y_EN = 0x0
7329 01:33:13.683810 WORK_FSP = 0x1
7330 01:33:13.686591 WL = 0x5
7331 01:33:13.687102 RL = 0x5
7332 01:33:13.689592 BL = 0x2
7333 01:33:13.690101 RPST = 0x0
7334 01:33:13.693178 RD_PRE = 0x0
7335 01:33:13.693595 WR_PRE = 0x1
7336 01:33:13.696324 WR_PST = 0x1
7337 01:33:13.696839 DBI_WR = 0x0
7338 01:33:13.699276 DBI_RD = 0x0
7339 01:33:13.699699 OTF = 0x1
7340 01:33:13.702721 ===================================
7341 01:33:13.709847 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7342 01:33:13.710296 ==
7343 01:33:13.712857 Dram Type= 6, Freq= 0, CH_0, rank 0
7344 01:33:13.719337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 01:33:13.719859 ==
7346 01:33:13.720198 [Duty_Offset_Calibration]
7347 01:33:13.722533 B0:1 B1:-1 CA:0
7348 01:33:13.722951
7349 01:33:13.725885 [DutyScan_Calibration_Flow] k_type=0
7350 01:33:13.735629
7351 01:33:13.736189 ==CLK 0==
7352 01:33:13.738960 Final CLK duty delay cell = 0
7353 01:33:13.742082 [0] MAX Duty = 5124%(X100), DQS PI = 22
7354 01:33:13.745721 [0] MIN Duty = 4907%(X100), DQS PI = 4
7355 01:33:13.746328 [0] AVG Duty = 5015%(X100)
7356 01:33:13.748463
7357 01:33:13.752024 CH0 CLK Duty spec in!! Max-Min= 217%
7358 01:33:13.755483 [DutyScan_Calibration_Flow] ====Done====
7359 01:33:13.755947
7360 01:33:13.758574 [DutyScan_Calibration_Flow] k_type=1
7361 01:33:13.774320
7362 01:33:13.774740 ==DQS 0 ==
7363 01:33:13.777994 Final DQS duty delay cell = -4
7364 01:33:13.780914 [-4] MAX Duty = 4969%(X100), DQS PI = 16
7365 01:33:13.784408 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7366 01:33:13.787717 [-4] AVG Duty = 4906%(X100)
7367 01:33:13.788223
7368 01:33:13.788556 ==DQS 1 ==
7369 01:33:13.791076 Final DQS duty delay cell = 0
7370 01:33:13.794012 [0] MAX Duty = 5156%(X100), DQS PI = 2
7371 01:33:13.797929 [0] MIN Duty = 5031%(X100), DQS PI = 16
7372 01:33:13.801180 [0] AVG Duty = 5093%(X100)
7373 01:33:13.801687
7374 01:33:13.804322 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7375 01:33:13.804828
7376 01:33:13.807639 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7377 01:33:13.810809 [DutyScan_Calibration_Flow] ====Done====
7378 01:33:13.811227
7379 01:33:13.814029 [DutyScan_Calibration_Flow] k_type=3
7380 01:33:13.832173
7381 01:33:13.832732 ==DQM 0 ==
7382 01:33:13.835216 Final DQM duty delay cell = 0
7383 01:33:13.838438 [0] MAX Duty = 5093%(X100), DQS PI = 20
7384 01:33:13.841602 [0] MIN Duty = 4876%(X100), DQS PI = 10
7385 01:33:13.845280 [0] AVG Duty = 4984%(X100)
7386 01:33:13.845857
7387 01:33:13.846268 ==DQM 1 ==
7388 01:33:13.848715 Final DQM duty delay cell = 0
7389 01:33:13.851727 [0] MAX Duty = 5000%(X100), DQS PI = 4
7390 01:33:13.855153 [0] MIN Duty = 4782%(X100), DQS PI = 20
7391 01:33:13.858669 [0] AVG Duty = 4891%(X100)
7392 01:33:13.859129
7393 01:33:13.861919 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7394 01:33:13.862508
7395 01:33:13.864859 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7396 01:33:13.868169 [DutyScan_Calibration_Flow] ====Done====
7397 01:33:13.868736
7398 01:33:13.871316 [DutyScan_Calibration_Flow] k_type=2
7399 01:33:13.888213
7400 01:33:13.888791 ==DQ 0 ==
7401 01:33:13.891548 Final DQ duty delay cell = -4
7402 01:33:13.894879 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7403 01:33:13.898685 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7404 01:33:13.901620 [-4] AVG Duty = 4953%(X100)
7405 01:33:13.902196
7406 01:33:13.902564 ==DQ 1 ==
7407 01:33:13.904363 Final DQ duty delay cell = 0
7408 01:33:13.908265 [0] MAX Duty = 5125%(X100), DQS PI = 48
7409 01:33:13.911481 [0] MIN Duty = 5000%(X100), DQS PI = 34
7410 01:33:13.915134 [0] AVG Duty = 5062%(X100)
7411 01:33:13.915689
7412 01:33:13.918019 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7413 01:33:13.918503
7414 01:33:13.921485 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7415 01:33:13.924356 [DutyScan_Calibration_Flow] ====Done====
7416 01:33:13.924822 ==
7417 01:33:13.927621 Dram Type= 6, Freq= 0, CH_1, rank 0
7418 01:33:13.931301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7419 01:33:13.931930 ==
7420 01:33:13.934149 [Duty_Offset_Calibration]
7421 01:33:13.934654 B0:-1 B1:1 CA:1
7422 01:33:13.937648
7423 01:33:13.941235 [DutyScan_Calibration_Flow] k_type=0
7424 01:33:13.949330
7425 01:33:13.949889 ==CLK 0==
7426 01:33:13.952814 Final CLK duty delay cell = 0
7427 01:33:13.955532 [0] MAX Duty = 5187%(X100), DQS PI = 22
7428 01:33:13.959028 [0] MIN Duty = 5000%(X100), DQS PI = 0
7429 01:33:13.962464 [0] AVG Duty = 5093%(X100)
7430 01:33:13.963026
7431 01:33:13.965721 CH1 CLK Duty spec in!! Max-Min= 187%
7432 01:33:13.968635 [DutyScan_Calibration_Flow] ====Done====
7433 01:33:13.969098
7434 01:33:13.971972 [DutyScan_Calibration_Flow] k_type=1
7435 01:33:13.988699
7436 01:33:13.989259 ==DQS 0 ==
7437 01:33:13.991787 Final DQS duty delay cell = 0
7438 01:33:13.995444 [0] MAX Duty = 5124%(X100), DQS PI = 18
7439 01:33:13.998598 [0] MIN Duty = 4907%(X100), DQS PI = 8
7440 01:33:14.002184 [0] AVG Duty = 5015%(X100)
7441 01:33:14.002757
7442 01:33:14.003125 ==DQS 1 ==
7443 01:33:14.005187 Final DQS duty delay cell = 0
7444 01:33:14.008869 [0] MAX Duty = 5093%(X100), DQS PI = 28
7445 01:33:14.011616 [0] MIN Duty = 4969%(X100), DQS PI = 56
7446 01:33:14.015567 [0] AVG Duty = 5031%(X100)
7447 01:33:14.016143
7448 01:33:14.018533 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7449 01:33:14.019105
7450 01:33:14.021543 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7451 01:33:14.025128 [DutyScan_Calibration_Flow] ====Done====
7452 01:33:14.025686
7453 01:33:14.027914 [DutyScan_Calibration_Flow] k_type=3
7454 01:33:14.045816
7455 01:33:14.046464 ==DQM 0 ==
7456 01:33:14.048899 Final DQM duty delay cell = 0
7457 01:33:14.052237 [0] MAX Duty = 5218%(X100), DQS PI = 18
7458 01:33:14.055279 [0] MIN Duty = 5031%(X100), DQS PI = 8
7459 01:33:14.058803 [0] AVG Duty = 5124%(X100)
7460 01:33:14.059366
7461 01:33:14.059732 ==DQM 1 ==
7462 01:33:14.061905 Final DQM duty delay cell = 0
7463 01:33:14.065336 [0] MAX Duty = 5125%(X100), DQS PI = 2
7464 01:33:14.068196 [0] MIN Duty = 4938%(X100), DQS PI = 34
7465 01:33:14.071621 [0] AVG Duty = 5031%(X100)
7466 01:33:14.072083
7467 01:33:14.075229 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7468 01:33:14.075711
7469 01:33:14.078630 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7470 01:33:14.081671 [DutyScan_Calibration_Flow] ====Done====
7471 01:33:14.082271
7472 01:33:14.085351 [DutyScan_Calibration_Flow] k_type=2
7473 01:33:14.102325
7474 01:33:14.102870 ==DQ 0 ==
7475 01:33:14.105668 Final DQ duty delay cell = 0
7476 01:33:14.109048 [0] MAX Duty = 5187%(X100), DQS PI = 32
7477 01:33:14.112294 [0] MIN Duty = 4906%(X100), DQS PI = 8
7478 01:33:14.112850 [0] AVG Duty = 5046%(X100)
7479 01:33:14.115295
7480 01:33:14.115750 ==DQ 1 ==
7481 01:33:14.119118 Final DQ duty delay cell = 0
7482 01:33:14.122336 [0] MAX Duty = 5156%(X100), DQS PI = 10
7483 01:33:14.125290 [0] MIN Duty = 4969%(X100), DQS PI = 32
7484 01:33:14.125839 [0] AVG Duty = 5062%(X100)
7485 01:33:14.128546
7486 01:33:14.133059 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7487 01:33:14.133677
7488 01:33:14.135256 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7489 01:33:14.138600 [DutyScan_Calibration_Flow] ====Done====
7490 01:33:14.141860 nWR fixed to 30
7491 01:33:14.145273 [ModeRegInit_LP4] CH0 RK0
7492 01:33:14.145826 [ModeRegInit_LP4] CH0 RK1
7493 01:33:14.148570 [ModeRegInit_LP4] CH1 RK0
7494 01:33:14.151526 [ModeRegInit_LP4] CH1 RK1
7495 01:33:14.151979 match AC timing 5
7496 01:33:14.158234 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7497 01:33:14.161363 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7498 01:33:14.165227 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7499 01:33:14.171553 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7500 01:33:14.174898 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7501 01:33:14.175401 [MiockJmeterHQA]
7502 01:33:14.175790
7503 01:33:14.177887 [DramcMiockJmeter] u1RxGatingPI = 0
7504 01:33:14.181435 0 : 4253, 4026
7505 01:33:14.181894 4 : 4252, 4027
7506 01:33:14.185021 8 : 4252, 4027
7507 01:33:14.185585 12 : 4252, 4027
7508 01:33:14.188366 16 : 4252, 4027
7509 01:33:14.188927 20 : 4363, 4138
7510 01:33:14.189298 24 : 4252, 4027
7511 01:33:14.191375 28 : 4362, 4137
7512 01:33:14.191937 32 : 4252, 4027
7513 01:33:14.194544 36 : 4252, 4027
7514 01:33:14.195168 40 : 4252, 4026
7515 01:33:14.197686 44 : 4255, 4029
7516 01:33:14.198248 48 : 4363, 4138
7517 01:33:14.201535 52 : 4252, 4027
7518 01:33:14.202099 56 : 4363, 4137
7519 01:33:14.202537 60 : 4252, 4029
7520 01:33:14.204752 64 : 4250, 4027
7521 01:33:14.205347 68 : 4250, 4027
7522 01:33:14.207897 72 : 4361, 4137
7523 01:33:14.208457 76 : 4250, 4027
7524 01:33:14.210705 80 : 4361, 4138
7525 01:33:14.211174 84 : 4252, 4027
7526 01:33:14.214278 88 : 4250, 4027
7527 01:33:14.214739 92 : 4250, 526
7528 01:33:14.215105 96 : 4360, 0
7529 01:33:14.217637 100 : 4253, 0
7530 01:33:14.218435 104 : 4253, 0
7531 01:33:14.220752 108 : 4249, 0
7532 01:33:14.221212 112 : 4253, 0
7533 01:33:14.221575 116 : 4363, 0
7534 01:33:14.224251 120 : 4361, 0
7535 01:33:14.224813 124 : 4249, 0
7536 01:33:14.227717 128 : 4253, 0
7537 01:33:14.228177 132 : 4361, 0
7538 01:33:14.228541 136 : 4250, 0
7539 01:33:14.230570 140 : 4250, 0
7540 01:33:14.231034 144 : 4250, 0
7541 01:33:14.231401 148 : 4250, 0
7542 01:33:14.234757 152 : 4250, 0
7543 01:33:14.235319 156 : 4250, 0
7544 01:33:14.237315 160 : 4250, 0
7545 01:33:14.237876 164 : 4250, 0
7546 01:33:14.238304 168 : 4360, 0
7547 01:33:14.240869 172 : 4361, 0
7548 01:33:14.241429 176 : 4250, 0
7549 01:33:14.243742 180 : 4250, 0
7550 01:33:14.244203 184 : 4361, 0
7551 01:33:14.244568 188 : 4250, 0
7552 01:33:14.246838 192 : 4250, 0
7553 01:33:14.247299 196 : 4250, 0
7554 01:33:14.250514 200 : 4250, 0
7555 01:33:14.251068 204 : 4250, 0
7556 01:33:14.251451 208 : 4252, 0
7557 01:33:14.253609 212 : 4250, 0
7558 01:33:14.254071 216 : 4249, 0
7559 01:33:14.257083 220 : 4360, 0
7560 01:33:14.257641 224 : 4361, 13
7561 01:33:14.258007 228 : 4250, 2994
7562 01:33:14.260121 232 : 4250, 4027
7563 01:33:14.260578 236 : 4361, 4137
7564 01:33:14.263620 240 : 4361, 4138
7565 01:33:14.264184 244 : 4250, 4027
7566 01:33:14.266826 248 : 4363, 4140
7567 01:33:14.267382 252 : 4249, 4027
7568 01:33:14.270344 256 : 4250, 4026
7569 01:33:14.270914 260 : 4250, 4027
7570 01:33:14.273392 264 : 4252, 4029
7571 01:33:14.273854 268 : 4250, 4027
7572 01:33:14.276521 272 : 4250, 4026
7573 01:33:14.276982 276 : 4250, 4027
7574 01:33:14.279910 280 : 4252, 4029
7575 01:33:14.280372 284 : 4249, 4027
7576 01:33:14.283296 288 : 4360, 4137
7577 01:33:14.283857 292 : 4361, 4137
7578 01:33:14.284228 296 : 4250, 4027
7579 01:33:14.286616 300 : 4363, 4140
7580 01:33:14.287076 304 : 4250, 4027
7581 01:33:14.289880 308 : 4250, 4026
7582 01:33:14.290379 312 : 4250, 4027
7583 01:33:14.293070 316 : 4252, 4029
7584 01:33:14.293624 320 : 4249, 4027
7585 01:33:14.296746 324 : 4252, 4029
7586 01:33:14.297303 328 : 4250, 4027
7587 01:33:14.299909 332 : 4252, 4030
7588 01:33:14.300516 336 : 4249, 3998
7589 01:33:14.303387 340 : 4361, 2368
7590 01:33:14.303963 344 : 4361, 106
7591 01:33:14.304336
7592 01:33:14.306461 MIOCK jitter meter ch=0
7593 01:33:14.306913
7594 01:33:14.309719 1T = (344-92) = 252 dly cells
7595 01:33:14.312721 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7596 01:33:14.316377 ==
7597 01:33:14.319334 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 01:33:14.323131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 01:33:14.323812 ==
7600 01:33:14.326116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7601 01:33:14.332536 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7602 01:33:14.335470 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7603 01:33:14.342242 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7604 01:33:14.350976 [CA 0] Center 43 (13~74) winsize 62
7605 01:33:14.354329 [CA 1] Center 43 (13~74) winsize 62
7606 01:33:14.358216 [CA 2] Center 39 (10~69) winsize 60
7607 01:33:14.361479 [CA 3] Center 39 (10~69) winsize 60
7608 01:33:14.364191 [CA 4] Center 37 (8~67) winsize 60
7609 01:33:14.367677 [CA 5] Center 36 (7~66) winsize 60
7610 01:33:14.368235
7611 01:33:14.370604 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7612 01:33:14.371059
7613 01:33:14.377494 [CATrainingPosCal] consider 1 rank data
7614 01:33:14.378025 u2DelayCellTimex100 = 258/100 ps
7615 01:33:14.384323 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7616 01:33:14.387324 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7617 01:33:14.390202 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7618 01:33:14.393904 CA3 delay=39 (10~69),Diff = 3 PI (11 cell)
7619 01:33:14.397080 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7620 01:33:14.400352 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7621 01:33:14.401022
7622 01:33:14.403549 CA PerBit enable=1, Macro0, CA PI delay=36
7623 01:33:14.404007
7624 01:33:14.406807 [CBTSetCACLKResult] CA Dly = 36
7625 01:33:14.410487 CS Dly: 12 (0~43)
7626 01:33:14.413499 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7627 01:33:14.416898 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7628 01:33:14.417458 ==
7629 01:33:14.420046 Dram Type= 6, Freq= 0, CH_0, rank 1
7630 01:33:14.426850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 01:33:14.427411 ==
7632 01:33:14.430134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7633 01:33:14.436808 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7634 01:33:14.439772 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7635 01:33:14.446848 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7636 01:33:14.454852 [CA 0] Center 42 (12~73) winsize 62
7637 01:33:14.458204 [CA 1] Center 43 (13~73) winsize 61
7638 01:33:14.461050 [CA 2] Center 37 (8~67) winsize 60
7639 01:33:14.464791 [CA 3] Center 37 (7~67) winsize 61
7640 01:33:14.468162 [CA 4] Center 36 (6~66) winsize 61
7641 01:33:14.471203 [CA 5] Center 35 (5~66) winsize 62
7642 01:33:14.471828
7643 01:33:14.474626 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7644 01:33:14.475085
7645 01:33:14.477772 [CATrainingPosCal] consider 2 rank data
7646 01:33:14.480910 u2DelayCellTimex100 = 258/100 ps
7647 01:33:14.487576 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7648 01:33:14.491144 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7649 01:33:14.494353 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7650 01:33:14.497808 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7651 01:33:14.500896 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7652 01:33:14.504522 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7653 01:33:14.505076
7654 01:33:14.507543 CA PerBit enable=1, Macro0, CA PI delay=36
7655 01:33:14.508094
7656 01:33:14.510619 [CBTSetCACLKResult] CA Dly = 36
7657 01:33:14.513836 CS Dly: 12 (0~43)
7658 01:33:14.517524 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7659 01:33:14.521596 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7660 01:33:14.522148
7661 01:33:14.524156 ----->DramcWriteLeveling(PI) begin...
7662 01:33:14.524615 ==
7663 01:33:14.527473 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 01:33:14.534217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 01:33:14.534787 ==
7666 01:33:14.537033 Write leveling (Byte 0): 36 => 36
7667 01:33:14.540642 Write leveling (Byte 1): 29 => 29
7668 01:33:14.541197 DramcWriteLeveling(PI) end<-----
7669 01:33:14.543607
7670 01:33:14.544070 ==
7671 01:33:14.547219 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 01:33:14.550568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 01:33:14.551120 ==
7674 01:33:14.553349 [Gating] SW mode calibration
7675 01:33:14.560045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7676 01:33:14.563773 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7677 01:33:14.570871 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7678 01:33:14.573374 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 01:33:14.576805 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 01:33:14.583442 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7681 01:33:14.586564 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7682 01:33:14.589940 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7683 01:33:14.596461 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7684 01:33:14.600016 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7685 01:33:14.603242 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7686 01:33:14.609593 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7687 01:33:14.612697 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7688 01:33:14.615994 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7689 01:33:14.622743 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7690 01:33:14.626035 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7691 01:33:14.629510 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7692 01:33:14.636506 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7693 01:33:14.639223 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7694 01:33:14.642357 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7695 01:33:14.649530 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7696 01:33:14.652462 1 6 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7697 01:33:14.656156 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7698 01:33:14.662569 1 6 20 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7699 01:33:14.665699 1 6 24 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
7700 01:33:14.669111 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7701 01:33:14.675315 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7702 01:33:14.679065 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7703 01:33:14.682485 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7704 01:33:14.688768 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7705 01:33:14.692139 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7706 01:33:14.695539 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7707 01:33:14.701787 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7708 01:33:14.705291 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 01:33:14.709352 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 01:33:14.715181 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 01:33:14.718327 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 01:33:14.725334 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 01:33:14.728014 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 01:33:14.731517 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 01:33:14.738294 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 01:33:14.741153 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 01:33:14.744640 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 01:33:14.751384 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7719 01:33:14.754498 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7720 01:33:14.757739 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7721 01:33:14.764076 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7722 01:33:14.764890 Total UI for P1: 0, mck2ui 16
7723 01:33:14.771354 best dqsien dly found for B0: ( 1, 9, 10)
7724 01:33:14.774240 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7725 01:33:14.777494 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7726 01:33:14.781002 Total UI for P1: 0, mck2ui 16
7727 01:33:14.784217 best dqsien dly found for B1: ( 1, 9, 20)
7728 01:33:14.787396 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7729 01:33:14.790502 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7730 01:33:14.790919
7731 01:33:14.797150 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7732 01:33:14.801015 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7733 01:33:14.801549 [Gating] SW calibration Done
7734 01:33:14.803902 ==
7735 01:33:14.807028 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 01:33:14.810547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 01:33:14.811074 ==
7738 01:33:14.811414 RX Vref Scan: 0
7739 01:33:14.811740
7740 01:33:14.813463 RX Vref 0 -> 0, step: 1
7741 01:33:14.813879
7742 01:33:14.817049 RX Delay 0 -> 252, step: 8
7743 01:33:14.820410 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7744 01:33:14.823682 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7745 01:33:14.826868 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7746 01:33:14.833835 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7747 01:33:14.836772 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7748 01:33:14.839965 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7749 01:33:14.843378 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7750 01:33:14.846543 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7751 01:33:14.853380 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7752 01:33:14.856651 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7753 01:33:14.860279 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7754 01:33:14.863419 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7755 01:33:14.869807 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7756 01:33:14.873467 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7757 01:33:14.876982 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7758 01:33:14.879470 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7759 01:33:14.880177 ==
7760 01:33:14.882935 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 01:33:14.889859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 01:33:14.890505 ==
7763 01:33:14.890995 DQS Delay:
7764 01:33:14.892724 DQS0 = 0, DQS1 = 0
7765 01:33:14.893195 DQM Delay:
7766 01:33:14.893670 DQM0 = 135, DQM1 = 126
7767 01:33:14.896044 DQ Delay:
7768 01:33:14.899277 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7769 01:33:14.902440 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7770 01:33:14.906044 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7771 01:33:14.909267 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7772 01:33:14.909817
7773 01:33:14.910235
7774 01:33:14.910591 ==
7775 01:33:14.912612 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 01:33:14.919302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 01:33:14.919864 ==
7778 01:33:14.920285
7779 01:33:14.920627
7780 01:33:14.920951 TX Vref Scan disable
7781 01:33:14.922233 == TX Byte 0 ==
7782 01:33:14.926110 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7783 01:33:14.932562 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7784 01:33:14.933123 == TX Byte 1 ==
7785 01:33:14.935970 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7786 01:33:14.942682 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7787 01:33:14.943270 ==
7788 01:33:14.945594 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 01:33:14.948930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 01:33:14.949484 ==
7791 01:33:14.961692
7792 01:33:14.965082 TX Vref early break, caculate TX vref
7793 01:33:14.968325 TX Vref=16, minBit 4, minWin=22, winSum=372
7794 01:33:14.971453 TX Vref=18, minBit 4, minWin=22, winSum=382
7795 01:33:14.974836 TX Vref=20, minBit 4, minWin=23, winSum=394
7796 01:33:14.978316 TX Vref=22, minBit 3, minWin=24, winSum=403
7797 01:33:14.981293 TX Vref=24, minBit 3, minWin=24, winSum=412
7798 01:33:14.987973 TX Vref=26, minBit 4, minWin=24, winSum=418
7799 01:33:14.991226 TX Vref=28, minBit 0, minWin=25, winSum=419
7800 01:33:14.994912 TX Vref=30, minBit 0, minWin=24, winSum=411
7801 01:33:14.998235 TX Vref=32, minBit 5, minWin=23, winSum=400
7802 01:33:15.001437 TX Vref=34, minBit 4, minWin=23, winSum=394
7803 01:33:15.008081 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7804 01:33:15.008638
7805 01:33:15.011149 Final TX Range 0 Vref 28
7806 01:33:15.011612
7807 01:33:15.012002 ==
7808 01:33:15.014385 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 01:33:15.017804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 01:33:15.018319 ==
7811 01:33:15.018695
7812 01:33:15.019033
7813 01:33:15.021366 TX Vref Scan disable
7814 01:33:15.027953 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7815 01:33:15.028507 == TX Byte 0 ==
7816 01:33:15.031333 u2DelayCellOfst[0]=18 cells (5 PI)
7817 01:33:15.034483 u2DelayCellOfst[1]=18 cells (5 PI)
7818 01:33:15.037698 u2DelayCellOfst[2]=15 cells (4 PI)
7819 01:33:15.040893 u2DelayCellOfst[3]=15 cells (4 PI)
7820 01:33:15.044108 u2DelayCellOfst[4]=11 cells (3 PI)
7821 01:33:15.047701 u2DelayCellOfst[5]=0 cells (0 PI)
7822 01:33:15.050732 u2DelayCellOfst[6]=18 cells (5 PI)
7823 01:33:15.054297 u2DelayCellOfst[7]=22 cells (6 PI)
7824 01:33:15.057833 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7825 01:33:15.060526 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7826 01:33:15.064383 == TX Byte 1 ==
7827 01:33:15.067560 u2DelayCellOfst[8]=0 cells (0 PI)
7828 01:33:15.070834 u2DelayCellOfst[9]=3 cells (1 PI)
7829 01:33:15.074351 u2DelayCellOfst[10]=7 cells (2 PI)
7830 01:33:15.074909 u2DelayCellOfst[11]=3 cells (1 PI)
7831 01:33:15.076948 u2DelayCellOfst[12]=15 cells (4 PI)
7832 01:33:15.080570 u2DelayCellOfst[13]=15 cells (4 PI)
7833 01:33:15.083882 u2DelayCellOfst[14]=15 cells (4 PI)
7834 01:33:15.086878 u2DelayCellOfst[15]=11 cells (3 PI)
7835 01:33:15.093791 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7836 01:33:15.097213 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7837 01:33:15.097767 DramC Write-DBI on
7838 01:33:15.100304 ==
7839 01:33:15.100772 Dram Type= 6, Freq= 0, CH_0, rank 0
7840 01:33:15.106649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7841 01:33:15.107191 ==
7842 01:33:15.107553
7843 01:33:15.107886
7844 01:33:15.109895 TX Vref Scan disable
7845 01:33:15.110509 == TX Byte 0 ==
7846 01:33:15.116361 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7847 01:33:15.116822 == TX Byte 1 ==
7848 01:33:15.120229 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7849 01:33:15.123038 DramC Write-DBI off
7850 01:33:15.123498
7851 01:33:15.123859 [DATLAT]
7852 01:33:15.126427 Freq=1600, CH0 RK0
7853 01:33:15.126882
7854 01:33:15.127240 DATLAT Default: 0xf
7855 01:33:15.129994 0, 0xFFFF, sum = 0
7856 01:33:15.130498 1, 0xFFFF, sum = 0
7857 01:33:15.133339 2, 0xFFFF, sum = 0
7858 01:33:15.133917 3, 0xFFFF, sum = 0
7859 01:33:15.136261 4, 0xFFFF, sum = 0
7860 01:33:15.139707 5, 0xFFFF, sum = 0
7861 01:33:15.140270 6, 0xFFFF, sum = 0
7862 01:33:15.142828 7, 0xFFFF, sum = 0
7863 01:33:15.143356 8, 0xFFFF, sum = 0
7864 01:33:15.146433 9, 0xFFFF, sum = 0
7865 01:33:15.146992 10, 0xFFFF, sum = 0
7866 01:33:15.149380 11, 0xFFFF, sum = 0
7867 01:33:15.149949 12, 0xFFFF, sum = 0
7868 01:33:15.152659 13, 0xFFFF, sum = 0
7869 01:33:15.153123 14, 0x0, sum = 1
7870 01:33:15.155980 15, 0x0, sum = 2
7871 01:33:15.156446 16, 0x0, sum = 3
7872 01:33:15.159356 17, 0x0, sum = 4
7873 01:33:15.159996 best_step = 15
7874 01:33:15.160372
7875 01:33:15.160710 ==
7876 01:33:15.162547 Dram Type= 6, Freq= 0, CH_0, rank 0
7877 01:33:15.169197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7878 01:33:15.169765 ==
7879 01:33:15.170134 RX Vref Scan: 1
7880 01:33:15.170521
7881 01:33:15.172672 Set Vref Range= 24 -> 127
7882 01:33:15.173217
7883 01:33:15.176095 RX Vref 24 -> 127, step: 1
7884 01:33:15.176648
7885 01:33:15.177011 RX Delay 19 -> 252, step: 4
7886 01:33:15.177352
7887 01:33:15.179249 Set Vref, RX VrefLevel [Byte0]: 24
7888 01:33:15.182086 [Byte1]: 24
7889 01:33:15.186753
7890 01:33:15.187308 Set Vref, RX VrefLevel [Byte0]: 25
7891 01:33:15.189485 [Byte1]: 25
7892 01:33:15.194107
7893 01:33:15.194721 Set Vref, RX VrefLevel [Byte0]: 26
7894 01:33:15.197229 [Byte1]: 26
7895 01:33:15.201827
7896 01:33:15.202330 Set Vref, RX VrefLevel [Byte0]: 27
7897 01:33:15.204913 [Byte1]: 27
7898 01:33:15.209818
7899 01:33:15.210432 Set Vref, RX VrefLevel [Byte0]: 28
7900 01:33:15.212400 [Byte1]: 28
7901 01:33:15.216767
7902 01:33:15.217221 Set Vref, RX VrefLevel [Byte0]: 29
7903 01:33:15.220163 [Byte1]: 29
7904 01:33:15.224716
7905 01:33:15.225266 Set Vref, RX VrefLevel [Byte0]: 30
7906 01:33:15.227962 [Byte1]: 30
7907 01:33:15.231852
7908 01:33:15.232408 Set Vref, RX VrefLevel [Byte0]: 31
7909 01:33:15.235138 [Byte1]: 31
7910 01:33:15.239349
7911 01:33:15.242859 Set Vref, RX VrefLevel [Byte0]: 32
7912 01:33:15.243411 [Byte1]: 32
7913 01:33:15.247373
7914 01:33:15.247929 Set Vref, RX VrefLevel [Byte0]: 33
7915 01:33:15.250766 [Byte1]: 33
7916 01:33:15.254605
7917 01:33:15.255160 Set Vref, RX VrefLevel [Byte0]: 34
7918 01:33:15.257960 [Byte1]: 34
7919 01:33:15.262127
7920 01:33:15.262719 Set Vref, RX VrefLevel [Byte0]: 35
7921 01:33:15.265337 [Byte1]: 35
7922 01:33:15.269734
7923 01:33:15.270407 Set Vref, RX VrefLevel [Byte0]: 36
7924 01:33:15.273216 [Byte1]: 36
7925 01:33:15.277399
7926 01:33:15.278146 Set Vref, RX VrefLevel [Byte0]: 37
7927 01:33:15.280749 [Byte1]: 37
7928 01:33:15.284845
7929 01:33:15.285297 Set Vref, RX VrefLevel [Byte0]: 38
7930 01:33:15.288028 [Byte1]: 38
7931 01:33:15.292638
7932 01:33:15.293093 Set Vref, RX VrefLevel [Byte0]: 39
7933 01:33:15.295592 [Byte1]: 39
7934 01:33:15.300045
7935 01:33:15.300499 Set Vref, RX VrefLevel [Byte0]: 40
7936 01:33:15.302940 [Byte1]: 40
7937 01:33:15.307729
7938 01:33:15.308275 Set Vref, RX VrefLevel [Byte0]: 41
7939 01:33:15.310939 [Byte1]: 41
7940 01:33:15.315172
7941 01:33:15.315624 Set Vref, RX VrefLevel [Byte0]: 42
7942 01:33:15.318341 [Byte1]: 42
7943 01:33:15.323340
7944 01:33:15.323797 Set Vref, RX VrefLevel [Byte0]: 43
7945 01:33:15.326269 [Byte1]: 43
7946 01:33:15.330518
7947 01:33:15.330926 Set Vref, RX VrefLevel [Byte0]: 44
7948 01:33:15.333885 [Byte1]: 44
7949 01:33:15.337806
7950 01:33:15.341364 Set Vref, RX VrefLevel [Byte0]: 45
7951 01:33:15.344230 [Byte1]: 45
7952 01:33:15.344775
7953 01:33:15.347259 Set Vref, RX VrefLevel [Byte0]: 46
7954 01:33:15.350761 [Byte1]: 46
7955 01:33:15.351220
7956 01:33:15.354599 Set Vref, RX VrefLevel [Byte0]: 47
7957 01:33:15.357628 [Byte1]: 47
7958 01:33:15.358220
7959 01:33:15.361217 Set Vref, RX VrefLevel [Byte0]: 48
7960 01:33:15.363810 [Byte1]: 48
7961 01:33:15.368523
7962 01:33:15.369073 Set Vref, RX VrefLevel [Byte0]: 49
7963 01:33:15.371525 [Byte1]: 49
7964 01:33:15.376091
7965 01:33:15.376643 Set Vref, RX VrefLevel [Byte0]: 50
7966 01:33:15.378902 [Byte1]: 50
7967 01:33:15.383267
7968 01:33:15.383721 Set Vref, RX VrefLevel [Byte0]: 51
7969 01:33:15.386618 [Byte1]: 51
7970 01:33:15.390958
7971 01:33:15.391570 Set Vref, RX VrefLevel [Byte0]: 52
7972 01:33:15.394061 [Byte1]: 52
7973 01:33:15.398248
7974 01:33:15.398702 Set Vref, RX VrefLevel [Byte0]: 53
7975 01:33:15.401814 [Byte1]: 53
7976 01:33:15.406573
7977 01:33:15.407120 Set Vref, RX VrefLevel [Byte0]: 54
7978 01:33:15.409450 [Byte1]: 54
7979 01:33:15.413547
7980 01:33:15.414015 Set Vref, RX VrefLevel [Byte0]: 55
7981 01:33:15.416862 [Byte1]: 55
7982 01:33:15.421011
7983 01:33:15.421585 Set Vref, RX VrefLevel [Byte0]: 56
7984 01:33:15.424691 [Byte1]: 56
7985 01:33:15.428898
7986 01:33:15.429350 Set Vref, RX VrefLevel [Byte0]: 57
7987 01:33:15.431797 [Byte1]: 57
7988 01:33:15.436861
7989 01:33:15.437424 Set Vref, RX VrefLevel [Byte0]: 58
7990 01:33:15.439865 [Byte1]: 58
7991 01:33:15.443710
7992 01:33:15.444165 Set Vref, RX VrefLevel [Byte0]: 59
7993 01:33:15.447058 [Byte1]: 59
7994 01:33:15.451695
7995 01:33:15.452249 Set Vref, RX VrefLevel [Byte0]: 60
7996 01:33:15.455126 [Byte1]: 60
7997 01:33:15.459105
7998 01:33:15.459656 Set Vref, RX VrefLevel [Byte0]: 61
7999 01:33:15.462403 [Byte1]: 61
8000 01:33:15.466515
8001 01:33:15.467060 Set Vref, RX VrefLevel [Byte0]: 62
8002 01:33:15.472979 [Byte1]: 62
8003 01:33:15.473528
8004 01:33:15.476147 Set Vref, RX VrefLevel [Byte0]: 63
8005 01:33:15.479626 [Byte1]: 63
8006 01:33:15.480082
8007 01:33:15.482882 Set Vref, RX VrefLevel [Byte0]: 64
8008 01:33:15.485926 [Byte1]: 64
8009 01:33:15.489530
8010 01:33:15.489981 Set Vref, RX VrefLevel [Byte0]: 65
8011 01:33:15.492536 [Byte1]: 65
8012 01:33:15.496677
8013 01:33:15.497130 Set Vref, RX VrefLevel [Byte0]: 66
8014 01:33:15.499920 [Byte1]: 66
8015 01:33:15.504966
8016 01:33:15.505516 Set Vref, RX VrefLevel [Byte0]: 67
8017 01:33:15.507863 [Byte1]: 67
8018 01:33:15.512232
8019 01:33:15.512776 Set Vref, RX VrefLevel [Byte0]: 68
8020 01:33:15.515475 [Byte1]: 68
8021 01:33:15.520283
8022 01:33:15.520830 Set Vref, RX VrefLevel [Byte0]: 69
8023 01:33:15.523101 [Byte1]: 69
8024 01:33:15.526818
8025 01:33:15.527268 Set Vref, RX VrefLevel [Byte0]: 70
8026 01:33:15.530526 [Byte1]: 70
8027 01:33:15.534592
8028 01:33:15.535076 Set Vref, RX VrefLevel [Byte0]: 71
8029 01:33:15.538050 [Byte1]: 71
8030 01:33:15.542307
8031 01:33:15.542853 Set Vref, RX VrefLevel [Byte0]: 72
8032 01:33:15.545770 [Byte1]: 72
8033 01:33:15.550455
8034 01:33:15.551000 Set Vref, RX VrefLevel [Byte0]: 73
8035 01:33:15.553428 [Byte1]: 73
8036 01:33:15.557515
8037 01:33:15.557971 Set Vref, RX VrefLevel [Byte0]: 74
8038 01:33:15.560649 [Byte1]: 74
8039 01:33:15.564926
8040 01:33:15.565377 Set Vref, RX VrefLevel [Byte0]: 75
8041 01:33:15.568149 [Byte1]: 75
8042 01:33:15.572692
8043 01:33:15.573240 Set Vref, RX VrefLevel [Byte0]: 76
8044 01:33:15.575719 [Byte1]: 76
8045 01:33:15.580185
8046 01:33:15.580637 Set Vref, RX VrefLevel [Byte0]: 77
8047 01:33:15.583573 [Byte1]: 77
8048 01:33:15.587896
8049 01:33:15.588367 Set Vref, RX VrefLevel [Byte0]: 78
8050 01:33:15.590772 [Byte1]: 78
8051 01:33:15.595004
8052 01:33:15.595456 Set Vref, RX VrefLevel [Byte0]: 79
8053 01:33:15.598364 [Byte1]: 79
8054 01:33:15.602704
8055 01:33:15.603255 Final RX Vref Byte 0 = 63 to rank0
8056 01:33:15.606487 Final RX Vref Byte 1 = 60 to rank0
8057 01:33:15.609403 Final RX Vref Byte 0 = 63 to rank1
8058 01:33:15.612918 Final RX Vref Byte 1 = 60 to rank1==
8059 01:33:15.615856 Dram Type= 6, Freq= 0, CH_0, rank 0
8060 01:33:15.622779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 01:33:15.623347 ==
8062 01:33:15.623715 DQS Delay:
8063 01:33:15.626135 DQS0 = 0, DQS1 = 0
8064 01:33:15.626734 DQM Delay:
8065 01:33:15.627100 DQM0 = 133, DQM1 = 123
8066 01:33:15.629221 DQ Delay:
8067 01:33:15.632529 DQ0 =130, DQ1 =134, DQ2 =132, DQ3 =132
8068 01:33:15.635619 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8069 01:33:15.639394 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
8070 01:33:15.642700 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8071 01:33:15.643160
8072 01:33:15.643520
8073 01:33:15.643857
8074 01:33:15.645981 [DramC_TX_OE_Calibration] TA2
8075 01:33:15.648757 Original DQ_B0 (3 6) =30, OEN = 27
8076 01:33:15.653117 Original DQ_B1 (3 6) =30, OEN = 27
8077 01:33:15.655322 24, 0x0, End_B0=24 End_B1=24
8078 01:33:15.658941 25, 0x0, End_B0=25 End_B1=25
8079 01:33:15.659492 26, 0x0, End_B0=26 End_B1=26
8080 01:33:15.662287 27, 0x0, End_B0=27 End_B1=27
8081 01:33:15.665600 28, 0x0, End_B0=28 End_B1=28
8082 01:33:15.668707 29, 0x0, End_B0=29 End_B1=29
8083 01:33:15.669319 30, 0x0, End_B0=30 End_B1=30
8084 01:33:15.671930 31, 0x5151, End_B0=30 End_B1=30
8085 01:33:15.675069 Byte0 end_step=30 best_step=27
8086 01:33:15.678462 Byte1 end_step=30 best_step=27
8087 01:33:15.681710 Byte0 TX OE(2T, 0.5T) = (3, 3)
8088 01:33:15.685176 Byte1 TX OE(2T, 0.5T) = (3, 3)
8089 01:33:15.685635
8090 01:33:15.685999
8091 01:33:15.691857 [DQSOSCAuto] RK0, (LSB)MR18= 0x2012, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8092 01:33:15.695207 CH0 RK0: MR19=303, MR18=2012
8093 01:33:15.701271 CH0_RK0: MR19=0x303, MR18=0x2012, DQSOSC=393, MR23=63, INC=23, DEC=15
8094 01:33:15.701725
8095 01:33:15.705321 ----->DramcWriteLeveling(PI) begin...
8096 01:33:15.705882 ==
8097 01:33:15.708622 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 01:33:15.711426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 01:33:15.711883 ==
8100 01:33:15.714483 Write leveling (Byte 0): 35 => 35
8101 01:33:15.717856 Write leveling (Byte 1): 29 => 29
8102 01:33:15.721410 DramcWriteLeveling(PI) end<-----
8103 01:33:15.721970
8104 01:33:15.722387 ==
8105 01:33:15.724971 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 01:33:15.731245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 01:33:15.731799 ==
8108 01:33:15.732168 [Gating] SW mode calibration
8109 01:33:15.741391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8110 01:33:15.744522 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8111 01:33:15.747617 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 01:33:15.755102 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 01:33:15.758010 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 01:33:15.761070 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 01:33:15.767694 1 4 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8116 01:33:15.770833 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8117 01:33:15.774227 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 01:33:15.781252 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8119 01:33:15.784601 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 01:33:15.787268 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 01:33:15.793850 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8122 01:33:15.797515 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8123 01:33:15.800574 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8124 01:33:15.807887 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8125 01:33:15.810372 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 01:33:15.813953 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 01:33:15.820136 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 01:33:15.823420 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 01:33:15.826768 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 01:33:15.833743 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
8131 01:33:15.836813 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8132 01:33:15.839916 1 6 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
8133 01:33:15.846418 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 01:33:15.849968 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 01:33:15.853035 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 01:33:15.859739 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 01:33:15.863226 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8138 01:33:15.866075 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8139 01:33:15.872804 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8140 01:33:15.875876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8141 01:33:15.879345 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 01:33:15.886225 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 01:33:15.889676 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 01:33:15.892938 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 01:33:15.899529 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 01:33:15.902838 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 01:33:15.906005 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 01:33:15.912362 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 01:33:15.915814 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 01:33:15.919034 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 01:33:15.925966 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 01:33:15.929068 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 01:33:15.932484 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8154 01:33:15.939122 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8155 01:33:15.942360 Total UI for P1: 0, mck2ui 16
8156 01:33:15.945923 best dqsien dly found for B0: ( 1, 9, 8)
8157 01:33:15.948902 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8158 01:33:15.952304 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8159 01:33:15.958929 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8160 01:33:15.962122 Total UI for P1: 0, mck2ui 16
8161 01:33:15.965256 best dqsien dly found for B1: ( 1, 9, 18)
8162 01:33:15.968904 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8163 01:33:15.972203 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8164 01:33:15.972708
8165 01:33:15.975284 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8166 01:33:15.978702 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8167 01:33:15.981766 [Gating] SW calibration Done
8168 01:33:15.982223 ==
8169 01:33:15.985023 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 01:33:15.988229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 01:33:15.988701 ==
8172 01:33:15.991929 RX Vref Scan: 0
8173 01:33:15.992483
8174 01:33:15.995189 RX Vref 0 -> 0, step: 1
8175 01:33:15.995745
8176 01:33:15.996115 RX Delay 0 -> 252, step: 8
8177 01:33:16.001613 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8178 01:33:16.005294 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8179 01:33:16.008754 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8180 01:33:16.011546 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8181 01:33:16.014635 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8182 01:33:16.022215 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8183 01:33:16.024673 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8184 01:33:16.027981 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8185 01:33:16.031680 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8186 01:33:16.034535 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8187 01:33:16.041367 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8188 01:33:16.044704 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8189 01:33:16.047606 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8190 01:33:16.050946 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8191 01:33:16.057636 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8192 01:33:16.060957 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8193 01:33:16.061422 ==
8194 01:33:16.064599 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 01:33:16.067467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 01:33:16.067933 ==
8197 01:33:16.070873 DQS Delay:
8198 01:33:16.071424 DQS0 = 0, DQS1 = 0
8199 01:33:16.071794 DQM Delay:
8200 01:33:16.074336 DQM0 = 132, DQM1 = 129
8201 01:33:16.074884 DQ Delay:
8202 01:33:16.077385 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8203 01:33:16.080799 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8204 01:33:16.084382 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8205 01:33:16.090317 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8206 01:33:16.090777
8207 01:33:16.091134
8208 01:33:16.091463 ==
8209 01:33:16.093792 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 01:33:16.097035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 01:33:16.097492 ==
8212 01:33:16.097853
8213 01:33:16.098241
8214 01:33:16.100771 TX Vref Scan disable
8215 01:33:16.103637 == TX Byte 0 ==
8216 01:33:16.107250 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8217 01:33:16.110451 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8218 01:33:16.113814 == TX Byte 1 ==
8219 01:33:16.116989 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8220 01:33:16.120733 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8221 01:33:16.121283 ==
8222 01:33:16.123669 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 01:33:16.126828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 01:33:16.130748 ==
8225 01:33:16.140800
8226 01:33:16.143648 TX Vref early break, caculate TX vref
8227 01:33:16.146678 TX Vref=16, minBit 1, minWin=22, winSum=375
8228 01:33:16.150487 TX Vref=18, minBit 1, minWin=22, winSum=390
8229 01:33:16.153590 TX Vref=20, minBit 1, minWin=23, winSum=396
8230 01:33:16.157203 TX Vref=22, minBit 1, minWin=23, winSum=404
8231 01:33:16.160242 TX Vref=24, minBit 6, minWin=24, winSum=413
8232 01:33:16.166696 TX Vref=26, minBit 7, minWin=24, winSum=417
8233 01:33:16.170225 TX Vref=28, minBit 1, minWin=23, winSum=413
8234 01:33:16.173570 TX Vref=30, minBit 1, minWin=24, winSum=410
8235 01:33:16.176698 TX Vref=32, minBit 5, minWin=23, winSum=395
8236 01:33:16.183476 [TxChooseVref] Worse bit 7, Min win 24, Win sum 417, Final Vref 26
8237 01:33:16.183941
8238 01:33:16.186313 Final TX Range 0 Vref 26
8239 01:33:16.186773
8240 01:33:16.187138 ==
8241 01:33:16.190026 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 01:33:16.193150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 01:33:16.193705 ==
8244 01:33:16.194065
8245 01:33:16.194466
8246 01:33:16.196559 TX Vref Scan disable
8247 01:33:16.202910 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8248 01:33:16.203452 == TX Byte 0 ==
8249 01:33:16.205961 u2DelayCellOfst[0]=15 cells (4 PI)
8250 01:33:16.209547 u2DelayCellOfst[1]=18 cells (5 PI)
8251 01:33:16.212521 u2DelayCellOfst[2]=15 cells (4 PI)
8252 01:33:16.215956 u2DelayCellOfst[3]=18 cells (5 PI)
8253 01:33:16.219218 u2DelayCellOfst[4]=11 cells (3 PI)
8254 01:33:16.223209 u2DelayCellOfst[5]=0 cells (0 PI)
8255 01:33:16.226032 u2DelayCellOfst[6]=18 cells (5 PI)
8256 01:33:16.229545 u2DelayCellOfst[7]=22 cells (6 PI)
8257 01:33:16.232514 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8258 01:33:16.235868 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8259 01:33:16.239316 == TX Byte 1 ==
8260 01:33:16.242488 u2DelayCellOfst[8]=0 cells (0 PI)
8261 01:33:16.245873 u2DelayCellOfst[9]=3 cells (1 PI)
8262 01:33:16.246382 u2DelayCellOfst[10]=7 cells (2 PI)
8263 01:33:16.248808 u2DelayCellOfst[11]=3 cells (1 PI)
8264 01:33:16.252385 u2DelayCellOfst[12]=15 cells (4 PI)
8265 01:33:16.255771 u2DelayCellOfst[13]=15 cells (4 PI)
8266 01:33:16.258900 u2DelayCellOfst[14]=18 cells (5 PI)
8267 01:33:16.262152 u2DelayCellOfst[15]=15 cells (4 PI)
8268 01:33:16.269078 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8269 01:33:16.272045 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8270 01:33:16.272512 DramC Write-DBI on
8271 01:33:16.272950 ==
8272 01:33:16.275382 Dram Type= 6, Freq= 0, CH_0, rank 1
8273 01:33:16.282060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 01:33:16.282681 ==
8275 01:33:16.283051
8276 01:33:16.283391
8277 01:33:16.283714 TX Vref Scan disable
8278 01:33:16.285842 == TX Byte 0 ==
8279 01:33:16.289373 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8280 01:33:16.292573 == TX Byte 1 ==
8281 01:33:16.296197 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8282 01:33:16.299508 DramC Write-DBI off
8283 01:33:16.300066
8284 01:33:16.300430 [DATLAT]
8285 01:33:16.300766 Freq=1600, CH0 RK1
8286 01:33:16.301088
8287 01:33:16.302549 DATLAT Default: 0xf
8288 01:33:16.305735 0, 0xFFFF, sum = 0
8289 01:33:16.306233 1, 0xFFFF, sum = 0
8290 01:33:16.309560 2, 0xFFFF, sum = 0
8291 01:33:16.310143 3, 0xFFFF, sum = 0
8292 01:33:16.312337 4, 0xFFFF, sum = 0
8293 01:33:16.312804 5, 0xFFFF, sum = 0
8294 01:33:16.315692 6, 0xFFFF, sum = 0
8295 01:33:16.316154 7, 0xFFFF, sum = 0
8296 01:33:16.318746 8, 0xFFFF, sum = 0
8297 01:33:16.319208 9, 0xFFFF, sum = 0
8298 01:33:16.322864 10, 0xFFFF, sum = 0
8299 01:33:16.323426 11, 0xFFFF, sum = 0
8300 01:33:16.325542 12, 0xFFFF, sum = 0
8301 01:33:16.326110 13, 0xFFFF, sum = 0
8302 01:33:16.328794 14, 0x0, sum = 1
8303 01:33:16.329421 15, 0x0, sum = 2
8304 01:33:16.331836 16, 0x0, sum = 3
8305 01:33:16.332297 17, 0x0, sum = 4
8306 01:33:16.335186 best_step = 15
8307 01:33:16.335789
8308 01:33:16.336330 ==
8309 01:33:16.339288 Dram Type= 6, Freq= 0, CH_0, rank 1
8310 01:33:16.342255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 01:33:16.342811 ==
8312 01:33:16.345589 RX Vref Scan: 0
8313 01:33:16.346146
8314 01:33:16.346555 RX Vref 0 -> 0, step: 1
8315 01:33:16.346896
8316 01:33:16.348239 RX Delay 11 -> 252, step: 4
8317 01:33:16.355002 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8318 01:33:16.358562 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8319 01:33:16.361514 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8320 01:33:16.364908 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8321 01:33:16.368571 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8322 01:33:16.374873 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8323 01:33:16.378150 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8324 01:33:16.381563 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8325 01:33:16.384790 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8326 01:33:16.391258 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8327 01:33:16.394688 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8328 01:33:16.397790 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8329 01:33:16.401027 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8330 01:33:16.404451 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8331 01:33:16.410974 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8332 01:33:16.414375 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8333 01:33:16.414859 ==
8334 01:33:16.418063 Dram Type= 6, Freq= 0, CH_0, rank 1
8335 01:33:16.421076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 01:33:16.421637 ==
8337 01:33:16.424003 DQS Delay:
8338 01:33:16.424536 DQS0 = 0, DQS1 = 0
8339 01:33:16.424904 DQM Delay:
8340 01:33:16.427272 DQM0 = 130, DQM1 = 125
8341 01:33:16.427743 DQ Delay:
8342 01:33:16.430912 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8343 01:33:16.434135 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8344 01:33:16.440950 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8345 01:33:16.443897 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8346 01:33:16.444362
8347 01:33:16.444721
8348 01:33:16.445057
8349 01:33:16.447201 [DramC_TX_OE_Calibration] TA2
8350 01:33:16.450748 Original DQ_B0 (3 6) =30, OEN = 27
8351 01:33:16.453987 Original DQ_B1 (3 6) =30, OEN = 27
8352 01:33:16.454615 24, 0x0, End_B0=24 End_B1=24
8353 01:33:16.457275 25, 0x0, End_B0=25 End_B1=25
8354 01:33:16.460643 26, 0x0, End_B0=26 End_B1=26
8355 01:33:16.463778 27, 0x0, End_B0=27 End_B1=27
8356 01:33:16.466781 28, 0x0, End_B0=28 End_B1=28
8357 01:33:16.467250 29, 0x0, End_B0=29 End_B1=29
8358 01:33:16.470410 30, 0x0, End_B0=30 End_B1=30
8359 01:33:16.473278 31, 0x5151, End_B0=30 End_B1=30
8360 01:33:16.476683 Byte0 end_step=30 best_step=27
8361 01:33:16.480040 Byte1 end_step=30 best_step=27
8362 01:33:16.483316 Byte0 TX OE(2T, 0.5T) = (3, 3)
8363 01:33:16.483789 Byte1 TX OE(2T, 0.5T) = (3, 3)
8364 01:33:16.484153
8365 01:33:16.484488
8366 01:33:16.493184 [DQSOSCAuto] RK1, (LSB)MR18= 0x1cff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8367 01:33:16.496793 CH0 RK1: MR19=302, MR18=1CFF
8368 01:33:16.502748 CH0_RK1: MR19=0x302, MR18=0x1CFF, DQSOSC=395, MR23=63, INC=23, DEC=15
8369 01:33:16.506248 [RxdqsGatingPostProcess] freq 1600
8370 01:33:16.509674 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8371 01:33:16.512849 best DQS0 dly(2T, 0.5T) = (1, 1)
8372 01:33:16.516575 best DQS1 dly(2T, 0.5T) = (1, 1)
8373 01:33:16.519387 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8374 01:33:16.522999 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8375 01:33:16.526301 best DQS0 dly(2T, 0.5T) = (1, 1)
8376 01:33:16.529645 best DQS1 dly(2T, 0.5T) = (1, 1)
8377 01:33:16.532815 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8378 01:33:16.536500 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8379 01:33:16.539568 Pre-setting of DQS Precalculation
8380 01:33:16.543076 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8381 01:33:16.543670 ==
8382 01:33:16.545896 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 01:33:16.549274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 01:33:16.549737 ==
8385 01:33:16.556470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8386 01:33:16.559586 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8387 01:33:16.565940 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8388 01:33:16.569528 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8389 01:33:16.579305 [CA 0] Center 41 (12~71) winsize 60
8390 01:33:16.582462 [CA 1] Center 41 (12~71) winsize 60
8391 01:33:16.586333 [CA 2] Center 37 (8~66) winsize 59
8392 01:33:16.589055 [CA 3] Center 36 (7~65) winsize 59
8393 01:33:16.592385 [CA 4] Center 37 (7~67) winsize 61
8394 01:33:16.596024 [CA 5] Center 36 (7~66) winsize 60
8395 01:33:16.596570
8396 01:33:16.598975 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8397 01:33:16.599525
8398 01:33:16.602394 [CATrainingPosCal] consider 1 rank data
8399 01:33:16.606013 u2DelayCellTimex100 = 258/100 ps
8400 01:33:16.609278 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8401 01:33:16.615651 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8402 01:33:16.618999 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8403 01:33:16.622468 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8404 01:33:16.625425 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8405 01:33:16.628559 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8406 01:33:16.629014
8407 01:33:16.632071 CA PerBit enable=1, Macro0, CA PI delay=36
8408 01:33:16.632524
8409 01:33:16.635297 [CBTSetCACLKResult] CA Dly = 36
8410 01:33:16.638635 CS Dly: 9 (0~40)
8411 01:33:16.642285 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8412 01:33:16.645802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8413 01:33:16.646387 ==
8414 01:33:16.648573 Dram Type= 6, Freq= 0, CH_1, rank 1
8415 01:33:16.652059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 01:33:16.655297 ==
8417 01:33:16.658665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8418 01:33:16.661683 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8419 01:33:16.668189 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8420 01:33:16.675104 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8421 01:33:16.682701 [CA 0] Center 43 (14~72) winsize 59
8422 01:33:16.685907 [CA 1] Center 43 (13~73) winsize 61
8423 01:33:16.689209 [CA 2] Center 37 (8~67) winsize 60
8424 01:33:16.692248 [CA 3] Center 37 (7~67) winsize 61
8425 01:33:16.695295 [CA 4] Center 37 (8~67) winsize 60
8426 01:33:16.698908 [CA 5] Center 37 (8~67) winsize 60
8427 01:33:16.699367
8428 01:33:16.702201 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8429 01:33:16.702766
8430 01:33:16.708959 [CATrainingPosCal] consider 2 rank data
8431 01:33:16.709517 u2DelayCellTimex100 = 258/100 ps
8432 01:33:16.715116 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8433 01:33:16.718331 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8434 01:33:16.721692 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8435 01:33:16.725193 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8436 01:33:16.728134 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8437 01:33:16.731474 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8438 01:33:16.731932
8439 01:33:16.734826 CA PerBit enable=1, Macro0, CA PI delay=36
8440 01:33:16.735285
8441 01:33:16.738019 [CBTSetCACLKResult] CA Dly = 36
8442 01:33:16.741467 CS Dly: 11 (0~44)
8443 01:33:16.745007 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8444 01:33:16.747944 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8445 01:33:16.748401
8446 01:33:16.751371 ----->DramcWriteLeveling(PI) begin...
8447 01:33:16.754955 ==
8448 01:33:16.758001 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 01:33:16.761148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 01:33:16.761610 ==
8451 01:33:16.764870 Write leveling (Byte 0): 24 => 24
8452 01:33:16.767683 Write leveling (Byte 1): 29 => 29
8453 01:33:16.771075 DramcWriteLeveling(PI) end<-----
8454 01:33:16.771620
8455 01:33:16.771977 ==
8456 01:33:16.774128 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 01:33:16.777832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 01:33:16.778272 ==
8459 01:33:16.780575 [Gating] SW mode calibration
8460 01:33:16.787138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8461 01:33:16.794122 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8462 01:33:16.796929 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 01:33:16.800608 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 01:33:16.806861 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 01:33:16.810250 1 4 12 | B1->B0 | 2a2a 2f2f | 1 1 | (0 0) (0 0)
8466 01:33:16.813936 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 01:33:16.820175 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 01:33:16.824019 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 01:33:16.826825 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 01:33:16.833431 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 01:33:16.836789 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 01:33:16.840119 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8473 01:33:16.846586 1 5 12 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (1 0)
8474 01:33:16.849711 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 01:33:16.853374 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 01:33:16.859599 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 01:33:16.863091 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 01:33:16.866514 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 01:33:16.873120 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 01:33:16.876471 1 6 8 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
8481 01:33:16.879400 1 6 12 | B1->B0 | 3535 3e3e | 0 1 | (1 1) (0 0)
8482 01:33:16.886053 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 01:33:16.889430 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 01:33:16.892898 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 01:33:16.899972 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 01:33:16.902622 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 01:33:16.906332 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 01:33:16.912842 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8489 01:33:16.915886 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8490 01:33:16.919136 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8491 01:33:16.925836 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 01:33:16.929333 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 01:33:16.932811 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 01:33:16.938747 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 01:33:16.942153 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 01:33:16.946120 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 01:33:16.952282 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 01:33:16.955466 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 01:33:16.958413 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 01:33:16.965261 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 01:33:16.968491 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 01:33:16.971997 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 01:33:16.978389 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 01:33:16.981759 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8505 01:33:16.984819 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8506 01:33:16.991363 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8507 01:33:16.994449 Total UI for P1: 0, mck2ui 16
8508 01:33:16.998479 best dqsien dly found for B0: ( 1, 9, 10)
8509 01:33:16.999034 Total UI for P1: 0, mck2ui 16
8510 01:33:17.004467 best dqsien dly found for B1: ( 1, 9, 10)
8511 01:33:17.008057 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8512 01:33:17.010982 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8513 01:33:17.011770
8514 01:33:17.014756 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8515 01:33:17.017575 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8516 01:33:17.021213 [Gating] SW calibration Done
8517 01:33:17.021963 ==
8518 01:33:17.024128 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 01:33:17.028076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 01:33:17.028536 ==
8521 01:33:17.031416 RX Vref Scan: 0
8522 01:33:17.031968
8523 01:33:17.034316 RX Vref 0 -> 0, step: 1
8524 01:33:17.034777
8525 01:33:17.035139 RX Delay 0 -> 252, step: 8
8526 01:33:17.040992 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8527 01:33:17.043930 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8528 01:33:17.047472 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8529 01:33:17.050757 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8530 01:33:17.054773 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8531 01:33:17.060737 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8532 01:33:17.063668 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8533 01:33:17.067433 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8534 01:33:17.070566 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8535 01:33:17.074115 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8536 01:33:17.080159 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8537 01:33:17.084025 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8538 01:33:17.086954 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8539 01:33:17.090016 iDelay=208, Bit 13, Center 135 (72 ~ 199) 128
8540 01:33:17.096727 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8541 01:33:17.099925 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8542 01:33:17.100341 ==
8543 01:33:17.103556 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 01:33:17.106544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 01:33:17.106963 ==
8546 01:33:17.109707 DQS Delay:
8547 01:33:17.110403 DQS0 = 0, DQS1 = 0
8548 01:33:17.110787 DQM Delay:
8549 01:33:17.113007 DQM0 = 137, DQM1 = 128
8550 01:33:17.113830 DQ Delay:
8551 01:33:17.116536 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8552 01:33:17.119839 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8553 01:33:17.126629 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8554 01:33:17.129444 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8555 01:33:17.129995
8556 01:33:17.130509
8557 01:33:17.130954 ==
8558 01:33:17.132724 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 01:33:17.136279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 01:33:17.136696 ==
8561 01:33:17.137062
8562 01:33:17.137378
8563 01:33:17.139300 TX Vref Scan disable
8564 01:33:17.142395 == TX Byte 0 ==
8565 01:33:17.146120 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8566 01:33:17.149234 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8567 01:33:17.152988 == TX Byte 1 ==
8568 01:33:17.155641 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8569 01:33:17.159262 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8570 01:33:17.159681 ==
8571 01:33:17.162588 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 01:33:17.166149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 01:33:17.168818 ==
8574 01:33:17.180246
8575 01:33:17.183607 TX Vref early break, caculate TX vref
8576 01:33:17.186664 TX Vref=16, minBit 0, minWin=22, winSum=372
8577 01:33:17.190442 TX Vref=18, minBit 0, minWin=22, winSum=381
8578 01:33:17.193524 TX Vref=20, minBit 6, minWin=23, winSum=391
8579 01:33:17.196988 TX Vref=22, minBit 0, minWin=24, winSum=400
8580 01:33:17.199995 TX Vref=24, minBit 0, minWin=25, winSum=412
8581 01:33:17.206596 TX Vref=26, minBit 1, minWin=25, winSum=414
8582 01:33:17.209676 TX Vref=28, minBit 0, minWin=25, winSum=422
8583 01:33:17.213349 TX Vref=30, minBit 0, minWin=24, winSum=410
8584 01:33:17.216499 TX Vref=32, minBit 1, minWin=24, winSum=401
8585 01:33:17.219955 TX Vref=34, minBit 0, minWin=23, winSum=390
8586 01:33:17.226511 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8587 01:33:17.227077
8588 01:33:17.229590 Final TX Range 0 Vref 28
8589 01:33:17.230144
8590 01:33:17.230529 ==
8591 01:33:17.232690 Dram Type= 6, Freq= 0, CH_1, rank 0
8592 01:33:17.236292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8593 01:33:17.236710 ==
8594 01:33:17.237035
8595 01:33:17.237341
8596 01:33:17.239635 TX Vref Scan disable
8597 01:33:17.245968 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8598 01:33:17.246429 == TX Byte 0 ==
8599 01:33:17.249413 u2DelayCellOfst[0]=18 cells (5 PI)
8600 01:33:17.252823 u2DelayCellOfst[1]=15 cells (4 PI)
8601 01:33:17.256172 u2DelayCellOfst[2]=0 cells (0 PI)
8602 01:33:17.259017 u2DelayCellOfst[3]=3 cells (1 PI)
8603 01:33:17.262749 u2DelayCellOfst[4]=7 cells (2 PI)
8604 01:33:17.265854 u2DelayCellOfst[5]=22 cells (6 PI)
8605 01:33:17.269032 u2DelayCellOfst[6]=22 cells (6 PI)
8606 01:33:17.272646 u2DelayCellOfst[7]=7 cells (2 PI)
8607 01:33:17.275985 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8608 01:33:17.279035 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8609 01:33:17.282519 == TX Byte 1 ==
8610 01:33:17.285616 u2DelayCellOfst[8]=0 cells (0 PI)
8611 01:33:17.288867 u2DelayCellOfst[9]=3 cells (1 PI)
8612 01:33:17.292314 u2DelayCellOfst[10]=11 cells (3 PI)
8613 01:33:17.292729 u2DelayCellOfst[11]=7 cells (2 PI)
8614 01:33:17.296038 u2DelayCellOfst[12]=15 cells (4 PI)
8615 01:33:17.298738 u2DelayCellOfst[13]=18 cells (5 PI)
8616 01:33:17.302230 u2DelayCellOfst[14]=22 cells (6 PI)
8617 01:33:17.305566 u2DelayCellOfst[15]=18 cells (5 PI)
8618 01:33:17.312026 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8619 01:33:17.315252 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8620 01:33:17.318265 DramC Write-DBI on
8621 01:33:17.318679 ==
8622 01:33:17.321601 Dram Type= 6, Freq= 0, CH_1, rank 0
8623 01:33:17.325319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8624 01:33:17.325737 ==
8625 01:33:17.326064
8626 01:33:17.326420
8627 01:33:17.328656 TX Vref Scan disable
8628 01:33:17.329165 == TX Byte 0 ==
8629 01:33:17.334806 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8630 01:33:17.335232 == TX Byte 1 ==
8631 01:33:17.338133 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8632 01:33:17.341568 DramC Write-DBI off
8633 01:33:17.342113
8634 01:33:17.342626 [DATLAT]
8635 01:33:17.344474 Freq=1600, CH1 RK0
8636 01:33:17.345203
8637 01:33:17.345768 DATLAT Default: 0xf
8638 01:33:17.347959 0, 0xFFFF, sum = 0
8639 01:33:17.351434 1, 0xFFFF, sum = 0
8640 01:33:17.351876 2, 0xFFFF, sum = 0
8641 01:33:17.354292 3, 0xFFFF, sum = 0
8642 01:33:17.354709 4, 0xFFFF, sum = 0
8643 01:33:17.358309 5, 0xFFFF, sum = 0
8644 01:33:17.358825 6, 0xFFFF, sum = 0
8645 01:33:17.361184 7, 0xFFFF, sum = 0
8646 01:33:17.361621 8, 0xFFFF, sum = 0
8647 01:33:17.364317 9, 0xFFFF, sum = 0
8648 01:33:17.364738 10, 0xFFFF, sum = 0
8649 01:33:17.368117 11, 0xFFFF, sum = 0
8650 01:33:17.368634 12, 0xFFFF, sum = 0
8651 01:33:17.371128 13, 0xFFFF, sum = 0
8652 01:33:17.371864 14, 0x0, sum = 1
8653 01:33:17.373936 15, 0x0, sum = 2
8654 01:33:17.374427 16, 0x0, sum = 3
8655 01:33:17.377525 17, 0x0, sum = 4
8656 01:33:17.378121 best_step = 15
8657 01:33:17.378823
8658 01:33:17.379379 ==
8659 01:33:17.380692 Dram Type= 6, Freq= 0, CH_1, rank 0
8660 01:33:17.387523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8661 01:33:17.388033 ==
8662 01:33:17.388362 RX Vref Scan: 1
8663 01:33:17.388737
8664 01:33:17.390748 Set Vref Range= 24 -> 127
8665 01:33:17.391162
8666 01:33:17.393809 RX Vref 24 -> 127, step: 1
8667 01:33:17.394279
8668 01:33:17.394635 RX Delay 11 -> 252, step: 4
8669 01:33:17.396971
8670 01:33:17.397379 Set Vref, RX VrefLevel [Byte0]: 24
8671 01:33:17.400494 [Byte1]: 24
8672 01:33:17.404725
8673 01:33:17.405131 Set Vref, RX VrefLevel [Byte0]: 25
8674 01:33:17.408463 [Byte1]: 25
8675 01:33:17.412543
8676 01:33:17.412950 Set Vref, RX VrefLevel [Byte0]: 26
8677 01:33:17.415678 [Byte1]: 26
8678 01:33:17.420148
8679 01:33:17.420656 Set Vref, RX VrefLevel [Byte0]: 27
8680 01:33:17.423669 [Byte1]: 27
8681 01:33:17.428116
8682 01:33:17.428624 Set Vref, RX VrefLevel [Byte0]: 28
8683 01:33:17.430992 [Byte1]: 28
8684 01:33:17.435442
8685 01:33:17.435853 Set Vref, RX VrefLevel [Byte0]: 29
8686 01:33:17.438637 [Byte1]: 29
8687 01:33:17.443102
8688 01:33:17.443639 Set Vref, RX VrefLevel [Byte0]: 30
8689 01:33:17.446152 [Byte1]: 30
8690 01:33:17.450413
8691 01:33:17.450823 Set Vref, RX VrefLevel [Byte0]: 31
8692 01:33:17.453617 [Byte1]: 31
8693 01:33:17.458433
8694 01:33:17.459000 Set Vref, RX VrefLevel [Byte0]: 32
8695 01:33:17.462312 [Byte1]: 32
8696 01:33:17.465633
8697 01:33:17.466089 Set Vref, RX VrefLevel [Byte0]: 33
8698 01:33:17.468768 [Byte1]: 33
8699 01:33:17.473734
8700 01:33:17.474347 Set Vref, RX VrefLevel [Byte0]: 34
8701 01:33:17.476489 [Byte1]: 34
8702 01:33:17.480934
8703 01:33:17.481496 Set Vref, RX VrefLevel [Byte0]: 35
8704 01:33:17.484553 [Byte1]: 35
8705 01:33:17.488647
8706 01:33:17.489173 Set Vref, RX VrefLevel [Byte0]: 36
8707 01:33:17.491837 [Byte1]: 36
8708 01:33:17.496436
8709 01:33:17.496998 Set Vref, RX VrefLevel [Byte0]: 37
8710 01:33:17.499577 [Byte1]: 37
8711 01:33:17.503886
8712 01:33:17.504364 Set Vref, RX VrefLevel [Byte0]: 38
8713 01:33:17.507365 [Byte1]: 38
8714 01:33:17.511865
8715 01:33:17.512421 Set Vref, RX VrefLevel [Byte0]: 39
8716 01:33:17.515027 [Byte1]: 39
8717 01:33:17.519271
8718 01:33:17.519833 Set Vref, RX VrefLevel [Byte0]: 40
8719 01:33:17.522310 [Byte1]: 40
8720 01:33:17.526845
8721 01:33:17.527406 Set Vref, RX VrefLevel [Byte0]: 41
8722 01:33:17.530348 [Byte1]: 41
8723 01:33:17.534633
8724 01:33:17.535233 Set Vref, RX VrefLevel [Byte0]: 42
8725 01:33:17.537494 [Byte1]: 42
8726 01:33:17.541800
8727 01:33:17.542410 Set Vref, RX VrefLevel [Byte0]: 43
8728 01:33:17.545423 [Byte1]: 43
8729 01:33:17.549729
8730 01:33:17.550324 Set Vref, RX VrefLevel [Byte0]: 44
8731 01:33:17.552824 [Byte1]: 44
8732 01:33:17.557242
8733 01:33:17.557800 Set Vref, RX VrefLevel [Byte0]: 45
8734 01:33:17.560354 [Byte1]: 45
8735 01:33:17.564684
8736 01:33:17.565262 Set Vref, RX VrefLevel [Byte0]: 46
8737 01:33:17.568184 [Byte1]: 46
8738 01:33:17.572513
8739 01:33:17.573070 Set Vref, RX VrefLevel [Byte0]: 47
8740 01:33:17.575719 [Byte1]: 47
8741 01:33:17.580372
8742 01:33:17.580933 Set Vref, RX VrefLevel [Byte0]: 48
8743 01:33:17.583326 [Byte1]: 48
8744 01:33:17.587258
8745 01:33:17.587710 Set Vref, RX VrefLevel [Byte0]: 49
8746 01:33:17.591039 [Byte1]: 49
8747 01:33:17.595192
8748 01:33:17.595642 Set Vref, RX VrefLevel [Byte0]: 50
8749 01:33:17.598530 [Byte1]: 50
8750 01:33:17.603023
8751 01:33:17.603659 Set Vref, RX VrefLevel [Byte0]: 51
8752 01:33:17.605884 [Byte1]: 51
8753 01:33:17.610577
8754 01:33:17.611124 Set Vref, RX VrefLevel [Byte0]: 52
8755 01:33:17.614058 [Byte1]: 52
8756 01:33:17.617990
8757 01:33:17.618592 Set Vref, RX VrefLevel [Byte0]: 53
8758 01:33:17.621776 [Byte1]: 53
8759 01:33:17.625849
8760 01:33:17.626517 Set Vref, RX VrefLevel [Byte0]: 54
8761 01:33:17.629416 [Byte1]: 54
8762 01:33:17.633432
8763 01:33:17.633982 Set Vref, RX VrefLevel [Byte0]: 55
8764 01:33:17.636561 [Byte1]: 55
8765 01:33:17.640993
8766 01:33:17.641546 Set Vref, RX VrefLevel [Byte0]: 56
8767 01:33:17.644535 [Byte1]: 56
8768 01:33:17.648950
8769 01:33:17.649578 Set Vref, RX VrefLevel [Byte0]: 57
8770 01:33:17.651663 [Byte1]: 57
8771 01:33:17.656239
8772 01:33:17.656794 Set Vref, RX VrefLevel [Byte0]: 58
8773 01:33:17.659429 [Byte1]: 58
8774 01:33:17.663884
8775 01:33:17.664441 Set Vref, RX VrefLevel [Byte0]: 59
8776 01:33:17.667013 [Byte1]: 59
8777 01:33:17.671193
8778 01:33:17.671752 Set Vref, RX VrefLevel [Byte0]: 60
8779 01:33:17.674769 [Byte1]: 60
8780 01:33:17.678685
8781 01:33:17.679140 Set Vref, RX VrefLevel [Byte0]: 61
8782 01:33:17.682455 [Byte1]: 61
8783 01:33:17.686832
8784 01:33:17.687387 Set Vref, RX VrefLevel [Byte0]: 62
8785 01:33:17.690122 [Byte1]: 62
8786 01:33:17.694031
8787 01:33:17.694549 Set Vref, RX VrefLevel [Byte0]: 63
8788 01:33:17.697847 [Byte1]: 63
8789 01:33:17.701568
8790 01:33:17.702020 Set Vref, RX VrefLevel [Byte0]: 64
8791 01:33:17.705092 [Byte1]: 64
8792 01:33:17.709252
8793 01:33:17.709806 Set Vref, RX VrefLevel [Byte0]: 65
8794 01:33:17.712792 [Byte1]: 65
8795 01:33:17.716782
8796 01:33:17.717240 Set Vref, RX VrefLevel [Byte0]: 66
8797 01:33:17.720188 [Byte1]: 66
8798 01:33:17.724660
8799 01:33:17.725120 Set Vref, RX VrefLevel [Byte0]: 67
8800 01:33:17.727912 [Byte1]: 67
8801 01:33:17.732834
8802 01:33:17.733351 Set Vref, RX VrefLevel [Byte0]: 68
8803 01:33:17.735624 [Byte1]: 68
8804 01:33:17.739813
8805 01:33:17.740310 Set Vref, RX VrefLevel [Byte0]: 69
8806 01:33:17.743029 [Byte1]: 69
8807 01:33:17.747849
8808 01:33:17.748353 Set Vref, RX VrefLevel [Byte0]: 70
8809 01:33:17.751237 [Byte1]: 70
8810 01:33:17.754969
8811 01:33:17.755430 Set Vref, RX VrefLevel [Byte0]: 71
8812 01:33:17.758276 [Byte1]: 71
8813 01:33:17.763120
8814 01:33:17.763691 Set Vref, RX VrefLevel [Byte0]: 72
8815 01:33:17.766199 [Byte1]: 72
8816 01:33:17.770243
8817 01:33:17.770705 Set Vref, RX VrefLevel [Byte0]: 73
8818 01:33:17.773713 [Byte1]: 73
8819 01:33:17.778265
8820 01:33:17.778823 Final RX Vref Byte 0 = 53 to rank0
8821 01:33:17.781689 Final RX Vref Byte 1 = 58 to rank0
8822 01:33:17.784560 Final RX Vref Byte 0 = 53 to rank1
8823 01:33:17.787775 Final RX Vref Byte 1 = 58 to rank1==
8824 01:33:17.791131 Dram Type= 6, Freq= 0, CH_1, rank 0
8825 01:33:17.797801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 01:33:17.798294 ==
8827 01:33:17.798663 DQS Delay:
8828 01:33:17.800693 DQS0 = 0, DQS1 = 0
8829 01:33:17.801210 DQM Delay:
8830 01:33:17.801570 DQM0 = 133, DQM1 = 127
8831 01:33:17.804338 DQ Delay:
8832 01:33:17.807242 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8833 01:33:17.810802 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8834 01:33:17.814560 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8835 01:33:17.817312 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =138
8836 01:33:17.817833
8837 01:33:17.818242
8838 01:33:17.818583
8839 01:33:17.820778 [DramC_TX_OE_Calibration] TA2
8840 01:33:17.824263 Original DQ_B0 (3 6) =30, OEN = 27
8841 01:33:17.827650 Original DQ_B1 (3 6) =30, OEN = 27
8842 01:33:17.830477 24, 0x0, End_B0=24 End_B1=24
8843 01:33:17.833683 25, 0x0, End_B0=25 End_B1=25
8844 01:33:17.834149 26, 0x0, End_B0=26 End_B1=26
8845 01:33:17.837092 27, 0x0, End_B0=27 End_B1=27
8846 01:33:17.840502 28, 0x0, End_B0=28 End_B1=28
8847 01:33:17.844015 29, 0x0, End_B0=29 End_B1=29
8848 01:33:17.844571 30, 0x0, End_B0=30 End_B1=30
8849 01:33:17.847197 31, 0x4141, End_B0=30 End_B1=30
8850 01:33:17.850210 Byte0 end_step=30 best_step=27
8851 01:33:17.853897 Byte1 end_step=30 best_step=27
8852 01:33:17.857361 Byte0 TX OE(2T, 0.5T) = (3, 3)
8853 01:33:17.860541 Byte1 TX OE(2T, 0.5T) = (3, 3)
8854 01:33:17.861089
8855 01:33:17.861456
8856 01:33:17.867184 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8857 01:33:17.870333 CH1 RK0: MR19=303, MR18=180E
8858 01:33:17.877057 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8859 01:33:17.877616
8860 01:33:17.880123 ----->DramcWriteLeveling(PI) begin...
8861 01:33:17.880756 ==
8862 01:33:17.883381 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 01:33:17.886561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 01:33:17.887024 ==
8865 01:33:17.889957 Write leveling (Byte 0): 24 => 24
8866 01:33:17.893207 Write leveling (Byte 1): 27 => 27
8867 01:33:17.896436 DramcWriteLeveling(PI) end<-----
8868 01:33:17.897066
8869 01:33:17.897442 ==
8870 01:33:17.900058 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 01:33:17.903416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 01:33:17.906292 ==
8873 01:33:17.906754 [Gating] SW mode calibration
8874 01:33:17.916359 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8875 01:33:17.919896 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8876 01:33:17.922910 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 01:33:17.929916 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 01:33:17.932929 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8879 01:33:17.936079 1 4 12 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
8880 01:33:17.942788 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 01:33:17.946742 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 01:33:17.949627 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 01:33:17.955995 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 01:33:17.959369 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8885 01:33:17.962758 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8886 01:33:17.969417 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8887 01:33:17.972817 1 5 12 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 1)
8888 01:33:17.975914 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 01:33:17.982599 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 01:33:17.985540 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 01:33:17.989013 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 01:33:17.995267 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8893 01:33:17.998663 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8894 01:33:18.002255 1 6 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8895 01:33:18.008868 1 6 12 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8896 01:33:18.012316 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 01:33:18.015078 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 01:33:18.021896 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 01:33:18.025703 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 01:33:18.028648 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 01:33:18.035056 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8902 01:33:18.038468 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8903 01:33:18.042301 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8904 01:33:18.048217 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 01:33:18.051579 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 01:33:18.054999 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 01:33:18.061727 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 01:33:18.064498 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 01:33:18.067951 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 01:33:18.074288 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 01:33:18.078210 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 01:33:18.081039 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 01:33:18.087505 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 01:33:18.091413 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 01:33:18.094541 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 01:33:18.101069 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 01:33:18.104170 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 01:33:18.107392 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8919 01:33:18.113791 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8920 01:33:18.117585 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8921 01:33:18.120597 Total UI for P1: 0, mck2ui 16
8922 01:33:18.123851 best dqsien dly found for B1: ( 1, 9, 10)
8923 01:33:18.127734 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8924 01:33:18.130448 Total UI for P1: 0, mck2ui 16
8925 01:33:18.133485 best dqsien dly found for B0: ( 1, 9, 14)
8926 01:33:18.136706 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8927 01:33:18.143476 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8928 01:33:18.144031
8929 01:33:18.146983 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8930 01:33:18.150657 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8931 01:33:18.153529 [Gating] SW calibration Done
8932 01:33:18.153983 ==
8933 01:33:18.157012 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 01:33:18.160315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 01:33:18.160881 ==
8936 01:33:18.163154 RX Vref Scan: 0
8937 01:33:18.163611
8938 01:33:18.163971 RX Vref 0 -> 0, step: 1
8939 01:33:18.164310
8940 01:33:18.166967 RX Delay 0 -> 252, step: 8
8941 01:33:18.169935 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8942 01:33:18.176872 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8943 01:33:18.179774 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8944 01:33:18.183103 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8945 01:33:18.186406 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8946 01:33:18.189708 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8947 01:33:18.196044 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8948 01:33:18.199579 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8949 01:33:18.202593 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8950 01:33:18.206154 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8951 01:33:18.209567 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8952 01:33:18.215964 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8953 01:33:18.219338 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8954 01:33:18.222466 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8955 01:33:18.225547 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8956 01:33:18.232413 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8957 01:33:18.232989 ==
8958 01:33:18.235764 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 01:33:18.239126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 01:33:18.239548 ==
8961 01:33:18.239879 DQS Delay:
8962 01:33:18.242619 DQS0 = 0, DQS1 = 0
8963 01:33:18.243139 DQM Delay:
8964 01:33:18.245838 DQM0 = 137, DQM1 = 129
8965 01:33:18.246503 DQ Delay:
8966 01:33:18.248861 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8967 01:33:18.252728 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8968 01:33:18.255428 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8969 01:33:18.259092 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8970 01:33:18.259768
8971 01:33:18.260119
8972 01:33:18.261970 ==
8973 01:33:18.265734 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 01:33:18.268911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 01:33:18.269432 ==
8976 01:33:18.269767
8977 01:33:18.270073
8978 01:33:18.271946 TX Vref Scan disable
8979 01:33:18.272361 == TX Byte 0 ==
8980 01:33:18.279127 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8981 01:33:18.282157 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8982 01:33:18.282727 == TX Byte 1 ==
8983 01:33:18.289171 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8984 01:33:18.291828 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8985 01:33:18.292350 ==
8986 01:33:18.295304 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 01:33:18.298422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 01:33:18.298841 ==
8989 01:33:18.311876
8990 01:33:18.315096 TX Vref early break, caculate TX vref
8991 01:33:18.318986 TX Vref=16, minBit 0, minWin=23, winSum=388
8992 01:33:18.321460 TX Vref=18, minBit 0, minWin=23, winSum=394
8993 01:33:18.325178 TX Vref=20, minBit 0, minWin=23, winSum=400
8994 01:33:18.328727 TX Vref=22, minBit 6, minWin=24, winSum=411
8995 01:33:18.331869 TX Vref=24, minBit 1, minWin=25, winSum=417
8996 01:33:18.338221 TX Vref=26, minBit 0, minWin=24, winSum=422
8997 01:33:18.341479 TX Vref=28, minBit 0, minWin=24, winSum=419
8998 01:33:18.345105 TX Vref=30, minBit 3, minWin=24, winSum=419
8999 01:33:18.348151 TX Vref=32, minBit 0, minWin=24, winSum=411
9000 01:33:18.351216 TX Vref=34, minBit 5, minWin=23, winSum=395
9001 01:33:18.357873 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 24
9002 01:33:18.358365
9003 01:33:18.361142 Final TX Range 0 Vref 24
9004 01:33:18.361603
9005 01:33:18.361964 ==
9006 01:33:18.364770 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 01:33:18.368555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 01:33:18.369126 ==
9009 01:33:18.369495
9010 01:33:18.369850
9011 01:33:18.371221 TX Vref Scan disable
9012 01:33:18.377617 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9013 01:33:18.378250 == TX Byte 0 ==
9014 01:33:18.380972 u2DelayCellOfst[0]=18 cells (5 PI)
9015 01:33:18.384458 u2DelayCellOfst[1]=15 cells (4 PI)
9016 01:33:18.387769 u2DelayCellOfst[2]=0 cells (0 PI)
9017 01:33:18.391128 u2DelayCellOfst[3]=7 cells (2 PI)
9018 01:33:18.394391 u2DelayCellOfst[4]=7 cells (2 PI)
9019 01:33:18.397318 u2DelayCellOfst[5]=18 cells (5 PI)
9020 01:33:18.400869 u2DelayCellOfst[6]=18 cells (5 PI)
9021 01:33:18.403906 u2DelayCellOfst[7]=7 cells (2 PI)
9022 01:33:18.407094 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9023 01:33:18.410605 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9024 01:33:18.413772 == TX Byte 1 ==
9025 01:33:18.417267 u2DelayCellOfst[8]=0 cells (0 PI)
9026 01:33:18.420546 u2DelayCellOfst[9]=3 cells (1 PI)
9027 01:33:18.421198 u2DelayCellOfst[10]=11 cells (3 PI)
9028 01:33:18.423907 u2DelayCellOfst[11]=7 cells (2 PI)
9029 01:33:18.427043 u2DelayCellOfst[12]=15 cells (4 PI)
9030 01:33:18.430567 u2DelayCellOfst[13]=18 cells (5 PI)
9031 01:33:18.434080 u2DelayCellOfst[14]=18 cells (5 PI)
9032 01:33:18.437123 u2DelayCellOfst[15]=18 cells (5 PI)
9033 01:33:18.443566 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9034 01:33:18.446711 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9035 01:33:18.447125 DramC Write-DBI on
9036 01:33:18.447468 ==
9037 01:33:18.450501 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 01:33:18.456667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 01:33:18.457180 ==
9040 01:33:18.457512
9041 01:33:18.457814
9042 01:33:18.460085 TX Vref Scan disable
9043 01:33:18.460498 == TX Byte 0 ==
9044 01:33:18.466493 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9045 01:33:18.466909 == TX Byte 1 ==
9046 01:33:18.469802 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9047 01:33:18.473051 DramC Write-DBI off
9048 01:33:18.473544
9049 01:33:18.474205 [DATLAT]
9050 01:33:18.476709 Freq=1600, CH1 RK1
9051 01:33:18.477197
9052 01:33:18.477527 DATLAT Default: 0xf
9053 01:33:18.479617 0, 0xFFFF, sum = 0
9054 01:33:18.480038 1, 0xFFFF, sum = 0
9055 01:33:18.482876 2, 0xFFFF, sum = 0
9056 01:33:18.483299 3, 0xFFFF, sum = 0
9057 01:33:18.486212 4, 0xFFFF, sum = 0
9058 01:33:18.486635 5, 0xFFFF, sum = 0
9059 01:33:18.489570 6, 0xFFFF, sum = 0
9060 01:33:18.492596 7, 0xFFFF, sum = 0
9061 01:33:18.493021 8, 0xFFFF, sum = 0
9062 01:33:18.496214 9, 0xFFFF, sum = 0
9063 01:33:18.496637 10, 0xFFFF, sum = 0
9064 01:33:18.499491 11, 0xFFFF, sum = 0
9065 01:33:18.499914 12, 0xFFFF, sum = 0
9066 01:33:18.502709 13, 0xFFFF, sum = 0
9067 01:33:18.503134 14, 0x0, sum = 1
9068 01:33:18.506060 15, 0x0, sum = 2
9069 01:33:18.506574 16, 0x0, sum = 3
9070 01:33:18.509975 17, 0x0, sum = 4
9071 01:33:18.510553 best_step = 15
9072 01:33:18.510892
9073 01:33:18.511200 ==
9074 01:33:18.512622 Dram Type= 6, Freq= 0, CH_1, rank 1
9075 01:33:18.515942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9076 01:33:18.519273 ==
9077 01:33:18.519689 RX Vref Scan: 0
9078 01:33:18.520017
9079 01:33:18.522459 RX Vref 0 -> 0, step: 1
9080 01:33:18.522883
9081 01:33:18.523213 RX Delay 11 -> 252, step: 4
9082 01:33:18.530280 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9083 01:33:18.533316 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9084 01:33:18.536359 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9085 01:33:18.539931 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9086 01:33:18.546532 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9087 01:33:18.550093 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9088 01:33:18.553303 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9089 01:33:18.556236 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9090 01:33:18.559505 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9091 01:33:18.565943 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9092 01:33:18.569359 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9093 01:33:18.572974 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9094 01:33:18.576080 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9095 01:33:18.579462 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9096 01:33:18.585920 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9097 01:33:18.589185 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9098 01:33:18.589701 ==
9099 01:33:18.592187 Dram Type= 6, Freq= 0, CH_1, rank 1
9100 01:33:18.595780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9101 01:33:18.596237 ==
9102 01:33:18.598803 DQS Delay:
9103 01:33:18.599220 DQS0 = 0, DQS1 = 0
9104 01:33:18.602268 DQM Delay:
9105 01:33:18.602721 DQM0 = 134, DQM1 = 126
9106 01:33:18.603085 DQ Delay:
9107 01:33:18.605457 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9108 01:33:18.612496 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9109 01:33:18.616329 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9110 01:33:18.619274 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9111 01:33:18.619754
9112 01:33:18.620183
9113 01:33:18.620588
9114 01:33:18.622612 [DramC_TX_OE_Calibration] TA2
9115 01:33:18.625770 Original DQ_B0 (3 6) =30, OEN = 27
9116 01:33:18.628890 Original DQ_B1 (3 6) =30, OEN = 27
9117 01:33:18.629364 24, 0x0, End_B0=24 End_B1=24
9118 01:33:18.632103 25, 0x0, End_B0=25 End_B1=25
9119 01:33:18.635666 26, 0x0, End_B0=26 End_B1=26
9120 01:33:18.638642 27, 0x0, End_B0=27 End_B1=27
9121 01:33:18.639244 28, 0x0, End_B0=28 End_B1=28
9122 01:33:18.641891 29, 0x0, End_B0=29 End_B1=29
9123 01:33:18.645675 30, 0x0, End_B0=30 End_B1=30
9124 01:33:18.648753 31, 0x4141, End_B0=30 End_B1=30
9125 01:33:18.651869 Byte0 end_step=30 best_step=27
9126 01:33:18.655467 Byte1 end_step=30 best_step=27
9127 01:33:18.655980 Byte0 TX OE(2T, 0.5T) = (3, 3)
9128 01:33:18.658858 Byte1 TX OE(2T, 0.5T) = (3, 3)
9129 01:33:18.659593
9130 01:33:18.660028
9131 01:33:18.668946 [DQSOSCAuto] RK1, (LSB)MR18= 0x905, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
9132 01:33:18.671888 CH1 RK1: MR19=303, MR18=905
9133 01:33:18.675045 CH1_RK1: MR19=0x303, MR18=0x905, DQSOSC=405, MR23=63, INC=22, DEC=15
9134 01:33:18.678599 [RxdqsGatingPostProcess] freq 1600
9135 01:33:18.685170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9136 01:33:18.688438 best DQS0 dly(2T, 0.5T) = (1, 1)
9137 01:33:18.691996 best DQS1 dly(2T, 0.5T) = (1, 1)
9138 01:33:18.694962 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9139 01:33:18.698242 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9140 01:33:18.701826 best DQS0 dly(2T, 0.5T) = (1, 1)
9141 01:33:18.704771 best DQS1 dly(2T, 0.5T) = (1, 1)
9142 01:33:18.705187 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9143 01:33:18.707966 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9144 01:33:18.711631 Pre-setting of DQS Precalculation
9145 01:33:18.718139 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9146 01:33:18.724861 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9147 01:33:18.731667 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9148 01:33:18.732219
9149 01:33:18.732581
9150 01:33:18.734842 [Calibration Summary] 3200 Mbps
9151 01:33:18.738037 CH 0, Rank 0
9152 01:33:18.738648 SW Impedance : PASS
9153 01:33:18.741136 DUTY Scan : NO K
9154 01:33:18.744626 ZQ Calibration : PASS
9155 01:33:18.745202 Jitter Meter : NO K
9156 01:33:18.747514 CBT Training : PASS
9157 01:33:18.751061 Write leveling : PASS
9158 01:33:18.751611 RX DQS gating : PASS
9159 01:33:18.754390 RX DQ/DQS(RDDQC) : PASS
9160 01:33:18.757283 TX DQ/DQS : PASS
9161 01:33:18.757767 RX DATLAT : PASS
9162 01:33:18.760970 RX DQ/DQS(Engine): PASS
9163 01:33:18.761537 TX OE : PASS
9164 01:33:18.764287 All Pass.
9165 01:33:18.764844
9166 01:33:18.765331 CH 0, Rank 1
9167 01:33:18.767505 SW Impedance : PASS
9168 01:33:18.771236 DUTY Scan : NO K
9169 01:33:18.771801 ZQ Calibration : PASS
9170 01:33:18.774143 Jitter Meter : NO K
9171 01:33:18.774753 CBT Training : PASS
9172 01:33:18.777497 Write leveling : PASS
9173 01:33:18.781209 RX DQS gating : PASS
9174 01:33:18.781923 RX DQ/DQS(RDDQC) : PASS
9175 01:33:18.783839 TX DQ/DQS : PASS
9176 01:33:18.786916 RX DATLAT : PASS
9177 01:33:18.787389 RX DQ/DQS(Engine): PASS
9178 01:33:18.790445 TX OE : PASS
9179 01:33:18.791015 All Pass.
9180 01:33:18.791503
9181 01:33:18.793415 CH 1, Rank 0
9182 01:33:18.793871 SW Impedance : PASS
9183 01:33:18.797193 DUTY Scan : NO K
9184 01:33:18.800702 ZQ Calibration : PASS
9185 01:33:18.801162 Jitter Meter : NO K
9186 01:33:18.803708 CBT Training : PASS
9187 01:33:18.807088 Write leveling : PASS
9188 01:33:18.807544 RX DQS gating : PASS
9189 01:33:18.809976 RX DQ/DQS(RDDQC) : PASS
9190 01:33:18.813456 TX DQ/DQS : PASS
9191 01:33:18.814218 RX DATLAT : PASS
9192 01:33:18.816817 RX DQ/DQS(Engine): PASS
9193 01:33:18.820101 TX OE : PASS
9194 01:33:18.820516 All Pass.
9195 01:33:18.820842
9196 01:33:18.821144 CH 1, Rank 1
9197 01:33:18.823233 SW Impedance : PASS
9198 01:33:18.826760 DUTY Scan : NO K
9199 01:33:18.827172 ZQ Calibration : PASS
9200 01:33:18.830199 Jitter Meter : NO K
9201 01:33:18.833390 CBT Training : PASS
9202 01:33:18.833950 Write leveling : PASS
9203 01:33:18.837092 RX DQS gating : PASS
9204 01:33:18.839860 RX DQ/DQS(RDDQC) : PASS
9205 01:33:18.840400 TX DQ/DQS : PASS
9206 01:33:18.843199 RX DATLAT : PASS
9207 01:33:18.843609 RX DQ/DQS(Engine): PASS
9208 01:33:18.846702 TX OE : PASS
9209 01:33:18.847219 All Pass.
9210 01:33:18.847547
9211 01:33:18.849694 DramC Write-DBI on
9212 01:33:18.853207 PER_BANK_REFRESH: Hybrid Mode
9213 01:33:18.853725 TX_TRACKING: ON
9214 01:33:18.863264 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9215 01:33:18.869780 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9216 01:33:18.879725 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9217 01:33:18.882809 [FAST_K] Save calibration result to emmc
9218 01:33:18.886078 sync common calibartion params.
9219 01:33:18.886606 sync cbt_mode0:1, 1:1
9220 01:33:18.889914 dram_init: ddr_geometry: 2
9221 01:33:18.892935 dram_init: ddr_geometry: 2
9222 01:33:18.893492 dram_init: ddr_geometry: 2
9223 01:33:18.895831 0:dram_rank_size:100000000
9224 01:33:18.899418 1:dram_rank_size:100000000
9225 01:33:18.902457 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9226 01:33:18.906026 DFS_SHUFFLE_HW_MODE: ON
9227 01:33:18.909704 dramc_set_vcore_voltage set vcore to 725000
9228 01:33:18.912790 Read voltage for 1600, 0
9229 01:33:18.913339 Vio18 = 0
9230 01:33:18.916016 Vcore = 725000
9231 01:33:18.916566 Vdram = 0
9232 01:33:18.916934 Vddq = 0
9233 01:33:18.919076 Vmddr = 0
9234 01:33:18.919531 switch to 3200 Mbps bootup
9235 01:33:18.922254 [DramcRunTimeConfig]
9236 01:33:18.922711 PHYPLL
9237 01:33:18.925784 DPM_CONTROL_AFTERK: ON
9238 01:33:18.926399 PER_BANK_REFRESH: ON
9239 01:33:18.929243 REFRESH_OVERHEAD_REDUCTION: ON
9240 01:33:18.932543 CMD_PICG_NEW_MODE: OFF
9241 01:33:18.933090 XRTWTW_NEW_MODE: ON
9242 01:33:18.935721 XRTRTR_NEW_MODE: ON
9243 01:33:18.936503 TX_TRACKING: ON
9244 01:33:18.938812 RDSEL_TRACKING: OFF
9245 01:33:18.942211 DQS Precalculation for DVFS: ON
9246 01:33:18.942675 RX_TRACKING: OFF
9247 01:33:18.945654 HW_GATING DBG: ON
9248 01:33:18.946245 ZQCS_ENABLE_LP4: ON
9249 01:33:18.949269 RX_PICG_NEW_MODE: ON
9250 01:33:18.949821 TX_PICG_NEW_MODE: ON
9251 01:33:18.952388 ENABLE_RX_DCM_DPHY: ON
9252 01:33:18.955295 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9253 01:33:18.958861 DUMMY_READ_FOR_TRACKING: OFF
9254 01:33:18.959362 !!! SPM_CONTROL_AFTERK: OFF
9255 01:33:18.961888 !!! SPM could not control APHY
9256 01:33:18.965559 IMPEDANCE_TRACKING: ON
9257 01:33:18.966108 TEMP_SENSOR: ON
9258 01:33:18.968493 HW_SAVE_FOR_SR: OFF
9259 01:33:18.971892 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9260 01:33:18.975832 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9261 01:33:18.978280 Read ODT Tracking: ON
9262 01:33:18.978740 Refresh Rate DeBounce: ON
9263 01:33:18.981821 DFS_NO_QUEUE_FLUSH: ON
9264 01:33:18.985120 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9265 01:33:18.988377 ENABLE_DFS_RUNTIME_MRW: OFF
9266 01:33:18.988954 DDR_RESERVE_NEW_MODE: ON
9267 01:33:18.991688 MR_CBT_SWITCH_FREQ: ON
9268 01:33:18.995177 =========================
9269 01:33:19.012695 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9270 01:33:19.015872 dram_init: ddr_geometry: 2
9271 01:33:19.033938 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9272 01:33:19.037480 dram_init: dram init end (result: 0)
9273 01:33:19.044006 DRAM-K: Full calibration passed in 24649 msecs
9274 01:33:19.047308 MRC: failed to locate region type 0.
9275 01:33:19.048088 DRAM rank0 size:0x100000000,
9276 01:33:19.050510 DRAM rank1 size=0x100000000
9277 01:33:19.060649 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9278 01:33:19.067076 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9279 01:33:19.073779 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9280 01:33:19.083401 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9281 01:33:19.083960 DRAM rank0 size:0x100000000,
9282 01:33:19.087050 DRAM rank1 size=0x100000000
9283 01:33:19.087602 CBMEM:
9284 01:33:19.089823 IMD: root @ 0xfffff000 254 entries.
9285 01:33:19.093714 IMD: root @ 0xffffec00 62 entries.
9286 01:33:19.096438 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9287 01:33:19.103200 WARNING: RO_VPD is uninitialized or empty.
9288 01:33:19.106341 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9289 01:33:19.114109 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9290 01:33:19.126895 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9291 01:33:19.137993 BS: romstage times (exec / console): total (unknown) / 24138 ms
9292 01:33:19.138739
9293 01:33:19.139334
9294 01:33:19.148085 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9295 01:33:19.151009 ARM64: Exception handlers installed.
9296 01:33:19.154608 ARM64: Testing exception
9297 01:33:19.158110 ARM64: Done test exception
9298 01:33:19.158597 Enumerating buses...
9299 01:33:19.160887 Show all devs... Before device enumeration.
9300 01:33:19.164599 Root Device: enabled 1
9301 01:33:19.167707 CPU_CLUSTER: 0: enabled 1
9302 01:33:19.168267 CPU: 00: enabled 1
9303 01:33:19.171053 Compare with tree...
9304 01:33:19.171608 Root Device: enabled 1
9305 01:33:19.174325 CPU_CLUSTER: 0: enabled 1
9306 01:33:19.177672 CPU: 00: enabled 1
9307 01:33:19.178285 Root Device scanning...
9308 01:33:19.181352 scan_static_bus for Root Device
9309 01:33:19.184295 CPU_CLUSTER: 0 enabled
9310 01:33:19.187523 scan_static_bus for Root Device done
9311 01:33:19.191298 scan_bus: bus Root Device finished in 8 msecs
9312 01:33:19.191859 done
9313 01:33:19.197111 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9314 01:33:19.200262 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9315 01:33:19.207092 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9316 01:33:19.213333 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9317 01:33:19.213896 Allocating resources...
9318 01:33:19.216581 Reading resources...
9319 01:33:19.219973 Root Device read_resources bus 0 link: 0
9320 01:33:19.223440 DRAM rank0 size:0x100000000,
9321 01:33:19.226464 DRAM rank1 size=0x100000000
9322 01:33:19.229876 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9323 01:33:19.233357 CPU: 00 missing read_resources
9324 01:33:19.236544 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9325 01:33:19.239692 Root Device read_resources bus 0 link: 0 done
9326 01:33:19.243418 Done reading resources.
9327 01:33:19.246274 Show resources in subtree (Root Device)...After reading.
9328 01:33:19.249495 Root Device child on link 0 CPU_CLUSTER: 0
9329 01:33:19.256375 CPU_CLUSTER: 0 child on link 0 CPU: 00
9330 01:33:19.262867 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9331 01:33:19.266117 CPU: 00
9332 01:33:19.269033 Root Device assign_resources, bus 0 link: 0
9333 01:33:19.272478 CPU_CLUSTER: 0 missing set_resources
9334 01:33:19.275860 Root Device assign_resources, bus 0 link: 0 done
9335 01:33:19.279227 Done setting resources.
9336 01:33:19.282817 Show resources in subtree (Root Device)...After assigning values.
9337 01:33:19.288793 Root Device child on link 0 CPU_CLUSTER: 0
9338 01:33:19.292422 CPU_CLUSTER: 0 child on link 0 CPU: 00
9339 01:33:19.298838 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9340 01:33:19.302048 CPU: 00
9341 01:33:19.302531 Done allocating resources.
9342 01:33:19.309026 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9343 01:33:19.311941 Enabling resources...
9344 01:33:19.312491 done.
9345 01:33:19.315128 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9346 01:33:19.318869 Initializing devices...
9347 01:33:19.319428 Root Device init
9348 01:33:19.321995 init hardware done!
9349 01:33:19.325122 0x00000018: ctrlr->caps
9350 01:33:19.325702 52.000 MHz: ctrlr->f_max
9351 01:33:19.328588 0.400 MHz: ctrlr->f_min
9352 01:33:19.331773 0x40ff8080: ctrlr->voltages
9353 01:33:19.332243 sclk: 390625
9354 01:33:19.332611 Bus Width = 1
9355 01:33:19.335107 sclk: 390625
9356 01:33:19.335564 Bus Width = 1
9357 01:33:19.338439 Early init status = 3
9358 01:33:19.341728 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9359 01:33:19.346738 in-header: 03 fc 00 00 01 00 00 00
9360 01:33:19.350253 in-data: 00
9361 01:33:19.353303 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9362 01:33:19.362127 in-header: 03 fd 00 00 00 00 00 00
9363 01:33:19.362578 in-data:
9364 01:33:19.365613 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9365 01:33:19.369993 in-header: 03 fc 00 00 01 00 00 00
9366 01:33:19.374118 in-data: 00
9367 01:33:19.377015 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9368 01:33:19.382241 in-header: 03 fd 00 00 00 00 00 00
9369 01:33:19.385396 in-data:
9370 01:33:19.388746 [SSUSB] Setting up USB HOST controller...
9371 01:33:19.392320 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9372 01:33:19.395377 [SSUSB] phy power-on done.
9373 01:33:19.398902 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9374 01:33:19.405324 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9375 01:33:19.408504 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9376 01:33:19.415236 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9377 01:33:19.421857 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9378 01:33:19.428294 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9379 01:33:19.434900 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9380 01:33:19.442211 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9381 01:33:19.444784 SPM: binary array size = 0x9dc
9382 01:33:19.448688 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9383 01:33:19.454918 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9384 01:33:19.461664 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9385 01:33:19.467908 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9386 01:33:19.471089 configure_display: Starting display init
9387 01:33:19.506439 anx7625_power_on_init: Init interface.
9388 01:33:19.509090 anx7625_disable_pd_protocol: Disabled PD feature.
9389 01:33:19.511942 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9390 01:33:19.539967 anx7625_start_dp_work: Secure OCM version=00
9391 01:33:19.543265 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9392 01:33:19.558524 sp_tx_get_edid_block: EDID Block = 1
9393 01:33:19.661021 Extracted contents:
9394 01:33:19.664113 header: 00 ff ff ff ff ff ff 00
9395 01:33:19.667328 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9396 01:33:19.670573 version: 01 04
9397 01:33:19.673806 basic params: 95 1f 11 78 0a
9398 01:33:19.677582 chroma info: 76 90 94 55 54 90 27 21 50 54
9399 01:33:19.680643 established: 00 00 00
9400 01:33:19.687079 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9401 01:33:19.690237 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9402 01:33:19.696902 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 01:33:19.703490 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9404 01:33:19.710710 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9405 01:33:19.713755 extensions: 00
9406 01:33:19.714189 checksum: fb
9407 01:33:19.714559
9408 01:33:19.717011 Manufacturer: IVO Model 57d Serial Number 0
9409 01:33:19.720428 Made week 0 of 2020
9410 01:33:19.720837 EDID version: 1.4
9411 01:33:19.723814 Digital display
9412 01:33:19.726713 6 bits per primary color channel
9413 01:33:19.727129 DisplayPort interface
9414 01:33:19.730137 Maximum image size: 31 cm x 17 cm
9415 01:33:19.733407 Gamma: 220%
9416 01:33:19.733829 Check DPMS levels
9417 01:33:19.736674 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9418 01:33:19.743510 First detailed timing is preferred timing
9419 01:33:19.743937 Established timings supported:
9420 01:33:19.746705 Standard timings supported:
9421 01:33:19.749945 Detailed timings
9422 01:33:19.752971 Hex of detail: 383680a07038204018303c0035ae10000019
9423 01:33:19.759932 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9424 01:33:19.763357 0780 0798 07c8 0820 hborder 0
9425 01:33:19.766383 0438 043b 0447 0458 vborder 0
9426 01:33:19.770361 -hsync -vsync
9427 01:33:19.770865 Did detailed timing
9428 01:33:19.777023 Hex of detail: 000000000000000000000000000000000000
9429 01:33:19.779533 Manufacturer-specified data, tag 0
9430 01:33:19.783136 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9431 01:33:19.786227 ASCII string: InfoVision
9432 01:33:19.789468 Hex of detail: 000000fe00523134304e574635205248200a
9433 01:33:19.792870 ASCII string: R140NWF5 RH
9434 01:33:19.793310 Checksum
9435 01:33:19.796103 Checksum: 0xfb (valid)
9436 01:33:19.799440 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9437 01:33:19.803045 DSI data_rate: 832800000 bps
9438 01:33:19.809557 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9439 01:33:19.813071 anx7625_parse_edid: pixelclock(138800).
9440 01:33:19.816016 hactive(1920), hsync(48), hfp(24), hbp(88)
9441 01:33:19.819690 vactive(1080), vsync(12), vfp(3), vbp(17)
9442 01:33:19.823502 anx7625_dsi_config: config dsi.
9443 01:33:19.829891 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9444 01:33:19.842588 anx7625_dsi_config: success to config DSI
9445 01:33:19.845859 anx7625_dp_start: MIPI phy setup OK.
9446 01:33:19.849451 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9447 01:33:19.852626 mtk_ddp_mode_set invalid vrefresh 60
9448 01:33:19.855703 main_disp_path_setup
9449 01:33:19.856170 ovl_layer_smi_id_en
9450 01:33:19.859245 ovl_layer_smi_id_en
9451 01:33:19.859763 ccorr_config
9452 01:33:19.860096 aal_config
9453 01:33:19.862648 gamma_config
9454 01:33:19.863055 postmask_config
9455 01:33:19.866021 dither_config
9456 01:33:19.869259 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9457 01:33:19.875687 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9458 01:33:19.879229 Root Device init finished in 555 msecs
9459 01:33:19.882371 CPU_CLUSTER: 0 init
9460 01:33:19.888978 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9461 01:33:19.892985 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9462 01:33:19.895790 APU_MBOX 0x190000b0 = 0x10001
9463 01:33:19.899167 APU_MBOX 0x190001b0 = 0x10001
9464 01:33:19.902545 APU_MBOX 0x190005b0 = 0x10001
9465 01:33:19.905953 APU_MBOX 0x190006b0 = 0x10001
9466 01:33:19.908705 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9467 01:33:19.921519 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9468 01:33:19.934365 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9469 01:33:19.940889 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9470 01:33:19.952241 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9471 01:33:19.961415 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9472 01:33:19.965084 CPU_CLUSTER: 0 init finished in 81 msecs
9473 01:33:19.968087 Devices initialized
9474 01:33:19.971578 Show all devs... After init.
9475 01:33:19.972177 Root Device: enabled 1
9476 01:33:19.974496 CPU_CLUSTER: 0: enabled 1
9477 01:33:19.977739 CPU: 00: enabled 1
9478 01:33:19.981573 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9479 01:33:19.984572 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9480 01:33:19.987883 ELOG: NV offset 0x57f000 size 0x1000
9481 01:33:19.994620 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9482 01:33:20.001293 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9483 01:33:20.004197 ELOG: Event(17) added with size 13 at 2024-06-05 01:33:19 UTC
9484 01:33:20.010864 out: cmd=0x121: 03 db 21 01 00 00 00 00
9485 01:33:20.014181 in-header: 03 da 00 00 2c 00 00 00
9486 01:33:20.027567 in-data: 63 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9487 01:33:20.030898 ELOG: Event(A1) added with size 10 at 2024-06-05 01:33:19 UTC
9488 01:33:20.040413 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9489 01:33:20.043864 ELOG: Event(A0) added with size 9 at 2024-06-05 01:33:19 UTC
9490 01:33:20.047320 elog_add_boot_reason: Logged dev mode boot
9491 01:33:20.053627 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9492 01:33:20.054216 Finalize devices...
9493 01:33:20.056723 Devices finalized
9494 01:33:20.060735 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9495 01:33:20.067016 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9496 01:33:20.070304 in-header: 03 07 00 00 08 00 00 00
9497 01:33:20.073623 in-data: aa e4 47 04 13 02 00 00
9498 01:33:20.074207 Chrome EC: UHEPI supported
9499 01:33:20.080275 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9500 01:33:20.083638 in-header: 03 a9 00 00 08 00 00 00
9501 01:33:20.086895 in-data: 84 60 60 08 00 00 00 00
9502 01:33:20.093167 ELOG: Event(91) added with size 10 at 2024-06-05 01:33:19 UTC
9503 01:33:20.096707 Chrome EC: clear events_b mask to 0x0000000020004000
9504 01:33:20.103168 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9505 01:33:20.107318 in-header: 03 fd 00 00 00 00 00 00
9506 01:33:20.110273 in-data:
9507 01:33:20.113672 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9508 01:33:20.117096 Writing coreboot table at 0xffe64000
9509 01:33:20.123553 0. 000000000010a000-0000000000113fff: RAMSTAGE
9510 01:33:20.126954 1. 0000000040000000-00000000400fffff: RAM
9511 01:33:20.129873 2. 0000000040100000-000000004032afff: RAMSTAGE
9512 01:33:20.133203 3. 000000004032b000-00000000545fffff: RAM
9513 01:33:20.136529 4. 0000000054600000-000000005465ffff: BL31
9514 01:33:20.143216 5. 0000000054660000-00000000ffe63fff: RAM
9515 01:33:20.146339 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9516 01:33:20.149860 7. 0000000100000000-000000023fffffff: RAM
9517 01:33:20.153249 Passing 5 GPIOs to payload:
9518 01:33:20.159812 NAME | PORT | POLARITY | VALUE
9519 01:33:20.163119 EC in RW | 0x000000aa | low | undefined
9520 01:33:20.166364 EC interrupt | 0x00000005 | low | undefined
9521 01:33:20.173063 TPM interrupt | 0x000000ab | high | undefined
9522 01:33:20.175881 SD card detect | 0x00000011 | high | undefined
9523 01:33:20.182954 speaker enable | 0x00000093 | high | undefined
9524 01:33:20.185828 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9525 01:33:20.189585 in-header: 03 f9 00 00 02 00 00 00
9526 01:33:20.190038 in-data: 02 00
9527 01:33:20.192526 ADC[4]: Raw value=900443 ID=7
9528 01:33:20.195645 ADC[3]: Raw value=212912 ID=1
9529 01:33:20.198763 RAM Code: 0x71
9530 01:33:20.199338 ADC[6]: Raw value=75036 ID=0
9531 01:33:20.202690 ADC[5]: Raw value=213282 ID=1
9532 01:33:20.205693 SKU Code: 0x1
9533 01:33:20.208827 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum faa4
9534 01:33:20.211979 coreboot table: 964 bytes.
9535 01:33:20.215703 IMD ROOT 0. 0xfffff000 0x00001000
9536 01:33:20.218790 IMD SMALL 1. 0xffffe000 0x00001000
9537 01:33:20.222217 RO MCACHE 2. 0xffffc000 0x00001104
9538 01:33:20.225295 CONSOLE 3. 0xfff7c000 0x00080000
9539 01:33:20.229189 FMAP 4. 0xfff7b000 0x00000452
9540 01:33:20.232091 TIME STAMP 5. 0xfff7a000 0x00000910
9541 01:33:20.235606 VBOOT WORK 6. 0xfff66000 0x00014000
9542 01:33:20.238369 RAMOOPS 7. 0xffe66000 0x00100000
9543 01:33:20.242283 COREBOOT 8. 0xffe64000 0x00002000
9544 01:33:20.242837 IMD small region:
9545 01:33:20.245573 IMD ROOT 0. 0xffffec00 0x00000400
9546 01:33:20.251825 VPD 1. 0xffffeb80 0x0000006c
9547 01:33:20.255572 MMC STATUS 2. 0xffffeb60 0x00000004
9548 01:33:20.258401 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9549 01:33:20.265397 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9550 01:33:20.304964 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9551 01:33:20.308504 Checking segment from ROM address 0x40100000
9552 01:33:20.314905 Checking segment from ROM address 0x4010001c
9553 01:33:20.318518 Loading segment from ROM address 0x40100000
9554 01:33:20.319060 code (compression=0)
9555 01:33:20.328082 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9556 01:33:20.334649 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9557 01:33:20.338043 it's not compressed!
9558 01:33:20.341486 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9559 01:33:20.347990 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9560 01:33:20.366029 Loading segment from ROM address 0x4010001c
9561 01:33:20.366626 Entry Point 0x80000000
9562 01:33:20.369541 Loaded segments
9563 01:33:20.372969 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9564 01:33:20.379104 Jumping to boot code at 0x80000000(0xffe64000)
9565 01:33:20.385683 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9566 01:33:20.392312 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9567 01:33:20.400140 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9568 01:33:20.403392 Checking segment from ROM address 0x40100000
9569 01:33:20.406590 Checking segment from ROM address 0x4010001c
9570 01:33:20.413808 Loading segment from ROM address 0x40100000
9571 01:33:20.414426 code (compression=1)
9572 01:33:20.420063 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9573 01:33:20.429531 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9574 01:33:20.430281 using LZMA
9575 01:33:20.438725 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9576 01:33:20.445307 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9577 01:33:20.448562 Loading segment from ROM address 0x4010001c
9578 01:33:20.449129 Entry Point 0x54601000
9579 01:33:20.451735 Loaded segments
9580 01:33:20.455041 NOTICE: MT8192 bl31_setup
9581 01:33:20.462344 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9582 01:33:20.465984 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9583 01:33:20.468809 WARNING: region 0:
9584 01:33:20.472160 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 01:33:20.472726 WARNING: region 1:
9586 01:33:20.478933 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9587 01:33:20.482126 WARNING: region 2:
9588 01:33:20.485498 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9589 01:33:20.488397 WARNING: region 3:
9590 01:33:20.491849 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9591 01:33:20.495078 WARNING: region 4:
9592 01:33:20.501845 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9593 01:33:20.502444 WARNING: region 5:
9594 01:33:20.505219 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9595 01:33:20.508547 WARNING: region 6:
9596 01:33:20.511536 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9597 01:33:20.515129 WARNING: region 7:
9598 01:33:20.518071 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9599 01:33:20.525183 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9600 01:33:20.528507 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9601 01:33:20.534755 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9602 01:33:20.538645 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9603 01:33:20.541219 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9604 01:33:20.548081 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9605 01:33:20.551295 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9606 01:33:20.554735 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9607 01:33:20.561668 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9608 01:33:20.564809 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9609 01:33:20.571341 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9610 01:33:20.574366 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9611 01:33:20.578204 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9612 01:33:20.584584 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9613 01:33:20.587667 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9614 01:33:20.590990 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9615 01:33:20.597615 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9616 01:33:20.600941 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9617 01:33:20.607558 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9618 01:33:20.610774 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9619 01:33:20.613857 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9620 01:33:20.620904 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9621 01:33:20.624123 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9622 01:33:20.630623 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9623 01:33:20.633744 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9624 01:33:20.636952 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9625 01:33:20.644187 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9626 01:33:20.647434 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9627 01:33:20.653794 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9628 01:33:20.656820 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9629 01:33:20.663453 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9630 01:33:20.666737 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9631 01:33:20.669818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9632 01:33:20.673729 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9633 01:33:20.680071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9634 01:33:20.682930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9635 01:33:20.686887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9636 01:33:20.689997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9637 01:33:20.696213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9638 01:33:20.699425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9639 01:33:20.702896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9640 01:33:20.706325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9641 01:33:20.712784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9642 01:33:20.716715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9643 01:33:20.720177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9644 01:33:20.726439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9645 01:33:20.729661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9646 01:33:20.733243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9647 01:33:20.739542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9648 01:33:20.742335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9649 01:33:20.745619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9650 01:33:20.752647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9651 01:33:20.755674 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9652 01:33:20.762519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9653 01:33:20.765711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9654 01:33:20.772593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9655 01:33:20.775386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9656 01:33:20.782000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9657 01:33:20.785645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9658 01:33:20.789055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9659 01:33:20.795156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9660 01:33:20.798592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9661 01:33:20.805535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9662 01:33:20.808583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9663 01:33:20.814832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9664 01:33:20.818093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9665 01:33:20.825529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9666 01:33:20.829075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9667 01:33:20.831643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9668 01:33:20.838232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9669 01:33:20.841502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9670 01:33:20.848195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9671 01:33:20.851507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9672 01:33:20.857900 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9673 01:33:20.861208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9674 01:33:20.867584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9675 01:33:20.870843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9676 01:33:20.878003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9677 01:33:20.880819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9678 01:33:20.884474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9679 01:33:20.890843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9680 01:33:20.894027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9681 01:33:20.900802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9682 01:33:20.904537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9683 01:33:20.911116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9684 01:33:20.914004 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9685 01:33:20.917247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9686 01:33:20.923702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9687 01:33:20.927162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9688 01:33:20.933517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9689 01:33:20.936954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9690 01:33:20.943478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9691 01:33:20.946664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9692 01:33:20.953526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9693 01:33:20.957096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9694 01:33:20.963382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9695 01:33:20.966604 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9696 01:33:20.969939 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9697 01:33:20.972977 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9698 01:33:20.979670 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9699 01:33:20.983204 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9700 01:33:20.986153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9701 01:33:20.992785 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9702 01:33:20.996173 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9703 01:33:21.002711 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9704 01:33:21.006233 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9705 01:33:21.009363 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9706 01:33:21.016464 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9707 01:33:21.019707 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9708 01:33:21.025798 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9709 01:33:21.029504 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9710 01:33:21.032885 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9711 01:33:21.039152 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9712 01:33:21.042744 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9713 01:33:21.048999 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9714 01:33:21.052324 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9715 01:33:21.055610 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9716 01:33:21.062348 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9717 01:33:21.065928 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9718 01:33:21.068973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9719 01:33:21.075216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9720 01:33:21.078640 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9721 01:33:21.082017 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9722 01:33:21.085265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9723 01:33:21.091691 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9724 01:33:21.095124 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9725 01:33:21.101663 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9726 01:33:21.105110 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9727 01:33:21.108417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9728 01:33:21.114725 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9729 01:33:21.118250 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9730 01:33:21.124989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9731 01:33:21.128005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9732 01:33:21.131590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9733 01:33:21.138014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9734 01:33:21.141189 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9735 01:33:21.147844 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9736 01:33:21.151226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9737 01:33:21.154562 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9738 01:33:21.161574 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9739 01:33:21.164251 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9740 01:33:21.170871 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9741 01:33:21.174554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9742 01:33:21.177661 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9743 01:33:21.184596 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9744 01:33:21.188243 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9745 01:33:21.190861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9746 01:33:21.197397 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9747 01:33:21.201103 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9748 01:33:21.207354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9749 01:33:21.210680 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9750 01:33:21.213653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9751 01:33:21.220663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9752 01:33:21.223842 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9753 01:33:21.230221 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9754 01:33:21.233927 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9755 01:33:21.240277 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9756 01:33:21.243682 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9757 01:33:21.246958 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9758 01:33:21.253368 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9759 01:33:21.257328 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9760 01:33:21.263372 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9761 01:33:21.266719 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9762 01:33:21.270827 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9763 01:33:21.276940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9764 01:33:21.279750 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9765 01:33:21.286740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9766 01:33:21.289660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9767 01:33:21.292918 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9768 01:33:21.299526 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9769 01:33:21.302740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9770 01:33:21.309559 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9771 01:33:21.313112 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9772 01:33:21.315946 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9773 01:33:21.322599 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9774 01:33:21.325623 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9775 01:33:21.332433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9776 01:33:21.335584 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9777 01:33:21.339060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9778 01:33:21.345441 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9779 01:33:21.348728 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9780 01:33:21.355409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9781 01:33:21.359209 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9782 01:33:21.362325 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9783 01:33:21.368718 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9784 01:33:21.372098 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9785 01:33:21.378441 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9786 01:33:21.381581 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9787 01:33:21.385180 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9788 01:33:21.391946 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9789 01:33:21.395242 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9790 01:33:21.401853 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9791 01:33:21.405260 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9792 01:33:21.411893 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9793 01:33:21.414621 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9794 01:33:21.418398 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9795 01:33:21.424613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9796 01:33:21.427815 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9797 01:33:21.434430 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9798 01:33:21.438326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9799 01:33:21.444245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9800 01:33:21.447909 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9801 01:33:21.451691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9802 01:33:21.457432 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9803 01:33:21.460729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9804 01:33:21.467147 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9805 01:33:21.470874 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9806 01:33:21.476918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9807 01:33:21.480629 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9808 01:33:21.487126 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9809 01:33:21.490783 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9810 01:33:21.493467 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9811 01:33:21.500272 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9812 01:33:21.503423 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9813 01:33:21.510113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9814 01:33:21.513197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9815 01:33:21.516905 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9816 01:33:21.523052 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9817 01:33:21.526563 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9818 01:33:21.533176 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9819 01:33:21.536415 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9820 01:33:21.542861 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9821 01:33:21.546197 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9822 01:33:21.552904 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9823 01:33:21.556304 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9824 01:33:21.559502 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9825 01:33:21.565915 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9826 01:33:21.569121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9827 01:33:21.576222 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9828 01:33:21.579399 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9829 01:33:21.582505 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9830 01:33:21.585777 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9831 01:33:21.592415 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9832 01:33:21.596120 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9833 01:33:21.598937 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9834 01:33:21.605673 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9835 01:33:21.608542 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9836 01:33:21.611718 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9837 01:33:21.618687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9838 01:33:21.621816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9839 01:33:21.628348 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9840 01:33:21.631396 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9841 01:33:21.634892 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9842 01:33:21.641502 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9843 01:33:21.644776 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9844 01:33:21.648260 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9845 01:33:21.654919 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9846 01:33:21.657653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9847 01:33:21.664502 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9848 01:33:21.667584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9849 01:33:21.670925 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9850 01:33:21.677631 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9851 01:33:21.680952 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9852 01:33:21.684413 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9853 01:33:21.690832 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9854 01:33:21.694368 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9855 01:33:21.700961 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9856 01:33:21.703935 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9857 01:33:21.707473 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9858 01:33:21.714098 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9859 01:33:21.716995 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9860 01:33:21.720595 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9861 01:33:21.727687 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9862 01:33:21.730558 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9863 01:33:21.733885 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9864 01:33:21.741026 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9865 01:33:21.743746 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9866 01:33:21.750368 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9867 01:33:21.754278 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9868 01:33:21.756952 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9869 01:33:21.760292 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9870 01:33:21.766851 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9871 01:33:21.770254 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9872 01:33:21.773702 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9873 01:33:21.776829 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9874 01:33:21.783549 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9875 01:33:21.786622 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9876 01:33:21.790000 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9877 01:33:21.793223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9878 01:33:21.800008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9879 01:33:21.802884 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9880 01:33:21.806555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9881 01:33:21.813324 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9882 01:33:21.816460 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9883 01:33:21.823354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9884 01:33:21.825912 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9885 01:33:21.829327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9886 01:33:21.836143 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9887 01:33:21.839238 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9888 01:33:21.846110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9889 01:33:21.849171 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9890 01:33:21.852679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9891 01:33:21.859065 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9892 01:33:21.862477 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9893 01:33:21.869246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9894 01:33:21.872319 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9895 01:33:21.878767 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9896 01:33:21.882340 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9897 01:33:21.885350 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9898 01:33:21.891966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9899 01:33:21.895212 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9900 01:33:21.901919 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9901 01:33:21.905412 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9902 01:33:21.911788 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9903 01:33:21.915296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9904 01:33:21.918446 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9905 01:33:21.925560 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9906 01:33:21.928460 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9907 01:33:21.934888 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9908 01:33:21.938505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9909 01:33:21.944847 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9910 01:33:21.948126 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9911 01:33:21.951881 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9912 01:33:21.958229 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9913 01:33:21.961040 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9914 01:33:21.968352 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9915 01:33:21.971853 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9916 01:33:21.974494 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9917 01:33:21.981564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9918 01:33:21.984668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9919 01:33:21.990629 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9920 01:33:21.994280 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9921 01:33:21.998023 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9922 01:33:22.004129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9923 01:33:22.007297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9924 01:33:22.013931 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9925 01:33:22.017028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9926 01:33:22.024748 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9927 01:33:22.026993 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9928 01:33:22.030761 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9929 01:33:22.037056 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9930 01:33:22.040450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9931 01:33:22.046944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9932 01:33:22.050839 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9933 01:33:22.057317 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9934 01:33:22.060472 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9935 01:33:22.064662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9936 01:33:22.070574 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9937 01:33:22.073645 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9938 01:33:22.080448 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9939 01:33:22.083827 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9940 01:33:22.086692 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9941 01:33:22.093056 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9942 01:33:22.096722 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9943 01:33:22.103048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9944 01:33:22.106056 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9945 01:33:22.109451 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9946 01:33:22.116294 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9947 01:33:22.119600 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9948 01:33:22.125966 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9949 01:33:22.129700 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9950 01:33:22.136004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9951 01:33:22.139241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9952 01:33:22.142315 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9953 01:33:22.149460 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9954 01:33:22.152683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9955 01:33:22.159104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9956 01:33:22.162563 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9957 01:33:22.169280 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9958 01:33:22.172096 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9959 01:33:22.178756 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9960 01:33:22.182062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9961 01:33:22.185294 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9962 01:33:22.192039 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9963 01:33:22.195113 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9964 01:33:22.201501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9965 01:33:22.204814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9966 01:33:22.211555 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9967 01:33:22.215134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9968 01:33:22.221492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9969 01:33:22.224710 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9970 01:33:22.228229 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9971 01:33:22.234786 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9972 01:33:22.238091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9973 01:33:22.244308 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9974 01:33:22.247635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9975 01:33:22.254618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9976 01:33:22.257682 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9977 01:33:22.264216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9978 01:33:22.267780 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9979 01:33:22.274311 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9980 01:33:22.277677 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9981 01:33:22.280681 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9982 01:33:22.287482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9983 01:33:22.290592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9984 01:33:22.297167 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9985 01:33:22.300519 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9986 01:33:22.307114 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9987 01:33:22.310431 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9988 01:33:22.316716 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9989 01:33:22.319924 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9990 01:33:22.323406 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9991 01:33:22.330491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9992 01:33:22.333540 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9993 01:33:22.339956 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9994 01:33:22.342943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9995 01:33:22.349512 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9996 01:33:22.352821 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9997 01:33:22.360403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9998 01:33:22.363104 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9999 01:33:22.369782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10000 01:33:22.373078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10001 01:33:22.376077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10002 01:33:22.382612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10003 01:33:22.386121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10004 01:33:22.392825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10005 01:33:22.396121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10006 01:33:22.402263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10007 01:33:22.405772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10008 01:33:22.412479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10009 01:33:22.415998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10010 01:33:22.422141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10011 01:33:22.425962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10012 01:33:22.432301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10013 01:33:22.435618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10014 01:33:22.441982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10015 01:33:22.445147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10016 01:33:22.448375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10017 01:33:22.455243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10018 01:33:22.458463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10019 01:33:22.465242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10020 01:33:22.468353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10021 01:33:22.474749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10022 01:33:22.481343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10023 01:33:22.484580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10024 01:33:22.491770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10025 01:33:22.495455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10026 01:33:22.501503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10027 01:33:22.504925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10028 01:33:22.511185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10029 01:33:22.514534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10030 01:33:22.521207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10031 01:33:22.524518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10032 01:33:22.531235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10033 01:33:22.534599 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10034 01:33:22.537698 INFO: [APUAPC] vio 0
10035 01:33:22.541256 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10036 01:33:22.544624 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10037 01:33:22.547468 INFO: [APUAPC] D0_APC_0: 0x400510
10038 01:33:22.550720 INFO: [APUAPC] D0_APC_1: 0x0
10039 01:33:22.554335 INFO: [APUAPC] D0_APC_2: 0x1540
10040 01:33:22.557198 INFO: [APUAPC] D0_APC_3: 0x0
10041 01:33:22.560820 INFO: [APUAPC] D1_APC_0: 0xffffffff
10042 01:33:22.563750 INFO: [APUAPC] D1_APC_1: 0xffffffff
10043 01:33:22.567592 INFO: [APUAPC] D1_APC_2: 0x3fffff
10044 01:33:22.570763 INFO: [APUAPC] D1_APC_3: 0x0
10045 01:33:22.574212 INFO: [APUAPC] D2_APC_0: 0xffffffff
10046 01:33:22.577019 INFO: [APUAPC] D2_APC_1: 0xffffffff
10047 01:33:22.580468 INFO: [APUAPC] D2_APC_2: 0x3fffff
10048 01:33:22.583935 INFO: [APUAPC] D2_APC_3: 0x0
10049 01:33:22.586881 INFO: [APUAPC] D3_APC_0: 0xffffffff
10050 01:33:22.590904 INFO: [APUAPC] D3_APC_1: 0xffffffff
10051 01:33:22.593966 INFO: [APUAPC] D3_APC_2: 0x3fffff
10052 01:33:22.597233 INFO: [APUAPC] D3_APC_3: 0x0
10053 01:33:22.600593 INFO: [APUAPC] D4_APC_0: 0xffffffff
10054 01:33:22.603594 INFO: [APUAPC] D4_APC_1: 0xffffffff
10055 01:33:22.606864 INFO: [APUAPC] D4_APC_2: 0x3fffff
10056 01:33:22.610373 INFO: [APUAPC] D4_APC_3: 0x0
10057 01:33:22.613551 INFO: [APUAPC] D5_APC_0: 0xffffffff
10058 01:33:22.616463 INFO: [APUAPC] D5_APC_1: 0xffffffff
10059 01:33:22.619961 INFO: [APUAPC] D5_APC_2: 0x3fffff
10060 01:33:22.623387 INFO: [APUAPC] D5_APC_3: 0x0
10061 01:33:22.626660 INFO: [APUAPC] D6_APC_0: 0xffffffff
10062 01:33:22.629859 INFO: [APUAPC] D6_APC_1: 0xffffffff
10063 01:33:22.633134 INFO: [APUAPC] D6_APC_2: 0x3fffff
10064 01:33:22.636783 INFO: [APUAPC] D6_APC_3: 0x0
10065 01:33:22.639932 INFO: [APUAPC] D7_APC_0: 0xffffffff
10066 01:33:22.642891 INFO: [APUAPC] D7_APC_1: 0xffffffff
10067 01:33:22.646225 INFO: [APUAPC] D7_APC_2: 0x3fffff
10068 01:33:22.649427 INFO: [APUAPC] D7_APC_3: 0x0
10069 01:33:22.653150 INFO: [APUAPC] D8_APC_0: 0xffffffff
10070 01:33:22.656818 INFO: [APUAPC] D8_APC_1: 0xffffffff
10071 01:33:22.659784 INFO: [APUAPC] D8_APC_2: 0x3fffff
10072 01:33:22.662693 INFO: [APUAPC] D8_APC_3: 0x0
10073 01:33:22.665990 INFO: [APUAPC] D9_APC_0: 0xffffffff
10074 01:33:22.669456 INFO: [APUAPC] D9_APC_1: 0xffffffff
10075 01:33:22.672624 INFO: [APUAPC] D9_APC_2: 0x3fffff
10076 01:33:22.676001 INFO: [APUAPC] D9_APC_3: 0x0
10077 01:33:22.679644 INFO: [APUAPC] D10_APC_0: 0xffffffff
10078 01:33:22.682444 INFO: [APUAPC] D10_APC_1: 0xffffffff
10079 01:33:22.686353 INFO: [APUAPC] D10_APC_2: 0x3fffff
10080 01:33:22.689676 INFO: [APUAPC] D10_APC_3: 0x0
10081 01:33:22.692346 INFO: [APUAPC] D11_APC_0: 0xffffffff
10082 01:33:22.696287 INFO: [APUAPC] D11_APC_1: 0xffffffff
10083 01:33:22.699284 INFO: [APUAPC] D11_APC_2: 0x3fffff
10084 01:33:22.702464 INFO: [APUAPC] D11_APC_3: 0x0
10085 01:33:22.705728 INFO: [APUAPC] D12_APC_0: 0xffffffff
10086 01:33:22.708766 INFO: [APUAPC] D12_APC_1: 0xffffffff
10087 01:33:22.712768 INFO: [APUAPC] D12_APC_2: 0x3fffff
10088 01:33:22.715663 INFO: [APUAPC] D12_APC_3: 0x0
10089 01:33:22.718746 INFO: [APUAPC] D13_APC_0: 0xffffffff
10090 01:33:22.722123 INFO: [APUAPC] D13_APC_1: 0xffffffff
10091 01:33:22.725663 INFO: [APUAPC] D13_APC_2: 0x3fffff
10092 01:33:22.728891 INFO: [APUAPC] D13_APC_3: 0x0
10093 01:33:22.731960 INFO: [APUAPC] D14_APC_0: 0xffffffff
10094 01:33:22.735765 INFO: [APUAPC] D14_APC_1: 0xffffffff
10095 01:33:22.738859 INFO: [APUAPC] D14_APC_2: 0x3fffff
10096 01:33:22.742547 INFO: [APUAPC] D14_APC_3: 0x0
10097 01:33:22.745499 INFO: [APUAPC] D15_APC_0: 0xffffffff
10098 01:33:22.748669 INFO: [APUAPC] D15_APC_1: 0xffffffff
10099 01:33:22.751705 INFO: [APUAPC] D15_APC_2: 0x3fffff
10100 01:33:22.755068 INFO: [APUAPC] D15_APC_3: 0x0
10101 01:33:22.758659 INFO: [APUAPC] APC_CON: 0x4
10102 01:33:22.762121 INFO: [NOCDAPC] D0_APC_0: 0x0
10103 01:33:22.764944 INFO: [NOCDAPC] D0_APC_1: 0x0
10104 01:33:22.765397 INFO: [NOCDAPC] D1_APC_0: 0x0
10105 01:33:22.768704 INFO: [NOCDAPC] D1_APC_1: 0xfff
10106 01:33:22.772077 INFO: [NOCDAPC] D2_APC_0: 0x0
10107 01:33:22.775320 INFO: [NOCDAPC] D2_APC_1: 0xfff
10108 01:33:22.778453 INFO: [NOCDAPC] D3_APC_0: 0x0
10109 01:33:22.781691 INFO: [NOCDAPC] D3_APC_1: 0xfff
10110 01:33:22.785293 INFO: [NOCDAPC] D4_APC_0: 0x0
10111 01:33:22.788774 INFO: [NOCDAPC] D4_APC_1: 0xfff
10112 01:33:22.791879 INFO: [NOCDAPC] D5_APC_0: 0x0
10113 01:33:22.795035 INFO: [NOCDAPC] D5_APC_1: 0xfff
10114 01:33:22.798344 INFO: [NOCDAPC] D6_APC_0: 0x0
10115 01:33:22.798893 INFO: [NOCDAPC] D6_APC_1: 0xfff
10116 01:33:22.801593 INFO: [NOCDAPC] D7_APC_0: 0x0
10117 01:33:22.804978 INFO: [NOCDAPC] D7_APC_1: 0xfff
10118 01:33:22.808430 INFO: [NOCDAPC] D8_APC_0: 0x0
10119 01:33:22.811356 INFO: [NOCDAPC] D8_APC_1: 0xfff
10120 01:33:22.814686 INFO: [NOCDAPC] D9_APC_0: 0x0
10121 01:33:22.817994 INFO: [NOCDAPC] D9_APC_1: 0xfff
10122 01:33:22.821147 INFO: [NOCDAPC] D10_APC_0: 0x0
10123 01:33:22.824368 INFO: [NOCDAPC] D10_APC_1: 0xfff
10124 01:33:22.827762 INFO: [NOCDAPC] D11_APC_0: 0x0
10125 01:33:22.831234 INFO: [NOCDAPC] D11_APC_1: 0xfff
10126 01:33:22.834797 INFO: [NOCDAPC] D12_APC_0: 0x0
10127 01:33:22.837724 INFO: [NOCDAPC] D12_APC_1: 0xfff
10128 01:33:22.841215 INFO: [NOCDAPC] D13_APC_0: 0x0
10129 01:33:22.844240 INFO: [NOCDAPC] D13_APC_1: 0xfff
10130 01:33:22.844657 INFO: [NOCDAPC] D14_APC_0: 0x0
10131 01:33:22.847417 INFO: [NOCDAPC] D14_APC_1: 0xfff
10132 01:33:22.850638 INFO: [NOCDAPC] D15_APC_0: 0x0
10133 01:33:22.854457 INFO: [NOCDAPC] D15_APC_1: 0xfff
10134 01:33:22.857429 INFO: [NOCDAPC] APC_CON: 0x4
10135 01:33:22.860657 INFO: [APUAPC] set_apusys_apc done
10136 01:33:22.864077 INFO: [DEVAPC] devapc_init done
10137 01:33:22.867804 INFO: GICv3 without legacy support detected.
10138 01:33:22.874028 INFO: ARM GICv3 driver initialized in EL3
10139 01:33:22.877495 INFO: Maximum SPI INTID supported: 639
10140 01:33:22.880458 INFO: BL31: Initializing runtime services
10141 01:33:22.887174 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10142 01:33:22.890274 INFO: SPM: enable CPC mode
10143 01:33:22.893540 INFO: mcdi ready for mcusys-off-idle and system suspend
10144 01:33:22.900212 INFO: BL31: Preparing for EL3 exit to normal world
10145 01:33:22.903644 INFO: Entry point address = 0x80000000
10146 01:33:22.904203 INFO: SPSR = 0x8
10147 01:33:22.910091
10148 01:33:22.910704
10149 01:33:22.911073
10150 01:33:22.913690 Starting depthcharge on Spherion...
10151 01:33:22.914293
10152 01:33:22.914681 Wipe memory regions:
10153 01:33:22.915022
10154 01:33:22.917515 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10155 01:33:22.918090 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10156 01:33:22.918807 Setting prompt string to ['asurada:']
10157 01:33:22.919295 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10158 01:33:22.920039 [0x00000040000000, 0x00000054600000)
10159 01:33:23.039459
10160 01:33:23.040017 [0x00000054660000, 0x00000080000000)
10161 01:33:23.299832
10162 01:33:23.300389 [0x000000821a7280, 0x000000ffe64000)
10163 01:33:24.045019
10164 01:33:24.045580 [0x00000100000000, 0x00000240000000)
10165 01:33:25.934898
10166 01:33:25.938056 Initializing XHCI USB controller at 0x11200000.
10167 01:33:26.976325
10168 01:33:26.979221 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10169 01:33:26.979684
10170 01:33:26.980047
10171 01:33:26.980897 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10173 01:33:27.082319 asurada: tftpboot 192.168.201.1 14173494/tftp-deploy-s3airdeb/kernel/image.itb 14173494/tftp-deploy-s3airdeb/kernel/cmdline
10174 01:33:27.083131 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10175 01:33:27.083681 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10176 01:33:27.087733 tftpboot 192.168.201.1 14173494/tftp-deploy-s3airdeb/kernel/image.itp-deploy-s3airdeb/kernel/cmdline
10177 01:33:27.088174
10178 01:33:27.088531 Waiting for link
10179 01:33:27.246424
10180 01:33:27.246989 R8152: Initializing
10181 01:33:27.247357
10182 01:33:27.249118 Version 6 (ocp_data = 5c30)
10183 01:33:27.249576
10184 01:33:27.252793 R8152: Done initializing
10185 01:33:27.253350
10186 01:33:27.253714 Adding net device
10187 01:33:29.155550
10188 01:33:29.156274 done.
10189 01:33:29.156846
10190 01:33:29.157423 MAC: 00:e0:4c:68:02:81
10191 01:33:29.158063
10192 01:33:29.159188 Sending DHCP discover... done.
10193 01:33:29.159777
10194 01:33:29.161719 Waiting for reply... done.
10195 01:33:29.162420
10196 01:33:29.165266 Sending DHCP request... done.
10197 01:33:29.165828
10198 01:33:29.166254 Waiting for reply... done.
10199 01:33:29.166612
10200 01:33:29.168741 My ip is 192.168.201.14
10201 01:33:29.169302
10202 01:33:29.171676 The DHCP server ip is 192.168.201.1
10203 01:33:29.172139
10204 01:33:29.175164 TFTP server IP predefined by user: 192.168.201.1
10205 01:33:29.175636
10206 01:33:29.181463 Bootfile predefined by user: 14173494/tftp-deploy-s3airdeb/kernel/image.itb
10207 01:33:29.181894
10208 01:33:29.185389 Sending tftp read request... done.
10209 01:33:29.185932
10210 01:33:29.194148 Waiting for the transfer...
10211 01:33:29.194717
10212 01:33:29.905151 00000000 ################################################################
10213 01:33:29.905673
10214 01:33:30.623232 00080000 ################################################################
10215 01:33:30.623749
10216 01:33:31.334786 00100000 ################################################################
10217 01:33:31.335325
10218 01:33:32.050550 00180000 ################################################################
10219 01:33:32.051132
10220 01:33:32.768508 00200000 ################################################################
10221 01:33:32.769072
10222 01:33:33.489324 00280000 ################################################################
10223 01:33:33.489872
10224 01:33:34.194526 00300000 ################################################################
10225 01:33:34.195134
10226 01:33:34.917034 00380000 ################################################################
10227 01:33:34.917561
10228 01:33:35.626745 00400000 ################################################################
10229 01:33:35.627249
10230 01:33:36.350938 00480000 ################################################################
10231 01:33:36.351449
10232 01:33:37.060265 00500000 ################################################################
10233 01:33:37.060788
10234 01:33:37.760513 00580000 ################################################################
10235 01:33:37.761049
10236 01:33:38.472570 00600000 ################################################################
10237 01:33:38.473193
10238 01:33:39.178924 00680000 ################################################################
10239 01:33:39.179491
10240 01:33:39.900551 00700000 ################################################################
10241 01:33:39.901100
10242 01:33:40.601512 00780000 ################################################################
10243 01:33:40.602020
10244 01:33:41.310532 00800000 ################################################################
10245 01:33:41.311201
10246 01:33:42.027219 00880000 ################################################################
10247 01:33:42.027792
10248 01:33:42.733796 00900000 ################################################################
10249 01:33:42.734338
10250 01:33:43.445549 00980000 ################################################################
10251 01:33:43.446096
10252 01:33:44.163220 00a00000 ################################################################
10253 01:33:44.163758
10254 01:33:44.869944 00a80000 ################################################################
10255 01:33:44.870554
10256 01:33:45.585539 00b00000 ################################################################
10257 01:33:45.586037
10258 01:33:46.316475 00b80000 ################################################################
10259 01:33:46.317011
10260 01:33:47.032727 00c00000 ################################################################
10261 01:33:47.033258
10262 01:33:47.746756 00c80000 ################################################################
10263 01:33:47.747268
10264 01:33:48.448573 00d00000 ################################################################
10265 01:33:48.449133
10266 01:33:49.154133 00d80000 ################################################################
10267 01:33:49.154707
10268 01:33:49.875579 00e00000 ################################################################
10269 01:33:49.876129
10270 01:33:50.571010 00e80000 ################################################################
10271 01:33:50.571523
10272 01:33:51.280012 00f00000 ################################################################
10273 01:33:51.280513
10274 01:33:51.987305 00f80000 ################################################################
10275 01:33:51.987879
10276 01:33:52.696502 01000000 ################################################################
10277 01:33:52.697114
10278 01:33:53.414942 01080000 ################################################################
10279 01:33:53.415493
10280 01:33:54.128220 01100000 ################################################################
10281 01:33:54.128747
10282 01:33:54.844982 01180000 ################################################################
10283 01:33:54.845596
10284 01:33:55.539837 01200000 ################################################################
10285 01:33:55.540439
10286 01:33:56.261141 01280000 ################################################################
10287 01:33:56.261820
10288 01:33:56.958033 01300000 ################################################################
10289 01:33:56.958572
10290 01:33:57.662263 01380000 ################################################################
10291 01:33:57.662770
10292 01:33:58.365590 01400000 ################################################################
10293 01:33:58.366189
10294 01:33:59.067850 01480000 ################################################################
10295 01:33:59.068390
10296 01:33:59.773299 01500000 ################################################################
10297 01:33:59.773814
10298 01:34:00.463911 01580000 ################################################################
10299 01:34:00.464434
10300 01:34:01.186621 01600000 ################################################################
10301 01:34:01.187137
10302 01:34:01.884375 01680000 ################################################################
10303 01:34:01.884892
10304 01:34:02.602426 01700000 ################################################################
10305 01:34:02.602973
10306 01:34:03.310353 01780000 ################################################################
10307 01:34:03.310875
10308 01:34:04.027160 01800000 ################################################################
10309 01:34:04.027678
10310 01:34:04.743908 01880000 ################################################################
10311 01:34:04.744412
10312 01:34:05.471947 01900000 ################################################################
10313 01:34:05.472572
10314 01:34:06.168438 01980000 ################################################################
10315 01:34:06.168941
10316 01:34:06.883489 01a00000 ################################################################
10317 01:34:06.884019
10318 01:34:07.603747 01a80000 ################################################################
10319 01:34:07.604333
10320 01:34:08.309558 01b00000 ################################################################
10321 01:34:08.310071
10322 01:34:09.022420 01b80000 ################################################################
10323 01:34:09.022927
10324 01:34:09.722224 01c00000 ################################################################
10325 01:34:09.722739
10326 01:34:10.425451 01c80000 ################################################################
10327 01:34:10.425982
10328 01:34:11.146323 01d00000 ################################################################
10329 01:34:11.146909
10330 01:34:11.856644 01d80000 ################################################################
10331 01:34:11.857167
10332 01:34:12.388657 01e00000 ################################################ done.
10333 01:34:12.389177
10334 01:34:12.392216 The bootfile was 31843562 bytes long.
10335 01:34:12.392640
10336 01:34:12.395061 Sending tftp read request... done.
10337 01:34:12.395479
10338 01:34:12.398631 Waiting for the transfer...
10339 01:34:12.399048
10340 01:34:12.401657 00000000 # done.
10341 01:34:12.402093
10342 01:34:12.408451 Command line loaded dynamically from TFTP file: 14173494/tftp-deploy-s3airdeb/kernel/cmdline
10343 01:34:12.408946
10344 01:34:12.431917 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10345 01:34:12.432455
10346 01:34:12.432789 Loading FIT.
10347 01:34:12.433096
10348 01:34:12.434634 Image ramdisk-1 has 18734352 bytes.
10349 01:34:12.435051
10350 01:34:12.438227 Image fdt-1 has 47258 bytes.
10351 01:34:12.438741
10352 01:34:12.441278 Image kernel-1 has 13059919 bytes.
10353 01:34:12.441698
10354 01:34:12.451226 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10355 01:34:12.451721
10356 01:34:12.467908 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10357 01:34:12.468425
10358 01:34:12.471744 Choosing best match conf-1 for compat google,spherion-rev2.
10359 01:34:12.477035
10360 01:34:12.480875 Connected to device vid:did:rid of 1ae0:0028:00
10361 01:34:12.488347
10362 01:34:12.491132 tpm_get_response: command 0x17b, return code 0x0
10363 01:34:12.491554
10364 01:34:12.494608 ec_init: CrosEC protocol v3 supported (256, 248)
10365 01:34:12.498937
10366 01:34:12.502035 tpm_cleanup: add release locality here.
10367 01:34:12.502496
10368 01:34:12.502829 Shutting down all USB controllers.
10369 01:34:12.505071
10370 01:34:12.505483 Removing current net device
10371 01:34:12.505808
10372 01:34:12.512121 Exiting depthcharge with code 4 at timestamp: 79069024
10373 01:34:12.512637
10374 01:34:12.515064 LZMA decompressing kernel-1 to 0x821a6718
10375 01:34:12.515482
10376 01:34:12.518278 LZMA decompressing kernel-1 to 0x40000000
10377 01:34:14.127732
10378 01:34:14.128233 jumping to kernel
10379 01:34:14.129814 end: 2.2.4 bootloader-commands (duration 00:00:51) [common]
10380 01:34:14.130350 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10381 01:34:14.130737 Setting prompt string to ['Linux version [0-9]']
10382 01:34:14.131080 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10383 01:34:14.131423 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10384 01:34:14.211155
10385 01:34:14.214145 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10386 01:34:14.218071 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10387 01:34:14.218603 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10388 01:34:14.218968 Setting prompt string to []
10389 01:34:14.219343 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10390 01:34:14.219703 Using line separator: #'\n'#
10391 01:34:14.220031 No login prompt set.
10392 01:34:14.220352 Parsing kernel messages
10393 01:34:14.220656 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10394 01:34:14.221242 [login-action] Waiting for messages, (timeout 00:03:35)
10395 01:34:14.221595 Waiting using forced prompt support (timeout 00:01:48)
10396 01:34:14.237288 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10397 01:34:14.240846 [ 0.000000] random: crng init done
10398 01:34:14.246983 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10399 01:34:14.250211 [ 0.000000] efi: UEFI not found.
10400 01:34:14.256772 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10401 01:34:14.266678 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10402 01:34:14.276667 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10403 01:34:14.283304 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10404 01:34:14.290281 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10405 01:34:14.296412 [ 0.000000] printk: bootconsole [mtk8250] enabled
10406 01:34:14.303530 [ 0.000000] NUMA: No NUMA configuration found
10407 01:34:14.309935 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10408 01:34:14.316690 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10409 01:34:14.317247 [ 0.000000] Zone ranges:
10410 01:34:14.322867 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10411 01:34:14.326480 [ 0.000000] DMA32 empty
10412 01:34:14.333308 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10413 01:34:14.336746 [ 0.000000] Movable zone start for each node
10414 01:34:14.339675 [ 0.000000] Early memory node ranges
10415 01:34:14.346131 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10416 01:34:14.353241 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10417 01:34:14.359297 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10418 01:34:14.366099 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10419 01:34:14.373083 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10420 01:34:14.378979 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10421 01:34:14.435865 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10422 01:34:14.442840 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10423 01:34:14.449047 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10424 01:34:14.452365 [ 0.000000] psci: probing for conduit method from DT.
10425 01:34:14.458894 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10426 01:34:14.462104 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10427 01:34:14.468903 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10428 01:34:14.471823 [ 0.000000] psci: SMC Calling Convention v1.2
10429 01:34:14.478426 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10430 01:34:14.481861 [ 0.000000] Detected VIPT I-cache on CPU0
10431 01:34:14.488018 [ 0.000000] CPU features: detected: GIC system register CPU interface
10432 01:34:14.494867 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10433 01:34:14.501359 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10434 01:34:14.508249 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10435 01:34:14.518073 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10436 01:34:14.524563 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10437 01:34:14.527588 [ 0.000000] alternatives: applying boot alternatives
10438 01:34:14.534722 [ 0.000000] Fallback order for Node 0: 0
10439 01:34:14.541738 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10440 01:34:14.544376 [ 0.000000] Policy zone: Normal
10441 01:34:14.567555 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10442 01:34:14.577416 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10443 01:34:14.589216 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10444 01:34:14.598599 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10445 01:34:14.605165 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10446 01:34:14.608436 <6>[ 0.000000] software IO TLB: area num 8.
10447 01:34:14.665555 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10448 01:34:14.814279 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10449 01:34:14.820810 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10450 01:34:14.827807 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10451 01:34:14.830450 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10452 01:34:14.837385 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10453 01:34:14.843784 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10454 01:34:14.850614 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10455 01:34:14.857283 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10456 01:34:14.863869 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10457 01:34:14.870136 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10458 01:34:14.876621 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10459 01:34:14.880037 <6>[ 0.000000] GICv3: 608 SPIs implemented
10460 01:34:14.883325 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10461 01:34:14.889896 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10462 01:34:14.893219 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10463 01:34:14.900182 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10464 01:34:14.912964 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10465 01:34:14.926467 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10466 01:34:14.932895 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10467 01:34:14.941281 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10468 01:34:14.954078 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10469 01:34:14.960644 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10470 01:34:14.967596 <6>[ 0.009180] Console: colour dummy device 80x25
10471 01:34:14.977191 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10472 01:34:14.983937 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10473 01:34:14.987789 <6>[ 0.029219] LSM: Security Framework initializing
10474 01:34:14.993681 <6>[ 0.034185] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10475 01:34:15.003996 <6>[ 0.041999] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10476 01:34:15.013587 <6>[ 0.051400] cblist_init_generic: Setting adjustable number of callback queues.
10477 01:34:15.017185 <6>[ 0.058844] cblist_init_generic: Setting shift to 3 and lim to 1.
10478 01:34:15.026838 <6>[ 0.065181] cblist_init_generic: Setting adjustable number of callback queues.
10479 01:34:15.033207 <6>[ 0.072654] cblist_init_generic: Setting shift to 3 and lim to 1.
10480 01:34:15.036844 <6>[ 0.079130] rcu: Hierarchical SRCU implementation.
10481 01:34:15.043433 <6>[ 0.079132] rcu: Max phase no-delay instances is 1000.
10482 01:34:15.050218 <6>[ 0.079155] printk: bootconsole [mtk8250] printing thread started
10483 01:34:15.056215 <6>[ 0.097449] EFI services will not be available.
10484 01:34:15.059795 <6>[ 0.097625] smp: Bringing up secondary CPUs ...
10485 01:34:15.066296 <6>[ 0.097924] Detected VIPT I-cache on CPU1
10486 01:34:15.072718 <6>[ 0.097990] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10487 01:34:15.079649 <6>[ 0.098022] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10488 01:34:15.089302 <6>[ 0.125899] Detected VIPT I-cache on CPU2
10489 01:34:15.095709 <6>[ 0.125951] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10490 01:34:15.106159 <6>[ 0.125968] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10491 01:34:15.108774 <6>[ 0.126221] Detected VIPT I-cache on CPU3
10492 01:34:15.115785 <6>[ 0.126270] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10493 01:34:15.122807 <6>[ 0.126285] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10494 01:34:15.125330 <6>[ 0.126593] CPU features: detected: Spectre-v4
10495 01:34:15.131874 <6>[ 0.126599] CPU features: detected: Spectre-BHB
10496 01:34:15.135319 <6>[ 0.126604] Detected PIPT I-cache on CPU4
10497 01:34:15.141821 <6>[ 0.126663] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10498 01:34:15.148823 <6>[ 0.126678] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10499 01:34:15.155235 <6>[ 0.126967] Detected PIPT I-cache on CPU5
10500 01:34:15.162044 <6>[ 0.127027] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10501 01:34:15.168657 <6>[ 0.127043] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10502 01:34:15.171835 <6>[ 0.127314] Detected PIPT I-cache on CPU6
10503 01:34:15.178434 <6>[ 0.127378] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10504 01:34:15.189160 <6>[ 0.127393] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10505 01:34:15.191954 <6>[ 0.127679] Detected PIPT I-cache on CPU7
10506 01:34:15.198891 <6>[ 0.127743] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10507 01:34:15.206102 <6>[ 0.127759] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10508 01:34:15.208701 <6>[ 0.127805] smp: Brought up 1 node, 8 CPUs
10509 01:34:15.215474 <6>[ 0.127809] SMP: Total of 8 processors activated.
10510 01:34:15.223136 <6>[ 0.127812] CPU features: detected: 32-bit EL0 Support
10511 01:34:15.228577 <6>[ 0.127814] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10512 01:34:15.235111 <6>[ 0.127816] CPU features: detected: Common not Private translations
10513 01:34:15.241877 <6>[ 0.127818] CPU features: detected: CRC32 instructions
10514 01:34:15.248171 <6>[ 0.127821] CPU features: detected: RCpc load-acquire (LDAPR)
10515 01:34:15.251204 <6>[ 0.127823] CPU features: detected: LSE atomic instructions
10516 01:34:15.257753 <6>[ 0.127824] CPU features: detected: Privileged Access Never
10517 01:34:15.264426 <6>[ 0.127826] CPU features: detected: RAS Extension Support
10518 01:34:15.271294 <6>[ 0.127829] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10519 01:34:15.274494 <6>[ 0.127897] CPU: All CPU(s) started at EL2
10520 01:34:15.280721 <6>[ 0.127898] alternatives: applying system-wide alternatives
10521 01:34:15.284052 <6>[ 0.141122] devtmpfs: initialized
10522 01:34:15.294139 <6>[ 0.147457] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10523 01:34:15.300298 <6>[ 0.147468] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10524 01:34:15.306993 <6>[ 0.148091] pinctrl core: initialized pinctrl subsystem
10525 01:34:15.310315 <6>[ 0.149270] DMI not present or invalid.
10526 01:34:15.316641 <6>[ 0.149580] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10527 01:34:15.323365 <6>[ 0.150309] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10528 01:34:15.333619 <6>[ 0.150508] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10529 01:34:15.358259 <6>[ < 0.400158] printk: console [ttyS0] printing thread started
10530 01:34:15.368350 6>[ 0.150655] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10531 01:34:15.374956 <6>[ 0.400174] printk: console [ttyS0] enabled
10532 01:34:15.378294 <6>[ 0.400176] printk: bootconsole [mtk8250] disabled
10533 01:34:15.384982 <6>[ 0.414280] printk: bootconsole [mtk8250] printing thread stopped
10534 01:34:15.391643 <6>[ 0.415597] SuperH (H)SCI(F) driver initialized
10535 01:34:15.394709 <6>[ 0.416057] msm_serial: driver initialized
10536 01:34:15.404811 <6>[ 0.420678] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10537 01:34:15.411272 <6>[ 0.420708] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10538 01:34:15.422484 <6>[ 0.420740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10539 01:34:15.428556 <6>[ 0.420770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10540 01:34:15.439902 <6>[ 0.420791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10541 01:34:15.452333 <6>[ 0.420819] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10542 01:34:15.468742 <6>[ 0.420846] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10543 01:34:15.469834 <6>[ 0.420971] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10544 01:34:15.474648 <6>[ 0.420999] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10545 01:34:15.482510 <6>[ 0.429799] loop: module loaded
10546 01:34:15.483613 <6>[ 0.432345] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10547 01:34:15.490502 <4>[ 0.449247] mtk-pmic-keys: Failed to locate of_node [id: -1]
10548 01:34:15.490979 <6>[ 0.450127] megasas: 07.719.03.00-rc1
10549 01:34:15.497061 <6>[ 0.460150] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10550 01:34:15.503765 <6>[ 0.468070] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10551 01:34:15.510279 <6>[ 0.480020] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10552 01:34:15.520838 <6>[ 0.538780] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10553 01:34:16.019064 <6>[ 1.060439] Freeing initrd memory: 18288K
10554 01:34:16.026745 <6>[ 1.067996] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10555 01:34:16.033373 <6>[ 1.072585] tun: Universal TUN/TAP device driver, 1.6
10556 01:34:16.036848 <6>[ 1.073334] thunder_xcv, ver 1.0
10557 01:34:16.040109 <6>[ 1.073351] thunder_bgx, ver 1.0
10558 01:34:16.043497 <6>[ 1.073364] nicpf, ver 1.0
10559 01:34:16.049992 <6>[ 1.074402] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10560 01:34:16.056733 <6>[ 1.074405] hns3: Copyright (c) 2017 Huawei Corporation.
10561 01:34:16.059753 <6>[ 1.074428] hclge is initializing
10562 01:34:16.066574 <6>[ 1.074441] e1000: Intel(R) PRO/1000 Network Driver
10563 01:34:16.070128 <6>[ 1.074443] e1000: Copyright (c) 1999-2006 Intel Corporation.
10564 01:34:16.076490 <6>[ 1.074459] e1000e: Intel(R) PRO/1000 Network Driver
10565 01:34:16.084101 <6>[ 1.074460] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10566 01:34:16.087141 <6>[ 1.074479] igb: Intel(R) Gigabit Ethernet Network Driver
10567 01:34:16.093954 <6>[ 1.074481] igb: Copyright (c) 2007-2014 Intel Corporation.
10568 01:34:16.100555 <6>[ 1.074495] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10569 01:34:16.107278 <6>[ 1.074497] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10570 01:34:16.111036 <6>[ 1.074786] sky2: driver version 1.30
10571 01:34:16.117745 <6>[ 1.075781] usbcore: registered new device driver r8152-cfgselector
10572 01:34:16.124356 <6>[ 1.075797] usbcore: registered new interface driver r8152
10573 01:34:16.127928 <6>[ 1.075870] VFIO - User Level meta-driver version: 0.3
10574 01:34:16.134970 <6>[ 1.078675] usbcore: registered new interface driver usb-storage
10575 01:34:16.140831 <6>[ 1.078855] usbcore: registered new device driver onboard-usb-hub
10576 01:34:16.147312 <6>[ 1.081595] mt6397-rtc mt6359-rtc: registered as rtc0
10577 01:34:16.153897 <6>[ 1.081743] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T01:34:15 UTC (1717551255)
10578 01:34:16.160686 <6>[ 1.082350] i2c_dev: i2c /dev entries driver
10579 01:34:16.167181 <6>[ 1.089466] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10580 01:34:16.173616 <4>[ 1.090184] cpu cpu0: supply cpu not found, using dummy regulator
10581 01:34:16.180605 <4>[ 1.090279] cpu cpu1: supply cpu not found, using dummy regulator
10582 01:34:16.186791 <4>[ 1.090332] cpu cpu2: supply cpu not found, using dummy regulator
10583 01:34:16.193683 <4>[ 1.090385] cpu cpu3: supply cpu not found, using dummy regulator
10584 01:34:16.200289 <4>[ 1.090432] cpu cpu4: supply cpu not found, using dummy regulator
10585 01:34:16.206586 <4>[ 1.090485] cpu cpu5: supply cpu not found, using dummy regulator
10586 01:34:16.213899 <4>[ 1.090556] cpu cpu6: supply cpu not found, using dummy regulator
10587 01:34:16.216518 <4>[ 1.090606] cpu cpu7: supply cpu not found, using dummy regulator
10588 01:34:16.223467 <6>[ 1.104820] cpu cpu0: EM: created perf domain
10589 01:34:16.226753 <6>[ 1.105135] cpu cpu4: EM: created perf domain
10590 01:34:16.233071 <6>[ 1.106902] sdhci: Secure Digital Host Controller Interface driver
10591 01:34:16.240274 <6>[ 1.106903] sdhci: Copyright(c) Pierre Ossman
10592 01:34:16.242906 <6>[ 1.107255] Synopsys Designware Multimedia Card Interface Driver
10593 01:34:16.249790 <6>[ 1.107620] sdhci-pltfm: SDHCI platform and OF driver helper
10594 01:34:16.253243 <6>[ 1.112288] mmc0: CQHCI version 5.10
10595 01:34:16.259373 <6>[ 1.118126] ledtrig-cpu: registered to indicate activity on CPUs
10596 01:34:16.266631 <6>[ 1.118970] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10597 01:34:16.272922 <6>[ 1.119244] usbcore: registered new interface driver usbhid
10598 01:34:16.276076 <6>[ 1.119245] usbhid: USB HID core driver
10599 01:34:16.283155 <6>[ 1.119359] spi_master spi0: will run message pump with realtime priority
10600 01:34:16.295821 <6>[ 1.152467] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10601 01:34:16.309546 <6>[ 1.155111] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10602 01:34:16.316438 <6>[ 1.155965] cros-ec-spi spi0.0: Chrome EC device registered
10603 01:34:16.325491 <6>[ 1.174192] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10604 01:34:16.332547 <6>[ 1.176552] NET: Registered PF_PACKET protocol family
10605 01:34:16.335334 <6>[ 1.176649] 9pnet: Installing 9P2000 support
10606 01:34:16.339341 <5>[ 1.176711] Key type dns_resolver registered
10607 01:34:16.345311 <6>[ 1.177078] registered taskstats version 1
10608 01:34:16.348645 <5>[ 1.177094] Loading compiled-in X.509 certificates
10609 01:34:16.358488 <4>[ 1.194206] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 01:34:16.369052 <4>[ 1.194372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 01:34:16.375590 <6>[ 1.203803] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10612 01:34:16.382053 <6>[ 1.205163] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10613 01:34:16.388538 <6>[ 1.205965] xhci-mtk 11200000.usb: xHCI Host Controller
10614 01:34:16.395163 <6>[ 1.205993] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10615 01:34:16.405219 <6>[ 1.206246] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10616 01:34:16.411667 <6>[ 1.206319] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10617 01:34:16.415033 <6>[ 1.206473] xhci-mtk 11200000.usb: xHCI Host Controller
10618 01:34:16.425139 <6>[ 1.206488] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10619 01:34:16.431825 <6>[ 1.206502] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10620 01:34:16.434840 <6>[ 1.207251] hub 1-0:1.0: USB hub found
10621 01:34:16.438004 <6>[ 1.207291] hub 1-0:1.0: 1 port detected
10622 01:34:16.447971 <6>[ 1.207653] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10623 01:34:16.451039 <6>[ 1.208242] hub 2-0:1.0: USB hub found
10624 01:34:16.454874 <6>[ 1.208276] hub 2-0:1.0: 1 port detected
10625 01:34:16.461396 <6>[ 1.213555] mtk-msdc 11f70000.mmc: Got CD GPIO
10626 01:34:16.464620 <6>[ 1.214413] mmc0: Command Queue Engine enabled
10627 01:34:16.471387 <6>[ 1.214422] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10628 01:34:16.477919 <6>[ 1.214946] mmcblk0: mmc0:0001 DA4128 116 GiB
10629 01:34:16.481497 <6>[ 1.218768] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10630 01:34:16.487972 <6>[ 1.220169] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10631 01:34:16.494430 <6>[ 1.220980] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10632 01:34:16.501728 <6>[ 1.221900] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10633 01:34:16.507505 <6>[ 1.230202] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10634 01:34:16.513897 <6>[ 1.230209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10635 01:34:16.523860 <4>[ 1.230372] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10636 01:34:16.534080 <6>[ 1.231001] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10637 01:34:16.540226 <6>[ 1.231004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10638 01:34:16.546914 <6>[ 1.231120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10639 01:34:16.556664 <6>[ 1.231134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10640 01:34:16.563510 <6>[ 1.231138] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10641 01:34:16.573242 <6>[ 1.231144] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10642 01:34:16.580287 <6>[ 1.232545] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10643 01:34:16.590245 <6>[ 1.232565] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10644 01:34:16.596496 <6>[ 1.232570] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10645 01:34:16.606673 <6>[ 1.232576] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10646 01:34:16.612836 <6>[ 1.232582] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10647 01:34:16.622805 <6>[ 1.232588] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10648 01:34:16.632610 <6>[ 1.232594] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10649 01:34:16.639274 <6>[ 1.232599] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10650 01:34:16.649170 <6>[ 1.232605] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10651 01:34:16.656092 <6>[ 1.232611] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10652 01:34:16.666616 <6>[ 1.232616] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10653 01:34:16.672340 <6>[ 1.232622] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10654 01:34:16.682283 <6>[ 1.232628] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10655 01:34:16.688853 <6>[ 1.232634] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10656 01:34:16.698951 <6>[ 1.232640] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10657 01:34:16.705666 <6>[ 1.233196] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10658 01:34:16.712205 <6>[ 1.234103] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10659 01:34:16.719276 <6>[ 1.234692] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10660 01:34:16.725385 <6>[ 1.235355] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10661 01:34:16.732124 <6>[ 1.235984] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10662 01:34:16.738798 <6>[ 1.236179] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10663 01:34:16.748589 <6>[ 1.236197] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10664 01:34:16.758291 <6>[ 1.236204] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10665 01:34:16.767855 <6>[ 1.236210] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10666 01:34:16.778233 <6>[ 1.236216] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10667 01:34:16.787867 <6>[ 1.236223] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10668 01:34:16.794448 <6>[ 1.236229] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10669 01:34:16.804465 <6>[ 1.236235] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10670 01:34:16.814799 <6>[ 1.236240] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10671 01:34:16.824565 <6>[ 1.236248] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10672 01:34:16.833989 <6>[ 1.236252] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10673 01:34:16.844129 <6>[ 1.236715] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10674 01:34:16.850609 <6>[ 1.249451] Trying to probe devices needed for running init ...
10675 01:34:16.857604 <6>[ 1.620848] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10676 01:34:16.860591 <6>[ 1.777015] hub 1-1:1.0: USB hub found
10677 01:34:16.863759 <6>[ 1.777376] hub 1-1:1.0: 4 ports detected
10678 01:34:16.867528 <6>[ 1.780624] hub 1-1:1.0: USB hub found
10679 01:34:16.873945 <6>[ 1.780942] hub 1-1:1.0: 4 ports detected
10680 01:34:16.880524 <6>[ 1.905041] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10681 01:34:16.894978 <6>[ 1.934006] hub 2-1:1.0: USB hub found
10682 01:34:16.898223 <6>[ 1.934431] hub 2-1:1.0: 3 ports detected
10683 01:34:16.901345 <6>[ 1.936808] hub 2-1:1.0: USB hub found
10684 01:34:16.904472 <6>[ 1.937142] hub 2-1:1.0: 3 ports detected
10685 01:34:17.062428 <6>[ 2.096979] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10686 01:34:17.183114 <6>[ 2.224427] hub 1-1.4:1.0: USB hub found
10687 01:34:17.186101 <6>[ 2.224852] hub 1-1.4:1.0: 2 ports detected
10688 01:34:17.189561 <6>[ 2.228363] hub 1-1.4:1.0: USB hub found
10689 01:34:17.196182 <6>[ 2.228722] hub 1-1.4:1.0: 2 ports detected
10690 01:34:17.266323 <6>[ 2.301126] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10691 01:34:17.369848 <6>[ 2.405497] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10692 01:34:17.398524 <4>[ 2.432753] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10693 01:34:17.408290 <4>[ 2.432772] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10694 01:34:17.426755 <6>[ 2.466318] r8152 2-1.3:1.0 eth0: v1.12.13
10695 01:34:17.485875 <6>[ 2.520768] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10696 01:34:17.670348 <6>[ 2.704960] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10697 01:34:19.034286 <6>[ 4.072927] r8152 2-1.3:1.0 eth0: carrier on
10698 01:34:21.238357 <5>[ 4.100903] Sending DHCP requests .., OK
10699 01:34:21.244871 <6>[ 6.276907] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10700 01:34:21.251761 Loading, please <6>[ 6.276925] IP-Config: Complete:
10701 01:34:21.252211 wait...
10702 01:34:21.261481 <6>[ 6.276927] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10703 01:34:21.271243 <6>[ 6.276937] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10704 01:34:21.278141 <6>[ 6.276942] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10705 01:34:21.281355 <6>[ 6.276948] nameserver0=192.168.201.1
10706 01:34:21.287743 Starting systemd<6>[ 6.277230] clk: Disabling unused clocks
10707 01:34:21.291151 -udevd version 2<6>[ 6.278261] ALSA device list:
10708 01:34:21.294480 52.22-1~deb12u1
10709 01:34:21.298055 <6>[ 6.278274] No soundcards found.
10710 01:34:21.298659
10711 01:34:21.304491 <6>[ 6.282586] Freeing unused kernel memory: 8512K
10712 01:34:21.307706 <6>[ 6.282778] Run /init as init process
10713 01:34:21.522327 <6>[ 6.559783] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10714 01:34:21.531541 <6>[ 6.559888] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10715 01:34:21.538560 <6>[ 6.559898] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10716 01:34:21.547845 <6>[ 6.565681] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10717 01:34:21.571035 <6>[ 6.604357] remoteproc remoteproc0: scp is available
10718 01:34:21.577097 <6>[ 6.604510] remoteproc remoteproc0: powering up scp
10719 01:34:21.583574 <6>[ 6.604525] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10720 01:34:21.590442 <6>[ 6.604594] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10721 01:34:21.597600 <4>[ 6.634359] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10722 01:34:21.603946 <4>[ 6.635341] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10723 01:34:21.613348 <3>[ 6.641543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 01:34:21.620060 <3>[ 6.641573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 01:34:21.630237 <3>[ 6.641583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 01:34:21.636529 <3>[ 6.647020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 01:34:21.646259 <3>[ 6.647053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 01:34:21.653199 <3>[ 6.647057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 01:34:21.663181 <3>[ 6.647063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 01:34:21.670405 <3>[ 6.647067] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 01:34:21.674063 <6>[ 6.651213] mc: Linux media interface: v0.10
10732 01:34:21.683779 <3>[ 6.653549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 01:34:21.690238 <3>[ 6.671768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 01:34:21.696676 <3>[ 6.671829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 01:34:21.707371 <3>[ 6.671833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 01:34:21.713878 <3>[ 6.671942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 01:34:21.723922 <3>[ 6.671947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 01:34:21.730489 <3>[ 6.671949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 01:34:21.740532 <3>[ 6.671954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 01:34:21.747084 <3>[ 6.671958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 01:34:21.753749 <3>[ 6.672017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 01:34:21.763486 <6>[ 6.674485] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10743 01:34:21.770047 <6>[ 6.686344] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10744 01:34:21.776532 <6>[ 6.686393] pci_bus 0000:00: root bus resource [bus 00-ff]
10745 01:34:21.783318 <6>[ 6.686408] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10746 01:34:21.793326 <6>[ 6.686417] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10747 01:34:21.799977 <6>[ 6.686532] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10748 01:34:21.806767 <6>[ 6.686583] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10749 01:34:21.809833 <6>[ 6.686789] pci 0000:00:00.0: supports D1 D2
10750 01:34:21.816270 <6>[ 6.686801] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10751 01:34:21.822903 <6>[ 6.688852] videodev: Linux video capture interface: v2.00
10752 01:34:21.833156 <6>[ 6.695280] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10753 01:34:21.837041 <6>[ 6.701248] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10754 01:34:21.846413 <6>[ 6.701297] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10755 01:34:21.852635 <6>[ 6.701319] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10756 01:34:21.859261 <6>[ 6.701334] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10757 01:34:21.866208 <6>[ 6.701468] pci 0000:01:00.0: supports D1 D2
10758 01:34:21.872284 <6>[ 6.701470] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10759 01:34:21.879317 <4>[ 6.701709] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10760 01:34:21.885752 <4>[ 6.701709] Fallback method does not support PEC.
10761 01:34:21.892644 <6>[ 6.716778] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10762 01:34:21.898927 <6>[ 6.716822] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10763 01:34:21.909050 <6>[ 6.716825] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10764 01:34:21.915225 <6>[ 6.716834] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10765 01:34:21.925333 <6>[ 6.716847] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10766 01:34:21.932125 <6>[ 6.716859] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10767 01:34:21.938810 <6>[ 6.716871] pci 0000:00:00.0: PCI bridge to [bus 01]
10768 01:34:21.945177 <6>[ 6.716875] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10769 01:34:21.951717 <6>[ 6.717033] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10770 01:34:21.958288 <6>[ 6.717604] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10771 01:34:21.965144 <6>[ 6.718062] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10772 01:34:21.971741 <3>[ 6.718672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10773 01:34:21.978066 <6>[ 6.730011] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10774 01:34:21.987753 <6>[ 6.730077] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10775 01:34:21.994805 <6>[ 6.730085] remoteproc remoteproc0: remote processor scp is now up
10776 01:34:22.004379 <6>[ 6.745269] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10777 01:34:22.010823 <6>[ 6.747188] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10778 01:34:22.020896 <6>[ 6.749255] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10779 01:34:22.027349 <3>[ 6.752475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 01:34:22.037172 <6>[ 6.753440] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10781 01:34:22.047512 <6>[ 6.753696] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10782 01:34:22.057841 <5>[ 6.780738] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10783 01:34:22.060581 <6>[ 6.786890] Bluetooth: Core ver 2.22
10784 01:34:22.064224 <6>[ 6.786970] NET: Registered PF_BLUETOOTH protocol family
10785 01:34:22.070754 <6>[ 6.786971] Bluetooth: HCI device and connection manager initialized
10786 01:34:22.077221 <6>[ 6.786992] Bluetooth: HCI socket layer initialized
10787 01:34:22.083373 <6>[ 6.786997] Bluetooth: L2CAP socket layer initialized
10788 01:34:22.087663 <6>[ 6.787005] Bluetooth: SCO socket layer initialized
10789 01:34:22.093676 <5>[ 6.795339] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10790 01:34:22.104026 <5>[ 6.795888] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10791 01:34:22.110480 <4>[ 6.795971] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10792 01:34:22.116362 <6>[ 6.795980] cfg80211: failed to load regulatory.db
10793 01:34:22.123175 <6>[ 6.818732] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10794 01:34:22.136900 <6>[ 6.819796] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10795 01:34:22.143038 <6>[ 6.819912] usbcore: registered new interface driver uvcvideo
10796 01:34:22.146697 <6>[ 6.858637] usbcore: registered new interface driver btusb
10797 01:34:22.153188 <6>[ 6.858719] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10798 01:34:22.163122 <4>[ 6.859673] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10799 01:34:22.169387 <3>[ 6.859684] Bluetooth: hci0: Failed to load firmware file (-2)
10800 01:34:22.176128 <3>[ 6.859686] Bluetooth: hci0: Failed to set up firmware (-2)
10801 01:34:22.186105 <4>[ 6.859688] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10802 01:34:22.192673 <6>[ 6.897333] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10803 01:34:22.199583 <6>[ 6.897433] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10804 01:34:22.205902 <6>[ 6.916839] mt7921e 0000:01:00.0: ASIC revision: 79610010
10805 01:34:22.215863 <6>[ 7.016270] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10806 01:34:22.216494 <6>[ 7.016270]
10807 01:34:22.218974 Begin: Loading essential drivers ... done.
10808 01:34:22.225673 Begin: Running /scripts/init-premount ... done.
10809 01:34:22.235760 Begin: Mounting roo<6>[ 7.272259] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10810 01:34:22.239270 t file system ... Begin: Running /scripts/nfs-top ... done.
10811 01:34:22.248474 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10812 01:34:22.252009 Device /sys/class/net/eth0 found
10813 01:34:22.252563 done.
10814 01:34:22.258557 Begin: Waiting up to 180 secs for any network device to become available ... done.
10815 01:34:22.318743 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10816 01:34:22.326288 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10817 01:34:22.332696 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10818 01:34:22.339344 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10819 01:34:22.346280 host : mt8192-asurada-spherion-r0-cbg-9
10820 01:34:22.352416 domain : lava-rack
10821 01:34:22.355566 rootserver: 192.168.201.1 rootpath:
10822 01:34:22.358914 filename :
10823 01:34:22.519038 done.
10824 01:34:22.527566 Begin: Running /scripts/nfs-bottom ... done.
10825 01:34:22.543093 Begin: Running /scripts/init-bottom ... done.
10826 01:34:23.897738 <6>[ 8.939962] NET: Registered PF_INET6 protocol family
10827 01:34:23.901144 <6>[ 8.941934] Segment Routing with IPv6
10828 01:34:23.907571 <6>[ 8.941951] In-situ OAM (IOAM) with IPv6
10829 01:34:24.072276 <30>[ 9.087873] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10830 01:34:24.078823 <30>[ 9.087913] systemd[1]: Detected architecture arm64.
10831 01:34:24.078916
10832 01:34:24.085247 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10833 01:34:24.085328
10834 01:34:24.113443 <30>[ 9.154555] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10835 01:34:25.313354 <30>[ 10.349872] systemd[1]: Queued start job for default target graphical.target.
10836 01:34:25.346707 [[0;32m OK [0m] Created slic<30>[ 10.382223] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10837 01:34:25.351463 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10838 01:34:25.375131 [[0;32m OK [0m] Created slic<30>[ 10.410722] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10839 01:34:25.378951 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10840 01:34:25.402865 [[0;32m OK [0m] Created slic<30>[ 10.438705] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10841 01:34:25.409317 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10842 01:34:25.430396 [[0;32m OK [0m] Created slic<30>[ 10.466341] systemd[1]: Created slice user.slice - User and Session Slice.
10843 01:34:25.433342 e [0;1;39muser.slice[0m - User and Session Slice.
10844 01:34:25.460768 [[0;32m OK [0m] Started [0;<30>[ 10.493816] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10845 01:34:25.464272 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10846 01:34:25.488380 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 10.521201] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10847 01:34:25.491489 -passwo… Requests to Wall Directory Watch.
10848 01:34:25.523909 Expecting device [0;1;<30>[ 10.549624] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10849 01:34:25.530224 <30>[ 10.549804] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10850 01:34:25.536570 39mdev-ttyS0.device[0m - /dev/ttyS0...
10851 01:34:25.557414 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 10.593344] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10852 01:34:25.560787 tsetup.…get[0m - Local Encrypted Volumes.
10853 01:34:25.588209 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 10.621042] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10854 01:34:25.591476 grityse…Local Integrity Protected Volumes.
10855 01:34:25.613675 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 10.649496] systemd[1]: Reached target paths.target - Path Units.
10856 01:34:25.614287 s.target[0m - Path Units.
10857 01:34:25.637952 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 10.673399] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10858 01:34:25.640552 te-fs.target[0m - Remote File Systems.
10859 01:34:25.661051 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 10.696955] systemd[1]: Reached target slices.target - Slice Units.
10860 01:34:25.663805 es.target[0m - Slice Units.
10861 01:34:25.685574 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 10.721426] systemd[1]: Reached target swap.target - Swaps.
10862 01:34:25.686139 .target[0m - Swaps.
10863 01:34:25.709992 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 10.745481] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10864 01:34:25.716109 tysetup… - Local Verity Protected Volumes.
10865 01:34:25.740367 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.773489] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10866 01:34:25.743762 d-initc… initctl Compatibility Named Pipe.
10867 01:34:25.768190 [[0;32m OK [<30>[ 10.804326] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10868 01:34:25.774555 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10869 01:34:25.794980 [[0;32m OK [0m] Listening on<30>[ 10.830575] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10870 01:34:25.801240 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10871 01:34:25.821582 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.857684] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10872 01:34:25.825244 d-journald.socket[0m - Journal Socket.
10873 01:34:25.846673 [[0;32m OK [0m] Listening on<30>[ 10.882771] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10874 01:34:25.853356 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10875 01:34:25.877551 [[0;32m OK [0m] Listening on<30>[ 10.913865] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10876 01:34:25.884555 [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10877 01:34:25.905568 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 10.941462] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10878 01:34:25.911977 d-udevd…l.socket[0m - udev Kernel Socket.
10879 01:34:25.973360 Mounting [0;1;39mdev-hugepages.mount[<30>[ 11.009345] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10880 01:34:25.976769 0m - Huge Pages File System...
10881 01:34:25.996060 Mountin<30>[ 11.035401] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10882 01:34:26.002830 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10883 01:34:26.029596 Mounting [0;1;39msys-kernel-debug.…<30>[ 11.064956] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10884 01:34:26.032199 [0m - Kernel Debug File System...
10885 01:34:26.059748 <30>[ 11.089109] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10886 01:34:26.073066 Startin<30>[ 11.092970] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10887 01:34:26.075872 g [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10888 01:34:26.137419 Starting [0;1;39mmodprobe@configfs…m<30>[ 11.173538] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10889 01:34:26.140924 - Load Kernel Module configfs...
10890 01:34:26.170876 Starting [0;1;39mmodpr<30>[ 11.206554] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10891 01:34:26.173819 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10892 01:34:26.221303 <6>[ 11.258111] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10893 01:34:26.242084 Starting [0;1;39mmodpr<30>[ 11.277706] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10894 01:34:26.244956 obe@drm.service[0m - Load Kernel Module drm...
10895 01:34:26.269135 <30>[ 11.308554] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10896 01:34:26.278963 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10897 01:34:26.306912 Starting [0;1;39mmodpr<30>[ 11.342852] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10898 01:34:26.311041 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10899 01:34:26.353554 Starting [0;1;39mmodpr<30>[ 11.389855] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10900 01:34:26.357198 obe@loop.ser…e<6>[ 11.390921] fuse: init (API version 7.37)
10901 01:34:26.360622 [0m - Load Kernel Module loop...
10902 01:34:26.393995 Starting [0;1;39msyste<30>[ 11.430473] systemd[1]: Starting systemd-journald.service - Journal Service...
10903 01:34:26.397520 md-journald.service[0m - Journal Service...
10904 01:34:26.425976 Starting [0;1;39msyste<30>[ 11.462076] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10905 01:34:26.428975 md-modules-l…rvice[0m - Load Kernel Modules...
10906 01:34:26.461046 Starting [0;1;39msyste<30>[ 11.493881] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10907 01:34:26.464122 md-network-g… units from Kernel command line...
10908 01:34:26.488743 Startin<30>[ 11.524573] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10909 01:34:26.495304 g [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10910 01:34:26.557894 Starting [0;1;39msyste<30>[ 11.593929] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10911 01:34:26.560845 md-udev-trig…[0m - Coldplug All udev Devices...
10912 01:34:26.597363 [[0;32m OK [0m] Mounted [0;<30>[ 11.633741] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10913 01:34:26.600706 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10914 01:34:26.625095 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.<30>[ 11.661475] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10915 01:34:26.628292 mount[…- POSIX Message Queue File System.
10916 01:34:26.653317 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-<30>[ 11.689621] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10917 01:34:26.656464 debug.m…nt[0m - Kernel Debug File System.
10918 01:34:26.676525 <3>[ 11.712835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 01:34:26.687422 <30>[ 11.717801] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10920 01:34:26.697121 [[0;32m OK [0m] Finished [0<3>[ 11.735092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 01:34:26.703521 ;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10922 01:34:26.723457 [[0;32m OK [0m] Finished [0<30>[ 11.761815] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10923 01:34:26.732990 ;1;39mmodprobe@c<30>[ 11.762315] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10924 01:34:26.743434 onfigfs…[0m - <3>[ 11.765173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 01:34:26.753392 Load Kernel Modu<3>[ 11.786850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 01:34:26.756512 le configfs.
10927 01:34:26.774867 [[0;32m OK [0m] Finished [0<30>[ 11.813807] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10928 01:34:26.785099 ;1;39mmodprobe@d<30>[ 11.814300] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10929 01:34:26.795135 m_mod.s…e[0m <3>[ 11.817444] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 01:34:26.805194 - Load Kernel Mo<3>[ 11.837085] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 01:34:26.808287 dule dm_mod.
10932 01:34:26.827060 [[0;32m OK [0m] Finished [0<30>[ 11.865990] systemd[1]: modprobe@drm.service: Deactivated successfully.
10933 01:34:26.837092 ;1;39mmodprobe@d<30>[ 11.866480] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10934 01:34:26.847206 <3>[ 11.869944] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 01:34:26.850563 rm.service[0m - Load Kernel Module drm.
10936 01:34:26.861159 <3>[ 11.900167] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 01:34:26.872863 [[0;32m OK [<30>[ 11.910772] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10938 01:34:26.882604 0m] Finished [0<30>[ 11.911288] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10939 01:34:26.895345 ;1;39mmodprobe@efi_psto…m - Lo<3>[ 11.931007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 01:34:26.895909 ad Kernel Module efi_pstore.
10941 01:34:26.917985 [[0;32m OK [0m] Finished [0<3>[ 11.953416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 01:34:26.926040 ;1;39mmodprobe@f<30>[ 11.953949] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10943 01:34:26.935303 use.service[0m <30>[ 11.954455] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10944 01:34:26.945614 - Load Kernel Mo<3>[ 11.984049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 01:34:26.948689 dule fuse.
10946 01:34:26.968888 [[0;32m OK [<30>[ 12.007174] systemd[1]: modprobe@loop.service: Deactivated successfully.
10947 01:34:26.978731 0m] Finished [0<30>[ 12.008225] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10948 01:34:26.982455 ;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10949 01:34:27.003948 <4>[ 12.036163] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10950 01:34:27.013493 <3>[ 12.036176] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10951 01:34:27.020271 <30>[ 12.054007] systemd[1]: Started systemd-journald.service - Journal Service.
10952 01:34:27.027352 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10953 01:34:27.049212 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10954 01:34:27.066507 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10955 01:34:27.086836 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10956 01:34:27.106796 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10957 01:34:27.131506 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10958 01:34:27.170103 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10959 01:34:27.194543 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10960 01:34:27.218567 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10961 01:34:27.243616 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10962 01:34:27.289183 <46>[ 12.327004] systemd-journald[312]: Received client request to flush runtime journal.
10963 01:34:27.302422 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10964 01:34:27.328190 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10965 01:34:27.612009 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10966 01:34:27.629820 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10967 01:34:27.650256 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10968 01:34:28.333538 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10969 01:34:28.700286 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10970 01:34:28.723021 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10971 01:34:28.765836 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10972 01:34:28.883955 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10973 01:34:28.906227 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10974 01:34:28.929628 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10975 01:34:28.990397 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10976 01:34:29.019670 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10977 01:34:29.252300 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10978 01:34:29.293883 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10979 01:34:29.380895 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10980 01:34:29.705657 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/system<6>[ 14.747321] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10981 01:34:29.708812 d-backlight.
10982 01:34:29.752764 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10983 01:34:29.802047 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10984 01:34:29.858155 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10985 01:34:29.910494 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10986 01:34:29.931405 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10987 01:34:29.950998 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10988 01:34:29.979248 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10989 01:34:29.994666 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10990 01:34:30.055688 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10991 01:34:30.079307 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10992 01:34:30.097401 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10993 01:34:30.147257 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10994 01:34:30.234830 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10995 01:34:30.254058 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10996 01:34:30.273684 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10997 01:34:30.288838 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10998 01:34:30.314779 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10999 01:34:30.337631 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11000 01:34:30.353421 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11001 01:34:30.373574 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11002 01:34:30.393635 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11003 01:34:30.409324 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11004 01:34:30.427643 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11005 01:34:30.445069 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11006 01:34:30.461212 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11007 01:34:30.509023 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11008 01:34:30.543826 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11009 01:34:30.653988 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11010 01:34:30.684412 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11011 01:34:30.733968 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11012 01:34:30.791318 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11013 01:34:30.829504 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11014 01:34:30.849841 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11015 01:34:30.957922 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11016 01:34:30.993463 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11017 01:34:31.015891 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11018 01:34:31.036903 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11019 01:34:31.053914 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11020 01:34:31.118845 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11021 01:34:31.171503 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11022 01:34:31.258443
11023 01:34:31.261988 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11024 01:34:31.262138
11025 01:34:31.264818 debian-bookworm-arm64 login: root (automatic login)
11026 01:34:31.264936
11027 01:34:31.601859 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
11028 01:34:31.602386
11029 01:34:31.608221 The programs included with the Debian GNU/Linux system are free software;
11030 01:34:31.614877 the exact distribution terms for each program are described in the
11031 01:34:31.618366 individual files in /usr/share/doc/*/copyright.
11032 01:34:31.618780
11033 01:34:31.625447 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11034 01:34:31.628023 permitted by applicable law.
11035 01:34:32.841187 Matched prompt #10: / #
11037 01:34:32.841482 Setting prompt string to ['/ #']
11038 01:34:32.841579 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11040 01:34:32.841770 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11041 01:34:32.841872 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
11042 01:34:32.841947 Setting prompt string to ['/ #']
11043 01:34:32.842011 Forcing a shell prompt, looking for ['/ #']
11045 01:34:32.892456 / #
11046 01:34:32.892922 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11047 01:34:32.893219 Waiting using forced prompt support (timeout 00:02:30)
11048 01:34:32.898264
11049 01:34:32.899097 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11050 01:34:32.899538 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11052 01:34:33.000742 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj'
11053 01:34:33.007187 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14173494/extract-nfsrootfs-378a4wyj'
11055 01:34:33.108796 / # export NFS_SERVER_IP='192.168.201.1'
11056 01:34:33.114788 export NFS_SERVER_IP='192.168.201.1'
11057 01:34:33.115607 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11058 01:34:33.116129 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11059 01:34:33.116590 end: 2 depthcharge-action (duration 00:01:44) [common]
11060 01:34:33.117029 start: 3 lava-test-retry (timeout 00:07:38) [common]
11061 01:34:33.117468 start: 3.1 lava-test-shell (timeout 00:07:38) [common]
11062 01:34:33.117865 Using namespace: common
11064 01:34:33.219044 / # #
11065 01:34:33.219643 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11066 01:34:33.225142 #
11067 01:34:33.225987 Using /lava-14173494
11069 01:34:33.327276 / # export SHELL=/bin/bash
11070 01:34:33.333514 export SHELL=/bin/bash
11072 01:34:33.435238 / # . /lava-14173494/environment
11073 01:34:33.441786 . /lava-14173494/environment
11075 01:34:33.550763 / # /lava-14173494/bin/lava-test-runner /lava-14173494/0
11076 01:34:33.551429 Test shell timeout: 10s (minimum of the action and connection timeout)
11077 01:34:33.557262 /lava-14173494/bin/lava-test-runner /lava-14173494/0
11078 01:34:33.857851 + export TESTRUN_ID=0_timesync-off
11079 01:34:33.861449 + TESTRUN_ID=0_timesync-off
11080 01:34:33.864577 + cd /lava-14173494/0/tests/0_timesync-off
11081 01:34:33.867928 ++ cat uuid
11082 01:34:33.876355 + UUID=14173494_1.6.2.3.1
11083 01:34:33.879224 + set +x
11084 01:34:33.882486 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14173494_1.6.2.3.1>
11085 01:34:33.883168 Received signal: <STARTRUN> 0_timesync-off 14173494_1.6.2.3.1
11086 01:34:33.883528 Starting test lava.0_timesync-off (14173494_1.6.2.3.1)
11087 01:34:33.883935 Skipping test definition patterns.
11088 01:34:33.885858 + systemctl stop systemd-timesyncd
11089 01:34:33.968456 + set +x
11090 01:34:33.971553 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14173494_1.6.2.3.1>
11091 01:34:33.971846 Received signal: <ENDRUN> 0_timesync-off 14173494_1.6.2.3.1
11092 01:34:33.971981 Ending use of test pattern.
11093 01:34:33.972073 Ending test lava.0_timesync-off (14173494_1.6.2.3.1), duration 0.09
11095 01:34:34.058801 + export TESTRUN_ID=1_kselftest-arm64
11096 01:34:34.058899 + TESTRUN_ID=1_kselftest-arm64
11097 01:34:34.065429 + cd /lava-14173494/0/tests/1_kselftest-arm64
11098 01:34:34.065512 ++ cat uuid
11099 01:34:34.071887 + UUID=14173494_1.6.2.3.5
11100 01:34:34.071969 + set +x
11101 01:34:34.077918 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14173494_1.6.2.3.5>
11102 01:34:34.078178 Received signal: <STARTRUN> 1_kselftest-arm64 14173494_1.6.2.3.5
11103 01:34:34.078249 Starting test lava.1_kselftest-arm64 (14173494_1.6.2.3.5)
11104 01:34:34.078329 Skipping test definition patterns.
11105 01:34:34.081237 + cd ./automated/linux/kselftest/
11106 01:34:34.110876 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11107 01:34:34.157899 INFO: install_deps skipped
11108 01:34:34.685347 --2024-06-05 01:34:34-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11109 01:34:34.698672 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11110 01:34:34.824826 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11111 01:34:34.949182 HTTP request sent, awaiting response... 200 OK
11112 01:34:34.952281 Length: 1648104 (1.6M) [application/octet-stream]
11113 01:34:34.955704 Saving to: 'kselftest_armhf.tar.gz'
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11121 01:34:35.881882
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11123 01:34:36.028081
11124 01:34:41.665972 skiplist:
11125 01:34:41.669173 ========================================
11126 01:34:41.672155 ========================================
11127 01:34:41.728555 arm64:tags_test
11128 01:34:41.731126 arm64:run_tags_test.sh
11129 01:34:41.731208 arm64:fake_sigreturn_bad_magic
11130 01:34:41.734368 arm64:fake_sigreturn_bad_size
11131 01:34:41.737677 arm64:fake_sigreturn_bad_size_for_magic0
11132 01:34:41.740893 arm64:fake_sigreturn_duplicated_fpsimd
11133 01:34:41.744386 arm64:fake_sigreturn_misaligned_sp
11134 01:34:41.747419 arm64:fake_sigreturn_missing_fpsimd
11135 01:34:41.750949 arm64:fake_sigreturn_sme_change_vl
11136 01:34:41.753829 arm64:fake_sigreturn_sve_change_vl
11137 01:34:41.757543 arm64:mangle_pstate_invalid_compat_toggle
11138 01:34:41.760528 arm64:mangle_pstate_invalid_daif_bits
11139 01:34:41.763972 arm64:mangle_pstate_invalid_mode_el1h
11140 01:34:41.767452 arm64:mangle_pstate_invalid_mode_el1t
11141 01:34:41.770607 arm64:mangle_pstate_invalid_mode_el2h
11142 01:34:41.773725 arm64:mangle_pstate_invalid_mode_el2t
11143 01:34:41.777421 arm64:mangle_pstate_invalid_mode_el3h
11144 01:34:41.783800 arm64:mangle_pstate_invalid_mode_el3t
11145 01:34:41.783880 arm64:sme_trap_no_sm
11146 01:34:41.787019 arm64:sme_trap_non_streaming
11147 01:34:41.787099 arm64:sme_trap_za
11148 01:34:41.790550 arm64:sme_vl
11149 01:34:41.790630 arm64:ssve_regs
11150 01:34:41.793545 arm64:sve_regs
11151 01:34:41.793626 arm64:sve_vl
11152 01:34:41.793689 arm64:za_no_regs
11153 01:34:41.796886 arm64:za_regs
11154 01:34:41.796966 arm64:pac
11155 01:34:41.800515 arm64:fp-stress
11156 01:34:41.800596 arm64:sve-ptrace
11157 01:34:41.803686 arm64:sve-probe-vls
11158 01:34:41.803790 arm64:vec-syscfg
11159 01:34:41.803856 arm64:za-fork
11160 01:34:41.806810 arm64:za-ptrace
11161 01:34:41.810348 arm64:check_buffer_fill
11162 01:34:41.810428 arm64:check_child_memory
11163 01:34:41.813449 arm64:check_gcr_el1_cswitch
11164 01:34:41.816615 arm64:check_ksm_options
11165 01:34:41.816695 arm64:check_mmap_options
11166 01:34:41.819877 arm64:check_prctl
11167 01:34:41.823440 arm64:check_tags_inclusion
11168 01:34:41.823532 arm64:check_user_mem
11169 01:34:41.826479 arm64:btitest
11170 01:34:41.826571 arm64:nobtitest
11171 01:34:41.826643 arm64:hwcap
11172 01:34:41.830168 arm64:ptrace
11173 01:34:41.830269 arm64:syscall-abi
11174 01:34:41.833231 arm64:tpidr2
11175 01:34:41.836748 ============== Tests to run ===============
11176 01:34:41.836885 arm64:tags_test
11177 01:34:41.839987 arm64:run_tags_test.sh
11178 01:34:41.843239 arm64:fake_sigreturn_bad_magic
11179 01:34:41.846470 arm64:fake_sigreturn_bad_size
11180 01:34:41.849897 arm64:fake_sigreturn_bad_size_for_magic0
11181 01:34:41.853632 arm64:fake_sigreturn_duplicated_fpsimd
11182 01:34:41.856787 arm64:fake_sigreturn_misaligned_sp
11183 01:34:41.860359 arm64:fake_sigreturn_missing_fpsimd
11184 01:34:41.863210 arm64:fake_sigreturn_sme_change_vl
11185 01:34:41.863619 arm64:fake_sigreturn_sve_change_vl
11186 01:34:41.869903 arm64:mangle_pstate_invalid_compat_toggle
11187 01:34:41.873306 arm64:mangle_pstate_invalid_daif_bits
11188 01:34:41.876503 arm64:mangle_pstate_invalid_mode_el1h
11189 01:34:41.879999 arm64:mangle_pstate_invalid_mode_el1t
11190 01:34:41.882974 arm64:mangle_pstate_invalid_mode_el2h
11191 01:34:41.886487 arm64:mangle_pstate_invalid_mode_el2t
11192 01:34:41.889507 arm64:mangle_pstate_invalid_mode_el3h
11193 01:34:41.892837 arm64:mangle_pstate_invalid_mode_el3t
11194 01:34:41.893253 arm64:sme_trap_no_sm
11195 01:34:41.896611 arm64:sme_trap_non_streaming
11196 01:34:41.899838 arm64:sme_trap_za
11197 01:34:41.900253 arm64:sme_vl
11198 01:34:41.900578 arm64:ssve_regs
11199 01:34:41.902721 arm64:sve_regs
11200 01:34:41.903132 arm64:sve_vl
11201 01:34:41.906217 arm64:za_no_regs
11202 01:34:41.906808 arm64:za_regs
11203 01:34:41.907165 arm64:pac
11204 01:34:41.909670 arm64:fp-stress
11205 01:34:41.910083 arm64:sve-ptrace
11206 01:34:41.912888 arm64:sve-probe-vls
11207 01:34:41.913413 arm64:vec-syscfg
11208 01:34:41.916079 arm64:za-fork
11209 01:34:41.916498 arm64:za-ptrace
11210 01:34:41.919538 arm64:check_buffer_fill
11211 01:34:41.922784 arm64:check_child_memory
11212 01:34:41.923202 arm64:check_gcr_el1_cswitch
11213 01:34:41.926086 arm64:check_ksm_options
11214 01:34:41.929436 arm64:check_mmap_options
11215 01:34:41.929851 arm64:check_prctl
11216 01:34:41.932791 arm64:check_tags_inclusion
11217 01:34:41.933349 arm64:check_user_mem
11218 01:34:41.935762 arm64:btitest
11219 01:34:41.936191 arm64:nobtitest
11220 01:34:41.939401 arm64:hwcap
11221 01:34:41.939817 arm64:ptrace
11222 01:34:41.942694 arm64:syscall-abi
11223 01:34:41.943111 arm64:tpidr2
11224 01:34:41.945906 ===========End Tests to run ===============
11225 01:34:41.949453 shardfile-arm64 pass
11226 01:34:42.232275 <12>[ 27.275992] kselftest: Running tests in arm64
11227 01:34:42.241709 TAP version 13
11228 01:34:42.259776 1..48
11229 01:34:42.283641 # selftests: arm64: tags_test
11230 01:34:42.774769 ok 1 selftests: arm64: tags_test
11231 01:34:42.794486 # selftests: arm64: run_tags_test.sh
11232 01:34:42.863534 # --------------------
11233 01:34:42.866860 # running tags test
11234 01:34:42.867417 # --------------------
11235 01:34:42.870194 # [PASS]
11236 01:34:42.873226 ok 2 selftests: arm64: run_tags_test.sh
11237 01:34:42.890860 # selftests: arm64: fake_sigreturn_bad_magic
11238 01:34:42.959312 # Registered handlers for all signals.
11239 01:34:42.959888 # Detected MINSTKSIGSZ:4720
11240 01:34:42.962545 # Testcase initialized.
11241 01:34:42.966312 # uc context validated.
11242 01:34:42.969340 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11243 01:34:42.972656 # Handled SIG_COPYCTX
11244 01:34:42.973286 # Available space:3568
11245 01:34:42.978961 # Using badly built context - ERR: BAD MAGIC !
11246 01:34:42.985525 # SIG_OK -- SP:0xFFFFDD0B74F0 si_addr@:0xffffdd0b74f0 si_code:2 token@:0xffffdd0b6290 offset:-4704
11247 01:34:42.988724 # ==>> completed. PASS(1)
11248 01:34:42.995309 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11249 01:34:43.002653 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDD0B6290
11250 01:34:43.008693 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11251 01:34:43.011675 # selftests: arm64: fake_sigreturn_bad_size
11252 01:34:43.039432 # Registered handlers for all signals.
11253 01:34:43.040193 # Detected MINSTKSIGSZ:4720
11254 01:34:43.043076 # Testcase initialized.
11255 01:34:43.046319 # uc context validated.
11256 01:34:43.049387 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11257 01:34:43.053017 # Handled SIG_COPYCTX
11258 01:34:43.053425 # Available space:3568
11259 01:34:43.055959 # uc context validated.
11260 01:34:43.062559 # Using badly built context - ERR: Bad size for esr_context
11261 01:34:43.069226 # SIG_OK -- SP:0xFFFFEA805CF0 si_addr@:0xffffea805cf0 si_code:2 token@:0xffffea804a90 offset:-4704
11262 01:34:43.072699 # ==>> completed. PASS(1)
11263 01:34:43.079008 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11264 01:34:43.085880 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEA804A90
11265 01:34:43.089050 ok 4 selftests: arm64: fake_sigreturn_bad_size
11266 01:34:43.095922 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11267 01:34:43.129736 # Registered handlers for all signals.
11268 01:34:43.130421 # Detected MINSTKSIGSZ:4720
11269 01:34:43.132613 # Testcase initialized.
11270 01:34:43.135846 # uc context validated.
11271 01:34:43.139151 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11272 01:34:43.142659 # Handled SIG_COPYCTX
11273 01:34:43.143111 # Available space:3568
11274 01:34:43.149162 # Using badly built context - ERR: Bad size for terminator
11275 01:34:43.158938 # SIG_OK -- SP:0xFFFFCBFD8600 si_addr@:0xffffcbfd8600 si_code:2 token@:0xffffcbfd73a0 offset:-4704
11276 01:34:43.159370 # ==>> completed. PASS(1)
11277 01:34:43.168860 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11278 01:34:43.175560 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCBFD73A0
11279 01:34:43.178959 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11280 01:34:43.185188 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11281 01:34:43.249524 # Registered handlers for all signals.
11282 01:34:43.250091 # Detected MINSTKSIGSZ:4720
11283 01:34:43.252772 # Testcase initialized.
11284 01:34:43.255982 # uc context validated.
11285 01:34:43.258980 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11286 01:34:43.262353 # Handled SIG_COPYCTX
11287 01:34:43.262774 # Available space:3568
11288 01:34:43.269373 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11289 01:34:43.278503 # SIG_OK -- SP:0xFFFFCB701430 si_addr@:0xffffcb701430 si_code:2 token@:0xffffcb7001d0 offset:-4704
11290 01:34:43.278958 # ==>> completed. PASS(1)
11291 01:34:43.288693 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11292 01:34:43.295373 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCB7001D0
11293 01:34:43.298484 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11294 01:34:43.304932 # selftests: arm64: fake_sigreturn_misaligned_sp
11295 01:34:43.345100 # Registered handlers for all signals.
11296 01:34:43.345596 # Detected MINSTKSIGSZ:4720
11297 01:34:43.348376 # Testcase initialized.
11298 01:34:43.351550 # uc context validated.
11299 01:34:43.355193 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11300 01:34:43.358539 # Handled SIG_COPYCTX
11301 01:34:43.364987 # SIG_OK -- SP:0xFFFFDA470BB3 si_addr@:0xffffda470bb3 si_code:2 token@:0xffffda470bb3 offset:0
11302 01:34:43.368250 # ==>> completed. PASS(1)
11303 01:34:43.374969 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11304 01:34:43.381266 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDA470BB3
11305 01:34:43.388240 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11306 01:34:43.391508 # selftests: arm64: fake_sigreturn_missing_fpsimd
11307 01:34:43.413346 # Registered handlers for all signals.
11308 01:34:43.413945 # Detected MINSTKSIGSZ:4720
11309 01:34:43.416606 # Testcase initialized.
11310 01:34:43.420048 # uc context validated.
11311 01:34:43.422957 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11312 01:34:43.426507 # Handled SIG_COPYCTX
11313 01:34:43.429946 # Mangling template header. Spare space:4096
11314 01:34:43.433071 # Using badly built context - ERR: Missing FPSIMD
11315 01:34:43.442830 # SIG_OK -- SP:0xFFFFF5B52A60 si_addr@:0xfffff5b52a60 si_code:2 token@:0xfffff5b51800 offset:-4704
11316 01:34:43.446075 # ==>> completed. PASS(1)
11317 01:34:43.452737 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11318 01:34:43.459438 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF5B51800
11319 01:34:43.462945 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11320 01:34:43.469175 # selftests: arm64: fake_sigreturn_sme_change_vl
11321 01:34:43.509025 # Registered handlers for all signals.
11322 01:34:43.509616 # Detected MINSTKSIGSZ:4720
11323 01:34:43.511866 # ==>> completed. SKIP.
11324 01:34:43.518883 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11325 01:34:43.521787 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11326 01:34:43.533258 # selftests: arm64: fake_sigreturn_sve_change_vl
11327 01:34:43.601487 # Registered handlers for all signals.
11328 01:34:43.602367 # Detected MINSTKSIGSZ:4720
11329 01:34:43.606247 # ==>> completed. SKIP.
11330 01:34:43.611499 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11331 01:34:43.614287 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11332 01:34:43.626703 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11333 01:34:43.704398 # Registered handlers for all signals.
11334 01:34:43.704947 # Detected MINSTKSIGSZ:4720
11335 01:34:43.707916 # Testcase initialized.
11336 01:34:43.710950 # uc context validated.
11337 01:34:43.711402 # Handled SIG_TRIG
11338 01:34:43.721006 # SIG_OK -- SP:0xFFFFFD9FFF20 si_addr@:0xfffffd9fff20 si_code:2 token@:(nil) offset:-281474936864544
11339 01:34:43.724127 # ==>> completed. PASS(1)
11340 01:34:43.731172 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11341 01:34:43.737289 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11342 01:34:43.740376 # selftests: arm64: mangle_pstate_invalid_daif_bits
11343 01:34:43.799486 # Registered handlers for all signals.
11344 01:34:43.800093 # Detected MINSTKSIGSZ:4720
11345 01:34:43.802700 # Testcase initialized.
11346 01:34:43.806135 # uc context validated.
11347 01:34:43.806634 # Handled SIG_TRIG
11348 01:34:43.815962 # SIG_OK -- SP:0xFFFFF375FA50 si_addr@:0xfffff375fa50 si_code:2 token@:(nil) offset:-281474766338640
11349 01:34:43.819331 # ==>> completed. PASS(1)
11350 01:34:43.826032 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11351 01:34:43.829108 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11352 01:34:43.836370 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11353 01:34:43.880311 # Registered handlers for all signals.
11354 01:34:43.880898 # Detected MINSTKSIGSZ:4720
11355 01:34:43.883801 # Testcase initialized.
11356 01:34:43.886757 # uc context validated.
11357 01:34:43.887168 # Handled SIG_TRIG
11358 01:34:43.896635 # SIG_OK -- SP:0xFFFFD1200AC0 si_addr@:0xffffd1200ac0 si_code:2 token@:(nil) offset:-281474190281408
11359 01:34:43.899899 # ==>> completed. PASS(1)
11360 01:34:43.906444 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11361 01:34:43.909567 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11362 01:34:43.916514 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11363 01:34:43.981520 # Registered handlers for all signals.
11364 01:34:43.982302 # Detected MINSTKSIGSZ:4720
11365 01:34:43.984254 # Testcase initialized.
11366 01:34:43.987581 # uc context validated.
11367 01:34:43.988087 # Handled SIG_TRIG
11368 01:34:43.997555 # SIG_OK -- SP:0xFFFFCDE9F6C0 si_addr@:0xffffcde9f6c0 si_code:2 token@:(nil) offset:-281474136405696
11369 01:34:44.000885 # ==>> completed. PASS(1)
11370 01:34:44.008026 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11371 01:34:44.010754 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11372 01:34:44.016970 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11373 01:34:44.083669 # Registered handlers for all signals.
11374 01:34:44.084211 # Detected MINSTKSIGSZ:4720
11375 01:34:44.087156 # Testcase initialized.
11376 01:34:44.090658 # uc context validated.
11377 01:34:44.091139 # Handled SIG_TRIG
11378 01:34:44.100086 # SIG_OK -- SP:0xFFFFFEAA17D0 si_addr@:0xfffffeaa17d0 si_code:2 token@:(nil) offset:-281474954303440
11379 01:34:44.103431 # ==>> completed. PASS(1)
11380 01:34:44.110119 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11381 01:34:44.113581 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11382 01:34:44.119765 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11383 01:34:44.175118 # Registered handlers for all signals.
11384 01:34:44.175701 # Detected MINSTKSIGSZ:4720
11385 01:34:44.178333 # Testcase initialized.
11386 01:34:44.181547 # uc context validated.
11387 01:34:44.182147 # Handled SIG_TRIG
11388 01:34:44.191583 # SIG_OK -- SP:0xFFFFEB699050 si_addr@:0xffffeb699050 si_code:2 token@:(nil) offset:-281474631307344
11389 01:34:44.195153 # ==>> completed. PASS(1)
11390 01:34:44.201236 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11391 01:34:44.205069 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11392 01:34:44.211211 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11393 01:34:44.281334 # Registered handlers for all signals.
11394 01:34:44.281903 # Detected MINSTKSIGSZ:4720
11395 01:34:44.283866 # Testcase initialized.
11396 01:34:44.287625 # uc context validated.
11397 01:34:44.288123 # Handled SIG_TRIG
11398 01:34:44.297192 # SIG_OK -- SP:0xFFFFEA369E50 si_addr@:0xffffea369e50 si_code:2 token@:(nil) offset:-281474611191376
11399 01:34:44.300264 # ==>> completed. PASS(1)
11400 01:34:44.307085 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11401 01:34:44.310694 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11402 01:34:44.317023 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11403 01:34:44.372893 # Registered handlers for all signals.
11404 01:34:44.373464 # Detected MINSTKSIGSZ:4720
11405 01:34:44.375942 # Testcase initialized.
11406 01:34:44.379591 # uc context validated.
11407 01:34:44.380165 # Handled SIG_TRIG
11408 01:34:44.389017 # SIG_OK -- SP:0xFFFFDE26EFB0 si_addr@:0xffffde26efb0 si_code:2 token@:(nil) offset:-281474408837040
11409 01:34:44.392412 # ==>> completed. PASS(1)
11410 01:34:44.398766 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11411 01:34:44.402063 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11412 01:34:44.405793 # selftests: arm64: sme_trap_no_sm
11413 01:34:44.464356 # Registered handlers for all signals.
11414 01:34:44.465039 # Detected MINSTKSIGSZ:4720
11415 01:34:44.468144 # ==>> completed. SKIP.
11416 01:34:44.477862 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11417 01:34:44.481025 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11418 01:34:44.493019 # selftests: arm64: sme_trap_non_streaming
11419 01:34:44.538343 # Registered handlers for all signals.
11420 01:34:44.538799 # Detected MINSTKSIGSZ:4720
11421 01:34:44.541587 # ==>> completed. SKIP.
11422 01:34:44.551230 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11423 01:34:44.558000 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11424 01:34:44.561162 # selftests: arm64: sme_trap_za
11425 01:34:44.643746 # Registered handlers for all signals.
11426 01:34:44.644476 # Detected MINSTKSIGSZ:4720
11427 01:34:44.647202 # Testcase initialized.
11428 01:34:44.657405 # SIG_OK -- SP:0xFFFFE6A3A930 si_addr@:0xaaaad5162510 si_code:1 token@:(nil) offset:-187650696160528
11429 01:34:44.657824 # ==>> completed. PASS(1)
11430 01:34:44.666923 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11431 01:34:44.670385 ok 21 selftests: arm64: sme_trap_za
11432 01:34:44.670803 # selftests: arm64: sme_vl
11433 01:34:44.754677 # Registered handlers for all signals.
11434 01:34:44.755345 # Detected MINSTKSIGSZ:4720
11435 01:34:44.757393 # ==>> completed. SKIP.
11436 01:34:44.763817 # # SME VL :: Check that we get the right SME VL reported
11437 01:34:44.767202 ok 22 selftests: arm64: sme_vl # SKIP
11438 01:34:44.775407 # selftests: arm64: ssve_regs
11439 01:34:44.849868 # Registered handlers for all signals.
11440 01:34:44.850555 # Detected MINSTKSIGSZ:4720
11441 01:34:44.853477 # ==>> completed. SKIP.
11442 01:34:44.859881 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11443 01:34:44.863047 ok 23 selftests: arm64: ssve_regs # SKIP
11444 01:34:44.869677 # selftests: arm64: sve_regs
11445 01:34:44.951744 # Registered handlers for all signals.
11446 01:34:44.952116 # Detected MINSTKSIGSZ:4720
11447 01:34:44.955266 # ==>> completed. SKIP.
11448 01:34:44.962026 # # SVE registers :: Check that we get the right SVE registers reported
11449 01:34:44.965153 ok 24 selftests: arm64: sve_regs # SKIP
11450 01:34:44.971223 # selftests: arm64: sve_vl
11451 01:34:45.043129 # Registered handlers for all signals.
11452 01:34:45.043663 # Detected MINSTKSIGSZ:4720
11453 01:34:45.046711 # ==>> completed. SKIP.
11454 01:34:45.049871 # # SVE VL :: Check that we get the right SVE VL reported
11455 01:34:45.056185 ok 25 selftests: arm64: sve_vl # SKIP
11456 01:34:45.063377 # selftests: arm64: za_no_regs
11457 01:34:45.141224 # Registered handlers for all signals.
11458 01:34:45.141762 # Detected MINSTKSIGSZ:4720
11459 01:34:45.144611 # ==>> completed. SKIP.
11460 01:34:45.151613 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11461 01:34:45.154756 ok 26 selftests: arm64: za_no_regs # SKIP
11462 01:34:45.162358 # selftests: arm64: za_regs
11463 01:34:45.240341 # Registered handlers for all signals.
11464 01:34:45.240928 # Detected MINSTKSIGSZ:4720
11465 01:34:45.243614 # ==>> completed. SKIP.
11466 01:34:45.250026 # # ZA register :: Check that we get the right ZA registers reported
11467 01:34:45.253091 ok 27 selftests: arm64: za_regs # SKIP
11468 01:34:45.262066 # selftests: arm64: pac
11469 01:34:45.320202 # TAP version 13
11470 01:34:45.320748 # 1..7
11471 01:34:45.323372 # # Starting 7 tests from 1 test cases.
11472 01:34:45.326629 # # RUN global.corrupt_pac ...
11473 01:34:45.330333 # # SKIP PAUTH not enabled
11474 01:34:45.333026 # # OK global.corrupt_pac
11475 01:34:45.336153 # ok 1 # SKIP PAUTH not enabled
11476 01:34:45.343070 # # RUN global.pac_instructions_not_nop ...
11477 01:34:45.346232 # # SKIP PAUTH not enabled
11478 01:34:45.349557 # # OK global.pac_instructions_not_nop
11479 01:34:45.352813 # ok 2 # SKIP PAUTH not enabled
11480 01:34:45.359290 # # RUN global.pac_instructions_not_nop_generic ...
11481 01:34:45.362814 # # SKIP Generic PAUTH not enabled
11482 01:34:45.366097 # # OK global.pac_instructions_not_nop_generic
11483 01:34:45.372582 # ok 3 # SKIP Generic PAUTH not enabled
11484 01:34:45.376085 # # RUN global.single_thread_different_keys ...
11485 01:34:45.379505 # # SKIP PAUTH not enabled
11486 01:34:45.385973 # # OK global.single_thread_different_keys
11487 01:34:45.386591 # ok 4 # SKIP PAUTH not enabled
11488 01:34:45.392397 # # RUN global.exec_changed_keys ...
11489 01:34:45.395872 # # SKIP PAUTH not enabled
11490 01:34:45.399335 # # OK global.exec_changed_keys
11491 01:34:45.402438 # ok 5 # SKIP PAUTH not enabled
11492 01:34:45.405725 # # RUN global.context_switch_keep_keys ...
11493 01:34:45.408835 # # SKIP PAUTH not enabled
11494 01:34:45.416141 # # OK global.context_switch_keep_keys
11495 01:34:45.416656 # ok 6 # SKIP PAUTH not enabled
11496 01:34:45.422262 # # RUN global.context_switch_keep_keys_generic ...
11497 01:34:45.425368 # # SKIP Generic PAUTH not enabled
11498 01:34:45.432149 # # OK global.context_switch_keep_keys_generic
11499 01:34:45.435533 # ok 7 # SKIP Generic PAUTH not enabled
11500 01:34:45.439125 # # PASSED: 7 / 7 tests passed.
11501 01:34:45.442818 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11502 01:34:45.445380 ok 28 selftests: arm64: pac
11503 01:34:45.448362 # selftests: arm64: fp-stress
11504 01:34:52.843616 <6>[ 37.888750] vpu: disabling
11505 01:34:52.847296 <6>[ 37.888832] vproc2: disabling
11506 01:34:52.850038 <6>[ 37.888871] vproc1: disabling
11507 01:34:52.853324 <6>[ 37.888909] vaud18: disabling
11508 01:34:52.856651 <6>[ 37.889092] vsram_others: disabling
11509 01:34:52.860253 <6>[ 37.889221] va09: disabling
11510 01:34:52.863442 <6>[ 37.889277] vsram_md: disabling
11511 01:34:52.866603 <6>[ 37.889374] Vgpu: disabling
11512 01:34:55.393475 # TAP version 13
11513 01:34:55.394035 # 1..16
11514 01:34:55.397459 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11515 01:34:55.400336 # # Will run for 10s
11516 01:34:55.403554 # # Started FPSIMD-0-0
11517 01:34:55.404038 # # Started FPSIMD-0-1
11518 01:34:55.406643 # # Started FPSIMD-1-0
11519 01:34:55.407114 # # Started FPSIMD-1-1
11520 01:34:55.410553 # # Started FPSIMD-2-0
11521 01:34:55.413453 # # Started FPSIMD-2-1
11522 01:34:55.413947 # # Started FPSIMD-3-0
11523 01:34:55.416767 # # Started FPSIMD-3-1
11524 01:34:55.420033 # # Started FPSIMD-4-0
11525 01:34:55.420483 # # Started FPSIMD-4-1
11526 01:34:55.422993 # # Started FPSIMD-5-0
11527 01:34:55.426520 # # Started FPSIMD-5-1
11528 01:34:55.426970 # # Started FPSIMD-6-0
11529 01:34:55.429909 # # Started FPSIMD-6-1
11530 01:34:55.430392 # # Started FPSIMD-7-0
11531 01:34:55.433406 # # Started FPSIMD-7-1
11532 01:34:55.436675 # # FPSIMD-0-1: Vector length: 128 bits
11533 01:34:55.439755 # # FPSIMD-0-1: PID: 1177
11534 01:34:55.442996 # # FPSIMD-0-0: Vector length: 128 bits
11535 01:34:55.446511 # # FPSIMD-0-0: PID: 1176
11536 01:34:55.449503 # # FPSIMD-2-1: Vector length: 128 bits
11537 01:34:55.449967 # # FPSIMD-2-1: PID: 1181
11538 01:34:55.453465 # # FPSIMD-1-1: Vector length: 128 bits
11539 01:34:55.456103 # # FPSIMD-1-1: PID: 1179
11540 01:34:55.459430 # # FPSIMD-2-0: Vector length: 128 bits
11541 01:34:55.463133 # # FPSIMD-2-0: PID: 1180
11542 01:34:55.466085 # # FPSIMD-1-0: Vector length: 128 bits
11543 01:34:55.469512 # # FPSIMD-1-0: PID: 1178
11544 01:34:55.472872 # # FPSIMD-4-0: Vector length: 128 bits
11545 01:34:55.476533 # # FPSIMD-4-0: PID: 1184
11546 01:34:55.479130 # # FPSIMD-4-1: Vector length: 128 bits
11547 01:34:55.479539 # # FPSIMD-4-1: PID: 1185
11548 01:34:55.482527 # # FPSIMD-3-1: Vector length: 128 bits
11549 01:34:55.485983 # # FPSIMD-3-1: PID: 1183
11550 01:34:55.489377 # # FPSIMD-6-0: Vector length: 128 bits
11551 01:34:55.492881 # # FPSIMD-6-0: PID: 1188
11552 01:34:55.495823 # # FPSIMD-6-1: Vector length: 128 bits
11553 01:34:55.498983 # # FPSIMD-6-1: PID: 1189
11554 01:34:55.502437 # # FPSIMD-5-1: Vector length: 128 bits
11555 01:34:55.505492 # # FPSIMD-5-1: PID: 1187
11556 01:34:55.509091 # # FPSIMD-5-0: Vector length: 128 bits
11557 01:34:55.509501 # # FPSIMD-5-0: PID: 1186
11558 01:34:55.512279 # # FPSIMD-7-0: Vector length: 128 bits
11559 01:34:55.515818 # # FPSIMD-7-0: PID: 1190
11560 01:34:55.518929 # # FPSIMD-7-1: Vector length: 128 bits
11561 01:34:55.522468 # # FPSIMD-7-1: PID: 1191
11562 01:34:55.525759 # # FPSIMD-3-0: Vector length: 128 bits
11563 01:34:55.528807 # # FPSIMD-3-0: PID: 1182
11564 01:34:55.529346 # # Finishing up...
11565 01:34:55.535407 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1324584, signals=10
11566 01:34:55.545680 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=995798, signals=10
11567 01:34:55.552162 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1915296, signals=10
11568 01:34:55.558640 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1203272, signals=10
11569 01:34:55.565137 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1298885, signals=10
11570 01:34:55.572240 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1338378, signals=10
11571 01:34:55.578270 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1423369, signals=10
11572 01:34:55.581392 # ok 1 FPSIMD-0-0
11573 01:34:55.581898 # ok 2 FPSIMD-0-1
11574 01:34:55.584883 # ok 3 FPSIMD-1-0
11575 01:34:55.585336 # ok 4 FPSIMD-1-1
11576 01:34:55.588107 # ok 5 FPSIMD-2-0
11577 01:34:55.588521 # ok 6 FPSIMD-2-1
11578 01:34:55.591627 # ok 7 FPSIMD-3-0
11579 01:34:55.592143 # ok 8 FPSIMD-3-1
11580 01:34:55.594888 # ok 9 FPSIMD-4-0
11581 01:34:55.595342 # ok 10 FPSIMD-4-1
11582 01:34:55.598434 # ok 11 FPSIMD-5-0
11583 01:34:55.601257 # ok 12 FPSIMD-5-1
11584 01:34:55.601684 # ok 13 FPSIMD-6-0
11585 01:34:55.605062 # ok 14 FPSIMD-6-1
11586 01:34:55.605576 # ok 15 FPSIMD-7-0
11587 01:34:55.607860 # ok 16 FPSIMD-7-1
11588 01:34:55.614468 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1237050, signals=9
11589 01:34:55.621233 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1063598, signals=10
11590 01:34:55.627680 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=820705, signals=10
11591 01:34:55.634138 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1358007, signals=9
11592 01:34:55.640962 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=940127, signals=10
11593 01:34:55.651097 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=933034, signals=9
11594 01:34:55.657456 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1043587, signals=10
11595 01:34:55.663834 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1419446, signals=10
11596 01:34:55.670909 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=902199, signals=10
11597 01:34:55.677559 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11598 01:34:55.680565 ok 29 selftests: arm64: fp-stress
11599 01:34:55.681090 # selftests: arm64: sve-ptrace
11600 01:34:55.683746 # TAP version 13
11601 01:34:55.684218 # 1..4104
11602 01:34:55.687222 # ok 2 # SKIP SVE not available
11603 01:34:55.690244 # # Planned tests != run tests (4104 != 1)
11604 01:34:55.697123 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11605 01:34:55.700072 ok 30 selftests: arm64: sve-ptrace # SKIP
11606 01:34:55.703716 # selftests: arm64: sve-probe-vls
11607 01:34:55.704245 # TAP version 13
11608 01:34:55.704769 # 1..2
11609 01:34:55.706812 # ok 2 # SKIP SVE not available
11610 01:34:55.710127 # # Planned tests != run tests (2 != 1)
11611 01:34:55.716686 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11612 01:34:55.720076 ok 31 selftests: arm64: sve-probe-vls # SKIP
11613 01:34:55.723259 # selftests: arm64: vec-syscfg
11614 01:34:55.723746 # TAP version 13
11615 01:34:55.726983 # 1..20
11616 01:34:55.730480 # ok 1 # SKIP SVE not supported
11617 01:34:55.730907 # ok 2 # SKIP SVE not supported
11618 01:34:55.732997 # ok 3 # SKIP SVE not supported
11619 01:34:55.736448 # ok 4 # SKIP SVE not supported
11620 01:34:55.739606 # ok 5 # SKIP SVE not supported
11621 01:34:55.742942 # ok 6 # SKIP SVE not supported
11622 01:34:55.746757 # ok 7 # SKIP SVE not supported
11623 01:34:55.749686 # ok 8 # SKIP SVE not supported
11624 01:34:55.753214 # ok 9 # SKIP SVE not supported
11625 01:34:55.753632 # ok 10 # SKIP SVE not supported
11626 01:34:55.756331 # ok 11 # SKIP SME not supported
11627 01:34:55.759838 # ok 12 # SKIP SME not supported
11628 01:34:55.763028 # ok 13 # SKIP SME not supported
11629 01:34:55.766330 # ok 14 # SKIP SME not supported
11630 01:34:55.769645 # ok 15 # SKIP SME not supported
11631 01:34:55.772900 # ok 16 # SKIP SME not supported
11632 01:34:55.776034 # ok 17 # SKIP SME not supported
11633 01:34:55.779690 # ok 18 # SKIP SME not supported
11634 01:34:55.780276 # ok 19 # SKIP SME not supported
11635 01:34:55.783075 # ok 20 # SKIP SME not supported
11636 01:34:55.789356 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11637 01:34:55.792615 ok 32 selftests: arm64: vec-syscfg
11638 01:34:55.796167 # selftests: arm64: za-fork
11639 01:34:55.796808 # TAP version 13
11640 01:34:55.797155 # 1..1
11641 01:34:55.798879 # # PID: 1268
11642 01:34:55.799429 # # SME support not present
11643 01:34:55.802634 # ok 0 skipped
11644 01:34:55.805659 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11645 01:34:55.809175 ok 33 selftests: arm64: za-fork
11646 01:34:55.816628 # selftests: arm64: za-ptrace
11647 01:34:55.877223 # TAP version 13
11648 01:34:55.877767 # 1..1
11649 01:34:55.880674 # ok 2 # SKIP SME not available
11650 01:34:55.887007 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11651 01:34:55.890153 ok 34 selftests: arm64: za-ptrace # SKIP
11652 01:34:55.904116 # selftests: arm64: check_buffer_fill
11653 01:34:55.984411 # # SKIP: MTE features unavailable
11654 01:34:55.993528 ok 35 selftests: arm64: check_buffer_fill # SKIP
11655 01:34:56.013688 # selftests: arm64: check_child_memory
11656 01:34:56.070685 # # SKIP: MTE features unavailable
11657 01:34:56.078863 ok 36 selftests: arm64: check_child_memory # SKIP
11658 01:34:56.097662 # selftests: arm64: check_gcr_el1_cswitch
11659 01:34:56.173562 # # SKIP: MTE features unavailable
11660 01:34:56.182732 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11661 01:34:56.201159 # selftests: arm64: check_ksm_options
11662 01:34:56.269763 # # SKIP: MTE features unavailable
11663 01:34:56.276794 ok 38 selftests: arm64: check_ksm_options # SKIP
11664 01:34:56.296609 # selftests: arm64: check_mmap_options
11665 01:34:56.358046 # # SKIP: MTE features unavailable
11666 01:34:56.365474 ok 39 selftests: arm64: check_mmap_options # SKIP
11667 01:34:56.381055 # selftests: arm64: check_prctl
11668 01:34:56.468840 # TAP version 13
11669 01:34:56.469414 # 1..5
11670 01:34:56.472293 # ok 1 check_basic_read
11671 01:34:56.472852 # ok 2 NONE
11672 01:34:56.475582 # ok 3 # SKIP SYNC
11673 01:34:56.476147 # ok 4 # SKIP ASYNC
11674 01:34:56.478672 # ok 5 # SKIP SYNC+ASYNC
11675 01:34:56.481758 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11676 01:34:56.485232 ok 40 selftests: arm64: check_prctl
11677 01:34:56.496991 # selftests: arm64: check_tags_inclusion
11678 01:34:56.574698 # # SKIP: MTE features unavailable
11679 01:34:56.582336 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11680 01:34:56.598256 # selftests: arm64: check_user_mem
11681 01:34:56.659148 # # SKIP: MTE features unavailable
11682 01:34:56.668319 ok 42 selftests: arm64: check_user_mem # SKIP
11683 01:34:56.684923 # selftests: arm64: btitest
11684 01:34:56.755505 # TAP version 13
11685 01:34:56.756063 # 1..18
11686 01:34:56.758804 # # HWCAP_PACA not present
11687 01:34:56.761820 # # HWCAP2_BTI not present
11688 01:34:56.765102 # # Test binary built for BTI
11689 01:34:56.768436 # ok 1 nohint_func/call_using_br_x0 # SKIP
11690 01:34:56.771401 # ok 1 nohint_func/call_using_br_x16 # SKIP
11691 01:34:56.774712 # ok 1 nohint_func/call_using_blr # SKIP
11692 01:34:56.778137 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11693 01:34:56.781711 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11694 01:34:56.787842 # ok 1 bti_none_func/call_using_blr # SKIP
11695 01:34:56.791308 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11696 01:34:56.794434 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11697 01:34:56.797843 # ok 1 bti_c_func/call_using_blr # SKIP
11698 01:34:56.801455 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11699 01:34:56.804361 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11700 01:34:56.807740 # ok 1 bti_j_func/call_using_blr # SKIP
11701 01:34:56.811355 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11702 01:34:56.818320 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11703 01:34:56.821103 # ok 1 bti_jc_func/call_using_blr # SKIP
11704 01:34:56.824536 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11705 01:34:56.827653 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11706 01:34:56.830933 # ok 1 paciasp_func/call_using_blr # SKIP
11707 01:34:56.837568 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11708 01:34:56.841471 # # WARNING - EXPECTED TEST COUNT WRONG
11709 01:34:56.844329 ok 43 selftests: arm64: btitest
11710 01:34:56.847652 # selftests: arm64: nobtitest
11711 01:34:56.848062 # TAP version 13
11712 01:34:56.848384 # 1..18
11713 01:34:56.850736 # # HWCAP_PACA not present
11714 01:34:56.854156 # # HWCAP2_BTI not present
11715 01:34:56.857170 # # Test binary not built for BTI
11716 01:34:56.860686 # ok 1 nohint_func/call_using_br_x0 # SKIP
11717 01:34:56.863797 # ok 1 nohint_func/call_using_br_x16 # SKIP
11718 01:34:56.867280 # ok 1 nohint_func/call_using_blr # SKIP
11719 01:34:56.870979 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11720 01:34:56.877300 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11721 01:34:56.880150 # ok 1 bti_none_func/call_using_blr # SKIP
11722 01:34:56.883590 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11723 01:34:56.886823 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11724 01:34:56.890129 # ok 1 bti_c_func/call_using_blr # SKIP
11725 01:34:56.893610 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11726 01:34:56.896980 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11727 01:34:56.900213 # ok 1 bti_j_func/call_using_blr # SKIP
11728 01:34:56.906871 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11729 01:34:56.910246 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11730 01:34:56.913648 # ok 1 bti_jc_func/call_using_blr # SKIP
11731 01:34:56.917004 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11732 01:34:56.919810 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11733 01:34:56.923029 # ok 1 paciasp_func/call_using_blr # SKIP
11734 01:34:56.929883 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11735 01:34:56.933278 # # WARNING - EXPECTED TEST COUNT WRONG
11736 01:34:56.936425 ok 44 selftests: arm64: nobtitest
11737 01:34:56.939599 # selftests: arm64: hwcap
11738 01:34:56.944019 # TAP version 13
11739 01:34:56.944539 # 1..28
11740 01:34:56.947266 # ok 1 cpuinfo_match_RNG
11741 01:34:56.950345 # # SIGILL reported for RNG
11742 01:34:56.950762 # ok 2 # SKIP sigill_RNG
11743 01:34:56.953694 # ok 3 cpuinfo_match_SME
11744 01:34:56.956928 # ok 4 sigill_SME
11745 01:34:56.957565 # ok 5 cpuinfo_match_SVE
11746 01:34:56.960226 # ok 6 sigill_SVE
11747 01:34:56.960639 # ok 7 cpuinfo_match_SVE 2
11748 01:34:56.963679 # # SIGILL reported for SVE 2
11749 01:34:56.966921 # ok 8 # SKIP sigill_SVE 2
11750 01:34:56.970042 # ok 9 cpuinfo_match_SVE AES
11751 01:34:56.973653 # # SIGILL reported for SVE AES
11752 01:34:56.974111 # ok 10 # SKIP sigill_SVE AES
11753 01:34:56.976697 # ok 11 cpuinfo_match_SVE2 PMULL
11754 01:34:56.980050 # # SIGILL reported for SVE2 PMULL
11755 01:34:56.983736 # ok 12 # SKIP sigill_SVE2 PMULL
11756 01:34:56.986669 # ok 13 cpuinfo_match_SVE2 BITPERM
11757 01:34:56.989961 # # SIGILL reported for SVE2 BITPERM
11758 01:34:56.993079 # ok 14 # SKIP sigill_SVE2 BITPERM
11759 01:34:56.996569 # ok 15 cpuinfo_match_SVE2 SHA3
11760 01:34:56.999776 # # SIGILL reported for SVE2 SHA3
11761 01:34:57.003132 # ok 16 # SKIP sigill_SVE2 SHA3
11762 01:34:57.006267 # ok 17 cpuinfo_match_SVE2 SM4
11763 01:34:57.009578 # # SIGILL reported for SVE2 SM4
11764 01:34:57.010190 # ok 18 # SKIP sigill_SVE2 SM4
11765 01:34:57.012874 # ok 19 cpuinfo_match_SVE2 I8MM
11766 01:34:57.016695 # # SIGILL reported for SVE2 I8MM
11767 01:34:57.020005 # ok 20 # SKIP sigill_SVE2 I8MM
11768 01:34:57.022964 # ok 21 cpuinfo_match_SVE2 F32MM
11769 01:34:57.026348 # # SIGILL reported for SVE2 F32MM
11770 01:34:57.029259 # ok 22 # SKIP sigill_SVE2 F32MM
11771 01:34:57.032639 # ok 23 cpuinfo_match_SVE2 F64MM
11772 01:34:57.036043 # # SIGILL reported for SVE2 F64MM
11773 01:34:57.039189 # ok 24 # SKIP sigill_SVE2 F64MM
11774 01:34:57.039634 # ok 25 cpuinfo_match_SVE2 BF16
11775 01:34:57.042370 # # SIGILL reported for SVE2 BF16
11776 01:34:57.045778 # ok 26 # SKIP sigill_SVE2 BF16
11777 01:34:57.049001 # ok 27 cpuinfo_match_SVE2 EBF16
11778 01:34:57.052279 # ok 28 # SKIP sigill_SVE2 EBF16
11779 01:34:57.059199 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11780 01:34:57.059618 ok 45 selftests: arm64: hwcap
11781 01:34:57.062082 # selftests: arm64: ptrace
11782 01:34:57.065713 # TAP version 13
11783 01:34:57.066122 # 1..7
11784 01:34:57.068985 # # Parent is 1510, child is 1511
11785 01:34:57.069395 # ok 1 read_tpidr_one
11786 01:34:57.072147 # ok 2 write_tpidr_one
11787 01:34:57.075666 # ok 3 verify_tpidr_one
11788 01:34:57.076080 # ok 4 count_tpidrs
11789 01:34:57.078984 # ok 5 tpidr2_write
11790 01:34:57.079427 # ok 6 tpidr2_read
11791 01:34:57.081946 # ok 7 write_tpidr_only
11792 01:34:57.085874 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11793 01:34:57.088848 ok 46 selftests: arm64: ptrace
11794 01:34:57.091901 # selftests: arm64: syscall-abi
11795 01:34:57.126750 # TAP version 13
11796 01:34:57.127278 # 1..2
11797 01:34:57.129884 # ok 1 getpid() FPSIMD
11798 01:34:57.133214 # ok 2 sched_yield() FPSIMD
11799 01:34:57.136528 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11800 01:34:57.139696 ok 47 selftests: arm64: syscall-abi
11801 01:34:57.149978 # selftests: arm64: tpidr2
11802 01:34:57.227351 # TAP version 13
11803 01:34:57.227857 # 1..5
11804 01:34:57.231383 # # PID: 1547
11805 01:34:57.232121 # # SME support not present
11806 01:34:57.233959 # ok 0 skipped, TPIDR2 not supported
11807 01:34:57.237350 # ok 1 skipped, TPIDR2 not supported
11808 01:34:57.240631 # ok 2 skipped, TPIDR2 not supported
11809 01:34:57.243894 # ok 3 skipped, TPIDR2 not supported
11810 01:34:57.247246 # ok 4 skipped, TPIDR2 not supported
11811 01:34:57.253820 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11812 01:34:57.256883 ok 48 selftests: arm64: tpidr2
11813 01:34:58.870761 arm64_tags_test pass
11814 01:34:58.874211 arm64_run_tags_test_sh pass
11815 01:34:58.877505 arm64_fake_sigreturn_bad_magic pass
11816 01:34:58.880791 arm64_fake_sigreturn_bad_size pass
11817 01:34:58.884142 arm64_fake_sigreturn_bad_size_for_magic0 pass
11818 01:34:58.886958 arm64_fake_sigreturn_duplicated_fpsimd pass
11819 01:34:58.890693 arm64_fake_sigreturn_misaligned_sp pass
11820 01:34:58.893948 arm64_fake_sigreturn_missing_fpsimd pass
11821 01:34:58.897286 arm64_fake_sigreturn_sme_change_vl skip
11822 01:34:58.903668 arm64_fake_sigreturn_sve_change_vl skip
11823 01:34:58.907271 arm64_mangle_pstate_invalid_compat_toggle pass
11824 01:34:58.910583 arm64_mangle_pstate_invalid_daif_bits pass
11825 01:34:58.913643 arm64_mangle_pstate_invalid_mode_el1h pass
11826 01:34:58.917250 arm64_mangle_pstate_invalid_mode_el1t pass
11827 01:34:58.920415 arm64_mangle_pstate_invalid_mode_el2h pass
11828 01:34:58.926741 arm64_mangle_pstate_invalid_mode_el2t pass
11829 01:34:58.930247 arm64_mangle_pstate_invalid_mode_el3h pass
11830 01:34:58.933709 arm64_mangle_pstate_invalid_mode_el3t pass
11831 01:34:58.937475 arm64_sme_trap_no_sm skip
11832 01:34:58.940236 arm64_sme_trap_non_streaming skip
11833 01:34:58.940761 arm64_sme_trap_za pass
11834 01:34:58.944039 arm64_sme_vl skip
11835 01:34:58.944604 arm64_ssve_regs skip
11836 01:34:58.946707 arm64_sve_regs skip
11837 01:34:58.947170 arm64_sve_vl skip
11838 01:34:58.950121 arm64_za_no_regs skip
11839 01:34:58.950720 arm64_za_regs skip
11840 01:34:58.953282 arm64_pac_PAUTH_not_enabled skip
11841 01:34:58.956621 arm64_pac_PAUTH_not_enabled_dup2 skip
11842 01:34:58.963264 arm64_pac_Generic_PAUTH_not_enabled skip
11843 01:34:58.966743 arm64_pac_PAUTH_not_enabled_dup3 skip
11844 01:34:58.969941 arm64_pac_PAUTH_not_enabled_dup4 skip
11845 01:34:58.973314 arm64_pac_PAUTH_not_enabled_dup5 skip
11846 01:34:58.976696 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11847 01:34:58.977302 arm64_pac pass
11848 01:34:58.980107 arm64_fp-stress_FPSIMD-0-0 pass
11849 01:34:58.983052 arm64_fp-stress_FPSIMD-0-1 pass
11850 01:34:58.986471 arm64_fp-stress_FPSIMD-1-0 pass
11851 01:34:58.989910 arm64_fp-stress_FPSIMD-1-1 pass
11852 01:34:58.993272 arm64_fp-stress_FPSIMD-2-0 pass
11853 01:34:58.993826 arm64_fp-stress_FPSIMD-2-1 pass
11854 01:34:58.996132 arm64_fp-stress_FPSIMD-3-0 pass
11855 01:34:58.999775 arm64_fp-stress_FPSIMD-3-1 pass
11856 01:34:59.003255 arm64_fp-stress_FPSIMD-4-0 pass
11857 01:34:59.006486 arm64_fp-stress_FPSIMD-4-1 pass
11858 01:34:59.009706 arm64_fp-stress_FPSIMD-5-0 pass
11859 01:34:59.013066 arm64_fp-stress_FPSIMD-5-1 pass
11860 01:34:59.015818 arm64_fp-stress_FPSIMD-6-0 pass
11861 01:34:59.016275 arm64_fp-stress_FPSIMD-6-1 pass
11862 01:34:59.019315 arm64_fp-stress_FPSIMD-7-0 pass
11863 01:34:59.022385 arm64_fp-stress_FPSIMD-7-1 pass
11864 01:34:59.025789 arm64_fp-stress pass
11865 01:34:59.029287 arm64_sve-ptrace_SVE_not_available skip
11866 01:34:59.030033 arm64_sve-ptrace skip
11867 01:34:59.036066 arm64_sve-probe-vls_SVE_not_available skip
11868 01:34:59.036657 arm64_sve-probe-vls skip
11869 01:34:59.039394 arm64_vec-syscfg_SVE_not_supported skip
11870 01:34:59.045573 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11871 01:34:59.049392 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11872 01:34:59.052179 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11873 01:34:59.055885 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11874 01:34:59.058974 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11875 01:34:59.065439 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11876 01:34:59.068934 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11877 01:34:59.072131 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11878 01:34:59.075602 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11879 01:34:59.078766 arm64_vec-syscfg_SME_not_supported skip
11880 01:34:59.085165 arm64_vec-syscfg_SME_not_supported_dup2 skip
11881 01:34:59.089023 arm64_vec-syscfg_SME_not_supported_dup3 skip
11882 01:34:59.091957 arm64_vec-syscfg_SME_not_supported_dup4 skip
11883 01:34:59.095184 arm64_vec-syscfg_SME_not_supported_dup5 skip
11884 01:34:59.098478 arm64_vec-syscfg_SME_not_supported_dup6 skip
11885 01:34:59.105893 arm64_vec-syscfg_SME_not_supported_dup7 skip
11886 01:34:59.108596 arm64_vec-syscfg_SME_not_supported_dup8 skip
11887 01:34:59.111866 arm64_vec-syscfg_SME_not_supported_dup9 skip
11888 01:34:59.114644 arm64_vec-syscfg_SME_not_supported_dup10 skip
11889 01:34:59.118400 arm64_vec-syscfg pass
11890 01:34:59.121881 arm64_za-fork_skipped pass
11891 01:34:59.122468 arm64_za-fork pass
11892 01:34:59.125023 arm64_za-ptrace_SME_not_available skip
11893 01:34:59.128031 arm64_za-ptrace skip
11894 01:34:59.131333 arm64_check_buffer_fill skip
11895 01:34:59.131787 arm64_check_child_memory skip
11896 01:34:59.134702 arm64_check_gcr_el1_cswitch skip
11897 01:34:59.137901 arm64_check_ksm_options skip
11898 01:34:59.141330 arm64_check_mmap_options skip
11899 01:34:59.144624 arm64_check_prctl_check_basic_read pass
11900 01:34:59.148129 arm64_check_prctl_NONE pass
11901 01:34:59.148859 arm64_check_prctl_SYNC skip
11902 01:34:59.151701 arm64_check_prctl_ASYNC skip
11903 01:34:59.154276 arm64_check_prctl_SYNC_ASYNC skip
11904 01:34:59.157748 arm64_check_prctl pass
11905 01:34:59.160967 arm64_check_tags_inclusion skip
11906 01:34:59.161413 arm64_check_user_mem skip
11907 01:34:59.167577 arm64_btitest_nohint_func_call_using_br_x0 skip
11908 01:34:59.171359 arm64_btitest_nohint_func_call_using_br_x16 skip
11909 01:34:59.174328 arm64_btitest_nohint_func_call_using_blr skip
11910 01:34:59.180976 arm64_btitest_bti_none_func_call_using_br_x0 skip
11911 01:34:59.184049 arm64_btitest_bti_none_func_call_using_br_x16 skip
11912 01:34:59.187462 arm64_btitest_bti_none_func_call_using_blr skip
11913 01:34:59.194017 arm64_btitest_bti_c_func_call_using_br_x0 skip
11914 01:34:59.197559 arm64_btitest_bti_c_func_call_using_br_x16 skip
11915 01:34:59.200640 arm64_btitest_bti_c_func_call_using_blr skip
11916 01:34:59.204416 arm64_btitest_bti_j_func_call_using_br_x0 skip
11917 01:34:59.210702 arm64_btitest_bti_j_func_call_using_br_x16 skip
11918 01:34:59.213682 arm64_btitest_bti_j_func_call_using_blr skip
11919 01:34:59.217291 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11920 01:34:59.220180 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11921 01:34:59.226899 arm64_btitest_bti_jc_func_call_using_blr skip
11922 01:34:59.230123 arm64_btitest_paciasp_func_call_using_br_x0 skip
11923 01:34:59.233250 arm64_btitest_paciasp_func_call_using_br_x16 skip
11924 01:34:59.239682 arm64_btitest_paciasp_func_call_using_blr skip
11925 01:34:59.239762 arm64_btitest pass
11926 01:34:59.243005 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11927 01:34:59.249577 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11928 01:34:59.252837 arm64_nobtitest_nohint_func_call_using_blr skip
11929 01:34:59.259678 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11930 01:34:59.262616 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11931 01:34:59.266155 arm64_nobtitest_bti_none_func_call_using_blr skip
11932 01:34:59.272679 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11933 01:34:59.276085 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11934 01:34:59.279389 arm64_nobtitest_bti_c_func_call_using_blr skip
11935 01:34:59.285890 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11936 01:34:59.289324 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11937 01:34:59.292516 arm64_nobtitest_bti_j_func_call_using_blr skip
11938 01:34:59.295653 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11939 01:34:59.302541 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11940 01:34:59.305778 arm64_nobtitest_bti_jc_func_call_using_blr skip
11941 01:34:59.308835 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11942 01:34:59.315733 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11943 01:34:59.319128 arm64_nobtitest_paciasp_func_call_using_blr skip
11944 01:34:59.321959 arm64_nobtitest pass
11945 01:34:59.325531 arm64_hwcap_cpuinfo_match_RNG pass
11946 01:34:59.325613 arm64_hwcap_sigill_RNG skip
11947 01:34:59.328771 arm64_hwcap_cpuinfo_match_SME pass
11948 01:34:59.331858 arm64_hwcap_sigill_SME pass
11949 01:34:59.335412 arm64_hwcap_cpuinfo_match_SVE pass
11950 01:34:59.338475 arm64_hwcap_sigill_SVE pass
11951 01:34:59.342026 arm64_hwcap_cpuinfo_match_SVE_2 pass
11952 01:34:59.345355 arm64_hwcap_sigill_SVE_2 skip
11953 01:34:59.348294 arm64_hwcap_cpuinfo_match_SVE_AES pass
11954 01:34:59.352012 arm64_hwcap_sigill_SVE_AES skip
11955 01:34:59.355163 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11956 01:34:59.358443 arm64_hwcap_sigill_SVE2_PMULL skip
11957 01:34:59.361594 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11958 01:34:59.364911 arm64_hwcap_sigill_SVE2_BITPERM skip
11959 01:34:59.368398 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11960 01:34:59.371394 arm64_hwcap_sigill_SVE2_SHA3 skip
11961 01:34:59.374681 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11962 01:34:59.378132 arm64_hwcap_sigill_SVE2_SM4 skip
11963 01:34:59.381397 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11964 01:34:59.384896 arm64_hwcap_sigill_SVE2_I8MM skip
11965 01:34:59.388155 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11966 01:34:59.391160 arm64_hwcap_sigill_SVE2_F32MM skip
11967 01:34:59.394591 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11968 01:34:59.398056 arm64_hwcap_sigill_SVE2_F64MM skip
11969 01:34:59.401331 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11970 01:34:59.404587 arm64_hwcap_sigill_SVE2_BF16 skip
11971 01:34:59.408127 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11972 01:34:59.411431 arm64_hwcap_sigill_SVE2_EBF16 skip
11973 01:34:59.414989 arm64_hwcap pass
11974 01:34:59.418575 arm64_ptrace_read_tpidr_one pass
11975 01:34:59.421146 arm64_ptrace_write_tpidr_one pass
11976 01:34:59.421575 arm64_ptrace_verify_tpidr_one pass
11977 01:34:59.424621 arm64_ptrace_count_tpidrs pass
11978 01:34:59.427945 arm64_ptrace_tpidr2_write pass
11979 01:34:59.431301 arm64_ptrace_tpidr2_read pass
11980 01:34:59.435604 arm64_ptrace_write_tpidr_only pass
11981 01:34:59.436023 arm64_ptrace pass
11982 01:34:59.437764 arm64_syscall-abi_getpid_FPSIMD pass
11983 01:34:59.444398 arm64_syscall-abi_sched_yield_FPSIMD pass
11984 01:34:59.444820 arm64_syscall-abi pass
11985 01:34:59.447732 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11986 01:34:59.454443 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11987 01:34:59.457547 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11988 01:34:59.464757 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11989 01:34:59.467810 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11990 01:34:59.470954 arm64_tpidr2 pass
11991 01:34:59.474262 + ../../utils/send-to-lava.sh ./output/result.txt
11992 01:34:59.480817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11993 01:34:59.481611 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11995 01:34:59.484048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11996 01:34:59.484922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11998 01:34:59.490506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11999 01:34:59.491182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12001 01:34:59.501668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12002 01:34:59.502347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12004 01:34:59.558694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12005 01:34:59.559377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12007 01:34:59.629084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12008 01:34:59.629790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12010 01:34:59.696436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12011 01:34:59.697128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12013 01:34:59.758843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12014 01:34:59.759101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12016 01:34:59.818137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12017 01:34:59.818841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12019 01:34:59.878336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12020 01:34:59.878602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12022 01:34:59.945337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12023 01:34:59.946112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12025 01:35:00.003548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12026 01:35:00.003813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12028 01:35:00.064246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12029 01:35:00.064924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12031 01:35:00.137763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12032 01:35:00.138029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12034 01:35:00.200909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12035 01:35:00.201176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12037 01:35:00.260792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12038 01:35:00.261467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12040 01:35:00.326935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12041 01:35:00.327622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12043 01:35:00.389322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12044 01:35:00.389988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12046 01:35:00.457704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12047 01:35:00.458375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12049 01:35:00.512978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12050 01:35:00.513259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12052 01:35:00.572815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12054 01:35:00.576134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12055 01:35:00.640266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12056 01:35:00.641043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12058 01:35:00.698135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12059 01:35:00.698449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12061 01:35:00.761112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12062 01:35:00.761390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12064 01:35:00.823428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12065 01:35:00.824118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12067 01:35:00.892652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12068 01:35:00.893484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12070 01:35:00.958884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12071 01:35:00.959210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12073 01:35:01.022541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12074 01:35:01.023226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12076 01:35:01.091810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12078 01:35:01.094649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12079 01:35:01.159124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12080 01:35:01.159384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12082 01:35:01.218211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12083 01:35:01.218560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12085 01:35:01.287864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12086 01:35:01.288565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12088 01:35:01.354099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12089 01:35:01.355012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12091 01:35:01.424567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12092 01:35:01.425524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12094 01:35:01.495813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12095 01:35:01.496563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12097 01:35:01.560737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12098 01:35:01.561500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12100 01:35:01.634765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12101 01:35:01.635522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12103 01:35:01.703605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12105 01:35:01.706942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12106 01:35:01.775111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12107 01:35:01.775908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12109 01:35:01.844977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12110 01:35:01.845899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12112 01:35:01.913041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12113 01:35:01.914030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12115 01:35:01.981929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12116 01:35:01.982735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12118 01:35:02.048526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12119 01:35:02.049253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12121 01:35:02.117163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12122 01:35:02.117841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12124 01:35:02.191545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12125 01:35:02.192228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12127 01:35:02.255148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12128 01:35:02.255830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12130 01:35:02.322944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12131 01:35:02.323626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12133 01:35:02.394696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12135 01:35:02.397715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12136 01:35:02.465166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12137 01:35:02.465847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12139 01:35:02.531709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12140 01:35:02.532402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12142 01:35:02.601130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12143 01:35:02.602024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12145 01:35:02.669070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12146 01:35:02.669742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12148 01:35:02.733003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12149 01:35:02.733694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12151 01:35:02.810955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12152 01:35:02.811708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12154 01:35:02.874807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12155 01:35:02.875633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12157 01:35:02.947759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12158 01:35:02.948687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12160 01:35:03.014063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12161 01:35:03.014910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12163 01:35:03.081560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12164 01:35:03.082404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12166 01:35:03.152265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12167 01:35:03.152978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12169 01:35:03.219580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12170 01:35:03.220298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12172 01:35:03.287674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12173 01:35:03.288405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12175 01:35:03.354815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12176 01:35:03.355519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12178 01:35:03.423474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12179 01:35:03.424210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12181 01:35:03.489227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12182 01:35:03.489936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12184 01:35:03.559379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12185 01:35:03.560075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12187 01:35:03.628068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12188 01:35:03.628775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12190 01:35:03.694651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12191 01:35:03.695325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12193 01:35:03.767110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12194 01:35:03.767804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12196 01:35:03.828594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12197 01:35:03.829274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12199 01:35:03.892962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12200 01:35:03.893238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12202 01:35:03.955691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12203 01:35:03.956441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12205 01:35:04.024097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12206 01:35:04.024844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12208 01:35:04.092418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12209 01:35:04.092689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12211 01:35:04.159111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12212 01:35:04.159632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12214 01:35:04.230808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12215 01:35:04.231498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12217 01:35:04.295879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12218 01:35:04.296552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12220 01:35:04.359105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12221 01:35:04.359790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12223 01:35:04.416168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12224 01:35:04.416890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12226 01:35:04.478916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12227 01:35:04.479603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12229 01:35:04.549136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12230 01:35:04.549889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12232 01:35:04.618767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12233 01:35:04.619514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12235 01:35:04.678751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12236 01:35:04.679419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12238 01:35:04.745923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12239 01:35:04.746702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12241 01:35:04.817380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12242 01:35:04.817655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12244 01:35:04.878448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12246 01:35:04.880933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12247 01:35:04.937542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12248 01:35:04.937882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12250 01:35:05.001535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12251 01:35:05.001883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12253 01:35:05.072392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12254 01:35:05.072682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12256 01:35:05.129467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12257 01:35:05.129745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12259 01:35:05.193469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12260 01:35:05.194141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12262 01:35:05.260737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12263 01:35:05.261008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12265 01:35:05.322691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12267 01:35:05.326044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12268 01:35:05.385441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12269 01:35:05.385700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12271 01:35:05.447181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12273 01:35:05.449790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12274 01:35:05.506679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12275 01:35:05.507019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12277 01:35:05.574907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12278 01:35:05.575739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12280 01:35:05.645437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12281 01:35:05.646152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12283 01:35:05.707364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12284 01:35:05.708050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12286 01:35:05.776916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12287 01:35:05.777633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12289 01:35:05.840179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12290 01:35:05.840517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12292 01:35:05.903603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12293 01:35:05.903926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12295 01:35:05.966745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12296 01:35:05.967024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12298 01:35:06.026580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12299 01:35:06.026849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12301 01:35:06.090278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12302 01:35:06.091079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12304 01:35:06.157822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12305 01:35:06.158666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12307 01:35:06.222532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12308 01:35:06.222801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12310 01:35:06.281586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12311 01:35:06.281860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12313 01:35:06.347861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12314 01:35:06.348583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12316 01:35:06.414234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12317 01:35:06.414962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12319 01:35:06.472593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12320 01:35:06.473316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12322 01:35:06.533730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12323 01:35:06.534454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12325 01:35:06.592859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12326 01:35:06.593591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12328 01:35:06.660648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12329 01:35:06.661332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12331 01:35:06.722725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12332 01:35:06.723481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12334 01:35:06.791473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12335 01:35:06.792186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12337 01:35:06.856996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12338 01:35:06.857696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12340 01:35:06.920077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12341 01:35:06.920775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12343 01:35:06.990728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12344 01:35:06.991452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12346 01:35:07.053757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12347 01:35:07.054495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12349 01:35:07.119987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12350 01:35:07.120735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12352 01:35:07.185537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12353 01:35:07.186308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12355 01:35:07.249701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12356 01:35:07.250497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12358 01:35:07.317501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12359 01:35:07.318215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12361 01:35:07.381275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12362 01:35:07.381952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12364 01:35:07.441499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12365 01:35:07.442207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12367 01:35:07.511105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12368 01:35:07.511789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12370 01:35:07.575697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12371 01:35:07.576701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12373 01:35:07.638156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12374 01:35:07.638885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12376 01:35:07.704010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12377 01:35:07.704686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12379 01:35:07.767234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12380 01:35:07.767949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12382 01:35:07.831136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12383 01:35:07.831843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12385 01:35:07.899828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12386 01:35:07.900532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12388 01:35:07.961186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12389 01:35:07.961933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12391 01:35:08.034469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12392 01:35:08.035170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12394 01:35:08.098594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12395 01:35:08.099440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12397 01:35:08.162123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12398 01:35:08.162887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12400 01:35:08.229438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12401 01:35:08.230362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12403 01:35:08.295807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12404 01:35:08.296537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12406 01:35:08.361060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12407 01:35:08.361747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12409 01:35:08.432392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12410 01:35:08.433107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12412 01:35:08.493458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12413 01:35:08.494122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12415 01:35:08.568772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12416 01:35:08.569499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12418 01:35:08.628004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12419 01:35:08.628822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12421 01:35:08.697033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12422 01:35:08.697738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12424 01:35:08.764924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12425 01:35:08.765634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12427 01:35:08.832598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12428 01:35:08.833332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12430 01:35:08.899594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12431 01:35:08.900269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12433 01:35:08.962018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12434 01:35:08.962791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12436 01:35:09.024732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12438 01:35:09.027447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12439 01:35:09.094534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12440 01:35:09.095232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12442 01:35:09.157812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12444 01:35:09.160678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12445 01:35:09.230955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12446 01:35:09.231689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12448 01:35:09.289912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12450 01:35:09.292771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12451 01:35:09.361555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12452 01:35:09.362277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12454 01:35:09.429100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12455 01:35:09.429794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12457 01:35:09.497910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12458 01:35:09.498702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12460 01:35:09.568698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12461 01:35:09.569376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12463 01:35:09.634920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12464 01:35:09.635630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12466 01:35:09.701286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12468 01:35:09.703999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12469 01:35:09.765332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12470 01:35:09.766036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12472 01:35:09.831268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12473 01:35:09.831953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12475 01:35:09.894008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12476 01:35:09.894812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12478 01:35:09.960326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12480 01:35:09.963094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12481 01:35:10.026224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12483 01:35:10.029059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12484 01:35:10.097240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12485 01:35:10.098079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12487 01:35:10.157160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12488 01:35:10.158009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12490 01:35:10.217476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12491 01:35:10.218342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12493 01:35:10.278344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12494 01:35:10.279046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12496 01:35:10.351054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12497 01:35:10.351765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12499 01:35:10.412688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12500 01:35:10.413468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12502 01:35:10.486434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12503 01:35:10.487575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12505 01:35:10.552017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12506 01:35:10.552908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12508 01:35:10.617615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12509 01:35:10.618279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12511 01:35:10.689885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12512 01:35:10.690688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12514 01:35:10.752299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12515 01:35:10.753139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12517 01:35:10.820665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12518 01:35:10.821365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12520 01:35:10.890206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12521 01:35:10.891066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12523 01:35:10.956726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12524 01:35:10.957604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12526 01:35:11.018431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12527 01:35:11.018930 + set +x
12528 01:35:11.019621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12530 01:35:11.025146 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14173494_1.6.2.3.5>
12531 01:35:11.025812 Received signal: <ENDRUN> 1_kselftest-arm64 14173494_1.6.2.3.5
12532 01:35:11.026222 Ending use of test pattern.
12533 01:35:11.026551 Ending test lava.1_kselftest-arm64 (14173494_1.6.2.3.5), duration 36.95
12535 01:35:11.028660 <LAVA_TEST_RUNNER EXIT>
12536 01:35:11.029320 ok: lava_test_shell seems to have completed
12537 01:35:11.035328 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12538 01:35:11.036088 end: 3.1 lava-test-shell (duration 00:00:38) [common]
12539 01:35:11.036533 end: 3 lava-test-retry (duration 00:00:38) [common]
12540 01:35:11.036960 start: 4 finalize (timeout 00:07:00) [common]
12541 01:35:11.037391 start: 4.1 power-off (timeout 00:00:30) [common]
12542 01:35:11.038122 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
12543 01:35:11.301017 >> Command sent successfully.
12544 01:35:11.311524 Returned 0 in 0 seconds
12545 01:35:11.412932 end: 4.1 power-off (duration 00:00:00) [common]
12547 01:35:11.414666 start: 4.2 read-feedback (timeout 00:07:00) [common]
12548 01:35:11.416008 Listened to connection for namespace 'common' for up to 1s
12549 01:35:12.416672 Finalising connection for namespace 'common'
12550 01:35:12.417384 Disconnecting from shell: Finalise
12551 01:35:12.417807 / #
12552 01:35:12.518947 end: 4.2 read-feedback (duration 00:00:01) [common]
12553 01:35:12.519770 end: 4 finalize (duration 00:00:01) [common]
12554 01:35:12.520424 Cleaning after the job
12555 01:35:12.520966 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/ramdisk
12556 01:35:12.531230 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/kernel
12557 01:35:12.564025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/dtb
12558 01:35:12.564357 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/nfsrootfs
12559 01:35:12.631879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173494/tftp-deploy-s3airdeb/modules
12560 01:35:12.637516 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173494
12561 01:35:13.193750 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173494
12562 01:35:13.193933 Job finished correctly