Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 00:37:46.370704 lava-dispatcher, installed at version: 2024.03
2 00:37:46.370917 start: 0 validate
3 00:37:46.371053 Start time: 2024-06-05 00:37:46.371046+00:00 (UTC)
4 00:37:46.371185 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:37:46.371318 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:37:46.641229 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:37:46.642043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:38:26.155487 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:38:26.156210 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:38:26.419204 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:38:26.419890 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:38:28.679906 validate duration: 42.31
14 00:38:28.680302 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:38:28.680468 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:38:28.680618 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:38:28.680787 Not decompressing ramdisk as can be used compressed.
18 00:38:28.680920 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 00:38:28.681012 saving as /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/ramdisk/rootfs.cpio.gz
20 00:38:28.681101 total size: 28105535 (26 MB)
21 00:38:28.939337 progress 0 % (0 MB)
22 00:38:28.946647 progress 5 % (1 MB)
23 00:38:28.953804 progress 10 % (2 MB)
24 00:38:28.960965 progress 15 % (4 MB)
25 00:38:28.968094 progress 20 % (5 MB)
26 00:38:28.975230 progress 25 % (6 MB)
27 00:38:28.982415 progress 30 % (8 MB)
28 00:38:28.989582 progress 35 % (9 MB)
29 00:38:28.996783 progress 40 % (10 MB)
30 00:38:29.003791 progress 45 % (12 MB)
31 00:38:29.010886 progress 50 % (13 MB)
32 00:38:29.018068 progress 55 % (14 MB)
33 00:38:29.025150 progress 60 % (16 MB)
34 00:38:29.032346 progress 65 % (17 MB)
35 00:38:29.039549 progress 70 % (18 MB)
36 00:38:29.046757 progress 75 % (20 MB)
37 00:38:29.056236 progress 80 % (21 MB)
38 00:38:29.067936 progress 85 % (22 MB)
39 00:38:29.079085 progress 90 % (24 MB)
40 00:38:29.090535 progress 95 % (25 MB)
41 00:38:29.099093 progress 100 % (26 MB)
42 00:38:29.099380 26 MB downloaded in 0.42 s (64.08 MB/s)
43 00:38:29.099625 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:38:29.100101 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:38:29.100247 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:38:29.100392 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:38:29.100605 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:38:29.100717 saving as /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/kernel/Image
50 00:38:29.100808 total size: 54682112 (52 MB)
51 00:38:29.100899 No compression specified
52 00:38:29.102536 progress 0 % (0 MB)
53 00:38:29.117463 progress 5 % (2 MB)
54 00:38:29.131803 progress 10 % (5 MB)
55 00:38:29.146320 progress 15 % (7 MB)
56 00:38:29.161159 progress 20 % (10 MB)
57 00:38:29.176329 progress 25 % (13 MB)
58 00:38:29.190798 progress 30 % (15 MB)
59 00:38:29.205166 progress 35 % (18 MB)
60 00:38:29.219274 progress 40 % (20 MB)
61 00:38:29.233480 progress 45 % (23 MB)
62 00:38:29.247714 progress 50 % (26 MB)
63 00:38:29.261953 progress 55 % (28 MB)
64 00:38:29.276213 progress 60 % (31 MB)
65 00:38:29.290405 progress 65 % (33 MB)
66 00:38:29.304712 progress 70 % (36 MB)
67 00:38:29.319036 progress 75 % (39 MB)
68 00:38:29.333522 progress 80 % (41 MB)
69 00:38:29.347679 progress 85 % (44 MB)
70 00:38:29.361923 progress 90 % (46 MB)
71 00:38:29.376157 progress 95 % (49 MB)
72 00:38:29.390029 progress 100 % (52 MB)
73 00:38:29.390302 52 MB downloaded in 0.29 s (180.14 MB/s)
74 00:38:29.390458 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:38:29.390700 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:38:29.390788 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:38:29.390874 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:38:29.391012 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:38:29.391086 saving as /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/dtb/mt8192-asurada-spherion-r0.dtb
81 00:38:29.391148 total size: 47258 (0 MB)
82 00:38:29.391211 No compression specified
83 00:38:29.392386 progress 69 % (0 MB)
84 00:38:29.392666 progress 100 % (0 MB)
85 00:38:29.392824 0 MB downloaded in 0.00 s (26.95 MB/s)
86 00:38:29.392951 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:38:29.393175 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:38:29.393274 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:38:29.393362 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:38:29.393477 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:38:29.393547 saving as /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/modules/modules.tar
93 00:38:29.393609 total size: 8605984 (8 MB)
94 00:38:29.393672 Using unxz to decompress xz
95 00:38:29.397946 progress 0 % (0 MB)
96 00:38:29.417627 progress 5 % (0 MB)
97 00:38:29.446167 progress 10 % (0 MB)
98 00:38:29.477956 progress 15 % (1 MB)
99 00:38:29.503670 progress 20 % (1 MB)
100 00:38:29.529068 progress 25 % (2 MB)
101 00:38:29.555262 progress 30 % (2 MB)
102 00:38:29.581763 progress 35 % (2 MB)
103 00:38:29.609898 progress 40 % (3 MB)
104 00:38:29.633928 progress 45 % (3 MB)
105 00:38:29.658930 progress 50 % (4 MB)
106 00:38:29.686394 progress 55 % (4 MB)
107 00:38:29.712484 progress 60 % (4 MB)
108 00:38:29.738397 progress 65 % (5 MB)
109 00:38:29.765585 progress 70 % (5 MB)
110 00:38:29.789949 progress 75 % (6 MB)
111 00:38:29.818489 progress 80 % (6 MB)
112 00:38:29.843937 progress 85 % (7 MB)
113 00:38:29.870297 progress 90 % (7 MB)
114 00:38:29.896587 progress 95 % (7 MB)
115 00:38:29.922814 progress 100 % (8 MB)
116 00:38:29.928390 8 MB downloaded in 0.53 s (15.35 MB/s)
117 00:38:29.928729 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:38:29.929129 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:38:29.929272 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:38:29.929409 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:38:29.929529 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:38:29.929666 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:38:29.929969 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k
125 00:38:29.930161 makedir: /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin
126 00:38:29.930310 makedir: /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/tests
127 00:38:29.930451 makedir: /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/results
128 00:38:29.930615 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-add-keys
129 00:38:29.930823 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-add-sources
130 00:38:29.931006 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-background-process-start
131 00:38:29.931190 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-background-process-stop
132 00:38:29.931369 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-common-functions
133 00:38:29.931552 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-echo-ipv4
134 00:38:29.931740 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-install-packages
135 00:38:29.931926 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-installed-packages
136 00:38:29.932109 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-os-build
137 00:38:29.932294 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-probe-channel
138 00:38:29.932481 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-probe-ip
139 00:38:29.932666 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-target-ip
140 00:38:29.932852 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-target-mac
141 00:38:29.933036 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-target-storage
142 00:38:29.933232 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-case
143 00:38:29.933428 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-event
144 00:38:29.933617 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-feedback
145 00:38:29.933804 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-raise
146 00:38:29.933992 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-reference
147 00:38:29.934175 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-runner
148 00:38:29.934358 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-set
149 00:38:29.934550 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-test-shell
150 00:38:29.934736 Updating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-install-packages (oe)
151 00:38:29.934957 Updating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/bin/lava-installed-packages (oe)
152 00:38:29.935136 Creating /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/environment
153 00:38:29.935291 LAVA metadata
154 00:38:29.935404 - LAVA_JOB_ID=14173456
155 00:38:29.935508 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:38:29.935669 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:38:29.935775 skipped lava-vland-overlay
158 00:38:29.935897 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:38:29.936030 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:38:29.936135 skipped lava-multinode-overlay
161 00:38:29.936247 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:38:29.936384 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:38:29.936505 Loading test definitions
164 00:38:29.936649 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:38:29.936768 Using /lava-14173456 at stage 0
166 00:38:29.937239 uuid=14173456_1.5.2.3.1 testdef=None
167 00:38:29.937378 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:38:29.937510 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:38:29.938282 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:38:29.938642 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:38:29.939565 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:38:29.939928 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:38:29.940805 runner path: /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14173456_1.5.2.3.1
176 00:38:29.941024 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:38:29.941339 Creating lava-test-runner.conf files
179 00:38:29.941408 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173456/lava-overlay-4ok5x13k/lava-14173456/0 for stage 0
180 00:38:29.941506 - 0_v4l2-compliance-mtk-vcodec-enc
181 00:38:29.941608 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:38:29.941694 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:38:29.949028 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:38:29.949160 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:38:29.949250 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:38:29.949348 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:38:29.949434 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:38:30.880281 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:38:30.880750 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:38:30.880913 extracting modules file /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173456/extract-overlay-ramdisk-xa8djapx/ramdisk
191 00:38:31.135354 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:38:31.135540 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:38:31.135676 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173456/compress-overlay-sbab5uri/overlay-1.5.2.4.tar.gz to ramdisk
194 00:38:31.135786 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173456/compress-overlay-sbab5uri/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173456/extract-overlay-ramdisk-xa8djapx/ramdisk
195 00:38:31.143714 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:38:31.143852 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:38:31.143994 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:38:31.144135 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:38:31.144256 Building ramdisk /var/lib/lava/dispatcher/tmp/14173456/extract-overlay-ramdisk-xa8djapx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173456/extract-overlay-ramdisk-xa8djapx/ramdisk
200 00:38:31.878165 >> 275895 blocks
201 00:38:36.179360 rename /var/lib/lava/dispatcher/tmp/14173456/extract-overlay-ramdisk-xa8djapx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/ramdisk/ramdisk.cpio.gz
202 00:38:36.179924 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:38:36.180109 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:38:36.180255 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:38:36.180411 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/kernel/Image']
206 00:38:50.868185 Returned 0 in 14 seconds
207 00:38:50.968899 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/kernel/image.itb
208 00:38:51.616001 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:38:51.616362 output: Created: Wed Jun 5 01:38:51 2024
210 00:38:51.616468 output: Image 0 (kernel-1)
211 00:38:51.616573 output: Description:
212 00:38:51.616637 output: Created: Wed Jun 5 01:38:51 2024
213 00:38:51.616701 output: Type: Kernel Image
214 00:38:51.616761 output: Compression: lzma compressed
215 00:38:51.616820 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
216 00:38:51.616881 output: Architecture: AArch64
217 00:38:51.616941 output: OS: Linux
218 00:38:51.616997 output: Load Address: 0x00000000
219 00:38:51.617053 output: Entry Point: 0x00000000
220 00:38:51.617109 output: Hash algo: crc32
221 00:38:51.617164 output: Hash value: 4c96ec19
222 00:38:51.617219 output: Image 1 (fdt-1)
223 00:38:51.617301 output: Description: mt8192-asurada-spherion-r0
224 00:38:51.617369 output: Created: Wed Jun 5 01:38:51 2024
225 00:38:51.617421 output: Type: Flat Device Tree
226 00:38:51.617474 output: Compression: uncompressed
227 00:38:51.617526 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:38:51.617578 output: Architecture: AArch64
229 00:38:51.617629 output: Hash algo: crc32
230 00:38:51.617680 output: Hash value: 0f8e4d2e
231 00:38:51.617731 output: Image 2 (ramdisk-1)
232 00:38:51.617782 output: Description: unavailable
233 00:38:51.617833 output: Created: Wed Jun 5 01:38:51 2024
234 00:38:51.617884 output: Type: RAMDisk Image
235 00:38:51.617935 output: Compression: Unknown Compression
236 00:38:51.617986 output: Data Size: 41203118 Bytes = 40237.42 KiB = 39.29 MiB
237 00:38:51.618038 output: Architecture: AArch64
238 00:38:51.618090 output: OS: Linux
239 00:38:51.618141 output: Load Address: unavailable
240 00:38:51.618192 output: Entry Point: unavailable
241 00:38:51.618244 output: Hash algo: crc32
242 00:38:51.618295 output: Hash value: f6594b4c
243 00:38:51.618346 output: Default Configuration: 'conf-1'
244 00:38:51.618397 output: Configuration 0 (conf-1)
245 00:38:51.618448 output: Description: mt8192-asurada-spherion-r0
246 00:38:51.618516 output: Kernel: kernel-1
247 00:38:51.618631 output: Init Ramdisk: ramdisk-1
248 00:38:51.618697 output: FDT: fdt-1
249 00:38:51.618748 output: Loadables: kernel-1
250 00:38:51.618799 output:
251 00:38:51.619001 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 00:38:51.619097 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 00:38:51.619198 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 00:38:51.619288 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 00:38:51.619365 No LXC device requested
256 00:38:51.619442 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:38:51.619527 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 00:38:51.619612 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:38:51.619718 Checking files for TFTP limit of 4294967296 bytes.
260 00:38:51.620262 end: 1 tftp-deploy (duration 00:00:23) [common]
261 00:38:51.620367 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:38:51.620457 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:38:51.620579 substitutions:
264 00:38:51.620645 - {DTB}: 14173456/tftp-deploy-4vimbs3l/dtb/mt8192-asurada-spherion-r0.dtb
265 00:38:51.620709 - {INITRD}: 14173456/tftp-deploy-4vimbs3l/ramdisk/ramdisk.cpio.gz
266 00:38:51.620767 - {KERNEL}: 14173456/tftp-deploy-4vimbs3l/kernel/Image
267 00:38:51.620824 - {LAVA_MAC}: None
268 00:38:51.620880 - {PRESEED_CONFIG}: None
269 00:38:51.620934 - {PRESEED_LOCAL}: None
270 00:38:51.620988 - {RAMDISK}: 14173456/tftp-deploy-4vimbs3l/ramdisk/ramdisk.cpio.gz
271 00:38:51.621042 - {ROOT_PART}: None
272 00:38:51.621096 - {ROOT}: None
273 00:38:51.621152 - {SERVER_IP}: 192.168.201.1
274 00:38:51.621205 - {TEE}: None
275 00:38:51.621266 Parsed boot commands:
276 00:38:51.621355 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:38:51.621533 Parsed boot commands: tftpboot 192.168.201.1 14173456/tftp-deploy-4vimbs3l/kernel/image.itb 14173456/tftp-deploy-4vimbs3l/kernel/cmdline
278 00:38:51.621622 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:38:51.621709 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:38:51.621797 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:38:51.621876 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:38:51.621946 Not connected, no need to disconnect.
283 00:38:51.622017 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:38:51.622092 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:38:51.622159 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 00:38:51.626045 Setting prompt string to ['lava-test: # ']
287 00:38:51.626427 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:38:51.626531 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:38:51.626676 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:38:51.626768 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:38:51.626965 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 00:39:05.597386 Returned 0 in 13 seconds
293 00:39:05.698012 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:39:05.698591 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:39:05.698690 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:39:05.698777 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:39:05.698842 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:39:05.698909 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:39:05.699314 [Enter `^Ec?' for help]
301 00:39:05.699395
302 00:39:05.699478
303 00:39:05.699558 F0: 102B 0000
304 00:39:05.699638
305 00:39:05.699717 F3: 1001 0000 [0200]
306 00:39:05.699797
307 00:39:05.699895 F3: 1001 0000
308 00:39:05.699993
309 00:39:05.700087 F7: 102D 0000
310 00:39:05.700180
311 00:39:05.700272 F1: 0000 0000
312 00:39:05.700365
313 00:39:05.700457 V0: 0000 0000 [0001]
314 00:39:05.700549
315 00:39:05.700641 00: 0007 8000
316 00:39:05.700738
317 00:39:05.700830 01: 0000 0000
318 00:39:05.700925
319 00:39:05.701017 BP: 0C00 0209 [0000]
320 00:39:05.701109
321 00:39:05.701201 G0: 1182 0000
322 00:39:05.701334
323 00:39:05.701427 EC: 0000 0021 [4000]
324 00:39:05.701519
325 00:39:05.701611 S7: 0000 0000 [0000]
326 00:39:05.701703
327 00:39:05.701793 CC: 0000 0000 [0001]
328 00:39:05.701884
329 00:39:05.701975 T0: 0000 0040 [010F]
330 00:39:05.702066
331 00:39:05.702156 Jump to BL
332 00:39:05.702247
333 00:39:05.702337
334 00:39:05.702427
335 00:39:05.702518 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:39:05.702615 ARM64: Exception handlers installed.
337 00:39:05.702710 ARM64: Testing exception
338 00:39:05.702801 ARM64: Done test exception
339 00:39:05.702892 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:39:05.702984 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:39:05.703075 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:39:05.703166 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:39:05.703258 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:39:05.703349 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:39:05.703440 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:39:05.703534 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:39:05.703630 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:39:05.703723 WDT: Last reset was cold boot
349 00:39:05.703809 SPI1(PAD0) initialized at 2873684 Hz
350 00:39:05.703892 SPI5(PAD0) initialized at 992727 Hz
351 00:39:05.703974 VBOOT: Loading verstage.
352 00:39:05.704057 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:39:05.704141 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:39:05.704276 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:39:05.704376 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:39:05.704460 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:39:05.704544 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:39:05.704647 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 00:39:05.704786
360 00:39:05.704867
361 00:39:05.704951 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:39:05.705034 ARM64: Exception handlers installed.
363 00:39:05.705154 ARM64: Testing exception
364 00:39:05.705236 ARM64: Done test exception
365 00:39:05.705360 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:39:05.705444 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:39:05.705526 Probing TPM: . done!
368 00:39:05.705608 TPM ready after 0 ms
369 00:39:05.705690 Connected to device vid:did:rid of 1ae0:0028:00
370 00:39:05.705773 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 00:39:05.705856 Initialized TPM device CR50 revision 0
372 00:39:05.705939 tlcl_send_startup: Startup return code is 0
373 00:39:05.706021 TPM: setup succeeded
374 00:39:05.706104 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:39:05.706187 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:39:05.706270 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:39:05.706352 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:39:05.706434 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:39:05.706517 in-header: 03 07 00 00 08 00 00 00
380 00:39:05.706599 in-data: aa e4 47 04 13 02 00 00
381 00:39:05.706747 Chrome EC: UHEPI supported
382 00:39:05.706830 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:39:05.706913 in-header: 03 a9 00 00 08 00 00 00
384 00:39:05.706994 in-data: 84 60 60 08 00 00 00 00
385 00:39:05.707075 Phase 1
386 00:39:05.707157 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:39:05.707240 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:39:05.707323 VB2:vb2_check_recovery() Recovery was requested manually
389 00:39:05.707423 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:39:05.707554 Recovery requested (1009000e)
391 00:39:05.707636 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:39:05.707751 tlcl_extend: response is 0
393 00:39:05.707849 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:39:05.707942 tlcl_extend: response is 0
395 00:39:05.707999 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:39:05.708056 read SPI 0x210d4 0x2173b: 15141 us, 9049 KB/s, 72.392 Mbps
397 00:39:05.708109 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:39:05.708162
399 00:39:05.708215
400 00:39:05.708267 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:39:05.708320 ARM64: Exception handlers installed.
402 00:39:05.708372 ARM64: Testing exception
403 00:39:05.708425 ARM64: Done test exception
404 00:39:05.708477 pmic_efuse_setting: Set efuses in 11 msecs
405 00:39:05.708529 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:39:05.708580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:39:05.708633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:39:05.708889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:39:05.708980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:39:05.709064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:39:05.709147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:39:05.709230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:39:05.709339 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:39:05.709394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:39:05.709447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:39:05.709500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:39:05.709553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:39:05.709605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:39:05.709657 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:39:05.709710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:39:05.709762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:39:05.709815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:39:05.709867 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:39:05.709919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:39:05.709971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:39:05.710024 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:39:05.710076 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:39:05.710129 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:39:05.710181 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:39:05.710233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:39:05.710286 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:39:05.710338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:39:05.710391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:39:05.710442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:39:05.710495 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:39:05.710547 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:39:05.710599 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:39:05.710651 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:39:05.710703 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:39:05.710755 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:39:05.710827 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:39:05.710911 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:39:05.710981 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:39:05.711033 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:39:05.711085 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:39:05.711137 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:39:05.711189 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:39:05.711241 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:39:05.711292 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:39:05.711343 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:39:05.711395 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:39:05.711447 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:39:05.711532 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:39:05.711584 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:39:05.711637 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:39:05.711689 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:39:05.711740 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:39:05.711793 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:39:05.711845 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:39:05.711897 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:39:05.711950 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:39:05.712002 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:39:05.712055 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:39:05.712106 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:39:05.712158 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
466 00:39:05.712210 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:39:05.712262 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 00:39:05.712314 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:39:05.712366 [RTC]rtc_get_frequency_meter,154: input=15, output=853
470 00:39:05.712418 [RTC]rtc_get_frequency_meter,154: input=7, output=726
471 00:39:05.712470 [RTC]rtc_get_frequency_meter,154: input=11, output=789
472 00:39:05.712522 [RTC]rtc_get_frequency_meter,154: input=13, output=821
473 00:39:05.712574 [RTC]rtc_get_frequency_meter,154: input=12, output=805
474 00:39:05.712648 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 00:39:05.712716 [RTC]rtc_get_frequency_meter,154: input=12, output=806
476 00:39:05.712768 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 00:39:05.712820 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 00:39:05.713065 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:39:05.713174 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 00:39:05.713293 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:39:05.713402 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 00:39:05.713495 ADC[4]: Raw value=904064 ID=7
483 00:39:05.713588 ADC[3]: Raw value=213916 ID=1
484 00:39:05.713680 RAM Code: 0x71
485 00:39:05.713771 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:39:05.713864 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:39:05.713957 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:39:05.714048 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:39:05.714172 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:39:05.714265 in-header: 03 07 00 00 08 00 00 00
491 00:39:05.714358 in-data: aa e4 47 04 13 02 00 00
492 00:39:05.714464 Chrome EC: UHEPI supported
493 00:39:05.714564 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:39:05.714647 in-header: 03 a9 00 00 08 00 00 00
495 00:39:05.714730 in-data: 84 60 60 08 00 00 00 00
496 00:39:05.714812 MRC: failed to locate region type 0.
497 00:39:05.714895 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:39:05.714978 DRAM-K: Running full calibration
499 00:39:05.715060 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:39:05.715142 header.status = 0x0
501 00:39:05.715224 header.version = 0x6 (expected: 0x6)
502 00:39:05.715306 header.size = 0xd00 (expected: 0xd00)
503 00:39:05.715387 header.flags = 0x0
504 00:39:05.715470 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:39:05.715553 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 00:39:05.715636 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:39:05.715718 dram_init: ddr_geometry: 2
508 00:39:05.715799 [EMI] MDL number = 2
509 00:39:05.715880 [EMI] Get MDL freq = 0
510 00:39:05.715962 dram_init: ddr_type: 0
511 00:39:05.716042 is_discrete_lpddr4: 1
512 00:39:05.716124 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:39:05.716205
514 00:39:05.716286
515 00:39:05.716367 [Bian_co] ETT version 0.0.0.1
516 00:39:05.716449 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:39:05.716530
518 00:39:05.716612 dramc_set_vcore_voltage set vcore to 650000
519 00:39:05.716715 Read voltage for 800, 4
520 00:39:05.716808 Vio18 = 0
521 00:39:05.716905 Vcore = 650000
522 00:39:05.716986 Vdram = 0
523 00:39:05.717068 Vddq = 0
524 00:39:05.717149 Vmddr = 0
525 00:39:05.717231 dram_init: config_dvfs: 1
526 00:39:05.717352 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:39:05.717435 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:39:05.717518 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 00:39:05.717600 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 00:39:05.717685 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 00:39:05.717751 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 00:39:05.717805 MEM_TYPE=3, freq_sel=18
533 00:39:05.717858 sv_algorithm_assistance_LP4_1600
534 00:39:05.717909 ============ PULL DRAM RESETB DOWN ============
535 00:39:05.717982 ========== PULL DRAM RESETB DOWN end =========
536 00:39:05.718070 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:39:05.718168 ===================================
538 00:39:05.718251 LPDDR4 DRAM CONFIGURATION
539 00:39:05.718332 ===================================
540 00:39:05.718414 EX_ROW_EN[0] = 0x0
541 00:39:05.718495 EX_ROW_EN[1] = 0x0
542 00:39:05.718595 LP4Y_EN = 0x0
543 00:39:05.718709 WORK_FSP = 0x0
544 00:39:05.718806 WL = 0x2
545 00:39:05.718874 RL = 0x2
546 00:39:05.718926 BL = 0x2
547 00:39:05.718978 RPST = 0x0
548 00:39:05.719030 RD_PRE = 0x0
549 00:39:05.719081 WR_PRE = 0x1
550 00:39:05.719133 WR_PST = 0x0
551 00:39:05.719184 DBI_WR = 0x0
552 00:39:05.719236 DBI_RD = 0x0
553 00:39:05.719287 OTF = 0x1
554 00:39:05.719339 ===================================
555 00:39:05.719391 ===================================
556 00:39:05.719443 ANA top config
557 00:39:05.719494 ===================================
558 00:39:05.719547 DLL_ASYNC_EN = 0
559 00:39:05.719598 ALL_SLAVE_EN = 1
560 00:39:05.719650 NEW_RANK_MODE = 1
561 00:39:05.719702 DLL_IDLE_MODE = 1
562 00:39:05.719754 LP45_APHY_COMB_EN = 1
563 00:39:05.719805 TX_ODT_DIS = 1
564 00:39:05.719857 NEW_8X_MODE = 1
565 00:39:05.719910 ===================================
566 00:39:05.719962 ===================================
567 00:39:05.720014 data_rate = 1600
568 00:39:05.720066 CKR = 1
569 00:39:05.720117 DQ_P2S_RATIO = 8
570 00:39:05.720169 ===================================
571 00:39:05.720221 CA_P2S_RATIO = 8
572 00:39:05.720272 DQ_CA_OPEN = 0
573 00:39:05.720324 DQ_SEMI_OPEN = 0
574 00:39:05.720375 CA_SEMI_OPEN = 0
575 00:39:05.720426 CA_FULL_RATE = 0
576 00:39:05.720478 DQ_CKDIV4_EN = 1
577 00:39:05.720529 CA_CKDIV4_EN = 1
578 00:39:05.720580 CA_PREDIV_EN = 0
579 00:39:05.720631 PH8_DLY = 0
580 00:39:05.720683 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:39:05.720734 DQ_AAMCK_DIV = 4
582 00:39:05.720786 CA_AAMCK_DIV = 4
583 00:39:05.720838 CA_ADMCK_DIV = 4
584 00:39:05.720889 DQ_TRACK_CA_EN = 0
585 00:39:05.720940 CA_PICK = 800
586 00:39:05.721016 CA_MCKIO = 800
587 00:39:05.721115 MCKIO_SEMI = 0
588 00:39:05.721197 PLL_FREQ = 3068
589 00:39:05.721295 DQ_UI_PI_RATIO = 32
590 00:39:05.721365 CA_UI_PI_RATIO = 0
591 00:39:05.721417 ===================================
592 00:39:05.721469 ===================================
593 00:39:05.721522 memory_type:LPDDR4
594 00:39:05.721574 GP_NUM : 10
595 00:39:05.721626 SRAM_EN : 1
596 00:39:05.721678 MD32_EN : 0
597 00:39:05.721949 ===================================
598 00:39:05.722038 [ANA_INIT] >>>>>>>>>>>>>>
599 00:39:05.722121 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:39:05.722208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:39:05.722290 ===================================
602 00:39:05.722387 data_rate = 1600,PCW = 0X7600
603 00:39:05.722492 ===================================
604 00:39:05.722572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:39:05.722683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:39:05.722772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:39:05.722846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:39:05.722920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:39:05.723011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:39:05.723104 [ANA_INIT] flow start
611 00:39:05.723195 [ANA_INIT] PLL >>>>>>>>
612 00:39:05.723286 [ANA_INIT] PLL <<<<<<<<
613 00:39:05.723377 [ANA_INIT] MIDPI >>>>>>>>
614 00:39:05.723468 [ANA_INIT] MIDPI <<<<<<<<
615 00:39:05.723558 [ANA_INIT] DLL >>>>>>>>
616 00:39:05.723648 [ANA_INIT] flow end
617 00:39:05.723739 ============ LP4 DIFF to SE enter ============
618 00:39:05.723830 ============ LP4 DIFF to SE exit ============
619 00:39:05.723921 [ANA_INIT] <<<<<<<<<<<<<
620 00:39:05.724011 [Flow] Enable top DCM control >>>>>
621 00:39:05.724102 [Flow] Enable top DCM control <<<<<
622 00:39:05.724192 Enable DLL master slave shuffle
623 00:39:05.724314 ==============================================================
624 00:39:05.724423 Gating Mode config
625 00:39:05.724528 ==============================================================
626 00:39:05.724619 Config description:
627 00:39:05.724710 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:39:05.724802 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:39:05.724894 SELPH_MODE 0: By rank 1: By Phase
630 00:39:05.724985 ==============================================================
631 00:39:05.725075 GAT_TRACK_EN = 1
632 00:39:05.725166 RX_GATING_MODE = 2
633 00:39:05.725264 RX_GATING_TRACK_MODE = 2
634 00:39:05.725388 SELPH_MODE = 1
635 00:39:05.725479 PICG_EARLY_EN = 1
636 00:39:05.725570 VALID_LAT_VALUE = 1
637 00:39:05.725661 ==============================================================
638 00:39:05.725752 Enter into Gating configuration >>>>
639 00:39:05.725842 Exit from Gating configuration <<<<
640 00:39:05.725932 Enter into DVFS_PRE_config >>>>>
641 00:39:05.726023 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:39:05.726117 Exit from DVFS_PRE_config <<<<<
643 00:39:05.726208 Enter into PICG configuration >>>>
644 00:39:05.726298 Exit from PICG configuration <<<<
645 00:39:05.726389 [RX_INPUT] configuration >>>>>
646 00:39:05.726479 [RX_INPUT] configuration <<<<<
647 00:39:05.726568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:39:05.726683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:39:05.726789 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:39:05.726880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:39:05.726970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:39:05.727061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:39:05.727151 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:39:05.727242 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:39:05.727333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:39:05.727423 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:39:05.727513 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:39:05.727604 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:39:05.727695 ===================================
660 00:39:05.727785 LPDDR4 DRAM CONFIGURATION
661 00:39:05.727875 ===================================
662 00:39:05.727965 EX_ROW_EN[0] = 0x0
663 00:39:05.728055 EX_ROW_EN[1] = 0x0
664 00:39:05.728145 LP4Y_EN = 0x0
665 00:39:05.728236 WORK_FSP = 0x0
666 00:39:05.728326 WL = 0x2
667 00:39:05.728416 RL = 0x2
668 00:39:05.728505 BL = 0x2
669 00:39:05.728595 RPST = 0x0
670 00:39:05.728684 RD_PRE = 0x0
671 00:39:05.728774 WR_PRE = 0x1
672 00:39:05.728863 WR_PST = 0x0
673 00:39:05.728953 DBI_WR = 0x0
674 00:39:05.729042 DBI_RD = 0x0
675 00:39:05.729132 OTF = 0x1
676 00:39:05.729222 ===================================
677 00:39:05.729355 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:39:05.729447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:39:05.729539 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:39:05.729630 ===================================
681 00:39:05.729721 LPDDR4 DRAM CONFIGURATION
682 00:39:05.729811 ===================================
683 00:39:05.729902 EX_ROW_EN[0] = 0x10
684 00:39:05.729992 EX_ROW_EN[1] = 0x0
685 00:39:05.730082 LP4Y_EN = 0x0
686 00:39:05.730172 WORK_FSP = 0x0
687 00:39:05.730262 WL = 0x2
688 00:39:05.730353 RL = 0x2
689 00:39:05.730443 BL = 0x2
690 00:39:05.730533 RPST = 0x0
691 00:39:05.730623 RD_PRE = 0x0
692 00:39:05.730713 WR_PRE = 0x1
693 00:39:05.730803 WR_PST = 0x0
694 00:39:05.730892 DBI_WR = 0x0
695 00:39:05.730982 DBI_RD = 0x0
696 00:39:05.731072 OTF = 0x1
697 00:39:05.731162 ===================================
698 00:39:05.731253 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:39:05.731344 nWR fixed to 40
700 00:39:05.731435 [ModeRegInit_LP4] CH0 RK0
701 00:39:05.731525 [ModeRegInit_LP4] CH0 RK1
702 00:39:05.731616 [ModeRegInit_LP4] CH1 RK0
703 00:39:05.731706 [ModeRegInit_LP4] CH1 RK1
704 00:39:05.731796 match AC timing 13
705 00:39:05.731886 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:39:05.732189 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:39:05.732282 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:39:05.732376 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:39:05.732470 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:39:05.732563 [EMI DOE] emi_dcm 0
711 00:39:05.732655 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:39:05.732748 ==
713 00:39:05.732841 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:39:05.732933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:39:05.733025 ==
716 00:39:05.733117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:39:05.733209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:39:05.733331 [CA 0] Center 37 (7~68) winsize 62
719 00:39:05.733437 [CA 1] Center 37 (7~68) winsize 62
720 00:39:05.733528 [CA 2] Center 34 (4~65) winsize 62
721 00:39:05.733618 [CA 3] Center 34 (4~65) winsize 62
722 00:39:05.733709 [CA 4] Center 33 (3~64) winsize 62
723 00:39:05.733801 [CA 5] Center 33 (3~64) winsize 62
724 00:39:05.733891
725 00:39:05.733982 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 00:39:05.734073
727 00:39:05.734164 [CATrainingPosCal] consider 1 rank data
728 00:39:05.734255 u2DelayCellTimex100 = 270/100 ps
729 00:39:05.734346 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 00:39:05.734437 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 00:39:05.734528 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 00:39:05.734619 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:39:05.734709 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 00:39:05.734800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:39:05.734890
736 00:39:05.734981 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:39:05.735071
738 00:39:05.735162 [CBTSetCACLKResult] CA Dly = 33
739 00:39:05.735252 CS Dly: 5 (0~36)
740 00:39:05.735342 ==
741 00:39:05.735434 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:39:05.735524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:39:05.735616 ==
744 00:39:05.735707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:39:05.735798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:39:05.735889 [CA 0] Center 38 (7~69) winsize 63
747 00:39:05.735980 [CA 1] Center 37 (7~68) winsize 62
748 00:39:05.736070 [CA 2] Center 35 (4~66) winsize 63
749 00:39:05.736160 [CA 3] Center 35 (4~66) winsize 63
750 00:39:05.736250 [CA 4] Center 34 (3~65) winsize 63
751 00:39:05.736340 [CA 5] Center 33 (3~64) winsize 62
752 00:39:05.736429
753 00:39:05.736520 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:39:05.736610
755 00:39:05.736700 [CATrainingPosCal] consider 2 rank data
756 00:39:05.736791 u2DelayCellTimex100 = 270/100 ps
757 00:39:05.736881 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 00:39:05.736972 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:39:05.737061 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 00:39:05.737152 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:39:05.737242 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 00:39:05.737371 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:39:05.737462
764 00:39:05.737552 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:39:05.737642
766 00:39:05.737732 [CBTSetCACLKResult] CA Dly = 33
767 00:39:05.737823 CS Dly: 6 (0~38)
768 00:39:05.737914
769 00:39:05.738004 ----->DramcWriteLeveling(PI) begin...
770 00:39:05.738099 ==
771 00:39:05.738190 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:39:05.738281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:39:05.738373 ==
774 00:39:05.738463 Write leveling (Byte 0): 28 => 28
775 00:39:05.738555 Write leveling (Byte 1): 28 => 28
776 00:39:05.738645 DramcWriteLeveling(PI) end<-----
777 00:39:05.738735
778 00:39:05.738825 ==
779 00:39:05.738916 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:39:05.739006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:39:05.739097 ==
782 00:39:05.739188 [Gating] SW mode calibration
783 00:39:05.739279 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:39:05.739370 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:39:05.739461 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:39:05.739552 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 00:39:05.739643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:39:05.739734 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:39:05.739824 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:39:05.739915 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:39:05.740005 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:39:05.740095 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:39:05.740186 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:39:05.740275 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:39:05.740365 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:39:05.740455 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:39:05.740544 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:39:05.740634 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:39:05.740724 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:39:05.740813 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:39:05.740902 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:39:05.740992 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
803 00:39:05.741082 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 00:39:05.741172 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 00:39:05.741266 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:39:05.741388 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:39:05.741479 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:39:05.741569 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:39:05.741660 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:39:05.741750 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:39:05.741840 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
812 00:39:05.741929 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 00:39:05.742020 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 00:39:05.742316 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:39:05.742408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:39:05.742502 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:39:05.742595 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:39:05.742711 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
819 00:39:05.742820 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
820 00:39:05.742912 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
821 00:39:05.743004 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:39:05.743095 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:39:05.743187 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:39:05.743278 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:39:05.743368 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:39:05.743459 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
827 00:39:05.743550 0 11 8 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (1 1)
828 00:39:05.743641 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
829 00:39:05.743731 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:39:05.743843 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:39:05.743943 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:39:05.744026 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:39:05.744109 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:39:05.744192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:39:05.744274 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 00:39:05.744356 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:39:05.744471 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:39:05.744560 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:39:05.744680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:39:05.744770 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:39:05.744859 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:39:05.744949 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:39:05.745039 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:39:05.745128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:39:05.745218 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:39:05.745348 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:39:05.745439 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:39:05.745530 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:39:05.745620 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:39:05.745711 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 00:39:05.745801 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 00:39:05.745891 Total UI for P1: 0, mck2ui 16
853 00:39:05.745982 best dqsien dly found for B0: ( 0, 14, 4)
854 00:39:05.746072 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 00:39:05.746162 Total UI for P1: 0, mck2ui 16
856 00:39:05.746253 best dqsien dly found for B1: ( 0, 14, 8)
857 00:39:05.746344 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 00:39:05.746434 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 00:39:05.746524
860 00:39:05.746615 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 00:39:05.746705 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 00:39:05.746797 [Gating] SW calibration Done
863 00:39:05.746919 ==
864 00:39:05.747013 Dram Type= 6, Freq= 0, CH_0, rank 0
865 00:39:05.747104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 00:39:05.747196 ==
867 00:39:05.747288 RX Vref Scan: 0
868 00:39:05.747380
869 00:39:05.747470 RX Vref 0 -> 0, step: 1
870 00:39:05.747561
871 00:39:05.747652 RX Delay -130 -> 252, step: 16
872 00:39:05.747742 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 00:39:05.747834 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 00:39:05.747925 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 00:39:05.748016 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 00:39:05.748107 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 00:39:05.748197 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 00:39:05.748288 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 00:39:05.748378 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 00:39:05.748469 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 00:39:05.748559 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 00:39:05.748649 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 00:39:05.748739 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 00:39:05.748829 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 00:39:05.748919 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 00:39:05.749010 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 00:39:05.749100 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 00:39:05.749190 ==
889 00:39:05.749308 Dram Type= 6, Freq= 0, CH_0, rank 0
890 00:39:05.749414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 00:39:05.749506 ==
892 00:39:05.749597 DQS Delay:
893 00:39:05.749689 DQS0 = 0, DQS1 = 0
894 00:39:05.749779 DQM Delay:
895 00:39:05.749870 DQM0 = 88, DQM1 = 75
896 00:39:05.749960 DQ Delay:
897 00:39:05.750051 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 00:39:05.750141 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 00:39:05.750232 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
900 00:39:05.750322 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 00:39:05.750412
902 00:39:05.750503
903 00:39:05.750594 ==
904 00:39:05.750684 Dram Type= 6, Freq= 0, CH_0, rank 0
905 00:39:05.750778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 00:39:05.750869 ==
907 00:39:05.750960
908 00:39:05.751051
909 00:39:05.751141 TX Vref Scan disable
910 00:39:05.751232 == TX Byte 0 ==
911 00:39:05.751322 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
912 00:39:05.751413 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
913 00:39:05.751504 == TX Byte 1 ==
914 00:39:05.751595 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
915 00:39:05.751685 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
916 00:39:05.751776 ==
917 00:39:05.751867 Dram Type= 6, Freq= 0, CH_0, rank 0
918 00:39:05.751957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 00:39:05.752049 ==
920 00:39:05.752140 TX Vref=22, minBit 3, minWin=26, winSum=437
921 00:39:05.752231 TX Vref=24, minBit 7, minWin=26, winSum=444
922 00:39:05.752536 TX Vref=26, minBit 0, minWin=27, winSum=444
923 00:39:05.752631 TX Vref=28, minBit 4, minWin=27, winSum=452
924 00:39:05.752725 TX Vref=30, minBit 1, minWin=27, winSum=448
925 00:39:05.752819 TX Vref=32, minBit 1, minWin=28, winSum=454
926 00:39:05.752912 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 32
927 00:39:05.753005
928 00:39:05.753097 Final TX Range 1 Vref 32
929 00:39:05.753188
930 00:39:05.753308 ==
931 00:39:05.753413 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:39:05.753505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:39:05.753597 ==
934 00:39:05.753688
935 00:39:05.753778
936 00:39:05.753869 TX Vref Scan disable
937 00:39:05.753959 == TX Byte 0 ==
938 00:39:05.754049 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
939 00:39:05.754140 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
940 00:39:05.754231 == TX Byte 1 ==
941 00:39:05.754322 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 00:39:05.754412 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 00:39:05.754507
944 00:39:05.754597 [DATLAT]
945 00:39:05.754687 Freq=800, CH0 RK0
946 00:39:05.754809
947 00:39:05.754899 DATLAT Default: 0xa
948 00:39:05.754989 0, 0xFFFF, sum = 0
949 00:39:05.755081 1, 0xFFFF, sum = 0
950 00:39:05.755174 2, 0xFFFF, sum = 0
951 00:39:05.755265 3, 0xFFFF, sum = 0
952 00:39:05.755357 4, 0xFFFF, sum = 0
953 00:39:05.755448 5, 0xFFFF, sum = 0
954 00:39:05.755540 6, 0xFFFF, sum = 0
955 00:39:05.755631 7, 0xFFFF, sum = 0
956 00:39:05.755723 8, 0xFFFF, sum = 0
957 00:39:05.755815 9, 0x0, sum = 1
958 00:39:05.755907 10, 0x0, sum = 2
959 00:39:05.755999 11, 0x0, sum = 3
960 00:39:05.756090 12, 0x0, sum = 4
961 00:39:05.756182 best_step = 10
962 00:39:05.756272
963 00:39:05.756361 ==
964 00:39:05.756451 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:39:05.756541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 00:39:05.756632 ==
967 00:39:05.756722 RX Vref Scan: 1
968 00:39:05.756812
969 00:39:05.756902 Set Vref Range= 32 -> 127
970 00:39:05.756992
971 00:39:05.757082 RX Vref 32 -> 127, step: 1
972 00:39:05.757171
973 00:39:05.757264 RX Delay -111 -> 252, step: 8
974 00:39:05.757387
975 00:39:05.757477 Set Vref, RX VrefLevel [Byte0]: 32
976 00:39:05.757567 [Byte1]: 32
977 00:39:05.757657
978 00:39:05.757747 Set Vref, RX VrefLevel [Byte0]: 33
979 00:39:05.757837 [Byte1]: 33
980 00:39:05.757927
981 00:39:05.758016 Set Vref, RX VrefLevel [Byte0]: 34
982 00:39:05.758105 [Byte1]: 34
983 00:39:05.758195
984 00:39:05.758285 Set Vref, RX VrefLevel [Byte0]: 35
985 00:39:05.758375 [Byte1]: 35
986 00:39:05.758465
987 00:39:05.758554 Set Vref, RX VrefLevel [Byte0]: 36
988 00:39:05.758644 [Byte1]: 36
989 00:39:05.758734
990 00:39:05.758823 Set Vref, RX VrefLevel [Byte0]: 37
991 00:39:05.758913 [Byte1]: 37
992 00:39:05.759003
993 00:39:05.759093 Set Vref, RX VrefLevel [Byte0]: 38
994 00:39:05.759182 [Byte1]: 38
995 00:39:05.759272
996 00:39:05.759362 Set Vref, RX VrefLevel [Byte0]: 39
997 00:39:05.759454 [Byte1]: 39
998 00:39:05.759544
999 00:39:05.759633 Set Vref, RX VrefLevel [Byte0]: 40
1000 00:39:05.759723 [Byte1]: 40
1001 00:39:05.759812
1002 00:39:05.759902 Set Vref, RX VrefLevel [Byte0]: 41
1003 00:39:05.759992 [Byte1]: 41
1004 00:39:05.760081
1005 00:39:05.760171 Set Vref, RX VrefLevel [Byte0]: 42
1006 00:39:05.760260 [Byte1]: 42
1007 00:39:05.760350
1008 00:39:05.760440 Set Vref, RX VrefLevel [Byte0]: 43
1009 00:39:05.760529 [Byte1]: 43
1010 00:39:05.760619
1011 00:39:05.760708 Set Vref, RX VrefLevel [Byte0]: 44
1012 00:39:05.760798 [Byte1]: 44
1013 00:39:05.760891
1014 00:39:05.760981 Set Vref, RX VrefLevel [Byte0]: 45
1015 00:39:05.761071 [Byte1]: 45
1016 00:39:05.761161
1017 00:39:05.761252 Set Vref, RX VrefLevel [Byte0]: 46
1018 00:39:05.761382 [Byte1]: 46
1019 00:39:05.761505
1020 00:39:05.761595 Set Vref, RX VrefLevel [Byte0]: 47
1021 00:39:05.761685 [Byte1]: 47
1022 00:39:05.761775
1023 00:39:05.761865 Set Vref, RX VrefLevel [Byte0]: 48
1024 00:39:05.761955 [Byte1]: 48
1025 00:39:05.762052
1026 00:39:05.762145 Set Vref, RX VrefLevel [Byte0]: 49
1027 00:39:05.762237 [Byte1]: 49
1028 00:39:05.762328
1029 00:39:05.762418 Set Vref, RX VrefLevel [Byte0]: 50
1030 00:39:05.762508 [Byte1]: 50
1031 00:39:05.762598
1032 00:39:05.762688 Set Vref, RX VrefLevel [Byte0]: 51
1033 00:39:05.762778 [Byte1]: 51
1034 00:39:05.762867
1035 00:39:05.762956 Set Vref, RX VrefLevel [Byte0]: 52
1036 00:39:05.763045 [Byte1]: 52
1037 00:39:05.763133
1038 00:39:05.763222 Set Vref, RX VrefLevel [Byte0]: 53
1039 00:39:05.763311 [Byte1]: 53
1040 00:39:05.763400
1041 00:39:05.763488 Set Vref, RX VrefLevel [Byte0]: 54
1042 00:39:05.763577 [Byte1]: 54
1043 00:39:05.763666
1044 00:39:05.763754 Set Vref, RX VrefLevel [Byte0]: 55
1045 00:39:05.763843 [Byte1]: 55
1046 00:39:05.763931
1047 00:39:05.764019 Set Vref, RX VrefLevel [Byte0]: 56
1048 00:39:05.764108 [Byte1]: 56
1049 00:39:05.764196
1050 00:39:05.764284 Set Vref, RX VrefLevel [Byte0]: 57
1051 00:39:05.764373 [Byte1]: 57
1052 00:39:05.764461
1053 00:39:05.764549 Set Vref, RX VrefLevel [Byte0]: 58
1054 00:39:05.764638 [Byte1]: 58
1055 00:39:05.764726
1056 00:39:05.764815 Set Vref, RX VrefLevel [Byte0]: 59
1057 00:39:05.764903 [Byte1]: 59
1058 00:39:05.764992
1059 00:39:05.765079 Set Vref, RX VrefLevel [Byte0]: 60
1060 00:39:05.765168 [Byte1]: 60
1061 00:39:05.765260
1062 00:39:05.765350 Set Vref, RX VrefLevel [Byte0]: 61
1063 00:39:05.765438 [Byte1]: 61
1064 00:39:05.765527
1065 00:39:05.765615 Set Vref, RX VrefLevel [Byte0]: 62
1066 00:39:05.765703 [Byte1]: 62
1067 00:39:05.765792
1068 00:39:05.765880 Set Vref, RX VrefLevel [Byte0]: 63
1069 00:39:05.765968 [Byte1]: 63
1070 00:39:05.766056
1071 00:39:05.766145 Set Vref, RX VrefLevel [Byte0]: 64
1072 00:39:05.766234 [Byte1]: 64
1073 00:39:05.766322
1074 00:39:05.766409 Set Vref, RX VrefLevel [Byte0]: 65
1075 00:39:05.766497 [Byte1]: 65
1076 00:39:05.766586
1077 00:39:05.766673 Set Vref, RX VrefLevel [Byte0]: 66
1078 00:39:05.766762 [Byte1]: 66
1079 00:39:05.766851
1080 00:39:05.766939 Set Vref, RX VrefLevel [Byte0]: 67
1081 00:39:05.767027 [Byte1]: 67
1082 00:39:05.767115
1083 00:39:05.767203 Set Vref, RX VrefLevel [Byte0]: 68
1084 00:39:05.767292 [Byte1]: 68
1085 00:39:05.767380
1086 00:39:05.767468 Set Vref, RX VrefLevel [Byte0]: 69
1087 00:39:05.767557 [Byte1]: 69
1088 00:39:05.767645
1089 00:39:05.767733 Set Vref, RX VrefLevel [Byte0]: 70
1090 00:39:05.768032 [Byte1]: 70
1091 00:39:05.768125
1092 00:39:05.768216 Set Vref, RX VrefLevel [Byte0]: 71
1093 00:39:05.768306 [Byte1]: 71
1094 00:39:05.768397
1095 00:39:05.768486 Set Vref, RX VrefLevel [Byte0]: 72
1096 00:39:05.768580 [Byte1]: 72
1097 00:39:05.768671
1098 00:39:05.768760 Set Vref, RX VrefLevel [Byte0]: 73
1099 00:39:05.768850 [Byte1]: 73
1100 00:39:05.768940
1101 00:39:05.769029 Set Vref, RX VrefLevel [Byte0]: 74
1102 00:39:05.769118 [Byte1]: 74
1103 00:39:05.769208
1104 00:39:05.769339 Set Vref, RX VrefLevel [Byte0]: 75
1105 00:39:05.769429 [Byte1]: 75
1106 00:39:05.769518
1107 00:39:05.769607 Set Vref, RX VrefLevel [Byte0]: 76
1108 00:39:05.769696 [Byte1]: 76
1109 00:39:05.769785
1110 00:39:05.769873 Set Vref, RX VrefLevel [Byte0]: 77
1111 00:39:05.769962 [Byte1]: 77
1112 00:39:05.770051
1113 00:39:05.770140 Final RX Vref Byte 0 = 56 to rank0
1114 00:39:05.770229 Final RX Vref Byte 1 = 59 to rank0
1115 00:39:05.770318 Final RX Vref Byte 0 = 56 to rank1
1116 00:39:05.770407 Final RX Vref Byte 1 = 59 to rank1==
1117 00:39:05.770497 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 00:39:05.770586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 00:39:05.770676 ==
1120 00:39:05.770765 DQS Delay:
1121 00:39:05.770854 DQS0 = 0, DQS1 = 0
1122 00:39:05.770942 DQM Delay:
1123 00:39:05.771031 DQM0 = 88, DQM1 = 76
1124 00:39:05.771119 DQ Delay:
1125 00:39:05.771208 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1126 00:39:05.771297 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1127 00:39:05.771388 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1128 00:39:05.771477 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1129 00:39:05.771566
1130 00:39:05.771653
1131 00:39:05.771742 [DQSOSCAuto] RK0, (LSB)MR18= 0x312b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1132 00:39:05.771832 CH0 RK0: MR19=606, MR18=312B
1133 00:39:05.771921 CH0_RK0: MR19=0x606, MR18=0x312B, DQSOSC=397, MR23=63, INC=93, DEC=62
1134 00:39:05.772010
1135 00:39:05.772098 ----->DramcWriteLeveling(PI) begin...
1136 00:39:05.772188 ==
1137 00:39:05.772278 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 00:39:05.772367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 00:39:05.772456 ==
1140 00:39:05.772545 Write leveling (Byte 0): 29 => 29
1141 00:39:05.772634 Write leveling (Byte 1): 28 => 28
1142 00:39:05.772723 DramcWriteLeveling(PI) end<-----
1143 00:39:05.772812
1144 00:39:05.772900 ==
1145 00:39:05.772989 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 00:39:05.773078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 00:39:05.773167 ==
1148 00:39:05.773261 [Gating] SW mode calibration
1149 00:39:05.773387 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 00:39:05.773477 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 00:39:05.773567 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 00:39:05.773656 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 00:39:05.773745 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 00:39:05.773834 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:39:05.773923 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:39:05.774012 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:39:05.774100 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:39:05.774189 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:39:05.774278 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:39:05.774366 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:39:05.774454 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:39:05.774543 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:39:05.774632 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:39:05.774721 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:39:05.774860 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:39:05.774963 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:39:05.775053 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:39:05.775142 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 00:39:05.775231 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1170 00:39:05.775320 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:39:05.775408 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:39:05.775497 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:39:05.775586 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:39:05.775675 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:39:05.775766 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:39:05.775855 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1177 00:39:05.775944 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (1 1) (1 1)
1178 00:39:05.776032 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 00:39:05.776120 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:39:05.776209 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:39:05.776297 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:39:05.776386 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:39:05.776474 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:39:05.776562 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1185 00:39:05.776651 0 10 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
1186 00:39:05.776740 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:39:05.776829 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:39:05.776917 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:39:05.777006 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:39:05.777096 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:39:05.777185 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:39:05.777296 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1193 00:39:05.777400 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1194 00:39:05.777488 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1195 00:39:05.777577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:39:05.777666 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:39:05.777966 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:39:05.778097 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:39:05.778190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:39:05.778281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1201 00:39:05.778372 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 00:39:05.778462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:39:05.778552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:39:05.778642 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:39:05.778732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:39:05.778823 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:39:05.778929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:39:05.779092 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:39:05.779194 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:39:05.779284 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:39:05.779373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:39:05.779462 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:39:05.779550 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:39:05.779639 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:39:05.779728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:39:05.779817 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1217 00:39:05.779905 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 00:39:05.779994 Total UI for P1: 0, mck2ui 16
1219 00:39:05.780084 best dqsien dly found for B0: ( 0, 14, 4)
1220 00:39:05.780173 Total UI for P1: 0, mck2ui 16
1221 00:39:05.780263 best dqsien dly found for B1: ( 0, 14, 4)
1222 00:39:05.780351 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 00:39:05.780440 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1224 00:39:05.780532
1225 00:39:05.780620 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 00:39:05.780710 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1227 00:39:05.780799 [Gating] SW calibration Done
1228 00:39:05.780888 ==
1229 00:39:05.780977 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 00:39:05.781067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 00:39:05.781156 ==
1232 00:39:05.781245 RX Vref Scan: 0
1233 00:39:05.781378
1234 00:39:05.781467 RX Vref 0 -> 0, step: 1
1235 00:39:05.781556
1236 00:39:05.781645 RX Delay -130 -> 252, step: 16
1237 00:39:05.781734 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1238 00:39:05.781823 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1239 00:39:05.781912 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1240 00:39:05.782001 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1241 00:39:05.782090 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1242 00:39:05.782178 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1243 00:39:05.782267 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1244 00:39:05.782355 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1245 00:39:05.782443 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1246 00:39:05.782532 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1247 00:39:05.782621 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1248 00:39:05.782709 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1249 00:39:05.782798 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1250 00:39:05.782886 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1251 00:39:05.782974 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1252 00:39:05.783062 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1253 00:39:05.783149 ==
1254 00:39:05.783238 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 00:39:05.783327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 00:39:05.783416 ==
1257 00:39:05.783505 DQS Delay:
1258 00:39:05.783593 DQS0 = 0, DQS1 = 0
1259 00:39:05.783681 DQM Delay:
1260 00:39:05.783770 DQM0 = 84, DQM1 = 77
1261 00:39:05.783858 DQ Delay:
1262 00:39:05.783947 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1263 00:39:05.784036 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1264 00:39:05.784125 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1265 00:39:05.784214 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1266 00:39:05.784302
1267 00:39:05.784390
1268 00:39:05.784478 ==
1269 00:39:05.784567 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 00:39:05.784656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 00:39:05.784747 ==
1272 00:39:05.784865
1273 00:39:05.784954
1274 00:39:05.785043 TX Vref Scan disable
1275 00:39:05.785132 == TX Byte 0 ==
1276 00:39:05.785220 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1277 00:39:05.785354 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1278 00:39:05.785444 == TX Byte 1 ==
1279 00:39:05.785533 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1280 00:39:05.785622 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1281 00:39:05.785711 ==
1282 00:39:05.785801 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 00:39:05.785890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 00:39:05.785979 ==
1285 00:39:05.786068 TX Vref=22, minBit 1, minWin=26, winSum=438
1286 00:39:05.786159 TX Vref=24, minBit 0, minWin=27, winSum=443
1287 00:39:05.786248 TX Vref=26, minBit 0, minWin=27, winSum=447
1288 00:39:05.786338 TX Vref=28, minBit 6, minWin=27, winSum=454
1289 00:39:05.786427 TX Vref=30, minBit 6, minWin=27, winSum=452
1290 00:39:05.786516 TX Vref=32, minBit 5, minWin=27, winSum=450
1291 00:39:05.786605 [TxChooseVref] Worse bit 6, Min win 27, Win sum 454, Final Vref 28
1292 00:39:05.786695
1293 00:39:05.786784 Final TX Range 1 Vref 28
1294 00:39:05.786873
1295 00:39:05.786959 ==
1296 00:39:05.787046 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 00:39:05.787136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 00:39:05.787227 ==
1299 00:39:05.787311
1300 00:39:05.787392
1301 00:39:05.787472 TX Vref Scan disable
1302 00:39:05.787553 == TX Byte 0 ==
1303 00:39:05.787632 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1304 00:39:05.787713 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1305 00:39:05.787797 == TX Byte 1 ==
1306 00:39:05.787880 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1307 00:39:05.787962 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1308 00:39:05.788044
1309 00:39:05.788124 [DATLAT]
1310 00:39:05.788205 Freq=800, CH0 RK1
1311 00:39:05.788287
1312 00:39:05.788367 DATLAT Default: 0xa
1313 00:39:05.788447 0, 0xFFFF, sum = 0
1314 00:39:05.788531 1, 0xFFFF, sum = 0
1315 00:39:05.788617 2, 0xFFFF, sum = 0
1316 00:39:05.788701 3, 0xFFFF, sum = 0
1317 00:39:05.788783 4, 0xFFFF, sum = 0
1318 00:39:05.788865 5, 0xFFFF, sum = 0
1319 00:39:05.788949 6, 0xFFFF, sum = 0
1320 00:39:05.789030 7, 0xFFFF, sum = 0
1321 00:39:05.789111 8, 0xFFFF, sum = 0
1322 00:39:05.789193 9, 0x0, sum = 1
1323 00:39:05.789303 10, 0x0, sum = 2
1324 00:39:05.789400 11, 0x0, sum = 3
1325 00:39:05.789739 12, 0x0, sum = 4
1326 00:39:05.789891 best_step = 10
1327 00:39:05.789990
1328 00:39:05.790073 ==
1329 00:39:05.790158 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 00:39:05.790278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 00:39:05.790361 ==
1332 00:39:05.790441 RX Vref Scan: 0
1333 00:39:05.790551
1334 00:39:05.790631 RX Vref 0 -> 0, step: 1
1335 00:39:05.790711
1336 00:39:05.790791 RX Delay -95 -> 252, step: 8
1337 00:39:05.790872 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1338 00:39:05.790953 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 00:39:05.791036 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1340 00:39:05.791147 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1341 00:39:05.791231 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 00:39:05.791312 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 00:39:05.791392 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 00:39:05.791472 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1345 00:39:05.791553 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1346 00:39:05.791663 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1347 00:39:05.791743 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 00:39:05.791851 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1349 00:39:05.791931 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1350 00:39:05.792010 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1351 00:39:05.792123 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 00:39:05.792202 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1353 00:39:05.792282 ==
1354 00:39:05.792362 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 00:39:05.792473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 00:39:05.792554 ==
1357 00:39:05.792633 DQS Delay:
1358 00:39:05.792713 DQS0 = 0, DQS1 = 0
1359 00:39:05.792794 DQM Delay:
1360 00:39:05.792873 DQM0 = 86, DQM1 = 76
1361 00:39:05.792987 DQ Delay:
1362 00:39:05.793067 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1363 00:39:05.793147 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 00:39:05.793245 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1365 00:39:05.793353 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1366 00:39:05.793433
1367 00:39:05.793513
1368 00:39:05.793624 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1369 00:39:05.793706 CH0 RK1: MR19=606, MR18=2E29
1370 00:39:05.793787 CH0_RK1: MR19=0x606, MR18=0x2E29, DQSOSC=398, MR23=63, INC=93, DEC=62
1371 00:39:05.793869 [RxdqsGatingPostProcess] freq 800
1372 00:39:05.793949 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 00:39:05.794027 Pre-setting of DQS Precalculation
1374 00:39:05.794103 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 00:39:05.794207 ==
1376 00:39:05.794282 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 00:39:05.794358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 00:39:05.794437 ==
1379 00:39:05.794548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 00:39:05.794631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 00:39:05.794714 [CA 0] Center 37 (6~68) winsize 63
1382 00:39:05.794795 [CA 1] Center 36 (6~67) winsize 62
1383 00:39:05.794877 [CA 2] Center 35 (5~65) winsize 61
1384 00:39:05.794959 [CA 3] Center 34 (4~65) winsize 62
1385 00:39:05.795039 [CA 4] Center 34 (4~65) winsize 62
1386 00:39:05.795121 [CA 5] Center 34 (3~65) winsize 63
1387 00:39:05.795233
1388 00:39:05.795312 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1389 00:39:05.795390
1390 00:39:05.795489 [CATrainingPosCal] consider 1 rank data
1391 00:39:05.795583 u2DelayCellTimex100 = 270/100 ps
1392 00:39:05.795674 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1393 00:39:05.795762 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 00:39:05.795853 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1395 00:39:05.795945 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 00:39:05.796035 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 00:39:05.796159 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1398 00:39:05.796261
1399 00:39:05.796364 CA PerBit enable=1, Macro0, CA PI delay=34
1400 00:39:05.796461
1401 00:39:05.796572 [CBTSetCACLKResult] CA Dly = 34
1402 00:39:05.796653 CS Dly: 4 (0~35)
1403 00:39:05.796733 ==
1404 00:39:05.796814 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 00:39:05.796895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 00:39:05.796976 ==
1407 00:39:05.797096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 00:39:05.797195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 00:39:05.797300 [CA 0] Center 36 (6~67) winsize 62
1410 00:39:05.797382 [CA 1] Center 36 (6~67) winsize 62
1411 00:39:05.797462 [CA 2] Center 34 (4~65) winsize 62
1412 00:39:05.797542 [CA 3] Center 34 (3~65) winsize 63
1413 00:39:05.797622 [CA 4] Center 34 (4~65) winsize 62
1414 00:39:05.797702 [CA 5] Center 33 (3~64) winsize 62
1415 00:39:05.797781
1416 00:39:05.797862 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 00:39:05.797941
1418 00:39:05.798021 [CATrainingPosCal] consider 2 rank data
1419 00:39:05.798101 u2DelayCellTimex100 = 270/100 ps
1420 00:39:05.798181 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 00:39:05.798261 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1422 00:39:05.798342 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1423 00:39:05.798421 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 00:39:05.798501 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1425 00:39:05.798581 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 00:39:05.798660
1427 00:39:05.798740 CA PerBit enable=1, Macro0, CA PI delay=33
1428 00:39:05.798819
1429 00:39:05.798898 [CBTSetCACLKResult] CA Dly = 33
1430 00:39:05.798978 CS Dly: 5 (0~38)
1431 00:39:05.799056
1432 00:39:05.799136 ----->DramcWriteLeveling(PI) begin...
1433 00:39:05.799216 ==
1434 00:39:05.799296 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 00:39:05.799377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 00:39:05.799456 ==
1437 00:39:05.799536 Write leveling (Byte 0): 25 => 25
1438 00:39:05.799616 Write leveling (Byte 1): 26 => 26
1439 00:39:05.799696 DramcWriteLeveling(PI) end<-----
1440 00:39:05.799774
1441 00:39:05.799852 ==
1442 00:39:05.799932 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 00:39:05.800012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 00:39:05.800091 ==
1445 00:39:05.800171 [Gating] SW mode calibration
1446 00:39:05.800251 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 00:39:05.800332 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 00:39:05.800412 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 00:39:05.800493 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1450 00:39:05.800786 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1451 00:39:05.800873 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:39:05.800955 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:39:05.801035 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:39:05.801116 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:39:05.801197 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:39:05.801317 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:39:05.801399 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:39:05.801480 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:39:05.801560 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:39:05.801641 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:39:05.801721 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:39:05.801801 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:39:05.801881 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:39:05.801962 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1465 00:39:05.802042 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1466 00:39:05.802122 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:39:05.802202 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:39:05.802283 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:39:05.802363 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:39:05.802443 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:39:05.802523 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:39:05.802603 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:39:05.802683 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1474 00:39:05.802763 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (0 0)
1475 00:39:05.802843 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 00:39:05.802924 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 00:39:05.803004 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:39:05.803084 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:39:05.803164 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:39:05.803244 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1481 00:39:05.803324 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 1)
1482 00:39:05.803405 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1483 00:39:05.803485 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:39:05.803565 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:39:05.803645 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:39:05.803728 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:39:05.803822 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:39:05.803913 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:39:05.803995 0 11 4 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
1490 00:39:05.804076 0 11 8 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
1491 00:39:05.804156 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 00:39:05.804236 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 00:39:05.804317 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:39:05.804397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:39:05.804477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:39:05.804557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:39:05.804638 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 00:39:05.804722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 00:39:05.804803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 00:39:05.804883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:39:05.804963 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:39:05.805043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:39:05.805123 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:39:05.805203 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:39:05.805306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:39:05.805374 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:39:05.805425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:39:05.805475 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:39:05.805526 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:39:05.805577 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:39:05.805628 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:39:05.805679 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:39:05.805730 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1514 00:39:05.805780 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 00:39:05.805830 Total UI for P1: 0, mck2ui 16
1516 00:39:05.805882 best dqsien dly found for B0: ( 0, 14, 4)
1517 00:39:05.805932 Total UI for P1: 0, mck2ui 16
1518 00:39:05.805983 best dqsien dly found for B1: ( 0, 14, 6)
1519 00:39:05.806033 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1520 00:39:05.806083 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 00:39:05.806134
1522 00:39:05.806185 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 00:39:05.806236 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 00:39:05.806286 [Gating] SW calibration Done
1525 00:39:05.806336 ==
1526 00:39:05.806386 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 00:39:05.806437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 00:39:05.806487 ==
1529 00:39:05.806538 RX Vref Scan: 0
1530 00:39:05.806588
1531 00:39:05.806637 RX Vref 0 -> 0, step: 1
1532 00:39:05.806687
1533 00:39:05.806738 RX Delay -130 -> 252, step: 16
1534 00:39:05.806788 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1535 00:39:05.806839 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1536 00:39:05.806890 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1537 00:39:05.806940 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1538 00:39:05.806991 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1539 00:39:05.807247 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1540 00:39:05.807339 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1541 00:39:05.807392 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1542 00:39:05.807443 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1543 00:39:05.807494 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1544 00:39:05.807545 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1545 00:39:05.807596 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1546 00:39:05.807647 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1547 00:39:05.807697 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1548 00:39:05.807747 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1549 00:39:05.807797 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1550 00:39:05.807848 ==
1551 00:39:05.807897 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 00:39:05.807948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 00:39:05.808021 ==
1554 00:39:05.808113 DQS Delay:
1555 00:39:05.808186 DQS0 = 0, DQS1 = 0
1556 00:39:05.808240 DQM Delay:
1557 00:39:05.808290 DQM0 = 85, DQM1 = 79
1558 00:39:05.808342 DQ Delay:
1559 00:39:05.808393 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1560 00:39:05.808444 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1561 00:39:05.808495 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1562 00:39:05.808547 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 00:39:05.808598
1564 00:39:05.808648
1565 00:39:05.808698 ==
1566 00:39:05.808749 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 00:39:05.808799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 00:39:05.808851 ==
1569 00:39:05.808901
1570 00:39:05.808951
1571 00:39:05.809001 TX Vref Scan disable
1572 00:39:05.809052 == TX Byte 0 ==
1573 00:39:05.809102 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1574 00:39:05.809153 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1575 00:39:05.809203 == TX Byte 1 ==
1576 00:39:05.809253 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1577 00:39:05.809348 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1578 00:39:05.809399 ==
1579 00:39:05.809449 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 00:39:05.809500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 00:39:05.809550 ==
1582 00:39:05.809601 TX Vref=22, minBit 3, minWin=27, winSum=444
1583 00:39:05.809652 TX Vref=24, minBit 4, minWin=27, winSum=447
1584 00:39:05.809703 TX Vref=26, minBit 0, minWin=28, winSum=453
1585 00:39:05.809754 TX Vref=28, minBit 4, minWin=27, winSum=452
1586 00:39:05.809805 TX Vref=30, minBit 0, minWin=28, winSum=458
1587 00:39:05.809855 TX Vref=32, minBit 6, minWin=27, winSum=453
1588 00:39:05.809906 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1589 00:39:05.809957
1590 00:39:05.810007 Final TX Range 1 Vref 30
1591 00:39:05.810057
1592 00:39:05.810107 ==
1593 00:39:05.810157 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 00:39:05.810207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 00:39:05.810258 ==
1596 00:39:05.810309
1597 00:39:05.810358
1598 00:39:05.810408 TX Vref Scan disable
1599 00:39:05.810459 == TX Byte 0 ==
1600 00:39:05.810509 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1601 00:39:05.810560 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1602 00:39:05.810611 == TX Byte 1 ==
1603 00:39:05.810661 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1604 00:39:05.810713 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1605 00:39:05.810763
1606 00:39:05.810813 [DATLAT]
1607 00:39:05.810863 Freq=800, CH1 RK0
1608 00:39:05.810914
1609 00:39:05.811002 DATLAT Default: 0xa
1610 00:39:05.811059 0, 0xFFFF, sum = 0
1611 00:39:05.811123 1, 0xFFFF, sum = 0
1612 00:39:05.811190 2, 0xFFFF, sum = 0
1613 00:39:05.811245 3, 0xFFFF, sum = 0
1614 00:39:05.811297 4, 0xFFFF, sum = 0
1615 00:39:05.811349 5, 0xFFFF, sum = 0
1616 00:39:05.811402 6, 0xFFFF, sum = 0
1617 00:39:05.811453 7, 0xFFFF, sum = 0
1618 00:39:05.811505 8, 0xFFFF, sum = 0
1619 00:39:05.811556 9, 0x0, sum = 1
1620 00:39:05.811608 10, 0x0, sum = 2
1621 00:39:05.811660 11, 0x0, sum = 3
1622 00:39:05.811711 12, 0x0, sum = 4
1623 00:39:05.811762 best_step = 10
1624 00:39:05.811813
1625 00:39:05.811863 ==
1626 00:39:05.811913 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 00:39:05.811963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 00:39:05.812015 ==
1629 00:39:05.812066 RX Vref Scan: 1
1630 00:39:05.812116
1631 00:39:05.812166 Set Vref Range= 32 -> 127
1632 00:39:05.812216
1633 00:39:05.812266 RX Vref 32 -> 127, step: 1
1634 00:39:05.812317
1635 00:39:05.812366 RX Delay -95 -> 252, step: 8
1636 00:39:05.812416
1637 00:39:05.812467 Set Vref, RX VrefLevel [Byte0]: 32
1638 00:39:05.812517 [Byte1]: 32
1639 00:39:05.812568
1640 00:39:05.812618 Set Vref, RX VrefLevel [Byte0]: 33
1641 00:39:05.812668 [Byte1]: 33
1642 00:39:05.812719
1643 00:39:05.812769 Set Vref, RX VrefLevel [Byte0]: 34
1644 00:39:05.812820 [Byte1]: 34
1645 00:39:05.812870
1646 00:39:05.812920 Set Vref, RX VrefLevel [Byte0]: 35
1647 00:39:05.812969 [Byte1]: 35
1648 00:39:05.813020
1649 00:39:05.813071 Set Vref, RX VrefLevel [Byte0]: 36
1650 00:39:05.813122 [Byte1]: 36
1651 00:39:05.813172
1652 00:39:05.813222 Set Vref, RX VrefLevel [Byte0]: 37
1653 00:39:05.813314 [Byte1]: 37
1654 00:39:05.813366
1655 00:39:05.813417 Set Vref, RX VrefLevel [Byte0]: 38
1656 00:39:05.813467 [Byte1]: 38
1657 00:39:05.813518
1658 00:39:05.813568 Set Vref, RX VrefLevel [Byte0]: 39
1659 00:39:05.813618 [Byte1]: 39
1660 00:39:05.813669
1661 00:39:05.813719 Set Vref, RX VrefLevel [Byte0]: 40
1662 00:39:05.813770 [Byte1]: 40
1663 00:39:05.813820
1664 00:39:05.813870 Set Vref, RX VrefLevel [Byte0]: 41
1665 00:39:05.813920 [Byte1]: 41
1666 00:39:05.813970
1667 00:39:05.814020 Set Vref, RX VrefLevel [Byte0]: 42
1668 00:39:05.814070 [Byte1]: 42
1669 00:39:05.814121
1670 00:39:05.814171 Set Vref, RX VrefLevel [Byte0]: 43
1671 00:39:05.814221 [Byte1]: 43
1672 00:39:05.814271
1673 00:39:05.814321 Set Vref, RX VrefLevel [Byte0]: 44
1674 00:39:05.814372 [Byte1]: 44
1675 00:39:05.814422
1676 00:39:05.814479 Set Vref, RX VrefLevel [Byte0]: 45
1677 00:39:05.814535 [Byte1]: 45
1678 00:39:05.814586
1679 00:39:05.814636 Set Vref, RX VrefLevel [Byte0]: 46
1680 00:39:05.814687 [Byte1]: 46
1681 00:39:05.814737
1682 00:39:05.814787 Set Vref, RX VrefLevel [Byte0]: 47
1683 00:39:05.814838 [Byte1]: 47
1684 00:39:05.814888
1685 00:39:05.814938 Set Vref, RX VrefLevel [Byte0]: 48
1686 00:39:05.814988 [Byte1]: 48
1687 00:39:05.815038
1688 00:39:05.815088 Set Vref, RX VrefLevel [Byte0]: 49
1689 00:39:05.815139 [Byte1]: 49
1690 00:39:05.815189
1691 00:39:05.815239 Set Vref, RX VrefLevel [Byte0]: 50
1692 00:39:05.815290 [Byte1]: 50
1693 00:39:05.815341
1694 00:39:05.815391 Set Vref, RX VrefLevel [Byte0]: 51
1695 00:39:05.815441 [Byte1]: 51
1696 00:39:05.815491
1697 00:39:05.815541 Set Vref, RX VrefLevel [Byte0]: 52
1698 00:39:05.815591 [Byte1]: 52
1699 00:39:05.815849
1700 00:39:05.815906 Set Vref, RX VrefLevel [Byte0]: 53
1701 00:39:05.815959 [Byte1]: 53
1702 00:39:05.816009
1703 00:39:05.816059 Set Vref, RX VrefLevel [Byte0]: 54
1704 00:39:05.816110 [Byte1]: 54
1705 00:39:05.816160
1706 00:39:05.816211 Set Vref, RX VrefLevel [Byte0]: 55
1707 00:39:05.816261 [Byte1]: 55
1708 00:39:05.816311
1709 00:39:05.816361 Set Vref, RX VrefLevel [Byte0]: 56
1710 00:39:05.816412 [Byte1]: 56
1711 00:39:05.816461
1712 00:39:05.816511 Set Vref, RX VrefLevel [Byte0]: 57
1713 00:39:05.816562 [Byte1]: 57
1714 00:39:05.816612
1715 00:39:05.816662 Set Vref, RX VrefLevel [Byte0]: 58
1716 00:39:05.816712 [Byte1]: 58
1717 00:39:05.816781
1718 00:39:05.816863 Set Vref, RX VrefLevel [Byte0]: 59
1719 00:39:05.816943 [Byte1]: 59
1720 00:39:05.817022
1721 00:39:05.817102 Set Vref, RX VrefLevel [Byte0]: 60
1722 00:39:05.817182 [Byte1]: 60
1723 00:39:05.817268
1724 00:39:05.817357 Set Vref, RX VrefLevel [Byte0]: 61
1725 00:39:05.817409 [Byte1]: 61
1726 00:39:05.817460
1727 00:39:05.817511 Set Vref, RX VrefLevel [Byte0]: 62
1728 00:39:05.817561 [Byte1]: 62
1729 00:39:05.817611
1730 00:39:05.817662 Set Vref, RX VrefLevel [Byte0]: 63
1731 00:39:05.817712 [Byte1]: 63
1732 00:39:05.817762
1733 00:39:05.817819 Set Vref, RX VrefLevel [Byte0]: 64
1734 00:39:05.817885 [Byte1]: 64
1735 00:39:05.817937
1736 00:39:05.817988 Set Vref, RX VrefLevel [Byte0]: 65
1737 00:39:05.818039 [Byte1]: 65
1738 00:39:05.818089
1739 00:39:05.818140 Set Vref, RX VrefLevel [Byte0]: 66
1740 00:39:05.818191 [Byte1]: 66
1741 00:39:05.818241
1742 00:39:05.818291 Set Vref, RX VrefLevel [Byte0]: 67
1743 00:39:05.818342 [Byte1]: 67
1744 00:39:05.818392
1745 00:39:05.818442 Set Vref, RX VrefLevel [Byte0]: 68
1746 00:39:05.818492 [Byte1]: 68
1747 00:39:05.818542
1748 00:39:05.818593 Set Vref, RX VrefLevel [Byte0]: 69
1749 00:39:05.818643 [Byte1]: 69
1750 00:39:05.818694
1751 00:39:05.818744 Set Vref, RX VrefLevel [Byte0]: 70
1752 00:39:05.818794 [Byte1]: 70
1753 00:39:05.818845
1754 00:39:05.818907 Set Vref, RX VrefLevel [Byte0]: 71
1755 00:39:05.818959 [Byte1]: 71
1756 00:39:05.819010
1757 00:39:05.819060 Set Vref, RX VrefLevel [Byte0]: 72
1758 00:39:05.819110 [Byte1]: 72
1759 00:39:05.819160
1760 00:39:05.819210 Set Vref, RX VrefLevel [Byte0]: 73
1761 00:39:05.819261 [Byte1]: 73
1762 00:39:05.819311
1763 00:39:05.819362 Set Vref, RX VrefLevel [Byte0]: 74
1764 00:39:05.819412 [Byte1]: 74
1765 00:39:05.819462
1766 00:39:05.819513 Set Vref, RX VrefLevel [Byte0]: 75
1767 00:39:05.819563 [Byte1]: 75
1768 00:39:05.819613
1769 00:39:05.819663 Final RX Vref Byte 0 = 60 to rank0
1770 00:39:05.819714 Final RX Vref Byte 1 = 49 to rank0
1771 00:39:05.819765 Final RX Vref Byte 0 = 60 to rank1
1772 00:39:05.819815 Final RX Vref Byte 1 = 49 to rank1==
1773 00:39:05.819866 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 00:39:05.819916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 00:39:05.819968 ==
1776 00:39:05.820019 DQS Delay:
1777 00:39:05.820069 DQS0 = 0, DQS1 = 0
1778 00:39:05.820120 DQM Delay:
1779 00:39:05.820170 DQM0 = 85, DQM1 = 79
1780 00:39:05.820221 DQ Delay:
1781 00:39:05.820271 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1782 00:39:05.820321 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1783 00:39:05.820371 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =72
1784 00:39:05.820422 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1785 00:39:05.820472
1786 00:39:05.820521
1787 00:39:05.820572 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e31, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1788 00:39:05.820624 CH1 RK0: MR19=606, MR18=1E31
1789 00:39:05.820675 CH1_RK0: MR19=0x606, MR18=0x1E31, DQSOSC=397, MR23=63, INC=93, DEC=62
1790 00:39:05.820726
1791 00:39:05.820776 ----->DramcWriteLeveling(PI) begin...
1792 00:39:05.820828 ==
1793 00:39:05.820878 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 00:39:05.820930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 00:39:05.820980 ==
1796 00:39:05.821031 Write leveling (Byte 0): 23 => 23
1797 00:39:05.821082 Write leveling (Byte 1): 28 => 28
1798 00:39:05.821133 DramcWriteLeveling(PI) end<-----
1799 00:39:05.821183
1800 00:39:05.821233 ==
1801 00:39:05.821327 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 00:39:05.821379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 00:39:05.821430 ==
1804 00:39:05.821480 [Gating] SW mode calibration
1805 00:39:05.821531 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 00:39:05.821583 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 00:39:05.821634 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1808 00:39:05.821685 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1809 00:39:05.821736 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1810 00:39:05.821787 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:39:05.821838 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:39:05.821953 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:39:05.822039 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:39:05.822126 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:39:05.822208 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:39:05.822289 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:39:05.822370 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:39:05.822465 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:39:05.822579 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:39:05.822682 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:39:05.822747 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:39:05.822820 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:39:05.822872 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1824 00:39:05.822923 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1825 00:39:05.822973 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:39:05.823040 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:39:05.823105 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:39:05.823159 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:39:05.823209 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:39:05.823467 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:39:05.823526 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:39:05.823577 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1833 00:39:05.823629 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1834 00:39:05.823679 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 00:39:05.823730 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 00:39:05.823780 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 00:39:05.823831 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 00:39:05.823881 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 00:39:05.823932 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1840 00:39:05.823982 0 10 4 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
1841 00:39:05.824033 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1842 00:39:05.824084 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:39:05.824134 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:39:05.824184 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:39:05.824234 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:39:05.824285 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:39:05.824335 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:39:05.824387 0 11 4 | B1->B0 | 2525 3433 | 0 1 | (0 0) (0 0)
1849 00:39:05.824437 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1850 00:39:05.824487 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 00:39:05.824537 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 00:39:05.824587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 00:39:05.824638 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 00:39:05.824687 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 00:39:05.824737 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 00:39:05.824837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1857 00:39:05.824888 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 00:39:05.824938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:39:05.824989 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:39:05.825039 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:39:05.825090 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:39:05.825140 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:39:05.825190 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:39:05.825240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:39:05.825346 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:39:05.825399 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:39:05.825450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:39:05.825500 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:39:05.825551 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:39:05.825601 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:39:05.825651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:39:05.825702 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1873 00:39:05.825752 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1874 00:39:05.825803 Total UI for P1: 0, mck2ui 16
1875 00:39:05.825853 best dqsien dly found for B0: ( 0, 14, 4)
1876 00:39:05.825904 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 00:39:05.825955 Total UI for P1: 0, mck2ui 16
1878 00:39:05.826005 best dqsien dly found for B1: ( 0, 14, 8)
1879 00:39:05.826056 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1880 00:39:05.826106 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1881 00:39:05.826156
1882 00:39:05.826212 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1883 00:39:05.826265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1884 00:39:05.826315 [Gating] SW calibration Done
1885 00:39:05.826365 ==
1886 00:39:05.826416 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 00:39:05.826466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 00:39:05.826517 ==
1889 00:39:05.826567 RX Vref Scan: 0
1890 00:39:05.826618
1891 00:39:05.826667 RX Vref 0 -> 0, step: 1
1892 00:39:05.826717
1893 00:39:05.826774 RX Delay -130 -> 252, step: 16
1894 00:39:05.826857 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1895 00:39:05.826908 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1896 00:39:05.826959 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1897 00:39:05.827009 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1898 00:39:05.827059 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1899 00:39:05.827110 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1900 00:39:05.827160 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1901 00:39:05.827210 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1902 00:39:05.827259 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1903 00:39:05.827309 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1904 00:39:05.827360 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1905 00:39:05.827410 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1906 00:39:05.827460 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1907 00:39:05.827511 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1908 00:39:05.827561 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1909 00:39:05.827611 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1910 00:39:05.827661 ==
1911 00:39:05.827711 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 00:39:05.827761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 00:39:05.827812 ==
1914 00:39:05.827862 DQS Delay:
1915 00:39:05.827911 DQS0 = 0, DQS1 = 0
1916 00:39:05.827962 DQM Delay:
1917 00:39:05.828012 DQM0 = 81, DQM1 = 82
1918 00:39:05.828062 DQ Delay:
1919 00:39:05.828112 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1920 00:39:05.828163 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1921 00:39:05.828214 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1922 00:39:05.984599 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1923 00:39:05.984793
1924 00:39:05.984901
1925 00:39:05.985000 ==
1926 00:39:05.985098 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 00:39:05.985195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 00:39:05.985305 ==
1929 00:39:05.985404
1930 00:39:05.985499
1931 00:39:05.985592 TX Vref Scan disable
1932 00:39:05.985687 == TX Byte 0 ==
1933 00:39:05.985781 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1934 00:39:05.986101 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1935 00:39:05.986208 == TX Byte 1 ==
1936 00:39:05.986307 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1937 00:39:05.986406 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1938 00:39:05.986502 ==
1939 00:39:05.986597 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 00:39:05.986693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 00:39:05.986788 ==
1942 00:39:05.986882 TX Vref=22, minBit 1, minWin=27, winSum=443
1943 00:39:05.986982 TX Vref=24, minBit 4, minWin=26, winSum=446
1944 00:39:05.987087 TX Vref=26, minBit 6, minWin=27, winSum=454
1945 00:39:05.987191 TX Vref=28, minBit 6, minWin=27, winSum=452
1946 00:39:05.987290 TX Vref=30, minBit 1, minWin=28, winSum=457
1947 00:39:05.987387 TX Vref=32, minBit 1, minWin=27, winSum=454
1948 00:39:05.987483 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
1949 00:39:05.987578
1950 00:39:05.987672 Final TX Range 1 Vref 30
1951 00:39:05.987767
1952 00:39:05.987859 ==
1953 00:39:05.987952 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 00:39:05.988046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 00:39:05.988141 ==
1956 00:39:05.988234
1957 00:39:05.988326
1958 00:39:05.988418 TX Vref Scan disable
1959 00:39:05.988511 == TX Byte 0 ==
1960 00:39:05.988604 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1961 00:39:05.988697 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1962 00:39:05.988790 == TX Byte 1 ==
1963 00:39:05.988882 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 00:39:05.988976 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 00:39:05.989069
1966 00:39:05.989160 [DATLAT]
1967 00:39:05.989251 Freq=800, CH1 RK1
1968 00:39:05.989386
1969 00:39:05.989479 DATLAT Default: 0xa
1970 00:39:05.989571 0, 0xFFFF, sum = 0
1971 00:39:05.989667 1, 0xFFFF, sum = 0
1972 00:39:05.989762 2, 0xFFFF, sum = 0
1973 00:39:05.989857 3, 0xFFFF, sum = 0
1974 00:39:05.989953 4, 0xFFFF, sum = 0
1975 00:39:05.990047 5, 0xFFFF, sum = 0
1976 00:39:05.990141 6, 0xFFFF, sum = 0
1977 00:39:05.990235 7, 0xFFFF, sum = 0
1978 00:39:05.990330 8, 0xFFFF, sum = 0
1979 00:39:05.990425 9, 0x0, sum = 1
1980 00:39:05.990518 10, 0x0, sum = 2
1981 00:39:05.990612 11, 0x0, sum = 3
1982 00:39:05.990706 12, 0x0, sum = 4
1983 00:39:05.990799 best_step = 10
1984 00:39:05.990891
1985 00:39:05.990982 ==
1986 00:39:05.991073 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 00:39:05.991166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 00:39:05.991260 ==
1989 00:39:05.991391 RX Vref Scan: 0
1990 00:39:05.991482
1991 00:39:05.991575 RX Vref 0 -> 0, step: 1
1992 00:39:05.991666
1993 00:39:05.991757 RX Delay -95 -> 252, step: 8
1994 00:39:05.991851 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1995 00:39:05.991942 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1996 00:39:05.992035 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1997 00:39:05.992127 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1998 00:39:05.992219 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1999 00:39:05.992311 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2000 00:39:05.992402 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2001 00:39:05.992494 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2002 00:39:05.992586 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2003 00:39:05.992678 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2004 00:39:05.992769 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2005 00:39:05.992861 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2006 00:39:05.992953 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2007 00:39:05.993045 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2008 00:39:05.993138 iDelay=209, Bit 14, Center 88 (-15 ~ 192) 208
2009 00:39:05.993230 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2010 00:39:05.993359 ==
2011 00:39:05.993453 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 00:39:05.993547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 00:39:05.993641 ==
2014 00:39:05.993733 DQS Delay:
2015 00:39:05.993826 DQS0 = 0, DQS1 = 0
2016 00:39:05.993918 DQM Delay:
2017 00:39:05.994010 DQM0 = 85, DQM1 = 81
2018 00:39:05.994103 DQ Delay:
2019 00:39:05.994196 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2020 00:39:05.994289 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2021 00:39:05.994381 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2022 00:39:05.994474 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2023 00:39:05.994567
2024 00:39:05.994658
2025 00:39:05.994750 [DQSOSCAuto] RK1, (LSB)MR18= 0x2844, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
2026 00:39:05.994844 CH1 RK1: MR19=606, MR18=2844
2027 00:39:05.994939 CH1_RK1: MR19=0x606, MR18=0x2844, DQSOSC=392, MR23=63, INC=96, DEC=64
2028 00:39:05.995032 [RxdqsGatingPostProcess] freq 800
2029 00:39:05.995125 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2030 00:39:05.995217 Pre-setting of DQS Precalculation
2031 00:39:05.995335 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2032 00:39:05.995518 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2033 00:39:05.995613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2034 00:39:05.995705
2035 00:39:05.995797
2036 00:39:05.995888 [Calibration Summary] 1600 Mbps
2037 00:39:05.995989 CH 0, Rank 0
2038 00:39:05.996084 SW Impedance : PASS
2039 00:39:05.996163 DUTY Scan : NO K
2040 00:39:05.996238 ZQ Calibration : PASS
2041 00:39:05.996310 Jitter Meter : NO K
2042 00:39:05.996382 CBT Training : PASS
2043 00:39:05.996453 Write leveling : PASS
2044 00:39:05.996524 RX DQS gating : PASS
2045 00:39:05.996614 RX DQ/DQS(RDDQC) : PASS
2046 00:39:05.996705 TX DQ/DQS : PASS
2047 00:39:05.996795 RX DATLAT : PASS
2048 00:39:05.996885 RX DQ/DQS(Engine): PASS
2049 00:39:05.996974 TX OE : NO K
2050 00:39:05.997064 All Pass.
2051 00:39:05.997153
2052 00:39:05.997242 CH 0, Rank 1
2053 00:39:05.997372 SW Impedance : PASS
2054 00:39:05.997462 DUTY Scan : NO K
2055 00:39:05.997551 ZQ Calibration : PASS
2056 00:39:05.997641 Jitter Meter : NO K
2057 00:39:05.997731 CBT Training : PASS
2058 00:39:05.997820 Write leveling : PASS
2059 00:39:05.997909 RX DQS gating : PASS
2060 00:39:05.997998 RX DQ/DQS(RDDQC) : PASS
2061 00:39:05.998086 TX DQ/DQS : PASS
2062 00:39:05.998175 RX DATLAT : PASS
2063 00:39:05.998264 RX DQ/DQS(Engine): PASS
2064 00:39:05.998353 TX OE : NO K
2065 00:39:05.998442 All Pass.
2066 00:39:05.998530
2067 00:39:05.998619 CH 1, Rank 0
2068 00:39:05.998708 SW Impedance : PASS
2069 00:39:05.998797 DUTY Scan : NO K
2070 00:39:05.998886 ZQ Calibration : PASS
2071 00:39:05.998975 Jitter Meter : NO K
2072 00:39:05.999064 CBT Training : PASS
2073 00:39:05.999153 Write leveling : PASS
2074 00:39:05.999241 RX DQS gating : PASS
2075 00:39:05.999330 RX DQ/DQS(RDDQC) : PASS
2076 00:39:05.999418 TX DQ/DQS : PASS
2077 00:39:05.999507 RX DATLAT : PASS
2078 00:39:05.999595 RX DQ/DQS(Engine): PASS
2079 00:39:05.999683 TX OE : NO K
2080 00:39:05.999772 All Pass.
2081 00:39:05.999860
2082 00:39:06.000156 CH 1, Rank 1
2083 00:39:06.000261 SW Impedance : PASS
2084 00:39:06.000388 DUTY Scan : NO K
2085 00:39:06.000478 ZQ Calibration : PASS
2086 00:39:06.000549 Jitter Meter : NO K
2087 00:39:06.000621 CBT Training : PASS
2088 00:39:06.000711 Write leveling : PASS
2089 00:39:06.000801 RX DQS gating : PASS
2090 00:39:06.000891 RX DQ/DQS(RDDQC) : PASS
2091 00:39:06.000980 TX DQ/DQS : PASS
2092 00:39:06.001069 RX DATLAT : PASS
2093 00:39:06.001175 RX DQ/DQS(Engine): PASS
2094 00:39:06.001275 TX OE : NO K
2095 00:39:06.001379 All Pass.
2096 00:39:06.001468
2097 00:39:06.001557 DramC Write-DBI off
2098 00:39:06.001646 PER_BANK_REFRESH: Hybrid Mode
2099 00:39:06.001736 TX_TRACKING: ON
2100 00:39:06.001825 [GetDramInforAfterCalByMRR] Vendor 6.
2101 00:39:06.001914 [GetDramInforAfterCalByMRR] Revision 606.
2102 00:39:06.002003 [GetDramInforAfterCalByMRR] Revision 2 0.
2103 00:39:06.002092 MR0 0x3b3b
2104 00:39:06.002182 MR8 0x5151
2105 00:39:06.002270 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 00:39:06.002360
2107 00:39:06.002448 MR0 0x3b3b
2108 00:39:06.002536 MR8 0x5151
2109 00:39:06.002625 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 00:39:06.002713
2111 00:39:06.002802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2112 00:39:06.002892 [FAST_K] Save calibration result to emmc
2113 00:39:06.002981 [FAST_K] Save calibration result to emmc
2114 00:39:06.003070 dram_init: config_dvfs: 1
2115 00:39:06.003159 dramc_set_vcore_voltage set vcore to 662500
2116 00:39:06.003309 Read voltage for 1200, 2
2117 00:39:06.003398 Vio18 = 0
2118 00:39:06.003486 Vcore = 662500
2119 00:39:06.003575 Vdram = 0
2120 00:39:06.003663 Vddq = 0
2121 00:39:06.003751 Vmddr = 0
2122 00:39:06.003839 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2123 00:39:06.003928 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2124 00:39:06.004017 MEM_TYPE=3, freq_sel=15
2125 00:39:06.004112 sv_algorithm_assistance_LP4_1600
2126 00:39:06.004208 ============ PULL DRAM RESETB DOWN ============
2127 00:39:06.004297 ========== PULL DRAM RESETB DOWN end =========
2128 00:39:06.004381 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 00:39:06.004464 ===================================
2130 00:39:06.004545 LPDDR4 DRAM CONFIGURATION
2131 00:39:06.004626 ===================================
2132 00:39:06.004707 EX_ROW_EN[0] = 0x0
2133 00:39:06.004787 EX_ROW_EN[1] = 0x0
2134 00:39:06.004898 LP4Y_EN = 0x0
2135 00:39:06.004983 WORK_FSP = 0x0
2136 00:39:06.005064 WL = 0x4
2137 00:39:06.005155 RL = 0x4
2138 00:39:06.005236 BL = 0x2
2139 00:39:06.005354 RPST = 0x0
2140 00:39:06.005435 RD_PRE = 0x0
2141 00:39:06.005515 WR_PRE = 0x1
2142 00:39:06.005594 WR_PST = 0x0
2143 00:39:06.005674 DBI_WR = 0x0
2144 00:39:06.005754 DBI_RD = 0x0
2145 00:39:06.005834 OTF = 0x1
2146 00:39:06.005915 ===================================
2147 00:39:06.005995 ===================================
2148 00:39:06.006076 ANA top config
2149 00:39:06.006156 ===================================
2150 00:39:06.006236 DLL_ASYNC_EN = 0
2151 00:39:06.006316 ALL_SLAVE_EN = 0
2152 00:39:06.006396 NEW_RANK_MODE = 1
2153 00:39:06.006477 DLL_IDLE_MODE = 1
2154 00:39:06.006557 LP45_APHY_COMB_EN = 1
2155 00:39:06.006637 TX_ODT_DIS = 1
2156 00:39:06.006718 NEW_8X_MODE = 1
2157 00:39:06.006798 ===================================
2158 00:39:06.006879 ===================================
2159 00:39:06.006959 data_rate = 2400
2160 00:39:06.007039 CKR = 1
2161 00:39:06.007119 DQ_P2S_RATIO = 8
2162 00:39:06.007213 ===================================
2163 00:39:06.007294 CA_P2S_RATIO = 8
2164 00:39:06.007374 DQ_CA_OPEN = 0
2165 00:39:06.007453 DQ_SEMI_OPEN = 0
2166 00:39:06.007534 CA_SEMI_OPEN = 0
2167 00:39:06.007613 CA_FULL_RATE = 0
2168 00:39:06.007693 DQ_CKDIV4_EN = 0
2169 00:39:06.007774 CA_CKDIV4_EN = 0
2170 00:39:06.007853 CA_PREDIV_EN = 0
2171 00:39:06.007933 PH8_DLY = 17
2172 00:39:06.008045 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2173 00:39:06.008125 DQ_AAMCK_DIV = 4
2174 00:39:06.008205 CA_AAMCK_DIV = 4
2175 00:39:06.008285 CA_ADMCK_DIV = 4
2176 00:39:06.008365 DQ_TRACK_CA_EN = 0
2177 00:39:06.008449 CA_PICK = 1200
2178 00:39:06.008544 CA_MCKIO = 1200
2179 00:39:06.008617 MCKIO_SEMI = 0
2180 00:39:06.008671 PLL_FREQ = 2366
2181 00:39:06.008724 DQ_UI_PI_RATIO = 32
2182 00:39:06.008775 CA_UI_PI_RATIO = 0
2183 00:39:06.008826 ===================================
2184 00:39:06.008879 ===================================
2185 00:39:06.008930 memory_type:LPDDR4
2186 00:39:06.008982 GP_NUM : 10
2187 00:39:06.009032 SRAM_EN : 1
2188 00:39:06.009084 MD32_EN : 0
2189 00:39:06.009135 ===================================
2190 00:39:06.009186 [ANA_INIT] >>>>>>>>>>>>>>
2191 00:39:06.009236 <<<<<< [CONFIGURE PHASE]: ANA_TX
2192 00:39:06.009327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2193 00:39:06.009380 ===================================
2194 00:39:06.009432 data_rate = 2400,PCW = 0X5b00
2195 00:39:06.009483 ===================================
2196 00:39:06.009534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2197 00:39:06.009586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 00:39:06.009637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 00:39:06.009693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2200 00:39:06.009766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2201 00:39:06.009838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2202 00:39:06.009909 [ANA_INIT] flow start
2203 00:39:06.009979 [ANA_INIT] PLL >>>>>>>>
2204 00:39:06.010050 [ANA_INIT] PLL <<<<<<<<
2205 00:39:06.010119 [ANA_INIT] MIDPI >>>>>>>>
2206 00:39:06.010207 [ANA_INIT] MIDPI <<<<<<<<
2207 00:39:06.010295 [ANA_INIT] DLL >>>>>>>>
2208 00:39:06.010383 [ANA_INIT] DLL <<<<<<<<
2209 00:39:06.010471 [ANA_INIT] flow end
2210 00:39:06.010560 ============ LP4 DIFF to SE enter ============
2211 00:39:06.010649 ============ LP4 DIFF to SE exit ============
2212 00:39:06.010738 [ANA_INIT] <<<<<<<<<<<<<
2213 00:39:06.010826 [Flow] Enable top DCM control >>>>>
2214 00:39:06.010914 [Flow] Enable top DCM control <<<<<
2215 00:39:06.011002 Enable DLL master slave shuffle
2216 00:39:06.011314 ==============================================================
2217 00:39:06.011406 Gating Mode config
2218 00:39:06.011497 ==============================================================
2219 00:39:06.011589 Config description:
2220 00:39:06.011680 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2221 00:39:06.011803 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2222 00:39:06.011893 SELPH_MODE 0: By rank 1: By Phase
2223 00:39:06.011983 ==============================================================
2224 00:39:06.012073 GAT_TRACK_EN = 1
2225 00:39:06.012161 RX_GATING_MODE = 2
2226 00:39:06.012250 RX_GATING_TRACK_MODE = 2
2227 00:39:06.012338 SELPH_MODE = 1
2228 00:39:06.012427 PICG_EARLY_EN = 1
2229 00:39:06.012515 VALID_LAT_VALUE = 1
2230 00:39:06.012603 ==============================================================
2231 00:39:06.012692 Enter into Gating configuration >>>>
2232 00:39:06.012780 Exit from Gating configuration <<<<
2233 00:39:06.012868 Enter into DVFS_PRE_config >>>>>
2234 00:39:06.012956 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2235 00:39:06.013046 Exit from DVFS_PRE_config <<<<<
2236 00:39:06.013135 Enter into PICG configuration >>>>
2237 00:39:06.013223 Exit from PICG configuration <<<<
2238 00:39:06.013354 [RX_INPUT] configuration >>>>>
2239 00:39:06.013443 [RX_INPUT] configuration <<<<<
2240 00:39:06.013531 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2241 00:39:06.013620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2242 00:39:06.013709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 00:39:06.013799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 00:39:06.013887 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 00:39:06.013976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 00:39:06.014065 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2247 00:39:06.014153 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2248 00:39:06.014242 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2249 00:39:06.014331 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2250 00:39:06.014419 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2251 00:39:06.014507 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2252 00:39:06.014596 ===================================
2253 00:39:06.014684 LPDDR4 DRAM CONFIGURATION
2254 00:39:06.014774 ===================================
2255 00:39:06.014864 EX_ROW_EN[0] = 0x0
2256 00:39:06.014953 EX_ROW_EN[1] = 0x0
2257 00:39:06.015042 LP4Y_EN = 0x0
2258 00:39:06.015134 WORK_FSP = 0x0
2259 00:39:06.015256 WL = 0x4
2260 00:39:06.015353 RL = 0x4
2261 00:39:06.015435 BL = 0x2
2262 00:39:06.015516 RPST = 0x0
2263 00:39:06.015597 RD_PRE = 0x0
2264 00:39:06.015677 WR_PRE = 0x1
2265 00:39:06.015757 WR_PST = 0x0
2266 00:39:06.015837 DBI_WR = 0x0
2267 00:39:06.015917 DBI_RD = 0x0
2268 00:39:06.015996 OTF = 0x1
2269 00:39:06.016077 ===================================
2270 00:39:06.016158 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2271 00:39:06.016239 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2272 00:39:06.016319 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 00:39:06.016400 ===================================
2274 00:39:06.016480 LPDDR4 DRAM CONFIGURATION
2275 00:39:06.016560 ===================================
2276 00:39:06.016641 EX_ROW_EN[0] = 0x10
2277 00:39:06.016720 EX_ROW_EN[1] = 0x0
2278 00:39:06.016800 LP4Y_EN = 0x0
2279 00:39:06.016880 WORK_FSP = 0x0
2280 00:39:06.016959 WL = 0x4
2281 00:39:06.017038 RL = 0x4
2282 00:39:06.017118 BL = 0x2
2283 00:39:06.017198 RPST = 0x0
2284 00:39:06.017306 RD_PRE = 0x0
2285 00:39:06.017400 WR_PRE = 0x1
2286 00:39:06.017480 WR_PST = 0x0
2287 00:39:06.017559 DBI_WR = 0x0
2288 00:39:06.017639 DBI_RD = 0x0
2289 00:39:06.017718 OTF = 0x1
2290 00:39:06.017799 ===================================
2291 00:39:06.017880 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2292 00:39:06.017960 ==
2293 00:39:06.018040 Dram Type= 6, Freq= 0, CH_0, rank 0
2294 00:39:06.018125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2295 00:39:06.018210 ==
2296 00:39:06.018291 [Duty_Offset_Calibration]
2297 00:39:06.018370 B0:2 B1:0 CA:4
2298 00:39:06.018449
2299 00:39:06.018529 [DutyScan_Calibration_Flow] k_type=0
2300 00:39:06.018608
2301 00:39:06.018687 ==CLK 0==
2302 00:39:06.018766 Final CLK duty delay cell = 0
2303 00:39:06.018847 [0] MAX Duty = 5156%(X100), DQS PI = 14
2304 00:39:06.018927 [0] MIN Duty = 4969%(X100), DQS PI = 8
2305 00:39:06.019006 [0] AVG Duty = 5062%(X100)
2306 00:39:06.019085
2307 00:39:06.019156 CH0 CLK Duty spec in!! Max-Min= 187%
2308 00:39:06.019209 [DutyScan_Calibration_Flow] ====Done====
2309 00:39:06.019261
2310 00:39:06.019312 [DutyScan_Calibration_Flow] k_type=1
2311 00:39:06.019363
2312 00:39:06.019414 ==DQS 0 ==
2313 00:39:06.019464 Final DQS duty delay cell = 0
2314 00:39:06.019515 [0] MAX Duty = 5156%(X100), DQS PI = 18
2315 00:39:06.019566 [0] MIN Duty = 5093%(X100), DQS PI = 0
2316 00:39:06.019617 [0] AVG Duty = 5124%(X100)
2317 00:39:06.019667
2318 00:39:06.019717 ==DQS 1 ==
2319 00:39:06.019768 Final DQS duty delay cell = 0
2320 00:39:06.019818 [0] MAX Duty = 5093%(X100), DQS PI = 50
2321 00:39:06.019869 [0] MIN Duty = 4969%(X100), DQS PI = 14
2322 00:39:06.019919 [0] AVG Duty = 5031%(X100)
2323 00:39:06.019968
2324 00:39:06.020019 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2325 00:39:06.020069
2326 00:39:06.020118 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2327 00:39:06.020169 [DutyScan_Calibration_Flow] ====Done====
2328 00:39:06.020219
2329 00:39:06.020269 [DutyScan_Calibration_Flow] k_type=3
2330 00:39:06.020319
2331 00:39:06.020406 ==DQM 0 ==
2332 00:39:06.020492 Final DQM duty delay cell = 0
2333 00:39:06.020543 [0] MAX Duty = 5125%(X100), DQS PI = 20
2334 00:39:06.020593 [0] MIN Duty = 4844%(X100), DQS PI = 50
2335 00:39:06.020643 [0] AVG Duty = 4984%(X100)
2336 00:39:06.020699
2337 00:39:06.020781 ==DQM 1 ==
2338 00:39:06.020862 Final DQM duty delay cell = 0
2339 00:39:06.021151 [0] MAX Duty = 4969%(X100), DQS PI = 4
2340 00:39:06.021254 [0] MIN Duty = 4875%(X100), DQS PI = 18
2341 00:39:06.021387 [0] AVG Duty = 4922%(X100)
2342 00:39:06.021475
2343 00:39:06.021531 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2344 00:39:06.021583
2345 00:39:06.021635 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2346 00:39:06.021686 [DutyScan_Calibration_Flow] ====Done====
2347 00:39:06.021737
2348 00:39:06.021787 [DutyScan_Calibration_Flow] k_type=2
2349 00:39:06.021839
2350 00:39:06.021889 ==DQ 0 ==
2351 00:39:06.021940 Final DQ duty delay cell = -4
2352 00:39:06.021991 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2353 00:39:06.022042 [-4] MIN Duty = 4844%(X100), DQS PI = 50
2354 00:39:06.022092 [-4] AVG Duty = 4922%(X100)
2355 00:39:06.022143
2356 00:39:06.022194 ==DQ 1 ==
2357 00:39:06.022244 Final DQ duty delay cell = 0
2358 00:39:06.022296 [0] MAX Duty = 5125%(X100), DQS PI = 4
2359 00:39:06.022347 [0] MIN Duty = 4938%(X100), DQS PI = 14
2360 00:39:06.022397 [0] AVG Duty = 5031%(X100)
2361 00:39:06.022448
2362 00:39:06.022498 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2363 00:39:06.022549
2364 00:39:06.022599 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2365 00:39:06.022665 [DutyScan_Calibration_Flow] ====Done====
2366 00:39:06.022717 ==
2367 00:39:06.022769 Dram Type= 6, Freq= 0, CH_1, rank 0
2368 00:39:06.022845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 00:39:06.022940 ==
2370 00:39:06.022997 [Duty_Offset_Calibration]
2371 00:39:06.023065 B0:0 B1:-1 CA:3
2372 00:39:06.023117
2373 00:39:06.023182 [DutyScan_Calibration_Flow] k_type=0
2374 00:39:06.023233
2375 00:39:06.023283 ==CLK 0==
2376 00:39:06.023334 Final CLK duty delay cell = -4
2377 00:39:06.023386 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2378 00:39:06.023437 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2379 00:39:06.023488 [-4] AVG Duty = 4938%(X100)
2380 00:39:06.023556
2381 00:39:06.023638 CH1 CLK Duty spec in!! Max-Min= 124%
2382 00:39:06.023691 [DutyScan_Calibration_Flow] ====Done====
2383 00:39:06.023773
2384 00:39:06.023869 [DutyScan_Calibration_Flow] k_type=1
2385 00:39:06.023919
2386 00:39:06.023970 ==DQS 0 ==
2387 00:39:06.024036 Final DQS duty delay cell = 0
2388 00:39:06.024118 [0] MAX Duty = 5156%(X100), DQS PI = 18
2389 00:39:06.024183 [0] MIN Duty = 4907%(X100), DQS PI = 38
2390 00:39:06.024263 [0] AVG Duty = 5031%(X100)
2391 00:39:06.024313
2392 00:39:06.024364 ==DQS 1 ==
2393 00:39:06.024446 Final DQS duty delay cell = 0
2394 00:39:06.024497 [0] MAX Duty = 5156%(X100), DQS PI = 8
2395 00:39:06.024564 [0] MIN Duty = 5000%(X100), DQS PI = 26
2396 00:39:06.024630 [0] AVG Duty = 5078%(X100)
2397 00:39:06.024680
2398 00:39:06.024731 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2399 00:39:06.024812
2400 00:39:06.024862 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2401 00:39:06.024929 [DutyScan_Calibration_Flow] ====Done====
2402 00:39:06.024994
2403 00:39:06.025044 [DutyScan_Calibration_Flow] k_type=3
2404 00:39:06.025094
2405 00:39:06.025159 ==DQM 0 ==
2406 00:39:06.025211 Final DQM duty delay cell = 0
2407 00:39:06.025272 [0] MAX Duty = 5031%(X100), DQS PI = 28
2408 00:39:06.025339 [0] MIN Duty = 4782%(X100), DQS PI = 38
2409 00:39:06.025390 [0] AVG Duty = 4906%(X100)
2410 00:39:06.025440
2411 00:39:06.025490 ==DQM 1 ==
2412 00:39:06.025541 Final DQM duty delay cell = 0
2413 00:39:06.025593 [0] MAX Duty = 5000%(X100), DQS PI = 34
2414 00:39:06.025644 [0] MIN Duty = 4844%(X100), DQS PI = 0
2415 00:39:06.025694 [0] AVG Duty = 4922%(X100)
2416 00:39:06.025745
2417 00:39:06.025796 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2418 00:39:06.025846
2419 00:39:06.025897 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2420 00:39:06.025947 [DutyScan_Calibration_Flow] ====Done====
2421 00:39:06.025998
2422 00:39:06.026048 [DutyScan_Calibration_Flow] k_type=2
2423 00:39:06.026099
2424 00:39:06.026149 ==DQ 0 ==
2425 00:39:06.026200 Final DQ duty delay cell = -4
2426 00:39:06.026251 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2427 00:39:06.026301 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2428 00:39:06.026352 [-4] AVG Duty = 4937%(X100)
2429 00:39:06.026402
2430 00:39:06.026452 ==DQ 1 ==
2431 00:39:06.026502 Final DQ duty delay cell = 0
2432 00:39:06.026554 [0] MAX Duty = 5031%(X100), DQS PI = 34
2433 00:39:06.026604 [0] MIN Duty = 4844%(X100), DQS PI = 0
2434 00:39:06.026654 [0] AVG Duty = 4937%(X100)
2435 00:39:06.026705
2436 00:39:06.026755 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2437 00:39:06.026806
2438 00:39:06.026855 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2439 00:39:06.026906 [DutyScan_Calibration_Flow] ====Done====
2440 00:39:06.026957 nWR fixed to 30
2441 00:39:06.027024 [ModeRegInit_LP4] CH0 RK0
2442 00:39:06.027120 [ModeRegInit_LP4] CH0 RK1
2443 00:39:06.027171 [ModeRegInit_LP4] CH1 RK0
2444 00:39:06.027222 [ModeRegInit_LP4] CH1 RK1
2445 00:39:06.027272 match AC timing 7
2446 00:39:06.027322 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2447 00:39:06.027373 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2448 00:39:06.027424 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2449 00:39:06.027475 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2450 00:39:06.027526 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2451 00:39:06.027576 ==
2452 00:39:06.027626 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 00:39:06.027678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 00:39:06.027729 ==
2455 00:39:06.027779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2456 00:39:06.027830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2457 00:39:06.027882 [CA 0] Center 39 (9~70) winsize 62
2458 00:39:06.027933 [CA 1] Center 38 (8~69) winsize 62
2459 00:39:06.027983 [CA 2] Center 35 (5~66) winsize 62
2460 00:39:06.028033 [CA 3] Center 35 (5~66) winsize 62
2461 00:39:06.028084 [CA 4] Center 33 (3~64) winsize 62
2462 00:39:06.028134 [CA 5] Center 33 (3~63) winsize 61
2463 00:39:06.028185
2464 00:39:06.028236 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2465 00:39:06.028317
2466 00:39:06.028367 [CATrainingPosCal] consider 1 rank data
2467 00:39:06.028417 u2DelayCellTimex100 = 270/100 ps
2468 00:39:06.028469 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2469 00:39:06.028519 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2470 00:39:06.028570 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2471 00:39:06.028621 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2472 00:39:06.028671 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2473 00:39:06.028722 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2474 00:39:06.028772
2475 00:39:06.028822 CA PerBit enable=1, Macro0, CA PI delay=33
2476 00:39:06.028873
2477 00:39:06.028923 [CBTSetCACLKResult] CA Dly = 33
2478 00:39:06.028973 CS Dly: 7 (0~38)
2479 00:39:06.029024 ==
2480 00:39:06.029074 Dram Type= 6, Freq= 0, CH_0, rank 1
2481 00:39:06.029125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 00:39:06.029176 ==
2483 00:39:06.029226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 00:39:06.029316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2485 00:39:06.029369 [CA 0] Center 39 (9~70) winsize 62
2486 00:39:06.029623 [CA 1] Center 39 (9~70) winsize 62
2487 00:39:06.029685 [CA 2] Center 35 (5~66) winsize 62
2488 00:39:06.029738 [CA 3] Center 35 (5~66) winsize 62
2489 00:39:06.029789 [CA 4] Center 34 (3~65) winsize 63
2490 00:39:06.029840 [CA 5] Center 33 (3~63) winsize 61
2491 00:39:06.029891
2492 00:39:06.029942 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2493 00:39:06.029994
2494 00:39:06.030044 [CATrainingPosCal] consider 2 rank data
2495 00:39:06.030095 u2DelayCellTimex100 = 270/100 ps
2496 00:39:06.030145 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2497 00:39:06.030196 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2498 00:39:06.030247 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 00:39:06.030297 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 00:39:06.030348 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2501 00:39:06.030399 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2502 00:39:06.030450
2503 00:39:06.030501 CA PerBit enable=1, Macro0, CA PI delay=33
2504 00:39:06.030551
2505 00:39:06.030602 [CBTSetCACLKResult] CA Dly = 33
2506 00:39:06.030652 CS Dly: 8 (0~40)
2507 00:39:06.030702
2508 00:39:06.030752 ----->DramcWriteLeveling(PI) begin...
2509 00:39:06.030834 ==
2510 00:39:06.030884 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 00:39:06.030935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 00:39:06.030986 ==
2513 00:39:06.031036 Write leveling (Byte 0): 31 => 31
2514 00:39:06.031087 Write leveling (Byte 1): 26 => 26
2515 00:39:06.031138 DramcWriteLeveling(PI) end<-----
2516 00:39:06.031189
2517 00:39:06.031238 ==
2518 00:39:06.031289 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 00:39:06.031339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 00:39:06.031390 ==
2521 00:39:06.031440 [Gating] SW mode calibration
2522 00:39:06.031491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2523 00:39:06.031543 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2524 00:39:06.031594 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2525 00:39:06.031645 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2526 00:39:06.031696 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 00:39:06.031747 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 00:39:06.031798 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 00:39:06.031848 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2530 00:39:06.031899 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2531 00:39:06.031949 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
2532 00:39:06.032000 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2533 00:39:06.032050 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 00:39:06.032100 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 00:39:06.032151 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 00:39:06.032201 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 00:39:06.032252 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 00:39:06.032302 1 0 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2539 00:39:06.032353 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2540 00:39:06.032404 1 1 0 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
2541 00:39:06.032454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 00:39:06.032505 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 00:39:06.032556 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 00:39:06.032607 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 00:39:06.032657 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 00:39:06.032707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 00:39:06.032757 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 00:39:06.032808 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2549 00:39:06.032859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:39:06.032909 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:39:06.032960 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:39:06.033011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:39:06.033061 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:39:06.033112 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:39:06.033162 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:39:06.033213 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:39:06.033293 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:39:06.033361 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:39:06.033412 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:39:06.033463 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:39:06.033513 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:39:06.033564 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2563 00:39:06.033614 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 00:39:06.033665 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 00:39:06.033715 Total UI for P1: 0, mck2ui 16
2566 00:39:06.033767 best dqsien dly found for B0: ( 1, 3, 26)
2567 00:39:06.033817 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 00:39:06.033868 Total UI for P1: 0, mck2ui 16
2569 00:39:06.033919 best dqsien dly found for B1: ( 1, 4, 0)
2570 00:39:06.033969 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2571 00:39:06.034020 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2572 00:39:06.034071
2573 00:39:06.034121 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2574 00:39:06.034172 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2575 00:39:06.034223 [Gating] SW calibration Done
2576 00:39:06.034274 ==
2577 00:39:06.034324 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 00:39:06.034375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 00:39:06.034426 ==
2580 00:39:06.034477 RX Vref Scan: 0
2581 00:39:06.034527
2582 00:39:06.034577 RX Vref 0 -> 0, step: 1
2583 00:39:06.034627
2584 00:39:06.034678 RX Delay -40 -> 252, step: 8
2585 00:39:06.034772 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2586 00:39:06.034835 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2587 00:39:06.034900 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2588 00:39:06.034963 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2589 00:39:06.035025 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2590 00:39:06.035292 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2591 00:39:06.035392 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2592 00:39:06.035507 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2593 00:39:06.035611 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2594 00:39:06.035738 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2595 00:39:06.035846 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2596 00:39:06.035958 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2597 00:39:06.036081 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2598 00:39:06.036186 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2599 00:39:06.036284 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2600 00:39:06.036348 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2601 00:39:06.036409 ==
2602 00:39:06.036464 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 00:39:06.036516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 00:39:06.036568 ==
2605 00:39:06.036626 DQS Delay:
2606 00:39:06.036681 DQS0 = 0, DQS1 = 0
2607 00:39:06.036732 DQM Delay:
2608 00:39:06.036783 DQM0 = 119, DQM1 = 106
2609 00:39:06.036845 DQ Delay:
2610 00:39:06.036905 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2611 00:39:06.036964 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2612 00:39:06.037028 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2613 00:39:06.037091 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =111
2614 00:39:06.037151
2615 00:39:06.037209
2616 00:39:06.037307 ==
2617 00:39:06.037385 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 00:39:06.037452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 00:39:06.037511 ==
2620 00:39:06.037577
2621 00:39:06.037635
2622 00:39:06.037689 TX Vref Scan disable
2623 00:39:06.037739 == TX Byte 0 ==
2624 00:39:06.037790 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2625 00:39:06.037841 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2626 00:39:06.037892 == TX Byte 1 ==
2627 00:39:06.037942 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2628 00:39:06.037993 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2629 00:39:06.038044 ==
2630 00:39:06.038094 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 00:39:06.038145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 00:39:06.038197 ==
2633 00:39:06.038247 TX Vref=22, minBit 1, minWin=24, winSum=409
2634 00:39:06.038299 TX Vref=24, minBit 3, minWin=25, winSum=414
2635 00:39:06.038350 TX Vref=26, minBit 10, minWin=25, winSum=417
2636 00:39:06.038400 TX Vref=28, minBit 1, minWin=25, winSum=425
2637 00:39:06.038450 TX Vref=30, minBit 4, minWin=26, winSum=427
2638 00:39:06.038502 TX Vref=32, minBit 0, minWin=26, winSum=427
2639 00:39:06.038553 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 30
2640 00:39:06.038604
2641 00:39:06.038654 Final TX Range 1 Vref 30
2642 00:39:06.038705
2643 00:39:06.038756 ==
2644 00:39:06.038806 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 00:39:06.038857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 00:39:06.038908 ==
2647 00:39:06.038958
2648 00:39:06.039009
2649 00:39:06.039059 TX Vref Scan disable
2650 00:39:06.039109 == TX Byte 0 ==
2651 00:39:06.039160 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2652 00:39:06.039211 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2653 00:39:06.039262 == TX Byte 1 ==
2654 00:39:06.039313 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2655 00:39:06.039364 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2656 00:39:06.039414
2657 00:39:06.039465 [DATLAT]
2658 00:39:06.039515 Freq=1200, CH0 RK0
2659 00:39:06.039565
2660 00:39:06.039615 DATLAT Default: 0xd
2661 00:39:06.039666 0, 0xFFFF, sum = 0
2662 00:39:06.039718 1, 0xFFFF, sum = 0
2663 00:39:06.039769 2, 0xFFFF, sum = 0
2664 00:39:06.039821 3, 0xFFFF, sum = 0
2665 00:39:06.039872 4, 0xFFFF, sum = 0
2666 00:39:06.039924 5, 0xFFFF, sum = 0
2667 00:39:06.039974 6, 0xFFFF, sum = 0
2668 00:39:06.040026 7, 0xFFFF, sum = 0
2669 00:39:06.040077 8, 0xFFFF, sum = 0
2670 00:39:06.040128 9, 0xFFFF, sum = 0
2671 00:39:06.040180 10, 0xFFFF, sum = 0
2672 00:39:06.040231 11, 0xFFFF, sum = 0
2673 00:39:06.040283 12, 0x0, sum = 1
2674 00:39:06.040335 13, 0x0, sum = 2
2675 00:39:06.040386 14, 0x0, sum = 3
2676 00:39:06.040437 15, 0x0, sum = 4
2677 00:39:06.040488 best_step = 13
2678 00:39:06.040538
2679 00:39:06.040588 ==
2680 00:39:06.040644 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 00:39:06.040696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 00:39:06.040748 ==
2683 00:39:06.040798 RX Vref Scan: 1
2684 00:39:06.040848
2685 00:39:06.040898 Set Vref Range= 32 -> 127
2686 00:39:06.040948
2687 00:39:06.040998 RX Vref 32 -> 127, step: 1
2688 00:39:06.041049
2689 00:39:06.041099 RX Delay -21 -> 252, step: 4
2690 00:39:06.041149
2691 00:39:06.041200 Set Vref, RX VrefLevel [Byte0]: 32
2692 00:39:06.041250 [Byte1]: 32
2693 00:39:06.041344
2694 00:39:06.041394 Set Vref, RX VrefLevel [Byte0]: 33
2695 00:39:06.041445 [Byte1]: 33
2696 00:39:06.041495
2697 00:39:06.041545 Set Vref, RX VrefLevel [Byte0]: 34
2698 00:39:06.041595 [Byte1]: 34
2699 00:39:06.041646
2700 00:39:06.041697 Set Vref, RX VrefLevel [Byte0]: 35
2701 00:39:06.041747 [Byte1]: 35
2702 00:39:06.041797
2703 00:39:06.041847 Set Vref, RX VrefLevel [Byte0]: 36
2704 00:39:06.041897 [Byte1]: 36
2705 00:39:06.041947
2706 00:39:06.041997 Set Vref, RX VrefLevel [Byte0]: 37
2707 00:39:06.042047 [Byte1]: 37
2708 00:39:06.042098
2709 00:39:06.042148 Set Vref, RX VrefLevel [Byte0]: 38
2710 00:39:06.042198 [Byte1]: 38
2711 00:39:06.042248
2712 00:39:06.042298 Set Vref, RX VrefLevel [Byte0]: 39
2713 00:39:06.042348 [Byte1]: 39
2714 00:39:06.042399
2715 00:39:06.042449 Set Vref, RX VrefLevel [Byte0]: 40
2716 00:39:06.042499 [Byte1]: 40
2717 00:39:06.042550
2718 00:39:06.042600 Set Vref, RX VrefLevel [Byte0]: 41
2719 00:39:06.042650 [Byte1]: 41
2720 00:39:06.042700
2721 00:39:06.042750 Set Vref, RX VrefLevel [Byte0]: 42
2722 00:39:06.042800 [Byte1]: 42
2723 00:39:06.042851
2724 00:39:06.042901 Set Vref, RX VrefLevel [Byte0]: 43
2725 00:39:06.042951 [Byte1]: 43
2726 00:39:06.043002
2727 00:39:06.043052 Set Vref, RX VrefLevel [Byte0]: 44
2728 00:39:06.043102 [Byte1]: 44
2729 00:39:06.043152
2730 00:39:06.043202 Set Vref, RX VrefLevel [Byte0]: 45
2731 00:39:06.043252 [Byte1]: 45
2732 00:39:06.043303
2733 00:39:06.043353 Set Vref, RX VrefLevel [Byte0]: 46
2734 00:39:06.043404 [Byte1]: 46
2735 00:39:06.043454
2736 00:39:06.043504 Set Vref, RX VrefLevel [Byte0]: 47
2737 00:39:06.043554 [Byte1]: 47
2738 00:39:06.043604
2739 00:39:06.043654 Set Vref, RX VrefLevel [Byte0]: 48
2740 00:39:06.043704 [Byte1]: 48
2741 00:39:06.043755
2742 00:39:06.043805 Set Vref, RX VrefLevel [Byte0]: 49
2743 00:39:06.043855 [Byte1]: 49
2744 00:39:06.043906
2745 00:39:06.043956 Set Vref, RX VrefLevel [Byte0]: 50
2746 00:39:06.044006 [Byte1]: 50
2747 00:39:06.044056
2748 00:39:06.044111 Set Vref, RX VrefLevel [Byte0]: 51
2749 00:39:06.044193 [Byte1]: 51
2750 00:39:06.044261
2751 00:39:06.044515 Set Vref, RX VrefLevel [Byte0]: 52
2752 00:39:06.044596 [Byte1]: 52
2753 00:39:06.044699
2754 00:39:06.044801 Set Vref, RX VrefLevel [Byte0]: 53
2755 00:39:06.044903 [Byte1]: 53
2756 00:39:06.044997
2757 00:39:06.045085 Set Vref, RX VrefLevel [Byte0]: 54
2758 00:39:06.045151 [Byte1]: 54
2759 00:39:06.045204
2760 00:39:06.045262 Set Vref, RX VrefLevel [Byte0]: 55
2761 00:39:06.045376 [Byte1]: 55
2762 00:39:06.045456
2763 00:39:06.045536 Set Vref, RX VrefLevel [Byte0]: 56
2764 00:39:06.045616 [Byte1]: 56
2765 00:39:06.045696
2766 00:39:06.045775 Set Vref, RX VrefLevel [Byte0]: 57
2767 00:39:06.045855 [Byte1]: 57
2768 00:39:06.045935
2769 00:39:06.046014 Set Vref, RX VrefLevel [Byte0]: 58
2770 00:39:06.046106 [Byte1]: 58
2771 00:39:06.046207
2772 00:39:06.046290 Set Vref, RX VrefLevel [Byte0]: 59
2773 00:39:06.046370 [Byte1]: 59
2774 00:39:06.046449
2775 00:39:06.046529 Set Vref, RX VrefLevel [Byte0]: 60
2776 00:39:06.046609 [Byte1]: 60
2777 00:39:06.046689
2778 00:39:06.046769 Set Vref, RX VrefLevel [Byte0]: 61
2779 00:39:06.046849 [Byte1]: 61
2780 00:39:06.046928
2781 00:39:06.047007 Set Vref, RX VrefLevel [Byte0]: 62
2782 00:39:06.047094 [Byte1]: 62
2783 00:39:06.047208
2784 00:39:06.047291 Set Vref, RX VrefLevel [Byte0]: 63
2785 00:39:06.047371 [Byte1]: 63
2786 00:39:06.047450
2787 00:39:06.047530 Set Vref, RX VrefLevel [Byte0]: 64
2788 00:39:06.047610 [Byte1]: 64
2789 00:39:06.047689
2790 00:39:06.047769 Set Vref, RX VrefLevel [Byte0]: 65
2791 00:39:06.047849 [Byte1]: 65
2792 00:39:06.047928
2793 00:39:06.048007 Set Vref, RX VrefLevel [Byte0]: 66
2794 00:39:06.048088 [Byte1]: 66
2795 00:39:06.048166
2796 00:39:06.048246 Set Vref, RX VrefLevel [Byte0]: 67
2797 00:39:06.048326 [Byte1]: 67
2798 00:39:06.048405
2799 00:39:06.048485 Set Vref, RX VrefLevel [Byte0]: 68
2800 00:39:06.048564 [Byte1]: 68
2801 00:39:06.048643
2802 00:39:06.048723 Set Vref, RX VrefLevel [Byte0]: 69
2803 00:39:06.048803 [Byte1]: 69
2804 00:39:06.048882
2805 00:39:06.048961 Final RX Vref Byte 0 = 56 to rank0
2806 00:39:06.049042 Final RX Vref Byte 1 = 49 to rank0
2807 00:39:06.049122 Final RX Vref Byte 0 = 56 to rank1
2808 00:39:06.049203 Final RX Vref Byte 1 = 49 to rank1==
2809 00:39:06.049308 Dram Type= 6, Freq= 0, CH_0, rank 0
2810 00:39:06.049376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2811 00:39:06.049428 ==
2812 00:39:06.049479 DQS Delay:
2813 00:39:06.049530 DQS0 = 0, DQS1 = 0
2814 00:39:06.049581 DQM Delay:
2815 00:39:06.049631 DQM0 = 119, DQM1 = 105
2816 00:39:06.049682 DQ Delay:
2817 00:39:06.049733 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =114
2818 00:39:06.049784 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2819 00:39:06.049835 DQ8 =94, DQ9 =90, DQ10 =104, DQ11 =100
2820 00:39:06.049886 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2821 00:39:06.049936
2822 00:39:06.049986
2823 00:39:06.050037 [DQSOSCAuto] RK0, (LSB)MR18= 0x904, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2824 00:39:06.050089 CH0 RK0: MR19=404, MR18=904
2825 00:39:06.050141 CH0_RK0: MR19=0x404, MR18=0x904, DQSOSC=406, MR23=63, INC=39, DEC=26
2826 00:39:06.050193
2827 00:39:06.050244 ----->DramcWriteLeveling(PI) begin...
2828 00:39:06.050296 ==
2829 00:39:06.050347 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 00:39:06.050398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 00:39:06.050449 ==
2832 00:39:06.050499 Write leveling (Byte 0): 32 => 32
2833 00:39:06.050550 Write leveling (Byte 1): 27 => 27
2834 00:39:06.050601 DramcWriteLeveling(PI) end<-----
2835 00:39:06.050651
2836 00:39:06.050702 ==
2837 00:39:06.050753 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 00:39:06.050804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 00:39:06.050855 ==
2840 00:39:06.050906 [Gating] SW mode calibration
2841 00:39:06.050957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2842 00:39:06.051008 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2843 00:39:06.051060 0 15 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
2844 00:39:06.051111 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2845 00:39:06.051162 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 00:39:06.051212 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 00:39:06.051263 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 00:39:06.051314 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 00:39:06.051365 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2850 00:39:06.051415 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2851 00:39:06.051465 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2852 00:39:06.051516 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 00:39:06.051567 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 00:39:06.051625 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 00:39:06.051677 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 00:39:06.051728 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 00:39:06.051779 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
2858 00:39:06.051830 1 0 28 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
2859 00:39:06.051880 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2860 00:39:06.051931 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 00:39:06.051983 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 00:39:06.052034 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 00:39:06.052084 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 00:39:06.052135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 00:39:06.052186 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2866 00:39:06.052237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2867 00:39:06.052287 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2868 00:39:06.052338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 00:39:06.052389 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 00:39:06.052439 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 00:39:06.052490 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 00:39:06.052540 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 00:39:06.052795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 00:39:06.052875 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 00:39:06.052979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 00:39:06.053083 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 00:39:06.053186 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 00:39:06.053296 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 00:39:06.053386 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:39:06.053471 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2881 00:39:06.053525 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2882 00:39:06.053576 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2883 00:39:06.053628 Total UI for P1: 0, mck2ui 16
2884 00:39:06.053680 best dqsien dly found for B0: ( 1, 3, 22)
2885 00:39:06.053731 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2886 00:39:06.053782 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 00:39:06.053833 Total UI for P1: 0, mck2ui 16
2888 00:39:06.053884 best dqsien dly found for B1: ( 1, 3, 30)
2889 00:39:06.053935 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2890 00:39:06.053986 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2891 00:39:06.054037
2892 00:39:06.054087 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2893 00:39:06.054138 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2894 00:39:06.054188 [Gating] SW calibration Done
2895 00:39:06.054239 ==
2896 00:39:06.054297 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 00:39:06.054349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 00:39:06.054400 ==
2899 00:39:06.054451 RX Vref Scan: 0
2900 00:39:06.054501
2901 00:39:06.054551 RX Vref 0 -> 0, step: 1
2902 00:39:06.054602
2903 00:39:06.054652 RX Delay -40 -> 252, step: 8
2904 00:39:06.054702 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2905 00:39:06.054754 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2906 00:39:06.054804 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2907 00:39:06.054855 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2908 00:39:06.054905 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2909 00:39:06.054956 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2910 00:39:06.055006 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2911 00:39:06.055056 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2912 00:39:06.055106 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2913 00:39:06.055157 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2914 00:39:06.055207 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2915 00:39:06.055258 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2916 00:39:06.055309 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2917 00:39:06.055359 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2918 00:39:06.055410 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2919 00:39:06.055460 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2920 00:39:06.055511 ==
2921 00:39:06.055561 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 00:39:06.055612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 00:39:06.055663 ==
2924 00:39:06.055714 DQS Delay:
2925 00:39:06.055764 DQS0 = 0, DQS1 = 0
2926 00:39:06.055814 DQM Delay:
2927 00:39:06.055865 DQM0 = 118, DQM1 = 106
2928 00:39:06.055915 DQ Delay:
2929 00:39:06.055966 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2930 00:39:06.056017 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2931 00:39:06.056068 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2932 00:39:06.056118 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2933 00:39:06.056168
2934 00:39:06.056218
2935 00:39:06.056269 ==
2936 00:39:06.171194 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 00:39:06.171335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 00:39:06.171401 ==
2939 00:39:06.171460
2940 00:39:06.171516
2941 00:39:06.171570 TX Vref Scan disable
2942 00:39:06.171624 == TX Byte 0 ==
2943 00:39:06.171678 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2944 00:39:06.171731 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2945 00:39:06.171783 == TX Byte 1 ==
2946 00:39:06.171836 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2947 00:39:06.171889 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2948 00:39:06.171941 ==
2949 00:39:06.171993 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 00:39:06.172044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 00:39:06.172096 ==
2952 00:39:06.172147 TX Vref=22, minBit 3, minWin=25, winSum=419
2953 00:39:06.172200 TX Vref=24, minBit 3, minWin=25, winSum=420
2954 00:39:06.172251 TX Vref=26, minBit 2, minWin=26, winSum=428
2955 00:39:06.172302 TX Vref=28, minBit 0, minWin=26, winSum=424
2956 00:39:06.172354 TX Vref=30, minBit 2, minWin=26, winSum=428
2957 00:39:06.172405 TX Vref=32, minBit 4, minWin=26, winSum=430
2958 00:39:06.172456 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 32
2959 00:39:06.172537
2960 00:39:06.172587 Final TX Range 1 Vref 32
2961 00:39:06.172638
2962 00:39:06.172688 ==
2963 00:39:06.172739 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 00:39:06.172790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 00:39:06.172840 ==
2966 00:39:06.172890
2967 00:39:06.172940
2968 00:39:06.172990 TX Vref Scan disable
2969 00:39:06.173041 == TX Byte 0 ==
2970 00:39:06.173091 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2971 00:39:06.173157 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2972 00:39:06.173209 == TX Byte 1 ==
2973 00:39:06.173268 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2974 00:39:06.173336 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2975 00:39:06.173387
2976 00:39:06.173437 [DATLAT]
2977 00:39:06.173488 Freq=1200, CH0 RK1
2978 00:39:06.173540
2979 00:39:06.173590 DATLAT Default: 0xd
2980 00:39:06.173641 0, 0xFFFF, sum = 0
2981 00:39:06.173694 1, 0xFFFF, sum = 0
2982 00:39:06.173745 2, 0xFFFF, sum = 0
2983 00:39:06.173797 3, 0xFFFF, sum = 0
2984 00:39:06.173849 4, 0xFFFF, sum = 0
2985 00:39:06.173900 5, 0xFFFF, sum = 0
2986 00:39:06.173952 6, 0xFFFF, sum = 0
2987 00:39:06.174004 7, 0xFFFF, sum = 0
2988 00:39:06.174055 8, 0xFFFF, sum = 0
2989 00:39:06.174107 9, 0xFFFF, sum = 0
2990 00:39:06.174158 10, 0xFFFF, sum = 0
2991 00:39:06.174210 11, 0xFFFF, sum = 0
2992 00:39:06.174261 12, 0x0, sum = 1
2993 00:39:06.174313 13, 0x0, sum = 2
2994 00:39:06.174365 14, 0x0, sum = 3
2995 00:39:06.174416 15, 0x0, sum = 4
2996 00:39:06.174468 best_step = 13
2997 00:39:06.174518
2998 00:39:06.174568 ==
2999 00:39:06.174618 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 00:39:06.174669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 00:39:06.174720 ==
3002 00:39:06.174770 RX Vref Scan: 0
3003 00:39:06.174821
3004 00:39:06.174871 RX Vref 0 -> 0, step: 1
3005 00:39:06.174921
3006 00:39:06.174971 RX Delay -21 -> 252, step: 4
3007 00:39:06.175022 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3008 00:39:06.175073 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3009 00:39:06.175124 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3010 00:39:06.175382 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3011 00:39:06.175445 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
3012 00:39:06.175498 iDelay=195, Bit 5, Center 110 (47 ~ 174) 128
3013 00:39:06.175550 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3014 00:39:06.175601 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3015 00:39:06.175651 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3016 00:39:06.175702 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3017 00:39:06.175753 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3018 00:39:06.175861 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3019 00:39:06.175963 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3020 00:39:06.176050 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3021 00:39:06.176130 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3022 00:39:06.176211 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3023 00:39:06.176290 ==
3024 00:39:06.176388 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 00:39:06.176519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 00:39:06.176600 ==
3027 00:39:06.176680 DQS Delay:
3028 00:39:06.176760 DQS0 = 0, DQS1 = 0
3029 00:39:06.176839 DQM Delay:
3030 00:39:06.176919 DQM0 = 118, DQM1 = 106
3031 00:39:06.176998 DQ Delay:
3032 00:39:06.177078 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3033 00:39:06.177158 DQ4 =122, DQ5 =110, DQ6 =128, DQ7 =124
3034 00:39:06.177239 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3035 00:39:06.177336 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =112
3036 00:39:06.177388
3037 00:39:06.177440
3038 00:39:06.177491 [DQSOSCAuto] RK1, (LSB)MR18= 0x300, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
3039 00:39:06.177543 CH0 RK1: MR19=404, MR18=300
3040 00:39:06.177595 CH0_RK1: MR19=0x404, MR18=0x300, DQSOSC=408, MR23=63, INC=39, DEC=26
3041 00:39:06.177647 [RxdqsGatingPostProcess] freq 1200
3042 00:39:06.177698 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3043 00:39:06.177749 best DQS0 dly(2T, 0.5T) = (0, 11)
3044 00:39:06.177800 best DQS1 dly(2T, 0.5T) = (0, 12)
3045 00:39:06.177851 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3046 00:39:06.177902 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3047 00:39:06.177953 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 00:39:06.178004 best DQS1 dly(2T, 0.5T) = (0, 11)
3049 00:39:06.178054 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 00:39:06.178105 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3051 00:39:06.178156 Pre-setting of DQS Precalculation
3052 00:39:06.178207 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3053 00:39:06.178258 ==
3054 00:39:06.178309 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 00:39:06.178361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 00:39:06.178412 ==
3057 00:39:06.178463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3058 00:39:06.178515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3059 00:39:06.178567 [CA 0] Center 38 (8~68) winsize 61
3060 00:39:06.178618 [CA 1] Center 37 (7~68) winsize 62
3061 00:39:06.178669 [CA 2] Center 35 (5~65) winsize 61
3062 00:39:06.178719 [CA 3] Center 34 (4~64) winsize 61
3063 00:39:06.178770 [CA 4] Center 34 (4~64) winsize 61
3064 00:39:06.178821 [CA 5] Center 33 (3~64) winsize 62
3065 00:39:06.178872
3066 00:39:06.178923 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3067 00:39:06.178974
3068 00:39:06.179025 [CATrainingPosCal] consider 1 rank data
3069 00:39:06.179076 u2DelayCellTimex100 = 270/100 ps
3070 00:39:06.179127 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3071 00:39:06.179178 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3072 00:39:06.179230 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3073 00:39:06.179280 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3074 00:39:06.179331 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3075 00:39:06.179383 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3076 00:39:06.179434
3077 00:39:06.179484 CA PerBit enable=1, Macro0, CA PI delay=33
3078 00:39:06.179535
3079 00:39:06.179586 [CBTSetCACLKResult] CA Dly = 33
3080 00:39:06.179638 CS Dly: 5 (0~36)
3081 00:39:06.179688 ==
3082 00:39:06.179739 Dram Type= 6, Freq= 0, CH_1, rank 1
3083 00:39:06.179790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 00:39:06.179859 ==
3085 00:39:06.179930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3086 00:39:06.179982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3087 00:39:06.180033 [CA 0] Center 37 (7~68) winsize 62
3088 00:39:06.180085 [CA 1] Center 37 (7~68) winsize 62
3089 00:39:06.180152 [CA 2] Center 35 (5~65) winsize 61
3090 00:39:06.180241 [CA 3] Center 33 (3~64) winsize 62
3091 00:39:06.180337 [CA 4] Center 34 (4~64) winsize 61
3092 00:39:06.180418 [CA 5] Center 33 (3~63) winsize 61
3093 00:39:06.180497
3094 00:39:06.180578 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3095 00:39:06.180658
3096 00:39:06.180738 [CATrainingPosCal] consider 2 rank data
3097 00:39:06.180819 u2DelayCellTimex100 = 270/100 ps
3098 00:39:06.180899 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3099 00:39:06.180980 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3100 00:39:06.181060 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3101 00:39:06.181141 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 00:39:06.181238 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3103 00:39:06.181321 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3104 00:39:06.181374
3105 00:39:06.181426 CA PerBit enable=1, Macro0, CA PI delay=33
3106 00:39:06.181478
3107 00:39:06.181528 [CBTSetCACLKResult] CA Dly = 33
3108 00:39:06.181580 CS Dly: 6 (0~39)
3109 00:39:06.181631
3110 00:39:06.181681 ----->DramcWriteLeveling(PI) begin...
3111 00:39:06.181734 ==
3112 00:39:06.181786 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 00:39:06.181837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 00:39:06.181889 ==
3115 00:39:06.181939 Write leveling (Byte 0): 25 => 25
3116 00:39:06.181990 Write leveling (Byte 1): 27 => 27
3117 00:39:06.182041 DramcWriteLeveling(PI) end<-----
3118 00:39:06.182093
3119 00:39:06.182143 ==
3120 00:39:06.182194 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 00:39:06.182250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 00:39:06.182303 ==
3123 00:39:06.182354 [Gating] SW mode calibration
3124 00:39:06.182406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3125 00:39:06.182458 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3126 00:39:06.182510 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3127 00:39:06.182562 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 00:39:06.182614 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 00:39:06.182868 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 00:39:06.182953 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 00:39:06.183039 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 00:39:06.183120 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
3133 00:39:06.183202 0 15 28 | B1->B0 | 2c2c 2626 | 1 0 | (1 1) (0 0)
3134 00:39:06.183283 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 00:39:06.183431 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 00:39:06.183552 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 00:39:06.183644 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 00:39:06.183734 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 00:39:06.183824 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 00:39:06.183914 1 0 24 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
3141 00:39:06.184004 1 0 28 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
3142 00:39:06.184093 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 00:39:06.184183 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 00:39:06.184272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 00:39:06.184361 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 00:39:06.184451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 00:39:06.184540 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 00:39:06.184629 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3149 00:39:06.184718 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3150 00:39:06.184807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 00:39:06.184896 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 00:39:06.184986 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 00:39:06.185074 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 00:39:06.185164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 00:39:06.185253 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 00:39:06.185384 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 00:39:06.185473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 00:39:06.185563 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 00:39:06.185652 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 00:39:06.185742 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 00:39:06.185831 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:39:06.185920 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:39:06.186009 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:39:06.186097 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3165 00:39:06.186186 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3166 00:39:06.186274 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 00:39:06.186362 Total UI for P1: 0, mck2ui 16
3168 00:39:06.186452 best dqsien dly found for B0: ( 1, 3, 26)
3169 00:39:06.186541 Total UI for P1: 0, mck2ui 16
3170 00:39:06.186630 best dqsien dly found for B1: ( 1, 3, 28)
3171 00:39:06.186719 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3172 00:39:06.186808 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3173 00:39:06.186897
3174 00:39:06.186986 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3175 00:39:06.187075 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3176 00:39:06.187164 [Gating] SW calibration Done
3177 00:39:06.187252 ==
3178 00:39:06.187342 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 00:39:06.187431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 00:39:06.187521 ==
3181 00:39:06.187610 RX Vref Scan: 0
3182 00:39:06.187700
3183 00:39:06.187789 RX Vref 0 -> 0, step: 1
3184 00:39:06.187878
3185 00:39:06.187966 RX Delay -40 -> 252, step: 8
3186 00:39:06.188056 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3187 00:39:06.188145 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3188 00:39:06.188234 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3189 00:39:06.188323 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3190 00:39:06.188411 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3191 00:39:06.188500 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3192 00:39:06.188589 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3193 00:39:06.188678 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3194 00:39:06.188767 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3195 00:39:06.188855 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3196 00:39:06.188944 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3197 00:39:06.189033 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3198 00:39:06.189122 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3199 00:39:06.189230 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3200 00:39:06.189344 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3201 00:39:06.189481 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3202 00:39:06.189553 ==
3203 00:39:06.189625 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 00:39:06.189697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 00:39:06.189768 ==
3206 00:39:06.189858 DQS Delay:
3207 00:39:06.189947 DQS0 = 0, DQS1 = 0
3208 00:39:06.190038 DQM Delay:
3209 00:39:06.190127 DQM0 = 114, DQM1 = 112
3210 00:39:06.190216 DQ Delay:
3211 00:39:06.190305 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3212 00:39:06.190394 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3213 00:39:06.190483 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3214 00:39:06.190572 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3215 00:39:06.190661
3216 00:39:06.190750
3217 00:39:06.190839 ==
3218 00:39:06.190928 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 00:39:06.191017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 00:39:06.191107 ==
3221 00:39:06.191196
3222 00:39:06.191285
3223 00:39:06.191375 TX Vref Scan disable
3224 00:39:06.191491 == TX Byte 0 ==
3225 00:39:06.191573 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3226 00:39:06.191655 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3227 00:39:06.191735 == TX Byte 1 ==
3228 00:39:06.191816 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3229 00:39:06.191897 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3230 00:39:06.191977 ==
3231 00:39:06.192058 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 00:39:06.192139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 00:39:06.192220 ==
3234 00:39:06.192301 TX Vref=22, minBit 9, minWin=24, winSum=413
3235 00:39:06.192382 TX Vref=24, minBit 8, minWin=25, winSum=418
3236 00:39:06.192464 TX Vref=26, minBit 11, minWin=24, winSum=418
3237 00:39:06.192778 TX Vref=28, minBit 9, minWin=25, winSum=423
3238 00:39:06.192865 TX Vref=30, minBit 9, minWin=25, winSum=426
3239 00:39:06.192947 TX Vref=32, minBit 2, minWin=26, winSum=427
3240 00:39:06.193029 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 32
3241 00:39:06.193109
3242 00:39:06.193190 Final TX Range 1 Vref 32
3243 00:39:06.193296
3244 00:39:06.193398 ==
3245 00:39:06.193487 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 00:39:06.193577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 00:39:06.193666 ==
3248 00:39:06.193755
3249 00:39:06.193844
3250 00:39:06.193932 TX Vref Scan disable
3251 00:39:06.194022 == TX Byte 0 ==
3252 00:39:06.194111 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3253 00:39:06.194200 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3254 00:39:06.194289 == TX Byte 1 ==
3255 00:39:06.194378 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3256 00:39:06.194467 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3257 00:39:06.194556
3258 00:39:06.194644 [DATLAT]
3259 00:39:06.194733 Freq=1200, CH1 RK0
3260 00:39:06.194821
3261 00:39:06.194910 DATLAT Default: 0xd
3262 00:39:06.194998 0, 0xFFFF, sum = 0
3263 00:39:06.195090 1, 0xFFFF, sum = 0
3264 00:39:06.195180 2, 0xFFFF, sum = 0
3265 00:39:06.195271 3, 0xFFFF, sum = 0
3266 00:39:06.195362 4, 0xFFFF, sum = 0
3267 00:39:06.195471 5, 0xFFFF, sum = 0
3268 00:39:06.195576 6, 0xFFFF, sum = 0
3269 00:39:06.195666 7, 0xFFFF, sum = 0
3270 00:39:06.195756 8, 0xFFFF, sum = 0
3271 00:39:06.195845 9, 0xFFFF, sum = 0
3272 00:39:06.195935 10, 0xFFFF, sum = 0
3273 00:39:06.196025 11, 0xFFFF, sum = 0
3274 00:39:06.196116 12, 0x0, sum = 1
3275 00:39:06.196206 13, 0x0, sum = 2
3276 00:39:06.196296 14, 0x0, sum = 3
3277 00:39:06.196387 15, 0x0, sum = 4
3278 00:39:06.196477 best_step = 13
3279 00:39:06.196565
3280 00:39:06.196653 ==
3281 00:39:06.196742 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 00:39:06.196831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 00:39:06.196920 ==
3284 00:39:06.197009 RX Vref Scan: 1
3285 00:39:06.197097
3286 00:39:06.197186 Set Vref Range= 32 -> 127
3287 00:39:06.197296
3288 00:39:06.197399 RX Vref 32 -> 127, step: 1
3289 00:39:06.197489
3290 00:39:06.197578 RX Delay -13 -> 252, step: 4
3291 00:39:06.197667
3292 00:39:06.197755 Set Vref, RX VrefLevel [Byte0]: 32
3293 00:39:06.197844 [Byte1]: 32
3294 00:39:06.197932
3295 00:39:06.198019 Set Vref, RX VrefLevel [Byte0]: 33
3296 00:39:06.198106 [Byte1]: 33
3297 00:39:06.198195
3298 00:39:06.198284 Set Vref, RX VrefLevel [Byte0]: 34
3299 00:39:06.198369 [Byte1]: 34
3300 00:39:06.198450
3301 00:39:06.198530 Set Vref, RX VrefLevel [Byte0]: 35
3302 00:39:06.198610 [Byte1]: 35
3303 00:39:06.198689
3304 00:39:06.198768 Set Vref, RX VrefLevel [Byte0]: 36
3305 00:39:06.198846 [Byte1]: 36
3306 00:39:06.198924
3307 00:39:06.199002 Set Vref, RX VrefLevel [Byte0]: 37
3308 00:39:06.199080 [Byte1]: 37
3309 00:39:06.199157
3310 00:39:06.199234 Set Vref, RX VrefLevel [Byte0]: 38
3311 00:39:06.199311 [Byte1]: 38
3312 00:39:06.199389
3313 00:39:06.199504 Set Vref, RX VrefLevel [Byte0]: 39
3314 00:39:06.199582 [Byte1]: 39
3315 00:39:06.199659
3316 00:39:06.199736 Set Vref, RX VrefLevel [Byte0]: 40
3317 00:39:06.199818 [Byte1]: 40
3318 00:39:06.199976
3319 00:39:06.200065 Set Vref, RX VrefLevel [Byte0]: 41
3320 00:39:06.200142 [Byte1]: 41
3321 00:39:06.200220
3322 00:39:06.200297 Set Vref, RX VrefLevel [Byte0]: 42
3323 00:39:06.200373 [Byte1]: 42
3324 00:39:06.200450
3325 00:39:06.200527 Set Vref, RX VrefLevel [Byte0]: 43
3326 00:39:06.200604 [Byte1]: 43
3327 00:39:06.200681
3328 00:39:06.200758 Set Vref, RX VrefLevel [Byte0]: 44
3329 00:39:06.200835 [Byte1]: 44
3330 00:39:06.200912
3331 00:39:06.200988 Set Vref, RX VrefLevel [Byte0]: 45
3332 00:39:06.201065 [Byte1]: 45
3333 00:39:06.201142
3334 00:39:06.201219 Set Vref, RX VrefLevel [Byte0]: 46
3335 00:39:06.201340 [Byte1]: 46
3336 00:39:06.201420
3337 00:39:06.201498 Set Vref, RX VrefLevel [Byte0]: 47
3338 00:39:06.201577 [Byte1]: 47
3339 00:39:06.201655
3340 00:39:06.201731 Set Vref, RX VrefLevel [Byte0]: 48
3341 00:39:06.201809 [Byte1]: 48
3342 00:39:06.201886
3343 00:39:06.201963 Set Vref, RX VrefLevel [Byte0]: 49
3344 00:39:06.202040 [Byte1]: 49
3345 00:39:06.202117
3346 00:39:06.202193 Set Vref, RX VrefLevel [Byte0]: 50
3347 00:39:06.202270 [Byte1]: 50
3348 00:39:06.202348
3349 00:39:06.202424 Set Vref, RX VrefLevel [Byte0]: 51
3350 00:39:06.202501 [Byte1]: 51
3351 00:39:06.202578
3352 00:39:06.202654 Set Vref, RX VrefLevel [Byte0]: 52
3353 00:39:06.202731 [Byte1]: 52
3354 00:39:06.202808
3355 00:39:06.202884 Set Vref, RX VrefLevel [Byte0]: 53
3356 00:39:06.202962 [Byte1]: 53
3357 00:39:06.203038
3358 00:39:06.203115 Set Vref, RX VrefLevel [Byte0]: 54
3359 00:39:06.203193 [Byte1]: 54
3360 00:39:06.203269
3361 00:39:06.203349 Set Vref, RX VrefLevel [Byte0]: 55
3362 00:39:06.203426 [Byte1]: 55
3363 00:39:06.203503
3364 00:39:06.203579 Set Vref, RX VrefLevel [Byte0]: 56
3365 00:39:06.203656 [Byte1]: 56
3366 00:39:06.203732
3367 00:39:06.203809 Set Vref, RX VrefLevel [Byte0]: 57
3368 00:39:06.203886 [Byte1]: 57
3369 00:39:06.203963
3370 00:39:06.204037 Set Vref, RX VrefLevel [Byte0]: 58
3371 00:39:06.204111 [Byte1]: 58
3372 00:39:06.204186
3373 00:39:06.204259 Set Vref, RX VrefLevel [Byte0]: 59
3374 00:39:06.204343 [Byte1]: 59
3375 00:39:06.204424
3376 00:39:06.204507 Set Vref, RX VrefLevel [Byte0]: 60
3377 00:39:06.204589 [Byte1]: 60
3378 00:39:06.204672
3379 00:39:06.204752 Set Vref, RX VrefLevel [Byte0]: 61
3380 00:39:06.204835 [Byte1]: 61
3381 00:39:06.204915
3382 00:39:06.204996 Set Vref, RX VrefLevel [Byte0]: 62
3383 00:39:06.205076 [Byte1]: 62
3384 00:39:06.205153
3385 00:39:06.205235 Set Vref, RX VrefLevel [Byte0]: 63
3386 00:39:06.205363 [Byte1]: 63
3387 00:39:06.205455
3388 00:39:06.205547 Set Vref, RX VrefLevel [Byte0]: 64
3389 00:39:06.205641 [Byte1]: 64
3390 00:39:06.205731
3391 00:39:06.205823 Set Vref, RX VrefLevel [Byte0]: 65
3392 00:39:06.205929 [Byte1]: 65
3393 00:39:06.206021
3394 00:39:06.206108 Final RX Vref Byte 0 = 53 to rank0
3395 00:39:06.206193 Final RX Vref Byte 1 = 49 to rank0
3396 00:39:06.206276 Final RX Vref Byte 0 = 53 to rank1
3397 00:39:06.206358 Final RX Vref Byte 1 = 49 to rank1==
3398 00:39:06.206440 Dram Type= 6, Freq= 0, CH_1, rank 0
3399 00:39:06.206521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3400 00:39:06.206602 ==
3401 00:39:06.206682 DQS Delay:
3402 00:39:06.206762 DQS0 = 0, DQS1 = 0
3403 00:39:06.206842 DQM Delay:
3404 00:39:06.206922 DQM0 = 115, DQM1 = 111
3405 00:39:06.207001 DQ Delay:
3406 00:39:06.207285 DQ0 =122, DQ1 =110, DQ2 =106, DQ3 =114
3407 00:39:06.207371 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3408 00:39:06.207530 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3409 00:39:06.207675 DQ12 =120, DQ13 =120, DQ14 =116, DQ15 =120
3410 00:39:06.207755
3411 00:39:06.207833
3412 00:39:06.207915 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3413 00:39:06.207996 CH1 RK0: MR19=304, MR18=F400
3414 00:39:06.208077 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3415 00:39:06.208157
3416 00:39:06.208236 ----->DramcWriteLeveling(PI) begin...
3417 00:39:06.208317 ==
3418 00:39:06.208397 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 00:39:06.208479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 00:39:06.208559 ==
3421 00:39:06.208638 Write leveling (Byte 0): 25 => 25
3422 00:39:06.208719 Write leveling (Byte 1): 27 => 27
3423 00:39:06.208798 DramcWriteLeveling(PI) end<-----
3424 00:39:06.208882
3425 00:39:06.208976 ==
3426 00:39:06.209069 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 00:39:06.209152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 00:39:06.209233 ==
3429 00:39:06.209354 [Gating] SW mode calibration
3430 00:39:06.209470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3431 00:39:06.209552 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3432 00:39:06.209633 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3433 00:39:06.209715 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 00:39:06.209796 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 00:39:06.209876 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 00:39:06.209957 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 00:39:06.210037 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3438 00:39:06.210118 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
3439 00:39:06.210198 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
3440 00:39:06.210279 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 00:39:06.210359 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 00:39:06.210440 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 00:39:06.210520 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 00:39:06.210601 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 00:39:06.210681 1 0 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
3446 00:39:06.210761 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3447 00:39:06.210842 1 0 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3448 00:39:06.210922 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 00:39:06.211002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 00:39:06.211082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 00:39:06.211162 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 00:39:06.211242 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 00:39:06.211322 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3454 00:39:06.211411 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3455 00:39:06.211465 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3456 00:39:06.211518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 00:39:06.211569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 00:39:06.211620 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 00:39:06.211671 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 00:39:06.211722 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 00:39:06.211773 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 00:39:06.211824 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 00:39:06.211874 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:39:06.211925 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:39:06.211975 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:39:06.212026 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:39:06.212077 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:39:06.212128 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:39:06.212178 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3470 00:39:06.212229 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3471 00:39:06.212279 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3472 00:39:06.212330 Total UI for P1: 0, mck2ui 16
3473 00:39:06.212381 best dqsien dly found for B0: ( 1, 3, 22)
3474 00:39:06.212432 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 00:39:06.212483 Total UI for P1: 0, mck2ui 16
3476 00:39:06.212534 best dqsien dly found for B1: ( 1, 3, 26)
3477 00:39:06.212585 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3478 00:39:06.212635 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3479 00:39:06.212685
3480 00:39:06.212736 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3481 00:39:06.212786 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3482 00:39:06.212837 [Gating] SW calibration Done
3483 00:39:06.212887 ==
3484 00:39:06.212937 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 00:39:06.212988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 00:39:06.213039 ==
3487 00:39:06.213090 RX Vref Scan: 0
3488 00:39:06.213140
3489 00:39:06.213190 RX Vref 0 -> 0, step: 1
3490 00:39:06.213242
3491 00:39:06.213333 RX Delay -40 -> 252, step: 8
3492 00:39:06.213384 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3493 00:39:06.213435 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3494 00:39:06.213487 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3495 00:39:06.213537 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3496 00:39:06.213587 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3497 00:39:06.213638 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3498 00:39:06.213689 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3499 00:39:06.213739 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3500 00:39:06.213789 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3501 00:39:06.213840 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3502 00:39:06.213891 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3503 00:39:06.213941 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3504 00:39:06.213991 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3505 00:39:06.214239 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3506 00:39:06.214297 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3507 00:39:06.214349 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3508 00:39:06.214400 ==
3509 00:39:06.214451 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 00:39:06.214502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 00:39:06.214554 ==
3512 00:39:06.214604 DQS Delay:
3513 00:39:06.214654 DQS0 = 0, DQS1 = 0
3514 00:39:06.214704 DQM Delay:
3515 00:39:06.214755 DQM0 = 115, DQM1 = 111
3516 00:39:06.214805 DQ Delay:
3517 00:39:06.214855 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3518 00:39:06.214907 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3519 00:39:06.214958 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3520 00:39:06.215018 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3521 00:39:06.215071
3522 00:39:06.215122
3523 00:39:06.215172 ==
3524 00:39:06.215222 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 00:39:06.215273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 00:39:06.215324 ==
3527 00:39:06.215386
3528 00:39:06.215483
3529 00:39:06.215535 TX Vref Scan disable
3530 00:39:06.215587 == TX Byte 0 ==
3531 00:39:06.215638 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3532 00:39:06.215689 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3533 00:39:06.215740 == TX Byte 1 ==
3534 00:39:06.215791 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3535 00:39:06.215842 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3536 00:39:06.215892 ==
3537 00:39:06.215942 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 00:39:06.215992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 00:39:06.216044 ==
3540 00:39:06.216094 TX Vref=22, minBit 9, minWin=25, winSum=419
3541 00:39:06.216146 TX Vref=24, minBit 3, minWin=25, winSum=419
3542 00:39:06.216197 TX Vref=26, minBit 9, minWin=25, winSum=424
3543 00:39:06.216248 TX Vref=28, minBit 2, minWin=26, winSum=430
3544 00:39:06.216298 TX Vref=30, minBit 8, minWin=26, winSum=429
3545 00:39:06.216349 TX Vref=32, minBit 3, minWin=26, winSum=431
3546 00:39:06.216400 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 32
3547 00:39:06.216451
3548 00:39:06.216502 Final TX Range 1 Vref 32
3549 00:39:06.216552
3550 00:39:06.216602 ==
3551 00:39:06.216653 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 00:39:06.216703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 00:39:06.216754 ==
3554 00:39:06.216804
3555 00:39:06.216854
3556 00:39:06.216904 TX Vref Scan disable
3557 00:39:06.216955 == TX Byte 0 ==
3558 00:39:06.217044 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3559 00:39:06.217164 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3560 00:39:06.217245 == TX Byte 1 ==
3561 00:39:06.217324 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 00:39:06.217382 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 00:39:06.217461
3564 00:39:06.217536 [DATLAT]
3565 00:39:06.217588 Freq=1200, CH1 RK1
3566 00:39:06.217640
3567 00:39:06.217691 DATLAT Default: 0xd
3568 00:39:06.217742 0, 0xFFFF, sum = 0
3569 00:39:06.217794 1, 0xFFFF, sum = 0
3570 00:39:06.217846 2, 0xFFFF, sum = 0
3571 00:39:06.217899 3, 0xFFFF, sum = 0
3572 00:39:06.217950 4, 0xFFFF, sum = 0
3573 00:39:06.218002 5, 0xFFFF, sum = 0
3574 00:39:06.218062 6, 0xFFFF, sum = 0
3575 00:39:06.218145 7, 0xFFFF, sum = 0
3576 00:39:06.218226 8, 0xFFFF, sum = 0
3577 00:39:06.218308 9, 0xFFFF, sum = 0
3578 00:39:06.218389 10, 0xFFFF, sum = 0
3579 00:39:06.218460 11, 0xFFFF, sum = 0
3580 00:39:06.218513 12, 0x0, sum = 1
3581 00:39:06.218564 13, 0x0, sum = 2
3582 00:39:06.218616 14, 0x0, sum = 3
3583 00:39:06.218667 15, 0x0, sum = 4
3584 00:39:06.218718 best_step = 13
3585 00:39:06.218769
3586 00:39:06.218819 ==
3587 00:39:06.218870 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 00:39:06.218921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 00:39:06.218972 ==
3590 00:39:06.219022 RX Vref Scan: 0
3591 00:39:06.219073
3592 00:39:06.219159 RX Vref 0 -> 0, step: 1
3593 00:39:06.219226
3594 00:39:06.219285 RX Delay -13 -> 252, step: 4
3595 00:39:06.219350 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3596 00:39:06.219405 iDelay=191, Bit 1, Center 114 (47 ~ 182) 136
3597 00:39:06.219469 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3598 00:39:06.219535 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3599 00:39:06.219616 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3600 00:39:06.219679 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3601 00:39:06.219739 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3602 00:39:06.219807 iDelay=191, Bit 7, Center 114 (47 ~ 182) 136
3603 00:39:06.219879 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3604 00:39:06.219939 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3605 00:39:06.220003 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3606 00:39:06.220069 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3607 00:39:06.220127 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3608 00:39:06.220185 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3609 00:39:06.220245 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3610 00:39:06.220314 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3611 00:39:06.220372 ==
3612 00:39:06.220439 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 00:39:06.220512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 00:39:06.220573 ==
3615 00:39:06.220631 DQS Delay:
3616 00:39:06.220690 DQS0 = 0, DQS1 = 0
3617 00:39:06.220753 DQM Delay:
3618 00:39:06.220813 DQM0 = 115, DQM1 = 112
3619 00:39:06.220871 DQ Delay:
3620 00:39:06.220924 DQ0 =116, DQ1 =114, DQ2 =108, DQ3 =112
3621 00:39:06.220989 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =114
3622 00:39:06.221054 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3623 00:39:06.221109 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3624 00:39:06.221160
3625 00:39:06.221211
3626 00:39:06.221284 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3627 00:39:06.221359 CH1 RK1: MR19=304, MR18=F90B
3628 00:39:06.221418 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3629 00:39:06.221480 [RxdqsGatingPostProcess] freq 1200
3630 00:39:06.221539 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3631 00:39:06.221604 best DQS0 dly(2T, 0.5T) = (0, 11)
3632 00:39:06.221663 best DQS1 dly(2T, 0.5T) = (0, 11)
3633 00:39:06.221721 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3634 00:39:06.221782 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3635 00:39:06.221846 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 00:39:06.221904 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 00:39:06.221961 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 00:39:06.222019 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 00:39:06.222079 Pre-setting of DQS Precalculation
3640 00:39:06.222145 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3641 00:39:06.222203 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3642 00:39:06.222462 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3643 00:39:06.222522
3644 00:39:06.222574
3645 00:39:06.222625 [Calibration Summary] 2400 Mbps
3646 00:39:06.222676 CH 0, Rank 0
3647 00:39:06.222727 SW Impedance : PASS
3648 00:39:06.222778 DUTY Scan : NO K
3649 00:39:06.222829 ZQ Calibration : PASS
3650 00:39:06.222879 Jitter Meter : NO K
3651 00:39:06.222931 CBT Training : PASS
3652 00:39:06.222982 Write leveling : PASS
3653 00:39:06.223033 RX DQS gating : PASS
3654 00:39:06.223084 RX DQ/DQS(RDDQC) : PASS
3655 00:39:06.223134 TX DQ/DQS : PASS
3656 00:39:06.223207 RX DATLAT : PASS
3657 00:39:06.223292 RX DQ/DQS(Engine): PASS
3658 00:39:06.223347 TX OE : NO K
3659 00:39:06.223399 All Pass.
3660 00:39:06.223480
3661 00:39:06.223531 CH 0, Rank 1
3662 00:39:06.223582 SW Impedance : PASS
3663 00:39:06.223633 DUTY Scan : NO K
3664 00:39:06.223683 ZQ Calibration : PASS
3665 00:39:06.223734 Jitter Meter : NO K
3666 00:39:06.223785 CBT Training : PASS
3667 00:39:06.223835 Write leveling : PASS
3668 00:39:06.223885 RX DQS gating : PASS
3669 00:39:06.223936 RX DQ/DQS(RDDQC) : PASS
3670 00:39:06.223986 TX DQ/DQS : PASS
3671 00:39:06.224037 RX DATLAT : PASS
3672 00:39:06.224087 RX DQ/DQS(Engine): PASS
3673 00:39:06.224137 TX OE : NO K
3674 00:39:06.224187 All Pass.
3675 00:39:06.224237
3676 00:39:06.224287 CH 1, Rank 0
3677 00:39:06.224336 SW Impedance : PASS
3678 00:39:06.224387 DUTY Scan : NO K
3679 00:39:06.224437 ZQ Calibration : PASS
3680 00:39:06.224487 Jitter Meter : NO K
3681 00:39:06.224537 CBT Training : PASS
3682 00:39:06.224587 Write leveling : PASS
3683 00:39:06.224637 RX DQS gating : PASS
3684 00:39:06.224687 RX DQ/DQS(RDDQC) : PASS
3685 00:39:06.224737 TX DQ/DQS : PASS
3686 00:39:06.224787 RX DATLAT : PASS
3687 00:39:06.224837 RX DQ/DQS(Engine): PASS
3688 00:39:06.224888 TX OE : NO K
3689 00:39:06.224938 All Pass.
3690 00:39:06.224988
3691 00:39:06.225038 CH 1, Rank 1
3692 00:39:06.225088 SW Impedance : PASS
3693 00:39:06.225139 DUTY Scan : NO K
3694 00:39:06.225189 ZQ Calibration : PASS
3695 00:39:06.225240 Jitter Meter : NO K
3696 00:39:06.225333 CBT Training : PASS
3697 00:39:06.225383 Write leveling : PASS
3698 00:39:06.225452 RX DQS gating : PASS
3699 00:39:06.225505 RX DQ/DQS(RDDQC) : PASS
3700 00:39:06.225556 TX DQ/DQS : PASS
3701 00:39:06.225606 RX DATLAT : PASS
3702 00:39:06.225657 RX DQ/DQS(Engine): PASS
3703 00:39:06.225707 TX OE : NO K
3704 00:39:06.225757 All Pass.
3705 00:39:06.225808
3706 00:39:06.225858 DramC Write-DBI off
3707 00:39:06.225908 PER_BANK_REFRESH: Hybrid Mode
3708 00:39:06.225959 TX_TRACKING: ON
3709 00:39:06.226010 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3710 00:39:06.226061 [FAST_K] Save calibration result to emmc
3711 00:39:06.226111 dramc_set_vcore_voltage set vcore to 650000
3712 00:39:06.226162 Read voltage for 600, 5
3713 00:39:06.226212 Vio18 = 0
3714 00:39:06.226263 Vcore = 650000
3715 00:39:06.226313 Vdram = 0
3716 00:39:06.226363 Vddq = 0
3717 00:39:06.226412 Vmddr = 0
3718 00:39:06.226463 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3719 00:39:06.226514 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3720 00:39:06.226565 MEM_TYPE=3, freq_sel=19
3721 00:39:06.226615 sv_algorithm_assistance_LP4_1600
3722 00:39:06.226666 ============ PULL DRAM RESETB DOWN ============
3723 00:39:06.226716 ========== PULL DRAM RESETB DOWN end =========
3724 00:39:06.226767 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3725 00:39:06.226818 ===================================
3726 00:39:06.226868 LPDDR4 DRAM CONFIGURATION
3727 00:39:06.226918 ===================================
3728 00:39:06.226969 EX_ROW_EN[0] = 0x0
3729 00:39:06.227019 EX_ROW_EN[1] = 0x0
3730 00:39:06.227069 LP4Y_EN = 0x0
3731 00:39:06.227119 WORK_FSP = 0x0
3732 00:39:06.227169 WL = 0x2
3733 00:39:06.227219 RL = 0x2
3734 00:39:06.227269 BL = 0x2
3735 00:39:06.227319 RPST = 0x0
3736 00:39:06.227369 RD_PRE = 0x0
3737 00:39:06.227423 WR_PRE = 0x1
3738 00:39:06.227474 WR_PST = 0x0
3739 00:39:06.227523 DBI_WR = 0x0
3740 00:39:06.227573 DBI_RD = 0x0
3741 00:39:06.227646 OTF = 0x1
3742 00:39:06.227712 ===================================
3743 00:39:06.227762 ===================================
3744 00:39:06.227813 ANA top config
3745 00:39:06.227863 ===================================
3746 00:39:06.227914 DLL_ASYNC_EN = 0
3747 00:39:06.227964 ALL_SLAVE_EN = 1
3748 00:39:06.228018 NEW_RANK_MODE = 1
3749 00:39:06.228072 DLL_IDLE_MODE = 1
3750 00:39:06.228124 LP45_APHY_COMB_EN = 1
3751 00:39:06.228174 TX_ODT_DIS = 1
3752 00:39:06.228229 NEW_8X_MODE = 1
3753 00:39:06.228281 ===================================
3754 00:39:06.228332 ===================================
3755 00:39:06.228382 data_rate = 1200
3756 00:39:06.228432 CKR = 1
3757 00:39:06.228482 DQ_P2S_RATIO = 8
3758 00:39:06.228532 ===================================
3759 00:39:06.228583 CA_P2S_RATIO = 8
3760 00:39:06.228633 DQ_CA_OPEN = 0
3761 00:39:06.228683 DQ_SEMI_OPEN = 0
3762 00:39:06.228733 CA_SEMI_OPEN = 0
3763 00:39:06.228783 CA_FULL_RATE = 0
3764 00:39:06.228834 DQ_CKDIV4_EN = 1
3765 00:39:06.228883 CA_CKDIV4_EN = 1
3766 00:39:06.228934 CA_PREDIV_EN = 0
3767 00:39:06.228984 PH8_DLY = 0
3768 00:39:06.229033 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3769 00:39:06.229084 DQ_AAMCK_DIV = 4
3770 00:39:06.229134 CA_AAMCK_DIV = 4
3771 00:39:06.229184 CA_ADMCK_DIV = 4
3772 00:39:06.229235 DQ_TRACK_CA_EN = 0
3773 00:39:06.229326 CA_PICK = 600
3774 00:39:06.229381 CA_MCKIO = 600
3775 00:39:06.229434 MCKIO_SEMI = 0
3776 00:39:06.229486 PLL_FREQ = 2288
3777 00:39:06.229537 DQ_UI_PI_RATIO = 32
3778 00:39:06.229587 CA_UI_PI_RATIO = 0
3779 00:39:06.229646 ===================================
3780 00:39:06.229699 ===================================
3781 00:39:06.229749 memory_type:LPDDR4
3782 00:39:06.229807 GP_NUM : 10
3783 00:39:06.229864 SRAM_EN : 1
3784 00:39:06.229922 MD32_EN : 0
3785 00:39:06.229972 ===================================
3786 00:39:06.230023 [ANA_INIT] >>>>>>>>>>>>>>
3787 00:39:06.230073 <<<<<< [CONFIGURE PHASE]: ANA_TX
3788 00:39:06.230125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3789 00:39:06.230176 ===================================
3790 00:39:06.230226 data_rate = 1200,PCW = 0X5800
3791 00:39:06.230276 ===================================
3792 00:39:06.230326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3793 00:39:06.230577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 00:39:06.230635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 00:39:06.230687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3796 00:39:06.230739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3797 00:39:06.230790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3798 00:39:06.230841 [ANA_INIT] flow start
3799 00:39:06.230892 [ANA_INIT] PLL >>>>>>>>
3800 00:39:06.230942 [ANA_INIT] PLL <<<<<<<<
3801 00:39:06.230993 [ANA_INIT] MIDPI >>>>>>>>
3802 00:39:06.231043 [ANA_INIT] MIDPI <<<<<<<<
3803 00:39:06.231094 [ANA_INIT] DLL >>>>>>>>
3804 00:39:06.231143 [ANA_INIT] flow end
3805 00:39:06.231193 ============ LP4 DIFF to SE enter ============
3806 00:39:06.231245 ============ LP4 DIFF to SE exit ============
3807 00:39:06.231296 [ANA_INIT] <<<<<<<<<<<<<
3808 00:39:06.231346 [Flow] Enable top DCM control >>>>>
3809 00:39:06.231455 [Flow] Enable top DCM control <<<<<
3810 00:39:06.231513 Enable DLL master slave shuffle
3811 00:39:06.231564 ==============================================================
3812 00:39:06.231619 Gating Mode config
3813 00:39:06.231682 ==============================================================
3814 00:39:06.231738 Config description:
3815 00:39:06.241722 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3816 00:39:06.248238 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3817 00:39:06.255171 SELPH_MODE 0: By rank 1: By Phase
3818 00:39:06.258327 ==============================================================
3819 00:39:06.261965 GAT_TRACK_EN = 1
3820 00:39:06.264991 RX_GATING_MODE = 2
3821 00:39:06.268556 RX_GATING_TRACK_MODE = 2
3822 00:39:06.272172 SELPH_MODE = 1
3823 00:39:06.274936 PICG_EARLY_EN = 1
3824 00:39:06.278051 VALID_LAT_VALUE = 1
3825 00:39:06.284726 ==============================================================
3826 00:39:06.288278 Enter into Gating configuration >>>>
3827 00:39:06.291139 Exit from Gating configuration <<<<
3828 00:39:06.294854 Enter into DVFS_PRE_config >>>>>
3829 00:39:06.305151 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3830 00:39:06.308627 Exit from DVFS_PRE_config <<<<<
3831 00:39:06.311387 Enter into PICG configuration >>>>
3832 00:39:06.314767 Exit from PICG configuration <<<<
3833 00:39:06.317597 [RX_INPUT] configuration >>>>>
3834 00:39:06.320703 [RX_INPUT] configuration <<<<<
3835 00:39:06.324685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3836 00:39:06.330610 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3837 00:39:06.337417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3838 00:39:06.340447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3839 00:39:06.347619 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 00:39:06.353612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 00:39:06.356813 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3842 00:39:06.363749 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3843 00:39:06.367746 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3844 00:39:06.370755 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3845 00:39:06.373730 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3846 00:39:06.380713 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3847 00:39:06.383701 ===================================
3848 00:39:06.383782 LPDDR4 DRAM CONFIGURATION
3849 00:39:06.387040 ===================================
3850 00:39:06.390284 EX_ROW_EN[0] = 0x0
3851 00:39:06.393535 EX_ROW_EN[1] = 0x0
3852 00:39:06.393615 LP4Y_EN = 0x0
3853 00:39:06.397000 WORK_FSP = 0x0
3854 00:39:06.397081 WL = 0x2
3855 00:39:06.400200 RL = 0x2
3856 00:39:06.400279 BL = 0x2
3857 00:39:06.403572 RPST = 0x0
3858 00:39:06.403651 RD_PRE = 0x0
3859 00:39:06.406679 WR_PRE = 0x1
3860 00:39:06.406758 WR_PST = 0x0
3861 00:39:06.410700 DBI_WR = 0x0
3862 00:39:06.410781 DBI_RD = 0x0
3863 00:39:06.413419 OTF = 0x1
3864 00:39:06.416346 ===================================
3865 00:39:06.420102 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3866 00:39:06.423066 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3867 00:39:06.430179 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3868 00:39:06.432981 ===================================
3869 00:39:06.433068 LPDDR4 DRAM CONFIGURATION
3870 00:39:06.436248 ===================================
3871 00:39:06.439796 EX_ROW_EN[0] = 0x10
3872 00:39:06.443049 EX_ROW_EN[1] = 0x0
3873 00:39:06.443133 LP4Y_EN = 0x0
3874 00:39:06.446339 WORK_FSP = 0x0
3875 00:39:06.446422 WL = 0x2
3876 00:39:06.449963 RL = 0x2
3877 00:39:06.450046 BL = 0x2
3878 00:39:06.453155 RPST = 0x0
3879 00:39:06.453239 RD_PRE = 0x0
3880 00:39:06.456438 WR_PRE = 0x1
3881 00:39:06.456521 WR_PST = 0x0
3882 00:39:06.459820 DBI_WR = 0x0
3883 00:39:06.459905 DBI_RD = 0x0
3884 00:39:06.462964 OTF = 0x1
3885 00:39:06.466575 ===================================
3886 00:39:06.472587 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3887 00:39:06.475851 nWR fixed to 30
3888 00:39:06.480384 [ModeRegInit_LP4] CH0 RK0
3889 00:39:06.480470 [ModeRegInit_LP4] CH0 RK1
3890 00:39:06.482814 [ModeRegInit_LP4] CH1 RK0
3891 00:39:06.486639 [ModeRegInit_LP4] CH1 RK1
3892 00:39:06.486723 match AC timing 17
3893 00:39:06.492399 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3894 00:39:06.495890 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3895 00:39:06.499227 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3896 00:39:06.506348 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3897 00:39:06.508928 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3898 00:39:06.509016 ==
3899 00:39:06.512206 Dram Type= 6, Freq= 0, CH_0, rank 0
3900 00:39:06.515447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3901 00:39:06.515532 ==
3902 00:39:06.522666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3903 00:39:06.529081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3904 00:39:06.532091 [CA 0] Center 36 (6~67) winsize 62
3905 00:39:06.535365 [CA 1] Center 36 (6~67) winsize 62
3906 00:39:06.538813 [CA 2] Center 34 (4~65) winsize 62
3907 00:39:06.542470 [CA 3] Center 34 (4~65) winsize 62
3908 00:39:06.545197 [CA 4] Center 33 (3~64) winsize 62
3909 00:39:06.548552 [CA 5] Center 33 (2~64) winsize 63
3910 00:39:06.548649
3911 00:39:06.551872 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3912 00:39:06.551991
3913 00:39:06.555235 [CATrainingPosCal] consider 1 rank data
3914 00:39:06.558270 u2DelayCellTimex100 = 270/100 ps
3915 00:39:06.561628 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3916 00:39:06.565179 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3917 00:39:06.568406 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3918 00:39:06.571635 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3919 00:39:06.578330 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3920 00:39:06.581486 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3921 00:39:06.581572
3922 00:39:06.585073 CA PerBit enable=1, Macro0, CA PI delay=33
3923 00:39:06.585158
3924 00:39:06.588672 [CBTSetCACLKResult] CA Dly = 33
3925 00:39:06.588758 CS Dly: 6 (0~37)
3926 00:39:06.588843 ==
3927 00:39:06.591286 Dram Type= 6, Freq= 0, CH_0, rank 1
3928 00:39:06.597924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 00:39:06.598016 ==
3930 00:39:06.601415 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 00:39:06.607940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3932 00:39:06.611322 [CA 0] Center 36 (6~67) winsize 62
3933 00:39:06.614621 [CA 1] Center 36 (6~67) winsize 62
3934 00:39:06.618648 [CA 2] Center 34 (4~65) winsize 62
3935 00:39:06.621103 [CA 3] Center 34 (3~65) winsize 63
3936 00:39:06.624106 [CA 4] Center 34 (3~65) winsize 63
3937 00:39:06.627703 [CA 5] Center 33 (3~64) winsize 62
3938 00:39:06.627789
3939 00:39:06.631133 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3940 00:39:06.631217
3941 00:39:06.634202 [CATrainingPosCal] consider 2 rank data
3942 00:39:06.637422 u2DelayCellTimex100 = 270/100 ps
3943 00:39:06.640831 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3944 00:39:06.647397 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3945 00:39:06.650428 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 00:39:06.654041 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 00:39:06.657038 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 00:39:06.660366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 00:39:06.660455
3950 00:39:06.664266 CA PerBit enable=1, Macro0, CA PI delay=33
3951 00:39:06.664352
3952 00:39:06.667796 [CBTSetCACLKResult] CA Dly = 33
3953 00:39:06.670780 CS Dly: 5 (0~36)
3954 00:39:06.670865
3955 00:39:06.674156 ----->DramcWriteLeveling(PI) begin...
3956 00:39:06.674242 ==
3957 00:39:06.677007 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 00:39:06.680454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 00:39:06.680543 ==
3960 00:39:06.683889 Write leveling (Byte 0): 32 => 32
3961 00:39:06.686789 Write leveling (Byte 1): 28 => 28
3962 00:39:06.690644 DramcWriteLeveling(PI) end<-----
3963 00:39:06.690733
3964 00:39:06.690818 ==
3965 00:39:06.693543 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 00:39:06.697082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 00:39:06.697169 ==
3968 00:39:06.700185 [Gating] SW mode calibration
3969 00:39:06.707071 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3970 00:39:06.713726 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3971 00:39:06.716958 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 00:39:06.720036 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 00:39:06.726426 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 00:39:06.729395 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
3975 00:39:06.732840 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
3976 00:39:06.739527 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 00:39:06.742836 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 00:39:06.745992 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 00:39:06.752838 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 00:39:06.756447 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 00:39:06.759441 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 00:39:06.766188 0 10 12 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (1 1)
3983 00:39:06.769492 0 10 16 | B1->B0 | 3838 4343 | 0 1 | (0 0) (0 0)
3984 00:39:06.772673 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 00:39:06.779160 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 00:39:06.782292 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 00:39:06.785741 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 00:39:06.792303 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 00:39:06.796048 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 00:39:06.798949 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3991 00:39:06.805662 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3992 00:39:06.809685 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 00:39:06.811939 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 00:39:06.818791 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 00:39:06.822084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:39:06.825622 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:39:06.831998 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:39:06.835307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:39:06.839072 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:39:06.844994 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:39:06.848119 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:39:06.855293 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:39:06.858253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:39:06.861575 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:39:06.865045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:39:06.871873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4007 00:39:06.874715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4008 00:39:06.878384 Total UI for P1: 0, mck2ui 16
4009 00:39:06.881216 best dqsien dly found for B0: ( 0, 13, 12)
4010 00:39:06.884433 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 00:39:06.888158 Total UI for P1: 0, mck2ui 16
4012 00:39:06.891248 best dqsien dly found for B1: ( 0, 13, 14)
4013 00:39:06.894679 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4014 00:39:06.901066 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4015 00:39:06.901153
4016 00:39:06.904301 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4017 00:39:06.908570 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4018 00:39:06.911146 [Gating] SW calibration Done
4019 00:39:06.911231 ==
4020 00:39:06.914377 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 00:39:06.918028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 00:39:06.918112 ==
4023 00:39:06.921075 RX Vref Scan: 0
4024 00:39:06.921156
4025 00:39:06.921221 RX Vref 0 -> 0, step: 1
4026 00:39:06.921321
4027 00:39:06.925535 RX Delay -230 -> 252, step: 16
4028 00:39:06.927691 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4029 00:39:06.934583 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4030 00:39:06.939099 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4031 00:39:06.940973 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4032 00:39:06.943950 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4033 00:39:06.951229 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4034 00:39:06.954301 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4035 00:39:06.957242 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4036 00:39:06.960428 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4037 00:39:06.963776 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4038 00:39:06.970311 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4039 00:39:06.973964 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4040 00:39:06.977095 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4041 00:39:06.983621 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4042 00:39:06.987014 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4043 00:39:06.991191 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4044 00:39:06.991278 ==
4045 00:39:06.993388 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 00:39:06.996441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 00:39:07.000505 ==
4048 00:39:07.000594 DQS Delay:
4049 00:39:07.000660 DQS0 = 0, DQS1 = 0
4050 00:39:07.003145 DQM Delay:
4051 00:39:07.003227 DQM0 = 45, DQM1 = 37
4052 00:39:07.006660 DQ Delay:
4053 00:39:07.006743 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4054 00:39:07.009899 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4055 00:39:07.013198 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4056 00:39:07.016450 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4057 00:39:07.016535
4058 00:39:07.020167
4059 00:39:07.020249 ==
4060 00:39:07.023305 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 00:39:07.026391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 00:39:07.026479 ==
4063 00:39:07.026544
4064 00:39:07.026603
4065 00:39:07.029637 TX Vref Scan disable
4066 00:39:07.029718 == TX Byte 0 ==
4067 00:39:07.036302 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4068 00:39:07.039464 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4069 00:39:07.039549 == TX Byte 1 ==
4070 00:39:07.046865 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4071 00:39:07.049246 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4072 00:39:07.049353 ==
4073 00:39:07.052408 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 00:39:07.056190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 00:39:07.056274 ==
4076 00:39:07.056339
4077 00:39:07.059537
4078 00:39:07.059621 TX Vref Scan disable
4079 00:39:07.062735 == TX Byte 0 ==
4080 00:39:07.066572 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4081 00:39:07.072589 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4082 00:39:07.072687 == TX Byte 1 ==
4083 00:39:07.075765 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4084 00:39:07.082740 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4085 00:39:07.082833
4086 00:39:07.082920 [DATLAT]
4087 00:39:07.082999 Freq=600, CH0 RK0
4088 00:39:07.083076
4089 00:39:07.086177 DATLAT Default: 0x9
4090 00:39:07.086260 0, 0xFFFF, sum = 0
4091 00:39:07.088809 1, 0xFFFF, sum = 0
4092 00:39:07.093137 2, 0xFFFF, sum = 0
4093 00:39:07.093222 3, 0xFFFF, sum = 0
4094 00:39:07.095296 4, 0xFFFF, sum = 0
4095 00:39:07.095381 5, 0xFFFF, sum = 0
4096 00:39:07.099569 6, 0xFFFF, sum = 0
4097 00:39:07.099654 7, 0xFFFF, sum = 0
4098 00:39:07.101976 8, 0x0, sum = 1
4099 00:39:07.102061 9, 0x0, sum = 2
4100 00:39:07.105816 10, 0x0, sum = 3
4101 00:39:07.105914 11, 0x0, sum = 4
4102 00:39:07.106021 best_step = 9
4103 00:39:07.106114
4104 00:39:07.108747 ==
4105 00:39:07.112194 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 00:39:07.115853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 00:39:07.115934 ==
4108 00:39:07.115998 RX Vref Scan: 1
4109 00:39:07.116056
4110 00:39:07.118565 RX Vref 0 -> 0, step: 1
4111 00:39:07.118645
4112 00:39:07.122014 RX Delay -179 -> 252, step: 8
4113 00:39:07.122093
4114 00:39:07.125356 Set Vref, RX VrefLevel [Byte0]: 56
4115 00:39:07.128686 [Byte1]: 49
4116 00:39:07.131235
4117 00:39:07.131316 Final RX Vref Byte 0 = 56 to rank0
4118 00:39:07.134708 Final RX Vref Byte 1 = 49 to rank0
4119 00:39:07.138159 Final RX Vref Byte 0 = 56 to rank1
4120 00:39:07.141249 Final RX Vref Byte 1 = 49 to rank1==
4121 00:39:07.144811 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 00:39:07.151550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 00:39:07.151648 ==
4124 00:39:07.151715 DQS Delay:
4125 00:39:07.154725 DQS0 = 0, DQS1 = 0
4126 00:39:07.154805 DQM Delay:
4127 00:39:07.154868 DQM0 = 44, DQM1 = 37
4128 00:39:07.157804 DQ Delay:
4129 00:39:07.161499 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4130 00:39:07.164357 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4131 00:39:07.168137 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =32
4132 00:39:07.171174 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4133 00:39:07.171271
4134 00:39:07.171368
4135 00:39:07.177833 [DQSOSCAuto] RK0, (LSB)MR18= 0x564d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
4136 00:39:07.180811 CH0 RK0: MR19=808, MR18=564D
4137 00:39:07.187305 CH0_RK0: MR19=0x808, MR18=0x564D, DQSOSC=393, MR23=63, INC=169, DEC=113
4138 00:39:07.187408
4139 00:39:07.190722 ----->DramcWriteLeveling(PI) begin...
4140 00:39:07.190844 ==
4141 00:39:07.194021 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 00:39:07.197611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 00:39:07.197697 ==
4144 00:39:07.200659 Write leveling (Byte 0): 33 => 33
4145 00:39:07.203950 Write leveling (Byte 1): 30 => 30
4146 00:39:07.207276 DramcWriteLeveling(PI) end<-----
4147 00:39:07.207361
4148 00:39:07.207425 ==
4149 00:39:07.210427 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 00:39:07.214190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 00:39:07.217478 ==
4152 00:39:07.217563 [Gating] SW mode calibration
4153 00:39:07.226847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4154 00:39:07.230430 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4155 00:39:07.233966 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 00:39:07.239925 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 00:39:07.243338 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4158 00:39:07.246930 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4159 00:39:07.253283 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4160 00:39:07.256401 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 00:39:07.259621 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 00:39:07.266595 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 00:39:07.270285 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 00:39:07.273144 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 00:39:07.279734 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 00:39:07.282849 0 10 12 | B1->B0 | 2727 3333 | 0 0 | (1 1) (0 0)
4167 00:39:07.286221 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
4168 00:39:07.292839 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 00:39:07.296130 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 00:39:07.299532 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 00:39:07.307085 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 00:39:07.309135 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 00:39:07.313066 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4174 00:39:07.319201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4175 00:39:07.322569 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 00:39:07.325856 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 00:39:07.332576 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 00:39:07.336252 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 00:39:07.338746 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 00:39:07.345663 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:39:07.348705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:39:07.352159 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:39:07.358537 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:39:07.361646 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:39:07.365564 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:39:07.371780 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:39:07.375060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:39:07.378524 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:39:07.384991 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:39:07.388495 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:39:07.391463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 00:39:07.394909 Total UI for P1: 0, mck2ui 16
4193 00:39:07.398197 best dqsien dly found for B0: ( 0, 13, 14)
4194 00:39:07.401500 Total UI for P1: 0, mck2ui 16
4195 00:39:07.405085 best dqsien dly found for B1: ( 0, 13, 14)
4196 00:39:07.411175 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4197 00:39:07.414527 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4198 00:39:07.414619
4199 00:39:07.417612 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 00:39:07.421066 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4201 00:39:07.424186 [Gating] SW calibration Done
4202 00:39:07.424274 ==
4203 00:39:07.427353 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 00:39:07.430858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 00:39:07.430970 ==
4206 00:39:07.434293 RX Vref Scan: 0
4207 00:39:07.434378
4208 00:39:07.434442 RX Vref 0 -> 0, step: 1
4209 00:39:07.434502
4210 00:39:07.437745 RX Delay -230 -> 252, step: 16
4211 00:39:07.445165 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4212 00:39:07.447222 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4213 00:39:07.450448 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4214 00:39:07.453809 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4215 00:39:07.457249 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4216 00:39:07.463641 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4217 00:39:07.467200 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4218 00:39:07.470394 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4219 00:39:07.473746 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4220 00:39:07.480288 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4221 00:39:07.483445 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4222 00:39:07.486842 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4223 00:39:07.490178 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4224 00:39:07.496890 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4225 00:39:07.500567 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4226 00:39:07.503268 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4227 00:39:07.503352 ==
4228 00:39:07.506704 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 00:39:07.513294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 00:39:07.513403 ==
4231 00:39:07.513469 DQS Delay:
4232 00:39:07.513528 DQS0 = 0, DQS1 = 0
4233 00:39:07.516896 DQM Delay:
4234 00:39:07.516977 DQM0 = 49, DQM1 = 37
4235 00:39:07.520087 DQ Delay:
4236 00:39:07.523328 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4237 00:39:07.523411 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4238 00:39:07.526610 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4239 00:39:07.532944 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4240 00:39:07.533038
4241 00:39:07.533102
4242 00:39:07.533160 ==
4243 00:39:07.536205 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 00:39:07.539813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 00:39:07.539896 ==
4246 00:39:07.539959
4247 00:39:07.540018
4248 00:39:07.542999 TX Vref Scan disable
4249 00:39:07.543079 == TX Byte 0 ==
4250 00:39:07.549534 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4251 00:39:07.552682 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4252 00:39:07.552766 == TX Byte 1 ==
4253 00:39:07.559446 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4254 00:39:07.562805 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4255 00:39:07.562889 ==
4256 00:39:07.565984 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 00:39:07.569072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 00:39:07.569154 ==
4259 00:39:07.572580
4260 00:39:07.572660
4261 00:39:07.572723 TX Vref Scan disable
4262 00:39:07.576214 == TX Byte 0 ==
4263 00:39:07.579190 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4264 00:39:07.585896 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4265 00:39:07.585991 == TX Byte 1 ==
4266 00:39:07.588971 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4267 00:39:07.595881 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4268 00:39:07.595982
4269 00:39:07.596047 [DATLAT]
4270 00:39:07.596106 Freq=600, CH0 RK1
4271 00:39:07.596165
4272 00:39:07.599313 DATLAT Default: 0x9
4273 00:39:07.602738 0, 0xFFFF, sum = 0
4274 00:39:07.602822 1, 0xFFFF, sum = 0
4275 00:39:07.605855 2, 0xFFFF, sum = 0
4276 00:39:07.605938 3, 0xFFFF, sum = 0
4277 00:39:07.609188 4, 0xFFFF, sum = 0
4278 00:39:07.609297 5, 0xFFFF, sum = 0
4279 00:39:07.612842 6, 0xFFFF, sum = 0
4280 00:39:07.612938 7, 0xFFFF, sum = 0
4281 00:39:07.616056 8, 0x0, sum = 1
4282 00:39:07.616139 9, 0x0, sum = 2
4283 00:39:07.619260 10, 0x0, sum = 3
4284 00:39:07.619342 11, 0x0, sum = 4
4285 00:39:07.619406 best_step = 9
4286 00:39:07.619464
4287 00:39:07.622365 ==
4288 00:39:07.625213 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 00:39:07.629060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 00:39:07.629171 ==
4291 00:39:07.629270 RX Vref Scan: 0
4292 00:39:07.629364
4293 00:39:07.632114 RX Vref 0 -> 0, step: 1
4294 00:39:07.632197
4295 00:39:07.635397 RX Delay -179 -> 252, step: 8
4296 00:39:07.641985 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4297 00:39:07.645222 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4298 00:39:07.648492 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4299 00:39:07.651712 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4300 00:39:07.658386 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4301 00:39:07.661518 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4302 00:39:07.664949 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4303 00:39:07.668536 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4304 00:39:07.671789 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4305 00:39:07.678305 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4306 00:39:07.681196 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4307 00:39:07.684793 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4308 00:39:07.688456 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4309 00:39:07.694725 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4310 00:39:07.697794 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4311 00:39:07.701731 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4312 00:39:07.701836 ==
4313 00:39:07.704337 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 00:39:07.707545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 00:39:07.710827 ==
4316 00:39:07.710911 DQS Delay:
4317 00:39:07.710973 DQS0 = 0, DQS1 = 0
4318 00:39:07.714203 DQM Delay:
4319 00:39:07.714284 DQM0 = 43, DQM1 = 36
4320 00:39:07.717591 DQ Delay:
4321 00:39:07.720891 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4322 00:39:07.720972 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4323 00:39:07.724945 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =32
4324 00:39:07.731226 DQ12 =36, DQ13 =40, DQ14 =48, DQ15 =44
4325 00:39:07.731321
4326 00:39:07.731385
4327 00:39:07.737566 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4328 00:39:07.740705 CH0 RK1: MR19=808, MR18=4D48
4329 00:39:07.747483 CH0_RK1: MR19=0x808, MR18=0x4D48, DQSOSC=395, MR23=63, INC=168, DEC=112
4330 00:39:07.750733 [RxdqsGatingPostProcess] freq 600
4331 00:39:07.753562 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4332 00:39:07.757225 Pre-setting of DQS Precalculation
4333 00:39:07.763335 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4334 00:39:07.763421 ==
4335 00:39:07.766770 Dram Type= 6, Freq= 0, CH_1, rank 0
4336 00:39:07.770380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 00:39:07.770471 ==
4338 00:39:07.777040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4339 00:39:07.783780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4340 00:39:07.786681 [CA 0] Center 36 (6~66) winsize 61
4341 00:39:07.789975 [CA 1] Center 35 (5~66) winsize 62
4342 00:39:07.793697 [CA 2] Center 34 (4~65) winsize 62
4343 00:39:07.797571 [CA 3] Center 34 (3~65) winsize 63
4344 00:39:07.799569 [CA 4] Center 34 (3~65) winsize 63
4345 00:39:07.803123 [CA 5] Center 33 (3~64) winsize 62
4346 00:39:07.803209
4347 00:39:07.806488 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4348 00:39:07.806571
4349 00:39:07.809519 [CATrainingPosCal] consider 1 rank data
4350 00:39:07.812865 u2DelayCellTimex100 = 270/100 ps
4351 00:39:07.816047 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4352 00:39:07.819291 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4353 00:39:07.822655 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4354 00:39:07.826109 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4355 00:39:07.828946 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4356 00:39:07.832746 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4357 00:39:07.835815
4358 00:39:07.839022 CA PerBit enable=1, Macro0, CA PI delay=33
4359 00:39:07.839108
4360 00:39:07.842747 [CBTSetCACLKResult] CA Dly = 33
4361 00:39:07.842832 CS Dly: 3 (0~34)
4362 00:39:07.842916 ==
4363 00:39:07.845881 Dram Type= 6, Freq= 0, CH_1, rank 1
4364 00:39:07.849077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 00:39:07.849165 ==
4366 00:39:07.856630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 00:39:07.862048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4368 00:39:07.865644 [CA 0] Center 36 (6~66) winsize 61
4369 00:39:07.868765 [CA 1] Center 35 (5~66) winsize 62
4370 00:39:07.872005 [CA 2] Center 34 (4~65) winsize 62
4371 00:39:07.875491 [CA 3] Center 34 (3~65) winsize 63
4372 00:39:07.878671 [CA 4] Center 34 (4~65) winsize 62
4373 00:39:07.882427 [CA 5] Center 34 (3~65) winsize 63
4374 00:39:07.882529
4375 00:39:07.885644 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4376 00:39:07.885730
4377 00:39:07.888219 [CATrainingPosCal] consider 2 rank data
4378 00:39:07.892334 u2DelayCellTimex100 = 270/100 ps
4379 00:39:07.895113 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4380 00:39:07.898239 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 00:39:07.905056 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 00:39:07.908432 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4383 00:39:07.911944 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 00:39:07.914650 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 00:39:07.914739
4386 00:39:07.917808 CA PerBit enable=1, Macro0, CA PI delay=33
4387 00:39:07.917893
4388 00:39:07.921246 [CBTSetCACLKResult] CA Dly = 33
4389 00:39:07.921372 CS Dly: 4 (0~36)
4390 00:39:07.921492
4391 00:39:07.928134 ----->DramcWriteLeveling(PI) begin...
4392 00:39:07.928268 ==
4393 00:39:07.930976 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 00:39:07.934655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 00:39:07.934740 ==
4396 00:39:07.937844 Write leveling (Byte 0): 29 => 29
4397 00:39:07.941080 Write leveling (Byte 1): 29 => 29
4398 00:39:07.944546 DramcWriteLeveling(PI) end<-----
4399 00:39:07.944631
4400 00:39:07.944714 ==
4401 00:39:07.947502 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 00:39:07.950839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 00:39:07.950928 ==
4404 00:39:07.954034 [Gating] SW mode calibration
4405 00:39:07.960776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 00:39:07.967503 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4407 00:39:07.970634 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 00:39:07.973977 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 00:39:07.980752 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 00:39:07.984001 0 9 12 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 0)
4411 00:39:07.987256 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 00:39:07.993902 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 00:39:07.996878 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 00:39:08.000278 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 00:39:08.006861 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 00:39:08.010482 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 00:39:08.014272 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4418 00:39:08.021537 0 10 12 | B1->B0 | 3838 3a3a | 0 1 | (0 0) (0 0)
4419 00:39:08.023892 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 00:39:08.027154 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 00:39:08.033832 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 00:39:08.037093 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 00:39:08.039843 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 00:39:08.046325 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 00:39:08.049856 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 00:39:08.052795 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4427 00:39:08.059525 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 00:39:08.062878 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 00:39:08.066342 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:39:08.072915 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:39:08.076319 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:39:08.079334 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:39:08.085903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:39:08.088961 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:39:08.092443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:39:08.098960 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:39:08.102441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:39:08.105578 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:39:08.112368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:39:08.115577 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:39:08.118966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:39:08.125210 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4443 00:39:08.128682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 00:39:08.132727 Total UI for P1: 0, mck2ui 16
4445 00:39:08.135423 best dqsien dly found for B0: ( 0, 13, 12)
4446 00:39:08.138727 Total UI for P1: 0, mck2ui 16
4447 00:39:08.142236 best dqsien dly found for B1: ( 0, 13, 12)
4448 00:39:08.145084 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4449 00:39:08.149131 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4450 00:39:08.149250
4451 00:39:08.151683 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4452 00:39:08.155398 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4453 00:39:08.158554 [Gating] SW calibration Done
4454 00:39:08.158657 ==
4455 00:39:08.161511 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 00:39:08.168304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 00:39:08.168412 ==
4458 00:39:08.168504 RX Vref Scan: 0
4459 00:39:08.168591
4460 00:39:08.171672 RX Vref 0 -> 0, step: 1
4461 00:39:08.171772
4462 00:39:08.174848 RX Delay -230 -> 252, step: 16
4463 00:39:08.178291 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4464 00:39:08.181916 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4465 00:39:08.185073 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4466 00:39:08.191695 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4467 00:39:08.195983 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4468 00:39:08.199137 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4469 00:39:08.200957 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4470 00:39:08.207680 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4471 00:39:08.210920 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4472 00:39:08.214614 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4473 00:39:08.218009 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4474 00:39:08.224240 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4475 00:39:08.227884 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4476 00:39:08.230755 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4477 00:39:08.234371 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4478 00:39:08.240447 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4479 00:39:08.240552 ==
4480 00:39:08.243896 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 00:39:08.247076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 00:39:08.247179 ==
4483 00:39:08.247267 DQS Delay:
4484 00:39:08.250501 DQS0 = 0, DQS1 = 0
4485 00:39:08.250602 DQM Delay:
4486 00:39:08.253897 DQM0 = 43, DQM1 = 38
4487 00:39:08.254000 DQ Delay:
4488 00:39:08.257250 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4489 00:39:08.260050 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4490 00:39:08.263609 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4491 00:39:08.267278 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4492 00:39:08.267382
4493 00:39:08.267469
4494 00:39:08.267552 ==
4495 00:39:08.270020 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 00:39:08.273783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 00:39:08.276890 ==
4498 00:39:08.276991
4499 00:39:08.277080
4500 00:39:08.277164 TX Vref Scan disable
4501 00:39:08.280268 == TX Byte 0 ==
4502 00:39:08.283418 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4503 00:39:08.289667 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4504 00:39:08.289775 == TX Byte 1 ==
4505 00:39:08.293420 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 00:39:08.299820 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 00:39:08.299936 ==
4508 00:39:08.302991 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 00:39:08.306461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 00:39:08.306566 ==
4511 00:39:08.306656
4512 00:39:08.306742
4513 00:39:08.309552 TX Vref Scan disable
4514 00:39:08.312973 == TX Byte 0 ==
4515 00:39:08.316581 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 00:39:08.319733 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 00:39:08.323029 == TX Byte 1 ==
4518 00:39:08.326122 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 00:39:08.329247 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 00:39:08.329386
4521 00:39:08.332725 [DATLAT]
4522 00:39:08.332830 Freq=600, CH1 RK0
4523 00:39:08.332918
4524 00:39:08.336171 DATLAT Default: 0x9
4525 00:39:08.336271 0, 0xFFFF, sum = 0
4526 00:39:08.339447 1, 0xFFFF, sum = 0
4527 00:39:08.339549 2, 0xFFFF, sum = 0
4528 00:39:08.342599 3, 0xFFFF, sum = 0
4529 00:39:08.342702 4, 0xFFFF, sum = 0
4530 00:39:08.345896 5, 0xFFFF, sum = 0
4531 00:39:08.345996 6, 0xFFFF, sum = 0
4532 00:39:08.349185 7, 0xFFFF, sum = 0
4533 00:39:08.349321 8, 0x0, sum = 1
4534 00:39:08.352529 9, 0x0, sum = 2
4535 00:39:08.352631 10, 0x0, sum = 3
4536 00:39:08.355575 11, 0x0, sum = 4
4537 00:39:08.355677 best_step = 9
4538 00:39:08.355764
4539 00:39:08.355848 ==
4540 00:39:08.359125 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 00:39:08.362263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 00:39:08.365605 ==
4543 00:39:08.365707 RX Vref Scan: 1
4544 00:39:08.365794
4545 00:39:08.368851 RX Vref 0 -> 0, step: 1
4546 00:39:08.368951
4547 00:39:08.372519 RX Delay -179 -> 252, step: 8
4548 00:39:08.372620
4549 00:39:08.376164 Set Vref, RX VrefLevel [Byte0]: 53
4550 00:39:08.378476 [Byte1]: 49
4551 00:39:08.378579
4552 00:39:08.382020 Final RX Vref Byte 0 = 53 to rank0
4553 00:39:08.385279 Final RX Vref Byte 1 = 49 to rank0
4554 00:39:08.389032 Final RX Vref Byte 0 = 53 to rank1
4555 00:39:08.392239 Final RX Vref Byte 1 = 49 to rank1==
4556 00:39:08.395450 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 00:39:08.398394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 00:39:08.398504 ==
4559 00:39:08.401638 DQS Delay:
4560 00:39:08.401743 DQS0 = 0, DQS1 = 0
4561 00:39:08.401835 DQM Delay:
4562 00:39:08.405293 DQM0 = 41, DQM1 = 34
4563 00:39:08.405412 DQ Delay:
4564 00:39:08.408486 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4565 00:39:08.411428 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4566 00:39:08.415605 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4567 00:39:08.418393 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4568 00:39:08.418491
4569 00:39:08.418559
4570 00:39:08.428717 [DQSOSCAuto] RK0, (LSB)MR18= 0x3851, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4571 00:39:08.431723 CH1 RK0: MR19=808, MR18=3851
4572 00:39:08.434538 CH1_RK0: MR19=0x808, MR18=0x3851, DQSOSC=394, MR23=63, INC=168, DEC=112
4573 00:39:08.434622
4574 00:39:08.438174 ----->DramcWriteLeveling(PI) begin...
4575 00:39:08.441430 ==
4576 00:39:08.444789 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 00:39:08.447937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 00:39:08.448020 ==
4579 00:39:08.451061 Write leveling (Byte 0): 30 => 30
4580 00:39:08.454498 Write leveling (Byte 1): 29 => 29
4581 00:39:08.458545 DramcWriteLeveling(PI) end<-----
4582 00:39:08.458632
4583 00:39:08.458696 ==
4584 00:39:08.460980 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 00:39:08.464385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 00:39:08.464473 ==
4587 00:39:08.467435 [Gating] SW mode calibration
4588 00:39:08.474815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 00:39:08.481085 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 00:39:08.484190 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 00:39:08.487857 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 00:39:08.493948 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4593 00:39:08.497209 0 9 12 | B1->B0 | 2f2f 2929 | 0 1 | (0 0) (1 0)
4594 00:39:08.501168 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4595 00:39:08.507750 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 00:39:08.510560 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 00:39:08.513925 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 00:39:08.520552 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 00:39:08.524088 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 00:39:08.526887 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 00:39:08.534303 0 10 12 | B1->B0 | 3232 4545 | 1 0 | (0 0) (0 0)
4602 00:39:08.537177 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 00:39:08.540239 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 00:39:08.546658 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 00:39:08.550067 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 00:39:08.553477 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 00:39:08.559767 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 00:39:08.562833 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 00:39:08.566350 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4610 00:39:08.572679 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 00:39:08.576950 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 00:39:08.579924 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 00:39:08.586000 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 00:39:08.589702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 00:39:08.592609 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:39:08.599228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:39:08.602551 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 00:39:08.605872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:39:08.612117 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:39:08.615352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:39:08.618881 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:39:08.625464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:39:08.628896 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:39:08.632460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4625 00:39:08.638691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4626 00:39:08.642632 Total UI for P1: 0, mck2ui 16
4627 00:39:08.646170 best dqsien dly found for B0: ( 0, 13, 8)
4628 00:39:08.649442 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 00:39:08.651529 Total UI for P1: 0, mck2ui 16
4630 00:39:08.654818 best dqsien dly found for B1: ( 0, 13, 12)
4631 00:39:08.658431 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4632 00:39:08.661748 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4633 00:39:08.661834
4634 00:39:08.664857 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4635 00:39:08.668345 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4636 00:39:08.671660 [Gating] SW calibration Done
4637 00:39:08.671743 ==
4638 00:39:08.674564 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 00:39:08.681438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 00:39:08.681555 ==
4641 00:39:08.681658 RX Vref Scan: 0
4642 00:39:08.681722
4643 00:39:08.684987 RX Vref 0 -> 0, step: 1
4644 00:39:08.685068
4645 00:39:08.689254 RX Delay -230 -> 252, step: 16
4646 00:39:08.691628 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4647 00:39:08.694945 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4648 00:39:08.701758 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4649 00:39:08.704757 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4650 00:39:08.708407 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4651 00:39:08.711371 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4652 00:39:08.714533 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4653 00:39:08.721405 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4654 00:39:08.724681 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4655 00:39:08.728221 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4656 00:39:08.730968 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4657 00:39:08.737577 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4658 00:39:08.741104 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4659 00:39:08.743929 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4660 00:39:08.747414 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4661 00:39:08.753851 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4662 00:39:08.753956 ==
4663 00:39:08.757392 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 00:39:08.760269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 00:39:08.760361 ==
4666 00:39:08.760442 DQS Delay:
4667 00:39:08.763896 DQS0 = 0, DQS1 = 0
4668 00:39:08.764025 DQM Delay:
4669 00:39:08.767042 DQM0 = 42, DQM1 = 38
4670 00:39:08.767127 DQ Delay:
4671 00:39:08.770724 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4672 00:39:08.773588 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4673 00:39:08.777114 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4674 00:39:08.780739 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4675 00:39:08.780865
4676 00:39:08.780932
4677 00:39:08.780992 ==
4678 00:39:08.783360 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 00:39:08.786733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 00:39:08.790162 ==
4681 00:39:08.790245
4682 00:39:08.790309
4683 00:39:08.790368 TX Vref Scan disable
4684 00:39:08.793615 == TX Byte 0 ==
4685 00:39:08.796957 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4686 00:39:08.799891 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4687 00:39:08.803282 == TX Byte 1 ==
4688 00:39:08.806606 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4689 00:39:08.813030 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4690 00:39:08.813117 ==
4691 00:39:08.816257 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 00:39:08.819502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 00:39:08.819585 ==
4694 00:39:08.819650
4695 00:39:08.819709
4696 00:39:08.822917 TX Vref Scan disable
4697 00:39:08.826095 == TX Byte 0 ==
4698 00:39:08.829946 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4699 00:39:08.833053 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4700 00:39:08.836311 == TX Byte 1 ==
4701 00:39:08.839664 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4702 00:39:08.842725 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4703 00:39:08.842807
4704 00:39:08.842871 [DATLAT]
4705 00:39:08.846574 Freq=600, CH1 RK1
4706 00:39:08.846660
4707 00:39:08.849668 DATLAT Default: 0x9
4708 00:39:08.849750 0, 0xFFFF, sum = 0
4709 00:39:08.852650 1, 0xFFFF, sum = 0
4710 00:39:08.852733 2, 0xFFFF, sum = 0
4711 00:39:08.856198 3, 0xFFFF, sum = 0
4712 00:39:08.856281 4, 0xFFFF, sum = 0
4713 00:39:08.858851 5, 0xFFFF, sum = 0
4714 00:39:08.858934 6, 0xFFFF, sum = 0
4715 00:39:08.862393 7, 0xFFFF, sum = 0
4716 00:39:08.862476 8, 0x0, sum = 1
4717 00:39:08.865543 9, 0x0, sum = 2
4718 00:39:08.865628 10, 0x0, sum = 3
4719 00:39:08.868835 11, 0x0, sum = 4
4720 00:39:08.868920 best_step = 9
4721 00:39:08.868984
4722 00:39:08.869044 ==
4723 00:39:08.872332 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 00:39:08.875661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 00:39:08.875751 ==
4726 00:39:08.878807 RX Vref Scan: 0
4727 00:39:08.878891
4728 00:39:08.882250 RX Vref 0 -> 0, step: 1
4729 00:39:08.882335
4730 00:39:08.882400 RX Delay -179 -> 252, step: 8
4731 00:39:08.890326 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4732 00:39:08.893275 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4733 00:39:08.896572 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4734 00:39:08.899985 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4735 00:39:08.906652 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4736 00:39:08.909787 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4737 00:39:08.913159 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4738 00:39:08.916336 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4739 00:39:08.923157 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4740 00:39:08.926396 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4741 00:39:08.929560 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4742 00:39:08.933164 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4743 00:39:08.939837 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4744 00:39:08.942792 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4745 00:39:08.946703 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4746 00:39:08.949410 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4747 00:39:08.949590 ==
4748 00:39:08.952448 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 00:39:08.959555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 00:39:08.959779 ==
4751 00:39:08.959969 DQS Delay:
4752 00:39:08.962781 DQS0 = 0, DQS1 = 0
4753 00:39:08.962951 DQM Delay:
4754 00:39:08.965802 DQM0 = 38, DQM1 = 34
4755 00:39:08.965988 DQ Delay:
4756 00:39:08.969106 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4757 00:39:08.973512 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4758 00:39:08.975712 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4759 00:39:08.978722 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4760 00:39:08.978925
4761 00:39:08.979062
4762 00:39:08.985380 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f64, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
4763 00:39:08.988969 CH1 RK1: MR19=808, MR18=3F64
4764 00:39:08.995328 CH1_RK1: MR19=0x808, MR18=0x3F64, DQSOSC=391, MR23=63, INC=171, DEC=114
4765 00:39:08.998472 [RxdqsGatingPostProcess] freq 600
4766 00:39:09.005075 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 00:39:09.008961 Pre-setting of DQS Precalculation
4768 00:39:09.011995 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 00:39:09.018616 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 00:39:09.025129 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 00:39:09.025231
4772 00:39:09.025306
4773 00:39:09.028209 [Calibration Summary] 1200 Mbps
4774 00:39:09.031423 CH 0, Rank 0
4775 00:39:09.031510 SW Impedance : PASS
4776 00:39:09.034912 DUTY Scan : NO K
4777 00:39:09.038044 ZQ Calibration : PASS
4778 00:39:09.038128 Jitter Meter : NO K
4779 00:39:09.041375 CBT Training : PASS
4780 00:39:09.044643 Write leveling : PASS
4781 00:39:09.044728 RX DQS gating : PASS
4782 00:39:09.047958 RX DQ/DQS(RDDQC) : PASS
4783 00:39:09.051381 TX DQ/DQS : PASS
4784 00:39:09.051468 RX DATLAT : PASS
4785 00:39:09.054814 RX DQ/DQS(Engine): PASS
4786 00:39:09.058270 TX OE : NO K
4787 00:39:09.058357 All Pass.
4788 00:39:09.058423
4789 00:39:09.058484 CH 0, Rank 1
4790 00:39:09.061117 SW Impedance : PASS
4791 00:39:09.064407 DUTY Scan : NO K
4792 00:39:09.064493 ZQ Calibration : PASS
4793 00:39:09.067822 Jitter Meter : NO K
4794 00:39:09.067929 CBT Training : PASS
4795 00:39:09.071179 Write leveling : PASS
4796 00:39:09.074710 RX DQS gating : PASS
4797 00:39:09.074799 RX DQ/DQS(RDDQC) : PASS
4798 00:39:09.077940 TX DQ/DQS : PASS
4799 00:39:09.081041 RX DATLAT : PASS
4800 00:39:09.081124 RX DQ/DQS(Engine): PASS
4801 00:39:09.084573 TX OE : NO K
4802 00:39:09.084663 All Pass.
4803 00:39:09.084730
4804 00:39:09.087889 CH 1, Rank 0
4805 00:39:09.088073 SW Impedance : PASS
4806 00:39:09.091326 DUTY Scan : NO K
4807 00:39:09.094593 ZQ Calibration : PASS
4808 00:39:09.094743 Jitter Meter : NO K
4809 00:39:09.097780 CBT Training : PASS
4810 00:39:09.100895 Write leveling : PASS
4811 00:39:09.101003 RX DQS gating : PASS
4812 00:39:09.104749 RX DQ/DQS(RDDQC) : PASS
4813 00:39:09.107817 TX DQ/DQS : PASS
4814 00:39:09.107932 RX DATLAT : PASS
4815 00:39:09.110752 RX DQ/DQS(Engine): PASS
4816 00:39:09.114129 TX OE : NO K
4817 00:39:09.114220 All Pass.
4818 00:39:09.114306
4819 00:39:09.114387 CH 1, Rank 1
4820 00:39:09.117497 SW Impedance : PASS
4821 00:39:09.120890 DUTY Scan : NO K
4822 00:39:09.120978 ZQ Calibration : PASS
4823 00:39:09.124308 Jitter Meter : NO K
4824 00:39:09.127426 CBT Training : PASS
4825 00:39:09.127535 Write leveling : PASS
4826 00:39:09.130930 RX DQS gating : PASS
4827 00:39:09.133942 RX DQ/DQS(RDDQC) : PASS
4828 00:39:09.134058 TX DQ/DQS : PASS
4829 00:39:09.137481 RX DATLAT : PASS
4830 00:39:09.140681 RX DQ/DQS(Engine): PASS
4831 00:39:09.140765 TX OE : NO K
4832 00:39:09.140851 All Pass.
4833 00:39:09.143695
4834 00:39:09.143780 DramC Write-DBI off
4835 00:39:09.147079 PER_BANK_REFRESH: Hybrid Mode
4836 00:39:09.147164 TX_TRACKING: ON
4837 00:39:09.156785 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 00:39:09.160152 [FAST_K] Save calibration result to emmc
4839 00:39:09.163764 dramc_set_vcore_voltage set vcore to 662500
4840 00:39:09.166447 Read voltage for 933, 3
4841 00:39:09.166531 Vio18 = 0
4842 00:39:09.170099 Vcore = 662500
4843 00:39:09.170180 Vdram = 0
4844 00:39:09.170245 Vddq = 0
4845 00:39:09.170306 Vmddr = 0
4846 00:39:09.176368 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 00:39:09.182974 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 00:39:09.183057 MEM_TYPE=3, freq_sel=17
4849 00:39:09.186265 sv_algorithm_assistance_LP4_1600
4850 00:39:09.189578 ============ PULL DRAM RESETB DOWN ============
4851 00:39:09.196495 ========== PULL DRAM RESETB DOWN end =========
4852 00:39:09.199596 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 00:39:09.203368 ===================================
4854 00:39:09.206353 LPDDR4 DRAM CONFIGURATION
4855 00:39:09.209556 ===================================
4856 00:39:09.209638 EX_ROW_EN[0] = 0x0
4857 00:39:09.212679 EX_ROW_EN[1] = 0x0
4858 00:39:09.216013 LP4Y_EN = 0x0
4859 00:39:09.216094 WORK_FSP = 0x0
4860 00:39:09.219744 WL = 0x3
4861 00:39:09.219825 RL = 0x3
4862 00:39:09.223033 BL = 0x2
4863 00:39:09.223117 RPST = 0x0
4864 00:39:09.226193 RD_PRE = 0x0
4865 00:39:09.226331 WR_PRE = 0x1
4866 00:39:09.229301 WR_PST = 0x0
4867 00:39:09.229453 DBI_WR = 0x0
4868 00:39:09.233165 DBI_RD = 0x0
4869 00:39:09.233340 OTF = 0x1
4870 00:39:09.236121 ===================================
4871 00:39:09.239674 ===================================
4872 00:39:09.242589 ANA top config
4873 00:39:09.245854 ===================================
4874 00:39:09.245969 DLL_ASYNC_EN = 0
4875 00:39:09.249082 ALL_SLAVE_EN = 1
4876 00:39:09.252865 NEW_RANK_MODE = 1
4877 00:39:09.256210 DLL_IDLE_MODE = 1
4878 00:39:09.259150 LP45_APHY_COMB_EN = 1
4879 00:39:09.259265 TX_ODT_DIS = 1
4880 00:39:09.262645 NEW_8X_MODE = 1
4881 00:39:09.265983 ===================================
4882 00:39:09.268823 ===================================
4883 00:39:09.273195 data_rate = 1866
4884 00:39:09.275668 CKR = 1
4885 00:39:09.279505 DQ_P2S_RATIO = 8
4886 00:39:09.282386 ===================================
4887 00:39:09.286137 CA_P2S_RATIO = 8
4888 00:39:09.286229 DQ_CA_OPEN = 0
4889 00:39:09.288851 DQ_SEMI_OPEN = 0
4890 00:39:09.292494 CA_SEMI_OPEN = 0
4891 00:39:09.295439 CA_FULL_RATE = 0
4892 00:39:09.299208 DQ_CKDIV4_EN = 1
4893 00:39:09.299291 CA_CKDIV4_EN = 1
4894 00:39:09.302286 CA_PREDIV_EN = 0
4895 00:39:09.305411 PH8_DLY = 0
4896 00:39:09.308920 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 00:39:09.312009 DQ_AAMCK_DIV = 4
4898 00:39:09.315279 CA_AAMCK_DIV = 4
4899 00:39:09.315395 CA_ADMCK_DIV = 4
4900 00:39:09.318958 DQ_TRACK_CA_EN = 0
4901 00:39:09.322057 CA_PICK = 933
4902 00:39:09.325661 CA_MCKIO = 933
4903 00:39:09.329111 MCKIO_SEMI = 0
4904 00:39:09.332020 PLL_FREQ = 3732
4905 00:39:09.335113 DQ_UI_PI_RATIO = 32
4906 00:39:09.338943 CA_UI_PI_RATIO = 0
4907 00:39:09.341835 ===================================
4908 00:39:09.345244 ===================================
4909 00:39:09.345383 memory_type:LPDDR4
4910 00:39:09.348415 GP_NUM : 10
4911 00:39:09.351490 SRAM_EN : 1
4912 00:39:09.351577 MD32_EN : 0
4913 00:39:09.354901 ===================================
4914 00:39:09.358447 [ANA_INIT] >>>>>>>>>>>>>>
4915 00:39:09.361590 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 00:39:09.364957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 00:39:09.368098 ===================================
4918 00:39:09.371341 data_rate = 1866,PCW = 0X8f00
4919 00:39:09.375012 ===================================
4920 00:39:09.378208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 00:39:09.381499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 00:39:09.388293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 00:39:09.391245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 00:39:09.394495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 00:39:09.397866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 00:39:09.401393 [ANA_INIT] flow start
4927 00:39:09.404299 [ANA_INIT] PLL >>>>>>>>
4928 00:39:09.404398 [ANA_INIT] PLL <<<<<<<<
4929 00:39:09.407481 [ANA_INIT] MIDPI >>>>>>>>
4930 00:39:09.411280 [ANA_INIT] MIDPI <<<<<<<<
4931 00:39:09.414402 [ANA_INIT] DLL >>>>>>>>
4932 00:39:09.414498 [ANA_INIT] flow end
4933 00:39:09.418071 ============ LP4 DIFF to SE enter ============
4934 00:39:09.424133 ============ LP4 DIFF to SE exit ============
4935 00:39:09.424236 [ANA_INIT] <<<<<<<<<<<<<
4936 00:39:09.427380 [Flow] Enable top DCM control >>>>>
4937 00:39:09.430748 [Flow] Enable top DCM control <<<<<
4938 00:39:09.434021 Enable DLL master slave shuffle
4939 00:39:09.440752 ==============================================================
4940 00:39:09.443758 Gating Mode config
4941 00:39:09.447361 ==============================================================
4942 00:39:09.450224 Config description:
4943 00:39:09.460552 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 00:39:09.466763 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 00:39:09.470358 SELPH_MODE 0: By rank 1: By Phase
4946 00:39:09.477004 ==============================================================
4947 00:39:09.479953 GAT_TRACK_EN = 1
4948 00:39:09.483206 RX_GATING_MODE = 2
4949 00:39:09.487128 RX_GATING_TRACK_MODE = 2
4950 00:39:09.487257 SELPH_MODE = 1
4951 00:39:09.490295 PICG_EARLY_EN = 1
4952 00:39:09.493575 VALID_LAT_VALUE = 1
4953 00:39:09.500381 ==============================================================
4954 00:39:09.503592 Enter into Gating configuration >>>>
4955 00:39:09.506439 Exit from Gating configuration <<<<
4956 00:39:09.509760 Enter into DVFS_PRE_config >>>>>
4957 00:39:09.519494 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 00:39:09.523062 Exit from DVFS_PRE_config <<<<<
4959 00:39:09.526428 Enter into PICG configuration >>>>
4960 00:39:09.529833 Exit from PICG configuration <<<<
4961 00:39:09.532988 [RX_INPUT] configuration >>>>>
4962 00:39:09.536442 [RX_INPUT] configuration <<<<<
4963 00:39:09.539171 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 00:39:09.545785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 00:39:09.552974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 00:39:09.559287 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 00:39:09.565757 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 00:39:09.572169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 00:39:09.575650 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 00:39:09.578632 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 00:39:09.581942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 00:39:09.588775 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 00:39:09.591944 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 00:39:09.595047 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 00:39:09.598497 ===================================
4976 00:39:09.601752 LPDDR4 DRAM CONFIGURATION
4977 00:39:09.605123 ===================================
4978 00:39:09.608613 EX_ROW_EN[0] = 0x0
4979 00:39:09.608699 EX_ROW_EN[1] = 0x0
4980 00:39:09.611592 LP4Y_EN = 0x0
4981 00:39:09.611676 WORK_FSP = 0x0
4982 00:39:09.615007 WL = 0x3
4983 00:39:09.615106 RL = 0x3
4984 00:39:09.618430 BL = 0x2
4985 00:39:09.618521 RPST = 0x0
4986 00:39:09.621870 RD_PRE = 0x0
4987 00:39:09.621968 WR_PRE = 0x1
4988 00:39:09.624579 WR_PST = 0x0
4989 00:39:09.624660 DBI_WR = 0x0
4990 00:39:09.628006 DBI_RD = 0x0
4991 00:39:09.628090 OTF = 0x1
4992 00:39:09.631385 ===================================
4993 00:39:09.638077 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 00:39:09.641322 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 00:39:09.645091 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 00:39:09.648589 ===================================
4997 00:39:09.651530 LPDDR4 DRAM CONFIGURATION
4998 00:39:09.654541 ===================================
4999 00:39:09.657690 EX_ROW_EN[0] = 0x10
5000 00:39:09.657770 EX_ROW_EN[1] = 0x0
5001 00:39:09.661456 LP4Y_EN = 0x0
5002 00:39:09.661561 WORK_FSP = 0x0
5003 00:39:09.664610 WL = 0x3
5004 00:39:09.664712 RL = 0x3
5005 00:39:09.667887 BL = 0x2
5006 00:39:09.667966 RPST = 0x0
5007 00:39:09.671153 RD_PRE = 0x0
5008 00:39:09.671232 WR_PRE = 0x1
5009 00:39:09.674554 WR_PST = 0x0
5010 00:39:09.674633 DBI_WR = 0x0
5011 00:39:09.677600 DBI_RD = 0x0
5012 00:39:09.677679 OTF = 0x1
5013 00:39:09.681249 ===================================
5014 00:39:09.687590 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 00:39:09.692412 nWR fixed to 30
5016 00:39:09.696063 [ModeRegInit_LP4] CH0 RK0
5017 00:39:09.696562 [ModeRegInit_LP4] CH0 RK1
5018 00:39:09.699126 [ModeRegInit_LP4] CH1 RK0
5019 00:39:09.702387 [ModeRegInit_LP4] CH1 RK1
5020 00:39:09.702729 match AC timing 9
5021 00:39:09.708915 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 00:39:09.712447 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 00:39:09.715949 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 00:39:09.722411 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 00:39:09.725180 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 00:39:09.725638 ==
5027 00:39:09.728661 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 00:39:09.732395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 00:39:09.735224 ==
5030 00:39:09.738727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 00:39:09.745047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5032 00:39:09.748425 [CA 0] Center 38 (7~69) winsize 63
5033 00:39:09.752013 [CA 1] Center 37 (7~68) winsize 62
5034 00:39:09.755162 [CA 2] Center 34 (4~65) winsize 62
5035 00:39:09.758401 [CA 3] Center 34 (4~65) winsize 62
5036 00:39:09.761898 [CA 4] Center 33 (2~64) winsize 63
5037 00:39:09.765098 [CA 5] Center 32 (2~63) winsize 62
5038 00:39:09.765517
5039 00:39:09.768367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5040 00:39:09.768743
5041 00:39:09.771377 [CATrainingPosCal] consider 1 rank data
5042 00:39:09.774684 u2DelayCellTimex100 = 270/100 ps
5043 00:39:09.778271 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5044 00:39:09.781524 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 00:39:09.784918 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5046 00:39:09.791428 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5047 00:39:09.794622 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5048 00:39:09.798664 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5049 00:39:09.799082
5050 00:39:09.801687 CA PerBit enable=1, Macro0, CA PI delay=32
5051 00:39:09.802084
5052 00:39:09.804411 [CBTSetCACLKResult] CA Dly = 32
5053 00:39:09.804685 CS Dly: 6 (0~37)
5054 00:39:09.804922 ==
5055 00:39:09.807768 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 00:39:09.814313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 00:39:09.814565 ==
5058 00:39:09.817452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 00:39:09.824370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5060 00:39:09.827798 [CA 0] Center 38 (8~69) winsize 62
5061 00:39:09.830939 [CA 1] Center 38 (8~68) winsize 61
5062 00:39:09.834154 [CA 2] Center 35 (5~65) winsize 61
5063 00:39:09.837550 [CA 3] Center 34 (4~65) winsize 62
5064 00:39:09.841113 [CA 4] Center 33 (2~64) winsize 63
5065 00:39:09.844163 [CA 5] Center 32 (2~63) winsize 62
5066 00:39:09.844280
5067 00:39:09.847558 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5068 00:39:09.847705
5069 00:39:09.850498 [CATrainingPosCal] consider 2 rank data
5070 00:39:09.853973 u2DelayCellTimex100 = 270/100 ps
5071 00:39:09.857300 CA0 delay=38 (8~69),Diff = 6 PI (37 cell)
5072 00:39:09.864069 CA1 delay=38 (8~68),Diff = 6 PI (37 cell)
5073 00:39:09.867368 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5074 00:39:09.870293 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5075 00:39:09.873632 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5076 00:39:09.876997 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5077 00:39:09.877108
5078 00:39:09.880099 CA PerBit enable=1, Macro0, CA PI delay=32
5079 00:39:09.880202
5080 00:39:09.883694 [CBTSetCACLKResult] CA Dly = 32
5081 00:39:09.887421 CS Dly: 7 (0~39)
5082 00:39:09.887578
5083 00:39:09.890236 ----->DramcWriteLeveling(PI) begin...
5084 00:39:09.890358 ==
5085 00:39:09.893712 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 00:39:09.896435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 00:39:09.896580 ==
5088 00:39:09.900143 Write leveling (Byte 0): 33 => 33
5089 00:39:09.903468 Write leveling (Byte 1): 27 => 27
5090 00:39:09.906757 DramcWriteLeveling(PI) end<-----
5091 00:39:09.906844
5092 00:39:09.906909 ==
5093 00:39:09.909848 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 00:39:09.913219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 00:39:09.913330 ==
5096 00:39:09.916676 [Gating] SW mode calibration
5097 00:39:09.923203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 00:39:09.930151 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 00:39:09.932970 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5100 00:39:09.936427 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 00:39:09.942910 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 00:39:09.946490 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 00:39:09.952778 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 00:39:09.956270 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 00:39:09.959515 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5106 00:39:09.963069 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5107 00:39:09.969234 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5108 00:39:09.973001 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5109 00:39:09.975936 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 00:39:09.982982 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 00:39:09.985829 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 00:39:09.989171 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 00:39:09.996218 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 00:39:09.998983 0 15 28 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
5115 00:39:10.002655 1 0 0 | B1->B0 | 3838 4545 | 0 0 | (0 0) (1 1)
5116 00:39:10.008803 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 00:39:10.012768 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 00:39:10.015449 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 00:39:10.022374 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 00:39:10.025899 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 00:39:10.028949 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 00:39:10.035469 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 00:39:10.038793 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5124 00:39:10.041955 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 00:39:10.048664 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 00:39:10.051790 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 00:39:10.055180 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:39:10.061698 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:39:10.065471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:39:10.068289 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:39:10.074966 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:39:10.078399 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:39:10.081754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:39:10.088430 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:39:10.091645 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:39:10.094474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:39:10.101576 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 00:39:10.104594 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5139 00:39:10.108067 Total UI for P1: 0, mck2ui 16
5140 00:39:10.111669 best dqsien dly found for B0: ( 1, 2, 24)
5141 00:39:10.115045 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5142 00:39:10.121205 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 00:39:10.124633 Total UI for P1: 0, mck2ui 16
5144 00:39:10.128041 best dqsien dly found for B1: ( 1, 2, 30)
5145 00:39:10.131538 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5146 00:39:10.134683 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5147 00:39:10.135077
5148 00:39:10.138040 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5149 00:39:10.141003 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5150 00:39:10.144726 [Gating] SW calibration Done
5151 00:39:10.145126 ==
5152 00:39:10.148371 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 00:39:10.151101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 00:39:10.151647 ==
5155 00:39:10.154137 RX Vref Scan: 0
5156 00:39:10.154516
5157 00:39:10.157389 RX Vref 0 -> 0, step: 1
5158 00:39:10.157777
5159 00:39:10.158077 RX Delay -80 -> 252, step: 8
5160 00:39:10.164110 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5161 00:39:10.167543 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5162 00:39:10.170609 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5163 00:39:10.174551 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5164 00:39:10.177120 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5165 00:39:10.180535 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5166 00:39:10.187050 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5167 00:39:10.190814 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5168 00:39:10.193671 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5169 00:39:10.197105 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5170 00:39:10.200604 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5171 00:39:10.207043 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5172 00:39:10.210653 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5173 00:39:10.213945 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5174 00:39:10.216861 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5175 00:39:10.220272 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5176 00:39:10.224041 ==
5177 00:39:10.226495 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 00:39:10.230042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 00:39:10.230426 ==
5180 00:39:10.230739 DQS Delay:
5181 00:39:10.233598 DQS0 = 0, DQS1 = 0
5182 00:39:10.233976 DQM Delay:
5183 00:39:10.236607 DQM0 = 101, DQM1 = 87
5184 00:39:10.237074 DQ Delay:
5185 00:39:10.239937 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =99
5186 00:39:10.243079 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =111
5187 00:39:10.246471 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5188 00:39:10.250237 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5189 00:39:10.250637
5190 00:39:10.251038
5191 00:39:10.251417 ==
5192 00:39:10.253482 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 00:39:10.256515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 00:39:10.259796 ==
5195 00:39:10.260272
5196 00:39:10.260574
5197 00:39:10.260852 TX Vref Scan disable
5198 00:39:10.263335 == TX Byte 0 ==
5199 00:39:10.266616 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5200 00:39:10.269816 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5201 00:39:10.272774 == TX Byte 1 ==
5202 00:39:10.276254 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5203 00:39:10.279803 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5204 00:39:10.282978 ==
5205 00:39:10.285824 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 00:39:10.289373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 00:39:10.289782 ==
5208 00:39:10.290101
5209 00:39:10.290397
5210 00:39:10.292689 TX Vref Scan disable
5211 00:39:10.293097 == TX Byte 0 ==
5212 00:39:10.299221 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5213 00:39:10.302417 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5214 00:39:10.303006 == TX Byte 1 ==
5215 00:39:10.309239 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5216 00:39:10.312775 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5217 00:39:10.313435
5218 00:39:10.313989 [DATLAT]
5219 00:39:10.315783 Freq=933, CH0 RK0
5220 00:39:10.316376
5221 00:39:10.316927 DATLAT Default: 0xd
5222 00:39:10.319039 0, 0xFFFF, sum = 0
5223 00:39:10.319445 1, 0xFFFF, sum = 0
5224 00:39:10.322231 2, 0xFFFF, sum = 0
5225 00:39:10.325562 3, 0xFFFF, sum = 0
5226 00:39:10.325938 4, 0xFFFF, sum = 0
5227 00:39:10.329427 5, 0xFFFF, sum = 0
5228 00:39:10.329803 6, 0xFFFF, sum = 0
5229 00:39:10.332213 7, 0xFFFF, sum = 0
5230 00:39:10.332609 8, 0xFFFF, sum = 0
5231 00:39:10.335783 9, 0xFFFF, sum = 0
5232 00:39:10.336098 10, 0x0, sum = 1
5233 00:39:10.339124 11, 0x0, sum = 2
5234 00:39:10.339597 12, 0x0, sum = 3
5235 00:39:10.341884 13, 0x0, sum = 4
5236 00:39:10.342268 best_step = 11
5237 00:39:10.342598
5238 00:39:10.342874 ==
5239 00:39:10.345579 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 00:39:10.348955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 00:39:10.349472 ==
5242 00:39:10.352400 RX Vref Scan: 1
5243 00:39:10.352936
5244 00:39:10.356341 RX Vref 0 -> 0, step: 1
5245 00:39:10.356941
5246 00:39:10.357443 RX Delay -61 -> 252, step: 4
5247 00:39:10.357741
5248 00:39:10.358562 Set Vref, RX VrefLevel [Byte0]: 56
5249 00:39:10.361929 [Byte1]: 49
5250 00:39:10.366646
5251 00:39:10.367015 Final RX Vref Byte 0 = 56 to rank0
5252 00:39:10.370054 Final RX Vref Byte 1 = 49 to rank0
5253 00:39:10.373763 Final RX Vref Byte 0 = 56 to rank1
5254 00:39:10.377131 Final RX Vref Byte 1 = 49 to rank1==
5255 00:39:10.380270 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 00:39:10.386811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 00:39:10.387190 ==
5258 00:39:10.387489 DQS Delay:
5259 00:39:10.387773 DQS0 = 0, DQS1 = 0
5260 00:39:10.390171 DQM Delay:
5261 00:39:10.390665 DQM0 = 102, DQM1 = 89
5262 00:39:10.393473 DQ Delay:
5263 00:39:10.396430 DQ0 =102, DQ1 =102, DQ2 =98, DQ3 =98
5264 00:39:10.399630 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5265 00:39:10.402723 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5266 00:39:10.406215 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =98
5267 00:39:10.406597
5268 00:39:10.406899
5269 00:39:10.412893 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5270 00:39:10.416471 CH0 RK0: MR19=505, MR18=1E19
5271 00:39:10.422981 CH0_RK0: MR19=0x505, MR18=0x1E19, DQSOSC=412, MR23=63, INC=63, DEC=42
5272 00:39:10.423463
5273 00:39:10.426004 ----->DramcWriteLeveling(PI) begin...
5274 00:39:10.426570 ==
5275 00:39:10.429419 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 00:39:10.432558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 00:39:10.432931 ==
5278 00:39:10.435942 Write leveling (Byte 0): 31 => 31
5279 00:39:10.439317 Write leveling (Byte 1): 30 => 30
5280 00:39:10.442877 DramcWriteLeveling(PI) end<-----
5281 00:39:10.443267
5282 00:39:10.443710 ==
5283 00:39:10.446120 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 00:39:10.452921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 00:39:10.453523 ==
5286 00:39:10.453920 [Gating] SW mode calibration
5287 00:39:10.462699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5288 00:39:10.465614 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5289 00:39:10.469095 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5290 00:39:10.475875 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 00:39:10.479217 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 00:39:10.485440 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 00:39:10.488871 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 00:39:10.492168 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 00:39:10.498684 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5296 00:39:10.501808 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 1)
5297 00:39:10.505219 0 15 0 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
5298 00:39:10.511787 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 00:39:10.514957 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 00:39:10.518497 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 00:39:10.524779 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 00:39:10.528218 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 00:39:10.531051 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5304 00:39:10.537975 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (1 1)
5305 00:39:10.541331 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5306 00:39:10.544677 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 00:39:10.551206 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 00:39:10.554476 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 00:39:10.558109 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 00:39:10.564608 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 00:39:10.567788 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5312 00:39:10.571181 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5313 00:39:10.578346 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5314 00:39:10.580983 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 00:39:10.584118 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 00:39:10.590594 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 00:39:10.594702 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 00:39:10.597370 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 00:39:10.604078 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 00:39:10.607667 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:39:10.610720 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:39:10.616949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:39:10.620817 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:39:10.623776 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:39:10.630438 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:39:10.633798 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:39:10.636915 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5328 00:39:10.643727 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5329 00:39:10.644214 Total UI for P1: 0, mck2ui 16
5330 00:39:10.646806 best dqsien dly found for B0: ( 1, 2, 24)
5331 00:39:10.653701 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5332 00:39:10.656957 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 00:39:10.659973 Total UI for P1: 0, mck2ui 16
5334 00:39:10.663469 best dqsien dly found for B1: ( 1, 2, 30)
5335 00:39:10.666484 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5336 00:39:10.670162 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5337 00:39:10.670737
5338 00:39:10.672999 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5339 00:39:10.680861 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5340 00:39:10.681297 [Gating] SW calibration Done
5341 00:39:10.681623 ==
5342 00:39:10.683350 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 00:39:10.689772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 00:39:10.690271 ==
5345 00:39:10.690596 RX Vref Scan: 0
5346 00:39:10.690895
5347 00:39:10.693506 RX Vref 0 -> 0, step: 1
5348 00:39:10.694016
5349 00:39:10.696276 RX Delay -80 -> 252, step: 8
5350 00:39:10.699467 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5351 00:39:10.703498 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5352 00:39:10.706423 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5353 00:39:10.712845 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5354 00:39:10.716056 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5355 00:39:10.719835 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5356 00:39:10.722511 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5357 00:39:10.725757 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5358 00:39:10.729556 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5359 00:39:10.735769 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5360 00:39:10.739298 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5361 00:39:10.742590 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5362 00:39:10.745784 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5363 00:39:10.748783 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5364 00:39:10.755659 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5365 00:39:10.758913 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5366 00:39:10.759336 ==
5367 00:39:10.762228 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 00:39:10.765488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 00:39:10.766049 ==
5370 00:39:10.769005 DQS Delay:
5371 00:39:10.769441 DQS0 = 0, DQS1 = 0
5372 00:39:10.769772 DQM Delay:
5373 00:39:10.772459 DQM0 = 100, DQM1 = 88
5374 00:39:10.772871 DQ Delay:
5375 00:39:10.775383 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =95
5376 00:39:10.778914 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5377 00:39:10.782350 DQ8 =79, DQ9 =71, DQ10 =91, DQ11 =83
5378 00:39:10.785371 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5379 00:39:10.785788
5380 00:39:10.786116
5381 00:39:10.786421 ==
5382 00:39:10.788441 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 00:39:10.795624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 00:39:10.796132 ==
5385 00:39:10.796459
5386 00:39:10.796757
5387 00:39:10.797046 TX Vref Scan disable
5388 00:39:10.798618 == TX Byte 0 ==
5389 00:39:10.802084 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5390 00:39:10.808719 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5391 00:39:10.809145 == TX Byte 1 ==
5392 00:39:10.811640 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5393 00:39:10.818836 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5394 00:39:10.819298 ==
5395 00:39:10.821857 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 00:39:10.825221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 00:39:10.825685 ==
5398 00:39:10.826113
5399 00:39:10.826514
5400 00:39:10.828307 TX Vref Scan disable
5401 00:39:10.828729 == TX Byte 0 ==
5402 00:39:10.835059 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5403 00:39:10.838672 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5404 00:39:10.841731 == TX Byte 1 ==
5405 00:39:10.844966 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5406 00:39:10.848670 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5407 00:39:10.849188
5408 00:39:10.849687 [DATLAT]
5409 00:39:10.851658 Freq=933, CH0 RK1
5410 00:39:10.852183
5411 00:39:10.852590 DATLAT Default: 0xb
5412 00:39:10.854587 0, 0xFFFF, sum = 0
5413 00:39:10.858087 1, 0xFFFF, sum = 0
5414 00:39:10.858519 2, 0xFFFF, sum = 0
5415 00:39:10.861699 3, 0xFFFF, sum = 0
5416 00:39:10.862129 4, 0xFFFF, sum = 0
5417 00:39:10.865111 5, 0xFFFF, sum = 0
5418 00:39:10.865586 6, 0xFFFF, sum = 0
5419 00:39:10.867960 7, 0xFFFF, sum = 0
5420 00:39:10.868396 8, 0xFFFF, sum = 0
5421 00:39:10.871733 9, 0xFFFF, sum = 0
5422 00:39:10.872260 10, 0x0, sum = 1
5423 00:39:10.874430 11, 0x0, sum = 2
5424 00:39:10.874948 12, 0x0, sum = 3
5425 00:39:10.877879 13, 0x0, sum = 4
5426 00:39:10.878399 best_step = 11
5427 00:39:10.878822
5428 00:39:10.879225 ==
5429 00:39:10.881408 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 00:39:10.884680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 00:39:10.887752 ==
5432 00:39:10.888175 RX Vref Scan: 0
5433 00:39:10.888712
5434 00:39:10.890981 RX Vref 0 -> 0, step: 1
5435 00:39:10.891400
5436 00:39:10.893990 RX Delay -69 -> 252, step: 4
5437 00:39:10.897990 iDelay=195, Bit 0, Center 98 (15 ~ 182) 168
5438 00:39:10.900745 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5439 00:39:10.907581 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5440 00:39:10.910521 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5441 00:39:10.913816 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5442 00:39:10.917785 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5443 00:39:10.920786 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5444 00:39:10.923887 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5445 00:39:10.930647 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5446 00:39:10.933905 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5447 00:39:10.937431 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5448 00:39:10.940455 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5449 00:39:10.943849 iDelay=195, Bit 12, Center 98 (15 ~ 182) 168
5450 00:39:10.950127 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5451 00:39:10.953398 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5452 00:39:10.956869 iDelay=195, Bit 15, Center 98 (15 ~ 182) 168
5453 00:39:10.957319 ==
5454 00:39:10.960320 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 00:39:10.963380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 00:39:10.963802 ==
5457 00:39:10.966589 DQS Delay:
5458 00:39:10.967038 DQS0 = 0, DQS1 = 0
5459 00:39:10.969798 DQM Delay:
5460 00:39:10.970258 DQM0 = 100, DQM1 = 90
5461 00:39:10.973219 DQ Delay:
5462 00:39:10.976595 DQ0 =98, DQ1 =102, DQ2 =96, DQ3 =98
5463 00:39:10.979599 DQ4 =102, DQ5 =92, DQ6 =110, DQ7 =108
5464 00:39:10.983007 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =84
5465 00:39:10.986681 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5466 00:39:10.987120
5467 00:39:10.987452
5468 00:39:10.992652 [DQSOSCAuto] RK1, (LSB)MR18= 0x1815, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5469 00:39:10.996346 CH0 RK1: MR19=505, MR18=1815
5470 00:39:11.002673 CH0_RK1: MR19=0x505, MR18=0x1815, DQSOSC=414, MR23=63, INC=63, DEC=42
5471 00:39:11.005633 [RxdqsGatingPostProcess] freq 933
5472 00:39:11.009112 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5473 00:39:11.012632 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 00:39:11.015894 best DQS1 dly(2T, 0.5T) = (0, 10)
5475 00:39:11.019235 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 00:39:11.022137 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5477 00:39:11.025917 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 00:39:11.028937 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 00:39:11.032191 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 00:39:11.035322 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 00:39:11.038595 Pre-setting of DQS Precalculation
5482 00:39:11.045403 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5483 00:39:11.045562 ==
5484 00:39:11.048953 Dram Type= 6, Freq= 0, CH_1, rank 0
5485 00:39:11.051930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 00:39:11.052085 ==
5487 00:39:11.058875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5488 00:39:11.061837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5489 00:39:11.065504 [CA 0] Center 36 (6~67) winsize 62
5490 00:39:11.068816 [CA 1] Center 36 (6~67) winsize 62
5491 00:39:11.072603 [CA 2] Center 34 (4~65) winsize 62
5492 00:39:11.075747 [CA 3] Center 33 (3~64) winsize 62
5493 00:39:11.079374 [CA 4] Center 34 (4~64) winsize 61
5494 00:39:11.082343 [CA 5] Center 33 (3~64) winsize 62
5495 00:39:11.082559
5496 00:39:11.085859 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5497 00:39:11.086092
5498 00:39:11.089248 [CATrainingPosCal] consider 1 rank data
5499 00:39:11.092274 u2DelayCellTimex100 = 270/100 ps
5500 00:39:11.096064 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 00:39:11.102204 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 00:39:11.105522 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 00:39:11.108722 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5504 00:39:11.112070 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5505 00:39:11.115724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5506 00:39:11.116225
5507 00:39:11.118678 CA PerBit enable=1, Macro0, CA PI delay=33
5508 00:39:11.119111
5509 00:39:11.122061 [CBTSetCACLKResult] CA Dly = 33
5510 00:39:11.125698 CS Dly: 5 (0~36)
5511 00:39:11.126109 ==
5512 00:39:11.128489 Dram Type= 6, Freq= 0, CH_1, rank 1
5513 00:39:11.131697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 00:39:11.132127 ==
5515 00:39:11.138306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 00:39:11.142365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 00:39:11.146052 [CA 0] Center 36 (6~67) winsize 62
5518 00:39:11.148899 [CA 1] Center 36 (6~67) winsize 62
5519 00:39:11.152146 [CA 2] Center 34 (4~65) winsize 62
5520 00:39:11.155660 [CA 3] Center 33 (3~64) winsize 62
5521 00:39:11.158674 [CA 4] Center 33 (3~63) winsize 61
5522 00:39:11.162086 [CA 5] Center 33 (3~63) winsize 61
5523 00:39:11.162274
5524 00:39:11.165865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 00:39:11.166013
5526 00:39:11.168567 [CATrainingPosCal] consider 2 rank data
5527 00:39:11.171664 u2DelayCellTimex100 = 270/100 ps
5528 00:39:11.175274 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 00:39:11.181605 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 00:39:11.185187 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5531 00:39:11.188044 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 00:39:11.191560 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
5533 00:39:11.194638 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5534 00:39:11.194719
5535 00:39:11.198153 CA PerBit enable=1, Macro0, CA PI delay=33
5536 00:39:11.198233
5537 00:39:11.201841 [CBTSetCACLKResult] CA Dly = 33
5538 00:39:11.204995 CS Dly: 5 (0~37)
5539 00:39:11.205091
5540 00:39:11.208300 ----->DramcWriteLeveling(PI) begin...
5541 00:39:11.208402 ==
5542 00:39:11.211560 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 00:39:11.214647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 00:39:11.214727 ==
5545 00:39:11.218247 Write leveling (Byte 0): 25 => 25
5546 00:39:11.220911 Write leveling (Byte 1): 29 => 29
5547 00:39:11.224522 DramcWriteLeveling(PI) end<-----
5548 00:39:11.224601
5549 00:39:11.224664 ==
5550 00:39:11.227551 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 00:39:11.230796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 00:39:11.230876 ==
5553 00:39:11.234382 [Gating] SW mode calibration
5554 00:39:11.241214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5555 00:39:11.247254 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5556 00:39:11.251165 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 00:39:11.257655 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 00:39:11.260921 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 00:39:11.264436 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 00:39:11.270538 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 00:39:11.273582 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 00:39:11.277447 0 14 24 | B1->B0 | 3232 3030 | 1 0 | (1 1) (0 0)
5563 00:39:11.283889 0 14 28 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 1)
5564 00:39:11.286938 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 00:39:11.290273 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 00:39:11.297108 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 00:39:11.300028 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 00:39:11.303425 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 00:39:11.306934 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 00:39:11.313769 0 15 24 | B1->B0 | 2626 3030 | 1 0 | (0 0) (0 0)
5571 00:39:11.316777 0 15 28 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
5572 00:39:11.320172 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 00:39:11.327017 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 00:39:11.329908 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 00:39:11.333336 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 00:39:11.340261 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 00:39:11.343699 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 00:39:11.350066 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 00:39:11.353353 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 00:39:11.356804 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 00:39:11.359982 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 00:39:11.366648 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:39:11.369724 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:39:11.377119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:39:11.379450 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:39:11.383023 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:39:11.389438 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:39:11.392944 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:39:11.395961 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:39:11.402368 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:39:11.405904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:39:11.409528 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:39:11.415815 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:39:11.419206 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:39:11.422560 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 00:39:11.425464 Total UI for P1: 0, mck2ui 16
5597 00:39:11.428735 best dqsien dly found for B0: ( 1, 2, 26)
5598 00:39:11.432704 Total UI for P1: 0, mck2ui 16
5599 00:39:11.435667 best dqsien dly found for B1: ( 1, 2, 26)
5600 00:39:11.438933 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5601 00:39:11.442172 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5602 00:39:11.442299
5603 00:39:11.445269 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5604 00:39:11.452168 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5605 00:39:11.452485 [Gating] SW calibration Done
5606 00:39:11.455075 ==
5607 00:39:11.455377 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 00:39:11.461955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 00:39:11.462199 ==
5610 00:39:11.462448 RX Vref Scan: 0
5611 00:39:11.462635
5612 00:39:11.465046 RX Vref 0 -> 0, step: 1
5613 00:39:11.465372
5614 00:39:11.468525 RX Delay -80 -> 252, step: 8
5615 00:39:11.471741 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5616 00:39:11.474916 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5617 00:39:11.477942 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5618 00:39:11.484589 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5619 00:39:11.488073 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5620 00:39:11.491407 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5621 00:39:11.494609 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5622 00:39:11.497914 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5623 00:39:11.501843 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5624 00:39:11.508027 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5625 00:39:11.511258 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5626 00:39:11.514122 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5627 00:39:11.517220 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5628 00:39:11.520662 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5629 00:39:11.527424 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5630 00:39:11.531020 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5631 00:39:11.531128 ==
5632 00:39:11.534055 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 00:39:11.537206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 00:39:11.537369 ==
5635 00:39:11.540718 DQS Delay:
5636 00:39:11.540817 DQS0 = 0, DQS1 = 0
5637 00:39:11.540912 DQM Delay:
5638 00:39:11.543558 DQM0 = 100, DQM1 = 95
5639 00:39:11.543657 DQ Delay:
5640 00:39:11.547055 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5641 00:39:11.550657 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5642 00:39:11.553863 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5643 00:39:11.557177 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5644 00:39:11.560393
5645 00:39:11.560583
5646 00:39:11.560713 ==
5647 00:39:11.563805 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 00:39:11.566683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 00:39:11.566792 ==
5650 00:39:11.566877
5651 00:39:11.566956
5652 00:39:11.570433 TX Vref Scan disable
5653 00:39:11.570551 == TX Byte 0 ==
5654 00:39:11.576795 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5655 00:39:11.580342 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5656 00:39:11.580489 == TX Byte 1 ==
5657 00:39:11.586825 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5658 00:39:11.589881 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5659 00:39:11.590070 ==
5660 00:39:11.593224 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 00:39:11.596906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 00:39:11.597238 ==
5663 00:39:11.597508
5664 00:39:11.600044
5665 00:39:11.600281 TX Vref Scan disable
5666 00:39:11.603163 == TX Byte 0 ==
5667 00:39:11.606600 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5668 00:39:11.610021 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5669 00:39:11.613126 == TX Byte 1 ==
5670 00:39:11.616671 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5671 00:39:11.623025 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5672 00:39:11.623482
5673 00:39:11.623819 [DATLAT]
5674 00:39:11.624178 Freq=933, CH1 RK0
5675 00:39:11.624556
5676 00:39:11.626417 DATLAT Default: 0xd
5677 00:39:11.626844 0, 0xFFFF, sum = 0
5678 00:39:11.629718 1, 0xFFFF, sum = 0
5679 00:39:11.630221 2, 0xFFFF, sum = 0
5680 00:39:11.632825 3, 0xFFFF, sum = 0
5681 00:39:11.636555 4, 0xFFFF, sum = 0
5682 00:39:11.637045 5, 0xFFFF, sum = 0
5683 00:39:11.639549 6, 0xFFFF, sum = 0
5684 00:39:11.640025 7, 0xFFFF, sum = 0
5685 00:39:11.642823 8, 0xFFFF, sum = 0
5686 00:39:11.643261 9, 0xFFFF, sum = 0
5687 00:39:11.646826 10, 0x0, sum = 1
5688 00:39:11.647307 11, 0x0, sum = 2
5689 00:39:11.649371 12, 0x0, sum = 3
5690 00:39:11.649790 13, 0x0, sum = 4
5691 00:39:11.650122 best_step = 11
5692 00:39:11.652987
5693 00:39:11.653465 ==
5694 00:39:11.656066 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 00:39:11.659482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 00:39:11.659914 ==
5697 00:39:11.660350 RX Vref Scan: 1
5698 00:39:11.660762
5699 00:39:11.662431 RX Vref 0 -> 0, step: 1
5700 00:39:11.662827
5701 00:39:11.665652 RX Delay -53 -> 252, step: 4
5702 00:39:11.666083
5703 00:39:11.669149 Set Vref, RX VrefLevel [Byte0]: 53
5704 00:39:11.672522 [Byte1]: 49
5705 00:39:11.676032
5706 00:39:11.676457 Final RX Vref Byte 0 = 53 to rank0
5707 00:39:11.679083 Final RX Vref Byte 1 = 49 to rank0
5708 00:39:11.682524 Final RX Vref Byte 0 = 53 to rank1
5709 00:39:11.685464 Final RX Vref Byte 1 = 49 to rank1==
5710 00:39:11.689395 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 00:39:11.695353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 00:39:11.695813 ==
5713 00:39:11.696250 DQS Delay:
5714 00:39:11.698626 DQS0 = 0, DQS1 = 0
5715 00:39:11.699167 DQM Delay:
5716 00:39:11.699597 DQM0 = 98, DQM1 = 94
5717 00:39:11.702070 DQ Delay:
5718 00:39:11.705312 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =100
5719 00:39:11.708651 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5720 00:39:11.712038 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5721 00:39:11.715506 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5722 00:39:11.715955
5723 00:39:11.716401
5724 00:39:11.721973 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5725 00:39:11.724836 CH1 RK0: MR19=505, MR18=C1C
5726 00:39:11.731769 CH1_RK0: MR19=0x505, MR18=0xC1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5727 00:39:11.732226
5728 00:39:11.734796 ----->DramcWriteLeveling(PI) begin...
5729 00:39:11.735292 ==
5730 00:39:11.738293 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 00:39:11.741807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:39:11.742341 ==
5733 00:39:11.744776 Write leveling (Byte 0): 26 => 26
5734 00:39:11.748179 Write leveling (Byte 1): 27 => 27
5735 00:39:11.751611 DramcWriteLeveling(PI) end<-----
5736 00:39:11.752134
5737 00:39:11.752482 ==
5738 00:39:11.755033 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 00:39:11.761521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 00:39:11.761978 ==
5741 00:39:11.762374 [Gating] SW mode calibration
5742 00:39:11.771349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5743 00:39:11.774872 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5744 00:39:11.781223 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 00:39:11.784883 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 00:39:11.787836 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 00:39:11.794774 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 00:39:11.797986 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 00:39:11.801194 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 00:39:11.804449 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
5751 00:39:11.810783 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5752 00:39:11.814407 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 00:39:11.817363 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 00:39:11.824068 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 00:39:11.827685 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 00:39:11.830582 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 00:39:11.837469 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 00:39:11.840512 0 15 24 | B1->B0 | 2929 3838 | 0 0 | (0 0) (1 1)
5759 00:39:11.844121 0 15 28 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5760 00:39:11.850629 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 00:39:11.853961 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 00:39:11.857461 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 00:39:11.863881 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 00:39:11.867139 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 00:39:11.870389 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 00:39:11.877183 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5767 00:39:11.880203 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 00:39:11.883735 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 00:39:11.890187 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 00:39:11.893860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 00:39:11.896624 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 00:39:11.903445 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 00:39:11.907019 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:39:11.909810 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:39:11.916762 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:39:11.919716 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:39:11.923014 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:39:11.929414 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:39:11.932607 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:39:11.936073 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:39:11.942575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:39:11.946407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5783 00:39:11.949527 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 00:39:11.956051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 00:39:11.959704 Total UI for P1: 0, mck2ui 16
5786 00:39:11.962390 best dqsien dly found for B0: ( 1, 2, 26)
5787 00:39:11.965995 Total UI for P1: 0, mck2ui 16
5788 00:39:11.969061 best dqsien dly found for B1: ( 1, 2, 28)
5789 00:39:11.972676 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5790 00:39:11.976356 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5791 00:39:11.976852
5792 00:39:11.979139 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5793 00:39:11.982361 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5794 00:39:11.985331 [Gating] SW calibration Done
5795 00:39:11.985802 ==
5796 00:39:11.989295 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 00:39:11.992736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 00:39:11.993174 ==
5799 00:39:11.995857 RX Vref Scan: 0
5800 00:39:11.996284
5801 00:39:11.998754 RX Vref 0 -> 0, step: 1
5802 00:39:11.999182
5803 00:39:11.999619 RX Delay -80 -> 252, step: 8
5804 00:39:12.005319 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5805 00:39:12.009054 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5806 00:39:12.012182 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5807 00:39:12.015283 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5808 00:39:12.018614 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5809 00:39:12.025080 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5810 00:39:12.028562 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5811 00:39:12.031657 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5812 00:39:12.035479 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5813 00:39:12.038002 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5814 00:39:12.041684 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5815 00:39:12.048075 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5816 00:39:12.051198 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5817 00:39:12.054602 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5818 00:39:12.057915 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5819 00:39:12.061332 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5820 00:39:12.064292 ==
5821 00:39:12.067489 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 00:39:12.071495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 00:39:12.071961 ==
5824 00:39:12.072439 DQS Delay:
5825 00:39:12.074600 DQS0 = 0, DQS1 = 0
5826 00:39:12.075048 DQM Delay:
5827 00:39:12.077867 DQM0 = 97, DQM1 = 94
5828 00:39:12.078276 DQ Delay:
5829 00:39:12.080943 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5830 00:39:12.084096 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5831 00:39:12.087906 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5832 00:39:12.090545 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5833 00:39:12.090960
5834 00:39:12.091286
5835 00:39:12.091584 ==
5836 00:39:12.094134 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 00:39:12.097639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 00:39:12.100785 ==
5839 00:39:12.101366
5840 00:39:12.101765
5841 00:39:12.102085 TX Vref Scan disable
5842 00:39:12.104250 == TX Byte 0 ==
5843 00:39:12.107045 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5844 00:39:12.111011 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5845 00:39:12.113477 == TX Byte 1 ==
5846 00:39:12.117620 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5847 00:39:12.120129 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5848 00:39:12.123814 ==
5849 00:39:12.127113 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 00:39:12.130163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 00:39:12.130583 ==
5852 00:39:12.130952
5853 00:39:12.131261
5854 00:39:12.134038 TX Vref Scan disable
5855 00:39:12.134446 == TX Byte 0 ==
5856 00:39:12.140399 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5857 00:39:12.143248 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5858 00:39:12.143676 == TX Byte 1 ==
5859 00:39:12.150365 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 00:39:12.153330 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 00:39:12.153714
5862 00:39:12.154027 [DATLAT]
5863 00:39:12.156592 Freq=933, CH1 RK1
5864 00:39:12.157054
5865 00:39:12.157426 DATLAT Default: 0xb
5866 00:39:12.159640 0, 0xFFFF, sum = 0
5867 00:39:12.160054 1, 0xFFFF, sum = 0
5868 00:39:12.163444 2, 0xFFFF, sum = 0
5869 00:39:12.163853 3, 0xFFFF, sum = 0
5870 00:39:12.166330 4, 0xFFFF, sum = 0
5871 00:39:12.169800 5, 0xFFFF, sum = 0
5872 00:39:12.170211 6, 0xFFFF, sum = 0
5873 00:39:12.173202 7, 0xFFFF, sum = 0
5874 00:39:12.173747 8, 0xFFFF, sum = 0
5875 00:39:12.176113 9, 0xFFFF, sum = 0
5876 00:39:12.176526 10, 0x0, sum = 1
5877 00:39:12.179562 11, 0x0, sum = 2
5878 00:39:12.179974 12, 0x0, sum = 3
5879 00:39:12.182985 13, 0x0, sum = 4
5880 00:39:12.183397 best_step = 11
5881 00:39:12.183717
5882 00:39:12.184015 ==
5883 00:39:12.186118 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 00:39:12.189718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 00:39:12.190160 ==
5886 00:39:12.192682 RX Vref Scan: 0
5887 00:39:12.193161
5888 00:39:12.195703 RX Vref 0 -> 0, step: 1
5889 00:39:12.196133
5890 00:39:12.196461 RX Delay -53 -> 252, step: 4
5891 00:39:12.203755 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5892 00:39:12.207120 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5893 00:39:12.210669 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5894 00:39:12.214073 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5895 00:39:12.216751 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5896 00:39:12.223676 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5897 00:39:12.227302 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5898 00:39:12.230246 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5899 00:39:12.234163 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5900 00:39:12.236747 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5901 00:39:12.240302 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5902 00:39:12.247137 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5903 00:39:12.250291 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5904 00:39:12.253652 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5905 00:39:12.256661 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5906 00:39:12.260097 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5907 00:39:12.263297 ==
5908 00:39:12.266543 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 00:39:12.270225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 00:39:12.270652 ==
5911 00:39:12.270980 DQS Delay:
5912 00:39:12.273246 DQS0 = 0, DQS1 = 0
5913 00:39:12.273711 DQM Delay:
5914 00:39:12.276203 DQM0 = 97, DQM1 = 92
5915 00:39:12.276611 DQ Delay:
5916 00:39:12.279473 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =94
5917 00:39:12.282796 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =96
5918 00:39:12.286373 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =86
5919 00:39:12.289732 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5920 00:39:12.290446
5921 00:39:12.290806
5922 00:39:12.299510 [DQSOSCAuto] RK1, (LSB)MR18= 0x1027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5923 00:39:12.299997 CH1 RK1: MR19=505, MR18=1027
5924 00:39:12.305855 CH1_RK1: MR19=0x505, MR18=0x1027, DQSOSC=409, MR23=63, INC=64, DEC=43
5925 00:39:12.309217 [RxdqsGatingPostProcess] freq 933
5926 00:39:12.315956 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 00:39:12.319525 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 00:39:12.322499 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 00:39:12.325888 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 00:39:12.329137 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 00:39:12.332425 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 00:39:12.332839 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 00:39:12.335754 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 00:39:12.338983 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 00:39:12.342082 Pre-setting of DQS Precalculation
5936 00:39:12.348833 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 00:39:12.355264 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 00:39:12.362274 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 00:39:12.362691
5940 00:39:12.363018
5941 00:39:12.365789 [Calibration Summary] 1866 Mbps
5942 00:39:12.368691 CH 0, Rank 0
5943 00:39:12.369096 SW Impedance : PASS
5944 00:39:12.371796 DUTY Scan : NO K
5945 00:39:12.375321 ZQ Calibration : PASS
5946 00:39:12.375728 Jitter Meter : NO K
5947 00:39:12.378508 CBT Training : PASS
5948 00:39:12.382065 Write leveling : PASS
5949 00:39:12.382471 RX DQS gating : PASS
5950 00:39:12.385413 RX DQ/DQS(RDDQC) : PASS
5951 00:39:12.385816 TX DQ/DQS : PASS
5952 00:39:12.388313 RX DATLAT : PASS
5953 00:39:12.391935 RX DQ/DQS(Engine): PASS
5954 00:39:12.392342 TX OE : NO K
5955 00:39:12.395083 All Pass.
5956 00:39:12.395484
5957 00:39:12.395806 CH 0, Rank 1
5958 00:39:12.398448 SW Impedance : PASS
5959 00:39:12.398851 DUTY Scan : NO K
5960 00:39:12.401452 ZQ Calibration : PASS
5961 00:39:12.404508 Jitter Meter : NO K
5962 00:39:12.404587 CBT Training : PASS
5963 00:39:12.408255 Write leveling : PASS
5964 00:39:12.411283 RX DQS gating : PASS
5965 00:39:12.411361 RX DQ/DQS(RDDQC) : PASS
5966 00:39:12.414515 TX DQ/DQS : PASS
5967 00:39:12.418374 RX DATLAT : PASS
5968 00:39:12.418453 RX DQ/DQS(Engine): PASS
5969 00:39:12.420913 TX OE : NO K
5970 00:39:12.420992 All Pass.
5971 00:39:12.421053
5972 00:39:12.424536 CH 1, Rank 0
5973 00:39:12.424615 SW Impedance : PASS
5974 00:39:12.427929 DUTY Scan : NO K
5975 00:39:12.431476 ZQ Calibration : PASS
5976 00:39:12.431561 Jitter Meter : NO K
5977 00:39:12.434415 CBT Training : PASS
5978 00:39:12.437999 Write leveling : PASS
5979 00:39:12.438091 RX DQS gating : PASS
5980 00:39:12.441155 RX DQ/DQS(RDDQC) : PASS
5981 00:39:12.444425 TX DQ/DQS : PASS
5982 00:39:12.444526 RX DATLAT : PASS
5983 00:39:12.447231 RX DQ/DQS(Engine): PASS
5984 00:39:12.451155 TX OE : NO K
5985 00:39:12.451569 All Pass.
5986 00:39:12.451893
5987 00:39:12.452198 CH 1, Rank 1
5988 00:39:12.454387 SW Impedance : PASS
5989 00:39:12.457893 DUTY Scan : NO K
5990 00:39:12.458307 ZQ Calibration : PASS
5991 00:39:12.461197 Jitter Meter : NO K
5992 00:39:12.461662 CBT Training : PASS
5993 00:39:12.464206 Write leveling : PASS
5994 00:39:12.467707 RX DQS gating : PASS
5995 00:39:12.468121 RX DQ/DQS(RDDQC) : PASS
5996 00:39:12.470900 TX DQ/DQS : PASS
5997 00:39:12.474111 RX DATLAT : PASS
5998 00:39:12.474525 RX DQ/DQS(Engine): PASS
5999 00:39:12.477427 TX OE : NO K
6000 00:39:12.477842 All Pass.
6001 00:39:12.478168
6002 00:39:12.480954 DramC Write-DBI off
6003 00:39:12.484184 PER_BANK_REFRESH: Hybrid Mode
6004 00:39:12.484599 TX_TRACKING: ON
6005 00:39:12.493936 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 00:39:12.497553 [FAST_K] Save calibration result to emmc
6007 00:39:12.500906 dramc_set_vcore_voltage set vcore to 650000
6008 00:39:12.504174 Read voltage for 400, 6
6009 00:39:12.504577 Vio18 = 0
6010 00:39:12.504895 Vcore = 650000
6011 00:39:12.507611 Vdram = 0
6012 00:39:12.508015 Vddq = 0
6013 00:39:12.508333 Vmddr = 0
6014 00:39:12.513886 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 00:39:12.517481 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 00:39:12.520485 MEM_TYPE=3, freq_sel=20
6017 00:39:12.523492 sv_algorithm_assistance_LP4_800
6018 00:39:12.527038 ============ PULL DRAM RESETB DOWN ============
6019 00:39:12.533620 ========== PULL DRAM RESETB DOWN end =========
6020 00:39:12.537295 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 00:39:12.540166 ===================================
6022 00:39:12.543762 LPDDR4 DRAM CONFIGURATION
6023 00:39:12.546906 ===================================
6024 00:39:12.547323 EX_ROW_EN[0] = 0x0
6025 00:39:12.550731 EX_ROW_EN[1] = 0x0
6026 00:39:12.551201 LP4Y_EN = 0x0
6027 00:39:12.553933 WORK_FSP = 0x0
6028 00:39:12.554350 WL = 0x2
6029 00:39:12.556762 RL = 0x2
6030 00:39:12.557362 BL = 0x2
6031 00:39:12.560435 RPST = 0x0
6032 00:39:12.563014 RD_PRE = 0x0
6033 00:39:12.563428 WR_PRE = 0x1
6034 00:39:12.566603 WR_PST = 0x0
6035 00:39:12.567028 DBI_WR = 0x0
6036 00:39:12.570293 DBI_RD = 0x0
6037 00:39:12.570702 OTF = 0x1
6038 00:39:12.573124 ===================================
6039 00:39:12.576814 ===================================
6040 00:39:12.579753 ANA top config
6041 00:39:12.583395 ===================================
6042 00:39:12.583809 DLL_ASYNC_EN = 0
6043 00:39:12.586247 ALL_SLAVE_EN = 1
6044 00:39:12.589607 NEW_RANK_MODE = 1
6045 00:39:12.593075 DLL_IDLE_MODE = 1
6046 00:39:12.593517 LP45_APHY_COMB_EN = 1
6047 00:39:12.596541 TX_ODT_DIS = 1
6048 00:39:12.599882 NEW_8X_MODE = 1
6049 00:39:12.603287 ===================================
6050 00:39:12.606417 ===================================
6051 00:39:12.610037 data_rate = 800
6052 00:39:12.612869 CKR = 1
6053 00:39:12.616026 DQ_P2S_RATIO = 4
6054 00:39:12.619395 ===================================
6055 00:39:12.619807 CA_P2S_RATIO = 4
6056 00:39:12.622589 DQ_CA_OPEN = 0
6057 00:39:12.625891 DQ_SEMI_OPEN = 1
6058 00:39:12.628983 CA_SEMI_OPEN = 1
6059 00:39:12.632644 CA_FULL_RATE = 0
6060 00:39:12.635764 DQ_CKDIV4_EN = 0
6061 00:39:12.636314 CA_CKDIV4_EN = 1
6062 00:39:12.639003 CA_PREDIV_EN = 0
6063 00:39:12.642442 PH8_DLY = 0
6064 00:39:12.646227 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 00:39:12.649021 DQ_AAMCK_DIV = 0
6066 00:39:12.652336 CA_AAMCK_DIV = 0
6067 00:39:12.652745 CA_ADMCK_DIV = 4
6068 00:39:12.655453 DQ_TRACK_CA_EN = 0
6069 00:39:12.658907 CA_PICK = 800
6070 00:39:12.662024 CA_MCKIO = 400
6071 00:39:12.665236 MCKIO_SEMI = 400
6072 00:39:12.668761 PLL_FREQ = 3016
6073 00:39:12.672091 DQ_UI_PI_RATIO = 32
6074 00:39:12.675477 CA_UI_PI_RATIO = 32
6075 00:39:12.679076 ===================================
6076 00:39:12.681890 ===================================
6077 00:39:12.682305 memory_type:LPDDR4
6078 00:39:12.685514 GP_NUM : 10
6079 00:39:12.689047 SRAM_EN : 1
6080 00:39:12.689566 MD32_EN : 0
6081 00:39:12.691857 ===================================
6082 00:39:12.695296 [ANA_INIT] >>>>>>>>>>>>>>
6083 00:39:12.698657 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 00:39:12.701983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 00:39:12.705139 ===================================
6086 00:39:12.708843 data_rate = 800,PCW = 0X7400
6087 00:39:12.712247 ===================================
6088 00:39:12.715121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 00:39:12.718310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 00:39:12.731941 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 00:39:12.735190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 00:39:12.738151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 00:39:12.741237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 00:39:12.745046 [ANA_INIT] flow start
6095 00:39:12.747827 [ANA_INIT] PLL >>>>>>>>
6096 00:39:12.748241 [ANA_INIT] PLL <<<<<<<<
6097 00:39:12.750948 [ANA_INIT] MIDPI >>>>>>>>
6098 00:39:12.754434 [ANA_INIT] MIDPI <<<<<<<<
6099 00:39:12.754862 [ANA_INIT] DLL >>>>>>>>
6100 00:39:12.757768 [ANA_INIT] flow end
6101 00:39:12.761245 ============ LP4 DIFF to SE enter ============
6102 00:39:12.767802 ============ LP4 DIFF to SE exit ============
6103 00:39:12.768219 [ANA_INIT] <<<<<<<<<<<<<
6104 00:39:12.771440 [Flow] Enable top DCM control >>>>>
6105 00:39:12.774707 [Flow] Enable top DCM control <<<<<
6106 00:39:12.777711 Enable DLL master slave shuffle
6107 00:39:12.784951 ==============================================================
6108 00:39:12.785466 Gating Mode config
6109 00:39:12.790713 ==============================================================
6110 00:39:12.794202 Config description:
6111 00:39:12.801093 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 00:39:12.807364 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 00:39:12.813933 SELPH_MODE 0: By rank 1: By Phase
6114 00:39:12.820748 ==============================================================
6115 00:39:12.823683 GAT_TRACK_EN = 0
6116 00:39:12.824092 RX_GATING_MODE = 2
6117 00:39:12.827565 RX_GATING_TRACK_MODE = 2
6118 00:39:12.830502 SELPH_MODE = 1
6119 00:39:12.833513 PICG_EARLY_EN = 1
6120 00:39:12.837600 VALID_LAT_VALUE = 1
6121 00:39:12.843766 ==============================================================
6122 00:39:12.847236 Enter into Gating configuration >>>>
6123 00:39:12.850567 Exit from Gating configuration <<<<
6124 00:39:12.853715 Enter into DVFS_PRE_config >>>>>
6125 00:39:12.863463 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 00:39:12.867163 Exit from DVFS_PRE_config <<<<<
6127 00:39:12.870414 Enter into PICG configuration >>>>
6128 00:39:12.873405 Exit from PICG configuration <<<<
6129 00:39:12.876572 [RX_INPUT] configuration >>>>>
6130 00:39:12.880294 [RX_INPUT] configuration <<<<<
6131 00:39:12.883551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 00:39:12.889735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 00:39:12.896918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 00:39:12.903293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 00:39:12.906313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 00:39:12.913058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 00:39:12.919697 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 00:39:12.922943 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 00:39:12.926046 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 00:39:12.929354 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 00:39:12.932680 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 00:39:12.939440 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 00:39:12.942429 ===================================
6144 00:39:12.946035 LPDDR4 DRAM CONFIGURATION
6145 00:39:12.948906 ===================================
6146 00:39:12.949358 EX_ROW_EN[0] = 0x0
6147 00:39:12.952595 EX_ROW_EN[1] = 0x0
6148 00:39:12.953003 LP4Y_EN = 0x0
6149 00:39:12.955609 WORK_FSP = 0x0
6150 00:39:12.956081 WL = 0x2
6151 00:39:12.959164 RL = 0x2
6152 00:39:12.959575 BL = 0x2
6153 00:39:12.962323 RPST = 0x0
6154 00:39:12.962980 RD_PRE = 0x0
6155 00:39:12.965680 WR_PRE = 0x1
6156 00:39:12.966093 WR_PST = 0x0
6157 00:39:12.968632 DBI_WR = 0x0
6158 00:39:12.972200 DBI_RD = 0x0
6159 00:39:12.972615 OTF = 0x1
6160 00:39:12.975652 ===================================
6161 00:39:12.979131 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 00:39:12.981883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 00:39:12.988496 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 00:39:12.991917 ===================================
6165 00:39:12.995137 LPDDR4 DRAM CONFIGURATION
6166 00:39:12.999004 ===================================
6167 00:39:12.999421 EX_ROW_EN[0] = 0x10
6168 00:39:13.001711 EX_ROW_EN[1] = 0x0
6169 00:39:13.002131 LP4Y_EN = 0x0
6170 00:39:13.005302 WORK_FSP = 0x0
6171 00:39:13.005718 WL = 0x2
6172 00:39:13.008455 RL = 0x2
6173 00:39:13.008896 BL = 0x2
6174 00:39:13.012035 RPST = 0x0
6175 00:39:13.012501 RD_PRE = 0x0
6176 00:39:13.015069 WR_PRE = 0x1
6177 00:39:13.015556 WR_PST = 0x0
6178 00:39:13.019529 DBI_WR = 0x0
6179 00:39:13.021828 DBI_RD = 0x0
6180 00:39:13.022242 OTF = 0x1
6181 00:39:13.024853 ===================================
6182 00:39:13.031449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 00:39:13.035046 nWR fixed to 30
6184 00:39:13.038622 [ModeRegInit_LP4] CH0 RK0
6185 00:39:13.039118 [ModeRegInit_LP4] CH0 RK1
6186 00:39:13.041463 [ModeRegInit_LP4] CH1 RK0
6187 00:39:13.045038 [ModeRegInit_LP4] CH1 RK1
6188 00:39:13.045554 match AC timing 19
6189 00:39:13.051495 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 00:39:13.055028 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 00:39:13.058095 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 00:39:13.064696 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 00:39:13.067766 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 00:39:13.067846 ==
6195 00:39:13.070991 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 00:39:13.074503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 00:39:13.074584 ==
6198 00:39:13.081056 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 00:39:13.087796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6200 00:39:13.091186 [CA 0] Center 36 (8~64) winsize 57
6201 00:39:13.094644 [CA 1] Center 36 (8~64) winsize 57
6202 00:39:13.097527 [CA 2] Center 36 (8~64) winsize 57
6203 00:39:13.101244 [CA 3] Center 36 (8~64) winsize 57
6204 00:39:13.104623 [CA 4] Center 36 (8~64) winsize 57
6205 00:39:13.104716 [CA 5] Center 36 (8~64) winsize 57
6206 00:39:13.107537
6207 00:39:13.111024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6208 00:39:13.111132
6209 00:39:13.114022 [CATrainingPosCal] consider 1 rank data
6210 00:39:13.117495 u2DelayCellTimex100 = 270/100 ps
6211 00:39:13.120856 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 00:39:13.124233 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 00:39:13.127215 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 00:39:13.130957 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 00:39:13.134205 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 00:39:13.137363 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 00:39:13.137774
6218 00:39:13.140842 CA PerBit enable=1, Macro0, CA PI delay=36
6219 00:39:13.143989
6220 00:39:13.144394 [CBTSetCACLKResult] CA Dly = 36
6221 00:39:13.147827 CS Dly: 1 (0~32)
6222 00:39:13.148449 ==
6223 00:39:13.150610 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 00:39:13.154170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 00:39:13.154594 ==
6226 00:39:13.160492 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 00:39:13.167082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 00:39:13.170832 [CA 0] Center 36 (8~64) winsize 57
6229 00:39:13.173553 [CA 1] Center 36 (8~64) winsize 57
6230 00:39:13.177140 [CA 2] Center 36 (8~64) winsize 57
6231 00:39:13.180081 [CA 3] Center 36 (8~64) winsize 57
6232 00:39:13.180487 [CA 4] Center 36 (8~64) winsize 57
6233 00:39:13.183214 [CA 5] Center 36 (8~64) winsize 57
6234 00:39:13.183633
6235 00:39:13.190172 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 00:39:13.190768
6237 00:39:13.193597 [CATrainingPosCal] consider 2 rank data
6238 00:39:13.196642 u2DelayCellTimex100 = 270/100 ps
6239 00:39:13.199969 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 00:39:13.203564 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 00:39:13.206595 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 00:39:13.210105 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 00:39:13.213546 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 00:39:13.216616 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 00:39:13.217158
6246 00:39:13.219608 CA PerBit enable=1, Macro0, CA PI delay=36
6247 00:39:13.220100
6248 00:39:13.223122 [CBTSetCACLKResult] CA Dly = 36
6249 00:39:13.226599 CS Dly: 1 (0~32)
6250 00:39:13.227032
6251 00:39:13.229800 ----->DramcWriteLeveling(PI) begin...
6252 00:39:13.230259 ==
6253 00:39:13.232681 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 00:39:13.235999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 00:39:13.236415 ==
6256 00:39:13.239366 Write leveling (Byte 0): 40 => 8
6257 00:39:13.242755 Write leveling (Byte 1): 40 => 8
6258 00:39:13.246035 DramcWriteLeveling(PI) end<-----
6259 00:39:13.246649
6260 00:39:13.247238 ==
6261 00:39:13.249131 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 00:39:13.252593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 00:39:13.253295 ==
6264 00:39:13.255921 [Gating] SW mode calibration
6265 00:39:13.262346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 00:39:13.269206 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 00:39:13.272470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 00:39:13.278698 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 00:39:13.282146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 00:39:13.285369 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 00:39:13.291976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 00:39:13.295699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 00:39:13.298592 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 00:39:13.305485 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 00:39:13.308435 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 00:39:13.312236 Total UI for P1: 0, mck2ui 16
6277 00:39:13.315344 best dqsien dly found for B0: ( 0, 14, 24)
6278 00:39:13.318603 Total UI for P1: 0, mck2ui 16
6279 00:39:13.321413 best dqsien dly found for B1: ( 0, 14, 24)
6280 00:39:13.325247 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 00:39:13.328057 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 00:39:13.328614
6283 00:39:13.331352 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 00:39:13.334942 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 00:39:13.338026 [Gating] SW calibration Done
6286 00:39:13.338583 ==
6287 00:39:13.341742 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 00:39:13.347982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 00:39:13.348393 ==
6290 00:39:13.348715 RX Vref Scan: 0
6291 00:39:13.349078
6292 00:39:13.351265 RX Vref 0 -> 0, step: 1
6293 00:39:13.351780
6294 00:39:13.355153 RX Delay -410 -> 252, step: 16
6295 00:39:13.358081 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6296 00:39:13.361126 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6297 00:39:13.368558 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6298 00:39:13.371391 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6299 00:39:13.374751 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6300 00:39:13.377797 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6301 00:39:13.383858 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6302 00:39:13.387486 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6303 00:39:13.391031 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6304 00:39:13.394047 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6305 00:39:13.400760 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6306 00:39:13.403684 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6307 00:39:13.407155 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6308 00:39:13.413999 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6309 00:39:13.416914 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6310 00:39:13.420439 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6311 00:39:13.420666 ==
6312 00:39:13.424045 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 00:39:13.426904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 00:39:13.430412 ==
6315 00:39:13.430686 DQS Delay:
6316 00:39:13.430902 DQS0 = 43, DQS1 = 51
6317 00:39:13.433240 DQM Delay:
6318 00:39:13.433541 DQM0 = 11, DQM1 = 10
6319 00:39:13.436653 DQ Delay:
6320 00:39:13.436922 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6321 00:39:13.440086 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6322 00:39:13.443533 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6323 00:39:13.447125 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6324 00:39:13.447395
6325 00:39:13.447605
6326 00:39:13.447801 ==
6327 00:39:13.449868 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 00:39:13.456672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 00:39:13.456954 ==
6330 00:39:13.457278
6331 00:39:13.457567
6332 00:39:13.459686 TX Vref Scan disable
6333 00:39:13.460033 == TX Byte 0 ==
6334 00:39:13.463023 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 00:39:13.469678 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 00:39:13.470019 == TX Byte 1 ==
6337 00:39:13.473226 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 00:39:13.476309 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 00:39:13.479710 ==
6340 00:39:13.482656 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 00:39:13.486190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 00:39:13.486603 ==
6343 00:39:13.486950
6344 00:39:13.487303
6345 00:39:13.489172 TX Vref Scan disable
6346 00:39:13.489583 == TX Byte 0 ==
6347 00:39:13.492975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 00:39:13.499523 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 00:39:13.499875 == TX Byte 1 ==
6350 00:39:13.502873 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 00:39:13.509500 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 00:39:13.509813
6353 00:39:13.510178 [DATLAT]
6354 00:39:13.510391 Freq=400, CH0 RK0
6355 00:39:13.510588
6356 00:39:13.512504 DATLAT Default: 0xf
6357 00:39:13.515750 0, 0xFFFF, sum = 0
6358 00:39:13.516143 1, 0xFFFF, sum = 0
6359 00:39:13.519347 2, 0xFFFF, sum = 0
6360 00:39:13.519706 3, 0xFFFF, sum = 0
6361 00:39:13.522214 4, 0xFFFF, sum = 0
6362 00:39:13.522565 5, 0xFFFF, sum = 0
6363 00:39:13.525663 6, 0xFFFF, sum = 0
6364 00:39:13.525933 7, 0xFFFF, sum = 0
6365 00:39:13.528809 8, 0xFFFF, sum = 0
6366 00:39:13.529079 9, 0xFFFF, sum = 0
6367 00:39:13.532591 10, 0xFFFF, sum = 0
6368 00:39:13.532936 11, 0xFFFF, sum = 0
6369 00:39:13.535542 12, 0xFFFF, sum = 0
6370 00:39:13.535956 13, 0x0, sum = 1
6371 00:39:13.538768 14, 0x0, sum = 2
6372 00:39:13.539155 15, 0x0, sum = 3
6373 00:39:13.542741 16, 0x0, sum = 4
6374 00:39:13.543013 best_step = 14
6375 00:39:13.543225
6376 00:39:13.543420 ==
6377 00:39:13.545452 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 00:39:13.552080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 00:39:13.552350 ==
6380 00:39:13.552562 RX Vref Scan: 1
6381 00:39:13.552758
6382 00:39:13.555362 RX Vref 0 -> 0, step: 1
6383 00:39:13.555629
6384 00:39:13.558391 RX Delay -343 -> 252, step: 8
6385 00:39:13.558657
6386 00:39:13.561738 Set Vref, RX VrefLevel [Byte0]: 56
6387 00:39:13.565650 [Byte1]: 49
6388 00:39:13.568591
6389 00:39:13.568865 Final RX Vref Byte 0 = 56 to rank0
6390 00:39:13.571674 Final RX Vref Byte 1 = 49 to rank0
6391 00:39:13.574807 Final RX Vref Byte 0 = 56 to rank1
6392 00:39:13.578315 Final RX Vref Byte 1 = 49 to rank1==
6393 00:39:13.581606 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 00:39:13.588355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 00:39:13.588716 ==
6396 00:39:13.589084 DQS Delay:
6397 00:39:13.591880 DQS0 = 44, DQS1 = 56
6398 00:39:13.592337 DQM Delay:
6399 00:39:13.592710 DQM0 = 10, DQM1 = 14
6400 00:39:13.594920 DQ Delay:
6401 00:39:13.598525 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6402 00:39:13.601644 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6403 00:39:13.602005 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6404 00:39:13.604728 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6405 00:39:13.608157
6406 00:39:13.608515
6407 00:39:13.614440 [DQSOSCAuto] RK0, (LSB)MR18= 0xa497, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6408 00:39:13.617889 CH0 RK0: MR19=C0C, MR18=A497
6409 00:39:13.624442 CH0_RK0: MR19=0xC0C, MR18=0xA497, DQSOSC=389, MR23=63, INC=390, DEC=260
6410 00:39:13.624807 ==
6411 00:39:13.627790 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 00:39:13.631499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 00:39:13.631863 ==
6414 00:39:13.634323 [Gating] SW mode calibration
6415 00:39:13.641242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 00:39:13.647482 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 00:39:13.650928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 00:39:13.654097 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 00:39:13.661109 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 00:39:13.664016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 00:39:13.667578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 00:39:13.674149 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 00:39:13.677495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 00:39:13.680931 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 00:39:13.687112 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 00:39:13.690988 Total UI for P1: 0, mck2ui 16
6427 00:39:13.693985 best dqsien dly found for B0: ( 0, 14, 24)
6428 00:39:13.696867 Total UI for P1: 0, mck2ui 16
6429 00:39:13.700603 best dqsien dly found for B1: ( 0, 14, 24)
6430 00:39:13.704100 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 00:39:13.706876 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 00:39:13.707432
6433 00:39:13.710280 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 00:39:13.713485 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 00:39:13.716940 [Gating] SW calibration Done
6436 00:39:13.717424 ==
6437 00:39:13.720526 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 00:39:13.723623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 00:39:13.724053 ==
6440 00:39:13.726870 RX Vref Scan: 0
6441 00:39:13.727293
6442 00:39:13.730032 RX Vref 0 -> 0, step: 1
6443 00:39:13.730457
6444 00:39:13.730891 RX Delay -410 -> 252, step: 16
6445 00:39:13.736986 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6446 00:39:13.739950 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6447 00:39:13.743401 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6448 00:39:13.750582 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6449 00:39:13.753135 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6450 00:39:13.756809 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6451 00:39:13.759862 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6452 00:39:13.766640 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6453 00:39:13.769600 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6454 00:39:13.772893 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6455 00:39:13.776637 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6456 00:39:13.782769 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6457 00:39:13.785976 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6458 00:39:13.789219 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6459 00:39:13.795732 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6460 00:39:13.799019 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6461 00:39:13.799423 ==
6462 00:39:13.802393 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 00:39:13.805909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 00:39:13.806319 ==
6465 00:39:13.809338 DQS Delay:
6466 00:39:13.809742 DQS0 = 35, DQS1 = 51
6467 00:39:13.810062 DQM Delay:
6468 00:39:13.812853 DQM0 = 7, DQM1 = 10
6469 00:39:13.813446 DQ Delay:
6470 00:39:13.815611 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6471 00:39:13.818757 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6472 00:39:13.822785 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6473 00:39:13.825403 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6474 00:39:13.825907
6475 00:39:13.826370
6476 00:39:13.826683 ==
6477 00:39:13.828670 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 00:39:13.831933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 00:39:13.835263 ==
6480 00:39:13.835730
6481 00:39:13.836062
6482 00:39:13.836362 TX Vref Scan disable
6483 00:39:13.838809 == TX Byte 0 ==
6484 00:39:13.841752 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6485 00:39:13.845528 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6486 00:39:13.848641 == TX Byte 1 ==
6487 00:39:13.851719 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6488 00:39:13.854818 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6489 00:39:13.855224 ==
6490 00:39:13.858411 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 00:39:13.864866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 00:39:13.865396 ==
6493 00:39:13.865851
6494 00:39:13.866374
6495 00:39:13.866742 TX Vref Scan disable
6496 00:39:13.868341 == TX Byte 0 ==
6497 00:39:13.871688 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6498 00:39:13.874589 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6499 00:39:13.878089 == TX Byte 1 ==
6500 00:39:13.881314 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 00:39:13.884485 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 00:39:13.884892
6503 00:39:13.887574 [DATLAT]
6504 00:39:13.887976 Freq=400, CH0 RK1
6505 00:39:13.888300
6506 00:39:13.891028 DATLAT Default: 0xe
6507 00:39:13.891430 0, 0xFFFF, sum = 0
6508 00:39:13.894250 1, 0xFFFF, sum = 0
6509 00:39:13.894622 2, 0xFFFF, sum = 0
6510 00:39:13.897658 3, 0xFFFF, sum = 0
6511 00:39:13.898072 4, 0xFFFF, sum = 0
6512 00:39:13.901443 5, 0xFFFF, sum = 0
6513 00:39:13.901908 6, 0xFFFF, sum = 0
6514 00:39:13.904279 7, 0xFFFF, sum = 0
6515 00:39:13.904647 8, 0xFFFF, sum = 0
6516 00:39:13.907618 9, 0xFFFF, sum = 0
6517 00:39:13.911399 10, 0xFFFF, sum = 0
6518 00:39:13.911883 11, 0xFFFF, sum = 0
6519 00:39:13.913987 12, 0xFFFF, sum = 0
6520 00:39:13.914409 13, 0x0, sum = 1
6521 00:39:13.917520 14, 0x0, sum = 2
6522 00:39:13.917937 15, 0x0, sum = 3
6523 00:39:13.921018 16, 0x0, sum = 4
6524 00:39:13.921467 best_step = 14
6525 00:39:13.921796
6526 00:39:13.922101 ==
6527 00:39:13.924385 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 00:39:13.927554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 00:39:13.927973 ==
6530 00:39:13.930747 RX Vref Scan: 0
6531 00:39:13.931165
6532 00:39:13.933764 RX Vref 0 -> 0, step: 1
6533 00:39:13.934179
6534 00:39:13.934544 RX Delay -343 -> 252, step: 8
6535 00:39:13.942555 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6536 00:39:13.945877 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6537 00:39:13.949423 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6538 00:39:13.955987 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6539 00:39:13.959106 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6540 00:39:13.962344 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6541 00:39:13.965928 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6542 00:39:13.972428 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6543 00:39:13.975824 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6544 00:39:13.978782 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6545 00:39:13.982173 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6546 00:39:13.988789 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6547 00:39:13.992178 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6548 00:39:13.995660 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6549 00:39:13.998664 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6550 00:39:14.005466 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6551 00:39:14.005942 ==
6552 00:39:14.008364 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 00:39:14.011509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 00:39:14.011920 ==
6555 00:39:14.014710 DQS Delay:
6556 00:39:14.015120 DQS0 = 44, DQS1 = 60
6557 00:39:14.015441 DQM Delay:
6558 00:39:14.018298 DQM0 = 9, DQM1 = 14
6559 00:39:14.018708 DQ Delay:
6560 00:39:14.021676 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6561 00:39:14.024882 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6562 00:39:14.028068 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6563 00:39:14.031477 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6564 00:39:14.031882
6565 00:39:14.032199
6566 00:39:14.041622 [DQSOSCAuto] RK1, (LSB)MR18= 0x8d85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6567 00:39:14.042098 CH0 RK1: MR19=C0C, MR18=8D85
6568 00:39:14.048186 CH0_RK1: MR19=0xC0C, MR18=0x8D85, DQSOSC=392, MR23=63, INC=384, DEC=256
6569 00:39:14.051390 [RxdqsGatingPostProcess] freq 400
6570 00:39:14.057993 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 00:39:14.061454 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 00:39:14.064464 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 00:39:14.067829 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 00:39:14.070500 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 00:39:14.074107 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 00:39:14.077422 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 00:39:14.080358 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 00:39:14.083836 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 00:39:14.084028 Pre-setting of DQS Precalculation
6580 00:39:14.090267 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 00:39:14.090426 ==
6582 00:39:14.093833 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 00:39:14.096724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 00:39:14.096869 ==
6585 00:39:14.103542 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 00:39:14.109634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6587 00:39:14.113402 [CA 0] Center 36 (8~64) winsize 57
6588 00:39:14.116848 [CA 1] Center 36 (8~64) winsize 57
6589 00:39:14.119644 [CA 2] Center 36 (8~64) winsize 57
6590 00:39:14.123056 [CA 3] Center 36 (8~64) winsize 57
6591 00:39:14.126164 [CA 4] Center 36 (8~64) winsize 57
6592 00:39:14.129540 [CA 5] Center 36 (8~64) winsize 57
6593 00:39:14.129625
6594 00:39:14.132578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6595 00:39:14.132655
6596 00:39:14.136126 [CATrainingPosCal] consider 1 rank data
6597 00:39:14.139442 u2DelayCellTimex100 = 270/100 ps
6598 00:39:14.143107 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 00:39:14.146119 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 00:39:14.150002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 00:39:14.152752 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 00:39:14.155674 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 00:39:14.159633 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 00:39:14.159746
6605 00:39:14.165734 CA PerBit enable=1, Macro0, CA PI delay=36
6606 00:39:14.165823
6607 00:39:14.165886 [CBTSetCACLKResult] CA Dly = 36
6608 00:39:14.169398 CS Dly: 1 (0~32)
6609 00:39:14.169477 ==
6610 00:39:14.172638 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 00:39:14.175559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 00:39:14.175639 ==
6613 00:39:14.182200 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 00:39:14.188956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 00:39:14.192528 [CA 0] Center 36 (8~64) winsize 57
6616 00:39:14.195447 [CA 1] Center 36 (8~64) winsize 57
6617 00:39:14.198729 [CA 2] Center 36 (8~64) winsize 57
6618 00:39:14.201752 [CA 3] Center 36 (8~64) winsize 57
6619 00:39:14.205721 [CA 4] Center 36 (8~64) winsize 57
6620 00:39:14.205803 [CA 5] Center 36 (8~64) winsize 57
6621 00:39:14.205866
6622 00:39:14.212188 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 00:39:14.212273
6624 00:39:14.215650 [CATrainingPosCal] consider 2 rank data
6625 00:39:14.218582 u2DelayCellTimex100 = 270/100 ps
6626 00:39:14.222143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 00:39:14.225242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 00:39:14.228082 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 00:39:14.231484 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 00:39:14.234816 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 00:39:14.238512 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 00:39:14.238597
6633 00:39:14.241377 CA PerBit enable=1, Macro0, CA PI delay=36
6634 00:39:14.241462
6635 00:39:14.244783 [CBTSetCACLKResult] CA Dly = 36
6636 00:39:14.248145 CS Dly: 1 (0~32)
6637 00:39:14.248258
6638 00:39:14.251433 ----->DramcWriteLeveling(PI) begin...
6639 00:39:14.251539 ==
6640 00:39:14.255089 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 00:39:14.258191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 00:39:14.258269 ==
6643 00:39:14.261200 Write leveling (Byte 0): 40 => 8
6644 00:39:14.264988 Write leveling (Byte 1): 40 => 8
6645 00:39:14.267974 DramcWriteLeveling(PI) end<-----
6646 00:39:14.268066
6647 00:39:14.268138 ==
6648 00:39:14.271441 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 00:39:14.274606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 00:39:14.274707 ==
6651 00:39:14.277909 [Gating] SW mode calibration
6652 00:39:14.284673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 00:39:14.291307 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 00:39:14.294735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 00:39:14.300760 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 00:39:14.304319 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 00:39:14.307505 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 00:39:14.314141 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 00:39:14.317648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 00:39:14.320564 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 00:39:14.327409 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 00:39:14.330348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 00:39:14.333615 Total UI for P1: 0, mck2ui 16
6664 00:39:14.337216 best dqsien dly found for B0: ( 0, 14, 24)
6665 00:39:14.340608 Total UI for P1: 0, mck2ui 16
6666 00:39:14.343774 best dqsien dly found for B1: ( 0, 14, 24)
6667 00:39:14.346852 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 00:39:14.350087 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 00:39:14.350205
6670 00:39:14.353481 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 00:39:14.356933 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 00:39:14.360304 [Gating] SW calibration Done
6673 00:39:14.360424 ==
6674 00:39:14.363715 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 00:39:14.370461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 00:39:14.370576 ==
6677 00:39:14.370649 RX Vref Scan: 0
6678 00:39:14.370714
6679 00:39:14.373316 RX Vref 0 -> 0, step: 1
6680 00:39:14.373407
6681 00:39:14.376678 RX Delay -410 -> 252, step: 16
6682 00:39:14.380194 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6683 00:39:14.383025 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6684 00:39:14.389980 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6685 00:39:14.393245 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6686 00:39:14.396666 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6687 00:39:14.399619 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6688 00:39:14.406446 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6689 00:39:14.409623 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6690 00:39:14.412785 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6691 00:39:14.416525 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6692 00:39:14.422970 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6693 00:39:14.426382 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6694 00:39:14.429587 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6695 00:39:14.432660 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6696 00:39:14.439264 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6697 00:39:14.442607 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6698 00:39:14.442692 ==
6699 00:39:14.445769 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 00:39:14.449613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 00:39:14.449696 ==
6702 00:39:14.452579 DQS Delay:
6703 00:39:14.452658 DQS0 = 35, DQS1 = 51
6704 00:39:14.455561 DQM Delay:
6705 00:39:14.455640 DQM0 = 6, DQM1 = 13
6706 00:39:14.455703 DQ Delay:
6707 00:39:14.459279 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6708 00:39:14.462219 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6709 00:39:14.465658 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 00:39:14.469222 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6711 00:39:14.469358
6712 00:39:14.469457
6713 00:39:14.469519 ==
6714 00:39:14.472042 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 00:39:14.478861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 00:39:14.478945 ==
6717 00:39:14.479028
6718 00:39:14.479107
6719 00:39:14.479184 TX Vref Scan disable
6720 00:39:14.482439 == TX Byte 0 ==
6721 00:39:14.485339 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 00:39:14.488844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 00:39:14.491924 == TX Byte 1 ==
6724 00:39:14.495345 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 00:39:14.498559 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 00:39:14.502191 ==
6727 00:39:14.505323 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 00:39:14.508283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 00:39:14.508382 ==
6730 00:39:14.508455
6731 00:39:14.508522
6732 00:39:14.511852 TX Vref Scan disable
6733 00:39:14.511948 == TX Byte 0 ==
6734 00:39:14.515092 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 00:39:14.521598 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 00:39:14.521698 == TX Byte 1 ==
6737 00:39:14.524658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 00:39:14.531576 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 00:39:14.531739
6740 00:39:14.531833 [DATLAT]
6741 00:39:14.531904 Freq=400, CH1 RK0
6742 00:39:14.531972
6743 00:39:14.534574 DATLAT Default: 0xf
6744 00:39:14.538056 0, 0xFFFF, sum = 0
6745 00:39:14.538155 1, 0xFFFF, sum = 0
6746 00:39:14.541365 2, 0xFFFF, sum = 0
6747 00:39:14.541459 3, 0xFFFF, sum = 0
6748 00:39:14.544922 4, 0xFFFF, sum = 0
6749 00:39:14.545016 5, 0xFFFF, sum = 0
6750 00:39:14.548309 6, 0xFFFF, sum = 0
6751 00:39:14.548405 7, 0xFFFF, sum = 0
6752 00:39:14.551637 8, 0xFFFF, sum = 0
6753 00:39:14.551732 9, 0xFFFF, sum = 0
6754 00:39:14.554984 10, 0xFFFF, sum = 0
6755 00:39:14.555079 11, 0xFFFF, sum = 0
6756 00:39:14.558123 12, 0xFFFF, sum = 0
6757 00:39:14.558224 13, 0x0, sum = 1
6758 00:39:14.561615 14, 0x0, sum = 2
6759 00:39:14.561726 15, 0x0, sum = 3
6760 00:39:14.564687 16, 0x0, sum = 4
6761 00:39:14.564798 best_step = 14
6762 00:39:14.564884
6763 00:39:14.564965 ==
6764 00:39:14.567800 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 00:39:14.574463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 00:39:14.574601 ==
6767 00:39:14.574708 RX Vref Scan: 1
6768 00:39:14.574807
6769 00:39:14.578433 RX Vref 0 -> 0, step: 1
6770 00:39:14.578568
6771 00:39:14.581194 RX Delay -343 -> 252, step: 8
6772 00:39:14.581344
6773 00:39:14.584318 Set Vref, RX VrefLevel [Byte0]: 53
6774 00:39:14.587756 [Byte1]: 49
6775 00:39:14.587890
6776 00:39:14.590680 Final RX Vref Byte 0 = 53 to rank0
6777 00:39:14.594232 Final RX Vref Byte 1 = 49 to rank0
6778 00:39:14.597558 Final RX Vref Byte 0 = 53 to rank1
6779 00:39:14.600631 Final RX Vref Byte 1 = 49 to rank1==
6780 00:39:14.604247 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 00:39:14.607546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 00:39:14.610663 ==
6783 00:39:14.610748 DQS Delay:
6784 00:39:14.610814 DQS0 = 44, DQS1 = 56
6785 00:39:14.614047 DQM Delay:
6786 00:39:14.614130 DQM0 = 11, DQM1 = 14
6787 00:39:14.617107 DQ Delay:
6788 00:39:14.620497 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6789 00:39:14.620582 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6790 00:39:14.624264 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6791 00:39:14.627030 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6792 00:39:14.627111
6793 00:39:14.627174
6794 00:39:14.636759 [DQSOSCAuto] RK0, (LSB)MR18= 0x7097, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6795 00:39:14.640126 CH1 RK0: MR19=C0C, MR18=7097
6796 00:39:14.646666 CH1_RK0: MR19=0xC0C, MR18=0x7097, DQSOSC=390, MR23=63, INC=388, DEC=258
6797 00:39:14.646767 ==
6798 00:39:14.650329 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 00:39:14.653539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 00:39:14.653641 ==
6801 00:39:14.656547 [Gating] SW mode calibration
6802 00:39:14.663472 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 00:39:14.669643 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 00:39:14.673121 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 00:39:14.676269 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 00:39:14.683745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 00:39:14.686987 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 00:39:14.689978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 00:39:14.696411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 00:39:14.699872 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 00:39:14.702943 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 00:39:14.709351 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 00:39:14.709648 Total UI for P1: 0, mck2ui 16
6814 00:39:14.716103 best dqsien dly found for B0: ( 0, 14, 24)
6815 00:39:14.716285 Total UI for P1: 0, mck2ui 16
6816 00:39:14.722693 best dqsien dly found for B1: ( 0, 14, 24)
6817 00:39:14.726234 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 00:39:14.729254 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 00:39:14.729399
6820 00:39:14.732509 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 00:39:14.735822 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 00:39:14.739557 [Gating] SW calibration Done
6823 00:39:14.739659 ==
6824 00:39:14.742152 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 00:39:14.745424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 00:39:14.745519 ==
6827 00:39:14.748788 RX Vref Scan: 0
6828 00:39:14.748899
6829 00:39:14.748994 RX Vref 0 -> 0, step: 1
6830 00:39:14.752747
6831 00:39:14.752853 RX Delay -410 -> 252, step: 16
6832 00:39:14.758837 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6833 00:39:14.762229 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6834 00:39:14.765728 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6835 00:39:14.768819 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6836 00:39:14.775661 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6837 00:39:14.779053 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6838 00:39:14.782409 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6839 00:39:14.785179 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6840 00:39:14.792073 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6841 00:39:14.795385 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6842 00:39:14.798499 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6843 00:39:14.801716 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6844 00:39:14.808798 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6845 00:39:14.811835 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6846 00:39:14.815222 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6847 00:39:14.821633 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6848 00:39:14.821735 ==
6849 00:39:14.825076 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 00:39:14.828706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 00:39:14.828817 ==
6852 00:39:14.828904 DQS Delay:
6853 00:39:14.831424 DQS0 = 43, DQS1 = 51
6854 00:39:14.831544 DQM Delay:
6855 00:39:14.835059 DQM0 = 9, DQM1 = 12
6856 00:39:14.835253 DQ Delay:
6857 00:39:14.838130 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6858 00:39:14.841559 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6859 00:39:14.844730 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6860 00:39:14.848131 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6861 00:39:14.848313
6862 00:39:14.848496
6863 00:39:14.848663 ==
6864 00:39:14.851623 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 00:39:14.854719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 00:39:14.854925 ==
6867 00:39:14.855131
6868 00:39:14.855353
6869 00:39:14.857905 TX Vref Scan disable
6870 00:39:14.858239 == TX Byte 0 ==
6871 00:39:14.864609 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6872 00:39:14.868167 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6873 00:39:14.868560 == TX Byte 1 ==
6874 00:39:14.874799 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6875 00:39:14.878566 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6876 00:39:14.878994 ==
6877 00:39:14.881251 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 00:39:14.884780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 00:39:14.885206 ==
6880 00:39:14.885674
6881 00:39:14.886080
6882 00:39:14.887923 TX Vref Scan disable
6883 00:39:14.891301 == TX Byte 0 ==
6884 00:39:14.895001 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6885 00:39:14.897902 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6886 00:39:14.898329 == TX Byte 1 ==
6887 00:39:14.904732 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 00:39:14.908146 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 00:39:14.908571
6890 00:39:14.908998 [DATLAT]
6891 00:39:14.911494 Freq=400, CH1 RK1
6892 00:39:14.911918
6893 00:39:14.912356 DATLAT Default: 0xe
6894 00:39:14.914601 0, 0xFFFF, sum = 0
6895 00:39:14.915034 1, 0xFFFF, sum = 0
6896 00:39:14.918056 2, 0xFFFF, sum = 0
6897 00:39:14.918490 3, 0xFFFF, sum = 0
6898 00:39:14.921095 4, 0xFFFF, sum = 0
6899 00:39:14.924465 5, 0xFFFF, sum = 0
6900 00:39:14.924774 6, 0xFFFF, sum = 0
6901 00:39:14.927411 7, 0xFFFF, sum = 0
6902 00:39:14.927643 8, 0xFFFF, sum = 0
6903 00:39:14.930876 9, 0xFFFF, sum = 0
6904 00:39:14.931063 10, 0xFFFF, sum = 0
6905 00:39:14.934463 11, 0xFFFF, sum = 0
6906 00:39:14.934651 12, 0xFFFF, sum = 0
6907 00:39:14.937480 13, 0x0, sum = 1
6908 00:39:14.937638 14, 0x0, sum = 2
6909 00:39:14.940962 15, 0x0, sum = 3
6910 00:39:14.941095 16, 0x0, sum = 4
6911 00:39:14.943756 best_step = 14
6912 00:39:14.943887
6913 00:39:14.944019 ==
6914 00:39:14.947325 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 00:39:14.950820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 00:39:14.950926 ==
6917 00:39:14.953857 RX Vref Scan: 0
6918 00:39:14.953960
6919 00:39:14.954064 RX Vref 0 -> 0, step: 1
6920 00:39:14.954162
6921 00:39:14.957234 RX Delay -343 -> 252, step: 8
6922 00:39:14.964453 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6923 00:39:14.968054 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6924 00:39:14.971406 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6925 00:39:14.977715 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6926 00:39:14.980905 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6927 00:39:14.984869 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6928 00:39:14.987931 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6929 00:39:14.994175 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6930 00:39:14.997696 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6931 00:39:15.000964 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6932 00:39:15.003983 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6933 00:39:15.010977 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6934 00:39:15.014120 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6935 00:39:15.017182 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6936 00:39:15.023828 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6937 00:39:15.026932 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6938 00:39:15.027213 ==
6939 00:39:15.030511 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 00:39:15.033747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 00:39:15.034113 ==
6942 00:39:15.037323 DQS Delay:
6943 00:39:15.037799 DQS0 = 48, DQS1 = 56
6944 00:39:15.038227 DQM Delay:
6945 00:39:15.040303 DQM0 = 11, DQM1 = 14
6946 00:39:15.040724 DQ Delay:
6947 00:39:15.043984 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6948 00:39:15.046998 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6949 00:39:15.050642 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6950 00:39:15.053974 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6951 00:39:15.054398
6952 00:39:15.054851
6953 00:39:15.063732 [DQSOSCAuto] RK1, (LSB)MR18= 0x80b8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 393 ps
6954 00:39:15.064144 CH1 RK1: MR19=C0C, MR18=80B8
6955 00:39:15.070051 CH1_RK1: MR19=0xC0C, MR18=0x80B8, DQSOSC=386, MR23=63, INC=396, DEC=264
6956 00:39:15.073511 [RxdqsGatingPostProcess] freq 400
6957 00:39:15.079729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 00:39:15.083311 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 00:39:15.086683 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 00:39:15.089979 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 00:39:15.093383 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 00:39:15.096740 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 00:39:15.099662 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 00:39:15.102780 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 00:39:15.106206 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 00:39:15.106634 Pre-setting of DQS Precalculation
6967 00:39:15.112966 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 00:39:15.119542 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 00:39:15.125984 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 00:39:15.126410
6971 00:39:15.129380
6972 00:39:15.129801 [Calibration Summary] 800 Mbps
6973 00:39:15.132733 CH 0, Rank 0
6974 00:39:15.133155 SW Impedance : PASS
6975 00:39:15.136007 DUTY Scan : NO K
6976 00:39:15.139309 ZQ Calibration : PASS
6977 00:39:15.139855 Jitter Meter : NO K
6978 00:39:15.142666 CBT Training : PASS
6979 00:39:15.145501 Write leveling : PASS
6980 00:39:15.145916 RX DQS gating : PASS
6981 00:39:15.148881 RX DQ/DQS(RDDQC) : PASS
6982 00:39:15.151970 TX DQ/DQS : PASS
6983 00:39:15.152387 RX DATLAT : PASS
6984 00:39:15.155431 RX DQ/DQS(Engine): PASS
6985 00:39:15.158877 TX OE : NO K
6986 00:39:15.159320 All Pass.
6987 00:39:15.159748
6988 00:39:15.160154 CH 0, Rank 1
6989 00:39:15.162418 SW Impedance : PASS
6990 00:39:15.165250 DUTY Scan : NO K
6991 00:39:15.165715 ZQ Calibration : PASS
6992 00:39:15.168693 Jitter Meter : NO K
6993 00:39:15.172018 CBT Training : PASS
6994 00:39:15.172427 Write leveling : NO K
6995 00:39:15.175399 RX DQS gating : PASS
6996 00:39:15.178952 RX DQ/DQS(RDDQC) : PASS
6997 00:39:15.179363 TX DQ/DQS : PASS
6998 00:39:15.181808 RX DATLAT : PASS
6999 00:39:15.182216 RX DQ/DQS(Engine): PASS
7000 00:39:15.185122 TX OE : NO K
7001 00:39:15.185560 All Pass.
7002 00:39:15.185882
7003 00:39:15.188317 CH 1, Rank 0
7004 00:39:15.191500 SW Impedance : PASS
7005 00:39:15.191913 DUTY Scan : NO K
7006 00:39:15.195246 ZQ Calibration : PASS
7007 00:39:15.195742 Jitter Meter : NO K
7008 00:39:15.198455 CBT Training : PASS
7009 00:39:15.201962 Write leveling : PASS
7010 00:39:15.202441 RX DQS gating : PASS
7011 00:39:15.205604 RX DQ/DQS(RDDQC) : PASS
7012 00:39:15.208108 TX DQ/DQS : PASS
7013 00:39:15.208522 RX DATLAT : PASS
7014 00:39:15.211601 RX DQ/DQS(Engine): PASS
7015 00:39:15.215139 TX OE : NO K
7016 00:39:15.215641 All Pass.
7017 00:39:15.215966
7018 00:39:15.216266 CH 1, Rank 1
7019 00:39:15.218544 SW Impedance : PASS
7020 00:39:15.221390 DUTY Scan : NO K
7021 00:39:15.221801 ZQ Calibration : PASS
7022 00:39:15.224826 Jitter Meter : NO K
7023 00:39:15.228186 CBT Training : PASS
7024 00:39:15.228643 Write leveling : NO K
7025 00:39:15.231685 RX DQS gating : PASS
7026 00:39:15.234735 RX DQ/DQS(RDDQC) : PASS
7027 00:39:15.235182 TX DQ/DQS : PASS
7028 00:39:15.237994 RX DATLAT : PASS
7029 00:39:15.241678 RX DQ/DQS(Engine): PASS
7030 00:39:15.242102 TX OE : NO K
7031 00:39:15.242532 All Pass.
7032 00:39:15.244772
7033 00:39:15.245195 DramC Write-DBI off
7034 00:39:15.248082 PER_BANK_REFRESH: Hybrid Mode
7035 00:39:15.248606 TX_TRACKING: ON
7036 00:39:15.258080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 00:39:15.261094 [FAST_K] Save calibration result to emmc
7038 00:39:15.264794 dramc_set_vcore_voltage set vcore to 725000
7039 00:39:15.267497 Read voltage for 1600, 0
7040 00:39:15.267919 Vio18 = 0
7041 00:39:15.271195 Vcore = 725000
7042 00:39:15.271651 Vdram = 0
7043 00:39:15.272083 Vddq = 0
7044 00:39:15.274403 Vmddr = 0
7045 00:39:15.278187 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 00:39:15.284289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 00:39:15.284811 MEM_TYPE=3, freq_sel=13
7048 00:39:15.287626 sv_algorithm_assistance_LP4_3733
7049 00:39:15.294557 ============ PULL DRAM RESETB DOWN ============
7050 00:39:15.297756 ========== PULL DRAM RESETB DOWN end =========
7051 00:39:15.301233 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 00:39:15.304334 ===================================
7053 00:39:15.307043 LPDDR4 DRAM CONFIGURATION
7054 00:39:15.310783 ===================================
7055 00:39:15.311207 EX_ROW_EN[0] = 0x0
7056 00:39:15.314434 EX_ROW_EN[1] = 0x0
7057 00:39:15.317011 LP4Y_EN = 0x0
7058 00:39:15.317467 WORK_FSP = 0x1
7059 00:39:15.320795 WL = 0x5
7060 00:39:15.321219 RL = 0x5
7061 00:39:15.323615 BL = 0x2
7062 00:39:15.324037 RPST = 0x0
7063 00:39:15.326886 RD_PRE = 0x0
7064 00:39:15.327311 WR_PRE = 0x1
7065 00:39:15.330540 WR_PST = 0x1
7066 00:39:15.330963 DBI_WR = 0x0
7067 00:39:15.333744 DBI_RD = 0x0
7068 00:39:15.334167 OTF = 0x1
7069 00:39:15.336821 ===================================
7070 00:39:15.340657 ===================================
7071 00:39:15.343322 ANA top config
7072 00:39:15.346811 ===================================
7073 00:39:15.350488 DLL_ASYNC_EN = 0
7074 00:39:15.351035 ALL_SLAVE_EN = 0
7075 00:39:15.353335 NEW_RANK_MODE = 1
7076 00:39:15.357006 DLL_IDLE_MODE = 1
7077 00:39:15.359842 LP45_APHY_COMB_EN = 1
7078 00:39:15.360424 TX_ODT_DIS = 0
7079 00:39:15.363703 NEW_8X_MODE = 1
7080 00:39:15.366938 ===================================
7081 00:39:15.369770 ===================================
7082 00:39:15.373241 data_rate = 3200
7083 00:39:15.376580 CKR = 1
7084 00:39:15.380204 DQ_P2S_RATIO = 8
7085 00:39:15.383595 ===================================
7086 00:39:15.386027 CA_P2S_RATIO = 8
7087 00:39:15.389519 DQ_CA_OPEN = 0
7088 00:39:15.389947 DQ_SEMI_OPEN = 0
7089 00:39:15.393251 CA_SEMI_OPEN = 0
7090 00:39:15.396687 CA_FULL_RATE = 0
7091 00:39:15.399543 DQ_CKDIV4_EN = 0
7092 00:39:15.402779 CA_CKDIV4_EN = 0
7093 00:39:15.405958 CA_PREDIV_EN = 0
7094 00:39:15.406531 PH8_DLY = 12
7095 00:39:15.409340 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 00:39:15.412533 DQ_AAMCK_DIV = 4
7097 00:39:15.416275 CA_AAMCK_DIV = 4
7098 00:39:15.419646 CA_ADMCK_DIV = 4
7099 00:39:15.422502 DQ_TRACK_CA_EN = 0
7100 00:39:15.422911 CA_PICK = 1600
7101 00:39:15.426088 CA_MCKIO = 1600
7102 00:39:15.428965 MCKIO_SEMI = 0
7103 00:39:15.432276 PLL_FREQ = 3068
7104 00:39:15.435874 DQ_UI_PI_RATIO = 32
7105 00:39:15.439223 CA_UI_PI_RATIO = 0
7106 00:39:15.442392 ===================================
7107 00:39:15.445552 ===================================
7108 00:39:15.448770 memory_type:LPDDR4
7109 00:39:15.449282 GP_NUM : 10
7110 00:39:15.452371 SRAM_EN : 1
7111 00:39:15.452774 MD32_EN : 0
7112 00:39:15.455475 ===================================
7113 00:39:15.458909 [ANA_INIT] >>>>>>>>>>>>>>
7114 00:39:15.461956 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 00:39:15.465212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 00:39:15.469003 ===================================
7117 00:39:15.472120 data_rate = 3200,PCW = 0X7600
7118 00:39:15.475532 ===================================
7119 00:39:15.478689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 00:39:15.484905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 00:39:15.488332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 00:39:15.494979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 00:39:15.497805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 00:39:15.501754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 00:39:15.502261 [ANA_INIT] flow start
7126 00:39:15.504685 [ANA_INIT] PLL >>>>>>>>
7127 00:39:15.508064 [ANA_INIT] PLL <<<<<<<<
7128 00:39:15.511968 [ANA_INIT] MIDPI >>>>>>>>
7129 00:39:15.512477 [ANA_INIT] MIDPI <<<<<<<<
7130 00:39:15.515245 [ANA_INIT] DLL >>>>>>>>
7131 00:39:15.517785 [ANA_INIT] DLL <<<<<<<<
7132 00:39:15.518196 [ANA_INIT] flow end
7133 00:39:15.521214 ============ LP4 DIFF to SE enter ============
7134 00:39:15.527536 ============ LP4 DIFF to SE exit ============
7135 00:39:15.527944 [ANA_INIT] <<<<<<<<<<<<<
7136 00:39:15.531052 [Flow] Enable top DCM control >>>>>
7137 00:39:15.534138 [Flow] Enable top DCM control <<<<<
7138 00:39:15.537562 Enable DLL master slave shuffle
7139 00:39:15.544384 ==============================================================
7140 00:39:15.547674 Gating Mode config
7141 00:39:15.551137 ==============================================================
7142 00:39:15.554556 Config description:
7143 00:39:15.564122 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 00:39:15.570654 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 00:39:15.574164 SELPH_MODE 0: By rank 1: By Phase
7146 00:39:15.580159 ==============================================================
7147 00:39:15.583583 GAT_TRACK_EN = 1
7148 00:39:15.587170 RX_GATING_MODE = 2
7149 00:39:15.590211 RX_GATING_TRACK_MODE = 2
7150 00:39:15.593711 SELPH_MODE = 1
7151 00:39:15.594117 PICG_EARLY_EN = 1
7152 00:39:15.597381 VALID_LAT_VALUE = 1
7153 00:39:15.603379 ==============================================================
7154 00:39:15.606907 Enter into Gating configuration >>>>
7155 00:39:15.609835 Exit from Gating configuration <<<<
7156 00:39:15.613218 Enter into DVFS_PRE_config >>>>>
7157 00:39:15.623144 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 00:39:15.626866 Exit from DVFS_PRE_config <<<<<
7159 00:39:15.629701 Enter into PICG configuration >>>>
7160 00:39:15.633581 Exit from PICG configuration <<<<
7161 00:39:15.636404 [RX_INPUT] configuration >>>>>
7162 00:39:15.639887 [RX_INPUT] configuration <<<<<
7163 00:39:15.643003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 00:39:15.649616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 00:39:15.656251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 00:39:15.662766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 00:39:15.669723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 00:39:15.675980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 00:39:15.679456 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 00:39:15.682284 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 00:39:15.685750 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 00:39:15.692316 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 00:39:15.695596 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 00:39:15.698934 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 00:39:15.702387 ===================================
7176 00:39:15.705637 LPDDR4 DRAM CONFIGURATION
7177 00:39:15.709432 ===================================
7178 00:39:15.709846 EX_ROW_EN[0] = 0x0
7179 00:39:15.712022 EX_ROW_EN[1] = 0x0
7180 00:39:15.715665 LP4Y_EN = 0x0
7181 00:39:15.716094 WORK_FSP = 0x1
7182 00:39:15.718944 WL = 0x5
7183 00:39:15.719402 RL = 0x5
7184 00:39:15.721962 BL = 0x2
7185 00:39:15.722644 RPST = 0x0
7186 00:39:15.725336 RD_PRE = 0x0
7187 00:39:15.725851 WR_PRE = 0x1
7188 00:39:15.728658 WR_PST = 0x1
7189 00:39:15.729142 DBI_WR = 0x0
7190 00:39:15.731725 DBI_RD = 0x0
7191 00:39:15.732260 OTF = 0x1
7192 00:39:15.735291 ===================================
7193 00:39:15.741804 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 00:39:15.745205 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 00:39:15.748548 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 00:39:15.751374 ===================================
7197 00:39:15.754823 LPDDR4 DRAM CONFIGURATION
7198 00:39:15.758370 ===================================
7199 00:39:15.761656 EX_ROW_EN[0] = 0x10
7200 00:39:15.762162 EX_ROW_EN[1] = 0x0
7201 00:39:15.764775 LP4Y_EN = 0x0
7202 00:39:15.765413 WORK_FSP = 0x1
7203 00:39:15.768220 WL = 0x5
7204 00:39:15.768753 RL = 0x5
7205 00:39:15.771608 BL = 0x2
7206 00:39:15.772018 RPST = 0x0
7207 00:39:15.774507 RD_PRE = 0x0
7208 00:39:15.774969 WR_PRE = 0x1
7209 00:39:15.777760 WR_PST = 0x1
7210 00:39:15.778205 DBI_WR = 0x0
7211 00:39:15.781117 DBI_RD = 0x0
7212 00:39:15.781573 OTF = 0x1
7213 00:39:15.784486 ===================================
7214 00:39:15.791185 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 00:39:15.791625 ==
7216 00:39:15.794199 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 00:39:15.800754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 00:39:15.801364 ==
7219 00:39:15.801709 [Duty_Offset_Calibration]
7220 00:39:15.804461 B0:2 B1:0 CA:4
7221 00:39:15.804867
7222 00:39:15.807527 [DutyScan_Calibration_Flow] k_type=0
7223 00:39:15.816600
7224 00:39:15.817123 ==CLK 0==
7225 00:39:15.819516 Final CLK duty delay cell = -4
7226 00:39:15.823399 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7227 00:39:15.826084 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7228 00:39:15.829709 [-4] AVG Duty = 4937%(X100)
7229 00:39:15.830120
7230 00:39:15.833179 CH0 CLK Duty spec in!! Max-Min= 187%
7231 00:39:15.836060 [DutyScan_Calibration_Flow] ====Done====
7232 00:39:15.836477
7233 00:39:15.839384 [DutyScan_Calibration_Flow] k_type=1
7234 00:39:15.856490
7235 00:39:15.857160 ==DQS 0 ==
7236 00:39:15.860105 Final DQS duty delay cell = 0
7237 00:39:15.863032 [0] MAX Duty = 5218%(X100), DQS PI = 38
7238 00:39:15.866355 [0] MIN Duty = 5093%(X100), DQS PI = 6
7239 00:39:15.869561 [0] AVG Duty = 5155%(X100)
7240 00:39:15.869974
7241 00:39:15.870294 ==DQS 1 ==
7242 00:39:15.872949 Final DQS duty delay cell = 0
7243 00:39:15.876263 [0] MAX Duty = 5156%(X100), DQS PI = 0
7244 00:39:15.880146 [0] MIN Duty = 4969%(X100), DQS PI = 10
7245 00:39:15.882753 [0] AVG Duty = 5062%(X100)
7246 00:39:15.883160
7247 00:39:15.886395 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7248 00:39:15.886835
7249 00:39:15.889431 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7250 00:39:15.892932 [DutyScan_Calibration_Flow] ====Done====
7251 00:39:15.893389
7252 00:39:15.896488 [DutyScan_Calibration_Flow] k_type=3
7253 00:39:15.913709
7254 00:39:15.914185 ==DQM 0 ==
7255 00:39:15.917222 Final DQM duty delay cell = 0
7256 00:39:15.920362 [0] MAX Duty = 5124%(X100), DQS PI = 22
7257 00:39:15.923840 [0] MIN Duty = 4875%(X100), DQS PI = 54
7258 00:39:15.927044 [0] AVG Duty = 4999%(X100)
7259 00:39:15.927518
7260 00:39:15.927846 ==DQM 1 ==
7261 00:39:15.930418 Final DQM duty delay cell = 0
7262 00:39:15.933688 [0] MAX Duty = 5000%(X100), DQS PI = 4
7263 00:39:15.936722 [0] MIN Duty = 4844%(X100), DQS PI = 14
7264 00:39:15.940273 [0] AVG Duty = 4922%(X100)
7265 00:39:15.940757
7266 00:39:15.943121 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7267 00:39:15.943536
7268 00:39:15.946867 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7269 00:39:15.950063 [DutyScan_Calibration_Flow] ====Done====
7270 00:39:15.950477
7271 00:39:15.952795 [DutyScan_Calibration_Flow] k_type=2
7272 00:39:15.970563
7273 00:39:15.970979 ==DQ 0 ==
7274 00:39:15.973930 Final DQ duty delay cell = 0
7275 00:39:15.977490 [0] MAX Duty = 5124%(X100), DQS PI = 22
7276 00:39:15.980800 [0] MIN Duty = 4938%(X100), DQS PI = 12
7277 00:39:15.981212 [0] AVG Duty = 5031%(X100)
7278 00:39:15.981582
7279 00:39:15.983941 ==DQ 1 ==
7280 00:39:15.987456 Final DQ duty delay cell = 0
7281 00:39:15.990539 [0] MAX Duty = 5187%(X100), DQS PI = 2
7282 00:39:15.994007 [0] MIN Duty = 4938%(X100), DQS PI = 12
7283 00:39:15.994419 [0] AVG Duty = 5062%(X100)
7284 00:39:15.994743
7285 00:39:15.997528 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7286 00:39:16.000831
7287 00:39:16.003927 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7288 00:39:16.007142 [DutyScan_Calibration_Flow] ====Done====
7289 00:39:16.007550 ==
7290 00:39:16.010486 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 00:39:16.013414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 00:39:16.013835 ==
7293 00:39:16.016820 [Duty_Offset_Calibration]
7294 00:39:16.017380 B0:0 B1:-1 CA:3
7295 00:39:16.017828
7296 00:39:16.020364 [DutyScan_Calibration_Flow] k_type=0
7297 00:39:16.029913
7298 00:39:16.030340 ==CLK 0==
7299 00:39:16.033411 Final CLK duty delay cell = -4
7300 00:39:16.037138 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7301 00:39:16.040404 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7302 00:39:16.043304 [-4] AVG Duty = 4906%(X100)
7303 00:39:16.043810
7304 00:39:16.046639 CH1 CLK Duty spec in!! Max-Min= 187%
7305 00:39:16.049558 [DutyScan_Calibration_Flow] ====Done====
7306 00:39:16.049965
7307 00:39:16.052995 [DutyScan_Calibration_Flow] k_type=1
7308 00:39:16.069389
7309 00:39:16.069940 ==DQS 0 ==
7310 00:39:16.072452 Final DQS duty delay cell = 0
7311 00:39:16.076084 [0] MAX Duty = 5218%(X100), DQS PI = 20
7312 00:39:16.079496 [0] MIN Duty = 4907%(X100), DQS PI = 60
7313 00:39:16.082367 [0] AVG Duty = 5062%(X100)
7314 00:39:16.082907
7315 00:39:16.083369 ==DQS 1 ==
7316 00:39:16.085981 Final DQS duty delay cell = -4
7317 00:39:16.088921 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7318 00:39:16.092823 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7319 00:39:16.096057 [-4] AVG Duty = 4922%(X100)
7320 00:39:16.096598
7321 00:39:16.098953 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7322 00:39:16.099359
7323 00:39:16.102616 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7324 00:39:16.105432 [DutyScan_Calibration_Flow] ====Done====
7325 00:39:16.105908
7326 00:39:16.108866 [DutyScan_Calibration_Flow] k_type=3
7327 00:39:16.126312
7328 00:39:16.126800 ==DQM 0 ==
7329 00:39:16.129679 Final DQM duty delay cell = 0
7330 00:39:16.133035 [0] MAX Duty = 5062%(X100), DQS PI = 30
7331 00:39:16.136546 [0] MIN Duty = 4750%(X100), DQS PI = 40
7332 00:39:16.139929 [0] AVG Duty = 4906%(X100)
7333 00:39:16.140337
7334 00:39:16.140659 ==DQM 1 ==
7335 00:39:16.143753 Final DQM duty delay cell = 0
7336 00:39:16.146860 [0] MAX Duty = 5000%(X100), DQS PI = 34
7337 00:39:16.150033 [0] MIN Duty = 4844%(X100), DQS PI = 0
7338 00:39:16.152827 [0] AVG Duty = 4922%(X100)
7339 00:39:16.153234
7340 00:39:16.156777 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7341 00:39:16.157185
7342 00:39:16.159578 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7343 00:39:16.163253 [DutyScan_Calibration_Flow] ====Done====
7344 00:39:16.163664
7345 00:39:16.166038 [DutyScan_Calibration_Flow] k_type=2
7346 00:39:16.183074
7347 00:39:16.183556 ==DQ 0 ==
7348 00:39:16.185969 Final DQ duty delay cell = -4
7349 00:39:16.188938 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7350 00:39:16.192794 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7351 00:39:16.196101 [-4] AVG Duty = 4891%(X100)
7352 00:39:16.196630
7353 00:39:16.196960 ==DQ 1 ==
7354 00:39:16.199085 Final DQ duty delay cell = 0
7355 00:39:16.202547 [0] MAX Duty = 5062%(X100), DQS PI = 32
7356 00:39:16.206203 [0] MIN Duty = 4875%(X100), DQS PI = 0
7357 00:39:16.208802 [0] AVG Duty = 4968%(X100)
7358 00:39:16.209215
7359 00:39:16.212208 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7360 00:39:16.212615
7361 00:39:16.215838 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7362 00:39:16.219081 [DutyScan_Calibration_Flow] ====Done====
7363 00:39:16.222787 nWR fixed to 30
7364 00:39:16.226291 [ModeRegInit_LP4] CH0 RK0
7365 00:39:16.226972 [ModeRegInit_LP4] CH0 RK1
7366 00:39:16.229096 [ModeRegInit_LP4] CH1 RK0
7367 00:39:16.232031 [ModeRegInit_LP4] CH1 RK1
7368 00:39:16.232439 match AC timing 5
7369 00:39:16.239131 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 00:39:16.241839 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 00:39:16.245709 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 00:39:16.251943 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 00:39:16.255051 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 00:39:16.255465 [MiockJmeterHQA]
7375 00:39:16.258479
7376 00:39:16.258931 [DramcMiockJmeter] u1RxGatingPI = 0
7377 00:39:16.261417 0 : 4363, 4137
7378 00:39:16.261836 4 : 4363, 4137
7379 00:39:16.264810 8 : 4250, 4025
7380 00:39:16.265221 12 : 4368, 4140
7381 00:39:16.268834 16 : 4253, 4027
7382 00:39:16.269249 20 : 4255, 4029
7383 00:39:16.271684 24 : 4363, 4138
7384 00:39:16.272098 28 : 4252, 4027
7385 00:39:16.272426 32 : 4255, 4029
7386 00:39:16.275055 36 : 4252, 4027
7387 00:39:16.275468 40 : 4253, 4026
7388 00:39:16.277989 44 : 4250, 4026
7389 00:39:16.278402 48 : 4253, 4026
7390 00:39:16.281552 52 : 4250, 4026
7391 00:39:16.281964 56 : 4361, 4137
7392 00:39:16.285243 60 : 4250, 4026
7393 00:39:16.285805 64 : 4250, 4027
7394 00:39:16.286146 68 : 4252, 4029
7395 00:39:16.288234 72 : 4250, 4027
7396 00:39:16.288658 76 : 4360, 4138
7397 00:39:16.292158 80 : 4250, 4027
7398 00:39:16.292671 84 : 4363, 4140
7399 00:39:16.294624 88 : 4250, 4027
7400 00:39:16.295042 92 : 4250, 4027
7401 00:39:16.295373 96 : 4253, 2666
7402 00:39:16.297912 100 : 4250, 0
7403 00:39:16.298332 104 : 4250, 0
7404 00:39:16.301472 108 : 4250, 0
7405 00:39:16.301893 112 : 4250, 0
7406 00:39:16.302221 116 : 4361, 0
7407 00:39:16.304886 120 : 4360, 0
7408 00:39:16.305451 124 : 4250, 0
7409 00:39:16.307957 128 : 4249, 0
7410 00:39:16.308523 132 : 4360, 0
7411 00:39:16.308886 136 : 4361, 0
7412 00:39:16.311505 140 : 4252, 0
7413 00:39:16.311972 144 : 4249, 0
7414 00:39:16.315054 148 : 4250, 0
7415 00:39:16.315629 152 : 4253, 0
7416 00:39:16.315969 156 : 4249, 0
7417 00:39:16.318406 160 : 4250, 0
7418 00:39:16.318915 164 : 4250, 0
7419 00:39:16.320979 168 : 4361, 0
7420 00:39:16.321428 172 : 4365, 0
7421 00:39:16.321812 176 : 4250, 0
7422 00:39:16.324642 180 : 4250, 0
7423 00:39:16.325130 184 : 4250, 0
7424 00:39:16.327423 188 : 4361, 0
7425 00:39:16.327837 192 : 4250, 0
7426 00:39:16.328165 196 : 4250, 0
7427 00:39:16.331019 200 : 4250, 0
7428 00:39:16.331436 204 : 4253, 0
7429 00:39:16.331764 208 : 4249, 0
7430 00:39:16.334114 212 : 4250, 0
7431 00:39:16.334534 216 : 4255, 0
7432 00:39:16.337540 220 : 4363, 406
7433 00:39:16.337955 224 : 4250, 3990
7434 00:39:16.340884 228 : 4250, 4027
7435 00:39:16.341333 232 : 4250, 4027
7436 00:39:16.344073 236 : 4250, 4027
7437 00:39:16.344560 240 : 4252, 4029
7438 00:39:16.347562 244 : 4250, 4027
7439 00:39:16.347983 248 : 4360, 4138
7440 00:39:16.348316 252 : 4250, 4027
7441 00:39:16.351017 256 : 4250, 4026
7442 00:39:16.351435 260 : 4250, 4027
7443 00:39:16.353738 264 : 4363, 4140
7444 00:39:16.354161 268 : 4361, 4138
7445 00:39:16.357081 272 : 4250, 4027
7446 00:39:16.357537 276 : 4363, 4139
7447 00:39:16.360622 280 : 4253, 4029
7448 00:39:16.361043 284 : 4250, 4027
7449 00:39:16.363588 288 : 4250, 4027
7450 00:39:16.364008 292 : 4253, 4029
7451 00:39:16.367080 296 : 4253, 4029
7452 00:39:16.367495 300 : 4363, 4140
7453 00:39:16.370663 304 : 4249, 4027
7454 00:39:16.371083 308 : 4250, 4026
7455 00:39:16.373716 312 : 4250, 4026
7456 00:39:16.374137 316 : 4363, 4140
7457 00:39:16.374471 320 : 4360, 4138
7458 00:39:16.377300 324 : 4248, 4024
7459 00:39:16.377724 328 : 4363, 4139
7460 00:39:16.380199 332 : 4253, 3999
7461 00:39:16.380632 336 : 4250, 1842
7462 00:39:16.381149
7463 00:39:16.383685 MIOCK jitter meter ch=0
7464 00:39:16.384096
7465 00:39:16.386673 1T = (336-100) = 236 dly cells
7466 00:39:16.393599 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7467 00:39:16.394098 ==
7468 00:39:16.396835 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 00:39:16.400241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7470 00:39:16.400720 ==
7471 00:39:16.407165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7472 00:39:16.409815 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7473 00:39:16.413543 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7474 00:39:16.419826 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7475 00:39:16.429334 [CA 0] Center 43 (13~73) winsize 61
7476 00:39:16.432558 [CA 1] Center 43 (13~73) winsize 61
7477 00:39:16.436050 [CA 2] Center 38 (9~67) winsize 59
7478 00:39:16.439049 [CA 3] Center 37 (8~67) winsize 60
7479 00:39:16.441999 [CA 4] Center 35 (6~65) winsize 60
7480 00:39:16.446080 [CA 5] Center 35 (5~66) winsize 62
7481 00:39:16.446587
7482 00:39:16.448941 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7483 00:39:16.449391
7484 00:39:16.455677 [CATrainingPosCal] consider 1 rank data
7485 00:39:16.456170 u2DelayCellTimex100 = 275/100 ps
7486 00:39:16.462644 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7487 00:39:16.465544 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7488 00:39:16.469070 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7489 00:39:16.472323 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7490 00:39:16.475487 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7491 00:39:16.478839 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7492 00:39:16.479252
7493 00:39:16.481589 CA PerBit enable=1, Macro0, CA PI delay=35
7494 00:39:16.482004
7495 00:39:16.485433 [CBTSetCACLKResult] CA Dly = 35
7496 00:39:16.488935 CS Dly: 10 (0~41)
7497 00:39:16.492004 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7498 00:39:16.495092 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7499 00:39:16.495643 ==
7500 00:39:16.498584 Dram Type= 6, Freq= 0, CH_0, rank 1
7501 00:39:16.505351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 00:39:16.505976 ==
7503 00:39:16.508393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 00:39:16.514840 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 00:39:16.518193 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 00:39:16.524384 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 00:39:16.533408 [CA 0] Center 43 (13~74) winsize 62
7508 00:39:16.536180 [CA 1] Center 43 (13~73) winsize 61
7509 00:39:16.539493 [CA 2] Center 38 (9~68) winsize 60
7510 00:39:16.542512 [CA 3] Center 38 (9~68) winsize 60
7511 00:39:16.546323 [CA 4] Center 36 (6~67) winsize 62
7512 00:39:16.549449 [CA 5] Center 36 (6~66) winsize 61
7513 00:39:16.549991
7514 00:39:16.553082 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 00:39:16.553690
7516 00:39:16.555622 [CATrainingPosCal] consider 2 rank data
7517 00:39:16.559188 u2DelayCellTimex100 = 275/100 ps
7518 00:39:16.565502 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7519 00:39:16.569024 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7520 00:39:16.572851 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7521 00:39:16.576102 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7522 00:39:16.578661 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7523 00:39:16.582003 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
7524 00:39:16.582550
7525 00:39:16.585430 CA PerBit enable=1, Macro0, CA PI delay=35
7526 00:39:16.585977
7527 00:39:16.588609 [CBTSetCACLKResult] CA Dly = 35
7528 00:39:16.592396 CS Dly: 11 (0~44)
7529 00:39:16.595591 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 00:39:16.598639 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 00:39:16.599187
7532 00:39:16.601852 ----->DramcWriteLeveling(PI) begin...
7533 00:39:16.602312 ==
7534 00:39:16.605309 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 00:39:16.612231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 00:39:16.612780 ==
7537 00:39:16.615598 Write leveling (Byte 0): 35 => 35
7538 00:39:16.618382 Write leveling (Byte 1): 25 => 25
7539 00:39:16.618920 DramcWriteLeveling(PI) end<-----
7540 00:39:16.621361
7541 00:39:16.621796 ==
7542 00:39:16.624902 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 00:39:16.628252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 00:39:16.628847 ==
7545 00:39:16.631608 [Gating] SW mode calibration
7546 00:39:16.638492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7547 00:39:16.641909 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7548 00:39:16.648261 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 00:39:16.651679 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 00:39:16.654507 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 00:39:16.661127 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7552 00:39:16.664622 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7553 00:39:16.667734 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7554 00:39:16.674258 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 00:39:16.677679 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 00:39:16.681231 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 00:39:16.687831 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 00:39:16.690952 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7559 00:39:16.694396 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
7560 00:39:16.701002 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7561 00:39:16.704407 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7562 00:39:16.707613 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7563 00:39:16.714110 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 00:39:16.717599 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 00:39:16.720637 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 00:39:16.727425 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7567 00:39:16.730467 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7568 00:39:16.733980 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7569 00:39:16.740133 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7570 00:39:16.743988 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 00:39:16.746968 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 00:39:16.753491 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 00:39:16.756858 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 00:39:16.759745 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 00:39:16.766615 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 00:39:16.769820 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7577 00:39:16.772731 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 00:39:16.779648 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 00:39:16.783706 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 00:39:16.789580 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 00:39:16.792719 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 00:39:16.796112 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 00:39:16.799305 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 00:39:16.805910 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 00:39:16.809486 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 00:39:16.816178 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 00:39:16.819343 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 00:39:16.822403 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 00:39:16.828936 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 00:39:16.832686 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 00:39:16.835664 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7592 00:39:16.839433 Total UI for P1: 0, mck2ui 16
7593 00:39:16.842142 best dqsien dly found for B0: ( 1, 9, 8)
7594 00:39:16.845861 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7595 00:39:16.852455 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 00:39:16.855536 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 00:39:16.859108 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 00:39:16.862524 Total UI for P1: 0, mck2ui 16
7599 00:39:16.865413 best dqsien dly found for B1: ( 1, 9, 22)
7600 00:39:16.868697 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7601 00:39:16.875292 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7602 00:39:16.875702
7603 00:39:16.878877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7604 00:39:16.881715 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7605 00:39:16.885217 [Gating] SW calibration Done
7606 00:39:16.885672 ==
7607 00:39:16.888627 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 00:39:16.891808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 00:39:16.892362 ==
7610 00:39:16.895156 RX Vref Scan: 0
7611 00:39:16.895562
7612 00:39:16.895886 RX Vref 0 -> 0, step: 1
7613 00:39:16.896250
7614 00:39:16.898265 RX Delay 0 -> 252, step: 8
7615 00:39:16.902028 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7616 00:39:16.907767 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7617 00:39:16.911005 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7618 00:39:16.914337 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7619 00:39:16.917792 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7620 00:39:16.921167 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7621 00:39:16.927396 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7622 00:39:16.930903 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7623 00:39:16.934278 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7624 00:39:16.937233 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7625 00:39:16.941106 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7626 00:39:16.947778 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7627 00:39:16.950747 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7628 00:39:16.954151 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7629 00:39:16.957437 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7630 00:39:16.964071 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7631 00:39:16.964361 ==
7632 00:39:16.967026 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 00:39:16.970643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 00:39:16.970970 ==
7635 00:39:16.971175 DQS Delay:
7636 00:39:16.973710 DQS0 = 0, DQS1 = 0
7637 00:39:16.974015 DQM Delay:
7638 00:39:16.977149 DQM0 = 131, DQM1 = 127
7639 00:39:16.977421 DQ Delay:
7640 00:39:16.980285 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7641 00:39:16.983313 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7642 00:39:16.986920 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7643 00:39:16.989906 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7644 00:39:16.993545
7645 00:39:16.993948
7646 00:39:16.994298 ==
7647 00:39:16.997081 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 00:39:16.999987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 00:39:17.000504 ==
7650 00:39:17.000980
7651 00:39:17.001466
7652 00:39:17.003598 TX Vref Scan disable
7653 00:39:17.004015 == TX Byte 0 ==
7654 00:39:17.009978 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7655 00:39:17.013522 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7656 00:39:17.014206 == TX Byte 1 ==
7657 00:39:17.019939 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7658 00:39:17.023491 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7659 00:39:17.023941 ==
7660 00:39:17.026755 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 00:39:17.029445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 00:39:17.029859 ==
7663 00:39:17.044331
7664 00:39:17.048598 TX Vref early break, caculate TX vref
7665 00:39:17.051372 TX Vref=16, minBit 11, minWin=21, winSum=369
7666 00:39:17.054703 TX Vref=18, minBit 3, minWin=23, winSum=380
7667 00:39:17.057716 TX Vref=20, minBit 7, minWin=23, winSum=389
7668 00:39:17.060799 TX Vref=22, minBit 7, minWin=23, winSum=398
7669 00:39:17.067411 TX Vref=24, minBit 10, minWin=24, winSum=409
7670 00:39:17.070684 TX Vref=26, minBit 1, minWin=24, winSum=412
7671 00:39:17.074147 TX Vref=28, minBit 1, minWin=25, winSum=418
7672 00:39:17.077595 TX Vref=30, minBit 2, minWin=25, winSum=414
7673 00:39:17.080853 TX Vref=32, minBit 2, minWin=24, winSum=408
7674 00:39:17.083746 TX Vref=34, minBit 6, minWin=23, winSum=390
7675 00:39:17.090977 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
7676 00:39:17.091489
7677 00:39:17.093771 Final TX Range 0 Vref 28
7678 00:39:17.094183
7679 00:39:17.094503 ==
7680 00:39:17.097366 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 00:39:17.100746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 00:39:17.101254 ==
7683 00:39:17.101645
7684 00:39:17.101950
7685 00:39:17.103735 TX Vref Scan disable
7686 00:39:17.110598 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7687 00:39:17.111067 == TX Byte 0 ==
7688 00:39:17.113842 u2DelayCellOfst[0]=14 cells (4 PI)
7689 00:39:17.117163 u2DelayCellOfst[1]=17 cells (5 PI)
7690 00:39:17.120332 u2DelayCellOfst[2]=14 cells (4 PI)
7691 00:39:17.123405 u2DelayCellOfst[3]=14 cells (4 PI)
7692 00:39:17.126761 u2DelayCellOfst[4]=10 cells (3 PI)
7693 00:39:17.130504 u2DelayCellOfst[5]=0 cells (0 PI)
7694 00:39:17.133747 u2DelayCellOfst[6]=17 cells (5 PI)
7695 00:39:17.137009 u2DelayCellOfst[7]=17 cells (5 PI)
7696 00:39:17.140126 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7697 00:39:17.143852 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7698 00:39:17.146946 == TX Byte 1 ==
7699 00:39:17.150450 u2DelayCellOfst[8]=0 cells (0 PI)
7700 00:39:17.153644 u2DelayCellOfst[9]=0 cells (0 PI)
7701 00:39:17.156803 u2DelayCellOfst[10]=3 cells (1 PI)
7702 00:39:17.160052 u2DelayCellOfst[11]=0 cells (0 PI)
7703 00:39:17.160463 u2DelayCellOfst[12]=7 cells (2 PI)
7704 00:39:17.163413 u2DelayCellOfst[13]=7 cells (2 PI)
7705 00:39:17.166443 u2DelayCellOfst[14]=14 cells (4 PI)
7706 00:39:17.169610 u2DelayCellOfst[15]=7 cells (2 PI)
7707 00:39:17.176681 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7708 00:39:17.179592 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7709 00:39:17.180007 DramC Write-DBI on
7710 00:39:17.182930 ==
7711 00:39:17.183340 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 00:39:17.189902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 00:39:17.190313 ==
7714 00:39:17.190638
7715 00:39:17.191008
7716 00:39:17.192982 TX Vref Scan disable
7717 00:39:17.193432 == TX Byte 0 ==
7718 00:39:17.199812 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7719 00:39:17.200321 == TX Byte 1 ==
7720 00:39:17.202767 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7721 00:39:17.206151 DramC Write-DBI off
7722 00:39:17.206624
7723 00:39:17.206946 [DATLAT]
7724 00:39:17.209063 Freq=1600, CH0 RK0
7725 00:39:17.209513
7726 00:39:17.209836 DATLAT Default: 0xf
7727 00:39:17.212771 0, 0xFFFF, sum = 0
7728 00:39:17.213185 1, 0xFFFF, sum = 0
7729 00:39:17.215722 2, 0xFFFF, sum = 0
7730 00:39:17.216134 3, 0xFFFF, sum = 0
7731 00:39:17.219170 4, 0xFFFF, sum = 0
7732 00:39:17.222197 5, 0xFFFF, sum = 0
7733 00:39:17.222610 6, 0xFFFF, sum = 0
7734 00:39:17.225638 7, 0xFFFF, sum = 0
7735 00:39:17.226051 8, 0xFFFF, sum = 0
7736 00:39:17.229014 9, 0xFFFF, sum = 0
7737 00:39:17.229482 10, 0xFFFF, sum = 0
7738 00:39:17.232583 11, 0xFFFF, sum = 0
7739 00:39:17.233081 12, 0xFFFF, sum = 0
7740 00:39:17.236099 13, 0xFFFF, sum = 0
7741 00:39:17.236606 14, 0x0, sum = 1
7742 00:39:17.239248 15, 0x0, sum = 2
7743 00:39:17.239672 16, 0x0, sum = 3
7744 00:39:17.242255 17, 0x0, sum = 4
7745 00:39:17.242668 best_step = 15
7746 00:39:17.243065
7747 00:39:17.243387 ==
7748 00:39:17.245552 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 00:39:17.249442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 00:39:17.252647 ==
7751 00:39:17.253151 RX Vref Scan: 1
7752 00:39:17.253563
7753 00:39:17.255355 Set Vref Range= 24 -> 127
7754 00:39:17.255760
7755 00:39:17.258748 RX Vref 24 -> 127, step: 1
7756 00:39:17.259155
7757 00:39:17.259478 RX Delay 19 -> 252, step: 4
7758 00:39:17.259781
7759 00:39:17.262258 Set Vref, RX VrefLevel [Byte0]: 24
7760 00:39:17.265607 [Byte1]: 24
7761 00:39:17.269052
7762 00:39:17.269497 Set Vref, RX VrefLevel [Byte0]: 25
7763 00:39:17.272607 [Byte1]: 25
7764 00:39:17.276716
7765 00:39:17.277122 Set Vref, RX VrefLevel [Byte0]: 26
7766 00:39:17.280139 [Byte1]: 26
7767 00:39:17.284230
7768 00:39:17.284717 Set Vref, RX VrefLevel [Byte0]: 27
7769 00:39:17.287855 [Byte1]: 27
7770 00:39:17.292012
7771 00:39:17.292417 Set Vref, RX VrefLevel [Byte0]: 28
7772 00:39:17.295223 [Byte1]: 28
7773 00:39:17.300129
7774 00:39:17.300648 Set Vref, RX VrefLevel [Byte0]: 29
7775 00:39:17.303340 [Byte1]: 29
7776 00:39:17.307498
7777 00:39:17.307977 Set Vref, RX VrefLevel [Byte0]: 30
7778 00:39:17.310449 [Byte1]: 30
7779 00:39:17.314861
7780 00:39:17.315292 Set Vref, RX VrefLevel [Byte0]: 31
7781 00:39:17.318293 [Byte1]: 31
7782 00:39:17.322222
7783 00:39:17.322634 Set Vref, RX VrefLevel [Byte0]: 32
7784 00:39:17.325493 [Byte1]: 32
7785 00:39:17.330111
7786 00:39:17.330527 Set Vref, RX VrefLevel [Byte0]: 33
7787 00:39:17.332886 [Byte1]: 33
7788 00:39:17.337430
7789 00:39:17.337948 Set Vref, RX VrefLevel [Byte0]: 34
7790 00:39:17.340663 [Byte1]: 34
7791 00:39:17.344772
7792 00:39:17.345179 Set Vref, RX VrefLevel [Byte0]: 35
7793 00:39:17.348324 [Byte1]: 35
7794 00:39:17.352980
7795 00:39:17.353527 Set Vref, RX VrefLevel [Byte0]: 36
7796 00:39:17.355662 [Byte1]: 36
7797 00:39:17.360206
7798 00:39:17.360619 Set Vref, RX VrefLevel [Byte0]: 37
7799 00:39:17.363301 [Byte1]: 37
7800 00:39:17.367523
7801 00:39:17.367999 Set Vref, RX VrefLevel [Byte0]: 38
7802 00:39:17.370943 [Byte1]: 38
7803 00:39:17.375275
7804 00:39:17.375686 Set Vref, RX VrefLevel [Byte0]: 39
7805 00:39:17.378448 [Byte1]: 39
7806 00:39:17.382983
7807 00:39:17.383396 Set Vref, RX VrefLevel [Byte0]: 40
7808 00:39:17.386450 [Byte1]: 40
7809 00:39:17.390736
7810 00:39:17.391246 Set Vref, RX VrefLevel [Byte0]: 41
7811 00:39:17.393909 [Byte1]: 41
7812 00:39:17.397928
7813 00:39:17.398337 Set Vref, RX VrefLevel [Byte0]: 42
7814 00:39:17.401551 [Byte1]: 42
7815 00:39:17.405769
7816 00:39:17.406193 Set Vref, RX VrefLevel [Byte0]: 43
7817 00:39:17.408688 [Byte1]: 43
7818 00:39:17.413150
7819 00:39:17.413690 Set Vref, RX VrefLevel [Byte0]: 44
7820 00:39:17.416638 [Byte1]: 44
7821 00:39:17.420424
7822 00:39:17.420867 Set Vref, RX VrefLevel [Byte0]: 45
7823 00:39:17.424227 [Byte1]: 45
7824 00:39:17.428715
7825 00:39:17.429128 Set Vref, RX VrefLevel [Byte0]: 46
7826 00:39:17.431459 [Byte1]: 46
7827 00:39:17.436314
7828 00:39:17.436732 Set Vref, RX VrefLevel [Byte0]: 47
7829 00:39:17.439070 [Byte1]: 47
7830 00:39:17.443489
7831 00:39:17.443903 Set Vref, RX VrefLevel [Byte0]: 48
7832 00:39:17.446770 [Byte1]: 48
7833 00:39:17.451097
7834 00:39:17.451614 Set Vref, RX VrefLevel [Byte0]: 49
7835 00:39:17.454327 [Byte1]: 49
7836 00:39:17.458898
7837 00:39:17.459346 Set Vref, RX VrefLevel [Byte0]: 50
7838 00:39:17.461933 [Byte1]: 50
7839 00:39:17.466242
7840 00:39:17.466702 Set Vref, RX VrefLevel [Byte0]: 51
7841 00:39:17.469375 [Byte1]: 51
7842 00:39:17.473961
7843 00:39:17.474383 Set Vref, RX VrefLevel [Byte0]: 52
7844 00:39:17.477067 [Byte1]: 52
7845 00:39:17.481192
7846 00:39:17.481405 Set Vref, RX VrefLevel [Byte0]: 53
7847 00:39:17.484360 [Byte1]: 53
7848 00:39:17.488576
7849 00:39:17.488801 Set Vref, RX VrefLevel [Byte0]: 54
7850 00:39:17.491886 [Byte1]: 54
7851 00:39:17.496219
7852 00:39:17.496368 Set Vref, RX VrefLevel [Byte0]: 55
7853 00:39:17.499741 [Byte1]: 55
7854 00:39:17.503578
7855 00:39:17.503761 Set Vref, RX VrefLevel [Byte0]: 56
7856 00:39:17.506711 [Byte1]: 56
7857 00:39:17.511024
7858 00:39:17.511107 Set Vref, RX VrefLevel [Byte0]: 57
7859 00:39:17.514289 [Byte1]: 57
7860 00:39:17.518911
7861 00:39:17.518993 Set Vref, RX VrefLevel [Byte0]: 58
7862 00:39:17.522278 [Byte1]: 58
7863 00:39:17.526525
7864 00:39:17.529639 Set Vref, RX VrefLevel [Byte0]: 59
7865 00:39:17.533029 [Byte1]: 59
7866 00:39:17.533146
7867 00:39:17.536196 Set Vref, RX VrefLevel [Byte0]: 60
7868 00:39:17.539485 [Byte1]: 60
7869 00:39:17.539568
7870 00:39:17.542655 Set Vref, RX VrefLevel [Byte0]: 61
7871 00:39:17.546430 [Byte1]: 61
7872 00:39:17.546605
7873 00:39:17.549628 Set Vref, RX VrefLevel [Byte0]: 62
7874 00:39:17.552818 [Byte1]: 62
7875 00:39:17.556885
7876 00:39:17.557104 Set Vref, RX VrefLevel [Byte0]: 63
7877 00:39:17.559817 [Byte1]: 63
7878 00:39:17.564418
7879 00:39:17.564543 Set Vref, RX VrefLevel [Byte0]: 64
7880 00:39:17.567856 [Byte1]: 64
7881 00:39:17.572000
7882 00:39:17.572225 Set Vref, RX VrefLevel [Byte0]: 65
7883 00:39:17.575738 [Byte1]: 65
7884 00:39:17.579822
7885 00:39:17.580081 Set Vref, RX VrefLevel [Byte0]: 66
7886 00:39:17.582660 [Byte1]: 66
7887 00:39:17.587151
7888 00:39:17.587477 Set Vref, RX VrefLevel [Byte0]: 67
7889 00:39:17.590679 [Byte1]: 67
7890 00:39:17.594994
7891 00:39:17.595461 Set Vref, RX VrefLevel [Byte0]: 68
7892 00:39:17.598024 [Byte1]: 68
7893 00:39:17.602542
7894 00:39:17.603094 Set Vref, RX VrefLevel [Byte0]: 69
7895 00:39:17.605716 [Byte1]: 69
7896 00:39:17.609877
7897 00:39:17.610291 Set Vref, RX VrefLevel [Byte0]: 70
7898 00:39:17.613150 [Byte1]: 70
7899 00:39:17.617756
7900 00:39:17.618168 Set Vref, RX VrefLevel [Byte0]: 71
7901 00:39:17.620633 [Byte1]: 71
7902 00:39:17.625047
7903 00:39:17.628474 Set Vref, RX VrefLevel [Byte0]: 72
7904 00:39:17.631920 [Byte1]: 72
7905 00:39:17.632352
7906 00:39:17.634926 Set Vref, RX VrefLevel [Byte0]: 73
7907 00:39:17.637809 [Byte1]: 73
7908 00:39:17.638107
7909 00:39:17.641444 Set Vref, RX VrefLevel [Byte0]: 74
7910 00:39:17.644549 [Byte1]: 74
7911 00:39:17.644759
7912 00:39:17.647772 Set Vref, RX VrefLevel [Byte0]: 75
7913 00:39:17.650678 [Byte1]: 75
7914 00:39:17.655064
7915 00:39:17.655213 Final RX Vref Byte 0 = 56 to rank0
7916 00:39:17.658447 Final RX Vref Byte 1 = 58 to rank0
7917 00:39:17.661470 Final RX Vref Byte 0 = 56 to rank1
7918 00:39:17.665069 Final RX Vref Byte 1 = 58 to rank1==
7919 00:39:17.668296 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 00:39:17.674785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 00:39:17.674876 ==
7922 00:39:17.674947 DQS Delay:
7923 00:39:17.675013 DQS0 = 0, DQS1 = 0
7924 00:39:17.678313 DQM Delay:
7925 00:39:17.678395 DQM0 = 128, DQM1 = 124
7926 00:39:17.681792 DQ Delay:
7927 00:39:17.684865 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7928 00:39:17.688309 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7929 00:39:17.691626 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7930 00:39:17.695198 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =132
7931 00:39:17.695353
7932 00:39:17.695424
7933 00:39:17.695487
7934 00:39:17.698252 [DramC_TX_OE_Calibration] TA2
7935 00:39:17.701537 Original DQ_B0 (3 6) =30, OEN = 27
7936 00:39:17.704619 Original DQ_B1 (3 6) =30, OEN = 27
7937 00:39:17.708117 24, 0x0, End_B0=24 End_B1=24
7938 00:39:17.708274 25, 0x0, End_B0=25 End_B1=25
7939 00:39:17.711641 26, 0x0, End_B0=26 End_B1=26
7940 00:39:17.714464 27, 0x0, End_B0=27 End_B1=27
7941 00:39:17.717871 28, 0x0, End_B0=28 End_B1=28
7942 00:39:17.721232 29, 0x0, End_B0=29 End_B1=29
7943 00:39:17.721404 30, 0x0, End_B0=30 End_B1=30
7944 00:39:17.724557 31, 0x4141, End_B0=30 End_B1=30
7945 00:39:17.727798 Byte0 end_step=30 best_step=27
7946 00:39:17.731459 Byte1 end_step=30 best_step=27
7947 00:39:17.734730 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 00:39:17.737645 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 00:39:17.737813
7950 00:39:17.737900
7951 00:39:17.744079 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7952 00:39:17.747379 CH0 RK0: MR19=303, MR18=1815
7953 00:39:17.754868 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7954 00:39:17.755019
7955 00:39:17.757455 ----->DramcWriteLeveling(PI) begin...
7956 00:39:17.757629 ==
7957 00:39:17.760885 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 00:39:17.764268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 00:39:17.764468 ==
7960 00:39:17.767099 Write leveling (Byte 0): 35 => 35
7961 00:39:17.770643 Write leveling (Byte 1): 25 => 25
7962 00:39:17.773982 DramcWriteLeveling(PI) end<-----
7963 00:39:17.774276
7964 00:39:17.774512 ==
7965 00:39:17.777483 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 00:39:17.780666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 00:39:17.784284 ==
7968 00:39:17.784829 [Gating] SW mode calibration
7969 00:39:17.793923 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 00:39:17.797336 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 00:39:17.800367 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 00:39:17.807392 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 00:39:17.810831 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7974 00:39:17.813543 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7975 00:39:17.820259 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7976 00:39:17.823705 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7977 00:39:17.826723 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 00:39:17.833423 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 00:39:17.836898 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 00:39:17.839920 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7981 00:39:17.846752 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7982 00:39:17.850280 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7983 00:39:17.853550 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7984 00:39:17.860016 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7985 00:39:17.863453 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 00:39:17.866467 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 00:39:17.872920 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 00:39:17.876173 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7989 00:39:17.879747 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7990 00:39:17.886477 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7991 00:39:17.889846 1 6 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7992 00:39:17.892906 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 00:39:17.899610 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 00:39:17.902778 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 00:39:17.906119 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 00:39:17.912450 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7997 00:39:17.915984 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7998 00:39:17.919149 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7999 00:39:17.925883 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8000 00:39:17.929125 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8001 00:39:17.932954 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 00:39:17.939087 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 00:39:17.942158 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 00:39:17.945357 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 00:39:17.952367 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 00:39:17.955237 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 00:39:17.958725 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 00:39:17.965368 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 00:39:17.968394 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 00:39:17.971865 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 00:39:17.978464 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 00:39:17.981725 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 00:39:17.985011 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8014 00:39:17.991405 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8015 00:39:17.995127 Total UI for P1: 0, mck2ui 16
8016 00:39:17.998387 best dqsien dly found for B0: ( 1, 9, 8)
8017 00:39:18.001805 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8018 00:39:18.004677 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8019 00:39:18.011732 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 00:39:18.014479 Total UI for P1: 0, mck2ui 16
8021 00:39:18.018109 best dqsien dly found for B1: ( 1, 9, 18)
8022 00:39:18.021374 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8023 00:39:18.024579 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8024 00:39:18.024877
8025 00:39:18.027890 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8026 00:39:18.031294 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8027 00:39:18.034239 [Gating] SW calibration Done
8028 00:39:18.034467 ==
8029 00:39:18.037770 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 00:39:18.041206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 00:39:18.041671 ==
8032 00:39:18.044604 RX Vref Scan: 0
8033 00:39:18.045049
8034 00:39:18.047942 RX Vref 0 -> 0, step: 1
8035 00:39:18.048350
8036 00:39:18.048732 RX Delay 0 -> 252, step: 8
8037 00:39:18.054576 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8038 00:39:18.057368 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8039 00:39:18.060959 iDelay=192, Bit 2, Center 131 (80 ~ 183) 104
8040 00:39:18.064202 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8041 00:39:18.067543 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8042 00:39:18.074030 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8043 00:39:18.077354 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8044 00:39:18.080371 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8045 00:39:18.084296 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8046 00:39:18.087350 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8047 00:39:18.093936 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8048 00:39:18.097551 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8049 00:39:18.100451 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
8050 00:39:18.103496 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8051 00:39:18.110240 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8052 00:39:18.113338 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8053 00:39:18.113872 ==
8054 00:39:18.116925 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 00:39:18.120186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 00:39:18.120798 ==
8057 00:39:18.121361 DQS Delay:
8058 00:39:18.124434 DQS0 = 0, DQS1 = 0
8059 00:39:18.124985 DQM Delay:
8060 00:39:18.127140 DQM0 = 131, DQM1 = 126
8061 00:39:18.127703 DQ Delay:
8062 00:39:18.130054 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8063 00:39:18.133516 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8064 00:39:18.136872 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8065 00:39:18.143196 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =135
8066 00:39:18.143796
8067 00:39:18.144322
8068 00:39:18.144840 ==
8069 00:39:18.146336 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 00:39:18.150184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 00:39:18.150917 ==
8072 00:39:18.151577
8073 00:39:18.152200
8074 00:39:18.153489 TX Vref Scan disable
8075 00:39:18.154021 == TX Byte 0 ==
8076 00:39:18.159664 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8077 00:39:18.163237 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8078 00:39:18.163704 == TX Byte 1 ==
8079 00:39:18.169631 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8080 00:39:18.172849 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8081 00:39:18.173556 ==
8082 00:39:18.176402 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 00:39:18.179873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 00:39:18.180474 ==
8085 00:39:18.196325
8086 00:39:18.199444 TX Vref early break, caculate TX vref
8087 00:39:18.202669 TX Vref=16, minBit 9, minWin=22, winSum=378
8088 00:39:18.205910 TX Vref=18, minBit 1, minWin=24, winSum=388
8089 00:39:18.208853 TX Vref=20, minBit 2, minWin=24, winSum=394
8090 00:39:18.212137 TX Vref=22, minBit 4, minWin=24, winSum=401
8091 00:39:18.215655 TX Vref=24, minBit 10, minWin=24, winSum=408
8092 00:39:18.221930 TX Vref=26, minBit 4, minWin=25, winSum=413
8093 00:39:18.225567 TX Vref=28, minBit 1, minWin=25, winSum=413
8094 00:39:18.228833 TX Vref=30, minBit 1, minWin=25, winSum=411
8095 00:39:18.231821 TX Vref=32, minBit 1, minWin=24, winSum=402
8096 00:39:18.235210 TX Vref=34, minBit 0, minWin=24, winSum=392
8097 00:39:18.241516 TX Vref=36, minBit 0, minWin=24, winSum=387
8098 00:39:18.245415 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 26
8099 00:39:18.245616
8100 00:39:18.248103 Final TX Range 0 Vref 26
8101 00:39:18.248271
8102 00:39:18.248416 ==
8103 00:39:18.251530 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 00:39:18.255012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 00:39:18.258025 ==
8106 00:39:18.258182
8107 00:39:18.258287
8108 00:39:18.258391 TX Vref Scan disable
8109 00:39:18.264798 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8110 00:39:18.264911 == TX Byte 0 ==
8111 00:39:18.268359 u2DelayCellOfst[0]=10 cells (3 PI)
8112 00:39:18.271327 u2DelayCellOfst[1]=14 cells (4 PI)
8113 00:39:18.274822 u2DelayCellOfst[2]=7 cells (2 PI)
8114 00:39:18.278015 u2DelayCellOfst[3]=10 cells (3 PI)
8115 00:39:18.281546 u2DelayCellOfst[4]=7 cells (2 PI)
8116 00:39:18.285007 u2DelayCellOfst[5]=0 cells (0 PI)
8117 00:39:18.288016 u2DelayCellOfst[6]=14 cells (4 PI)
8118 00:39:18.291530 u2DelayCellOfst[7]=14 cells (4 PI)
8119 00:39:18.294354 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8120 00:39:18.297901 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8121 00:39:18.301213 == TX Byte 1 ==
8122 00:39:18.304526 u2DelayCellOfst[8]=0 cells (0 PI)
8123 00:39:18.307998 u2DelayCellOfst[9]=0 cells (0 PI)
8124 00:39:18.310814 u2DelayCellOfst[10]=3 cells (1 PI)
8125 00:39:18.314390 u2DelayCellOfst[11]=3 cells (1 PI)
8126 00:39:18.317712 u2DelayCellOfst[12]=7 cells (2 PI)
8127 00:39:18.317814 u2DelayCellOfst[13]=7 cells (2 PI)
8128 00:39:18.321404 u2DelayCellOfst[14]=10 cells (3 PI)
8129 00:39:18.324367 u2DelayCellOfst[15]=7 cells (2 PI)
8130 00:39:18.330959 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8131 00:39:18.333947 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8132 00:39:18.334027 DramC Write-DBI on
8133 00:39:18.337318 ==
8134 00:39:18.341090 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 00:39:18.344086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 00:39:18.344167 ==
8137 00:39:18.344230
8138 00:39:18.344290
8139 00:39:18.347144 TX Vref Scan disable
8140 00:39:18.347224 == TX Byte 0 ==
8141 00:39:18.353869 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8142 00:39:18.353950 == TX Byte 1 ==
8143 00:39:18.357267 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8144 00:39:18.360772 DramC Write-DBI off
8145 00:39:18.360868
8146 00:39:18.360964 [DATLAT]
8147 00:39:18.363722 Freq=1600, CH0 RK1
8148 00:39:18.363825
8149 00:39:18.363921 DATLAT Default: 0xf
8150 00:39:18.367318 0, 0xFFFF, sum = 0
8151 00:39:18.367416 1, 0xFFFF, sum = 0
8152 00:39:18.370560 2, 0xFFFF, sum = 0
8153 00:39:18.370665 3, 0xFFFF, sum = 0
8154 00:39:18.373860 4, 0xFFFF, sum = 0
8155 00:39:18.377249 5, 0xFFFF, sum = 0
8156 00:39:18.377375 6, 0xFFFF, sum = 0
8157 00:39:18.380195 7, 0xFFFF, sum = 0
8158 00:39:18.380300 8, 0xFFFF, sum = 0
8159 00:39:18.383862 9, 0xFFFF, sum = 0
8160 00:39:18.383960 10, 0xFFFF, sum = 0
8161 00:39:18.387003 11, 0xFFFF, sum = 0
8162 00:39:18.387128 12, 0xFFFF, sum = 0
8163 00:39:18.390164 13, 0xFFFF, sum = 0
8164 00:39:18.390267 14, 0x0, sum = 1
8165 00:39:18.393569 15, 0x0, sum = 2
8166 00:39:18.393671 16, 0x0, sum = 3
8167 00:39:18.396603 17, 0x0, sum = 4
8168 00:39:18.396700 best_step = 15
8169 00:39:18.396787
8170 00:39:18.396871 ==
8171 00:39:18.400620 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 00:39:18.406960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 00:39:18.407041 ==
8174 00:39:18.407105 RX Vref Scan: 0
8175 00:39:18.407164
8176 00:39:18.410057 RX Vref 0 -> 0, step: 1
8177 00:39:18.410138
8178 00:39:18.413512 RX Delay 11 -> 252, step: 4
8179 00:39:18.416407 iDelay=191, Bit 0, Center 124 (75 ~ 174) 100
8180 00:39:18.419727 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8181 00:39:18.423334 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8182 00:39:18.429684 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8183 00:39:18.432696 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8184 00:39:18.436300 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8185 00:39:18.439966 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8186 00:39:18.442659 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8187 00:39:18.449861 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8188 00:39:18.453103 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8189 00:39:18.456041 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8190 00:39:18.459273 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8191 00:39:18.466036 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8192 00:39:18.469512 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8193 00:39:18.472944 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8194 00:39:18.476235 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8195 00:39:18.476314 ==
8196 00:39:18.479207 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 00:39:18.485879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 00:39:18.485960 ==
8199 00:39:18.486024 DQS Delay:
8200 00:39:18.486084 DQS0 = 0, DQS1 = 0
8201 00:39:18.489305 DQM Delay:
8202 00:39:18.489384 DQM0 = 128, DQM1 = 124
8203 00:39:18.492606 DQ Delay:
8204 00:39:18.495410 DQ0 =124, DQ1 =132, DQ2 =124, DQ3 =126
8205 00:39:18.498944 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8206 00:39:18.502404 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8207 00:39:18.505705 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8208 00:39:18.505784
8209 00:39:18.505847
8210 00:39:18.505904
8211 00:39:18.509052 [DramC_TX_OE_Calibration] TA2
8212 00:39:18.512300 Original DQ_B0 (3 6) =30, OEN = 27
8213 00:39:18.515445 Original DQ_B1 (3 6) =30, OEN = 27
8214 00:39:18.518604 24, 0x0, End_B0=24 End_B1=24
8215 00:39:18.518684 25, 0x0, End_B0=25 End_B1=25
8216 00:39:18.521944 26, 0x0, End_B0=26 End_B1=26
8217 00:39:18.525352 27, 0x0, End_B0=27 End_B1=27
8218 00:39:18.528535 28, 0x0, End_B0=28 End_B1=28
8219 00:39:18.532031 29, 0x0, End_B0=29 End_B1=29
8220 00:39:18.532111 30, 0x0, End_B0=30 End_B1=30
8221 00:39:18.535049 31, 0x4141, End_B0=30 End_B1=30
8222 00:39:18.538605 Byte0 end_step=30 best_step=27
8223 00:39:18.541553 Byte1 end_step=30 best_step=27
8224 00:39:18.544936 Byte0 TX OE(2T, 0.5T) = (3, 3)
8225 00:39:18.548384 Byte1 TX OE(2T, 0.5T) = (3, 3)
8226 00:39:18.548463
8227 00:39:18.548525
8228 00:39:18.554903 [DQSOSCAuto] RK1, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8229 00:39:18.558382 CH0 RK1: MR19=303, MR18=1614
8230 00:39:18.564775 CH0_RK1: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
8231 00:39:18.568200 [RxdqsGatingPostProcess] freq 1600
8232 00:39:18.571690 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8233 00:39:18.574614 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 00:39:18.578152 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 00:39:18.581561 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 00:39:18.584517 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 00:39:18.587855 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 00:39:18.591332 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 00:39:18.594701 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 00:39:18.598137 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 00:39:18.600796 Pre-setting of DQS Precalculation
8242 00:39:18.604337 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8243 00:39:18.604417 ==
8244 00:39:18.607842 Dram Type= 6, Freq= 0, CH_1, rank 0
8245 00:39:18.614537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 00:39:18.614617 ==
8247 00:39:18.617830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8248 00:39:18.624015 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8249 00:39:18.627625 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8250 00:39:18.634312 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8251 00:39:18.641661 [CA 0] Center 42 (12~72) winsize 61
8252 00:39:18.645695 [CA 1] Center 42 (12~72) winsize 61
8253 00:39:18.648279 [CA 2] Center 38 (9~67) winsize 59
8254 00:39:18.651946 [CA 3] Center 37 (8~66) winsize 59
8255 00:39:18.655215 [CA 4] Center 37 (7~68) winsize 62
8256 00:39:18.658520 [CA 5] Center 36 (7~66) winsize 60
8257 00:39:18.658602
8258 00:39:18.661504 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8259 00:39:18.661582
8260 00:39:18.664986 [CATrainingPosCal] consider 1 rank data
8261 00:39:18.668779 u2DelayCellTimex100 = 275/100 ps
8262 00:39:18.671557 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8263 00:39:18.678125 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8264 00:39:18.681629 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8265 00:39:18.685102 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8266 00:39:18.688114 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8267 00:39:18.691445 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8268 00:39:18.691557
8269 00:39:18.694438 CA PerBit enable=1, Macro0, CA PI delay=36
8270 00:39:18.694517
8271 00:39:18.698040 [CBTSetCACLKResult] CA Dly = 36
8272 00:39:18.701402 CS Dly: 8 (0~39)
8273 00:39:18.704614 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8274 00:39:18.708032 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8275 00:39:18.708117 ==
8276 00:39:18.711253 Dram Type= 6, Freq= 0, CH_1, rank 1
8277 00:39:18.717511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 00:39:18.717599 ==
8279 00:39:18.720854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 00:39:18.727806 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 00:39:18.731118 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 00:39:18.737429 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 00:39:18.745148 [CA 0] Center 42 (12~72) winsize 61
8284 00:39:18.748088 [CA 1] Center 43 (14~72) winsize 59
8285 00:39:18.751411 [CA 2] Center 37 (8~67) winsize 60
8286 00:39:18.754517 [CA 3] Center 36 (7~66) winsize 60
8287 00:39:18.758577 [CA 4] Center 37 (7~67) winsize 61
8288 00:39:18.761581 [CA 5] Center 36 (7~66) winsize 60
8289 00:39:18.761651
8290 00:39:18.764535 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 00:39:18.764633
8292 00:39:18.771207 [CATrainingPosCal] consider 2 rank data
8293 00:39:18.771283 u2DelayCellTimex100 = 275/100 ps
8294 00:39:18.777699 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8295 00:39:18.781141 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8296 00:39:18.784646 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8297 00:39:18.787703 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8298 00:39:18.791245 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8299 00:39:18.794340 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8300 00:39:18.794444
8301 00:39:18.797651 CA PerBit enable=1, Macro0, CA PI delay=36
8302 00:39:18.797731
8303 00:39:18.801387 [CBTSetCACLKResult] CA Dly = 36
8304 00:39:18.804263 CS Dly: 9 (0~42)
8305 00:39:18.807666 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 00:39:18.811109 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 00:39:18.811192
8308 00:39:18.814399 ----->DramcWriteLeveling(PI) begin...
8309 00:39:18.814479 ==
8310 00:39:18.817404 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 00:39:18.823998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 00:39:18.824079 ==
8313 00:39:18.827428 Write leveling (Byte 0): 25 => 25
8314 00:39:18.830728 Write leveling (Byte 1): 26 => 26
8315 00:39:18.830808 DramcWriteLeveling(PI) end<-----
8316 00:39:18.830871
8317 00:39:18.834085 ==
8318 00:39:18.837398 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 00:39:18.840759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 00:39:18.840839 ==
8321 00:39:18.843904 [Gating] SW mode calibration
8322 00:39:18.850368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8323 00:39:18.853789 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8324 00:39:18.860036 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 00:39:18.863766 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 00:39:18.866669 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 00:39:18.873500 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8328 00:39:18.876596 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 00:39:18.880031 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 00:39:18.886514 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 00:39:18.889907 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 00:39:18.893099 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 00:39:18.899843 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 00:39:18.903220 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8335 00:39:18.906283 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8336 00:39:18.913186 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8337 00:39:18.916609 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 00:39:18.919633 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 00:39:18.925933 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 00:39:18.929425 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 00:39:18.932864 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 00:39:18.939218 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8343 00:39:18.942576 1 6 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
8344 00:39:18.946038 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 00:39:18.952303 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 00:39:18.955648 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 00:39:18.959162 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 00:39:18.965599 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 00:39:18.968973 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 00:39:18.972122 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 00:39:18.979073 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8352 00:39:18.982008 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8353 00:39:18.985615 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 00:39:18.992186 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 00:39:18.995046 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 00:39:18.998710 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 00:39:19.005349 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 00:39:19.008678 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 00:39:19.011824 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 00:39:19.018299 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 00:39:19.021730 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 00:39:19.024887 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 00:39:19.031568 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 00:39:19.034698 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 00:39:19.038460 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 00:39:19.044991 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8367 00:39:19.048188 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 00:39:19.051035 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8369 00:39:19.054483 Total UI for P1: 0, mck2ui 16
8370 00:39:19.057948 best dqsien dly found for B0: ( 1, 9, 10)
8371 00:39:19.064429 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 00:39:19.068060 Total UI for P1: 0, mck2ui 16
8373 00:39:19.071139 best dqsien dly found for B1: ( 1, 9, 14)
8374 00:39:19.074724 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8375 00:39:19.077645 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8376 00:39:19.077716
8377 00:39:19.081390 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8378 00:39:19.084695 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8379 00:39:19.087357 [Gating] SW calibration Done
8380 00:39:19.087452 ==
8381 00:39:19.090628 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 00:39:19.094148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 00:39:19.094222 ==
8384 00:39:19.097125 RX Vref Scan: 0
8385 00:39:19.097234
8386 00:39:19.100430 RX Vref 0 -> 0, step: 1
8387 00:39:19.100507
8388 00:39:19.100569 RX Delay 0 -> 252, step: 8
8389 00:39:19.107197 iDelay=200, Bit 0, Center 147 (96 ~ 199) 104
8390 00:39:19.111073 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8391 00:39:19.114001 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8392 00:39:19.117357 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8393 00:39:19.120479 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8394 00:39:19.126863 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8395 00:39:19.130418 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8396 00:39:19.133758 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8397 00:39:19.136822 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8398 00:39:19.143164 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8399 00:39:19.146614 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8400 00:39:19.150045 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8401 00:39:19.153327 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8402 00:39:19.156492 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8403 00:39:19.162952 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8404 00:39:19.166569 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8405 00:39:19.166650 ==
8406 00:39:19.169505 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 00:39:19.172873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 00:39:19.172953 ==
8409 00:39:19.176758 DQS Delay:
8410 00:39:19.176834 DQS0 = 0, DQS1 = 0
8411 00:39:19.176895 DQM Delay:
8412 00:39:19.179651 DQM0 = 135, DQM1 = 132
8413 00:39:19.179719 DQ Delay:
8414 00:39:19.183236 DQ0 =147, DQ1 =131, DQ2 =123, DQ3 =135
8415 00:39:19.189524 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8416 00:39:19.192500 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8417 00:39:19.195970 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8418 00:39:19.196051
8419 00:39:19.196114
8420 00:39:19.196173 ==
8421 00:39:19.199331 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 00:39:19.202769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 00:39:19.202850 ==
8424 00:39:19.202914
8425 00:39:19.202972
8426 00:39:19.206098 TX Vref Scan disable
8427 00:39:19.209479 == TX Byte 0 ==
8428 00:39:19.212496 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8429 00:39:19.215854 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8430 00:39:19.219154 == TX Byte 1 ==
8431 00:39:19.222608 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8432 00:39:19.225850 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8433 00:39:19.225930 ==
8434 00:39:19.228829 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 00:39:19.235263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 00:39:19.235344 ==
8437 00:39:19.247963
8438 00:39:19.251105 TX Vref early break, caculate TX vref
8439 00:39:19.254116 TX Vref=16, minBit 8, minWin=21, winSum=368
8440 00:39:19.257835 TX Vref=18, minBit 8, minWin=22, winSum=378
8441 00:39:19.261026 TX Vref=20, minBit 3, minWin=23, winSum=390
8442 00:39:19.264529 TX Vref=22, minBit 8, minWin=23, winSum=394
8443 00:39:19.267371 TX Vref=24, minBit 8, minWin=24, winSum=406
8444 00:39:19.273849 TX Vref=26, minBit 1, minWin=25, winSum=414
8445 00:39:19.277558 TX Vref=28, minBit 1, minWin=25, winSum=415
8446 00:39:19.280384 TX Vref=30, minBit 9, minWin=24, winSum=415
8447 00:39:19.283856 TX Vref=32, minBit 0, minWin=24, winSum=407
8448 00:39:19.287378 TX Vref=34, minBit 9, minWin=23, winSum=396
8449 00:39:19.293780 TX Vref=36, minBit 9, minWin=22, winSum=385
8450 00:39:19.297196 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
8451 00:39:19.297312
8452 00:39:19.300142 Final TX Range 0 Vref 28
8453 00:39:19.300215
8454 00:39:19.300293 ==
8455 00:39:19.303576 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 00:39:19.307082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 00:39:19.310373 ==
8458 00:39:19.310455
8459 00:39:19.310555
8460 00:39:19.310635 TX Vref Scan disable
8461 00:39:19.317010 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8462 00:39:19.317119 == TX Byte 0 ==
8463 00:39:19.320684 u2DelayCellOfst[0]=14 cells (4 PI)
8464 00:39:19.323366 u2DelayCellOfst[1]=10 cells (3 PI)
8465 00:39:19.327160 u2DelayCellOfst[2]=0 cells (0 PI)
8466 00:39:19.330180 u2DelayCellOfst[3]=7 cells (2 PI)
8467 00:39:19.333402 u2DelayCellOfst[4]=7 cells (2 PI)
8468 00:39:19.336755 u2DelayCellOfst[5]=17 cells (5 PI)
8469 00:39:19.340145 u2DelayCellOfst[6]=14 cells (4 PI)
8470 00:39:19.343513 u2DelayCellOfst[7]=7 cells (2 PI)
8471 00:39:19.346765 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8472 00:39:19.349892 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8473 00:39:19.353168 == TX Byte 1 ==
8474 00:39:19.356729 u2DelayCellOfst[8]=0 cells (0 PI)
8475 00:39:19.359571 u2DelayCellOfst[9]=3 cells (1 PI)
8476 00:39:19.362929 u2DelayCellOfst[10]=10 cells (3 PI)
8477 00:39:19.366488 u2DelayCellOfst[11]=3 cells (1 PI)
8478 00:39:19.369382 u2DelayCellOfst[12]=14 cells (4 PI)
8479 00:39:19.373309 u2DelayCellOfst[13]=14 cells (4 PI)
8480 00:39:19.376047 u2DelayCellOfst[14]=17 cells (5 PI)
8481 00:39:19.376161 u2DelayCellOfst[15]=17 cells (5 PI)
8482 00:39:19.382510 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8483 00:39:19.386210 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 00:39:19.389021 DramC Write-DBI on
8485 00:39:19.389118 ==
8486 00:39:19.392602 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 00:39:19.395617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 00:39:19.395698 ==
8489 00:39:19.395761
8490 00:39:19.395820
8491 00:39:19.399232 TX Vref Scan disable
8492 00:39:19.399312 == TX Byte 0 ==
8493 00:39:19.405802 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8494 00:39:19.405882 == TX Byte 1 ==
8495 00:39:19.409165 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8496 00:39:19.412402 DramC Write-DBI off
8497 00:39:19.412482
8498 00:39:19.412545 [DATLAT]
8499 00:39:19.415421 Freq=1600, CH1 RK0
8500 00:39:19.415501
8501 00:39:19.415563 DATLAT Default: 0xf
8502 00:39:19.418961 0, 0xFFFF, sum = 0
8503 00:39:19.422003 1, 0xFFFF, sum = 0
8504 00:39:19.422085 2, 0xFFFF, sum = 0
8505 00:39:19.425495 3, 0xFFFF, sum = 0
8506 00:39:19.425576 4, 0xFFFF, sum = 0
8507 00:39:19.428923 5, 0xFFFF, sum = 0
8508 00:39:19.429004 6, 0xFFFF, sum = 0
8509 00:39:19.431994 7, 0xFFFF, sum = 0
8510 00:39:19.432074 8, 0xFFFF, sum = 0
8511 00:39:19.435639 9, 0xFFFF, sum = 0
8512 00:39:19.435746 10, 0xFFFF, sum = 0
8513 00:39:19.438988 11, 0xFFFF, sum = 0
8514 00:39:19.439089 12, 0xFFFF, sum = 0
8515 00:39:19.441883 13, 0xFFFF, sum = 0
8516 00:39:19.441966 14, 0x0, sum = 1
8517 00:39:19.445204 15, 0x0, sum = 2
8518 00:39:19.445354 16, 0x0, sum = 3
8519 00:39:19.448716 17, 0x0, sum = 4
8520 00:39:19.448822 best_step = 15
8521 00:39:19.448912
8522 00:39:19.448996 ==
8523 00:39:19.451669 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 00:39:19.458594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 00:39:19.458678 ==
8526 00:39:19.458739 RX Vref Scan: 1
8527 00:39:19.458796
8528 00:39:19.462053 Set Vref Range= 24 -> 127
8529 00:39:19.462122
8530 00:39:19.465738 RX Vref 24 -> 127, step: 1
8531 00:39:19.465815
8532 00:39:19.465887 RX Delay 19 -> 252, step: 4
8533 00:39:19.468584
8534 00:39:19.468680 Set Vref, RX VrefLevel [Byte0]: 24
8535 00:39:19.471806 [Byte1]: 24
8536 00:39:19.475817
8537 00:39:19.475914 Set Vref, RX VrefLevel [Byte0]: 25
8538 00:39:19.479338 [Byte1]: 25
8539 00:39:19.483359
8540 00:39:19.483458 Set Vref, RX VrefLevel [Byte0]: 26
8541 00:39:19.486940 [Byte1]: 26
8542 00:39:19.491108
8543 00:39:19.491183 Set Vref, RX VrefLevel [Byte0]: 27
8544 00:39:19.494336 [Byte1]: 27
8545 00:39:19.499044
8546 00:39:19.499116 Set Vref, RX VrefLevel [Byte0]: 28
8547 00:39:19.501878 [Byte1]: 28
8548 00:39:19.505991
8549 00:39:19.506060 Set Vref, RX VrefLevel [Byte0]: 29
8550 00:39:19.509459 [Byte1]: 29
8551 00:39:19.513552
8552 00:39:19.513619 Set Vref, RX VrefLevel [Byte0]: 30
8553 00:39:19.517087 [Byte1]: 30
8554 00:39:19.521559
8555 00:39:19.521628 Set Vref, RX VrefLevel [Byte0]: 31
8556 00:39:19.524530 [Byte1]: 31
8557 00:39:19.528738
8558 00:39:19.528806 Set Vref, RX VrefLevel [Byte0]: 32
8559 00:39:19.532284 [Byte1]: 32
8560 00:39:19.536693
8561 00:39:19.536761 Set Vref, RX VrefLevel [Byte0]: 33
8562 00:39:19.539702 [Byte1]: 33
8563 00:39:19.544071
8564 00:39:19.544168 Set Vref, RX VrefLevel [Byte0]: 34
8565 00:39:19.547788 [Byte1]: 34
8566 00:39:19.551969
8567 00:39:19.552040 Set Vref, RX VrefLevel [Byte0]: 35
8568 00:39:19.555124 [Byte1]: 35
8569 00:39:19.559359
8570 00:39:19.559430 Set Vref, RX VrefLevel [Byte0]: 36
8571 00:39:19.562780 [Byte1]: 36
8572 00:39:19.566595
8573 00:39:19.566671 Set Vref, RX VrefLevel [Byte0]: 37
8574 00:39:19.569933 [Byte1]: 37
8575 00:39:19.574576
8576 00:39:19.574648 Set Vref, RX VrefLevel [Byte0]: 38
8577 00:39:19.577727 [Byte1]: 38
8578 00:39:19.581960
8579 00:39:19.582056 Set Vref, RX VrefLevel [Byte0]: 39
8580 00:39:19.585211 [Byte1]: 39
8581 00:39:19.589414
8582 00:39:19.589485 Set Vref, RX VrefLevel [Byte0]: 40
8583 00:39:19.593088 [Byte1]: 40
8584 00:39:19.596907
8585 00:39:19.596989 Set Vref, RX VrefLevel [Byte0]: 41
8586 00:39:19.600416 [Byte1]: 41
8587 00:39:19.604398
8588 00:39:19.604478 Set Vref, RX VrefLevel [Byte0]: 42
8589 00:39:19.607994 [Byte1]: 42
8590 00:39:19.611929
8591 00:39:19.612023 Set Vref, RX VrefLevel [Byte0]: 43
8592 00:39:19.615596 [Byte1]: 43
8593 00:39:19.619679
8594 00:39:19.619758 Set Vref, RX VrefLevel [Byte0]: 44
8595 00:39:19.623250 [Byte1]: 44
8596 00:39:19.627415
8597 00:39:19.627495 Set Vref, RX VrefLevel [Byte0]: 45
8598 00:39:19.630760 [Byte1]: 45
8599 00:39:19.634799
8600 00:39:19.634878 Set Vref, RX VrefLevel [Byte0]: 46
8601 00:39:19.638316 [Byte1]: 46
8602 00:39:19.642743
8603 00:39:19.642823 Set Vref, RX VrefLevel [Byte0]: 47
8604 00:39:19.645600 [Byte1]: 47
8605 00:39:19.650126
8606 00:39:19.650205 Set Vref, RX VrefLevel [Byte0]: 48
8607 00:39:19.653393 [Byte1]: 48
8608 00:39:19.657472
8609 00:39:19.657577 Set Vref, RX VrefLevel [Byte0]: 49
8610 00:39:19.661138 [Byte1]: 49
8611 00:39:19.665445
8612 00:39:19.665525 Set Vref, RX VrefLevel [Byte0]: 50
8613 00:39:19.668962 [Byte1]: 50
8614 00:39:19.672556
8615 00:39:19.672636 Set Vref, RX VrefLevel [Byte0]: 51
8616 00:39:19.676180 [Byte1]: 51
8617 00:39:19.680461
8618 00:39:19.680541 Set Vref, RX VrefLevel [Byte0]: 52
8619 00:39:19.683445 [Byte1]: 52
8620 00:39:19.688133
8621 00:39:19.688212 Set Vref, RX VrefLevel [Byte0]: 53
8622 00:39:19.691592 [Byte1]: 53
8623 00:39:19.695341
8624 00:39:19.695421 Set Vref, RX VrefLevel [Byte0]: 54
8625 00:39:19.698787 [Byte1]: 54
8626 00:39:19.703382
8627 00:39:19.703462 Set Vref, RX VrefLevel [Byte0]: 55
8628 00:39:19.706164 [Byte1]: 55
8629 00:39:19.710761
8630 00:39:19.710868 Set Vref, RX VrefLevel [Byte0]: 56
8631 00:39:19.714009 [Byte1]: 56
8632 00:39:19.718124
8633 00:39:19.718203 Set Vref, RX VrefLevel [Byte0]: 57
8634 00:39:19.721500 [Byte1]: 57
8635 00:39:19.725669
8636 00:39:19.725749 Set Vref, RX VrefLevel [Byte0]: 58
8637 00:39:19.728955 [Byte1]: 58
8638 00:39:19.733235
8639 00:39:19.733322 Set Vref, RX VrefLevel [Byte0]: 59
8640 00:39:19.736985 [Byte1]: 59
8641 00:39:19.740870
8642 00:39:19.740950 Set Vref, RX VrefLevel [Byte0]: 60
8643 00:39:19.744265 [Byte1]: 60
8644 00:39:19.748314
8645 00:39:19.748393 Set Vref, RX VrefLevel [Byte0]: 61
8646 00:39:19.751773 [Byte1]: 61
8647 00:39:19.755980
8648 00:39:19.756063 Set Vref, RX VrefLevel [Byte0]: 62
8649 00:39:19.759174 [Byte1]: 62
8650 00:39:19.763676
8651 00:39:19.763755 Set Vref, RX VrefLevel [Byte0]: 63
8652 00:39:19.767216 [Byte1]: 63
8653 00:39:19.771428
8654 00:39:19.771508 Set Vref, RX VrefLevel [Byte0]: 64
8655 00:39:19.774514 [Byte1]: 64
8656 00:39:19.779007
8657 00:39:19.779110 Set Vref, RX VrefLevel [Byte0]: 65
8658 00:39:19.781947 [Byte1]: 65
8659 00:39:19.786410
8660 00:39:19.786484 Set Vref, RX VrefLevel [Byte0]: 66
8661 00:39:19.790039 [Byte1]: 66
8662 00:39:19.794086
8663 00:39:19.794155 Set Vref, RX VrefLevel [Byte0]: 67
8664 00:39:19.796983 [Byte1]: 67
8665 00:39:19.801525
8666 00:39:19.801606 Set Vref, RX VrefLevel [Byte0]: 68
8667 00:39:19.805115 [Byte1]: 68
8668 00:39:19.809194
8669 00:39:19.809300 Set Vref, RX VrefLevel [Byte0]: 69
8670 00:39:19.812494 [Byte1]: 69
8671 00:39:19.816708
8672 00:39:19.816789 Set Vref, RX VrefLevel [Byte0]: 70
8673 00:39:19.820388 [Byte1]: 70
8674 00:39:19.824305
8675 00:39:19.824386 Final RX Vref Byte 0 = 55 to rank0
8676 00:39:19.827406 Final RX Vref Byte 1 = 62 to rank0
8677 00:39:19.830873 Final RX Vref Byte 0 = 55 to rank1
8678 00:39:19.834080 Final RX Vref Byte 1 = 62 to rank1==
8679 00:39:19.837455 Dram Type= 6, Freq= 0, CH_1, rank 0
8680 00:39:19.844098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8681 00:39:19.844180 ==
8682 00:39:19.844243 DQS Delay:
8683 00:39:19.847290 DQS0 = 0, DQS1 = 0
8684 00:39:19.847371 DQM Delay:
8685 00:39:19.847450 DQM0 = 132, DQM1 = 130
8686 00:39:19.850519 DQ Delay:
8687 00:39:19.854109 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8688 00:39:19.857322 DQ4 =130, DQ5 =144, DQ6 =144, DQ7 =126
8689 00:39:19.860377 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8690 00:39:19.863736 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8691 00:39:19.863811
8692 00:39:19.863884
8693 00:39:19.863943
8694 00:39:19.867043 [DramC_TX_OE_Calibration] TA2
8695 00:39:19.870046 Original DQ_B0 (3 6) =30, OEN = 27
8696 00:39:19.873675 Original DQ_B1 (3 6) =30, OEN = 27
8697 00:39:19.877230 24, 0x0, End_B0=24 End_B1=24
8698 00:39:19.879974 25, 0x0, End_B0=25 End_B1=25
8699 00:39:19.880084 26, 0x0, End_B0=26 End_B1=26
8700 00:39:19.883465 27, 0x0, End_B0=27 End_B1=27
8701 00:39:19.886692 28, 0x0, End_B0=28 End_B1=28
8702 00:39:19.889993 29, 0x0, End_B0=29 End_B1=29
8703 00:39:19.890068 30, 0x0, End_B0=30 End_B1=30
8704 00:39:19.893371 31, 0x4141, End_B0=30 End_B1=30
8705 00:39:19.896866 Byte0 end_step=30 best_step=27
8706 00:39:19.900300 Byte1 end_step=30 best_step=27
8707 00:39:19.903080 Byte0 TX OE(2T, 0.5T) = (3, 3)
8708 00:39:19.906562 Byte1 TX OE(2T, 0.5T) = (3, 3)
8709 00:39:19.906659
8710 00:39:19.906756
8711 00:39:19.913413 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8712 00:39:19.916501 CH1 RK0: MR19=303, MR18=C16
8713 00:39:19.922873 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8714 00:39:19.922953
8715 00:39:19.926353 ----->DramcWriteLeveling(PI) begin...
8716 00:39:19.926427 ==
8717 00:39:19.929826 Dram Type= 6, Freq= 0, CH_1, rank 1
8718 00:39:19.933052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 00:39:19.933130 ==
8720 00:39:19.936600 Write leveling (Byte 0): 24 => 24
8721 00:39:19.939597 Write leveling (Byte 1): 26 => 26
8722 00:39:19.943188 DramcWriteLeveling(PI) end<-----
8723 00:39:19.943261
8724 00:39:19.943322 ==
8725 00:39:19.946208 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 00:39:19.949481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 00:39:19.949554 ==
8728 00:39:19.952830 [Gating] SW mode calibration
8729 00:39:19.959346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8730 00:39:19.966229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8731 00:39:19.969419 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 00:39:19.976278 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 00:39:19.979155 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8734 00:39:19.982266 1 4 12 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
8735 00:39:19.989736 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 00:39:19.992384 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 00:39:19.995819 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 00:39:20.002182 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 00:39:20.005398 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 00:39:20.008634 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8741 00:39:20.015914 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8742 00:39:20.018781 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8743 00:39:20.021858 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8744 00:39:20.028564 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 00:39:20.031986 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 00:39:20.035665 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 00:39:20.041843 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 00:39:20.045312 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8749 00:39:20.048634 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (1 1)
8750 00:39:20.055032 1 6 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8751 00:39:20.058672 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 00:39:20.061777 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 00:39:20.068526 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 00:39:20.071695 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 00:39:20.075263 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 00:39:20.081692 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8757 00:39:20.084740 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8758 00:39:20.088042 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8759 00:39:20.094639 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8760 00:39:20.097943 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 00:39:20.101306 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 00:39:20.108268 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 00:39:20.111339 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 00:39:20.114794 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 00:39:20.121441 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 00:39:20.124443 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 00:39:20.128337 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 00:39:20.135074 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 00:39:20.138174 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 00:39:20.141266 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 00:39:20.147671 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 00:39:20.151128 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8773 00:39:20.154433 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8774 00:39:20.157810 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8775 00:39:20.160949 Total UI for P1: 0, mck2ui 16
8776 00:39:20.164723 best dqsien dly found for B0: ( 1, 9, 6)
8777 00:39:20.170955 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8778 00:39:20.173976 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 00:39:20.177406 Total UI for P1: 0, mck2ui 16
8780 00:39:20.180926 best dqsien dly found for B1: ( 1, 9, 14)
8781 00:39:20.184257 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8782 00:39:20.187555 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8783 00:39:20.187623
8784 00:39:20.190811 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8785 00:39:20.197059 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8786 00:39:20.197144 [Gating] SW calibration Done
8787 00:39:20.197209 ==
8788 00:39:20.200506 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 00:39:20.207130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 00:39:20.207212 ==
8791 00:39:20.207275 RX Vref Scan: 0
8792 00:39:20.207335
8793 00:39:20.210316 RX Vref 0 -> 0, step: 1
8794 00:39:20.210397
8795 00:39:20.213801 RX Delay 0 -> 252, step: 8
8796 00:39:20.217416 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8797 00:39:20.220419 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8798 00:39:20.223761 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8799 00:39:20.230283 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8800 00:39:20.233688 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8801 00:39:20.236826 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8802 00:39:20.239942 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8803 00:39:20.243594 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8804 00:39:20.250602 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8805 00:39:20.253526 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8806 00:39:20.256393 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8807 00:39:20.259831 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8808 00:39:20.266855 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8809 00:39:20.269691 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8810 00:39:20.273210 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8811 00:39:20.276093 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8812 00:39:20.276173 ==
8813 00:39:20.279570 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 00:39:20.286378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 00:39:20.286457 ==
8816 00:39:20.286521 DQS Delay:
8817 00:39:20.286579 DQS0 = 0, DQS1 = 0
8818 00:39:20.289293 DQM Delay:
8819 00:39:20.289373 DQM0 = 136, DQM1 = 130
8820 00:39:20.292937 DQ Delay:
8821 00:39:20.296086 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8822 00:39:20.299759 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8823 00:39:20.302583 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8824 00:39:20.306064 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8825 00:39:20.306145
8826 00:39:20.306211
8827 00:39:20.306271 ==
8828 00:39:20.309680 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 00:39:20.315877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 00:39:20.315962 ==
8831 00:39:20.316025
8832 00:39:20.316083
8833 00:39:20.316140 TX Vref Scan disable
8834 00:39:20.319067 == TX Byte 0 ==
8835 00:39:20.321960 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8836 00:39:20.328930 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8837 00:39:20.329032 == TX Byte 1 ==
8838 00:39:20.331780 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8839 00:39:20.338973 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8840 00:39:20.339050 ==
8841 00:39:20.341736 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 00:39:20.345371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 00:39:20.345479 ==
8844 00:39:20.359866
8845 00:39:20.363201 TX Vref early break, caculate TX vref
8846 00:39:20.366595 TX Vref=16, minBit 9, minWin=22, winSum=378
8847 00:39:20.369952 TX Vref=18, minBit 9, minWin=22, winSum=385
8848 00:39:20.372925 TX Vref=20, minBit 8, minWin=23, winSum=393
8849 00:39:20.376365 TX Vref=22, minBit 9, minWin=23, winSum=404
8850 00:39:20.379484 TX Vref=24, minBit 9, minWin=24, winSum=407
8851 00:39:20.386437 TX Vref=26, minBit 9, minWin=24, winSum=416
8852 00:39:20.389426 TX Vref=28, minBit 9, minWin=24, winSum=418
8853 00:39:20.392932 TX Vref=30, minBit 0, minWin=25, winSum=414
8854 00:39:20.395858 TX Vref=32, minBit 8, minWin=24, winSum=410
8855 00:39:20.399594 TX Vref=34, minBit 9, minWin=23, winSum=400
8856 00:39:20.405999 TX Vref=36, minBit 9, minWin=23, winSum=397
8857 00:39:20.409418 TX Vref=38, minBit 0, minWin=22, winSum=385
8858 00:39:20.412976 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 30
8859 00:39:20.415665
8860 00:39:20.415745 Final TX Range 0 Vref 30
8861 00:39:20.415809
8862 00:39:20.415867 ==
8863 00:39:20.418899 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 00:39:20.425680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 00:39:20.425764 ==
8866 00:39:20.425829
8867 00:39:20.425888
8868 00:39:20.425944 TX Vref Scan disable
8869 00:39:20.432775 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8870 00:39:20.432857 == TX Byte 0 ==
8871 00:39:20.436052 u2DelayCellOfst[0]=14 cells (4 PI)
8872 00:39:20.439531 u2DelayCellOfst[1]=10 cells (3 PI)
8873 00:39:20.443166 u2DelayCellOfst[2]=0 cells (0 PI)
8874 00:39:20.445994 u2DelayCellOfst[3]=7 cells (2 PI)
8875 00:39:20.449450 u2DelayCellOfst[4]=7 cells (2 PI)
8876 00:39:20.452819 u2DelayCellOfst[5]=14 cells (4 PI)
8877 00:39:20.455842 u2DelayCellOfst[6]=14 cells (4 PI)
8878 00:39:20.459242 u2DelayCellOfst[7]=7 cells (2 PI)
8879 00:39:20.462714 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8880 00:39:20.466009 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8881 00:39:20.469655 == TX Byte 1 ==
8882 00:39:20.472702 u2DelayCellOfst[8]=0 cells (0 PI)
8883 00:39:20.475668 u2DelayCellOfst[9]=3 cells (1 PI)
8884 00:39:20.479329 u2DelayCellOfst[10]=10 cells (3 PI)
8885 00:39:20.482717 u2DelayCellOfst[11]=3 cells (1 PI)
8886 00:39:20.485498 u2DelayCellOfst[12]=14 cells (4 PI)
8887 00:39:20.489004 u2DelayCellOfst[13]=14 cells (4 PI)
8888 00:39:20.489111 u2DelayCellOfst[14]=14 cells (4 PI)
8889 00:39:20.492572 u2DelayCellOfst[15]=17 cells (5 PI)
8890 00:39:20.499148 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8891 00:39:20.502099 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8892 00:39:20.505434 DramC Write-DBI on
8893 00:39:20.505515 ==
8894 00:39:20.508741 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 00:39:20.512201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 00:39:20.512305 ==
8897 00:39:20.512389
8898 00:39:20.512450
8899 00:39:20.515206 TX Vref Scan disable
8900 00:39:20.515289 == TX Byte 0 ==
8901 00:39:20.522306 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8902 00:39:20.522387 == TX Byte 1 ==
8903 00:39:20.525476 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8904 00:39:20.528947 DramC Write-DBI off
8905 00:39:20.529021
8906 00:39:20.529090 [DATLAT]
8907 00:39:20.531682 Freq=1600, CH1 RK1
8908 00:39:20.531752
8909 00:39:20.531816 DATLAT Default: 0xf
8910 00:39:20.535510 0, 0xFFFF, sum = 0
8911 00:39:20.535583 1, 0xFFFF, sum = 0
8912 00:39:20.538535 2, 0xFFFF, sum = 0
8913 00:39:20.538613 3, 0xFFFF, sum = 0
8914 00:39:20.541868 4, 0xFFFF, sum = 0
8915 00:39:20.545166 5, 0xFFFF, sum = 0
8916 00:39:20.545272 6, 0xFFFF, sum = 0
8917 00:39:20.548419 7, 0xFFFF, sum = 0
8918 00:39:20.548495 8, 0xFFFF, sum = 0
8919 00:39:20.551576 9, 0xFFFF, sum = 0
8920 00:39:20.551678 10, 0xFFFF, sum = 0
8921 00:39:20.554945 11, 0xFFFF, sum = 0
8922 00:39:20.555031 12, 0xFFFF, sum = 0
8923 00:39:20.558355 13, 0xFFFF, sum = 0
8924 00:39:20.558438 14, 0x0, sum = 1
8925 00:39:20.561654 15, 0x0, sum = 2
8926 00:39:20.561735 16, 0x0, sum = 3
8927 00:39:20.564800 17, 0x0, sum = 4
8928 00:39:20.564882 best_step = 15
8929 00:39:20.564944
8930 00:39:20.565003 ==
8931 00:39:20.568245 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 00:39:20.575026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 00:39:20.575108 ==
8934 00:39:20.575172 RX Vref Scan: 0
8935 00:39:20.575234
8936 00:39:20.578401 RX Vref 0 -> 0, step: 1
8937 00:39:20.578481
8938 00:39:20.582125 RX Delay 19 -> 252, step: 4
8939 00:39:20.584772 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8940 00:39:20.588348 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8941 00:39:20.591201 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8942 00:39:20.597950 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8943 00:39:20.601107 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8944 00:39:20.604547 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8945 00:39:20.608084 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8946 00:39:20.611412 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8947 00:39:20.617704 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
8948 00:39:20.621029 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8949 00:39:20.624723 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8950 00:39:20.627763 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8951 00:39:20.630691 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8952 00:39:20.637608 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8953 00:39:20.641086 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8954 00:39:20.644039 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8955 00:39:20.644148 ==
8956 00:39:20.647482 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 00:39:20.653861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 00:39:20.653943 ==
8959 00:39:20.654006 DQS Delay:
8960 00:39:20.654064 DQS0 = 0, DQS1 = 0
8961 00:39:20.657331 DQM Delay:
8962 00:39:20.657430 DQM0 = 132, DQM1 = 127
8963 00:39:20.660814 DQ Delay:
8964 00:39:20.663656 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8965 00:39:20.667184 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =128
8966 00:39:20.670233 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8967 00:39:20.673767 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8968 00:39:20.673850
8969 00:39:20.673919
8970 00:39:20.673977
8971 00:39:20.676818 [DramC_TX_OE_Calibration] TA2
8972 00:39:20.680091 Original DQ_B0 (3 6) =30, OEN = 27
8973 00:39:20.683670 Original DQ_B1 (3 6) =30, OEN = 27
8974 00:39:20.687026 24, 0x0, End_B0=24 End_B1=24
8975 00:39:20.687101 25, 0x0, End_B0=25 End_B1=25
8976 00:39:20.690611 26, 0x0, End_B0=26 End_B1=26
8977 00:39:20.693635 27, 0x0, End_B0=27 End_B1=27
8978 00:39:20.696691 28, 0x0, End_B0=28 End_B1=28
8979 00:39:20.700620 29, 0x0, End_B0=29 End_B1=29
8980 00:39:20.700695 30, 0x0, End_B0=30 End_B1=30
8981 00:39:20.703463 31, 0x4141, End_B0=30 End_B1=30
8982 00:39:20.707004 Byte0 end_step=30 best_step=27
8983 00:39:20.709944 Byte1 end_step=30 best_step=27
8984 00:39:20.713578 Byte0 TX OE(2T, 0.5T) = (3, 3)
8985 00:39:20.716711 Byte1 TX OE(2T, 0.5T) = (3, 3)
8986 00:39:20.716788
8987 00:39:20.716848
8988 00:39:20.723396 [DQSOSCAuto] RK1, (LSB)MR18= 0x121f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
8989 00:39:20.726413 CH1 RK1: MR19=303, MR18=121F
8990 00:39:20.733064 CH1_RK1: MR19=0x303, MR18=0x121F, DQSOSC=394, MR23=63, INC=23, DEC=15
8991 00:39:20.736519 [RxdqsGatingPostProcess] freq 1600
8992 00:39:20.739783 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8993 00:39:20.743190 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 00:39:20.746250 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 00:39:20.749475 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 00:39:20.752977 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 00:39:20.756330 best DQS0 dly(2T, 0.5T) = (1, 1)
8998 00:39:20.759717 best DQS1 dly(2T, 0.5T) = (1, 1)
8999 00:39:20.762755 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9000 00:39:20.766056 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9001 00:39:20.769370 Pre-setting of DQS Precalculation
9002 00:39:20.772794 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9003 00:39:20.779475 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9004 00:39:20.788943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9005 00:39:20.789049
9006 00:39:20.789139
9007 00:39:20.792817 [Calibration Summary] 3200 Mbps
9008 00:39:20.792916 CH 0, Rank 0
9009 00:39:20.795621 SW Impedance : PASS
9010 00:39:20.795691 DUTY Scan : NO K
9011 00:39:20.798851 ZQ Calibration : PASS
9012 00:39:20.802718 Jitter Meter : NO K
9013 00:39:20.802791 CBT Training : PASS
9014 00:39:20.805869 Write leveling : PASS
9015 00:39:20.809068 RX DQS gating : PASS
9016 00:39:20.809164 RX DQ/DQS(RDDQC) : PASS
9017 00:39:20.812301 TX DQ/DQS : PASS
9018 00:39:20.815255 RX DATLAT : PASS
9019 00:39:20.815326 RX DQ/DQS(Engine): PASS
9020 00:39:20.818679 TX OE : PASS
9021 00:39:20.818784 All Pass.
9022 00:39:20.818877
9023 00:39:20.822283 CH 0, Rank 1
9024 00:39:20.822353 SW Impedance : PASS
9025 00:39:20.825136 DUTY Scan : NO K
9026 00:39:20.828709 ZQ Calibration : PASS
9027 00:39:20.828805 Jitter Meter : NO K
9028 00:39:20.832039 CBT Training : PASS
9029 00:39:20.832110 Write leveling : PASS
9030 00:39:20.835318 RX DQS gating : PASS
9031 00:39:20.838622 RX DQ/DQS(RDDQC) : PASS
9032 00:39:20.838696 TX DQ/DQS : PASS
9033 00:39:20.842430 RX DATLAT : PASS
9034 00:39:20.845362 RX DQ/DQS(Engine): PASS
9035 00:39:20.845470 TX OE : PASS
9036 00:39:20.848780 All Pass.
9037 00:39:20.848857
9038 00:39:20.848920 CH 1, Rank 0
9039 00:39:20.851735 SW Impedance : PASS
9040 00:39:20.851805 DUTY Scan : NO K
9041 00:39:20.855023 ZQ Calibration : PASS
9042 00:39:20.858668 Jitter Meter : NO K
9043 00:39:20.858738 CBT Training : PASS
9044 00:39:20.861284 Write leveling : PASS
9045 00:39:20.864760 RX DQS gating : PASS
9046 00:39:20.864856 RX DQ/DQS(RDDQC) : PASS
9047 00:39:20.868078 TX DQ/DQS : PASS
9048 00:39:20.871534 RX DATLAT : PASS
9049 00:39:20.871610 RX DQ/DQS(Engine): PASS
9050 00:39:20.874789 TX OE : PASS
9051 00:39:20.874886 All Pass.
9052 00:39:20.874973
9053 00:39:20.877897 CH 1, Rank 1
9054 00:39:20.877971 SW Impedance : PASS
9055 00:39:20.881413 DUTY Scan : NO K
9056 00:39:20.884561 ZQ Calibration : PASS
9057 00:39:20.884656 Jitter Meter : NO K
9058 00:39:20.888110 CBT Training : PASS
9059 00:39:20.891286 Write leveling : PASS
9060 00:39:20.891358 RX DQS gating : PASS
9061 00:39:20.894701 RX DQ/DQS(RDDQC) : PASS
9062 00:39:20.897986 TX DQ/DQS : PASS
9063 00:39:20.898061 RX DATLAT : PASS
9064 00:39:20.901191 RX DQ/DQS(Engine): PASS
9065 00:39:20.901330 TX OE : PASS
9066 00:39:20.904814 All Pass.
9067 00:39:20.904907
9068 00:39:20.904992 DramC Write-DBI on
9069 00:39:20.907706 PER_BANK_REFRESH: Hybrid Mode
9070 00:39:20.911544 TX_TRACKING: ON
9071 00:39:20.918155 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9072 00:39:20.927701 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9073 00:39:20.934143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9074 00:39:20.937367 [FAST_K] Save calibration result to emmc
9075 00:39:20.940813 sync common calibartion params.
9076 00:39:20.944233 sync cbt_mode0:1, 1:1
9077 00:39:20.944302 dram_init: ddr_geometry: 2
9078 00:39:20.947320 dram_init: ddr_geometry: 2
9079 00:39:20.950578 dram_init: ddr_geometry: 2
9080 00:39:20.950675 0:dram_rank_size:100000000
9081 00:39:20.954368 1:dram_rank_size:100000000
9082 00:39:20.960539 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9083 00:39:20.964082 DFS_SHUFFLE_HW_MODE: ON
9084 00:39:20.967331 dramc_set_vcore_voltage set vcore to 725000
9085 00:39:20.967408 Read voltage for 1600, 0
9086 00:39:20.970799 Vio18 = 0
9087 00:39:20.970872 Vcore = 725000
9088 00:39:20.970940 Vdram = 0
9089 00:39:20.973732 Vddq = 0
9090 00:39:20.973804 Vmddr = 0
9091 00:39:20.977002 switch to 3200 Mbps bootup
9092 00:39:20.977068 [DramcRunTimeConfig]
9093 00:39:20.977131 PHYPLL
9094 00:39:20.980132 DPM_CONTROL_AFTERK: ON
9095 00:39:20.983539 PER_BANK_REFRESH: ON
9096 00:39:20.986975 REFRESH_OVERHEAD_REDUCTION: ON
9097 00:39:20.987048 CMD_PICG_NEW_MODE: OFF
9098 00:39:20.990034 XRTWTW_NEW_MODE: ON
9099 00:39:20.990107 XRTRTR_NEW_MODE: ON
9100 00:39:20.993638 TX_TRACKING: ON
9101 00:39:20.993735 RDSEL_TRACKING: OFF
9102 00:39:20.996932 DQS Precalculation for DVFS: ON
9103 00:39:20.999896 RX_TRACKING: OFF
9104 00:39:20.999992 HW_GATING DBG: ON
9105 00:39:21.003271 ZQCS_ENABLE_LP4: ON
9106 00:39:21.003377 RX_PICG_NEW_MODE: ON
9107 00:39:21.006434 TX_PICG_NEW_MODE: ON
9108 00:39:21.006509 ENABLE_RX_DCM_DPHY: ON
9109 00:39:21.010175 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9110 00:39:21.012891 DUMMY_READ_FOR_TRACKING: OFF
9111 00:39:21.016415 !!! SPM_CONTROL_AFTERK: OFF
9112 00:39:21.019542 !!! SPM could not control APHY
9113 00:39:21.019638 IMPEDANCE_TRACKING: ON
9114 00:39:21.022733 TEMP_SENSOR: ON
9115 00:39:21.022828 HW_SAVE_FOR_SR: OFF
9116 00:39:21.025980 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9117 00:39:21.029412 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9118 00:39:21.033578 Read ODT Tracking: ON
9119 00:39:21.035891 Refresh Rate DeBounce: ON
9120 00:39:21.035958 DFS_NO_QUEUE_FLUSH: ON
9121 00:39:21.039363 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9122 00:39:21.042774 ENABLE_DFS_RUNTIME_MRW: OFF
9123 00:39:21.046244 DDR_RESERVE_NEW_MODE: ON
9124 00:39:21.046315 MR_CBT_SWITCH_FREQ: ON
9125 00:39:21.049094 =========================
9126 00:39:21.068091 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9127 00:39:21.071519 dram_init: ddr_geometry: 2
9128 00:39:21.090004 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9129 00:39:21.093204 dram_init: dram init end (result: 0)
9130 00:39:21.099356 DRAM-K: Full calibration passed in 24458 msecs
9131 00:39:21.102817 MRC: failed to locate region type 0.
9132 00:39:21.102896 DRAM rank0 size:0x100000000,
9133 00:39:21.106398 DRAM rank1 size=0x100000000
9134 00:39:21.116036 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9135 00:39:21.122684 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9136 00:39:21.132715 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9137 00:39:21.139388 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9138 00:39:21.139495 DRAM rank0 size:0x100000000,
9139 00:39:21.142071 DRAM rank1 size=0x100000000
9140 00:39:21.142144 CBMEM:
9141 00:39:21.146352 IMD: root @ 0xfffff000 254 entries.
9142 00:39:21.148947 IMD: root @ 0xffffec00 62 entries.
9143 00:39:21.155526 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9144 00:39:21.159009 WARNING: RO_VPD is uninitialized or empty.
9145 00:39:21.162371 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9146 00:39:21.169666 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9147 00:39:21.182537 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9148 00:39:21.194205 BS: romstage times (exec / console): total (unknown) / 23984 ms
9149 00:39:21.194283
9150 00:39:21.194351
9151 00:39:21.203976 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9152 00:39:21.207339 ARM64: Exception handlers installed.
9153 00:39:21.210630 ARM64: Testing exception
9154 00:39:21.213562 ARM64: Done test exception
9155 00:39:21.213634 Enumerating buses...
9156 00:39:21.217371 Show all devs... Before device enumeration.
9157 00:39:21.220066 Root Device: enabled 1
9158 00:39:21.223326 CPU_CLUSTER: 0: enabled 1
9159 00:39:21.223401 CPU: 00: enabled 1
9160 00:39:21.226801 Compare with tree...
9161 00:39:21.226880 Root Device: enabled 1
9162 00:39:21.230174 CPU_CLUSTER: 0: enabled 1
9163 00:39:21.233224 CPU: 00: enabled 1
9164 00:39:21.233350 Root Device scanning...
9165 00:39:21.236619 scan_static_bus for Root Device
9166 00:39:21.239858 CPU_CLUSTER: 0 enabled
9167 00:39:21.243314 scan_static_bus for Root Device done
9168 00:39:21.246706 scan_bus: bus Root Device finished in 8 msecs
9169 00:39:21.246779 done
9170 00:39:21.253288 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9171 00:39:21.256695 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9172 00:39:21.262870 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9173 00:39:21.269813 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9174 00:39:21.269894 Allocating resources...
9175 00:39:21.272945 Reading resources...
9176 00:39:21.276625 Root Device read_resources bus 0 link: 0
9177 00:39:21.279731 DRAM rank0 size:0x100000000,
9178 00:39:21.279803 DRAM rank1 size=0x100000000
9179 00:39:21.285907 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9180 00:39:21.285980 CPU: 00 missing read_resources
9181 00:39:21.292639 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9182 00:39:21.296136 Root Device read_resources bus 0 link: 0 done
9183 00:39:21.299375 Done reading resources.
9184 00:39:21.302474 Show resources in subtree (Root Device)...After reading.
9185 00:39:21.305643 Root Device child on link 0 CPU_CLUSTER: 0
9186 00:39:21.308830 CPU_CLUSTER: 0 child on link 0 CPU: 00
9187 00:39:21.319200 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9188 00:39:21.319310 CPU: 00
9189 00:39:21.325482 Root Device assign_resources, bus 0 link: 0
9190 00:39:21.329057 CPU_CLUSTER: 0 missing set_resources
9191 00:39:21.332368 Root Device assign_resources, bus 0 link: 0 done
9192 00:39:21.335345 Done setting resources.
9193 00:39:21.338821 Show resources in subtree (Root Device)...After assigning values.
9194 00:39:21.342324 Root Device child on link 0 CPU_CLUSTER: 0
9195 00:39:21.348507 CPU_CLUSTER: 0 child on link 0 CPU: 00
9196 00:39:21.355039 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9197 00:39:21.358389 CPU: 00
9198 00:39:21.358460 Done allocating resources.
9199 00:39:21.365177 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9200 00:39:21.365315 Enabling resources...
9201 00:39:21.368484 done.
9202 00:39:21.371497 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9203 00:39:21.374903 Initializing devices...
9204 00:39:21.374978 Root Device init
9205 00:39:21.378542 init hardware done!
9206 00:39:21.381385 0x00000018: ctrlr->caps
9207 00:39:21.381457 52.000 MHz: ctrlr->f_max
9208 00:39:21.384478 0.400 MHz: ctrlr->f_min
9209 00:39:21.388319 0x40ff8080: ctrlr->voltages
9210 00:39:21.388399 sclk: 390625
9211 00:39:21.388462 Bus Width = 1
9212 00:39:21.391224 sclk: 390625
9213 00:39:21.391293 Bus Width = 1
9214 00:39:21.394787 Early init status = 3
9215 00:39:21.397927 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9216 00:39:21.402693 in-header: 03 fc 00 00 01 00 00 00
9217 00:39:21.405935 in-data: 00
9218 00:39:21.409047 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9219 00:39:21.414984 in-header: 03 fd 00 00 00 00 00 00
9220 00:39:21.418272 in-data:
9221 00:39:21.421503 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9222 00:39:21.425971 in-header: 03 fc 00 00 01 00 00 00
9223 00:39:21.429414 in-data: 00
9224 00:39:21.432728 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9225 00:39:21.438434 in-header: 03 fd 00 00 00 00 00 00
9226 00:39:21.441426 in-data:
9227 00:39:21.444497 [SSUSB] Setting up USB HOST controller...
9228 00:39:21.448106 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9229 00:39:21.451340 [SSUSB] phy power-on done.
9230 00:39:21.454661 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9231 00:39:21.461097 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9232 00:39:21.464422 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9233 00:39:21.471270 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9234 00:39:21.478003 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9235 00:39:21.484311 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9236 00:39:21.491144 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9237 00:39:21.497616 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9238 00:39:21.500922 SPM: binary array size = 0x9dc
9239 00:39:21.504339 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9240 00:39:21.511189 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9241 00:39:21.517793 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9242 00:39:21.523967 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9243 00:39:21.527615 configure_display: Starting display init
9244 00:39:21.561161 anx7625_power_on_init: Init interface.
9245 00:39:21.564616 anx7625_disable_pd_protocol: Disabled PD feature.
9246 00:39:21.568014 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9247 00:39:21.595516 anx7625_start_dp_work: Secure OCM version=00
9248 00:39:21.599007 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9249 00:39:21.614140 sp_tx_get_edid_block: EDID Block = 1
9250 00:39:21.716262 Extracted contents:
9251 00:39:21.719866 header: 00 ff ff ff ff ff ff 00
9252 00:39:21.723364 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9253 00:39:21.726466 version: 01 04
9254 00:39:21.730020 basic params: 95 1f 11 78 0a
9255 00:39:21.733160 chroma info: 76 90 94 55 54 90 27 21 50 54
9256 00:39:21.736121 established: 00 00 00
9257 00:39:21.743193 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9258 00:39:21.746257 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9259 00:39:21.752841 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9260 00:39:21.759426 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9261 00:39:21.765727 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9262 00:39:21.769225 extensions: 00
9263 00:39:21.769350 checksum: fb
9264 00:39:21.769414
9265 00:39:21.772581 Manufacturer: IVO Model 57d Serial Number 0
9266 00:39:21.775680 Made week 0 of 2020
9267 00:39:21.778981 EDID version: 1.4
9268 00:39:21.779060 Digital display
9269 00:39:21.782734 6 bits per primary color channel
9270 00:39:21.782814 DisplayPort interface
9271 00:39:21.785786 Maximum image size: 31 cm x 17 cm
9272 00:39:21.789175 Gamma: 220%
9273 00:39:21.789315 Check DPMS levels
9274 00:39:21.792488 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9275 00:39:21.799073 First detailed timing is preferred timing
9276 00:39:21.799152 Established timings supported:
9277 00:39:21.802306 Standard timings supported:
9278 00:39:21.805873 Detailed timings
9279 00:39:21.809592 Hex of detail: 383680a07038204018303c0035ae10000019
9280 00:39:21.815815 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9281 00:39:21.819157 0780 0798 07c8 0820 hborder 0
9282 00:39:21.822078 0438 043b 0447 0458 vborder 0
9283 00:39:21.825559 -hsync -vsync
9284 00:39:21.825626 Did detailed timing
9285 00:39:21.832295 Hex of detail: 000000000000000000000000000000000000
9286 00:39:21.835395 Manufacturer-specified data, tag 0
9287 00:39:21.838860 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9288 00:39:21.842373 ASCII string: InfoVision
9289 00:39:21.845126 Hex of detail: 000000fe00523134304e574635205248200a
9290 00:39:21.848400 ASCII string: R140NWF5 RH
9291 00:39:21.848472 Checksum
9292 00:39:21.851981 Checksum: 0xfb (valid)
9293 00:39:21.855189 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9294 00:39:21.858410 DSI data_rate: 832800000 bps
9295 00:39:21.864837 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9296 00:39:21.867886 anx7625_parse_edid: pixelclock(138800).
9297 00:39:21.871545 hactive(1920), hsync(48), hfp(24), hbp(88)
9298 00:39:21.874970 vactive(1080), vsync(12), vfp(3), vbp(17)
9299 00:39:21.878074 anx7625_dsi_config: config dsi.
9300 00:39:21.884705 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9301 00:39:21.898310 anx7625_dsi_config: success to config DSI
9302 00:39:21.901891 anx7625_dp_start: MIPI phy setup OK.
9303 00:39:21.904938 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9304 00:39:21.908545 mtk_ddp_mode_set invalid vrefresh 60
9305 00:39:21.911753 main_disp_path_setup
9306 00:39:21.911829 ovl_layer_smi_id_en
9307 00:39:21.914619 ovl_layer_smi_id_en
9308 00:39:21.914692 ccorr_config
9309 00:39:21.914754 aal_config
9310 00:39:21.918200 gamma_config
9311 00:39:21.918294 postmask_config
9312 00:39:21.921313 dither_config
9313 00:39:21.924622 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9314 00:39:21.931203 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9315 00:39:21.934612 Root Device init finished in 555 msecs
9316 00:39:21.937887 CPU_CLUSTER: 0 init
9317 00:39:21.945050 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9318 00:39:21.951482 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9319 00:39:21.951585 APU_MBOX 0x190000b0 = 0x10001
9320 00:39:21.954399 APU_MBOX 0x190001b0 = 0x10001
9321 00:39:21.957935 APU_MBOX 0x190005b0 = 0x10001
9322 00:39:21.961137 APU_MBOX 0x190006b0 = 0x10001
9323 00:39:21.967556 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9324 00:39:21.977923 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9325 00:39:21.990015 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9326 00:39:21.996680 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9327 00:39:22.008082 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9328 00:39:22.017031 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9329 00:39:22.020385 CPU_CLUSTER: 0 init finished in 81 msecs
9330 00:39:22.023892 Devices initialized
9331 00:39:22.027069 Show all devs... After init.
9332 00:39:22.027149 Root Device: enabled 1
9333 00:39:22.030351 CPU_CLUSTER: 0: enabled 1
9334 00:39:22.034039 CPU: 00: enabled 1
9335 00:39:22.037388 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9336 00:39:22.040737 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9337 00:39:22.044138 ELOG: NV offset 0x57f000 size 0x1000
9338 00:39:22.050271 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9339 00:39:22.056802 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9340 00:39:22.060567 ELOG: Event(17) added with size 13 at 2024-06-05 00:39:22 UTC
9341 00:39:22.066852 out: cmd=0x121: 03 db 21 01 00 00 00 00
9342 00:39:22.070558 in-header: 03 c6 00 00 2c 00 00 00
9343 00:39:22.080443 in-data: 77 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9344 00:39:22.086682 ELOG: Event(A1) added with size 10 at 2024-06-05 00:39:22 UTC
9345 00:39:22.093093 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9346 00:39:22.099988 ELOG: Event(A0) added with size 9 at 2024-06-05 00:39:22 UTC
9347 00:39:22.103451 elog_add_boot_reason: Logged dev mode boot
9348 00:39:22.109925 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9349 00:39:22.110000 Finalize devices...
9350 00:39:22.113264 Devices finalized
9351 00:39:22.116440 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9352 00:39:22.119524 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9353 00:39:22.123277 in-header: 03 07 00 00 08 00 00 00
9354 00:39:22.126564 in-data: aa e4 47 04 13 02 00 00
9355 00:39:22.129677 Chrome EC: UHEPI supported
9356 00:39:22.136027 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9357 00:39:22.139579 in-header: 03 a9 00 00 08 00 00 00
9358 00:39:22.142670 in-data: 84 60 60 08 00 00 00 00
9359 00:39:22.150192 ELOG: Event(91) added with size 10 at 2024-06-05 00:39:22 UTC
9360 00:39:22.153020 Chrome EC: clear events_b mask to 0x0000000020004000
9361 00:39:22.159370 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9362 00:39:22.164499 in-header: 03 fd 00 00 00 00 00 00
9363 00:39:22.164578 in-data:
9364 00:39:22.171267 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9365 00:39:22.175203 Writing coreboot table at 0xffe64000
9366 00:39:22.177897 0. 000000000010a000-0000000000113fff: RAMSTAGE
9367 00:39:22.180909 1. 0000000040000000-00000000400fffff: RAM
9368 00:39:22.187365 2. 0000000040100000-000000004032afff: RAMSTAGE
9369 00:39:22.191042 3. 000000004032b000-00000000545fffff: RAM
9370 00:39:22.194214 4. 0000000054600000-000000005465ffff: BL31
9371 00:39:22.197482 5. 0000000054660000-00000000ffe63fff: RAM
9372 00:39:22.204153 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9373 00:39:22.207592 7. 0000000100000000-000000023fffffff: RAM
9374 00:39:22.210665 Passing 5 GPIOs to payload:
9375 00:39:22.214135 NAME | PORT | POLARITY | VALUE
9376 00:39:22.220526 EC in RW | 0x000000aa | low | undefined
9377 00:39:22.223680 EC interrupt | 0x00000005 | low | undefined
9378 00:39:22.227060 TPM interrupt | 0x000000ab | high | undefined
9379 00:39:22.233328 SD card detect | 0x00000011 | high | undefined
9380 00:39:22.237345 speaker enable | 0x00000093 | high | undefined
9381 00:39:22.240045 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9382 00:39:22.243660 in-header: 03 f9 00 00 02 00 00 00
9383 00:39:22.246867 in-data: 02 00
9384 00:39:22.250066 ADC[4]: Raw value=902955 ID=7
9385 00:39:22.250160 ADC[3]: Raw value=213546 ID=1
9386 00:39:22.253249 RAM Code: 0x71
9387 00:39:22.256542 ADC[6]: Raw value=75000 ID=0
9388 00:39:22.260125 ADC[5]: Raw value=213546 ID=1
9389 00:39:22.260194 SKU Code: 0x1
9390 00:39:22.266358 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c44e
9391 00:39:22.266470 coreboot table: 964 bytes.
9392 00:39:22.269971 IMD ROOT 0. 0xfffff000 0x00001000
9393 00:39:22.273017 IMD SMALL 1. 0xffffe000 0x00001000
9394 00:39:22.276496 RO MCACHE 2. 0xffffc000 0x00001104
9395 00:39:22.279646 CONSOLE 3. 0xfff7c000 0x00080000
9396 00:39:22.283269 FMAP 4. 0xfff7b000 0x00000452
9397 00:39:22.286294 TIME STAMP 5. 0xfff7a000 0x00000910
9398 00:39:22.289866 VBOOT WORK 6. 0xfff66000 0x00014000
9399 00:39:22.293409 RAMOOPS 7. 0xffe66000 0x00100000
9400 00:39:22.296063 COREBOOT 8. 0xffe64000 0x00002000
9401 00:39:22.299742 IMD small region:
9402 00:39:22.303008 IMD ROOT 0. 0xffffec00 0x00000400
9403 00:39:22.305989 VPD 1. 0xffffeb80 0x0000006c
9404 00:39:22.309370 MMC STATUS 2. 0xffffeb60 0x00000004
9405 00:39:22.316193 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9406 00:39:22.322576 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9407 00:39:22.360934 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9408 00:39:22.364250 Checking segment from ROM address 0x40100000
9409 00:39:22.367551 Checking segment from ROM address 0x4010001c
9410 00:39:22.373830 Loading segment from ROM address 0x40100000
9411 00:39:22.373907 code (compression=0)
9412 00:39:22.383872 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9413 00:39:22.390630 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9414 00:39:22.390715 it's not compressed!
9415 00:39:22.396938 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9416 00:39:22.404002 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9417 00:39:22.421422 Loading segment from ROM address 0x4010001c
9418 00:39:22.421505 Entry Point 0x80000000
9419 00:39:22.424378 Loaded segments
9420 00:39:22.427871 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9421 00:39:22.434210 Jumping to boot code at 0x80000000(0xffe64000)
9422 00:39:22.441104 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9423 00:39:22.447759 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9424 00:39:22.455479 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9425 00:39:22.458863 Checking segment from ROM address 0x40100000
9426 00:39:22.462529 Checking segment from ROM address 0x4010001c
9427 00:39:22.469206 Loading segment from ROM address 0x40100000
9428 00:39:22.469334 code (compression=1)
9429 00:39:22.475333 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9430 00:39:22.485377 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9431 00:39:22.485457 using LZMA
9432 00:39:22.494012 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9433 00:39:22.500320 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9434 00:39:22.503817 Loading segment from ROM address 0x4010001c
9435 00:39:22.507250 Entry Point 0x54601000
9436 00:39:22.507325 Loaded segments
9437 00:39:22.510266 NOTICE: MT8192 bl31_setup
9438 00:39:22.517451 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9439 00:39:22.520877 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9440 00:39:22.524171 WARNING: region 0:
9441 00:39:22.527852 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 00:39:22.527926 WARNING: region 1:
9443 00:39:22.534349 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9444 00:39:22.538141 WARNING: region 2:
9445 00:39:22.540495 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9446 00:39:22.544150 WARNING: region 3:
9447 00:39:22.550914 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 00:39:22.550990 WARNING: region 4:
9449 00:39:22.557014 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 00:39:22.557090 WARNING: region 5:
9451 00:39:22.560468 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 00:39:22.563952 WARNING: region 6:
9453 00:39:22.566957 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 00:39:22.570111 WARNING: region 7:
9455 00:39:22.573579 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 00:39:22.580242 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9457 00:39:22.583663 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9458 00:39:22.590078 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9459 00:39:22.593371 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9460 00:39:22.596796 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9461 00:39:22.603564 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9462 00:39:22.606455 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9463 00:39:22.609998 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9464 00:39:22.616321 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9465 00:39:22.619880 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9466 00:39:22.626608 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9467 00:39:22.629826 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9468 00:39:22.633227 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9469 00:39:22.639624 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9470 00:39:22.643045 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9471 00:39:22.650131 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9472 00:39:22.652851 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9473 00:39:22.656079 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9474 00:39:22.662673 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9475 00:39:22.666209 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9476 00:39:22.672852 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9477 00:39:22.675770 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9478 00:39:22.679210 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9479 00:39:22.685745 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9480 00:39:22.688920 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9481 00:39:22.695841 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9482 00:39:22.699232 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9483 00:39:22.702134 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9484 00:39:22.708619 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9485 00:39:22.712445 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9486 00:39:22.718750 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9487 00:39:22.722078 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9488 00:39:22.725601 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9489 00:39:22.731767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9490 00:39:22.735112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9491 00:39:22.738259 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9492 00:39:22.741687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9493 00:39:22.748066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9494 00:39:22.751226 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9495 00:39:22.754818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9496 00:39:22.757764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9497 00:39:22.764649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9498 00:39:22.767671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9499 00:39:22.770939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9500 00:39:22.777674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9501 00:39:22.781463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9502 00:39:22.784332 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9503 00:39:22.787784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9504 00:39:22.794460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9505 00:39:22.797398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9506 00:39:22.803815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9507 00:39:22.807514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9508 00:39:22.814003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9509 00:39:22.817463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9510 00:39:22.820378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9511 00:39:22.827607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9512 00:39:22.830351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9513 00:39:22.837023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9514 00:39:22.840433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9515 00:39:22.846577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9516 00:39:22.849926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9517 00:39:22.856675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9518 00:39:22.859992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9519 00:39:22.863438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9520 00:39:22.869822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9521 00:39:22.873122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9522 00:39:22.879739 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9523 00:39:22.883376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9524 00:39:22.889659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9525 00:39:22.893237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9526 00:39:22.899647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9527 00:39:22.902898 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9528 00:39:22.906325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9529 00:39:22.912736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9530 00:39:22.916150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9531 00:39:22.922692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9532 00:39:22.926189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9533 00:39:22.932793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9534 00:39:22.936374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9535 00:39:22.942562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9536 00:39:22.946258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9537 00:39:22.949241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9538 00:39:22.956028 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9539 00:39:22.959222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9540 00:39:22.965944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9541 00:39:22.969079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9542 00:39:22.975784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9543 00:39:22.978865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9544 00:39:22.985730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9545 00:39:22.989467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9546 00:39:22.991952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9547 00:39:22.998764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9548 00:39:23.002245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9549 00:39:23.008770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9550 00:39:23.012182 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9551 00:39:23.018710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9552 00:39:23.021854 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9553 00:39:23.025594 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9554 00:39:23.031770 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9555 00:39:23.035000 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9556 00:39:23.038541 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9557 00:39:23.041407 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9558 00:39:23.048112 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9559 00:39:23.051319 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9560 00:39:23.058368 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9561 00:39:23.061064 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9562 00:39:23.067966 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9563 00:39:23.071312 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9564 00:39:23.074827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9565 00:39:23.081012 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9566 00:39:23.084582 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9567 00:39:23.091114 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9568 00:39:23.094433 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9569 00:39:23.098045 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9570 00:39:23.103895 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9571 00:39:23.108033 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9572 00:39:23.110617 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9573 00:39:23.117352 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9574 00:39:23.120697 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9575 00:39:23.124274 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9576 00:39:23.130613 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9577 00:39:23.134099 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9578 00:39:23.137008 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9579 00:39:23.140905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9580 00:39:23.147087 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9581 00:39:23.150719 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9582 00:39:23.157105 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9583 00:39:23.160373 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9584 00:39:23.163444 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9585 00:39:23.170519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9586 00:39:23.173666 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9587 00:39:23.180134 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9588 00:39:23.183501 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9589 00:39:23.186701 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9590 00:39:23.193118 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9591 00:39:23.196605 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9592 00:39:23.203448 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9593 00:39:23.206715 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9594 00:39:23.209641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9595 00:39:23.216140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9596 00:39:23.219633 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9597 00:39:23.226002 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9598 00:39:23.229321 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9599 00:39:23.232812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9600 00:39:23.239495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9601 00:39:23.242767 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9602 00:39:23.249539 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9603 00:39:23.252939 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9604 00:39:23.256338 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9605 00:39:23.262537 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9606 00:39:23.265944 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9607 00:39:23.272431 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9608 00:39:23.276018 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9609 00:39:23.279303 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9610 00:39:23.285651 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9611 00:39:23.288848 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9612 00:39:23.295579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9613 00:39:23.298730 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9614 00:39:23.302498 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9615 00:39:23.309089 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9616 00:39:23.312201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9617 00:39:23.318710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9618 00:39:23.322057 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9619 00:39:23.325418 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9620 00:39:23.332168 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9621 00:39:23.335422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9622 00:39:23.341912 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9623 00:39:23.345567 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9624 00:39:23.348427 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9625 00:39:23.355024 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9626 00:39:23.358356 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9627 00:39:23.365178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9628 00:39:23.368655 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9629 00:39:23.371747 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9630 00:39:23.378082 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9631 00:39:23.381825 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9632 00:39:23.388494 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9633 00:39:23.391583 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9634 00:39:23.394944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9635 00:39:23.401352 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9636 00:39:23.404764 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9637 00:39:23.411588 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9638 00:39:23.414619 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9639 00:39:23.417835 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9640 00:39:23.424815 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9641 00:39:23.428136 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9642 00:39:23.431109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9643 00:39:23.437791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9644 00:39:23.441395 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9645 00:39:23.447940 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9646 00:39:23.450799 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9647 00:39:23.457435 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9648 00:39:23.461127 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9649 00:39:23.464146 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9650 00:39:23.471042 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9651 00:39:23.474023 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9652 00:39:23.481130 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9653 00:39:23.484330 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9654 00:39:23.490316 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9655 00:39:23.493975 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9656 00:39:23.497217 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9657 00:39:23.503962 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9658 00:39:23.506720 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9659 00:39:23.513187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9660 00:39:23.516659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9661 00:39:23.523389 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9662 00:39:23.526592 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9663 00:39:23.529935 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9664 00:39:23.536478 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9665 00:39:23.540053 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9666 00:39:23.546804 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9667 00:39:23.550066 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9668 00:39:23.556563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9669 00:39:23.559786 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9670 00:39:23.563385 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9671 00:39:23.569586 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9672 00:39:23.573310 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9673 00:39:23.579791 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9674 00:39:23.582923 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9675 00:39:23.589226 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9676 00:39:23.592745 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9677 00:39:23.596485 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9678 00:39:23.602732 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9679 00:39:23.605919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9680 00:39:23.612521 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9681 00:39:23.616020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9682 00:39:23.619502 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9683 00:39:23.626087 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9684 00:39:23.629120 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9685 00:39:23.635848 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9686 00:39:23.638805 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9687 00:39:23.642775 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9688 00:39:23.645631 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9689 00:39:23.649163 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9690 00:39:23.655807 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9691 00:39:23.659277 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9692 00:39:23.665734 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9693 00:39:23.668727 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9694 00:39:23.672105 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9695 00:39:23.678942 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9696 00:39:23.681945 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9697 00:39:23.688277 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9698 00:39:23.691682 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9699 00:39:23.695085 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9700 00:39:23.701795 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9701 00:39:23.705077 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9702 00:39:23.708155 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9703 00:39:23.714916 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9704 00:39:23.718038 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9705 00:39:23.721497 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9706 00:39:23.728171 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9707 00:39:23.731849 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9708 00:39:23.738143 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9709 00:39:23.741501 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9710 00:39:23.744573 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9711 00:39:23.751355 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9712 00:39:23.754853 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9713 00:39:23.761142 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9714 00:39:23.764676 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9715 00:39:23.767502 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9716 00:39:23.774077 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9717 00:39:23.777670 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9718 00:39:23.780594 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9719 00:39:23.787512 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9720 00:39:23.790914 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9721 00:39:23.797149 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9722 00:39:23.800783 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9723 00:39:23.804009 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9724 00:39:23.810281 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9725 00:39:23.813650 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9726 00:39:23.816895 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9727 00:39:23.820088 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9728 00:39:23.826782 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9729 00:39:23.829998 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9730 00:39:23.833158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9731 00:39:23.837035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9732 00:39:23.843301 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9733 00:39:23.846644 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9734 00:39:23.849654 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9735 00:39:23.853364 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9736 00:39:23.859685 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9737 00:39:23.863003 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9738 00:39:23.866144 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9739 00:39:23.873355 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9740 00:39:23.876360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9741 00:39:23.882909 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9742 00:39:23.885979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9743 00:39:23.892991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9744 00:39:23.895978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9745 00:39:23.899422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9746 00:39:23.905652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9747 00:39:23.909187 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9748 00:39:23.915868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9749 00:39:23.918967 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9750 00:39:23.925433 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9751 00:39:23.928968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9752 00:39:23.932106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9753 00:39:23.938551 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9754 00:39:23.942482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9755 00:39:23.948660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9756 00:39:23.951967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9757 00:39:23.955255 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9758 00:39:23.961879 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9759 00:39:23.965121 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9760 00:39:23.971546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9761 00:39:23.974770 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9762 00:39:23.978246 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9763 00:39:23.984770 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9764 00:39:23.988545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9765 00:39:23.994712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9766 00:39:23.998075 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9767 00:39:24.004488 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9768 00:39:24.008081 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9769 00:39:24.011371 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9770 00:39:24.017780 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9771 00:39:24.021152 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9772 00:39:24.027677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9773 00:39:24.031092 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9774 00:39:24.037495 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9775 00:39:24.040939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9776 00:39:24.044049 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9777 00:39:24.050874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9778 00:39:24.054176 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9779 00:39:24.060376 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9780 00:39:24.063934 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9781 00:39:24.070184 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9782 00:39:24.073761 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9783 00:39:24.077064 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9784 00:39:24.083431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9785 00:39:24.086685 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9786 00:39:24.093590 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9787 00:39:24.097090 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9788 00:39:24.100241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9789 00:39:24.106708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9790 00:39:24.109666 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9791 00:39:24.116955 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9792 00:39:24.119967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9793 00:39:24.123045 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9794 00:39:24.129923 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9795 00:39:24.132756 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9796 00:39:24.139461 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9797 00:39:24.142978 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9798 00:39:24.149439 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9799 00:39:24.152953 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9800 00:39:24.159148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9801 00:39:24.162483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9802 00:39:24.166154 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9803 00:39:24.172914 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9804 00:39:24.175653 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9805 00:39:24.182372 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9806 00:39:24.186080 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9807 00:39:24.189081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9808 00:39:24.195665 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9809 00:39:24.198968 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9810 00:39:24.205528 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9811 00:39:24.208613 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9812 00:39:24.215758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9813 00:39:24.219115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9814 00:39:24.222221 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9815 00:39:24.228856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9816 00:39:24.231843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9817 00:39:24.238757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9818 00:39:24.241815 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9819 00:39:24.248189 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9820 00:39:24.251446 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9821 00:39:24.258519 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9822 00:39:24.261545 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9823 00:39:24.267898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9824 00:39:24.271175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9825 00:39:24.274777 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9826 00:39:24.281075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9827 00:39:24.284615 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9828 00:39:24.291109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9829 00:39:24.294468 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9830 00:39:24.301085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9831 00:39:24.304528 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9832 00:39:24.310940 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9833 00:39:24.314328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9834 00:39:24.317618 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9835 00:39:24.324014 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9836 00:39:24.327280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9837 00:39:24.334067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9838 00:39:24.337705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9839 00:39:24.344254 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9840 00:39:24.346986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9841 00:39:24.350607 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9842 00:39:24.357165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9843 00:39:24.360589 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9844 00:39:24.367070 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9845 00:39:24.370332 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9846 00:39:24.376628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9847 00:39:24.380002 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9848 00:39:24.387118 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9849 00:39:24.390366 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9850 00:39:24.393371 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9851 00:39:24.400305 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9852 00:39:24.403299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9853 00:39:24.409647 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9854 00:39:24.413137 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9855 00:39:24.419802 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9856 00:39:24.422996 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9857 00:39:24.429408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9858 00:39:24.432788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9859 00:39:24.436374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9860 00:39:24.443119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9861 00:39:24.446026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9862 00:39:24.452363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9863 00:39:24.456121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9864 00:39:24.462765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9865 00:39:24.465458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9866 00:39:24.472019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9867 00:39:24.475598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9868 00:39:24.482368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9869 00:39:24.485517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9870 00:39:24.492146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9871 00:39:24.495369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9872 00:39:24.501935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9873 00:39:24.505810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9874 00:39:24.511793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9875 00:39:24.515274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9876 00:39:24.521406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9877 00:39:24.524796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9878 00:39:24.531260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9879 00:39:24.534529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9880 00:39:24.541494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9881 00:39:24.544492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9882 00:39:24.551451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9883 00:39:24.554612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9884 00:39:24.561275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9885 00:39:24.564922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9886 00:39:24.570869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9887 00:39:24.574614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9888 00:39:24.581098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9889 00:39:24.584743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9890 00:39:24.590570 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9891 00:39:24.590653 INFO: [APUAPC] vio 0
9892 00:39:24.597592 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9893 00:39:24.600953 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9894 00:39:24.603912 INFO: [APUAPC] D0_APC_0: 0x400510
9895 00:39:24.607282 INFO: [APUAPC] D0_APC_1: 0x0
9896 00:39:24.610658 INFO: [APUAPC] D0_APC_2: 0x1540
9897 00:39:24.614117 INFO: [APUAPC] D0_APC_3: 0x0
9898 00:39:24.617430 INFO: [APUAPC] D1_APC_0: 0xffffffff
9899 00:39:24.620531 INFO: [APUAPC] D1_APC_1: 0xffffffff
9900 00:39:24.623878 INFO: [APUAPC] D1_APC_2: 0x3fffff
9901 00:39:24.627369 INFO: [APUAPC] D1_APC_3: 0x0
9902 00:39:24.630329 INFO: [APUAPC] D2_APC_0: 0xffffffff
9903 00:39:24.633568 INFO: [APUAPC] D2_APC_1: 0xffffffff
9904 00:39:24.636776 INFO: [APUAPC] D2_APC_2: 0x3fffff
9905 00:39:24.640362 INFO: [APUAPC] D2_APC_3: 0x0
9906 00:39:24.643686 INFO: [APUAPC] D3_APC_0: 0xffffffff
9907 00:39:24.647065 INFO: [APUAPC] D3_APC_1: 0xffffffff
9908 00:39:24.650131 INFO: [APUAPC] D3_APC_2: 0x3fffff
9909 00:39:24.653608 INFO: [APUAPC] D3_APC_3: 0x0
9910 00:39:24.656666 INFO: [APUAPC] D4_APC_0: 0xffffffff
9911 00:39:24.659952 INFO: [APUAPC] D4_APC_1: 0xffffffff
9912 00:39:24.663097 INFO: [APUAPC] D4_APC_2: 0x3fffff
9913 00:39:24.666469 INFO: [APUAPC] D4_APC_3: 0x0
9914 00:39:24.669575 INFO: [APUAPC] D5_APC_0: 0xffffffff
9915 00:39:24.673239 INFO: [APUAPC] D5_APC_1: 0xffffffff
9916 00:39:24.676098 INFO: [APUAPC] D5_APC_2: 0x3fffff
9917 00:39:24.679332 INFO: [APUAPC] D5_APC_3: 0x0
9918 00:39:24.682931 INFO: [APUAPC] D6_APC_0: 0xffffffff
9919 00:39:24.686377 INFO: [APUAPC] D6_APC_1: 0xffffffff
9920 00:39:24.689390 INFO: [APUAPC] D6_APC_2: 0x3fffff
9921 00:39:24.692503 INFO: [APUAPC] D6_APC_3: 0x0
9922 00:39:24.696484 INFO: [APUAPC] D7_APC_0: 0xffffffff
9923 00:39:24.699307 INFO: [APUAPC] D7_APC_1: 0xffffffff
9924 00:39:24.702436 INFO: [APUAPC] D7_APC_2: 0x3fffff
9925 00:39:24.705759 INFO: [APUAPC] D7_APC_3: 0x0
9926 00:39:24.709007 INFO: [APUAPC] D8_APC_0: 0xffffffff
9927 00:39:24.712639 INFO: [APUAPC] D8_APC_1: 0xffffffff
9928 00:39:24.715892 INFO: [APUAPC] D8_APC_2: 0x3fffff
9929 00:39:24.718726 INFO: [APUAPC] D8_APC_3: 0x0
9930 00:39:24.722229 INFO: [APUAPC] D9_APC_0: 0xffffffff
9931 00:39:24.725521 INFO: [APUAPC] D9_APC_1: 0xffffffff
9932 00:39:24.728988 INFO: [APUAPC] D9_APC_2: 0x3fffff
9933 00:39:24.732060 INFO: [APUAPC] D9_APC_3: 0x0
9934 00:39:24.735647 INFO: [APUAPC] D10_APC_0: 0xffffffff
9935 00:39:24.738789 INFO: [APUAPC] D10_APC_1: 0xffffffff
9936 00:39:24.741688 INFO: [APUAPC] D10_APC_2: 0x3fffff
9937 00:39:24.745386 INFO: [APUAPC] D10_APC_3: 0x0
9938 00:39:24.748291 INFO: [APUAPC] D11_APC_0: 0xffffffff
9939 00:39:24.751916 INFO: [APUAPC] D11_APC_1: 0xffffffff
9940 00:39:24.755024 INFO: [APUAPC] D11_APC_2: 0x3fffff
9941 00:39:24.758423 INFO: [APUAPC] D11_APC_3: 0x0
9942 00:39:24.761892 INFO: [APUAPC] D12_APC_0: 0xffffffff
9943 00:39:24.764967 INFO: [APUAPC] D12_APC_1: 0xffffffff
9944 00:39:24.768431 INFO: [APUAPC] D12_APC_2: 0x3fffff
9945 00:39:24.771862 INFO: [APUAPC] D12_APC_3: 0x0
9946 00:39:24.774782 INFO: [APUAPC] D13_APC_0: 0xffffffff
9947 00:39:24.778011 INFO: [APUAPC] D13_APC_1: 0xffffffff
9948 00:39:24.781149 INFO: [APUAPC] D13_APC_2: 0x3fffff
9949 00:39:24.785263 INFO: [APUAPC] D13_APC_3: 0x0
9950 00:39:24.788018 INFO: [APUAPC] D14_APC_0: 0xffffffff
9951 00:39:24.790994 INFO: [APUAPC] D14_APC_1: 0xffffffff
9952 00:39:24.794675 INFO: [APUAPC] D14_APC_2: 0x3fffff
9953 00:39:24.797839 INFO: [APUAPC] D14_APC_3: 0x0
9954 00:39:24.801338 INFO: [APUAPC] D15_APC_0: 0xffffffff
9955 00:39:24.804669 INFO: [APUAPC] D15_APC_1: 0xffffffff
9956 00:39:24.807555 INFO: [APUAPC] D15_APC_2: 0x3fffff
9957 00:39:24.811584 INFO: [APUAPC] D15_APC_3: 0x0
9958 00:39:24.814710 INFO: [APUAPC] APC_CON: 0x4
9959 00:39:24.818140 INFO: [NOCDAPC] D0_APC_0: 0x0
9960 00:39:24.818244 INFO: [NOCDAPC] D0_APC_1: 0x0
9961 00:39:24.820871 INFO: [NOCDAPC] D1_APC_0: 0x0
9962 00:39:24.824592 INFO: [NOCDAPC] D1_APC_1: 0xfff
9963 00:39:24.827464 INFO: [NOCDAPC] D2_APC_0: 0x0
9964 00:39:24.830945 INFO: [NOCDAPC] D2_APC_1: 0xfff
9965 00:39:24.834546 INFO: [NOCDAPC] D3_APC_0: 0x0
9966 00:39:24.837534 INFO: [NOCDAPC] D3_APC_1: 0xfff
9967 00:39:24.841107 INFO: [NOCDAPC] D4_APC_0: 0x0
9968 00:39:24.844006 INFO: [NOCDAPC] D4_APC_1: 0xfff
9969 00:39:24.847696 INFO: [NOCDAPC] D5_APC_0: 0x0
9970 00:39:24.850925 INFO: [NOCDAPC] D5_APC_1: 0xfff
9971 00:39:24.851028 INFO: [NOCDAPC] D6_APC_0: 0x0
9972 00:39:24.854207 INFO: [NOCDAPC] D6_APC_1: 0xfff
9973 00:39:24.857575 INFO: [NOCDAPC] D7_APC_0: 0x0
9974 00:39:24.860894 INFO: [NOCDAPC] D7_APC_1: 0xfff
9975 00:39:24.863601 INFO: [NOCDAPC] D8_APC_0: 0x0
9976 00:39:24.867230 INFO: [NOCDAPC] D8_APC_1: 0xfff
9977 00:39:24.870645 INFO: [NOCDAPC] D9_APC_0: 0x0
9978 00:39:24.873609 INFO: [NOCDAPC] D9_APC_1: 0xfff
9979 00:39:24.876999 INFO: [NOCDAPC] D10_APC_0: 0x0
9980 00:39:24.880366 INFO: [NOCDAPC] D10_APC_1: 0xfff
9981 00:39:24.883682 INFO: [NOCDAPC] D11_APC_0: 0x0
9982 00:39:24.887409 INFO: [NOCDAPC] D11_APC_1: 0xfff
9983 00:39:24.889934 INFO: [NOCDAPC] D12_APC_0: 0x0
9984 00:39:24.893538 INFO: [NOCDAPC] D12_APC_1: 0xfff
9985 00:39:24.896973 INFO: [NOCDAPC] D13_APC_0: 0x0
9986 00:39:24.897075 INFO: [NOCDAPC] D13_APC_1: 0xfff
9987 00:39:24.899747 INFO: [NOCDAPC] D14_APC_0: 0x0
9988 00:39:24.903336 INFO: [NOCDAPC] D14_APC_1: 0xfff
9989 00:39:24.906678 INFO: [NOCDAPC] D15_APC_0: 0x0
9990 00:39:24.909725 INFO: [NOCDAPC] D15_APC_1: 0xfff
9991 00:39:24.913338 INFO: [NOCDAPC] APC_CON: 0x4
9992 00:39:24.916823 INFO: [APUAPC] set_apusys_apc done
9993 00:39:24.919889 INFO: [DEVAPC] devapc_init done
9994 00:39:24.922949 INFO: GICv3 without legacy support detected.
9995 00:39:24.929766 INFO: ARM GICv3 driver initialized in EL3
9996 00:39:24.932867 INFO: Maximum SPI INTID supported: 639
9997 00:39:24.936162 INFO: BL31: Initializing runtime services
9998 00:39:24.943364 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9999 00:39:24.943478 INFO: SPM: enable CPC mode
10000 00:39:24.949458 INFO: mcdi ready for mcusys-off-idle and system suspend
10001 00:39:24.953208 INFO: BL31: Preparing for EL3 exit to normal world
10002 00:39:24.959580 INFO: Entry point address = 0x80000000
10003 00:39:24.959683 INFO: SPSR = 0x8
10004 00:39:24.965730
10005 00:39:24.965834
10006 00:39:24.965924
10007 00:39:24.969143 Starting depthcharge on Spherion...
10008 00:39:24.969244
10009 00:39:24.969336 Wipe memory regions:
10010 00:39:24.969396
10011 00:39:24.970100 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10012 00:39:24.970280 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10013 00:39:24.970392 Setting prompt string to ['asurada:']
10014 00:39:24.970515 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10015 00:39:24.972399 [0x00000040000000, 0x00000054600000)
10016 00:39:25.094738
10017 00:39:25.094903 [0x00000054660000, 0x00000080000000)
10018 00:39:25.355496
10019 00:39:25.355681 [0x000000821a7280, 0x000000ffe64000)
10020 00:39:26.099584
10021 00:39:26.099747 [0x00000100000000, 0x00000240000000)
10022 00:39:27.989755
10023 00:39:27.993355 Initializing XHCI USB controller at 0x11200000.
10024 00:39:29.031352
10025 00:39:29.034548 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10026 00:39:29.034659
10027 00:39:29.034757
10028 00:39:29.035073 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 00:39:29.135440 asurada: tftpboot 192.168.201.1 14173456/tftp-deploy-4vimbs3l/kernel/image.itb 14173456/tftp-deploy-4vimbs3l/kernel/cmdline
10031 00:39:29.135614 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 00:39:29.135731 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10033 00:39:29.139535 tftpboot 192.168.201.1 14173456/tftp-deploy-4vimbs3l/kernel/image.itp-deploy-4vimbs3l/kernel/cmdline
10034 00:39:29.139642
10035 00:39:29.139746 Waiting for link
10036 00:39:29.297717
10037 00:39:29.297874 R8152: Initializing
10038 00:39:29.297968
10039 00:39:29.301186 Version 6 (ocp_data = 5c30)
10040 00:39:29.301323
10041 00:39:29.304610 R8152: Done initializing
10042 00:39:29.304712
10043 00:39:29.304841 Adding net device
10044 00:39:31.272793
10045 00:39:31.272953 done.
10046 00:39:31.273053
10047 00:39:31.273142 MAC: 00:24:32:30:7c:7b
10048 00:39:31.273237
10049 00:39:31.276325 Sending DHCP discover... done.
10050 00:39:31.276402
10051 00:39:31.279258 Waiting for reply... done.
10052 00:39:31.279360
10053 00:39:31.282556 Sending DHCP request... done.
10054 00:39:31.282662
10055 00:39:31.282755 Waiting for reply... done.
10056 00:39:31.282849
10057 00:39:31.285823 My ip is 192.168.201.14
10058 00:39:31.285930
10059 00:39:31.288975 The DHCP server ip is 192.168.201.1
10060 00:39:31.289080
10061 00:39:31.292413 TFTP server IP predefined by user: 192.168.201.1
10062 00:39:31.292518
10063 00:39:31.298951 Bootfile predefined by user: 14173456/tftp-deploy-4vimbs3l/kernel/image.itb
10064 00:39:31.299056
10065 00:39:31.302173 Sending tftp read request... done.
10066 00:39:31.302277
10067 00:39:31.305498 Waiting for the transfer...
10068 00:39:31.308954
10069 00:39:31.822654 00000000 ################################################################
10070 00:39:31.822802
10071 00:39:32.335047 00080000 ################################################################
10072 00:39:32.335194
10073 00:39:32.846508 00100000 ################################################################
10074 00:39:32.846653
10075 00:39:33.376461 00180000 ################################################################
10076 00:39:33.376605
10077 00:39:33.888905 00200000 ################################################################
10078 00:39:33.889061
10079 00:39:34.412096 00280000 ################################################################
10080 00:39:34.412237
10081 00:39:34.930408 00300000 ################################################################
10082 00:39:34.930566
10083 00:39:35.443920 00380000 ################################################################
10084 00:39:35.444051
10085 00:39:35.959027 00400000 ################################################################
10086 00:39:35.959184
10087 00:39:36.472689 00480000 ################################################################
10088 00:39:36.472852
10089 00:39:36.988009 00500000 ################################################################
10090 00:39:36.988172
10091 00:39:37.499958 00580000 ################################################################
10092 00:39:37.500128
10093 00:39:38.016589 00600000 ################################################################
10094 00:39:38.016768
10095 00:39:38.544022 00680000 ################################################################
10096 00:39:38.544158
10097 00:39:39.092229 00700000 ################################################################
10098 00:39:39.092412
10099 00:39:39.698252 00780000 ################################################################
10100 00:39:39.698386
10101 00:39:40.317362 00800000 ################################################################
10102 00:39:40.317509
10103 00:39:40.924880 00880000 ################################################################
10104 00:39:40.925011
10105 00:39:41.526450 00900000 ################################################################
10106 00:39:41.526581
10107 00:39:42.139177 00980000 ################################################################
10108 00:39:42.139308
10109 00:39:42.757210 00a00000 ################################################################
10110 00:39:42.757384
10111 00:39:43.357006 00a80000 ################################################################
10112 00:39:43.357176
10113 00:39:43.980123 00b00000 ################################################################
10114 00:39:43.980296
10115 00:39:44.579582 00b80000 ################################################################
10116 00:39:44.579923
10117 00:39:45.174056 00c00000 ################################################################
10118 00:39:45.174185
10119 00:39:45.790838 00c80000 ################################################################
10120 00:39:45.790977
10121 00:39:46.412242 00d00000 ################################################################
10122 00:39:46.412389
10123 00:39:47.011054 00d80000 ################################################################
10124 00:39:47.011204
10125 00:39:47.598539 00e00000 ################################################################
10126 00:39:47.598674
10127 00:39:48.164560 00e80000 ################################################################
10128 00:39:48.164708
10129 00:39:48.735148 00f00000 ################################################################
10130 00:39:48.735290
10131 00:39:49.300854 00f80000 ################################################################
10132 00:39:49.300991
10133 00:39:49.879698 01000000 ################################################################
10134 00:39:49.879834
10135 00:39:50.438760 01080000 ################################################################
10136 00:39:50.438898
10137 00:39:51.018973 01100000 ################################################################
10138 00:39:51.019112
10139 00:39:51.599221 01180000 ################################################################
10140 00:39:51.599355
10141 00:39:52.178810 01200000 ################################################################
10142 00:39:52.178980
10143 00:39:52.723401 01280000 ################################################################
10144 00:39:52.723586
10145 00:39:53.299692 01300000 ################################################################
10146 00:39:53.299829
10147 00:39:53.892198 01380000 ################################################################
10148 00:39:53.892788
10149 00:39:54.496862 01400000 ################################################################
10150 00:39:54.497005
10151 00:39:55.049355 01480000 ################################################################
10152 00:39:55.049508
10153 00:39:55.647224 01500000 ################################################################
10154 00:39:55.647833
10155 00:39:56.299714 01580000 ################################################################
10156 00:39:56.299844
10157 00:39:56.963202 01600000 ################################################################
10158 00:39:56.963719
10159 00:39:57.591953 01680000 ################################################################
10160 00:39:57.592111
10161 00:39:58.171934 01700000 ################################################################
10162 00:39:58.172071
10163 00:39:58.740780 01780000 ################################################################
10164 00:39:58.740969
10165 00:39:59.372730 01800000 ################################################################
10166 00:39:59.372876
10167 00:39:59.938719 01880000 ################################################################
10168 00:39:59.938884
10169 00:40:00.498826 01900000 ################################################################
10170 00:40:00.498966
10171 00:40:01.105879 01980000 ################################################################
10172 00:40:01.106407
10173 00:40:01.771970 01a00000 ################################################################
10174 00:40:01.772097
10175 00:40:02.450198 01a80000 ################################################################
10176 00:40:02.450682
10177 00:40:03.144577 01b00000 ################################################################
10178 00:40:03.145236
10179 00:40:03.816233 01b80000 ################################################################
10180 00:40:03.816447
10181 00:40:04.369721 01c00000 ################################################################
10182 00:40:04.369868
10183 00:40:04.919786 01c80000 ################################################################
10184 00:40:04.919946
10185 00:40:05.485231 01d00000 ################################################################
10186 00:40:05.485393
10187 00:40:06.075884 01d80000 ################################################################
10188 00:40:06.076386
10189 00:40:06.723816 01e00000 ################################################################
10190 00:40:06.723948
10191 00:40:07.368918 01e80000 ################################################################
10192 00:40:07.369055
10193 00:40:07.975582 01f00000 ################################################################
10194 00:40:07.975720
10195 00:40:08.596865 01f80000 ################################################################
10196 00:40:08.596995
10197 00:40:09.263556 02000000 ################################################################
10198 00:40:09.264223
10199 00:40:09.844653 02080000 ################################################################
10200 00:40:09.844809
10201 00:40:10.398863 02100000 ################################################################
10202 00:40:10.398996
10203 00:40:10.954400 02180000 ################################################################
10204 00:40:10.954532
10205 00:40:11.519197 02200000 ################################################################
10206 00:40:11.519325
10207 00:40:12.114489 02280000 ################################################################
10208 00:40:12.114624
10209 00:40:12.718742 02300000 ################################################################
10210 00:40:12.718888
10211 00:40:13.262456 02380000 ################################################################
10212 00:40:13.262630
10213 00:40:13.796648 02400000 ################################################################
10214 00:40:13.796792
10215 00:40:14.349952 02480000 ################################################################
10216 00:40:14.350090
10217 00:40:14.895526 02500000 ################################################################
10218 00:40:14.895673
10219 00:40:15.443571 02580000 ################################################################
10220 00:40:15.443715
10221 00:40:16.072252 02600000 ################################################################
10222 00:40:16.072398
10223 00:40:16.678414 02680000 ################################################################
10224 00:40:16.678554
10225 00:40:17.328747 02700000 ################################################################
10226 00:40:17.329457
10227 00:40:17.898253 02780000 ################################################################
10228 00:40:17.898407
10229 00:40:18.448890 02800000 ################################################################
10230 00:40:18.449017
10231 00:40:19.038267 02880000 ################################################################
10232 00:40:19.038397
10233 00:40:19.668752 02900000 ################################################################
10234 00:40:19.668884
10235 00:40:20.217715 02980000 ################################################################
10236 00:40:20.217862
10237 00:40:20.834565 02a00000 ################################################################
10238 00:40:20.835332
10239 00:40:21.491923 02a80000 ################################################################
10240 00:40:21.492069
10241 00:40:22.079320 02b00000 ################################################################
10242 00:40:22.079468
10243 00:40:22.671318 02b80000 ################################################################
10244 00:40:22.671475
10245 00:40:23.222720 02c00000 ################################################################
10246 00:40:23.222859
10247 00:40:23.790687 02c80000 ################################################################
10248 00:40:23.790819
10249 00:40:24.355270 02d00000 ################################################################
10250 00:40:24.355428
10251 00:40:24.938780 02d80000 ################################################################
10252 00:40:24.938931
10253 00:40:25.604112 02e00000 ################################################################
10254 00:40:25.604615
10255 00:40:26.214869 02e80000 ################################################################
10256 00:40:26.215015
10257 00:40:26.807882 02f00000 ################################################################
10258 00:40:26.808016
10259 00:40:27.387255 02f80000 ################################################################
10260 00:40:27.387387
10261 00:40:28.008847 03000000 ################################################################
10262 00:40:28.009515
10263 00:40:28.600416 03080000 ################################################################
10264 00:40:28.600553
10265 00:40:29.255642 03100000 ################################################################
10266 00:40:29.255886
10267 00:40:29.943252 03180000 ################################################################
10268 00:40:29.943747
10269 00:40:30.613764 03200000 ################################################################
10270 00:40:30.614368
10271 00:40:31.290826 03280000 ################################################################
10272 00:40:31.291364
10273 00:40:31.948297 03300000 ################################################################
10274 00:40:31.948798
10275 00:40:32.339392 03380000 ###################################### done.
10276 00:40:32.339884
10277 00:40:32.342401 The bootfile was 54312330 bytes long.
10278 00:40:32.342857
10279 00:40:32.345494 Sending tftp read request... done.
10280 00:40:32.345908
10281 00:40:32.349775 Waiting for the transfer...
10282 00:40:32.350191
10283 00:40:32.350513 00000000 # done.
10284 00:40:32.350827
10285 00:40:32.356281 Command line loaded dynamically from TFTP file: 14173456/tftp-deploy-4vimbs3l/kernel/cmdline
10286 00:40:32.359274
10287 00:40:32.372579 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10288 00:40:32.373038
10289 00:40:32.373417 Loading FIT.
10290 00:40:32.373730
10291 00:40:32.376481 Image ramdisk-1 has 41203118 bytes.
10292 00:40:32.376952
10293 00:40:32.379420 Image fdt-1 has 47258 bytes.
10294 00:40:32.379889
10295 00:40:32.382386 Image kernel-1 has 13059919 bytes.
10296 00:40:32.382793
10297 00:40:32.389313 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10298 00:40:32.389734
10299 00:40:32.408840 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10300 00:40:32.409319
10301 00:40:32.412129 Choosing best match conf-1 for compat google,spherion-rev2.
10302 00:40:32.418105
10303 00:40:32.421841 Connected to device vid:did:rid of 1ae0:0028:00
10304 00:40:32.428937
10305 00:40:32.432029 tpm_get_response: command 0x17b, return code 0x0
10306 00:40:32.432442
10307 00:40:32.435564 ec_init: CrosEC protocol v3 supported (256, 248)
10308 00:40:32.439307
10309 00:40:32.442993 tpm_cleanup: add release locality here.
10310 00:40:32.443406
10311 00:40:32.443731 Shutting down all USB controllers.
10312 00:40:32.446073
10313 00:40:32.446481 Removing current net device
10314 00:40:32.446809
10315 00:40:32.452833 Exiting depthcharge with code 4 at timestamp: 96763258
10316 00:40:32.453245
10317 00:40:32.455961 LZMA decompressing kernel-1 to 0x821a6718
10318 00:40:32.456422
10319 00:40:32.459315 LZMA decompressing kernel-1 to 0x40000000
10320 00:40:34.069135
10321 00:40:34.069679 jumping to kernel
10322 00:40:34.071542 end: 2.2.4 bootloader-commands (duration 00:01:09) [common]
10323 00:40:34.072021 start: 2.2.5 auto-login-action (timeout 00:03:18) [common]
10324 00:40:34.072388 Setting prompt string to ['Linux version [0-9]']
10325 00:40:34.072763 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10326 00:40:34.073314 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10327 00:40:34.151051
10328 00:40:34.153973 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10329 00:40:34.157808 start: 2.2.5.1 login-action (timeout 00:03:17) [common]
10330 00:40:34.158283 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10331 00:40:34.158643 Setting prompt string to []
10332 00:40:34.159102 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10333 00:40:34.159486 Using line separator: #'\n'#
10334 00:40:34.159790 No login prompt set.
10335 00:40:34.160094 Parsing kernel messages
10336 00:40:34.160376 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10337 00:40:34.160889 [login-action] Waiting for messages, (timeout 00:03:17)
10338 00:40:34.161227 Waiting using forced prompt support (timeout 00:01:39)
10339 00:40:34.177112 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10340 00:40:34.180404 [ 0.000000] random: crng init done
10341 00:40:34.186984 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10342 00:40:34.190970 [ 0.000000] efi: UEFI not found.
10343 00:40:34.197528 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10344 00:40:34.207450 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10345 00:40:34.217401 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10346 00:40:34.223781 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10347 00:40:34.230533 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10348 00:40:34.236902 [ 0.000000] printk: bootconsole [mtk8250] enabled
10349 00:40:34.243422 [ 0.000000] NUMA: No NUMA configuration found
10350 00:40:34.250316 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10351 00:40:34.253845 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10352 00:40:34.257705 [ 0.000000] Zone ranges:
10353 00:40:34.263479 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10354 00:40:34.266537 [ 0.000000] DMA32 empty
10355 00:40:34.273997 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10356 00:40:34.277677 [ 0.000000] Movable zone start for each node
10357 00:40:34.279900 [ 0.000000] Early memory node ranges
10358 00:40:34.287274 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10359 00:40:34.293625 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10360 00:40:34.299843 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10361 00:40:34.306615 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10362 00:40:34.313085 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10363 00:40:34.319851 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10364 00:40:34.376268 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10365 00:40:34.382792 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10366 00:40:34.389100 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10367 00:40:34.392495 [ 0.000000] psci: probing for conduit method from DT.
10368 00:40:34.399158 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10369 00:40:34.402661 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10370 00:40:34.408826 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10371 00:40:34.412520 [ 0.000000] psci: SMC Calling Convention v1.2
10372 00:40:34.418872 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10373 00:40:34.422070 [ 0.000000] Detected VIPT I-cache on CPU0
10374 00:40:34.429238 [ 0.000000] CPU features: detected: GIC system register CPU interface
10375 00:40:34.435869 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10376 00:40:34.442603 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10377 00:40:34.449001 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10378 00:40:34.455796 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10379 00:40:34.465338 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10380 00:40:34.468783 [ 0.000000] alternatives: applying boot alternatives
10381 00:40:34.475665 [ 0.000000] Fallback order for Node 0: 0
10382 00:40:34.481949 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10383 00:40:34.485241 [ 0.000000] Policy zone: Normal
10384 00:40:34.498999 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10385 00:40:34.508672 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10386 00:40:34.520896 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10387 00:40:34.530325 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10388 00:40:34.537529 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10389 00:40:34.540286 <6>[ 0.000000] software IO TLB: area num 8.
10390 00:40:34.596646 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10391 00:40:34.747125 <6>[ 0.000000] Memory: 7923948K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428820K reserved, 32768K cma-reserved)
10392 00:40:34.753208 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10393 00:40:34.759621 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10394 00:40:34.763620 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10395 00:40:34.769702 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10396 00:40:34.776243 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10397 00:40:34.779848 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10398 00:40:34.789587 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10399 00:40:34.796552 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10400 00:40:34.802860 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10401 00:40:34.809349 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10402 00:40:34.812458 <6>[ 0.000000] GICv3: 608 SPIs implemented
10403 00:40:34.816392 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10404 00:40:34.822726 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10405 00:40:34.825900 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10406 00:40:34.832105 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10407 00:40:34.845546 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10408 00:40:34.859150 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10409 00:40:34.865615 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10410 00:40:34.873828 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10411 00:40:34.886269 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10412 00:40:34.892878 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10413 00:40:34.900208 <6>[ 0.009180] Console: colour dummy device 80x25
10414 00:40:34.909802 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10415 00:40:34.916874 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10416 00:40:34.919689 <6>[ 0.029286] LSM: Security Framework initializing
10417 00:40:34.926420 <6>[ 0.034254] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 00:40:34.936451 <6>[ 0.042069] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 00:40:34.942855 <6>[ 0.051324] cblist_init_generic: Setting adjustable number of callback queues.
10420 00:40:34.949725 <6>[ 0.058813] cblist_init_generic: Setting shift to 3 and lim to 1.
10421 00:40:34.959579 <6>[ 0.065150] cblist_init_generic: Setting adjustable number of callback queues.
10422 00:40:34.965877 <6>[ 0.072579] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 00:40:34.969045 <6>[ 0.079056] rcu: Hierarchical SRCU implementation.
10424 00:40:34.976120 <6>[ 0.079058] rcu: Max phase no-delay instances is 1000.
10425 00:40:34.982243 <6>[ 0.079082] printk: bootconsole [mtk8250] printing thread started
10426 00:40:34.989685 <6>[ 0.097367] EFI services will not be available.
10427 00:40:34.992855 <6>[ 0.097571] smp: Bringing up secondary CPUs ...
10428 00:40:34.996206 <6>[ 0.097871] Detected VIPT I-cache on CPU1
10429 00:40:35.003332 <6>[ 0.097939] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10430 00:40:35.013892 <6>[ 0.097970] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10431 00:40:35.021737 <6>[ 0.125846] Detected VIPT I-cache on CPU2
10432 00:40:35.027994 <6>[ 0.125901] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10433 00:40:35.037636 <6>[ 0.125919] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10434 00:40:35.041023 <6>[ 0.126176] Detected VIPT I-cache on CPU3
10435 00:40:35.048231 <6>[ 0.126224] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10436 00:40:35.054386 <6>[ 0.126238] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10437 00:40:35.057482 <6>[ 0.126543] CPU features: detected: Spectre-v4
10438 00:40:35.064612 <6>[ 0.126549] CPU features: detected: Spectre-BHB
10439 00:40:35.067623 <6>[ 0.126554] Detected PIPT I-cache on CPU4
10440 00:40:35.074073 <6>[ 0.126614] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10441 00:40:35.081002 <6>[ 0.126630] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10442 00:40:35.087159 <6>[ 0.126923] Detected PIPT I-cache on CPU5
10443 00:40:35.093793 <6>[ 0.126984] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10444 00:40:35.100387 <6>[ 0.127000] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10445 00:40:35.104155 <6>[ 0.127271] Detected PIPT I-cache on CPU6
10446 00:40:35.110501 <6>[ 0.127337] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10447 00:40:35.121124 <6>[ 0.127352] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10448 00:40:35.124943 <6>[ 0.127642] Detected PIPT I-cache on CPU7
10449 00:40:35.131056 <6>[ 0.127706] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10450 00:40:35.137738 <6>[ 0.127721] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10451 00:40:35.140978 <6>[ 0.127766] smp: Brought up 1 node, 8 CPUs
10452 00:40:35.147939 <6>[ 0.127771] SMP: Total of 8 processors activated.
10453 00:40:35.151098 <6>[ 0.127773] CPU features: detected: 32-bit EL0 Support
10454 00:40:35.161157 <6>[ 0.127776] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10455 00:40:35.167922 <6>[ 0.127778] CPU features: detected: Common not Private translations
10456 00:40:35.173926 <6>[ 0.127780] CPU features: detected: CRC32 instructions
10457 00:40:35.180843 <6>[ 0.127783] CPU features: detected: RCpc load-acquire (LDAPR)
10458 00:40:35.183882 <6>[ 0.127784] CPU features: detected: LSE atomic instructions
10459 00:40:35.190617 <6>[ 0.127786] CPU features: detected: Privileged Access Never
10460 00:40:35.197002 <6>[ 0.127787] CPU features: detected: RAS Extension Support
10461 00:40:35.203592 <6>[ 0.127791] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10462 00:40:35.207166 <6>[ 0.127858] CPU: All CPU(s) started at EL2
10463 00:40:35.213781 <6>[ 0.127859] alternatives: applying system-wide alternatives
10464 00:40:35.217118 <6>[ 0.141052] devtmpfs: initialized
10465 00:40:35.226958 <6>[ 0.147373] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10466 00:40:35.233343 <6>[ 0.147388] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10467 00:40:35.239677 <6>[ 0.148245] pinctrl core: initialized pinctrl subsystem
10468 00:40:35.265066 <6>[ 0.374541] printk:< console [ttyS0] printing thread started
10469 00:40:35.268437 6>[ 0.149426] DMI not present or invalid.
10470 00:40:35.274913 <6>[ 0.374547] printk: console [ttyS0] enabled
10471 00:40:35.278368 <6>[ 0.374550] printk: bootconsole [mtk8250] disabled
10472 00:40:35.284929 <6>[ 0.384476] printk: bootconsole [mtk8250] printing thread stopped
10473 00:40:35.291562 <6>[ 0.385742] SuperH (H)SCI(F) driver initialized
10474 00:40:35.294915 <6>[ 0.386212] msm_serial: driver initialized
10475 00:40:35.304677 <6>[ 0.390796] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10476 00:40:35.311569 <6>[ 0.390824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10477 00:40:35.321387 <6>[ 0.390853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10478 00:40:35.332983 <6>[ 0.390883] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10479 00:40:35.338828 <6>[ 0.390904] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10480 00:40:35.351626 <6>[ 0.390933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10481 00:40:35.366401 <6>[ 0.390961] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10482 00:40:35.368142 <6>[ 0.391080] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10483 00:40:35.377433 <6>[ 0.391110] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10484 00:40:35.377851 <6>[ 0.404125] loop: module loaded
10485 00:40:35.380541 <6>[ 0.406780] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10486 00:40:35.388947 <4>[ 0.423889] mtk-pmic-keys: Failed to locate of_node [id: -1]
10487 00:40:35.391732 <6>[ 0.424878] megasas: 07.719.03.00-rc1
10488 00:40:35.398714 <6>[ 0.436590] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10489 00:40:35.405729 <6>[ 0.440060] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10490 00:40:35.411602 <6>[ 0.452101] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10491 00:40:35.421516 <6>[ 0.504694] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10492 00:40:36.882602 <6>[ 1.991333] Freeing initrd memory: 40232K
10493 00:40:36.891487 <6>[ 1.998649] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10494 00:40:36.897801 <6>[ 2.003500] tun: Universal TUN/TAP device driver, 1.6
10495 00:40:36.901840 <6>[ 2.004265] thunder_xcv, ver 1.0
10496 00:40:36.904367 <6>[ 2.004283] thunder_bgx, ver 1.0
10497 00:40:36.908256 <6>[ 2.004299] nicpf, ver 1.0
10498 00:40:36.914250 <6>[ 2.005379] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10499 00:40:36.921200 <6>[ 2.005382] hns3: Copyright (c) 2017 Huawei Corporation.
10500 00:40:36.923994 <6>[ 2.005406] hclge is initializing
10501 00:40:36.931193 <6>[ 2.005419] e1000: Intel(R) PRO/1000 Network Driver
10502 00:40:36.933801 <6>[ 2.005421] e1000: Copyright (c) 1999-2006 Intel Corporation.
10503 00:40:36.941404 <6>[ 2.005437] e1000e: Intel(R) PRO/1000 Network Driver
10504 00:40:36.947926 <6>[ 2.005439] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10505 00:40:36.951126 <6>[ 2.005456] igb: Intel(R) Gigabit Ethernet Network Driver
10506 00:40:36.958186 <6>[ 2.005459] igb: Copyright (c) 2007-2014 Intel Corporation.
10507 00:40:36.964514 <6>[ 2.005472] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10508 00:40:36.971843 <6>[ 2.005474] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10509 00:40:36.975175 <6>[ 2.005761] sky2: driver version 1.30
10510 00:40:36.981817 <6>[ 2.006766] usbcore: registered new device driver r8152-cfgselector
10511 00:40:36.985074 <6>[ 2.006785] usbcore: registered new interface driver r8152
10512 00:40:36.992189 <6>[ 2.006866] VFIO - User Level meta-driver version: 0.3
10513 00:40:36.998582 <6>[ 2.009689] usbcore: registered new interface driver usb-storage
10514 00:40:37.004997 <6>[ 2.009875] usbcore: registered new device driver onboard-usb-hub
10515 00:40:37.012545 <6>[ 2.012658] mt6397-rtc mt6359-rtc: registered as rtc0
10516 00:40:37.017895 <6>[ 2.012806] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T00:40:37 UTC (1717548037)
10517 00:40:37.024800 <6>[ 2.013420] i2c_dev: i2c /dev entries driver
10518 00:40:37.031499 <6>[ 2.020638] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10519 00:40:37.037845 <4>[ 2.021364] cpu cpu0: supply cpu not found, using dummy regulator
10520 00:40:37.044636 <4>[ 2.021441] cpu cpu1: supply cpu not found, using dummy regulator
10521 00:40:37.051475 <4>[ 2.021516] cpu cpu2: supply cpu not found, using dummy regulator
10522 00:40:37.057757 <4>[ 2.021572] cpu cpu3: supply cpu not found, using dummy regulator
10523 00:40:37.064410 <4>[ 2.021649] cpu cpu4: supply cpu not found, using dummy regulator
10524 00:40:37.071205 <4>[ 2.021703] cpu cpu5: supply cpu not found, using dummy regulator
10525 00:40:37.074316 <4>[ 2.021754] cpu cpu6: supply cpu not found, using dummy regulator
10526 00:40:37.081334 <4>[ 2.021804] cpu cpu7: supply cpu not found, using dummy regulator
10527 00:40:37.087313 <6>[ 2.036773] cpu cpu0: EM: created perf domain
10528 00:40:37.091387 <6>[ 2.037093] cpu cpu4: EM: created perf domain
10529 00:40:37.097572 <6>[ 2.038829] sdhci: Secure Digital Host Controller Interface driver
10530 00:40:37.104500 <6>[ 2.038831] sdhci: Copyright(c) Pierre Ossman
10531 00:40:37.107206 <6>[ 2.039201] Synopsys Designware Multimedia Card Interface Driver
10532 00:40:37.113972 <6>[ 2.039567] sdhci-pltfm: SDHCI platform and OF driver helper
10533 00:40:37.117302 <6>[ 2.044234] mmc0: CQHCI version 5.10
10534 00:40:37.124455 <6>[ 2.049900] ledtrig-cpu: registered to indicate activity on CPUs
10535 00:40:37.130667 <6>[ 2.050773] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10536 00:40:37.137540 <6>[ 2.051050] usbcore: registered new interface driver usbhid
10537 00:40:37.140495 <6>[ 2.051051] usbhid: USB HID core driver
10538 00:40:37.146947 <6>[ 2.051173] spi_master spi0: will run message pump with realtime priority
10539 00:40:37.160215 <6>[ 2.083981] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10540 00:40:37.173066 <6>[ 2.087074] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10541 00:40:37.180547 <6>[ 2.088119] cros-ec-spi spi0.0: Chrome EC device registered
10542 00:40:37.190228 <6>[ 2.107201] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10543 00:40:37.196413 <6>[ 2.109605] NET: Registered PF_PACKET protocol family
10544 00:40:37.199675 <6>[ 2.109704] 9pnet: Installing 9P2000 support
10545 00:40:37.202887 <5>[ 2.109746] Key type dns_resolver registered
10546 00:40:37.209914 <6>[ 2.110169] registered taskstats version 1
10547 00:40:37.213100 <5>[ 2.110186] Loading compiled-in X.509 certificates
10548 00:40:37.223024 <4>[ 2.125331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 00:40:37.232902 <4>[ 2.125480] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 00:40:37.239181 <6>[ 2.133986] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10551 00:40:37.245726 <6>[ 2.134566] xhci-mtk 11200000.usb: xHCI Host Controller
10552 00:40:37.252684 <6>[ 2.134585] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10553 00:40:37.262334 <6>[ 2.134807] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10554 00:40:37.269340 <6>[ 2.134855] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10555 00:40:37.275302 <6>[ 2.135006] xhci-mtk 11200000.usb: xHCI Host Controller
10556 00:40:37.282522 <6>[ 2.135022] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10557 00:40:37.288787 <6>[ 2.135036] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10558 00:40:37.291750 <6>[ 2.135709] hub 1-0:1.0: USB hub found
10559 00:40:37.299111 <6>[ 2.135743] hub 1-0:1.0: 1 port detected
10560 00:40:37.305184 <6>[ 2.136111] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10561 00:40:37.311638 <6>[ 2.136482] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10562 00:40:37.314812 <6>[ 2.136572] hub 2-0:1.0: USB hub found
10563 00:40:37.318164 <6>[ 2.136621] hub 2-0:1.0: 1 port detected
10564 00:40:37.325079 <6>[ 2.142307] mtk-msdc 11f70000.mmc: Got CD GPIO
10565 00:40:37.328652 <6>[ 2.152783] mmc0: Command Queue Engine enabled
10566 00:40:37.334848 <6>[ 2.152800] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10567 00:40:37.341596 <6>[ 2.153430] mmcblk0: mmc0:0001 DA4128 116 GiB
10568 00:40:37.348220 <6>[ 2.156973] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10569 00:40:37.354965 <6>[ 2.158671] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10570 00:40:37.361577 <6>[ 2.158679] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10571 00:40:37.371092 <4>[ 2.158853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10572 00:40:37.377728 <6>[ 2.158863] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10573 00:40:37.381187 <6>[ 2.159463] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10574 00:40:37.391069 <6>[ 2.159493] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10575 00:40:37.397824 <6>[ 2.159496] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10576 00:40:37.404408 <6>[ 2.159659] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10577 00:40:37.414489 <6>[ 2.159670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10578 00:40:37.420776 <6>[ 2.159675] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10579 00:40:37.430508 <6>[ 2.159683] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10580 00:40:37.437543 <6>[ 2.160060] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10581 00:40:37.443638 <6>[ 2.161883] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10582 00:40:37.453801 <6>[ 2.161901] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10583 00:40:37.460423 <6>[ 2.161907] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10584 00:40:37.470265 <6>[ 2.161912] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10585 00:40:37.480145 <6>[ 2.161918] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10586 00:40:37.486972 <6>[ 2.161924] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10587 00:40:37.496420 <6>[ 2.161929] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10588 00:40:37.503157 <6>[ 2.161935] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10589 00:40:37.513072 <6>[ 2.161940] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10590 00:40:37.519887 <6>[ 2.161946] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10591 00:40:37.529744 <6>[ 2.161951] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10592 00:40:37.536386 <6>[ 2.161957] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10593 00:40:37.546208 <6>[ 2.161962] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10594 00:40:37.553033 <6>[ 2.161968] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10595 00:40:37.563112 <6>[ 2.161974] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10596 00:40:37.569153 <6>[ 2.162575] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10597 00:40:37.575628 <6>[ 2.163428] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10598 00:40:37.582313 <6>[ 2.163972] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10599 00:40:37.589134 <6>[ 2.164622] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10600 00:40:37.595734 <6>[ 2.165285] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10601 00:40:37.605560 <6>[ 2.165468] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10602 00:40:37.611911 <6>[ 2.165484] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10603 00:40:37.622048 <6>[ 2.165490] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10604 00:40:37.632187 <6>[ 2.165497] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10605 00:40:37.641525 <6>[ 2.165503] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10606 00:40:37.652190 <6>[ 2.165509] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10607 00:40:37.658291 <6>[ 2.165515] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10608 00:40:37.668698 <6>[ 2.165521] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10609 00:40:37.678334 <6>[ 2.165526] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10610 00:40:37.688179 <6>[ 2.165534] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10611 00:40:37.697641 <6>[ 2.165538] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10612 00:40:37.708000 <6>[ 2.166025] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10613 00:40:37.714566 <6>[ 2.556684] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10614 00:40:37.717661 <6>[ 2.708639] hub 1-1:1.0: USB hub found
10615 00:40:37.721235 <6>[ 2.709006] hub 1-1:1.0: 4 ports detected
10616 00:40:37.727629 <6>[ 2.712167] hub 1-1:1.0: USB hub found
10617 00:40:37.730581 <6>[ 2.712434] hub 1-1:1.0: 4 ports detected
10618 00:40:37.737431 <6>[ 2.832906] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10619 00:40:37.750963 <6>[ 2.857622] hub 2-1:1.0: USB hub found
10620 00:40:37.754269 <6>[ 2.858034] hub 2-1:1.0: 3 ports detected
10621 00:40:37.757824 <6>[ 2.861158] hub 2-1:1.0: USB hub found
10622 00:40:37.761219 <6>[ 2.861515] hub 2-1:1.0: 3 ports detected
10623 00:40:37.926610 <6>[ 3.028901] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10624 00:40:38.046763 <6>[ 3.156373] hub 1-1.4:1.0: USB hub found
10625 00:40:38.050041 <6>[ 3.156801] hub 1-1.4:1.0: 2 ports detected
10626 00:40:38.053354 <6>[ 3.159988] hub 1-1.4:1.0: USB hub found
10627 00:40:38.060052 <6>[ 3.160313] hub 1-1.4:1.0: 2 ports detected
10628 00:40:38.130387 <6>[ 3.233019] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10629 00:40:38.234465 <6>[ 3.337450] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10630 00:40:38.258937 <4>[ 3.364448] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10631 00:40:38.267846 <4>[ 3.364467] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10632 00:40:38.290616 <6>[ 3.398647] r8152 2-1.3:1.0 eth0: v1.12.13
10633 00:40:38.349850 <6>[ 3.452844] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10634 00:40:38.534447 <6>[ 3.636871] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10635 00:40:39.942569 <6>[ 5.049464] r8152 2-1.3:1.0 eth0: carrier on
10636 00:40:39.986699 <5>[ 5.076873] Sending DHCP requests ., OK
10637 00:40:39.993403 <6>[ 5.092770] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10638 00:40:39.997691 <6>[ 5.092782] IP-Config: Complete:
10639 00:40:40.006556 <6>[ 5.092783] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10640 00:40:40.017669 <6>[ 5.092792] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10641 00:40:40.023748 <6>[ 5.092796] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10642 00:40:40.030114 <6>[ 5.092801] nameserver0=192.168.201.1
10643 00:40:40.033376 <6>[ 5.093040] clk: Disabling unused clocks
10644 00:40:40.036362 <6>[ 5.093864] ALSA device list:
10645 00:40:40.039816 <6>[ 5.093873] No soundcards found.
10646 00:40:40.047249 <6>[ 5.097958] Freeing unused kernel memory: 8512K
10647 00:40:40.049411 <6>[ 5.098093] Run /init as init process
10648 00:40:40.058667 <6>[ 5.165032] NET: Registered PF_INET6 protocol family
10649 00:40:40.061892 <6>[ 5.166466] Segment Routing with IPv6
10650 00:40:40.062318
10651 00:40:40.071599 Welcome to [1mDebian GNU/Linu<6>[ 5.166479] In-situ OAM (IOAM) with IPv6
10652 00:40:40.104737 <30>[ 5.178077] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10653 00:40:40.107730 <30>[ 5.178098] systemd[1]: Detected architecture arm64.
10654 00:40:40.111673 x 12 (bookworm)[0m!
10655 00:40:40.112122
10656 00:40:40.131053 <30>[ 5.236960] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10657 00:40:40.274129 <30>[ 5.378950] systemd[1]: Queued start job for default target graphical.target.
10658 00:40:40.303812 [[0;32m OK [0m] Created slic<30>[ 5.407020] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10659 00:40:40.306997 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10660 00:40:40.330445 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 5.433647] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10661 00:40:40.333775 m-modpr…lice[0m - Slice /system/modprobe.
10662 00:40:40.359416 [[0;32m OK [0m] Created slic<30>[ 5.462101] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10663 00:40:40.365379 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10664 00:40:40.387302 [[0;32m OK [0m] Created slic<30>[ 5.490698] systemd[1]: Created slice user.slice - User and Session Slice.
10665 00:40:40.390726 e [0;1;39muser.slice[0m - User and Session Slice.
10666 00:40:40.417640 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 5.517653] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10667 00:40:40.421126 -passwo…quests to Console Directory Watch.
10668 00:40:40.445074 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 5.545024] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10669 00:40:40.448190 -passwo… Requests to Wall Directory Watch.
10670 00:40:40.483474 Expecting device [0;1;39mdev-ttyS0.dev<30>[ 5.573430] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10671 00:40:40.490028 ice[0m - /dev/t<30>[ 5.573606] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10672 00:40:40.493221 tyS0...
10673 00:40:40.514116 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 5.616979] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10674 00:40:40.516630 tsetup.…get[0m - Local Encrypted Volumes.
10675 00:40:40.540949 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 5.641008] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10676 00:40:40.544126 grityse…Local Integrity Protected Volumes.
10677 00:40:40.565990 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 5.669467] systemd[1]: Reached target paths.target - Path Units.
10678 00:40:40.566450 s.target[0m - Path Units.
10679 00:40:40.590434 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 5.693358] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10680 00:40:40.593356 te-fs.target[0m - Remote File Systems.
10681 00:40:40.613663 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 5.716950] systemd[1]: Reached target slices.target - Slice Units.
10682 00:40:40.616661 es.target[0m - Slice Units.
10683 00:40:40.638275 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 5.741379] systemd[1]: Reached target swap.target - Swaps.
10684 00:40:40.638807 .target[0m - Swaps.
10685 00:40:40.662343 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 5.765439] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10686 00:40:40.668529 tysetup… - Local Verity Protected Volumes.
10687 00:40:40.690496 [[0;32m OK [0m] Listening on<30>[ 5.793850] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10688 00:40:40.697314 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10689 00:40:40.719711 [[0;32m OK [0m] Listening on<30>[ 5.822861] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10690 00:40:40.726222 [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10691 00:40:40.749834 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 5.849539] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10692 00:40:40.753336 d-journ…t[0m - Journal Socket (/dev/log).
10693 00:40:40.774034 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 5.877561] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10694 00:40:40.777249 d-journald.socket[0m - Journal Socket.
10695 00:40:40.798119 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 5.901635] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10696 00:40:40.804439 d-netwo… - Network Service Netlink Socket.
10697 00:40:40.827075 [[0;32m OK [0m] Listening on<30>[ 5.930318] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10698 00:40:40.833659 [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10699 00:40:40.854550 [[0;32m OK [0m] Listening on<30>[ 5.958027] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10700 00:40:40.858180 [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10701 00:40:40.906372 Mounting [0;1;39mdev-hugepages.mount[<30>[ 6.009371] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10702 00:40:40.909699 0m - Huge Pages File System...
10703 00:40:40.929071 Mountin<30>[ 6.035725] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10704 00:40:40.935622 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10705 00:40:40.962776 Mounting [0;1;39msys-kernel-debug.…<30>[ 6.065499] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10706 00:40:40.965677 [0m - Kernel Debug File System...
10707 00:40:40.996451 <30>[ 6.093550] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10708 00:40:41.006571 <30>[ 6.098923] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10709 00:40:41.013035 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10710 00:40:41.038734 Starting [0;1;39mmodpr<30>[ 6.142218] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10711 00:40:41.042290 obe@configfs…m - Load Kernel Module configfs...
10712 00:40:41.070758 Starting [0;1;39mmodpr<30>[ 6.174183] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10713 00:40:41.083816 obe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 6.186594] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10714 00:40:41.084397 .
10715 00:40:41.142361 Starting [0;1;39mmodprobe@drm.service<30>[ 6.245508] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10716 00:40:41.145167 [0m - Load Kernel Module drm...
10717 00:40:41.173536 Starting [0;1;39mmodprobe@efi_psto…-<30>[ 6.276707] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10718 00:40:41.176993 Load Kernel Module efi_pstore...
10719 00:40:41.206993 Starting [0;1;39mmodpr<30>[ 6.310315] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10720 00:40:41.210304 obe@loop.ser…e[0m - Load Kernel Module loop...
10721 00:40:41.262128 Starting [0;1;39msystemd-journald.serv<30>[ 6.365427] systemd[1]: Starting systemd-journald.service - Journal Service...
10722 00:40:41.265137 ice[0m - Journal Service...
10723 00:40:41.285927 Startin<30>[ 6.392156] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10724 00:40:41.292168 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10725 00:40:41.321974 Starting [0;1;39msyste<30>[ 6.422042] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10726 00:40:41.325389 md-network-g… units from Kernel command line...
10727 00:40:41.348664 Startin<30>[ 6.451788] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10728 00:40:41.354608 g [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10729 00:40:41.374362 <30>[ 6.480368] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10730 00:40:41.380550 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10731 00:40:41.409895 [[0;32m OK [<30>[ 6.516024] systemd[1]: Started systemd-journald.service - Journal Service.
10732 00:40:41.415772 0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10733 00:40:41.438671 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10734 00:40:41.458926 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10735 00:40:41.478796 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10736 00:40:41.502986 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10737 00:40:41.529500 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10738 00:40:41.549141 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10739 00:40:41.569205 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10740 00:40:41.589214 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10741 00:40:41.614176 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10742 00:40:41.631975 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10743 00:40:41.651765 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10744 00:40:41.672241 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10745 00:40:41.687508 See 'systemctl status systemd-remount-fs.service' for details.
10746 00:40:41.707667 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10747 00:40:41.729392 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10748 00:40:41.782860 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10749 00:40:41.804845 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10750 00:40:41.818327 <46>[ 6.923294] systemd-journald[199]: Received client request to flush runtime journal.
10751 00:40:41.832728 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10752 00:40:41.857906 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10753 00:40:41.879442 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10754 00:40:41.899659 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10755 00:40:41.919917 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10756 00:40:41.939905 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10757 00:40:41.963819 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10758 00:40:41.983570 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10759 00:40:42.039229 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10760 00:40:42.075032 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10761 00:40:42.095275 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10762 00:40:42.114677 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10763 00:40:42.171682 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10764 00:40:42.196019 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10765 00:40:42.218390 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10766 00:40:42.236628 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10767 00:40:42.273085 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10768 00:40:42.300852 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10769 00:40:42.329982 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10770 00:40:42.395223 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10771 00:40:42.401394 <5>[ 7.506179] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10772 00:40:42.426560 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10773 00:40:42.437370 <5>[ 7.543277] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10774 00:40:42.447958 [[0;32m OK [<5>[ 7.543626] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10775 00:40:42.461366 0m] Started [0;<4>[ 7.543910] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10776 00:40:42.468265 1;39msystemd-tim<6>[ 7.543933] cfg80211: failed to load regulatory.db
10777 00:40:42.474817 esyncd.…0m - N<46>[ 7.568413] systemd-journald[199]: Time jumped backwards, rotating.
10778 00:40:42.477942 etwork Time Synchronization.
10779 00:40:42.496236 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10780 00:40:42.589140 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10781 00:40:42.610601 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10782 00:40:42.636480 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10783 00:40:42.645607 <3>[ 7.751328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 00:40:42.652246 <3>[ 7.751349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 00:40:42.662025 <3>[ 7.751357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 00:40:42.669298 <6>[ 7.761458] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10787 00:40:42.678936 <6>[ 7.761509] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10788 00:40:42.686103 <6>[ 7.761521] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10789 00:40:42.695414 <3>[ 7.765655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 00:40:42.701873 <3>[ 7.765678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 00:40:42.711672 <3>[ 7.765686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 00:40:42.718178 <3>[ 7.765695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 00:40:42.728125 <3>[ 7.765702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 00:40:42.734673 <6>[ 7.781738] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10795 00:40:42.741681 <3>[ 7.785161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 00:40:42.752145 <3>[ 7.794273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 00:40:42.761159 [[0;32m OK [<3>[ 7.794293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 00:40:42.768002 <3>[ 7.794302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 00:40:42.774890 0m] Reached targ<6>[ 7.797750] remoteproc remoteproc0: scp is available
10800 00:40:42.781739 et [0;1;39mtime<6>[ 7.797857] remoteproc remoteproc0: powering up scp
10801 00:40:42.791438 -set.target[0m <6>[ 7.797862] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10802 00:40:42.798089 <6>[ 7.797887] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10803 00:40:42.804710 <3>[ 7.815655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 00:40:42.811308 <3>[ 7.815674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 00:40:42.821189 <3>[ 7.815678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 00:40:42.828198 <3>[ 7.815684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 00:40:42.838628 <3>[ 7.815687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 00:40:42.845332 <3>[ 7.815727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 00:40:42.848502 <6>[ 7.886203] mc: Linux media interface: v0.10
10810 00:40:42.858445 <6>[ 7.887155] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10811 00:40:42.865810 <6>[ 7.891122] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10812 00:40:42.868754 <6>[ 7.891136] pci_bus 0000:00: root bus resource [bus 00-ff]
10813 00:40:42.875333 <6>[ 7.891142] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10814 00:40:42.888864 - System Time Se<6>[ 7.891147] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10815 00:40:42.895798 <6>[ 7.891185] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10816 00:40:42.896231 t.
10817 00:40:42.903061 <6>[ 7.891206] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10818 00:40:42.905919 <6>[ 7.891285] pci 0000:00:00.0: supports D1 D2
10819 00:40:42.912983 <6>[ 7.891289] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10820 00:40:42.923384 <4>[ 7.910541] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10821 00:40:42.926484 <4>[ 7.910541] Fallback method does not support PEC.
10822 00:40:42.933179 <4>[ 7.914750] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10823 00:40:42.943154 <4>[ 7.921443] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10824 00:40:42.950034 <6>[ 7.923607] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10825 00:40:42.956934 <6>[ 7.923615] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10826 00:40:42.962942 <6>[ 7.923626] remoteproc remoteproc0: remote processor scp is now up
10827 00:40:42.972656 [[0;32m OK [<6>[ 7.927054] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10828 00:40:42.983310 0m] Started [0;<3>[ 7.927311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10829 00:40:42.990174 1;39mfstrim.time<6>[ 7.932700] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10830 00:40:42.999828 r[0m - Discard <6>[ 7.932770] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10831 00:40:43.006912 <6>[ 7.932802] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10832 00:40:43.017240 unused blocks on<6>[ 7.932823] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10833 00:40:43.017820 ce a week.
10834 00:40:43.020543 <6>[ 7.933005] pci 0000:01:00.0: supports D1 D2
10835 00:40:43.030632 <6>[ 7.933009] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10836 00:40:43.038650 <3>[ 7.957436] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 00:40:43.044793 <3>[ 7.958054] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10838 00:40:43.058486 [[0;32m OK [0m] Reached target [0;1;39mtime<6>[ 7.973192] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10839 00:40:43.068811 rs.target[0m - <6>[ 7.973344] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10840 00:40:43.069253 Timer Units.
10841 00:40:43.075185 <6>[ 7.973355] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10842 00:40:43.085370 <6>[ 7.973388] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10843 00:40:43.092023 <6>[ 7.973405] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10844 00:40:43.098654 <6>[ 7.973422] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10845 00:40:43.105729 <6>[ 7.973440] pci 0000:00:00.0: PCI bridge to [bus 01]
10846 00:40:43.112229 <6>[ 7.973451] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10847 00:40:43.118864 <6>[ 7.974174] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10848 00:40:43.125663 <6>[ 7.975785] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10849 00:40:43.132004 <6>[ 7.976170] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10850 00:40:43.138655 <6>[ 7.980909] videodev: Linux video capture interface: v2.00
10851 00:40:43.145205 <3>[ 7.992639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 00:40:43.155600 <6>[ 7.993676] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10853 00:40:43.161760 <6>[ 7.994887] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10854 00:40:43.172068 <6>[ 8.005001] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10855 00:40:43.181815 <6>[ 8.005423] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10856 00:40:43.192433 <3>[ 8.013452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 00:40:43.201773 <6>[ 8.027205] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10858 00:40:43.208270 <3>[ 8.052842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 00:40:43.218056 <3>[ 8.053550] power_supply sbs-5-000b: driver failed to report `health' property: -6
10860 00:40:43.221728 <6>[ 8.066774] Bluetooth: Core ver 2.22
10861 00:40:43.224620 <6>[ 8.066871] NET: Registered PF_BLUETOOTH protocol family
10862 00:40:43.232240 <6>[ 8.066873] Bluetooth: HCI device and connection manager initialized
10863 00:40:43.237616 <6>[ 8.066889] Bluetooth: HCI socket layer initialized
10864 00:40:43.244297 <6>[ 8.066893] Bluetooth: L2CAP socket layer initialized
10865 00:40:43.247733 <6>[ 8.066901] Bluetooth: SCO socket layer initialized
10866 00:40:43.257775 <3>[ 8.099662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 00:40:43.264239 <3>[ 8.100516] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10868 00:40:43.271206 <6>[ 8.123797] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10869 00:40:43.284250 <6>[ 8.124881] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10870 00:40:43.290449 <6>[ 8.124979] usbcore: registered new interface driver uvcvideo
10871 00:40:43.300289 <3>[ 8.131600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 00:40:43.303619 <6>[ 8.138709] usbcore: registered new interface driver btusb
10873 00:40:43.317028 <4>[ 8.140163] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10874 00:40:43.320242 <3>[ 8.140187] Bluetooth: hci0: Failed to load firmware file (-2)
10875 00:40:43.327398 <3>[ 8.140191] Bluetooth: hci0: Failed to set up firmware (-2)
10876 00:40:43.336794 <4>[ 8.140196] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10877 00:40:43.343586 <6>[ 8.162844] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10878 00:40:43.353533 <6>[ 8.167312] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10879 00:40:43.356367 <6>[ 8.167423] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10880 00:40:43.363246 <6>[ 8.184783] mt7921e 0000:01:00.0: ASIC revision: 79610010
10881 00:40:43.373043 <6>[ 8.279450] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10882 00:40:43.373484 <6>[ 8.279450]
10883 00:40:43.382842 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10884 00:40:43.401702 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10885 00:40:43.418272 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10886 00:40:43.437633 <6>[ 8.541622] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10887 00:40:43.475393 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10888 00:40:43.503390 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10889 00:40:43.531616 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10890 00:40:43.557327 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10891 00:40:43.592429 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10892 00:40:43.650045 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10893 00:40:43.670492 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10894 00:40:43.690383 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10895 00:40:43.707186 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10896 00:40:43.767273 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10897 00:40:43.789350 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10898 00:40:43.807210 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10899 00:40:43.822569 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10900 00:40:43.842798 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10901 00:40:43.907632 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10902 00:40:43.932473 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10903 00:40:43.957242 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10904 00:40:44.028743 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10905 00:40:44.048898 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10906 00:40:44.076830 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10907 00:40:44.111747
10908 00:40:44.114895 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10909 00:40:44.115300
10910 00:40:44.118437 debian-bookworm-arm64 login: root (automatic login)
10911 00:40:44.118846
10912 00:40:44.131919 Linux debian-bookworm-arm64 6.1.92-cip22-rt12 #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 aarch64
10913 00:40:44.132438
10914 00:40:44.138475 The programs included with the Debian GNU/Linux system are free software;
10915 00:40:44.145590 the exact distribution terms for each program are described in the
10916 00:40:44.148750 individual files in /usr/share/doc/*/copyright.
10917 00:40:44.149161
10918 00:40:44.155557 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10919 00:40:44.158870 permitted by applicable law.
10920 00:40:44.160177 Matched prompt #10: / #
10922 00:40:44.161185 Setting prompt string to ['/ #']
10923 00:40:44.161825 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10925 00:40:44.163105 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10926 00:40:44.163584 start: 2.2.6 expect-shell-connection (timeout 00:03:07) [common]
10927 00:40:44.164013 Setting prompt string to ['/ #']
10928 00:40:44.164360 Forcing a shell prompt, looking for ['/ #']
10930 00:40:44.215121 / #
10931 00:40:44.215719 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10932 00:40:44.216234 Waiting using forced prompt support (timeout 00:02:30)
10933 00:40:44.221564
10934 00:40:44.222523 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10935 00:40:44.223089 start: 2.2.7 export-device-env (timeout 00:03:07) [common]
10936 00:40:44.223633 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10937 00:40:44.224114 end: 2.2 depthcharge-retry (duration 00:01:53) [common]
10938 00:40:44.224607 end: 2 depthcharge-action (duration 00:01:53) [common]
10939 00:40:44.225042 start: 3 lava-test-retry (timeout 00:07:44) [common]
10940 00:40:44.225507 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
10941 00:40:44.225980 Using namespace: common
10943 00:40:44.327053 / # #
10944 00:40:44.327676 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10945 00:40:44.328294 #<6>[ 9.396873] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10946 00:40:44.333295
10947 00:40:44.334027 Using /lava-14173456
10949 00:40:44.435071 / # export SHELL=/bin/sh
10950 00:40:44.441627 export SHELL=/bin/sh
10952 00:40:44.543000 / # . /lava-14173456/environment
10953 00:40:44.549388 . /lava-14173456/environment
10955 00:40:44.650939 / # /lava-14173456/bin/lava-test-runner /lava-14173456/0
10956 00:40:44.651571 Test shell timeout: 10s (minimum of the action and connection timeout)
10957 00:40:44.657396 /lava-14173456/bin/lava-test-runner /lava-14173456/0
10958 00:40:44.679288 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10959 00:40:44.685911 + cd /lava-14173456/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10960 00:40:44.686381 + cat uuid
10961 00:40:44.689889 + UUID=14173456_1.5.2.3.1
10962 00:40:44.690302 + set +x
10963 00:40:44.696186 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14173456_1.5.2.3.1>
10964 00:40:44.696901 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14173456_1.5.2.3.1
10965 00:40:44.697429 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14173456_1.5.2.3.1)
10966 00:40:44.697831 Skipping test definition patterns.
10967 00:40:44.699236 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10968 00:40:44.705713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10969 00:40:44.706170 device: /dev/video2
10970 00:40:44.706753 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10972 00:40:44.717393 <4>[ 9.820775] use of bytesused == 0 is deprecated and will be removed in the future,
10973 00:40:44.720620 <4>[ 9.820784] use the actual size instead.
10974 00:40:44.729219 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
10975 00:40:44.741098 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
10976 00:40:44.748525
10977 00:40:44.762939 Compliance test for mtk-vcodec-enc device /dev/video2:
10978 00:40:44.768819
10979 00:40:44.778491 Driver Info:
10980 00:40:44.788155 Driver name : mtk-vcodec-enc
10981 00:40:44.801498 Card type : MT8192 video encoder
10982 00:40:44.815239 Bus info : platform:17020000.vcodec
10983 00:40:44.821982 Driver version : 6.1.92
10984 00:40:44.833731 Capabilities : 0x84204000
10985 00:40:44.845012 Video Memory-to-Memory Multiplanar
10986 00:40:44.856544 Streaming
10987 00:40:44.871750 Extended Pix Format
10988 00:40:44.881079 Device Capabilities
10989 00:40:44.891685 Device Caps : 0x04204000
10990 00:40:44.906000 Video Memory-to-Memory Multiplanar
10991 00:40:44.917925 Streaming
10992 00:40:44.928932 Extended Pix Format
10993 00:40:44.944347 Detected Stateful Encoder
10994 00:40:44.955635
10995 00:40:44.975909 Required ioctls:
10996 00:40:44.991024 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10997 00:40:44.991565 test VIDIOC_QUERYCAP: OK
10998 00:40:44.992172 Received signal: <TESTSET> START Required-ioctls
10999 00:40:44.992643 Starting test_set Required-ioctls
11000 00:40:45.014242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11001 00:40:45.014991 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11003 00:40:45.017318 test invalid ioctls: OK
11004 00:40:45.039454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11005 00:40:45.040011
11006 00:40:45.040597 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11008 00:40:45.049546 Allow for multiple opens:
11009 00:40:45.059575 <LAVA_SIGNAL_TESTSET STOP>
11010 00:40:45.060244 Received signal: <TESTSET> STOP
11011 00:40:45.060601 Closing test_set Required-ioctls
11012 00:40:45.069367 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11013 00:40:45.070040 Received signal: <TESTSET> START Allow-for-multiple-opens
11014 00:40:45.070400 Starting test_set Allow-for-multiple-opens
11015 00:40:45.073110 test second /dev/video2 open: OK
11016 00:40:45.096497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11017 00:40:45.097320 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11019 00:40:45.099713 test VIDIOC_QUERYCAP: OK
11020 00:40:45.127516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11021 00:40:45.128294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11023 00:40:45.130267 test VIDIOC_G/S_PRIORITY: OK
11024 00:40:45.152596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11025 00:40:45.153401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11027 00:40:45.155587 test for unlimited opens: OK
11028 00:40:45.180673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11029 00:40:45.181292
11030 00:40:45.181894 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11032 00:40:45.188155 Debug ioctls:
11033 00:40:45.196029 <LAVA_SIGNAL_TESTSET STOP>
11034 00:40:45.196691 Received signal: <TESTSET> STOP
11035 00:40:45.197055 Closing test_set Allow-for-multiple-opens
11036 00:40:45.205659 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11037 00:40:45.206320 Received signal: <TESTSET> START Debug-ioctls
11038 00:40:45.206682 Starting test_set Debug-ioctls
11039 00:40:45.209399 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11040 00:40:45.230255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11041 00:40:45.231005 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11043 00:40:45.236842 test VIDIOC_LOG_STATUS: OK (Not Supported)
11044 00:40:45.255832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11045 00:40:45.256248
11046 00:40:45.256823 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11048 00:40:45.270251 Input ioctls:
11049 00:40:45.277880 <LAVA_SIGNAL_TESTSET STOP>
11050 00:40:45.278545 Received signal: <TESTSET> STOP
11051 00:40:45.278891 Closing test_set Debug-ioctls
11052 00:40:45.287527 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11053 00:40:45.288187 Received signal: <TESTSET> START Input-ioctls
11054 00:40:45.288535 Starting test_set Input-ioctls
11055 00:40:45.290626 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11056 00:40:45.315021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11057 00:40:45.315688 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11059 00:40:45.318560 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11060 00:40:45.336286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11061 00:40:45.336948 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11063 00:40:45.342373 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11064 00:40:45.361023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11065 00:40:45.361729 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11067 00:40:45.367253 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11068 00:40:45.391488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11069 00:40:45.392332 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11071 00:40:45.395093 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11072 00:40:45.419207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11073 00:40:45.419949 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11075 00:40:45.421985 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11076 00:40:45.445658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11077 00:40:45.446326 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11079 00:40:45.448558 Inputs: 0 Audio Inputs: 0 Tuners: 0
11080 00:40:45.457855
11081 00:40:45.476611 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11082 00:40:45.498322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11083 00:40:45.499033 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11085 00:40:45.505212 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11086 00:40:45.521816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11087 00:40:45.522565 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11089 00:40:45.528165 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11090 00:40:45.546061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11091 00:40:45.546315 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11093 00:40:45.552728 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11094 00:40:45.573382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11095 00:40:45.573647 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11097 00:40:45.579790 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11098 00:40:45.598009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11099 00:40:45.598688
11100 00:40:45.599309 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11102 00:40:45.618827 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11103 00:40:45.641088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11104 00:40:45.641795 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11106 00:40:45.647320 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11107 00:40:45.671218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11108 00:40:45.671983 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11110 00:40:45.675320 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11111 00:40:45.692718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11112 00:40:45.693403 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11114 00:40:45.695729 test VIDIOC_G/S_EDID: OK (Not Supported)
11115 00:40:45.720864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11116 00:40:45.721316
11117 00:40:45.721921 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11119 00:40:45.732347 Control ioctls:
11120 00:40:45.739533 <LAVA_SIGNAL_TESTSET STOP>
11121 00:40:45.740203 Received signal: <TESTSET> STOP
11122 00:40:45.740552 Closing test_set Input-ioctls
11123 00:40:45.748701 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11124 00:40:45.749482 Received signal: <TESTSET> START Control-ioctls
11125 00:40:45.749844 Starting test_set Control-ioctls
11126 00:40:45.751736 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11127 00:40:45.779153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11128 00:40:45.779586 test VIDIOC_QUERYCTRL: OK
11129 00:40:45.780165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11131 00:40:45.800188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11132 00:40:45.800862 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11134 00:40:45.802777 test VIDIOC_G/S_CTRL: OK
11135 00:40:45.823283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11136 00:40:45.823965 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11138 00:40:45.826363 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11139 00:40:45.847319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11140 00:40:45.847981 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11142 00:40:45.853701 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11143 00:40:45.860228 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11144 00:40:45.883433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11145 00:40:45.884108 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11147 00:40:45.887084 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11148 00:40:45.905069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11149 00:40:45.905940 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11151 00:40:45.908460 Standard Controls: 16 Private Controls: 0
11152 00:40:45.917542
11153 00:40:45.930662 Format ioctls:
11154 00:40:45.937916 <LAVA_SIGNAL_TESTSET STOP>
11155 00:40:45.938577 Received signal: <TESTSET> STOP
11156 00:40:45.938924 Closing test_set Control-ioctls
11157 00:40:45.948272 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11158 00:40:45.948936 Received signal: <TESTSET> START Format-ioctls
11159 00:40:45.949325 Starting test_set Format-ioctls
11160 00:40:45.951247 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11161 00:40:45.974422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11162 00:40:45.975102 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11164 00:40:45.977621 test VIDIOC_G/S_PARM: OK
11165 00:40:45.995474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11166 00:40:45.996139 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11168 00:40:45.998921 test VIDIOC_G_FBUF: OK (Not Supported)
11169 00:40:46.020984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11170 00:40:46.022073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11172 00:40:46.024556 test VIDIOC_G_FMT: OK
11173 00:40:46.045961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11174 00:40:46.046397 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11176 00:40:46.049124 test VIDIOC_TRY_FMT: OK
11177 00:40:46.070126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11178 00:40:46.070432 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11180 00:40:46.076745 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11181 00:40:46.080736 test VIDIOC_S_FMT: FAIL
11182 00:40:46.111962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11183 00:40:46.112282 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11185 00:40:46.115307 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11186 00:40:46.137310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11187 00:40:46.137620 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11189 00:40:46.140232 test Cropping: OK
11190 00:40:46.161296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11191 00:40:46.161607 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11193 00:40:46.164604 test Composing: OK (Not Supported)
11194 00:40:46.188474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11195 00:40:46.188799 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11197 00:40:46.191957 test Scaling: OK (Not Supported)
11198 00:40:46.212977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11199 00:40:46.213114
11200 00:40:46.213357 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11202 00:40:46.224150 Codec ioctls:
11203 00:40:46.231962 <LAVA_SIGNAL_TESTSET STOP>
11204 00:40:46.232242 Received signal: <TESTSET> STOP
11205 00:40:46.232312 Closing test_set Format-ioctls
11206 00:40:46.240716 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11207 00:40:46.240969 Received signal: <TESTSET> START Codec-ioctls
11208 00:40:46.241040 Starting test_set Codec-ioctls
11209 00:40:46.243852 test VIDIOC_(TRY_)ENCODER_CMD: OK
11210 00:40:46.266493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11211 00:40:46.266781 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11213 00:40:46.272819 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11214 00:40:46.290521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11215 00:40:46.290789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11217 00:40:46.296941 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11218 00:40:46.314216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11219 00:40:46.314338
11220 00:40:46.314598 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11222 00:40:46.324677 Buffer ioctls:
11223 00:40:46.333046 <LAVA_SIGNAL_TESTSET STOP>
11224 00:40:46.333362 Received signal: <TESTSET> STOP
11225 00:40:46.333474 Closing test_set Codec-ioctls
11226 00:40:46.344468 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11227 00:40:46.344869 Received signal: <TESTSET> START Buffer-ioctls
11228 00:40:46.345046 Starting test_set Buffer-ioctls
11229 00:40:46.347549 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11230 00:40:46.373054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11231 00:40:46.373835 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11233 00:40:46.375919 test CREATE_BUFS maximum buffers: OK
11234 00:40:46.392794 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11236 00:40:46.395680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11237 00:40:46.396094 test VIDIOC_EXPBUF: OK
11238 00:40:46.416536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11239 00:40:46.417201 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11241 00:40:46.420041 test Requests: OK (Not Supported)
11242 00:40:46.442725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11243 00:40:46.443171
11244 00:40:46.443749 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11246 00:40:46.453745 Test input 0:
11247 00:40:46.464101
11248 00:40:46.475441 Streaming ioctls:
11249 00:40:46.483693 <LAVA_SIGNAL_TESTSET STOP>
11250 00:40:46.484350 Received signal: <TESTSET> STOP
11251 00:40:46.484693 Closing test_set Buffer-ioctls
11252 00:40:46.493683 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11253 00:40:46.494338 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11254 00:40:46.494684 Starting test_set Streaming-ioctls_Test-input-0
11255 00:40:46.496523 test read/write: OK (Not Supported)
11256 00:40:46.519026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11257 00:40:46.519688 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11259 00:40:46.524853 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11260 00:40:46.531686 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11261 00:40:46.537737 test blocking wait: FAIL
11262 00:40:46.563279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11263 00:40:46.563946 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11265 00:40:46.569348 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11266 00:40:46.572808 test MMAP (select): FAIL
11267 00:40:46.603271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11268 00:40:46.604043 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11270 00:40:46.609490 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11271 00:40:46.613864 test MMAP (epoll): FAIL
11272 00:40:46.639603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11273 00:40:46.640285 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11275 00:40:46.645762 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11276 00:40:46.653236 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11277 00:40:46.660313 test USERPTR (select): FAIL
11278 00:40:46.685536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11279 00:40:46.686276 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11281 00:40:46.691687 test DMABUF: Cannot test, specify --expbuf-device
11282 00:40:46.696232
11283 00:40:46.713353 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11284 00:40:46.716204 <LAVA_TEST_RUNNER EXIT>
11285 00:40:46.716874 ok: lava_test_shell seems to have completed
11286 00:40:46.717246 Marking unfinished test run as failed
11288 00:40:46.722220 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11289 00:40:46.722864 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11290 00:40:46.723446 end: 3 lava-test-retry (duration 00:00:02) [common]
11291 00:40:46.724131 start: 4 finalize (timeout 00:07:42) [common]
11292 00:40:46.724801 start: 4.1 power-off (timeout 00:00:30) [common]
11293 00:40:46.726265 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11294 00:40:46.983412 >> Command sent successfully.
11295 00:40:46.993566 Returned 0 in 0 seconds
11296 00:40:47.094723 end: 4.1 power-off (duration 00:00:00) [common]
11298 00:40:47.096118 start: 4.2 read-feedback (timeout 00:07:42) [common]
11299 00:40:47.097366 Listened to connection for namespace 'common' for up to 1s
11300 00:40:48.097517 Finalising connection for namespace 'common'
11301 00:40:48.098142 Disconnecting from shell: Finalise
11302 00:40:48.098554 / #
11303 00:40:48.199454 end: 4.2 read-feedback (duration 00:00:01) [common]
11304 00:40:48.200108 end: 4 finalize (duration 00:00:01) [common]
11305 00:40:48.200706 Cleaning after the job
11306 00:40:48.201168 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/ramdisk
11307 00:40:48.220132 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/kernel
11308 00:40:48.240749 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/dtb
11309 00:40:48.241125 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173456/tftp-deploy-4vimbs3l/modules
11310 00:40:48.250210 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173456
11311 00:40:48.316138 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173456
11312 00:40:48.316303 Job finished correctly