[Enter `^Ec?' for help] [DL] 00000000 00000000 010701 F0: 102B 0000 F3: 1006 0033 [0200] F3: 4001 00E0 [0200] F3: 0000 0000 V0: 0000 0000 [0001] 00: 1027 0002 01: 0000 0000 BP: 0C00 0251 [0000] G0: 1182 0000 EC: 0004 0000 [0001] S7: 0000 0000 [0000] CC: 0000 0000 [0001] T0: 0000 00DB [000F] Jump to BL coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception WDT: Last reset was cold boot SPI0(PAD0) initialized at 992727 Hz FMAP: area RW_NVRAM found @ 554000 (8192 bytes) Manufacturer: ef SF: Detected W25Q64DW with sector size 0x1000, total 0x800000 Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 19 00 00 08 00 00 00 in-data: a2 e0 47 00 13 00 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 Phase 1 FMAP: area GBB found @ 3f5000 (12032 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 VB2:vb2_check_recovery() Recovery was requested manually VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0 Recovery requested (1009000e) tlcl_extend: response is 0 tlcl_extend: response is 0 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x9a6d, sec=0x2008 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a [RTC]rtc_get_frequency_meter,134: input=0xf, output=822 [RTC]rtc_get_frequency_meter,134: input=0x7, output=697 [RTC]rtc_get_frequency_meter,134: input=0xb, output=761 [RTC]rtc_get_frequency_meter,134: input=0xd, output=791 [RTC]rtc_get_frequency_meter,134: input=0xe, output=807 [RTC]rtc_get_frequency_meter,134: input=0xd, output=791 [RTC]rtc_get_frequency_meter,134: input=0xe, output=806 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x9a6d [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 19 00 00 08 00 00 00 in-data: a2 e0 47 00 13 00 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 Skip loading cached calibration data out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 ADC[3]: Raw value=214540 ID=1 Manufacturer: ef SF: Detected W25Q64DW with sector size 0x1000, total 0x800000 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB' CBFS: Found @ offset 3c700 size 44 DRAM-K: Full Calibration FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/dram' CBFS: Found @ offset 24b00 size 12268 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps ddr_geometry: 1, config: 0x0 header.status = 0x0 header.magic = 0x44524d4b (expected: 0x44524d4b) header.version = 0x5 (expected: 0x5) header.size = 0x8f0 (expected: 0x8f0) header.config = 0x0 header.flags = 0x0 header.checksum = 0x0 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5 Set DRAM voltage: vdram1 = 1125000, vddq = 600000 Get DRAM voltage to vdram1 = 1125000, vddq = 600000 ddr_geometry:1 [EMI] new MDL number = 1 dram_cbt_mode_extern: 0 dram_cbt_mode [RK0]: 0, [RK1]: 0 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154] [Bianco] ETT version 0.0.0.1 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6 vSetVcoreByFreq with vcore:762500, freq=1600 [DramcInit] AutoRefreshCKEOff AutoREF OFF DDRPhyPLLSetting-CKEOFF DDRPhyPLLSetting-CKEON Enable WDQS [ModeRegInit_LP4] CH0 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH0 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 match AC timing 3 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0 [MiockJmeterHQA] vSetVcoreByFreq with vcore:762500, freq=1600 MIOCK jitter meter ch=0 1T = (103-19) = 84 dly cells Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps vSetVcoreByFreq with vcore:725000, freq=1200 MIOCK jitter meter ch=0 1T = (97-19) = 78 dly cells Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps vSetVcoreByFreq with vcore:725000, freq=800 MIOCK jitter meter ch=0 1T = (97-19) = 78 dly cells Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps vSetVcoreByFreq with vcore:762500, freq=1600 vSetVcoreByFreq with vcore:762500, freq=1600 K DRVP 1. OCD DRVP=0 CALOUT=0 1. OCD DRVP=1 CALOUT=0 1. OCD DRVP=2 CALOUT=0 1. OCD DRVP=3 CALOUT=0 1. OCD DRVP=4 CALOUT=0 1. OCD DRVP=5 CALOUT=0 1. OCD DRVP=6 CALOUT=0 1. OCD DRVP=7 CALOUT=0 1. OCD DRVP=8 CALOUT=1 1. OCD DRVP calibration OK! DRVP=8 K ODTN 3. OCD ODTN=0 ,CALOUT=1 3. OCD ODTN=1 ,CALOUT=1 3. OCD ODTN=2 ,CALOUT=1 3. OCD ODTN=3 ,CALOUT=1 3. OCD ODTN=4 ,CALOUT=1 3. OCD ODTN=5 ,CALOUT=1 3. OCD ODTN=6 ,CALOUT=1 3. OCD ODTN=7 ,CALOUT=0 3. OCD ODTN calibration OK! ODTN=7 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust) K DRVP 1. OCD DRVP=0 CALOUT=0 1. OCD DRVP=1 CALOUT=0 1. OCD DRVP=2 CALOUT=0 1. OCD DRVP=3 CALOUT=0 1. OCD DRVP=4 CALOUT=0 1. OCD DRVP=5 CALOUT=0 1. OCD DRVP=6 CALOUT=0 1. OCD DRVP=7 CALOUT=0 1. OCD DRVP=8 CALOUT=0 1. OCD DRVP=9 CALOUT=1 1. OCD DRVP calibration OK! DRVP=9 K ODTN 3. OCD ODTN=0 ,CALOUT=1 3. OCD ODTN=1 ,CALOUT=1 3. OCD ODTN=2 ,CALOUT=1 3. OCD ODTN=3 ,CALOUT=1 3. OCD ODTN=4 ,CALOUT=1 3. OCD ODTN=5 ,CALOUT=1 3. OCD ODTN=6 ,CALOUT=1 3. OCD ODTN=7 ,CALOUT=1 3. OCD ODTN=8 ,CALOUT=1 3. OCD ODTN=9 ,CALOUT=1 3. OCD ODTN=10 ,CALOUT=1 3. OCD ODTN=11 ,CALOUT=1 3. OCD ODTN=12 ,CALOUT=1 3. OCD ODTN=13 ,CALOUT=1 3. OCD ODTN=14 ,CALOUT=0 3. OCD ODTN calibration OK! ODTN=14 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=14 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=14 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=14 (After Adjust) [DramcInit] AutoRefreshCKEOff AutoREF OFF DDRPhyPLLSetting-CKEOFF DDRPhyPLLSetting-CKEON Enable WDQS == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [Duty_Offset_Calibration] =========================== B0:2 B1:2 CA:1 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [Duty_Offset_Calibration] =========================== B0:0 B1:0 CA:-1 [ModeRegInit_LP4] CH0 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH0 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 match AC timing 3 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0 DramC Write-DBI off DramC Read-DBI off Write Rank0 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x2d === u2Vref_new: 0x58 --> 0x38 === u2Vref_new: 0x5a --> 0x39 === u2Vref_new: 0x5c --> 0x3c === u2Vref_new: 0x5e --> 0x3d === u2Vref_new: 0x60 --> 0xa0 [CA 0] Center 34 (6~63) winsize 58 [CA 1] Center 35 (8~63) winsize 56 [CA 2] Center 30 (1~59) winsize 59 [CA 3] Center 25 (-2~53) winsize 56 [CA 4] Center 26 (-2~54) winsize 57 [CA 5] Center 31 (2~60) winsize 59 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 744/100 ps CA0 delay=34 (6~63),Diff = 9 PI (11 cell) CA1 delay=35 (8~63),Diff = 10 PI (13 cell) CA2 delay=30 (1~59),Diff = 5 PI (6 cell) CA3 delay=25 (-2~53),Diff = 0 PI (0 cell) CA4 delay=26 (-2~54),Diff = 1 PI (1 cell) CA5 delay=31 (2~60),Diff = 6 PI (7 cell) CA PerBit enable=1, Macro0, CA PI delay=25 === u2Vref_new: 0x5e --> 0x3d Vref(ca) range 1: 30 CS Dly= 7 (38-0-32) Write Rank0 MR13 =0xd8 Write Rank0 MR13 =0xd8 Write Rank0 MR12 =0x5e Write Rank1 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x2d === u2Vref_new: 0x58 --> 0x38 === u2Vref_new: 0x5a --> 0x39 === u2Vref_new: 0x5c --> 0x3c === u2Vref_new: 0x5e --> 0x3d === u2Vref_new: 0x60 --> 0xa0 [CA 0] Center 35 (8~63) winsize 56 [CA 1] Center 35 (8~63) winsize 56 [CA 2] Center 31 (2~60) winsize 59 [CA 3] Center 25 (-2~53) winsize 56 [CA 4] Center 26 (-2~55) winsize 58 [CA 5] Center 32 (3~61) winsize 59 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 744/100 ps CA0 delay=35 (8~63),Diff = 10 PI (13 cell) CA1 delay=35 (8~63),Diff = 10 PI (13 cell) CA2 delay=30 (2~59),Diff = 5 PI (6 cell) CA3 delay=25 (-2~53),Diff = 0 PI (0 cell) CA4 delay=26 (-2~54),Diff = 1 PI (1 cell) CA5 delay=31 (3~60),Diff = 6 PI (7 cell) CA PerBit enable=1, Macro0, CA PI delay=25 === u2Vref_new: 0x60 --> 0xa0 Vref(ca) range 1: 32 CS Dly= 7 (38-0-32) Write Rank1 MR13 =0xd8 Write Rank1 MR13 =0xd8 Write Rank1 MR12 =0x60 [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 0 ff 25 0 ff 26 0 ff 27 0 ff 28 0 ff 29 0 ff 30 0 ff 31 0 ff 32 ff ff 33 ff ff 34 ff ff 35 ff ff 36 ff ff 37 ff ff 38 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 32 DQS1 dly: 24 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0 3 2 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0 3 2 16 |1a1a 2b2a |(11 11)(11 11) |(1 1)(0 0)| 0 3 2 20 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 16 |0 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (1) [Byte 1] Lead/lag falling Transition (3, 3, 20) 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 4 12 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 4 16 |707 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 20 |3d3d 100f |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 6, 4) 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 1] Lead/lag falling Transition (3, 6, 8) 3 6 12 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0 [Byte 0] Lead/lag Transition tap number (3) [Byte 1] Lead/lag Transition tap number (2) 3 6 16 |202 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0 3 6 20 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 6, 20) 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 1]First pass (3, 6, 24) 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10) best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12) Write Rank0 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 3) best RODT dly(2T, 0.5T) = (2, 3) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxoxxxx xxxxxxxx [MSB] -2, [0] xxxoxxxx oxxxxxxx [MSB] -1, [0] xxxoxxxx oxxoxxxx [MSB] 0, [0] xxxoxoxx ooxoxxxx [MSB] 1, [0] xxxoxoox ooxoooxx [MSB] 2, [0] xxxoxoox ooxoooxx [MSB] 3, [0] xxxoxooo ooxoooox [MSB] 4, [0] xoxoxooo ooxoooox [MSB] 5, [0] xoxooooo ooxooooo [MSB] 6, [0] xooooooo ooxooooo [MSB] 7, [0] oooooooo ooxooooo [MSB] 33, [0] oooxoooo oooooooo [MSB] 34, [0] oooxoxoo oooooooo [MSB] 35, [0] oooxoxoo xooxoooo [MSB] 36, [0] oooxoxoo xxoxoooo [MSB] 37, [0] oooxoxoo xxoxxxoo [MSB] 38, [0] oooxoxxx xxoxxxxo [MSB] 39, [0] xooxoxxx xxoxxxxo [MSB] 40, [0] xxoxoxxx xxoxxxxo [MSB] 41, [0] xxxxxxxx xxoxxxxx [MSB] 42, [0] xxxxxxxx xxoxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 22 (7 ~ 38) 32 iDelay=43, Bit 1, Center 21 (4 ~ 39) 36 iDelay=43, Bit 2, Center 23 (6 ~ 40) 35 iDelay=43, Bit 3, Center 14 (-3 ~ 32) 36 iDelay=43, Bit 4, Center 22 (5 ~ 40) 36 iDelay=43, Bit 5, Center 16 (0 ~ 33) 34 iDelay=43, Bit 6, Center 19 (1 ~ 37) 37 iDelay=43, Bit 7, Center 20 (3 ~ 37) 35 iDelay=43, Bit 8, Center 16 (-2 ~ 34) 37 iDelay=43, Bit 9, Center 17 (0 ~ 35) 36 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35 iDelay=43, Bit 11, Center 16 (-1 ~ 34) 36 iDelay=43, Bit 12, Center 18 (1 ~ 36) 36 iDelay=43, Bit 13, Center 18 (1 ~ 36) 36 iDelay=43, Bit 14, Center 20 (3 ~ 37) 35 iDelay=43, Bit 15, Center 22 (5 ~ 40) 36 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 19, DQM1 = 19 DQ Delay: DQ0 =22, DQ1 =21, DQ2 =23, DQ3 =14 DQ4 =22, DQ5 =16, DQ6 =19, DQ7 =20 DQ8 =16, DQ9 =17, DQ10 =25, DQ11 =16 DQ12 =18, DQ13 =18, DQ14 =20, DQ15 =22 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 920~1176 TX Vref Scan disable 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB] 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB] 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB] 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB] 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB] 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB] 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB] 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB] 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB] 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB] 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB] 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB] 968 |3 6 8|[0] xxxxxxxx oxxxxxxx [MSB] 969 |3 6 9|[0] xxxxxxxx oxxoxxxx [MSB] 970 |3 6 10|[0] xxxxxxxx ooxooxxx [MSB] 971 |3 6 11|[0] xxxxxxxx ooxoooxx [MSB] 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB] 973 |3 6 13|[0] xxxxxxxx ooxooooo [MSB] 974 |3 6 14|[0] xxxxxxxx ooxooooo [MSB] 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB] 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB] 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB] 978 |3 6 18|[0] xxxoxoox oooooooo [MSB] 979 |3 6 19|[0] xxxoooox oooooooo [MSB] 980 |3 6 20|[0] xoxooooo oooooooo [MSB] 981 |3 6 21|[0] xooooooo oooooooo [MSB] 989 |3 6 29|[0] oooooooo xooxoooo [MSB] 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB] 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB] 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB] 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB] 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB] 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB] 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB] 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB] 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB] 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=988, DQM PI dly= 988 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28) Byte1, DQ PI dly=980, DQM PI dly= 980 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 956~1020 Write Rank0 MR14 =0x0 CH=0, VrefRange= 0, VrefLevel = 0 TX Bit0 (984~997) 14 990, Bit8 (971~982) 12 976, TX Bit1 (983~995) 13 989, Bit9 (973~984) 12 978, TX Bit2 (983~996) 14 989, Bit10 (978~989) 12 983, TX Bit3 (977~990) 14 983, Bit11 (973~982) 10 977, TX Bit4 (983~992) 10 987, Bit12 (973~985) 13 979, TX Bit5 (981~991) 11 986, Bit13 (974~984) 11 979, TX Bit6 (982~993) 12 987, Bit14 (974~988) 15 981, TX Bit7 (983~993) 11 988, Bit15 (976~991) 16 983, Write Rank0 MR14 =0x2 CH=0, VrefRange= 0, VrefLevel = 2 TX Bit0 (984~998) 15 991, Bit8 (971~983) 13 977, TX Bit1 (982~996) 15 989, Bit9 (973~985) 13 979, TX Bit2 (983~997) 15 990, Bit10 (977~989) 13 983, TX Bit3 (977~991) 15 984, Bit11 (972~983) 12 977, TX Bit4 (983~993) 11 988, Bit12 (973~985) 13 979, TX Bit5 (979~991) 13 985, Bit13 (974~985) 12 979, TX Bit6 (981~993) 13 987, Bit14 (974~989) 16 981, TX Bit7 (983~993) 11 988, Bit15 (976~991) 16 983, Write Rank0 MR14 =0x4 CH=0, VrefRange= 0, VrefLevel = 4 TX Bit0 (983~998) 16 990, Bit8 (970~984) 15 977, TX Bit1 (982~996) 15 989, Bit9 (972~986) 15 979, TX Bit2 (983~998) 16 990, Bit10 (976~990) 15 983, TX Bit3 (976~991) 16 983, Bit11 (972~984) 13 978, TX Bit4 (982~994) 13 988, Bit12 (973~987) 15 980, TX Bit5 (979~992) 14 985, Bit13 (973~986) 14 979, TX Bit6 (980~994) 15 987, Bit14 (973~989) 17 981, TX Bit7 (982~994) 13 988, Bit15 (975~992) 18 983, Write Rank0 MR14 =0x6 CH=0, VrefRange= 0, VrefLevel = 6 TX Bit0 (983~999) 17 991, Bit8 (970~984) 15 977, TX Bit1 (982~998) 17 990, Bit9 (972~987) 16 979, TX Bit2 (983~999) 17 991, Bit10 (976~991) 16 983, TX Bit3 (976~992) 17 984, Bit11 (971~984) 14 977, TX Bit4 (982~995) 14 988, Bit12 (973~988) 16 980, TX Bit5 (979~992) 14 985, Bit13 (973~987) 15 980, TX Bit6 (980~995) 16 987, Bit14 (973~990) 18 981, TX Bit7 (982~995) 14 988, Bit15 (975~992) 18 983, Write Rank0 MR14 =0x8 CH=0, VrefRange= 0, VrefLevel = 8 TX Bit0 (983~999) 17 991, Bit8 (969~985) 17 977, TX Bit1 (981~998) 18 989, Bit9 (972~988) 17 980, TX Bit2 (982~999) 18 990, Bit10 (976~992) 17 984, TX Bit3 (976~992) 17 984, Bit11 (971~985) 15 978, TX Bit4 (982~996) 15 989, Bit12 (972~988) 17 980, TX Bit5 (978~993) 16 985, Bit13 (973~987) 15 980, TX Bit6 (979~996) 18 987, Bit14 (973~990) 18 981, TX Bit7 (982~996) 15 989, Bit15 (975~994) 20 984, Write Rank0 MR14 =0xa CH=0, VrefRange= 0, VrefLevel = 10 TX Bit0 (983~999) 17 991, Bit8 (969~986) 18 977, TX Bit1 (981~999) 19 990, Bit9 (971~988) 18 979, TX Bit2 (982~999) 18 990, Bit10 (975~993) 19 984, TX Bit3 (976~993) 18 984, Bit11 (970~986) 17 978, TX Bit4 (981~997) 17 989, Bit12 (972~988) 17 980, TX Bit5 (978~994) 17 986, Bit13 (972~988) 17 980, TX Bit6 (978~997) 20 987, Bit14 (972~991) 20 981, TX Bit7 (981~997) 17 989, Bit15 (974~994) 21 984, Write Rank0 MR14 =0xc CH=0, VrefRange= 0, VrefLevel = 12 TX Bit0 (983~1000) 18 991, Bit8 (968~987) 20 977, TX Bit1 (981~999) 19 990, Bit9 (971~989) 19 980, TX Bit2 (982~1000) 19 991, Bit10 (975~994) 20 984, TX Bit3 (976~993) 18 984, Bit11 (970~988) 19 979, TX Bit4 (980~998) 19 989, Bit12 (971~989) 19 980, TX Bit5 (978~995) 18 986, Bit13 (971~989) 19 980, TX Bit6 (978~997) 20 987, Bit14 (972~991) 20 981, TX Bit7 (980~998) 19 989, Bit15 (974~995) 22 984, Write Rank0 MR14 =0xe CH=0, VrefRange= 0, VrefLevel = 14 TX Bit0 (982~1000) 19 991, Bit8 (969~987) 19 978, TX Bit1 (980~999) 20 989, Bit9 (970~989) 20 979, TX Bit2 (981~1000) 20 990, Bit10 (975~995) 21 985, TX Bit3 (975~994) 20 984, Bit11 (969~988) 20 978, TX Bit4 (980~998) 19 989, Bit12 (971~989) 19 980, TX Bit5 (977~995) 19 986, Bit13 (971~989) 19 980, TX Bit6 (978~998) 21 988, Bit14 (972~992) 21 982, TX Bit7 (980~998) 19 989, Bit15 (974~996) 23 985, Write Rank0 MR14 =0x10 CH=0, VrefRange= 0, VrefLevel = 16 TX Bit0 (982~1001) 20 991, Bit8 (968~988) 21 978, TX Bit1 (979~1000) 22 989, Bit9 (969~989) 21 979, TX Bit2 (981~1001) 21 991, Bit10 (975~996) 22 985, TX Bit3 (975~994) 20 984, Bit11 (969~988) 20 978, TX Bit4 (980~999) 20 989, Bit12 (970~990) 21 980, TX Bit5 (977~996) 20 986, Bit13 (970~990) 21 980, TX Bit6 (977~998) 22 987, Bit14 (971~992) 22 981, TX Bit7 (980~999) 20 989, Bit15 (974~996) 23 985, Write Rank0 MR14 =0x12 CH=0, VrefRange= 0, VrefLevel = 18 TX Bit0 (982~1002) 21 992, Bit8 (968~988) 21 978, TX Bit1 (979~1000) 22 989, Bit9 (969~990) 22 979, TX Bit2 (980~1001) 22 990, Bit10 (975~996) 22 985, TX Bit3 (975~995) 21 985, Bit11 (969~989) 21 979, TX Bit4 (979~999) 21 989, Bit12 (970~990) 21 980, TX Bit5 (977~997) 21 987, Bit13 (970~990) 21 980, TX Bit6 (977~998) 22 987, Bit14 (971~992) 22 981, TX Bit7 (979~999) 21 989, Bit15 (974~996) 23 985, Write Rank0 MR14 =0x14 CH=0, VrefRange= 0, VrefLevel = 20 TX Bit0 (982~1002) 21 992, Bit8 (968~988) 21 978, TX Bit1 (979~1000) 22 989, Bit9 (969~990) 22 979, TX Bit2 (980~1001) 22 990, Bit10 (975~996) 22 985, TX Bit3 (975~995) 21 985, Bit11 (969~989) 21 979, TX Bit4 (979~999) 21 989, Bit12 (970~990) 21 980, TX Bit5 (977~997) 21 987, Bit13 (970~990) 21 980, TX Bit6 (977~998) 22 987, Bit14 (971~992) 22 981, TX Bit7 (979~999) 21 989, Bit15 (974~996) 23 985, Write Rank0 MR14 =0x16 CH=0, VrefRange= 0, VrefLevel = 22 TX Bit0 (980~1003) 24 991, Bit8 (968~989) 22 978, TX Bit1 (979~1001) 23 990, Bit9 (969~991) 23 980, TX Bit2 (980~1002) 23 991, Bit10 (974~996) 23 985, TX Bit3 (975~996) 22 985, Bit11 (968~990) 23 979, TX Bit4 (978~1000) 23 989, Bit12 (969~992) 24 980, TX Bit5 (977~998) 22 987, Bit13 (969~991) 23 980, TX Bit6 (977~999) 23 988, Bit14 (970~994) 25 982, TX Bit7 (978~1000) 23 989, Bit15 (973~997) 25 985, Write Rank0 MR14 =0x18 CH=0, VrefRange= 0, VrefLevel = 24 TX Bit0 (980~1003) 24 991, Bit8 (967~990) 24 978, TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979, TX Bit2 (979~1003) 25 991, Bit10 (974~997) 24 985, TX Bit3 (974~997) 24 985, Bit11 (968~990) 23 979, TX Bit4 (978~1000) 23 989, Bit12 (969~992) 24 980, TX Bit5 (976~998) 23 987, Bit13 (969~991) 23 980, TX Bit6 (977~999) 23 988, Bit14 (970~995) 26 982, TX Bit7 (978~1000) 23 989, Bit15 (972~997) 26 984, Write Rank0 MR14 =0x1a CH=0, VrefRange= 0, VrefLevel = 26 TX Bit0 (980~1003) 24 991, Bit8 (967~990) 24 978, TX Bit1 (978~1002) 25 990, Bit9 (969~992) 24 980, TX Bit2 (979~1003) 25 991, Bit10 (974~997) 24 985, TX Bit3 (974~998) 25 986, Bit11 (968~991) 24 979, TX Bit4 (977~1000) 24 988, Bit12 (968~993) 26 980, TX Bit5 (976~999) 24 987, Bit13 (969~992) 24 980, TX Bit6 (976~999) 24 987, Bit14 (969~995) 27 982, TX Bit7 (978~1001) 24 989, Bit15 (972~997) 26 984, Write Rank0 MR14 =0x1c CH=0, VrefRange= 0, VrefLevel = 28 TX Bit0 (979~1004) 26 991, Bit8 (967~990) 24 978, TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979, TX Bit2 (979~1004) 26 991, Bit10 (974~998) 25 986, TX Bit3 (974~998) 25 986, Bit11 (968~991) 24 979, TX Bit4 (977~1001) 25 989, Bit12 (968~993) 26 980, TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981, TX Bit6 (976~1000) 25 988, Bit14 (969~996) 28 982, TX Bit7 (977~1001) 25 989, Bit15 (971~997) 27 984, Write Rank0 MR14 =0x1e CH=0, VrefRange= 0, VrefLevel = 30 TX Bit0 (979~1004) 26 991, Bit8 (967~990) 24 978, TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979, TX Bit2 (979~1004) 26 991, Bit10 (974~998) 25 986, TX Bit3 (974~998) 25 986, Bit11 (968~991) 24 979, TX Bit4 (977~1001) 25 989, Bit12 (968~993) 26 980, TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981, TX Bit6 (976~1000) 25 988, Bit14 (969~996) 28 982, TX Bit7 (977~1001) 25 989, Bit15 (971~997) 27 984, Write Rank0 MR14 =0x20 CH=0, VrefRange= 0, VrefLevel = 32 TX Bit0 (979~1004) 26 991, Bit8 (967~990) 24 978, TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979, TX Bit2 (979~1004) 26 991, Bit10 (974~998) 25 986, TX Bit3 (974~998) 25 986, Bit11 (968~991) 24 979, TX Bit4 (977~1001) 25 989, Bit12 (968~993) 26 980, TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981, TX Bit6 (976~1000) 25 988, Bit14 (969~996) 28 982, TX Bit7 (977~1001) 25 989, Bit15 (971~997) 27 984, Write Rank0 MR14 =0x22 CH=0, VrefRange= 0, VrefLevel = 34 TX Bit0 (979~1004) 26 991, Bit8 (967~990) 24 978, TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979, TX Bit2 (979~1004) 26 991, Bit10 (974~998) 25 986, TX Bit3 (974~998) 25 986, Bit11 (968~991) 24 979, TX Bit4 (977~1001) 25 989, Bit12 (968~993) 26 980, TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981, TX Bit6 (976~1000) 25 988, Bit14 (969~996) 28 982, TX Bit7 (977~1001) 25 989, Bit15 (971~997) 27 984, Write Rank0 MR14 =0x24 CH=0, VrefRange= 0, VrefLevel = 36 TX Bit0 (979~1004) 26 991, Bit8 (967~990) 24 978, TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979, TX Bit2 (979~1004) 26 991, Bit10 (974~998) 25 986, TX Bit3 (974~998) 25 986, Bit11 (968~991) 24 979, TX Bit4 (977~1001) 25 989, Bit12 (968~993) 26 980, TX Bit5 (976~999) 24 987, Bit13 (969~993) 25 981, TX Bit6 (976~1000) 25 988, Bit14 (969~996) 28 982, TX Bit7 (977~1001) 25 989, Bit15 (971~997) 27 984, TX Vref found, early break! 373< 383 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps u1DelayCellOfst[0]=6 cells (5 PI) u1DelayCellOfst[1]=5 cells (4 PI) u1DelayCellOfst[2]=6 cells (5 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=3 cells (3 PI) u1DelayCellOfst[5]=1 cells (1 PI) u1DelayCellOfst[6]=2 cells (2 PI) u1DelayCellOfst[7]=3 cells (3 PI) Byte0, DQ PI dly=986, DQM PI dly= 988 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26) u1DelayCellOfst[8]=0 cells (0 PI) u1DelayCellOfst[9]=1 cells (1 PI) u1DelayCellOfst[10]=10 cells (8 PI) u1DelayCellOfst[11]=1 cells (1 PI) u1DelayCellOfst[12]=2 cells (2 PI) u1DelayCellOfst[13]=3 cells (3 PI) u1DelayCellOfst[14]=5 cells (4 PI) u1DelayCellOfst[15]=7 cells (6 PI) Byte1, DQ PI dly=978, DQM PI dly= 982 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18) Write Rank0 MR14 =0x1c Final TX Range 0 Vref 28 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 702~766 TX Vref Scan disable 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB] 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB] 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB] 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB] 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB] 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB] 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB] 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB] 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB] 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB] 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB] 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB] 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB] 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB] 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB] 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB] 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB] 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB] 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB] 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB] 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB] 747 |2 6 43|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=733, DQM PI dly= 733 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 29) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 29) Byte1, DQ PI dly=724, DQM PI dly= 724 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank0 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK0, use_rxtx_scan=0 DATLAT Default: 0xf 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 1 RX Vref found, early break! Final RX Vref 11, apply to both rank0 and 1 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 19, DQM1 = 18 DQ Delay: DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =15 DQ4 =21, DQ5 =16, DQ6 =19, DQ7 =21 DQ8 =15, DQ9 =16, DQ10 =24, DQ11 =16 DQ12 =18, DQ13 =18, DQ14 =20, DQ15 =22 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFF, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps CH0_RK0: MR19=0x202, MR18=0xAEAE, DQSOSC=459, MR23=63, INC=11, DEC=17 Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps CH0 RK0: MR19=202, MR18=ADAD [RankSwap] Rank num 2, (Multi 1), Rank 1 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 ff 23 0 ff 24 0 ff 25 0 ff 26 0 ff 27 0 ff 28 0 ff 29 0 ff 30 0 ff 31 ff ff 32 ff ff 33 ff ff 34 ff ff 35 ff ff 36 ff ff 37 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 31 DQS1 dly: 22 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank1 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0 3 2 16 |504 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0 3 2 20 |3d3d 404 |(11 11)(11 11) |(1 1)(0 0)| 0 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 20 |707 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 [Byte 0] Lead/lag Transition tap number (1) 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 4 16 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 4 20 |3d3d 807 |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 6, 4) 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (2) [Byte 1] Lead/lag falling Transition (3, 6, 8) 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0 [Byte 1] Lead/lag Transition tap number (2) 3 6 16 |605 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0 3 6 20 |404 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 6, 24) [Byte 1]First pass (3, 6, 24) 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 6, 8) best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 8) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12) Write Rank1 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 3) best RODT dly(2T, 0.5T) = (2, 3) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxoxxxx xxxxxxxx [MSB] -1, [0] xxxoxxxx xxxxxxxx [MSB] 0, [0] xxxoxoxx xxxoxxxx [MSB] 1, [0] xxxoxoox oxxoxxxx [MSB] 2, [0] xxxoxooo oxxoxxxx [MSB] 3, [0] xoxooooo ooxooxxx [MSB] 4, [0] xoxooooo ooxoooxx [MSB] 5, [0] ooxooooo ooxoooox [MSB] 6, [0] oooooooo ooxooooo [MSB] 7, [0] oooooooo ooxooooo [MSB] 8, [0] oooooooo ooxooooo [MSB] 9, [0] oooooooo ooxooooo [MSB] 33, [0] oooxoxoo oooooooo [MSB] 34, [0] oooxoxoo xooooooo [MSB] 35, [0] oooxoxoo xooxoooo [MSB] 36, [0] oooxoxoo xxoxxooo [MSB] 37, [0] oooxoxxo xxoxxxxo [MSB] 38, [0] xooxoxxx xxoxxxxo [MSB] 39, [0] xxoxoxxx xxoxxxxo [MSB] 40, [0] xxxxoxxx xxoxxxxo [MSB] 41, [0] xxxxxxxx xxoxxxxx [MSB] 42, [0] xxxxxxxx xxoxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 21 (5 ~ 37) 33 iDelay=43, Bit 1, Center 20 (3 ~ 38) 36 iDelay=43, Bit 2, Center 22 (6 ~ 39) 34 iDelay=43, Bit 3, Center 15 (-2 ~ 32) 35 iDelay=43, Bit 4, Center 21 (3 ~ 40) 38 iDelay=43, Bit 5, Center 16 (0 ~ 32) 33 iDelay=43, Bit 6, Center 18 (1 ~ 36) 36 iDelay=43, Bit 7, Center 19 (2 ~ 37) 36 iDelay=43, Bit 8, Center 17 (1 ~ 33) 33 iDelay=43, Bit 9, Center 19 (3 ~ 35) 33 iDelay=43, Bit 10, Center 26 (10 ~ 42) 33 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35 iDelay=43, Bit 12, Center 19 (3 ~ 35) 33 iDelay=43, Bit 13, Center 20 (4 ~ 36) 33 iDelay=43, Bit 14, Center 20 (5 ~ 36) 32 iDelay=43, Bit 15, Center 23 (6 ~ 40) 35 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 19, DQM1 = 20 DQ Delay: DQ0 =21, DQ1 =20, DQ2 =22, DQ3 =15 DQ4 =21, DQ5 =16, DQ6 =18, DQ7 =19 DQ8 =17, DQ9 =19, DQ10 =26, DQ11 =17 DQ12 =19, DQ13 =20, DQ14 =20, DQ15 =23 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 918~1174 TX Vref Scan disable 918 |3 4 22|[0] xxxxxxxx xxxxxxxx [MSB] 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB] 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB] 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB] 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB] 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB] 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB] 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB] 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB] 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB] 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB] 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB] 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB] 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB] 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB] 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB] 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB] 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB] 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB] 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB] 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB] 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB] 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB] 977 |3 6 17|[0] xxxoxooo oooooooo [MSB] 978 |3 6 18|[0] xoxooooo oooooooo [MSB] 979 |3 6 19|[0] xoxooooo oooooooo [MSB] 980 |3 6 20|[0] xooooooo oooooooo [MSB] 986 |3 6 26|[0] oooooooo oooxoooo [MSB] 987 |3 6 27|[0] oooooooo xooxoooo [MSB] 988 |3 6 28|[0] oooooooo xxoxoooo [MSB] 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB] 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB] 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB] 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB] 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB] 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB] 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB] 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB] 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB] 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB] 999 |3 6 39|[0] xxoxxxxx xxxxxxxx [MSB] 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=987, DQM PI dly= 987 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27) Byte1, DQ PI dly=978, DQM PI dly= 978 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 954~1018 Write Rank1 MR14 =0x0 CH=0, VrefRange= 0, VrefLevel = 0 TX Bit0 (983~995) 13 989, Bit8 (968~981) 14 974, TX Bit1 (982~993) 12 987, Bit9 (971~982) 12 976, TX Bit2 (983~994) 12 988, Bit10 (975~989) 15 982, TX Bit3 (977~990) 14 983, Bit11 (969~981) 13 975, TX Bit4 (981~993) 13 987, Bit12 (971~983) 13 977, TX Bit5 (978~991) 14 984, Bit13 (971~984) 14 977, TX Bit6 (978~992) 15 985, Bit14 (972~985) 14 978, TX Bit7 (980~994) 15 987, Bit15 (975~986) 12 980, Write Rank1 MR14 =0x2 CH=0, VrefRange= 0, VrefLevel = 2 TX Bit0 (983~996) 14 989, Bit8 (968~982) 15 975, TX Bit1 (981~994) 14 987, Bit9 (971~983) 13 977, TX Bit2 (983~995) 13 989, Bit10 (975~989) 15 982, TX Bit3 (976~990) 15 983, Bit11 (969~981) 13 975, TX Bit4 (981~994) 14 987, Bit12 (970~983) 14 976, TX Bit5 (979~992) 14 985, Bit13 (970~984) 15 977, TX Bit6 (978~992) 15 985, Bit14 (972~986) 15 979, TX Bit7 (980~995) 16 987, Bit15 (974~987) 14 980, Write Rank1 MR14 =0x4 CH=0, VrefRange= 0, VrefLevel = 4 TX Bit0 (983~997) 15 990, Bit8 (968~982) 15 975, TX Bit1 (981~995) 15 988, Bit9 (970~983) 14 976, TX Bit2 (983~997) 15 990, Bit10 (975~990) 16 982, TX Bit3 (976~991) 16 983, Bit11 (969~982) 14 975, TX Bit4 (980~995) 16 987, Bit12 (969~984) 16 976, TX Bit5 (978~992) 15 985, Bit13 (970~985) 16 977, TX Bit6 (978~993) 16 985, Bit14 (971~987) 17 979, TX Bit7 (979~995) 17 987, Bit15 (975~988) 14 981, Write Rank1 MR14 =0x6 CH=0, VrefRange= 0, VrefLevel = 6 TX Bit0 (983~997) 15 990, Bit8 (967~983) 17 975, TX Bit1 (980~996) 17 988, Bit9 (970~984) 15 977, TX Bit2 (982~998) 17 990, Bit10 (974~990) 17 982, TX Bit3 (976~991) 16 983, Bit11 (968~983) 16 975, TX Bit4 (980~996) 17 988, Bit12 (970~984) 15 977, TX Bit5 (977~993) 17 985, Bit13 (970~985) 16 977, TX Bit6 (977~993) 17 985, Bit14 (970~988) 19 979, TX Bit7 (979~996) 18 987, Bit15 (974~989) 16 981, Write Rank1 MR14 =0x8 CH=0, VrefRange= 0, VrefLevel = 8 TX Bit0 (982~998) 17 990, Bit8 (967~983) 17 975, TX Bit1 (980~997) 18 988, Bit9 (969~984) 16 976, TX Bit2 (982~998) 17 990, Bit10 (974~990) 17 982, TX Bit3 (975~991) 17 983, Bit11 (968~983) 16 975, TX Bit4 (981~997) 17 989, Bit12 (969~985) 17 977, TX Bit5 (977~993) 17 985, Bit13 (969~986) 18 977, TX Bit6 (977~995) 19 986, Bit14 (971~989) 19 980, TX Bit7 (978~998) 21 988, Bit15 (974~989) 16 981, Write Rank1 MR14 =0xa CH=0, VrefRange= 0, VrefLevel = 10 TX Bit0 (982~998) 17 990, Bit8 (967~984) 18 975, TX Bit1 (980~998) 19 989, Bit9 (969~985) 17 977, TX Bit2 (982~999) 18 990, Bit10 (974~991) 18 982, TX Bit3 (975~992) 18 983, Bit11 (967~983) 17 975, TX Bit4 (979~997) 19 988, Bit12 (968~986) 19 977, TX Bit5 (977~994) 18 985, Bit13 (968~987) 20 977, TX Bit6 (977~995) 19 986, Bit14 (969~989) 21 979, TX Bit7 (978~998) 21 988, Bit15 (973~990) 18 981, Write Rank1 MR14 =0xc CH=0, VrefRange= 0, VrefLevel = 12 TX Bit0 (982~999) 18 990, Bit8 (967~985) 19 976, TX Bit1 (978~998) 21 988, Bit9 (968~986) 19 977, TX Bit2 (981~999) 19 990, Bit10 (973~992) 20 982, TX Bit3 (975~992) 18 983, Bit11 (967~984) 18 975, TX Bit4 (979~998) 20 988, Bit12 (968~986) 19 977, TX Bit5 (977~995) 19 986, Bit13 (968~988) 21 978, TX Bit6 (977~997) 21 987, Bit14 (969~990) 22 979, TX Bit7 (978~999) 22 988, Bit15 (973~990) 18 981, Write Rank1 MR14 =0xe CH=0, VrefRange= 0, VrefLevel = 14 TX Bit0 (981~999) 19 990, Bit8 (967~985) 19 976, TX Bit1 (978~999) 22 988, Bit9 (968~987) 20 977, TX Bit2 (981~999) 19 990, Bit10 (973~992) 20 982, TX Bit3 (975~992) 18 983, Bit11 (967~984) 18 975, TX Bit4 (978~998) 21 988, Bit12 (968~988) 21 978, TX Bit5 (976~996) 21 986, Bit13 (968~988) 21 978, TX Bit6 (977~997) 21 987, Bit14 (968~990) 23 979, TX Bit7 (978~999) 22 988, Bit15 (973~990) 18 981, Write Rank1 MR14 =0x10 CH=0, VrefRange= 0, VrefLevel = 16 TX Bit0 (980~999) 20 989, Bit8 (966~985) 20 975, TX Bit1 (978~999) 22 988, Bit9 (968~987) 20 977, TX Bit2 (981~1000) 20 990, Bit10 (973~992) 20 982, TX Bit3 (974~993) 20 983, Bit11 (967~985) 19 976, TX Bit4 (978~999) 22 988, Bit12 (968~989) 22 978, TX Bit5 (976~997) 22 986, Bit13 (968~989) 22 978, TX Bit6 (976~998) 23 987, Bit14 (968~990) 23 979, TX Bit7 (977~1000) 24 988, Bit15 (973~991) 19 982, Write Rank1 MR14 =0x12 CH=0, VrefRange= 0, VrefLevel = 18 TX Bit0 (981~1000) 20 990, Bit8 (966~986) 21 976, TX Bit1 (978~1000) 23 989, Bit9 (968~988) 21 978, TX Bit2 (980~1000) 21 990, Bit10 (973~993) 21 983, TX Bit3 (974~993) 20 983, Bit11 (967~985) 19 976, TX Bit4 (978~999) 22 988, Bit12 (968~989) 22 978, TX Bit5 (976~997) 22 986, Bit13 (968~989) 22 978, TX Bit6 (976~998) 23 987, Bit14 (968~990) 23 979, TX Bit7 (977~1000) 24 988, Bit15 (973~992) 20 982, Write Rank1 MR14 =0x14 CH=0, VrefRange= 0, VrefLevel = 20 TX Bit0 (980~1000) 21 990, Bit8 (966~988) 23 977, TX Bit1 (978~1000) 23 989, Bit9 (967~989) 23 978, TX Bit2 (979~1001) 23 990, Bit10 (972~994) 23 983, TX Bit3 (974~994) 21 984, Bit11 (966~987) 22 976, TX Bit4 (977~999) 23 988, Bit12 (968~989) 22 978, TX Bit5 (976~997) 22 986, Bit13 (968~990) 23 979, TX Bit6 (976~999) 24 987, Bit14 (968~991) 24 979, TX Bit7 (977~1000) 24 988, Bit15 (972~993) 22 982, Write Rank1 MR14 =0x16 CH=0, VrefRange= 0, VrefLevel = 22 TX Bit0 (979~1001) 23 990, Bit8 (965~988) 24 976, TX Bit1 (977~1000) 24 988, Bit9 (967~989) 23 978, TX Bit2 (979~1001) 23 990, Bit10 (972~995) 24 983, TX Bit3 (973~995) 23 984, Bit11 (966~988) 23 977, TX Bit4 (977~1000) 24 988, Bit12 (967~990) 24 978, TX Bit5 (976~998) 23 987, Bit13 (967~990) 24 978, TX Bit6 (976~999) 24 987, Bit14 (968~991) 24 979, TX Bit7 (977~1001) 25 989, Bit15 (972~993) 22 982, Write Rank1 MR14 =0x18 CH=0, VrefRange= 0, VrefLevel = 24 TX Bit0 (979~1002) 24 990, Bit8 (965~988) 24 976, TX Bit1 (977~1000) 24 988, Bit9 (967~989) 23 978, TX Bit2 (979~1001) 23 990, Bit10 (971~996) 26 983, TX Bit3 (973~995) 23 984, Bit11 (966~989) 24 977, TX Bit4 (977~1000) 24 988, Bit12 (967~990) 24 978, TX Bit5 (976~998) 23 987, Bit13 (967~989) 23 978, TX Bit6 (976~999) 24 987, Bit14 (967~991) 25 979, TX Bit7 (977~1001) 25 989, Bit15 (971~993) 23 982, Write Rank1 MR14 =0x1a CH=0, VrefRange= 0, VrefLevel = 26 TX Bit0 (978~1002) 25 990, Bit8 (965~988) 24 976, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (978~1002) 25 990, Bit10 (971~996) 26 983, TX Bit3 (973~996) 24 984, Bit11 (966~989) 24 977, TX Bit4 (977~1001) 25 989, Bit12 (967~990) 24 978, TX Bit5 (975~998) 24 986, Bit13 (967~989) 23 978, TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979, TX Bit7 (976~1001) 26 988, Bit15 (970~993) 24 981, Write Rank1 MR14 =0x1c CH=0, VrefRange= 0, VrefLevel = 28 TX Bit0 (978~1002) 25 990, Bit8 (965~988) 24 976, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (978~1002) 25 990, Bit10 (971~996) 26 983, TX Bit3 (973~996) 24 984, Bit11 (966~989) 24 977, TX Bit4 (977~1001) 25 989, Bit12 (967~990) 24 978, TX Bit5 (975~998) 24 986, Bit13 (967~989) 23 978, TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979, TX Bit7 (976~1001) 26 988, Bit15 (970~993) 24 981, Write Rank1 MR14 =0x1e CH=0, VrefRange= 0, VrefLevel = 30 TX Bit0 (978~1002) 25 990, Bit8 (965~988) 24 976, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (978~1002) 25 990, Bit10 (971~996) 26 983, TX Bit3 (973~996) 24 984, Bit11 (966~989) 24 977, TX Bit4 (977~1001) 25 989, Bit12 (967~990) 24 978, TX Bit5 (975~998) 24 986, Bit13 (967~989) 23 978, TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979, TX Bit7 (976~1001) 26 988, Bit15 (970~993) 24 981, Write Rank1 MR14 =0x20 CH=0, VrefRange= 0, VrefLevel = 32 TX Bit0 (978~1002) 25 990, Bit8 (965~988) 24 976, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (978~1002) 25 990, Bit10 (971~996) 26 983, TX Bit3 (973~996) 24 984, Bit11 (966~989) 24 977, TX Bit4 (977~1001) 25 989, Bit12 (967~990) 24 978, TX Bit5 (975~998) 24 986, Bit13 (967~989) 23 978, TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979, TX Bit7 (976~1001) 26 988, Bit15 (970~993) 24 981, Write Rank1 MR14 =0x22 CH=0, VrefRange= 0, VrefLevel = 34 TX Bit0 (978~1002) 25 990, Bit8 (965~988) 24 976, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (978~1002) 25 990, Bit10 (971~996) 26 983, TX Bit3 (973~996) 24 984, Bit11 (966~989) 24 977, TX Bit4 (977~1001) 25 989, Bit12 (967~990) 24 978, TX Bit5 (975~998) 24 986, Bit13 (967~989) 23 978, TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979, TX Bit7 (976~1001) 26 988, Bit15 (970~993) 24 981, TX Vref found, early break! 365< 372 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps u1DelayCellOfst[0]=7 cells (6 PI) u1DelayCellOfst[1]=6 cells (5 PI) u1DelayCellOfst[2]=7 cells (6 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=6 cells (5 PI) u1DelayCellOfst[5]=2 cells (2 PI) u1DelayCellOfst[6]=3 cells (3 PI) u1DelayCellOfst[7]=5 cells (4 PI) Byte0, DQ PI dly=984, DQM PI dly= 987 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24) u1DelayCellOfst[8]=0 cells (0 PI) u1DelayCellOfst[9]=2 cells (2 PI) u1DelayCellOfst[10]=9 cells (7 PI) u1DelayCellOfst[11]=1 cells (1 PI) u1DelayCellOfst[12]=2 cells (2 PI) u1DelayCellOfst[13]=2 cells (2 PI) u1DelayCellOfst[14]=3 cells (3 PI) u1DelayCellOfst[15]=6 cells (5 PI) Byte1, DQ PI dly=976, DQM PI dly= 979 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16) Write Rank1 MR14 =0x1a Final TX Range 0 Vref 26 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 699~763 TX Vref Scan disable 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB] 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB] 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB] 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB] 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB] 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB] 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB] 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB] 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB] 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB] 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB] 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB] 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB] 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB] 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB] 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB] 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB] 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB] 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB] 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB] 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB] 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB] 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB] 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=733, DQM PI dly= 733 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 29) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 29) Byte1, DQ PI dly=722, DQM PI dly= 722 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank1 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK1, use_rxtx_scan=0 DATLAT Default: 0x10 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxoxxxx xxxxxxxx [MSB] -2, [0] xxxoxxxx xxxxxxxx [MSB] -1, [0] xxxoxxxx xxxxxxxx [MSB] 0, [0] xxxoxoxx oxxoxxxx [MSB] 1, [0] xxxoxoox oxxoxxxx [MSB] 2, [0] xxxoxoox ooxoxxxx [MSB] 3, [0] xoxoxoox ooxoooxx [MSB] 4, [0] ooxoxooo ooxoooxx [MSB] 5, [0] oooooooo ooxoooox [MSB] 6, [0] oooooooo ooxooooo [MSB] 7, [0] oooooooo ooxooooo [MSB] 8, [0] oooooooo ooxooooo [MSB] 32, [0] oooxoooo oooooooo [MSB] 33, [0] oooxoxoo oooooooo [MSB] 34, [0] oooxoxoo xooxoooo [MSB] 35, [0] oooxoxoo xooxoooo [MSB] 36, [0] oooxoxxo xxoxoooo [MSB] 37, [0] oooxoxxo xxoxxxoo [MSB] 38, [0] oooxoxxx xxoxxxxo [MSB] 39, [0] xooxxxxx xxoxxxxo [MSB] 40, [0] xxoxxxxx xxoxxxxo [MSB] 41, [0] xxxxxxxx xxoxxxxx [MSB] 42, [0] xxxxxxxx xxoxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 21 (4 ~ 38) 35 iDelay=43, Bit 1, Center 21 (3 ~ 39) 37 iDelay=43, Bit 2, Center 22 (5 ~ 40) 36 iDelay=43, Bit 3, Center 14 (-3 ~ 31) 35 iDelay=43, Bit 4, Center 21 (5 ~ 38) 34 iDelay=43, Bit 5, Center 16 (0 ~ 32) 33 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35 iDelay=43, Bit 7, Center 20 (4 ~ 37) 34 iDelay=43, Bit 8, Center 16 (0 ~ 33) 34 iDelay=43, Bit 9, Center 18 (2 ~ 35) 34 iDelay=43, Bit 10, Center 25 (9 ~ 42) 34 iDelay=43, Bit 11, Center 16 (0 ~ 33) 34 iDelay=43, Bit 12, Center 19 (3 ~ 36) 34 iDelay=43, Bit 13, Center 19 (3 ~ 36) 34 iDelay=43, Bit 14, Center 21 (5 ~ 37) 33 iDelay=43, Bit 15, Center 23 (6 ~ 40) 35 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 19, DQM1 = 19 DQ Delay: DQ0 =21, DQ1 =21, DQ2 =22, DQ3 =14 DQ4 =21, DQ5 =16, DQ6 =18, DQ7 =20 DQ8 =16, DQ9 =18, DQ10 =25, DQ11 =16 DQ12 =19, DQ13 =19, DQ14 =21, DQ15 =23 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFF, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0xb4b4, (MSB)MR19= 0x202, tDQSOscB0 = 455 ps tDQSOscB1 = 455 ps CH0_RK1: MR19=0x202, MR18=0xB4B4, DQSOSC=455, MR23=63, INC=11, DEC=17 Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0xb1b1, (MSB)MR19= 0x202, tDQSOscB0 = 457 ps tDQSOscB1 = 457 ps CH0 RK1: MR19=202, MR18=B1B1 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 Rank: 0 best DQS0 dly(2T, 0.5T) = (2, 6) best DQS1 dly(2T, 0.5T) = (2, 6) best DQS0 P1 dly(2T, 0.5T) = (3, 2) best DQS1 P1 dly(2T, 0.5T) = (3, 2) Rank: 1 best DQS0 dly(2T, 0.5T) = (2, 6) best DQS1 dly(2T, 0.5T) = (2, 6) best DQS0 P1 dly(2T, 0.5T) = (3, 2) best DQS1 P1 dly(2T, 0.5T) = (3, 2) TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16 Write Rank0 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x3a === u2Vref_new: 0x58 --> 0x58 === u2Vref_new: 0x5a --> 0x5a === u2Vref_new: 0x5c --> 0x78 === u2Vref_new: 0x5e --> 0x7a === u2Vref_new: 0x60 --> 0x90 [CA 0] Center 37 (12~63) winsize 52 [CA 1] Center 37 (11~63) winsize 53 [CA 2] Center 35 (7~63) winsize 57 [CA 3] Center 35 (8~63) winsize 56 [CA 4] Center 34 (5~63) winsize 59 [CA 5] Center 28 (-1~57) winsize 59 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 744/100 ps CA0 delay=37 (12~63),Diff = 9 PI (11 cell) CA1 delay=37 (11~63),Diff = 9 PI (11 cell) CA2 delay=35 (7~63),Diff = 7 PI (9 cell) CA3 delay=35 (8~63),Diff = 7 PI (9 cell) CA4 delay=34 (5~63),Diff = 6 PI (7 cell) CA5 delay=28 (-1~57),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=28 === u2Vref_new: 0x5c --> 0x78 Vref(ca) range 1: 28 CS Dly= 10 (41-0-32) Write Rank0 MR13 =0xd8 Write Rank0 MR13 =0xd8 Write Rank0 MR12 =0x5c Write Rank1 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x3a === u2Vref_new: 0x58 --> 0x58 === u2Vref_new: 0x5a --> 0x5a === u2Vref_new: 0x5c --> 0x78 === u2Vref_new: 0x5e --> 0x7a === u2Vref_new: 0x60 --> 0x90 [CA 0] Center 37 (11~63) winsize 53 [CA 1] Center 37 (11~63) winsize 53 [CA 2] Center 34 (6~63) winsize 58 [CA 3] Center 35 (7~63) winsize 57 [CA 4] Center 34 (6~63) winsize 58 [CA 5] Center 28 (-1~57) winsize 59 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 744/100 ps CA0 delay=37 (12~63),Diff = 9 PI (11 cell) CA1 delay=37 (11~63),Diff = 9 PI (11 cell) CA2 delay=35 (7~63),Diff = 7 PI (9 cell) CA3 delay=35 (8~63),Diff = 7 PI (9 cell) CA4 delay=34 (6~63),Diff = 6 PI (7 cell) CA5 delay=28 (-1~57),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=28 === u2Vref_new: 0x5c --> 0x78 Vref(ca) range 1: 28 CS Dly= 9 (40-0-32) Write Rank1 MR13 =0xd8 Write Rank1 MR13 =0xd8 Write Rank1 MR12 =0x5c [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 0 0 25 0 0 26 0 0 27 0 0 28 0 0 29 0 0 30 0 0 31 0 0 32 0 0 33 0 0 34 0 ff 35 0 ff 36 ff ff 37 ff ff 38 ff ff 39 ff ff 40 ff ff 41 ff ff 42 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 36 DQS1 dly: 34 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |2c2b 302 |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 8 |2c2b 3535 |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 12 |2c2b 3736 |(11 11)(11 11) |(1 1)(0 0)| 0 3 1 16 |2c2b 3535 |(11 11)(11 11) |(0 0)(1 1)| 0 3 1 20 |2c2b 3635 |(11 11)(11 11) |(1 0)(0 0)| 0 3 1 24 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 0)| 0 3 1 28 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 1] Lead/lag Transition tap number (1) 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 8 |2c2b 1f1e |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 12 |2c2b 3434 |(11 11)(0 0) |(1 0)(0 0)| 0 3 2 16 |2c2b 1a19 |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 24 |201 2727 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 28 |1110 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 0 |3534 403 |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0 3 3 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 16 |3534 3b3b |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 20 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (1) 3 3 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 4 0 |3534 a09 |(11 11)(11 11) |(0 0)(1 1)| 0 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0 [Byte 1] Lead/lag Transition tap number (1) 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 4 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 4 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0 3 4 24 |201 3534 |(11 11)(11 11) |(0 1)(0 0)| 0 3 4 28 |2121 201 |(11 11)(11 11) |(1 1)(0 1)| 0 3 5 0 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 6, 16) 3 6 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (2) [Byte 1] Lead/lag falling Transition (3, 6, 20) 3 6 24 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0 [Byte 1] Lead/lag Transition tap number (2) 3 6 28 |1010 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0 3 7 0 |4646 2525 |(0 0)(11 11) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 7, 0) 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 1]First pass (3, 7, 4) 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 6, 20) best DQS1 dly(2T, 0.5T, PI) = (3, 6, 24) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 20) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 24) Write Rank0 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 3) best RODT dly(2T, 0.5T) = (2, 3) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxo [MSB] -3, [0] xxxxxxxx xxxxxxxo [MSB] -2, [0] xxxxxxxx xxxxxxxo [MSB] -1, [0] xxxxxxxx xxxxxxxo [MSB] 0, [0] xxxxxxxx xoxxxxxo [MSB] 1, [0] xxxoxxxx ooxxxxxo [MSB] 2, [0] xxxoxxxx ooxxxxxo [MSB] 3, [0] xoooxxxx oooxxxxo [MSB] 4, [0] xxooxxxo oooxxxxo [MSB] 5, [0] xooooxxo oooooooo [MSB] 6, [0] xooooxxo oooooooo [MSB] 7, [0] xoooooxo oooooooo [MSB] 8, [0] xooooooo oooooooo [MSB] 33, [0] oooxoooo ooooooox [MSB] 34, [0] oooxoooo ooooooox [MSB] 35, [0] oooxoooo xxooooox [MSB] 36, [0] oooxoooo xxooooox [MSB] 37, [0] ooxxoooo xxooooox [MSB] 38, [0] ooxxoooo xxooooox [MSB] 39, [0] xxxxxoox xxooxoox [MSB] 40, [0] xxxxxoox xxxoxoox [MSB] 41, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=41, Bit 0, Center 23 (9 ~ 38) 30 iDelay=41, Bit 1, Center 21 (5 ~ 38) 34 iDelay=41, Bit 2, Center 19 (3 ~ 36) 34 iDelay=41, Bit 3, Center 16 (1 ~ 32) 32 iDelay=41, Bit 4, Center 21 (5 ~ 38) 34 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34 iDelay=41, Bit 6, Center 24 (8 ~ 40) 33 iDelay=41, Bit 7, Center 21 (4 ~ 38) 35 iDelay=41, Bit 8, Center 17 (1 ~ 34) 34 iDelay=41, Bit 9, Center 17 (0 ~ 34) 35 iDelay=41, Bit 10, Center 21 (3 ~ 39) 37 iDelay=41, Bit 11, Center 22 (5 ~ 40) 36 iDelay=41, Bit 12, Center 21 (5 ~ 38) 34 iDelay=41, Bit 13, Center 22 (5 ~ 40) 36 iDelay=41, Bit 14, Center 22 (5 ~ 40) 36 iDelay=41, Bit 15, Center 14 (-4 ~ 32) 37 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 21, DQM1 = 19 DQ Delay: DQ0 =23, DQ1 =21, DQ2 =19, DQ3 =16 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =21 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =14 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 930~1186 TX Vref Scan disable 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB] 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB] 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB] 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB] 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB] 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB] 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB] 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB] 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB] 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB] 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB] 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB] 978 |3 6 18|[0] xxxxxxxx xxxxxxxx [MSB] 979 |3 6 19|[0] xxxxxxxx xxxxxxxx [MSB] 980 |3 6 20|[0] xxxxxxxx xxxxxxxx [MSB] 981 |3 6 21|[0] xxxxxxxx oxxxxxxo [MSB] 982 |3 6 22|[0] xxxxxxxx ooxxxxxo [MSB] 983 |3 6 23|[0] xxxxxxxx ooxxxxxo [MSB] 984 |3 6 24|[0] xxxxxxxx ooxxxxxo [MSB] 985 |3 6 25|[0] oooooooo oooxoxoo [MSB] 997 |3 6 37|[0] oooooooo ooooooox [MSB] 998 |3 6 38|[0] oooooooo ooooooox [MSB] 999 |3 6 39|[0] oooooooo ooooooox [MSB] 1000 |3 6 40|[0] oooooooo ooooooox [MSB] 1001 |3 6 41|[0] oooooooo oxooooox [MSB] 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB] 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB] 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB] 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB] 1006 |3 6 46|[0] ooxxoooo xxxxxxxx [MSB] 1007 |3 6 47|[0] ooxxxxxx xxxxxxxx [MSB] 1008 |3 6 48|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=994, DQM PI dly= 994 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 34) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 34) Byte1, DQ PI dly=990, DQM PI dly= 990 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 966~1030 Write Rank0 MR14 =0x0 CH=1, VrefRange= 0, VrefLevel = 0 TX Bit0 (987~1004) 18 995, Bit8 (985~995) 11 990, TX Bit1 (985~1002) 18 993, Bit9 (985~994) 10 989, TX Bit2 (985~998) 14 991, Bit10 (987~1000) 14 993, TX Bit3 (984~996) 13 990, Bit11 (988~1000) 13 994, TX Bit4 (986~1002) 17 994, Bit12 (987~999) 13 993, TX Bit5 (987~1003) 17 995, Bit13 (988~999) 12 993, TX Bit6 (986~1003) 18 994, Bit14 (987~996) 10 991, TX Bit7 (986~1000) 15 993, Bit15 (982~992) 11 987, Write Rank0 MR14 =0x2 CH=1, VrefRange= 0, VrefLevel = 2 TX Bit0 (986~1005) 20 995, Bit8 (985~996) 12 990, TX Bit1 (985~1004) 20 994, Bit9 (985~995) 11 990, TX Bit2 (985~999) 15 992, Bit10 (987~1001) 15 994, TX Bit3 (984~997) 14 990, Bit11 (987~1000) 14 993, TX Bit4 (986~1003) 18 994, Bit12 (987~1000) 14 993, TX Bit5 (987~1004) 18 995, Bit13 (987~1000) 14 993, TX Bit6 (986~1004) 19 995, Bit14 (987~996) 10 991, TX Bit7 (986~1001) 16 993, Bit15 (981~993) 13 987, Write Rank0 MR14 =0x4 CH=1, VrefRange= 0, VrefLevel = 4 TX Bit0 (987~1006) 20 996, Bit8 (985~997) 13 991, TX Bit1 (985~1004) 20 994, Bit9 (985~995) 11 990, TX Bit2 (984~1000) 17 992, Bit10 (986~1001) 16 993, TX Bit3 (983~998) 16 990, Bit11 (987~1001) 15 994, TX Bit4 (986~1004) 19 995, Bit12 (986~1001) 16 993, TX Bit5 (987~1005) 19 996, Bit13 (987~1001) 15 994, TX Bit6 (986~1004) 19 995, Bit14 (986~998) 13 992, TX Bit7 (986~1002) 17 994, Bit15 (981~993) 13 987, Write Rank0 MR14 =0x6 CH=1, VrefRange= 0, VrefLevel = 6 TX Bit0 (986~1005) 20 995, Bit8 (984~998) 15 991, TX Bit1 (985~1005) 21 995, Bit9 (985~997) 13 991, TX Bit2 (984~1001) 18 992, Bit10 (986~1001) 16 993, TX Bit3 (983~998) 16 990, Bit11 (987~1001) 15 994, TX Bit4 (985~1005) 21 995, Bit12 (986~1001) 16 993, TX Bit5 (986~1005) 20 995, Bit13 (987~1001) 15 994, TX Bit6 (986~1005) 20 995, Bit14 (986~999) 14 992, TX Bit7 (986~1003) 18 994, Bit15 (980~994) 15 987, Write Rank0 MR14 =0x8 CH=1, VrefRange= 0, VrefLevel = 8 TX Bit0 (986~1006) 21 996, Bit8 (983~999) 17 991, TX Bit1 (985~1006) 22 995, Bit9 (984~997) 14 990, TX Bit2 (984~1002) 19 993, Bit10 (986~1001) 16 993, TX Bit3 (983~998) 16 990, Bit11 (986~1001) 16 993, TX Bit4 (985~1005) 21 995, Bit12 (986~1002) 17 994, TX Bit5 (986~1005) 20 995, Bit13 (987~1001) 15 994, TX Bit6 (985~1005) 21 995, Bit14 (986~1000) 15 993, TX Bit7 (985~1004) 20 994, Bit15 (980~994) 15 987, Write Rank0 MR14 =0xa CH=1, VrefRange= 0, VrefLevel = 10 TX Bit0 (985~1007) 23 996, Bit8 (982~1000) 19 991, TX Bit1 (985~1006) 22 995, Bit9 (984~998) 15 991, TX Bit2 (984~1003) 20 993, Bit10 (986~1002) 17 994, TX Bit3 (982~1000) 19 991, Bit11 (986~1002) 17 994, TX Bit4 (985~1005) 21 995, Bit12 (986~1002) 17 994, TX Bit5 (986~1006) 21 996, Bit13 (987~1002) 16 994, TX Bit6 (985~1006) 22 995, Bit14 (986~1001) 16 993, TX Bit7 (985~1004) 20 994, Bit15 (980~994) 15 987, Write Rank0 MR14 =0xc CH=1, VrefRange= 0, VrefLevel = 12 TX Bit0 (986~1007) 22 996, Bit8 (982~1000) 19 991, TX Bit1 (985~1006) 22 995, Bit9 (983~999) 17 991, TX Bit2 (984~1003) 20 993, Bit10 (985~1002) 18 993, TX Bit3 (982~1000) 19 991, Bit11 (986~1002) 17 994, TX Bit4 (985~1006) 22 995, Bit12 (985~1002) 18 993, TX Bit5 (985~1006) 22 995, Bit13 (986~1002) 17 994, TX Bit6 (985~1006) 22 995, Bit14 (986~1001) 16 993, TX Bit7 (985~1005) 21 995, Bit15 (979~995) 17 987, Write Rank0 MR14 =0xe CH=1, VrefRange= 0, VrefLevel = 14 TX Bit0 (986~1007) 22 996, Bit8 (982~1001) 20 991, TX Bit1 (984~1006) 23 995, Bit9 (982~1000) 19 991, TX Bit2 (983~1005) 23 994, Bit10 (985~1003) 19 994, TX Bit3 (982~1001) 20 991, Bit11 (986~1003) 18 994, TX Bit4 (985~1006) 22 995, Bit12 (985~1003) 19 994, TX Bit5 (985~1006) 22 995, Bit13 (986~1003) 18 994, TX Bit6 (985~1006) 22 995, Bit14 (986~1002) 17 994, TX Bit7 (985~1005) 21 995, Bit15 (979~995) 17 987, Write Rank0 MR14 =0x10 CH=1, VrefRange= 0, VrefLevel = 16 TX Bit0 (985~1008) 24 996, Bit8 (981~1001) 21 991, TX Bit1 (984~1007) 24 995, Bit9 (982~1000) 19 991, TX Bit2 (983~1005) 23 994, Bit10 (984~1003) 20 993, TX Bit3 (981~1002) 22 991, Bit11 (986~1003) 18 994, TX Bit4 (984~1006) 23 995, Bit12 (986~1003) 18 994, TX Bit5 (985~1006) 22 995, Bit13 (986~1003) 18 994, TX Bit6 (985~1006) 22 995, Bit14 (985~1002) 18 993, TX Bit7 (985~1005) 21 995, Bit15 (978~996) 19 987, Write Rank0 MR14 =0x12 CH=1, VrefRange= 0, VrefLevel = 18 TX Bit0 (985~1008) 24 996, Bit8 (981~1001) 21 991, TX Bit1 (984~1007) 24 995, Bit9 (982~1001) 20 991, TX Bit2 (983~1005) 23 994, Bit10 (985~1003) 19 994, TX Bit3 (981~1002) 22 991, Bit11 (985~1003) 19 994, TX Bit4 (984~1006) 23 995, Bit12 (985~1003) 19 994, TX Bit5 (985~1007) 23 996, Bit13 (986~1003) 18 994, TX Bit6 (984~1007) 24 995, Bit14 (985~1002) 18 993, TX Bit7 (984~1006) 23 995, Bit15 (978~997) 20 987, Write Rank0 MR14 =0x14 CH=1, VrefRange= 0, VrefLevel = 20 TX Bit0 (985~1008) 24 996, Bit8 (981~1002) 22 991, TX Bit1 (984~1007) 24 995, Bit9 (981~1001) 21 991, TX Bit2 (983~1006) 24 994, Bit10 (984~1004) 21 994, TX Bit3 (981~1003) 23 992, Bit11 (985~1004) 20 994, TX Bit4 (984~1007) 24 995, Bit12 (984~1004) 21 994, TX Bit5 (985~1007) 23 996, Bit13 (986~1004) 19 995, TX Bit6 (984~1007) 24 995, Bit14 (985~1003) 19 994, TX Bit7 (984~1006) 23 995, Bit15 (978~998) 21 988, Write Rank0 MR14 =0x16 CH=1, VrefRange= 0, VrefLevel = 22 TX Bit0 (985~1009) 25 997, Bit8 (980~1002) 23 991, TX Bit1 (984~1008) 25 996, Bit9 (980~1001) 22 990, TX Bit2 (982~1006) 25 994, Bit10 (984~1005) 22 994, TX Bit3 (980~1004) 25 992, Bit11 (984~1005) 22 994, TX Bit4 (984~1007) 24 995, Bit12 (985~1005) 21 995, TX Bit5 (985~1008) 24 996, Bit13 (986~1005) 20 995, TX Bit6 (984~1008) 25 996, Bit14 (985~1003) 19 994, TX Bit7 (984~1007) 24 995, Bit15 (978~999) 22 988, Write Rank0 MR14 =0x18 CH=1, VrefRange= 0, VrefLevel = 24 TX Bit0 (985~1009) 25 997, Bit8 (980~1002) 23 991, TX Bit1 (984~1008) 25 996, Bit9 (980~1002) 23 991, TX Bit2 (982~1006) 25 994, Bit10 (983~1006) 24 994, TX Bit3 (980~1004) 25 992, Bit11 (985~1005) 21 995, TX Bit4 (984~1008) 25 996, Bit12 (984~1005) 22 994, TX Bit5 (985~1008) 24 996, Bit13 (985~1005) 21 995, TX Bit6 (984~1008) 25 996, Bit14 (984~1003) 20 993, TX Bit7 (984~1007) 24 995, Bit15 (978~999) 22 988, Write Rank0 MR14 =0x1a CH=1, VrefRange= 0, VrefLevel = 26 TX Bit0 (985~1009) 25 997, Bit8 (980~1003) 24 991, TX Bit1 (983~1008) 26 995, Bit9 (980~1002) 23 991, TX Bit2 (982~1007) 26 994, Bit10 (983~1005) 23 994, TX Bit3 (979~1005) 27 992, Bit11 (984~1007) 24 995, TX Bit4 (984~1008) 25 996, Bit12 (984~1006) 23 995, TX Bit5 (985~1008) 24 996, Bit13 (985~1006) 22 995, TX Bit6 (984~1008) 25 996, Bit14 (983~1004) 22 993, TX Bit7 (984~1007) 24 995, Bit15 (978~1000) 23 989, Write Rank0 MR14 =0x1c CH=1, VrefRange= 0, VrefLevel = 28 TX Bit0 (985~1010) 26 997, Bit8 (980~1002) 23 991, TX Bit1 (984~1008) 25 996, Bit9 (979~1002) 24 990, TX Bit2 (982~1006) 25 994, Bit10 (983~1005) 23 994, TX Bit3 (979~1005) 27 992, Bit11 (984~1006) 23 995, TX Bit4 (984~1008) 25 996, Bit12 (984~1006) 23 995, TX Bit5 (984~1009) 26 996, Bit13 (985~1006) 22 995, TX Bit6 (984~1009) 26 996, Bit14 (983~1005) 23 994, TX Bit7 (984~1008) 25 996, Bit15 (977~1000) 24 988, Write Rank0 MR14 =0x1e CH=1, VrefRange= 0, VrefLevel = 30 TX Bit0 (985~1010) 26 997, Bit8 (980~1002) 23 991, TX Bit1 (984~1008) 25 996, Bit9 (979~1002) 24 990, TX Bit2 (982~1006) 25 994, Bit10 (983~1005) 23 994, TX Bit3 (979~1005) 27 992, Bit11 (984~1006) 23 995, TX Bit4 (984~1008) 25 996, Bit12 (984~1006) 23 995, TX Bit5 (984~1009) 26 996, Bit13 (985~1006) 22 995, TX Bit6 (984~1009) 26 996, Bit14 (983~1005) 23 994, TX Bit7 (984~1008) 25 996, Bit15 (977~1000) 24 988, Write Rank0 MR14 =0x20 CH=1, VrefRange= 0, VrefLevel = 32 TX Bit0 (985~1010) 26 997, Bit8 (980~1002) 23 991, TX Bit1 (984~1008) 25 996, Bit9 (979~1002) 24 990, TX Bit2 (982~1006) 25 994, Bit10 (983~1005) 23 994, TX Bit3 (979~1005) 27 992, Bit11 (984~1006) 23 995, TX Bit4 (984~1008) 25 996, Bit12 (984~1006) 23 995, TX Bit5 (984~1009) 26 996, Bit13 (985~1006) 22 995, TX Bit6 (984~1009) 26 996, Bit14 (983~1005) 23 994, TX Bit7 (984~1008) 25 996, Bit15 (977~1000) 24 988, Write Rank0 MR14 =0x22 CH=1, VrefRange= 0, VrefLevel = 34 TX Bit0 (985~1010) 26 997, Bit8 (980~1002) 23 991, TX Bit1 (984~1008) 25 996, Bit9 (979~1002) 24 990, TX Bit2 (982~1006) 25 994, Bit10 (983~1005) 23 994, TX Bit3 (979~1005) 27 992, Bit11 (984~1006) 23 995, TX Bit4 (984~1008) 25 996, Bit12 (984~1006) 23 995, TX Bit5 (984~1009) 26 996, Bit13 (985~1006) 22 995, TX Bit6 (984~1009) 26 996, Bit14 (983~1005) 23 994, TX Bit7 (984~1008) 25 996, Bit15 (977~1000) 24 988, TX Vref found, early break! 368< 370 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps u1DelayCellOfst[0]=6 cells (5 PI) u1DelayCellOfst[1]=5 cells (4 PI) u1DelayCellOfst[2]=2 cells (2 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=5 cells (4 PI) u1DelayCellOfst[5]=5 cells (4 PI) u1DelayCellOfst[6]=5 cells (4 PI) u1DelayCellOfst[7]=5 cells (4 PI) Byte0, DQ PI dly=992, DQM PI dly= 994 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32) u1DelayCellOfst[8]=3 cells (3 PI) u1DelayCellOfst[9]=2 cells (2 PI) u1DelayCellOfst[10]=7 cells (6 PI) u1DelayCellOfst[11]=9 cells (7 PI) u1DelayCellOfst[12]=9 cells (7 PI) u1DelayCellOfst[13]=9 cells (7 PI) u1DelayCellOfst[14]=7 cells (6 PI) u1DelayCellOfst[15]=0 cells (0 PI) Byte1, DQ PI dly=988, DQM PI dly= 991 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28) Write Rank0 MR14 =0x1c Final TX Range 0 Vref 28 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 711~775 TX Vref Scan disable 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB] 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB] 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB] 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB] 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB] 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB] 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB] 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB] 719 |2 6 15|[0] xxxxxxxx xxxxxxxx [MSB] 720 |2 6 16|[0] xxxxxxxx xxxxxxxx [MSB] 721 |2 6 17|[0] xxxxxxxx xxxxxxxx [MSB] 722 |2 6 18|[0] xxxxxxxx xxxxxxxx [MSB] 723 |2 6 19|[0] xxxxxxxx xxxxxxxx [MSB] 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB] 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB] 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB] 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB] 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB] 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB] 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB] 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB] 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB] 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB] 754 |2 6 50|[0] oooooooo xxxxxxxx [MSB] 755 |2 6 51|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=741, DQM PI dly= 741 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 37) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 37) Byte1, DQ PI dly=735, DQM PI dly= 735 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank0 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK0, use_rxtx_scan=0 DATLAT Default: 0xf 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 1 RX Vref found, early break! Final RX Vref 11, apply to both rank0 and 1 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =22, DQ1 =20, DQ2 =19, DQ3 =16 DQ4 =20, DQ5 =22, DQ6 =24, DQ7 =21 DQ8 =17, DQ9 =17, DQ10 =20, DQ11 =21 DQ12 =22, DQ13 =21, DQ14 =22, DQ15 =14 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFF, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps CH1_RK0: MR19=0x202, MR18=0xADAD, DQSOSC=459, MR23=63, INC=11, DEC=17 Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b0, (MSB)MR19= 0x202, tDQSOscB0 = 457 ps tDQSOscB1 = 457 ps CH1 RK0: MR19=202, MR18=B0B0 [RankSwap] Rank num 2, (Multi 1), Rank 1 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 0 0 25 0 0 26 0 0 27 0 0 28 0 ff 29 0 ff 30 0 ff 31 0 ff 32 0 ff 33 0 ff 34 0 ff 35 ff ff 36 ff ff 37 ff ff 38 ff ff 39 ff ff 40 ff ff 41 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 35 DQS1 dly: 28 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank1 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |2c2b 3635 |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 4 |2c2b 100 |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 8 |2c2b 3535 |(11 11)(0 0) |(1 1)(0 0)| 0 3 1 12 |2c2b 3534 |(11 11)(11 11) |(0 0)(1 1)| 0 3 1 16 |2c2b 3736 |(11 11)(11 11) |(1 0)(0 0)| 0 3 1 20 |2c2b 3636 |(11 11)(0 0) |(1 0)(1 1)| 0 3 1 24 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 1] Lead/lag Transition tap number (1) 3 1 28 |2c2b 3535 |(11 11)(0 0) |(1 0)(0 0)| 0 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 12 |2c2b 3434 |(11 11)(11 11) |(1 0)(0 0)| 0 3 2 16 |2c2c 3434 |(11 10)(0 0) |(1 0)(1 1)| 0 3 2 20 |303 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 2 24 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 28 |3534 3c3b |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 0 |3534 2828 |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 4 |3534 3c3b |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 8 |3534 3d3d |(11 11)(0 0) |(0 0)(1 1)| 0 3 3 12 |3534 3c3b |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 16 |3534 3b3b |(11 11)(0 0) |(1 1)(1 1)| 0 3 3 20 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (1) 3 3 24 |3534 e0e |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0 [Byte 1] Lead/lag Transition tap number (1) 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0 3 4 20 |e0e 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 6, 8) 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (3) [Byte 1] Lead/lag falling Transition (3, 6, 16) 3 6 20 |202 3e3d |(11 11)(11 11) |(0 0)(1 0)| 0 [Byte 1] Lead/lag Transition tap number (2) 3 6 24 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 6, 24) 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 1]First pass (3, 6, 28) 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 6, 14) best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 14) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20) Write Rank1 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 3) best RODT dly(2T, 0.5T) = (2, 3) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxxxxxx xxxxxxxx [MSB] -1, [0] xxxxxxxx xxxxxxxo [MSB] 0, [0] xxxoxxxx xxxxxxxo [MSB] 1, [0] xxxoxxxx xxxxxxxo [MSB] 2, [0] xxxoxxxx ooxxxxxo [MSB] 3, [0] xoooxxxo ooxxxxxo [MSB] 4, [0] xooooxxo oooxxxxo [MSB] 5, [0] xooooxxo oooxxxxo [MSB] 6, [0] xooooooo ooooxxoo [MSB] 33, [0] oooxoooo ooooooox [MSB] 34, [0] oooxoooo ooooooox [MSB] 35, [0] ooxxoooo xoooooox [MSB] 36, [0] ooxxoooo xxooooox [MSB] 37, [0] ooxxoooo xxooooox [MSB] 38, [0] oxxxooox xxooooox [MSB] 39, [0] xxxxxoox xxxoxoox [MSB] 40, [0] xxxxxoox xxxoxxox [MSB] 41, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=41, Bit 0, Center 22 (7 ~ 38) 32 iDelay=41, Bit 1, Center 20 (3 ~ 37) 35 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32 iDelay=41, Bit 3, Center 16 (0 ~ 32) 33 iDelay=41, Bit 4, Center 21 (4 ~ 38) 35 iDelay=41, Bit 5, Center 23 (6 ~ 40) 35 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35 iDelay=41, Bit 8, Center 18 (2 ~ 34) 33 iDelay=41, Bit 9, Center 18 (2 ~ 35) 34 iDelay=41, Bit 10, Center 21 (4 ~ 38) 35 iDelay=41, Bit 11, Center 23 (6 ~ 40) 35 iDelay=41, Bit 12, Center 22 (7 ~ 38) 32 iDelay=41, Bit 13, Center 23 (7 ~ 39) 33 iDelay=41, Bit 14, Center 23 (6 ~ 40) 35 iDelay=41, Bit 15, Center 15 (-1 ~ 32) 34 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 20 DQ Delay: DQ0 =22, DQ1 =20, DQ2 =18, DQ3 =16 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20 DQ8 =18, DQ9 =18, DQ10 =21, DQ11 =23 DQ12 =22, DQ13 =23, DQ14 =23, DQ15 =15 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 924~1180 TX Vref Scan disable 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB] 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB] 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB] 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB] 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB] 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB] 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB] 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB] 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB] 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB] 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB] 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB] 972 |3 6 12|[0] xxxxxxxx oxxxxxxo [MSB] 973 |3 6 13|[0] xxxxxxxx ooxxxxxo [MSB] 974 |3 6 14|[0] xxxxxxxx ooxxxxxo [MSB] 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB] 976 |3 6 16|[0] xxxxxxxx oooxxxxo [MSB] 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB] 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB] 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB] 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB] 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB] 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB] 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB] 984 |3 6 24|[0] xooooooo oooooooo [MSB] 992 |3 6 32|[0] oooooooo ooooooox [MSB] 993 |3 6 33|[0] oooooooo oxooooox [MSB] 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB] 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB] 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB] 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB] 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB] 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB] 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB] 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB] 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB] 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB] 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB] 1005 |3 6 45|[0] ooxxoooo xxxxxxxx [MSB] 1006 |3 6 46|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=993, DQM PI dly= 993 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33) Byte1, DQ PI dly=983, DQM PI dly= 983 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 959~1023 Write Rank1 MR14 =0x0 CH=1, VrefRange= 0, VrefLevel = 0 TX Bit0 (986~1000) 15 993, Bit8 (976~989) 14 982, TX Bit1 (985~998) 14 991, Bit9 (977~986) 10 981, TX Bit2 (984~998) 15 991, Bit10 (979~992) 14 985, TX Bit3 (982~995) 14 988, Bit11 (979~992) 14 985, TX Bit4 (985~999) 15 992, Bit12 (979~991) 13 985, TX Bit5 (985~1000) 16 992, Bit13 (979~993) 15 986, TX Bit6 (985~1000) 16 992, Bit14 (979~992) 14 985, TX Bit7 (985~1000) 16 992, Bit15 (972~984) 13 978, Write Rank1 MR14 =0x2 CH=1, VrefRange= 0, VrefLevel = 2 TX Bit0 (986~1001) 16 993, Bit8 (976~990) 15 983, TX Bit1 (985~999) 15 992, Bit9 (977~987) 11 982, TX Bit2 (983~999) 17 991, Bit10 (979~992) 14 985, TX Bit3 (981~996) 16 988, Bit11 (979~992) 14 985, TX Bit4 (985~1000) 16 992, Bit12 (979~992) 14 985, TX Bit5 (986~1000) 15 993, Bit13 (979~993) 15 986, TX Bit6 (985~1000) 16 992, Bit14 (979~992) 14 985, TX Bit7 (985~1000) 16 992, Bit15 (972~985) 14 978, Write Rank1 MR14 =0x4 CH=1, VrefRange= 0, VrefLevel = 4 TX Bit0 (986~1002) 17 994, Bit8 (975~991) 17 983, TX Bit1 (985~1000) 16 992, Bit9 (976~987) 12 981, TX Bit2 (984~999) 16 991, Bit10 (978~993) 16 985, TX Bit3 (981~997) 17 989, Bit11 (979~993) 15 986, TX Bit4 (985~1001) 17 993, Bit12 (979~993) 15 986, TX Bit5 (986~1001) 16 993, Bit13 (979~994) 16 986, TX Bit6 (984~1001) 18 992, Bit14 (978~992) 15 985, TX Bit7 (985~1001) 17 993, Bit15 (972~985) 14 978, Write Rank1 MR14 =0x6 CH=1, VrefRange= 0, VrefLevel = 6 TX Bit0 (985~1003) 19 994, Bit8 (974~991) 18 982, TX Bit1 (984~1001) 18 992, Bit9 (975~988) 14 981, TX Bit2 (983~1000) 18 991, Bit10 (978~993) 16 985, TX Bit3 (980~997) 18 988, Bit11 (979~993) 15 986, TX Bit4 (984~1002) 19 993, Bit12 (979~993) 15 986, TX Bit5 (985~1002) 18 993, Bit13 (978~994) 17 986, TX Bit6 (984~1002) 19 993, Bit14 (978~993) 16 985, TX Bit7 (984~1002) 19 993, Bit15 (972~986) 15 979, Write Rank1 MR14 =0x8 CH=1, VrefRange= 0, VrefLevel = 8 TX Bit0 (985~1003) 19 994, Bit8 (974~992) 19 983, TX Bit1 (984~1002) 19 993, Bit9 (975~990) 16 982, TX Bit2 (983~1000) 18 991, Bit10 (977~994) 18 985, TX Bit3 (980~998) 19 989, Bit11 (978~994) 17 986, TX Bit4 (984~1002) 19 993, Bit12 (978~993) 16 985, TX Bit5 (985~1003) 19 994, Bit13 (978~995) 18 986, TX Bit6 (984~1002) 19 993, Bit14 (978~994) 17 986, TX Bit7 (984~1002) 19 993, Bit15 (971~987) 17 979, Write Rank1 MR14 =0xa CH=1, VrefRange= 0, VrefLevel = 10 TX Bit0 (985~1004) 20 994, Bit8 (973~992) 20 982, TX Bit1 (984~1003) 20 993, Bit9 (974~990) 17 982, TX Bit2 (982~1001) 20 991, Bit10 (977~994) 18 985, TX Bit3 (979~998) 20 988, Bit11 (978~994) 17 986, TX Bit4 (984~1003) 20 993, Bit12 (978~994) 17 986, TX Bit5 (985~1004) 20 994, Bit13 (978~995) 18 986, TX Bit6 (984~1003) 20 993, Bit14 (977~994) 18 985, TX Bit7 (984~1003) 20 993, Bit15 (971~988) 18 979, Write Rank1 MR14 =0xc CH=1, VrefRange= 0, VrefLevel = 12 TX Bit0 (985~1005) 21 995, Bit8 (973~992) 20 982, TX Bit1 (984~1004) 21 994, Bit9 (974~991) 18 982, TX Bit2 (982~1002) 21 992, Bit10 (976~995) 20 985, TX Bit3 (979~999) 21 989, Bit11 (977~995) 19 986, TX Bit4 (984~1003) 20 993, Bit12 (978~994) 17 986, TX Bit5 (985~1005) 21 995, Bit13 (978~996) 19 987, TX Bit6 (984~1004) 21 994, Bit14 (977~994) 18 985, TX Bit7 (984~1004) 21 994, Bit15 (971~989) 19 980, Write Rank1 MR14 =0xe CH=1, VrefRange= 0, VrefLevel = 14 TX Bit0 (985~1005) 21 995, Bit8 (973~993) 21 983, TX Bit1 (984~1005) 22 994, Bit9 (973~991) 19 982, TX Bit2 (982~1002) 21 992, Bit10 (976~996) 21 986, TX Bit3 (979~999) 21 989, Bit11 (977~996) 20 986, TX Bit4 (984~1004) 21 994, Bit12 (977~995) 19 986, TX Bit5 (985~1005) 21 995, Bit13 (978~997) 20 987, TX Bit6 (983~1005) 23 994, Bit14 (977~995) 19 986, TX Bit7 (984~1005) 22 994, Bit15 (971~990) 20 980, Write Rank1 MR14 =0x10 CH=1, VrefRange= 0, VrefLevel = 16 TX Bit0 (985~1006) 22 995, Bit8 (973~993) 21 983, TX Bit1 (983~1005) 23 994, Bit9 (973~992) 20 982, TX Bit2 (981~1003) 23 992, Bit10 (975~996) 22 985, TX Bit3 (979~1000) 22 989, Bit11 (977~996) 20 986, TX Bit4 (983~1005) 23 994, Bit12 (977~996) 20 986, TX Bit5 (984~1006) 23 995, Bit13 (977~997) 21 987, TX Bit6 (983~1005) 23 994, Bit14 (977~996) 20 986, TX Bit7 (984~1005) 22 994, Bit15 (971~991) 21 981, Write Rank1 MR14 =0x12 CH=1, VrefRange= 0, VrefLevel = 18 TX Bit0 (984~1006) 23 995, Bit8 (972~993) 22 982, TX Bit1 (983~1005) 23 994, Bit9 (973~992) 20 982, TX Bit2 (981~1004) 24 992, Bit10 (975~997) 23 986, TX Bit3 (978~1000) 23 989, Bit11 (977~997) 21 987, TX Bit4 (983~1005) 23 994, Bit12 (976~997) 22 986, TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987, TX Bit6 (983~1005) 23 994, Bit14 (976~996) 21 986, TX Bit7 (984~1005) 22 994, Bit15 (970~991) 22 980, Write Rank1 MR14 =0x14 CH=1, VrefRange= 0, VrefLevel = 20 TX Bit0 (984~1006) 23 995, Bit8 (973~994) 22 983, TX Bit1 (983~1005) 23 994, Bit9 (972~992) 21 982, TX Bit2 (980~1005) 26 992, Bit10 (975~998) 24 986, TX Bit3 (978~1001) 24 989, Bit11 (976~998) 23 987, TX Bit4 (983~1006) 24 994, Bit12 (976~997) 22 986, TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987, TX Bit6 (983~1005) 23 994, Bit14 (976~997) 22 986, TX Bit7 (984~1005) 22 994, Bit15 (970~992) 23 981, Write Rank1 MR14 =0x16 CH=1, VrefRange= 0, VrefLevel = 22 TX Bit0 (984~1006) 23 995, Bit8 (972~994) 23 983, TX Bit1 (982~1006) 25 994, Bit9 (972~993) 22 982, TX Bit2 (980~1005) 26 992, Bit10 (975~998) 24 986, TX Bit3 (978~1001) 24 989, Bit11 (975~999) 25 987, TX Bit4 (982~1006) 25 994, Bit12 (976~998) 23 987, TX Bit5 (984~1006) 23 995, Bit13 (977~999) 23 988, TX Bit6 (983~1006) 24 994, Bit14 (975~998) 24 986, TX Bit7 (983~1006) 24 994, Bit15 (970~992) 23 981, Write Rank1 MR14 =0x18 CH=1, VrefRange= 0, VrefLevel = 24 TX Bit0 (984~1007) 24 995, Bit8 (971~995) 25 983, TX Bit1 (982~1006) 25 994, Bit9 (972~993) 22 982, TX Bit2 (980~1005) 26 992, Bit10 (974~998) 25 986, TX Bit3 (978~1002) 25 990, Bit11 (975~999) 25 987, TX Bit4 (982~1006) 25 994, Bit12 (976~998) 23 987, TX Bit5 (984~1007) 24 995, Bit13 (976~999) 24 987, TX Bit6 (982~1006) 25 994, Bit14 (975~998) 24 986, TX Bit7 (983~1006) 24 994, Bit15 (970~993) 24 981, Write Rank1 MR14 =0x1a CH=1, VrefRange= 0, VrefLevel = 26 TX Bit0 (984~1007) 24 995, Bit8 (971~996) 26 983, TX Bit1 (982~1006) 25 994, Bit9 (972~993) 22 982, TX Bit2 (979~1005) 27 992, Bit10 (973~999) 27 986, TX Bit3 (978~1002) 25 990, Bit11 (975~999) 25 987, TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987, TX Bit5 (984~1007) 24 995, Bit13 (976~1000) 25 988, TX Bit6 (982~1006) 25 994, Bit14 (974~999) 26 986, TX Bit7 (983~1006) 24 994, Bit15 (969~993) 25 981, Write Rank1 MR14 =0x1c CH=1, VrefRange= 0, VrefLevel = 28 TX Bit0 (984~1008) 25 996, Bit8 (972~996) 25 984, TX Bit1 (982~1007) 26 994, Bit9 (971~994) 24 982, TX Bit2 (979~1005) 27 992, Bit10 (973~999) 27 986, TX Bit3 (977~1003) 27 990, Bit11 (974~999) 26 986, TX Bit4 (982~1007) 26 994, Bit12 (975~999) 25 987, TX Bit5 (983~1007) 25 995, Bit13 (976~1000) 25 988, TX Bit6 (982~1007) 26 994, Bit14 (974~999) 26 986, TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981, Write Rank1 MR14 =0x1e CH=1, VrefRange= 0, VrefLevel = 30 TX Bit0 (983~1008) 26 995, Bit8 (972~996) 25 984, TX Bit1 (982~1006) 25 994, Bit9 (971~994) 24 982, TX Bit2 (979~1005) 27 992, Bit10 (973~1000) 28 986, TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987, TX Bit4 (982~1007) 26 994, Bit12 (974~999) 26 986, TX Bit5 (983~1008) 26 995, Bit13 (975~1000) 26 987, TX Bit6 (982~1007) 26 994, Bit14 (974~999) 26 986, TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981, Write Rank1 MR14 =0x20 CH=1, VrefRange= 0, VrefLevel = 32 TX Bit0 (983~1008) 26 995, Bit8 (972~996) 25 984, TX Bit1 (982~1006) 25 994, Bit9 (971~994) 24 982, TX Bit2 (979~1005) 27 992, Bit10 (973~1000) 28 986, TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987, TX Bit4 (982~1007) 26 994, Bit12 (974~999) 26 986, TX Bit5 (983~1008) 26 995, Bit13 (975~1000) 26 987, TX Bit6 (982~1007) 26 994, Bit14 (974~999) 26 986, TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981, Write Rank1 MR14 =0x22 CH=1, VrefRange= 0, VrefLevel = 34 TX Bit0 (983~1008) 26 995, Bit8 (972~996) 25 984, TX Bit1 (982~1006) 25 994, Bit9 (971~994) 24 982, TX Bit2 (979~1005) 27 992, Bit10 (973~1000) 28 986, TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987, TX Bit4 (982~1007) 26 994, Bit12 (974~999) 26 986, TX Bit5 (983~1008) 26 995, Bit13 (975~1000) 26 987, TX Bit6 (982~1007) 26 994, Bit14 (974~999) 26 986, TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981, Write Rank1 MR14 =0x24 CH=1, VrefRange= 0, VrefLevel = 36 TX Bit0 (983~1008) 26 995, Bit8 (972~996) 25 984, TX Bit1 (982~1006) 25 994, Bit9 (971~994) 24 982, TX Bit2 (979~1005) 27 992, Bit10 (973~1000) 28 986, TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987, TX Bit4 (982~1007) 26 994, Bit12 (974~999) 26 986, TX Bit5 (983~1008) 26 995, Bit13 (975~1000) 26 987, TX Bit6 (982~1007) 26 994, Bit14 (974~999) 26 986, TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981, TX Vref found, early break! 389< 392 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps u1DelayCellOfst[0]=6 cells (5 PI) u1DelayCellOfst[1]=5 cells (4 PI) u1DelayCellOfst[2]=2 cells (2 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=5 cells (4 PI) u1DelayCellOfst[5]=6 cells (5 PI) u1DelayCellOfst[6]=5 cells (4 PI) u1DelayCellOfst[7]=5 cells (4 PI) Byte0, DQ PI dly=990, DQM PI dly= 992 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30) u1DelayCellOfst[8]=3 cells (3 PI) u1DelayCellOfst[9]=1 cells (1 PI) u1DelayCellOfst[10]=6 cells (5 PI) u1DelayCellOfst[11]=7 cells (6 PI) u1DelayCellOfst[12]=6 cells (5 PI) u1DelayCellOfst[13]=7 cells (6 PI) u1DelayCellOfst[14]=6 cells (5 PI) u1DelayCellOfst[15]=0 cells (0 PI) Byte1, DQ PI dly=981, DQM PI dly= 984 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21) wait MRW command Rank1 MR14 =0x1e fired (1) Write Rank1 MR14 =0x1e Final TX Range 0 Vref 30 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 704~768 TX Vref Scan disable 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB] 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB] 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB] 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB] 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB] 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB] 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB] 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB] 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB] 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB] 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB] 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB] 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB] 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB] 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB] 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB] 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB] 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB] 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB] 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB] 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB] 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB] 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB] 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB] 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB] 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB] 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB] 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB] 753 |2 6 49|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=739, DQM PI dly= 739 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 35) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 35) Byte1, DQ PI dly=728, DQM PI dly= 728 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank1 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK1, use_rxtx_scan=0 DATLAT Default: 0x10 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxxxxxx xxxxxxxo [MSB] -1, [0] xxxxxxxx xxxxxxxo [MSB] 0, [0] xxxoxxxx xxxxxxxo [MSB] 1, [0] xxxoxxxx ooxxxxxo [MSB] 2, [0] xoooxxxx ooxxxxxo [MSB] 3, [0] xooooxxx ooxxxxxo [MSB] 4, [0] xooooxxo oooxxxxo [MSB] 5, [0] ooooooxo ooooxxxo [MSB] 6, [0] ooooooxo ooooxooo [MSB] 33, [0] oooxoooo ooooooox [MSB] 34, [0] oooxoooo ooooooox [MSB] 35, [0] oooxoooo xxooooox [MSB] 36, [0] ooxxoooo xxooooox [MSB] 37, [0] ooxxoooo xxooooox [MSB] 38, [0] oxxxoooo xxxoooox [MSB] 39, [0] xxxxxoox xxxxxxxx [MSB] 40, [0] xxxxxoox xxxxxxxx [MSB] 41, [0] xxxxxxox xxxxxxxx [MSB] 42, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=42, Bit 0, Center 21 (5 ~ 38) 34 iDelay=42, Bit 1, Center 19 (2 ~ 37) 36 iDelay=42, Bit 2, Center 18 (2 ~ 35) 34 iDelay=42, Bit 3, Center 16 (0 ~ 32) 33 iDelay=42, Bit 4, Center 20 (3 ~ 38) 36 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36 iDelay=42, Bit 6, Center 24 (7 ~ 41) 35 iDelay=42, Bit 7, Center 21 (4 ~ 38) 35 iDelay=42, Bit 8, Center 17 (1 ~ 34) 34 iDelay=42, Bit 9, Center 17 (1 ~ 34) 34 iDelay=42, Bit 10, Center 20 (4 ~ 37) 34 iDelay=42, Bit 11, Center 21 (5 ~ 38) 34 iDelay=42, Bit 12, Center 22 (7 ~ 38) 32 iDelay=42, Bit 13, Center 22 (6 ~ 38) 33 iDelay=42, Bit 14, Center 22 (6 ~ 38) 33 iDelay=42, Bit 15, Center 15 (-2 ~ 32) 35 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =21, DQ1 =19, DQ2 =18, DQ3 =16 DQ4 =20, DQ5 =22, DQ6 =24, DQ7 =21 DQ8 =17, DQ9 =17, DQ10 =20, DQ11 =21 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =15 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFF, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0x202, tDQSOscB0 = 457 ps tDQSOscB1 = 457 ps CH1_RK1: MR19=0x202, MR18=0xB0B0, DQSOSC=457, MR23=63, INC=11, DEC=17 Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0x202, tDQSOscB0 = 457 ps tDQSOscB1 = 457 ps CH1 RK1: MR19=202, MR18=B0B0 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 Rank: 0 best DQS0 dly(2T, 0.5T) = (2, 6) best DQS1 dly(2T, 0.5T) = (2, 6) best DQS0 P1 dly(2T, 0.5T) = (3, 2) best DQS1 P1 dly(2T, 0.5T) = (3, 2) Rank: 1 best DQS0 dly(2T, 0.5T) = (2, 6) best DQS1 dly(2T, 0.5T) = (2, 6) best DQS0 P1 dly(2T, 0.5T) = (3, 2) best DQS1 P1 dly(2T, 0.5T) = (3, 2) TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16 [Calibration Summary] Freqency 1600 CH 0, Rank 0 All Pass. CH 0, Rank 1 All Pass. CH 1, Rank 0 All Pass. CH 1, Rank 1 All Pass. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 DramC Write-DBI on [GetDramInforAfterCalByMRR] Vendor 6. [GetDramInforAfterCalByMRR] Revision 505. MR8 1111 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000. MR8 1111 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000. MR8 1111 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000. MR8 1111 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000. [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0 Write Rank0 MR13 =0xd0 Write Rank1 MR13 =0xd0 Write Rank0 MR13 =0xd0 Write Rank1 MR13 =0xd0 Save calibration result to emmc [DramcModeReg_Check] Freq_1600, FSP_1 FSP_1, CH_0, RK0 Write Rank0 MR13 =0xd8 MR12 = 0x5e (global = 0x5e) match MR14 = 0x1c (global = 0x1c) match FSP_1, CH_0, RK1 Write Rank1 MR13 =0xd8 MR12 = 0x60 (global = 0x60) match MR14 = 0x1a (global = 0x1a) match FSP_1, CH_1, RK0 Write Rank0 MR13 =0xd8 MR12 = 0x5c (global = 0x5c) match MR14 = 0x1c (global = 0x1c) match FSP_1, CH_1, RK1 Write Rank1 MR13 =0xd8 MR12 = 0x5c (global = 0x5c) match MR14 = 0x1e (global = 0x1e) match [MEM_TEST] 02: After DFS, before run time config [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0) [TA2_TEST] === TA2 HW TA2 PAT: XTALK HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0 Settings after calibration [DramcRunTimeConfig] TransferPLLToSPMControl - MODE SW PHYPLL TX_TRACKING: ON RX_TRACKING: ON HW_GATING: ON HW_GATING DBG: OFF ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 High Freq DUMMY_READ_FOR_TRACKING: ON ZQCS_ENABLE_LP4: OFF LOWPOWER_GOLDEN_SETTINGS(DCM): ON DUMMY_READ_FOR_DQS_GATING_RETRY: OFF SPM_CONTROL_AFTERK: ON IMPEDANCE_TRACKING: ON TEMP_SENSOR: ON PER_BANK_REFRESH: ON HW_SAVE_FOR_SR: ON SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON CLK_FREE_FUN_FOR_DRAMC_PSEL: ON PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON Read ODT Tracking: ON ========================= [TA2_TEST] === TA2 HW HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0 [MEM_TEST] 03: After run time config [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0) [complex_mem_test] start addr:0x40024000, len:131072 1st complex R/W mem test pass save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0 sync preloader write leveling sync preloader cbt_mr12 sync preloader cbt_clk_dly sync preloader cbt_cmd_dly sync preloader cbt_cs sync preloader cbt_ca_perbit_delay sync preloader clk_delay sync preloader dqs_delay sync preloader u1Gating2T_Save sync preloader u1Gating05T_Save sync preloader u1Gatingfine_tune_Save sync preloader u1Gatingucpass_count_Save sync preloader u1TxWindowPerbitVref_Save sync preloader u1TxCenter_min_Save sync preloader u1TxCenter_max_Save sync preloader u1Txwin_center_Save sync preloader u1Txfirst_pass_Save sync preloader u1Txlast_pass_Save sync preloader u1RxDatlat_Save sync preloader u1RxWinPerbitVref_Save sync preloader u1RxWinPerbitDQ_firsbypass_Save sync preloader u1RxWinPerbitDQ_lastbypass_Save sync preloader delay_cell_unit save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1 sync preloader write leveling sync preloader cbt_mr12 sync preloader cbt_clk_dly sync preloader cbt_cmd_dly sync preloader cbt_cs sync preloader cbt_ca_perbit_delay sync preloader clk_delay sync preloader dqs_delay sync preloader u1Gating2T_Save sync preloader u1Gating05T_Save sync preloader u1Gatingfine_tune_Save sync preloader u1Gatingucpass_count_Save sync preloader u1TxWindowPerbitVref_Save sync preloader u1TxCenter_min_Save sync preloader u1TxCenter_max_Save sync preloader u1Txwin_center_Save sync preloader u1Txfirst_pass_Save sync preloader u1Txlast_pass_Save sync preloader u1RxDatlat_Save sync preloader u1RxWinPerbitVref_Save sync preloader u1RxWinPerbitDQ_firsbypass_Save sync preloader u1RxWinPerbitDQ_lastbypass_Save sync preloader delay_cell_unit save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2 sync preloader write leveling sync preloader cbt_mr12 sync preloader cbt_clk_dly sync preloader cbt_cmd_dly sync preloader cbt_cs sync preloader cbt_ca_perbit_delay sync preloader clk_delay sync preloader dqs_delay sync preloader u1Gating2T_Save sync preloader u1Gating05T_Save sync preloader u1Gatingfine_tune_Save sync preloader u1Gatingucpass_count_Save sync preloader u1TxWindowPerbitVref_Save sync preloader u1TxCenter_min_Save sync preloader u1TxCenter_max_Save sync preloader u1Txwin_center_Save sync preloader u1Txfirst_pass_Save sync preloader u1Txlast_pass_Save sync preloader u1RxDatlat_Save sync preloader u1RxWinPerbitVref_Save sync preloader u1RxWinPerbitDQ_firsbypass_Save sync preloader u1RxWinPerbitDQ_lastbypass_Save sync preloader delay_cell_unit just_for_test_dump_coreboot_params dump all params dump source = 0x0 dump params frequency:1600 dump params rank number:2 dump params write leveling write leveling[0][0][0] = 0x20 write leveling[0][0][1] = 0x18 write leveling[0][1][0] = 0x1f write leveling[0][1][1] = 0x16 write leveling[1][0][0] = 0x24 write leveling[1][0][1] = 0x22 write leveling[1][1][0] = 0x23 write leveling[1][1][1] = 0x1c dump params cbt_cs cbt_cs[0][0] = 0x7 cbt_cs[0][1] = 0x7 cbt_cs[1][0] = 0x9 cbt_cs[1][1] = 0x9 dump params cbt_mr12 cbt_mr12[0][0] = 0x1e cbt_mr12[0][1] = 0x20 cbt_mr12[1][0] = 0x1c cbt_mr12[1][1] = 0x1c dump params tx window tx_center_min[0][0][0] = 986 tx_center_max[0][0][0] = 991 tx_center_min[0][0][1] = 978 tx_center_max[0][0][1] = 986 tx_center_min[0][1][0] = 984 tx_center_max[0][1][0] = 990 tx_center_min[0][1][1] = 976 tx_center_max[0][1][1] = 983 tx_center_min[1][0][0] = 992 tx_center_max[1][0][0] = 997 tx_center_min[1][0][1] = 988 tx_center_max[1][0][1] = 995 tx_center_min[1][1][0] = 990 tx_center_max[1][1][0] = 995 tx_center_min[1][1][1] = 981 tx_center_max[1][1][1] = 987 dump params tx window tx_win_center[0][0][0] = 991 tx_first_pass[0][0][0] = 979 tx_last_pass[0][0][0] = 1004 tx_win_center[0][0][1] = 990 tx_first_pass[0][0][1] = 978 tx_last_pass[0][0][1] = 1002 tx_win_center[0][0][2] = 991 tx_first_pass[0][0][2] = 979 tx_last_pass[0][0][2] = 1004 tx_win_center[0][0][3] = 986 tx_first_pass[0][0][3] = 974 tx_last_pass[0][0][3] = 998 tx_win_center[0][0][4] = 989 tx_first_pass[0][0][4] = 977 tx_last_pass[0][0][4] = 1001 tx_win_center[0][0][5] = 987 tx_first_pass[0][0][5] = 976 tx_last_pass[0][0][5] = 999 tx_win_center[0][0][6] = 988 tx_first_pass[0][0][6] = 976 tx_last_pass[0][0][6] = 1000 tx_win_center[0][0][7] = 989 tx_first_pass[0][0][7] = 977 tx_last_pass[0][0][7] = 1001 tx_win_center[0][0][8] = 978 tx_first_pass[0][0][8] = 967 tx_last_pass[0][0][8] = 990 tx_win_center[0][0][9] = 979 tx_first_pass[0][0][9] = 968 tx_last_pass[0][0][9] = 991 tx_win_center[0][0][10] = 986 tx_first_pass[0][0][10] = 974 tx_last_pass[0][0][10] = 998 tx_win_center[0][0][11] = 979 tx_first_pass[0][0][11] = 968 tx_last_pass[0][0][11] = 991 tx_win_center[0][0][12] = 980 tx_first_pass[0][0][12] = 968 tx_last_pass[0][0][12] = 993 tx_win_center[0][0][13] = 981 tx_first_pass[0][0][13] = 969 tx_last_pass[0][0][13] = 993 tx_win_center[0][0][14] = 982 tx_first_pass[0][0][14] = 969 tx_last_pass[0][0][14] = 996 tx_win_center[0][0][15] = 984 tx_first_pass[0][0][15] = 971 tx_last_pass[0][0][15] = 997 tx_win_center[0][1][0] = 990 tx_first_pass[0][1][0] = 978 tx_last_pass[0][1][0] = 1002 tx_win_center[0][1][1] = 989 tx_first_pass[0][1][1] = 977 tx_last_pass[0][1][1] = 1001 tx_win_center[0][1][2] = 990 tx_first_pass[0][1][2] = 978 tx_last_pass[0][1][2] = 1002 tx_win_center[0][1][3] = 984 tx_first_pass[0][1][3] = 973 tx_last_pass[0][1][3] = 996 tx_win_center[0][1][4] = 989 tx_first_pass[0][1][4] = 977 tx_last_pass[0][1][4] = 1001 tx_win_center[0][1][5] = 986 tx_first_pass[0][1][5] = 975 tx_last_pass[0][1][5] = 998 tx_win_center[0][1][6] = 987 tx_first_pass[0][1][6] = 975 tx_last_pass[0][1][6] = 999 tx_win_center[0][1][7] = 988 tx_first_pass[0][1][7] = 976 tx_last_pass[0][1][7] = 1001 tx_win_center[0][1][8] = 976 tx_first_pass[0][1][8] = 965 tx_last_pass[0][1][8] = 988 tx_win_center[0][1][9] = 978 tx_first_pass[0][1][9] = 967 tx_last_pass[0][1][9] = 989 tx_win_center[0][1][10] = 983 tx_first_pass[0][1][10] = 971 tx_last_pass[0][1][10] = 996 tx_win_center[0][1][11] = 977 tx_first_pass[0][1][11] = 966 tx_last_pass[0][1][11] = 989 tx_win_center[0][1][12] = 978 tx_first_pass[0][1][12] = 967 tx_last_pass[0][1][12] = 990 tx_win_center[0][1][13] = 978 tx_first_pass[0][1][13] = 967 tx_last_pass[0][1][13] = 989 tx_win_center[0][1][14] = 979 tx_first_pass[0][1][14] = 967 tx_last_pass[0][1][14] = 991 tx_win_center[0][1][15] = 981 tx_first_pass[0][1][15] = 970 tx_last_pass[0][1][15] = 993 tx_win_center[1][0][0] = 997 tx_first_pass[1][0][0] = 985 tx_last_pass[1][0][0] = 1010 tx_win_center[1][0][1] = 996 tx_first_pass[1][0][1] = 984 tx_last_pass[1][0][1] = 1008 tx_win_center[1][0][2] = 994 tx_first_pass[1][0][2] = 982 tx_last_pass[1][0][2] = 1006 tx_win_center[1][0][3] = 992 tx_first_pass[1][0][3] = 979 tx_last_pass[1][0][3] = 1005 tx_win_center[1][0][4] = 996 tx_first_pass[1][0][4] = 984 tx_last_pass[1][0][4] = 1008 tx_win_center[1][0][5] = 996 tx_first_pass[1][0][5] = 984 tx_last_pass[1][0][5] = 1009 tx_win_center[1][0][6] = 996 tx_first_pass[1][0][6] = 984 tx_last_pass[1][0][6] = 1009 tx_win_center[1][0][7] = 996 tx_first_pass[1][0][7] = 984 tx_last_pass[1][0][7] = 1008 tx_win_center[1][0][8] = 991 tx_first_pass[1][0][8] = 980 tx_last_pass[1][0][8] = 1002 tx_win_center[1][0][9] = 990 tx_first_pass[1][0][9] = 979 tx_last_pass[1][0][9] = 1002 tx_win_center[1][0][10] = 994 tx_first_pass[1][0][10] = 983 tx_last_pass[1][0][10] = 1005 tx_win_center[1][0][11] = 995 tx_first_pass[1][0][11] = 984 tx_last_pass[1][0][11] = 1006 tx_win_center[1][0][12] = 995 tx_first_pass[1][0][12] = 984 tx_last_pass[1][0][12] = 1006 tx_win_center[1][0][13] = 995 tx_first_pass[1][0][13] = 985 tx_last_pass[1][0][13] = 1006 tx_win_center[1][0][14] = 994 tx_first_pass[1][0][14] = 983 tx_last_pass[1][0][14] = 1005 tx_win_center[1][0][15] = 988 tx_first_pass[1][0][15] = 977 tx_last_pass[1][0][15] = 1000 tx_win_center[1][1][0] = 995 tx_first_pass[1][1][0] = 983 tx_last_pass[1][1][0] = 1008 tx_win_center[1][1][1] = 994 tx_first_pass[1][1][1] = 982 tx_last_pass[1][1][1] = 1006 tx_win_center[1][1][2] = 992 tx_first_pass[1][1][2] = 979 tx_last_pass[1][1][2] = 1005 tx_win_center[1][1][3] = 990 tx_first_pass[1][1][3] = 978 tx_last_pass[1][1][3] = 1003 tx_win_center[1][1][4] = 994 tx_first_pass[1][1][4] = 982 tx_last_pass[1][1][4] = 1007 tx_win_center[1][1][5] = 995 tx_first_pass[1][1][5] = 983 tx_last_pass[1][1][5] = 1008 tx_win_center[1][1][6] = 994 tx_first_pass[1][1][6] = 982 tx_last_pass[1][1][6] = 1007 tx_win_center[1][1][7] = 994 tx_first_pass[1][1][7] = 982 tx_last_pass[1][1][7] = 1007 tx_win_center[1][1][8] = 984 tx_first_pass[1][1][8] = 972 tx_last_pass[1][1][8] = 996 tx_win_center[1][1][9] = 982 tx_first_pass[1][1][9] = 971 tx_last_pass[1][1][9] = 994 tx_win_center[1][1][10] = 986 tx_first_pass[1][1][10] = 973 tx_last_pass[1][1][10] = 1000 tx_win_center[1][1][11] = 987 tx_first_pass[1][1][11] = 975 tx_last_pass[1][1][11] = 999 tx_win_center[1][1][12] = 986 tx_first_pass[1][1][12] = 974 tx_last_pass[1][1][12] = 999 tx_win_center[1][1][13] = 987 tx_first_pass[1][1][13] = 975 tx_last_pass[1][1][13] = 1000 tx_win_center[1][1][14] = 986 tx_first_pass[1][1][14] = 974 tx_last_pass[1][1][14] = 999 tx_win_center[1][1][15] = 981 tx_first_pass[1][1][15] = 969 tx_last_pass[1][1][15] = 993 dump params rx window rx_firspass[0][0][0] = 5 rx_lastpass[0][0][0] = 39 rx_firspass[0][0][1] = 5 rx_lastpass[0][0][1] = 36 rx_firspass[0][0][2] = 7 rx_lastpass[0][0][2] = 37 rx_firspass[0][0][3] = -1 rx_lastpass[0][0][3] = 30 rx_firspass[0][0][4] = 5 rx_lastpass[0][0][4] = 36 rx_firspass[0][0][5] = 1 rx_lastpass[0][0][5] = 33 rx_firspass[0][0][6] = 4 rx_lastpass[0][0][6] = 33 rx_firspass[0][0][7] = 7 rx_lastpass[0][0][7] = 36 rx_firspass[0][0][8] = 0 rx_lastpass[0][0][8] = 31 rx_firspass[0][0][9] = 1 rx_lastpass[0][0][9] = 32 rx_firspass[0][0][10] = 9 rx_lastpass[0][0][10] = 39 rx_firspass[0][0][11] = 1 rx_lastpass[0][0][11] = 30 rx_firspass[0][0][12] = 1 rx_lastpass[0][0][12] = 33 rx_firspass[0][0][13] = 2 rx_lastpass[0][0][13] = 33 rx_firspass[0][0][14] = 3 rx_lastpass[0][0][14] = 36 rx_firspass[0][0][15] = 7 rx_lastpass[0][0][15] = 37 rx_firspass[0][1][0] = 4 rx_lastpass[0][1][0] = 38 rx_firspass[0][1][1] = 3 rx_lastpass[0][1][1] = 39 rx_firspass[0][1][2] = 5 rx_lastpass[0][1][2] = 40 rx_firspass[0][1][3] = -3 rx_lastpass[0][1][3] = 31 rx_firspass[0][1][4] = 5 rx_lastpass[0][1][4] = 38 rx_firspass[0][1][5] = 0 rx_lastpass[0][1][5] = 32 rx_firspass[0][1][6] = 1 rx_lastpass[0][1][6] = 35 rx_firspass[0][1][7] = 4 rx_lastpass[0][1][7] = 37 rx_firspass[0][1][8] = 0 rx_lastpass[0][1][8] = 33 rx_firspass[0][1][9] = 2 rx_lastpass[0][1][9] = 35 rx_firspass[0][1][10] = 9 rx_lastpass[0][1][10] = 42 rx_firspass[0][1][11] = 0 rx_lastpass[0][1][11] = 33 rx_firspass[0][1][12] = 3 rx_lastpass[0][1][12] = 36 rx_firspass[0][1][13] = 3 rx_lastpass[0][1][13] = 36 rx_firspass[0][1][14] = 5 rx_lastpass[0][1][14] = 37 rx_firspass[0][1][15] = 6 rx_lastpass[0][1][15] = 40 rx_firspass[1][0][0] = 4 rx_lastpass[1][0][0] = 39 rx_firspass[1][0][1] = 3 rx_lastpass[1][0][1] = 36 rx_firspass[1][0][2] = 4 rx_lastpass[1][0][2] = 36 rx_firspass[1][0][3] = -1 rx_lastpass[1][0][3] = 34 rx_firspass[1][0][4] = 5 rx_lastpass[1][0][4] = 36 rx_firspass[1][0][5] = 6 rx_lastpass[1][0][5] = 38 rx_firspass[1][0][6] = 9 rx_lastpass[1][0][6] = 39 rx_firspass[1][0][7] = 5 rx_lastpass[1][0][7] = 37 rx_firspass[1][0][8] = 0 rx_lastpass[1][0][8] = 33 rx_firspass[1][0][9] = 2 rx_lastpass[1][0][9] = 32 rx_firspass[1][0][10] = 5 rx_lastpass[1][0][10] = 36 rx_firspass[1][0][11] = 7 rx_lastpass[1][0][11] = 36 rx_firspass[1][0][12] = 5 rx_lastpass[1][0][12] = 37 rx_firspass[1][0][13] = 7 rx_lastpass[1][0][13] = 36 rx_firspass[1][0][14] = 7 rx_lastpass[1][0][14] = 37 rx_firspass[1][0][15] = 0 rx_lastpass[1][0][15] = 29 rx_firspass[1][1][0] = 5 rx_lastpass[1][1][0] = 38 rx_firspass[1][1][1] = 2 rx_lastpass[1][1][1] = 37 rx_firspass[1][1][2] = 2 rx_lastpass[1][1][2] = 35 rx_firspass[1][1][3] = 0 rx_lastpass[1][1][3] = 32 rx_firspass[1][1][4] = 3 rx_lastpass[1][1][4] = 38 rx_firspass[1][1][5] = 5 rx_lastpass[1][1][5] = 40 rx_firspass[1][1][6] = 7 rx_lastpass[1][1][6] = 41 rx_firspass[1][1][7] = 4 rx_lastpass[1][1][7] = 38 rx_firspass[1][1][8] = 1 rx_lastpass[1][1][8] = 34 rx_firspass[1][1][9] = 1 rx_lastpass[1][1][9] = 34 rx_firspass[1][1][10] = 4 rx_lastpass[1][1][10] = 37 rx_firspass[1][1][11] = 5 rx_lastpass[1][1][11] = 38 rx_firspass[1][1][12] = 7 rx_lastpass[1][1][12] = 38 rx_firspass[1][1][13] = 6 rx_lastpass[1][1][13] = 38 rx_firspass[1][1][14] = 6 rx_lastpass[1][1][14] = 38 rx_firspass[1][1][15] = -2 rx_lastpass[1][1][15] = 32 dump params clk_delay clk_delay[0] = 1 clk_delay[1] = 0 dump params dqs_delay dqs_delay[0][0] = 0 dqs_delay[0][1] = 0 dqs_delay[1][0] = -1 dqs_delay[1][1] = 0 dump params delay_cell_unit = 744 dump source = 0x0 dump params frequency:1200 dump params rank number:2 dump params write leveling write leveling[0][0][0] = 0x0 write leveling[0][0][1] = 0x0 write leveling[0][1][0] = 0x0 write leveling[0][1][1] = 0x0 write leveling[1][0][0] = 0x0 write leveling[1][0][1] = 0x0 write leveling[1][1][0] = 0x0 write leveling[1][1][1] = 0x0 dump params cbt_cs cbt_cs[0][0] = 0x0 cbt_cs[0][1] = 0x0 cbt_cs[1][0] = 0x0 cbt_cs[1][1] = 0x0 dump params cbt_mr12 cbt_mr12[0][0] = 0x0 cbt_mr12[0][1] = 0x0 cbt_mr12[1][0] = 0x0 cbt_mr12[1][1] = 0x0 dump params tx window tx_center_min[0][0][0] = 0 tx_center_max[0][0][0] = 0 tx_center_min[0][0][1] = 0 tx_center_max[0][0][1] = 0 tx_center_min[0][1][0] = 0 tx_center_max[0][1][0] = 0 tx_center_min[0][1][1] = 0 tx_center_max[0][1][1] = 0 tx_center_min[1][0][0] = 0 tx_center_max[1][0][0] = 0 tx_center_min[1][0][1] = 0 tx_center_max[1][0][1] = 0 tx_center_min[1][1][0] = 0 tx_center_max[1][1][0] = 0 tx_center_min[1][1][1] = 0 tx_center_max[1][1][1] = 0 dump params tx window tx_win_center[0][0][0] = 0 tx_first_pass[0][0][0] = 0 tx_last_pass[0][0][0] = 0 tx_win_center[0][0][1] = 0 tx_first_pass[0][0][1] = 0 tx_last_pass[0][0][1] = 0 tx_win_center[0][0][2] = 0 tx_first_pass[0][0][2] = 0 tx_last_pass[0][0][2] = 0 tx_win_center[0][0][3] = 0 tx_first_pass[0][0][3] = 0 tx_last_pass[0][0][3] = 0 tx_win_center[0][0][4] = 0 tx_first_pass[0][0][4] = 0 tx_last_pass[0][0][4] = 0 tx_win_center[0][0][5] = 0 tx_first_pass[0][0][5] = 0 tx_last_pass[0][0][5] = 0 tx_win_center[0][0][6] = 0 tx_first_pass[0][0][6] = 0 tx_last_pass[0][0][6] = 0 tx_win_center[0][0][7] = 0 tx_first_pass[0][0][7] = 0 tx_last_pass[0][0][7] = 0 tx_win_center[0][0][8] = 0 tx_first_pass[0][0][8] = 0 tx_last_pass[0][0][8] = 0 tx_win_center[0][0][9] = 0 tx_first_pass[0][0][9] = 0 tx_last_pass[0][0][9] = 0 tx_win_center[0][0][10] = 0 tx_first_pass[0][0][10] = 0 tx_last_pass[0][0][10] = 0 tx_win_center[0][0][11] = 0 tx_first_pass[0][0][11] = 0 tx_last_pass[0][0][11] = 0 tx_win_center[0][0][12] = 0 tx_first_pass[0][0][12] = 0 tx_last_pass[0][0][12] = 0 tx_win_center[0][0][13] = 0 tx_first_pass[0][0][13] = 0 tx_last_pass[0][0][13] = 0 tx_win_center[0][0][14] = 0 tx_first_pass[0][0][14] = 0 tx_last_pass[0][0][14] = 0 tx_win_center[0][0][15] = 0 tx_first_pass[0][0][15] = 0 tx_last_pass[0][0][15] = 0 tx_win_center[0][1][0] = 0 tx_first_pass[0][1][0] = 0 tx_last_pass[0][1][0] = 0 tx_win_center[0][1][1] = 0 tx_first_pass[0][1][1] = 0 tx_last_pass[0][1][1] = 0 tx_win_center[0][1][2] = 0 tx_first_pass[0][1][2] = 0 tx_last_pass[0][1][2] = 0 tx_win_center[0][1][3] = 0 tx_first_pass[0][1][3] = 0 tx_last_pass[0][1][3] = 0 tx_win_center[0][1][4] = 0 tx_first_pass[0][1][4] = 0 tx_last_pass[0][1][4] = 0 tx_win_center[0][1][5] = 0 tx_first_pass[0][1][5] = 0 tx_last_pass[0][1][5] = 0 tx_win_center[0][1][6] = 0 tx_first_pass[0][1][6] = 0 tx_last_pass[0][1][6] = 0 tx_win_center[0][1][7] = 0 tx_first_pass[0][1][7] = 0 tx_last_pass[0][1][7] = 0 tx_win_center[0][1][8] = 0 tx_first_pass[0][1][8] = 0 tx_last_pass[0][1][8] = 0 tx_win_center[0][1][9] = 0 tx_first_pass[0][1][9] = 0 tx_last_pass[0][1][9] = 0 tx_win_center[0][1][10] = 0 tx_first_pass[0][1][10] = 0 tx_last_pass[0][1][10] = 0 tx_win_center[0][1][11] = 0 tx_first_pass[0][1][11] = 0 tx_last_pass[0][1][11] = 0 tx_win_center[0][1][12] = 0 tx_first_pass[0][1][12] = 0 tx_last_pass[0][1][12] = 0 tx_win_center[0][1][13] = 0 tx_first_pass[0][1][13] = 0 tx_last_pass[0][1][13] = 0 tx_win_center[0][1][14] = 0 tx_first_pass[0][1][14] = 0 tx_last_pass[0][1][14] = 0 tx_win_center[0][1][15] = 0 tx_first_pass[0][1][15] = 0 tx_last_pass[0][1][15] = 0 tx_win_center[1][0][0] = 0 tx_first_pass[1][0][0] = 0 tx_last_pass[1][0][0] = 0 tx_win_center[1][0][1] = 0 tx_first_pass[1][0][1] = 0 tx_last_pass[1][0][1] = 0 tx_win_center[1][0][2] = 0 tx_first_pass[1][0][2] = 0 tx_last_pass[1][0][2] = 0 tx_win_center[1][0][3] = 0 tx_first_pass[1][0][3] = 0 tx_last_pass[1][0][3] = 0 tx_win_center[1][0][4] = 0 tx_first_pass[1][0][4] = 0 tx_last_pass[1][0][4] = 0 tx_win_center[1][0][5] = 0 tx_first_pass[1][0][5] = 0 tx_last_pass[1][0][5] = 0 tx_win_center[1][0][6] = 0 tx_first_pass[1][0][6] = 0 tx_last_pass[1][0][6] = 0 tx_win_center[1][0][7] = 0 tx_first_pass[1][0][7] = 0 tx_last_pass[1][0][7] = 0 tx_win_center[1][0][8] = 0 tx_first_pass[1][0][8] = 0 tx_last_pass[1][0][8] = 0 tx_win_center[1][0][9] = 0 tx_first_pass[1][0][9] = 0 tx_last_pass[1][0][9] = 0 tx_win_center[1][0][10] = 0 tx_first_pass[1][0][10] = 0 tx_last_pass[1][0][10] = 0 tx_win_center[1][0][11] = 0 tx_first_pass[1][0][11] = 0 tx_last_pass[1][0][11] = 0 tx_win_center[1][0][12] = 0 tx_first_pass[1][0][12] = 0 tx_last_pass[1][0][12] = 0 tx_win_center[1][0][13] = 0 tx_first_pass[1][0][13] = 0 tx_last_pass[1][0][13] = 0 tx_win_center[1][0][14] = 0 tx_first_pass[1][0][14] = 0 tx_last_pass[1][0][14] = 0 tx_win_center[1][0][15] = 0 tx_first_pass[1][0][15] = 0 tx_last_pass[1][0][15] = 0 tx_win_center[1][1][0] = 0 tx_first_pass[1][1][0] = 0 tx_last_pass[1][1][0] = 0 tx_win_center[1][1][1] = 0 tx_first_pass[1][1][1] = 0 tx_last_pass[1][1][1] = 0 tx_win_center[1][1][2] = 0 tx_first_pass[1][1][2] = 0 tx_last_pass[1][1][2] = 0 tx_win_center[1][1][3] = 0 tx_first_pass[1][1][3] = 0 tx_last_pass[1][1][3] = 0 tx_win_center[1][1][4] = 0 tx_first_pass[1][1][4] = 0 tx_last_pass[1][1][4] = 0 tx_win_center[1][1][5] = 0 tx_first_pass[1][1][5] = 0 tx_last_pass[1][1][5] = 0 tx_win_center[1][1][6] = 0 tx_first_pass[1][1][6] = 0 tx_last_pass[1][1][6] = 0 tx_win_center[1][1][7] = 0 tx_first_pass[1][1][7] = 0 tx_last_pass[1][1][7] = 0 tx_win_center[1][1][8] = 0 tx_first_pass[1][1][8] = 0 tx_last_pass[1][1][8] = 0 tx_win_center[1][1][9] = 0 tx_first_pass[1][1][9] = 0 tx_last_pass[1][1][9] = 0 tx_win_center[1][1][10] = 0 tx_first_pass[1][1][10] = 0 tx_last_pass[1][1][10] = 0 tx_win_center[1][1][11] = 0 tx_first_pass[1][1][11] = 0 tx_last_pass[1][1][11] = 0 tx_win_center[1][1][12] = 0 tx_first_pass[1][1][12] = 0 tx_last_pass[1][1][12] = 0 tx_win_center[1][1][13] = 0 tx_first_pass[1][1][13] = 0 tx_last_pass[1][1][13] = 0 tx_win_center[1][1][14] = 0 tx_first_pass[1][1][14] = 0 tx_last_pass[1][1][14] = 0 tx_win_center[1][1][15] = 0 tx_first_pass[1][1][15] = 0 tx_last_pass[1][1][15] = 0 dump params rx window rx_firspass[0][0][0] = 0 rx_lastpass[0][0][0] = 0 rx_firspass[0][0][1] = 0 rx_lastpass[0][0][1] = 0 rx_firspass[0][0][2] = 0 rx_lastpass[0][0][2] = 0 rx_firspass[0][0][3] = 0 rx_lastpass[0][0][3] = 0 rx_firspass[0][0][4] = 0 rx_lastpass[0][0][4] = 0 rx_firspass[0][0][5] = 0 rx_lastpass[0][0][5] = 0 rx_firspass[0][0][6] = 0 rx_lastpass[0][0][6] = 0 rx_firspass[0][0][7] = 0 rx_lastpass[0][0][7] = 0 rx_firspass[0][0][8] = 0 rx_lastpass[0][0][8] = 0 rx_firspass[0][0][9] = 0 rx_lastpass[0][0][9] = 0 rx_firspass[0][0][10] = 0 rx_lastpass[0][0][10] = 0 rx_firspass[0][0][11] = 0 rx_lastpass[0][0][11] = 0 rx_firspass[0][0][12] = 0 rx_lastpass[0][0][12] = 0 rx_firspass[0][0][13] = 0 rx_lastpass[0][0][13] = 0 rx_firspass[0][0][14] = 0 rx_lastpass[0][0][14] = 0 rx_firspass[0][0][15] = 0 rx_lastpass[0][0][15] = 0 rx_firspass[0][1][0] = 0 rx_lastpass[0][1][0] = 0 rx_firspass[0][1][1] = 0 rx_lastpass[0][1][1] = 0 rx_firspass[0][1][2] = 0 rx_lastpass[0][1][2] = 0 rx_firspass[0][1][3] = 0 rx_lastpass[0][1][3] = 0 rx_firspass[0][1][4] = 0 rx_lastpass[0][1][4] = 0 rx_firspass[0][1][5] = 0 rx_lastpass[0][1][5] = 0 rx_firspass[0][1][6] = 0 rx_lastpass[0][1][6] = 0 rx_firspass[0][1][7] = 0 rx_lastpass[0][1][7] = 0 rx_firspass[0][1][8] = 0 rx_lastpass[0][1][8] = 0 rx_firspass[0][1][9] = 0 rx_lastpass[0][1][9] = 0 rx_firspass[0][1][10] = 0 rx_lastpass[0][1][10] = 0 rx_firspass[0][1][11] = 0 rx_lastpass[0][1][11] = 0 rx_firspass[0][1][12] = 0 rx_lastpass[0][1][12] = 0 rx_firspass[0][1][13] = 0 rx_lastpass[0][1][13] = 0 rx_firspass[0][1][14] = 0 rx_lastpass[0][1][14] = 0 rx_firspass[0][1][15] = 0 rx_lastpass[0][1][15] = 0 rx_firspass[1][0][0] = 0 rx_lastpass[1][0][0] = 0 rx_firspass[1][0][1] = 0 rx_lastpass[1][0][1] = 0 rx_firspass[1][0][2] = 0 rx_lastpass[1][0][2] = 0 rx_firspass[1][0][3] = 0 rx_lastpass[1][0][3] = 0 rx_firspass[1][0][4] = 0 rx_lastpass[1][0][4] = 0 rx_firspass[1][0][5] = 0 rx_lastpass[1][0][5] = 0 rx_firspass[1][0][6] = 0 rx_lastpass[1][0][6] = 0 rx_firspass[1][0][7] = 0 rx_lastpass[1][0][7] = 0 rx_firspass[1][0][8] = 0 rx_lastpass[1][0][8] = 0 rx_firspass[1][0][9] = 0 rx_lastpass[1][0][9] = 0 rx_firspass[1][0][10] = 0 rx_lastpass[1][0][10] = 0 rx_firspass[1][0][11] = 0 rx_lastpass[1][0][11] = 0 rx_firspass[1][0][12] = 0 rx_lastpass[1][0][12] = 0 rx_firspass[1][0][13] = 0 rx_lastpass[1][0][13] = 0 rx_firspass[1][0][14] = 0 rx_lastpass[1][0][14] = 0 rx_firspass[1][0][15] = 0 rx_lastpass[1][0][15] = 0 rx_firspass[1][1][0] = 0 rx_lastpass[1][1][0] = 0 rx_firspass[1][1][1] = 0 rx_lastpass[1][1][1] = 0 rx_firspass[1][1][2] = 0 rx_lastpass[1][1][2] = 0 rx_firspass[1][1][3] = 0 rx_lastpass[1][1][3] = 0 rx_firspass[1][1][4] = 0 rx_lastpass[1][1][4] = 0 rx_firspass[1][1][5] = 0 rx_lastpass[1][1][5] = 0 rx_firspass[1][1][6] = 0 rx_lastpass[1][1][6] = 0 rx_firspass[1][1][7] = 0 rx_lastpass[1][1][7] = 0 rx_firspass[1][1][8] = 0 rx_lastpass[1][1][8] = 0 rx_firspass[1][1][9] = 0 rx_lastpass[1][1][9] = 0 rx_firspass[1][1][10] = 0 rx_lastpass[1][1][10] = 0 rx_firspass[1][1][11] = 0 rx_lastpass[1][1][11] = 0 rx_firspass[1][1][12] = 0 rx_lastpass[1][1][12] = 0 rx_firspass[1][1][13] = 0 rx_lastpass[1][1][13] = 0 rx_firspass[1][1][14] = 0 rx_lastpass[1][1][14] = 0 rx_firspass[1][1][15] = 0 rx_lastpass[1][1][15] = 0 dump params clk_delay clk_delay[0] = 0 clk_delay[1] = 0 dump params dqs_delay dqs_delay[0][0] = 0 dqs_delay[0][1] = 0 dqs_delay[1][0] = 0 dqs_delay[1][1] = 0 dump params delay_cell_unit = 744 dump source = 0x0 dump params frequency:800 dump params rank number:2 dump params write leveling write leveling[0][0][0] = 0x0 write leveling[0][0][1] = 0x0 write leveling[0][1][0] = 0x0 write leveling[0][1][1] = 0x0 write leveling[1][0][0] = 0x0 write leveling[1][0][1] = 0x0 write leveling[1][1][0] = 0x0 write leveling[1][1][1] = 0x0 dump params cbt_cs cbt_cs[0][0] = 0x0 cbt_cs[0][1] = 0x0 cbt_cs[1][0] = 0x0 cbt_cs[1][1] = 0x0 dump params cbt_mr12 cbt_mr12[0][0] = 0x0 cbt_mr12[0][1] = 0x0 cbt_mr12[1][0] = 0x0 cbt_mr12[1][1] = 0x0 dump params tx window tx_center_min[0][0][0] = 0 tx_center_max[0][0][0] = 0 tx_center_min[0][0][1] = 0 tx_center_max[0][0][1] = 0 tx_center_min[0][1][0] = 0 tx_center_max[0][1][0] = 0 tx_center_min[0][1][1] = 0 tx_center_max[0][1][1] = 0 tx_center_min[1][0][0] = 0 tx_center_max[1][0][0] = 0 tx_center_min[1][0][1] = 0 tx_center_max[1][0][1] = 0 tx_center_min[1][1][0] = 0 tx_center_max[1][1][0] = 0 tx_center_min[1][1][1] = 0 tx_center_max[1][1][1] = 0 dump params tx window tx_win_center[0][0][0] = 0 tx_first_pass[0][0][0] = 0 tx_last_pass[0][0][0] = 0 tx_win_center[0][0][1] = 0 tx_first_pass[0][0][1] = 0 tx_last_pass[0][0][1] = 0 tx_win_center[0][0][2] = 0 tx_first_pass[0][0][2] = 0 tx_last_pass[0][0][2] = 0 tx_win_center[0][0][3] = 0 tx_first_pass[0][0][3] = 0 tx_last_pass[0][0][3] = 0 tx_win_center[0][0][4] = 0 tx_first_pass[0][0][4] = 0 tx_last_pass[0][0][4] = 0 tx_win_center[0][0][5] = 0 tx_first_pass[0][0][5] = 0 tx_last_pass[0][0][5] = 0 tx_win_center[0][0][6] = 0 tx_first_pass[0][0][6] = 0 tx_last_pass[0][0][6] = 0 tx_win_center[0][0][7] = 0 tx_first_pass[0][0][7] = 0 tx_last_pass[0][0][7] = 0 tx_win_center[0][0][8] = 0 tx_first_pass[0][0][8] = 0 tx_last_pass[0][0][8] = 0 tx_win_center[0][0][9] = 0 tx_first_pass[0][0][9] = 0 tx_last_pass[0][0][9] = 0 tx_win_center[0][0][10] = 0 tx_first_pass[0][0][10] = 0 tx_last_pass[0][0][10] = 0 tx_win_center[0][0][11] = 0 tx_first_pass[0][0][11] = 0 tx_last_pass[0][0][11] = 0 tx_win_center[0][0][12] = 0 tx_first_pass[0][0][12] = 0 tx_last_pass[0][0][12] = 0 tx_win_center[0][0][13] = 0 tx_first_pass[0][0][13] = 0 tx_last_pass[0][0][13] = 0 tx_win_center[0][0][14] = 0 tx_first_pass[0][0][14] = 0 tx_last_pass[0][0][14] = 0 tx_win_center[0][0][15] = 0 tx_first_pass[0][0][15] = 0 tx_last_pass[0][0][15] = 0 tx_win_center[0][1][0] = 0 tx_first_pass[0][1][0] = 0 tx_last_pass[0][1][0] = 0 tx_win_center[0][1][1] = 0 tx_first_pass[0][1][1] = 0 tx_last_pass[0][1][1] = 0 tx_win_center[0][1][2] = 0 tx_first_pass[0][1][2] = 0 tx_last_pass[0][1][2] = 0 tx_win_center[0][1][3] = 0 tx_first_pass[0][1][3] = 0 tx_last_pass[0][1][3] = 0 tx_win_center[0][1][4] = 0 tx_first_pass[0][1][4] = 0 tx_last_pass[0][1][4] = 0 tx_win_center[0][1][5] = 0 tx_first_pass[0][1][5] = 0 tx_last_pass[0][1][5] = 0 tx_win_center[0][1][6] = 0 tx_first_pass[0][1][6] = 0 tx_last_pass[0][1][6] = 0 tx_win_center[0][1][7] = 0 tx_first_pass[0][1][7] = 0 tx_last_pass[0][1][7] = 0 tx_win_center[0][1][8] = 0 tx_first_pass[0][1][8] = 0 tx_last_pass[0][1][8] = 0 tx_win_center[0][1][9] = 0 tx_first_pass[0][1][9] = 0 tx_last_pass[0][1][9] = 0 tx_win_center[0][1][10] = 0 tx_first_pass[0][1][10] = 0 tx_last_pass[0][1][10] = 0 tx_win_center[0][1][11] = 0 tx_first_pass[0][1][11] = 0 tx_last_pass[0][1][11] = 0 tx_win_center[0][1][12] = 0 tx_first_pass[0][1][12] = 0 tx_last_pass[0][1][12] = 0 tx_win_center[0][1][13] = 0 tx_first_pass[0][1][13] = 0 tx_last_pass[0][1][13] = 0 tx_win_center[0][1][14] = 0 tx_first_pass[0][1][14] = 0 tx_last_pass[0][1][14] = 0 tx_win_center[0][1][15] = 0 tx_first_pass[0][1][15] = 0 tx_last_pass[0][1][15] = 0 tx_win_center[1][0][0] = 0 tx_first_pass[1][0][0] = 0 tx_last_pass[1][0][0] = 0 tx_win_center[1][0][1] = 0 tx_first_pass[1][0][1] = 0 tx_last_pass[1][0][1] = 0 tx_win_center[1][0][2] = 0 tx_first_pass[1][0][2] = 0 tx_last_pass[1][0][2] = 0 tx_win_center[1][0][3] = 0 tx_first_pass[1][0][3] = 0 tx_last_pass[1][0][3] = 0 tx_win_center[1][0][4] = 0 tx_first_pass[1][0][4] = 0 tx_last_pass[1][0][4] = 0 tx_win_center[1][0][5] = 0 tx_first_pass[1][0][5] = 0 tx_last_pass[1][0][5] = 0 tx_win_center[1][0][6] = 0 tx_first_pass[1][0][6] = 0 tx_last_pass[1][0][6] = 0 tx_win_center[1][0][7] = 0 tx_first_pass[1][0][7] = 0 tx_last_pass[1][0][7] = 0 tx_win_center[1][0][8] = 0 tx_first_pass[1][0][8] = 0 tx_last_pass[1][0][8] = 0 tx_win_center[1][0][9] = 0 tx_first_pass[1][0][9] = 0 tx_last_pass[1][0][9] = 0 tx_win_center[1][0][10] = 0 tx_first_pass[1][0][10] = 0 tx_last_pass[1][0][10] = 0 tx_win_center[1][0][11] = 0 tx_first_pass[1][0][11] = 0 tx_last_pass[1][0][11] = 0 tx_win_center[1][0][12] = 0 tx_first_pass[1][0][12] = 0 tx_last_pass[1][0][12] = 0 tx_win_center[1][0][13] = 0 tx_first_pass[1][0][13] = 0 tx_last_pass[1][0][13] = 0 tx_win_center[1][0][14] = 0 tx_first_pass[1][0][14] = 0 tx_last_pass[1][0][14] = 0 tx_win_center[1][0][15] = 0 tx_first_pass[1][0][15] = 0 tx_last_pass[1][0][15] = 0 tx_win_center[1][1][0] = 0 tx_first_pass[1][1][0] = 0 tx_last_pass[1][1][0] = 0 tx_win_center[1][1][1] = 0 tx_first_pass[1][1][1] = 0 tx_last_pass[1][1][1] = 0 tx_win_center[1][1][2] = 0 tx_first_pass[1][1][2] = 0 tx_last_pass[1][1][2] = 0 tx_win_center[1][1][3] = 0 tx_first_pass[1][1][3] = 0 tx_last_pass[1][1][3] = 0 tx_win_center[1][1][4] = 0 tx_first_pass[1][1][4] = 0 tx_last_pass[1][1][4] = 0 tx_win_center[1][1][5] = 0 tx_first_pass[1][1][5] = 0 tx_last_pass[1][1][5] = 0 tx_win_center[1][1][6] = 0 tx_first_pass[1][1][6] = 0 tx_last_pass[1][1][6] = 0 tx_win_center[1][1][7] = 0 tx_first_pass[1][1][7] = 0 tx_last_pass[1][1][7] = 0 tx_win_center[1][1][8] = 0 tx_first_pass[1][1][8] = 0 tx_last_pass[1][1][8] = 0 tx_win_center[1][1][9] = 0 tx_first_pass[1][1][9] = 0 tx_last_pass[1][1][9] = 0 tx_win_center[1][1][10] = 0 tx_first_pass[1][1][10] = 0 tx_last_pass[1][1][10] = 0 tx_win_center[1][1][11] = 0 tx_first_pass[1][1][11] = 0 tx_last_pass[1][1][11] = 0 tx_win_center[1][1][12] = 0 tx_first_pass[1][1][12] = 0 tx_last_pass[1][1][12] = 0 tx_win_center[1][1][13] = 0 tx_first_pass[1][1][13] = 0 tx_last_pass[1][1][13] = 0 tx_win_center[1][1][14] = 0 tx_first_pass[1][1][14] = 0 tx_last_pass[1][1][14] = 0 tx_win_center[1][1][15] = 0 tx_first_pass[1][1][15] = 0 tx_last_pass[1][1][15] = 0 dump params rx window rx_firspass[0][0][0] = 0 rx_lastpass[0][0][0] = 0 rx_firspass[0][0][1] = 0 rx_lastpass[0][0][1] = 0 rx_firspass[0][0][2] = 0 rx_lastpass[0][0][2] = 0 rx_firspass[0][0][3] = 0 rx_lastpass[0][0][3] = 0 rx_firspass[0][0][4] = 0 rx_lastpass[0][0][4] = 0 rx_firspass[0][0][5] = 0 rx_lastpass[0][0][5] = 0 rx_firspass[0][0][6] = 0 rx_lastpass[0][0][6] = 0 rx_firspass[0][0][7] = 0 rx_lastpass[0][0][7] = 0 rx_firspass[0][0][8] = 0 rx_lastpass[0][0][8] = 0 rx_firspass[0][0][9] = 0 rx_lastpass[0][0][9] = 0 rx_firspass[0][0][10] = 0 rx_lastpass[0][0][10] = 0 rx_firspass[0][0][11] = 0 rx_lastpass[0][0][11] = 0 rx_firspass[0][0][12] = 0 rx_lastpass[0][0][12] = 0 rx_firspass[0][0][13] = 0 rx_lastpass[0][0][13] = 0 rx_firspass[0][0][14] = 0 rx_lastpass[0][0][14] = 0 rx_firspass[0][0][15] = 0 rx_lastpass[0][0][15] = 0 rx_firspass[0][1][0] = 0 rx_lastpass[0][1][0] = 0 rx_firspass[0][1][1] = 0 rx_lastpass[0][1][1] = 0 rx_firspass[0][1][2] = 0 rx_lastpass[0][1][2] = 0 rx_firspass[0][1][3] = 0 rx_lastpass[0][1][3] = 0 rx_firspass[0][1][4] = 0 rx_lastpass[0][1][4] = 0 rx_firspass[0][1][5] = 0 rx_lastpass[0][1][5] = 0 rx_firspass[0][1][6] = 0 rx_lastpass[0][1][6] = 0 rx_firspass[0][1][7] = 0 rx_lastpass[0][1][7] = 0 rx_firspass[0][1][8] = 0 rx_lastpass[0][1][8] = 0 rx_firspass[0][1][9] = 0 rx_lastpass[0][1][9] = 0 rx_firspass[0][1][10] = 0 rx_lastpass[0][1][10] = 0 rx_firspass[0][1][11] = 0 rx_lastpass[0][1][11] = 0 rx_firspass[0][1][12] = 0 rx_lastpass[0][1][12] = 0 rx_firspass[0][1][13] = 0 rx_lastpass[0][1][13] = 0 rx_firspass[0][1][14] = 0 rx_lastpass[0][1][14] = 0 rx_firspass[0][1][15] = 0 rx_lastpass[0][1][15] = 0 rx_firspass[1][0][0] = 0 rx_lastpass[1][0][0] = 0 rx_firspass[1][0][1] = 0 rx_lastpass[1][0][1] = 0 rx_firspass[1][0][2] = 0 rx_lastpass[1][0][2] = 0 rx_firspass[1][0][3] = 0 rx_lastpass[1][0][3] = 0 rx_firspass[1][0][4] = 0 rx_lastpass[1][0][4] = 0 rx_firspass[1][0][5] = 0 rx_lastpass[1][0][5] = 0 rx_firspass[1][0][6] = 0 rx_lastpass[1][0][6] = 0 rx_firspass[1][0][7] = 0 rx_lastpass[1][0][7] = 0 rx_firspass[1][0][8] = 0 rx_lastpass[1][0][8] = 0 rx_firspass[1][0][9] = 0 rx_lastpass[1][0][9] = 0 rx_firspass[1][0][10] = 0 rx_lastpass[1][0][10] = 0 rx_firspass[1][0][11] = 0 rx_lastpass[1][0][11] = 0 rx_firspass[1][0][12] = 0 rx_lastpass[1][0][12] = 0 rx_firspass[1][0][13] = 0 rx_lastpass[1][0][13] = 0 rx_firspass[1][0][14] = 0 rx_lastpass[1][0][14] = 0 rx_firspass[1][0][15] = 0 rx_lastpass[1][0][15] = 0 rx_firspass[1][1][0] = 0 rx_lastpass[1][1][0] = 0 rx_firspass[1][1][1] = 0 rx_lastpass[1][1][1] = 0 rx_firspass[1][1][2] = 0 rx_lastpass[1][1][2] = 0 rx_firspass[1][1][3] = 0 rx_lastpass[1][1][3] = 0 rx_firspass[1][1][4] = 0 rx_lastpass[1][1][4] = 0 rx_firspass[1][1][5] = 0 rx_lastpass[1][1][5] = 0 rx_firspass[1][1][6] = 0 rx_lastpass[1][1][6] = 0 rx_firspass[1][1][7] = 0 rx_lastpass[1][1][7] = 0 rx_firspass[1][1][8] = 0 rx_lastpass[1][1][8] = 0 rx_firspass[1][1][9] = 0 rx_lastpass[1][1][9] = 0 rx_firspass[1][1][10] = 0 rx_lastpass[1][1][10] = 0 rx_firspass[1][1][11] = 0 rx_lastpass[1][1][11] = 0 rx_firspass[1][1][12] = 0 rx_lastpass[1][1][12] = 0 rx_firspass[1][1][13] = 0 rx_lastpass[1][1][13] = 0 rx_firspass[1][1][14] = 0 rx_lastpass[1][1][14] = 0 rx_firspass[1][1][15] = 0 rx_lastpass[1][1][15] = 0 dump params clk_delay clk_delay[0] = 0 clk_delay[1] = 0 dump params dqs_delay dqs_delay[0][0] = 0 dqs_delay[0][1] = 0 dqs_delay[1][0] = 0 dqs_delay[1][1] = 0 dump params delay_cell_unit = 744 mt_set_emi_preloader end [mt_mem_init] dram size: 0x100000000, rank number: 2 [complex_mem_test] start addr:0x40000000, len:20480 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0 [complex_mem_test] start addr:0x80000000, len:20480 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0 [complex_mem_test] start addr:0xc0000000, len:20480 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0 [complex_mem_test] start addr:0x56000000, len:8192 [MEM] 1st complex R/W mem test pass (start addr:0x56000000) ddr_geometry:1 [complex_mem_test] start addr:0x80000000, len:8192 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1) dram_init: dram init end (result: 0) Successfully loaded DRAM blobs and ran DRAM calibration Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal CBMEM: IMD: root @ 00000000fffff000 254 entries. IMD: root @ 00000000ffffec00 62 entries. VBOOT: copying vboot_working_data (256 bytes) to CBMEM... out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 Chrome EC: clear events_b mask to 0x0000000020004000 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00 in-header: 03 fd 00 00 00 00 00 00 in-data: FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 10d40 size d563 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps Accumulated console time in romstage 13481 ms coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception FMAP: area RO_VPD found @ 3f8000 (32768 bytes) Manufacturer: ef SF: Detected W25Q64DW with sector size 0x1000, total 0x800000 WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 550000 (16384 bytes) FMAP: area RW_VPD found @ 550000 (16384 bytes) read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 10689 usecs done BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Setting resources... Root Device assign_resources, bus 0 link: 0 CPU_CLUSTER: 0 missing set_resources Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Done allocating resources. BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0 Initializing devices... Root Device init ... mainboard_init: Starting display init. ADC[4]: Raw value=75908 ID=0 anx7625_power_on_init: Init interface. anx7625_disable_pd_protocol: Disabled PD feature. anx7625_power_on_init: Firmware: ver 0x13, rev 0x0. anx7625_start_dp_work: Secure OCM version=00 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91 sp_tx_get_edid_block: EDID Block = 1 Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 06 af 5c 14 00 00 00 00 00 1a version: 01 04 basic params: 95 1a 0e 78 02 chroma info: 99 85 95 55 56 92 28 22 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a extensions: 00 checksum: ae Manufacturer: AUO Model 145c Serial Number 0 Made week 0 of 2016 EDID version: 1.4 Digital display 6 bits per primary color channel DisplayPort interface Maximum image size: 26 cm x 14 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4 First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: ce1d56ea50001a3030204600009010000018 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm 0556 0586 05a6 0640 hborder 0 0300 0304 030a 031a vborder 0 -hsync -vsync Did detailed timing Hex of detail: 0000000f0000000000000000000000000020 Manufacturer-specified data, tag 15 Hex of detail: 000000fe0041554f0a202020202020202020 ASCII string: AUO Hex of detail: 000000fe004231313658414230312e34200a ASCII string: B116XAB01.4 Checksum Checksum: 0xae (valid) get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz DSI data_rate: 457800000 bps anx7625_parse_edid: set default k value to 0x3d for panel anx7625_parse_edid: pixelclock(76300). hactive(1366), hsync(32), hfp(48), hbp(154) vactive(768), vsync(6), vfp(4), vbp(16) anx7625_dsi_config: config dsi. anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8). anx7625_dsi_config: success to config DSI anx7625_dp_start: MIPI phy setup OK. [SSUSB] Setting up USB HOST controller... [SSUSB] u3phy_ports_enable u2p:1, u3p:0 [SSUSB] phy power-on done. out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00 in-header: 03 fc 01 00 00 00 00 00 in-data: handle_proto3_response: EC response with error code: 1 SPM: pcm index = 1 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'pcm_allinone_lp4_3200.bin' CBFS: Found @ offset 1e7c0 size 1026 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps SPM: binary array size = 2988 SPM: version = pcm_allinone_v1.17.2_20180829 SPM binary loaded in 32 msecs spm_kick_im_to_fetch: ptr = 000000004021eec2 spm_kick_im_to_fetch: len = 2988 SPM: spm_kick_pcm_to_run SPM: spm_kick_pcm_to_run done SPM: spm_init done in 52 msecs Root Device init finished in 494987 usecs CPU_CLUSTER: 0 init ... Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'sspm.bin' CBFS: Found @ offset 208c0 size 41cb read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps CPU_CLUSTER: 0 init finished in 42803 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0 FMAP: area RW_ELOG found @ 558000 (4096 bytes) ELOG: NV offset 0x558000 size 0x1000 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:07 UTC out: cmd=0x121: 03 db 21 01 00 00 00 00 in-header: 03 c7 00 00 2c 00 00 00 in-data: b8 4a 00 00 00 00 00 00 02 10 00 00 06 80 00 00 ad c3 00 00 06 80 00 00 81 ea 01 00 06 80 00 00 98 17 06 00 06 80 00 00 93 af 0b 00 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 19 00 00 08 00 00 00 in-data: a2 e0 47 00 13 00 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00 in-header: 03 e1 00 00 08 00 00 00 in-data: 84 20 60 10 00 00 00 00 FMAP: area RW_NVRAM found @ 554000 (8192 bytes) out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00 in-header: 03 e1 00 00 08 00 00 00 in-data: 84 20 60 10 00 00 00 00 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:07 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:07 UTC elog_add_boot_reason: Logged dev mode boot Finalize devices... Devices finalized BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0 ELOG: Event(91) added with size 10 at 2024-06-16 00:56:07 UTC Writing coreboot table at 0xffeda000 0. 0000000000114000-000000000011efff: RAMSTAGE 1. 0000000040000000-000000004023cfff: RAMSTAGE 2. 000000004023d000-00000000545fffff: RAM 3. 0000000054600000-000000005465ffff: BL31 4. 0000000054660000-00000000ffed9fff: RAM 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES 6. 0000000100000000-000000013fffffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE write protect | 0x00000096 | low | high EC in RW | 0x000000b1 | high | undefined EC interrupt | 0x00000097 | low | undefined TPM interrupt | 0x00000099 | high | undefined speaker enable | 0x000000af | high | undefined out: cmd=0x6: 03 f7 06 00 00 00 00 00 in-header: 03 f7 00 00 02 00 00 00 in-data: 04 00 Board ID: 4 ADC[3]: Raw value=213471 ID=1 RAM code: 1 SKU ID: 16 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum f809 coreboot table: 940 bytes. IMD ROOT 0. 00000000fffff000 00001000 IMD SMALL 1. 00000000ffffe000 00001000 CONSOLE 2. 00000000fffde000 00020000 FMAP 3. 00000000fffdd000 0000047c TIME STAMP 4. 00000000fffdc000 00000910 RAMOOPS 5. 00000000ffedc000 00100000 COREBOOT 6. 00000000ffeda000 00002000 IMD small region: IMD ROOT 0. 00000000ffffec00 00000400 VBOOT WORK 1. 00000000ffffeb00 00000100 EC HOSTEVENT 2. 00000000ffffeae0 00000008 VPD 3. 00000000ffffea60 0000006c BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00 in-header: 03 e1 00 00 08 00 00 00 in-data: 84 20 60 10 00 00 00 00 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset dc040 size 439a0 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps Checking segment from ROM address 0x0000000040003a00 Checking segment from ROM address 0x0000000040003a1c Loading segment from ROM address 0x0000000040003a00 code (compression=0) New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968 it's not compressed! [ 0x80000000, 80043968, 0x811994a0) <- 40003a38 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38 Loading segment from ROM address 0x0000000040003a1c Entry Point 0x0000000080000000 Loaded segments BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0 Jumping to boot code at 0000000080000000(00000000ffeda000) CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 36dc0 size 5820 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps Checking segment from ROM address 0x0000000040003a00 Checking segment from ROM address 0x0000000040003a1c Loading segment from ROM address 0x0000000040003a00 code (compression=1) New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8 using LZMA [ 0x54600000, 5460f420, 0x54629000) <- 40003a38 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0 Loading segment from ROM address 0x0000000040003a1c Entry Point 0x0000000054601000 Loaded segments NOTICE: MT8183 bl31_setup NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022 INFO: [DEVAPC] dump DEVAPC registers: INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0 INFO: [DEVAPC] MAS_DOM_0 = 0x1 INFO: [DEVAPC] MAS_DOM_1 = 0x200 INFO: [DEVAPC] MAS_DOM_2 = 0x0 INFO: [DEVAPC] MAS_DOM_3 = 0x2000 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24 WARNING: region 0: WARNING: apc:0x168, sa:0x0, ea:0xfff WARNING: region 1: WARNING: apc:0x140, sa:0x1000, ea:0x128f WARNING: region 2: WARNING: apc:0x168, sa:0x1290, ea:0x1fff WARNING: region 3: WARNING: apc:0x168, sa:0x2000, ea:0xbfff WARNING: region 4: WARNING: apc:0x168, sa:0xc000, ea:0x1ffff WARNING: region 5: WARNING: apc:0x0, sa:0x0, ea:0x0 WARNING: region 6: WARNING: apc:0x0, sa:0x0, ea:0x0 WARNING: region 7: WARNING: apc:0x0, sa:0x0, ea:0x0 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3 INFO: SPM: enable SPMC mode NOTICE: spm_boot_init() start NOTICE: spm_boot_init() end INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x80000000 INFO: SPSR = 0x8 Starting depthcharge on Juniper... vboot_handoff: creating legacy vboot_handoff structure ec_init(0): CrosEC protocol v3 supported (544, 544) Wipe memory regions: [0x00000040000000, 0x00000054600000) [0x00000054660000, 0x00000080000000) [0x000000811994a0, 0x000000ffeda000) [0x00000100000000, 0x00000140000000) Initializing XHCI USB controller at 0x11200000. [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54 jacuzzi: tftpboot 192.168.201.1 14368598/tftp-deploy-xkhdqcna/kernel/image.itb 14368598/tftp-deploy-xkhdqcna/kernel/cmdline tftpboot 192.168.201.1 14368598/tftp-deploy-xkhdqcna/kernel/image.ittp-deploy-xkhdqcna/kernel/cmdline Waiting for link R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device done. MAC: 00:e0:4c:72:3d:a6 Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.20 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 14368598/tftp-deploy-xkhdqcna/kernel/image.itb Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ################################################################ 00d00000 ################################################################ 00d80000 ################################################################ 00e00000 ################################################################ 00e80000 ################################################################ 00f00000 ################################################################ 00f80000 ################################################################ 01000000 ################################################################ 01080000 ################################################################ 01100000 ################################################################ 01180000 ################################################################ 01200000 ################################################################ 01280000 ################################################################ 01300000 ################################################################ 01380000 ################################################################ 01400000 ################################################################ 01480000 ################################################################ 01500000 ################################################################ 01580000 ################################################################ 01600000 ################################################################ 01680000 ################################################################ 01700000 ################################################################ 01780000 ################################################################ 01800000 ################################################################ 01880000 ################################################################ 01900000 ################################################################ 01980000 ################################################################ 01a00000 ################################################################ 01a80000 ################################################################ 01b00000 ################################################################ 01b80000 ################################################################ 01c00000 ################################################################ 01c80000 ################################################################ 01d00000 ################################################################ 01d80000 ################################################################ 01e00000 ################################################################ 01e80000 ################################################################ 01f00000 ################################################################ 01f80000 ################################################################ 02000000 ################################################################ 02080000 ########################################################## done. The bootfile was 34547958 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 14368598/tftp-deploy-xkhdqcna/kernel/cmdline The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 Loading FIT. Image ramdisk-1 has 21363173 bytes. Image fdt-1 has 57695 bytes. Image kernel-1 has 13125045 bytes. Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183 Choosing best match conf-1 for compat google,juniper-sku16. Connected to device vid:did:rid of 1ae0:0028:00 tpm_get_response: command 0x17b, return code 0x0 tpm_cleanup: add release locality here. Shutting down all USB controllers. Removing current net device Exiting depthcharge with code 4 at timestamp: 35300189 LZMA decompressing kernel-1 to 0x80193568 LZMA decompressing kernel-1 to 0x40000000 jumping to kernel [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 [ 0.000000] random: crng init done [ 0.000000] Machine model: Google juniper sku16 board [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8') [ 0.000000] printk: bootconsole [mtk8250] enabled [ 0.000000] NUMA: No NUMA configuration found [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff] [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff] [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.1 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI) [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space. <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off <6>[ 0.000000] software IO TLB: area num 8. <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB) <6>[ 0.000000] Memory: 3894212K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 264252K reserved, 32768K cma-reserved) <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation. <6>[ 0.000000] rcu: RCU event tracing is enabled. <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8. <6>[ 0.000000] Trampoline variant of Tasks RCU enabled. <6>[ 0.000000] Tracing variant of Tasks RCU enabled. <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode <6>[ 0.000000] GICv3: 640 SPIs implemented <6>[ 0.000000] GICv3: 0 Extended SPIs implemented <6>[ 0.000000] Root IRQ handler: gic_handle_irq <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] } <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] } <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys). <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns <6>[ 0.009475] Console: colour dummy device 80x25 <6>[ 0.014514] printk: console [tty1] enabled <6>[ 0.018902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000) <6>[ 0.029367] pid_max: default: 32768 minimum: 301 <6>[ 0.034249] LSM: Security Framework initializing <6>[ 0.039165] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.046789] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <4>[ 0.055658] cacheinfo: Unable to detect cache hierarchy for CPU 0 <6>[ 0.062287] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.069734] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.076085] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.083530] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.089929] rcu: Hierarchical SRCU implementation. <6>[ 0.094955] rcu: Max phase no-delay instances is 1000. <6>[ 0.102894] EFI services will not be available. <6>[ 0.107844] smp: Bringing up secondary CPUs ... <6>[ 0.113066] Detected VIPT I-cache on CPU1 <4>[ 0.113113] cacheinfo: Unable to detect cache hierarchy for CPU 1 <6>[ 0.113122] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000 <6>[ 0.113154] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] <6>[ 0.113635] Detected VIPT I-cache on CPU2 <4>[ 0.113669] cacheinfo: Unable to detect cache hierarchy for CPU 2 <6>[ 0.113674] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000 <6>[ 0.113686] CPU2: Booted secondary processor 0x0000000002 [0x410fd034] <6>[ 0.114132] Detected VIPT I-cache on CPU3 <4>[ 0.114162] cacheinfo: Unable to detect cache hierarchy for CPU 3 <6>[ 0.114167] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000 <6>[ 0.114178] CPU3: Booted secondary processor 0x0000000003 [0x410fd034] <6>[ 0.114752] CPU features: detected: Spectre-v2 <6>[ 0.114762] CPU features: detected: Spectre-BHB <6>[ 0.114766] CPU features: detected: ARM erratum 858921 <6>[ 0.114772] Detected VIPT I-cache on CPU4 <4>[ 0.114820] cacheinfo: Unable to detect cache hierarchy for CPU 4 <6>[ 0.114828] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000 <6>[ 0.114836] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.114846] arch_timer: CPU4: Trapping CNTVCT access <6>[ 0.114854] CPU4: Booted secondary processor 0x0000000100 [0x410fd092] <6>[ 0.115338] Detected VIPT I-cache on CPU5 <4>[ 0.115380] cacheinfo: Unable to detect cache hierarchy for CPU 5 <6>[ 0.115385] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000 <6>[ 0.115392] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.115398] arch_timer: CPU5: Trapping CNTVCT access <6>[ 0.115403] CPU5: Booted secondary processor 0x0000000101 [0x410fd092] <6>[ 0.115839] Detected VIPT I-cache on CPU6 <4>[ 0.115884] cacheinfo: Unable to detect cache hierarchy for CPU 6 <6>[ 0.115890] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000 <6>[ 0.115897] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.115903] arch_timer: CPU6: Trapping CNTVCT access <6>[ 0.115909] CPU6: Booted secondary processor 0x0000000102 [0x410fd092] <6>[ 0.116439] Detected VIPT I-cache on CPU7 <4>[ 0.116482] cacheinfo: Unable to detect cache hierarchy for CPU 7 <6>[ 0.116488] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000 <6>[ 0.116495] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.116501] arch_timer: CPU7: Trapping CNTVCT access <6>[ 0.116507] CPU7: Booted secondary processor 0x0000000103 [0x410fd092] <6>[ 0.116555] smp: Brought up 1 node, 8 CPUs <6>[ 0.355454] SMP: Total of 8 processors activated. <6>[ 0.360389] CPU features: detected: 32-bit EL0 Support <6>[ 0.365767] CPU features: detected: 32-bit EL1 Support <6>[ 0.371135] CPU features: detected: CRC32 instructions <6>[ 0.376560] CPU: All CPU(s) started at EL2 <6>[ 0.380897] alternatives: applying system-wide alternatives <6>[ 0.388907] devtmpfs: initialized <6>[ 0.397846] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns <6>[ 0.407795] futex hash table entries: 2048 (order: 5, 131072 bytes, linear) <6>[ 0.415523] pinctrl core: initialized pinctrl subsystem <6>[ 0.422648] DMI not present or invalid. <6>[ 0.427018] NET: Registered PF_NETLINK/PF_ROUTE protocol family <6>[ 0.433922] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations <6>[ 0.441450] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations <6>[ 0.449698] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations <6>[ 0.457876] audit: initializing netlink subsys (disabled) <5>[ 0.463580] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1 <6>[ 0.464560] thermal_sys: Registered thermal governor 'step_wise' <6>[ 0.471547] thermal_sys: Registered thermal governor 'power_allocator' <6>[ 0.477843] cpuidle: using governor menu <6>[ 0.488808] NET: Registered PF_QIPCRTR protocol family <6>[ 0.494293] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. <6>[ 0.501389] ASID allocator initialised with 32768 entries <6>[ 0.508158] Serial: AMBA PL011 UART driver <4>[ 0.518583] Trying to register duplicate clock ID: 113 <6>[ 0.574962] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58 <6>[ 0.589327] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58 <6>[ 0.599069] KASLR enabled <6>[ 0.607073] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages <6>[ 0.614076] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page <6>[ 0.620552] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages <6>[ 0.627542] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page <6>[ 0.634016] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages <6>[ 0.641006] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page <6>[ 0.647480] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages <6>[ 0.654469] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page <6>[ 0.662047] ACPI: Interpreter disabled. <6>[ 0.670049] iommu: Default domain type: Translated <6>[ 0.675156] iommu: DMA domain TLB invalidation policy: strict mode <5>[ 0.681789] SCSI subsystem initialized <6>[ 0.686203] usbcore: registered new interface driver usbfs <6>[ 0.691932] usbcore: registered new interface driver hub <6>[ 0.697473] usbcore: registered new device driver usb <6>[ 0.703780] pps_core: LinuxPPS API ver. 1 registered <6>[ 0.708965] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <6>[ 0.718289] PTP clock support registered <6>[ 0.722540] EDAC MC: Ver: 3.0.0 <6>[ 0.728169] FPGA manager framework <6>[ 0.731854] Advanced Linux Sound Architecture Driver Initialized. <6>[ 0.738606] vgaarb: loaded <6>[ 0.741725] clocksource: Switched to clocksource arch_sys_counter <5>[ 0.748155] VFS: Disk quotas dquot_6.6.0 <6>[ 0.752331] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) <6>[ 0.759504] pnp: PnP ACPI: disabled <6>[ 0.766379] NET: Registered PF_INET protocol family <6>[ 0.771601] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) <6>[ 0.781502] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) <6>[ 0.790255] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) <6>[ 0.798206] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) <6>[ 0.806440] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear) <6>[ 0.814535] TCP: Hash tables configured (established 32768 bind 32768) <6>[ 0.821362] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.828332] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.835810] NET: Registered PF_UNIX/PF_LOCAL protocol family <6>[ 0.841938] RPC: Registered named UNIX socket transport module. <6>[ 0.848082] RPC: Registered udp transport module. <6>[ 0.853006] RPC: Registered tcp transport module. <6>[ 0.857930] RPC: Registered tcp NFSv4.1 backchannel transport module. <6>[ 0.864583] PCI: CLS 0 bytes, default 64 <6>[ 0.868867] Unpacking initramfs... <6>[ 0.889934] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available <6>[ 0.898562] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available <6>[ 0.907418] kvm [1]: IPA Size Limit: 40 bits <6>[ 0.913759] kvm [1]: vgic-v2@c420000 <6>[ 0.917580] kvm [1]: GIC system register CPU interface enabled <6>[ 0.923774] kvm [1]: vgic interrupt IRQ18 <6>[ 0.928143] kvm [1]: Hyp mode initialized successfully <5>[ 0.934507] Initialise system trusted keyrings <6>[ 0.939305] workingset: timestamp_bits=42 max_order=20 bucket_order=0 <6>[ 0.949269] squashfs: version 4.0 (2009/01/31) Phillip Lougher <5>[ 0.955691] NFS: Registering the id_resolver key type <5>[ 0.961005] Key type id_resolver registered <5>[ 0.965419] Key type id_legacy registered <6>[ 0.969730] nfs4filelayout_init: NFSv4 File Layout Driver Registering... <6>[ 0.976651] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... <6>[ 0.984391] 9p: Installing v9fs 9p2000 file system support <5>[ 1.012760] Key type asymmetric registered <5>[ 1.017107] Asymmetric key parser 'x509' registered <6>[ 1.022263] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243) <6>[ 1.029875] io scheduler mq-deadline registered <6>[ 1.034631] io scheduler kyber registered <6>[ 1.055406] EINJ: ACPI disabled. <4>[ 1.059200] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17 <6>[ 1.100148] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled <6>[ 1.108625] printk: console [ttyS0] disabled <6>[ 1.133285] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2 <6>[ 1.142760] printk: console [ttyS0] enabled <6>[ 1.142760] printk: console [ttyS0] enabled <6>[ 1.151678] printk: bootconsole [mtk8250] disabled <6>[ 1.151678] printk: bootconsole [mtk8250] disabled <3>[ 1.162219] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47 <3>[ 1.170602] mt6577-uart 11003000.serial: Error applying setting, reverse things back <6>[ 1.199014] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2 <6>[ 1.208674] serial serial0: tty port ttyS1 registered <6>[ 1.215243] SuperH (H)SCI(F) driver initialized <6>[ 1.220752] msm_serial: driver initialized <6>[ 1.231137] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000 <6>[ 1.239735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000 <6>[ 1.248308] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000 <6>[ 1.256876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000 <6>[ 1.265527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000 <6>[ 1.274187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000 <6>[ 1.282927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000 <6>[ 1.291666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000 <6>[ 1.300231] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000 <6>[ 1.309044] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000 <4>[ 1.321432] cacheinfo: Unable to detect cache hierarchy for CPU 0 <6>[ 1.330804] loop: module loaded <6>[ 1.342740] vsim1: Bringing 1800000uV into 2700000-2700000uV <6>[ 1.360681] megasas: 07.719.03.00-rc1 <6>[ 1.369502] spi-nor spi1.0: w25q64dw (8192 Kbytes) <6>[ 1.381118] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2 <6>[ 1.397927] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0) <6>[ 1.448121] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d <6>[ 1.568444] Freeing initrd memory: 20860K <4>[ 1.584192] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m' <4>[ 1.593421] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1 <4>[ 1.600119] Hardware name: Google juniper sku16 board (DT) <4>[ 1.605858] Call trace: <4>[ 1.608558] dump_backtrace.part.0+0xe0/0xf0 <4>[ 1.613095] show_stack+0x18/0x30 <4>[ 1.616667] dump_stack_lvl+0x68/0x84 <4>[ 1.620588] dump_stack+0x18/0x34 <4>[ 1.624158] sysfs_warn_dup+0x64/0x80 <4>[ 1.628079] sysfs_do_create_link_sd+0xf0/0x100 <4>[ 1.632866] sysfs_create_link+0x20/0x40 <4>[ 1.637046] bus_add_device+0x68/0x10c <4>[ 1.641052] device_add+0x340/0x7ac <4>[ 1.644796] of_device_add+0x44/0x60 <4>[ 1.648630] of_platform_device_create_pdata+0x90/0x120 <4>[ 1.654111] of_platform_bus_create+0x170/0x370 <4>[ 1.658898] of_platform_populate+0x50/0xfc <4>[ 1.663338] parse_mtd_partitions+0x1dc/0x510 <4>[ 1.667950] mtd_device_parse_register+0xf8/0x2e0 <4>[ 1.672908] spi_nor_probe+0x21c/0x2f0 <4>[ 1.676914] spi_mem_probe+0x6c/0xb0 <4>[ 1.680747] spi_probe+0x84/0xe4 <4>[ 1.684229] really_probe+0xbc/0x2e0 <4>[ 1.688060] __driver_probe_device+0x78/0x11c <4>[ 1.692672] driver_probe_device+0xd8/0x160 <4>[ 1.697110] __device_attach_driver+0xb8/0x134 <4>[ 1.701809] bus_for_each_drv+0x78/0xd0 <4>[ 1.705900] __device_attach+0xa8/0x1c0 <4>[ 1.709990] device_initial_probe+0x14/0x20 <4>[ 1.714429] bus_probe_device+0x9c/0xa4 <4>[ 1.718519] device_add+0x3ac/0x7ac <4>[ 1.722261] __spi_add_device+0x78/0x120 <4>[ 1.726439] spi_add_device+0x40/0x7c <4>[ 1.730358] spi_register_controller+0x610/0xad0 <4>[ 1.735230] devm_spi_register_controller+0x4c/0xa4 <4>[ 1.740364] mtk_spi_probe+0x3f8/0x650 <4>[ 1.744368] platform_probe+0x68/0xe0 <4>[ 1.748287] really_probe+0xbc/0x2e0 <4>[ 1.752117] __driver_probe_device+0x78/0x11c <4>[ 1.756729] driver_probe_device+0xd8/0x160 <4>[ 1.761167] __driver_attach+0x94/0x19c <4>[ 1.765257] bus_for_each_dev+0x70/0xd0 <4>[ 1.769347] driver_attach+0x24/0x30 <4>[ 1.773177] bus_add_driver+0x154/0x20c <4>[ 1.777267] driver_register+0x78/0x130 <4>[ 1.781358] __platform_driver_register+0x28/0x34 <4>[ 1.786318] mtk_spi_driver_init+0x1c/0x28 <4>[ 1.790671] do_one_initcall+0x50/0x1d0 <4>[ 1.794761] kernel_init_freeable+0x21c/0x288 <4>[ 1.799375] kernel_init+0x24/0x12c <4>[ 1.803120] ret_from_fork+0x10/0x20 <6>[ 1.812031] tun: Universal TUN/TAP device driver, 1.6 <6>[ 1.818329] thunder_xcv, ver 1.0 <6>[ 1.821842] thunder_bgx, ver 1.0 <6>[ 1.825340] nicpf, ver 1.0 <6>[ 1.829711] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version <6>[ 1.837202] hns3: Copyright (c) 2017 Huawei Corporation. <6>[ 1.842804] hclge is initializing <6>[ 1.846394] e1000: Intel(R) PRO/1000 Network Driver <6>[ 1.851531] e1000: Copyright (c) 1999-2006 Intel Corporation. <6>[ 1.857553] e1000e: Intel(R) PRO/1000 Network Driver <6>[ 1.862774] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. <6>[ 1.868969] igb: Intel(R) Gigabit Ethernet Network Driver <6>[ 1.874627] igb: Copyright (c) 2007-2014 Intel Corporation. <6>[ 1.880470] igbvf: Intel(R) Gigabit Virtual Function Network Driver <6>[ 1.886993] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. <6>[ 1.893550] sky2: driver version 1.30 <6>[ 1.898817] usbcore: registered new device driver r8152-cfgselector <6>[ 1.905360] usbcore: registered new interface driver r8152 <6>[ 1.911186] VFIO - User Level meta-driver version: 0.3 <6>[ 1.918995] mtu3 11201000.usb: uwk - reg:0x420, version:101 <4>[ 1.924873] mtu3 11201000.usb: supply vbus not found, using dummy regulator <6>[ 1.932171] mtu3 11201000.usb: dr_mode: 1, drd: auto <6>[ 1.937400] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0 <6>[ 1.943594] mtu3 11201000.usb: usb3-drd: 0 <6>[ 1.949161] mtu3 11201000.usb: xHCI platform device register success... <4>[ 1.957869] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator <6>[ 1.965800] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 1.971298] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1 <6>[ 1.979018] xhci-mtk 11200000.usb: USB3 root hub has no ports <6>[ 1.985026] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010 <6>[ 1.994448] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000 <6>[ 2.000520] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 2.006009] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2 <6>[ 2.013667] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed <6>[ 2.020480] hub 1-0:1.0: USB hub found <6>[ 2.024509] hub 1-0:1.0: 1 port detected <6>[ 2.029848] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. <6>[ 2.038484] hub 2-0:1.0: USB hub found <3>[ 2.042535] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19) <6>[ 2.050428] usbcore: registered new interface driver usb-storage <6>[ 2.057020] usbcore: registered new device driver onboard-usb-hub <4>[ 2.065824] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator <6>[ 2.078063] mt6397-rtc mt6358-rtc: registered as rtc0 <6>[ 2.083539] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-16T00:56:30 UTC (1718499390) <6>[ 2.093430] i2c_dev: i2c /dev entries driver <6>[ 2.099856] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58 <6>[ 2.108199] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58 <6>[ 2.117104] i2c 4-0058: Fixed dependency cycle(s) with /panel <6>[ 2.123136] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000 <3>[ 2.130591] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host. <6>[ 2.150529] cpu cpu0: EM: created perf domain <6>[ 2.156007] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz <6>[ 2.167282] cpu cpu4: EM: created perf domain <6>[ 2.174017] sdhci: Secure Digital Host Controller Interface driver <6>[ 2.180466] sdhci: Copyright(c) Pierre Ossman <6>[ 2.185868] Synopsys Designware Multimedia Card Interface Driver <6>[ 2.186379] mtk-msdc 11240000.mmc: allocated mmc-pwrseq <6>[ 2.193025] sdhci-pltfm: SDHCI platform and OF driver helper <6>[ 2.205844] ledtrig-cpu: registered to indicate activity on CPUs <6>[ 2.213602] usbcore: registered new interface driver usbhid <6>[ 2.219447] usbhid: USB HID core driver <6>[ 2.223711] spi_master spi2: will run message pump with realtime priority <4>[ 2.223717] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator <4>[ 2.237995] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator <6>[ 2.245867] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0 <6>[ 2.261686] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1 <4>[ 2.270074] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes) <6>[ 2.282657] cros-ec-spi spi2.0: Chrome EC device registered <4>[ 2.290056] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes) <4>[ 2.301627] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes) <4>[ 2.310301] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes) <6>[ 2.320244] mmc1: new ultra high speed SDR104 SDIO card at address 0001 <6>[ 2.350708] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14 <6>[ 2.358152] mmc0: new HS400 MMC card at address 0001 <6>[ 2.364856] mmcblk0: mmc0:0001 DA4032 29.1 GiB <6>[ 2.375847] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 <6>[ 2.377615] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound <6>[ 2.384573] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB <6>[ 2.389733] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2 <6>[ 2.389846] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c <6>[ 2.394292] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <6>[ 2.429649] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB <6>[ 2.430064] NET: Registered PF_PACKET protocol family <6>[ 2.436334] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0) <6>[ 2.440449] 9pnet: Installing 9P2000 support <6>[ 2.446881] usb 1-1: new high-speed USB device number 2 using xhci-mtk <5>[ 2.451496] Key type dns_resolver registered <6>[ 2.463343] registered taskstats version 1 <5>[ 2.467712] Loading compiled-in X.509 certificates <3>[ 2.507247] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517 <6>[ 2.534831] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <6>[ 2.548384] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.556960] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.565487] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.574014] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.582537] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.591059] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.599581] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.608675] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0 <6>[ 2.609671] hub 1-1:1.0: USB hub found <6>[ 2.616039] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0 <6>[ 2.619682] hub 1-1:1.0: 3 ports detected <6>[ 2.626413] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0 <6>[ 2.637227] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0 <6>[ 2.644740] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0 <6>[ 2.653101] panfrost 13040000.gpu: clock rate = 511999970 <6>[ 2.658802] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet <6>[ 2.669319] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0 <6>[ 2.677332] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400 <6>[ 2.685764] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7 <6>[ 2.697840] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1 <6>[ 2.709003] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0 <6>[ 2.717846] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.726986] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.736117] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.745246] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.754547] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.763846] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops) <6>[ 2.773319] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops) <6>[ 2.782794] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops) <6>[ 2.791920] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops) <6>[ 2.865442] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops) <6>[ 2.874331] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing <6>[ 2.886181] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1 <6>[ 2.917760] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk <6>[ 3.101995] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk <4>[ 3.205268] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2 <4>[ 3.205285] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2) <6>[ 3.242635] r8152 1-1.2:1.0 eth0: v1.12.13 <6>[ 3.321756] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk <6>[ 3.561592] Console: switching to colour frame buffer device 170x48 <6>[ 3.622248] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device <6>[ 3.639222] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <6>[ 3.656675] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <6>[ 3.669138] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4 <6>[ 3.677422] input: volume-buttons as /devices/platform/volume-buttons/input/input5 <6>[ 3.684746] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <6>[ 3.703710] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <6>[ 4.872016] r8152 1-1.2:1.0 eth0: carrier on <5>[ 4.893763] Sending DHCP requests .., OK <6>[ 7.178169] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.20 <6>[ 7.186619] IP-Config: Complete: <6>[ 7.190186] device=eth0, hwaddr=00:e0:4c:72:3d:a6, ipaddr=192.168.201.20, mask=255.255.255.0, gw=192.168.201.1 <6>[ 7.201092] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4, domain=lava-rack, nis-domain=(none) <6>[ 7.215410] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath= <6>[ 7.215421] nameserver0=192.168.201.1 <6>[ 7.235295] clk: Disabling unused clocks <6>[ 7.243251] ALSA device list: <6>[ 7.249295] No soundcards found. <6>[ 7.258407] Freeing unused kernel memory: 8512K <6>[ 7.265560] Run /init as init process Starting syslogd: OK Starting klogd: OK Running sysctl: OK Populating /dev using udev: <30>[ 7.327376] udevd[206]: starting version 3.2.9 <27>[ 7.335210] udevd[206]: specified user 'tss' unknown <27>[ 7.341319] udevd[206]: specified group 'tss' unknown <30>[ 7.348331] udevd[207]: starting eudev-3.2.9 <27>[ 7.370576] udevd[207]: specified user 'tss' unknown <27>[ 7.377119] udevd[207]: specified group 'tss' unknown <3>[ 7.518635] mtk-scp 10500000.scp: invalid resource <6>[ 7.524232] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0) <6>[ 7.524554] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000 <3>[ 7.529813] thermal_sys: Failed to find 'trips' node <3>[ 7.529818] thermal_sys: Failed to find trip points for thermal-sensor1 id=0 <3>[ 7.529825] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22 <4>[ 7.529829] generic-adc-thermal: probe of thermal-sensor1 failed with error -22 <3>[ 7.535740] thermal_sys: Failed to find 'trips' node <6>[ 7.555561] remoteproc remoteproc0: scp is available <3>[ 7.564737] thermal_sys: Failed to find trip points for thermal-sensor2 id=0 <4>[ 7.575961] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator <4>[ 7.576503] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2 <6>[ 7.576515] remoteproc remoteproc0: powering up scp <4>[ 7.576528] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2 <3>[ 7.576531] remoteproc remoteproc0: request_firmware failed: -2 <3>[ 7.581117] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22 <4>[ 7.592709] elants_i2c 0-0010: supply vccio not found, using dummy regulator <4>[ 7.595707] generic-adc-thermal: probe of thermal-sensor2 failed with error -22 <3>[ 7.601864] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015 <3>[ 7.601875] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22 <3>[ 7.601879] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris <3>[ 7.601883] elan_i2c 2-0015: Error applying setting, reverse things back <3>[ 7.611162] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <4>[ 7.620244] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW <3>[ 7.625332] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.631230] mc: Linux media interface: v0.10 <6>[ 7.633673] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20 <5>[ 7.635423] cfg80211: Loading compiled-in X.509 certificates for regulatory database <3>[ 7.640692] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.649862] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <3>[ 7.658619] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.658752] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered <5>[ 7.661994] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' <5>[ 7.662482] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600' <4>[ 7.662558] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 <6>[ 7.662567] cfg80211: failed to load regulatory.db <3>[ 7.665289] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present! <3>[ 7.678091] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.692538] videodev: Linux video capture interface: v2.00 <6>[ 7.692977] cs_system_cfg: CoreSight Configuration manager initialised <3>[ 7.702185] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.744659] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized <6>[ 7.753694] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7 <3>[ 7.755558] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.771519] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized <3>[ 7.773220] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.780169] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized <3>[ 7.790160] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.797831] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized <6>[ 7.803280] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0 <6>[ 7.816441] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567) <6>[ 7.823399] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized <6>[ 7.823667] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0) <6>[ 7.824997] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0 <6>[ 7.825962] Bluetooth: Core ver 2.22 <6>[ 7.826006] NET: Registered PF_BLUETOOTH protocol family <6>[ 7.826008] Bluetooth: HCI device and connection manager initialized <6>[ 7.826018] Bluetooth: HCI socket layer initialized <6>[ 7.826022] Bluetooth: L2CAP socket layer initialized <6>[ 7.826029] Bluetooth: SCO socket layer initialized <6>[ 7.826051] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1 <6>[ 7.847127] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8 <6>[ 7.853830] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized <6>[ 7.863113] usbcore: registered new interface driver uvcvideo <6>[ 7.863172] Bluetooth: HCI UART driver ver 2.3 <6>[ 7.863179] Bluetooth: HCI UART protocol H4 registered <6>[ 7.863216] Bluetooth: HCI UART protocol LL registered <6>[ 7.863229] Bluetooth: HCI UART protocol Three-wire (H5) registered <3>[ 7.863329] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t' <6>[ 7.863563] Bluetooth: HCI UART protocol Broadcom registered <6>[ 7.863589] Bluetooth: HCI UART protocol QCA registered <6>[ 7.863601] Bluetooth: HCI UART protocol Marvell registered <3>[ 7.864181] debugfs: File 'Playback' in directory 'dapm' already present! <3>[ 7.864192] debugfs: File 'Capture' in directory 'dapm' already present! <6>[ 7.864478] Bluetooth: hci0: setting up ROME/QCA6390 <6>[ 7.865749] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6 <6>[ 7.871618] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized <6>[ 7.887524] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000 <6>[ 7.888292] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized <6>[ 7.896028] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 <3>[ 8.077368] Bluetooth: hci0: Frame reassembly failed (-84) <6>[ 8.080016] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77 <4>[ 8.220244] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA. <4>[ 8.220244] Fallback method does not support PEC. <3>[ 8.238119] power_supply sbs-12-000b: driver failed to report `technology' property: -5 done Saving random seed: <3>[ 8.253797] power_supply sbs-12-000b: driver failed to report `technology' property: -5 OK Starting network: ip: RTNETLINK answers: File exists FAIL Starting dropbear sshd: <6>[ 8.316909] NET: Registered PF_INET6 protocol family <6>[ 8.325503] Segment Routing with IPv6 <6>[ 8.331333] In-situ OAM (IOAM) with IPv6 OK /bin/sh: can't access tty; job control turned off / # <6>[ 8.363263] Bluetooth: hci0: QCA Product ID :0x00000008 <6>[ 8.367075] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91 <6>[ 8.368974] Bluetooth: hci0: QCA SOC Version :0x00000044 <6>[ 8.393772] Bluetooth: hci0: QCA ROM Version :0x00000302 <6>[ 8.403184] Bluetooth: hci0: QCA Patch Version:0x00000111 / # <6>[ 8.412246] Bluetooth: hci0: QCA controller version 0x00440302 <6>[ 8.421231] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin # <4>[ 8.430991] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2 <3>[ 8.442685] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2) <3>[ 8.452996] Bluetooth: hci0: QCA Failed to download patch (-2) # / # export SHELL=/bin/sh export SHELL=/bin/sh / # . /lava-14368598/environment . /lava-14368598/environment<6>[ 8.724846] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1 / # /lava-14368598/bin/lava-test-runner /lava-14368598/0 <4>[ 8.809815] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes) /lava-14368598/bin/lava-test-runner /lava-14368598/0<4>[ 8.830943] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes) <4>[ 8.847026] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes) <4>[ 8.860244] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes) + export 'TESTRUN_ID=0_dmesg' +<8>[ 8.897731] cd /lava-14368598/0/tests/0_dmesg + cat uuid + UUID=14368598_1.5.2.3.1 + set +x + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh <8>[ 8.921652] <8>[ 8.946592] <8>[ 8.972862] <8>[ 8.984501] + set +x / #