Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:58:06.946535 lava-dispatcher, installed at version: 2024.03
2 00:58:06.946751 start: 0 validate
3 00:58:06.946870 Start time: 2024-06-16 00:58:06.946863+00:00 (UTC)
4 00:58:06.947001 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:58:06.947139 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 00:58:07.202756 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:58:07.203505 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:58:07.457921 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:58:07.458806 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:58:07.713028 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:58:07.713679 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:58:07.971938 validate duration: 1.03
14 00:58:07.972246 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:58:07.972342 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:58:07.972424 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:58:07.972582 Not decompressing ramdisk as can be used compressed.
18 00:58:07.972676 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 00:58:07.972751 saving as /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/ramdisk/rootfs.cpio.gz
20 00:58:07.972822 total size: 8181887 (7 MB)
21 00:58:07.973774 progress 0 % (0 MB)
22 00:58:07.976105 progress 5 % (0 MB)
23 00:58:07.978105 progress 10 % (0 MB)
24 00:58:07.980333 progress 15 % (1 MB)
25 00:58:07.982409 progress 20 % (1 MB)
26 00:58:07.984573 progress 25 % (1 MB)
27 00:58:07.986665 progress 30 % (2 MB)
28 00:58:07.988912 progress 35 % (2 MB)
29 00:58:07.990918 progress 40 % (3 MB)
30 00:58:07.993028 progress 45 % (3 MB)
31 00:58:07.995037 progress 50 % (3 MB)
32 00:58:07.997129 progress 55 % (4 MB)
33 00:58:07.999110 progress 60 % (4 MB)
34 00:58:08.001292 progress 65 % (5 MB)
35 00:58:08.003282 progress 70 % (5 MB)
36 00:58:08.005441 progress 75 % (5 MB)
37 00:58:08.007477 progress 80 % (6 MB)
38 00:58:08.009556 progress 85 % (6 MB)
39 00:58:08.011535 progress 90 % (7 MB)
40 00:58:08.013619 progress 95 % (7 MB)
41 00:58:08.015617 progress 100 % (7 MB)
42 00:58:08.015811 7 MB downloaded in 0.04 s (181.54 MB/s)
43 00:58:08.015957 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:58:08.016172 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:58:08.016252 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:58:08.016328 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:58:08.016495 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:58:08.016556 saving as /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/kernel/Image
50 00:58:08.016608 total size: 54813184 (52 MB)
51 00:58:08.016663 No compression specified
52 00:58:08.017759 progress 0 % (0 MB)
53 00:58:08.031570 progress 5 % (2 MB)
54 00:58:08.045520 progress 10 % (5 MB)
55 00:58:08.059064 progress 15 % (7 MB)
56 00:58:08.072587 progress 20 % (10 MB)
57 00:58:08.086270 progress 25 % (13 MB)
58 00:58:08.099860 progress 30 % (15 MB)
59 00:58:08.113590 progress 35 % (18 MB)
60 00:58:08.127318 progress 40 % (20 MB)
61 00:58:08.140894 progress 45 % (23 MB)
62 00:58:08.154666 progress 50 % (26 MB)
63 00:58:08.168269 progress 55 % (28 MB)
64 00:58:08.181642 progress 60 % (31 MB)
65 00:58:08.195303 progress 65 % (34 MB)
66 00:58:08.209101 progress 70 % (36 MB)
67 00:58:08.222832 progress 75 % (39 MB)
68 00:58:08.236517 progress 80 % (41 MB)
69 00:58:08.249906 progress 85 % (44 MB)
70 00:58:08.263464 progress 90 % (47 MB)
71 00:58:08.276911 progress 95 % (49 MB)
72 00:58:08.290089 progress 100 % (52 MB)
73 00:58:08.290300 52 MB downloaded in 0.27 s (191.00 MB/s)
74 00:58:08.290452 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:58:08.290661 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:58:08.290744 start: 1.3 download-retry (timeout 00:10:00) [common]
78 00:58:08.290821 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 00:58:08.290952 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:58:08.291015 saving as /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/dtb/mt8192-asurada-spherion-r0.dtb
81 00:58:08.291070 total size: 47258 (0 MB)
82 00:58:08.291125 No compression specified
83 00:58:08.292139 progress 69 % (0 MB)
84 00:58:08.292400 progress 100 % (0 MB)
85 00:58:08.292549 0 MB downloaded in 0.00 s (30.52 MB/s)
86 00:58:08.292663 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:58:08.292864 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:58:08.292940 start: 1.4 download-retry (timeout 00:10:00) [common]
90 00:58:08.293016 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 00:58:08.293120 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:58:08.293182 saving as /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/modules/modules.tar
93 00:58:08.293236 total size: 8617404 (8 MB)
94 00:58:08.293291 Using unxz to decompress xz
95 00:58:08.294622 progress 0 % (0 MB)
96 00:58:08.313018 progress 5 % (0 MB)
97 00:58:08.338762 progress 10 % (0 MB)
98 00:58:08.364927 progress 15 % (1 MB)
99 00:58:08.387826 progress 20 % (1 MB)
100 00:58:08.410294 progress 25 % (2 MB)
101 00:58:08.432986 progress 30 % (2 MB)
102 00:58:08.457957 progress 35 % (2 MB)
103 00:58:08.480972 progress 40 % (3 MB)
104 00:58:08.502658 progress 45 % (3 MB)
105 00:58:08.526963 progress 50 % (4 MB)
106 00:58:08.551950 progress 55 % (4 MB)
107 00:58:08.575613 progress 60 % (4 MB)
108 00:58:08.598390 progress 65 % (5 MB)
109 00:58:08.623479 progress 70 % (5 MB)
110 00:58:08.646112 progress 75 % (6 MB)
111 00:58:08.670415 progress 80 % (6 MB)
112 00:58:08.693153 progress 85 % (7 MB)
113 00:58:08.717593 progress 90 % (7 MB)
114 00:58:08.742442 progress 95 % (7 MB)
115 00:58:08.767071 progress 100 % (8 MB)
116 00:58:08.772712 8 MB downloaded in 0.48 s (17.14 MB/s)
117 00:58:08.772859 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:58:08.773065 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:58:08.773142 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:58:08.773219 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:58:08.773292 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:58:08.773364 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:58:08.773522 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq
125 00:58:08.773634 makedir: /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin
126 00:58:08.773722 makedir: /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/tests
127 00:58:08.773807 makedir: /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/results
128 00:58:08.773889 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-add-keys
129 00:58:08.774018 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-add-sources
130 00:58:08.774132 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-background-process-start
131 00:58:08.774274 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-background-process-stop
132 00:58:08.774408 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-common-functions
133 00:58:08.774520 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-echo-ipv4
134 00:58:08.774631 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-install-packages
135 00:58:08.774739 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-installed-packages
136 00:58:08.774847 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-os-build
137 00:58:08.774956 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-probe-channel
138 00:58:08.775064 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-probe-ip
139 00:58:08.775173 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-target-ip
140 00:58:08.775282 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-target-mac
141 00:58:08.775389 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-target-storage
142 00:58:08.775499 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-case
143 00:58:08.775609 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-event
144 00:58:08.775715 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-feedback
145 00:58:08.775822 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-raise
146 00:58:08.775929 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-reference
147 00:58:08.776037 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-runner
148 00:58:08.776144 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-set
149 00:58:08.776251 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-test-shell
150 00:58:08.776360 Updating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-install-packages (oe)
151 00:58:08.776523 Updating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/bin/lava-installed-packages (oe)
152 00:58:08.776628 Creating /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/environment
153 00:58:08.776711 LAVA metadata
154 00:58:08.776774 - LAVA_JOB_ID=14368627
155 00:58:08.776828 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:58:08.776915 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:58:08.776970 skipped lava-vland-overlay
158 00:58:08.777034 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:58:08.777103 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:58:08.777155 skipped lava-multinode-overlay
161 00:58:08.777218 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:58:08.777287 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:58:08.777347 Loading test definitions
164 00:58:08.777437 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:58:08.777508 Using /lava-14368627 at stage 0
166 00:58:08.777799 uuid=14368627_1.5.2.3.1 testdef=None
167 00:58:08.777878 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:58:08.777953 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:58:08.778475 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:58:08.778672 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:58:08.779225 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:58:08.779428 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:58:08.780515 runner path: /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/0/tests/0_dmesg test_uuid 14368627_1.5.2.3.1
176 00:58:08.780656 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:58:08.780842 Creating lava-test-runner.conf files
179 00:58:08.780897 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368627/lava-overlay-jj1u0iqq/lava-14368627/0 for stage 0
180 00:58:08.780975 - 0_dmesg
181 00:58:08.781063 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:58:08.781139 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:58:08.787157 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:58:08.787250 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:58:08.787326 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:58:08.787406 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:58:08.787481 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:58:09.014665 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 00:58:09.014816 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 00:58:09.014892 extracting modules file /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368627/extract-overlay-ramdisk-bwux_hep/ramdisk
191 00:58:09.222207 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:58:09.222399 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 00:58:09.222481 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368627/compress-overlay-zui14zw3/overlay-1.5.2.4.tar.gz to ramdisk
194 00:58:09.222542 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368627/compress-overlay-zui14zw3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368627/extract-overlay-ramdisk-bwux_hep/ramdisk
195 00:58:09.228646 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:58:09.228738 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 00:58:09.228815 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:58:09.228891 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 00:58:09.228958 Building ramdisk /var/lib/lava/dispatcher/tmp/14368627/extract-overlay-ramdisk-bwux_hep/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368627/extract-overlay-ramdisk-bwux_hep/ramdisk
200 00:58:09.600158 >> 145187 blocks
201 00:58:11.908985 rename /var/lib/lava/dispatcher/tmp/14368627/extract-overlay-ramdisk-bwux_hep/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/ramdisk/ramdisk.cpio.gz
202 00:58:11.909159 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 00:58:11.909247 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 00:58:11.909326 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 00:58:11.909407 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/kernel/Image']
206 00:58:25.070470 Returned 0 in 13 seconds
207 00:58:25.171328 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/kernel/image.itb
208 00:58:25.649168 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:58:25.649309 output: Created: Sun Jun 16 01:58:25 2024
210 00:58:25.649373 output: Image 0 (kernel-1)
211 00:58:25.649435 output: Description:
212 00:58:25.649495 output: Created: Sun Jun 16 01:58:25 2024
213 00:58:25.649553 output: Type: Kernel Image
214 00:58:25.649611 output: Compression: lzma compressed
215 00:58:25.649672 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
216 00:58:25.649730 output: Architecture: AArch64
217 00:58:25.649785 output: OS: Linux
218 00:58:25.649840 output: Load Address: 0x00000000
219 00:58:25.649896 output: Entry Point: 0x00000000
220 00:58:25.649949 output: Hash algo: crc32
221 00:58:25.650002 output: Hash value: f6f06660
222 00:58:25.650053 output: Image 1 (fdt-1)
223 00:58:25.650103 output: Description: mt8192-asurada-spherion-r0
224 00:58:25.650151 output: Created: Sun Jun 16 01:58:25 2024
225 00:58:25.650201 output: Type: Flat Device Tree
226 00:58:25.650281 output: Compression: uncompressed
227 00:58:25.650344 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:58:25.650392 output: Architecture: AArch64
229 00:58:25.650440 output: Hash algo: crc32
230 00:58:25.650487 output: Hash value: 0f8e4d2e
231 00:58:25.650537 output: Image 2 (ramdisk-1)
232 00:58:25.650584 output: Description: unavailable
233 00:58:25.650631 output: Created: Sun Jun 16 01:58:25 2024
234 00:58:25.650680 output: Type: RAMDisk Image
235 00:58:25.650730 output: Compression: uncompressed
236 00:58:25.650777 output: Data Size: 21373997 Bytes = 20873.04 KiB = 20.38 MiB
237 00:58:25.650825 output: Architecture: AArch64
238 00:58:25.650891 output: OS: Linux
239 00:58:25.650941 output: Load Address: unavailable
240 00:58:25.650990 output: Entry Point: unavailable
241 00:58:25.651037 output: Hash algo: crc32
242 00:58:25.651084 output: Hash value: d17713dd
243 00:58:25.651131 output: Default Configuration: 'conf-1'
244 00:58:25.651179 output: Configuration 0 (conf-1)
245 00:58:25.651227 output: Description: mt8192-asurada-spherion-r0
246 00:58:25.651275 output: Kernel: kernel-1
247 00:58:25.651323 output: Init Ramdisk: ramdisk-1
248 00:58:25.651371 output: FDT: fdt-1
249 00:58:25.651419 output: Loadables: kernel-1
250 00:58:25.651467 output:
251 00:58:25.651604 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:58:25.651690 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:58:25.651777 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 00:58:25.651860 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
255 00:58:25.651927 No LXC device requested
256 00:58:25.652000 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:58:25.652076 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
258 00:58:25.652145 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:58:25.652205 Checking files for TFTP limit of 4294967296 bytes.
260 00:58:25.652642 end: 1 tftp-deploy (duration 00:00:18) [common]
261 00:58:25.652740 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:58:25.652820 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:58:25.652926 substitutions:
264 00:58:25.652984 - {DTB}: 14368627/tftp-deploy-szphy0p4/dtb/mt8192-asurada-spherion-r0.dtb
265 00:58:25.653042 - {INITRD}: 14368627/tftp-deploy-szphy0p4/ramdisk/ramdisk.cpio.gz
266 00:58:25.653094 - {KERNEL}: 14368627/tftp-deploy-szphy0p4/kernel/Image
267 00:58:25.653144 - {LAVA_MAC}: None
268 00:58:25.653193 - {PRESEED_CONFIG}: None
269 00:58:25.653242 - {PRESEED_LOCAL}: None
270 00:58:25.653290 - {RAMDISK}: 14368627/tftp-deploy-szphy0p4/ramdisk/ramdisk.cpio.gz
271 00:58:25.653345 - {ROOT_PART}: None
272 00:58:25.653394 - {ROOT}: None
273 00:58:25.653442 - {SERVER_IP}: 192.168.201.1
274 00:58:25.653490 - {TEE}: None
275 00:58:25.653538 Parsed boot commands:
276 00:58:25.653585 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:58:25.653731 Parsed boot commands: tftpboot 192.168.201.1 14368627/tftp-deploy-szphy0p4/kernel/image.itb 14368627/tftp-deploy-szphy0p4/kernel/cmdline
278 00:58:25.653811 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:58:25.653885 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:58:25.653962 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:58:25.654037 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:58:25.654098 Not connected, no need to disconnect.
283 00:58:25.654164 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:58:25.654242 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:58:25.654342 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 00:58:25.657654 Setting prompt string to ['lava-test: # ']
287 00:58:25.657957 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:58:25.658048 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:58:25.658135 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:58:25.658236 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:58:25.658411 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
292 00:58:39.372440 Returned 0 in 13 seconds
293 00:58:39.472989 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:58:39.473307 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:58:39.473399 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:58:39.473487 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:58:39.473549 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:58:39.473616 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:58:39.473979 [Enter `^Ec?' for help]
301 00:58:39.474058
302 00:58:39.474122
303 00:58:39.474183 F0: 102B 0000
304 00:58:39.474287
305 00:58:39.474349 F3: 1001 0000 [0200]
306 00:58:39.474407
307 00:58:39.474468 F3: 1001 0000
308 00:58:39.474527
309 00:58:39.474582 F7: 102D 0000
310 00:58:39.474636
311 00:58:39.474687 F1: 0000 0000
312 00:58:39.474738
313 00:58:39.474790 V0: 0000 0000 [0001]
314 00:58:39.474839
315 00:58:39.474887 00: 0007 8000
316 00:58:39.474937
317 00:58:39.474986 01: 0000 0000
318 00:58:39.475036
319 00:58:39.475084 BP: 0C00 0209 [0000]
320 00:58:39.475132
321 00:58:39.475182 G0: 1182 0000
322 00:58:39.475230
323 00:58:39.475278 EC: 0000 0021 [4000]
324 00:58:39.475326
325 00:58:39.475374 S7: 0000 0000 [0000]
326 00:58:39.475422
327 00:58:39.475470 CC: 0000 0000 [0001]
328 00:58:39.475518
329 00:58:39.475567 T0: 0000 0040 [010F]
330 00:58:39.475615
331 00:58:39.475663 Jump to BL
332 00:58:39.475711
333 00:58:39.475759
334 00:58:39.475808
335 00:58:39.475857 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:58:39.475909 ARM64: Exception handlers installed.
337 00:58:39.475959 ARM64: Testing exception
338 00:58:39.476009 ARM64: Done test exception
339 00:58:39.476058 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:58:39.476108 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:58:39.476157 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:58:39.476206 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:58:39.476256 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:58:39.476305 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:58:39.476354 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:58:39.476404 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:58:39.476453 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:58:39.476502 WDT: Last reset was cold boot
349 00:58:39.476551 SPI1(PAD0) initialized at 2873684 Hz
350 00:58:39.476606 SPI5(PAD0) initialized at 992727 Hz
351 00:58:39.476655 VBOOT: Loading verstage.
352 00:58:39.476704 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:58:39.476753 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:58:39.476803 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:58:39.476853 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:58:39.476902 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:58:39.476952 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:58:39.477002 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 00:58:39.477087
360 00:58:39.477189
361 00:58:39.477252 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:58:39.477302 ARM64: Exception handlers installed.
363 00:58:39.477351 ARM64: Testing exception
364 00:58:39.477399 ARM64: Done test exception
365 00:58:39.477448 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:58:39.477497 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:58:39.477546 Probing TPM: . done!
368 00:58:39.477594 TPM ready after 0 ms
369 00:58:39.477644 Connected to device vid:did:rid of 1ae0:0028:00
370 00:58:39.477692 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
371 00:58:39.477742 Initialized TPM device CR50 revision 0
372 00:58:39.477791 tlcl_send_startup: Startup return code is 0
373 00:58:39.477839 TPM: setup succeeded
374 00:58:39.477888 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:58:39.477937 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:58:39.477986 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:58:39.478035 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:58:39.478084 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:58:39.478133 in-header: 03 07 00 00 08 00 00 00
380 00:58:39.478180 in-data: aa e4 47 04 13 02 00 00
381 00:58:39.478278 Chrome EC: UHEPI supported
382 00:58:39.478329 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:58:39.478379 in-header: 03 a9 00 00 08 00 00 00
384 00:58:39.478428 in-data: 84 60 60 08 00 00 00 00
385 00:58:39.478477 Phase 1
386 00:58:39.478526 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:58:39.478576 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:58:39.478625 VB2:vb2_check_recovery() Recovery was requested manually
389 00:58:39.478674 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:58:39.478723 Recovery requested (1009000e)
391 00:58:39.478772 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:58:39.478822 tlcl_extend: response is 0
393 00:58:39.478901 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:58:39.478950 tlcl_extend: response is 0
395 00:58:39.479028 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:58:39.479077 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:58:39.479126 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:58:39.479205
399 00:58:39.479282
400 00:58:39.479330 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:58:39.479409 ARM64: Exception handlers installed.
402 00:58:39.479458 ARM64: Testing exception
403 00:58:39.479506 ARM64: Done test exception
404 00:58:39.479555 pmic_efuse_setting: Set efuses in 11 msecs
405 00:58:39.479635 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:58:39.479684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:58:39.479781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:58:39.480024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:58:39.480085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:58:39.480150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:58:39.480199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:58:39.480248 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:58:39.480312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:58:39.480377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:58:39.480427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:58:39.480491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:58:39.480554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:58:39.480603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:58:39.480652 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:58:39.480718 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:58:39.480783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:58:39.480832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:58:39.480881 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:58:39.480931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:58:39.480980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:58:39.481029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:58:39.481078 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:58:39.481127 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:58:39.481175 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:58:39.481224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:58:39.481273 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:58:39.481322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:58:39.481372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:58:39.481421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:58:39.481470 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:58:39.481519 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:58:39.481568 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:58:39.481617 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:58:39.481667 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:58:39.481716 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:58:39.481764 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:58:39.481814 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:58:39.481863 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:58:39.481911 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:58:39.481960 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:58:39.482009 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:58:39.482058 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:58:39.482107 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:58:39.482156 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:58:39.482204 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:58:39.482292 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:58:39.482341 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:58:39.482390 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:58:39.482452 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:58:39.482614 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:58:39.482712 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:58:39.482785 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:58:39.482851 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:58:39.482901 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:58:39.482951 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:58:39.483015 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:58:39.483080 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:58:39.483129 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:58:39.483178 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:58:39.483256 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
466 00:58:39.483305 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:58:39.483354 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 00:58:39.483403 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:58:39.483453 [RTC]rtc_get_frequency_meter,154: input=15, output=764
470 00:58:39.483502 [RTC]rtc_get_frequency_meter,154: input=23, output=948
471 00:58:39.483551 [RTC]rtc_get_frequency_meter,154: input=19, output=857
472 00:58:39.483601 [RTC]rtc_get_frequency_meter,154: input=17, output=810
473 00:58:39.483650 [RTC]rtc_get_frequency_meter,154: input=16, output=787
474 00:58:39.483699 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 00:58:39.483748 [RTC]rtc_get_frequency_meter,154: input=17, output=810
476 00:58:39.483797 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 00:58:39.483845 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 00:58:39.484081 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:58:39.484155 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:58:39.484220 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:58:39.484269 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:58:39.484318 ADC[4]: Raw value=669695 ID=5
483 00:58:39.484382 ADC[3]: Raw value=212917 ID=1
484 00:58:39.484446 RAM Code: 0x51
485 00:58:39.484494 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:58:39.484559 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:58:39.484622 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 00:58:39.484671 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 00:58:39.484735 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:58:39.484797 in-header: 03 07 00 00 08 00 00 00
491 00:58:39.484846 in-data: aa e4 47 04 13 02 00 00
492 00:58:39.484910 Chrome EC: UHEPI supported
493 00:58:39.484959 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:58:39.485009 in-header: 03 a9 00 00 08 00 00 00
495 00:58:39.485058 in-data: 84 60 60 08 00 00 00 00
496 00:58:39.485108 MRC: failed to locate region type 0.
497 00:58:39.485158 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:58:39.485221 DRAM-K: Running full calibration
499 00:58:39.485284 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 00:58:39.485347 header.status = 0x0
501 00:58:39.485396 header.version = 0x6 (expected: 0x6)
502 00:58:39.485444 header.size = 0xd00 (expected: 0xd00)
503 00:58:39.485494 header.flags = 0x0
504 00:58:39.485543 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:58:39.485592 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 00:58:39.485641 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:58:39.485690 dram_init: ddr_geometry: 0
508 00:58:39.485739 [EMI] MDL number = 0
509 00:58:39.485787 [EMI] Get MDL freq = 0
510 00:58:39.485836 dram_init: ddr_type: 0
511 00:58:39.485887 is_discrete_lpddr4: 1
512 00:58:39.485935 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:58:39.485984
514 00:58:39.486032
515 00:58:39.486080 [Bian_co] ETT version 0.0.0.1
516 00:58:39.486128 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 00:58:39.486177
518 00:58:39.486269 dramc_set_vcore_voltage set vcore to 650000
519 00:58:39.486321 Read voltage for 800, 4
520 00:58:39.486370 Vio18 = 0
521 00:58:39.486418 Vcore = 650000
522 00:58:39.486467 Vdram = 0
523 00:58:39.486515 Vddq = 0
524 00:58:39.486579 Vmddr = 0
525 00:58:39.486642 dram_init: config_dvfs: 1
526 00:58:39.486690 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:58:39.486753 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:58:39.486817 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 00:58:39.486866 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 00:58:39.486915 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 00:58:39.486963 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 00:58:39.487012 MEM_TYPE=3, freq_sel=18
533 00:58:39.487061 sv_algorithm_assistance_LP4_1600
534 00:58:39.487109 ============ PULL DRAM RESETB DOWN ============
535 00:58:39.487206 ========== PULL DRAM RESETB DOWN end =========
536 00:58:39.487256 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:58:39.487305 ===================================
538 00:58:39.487354 LPDDR4 DRAM CONFIGURATION
539 00:58:39.487403 ===================================
540 00:58:39.487452 EX_ROW_EN[0] = 0x0
541 00:58:39.487500 EX_ROW_EN[1] = 0x0
542 00:58:39.487548 LP4Y_EN = 0x0
543 00:58:39.487614 WORK_FSP = 0x0
544 00:58:39.487676 WL = 0x2
545 00:58:39.487724 RL = 0x2
546 00:58:39.487787 BL = 0x2
547 00:58:39.487849 RPST = 0x0
548 00:58:39.487897 RD_PRE = 0x0
549 00:58:39.487944 WR_PRE = 0x1
550 00:58:39.487991 WR_PST = 0x0
551 00:58:39.488071 DBI_WR = 0x0
552 00:58:39.488118 DBI_RD = 0x0
553 00:58:39.488167 OTF = 0x1
554 00:58:39.488215 ===================================
555 00:58:39.488264 ===================================
556 00:58:39.488312 ANA top config
557 00:58:39.488360 ===================================
558 00:58:39.488409 DLL_ASYNC_EN = 0
559 00:58:39.488457 ALL_SLAVE_EN = 1
560 00:58:39.488506 NEW_RANK_MODE = 1
561 00:58:39.488554 DLL_IDLE_MODE = 1
562 00:58:39.488632 LP45_APHY_COMB_EN = 1
563 00:58:39.488680 TX_ODT_DIS = 1
564 00:58:39.488743 NEW_8X_MODE = 1
565 00:58:39.488806 ===================================
566 00:58:39.488854 ===================================
567 00:58:39.488916 data_rate = 1600
568 00:58:39.488995 CKR = 1
569 00:58:39.489044 DQ_P2S_RATIO = 8
570 00:58:39.489093 ===================================
571 00:58:39.489186 CA_P2S_RATIO = 8
572 00:58:39.489233 DQ_CA_OPEN = 0
573 00:58:39.489296 DQ_SEMI_OPEN = 0
574 00:58:39.489358 CA_SEMI_OPEN = 0
575 00:58:39.489406 CA_FULL_RATE = 0
576 00:58:39.489454 DQ_CKDIV4_EN = 1
577 00:58:39.489502 CA_CKDIV4_EN = 1
578 00:58:39.489580 CA_PREDIV_EN = 0
579 00:58:39.489628 PH8_DLY = 0
580 00:58:39.489676 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:58:39.489754 DQ_AAMCK_DIV = 4
582 00:58:39.489803 CA_AAMCK_DIV = 4
583 00:58:39.489851 CA_ADMCK_DIV = 4
584 00:58:39.489898 DQ_TRACK_CA_EN = 0
585 00:58:39.489945 CA_PICK = 800
586 00:58:39.489994 CA_MCKIO = 800
587 00:58:39.490043 MCKIO_SEMI = 0
588 00:58:39.490106 PLL_FREQ = 3068
589 00:58:39.490156 DQ_UI_PI_RATIO = 32
590 00:58:39.490205 CA_UI_PI_RATIO = 0
591 00:58:39.490279 ===================================
592 00:58:39.490328 ===================================
593 00:58:39.490377 memory_type:LPDDR4
594 00:58:39.490425 GP_NUM : 10
595 00:58:39.490473 SRAM_EN : 1
596 00:58:39.490521 MD32_EN : 0
597 00:58:39.490570 ===================================
598 00:58:39.490844 [ANA_INIT] >>>>>>>>>>>>>>
599 00:58:39.490989 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:58:39.491093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:58:39.491150 ===================================
602 00:58:39.491229 data_rate = 1600,PCW = 0X7600
603 00:58:39.491278 ===================================
604 00:58:39.491327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:58:39.491376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:58:39.491425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:58:39.491475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:58:39.491555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:58:39.491632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:58:39.491682 [ANA_INIT] flow start
611 00:58:39.491731 [ANA_INIT] PLL >>>>>>>>
612 00:58:39.491780 [ANA_INIT] PLL <<<<<<<<
613 00:58:39.491828 [ANA_INIT] MIDPI >>>>>>>>
614 00:58:39.491876 [ANA_INIT] MIDPI <<<<<<<<
615 00:58:39.491925 [ANA_INIT] DLL >>>>>>>>
616 00:58:39.491973 [ANA_INIT] flow end
617 00:58:39.492022 ============ LP4 DIFF to SE enter ============
618 00:58:39.492071 ============ LP4 DIFF to SE exit ============
619 00:58:39.492120 [ANA_INIT] <<<<<<<<<<<<<
620 00:58:39.492169 [Flow] Enable top DCM control >>>>>
621 00:58:39.492218 [Flow] Enable top DCM control <<<<<
622 00:58:39.492297 Enable DLL master slave shuffle
623 00:58:39.492346 ==============================================================
624 00:58:39.492409 Gating Mode config
625 00:58:39.492475 ==============================================================
626 00:58:39.492524 Config description:
627 00:58:39.492572 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:58:39.492651 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:58:39.492700 SELPH_MODE 0: By rank 1: By Phase
630 00:58:39.492749 ==============================================================
631 00:58:39.492797 GAT_TRACK_EN = 1
632 00:58:39.492846 RX_GATING_MODE = 2
633 00:58:39.492893 RX_GATING_TRACK_MODE = 2
634 00:58:39.492942 SELPH_MODE = 1
635 00:58:39.493006 PICG_EARLY_EN = 1
636 00:58:39.493068 VALID_LAT_VALUE = 1
637 00:58:39.493117 ==============================================================
638 00:58:39.493166 Enter into Gating configuration >>>>
639 00:58:39.493230 Exit from Gating configuration <<<<
640 00:58:39.493280 Enter into DVFS_PRE_config >>>>>
641 00:58:39.493342 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:58:39.493395 Exit from DVFS_PRE_config <<<<<
643 00:58:39.493444 Enter into PICG configuration >>>>
644 00:58:39.493492 Exit from PICG configuration <<<<
645 00:58:39.493540 [RX_INPUT] configuration >>>>>
646 00:58:39.493620 [RX_INPUT] configuration <<<<<
647 00:58:39.493668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:58:39.493734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:58:39.493839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:58:39.493904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:58:39.493954 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:58:39.494005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:58:39.494055 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:58:39.494104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:58:39.494154 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:58:39.494204 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:58:39.494280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:58:39.494330 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:58:39.494379 ===================================
660 00:58:39.494428 LPDDR4 DRAM CONFIGURATION
661 00:58:39.494477 ===================================
662 00:58:39.494556 EX_ROW_EN[0] = 0x0
663 00:58:39.494605 EX_ROW_EN[1] = 0x0
664 00:58:39.494653 LP4Y_EN = 0x0
665 00:58:39.494702 WORK_FSP = 0x0
666 00:58:39.494751 WL = 0x2
667 00:58:39.494799 RL = 0x2
668 00:58:39.494847 BL = 0x2
669 00:58:39.494895 RPST = 0x0
670 00:58:39.494943 RD_PRE = 0x0
671 00:58:39.494991 WR_PRE = 0x1
672 00:58:39.495040 WR_PST = 0x0
673 00:58:39.495088 DBI_WR = 0x0
674 00:58:39.495137 DBI_RD = 0x0
675 00:58:39.495185 OTF = 0x1
676 00:58:39.495233 ===================================
677 00:58:39.495282 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:58:39.495331 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:58:39.495396 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:58:39.495460 ===================================
681 00:58:39.495509 LPDDR4 DRAM CONFIGURATION
682 00:58:39.495557 ===================================
683 00:58:39.495624 EX_ROW_EN[0] = 0x10
684 00:58:39.495686 EX_ROW_EN[1] = 0x0
685 00:58:39.495735 LP4Y_EN = 0x0
686 00:58:39.495783 WORK_FSP = 0x0
687 00:58:39.495831 WL = 0x2
688 00:58:39.495879 RL = 0x2
689 00:58:39.495928 BL = 0x2
690 00:58:39.495977 RPST = 0x0
691 00:58:39.496025 RD_PRE = 0x0
692 00:58:39.496072 WR_PRE = 0x1
693 00:58:39.496120 WR_PST = 0x0
694 00:58:39.496169 DBI_WR = 0x0
695 00:58:39.496217 DBI_RD = 0x0
696 00:58:39.496265 OTF = 0x1
697 00:58:39.496312 ===================================
698 00:58:39.496361 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:58:39.496410 nWR fixed to 40
700 00:58:39.496459 [ModeRegInit_LP4] CH0 RK0
701 00:58:39.496508 [ModeRegInit_LP4] CH0 RK1
702 00:58:39.496556 [ModeRegInit_LP4] CH1 RK0
703 00:58:39.496604 [ModeRegInit_LP4] CH1 RK1
704 00:58:39.496652 match AC timing 12
705 00:58:39.496701 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 00:58:39.496750 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:58:39.497080 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:58:39.497199 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:58:39.497277 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:58:39.497372 [EMI DOE] emi_dcm 0
711 00:58:39.497423 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:58:39.497503 ==
713 00:58:39.497569 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:58:39.497633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 00:58:39.497711 ==
716 00:58:39.497760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:58:39.497809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:58:39.497874 [CA 0] Center 37 (7~68) winsize 62
719 00:58:39.497938 [CA 1] Center 37 (7~68) winsize 62
720 00:58:39.498001 [CA 2] Center 35 (5~66) winsize 62
721 00:58:39.498057 [CA 3] Center 35 (4~66) winsize 63
722 00:58:39.498137 [CA 4] Center 34 (4~65) winsize 62
723 00:58:39.498223 [CA 5] Center 33 (3~64) winsize 62
724 00:58:39.498278
725 00:58:39.498328 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 00:58:39.498379
727 00:58:39.498429 [CATrainingPosCal] consider 1 rank data
728 00:58:39.498479 u2DelayCellTimex100 = 270/100 ps
729 00:58:39.498529 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 00:58:39.498579 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 00:58:39.498642 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 00:58:39.498690 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
733 00:58:39.498739 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 00:58:39.498787 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:58:39.498835
736 00:58:39.498884 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:58:39.498932
738 00:58:39.498979 [CBTSetCACLKResult] CA Dly = 33
739 00:58:39.499028 CS Dly: 6 (0~37)
740 00:58:39.499076 ==
741 00:58:39.499125 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:58:39.499174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 00:58:39.499223 ==
744 00:58:39.499271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:58:39.499320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:58:39.499369 [CA 0] Center 37 (6~68) winsize 63
747 00:58:39.499443 [CA 1] Center 37 (6~68) winsize 63
748 00:58:39.499505 [CA 2] Center 35 (4~66) winsize 63
749 00:58:39.499554 [CA 3] Center 34 (4~65) winsize 62
750 00:58:39.499603 [CA 4] Center 33 (3~64) winsize 62
751 00:58:39.499683 [CA 5] Center 33 (3~64) winsize 62
752 00:58:39.499731
753 00:58:39.499780 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:58:39.499829
755 00:58:39.499877 [CATrainingPosCal] consider 2 rank data
756 00:58:39.499926 u2DelayCellTimex100 = 270/100 ps
757 00:58:39.499975 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 00:58:39.500024 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:58:39.500073 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 00:58:39.500122 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:58:39.500171 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
762 00:58:39.500219 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:58:39.500268
764 00:58:39.500316 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:58:39.500365
766 00:58:39.500413 [CBTSetCACLKResult] CA Dly = 33
767 00:58:39.500461 CS Dly: 6 (0~38)
768 00:58:39.500509
769 00:58:39.500557 ----->DramcWriteLeveling(PI) begin...
770 00:58:39.500609 ==
771 00:58:39.500658 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:58:39.500706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 00:58:39.500755 ==
774 00:58:39.500803 Write leveling (Byte 0): 29 => 29
775 00:58:39.500852 Write leveling (Byte 1): 28 => 28
776 00:58:39.500900 DramcWriteLeveling(PI) end<-----
777 00:58:39.500948
778 00:58:39.500996 ==
779 00:58:39.501045 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:58:39.501094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 00:58:39.501142 ==
782 00:58:39.501190 [Gating] SW mode calibration
783 00:58:39.501239 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:58:39.501289 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:58:39.501338 0 6 0 | B1->B0 | 3333 3232 | 0 1 | (0 0) (1 0)
786 00:58:39.501387 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
787 00:58:39.501435 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:58:39.501484 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:58:39.501533 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:58:39.501581 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:58:39.501629 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:58:39.501737 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:58:39.501877 0 7 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
794 00:58:39.501971 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
795 00:58:39.502050 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 00:58:39.502128 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 00:58:39.502205 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 00:58:39.502300 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 00:58:39.502350 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 00:58:39.502398 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 00:58:39.502447 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 00:58:39.502496 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
803 00:58:39.502547 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 00:58:39.502596 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 00:58:39.502645 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 00:58:39.502693 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 00:58:39.502742 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 00:58:39.502791 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 00:58:39.502840 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 00:58:39.502889 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 00:58:39.502938 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 00:58:39.502987 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 00:58:39.503036 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 00:58:39.503287 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 00:58:39.503344 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 00:58:39.503410 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 00:58:39.503474 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
818 00:58:39.503523 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 00:58:39.503573 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 00:58:39.503650 Total UI for P1: 0, mck2ui 16
821 00:58:39.503699 best dqsien dly found for B0: ( 0, 10, 2)
822 00:58:39.503748 Total UI for P1: 0, mck2ui 16
823 00:58:39.503826 best dqsien dly found for B1: ( 0, 10, 2)
824 00:58:39.503875 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 00:58:39.503924 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
826 00:58:39.504004
827 00:58:39.504053 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 00:58:39.504102 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 00:58:39.504166 [Gating] SW calibration Done
830 00:58:39.504272 ==
831 00:58:39.504352 Dram Type= 6, Freq= 0, CH_0, rank 0
832 00:58:39.504451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 00:58:39.504500 ==
834 00:58:39.504549 RX Vref Scan: 0
835 00:58:39.504612
836 00:58:39.504675 RX Vref 0 -> 0, step: 1
837 00:58:39.504722
838 00:58:39.504770 RX Delay -130 -> 252, step: 16
839 00:58:39.504819 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 00:58:39.504867 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 00:58:39.504916 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 00:58:39.504964 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 00:58:39.505013 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 00:58:39.505061 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 00:58:39.505110 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 00:58:39.505158 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 00:58:39.505206 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 00:58:39.505255 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 00:58:39.505302 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 00:58:39.505351 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 00:58:39.505399 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 00:58:39.505447 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
853 00:58:39.505495 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 00:58:39.505544 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 00:58:39.505591 ==
856 00:58:39.505639 Dram Type= 6, Freq= 0, CH_0, rank 0
857 00:58:39.505688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 00:58:39.505736 ==
859 00:58:39.505783 DQS Delay:
860 00:58:39.505831 DQS0 = 0, DQS1 = 0
861 00:58:39.505879 DQM Delay:
862 00:58:39.505927 DQM0 = 82, DQM1 = 73
863 00:58:39.505975 DQ Delay:
864 00:58:39.506023 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 00:58:39.506071 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 00:58:39.506119 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 00:58:39.506168 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
868 00:58:39.506243
869 00:58:39.506341
870 00:58:39.506405 ==
871 00:58:39.506469 Dram Type= 6, Freq= 0, CH_0, rank 0
872 00:58:39.506518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 00:58:39.506567 ==
874 00:58:39.506631
875 00:58:39.506695
876 00:58:39.506746 TX Vref Scan disable
877 00:58:39.506795 == TX Byte 0 ==
878 00:58:39.506875 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
879 00:58:39.506923 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
880 00:58:39.507001 == TX Byte 1 ==
881 00:58:39.507050 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
882 00:58:39.507099 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
883 00:58:39.507147 ==
884 00:58:39.507225 Dram Type= 6, Freq= 0, CH_0, rank 0
885 00:58:39.507273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 00:58:39.507322 ==
887 00:58:39.507370 TX Vref=22, minBit 0, minWin=27, winSum=445
888 00:58:39.507450 TX Vref=24, minBit 2, minWin=27, winSum=446
889 00:58:39.507499 TX Vref=26, minBit 4, minWin=27, winSum=451
890 00:58:39.507565 TX Vref=28, minBit 4, minWin=27, winSum=455
891 00:58:39.507627 TX Vref=30, minBit 0, minWin=28, winSum=454
892 00:58:39.507676 TX Vref=32, minBit 0, minWin=28, winSum=455
893 00:58:39.507724 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
894 00:58:39.507773
895 00:58:39.507821 Final TX Range 1 Vref 32
896 00:58:39.507869
897 00:58:39.507944 ==
898 00:58:39.508008 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:58:39.508056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 00:58:39.508120 ==
901 00:58:39.508183
902 00:58:39.508231
903 00:58:39.508279 TX Vref Scan disable
904 00:58:39.508358 == TX Byte 0 ==
905 00:58:39.508407 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
906 00:58:39.508455 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
907 00:58:39.508532 == TX Byte 1 ==
908 00:58:39.508580 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
909 00:58:39.508629 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
910 00:58:39.508707
911 00:58:39.508754 [DATLAT]
912 00:58:39.508802 Freq=800, CH0 RK0
913 00:58:39.508850
914 00:58:39.508898 DATLAT Default: 0xa
915 00:58:39.508946 0, 0xFFFF, sum = 0
916 00:58:39.508995 1, 0xFFFF, sum = 0
917 00:58:39.509045 2, 0xFFFF, sum = 0
918 00:58:39.509094 3, 0xFFFF, sum = 0
919 00:58:39.509145 4, 0xFFFF, sum = 0
920 00:58:39.509195 5, 0xFFFF, sum = 0
921 00:58:39.509244 6, 0xFFFF, sum = 0
922 00:58:39.509293 7, 0xFFFF, sum = 0
923 00:58:39.509342 8, 0x0, sum = 1
924 00:58:39.509391 9, 0x0, sum = 2
925 00:58:39.509440 10, 0x0, sum = 3
926 00:58:39.509489 11, 0x0, sum = 4
927 00:58:39.509538 best_step = 9
928 00:58:39.509587
929 00:58:39.509635 ==
930 00:58:39.509683 Dram Type= 6, Freq= 0, CH_0, rank 0
931 00:58:39.509731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 00:58:39.509780 ==
933 00:58:39.509827 RX Vref Scan: 1
934 00:58:39.509906
935 00:58:39.509954 Set Vref Range= 32 -> 127
936 00:58:39.510003
937 00:58:39.510051 RX Vref 32 -> 127, step: 1
938 00:58:39.510115
939 00:58:39.510164 RX Delay -111 -> 252, step: 8
940 00:58:39.510219
941 00:58:39.510284 Set Vref, RX VrefLevel [Byte0]: 32
942 00:58:39.510333 [Byte1]: 32
943 00:58:39.510381
944 00:58:39.510428 Set Vref, RX VrefLevel [Byte0]: 33
945 00:58:39.510476 [Byte1]: 33
946 00:58:39.510525
947 00:58:39.510573 Set Vref, RX VrefLevel [Byte0]: 34
948 00:58:39.510621 [Byte1]: 34
949 00:58:39.510670
950 00:58:39.510717 Set Vref, RX VrefLevel [Byte0]: 35
951 00:58:39.510765 [Byte1]: 35
952 00:58:39.510813
953 00:58:39.510861 Set Vref, RX VrefLevel [Byte0]: 36
954 00:58:39.510909 [Byte1]: 36
955 00:58:39.510956
956 00:58:39.511004 Set Vref, RX VrefLevel [Byte0]: 37
957 00:58:39.511053 [Byte1]: 37
958 00:58:39.511102
959 00:58:39.511150 Set Vref, RX VrefLevel [Byte0]: 38
960 00:58:39.511198 [Byte1]: 38
961 00:58:39.511245
962 00:58:39.511293 Set Vref, RX VrefLevel [Byte0]: 39
963 00:58:39.511547 [Byte1]: 39
964 00:58:39.511616
965 00:58:39.511666 Set Vref, RX VrefLevel [Byte0]: 40
966 00:58:39.511732 [Byte1]: 40
967 00:58:39.511781
968 00:58:39.511844 Set Vref, RX VrefLevel [Byte0]: 41
969 00:58:39.511908 [Byte1]: 41
970 00:58:39.511958
971 00:58:39.512006 Set Vref, RX VrefLevel [Byte0]: 42
972 00:58:39.512056 [Byte1]: 42
973 00:58:39.512118
974 00:58:39.512167 Set Vref, RX VrefLevel [Byte0]: 43
975 00:58:39.512215 [Byte1]: 43
976 00:58:39.512264
977 00:58:39.512312 Set Vref, RX VrefLevel [Byte0]: 44
978 00:58:39.512360 [Byte1]: 44
979 00:58:39.512408
980 00:58:39.512501 Set Vref, RX VrefLevel [Byte0]: 45
981 00:58:39.512565 [Byte1]: 45
982 00:58:39.512613
983 00:58:39.512660 Set Vref, RX VrefLevel [Byte0]: 46
984 00:58:39.512709 [Byte1]: 46
985 00:58:39.512758
986 00:58:39.512806 Set Vref, RX VrefLevel [Byte0]: 47
987 00:58:39.512855 [Byte1]: 47
988 00:58:39.512903
989 00:58:39.512951 Set Vref, RX VrefLevel [Byte0]: 48
990 00:58:39.512999 [Byte1]: 48
991 00:58:39.513090
992 00:58:39.513137 Set Vref, RX VrefLevel [Byte0]: 49
993 00:58:39.513185 [Byte1]: 49
994 00:58:39.513233
995 00:58:39.513280 Set Vref, RX VrefLevel [Byte0]: 50
996 00:58:39.513329 [Byte1]: 50
997 00:58:39.513377
998 00:58:39.513425 Set Vref, RX VrefLevel [Byte0]: 51
999 00:58:39.513473 [Byte1]: 51
1000 00:58:39.513521
1001 00:58:39.513569 Set Vref, RX VrefLevel [Byte0]: 52
1002 00:58:39.513617 [Byte1]: 52
1003 00:58:39.513664
1004 00:58:39.513711 Set Vref, RX VrefLevel [Byte0]: 53
1005 00:58:39.513759 [Byte1]: 53
1006 00:58:39.513807
1007 00:58:39.513855 Set Vref, RX VrefLevel [Byte0]: 54
1008 00:58:39.513904 [Byte1]: 54
1009 00:58:39.513953
1010 00:58:39.514001 Set Vref, RX VrefLevel [Byte0]: 55
1011 00:58:39.514051 [Byte1]: 55
1012 00:58:39.514100
1013 00:58:39.514147 Set Vref, RX VrefLevel [Byte0]: 56
1014 00:58:39.514196 [Byte1]: 56
1015 00:58:39.514290
1016 00:58:39.514340 Set Vref, RX VrefLevel [Byte0]: 57
1017 00:58:39.514390 [Byte1]: 57
1018 00:58:39.514438
1019 00:58:39.514486 Set Vref, RX VrefLevel [Byte0]: 58
1020 00:58:39.514535 [Byte1]: 58
1021 00:58:39.514584
1022 00:58:39.514635 Set Vref, RX VrefLevel [Byte0]: 59
1023 00:58:39.514684 [Byte1]: 59
1024 00:58:39.514732
1025 00:58:39.514780 Set Vref, RX VrefLevel [Byte0]: 60
1026 00:58:39.514828 [Byte1]: 60
1027 00:58:39.514877
1028 00:58:39.514924 Set Vref, RX VrefLevel [Byte0]: 61
1029 00:58:39.514972 [Byte1]: 61
1030 00:58:39.515020
1031 00:58:39.515068 Set Vref, RX VrefLevel [Byte0]: 62
1032 00:58:39.515116 [Byte1]: 62
1033 00:58:39.515164
1034 00:58:39.515212 Set Vref, RX VrefLevel [Byte0]: 63
1035 00:58:39.515261 [Byte1]: 63
1036 00:58:39.515309
1037 00:58:39.515357 Set Vref, RX VrefLevel [Byte0]: 64
1038 00:58:39.515405 [Byte1]: 64
1039 00:58:39.515453
1040 00:58:39.515501 Set Vref, RX VrefLevel [Byte0]: 65
1041 00:58:39.515550 [Byte1]: 65
1042 00:58:39.515598
1043 00:58:39.515645 Set Vref, RX VrefLevel [Byte0]: 66
1044 00:58:39.515693 [Byte1]: 66
1045 00:58:39.515741
1046 00:58:39.515789 Set Vref, RX VrefLevel [Byte0]: 67
1047 00:58:39.515837 [Byte1]: 67
1048 00:58:39.515885
1049 00:58:39.515933 Set Vref, RX VrefLevel [Byte0]: 68
1050 00:58:39.515981 [Byte1]: 68
1051 00:58:39.516030
1052 00:58:39.516077 Set Vref, RX VrefLevel [Byte0]: 69
1053 00:58:39.516125 [Byte1]: 69
1054 00:58:39.516173
1055 00:58:39.516221 Set Vref, RX VrefLevel [Byte0]: 70
1056 00:58:39.516270 [Byte1]: 70
1057 00:58:39.516318
1058 00:58:39.516366 Set Vref, RX VrefLevel [Byte0]: 71
1059 00:58:39.516415 [Byte1]: 71
1060 00:58:39.516463
1061 00:58:39.516511 Set Vref, RX VrefLevel [Byte0]: 72
1062 00:58:39.516558 [Byte1]: 72
1063 00:58:39.516606
1064 00:58:39.516653 Set Vref, RX VrefLevel [Byte0]: 73
1065 00:58:39.516701 [Byte1]: 73
1066 00:58:39.516750
1067 00:58:39.516797 Set Vref, RX VrefLevel [Byte0]: 74
1068 00:58:39.516845 [Byte1]: 74
1069 00:58:39.516893
1070 00:58:39.516941 Set Vref, RX VrefLevel [Byte0]: 75
1071 00:58:39.516990 [Byte1]: 75
1072 00:58:39.517038
1073 00:58:39.517085 Final RX Vref Byte 0 = 53 to rank0
1074 00:58:39.517133 Final RX Vref Byte 1 = 55 to rank0
1075 00:58:39.517181 Final RX Vref Byte 0 = 53 to rank1
1076 00:58:39.517230 Final RX Vref Byte 1 = 55 to rank1==
1077 00:58:39.517278 Dram Type= 6, Freq= 0, CH_0, rank 0
1078 00:58:39.517327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1079 00:58:39.517376 ==
1080 00:58:39.517425 DQS Delay:
1081 00:58:39.517473 DQS0 = 0, DQS1 = 0
1082 00:58:39.517521 DQM Delay:
1083 00:58:39.517568 DQM0 = 83, DQM1 = 73
1084 00:58:39.517617 DQ Delay:
1085 00:58:39.517665 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1086 00:58:39.517715 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1087 00:58:39.517763 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1088 00:58:39.517811 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1089 00:58:39.517859
1090 00:58:39.517907
1091 00:58:39.517977 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1092 00:58:39.518056 CH0 RK0: MR19=606, MR18=3E3E
1093 00:58:39.518135 CH0_RK0: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1094 00:58:39.518237
1095 00:58:39.518292 ----->DramcWriteLeveling(PI) begin...
1096 00:58:39.518357 ==
1097 00:58:39.518406 Dram Type= 6, Freq= 0, CH_0, rank 1
1098 00:58:39.518504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1099 00:58:39.518586 ==
1100 00:58:39.518668 Write leveling (Byte 0): 31 => 31
1101 00:58:39.518733 Write leveling (Byte 1): 31 => 31
1102 00:58:39.518782 DramcWriteLeveling(PI) end<-----
1103 00:58:39.518830
1104 00:58:39.518878 ==
1105 00:58:39.518926 Dram Type= 6, Freq= 0, CH_0, rank 1
1106 00:58:39.518974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1107 00:58:39.519023 ==
1108 00:58:39.519109 [Gating] SW mode calibration
1109 00:58:39.519157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1110 00:58:39.519206 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1111 00:58:39.519291 0 6 0 | B1->B0 | 3030 3030 | 1 1 | (1 0) (1 0)
1112 00:58:39.519340 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
1113 00:58:39.519389 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 00:58:39.519641 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 00:58:39.519699 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 00:58:39.519749 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 00:58:39.519798 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 00:58:39.519847 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 00:58:39.519896 0 7 0 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
1120 00:58:39.519944 0 7 4 | B1->B0 | 3f3f 4545 | 1 0 | (0 0) (0 0)
1121 00:58:39.519994 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 00:58:39.520042 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 00:58:39.520091 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 00:58:39.520139 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 00:58:39.520187 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 00:58:39.520235 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 00:58:39.520284 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1128 00:58:39.520333 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 00:58:39.520410 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 00:58:39.520458 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 00:58:39.520506 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 00:58:39.520553 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 00:58:39.520639 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 00:58:39.520687 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 00:58:39.520735 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 00:58:39.520784 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 00:58:39.520833 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 00:58:39.520881 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 00:58:39.520954 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 00:58:39.521017 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 00:58:39.521064 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 00:58:39.521135 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 00:58:39.521198 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1144 00:58:39.521247 Total UI for P1: 0, mck2ui 16
1145 00:58:39.521316 best dqsien dly found for B0: ( 0, 9, 30)
1146 00:58:39.521378 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1147 00:58:39.521426 Total UI for P1: 0, mck2ui 16
1148 00:58:39.521475 best dqsien dly found for B1: ( 0, 10, 0)
1149 00:58:39.521559 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1150 00:58:39.521607 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1151 00:58:39.521654
1152 00:58:39.521703 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1153 00:58:39.521752 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1154 00:58:39.521800 [Gating] SW calibration Done
1155 00:58:39.521871 ==
1156 00:58:39.521936 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 00:58:39.521985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1158 00:58:39.522033 ==
1159 00:58:39.522097 RX Vref Scan: 0
1160 00:58:39.522146
1161 00:58:39.522196 RX Vref 0 -> 0, step: 1
1162 00:58:39.522273
1163 00:58:39.522322 RX Delay -130 -> 252, step: 16
1164 00:58:39.522371 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1165 00:58:39.522420 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1166 00:58:39.522468 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1167 00:58:39.522516 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1168 00:58:39.522565 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1169 00:58:39.522614 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1170 00:58:39.522662 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1171 00:58:39.522711 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1172 00:58:39.522759 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1173 00:58:39.522808 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1174 00:58:39.522856 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1175 00:58:39.522904 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1176 00:58:39.522953 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1177 00:58:39.523002 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1178 00:58:39.523051 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1179 00:58:39.523099 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1180 00:58:39.523147 ==
1181 00:58:39.523196 Dram Type= 6, Freq= 0, CH_0, rank 1
1182 00:58:39.523245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1183 00:58:39.523294 ==
1184 00:58:39.523342 DQS Delay:
1185 00:58:39.523390 DQS0 = 0, DQS1 = 0
1186 00:58:39.523438 DQM Delay:
1187 00:58:39.523486 DQM0 = 81, DQM1 = 75
1188 00:58:39.523534 DQ Delay:
1189 00:58:39.523583 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1190 00:58:39.523632 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1191 00:58:39.523679 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1192 00:58:39.523728 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1193 00:58:39.523777
1194 00:58:39.523824
1195 00:58:39.523872 ==
1196 00:58:39.523920 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 00:58:39.523968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1198 00:58:39.524016 ==
1199 00:58:39.524064
1200 00:58:39.524112
1201 00:58:39.524160 TX Vref Scan disable
1202 00:58:39.524208 == TX Byte 0 ==
1203 00:58:39.524256 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1204 00:58:39.524306 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1205 00:58:39.524354 == TX Byte 1 ==
1206 00:58:39.524402 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1207 00:58:39.524450 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1208 00:58:39.524498 ==
1209 00:58:39.524546 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 00:58:39.524595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1211 00:58:39.524643 ==
1212 00:58:39.524691 TX Vref=22, minBit 9, minWin=27, winSum=450
1213 00:58:39.524741 TX Vref=24, minBit 2, minWin=28, winSum=455
1214 00:58:39.524789 TX Vref=26, minBit 0, minWin=28, winSum=454
1215 00:58:39.524838 TX Vref=28, minBit 4, minWin=28, winSum=460
1216 00:58:39.524886 TX Vref=30, minBit 2, minWin=28, winSum=458
1217 00:58:39.524934 TX Vref=32, minBit 2, minWin=28, winSum=459
1218 00:58:39.524983 [TxChooseVref] Worse bit 4, Min win 28, Win sum 460, Final Vref 28
1219 00:58:39.525031
1220 00:58:39.525080 Final TX Range 1 Vref 28
1221 00:58:39.525128
1222 00:58:39.525176 ==
1223 00:58:39.525224 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 00:58:39.525273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1225 00:58:39.525322 ==
1226 00:58:39.525370
1227 00:58:39.525417
1228 00:58:39.525657 TX Vref Scan disable
1229 00:58:39.525714 == TX Byte 0 ==
1230 00:58:39.525765 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1231 00:58:39.525815 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1232 00:58:39.525904 == TX Byte 1 ==
1233 00:58:39.525952 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1234 00:58:39.526041 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1235 00:58:39.526132
1236 00:58:39.526230 [DATLAT]
1237 00:58:39.526297 Freq=800, CH0 RK1
1238 00:58:39.526346
1239 00:58:39.526395 DATLAT Default: 0x9
1240 00:58:39.526445 0, 0xFFFF, sum = 0
1241 00:58:39.526494 1, 0xFFFF, sum = 0
1242 00:58:39.526543 2, 0xFFFF, sum = 0
1243 00:58:39.526592 3, 0xFFFF, sum = 0
1244 00:58:39.526671 4, 0xFFFF, sum = 0
1245 00:58:39.526721 5, 0xFFFF, sum = 0
1246 00:58:39.526770 6, 0xFFFF, sum = 0
1247 00:58:39.526819 7, 0xFFFF, sum = 0
1248 00:58:39.526868 8, 0x0, sum = 1
1249 00:58:39.526917 9, 0x0, sum = 2
1250 00:58:39.526966 10, 0x0, sum = 3
1251 00:58:39.527015 11, 0x0, sum = 4
1252 00:58:39.527064 best_step = 9
1253 00:58:39.527113
1254 00:58:39.527160 ==
1255 00:58:39.527208 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 00:58:39.527256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 00:58:39.527305 ==
1258 00:58:39.527354 RX Vref Scan: 0
1259 00:58:39.527402
1260 00:58:39.527449 RX Vref 0 -> 0, step: 1
1261 00:58:39.527497
1262 00:58:39.527545 RX Delay -95 -> 252, step: 8
1263 00:58:39.527595 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1264 00:58:39.527643 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1265 00:58:39.527692 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1266 00:58:39.527740 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1267 00:58:39.527788 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1268 00:58:39.527836 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1269 00:58:39.527884 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1270 00:58:39.527933 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1271 00:58:39.527981 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1272 00:58:39.528029 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1273 00:58:39.528078 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1274 00:58:39.528126 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1275 00:58:39.528174 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1276 00:58:39.528223 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1277 00:58:39.528271 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1278 00:58:39.528319 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1279 00:58:39.528367 ==
1280 00:58:39.528416 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 00:58:39.528464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1282 00:58:39.528514 ==
1283 00:58:39.528562 DQS Delay:
1284 00:58:39.528610 DQS0 = 0, DQS1 = 0
1285 00:58:39.528659 DQM Delay:
1286 00:58:39.528707 DQM0 = 86, DQM1 = 74
1287 00:58:39.528755 DQ Delay:
1288 00:58:39.528856 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1289 00:58:39.528932 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1290 00:58:39.528995 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1291 00:58:39.529044 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1292 00:58:39.529093
1293 00:58:39.529140
1294 00:58:39.529188 [DQSOSCAuto] RK1, (LSB)MR18= 0x4949, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1295 00:58:39.529237 CH0 RK1: MR19=606, MR18=4949
1296 00:58:39.529285 CH0_RK1: MR19=0x606, MR18=0x4949, DQSOSC=391, MR23=63, INC=96, DEC=64
1297 00:58:39.529334 [RxdqsGatingPostProcess] freq 800
1298 00:58:39.529381 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1299 00:58:39.529430 Pre-setting of DQS Precalculation
1300 00:58:39.529478 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1301 00:58:39.529526 ==
1302 00:58:39.529573 Dram Type= 6, Freq= 0, CH_1, rank 0
1303 00:58:39.529621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1304 00:58:39.529669 ==
1305 00:58:39.529717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1306 00:58:39.529765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1307 00:58:39.529814 [CA 0] Center 37 (6~68) winsize 63
1308 00:58:39.529863 [CA 1] Center 37 (6~68) winsize 63
1309 00:58:39.529911 [CA 2] Center 34 (4~65) winsize 62
1310 00:58:39.529959 [CA 3] Center 34 (4~65) winsize 62
1311 00:58:39.530007 [CA 4] Center 33 (3~64) winsize 62
1312 00:58:39.530054 [CA 5] Center 33 (3~64) winsize 62
1313 00:58:39.530102
1314 00:58:39.530149 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1315 00:58:39.530197
1316 00:58:39.530290 [CATrainingPosCal] consider 1 rank data
1317 00:58:39.530340 u2DelayCellTimex100 = 270/100 ps
1318 00:58:39.530388 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1319 00:58:39.530437 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1320 00:58:39.530485 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1321 00:58:39.530533 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1322 00:58:39.530581 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1323 00:58:39.530629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1324 00:58:39.530677
1325 00:58:39.530725 CA PerBit enable=1, Macro0, CA PI delay=33
1326 00:58:39.530772
1327 00:58:39.530819 [CBTSetCACLKResult] CA Dly = 33
1328 00:58:39.530867 CS Dly: 4 (0~35)
1329 00:58:39.530919 ==
1330 00:58:39.530967 Dram Type= 6, Freq= 0, CH_1, rank 1
1331 00:58:39.531015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1332 00:58:39.531065 ==
1333 00:58:39.531113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1334 00:58:39.531162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1335 00:58:39.531210 [CA 0] Center 36 (6~67) winsize 62
1336 00:58:39.531258 [CA 1] Center 37 (6~68) winsize 63
1337 00:58:39.531306 [CA 2] Center 34 (4~65) winsize 62
1338 00:58:39.531355 [CA 3] Center 34 (4~65) winsize 62
1339 00:58:39.531402 [CA 4] Center 33 (3~64) winsize 62
1340 00:58:39.531450 [CA 5] Center 33 (3~64) winsize 62
1341 00:58:39.531497
1342 00:58:39.531545 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1343 00:58:39.531593
1344 00:58:39.531640 [CATrainingPosCal] consider 2 rank data
1345 00:58:39.531688 u2DelayCellTimex100 = 270/100 ps
1346 00:58:39.531736 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1347 00:58:39.531784 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1348 00:58:39.531833 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1349 00:58:39.531881 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1350 00:58:39.531929 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1351 00:58:39.531976 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1352 00:58:39.532024
1353 00:58:39.532072 CA PerBit enable=1, Macro0, CA PI delay=33
1354 00:58:39.532119
1355 00:58:39.532166 [CBTSetCACLKResult] CA Dly = 33
1356 00:58:39.532214 CS Dly: 5 (0~37)
1357 00:58:39.532262
1358 00:58:39.532310 ----->DramcWriteLeveling(PI) begin...
1359 00:58:39.532359 ==
1360 00:58:39.532407 Dram Type= 6, Freq= 0, CH_1, rank 0
1361 00:58:39.532645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1362 00:58:39.532739 ==
1363 00:58:39.532788 Write leveling (Byte 0): 25 => 25
1364 00:58:39.532836 Write leveling (Byte 1): 25 => 25
1365 00:58:39.532915 DramcWriteLeveling(PI) end<-----
1366 00:58:39.532994
1367 00:58:39.533042 ==
1368 00:58:39.533090 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 00:58:39.533138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1370 00:58:39.533187 ==
1371 00:58:39.533235 [Gating] SW mode calibration
1372 00:58:39.533284 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1373 00:58:39.533333 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1374 00:58:39.533381 0 6 0 | B1->B0 | 3131 2424 | 0 0 | (1 1) (1 0)
1375 00:58:39.533431 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 00:58:39.533480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 00:58:39.533527 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 00:58:39.533577 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 00:58:39.533625 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 00:58:39.533673 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 00:58:39.533721 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 00:58:39.533768 0 7 0 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
1383 00:58:39.533816 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 00:58:39.533864 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 00:58:39.533912 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 00:58:39.533960 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 00:58:39.534007 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 00:58:39.534081 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 00:58:39.534130 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1390 00:58:39.534179 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1391 00:58:39.534248 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 00:58:39.534297 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 00:58:39.534345 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 00:58:39.534393 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 00:58:39.534441 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 00:58:39.534489 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 00:58:39.534537 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 00:58:39.534585 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 00:58:39.534633 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 00:58:39.534681 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 00:58:39.534729 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 00:58:39.534777 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 00:58:39.534824 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 00:58:39.534872 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 00:58:39.534920 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 00:58:39.534968 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1407 00:58:39.535016 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1408 00:58:39.535064 Total UI for P1: 0, mck2ui 16
1409 00:58:39.535113 best dqsien dly found for B0: ( 0, 10, 0)
1410 00:58:39.535161 Total UI for P1: 0, mck2ui 16
1411 00:58:39.535209 best dqsien dly found for B1: ( 0, 10, 0)
1412 00:58:39.535257 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1413 00:58:39.535305 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1414 00:58:39.535353
1415 00:58:39.535400 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1416 00:58:39.535448 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1417 00:58:39.535496 [Gating] SW calibration Done
1418 00:58:39.535544 ==
1419 00:58:39.535592 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 00:58:39.535640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1421 00:58:39.535688 ==
1422 00:58:39.535736 RX Vref Scan: 0
1423 00:58:39.535783
1424 00:58:39.535830 RX Vref 0 -> 0, step: 1
1425 00:58:39.535877
1426 00:58:39.535924 RX Delay -130 -> 252, step: 16
1427 00:58:39.535973 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1428 00:58:39.536021 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1429 00:58:39.536070 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1430 00:58:39.536119 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1431 00:58:39.536166 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1432 00:58:39.536214 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1433 00:58:39.536262 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1434 00:58:39.536310 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1435 00:58:39.536357 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1436 00:58:39.536405 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1437 00:58:39.536453 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1438 00:58:39.536501 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1439 00:58:39.536549 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1440 00:58:39.536597 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1441 00:58:39.536646 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1442 00:58:39.536694 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1443 00:58:39.536742 ==
1444 00:58:39.536791 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 00:58:39.536839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1446 00:58:39.536888 ==
1447 00:58:39.536970 DQS Delay:
1448 00:58:39.537018 DQS0 = 0, DQS1 = 0
1449 00:58:39.537066 DQM Delay:
1450 00:58:39.537114 DQM0 = 85, DQM1 = 74
1451 00:58:39.537162 DQ Delay:
1452 00:58:39.537209 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1453 00:58:39.537257 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1454 00:58:39.537304 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1455 00:58:39.537352 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1456 00:58:39.537401
1457 00:58:39.537448
1458 00:58:39.537495 ==
1459 00:58:39.537542 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 00:58:39.537590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1461 00:58:39.537638 ==
1462 00:58:39.537686
1463 00:58:39.537733
1464 00:58:39.537780 TX Vref Scan disable
1465 00:58:39.537828 == TX Byte 0 ==
1466 00:58:39.537875 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1467 00:58:39.537924 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1468 00:58:39.537972 == TX Byte 1 ==
1469 00:58:39.538020 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1470 00:58:39.538068 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1471 00:58:39.538115 ==
1472 00:58:39.538351 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 00:58:39.538406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1474 00:58:39.538525 ==
1475 00:58:39.538574 TX Vref=22, minBit 0, minWin=27, winSum=447
1476 00:58:39.538638 TX Vref=24, minBit 3, minWin=27, winSum=447
1477 00:58:39.538688 TX Vref=26, minBit 3, minWin=27, winSum=452
1478 00:58:39.538738 TX Vref=28, minBit 0, minWin=28, winSum=457
1479 00:58:39.538801 TX Vref=30, minBit 0, minWin=28, winSum=459
1480 00:58:39.538849 TX Vref=32, minBit 0, minWin=28, winSum=456
1481 00:58:39.538897 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1482 00:58:39.538946
1483 00:58:39.538994 Final TX Range 1 Vref 30
1484 00:58:39.539043
1485 00:58:39.539091 ==
1486 00:58:39.539139 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 00:58:39.539187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 00:58:39.539277 ==
1489 00:58:39.539324
1490 00:58:39.539370
1491 00:58:39.539418 TX Vref Scan disable
1492 00:58:39.539466 == TX Byte 0 ==
1493 00:58:39.539514 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1494 00:58:39.539562 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1495 00:58:39.539610 == TX Byte 1 ==
1496 00:58:39.539659 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1497 00:58:39.539708 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1498 00:58:39.539756
1499 00:58:39.539803 [DATLAT]
1500 00:58:39.539851 Freq=800, CH1 RK0
1501 00:58:39.539898
1502 00:58:39.539946 DATLAT Default: 0xa
1503 00:58:39.539993 0, 0xFFFF, sum = 0
1504 00:58:39.540042 1, 0xFFFF, sum = 0
1505 00:58:39.540091 2, 0xFFFF, sum = 0
1506 00:58:39.540140 3, 0xFFFF, sum = 0
1507 00:58:39.540188 4, 0xFFFF, sum = 0
1508 00:58:39.540236 5, 0xFFFF, sum = 0
1509 00:58:39.540284 6, 0xFFFF, sum = 0
1510 00:58:39.540333 7, 0xFFFF, sum = 0
1511 00:58:39.540381 8, 0x0, sum = 1
1512 00:58:39.540430 9, 0x0, sum = 2
1513 00:58:39.540479 10, 0x0, sum = 3
1514 00:58:39.540527 11, 0x0, sum = 4
1515 00:58:39.540576 best_step = 9
1516 00:58:39.540623
1517 00:58:39.540670 ==
1518 00:58:39.540717 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 00:58:39.540765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 00:58:39.540813 ==
1521 00:58:39.540861 RX Vref Scan: 1
1522 00:58:39.540908
1523 00:58:39.540955 Set Vref Range= 32 -> 127
1524 00:58:39.541002
1525 00:58:39.541049 RX Vref 32 -> 127, step: 1
1526 00:58:39.541097
1527 00:58:39.541143 RX Delay -111 -> 252, step: 8
1528 00:58:39.541191
1529 00:58:39.541239 Set Vref, RX VrefLevel [Byte0]: 32
1530 00:58:39.541287 [Byte1]: 32
1531 00:58:39.541335
1532 00:58:39.541383 Set Vref, RX VrefLevel [Byte0]: 33
1533 00:58:39.541431 [Byte1]: 33
1534 00:58:39.541478
1535 00:58:39.541526 Set Vref, RX VrefLevel [Byte0]: 34
1536 00:58:39.541574 [Byte1]: 34
1537 00:58:39.541620
1538 00:58:39.541667 Set Vref, RX VrefLevel [Byte0]: 35
1539 00:58:39.541715 [Byte1]: 35
1540 00:58:39.541763
1541 00:58:39.541810 Set Vref, RX VrefLevel [Byte0]: 36
1542 00:58:39.541858 [Byte1]: 36
1543 00:58:39.541905
1544 00:58:39.541953 Set Vref, RX VrefLevel [Byte0]: 37
1545 00:58:39.542001 [Byte1]: 37
1546 00:58:39.542049
1547 00:58:39.542096 Set Vref, RX VrefLevel [Byte0]: 38
1548 00:58:39.542143 [Byte1]: 38
1549 00:58:39.542190
1550 00:58:39.542276 Set Vref, RX VrefLevel [Byte0]: 39
1551 00:58:39.542324 [Byte1]: 39
1552 00:58:39.542372
1553 00:58:39.542420 Set Vref, RX VrefLevel [Byte0]: 40
1554 00:58:39.542468 [Byte1]: 40
1555 00:58:39.542516
1556 00:58:39.542563 Set Vref, RX VrefLevel [Byte0]: 41
1557 00:58:39.542611 [Byte1]: 41
1558 00:58:39.542658
1559 00:58:39.542705 Set Vref, RX VrefLevel [Byte0]: 42
1560 00:58:39.542753 [Byte1]: 42
1561 00:58:39.542800
1562 00:58:39.542847 Set Vref, RX VrefLevel [Byte0]: 43
1563 00:58:39.542895 [Byte1]: 43
1564 00:58:39.542942
1565 00:58:39.542990 Set Vref, RX VrefLevel [Byte0]: 44
1566 00:58:39.543038 [Byte1]: 44
1567 00:58:39.543085
1568 00:58:39.543132 Set Vref, RX VrefLevel [Byte0]: 45
1569 00:58:39.543179 [Byte1]: 45
1570 00:58:39.543227
1571 00:58:39.543274 Set Vref, RX VrefLevel [Byte0]: 46
1572 00:58:39.543323 [Byte1]: 46
1573 00:58:39.543371
1574 00:58:39.543418 Set Vref, RX VrefLevel [Byte0]: 47
1575 00:58:39.543465 [Byte1]: 47
1576 00:58:39.543513
1577 00:58:39.543559 Set Vref, RX VrefLevel [Byte0]: 48
1578 00:58:39.543606 [Byte1]: 48
1579 00:58:39.543653
1580 00:58:39.543701 Set Vref, RX VrefLevel [Byte0]: 49
1581 00:58:39.543748 [Byte1]: 49
1582 00:58:39.543796
1583 00:58:39.543844 Set Vref, RX VrefLevel [Byte0]: 50
1584 00:58:39.543891 [Byte1]: 50
1585 00:58:39.543938
1586 00:58:39.543985 Set Vref, RX VrefLevel [Byte0]: 51
1587 00:58:39.544033 [Byte1]: 51
1588 00:58:39.544080
1589 00:58:39.544127 Set Vref, RX VrefLevel [Byte0]: 52
1590 00:58:39.544174 [Byte1]: 52
1591 00:58:39.544222
1592 00:58:39.544269 Set Vref, RX VrefLevel [Byte0]: 53
1593 00:58:39.544317 [Byte1]: 53
1594 00:58:39.544364
1595 00:58:39.544411 Set Vref, RX VrefLevel [Byte0]: 54
1596 00:58:39.544474 [Byte1]: 54
1597 00:58:39.544538
1598 00:58:39.544585 Set Vref, RX VrefLevel [Byte0]: 55
1599 00:58:39.544632 [Byte1]: 55
1600 00:58:39.544679
1601 00:58:39.544727 Set Vref, RX VrefLevel [Byte0]: 56
1602 00:58:39.544774 [Byte1]: 56
1603 00:58:39.544822
1604 00:58:39.544870 Set Vref, RX VrefLevel [Byte0]: 57
1605 00:58:39.544959 [Byte1]: 57
1606 00:58:39.545008
1607 00:58:39.545055 Set Vref, RX VrefLevel [Byte0]: 58
1608 00:58:39.545103 [Byte1]: 58
1609 00:58:39.545150
1610 00:58:39.545197 Set Vref, RX VrefLevel [Byte0]: 59
1611 00:58:39.545245 [Byte1]: 59
1612 00:58:39.545293
1613 00:58:39.545341 Set Vref, RX VrefLevel [Byte0]: 60
1614 00:58:39.545390 [Byte1]: 60
1615 00:58:39.545438
1616 00:58:39.545485 Set Vref, RX VrefLevel [Byte0]: 61
1617 00:58:39.545533 [Byte1]: 61
1618 00:58:39.545580
1619 00:58:39.545627 Set Vref, RX VrefLevel [Byte0]: 62
1620 00:58:39.545675 [Byte1]: 62
1621 00:58:39.545722
1622 00:58:39.545769 Set Vref, RX VrefLevel [Byte0]: 63
1623 00:58:39.545817 [Byte1]: 63
1624 00:58:39.545865
1625 00:58:39.545912 Set Vref, RX VrefLevel [Byte0]: 64
1626 00:58:39.545960 [Byte1]: 64
1627 00:58:39.546007
1628 00:58:39.546054 Set Vref, RX VrefLevel [Byte0]: 65
1629 00:58:39.546102 [Byte1]: 65
1630 00:58:39.546164
1631 00:58:39.546220 Set Vref, RX VrefLevel [Byte0]: 66
1632 00:58:39.546285 [Byte1]: 66
1633 00:58:39.546332
1634 00:58:39.546380 Set Vref, RX VrefLevel [Byte0]: 67
1635 00:58:39.546427 [Byte1]: 67
1636 00:58:39.546475
1637 00:58:39.546523 Set Vref, RX VrefLevel [Byte0]: 68
1638 00:58:39.546758 [Byte1]: 68
1639 00:58:39.546812
1640 00:58:39.546861 Set Vref, RX VrefLevel [Byte0]: 69
1641 00:58:39.546974 [Byte1]: 69
1642 00:58:39.547025
1643 00:58:39.547089 Set Vref, RX VrefLevel [Byte0]: 70
1644 00:58:39.547152 [Byte1]: 70
1645 00:58:39.547200
1646 00:58:39.547264 Set Vref, RX VrefLevel [Byte0]: 71
1647 00:58:39.547313 [Byte1]: 71
1648 00:58:39.547362
1649 00:58:39.547411 Set Vref, RX VrefLevel [Byte0]: 72
1650 00:58:39.547461 [Byte1]: 72
1651 00:58:39.547510
1652 00:58:39.547559 Set Vref, RX VrefLevel [Byte0]: 73
1653 00:58:39.547608 [Byte1]: 73
1654 00:58:39.547657
1655 00:58:39.547705 Set Vref, RX VrefLevel [Byte0]: 74
1656 00:58:39.547755 [Byte1]: 74
1657 00:58:39.547803
1658 00:58:39.547852 Set Vref, RX VrefLevel [Byte0]: 75
1659 00:58:39.547901 [Byte1]: 75
1660 00:58:39.547950
1661 00:58:39.547998 Set Vref, RX VrefLevel [Byte0]: 76
1662 00:58:39.548047 [Byte1]: 76
1663 00:58:39.548095
1664 00:58:39.548144 Set Vref, RX VrefLevel [Byte0]: 77
1665 00:58:39.548192 [Byte1]: 77
1666 00:58:39.548241
1667 00:58:39.548289 Set Vref, RX VrefLevel [Byte0]: 78
1668 00:58:39.548337 [Byte1]: 78
1669 00:58:39.548385
1670 00:58:39.548434 Set Vref, RX VrefLevel [Byte0]: 79
1671 00:58:39.548482 [Byte1]: 79
1672 00:58:39.548531
1673 00:58:39.548579 Final RX Vref Byte 0 = 58 to rank0
1674 00:58:39.548628 Final RX Vref Byte 1 = 55 to rank0
1675 00:58:39.548677 Final RX Vref Byte 0 = 58 to rank1
1676 00:58:39.548726 Final RX Vref Byte 1 = 55 to rank1==
1677 00:58:39.548775 Dram Type= 6, Freq= 0, CH_1, rank 0
1678 00:58:39.548824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1679 00:58:39.548873 ==
1680 00:58:39.548922 DQS Delay:
1681 00:58:39.548972 DQS0 = 0, DQS1 = 0
1682 00:58:39.549021 DQM Delay:
1683 00:58:39.549070 DQM0 = 81, DQM1 = 75
1684 00:58:39.549119 DQ Delay:
1685 00:58:39.549167 DQ0 =88, DQ1 =72, DQ2 =72, DQ3 =76
1686 00:58:39.549216 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1687 00:58:39.549264 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1688 00:58:39.549312 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1689 00:58:39.549361
1690 00:58:39.549409
1691 00:58:39.549458 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1692 00:58:39.549508 CH1 RK0: MR19=606, MR18=5151
1693 00:58:39.549557 CH1_RK0: MR19=0x606, MR18=0x5151, DQSOSC=389, MR23=63, INC=97, DEC=65
1694 00:58:39.549607
1695 00:58:39.549655 ----->DramcWriteLeveling(PI) begin...
1696 00:58:39.549705 ==
1697 00:58:39.549755 Dram Type= 6, Freq= 0, CH_1, rank 1
1698 00:58:39.549805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1699 00:58:39.549854 ==
1700 00:58:39.549903 Write leveling (Byte 0): 25 => 25
1701 00:58:39.549952 Write leveling (Byte 1): 25 => 25
1702 00:58:39.550002 DramcWriteLeveling(PI) end<-----
1703 00:58:39.550051
1704 00:58:39.550099 ==
1705 00:58:39.550147 Dram Type= 6, Freq= 0, CH_1, rank 1
1706 00:58:39.550196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1707 00:58:39.550256 ==
1708 00:58:39.550306 [Gating] SW mode calibration
1709 00:58:39.550355 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1710 00:58:39.550406 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1711 00:58:39.550455 0 6 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
1712 00:58:39.550505 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 00:58:39.550554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 00:58:39.550603 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1715 00:58:39.550652 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1716 00:58:39.550702 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1717 00:58:39.550751 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1718 00:58:39.550800 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1719 00:58:39.550849 0 7 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1720 00:58:39.550898 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 00:58:39.550947 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 00:58:39.550996 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1723 00:58:39.551044 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1724 00:58:39.551093 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1725 00:58:39.551142 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1726 00:58:39.551191 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1727 00:58:39.551240 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1728 00:58:39.551288 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 00:58:39.551337 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 00:58:39.551386 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 00:58:39.551435 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 00:58:39.551484 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 00:58:39.551546 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 00:58:39.551597 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 00:58:39.551647 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 00:58:39.551696 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 00:58:39.551745 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 00:58:39.551794 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 00:58:39.551843 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1740 00:58:39.551891 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1741 00:58:39.551940 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1742 00:58:39.551989 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1743 00:58:39.552038 Total UI for P1: 0, mck2ui 16
1744 00:58:39.552088 best dqsien dly found for B0: ( 0, 9, 24)
1745 00:58:39.552138 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1746 00:58:39.552187 Total UI for P1: 0, mck2ui 16
1747 00:58:39.552236 best dqsien dly found for B1: ( 0, 9, 28)
1748 00:58:39.552285 best DQS0 dly(MCK, UI, PI) = (0, 9, 24)
1749 00:58:39.552334 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1750 00:58:39.552382
1751 00:58:39.552431 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 24)
1752 00:58:39.552480 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1753 00:58:39.552529 [Gating] SW calibration Done
1754 00:58:39.552577 ==
1755 00:58:39.552817 Dram Type= 6, Freq= 0, CH_1, rank 1
1756 00:58:39.552875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1757 00:58:39.552925 ==
1758 00:58:39.552975 RX Vref Scan: 0
1759 00:58:39.553023
1760 00:58:39.553072 RX Vref 0 -> 0, step: 1
1761 00:58:39.553122
1762 00:58:39.553171 RX Delay -130 -> 252, step: 16
1763 00:58:39.553221 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1764 00:58:39.553270 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1765 00:58:39.553321 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1766 00:58:39.553371 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1767 00:58:39.553419 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1768 00:58:39.553469 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1769 00:58:39.553519 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1770 00:58:39.553570 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1771 00:58:39.553620 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1772 00:58:39.553670 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1773 00:58:39.553719 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1774 00:58:39.553769 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1775 00:58:39.553819 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1776 00:58:39.553868 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1777 00:58:39.553918 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1778 00:58:39.553967 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1779 00:58:39.554017 ==
1780 00:58:39.554066 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 00:58:39.554115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1782 00:58:39.554165 ==
1783 00:58:39.554223 DQS Delay:
1784 00:58:39.554275 DQS0 = 0, DQS1 = 0
1785 00:58:39.554324 DQM Delay:
1786 00:58:39.554373 DQM0 = 85, DQM1 = 73
1787 00:58:39.554422 DQ Delay:
1788 00:58:39.554471 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1789 00:58:39.554521 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1790 00:58:39.554570 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1791 00:58:39.554620 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1792 00:58:39.554669
1793 00:58:39.554717
1794 00:58:39.554765 ==
1795 00:58:39.554813 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 00:58:39.554864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1797 00:58:39.554920 ==
1798 00:58:39.554969
1799 00:58:39.555018
1800 00:58:39.555067 TX Vref Scan disable
1801 00:58:39.555116 == TX Byte 0 ==
1802 00:58:39.555166 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1803 00:58:39.555215 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1804 00:58:39.555264 == TX Byte 1 ==
1805 00:58:39.555313 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1806 00:58:39.555362 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1807 00:58:39.555411 ==
1808 00:58:39.555460 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 00:58:39.555510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1810 00:58:39.555560 ==
1811 00:58:39.555610 TX Vref=22, minBit 0, minWin=27, winSum=451
1812 00:58:39.555660 TX Vref=24, minBit 0, minWin=27, winSum=453
1813 00:58:39.555710 TX Vref=26, minBit 3, minWin=28, winSum=457
1814 00:58:39.555759 TX Vref=28, minBit 0, minWin=28, winSum=457
1815 00:58:39.555809 TX Vref=30, minBit 9, minWin=27, winSum=455
1816 00:58:39.555859 TX Vref=32, minBit 9, minWin=27, winSum=454
1817 00:58:39.555908 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 26
1818 00:58:39.555958
1819 00:58:39.556007 Final TX Range 1 Vref 26
1820 00:58:39.556056
1821 00:58:39.556104 ==
1822 00:58:39.556153 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 00:58:39.556201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1824 00:58:39.556250 ==
1825 00:58:39.556298
1826 00:58:39.556348
1827 00:58:39.556397 TX Vref Scan disable
1828 00:58:39.556446 == TX Byte 0 ==
1829 00:58:39.556495 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1830 00:58:39.556544 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1831 00:58:39.556593 == TX Byte 1 ==
1832 00:58:39.556641 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1833 00:58:39.556690 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1834 00:58:39.556739
1835 00:58:39.556787 [DATLAT]
1836 00:58:39.556835 Freq=800, CH1 RK1
1837 00:58:39.556884
1838 00:58:39.556932 DATLAT Default: 0x9
1839 00:58:39.556982 0, 0xFFFF, sum = 0
1840 00:58:39.557032 1, 0xFFFF, sum = 0
1841 00:58:39.557082 2, 0xFFFF, sum = 0
1842 00:58:39.557132 3, 0xFFFF, sum = 0
1843 00:58:39.557182 4, 0xFFFF, sum = 0
1844 00:58:39.557231 5, 0xFFFF, sum = 0
1845 00:58:39.557280 6, 0xFFFF, sum = 0
1846 00:58:39.557330 7, 0xFFFF, sum = 0
1847 00:58:39.557379 8, 0x0, sum = 1
1848 00:58:39.557428 9, 0x0, sum = 2
1849 00:58:39.557479 10, 0x0, sum = 3
1850 00:58:39.557529 11, 0x0, sum = 4
1851 00:58:39.557579 best_step = 9
1852 00:58:39.557628
1853 00:58:39.557677 ==
1854 00:58:39.557726 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 00:58:39.557777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1856 00:58:39.557826 ==
1857 00:58:39.557875 RX Vref Scan: 0
1858 00:58:39.557923
1859 00:58:39.557971 RX Vref 0 -> 0, step: 1
1860 00:58:39.558020
1861 00:58:39.558068 RX Delay -111 -> 252, step: 8
1862 00:58:39.558117 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1863 00:58:39.558166 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1864 00:58:39.558222 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1865 00:58:39.558274 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1866 00:58:39.558323 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1867 00:58:39.558373 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1868 00:58:39.558422 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1869 00:58:39.558471 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1870 00:58:39.558520 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1871 00:58:39.558570 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1872 00:58:39.558619 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1873 00:58:39.558669 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1874 00:58:39.558718 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1875 00:58:39.558767 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1876 00:58:39.558817 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1877 00:58:39.558866 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1878 00:58:39.558915 ==
1879 00:58:39.558963 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 00:58:39.559012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1881 00:58:39.559062 ==
1882 00:58:39.559111 DQS Delay:
1883 00:58:39.559159 DQS0 = 0, DQS1 = 0
1884 00:58:39.559209 DQM Delay:
1885 00:58:39.559257 DQM0 = 83, DQM1 = 73
1886 00:58:39.559306 DQ Delay:
1887 00:58:39.559355 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =80
1888 00:58:39.559404 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1889 00:58:39.559453 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1890 00:58:39.559502 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1891 00:58:39.559551
1892 00:58:39.559600
1893 00:58:39.559650 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1894 00:58:39.559700 CH1 RK1: MR19=606, MR18=3B3B
1895 00:58:39.559942 CH1_RK1: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1896 00:58:39.559998 [RxdqsGatingPostProcess] freq 800
1897 00:58:39.560048 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1898 00:58:39.560099 Pre-setting of DQS Precalculation
1899 00:58:39.560149 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1900 00:58:39.560199 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1901 00:58:39.560249 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1902 00:58:39.560302
1903 00:58:39.560350
1904 00:58:39.560399 [Calibration Summary] 1600 Mbps
1905 00:58:39.560448 CH 0, Rank 0
1906 00:58:39.560497 SW Impedance : PASS
1907 00:58:39.560546 DUTY Scan : NO K
1908 00:58:39.560596 ZQ Calibration : PASS
1909 00:58:39.560646 Jitter Meter : NO K
1910 00:58:39.560695 CBT Training : PASS
1911 00:58:39.560743 Write leveling : PASS
1912 00:58:39.560791 RX DQS gating : PASS
1913 00:58:39.560840 RX DQ/DQS(RDDQC) : PASS
1914 00:58:39.560889 TX DQ/DQS : PASS
1915 00:58:39.560938 RX DATLAT : PASS
1916 00:58:39.560986 RX DQ/DQS(Engine): PASS
1917 00:58:39.561035 TX OE : NO K
1918 00:58:39.561083 All Pass.
1919 00:58:39.561132
1920 00:58:39.561181 CH 0, Rank 1
1921 00:58:39.561230 SW Impedance : PASS
1922 00:58:39.561279 DUTY Scan : NO K
1923 00:58:39.561328 ZQ Calibration : PASS
1924 00:58:39.561376 Jitter Meter : NO K
1925 00:58:39.561425 CBT Training : PASS
1926 00:58:39.561473 Write leveling : PASS
1927 00:58:39.561522 RX DQS gating : PASS
1928 00:58:39.561570 RX DQ/DQS(RDDQC) : PASS
1929 00:58:39.561620 TX DQ/DQS : PASS
1930 00:58:39.561669 RX DATLAT : PASS
1931 00:58:39.561718 RX DQ/DQS(Engine): PASS
1932 00:58:39.561766 TX OE : NO K
1933 00:58:39.705319 All Pass.
1934 00:58:39.705440
1935 00:58:39.705500 CH 1, Rank 0
1936 00:58:39.705554 SW Impedance : PASS
1937 00:58:39.705608 DUTY Scan : NO K
1938 00:58:39.705660 ZQ Calibration : PASS
1939 00:58:39.705711 Jitter Meter : NO K
1940 00:58:39.705760 CBT Training : PASS
1941 00:58:39.705809 Write leveling : PASS
1942 00:58:39.705858 RX DQS gating : PASS
1943 00:58:39.705906 RX DQ/DQS(RDDQC) : PASS
1944 00:58:39.705955 TX DQ/DQS : PASS
1945 00:58:39.706005 RX DATLAT : PASS
1946 00:58:39.706053 RX DQ/DQS(Engine): PASS
1947 00:58:39.706101 TX OE : NO K
1948 00:58:39.706149 All Pass.
1949 00:58:39.706197
1950 00:58:39.706286 CH 1, Rank 1
1951 00:58:39.706334 SW Impedance : PASS
1952 00:58:39.706383 DUTY Scan : NO K
1953 00:58:39.706431 ZQ Calibration : PASS
1954 00:58:39.706480 Jitter Meter : NO K
1955 00:58:39.706529 CBT Training : PASS
1956 00:58:39.706577 Write leveling : PASS
1957 00:58:39.706625 RX DQS gating : PASS
1958 00:58:39.706673 RX DQ/DQS(RDDQC) : PASS
1959 00:58:39.706722 TX DQ/DQS : PASS
1960 00:58:39.706771 RX DATLAT : PASS
1961 00:58:39.706819 RX DQ/DQS(Engine): PASS
1962 00:58:39.706867 TX OE : NO K
1963 00:58:39.706915 All Pass.
1964 00:58:39.706963
1965 00:58:39.707011 DramC Write-DBI off
1966 00:58:39.707059 PER_BANK_REFRESH: Hybrid Mode
1967 00:58:39.707107 TX_TRACKING: ON
1968 00:58:39.707180 [GetDramInforAfterCalByMRR] Vendor 6.
1969 00:58:39.707330 [GetDramInforAfterCalByMRR] Revision 606.
1970 00:58:39.707383 [GetDramInforAfterCalByMRR] Revision 2 0.
1971 00:58:39.707432 MR0 0x3939
1972 00:58:39.707481 MR8 0x1111
1973 00:58:39.707529 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1974 00:58:39.707578
1975 00:58:39.707625 MR0 0x3939
1976 00:58:39.707673 MR8 0x1111
1977 00:58:39.707721 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1978 00:58:39.707768
1979 00:58:39.707817 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1980 00:58:39.707867 [FAST_K] Save calibration result to emmc
1981 00:58:39.707916 [FAST_K] Save calibration result to emmc
1982 00:58:39.707964 dram_init: config_dvfs: 1
1983 00:58:39.708013 dramc_set_vcore_voltage set vcore to 662500
1984 00:58:39.708061 Read voltage for 1200, 2
1985 00:58:39.708110 Vio18 = 0
1986 00:58:39.708158 Vcore = 662500
1987 00:58:39.708206 Vdram = 0
1988 00:58:39.708253 Vddq = 0
1989 00:58:39.708301 Vmddr = 0
1990 00:58:39.708348 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1991 00:58:39.708397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1992 00:58:39.708446 MEM_TYPE=3, freq_sel=15
1993 00:58:39.708494 sv_algorithm_assistance_LP4_1600
1994 00:58:39.708542 ============ PULL DRAM RESETB DOWN ============
1995 00:58:39.708591 ========== PULL DRAM RESETB DOWN end =========
1996 00:58:39.708640 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1997 00:58:39.708688 ===================================
1998 00:58:39.708735 LPDDR4 DRAM CONFIGURATION
1999 00:58:39.708783 ===================================
2000 00:58:39.708832 EX_ROW_EN[0] = 0x0
2001 00:58:39.708880 EX_ROW_EN[1] = 0x0
2002 00:58:39.708928 LP4Y_EN = 0x0
2003 00:58:39.708976 WORK_FSP = 0x0
2004 00:58:39.709023 WL = 0x4
2005 00:58:39.709071 RL = 0x4
2006 00:58:39.709118 BL = 0x2
2007 00:58:39.709165 RPST = 0x0
2008 00:58:39.709212 RD_PRE = 0x0
2009 00:58:39.709259 WR_PRE = 0x1
2010 00:58:39.709307 WR_PST = 0x0
2011 00:58:39.709354 DBI_WR = 0x0
2012 00:58:39.709401 DBI_RD = 0x0
2013 00:58:39.709448 OTF = 0x1
2014 00:58:39.709496 ===================================
2015 00:58:39.709545 ===================================
2016 00:58:39.709592 ANA top config
2017 00:58:39.709640 ===================================
2018 00:58:39.709688 DLL_ASYNC_EN = 0
2019 00:58:39.709736 ALL_SLAVE_EN = 0
2020 00:58:39.709784 NEW_RANK_MODE = 1
2021 00:58:39.709833 DLL_IDLE_MODE = 1
2022 00:58:39.709880 LP45_APHY_COMB_EN = 1
2023 00:58:39.709927 TX_ODT_DIS = 1
2024 00:58:39.709975 NEW_8X_MODE = 1
2025 00:58:39.710024 ===================================
2026 00:58:39.710071 ===================================
2027 00:58:39.710119 data_rate = 2400
2028 00:58:39.710167 CKR = 1
2029 00:58:39.710220 DQ_P2S_RATIO = 8
2030 00:58:39.710305 ===================================
2031 00:58:39.710353 CA_P2S_RATIO = 8
2032 00:58:39.710401 DQ_CA_OPEN = 0
2033 00:58:39.710449 DQ_SEMI_OPEN = 0
2034 00:58:39.710497 CA_SEMI_OPEN = 0
2035 00:58:39.710545 CA_FULL_RATE = 0
2036 00:58:39.710593 DQ_CKDIV4_EN = 0
2037 00:58:39.710641 CA_CKDIV4_EN = 0
2038 00:58:39.710690 CA_PREDIV_EN = 0
2039 00:58:39.710737 PH8_DLY = 17
2040 00:58:39.710786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2041 00:58:39.710833 DQ_AAMCK_DIV = 4
2042 00:58:39.710880 CA_AAMCK_DIV = 4
2043 00:58:39.710928 CA_ADMCK_DIV = 4
2044 00:58:39.711175 DQ_TRACK_CA_EN = 0
2045 00:58:39.711232 CA_PICK = 1200
2046 00:58:39.711282 CA_MCKIO = 1200
2047 00:58:39.711330 MCKIO_SEMI = 0
2048 00:58:39.711379 PLL_FREQ = 2366
2049 00:58:39.711427 DQ_UI_PI_RATIO = 32
2050 00:58:39.711475 CA_UI_PI_RATIO = 0
2051 00:58:39.711522 ===================================
2052 00:58:39.711609 ===================================
2053 00:58:39.711657 memory_type:LPDDR4
2054 00:58:39.711705 GP_NUM : 10
2055 00:58:39.711753 SRAM_EN : 1
2056 00:58:39.711801 MD32_EN : 0
2057 00:58:39.711849 ===================================
2058 00:58:39.711897 [ANA_INIT] >>>>>>>>>>>>>>
2059 00:58:39.711945 <<<<<< [CONFIGURE PHASE]: ANA_TX
2060 00:58:39.711994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2061 00:58:39.712042 ===================================
2062 00:58:39.712090 data_rate = 2400,PCW = 0X5b00
2063 00:58:39.712139 ===================================
2064 00:58:39.712187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2065 00:58:39.712236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2066 00:58:39.712285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2067 00:58:39.712334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2068 00:58:39.712383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2069 00:58:39.712431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2070 00:58:39.712480 [ANA_INIT] flow start
2071 00:58:39.712528 [ANA_INIT] PLL >>>>>>>>
2072 00:58:39.712576 [ANA_INIT] PLL <<<<<<<<
2073 00:58:39.712625 [ANA_INIT] MIDPI >>>>>>>>
2074 00:58:39.712673 [ANA_INIT] MIDPI <<<<<<<<
2075 00:58:39.712721 [ANA_INIT] DLL >>>>>>>>
2076 00:58:39.712808 [ANA_INIT] DLL <<<<<<<<
2077 00:58:39.712856 [ANA_INIT] flow end
2078 00:58:39.712905 ============ LP4 DIFF to SE enter ============
2079 00:58:39.712954 ============ LP4 DIFF to SE exit ============
2080 00:58:39.713003 [ANA_INIT] <<<<<<<<<<<<<
2081 00:58:39.713051 [Flow] Enable top DCM control >>>>>
2082 00:58:39.713100 [Flow] Enable top DCM control <<<<<
2083 00:58:39.713148 Enable DLL master slave shuffle
2084 00:58:39.713196 ==============================================================
2085 00:58:39.713245 Gating Mode config
2086 00:58:39.713294 ==============================================================
2087 00:58:39.713342 Config description:
2088 00:58:39.713391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2089 00:58:39.713441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2090 00:58:39.713490 SELPH_MODE 0: By rank 1: By Phase
2091 00:58:39.713539 ==============================================================
2092 00:58:39.713587 GAT_TRACK_EN = 1
2093 00:58:39.713636 RX_GATING_MODE = 2
2094 00:58:39.713685 RX_GATING_TRACK_MODE = 2
2095 00:58:39.713733 SELPH_MODE = 1
2096 00:58:39.713781 PICG_EARLY_EN = 1
2097 00:58:39.713830 VALID_LAT_VALUE = 1
2098 00:58:39.713877 ==============================================================
2099 00:58:39.713926 Enter into Gating configuration >>>>
2100 00:58:39.713974 Exit from Gating configuration <<<<
2101 00:58:39.714023 Enter into DVFS_PRE_config >>>>>
2102 00:58:39.714072 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2103 00:58:39.714122 Exit from DVFS_PRE_config <<<<<
2104 00:58:39.714170 Enter into PICG configuration >>>>
2105 00:58:39.714243 Exit from PICG configuration <<<<
2106 00:58:39.714308 [RX_INPUT] configuration >>>>>
2107 00:58:39.714356 [RX_INPUT] configuration <<<<<
2108 00:58:39.714405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2109 00:58:39.714453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2110 00:58:39.714502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2111 00:58:39.714552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2112 00:58:39.714601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2113 00:58:39.714650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2114 00:58:39.714699 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2115 00:58:39.714747 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2116 00:58:39.714796 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2117 00:58:39.714844 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2118 00:58:39.714893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2119 00:58:39.714942 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 00:58:39.714991 ===================================
2121 00:58:39.715040 LPDDR4 DRAM CONFIGURATION
2122 00:58:39.715088 ===================================
2123 00:58:39.715137 EX_ROW_EN[0] = 0x0
2124 00:58:39.715185 EX_ROW_EN[1] = 0x0
2125 00:58:39.715233 LP4Y_EN = 0x0
2126 00:58:39.715281 WORK_FSP = 0x0
2127 00:58:39.715329 WL = 0x4
2128 00:58:39.715378 RL = 0x4
2129 00:58:39.715426 BL = 0x2
2130 00:58:39.715474 RPST = 0x0
2131 00:58:39.715523 RD_PRE = 0x0
2132 00:58:39.715571 WR_PRE = 0x1
2133 00:58:39.715620 WR_PST = 0x0
2134 00:58:39.715667 DBI_WR = 0x0
2135 00:58:39.715715 DBI_RD = 0x0
2136 00:58:39.715763 OTF = 0x1
2137 00:58:39.715811 ===================================
2138 00:58:39.715860 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2139 00:58:39.715908 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2140 00:58:39.715957 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 00:58:39.716005 ===================================
2142 00:58:39.716053 LPDDR4 DRAM CONFIGURATION
2143 00:58:39.716101 ===================================
2144 00:58:39.716149 EX_ROW_EN[0] = 0x10
2145 00:58:39.716197 EX_ROW_EN[1] = 0x0
2146 00:58:39.716245 LP4Y_EN = 0x0
2147 00:58:39.716293 WORK_FSP = 0x0
2148 00:58:39.716342 WL = 0x4
2149 00:58:39.716390 RL = 0x4
2150 00:58:39.716438 BL = 0x2
2151 00:58:39.716679 RPST = 0x0
2152 00:58:39.716762 RD_PRE = 0x0
2153 00:58:39.716811 WR_PRE = 0x1
2154 00:58:39.716860 WR_PST = 0x0
2155 00:58:39.716909 DBI_WR = 0x0
2156 00:58:39.716973 DBI_RD = 0x0
2157 00:58:39.717036 OTF = 0x1
2158 00:58:39.717109 ===================================
2159 00:58:39.717159 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2160 00:58:39.717254 ==
2161 00:58:39.717303 Dram Type= 6, Freq= 0, CH_0, rank 0
2162 00:58:39.717373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2163 00:58:39.717424 ==
2164 00:58:39.717474 [Duty_Offset_Calibration]
2165 00:58:39.717522 B0:0 B1:2 CA:1
2166 00:58:39.717570
2167 00:58:39.717619 [DutyScan_Calibration_Flow] k_type=0
2168 00:58:39.717667
2169 00:58:39.717715 ==CLK 0==
2170 00:58:39.717763 Final CLK duty delay cell = 0
2171 00:58:39.717812 [0] MAX Duty = 5093%(X100), DQS PI = 12
2172 00:58:39.717861 [0] MIN Duty = 4938%(X100), DQS PI = 52
2173 00:58:39.717909 [0] AVG Duty = 5015%(X100)
2174 00:58:39.717957
2175 00:58:39.718005 CH0 CLK Duty spec in!! Max-Min= 155%
2176 00:58:39.718054 [DutyScan_Calibration_Flow] ====Done====
2177 00:58:39.718102
2178 00:58:39.718151 [DutyScan_Calibration_Flow] k_type=1
2179 00:58:39.718199
2180 00:58:39.718304 ==DQS 0 ==
2181 00:58:39.718355 Final DQS duty delay cell = 0
2182 00:58:39.718405 [0] MAX Duty = 5125%(X100), DQS PI = 32
2183 00:58:39.718454 [0] MIN Duty = 5000%(X100), DQS PI = 6
2184 00:58:39.718504 [0] AVG Duty = 5062%(X100)
2185 00:58:39.718553
2186 00:58:39.718602 ==DQS 1 ==
2187 00:58:39.718650 Final DQS duty delay cell = 0
2188 00:58:39.718699 [0] MAX Duty = 5031%(X100), DQS PI = 50
2189 00:58:39.718748 [0] MIN Duty = 4906%(X100), DQS PI = 16
2190 00:58:39.718797 [0] AVG Duty = 4968%(X100)
2191 00:58:39.718845
2192 00:58:39.718893 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2193 00:58:39.718942
2194 00:58:39.718989 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2195 00:58:39.719037 [DutyScan_Calibration_Flow] ====Done====
2196 00:58:39.719086
2197 00:58:39.719133 [DutyScan_Calibration_Flow] k_type=3
2198 00:58:39.719182
2199 00:58:39.719230 ==DQM 0 ==
2200 00:58:39.719278 Final DQM duty delay cell = 0
2201 00:58:39.719327 [0] MAX Duty = 5187%(X100), DQS PI = 22
2202 00:58:39.719375 [0] MIN Duty = 4969%(X100), DQS PI = 38
2203 00:58:39.719423 [0] AVG Duty = 5078%(X100)
2204 00:58:39.719472
2205 00:58:39.719519 ==DQM 1 ==
2206 00:58:39.719568 Final DQM duty delay cell = 4
2207 00:58:39.719617 [4] MAX Duty = 5187%(X100), DQS PI = 54
2208 00:58:39.719666 [4] MIN Duty = 5000%(X100), DQS PI = 16
2209 00:58:39.719714 [4] AVG Duty = 5093%(X100)
2210 00:58:39.719762
2211 00:58:39.719811 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2212 00:58:39.719859
2213 00:58:39.719907 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2214 00:58:39.719956 [DutyScan_Calibration_Flow] ====Done====
2215 00:58:39.720004
2216 00:58:39.720053 [DutyScan_Calibration_Flow] k_type=2
2217 00:58:39.720101
2218 00:58:39.720148 ==DQ 0 ==
2219 00:58:39.720197 Final DQ duty delay cell = -4
2220 00:58:39.720245 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2221 00:58:39.720294 [-4] MIN Duty = 4813%(X100), DQS PI = 6
2222 00:58:39.720342 [-4] AVG Duty = 4937%(X100)
2223 00:58:39.720390
2224 00:58:39.720438 ==DQ 1 ==
2225 00:58:39.720487 Final DQ duty delay cell = -4
2226 00:58:39.720536 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2227 00:58:39.720584 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2228 00:58:39.720632 [-4] AVG Duty = 4984%(X100)
2229 00:58:39.720680
2230 00:58:39.720728 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2231 00:58:39.720777
2232 00:58:39.720824 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2233 00:58:39.720872 [DutyScan_Calibration_Flow] ====Done====
2234 00:58:39.720920 ==
2235 00:58:39.720969 Dram Type= 6, Freq= 0, CH_1, rank 0
2236 00:58:39.721017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2237 00:58:39.721066 ==
2238 00:58:39.721114 [Duty_Offset_Calibration]
2239 00:58:39.721162 B0:0 B1:5 CA:-5
2240 00:58:39.721210
2241 00:58:39.721257 [DutyScan_Calibration_Flow] k_type=0
2242 00:58:39.721305
2243 00:58:39.721353 ==CLK 0==
2244 00:58:39.721401 Final CLK duty delay cell = 0
2245 00:58:39.721450 [0] MAX Duty = 5094%(X100), DQS PI = 24
2246 00:58:39.721498 [0] MIN Duty = 4875%(X100), DQS PI = 46
2247 00:58:39.721546 [0] AVG Duty = 4984%(X100)
2248 00:58:39.721594
2249 00:58:39.721642 CH1 CLK Duty spec in!! Max-Min= 219%
2250 00:58:39.721689 [DutyScan_Calibration_Flow] ====Done====
2251 00:58:39.721737
2252 00:58:39.721785 [DutyScan_Calibration_Flow] k_type=1
2253 00:58:39.721833
2254 00:58:39.721881 ==DQS 0 ==
2255 00:58:39.721929 Final DQS duty delay cell = 0
2256 00:58:39.721978 [0] MAX Duty = 5125%(X100), DQS PI = 16
2257 00:58:39.722026 [0] MIN Duty = 4875%(X100), DQS PI = 40
2258 00:58:39.722075 [0] AVG Duty = 5000%(X100)
2259 00:58:39.722122
2260 00:58:39.722170 ==DQS 1 ==
2261 00:58:39.722242 Final DQS duty delay cell = -4
2262 00:58:39.722308 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2263 00:58:39.722357 [-4] MIN Duty = 4876%(X100), DQS PI = 60
2264 00:58:39.722406 [-4] AVG Duty = 4938%(X100)
2265 00:58:39.722454
2266 00:58:39.722502 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2267 00:58:39.722551
2268 00:58:39.722598 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2269 00:58:39.722647 [DutyScan_Calibration_Flow] ====Done====
2270 00:58:39.722696
2271 00:58:39.722743 [DutyScan_Calibration_Flow] k_type=3
2272 00:58:39.722792
2273 00:58:39.722840 ==DQM 0 ==
2274 00:58:39.722889 Final DQM duty delay cell = -4
2275 00:58:39.722937 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2276 00:58:39.722986 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2277 00:58:39.723034 [-4] AVG Duty = 4969%(X100)
2278 00:58:39.723082
2279 00:58:39.723130 ==DQM 1 ==
2280 00:58:39.723177 Final DQM duty delay cell = -4
2281 00:58:39.723225 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2282 00:58:39.723274 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2283 00:58:39.723322 [-4] AVG Duty = 4968%(X100)
2284 00:58:39.723371
2285 00:58:39.723419 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2286 00:58:39.723468
2287 00:58:39.723515 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2288 00:58:39.723564 [DutyScan_Calibration_Flow] ====Done====
2289 00:58:39.723612
2290 00:58:39.723659 [DutyScan_Calibration_Flow] k_type=2
2291 00:58:39.723707
2292 00:58:39.723756 ==DQ 0 ==
2293 00:58:39.723804 Final DQ duty delay cell = 0
2294 00:58:39.723853 [0] MAX Duty = 5062%(X100), DQS PI = 0
2295 00:58:39.723902 [0] MIN Duty = 4969%(X100), DQS PI = 24
2296 00:58:39.723950 [0] AVG Duty = 5015%(X100)
2297 00:58:39.723998
2298 00:58:39.724046 ==DQ 1 ==
2299 00:58:39.724093 Final DQ duty delay cell = 0
2300 00:58:39.724141 [0] MAX Duty = 5000%(X100), DQS PI = 6
2301 00:58:39.724189 [0] MIN Duty = 4907%(X100), DQS PI = 0
2302 00:58:39.724236 [0] AVG Duty = 4953%(X100)
2303 00:58:39.724283
2304 00:58:39.724331 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2305 00:58:39.724378
2306 00:58:39.724425 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2307 00:58:39.724473 [DutyScan_Calibration_Flow] ====Done====
2308 00:58:39.724520 nWR fixed to 30
2309 00:58:39.724568 [ModeRegInit_LP4] CH0 RK0
2310 00:58:39.724615 [ModeRegInit_LP4] CH0 RK1
2311 00:58:39.724663 [ModeRegInit_LP4] CH1 RK0
2312 00:58:39.724710 [ModeRegInit_LP4] CH1 RK1
2313 00:58:39.724757 match AC timing 6
2314 00:58:39.724996 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2315 00:58:39.725053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2316 00:58:39.725103 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2317 00:58:39.725152 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2318 00:58:39.725201 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2319 00:58:39.725249 ==
2320 00:58:39.725297 Dram Type= 6, Freq= 0, CH_0, rank 0
2321 00:58:39.725346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2322 00:58:39.725432 ==
2323 00:58:39.725480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2324 00:58:39.725528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2325 00:58:39.725577 [CA 0] Center 39 (9~70) winsize 62
2326 00:58:39.725625 [CA 1] Center 39 (8~70) winsize 63
2327 00:58:39.725672 [CA 2] Center 36 (5~67) winsize 63
2328 00:58:39.725719 [CA 3] Center 35 (4~66) winsize 63
2329 00:58:39.725767 [CA 4] Center 34 (3~65) winsize 63
2330 00:58:39.725815 [CA 5] Center 33 (3~64) winsize 62
2331 00:58:39.725863
2332 00:58:39.725911 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2333 00:58:39.725961
2334 00:58:39.726009 [CATrainingPosCal] consider 1 rank data
2335 00:58:39.726057 u2DelayCellTimex100 = 270/100 ps
2336 00:58:39.726104 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2337 00:58:39.726152 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2338 00:58:39.726200 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2339 00:58:39.726296 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2340 00:58:39.726346 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2341 00:58:39.726394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2342 00:58:39.726442
2343 00:58:39.726489 CA PerBit enable=1, Macro0, CA PI delay=33
2344 00:58:39.726537
2345 00:58:39.726585 [CBTSetCACLKResult] CA Dly = 33
2346 00:58:39.726633 CS Dly: 7 (0~38)
2347 00:58:39.726681 ==
2348 00:58:39.726729 Dram Type= 6, Freq= 0, CH_0, rank 1
2349 00:58:39.726777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2350 00:58:39.726826 ==
2351 00:58:39.726874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2352 00:58:39.726923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2353 00:58:39.726972 [CA 0] Center 39 (8~70) winsize 63
2354 00:58:39.727020 [CA 1] Center 39 (8~70) winsize 63
2355 00:58:39.727069 [CA 2] Center 35 (5~66) winsize 62
2356 00:58:39.727117 [CA 3] Center 35 (4~66) winsize 63
2357 00:58:39.727164 [CA 4] Center 33 (3~64) winsize 62
2358 00:58:39.727212 [CA 5] Center 33 (3~64) winsize 62
2359 00:58:39.727260
2360 00:58:39.727309 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2361 00:58:39.727357
2362 00:58:39.727404 [CATrainingPosCal] consider 2 rank data
2363 00:58:39.727452 u2DelayCellTimex100 = 270/100 ps
2364 00:58:39.727538 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2365 00:58:39.727601 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2366 00:58:39.727679 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2367 00:58:39.727742 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2368 00:58:39.727791 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2369 00:58:39.727839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2370 00:58:39.727886
2371 00:58:39.727934 CA PerBit enable=1, Macro0, CA PI delay=33
2372 00:58:39.727983
2373 00:58:39.728031 [CBTSetCACLKResult] CA Dly = 33
2374 00:58:39.728080 CS Dly: 7 (0~39)
2375 00:58:39.728127
2376 00:58:39.728174 ----->DramcWriteLeveling(PI) begin...
2377 00:58:39.728222 ==
2378 00:58:39.728270 Dram Type= 6, Freq= 0, CH_0, rank 0
2379 00:58:39.728318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2380 00:58:39.728366 ==
2381 00:58:39.728414 Write leveling (Byte 0): 27 => 27
2382 00:58:39.728462 Write leveling (Byte 1): 27 => 27
2383 00:58:39.728509 DramcWriteLeveling(PI) end<-----
2384 00:58:39.728558
2385 00:58:39.728604 ==
2386 00:58:39.728652 Dram Type= 6, Freq= 0, CH_0, rank 0
2387 00:58:39.728700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2388 00:58:39.728748 ==
2389 00:58:39.728797 [Gating] SW mode calibration
2390 00:58:39.728846 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2391 00:58:39.728895 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2392 00:58:39.728943 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2393 00:58:39.728992 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2394 00:58:39.729040 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2395 00:58:39.729087 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2396 00:58:39.729135 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2397 00:58:39.729183 0 11 20 | B1->B0 | 2d2d 2828 | 1 1 | (1 0) (1 0)
2398 00:58:39.729231 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 00:58:39.729279 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 00:58:39.729326 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2401 00:58:39.729374 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2402 00:58:39.729422 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2403 00:58:39.729470 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2404 00:58:39.729517 0 12 16 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
2405 00:58:39.729565 0 12 20 | B1->B0 | 3636 3f3f | 0 1 | (0 0) (0 0)
2406 00:58:39.729613 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 00:58:39.729661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 00:58:39.729709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 00:58:39.729757 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2410 00:58:39.729806 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2411 00:58:39.729888 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2412 00:58:39.729935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2413 00:58:39.729983 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2414 00:58:39.730031 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 00:58:39.730078 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 00:58:39.730126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 00:58:39.730173 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 00:58:39.730225 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 00:58:39.730308 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 00:58:39.730355 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 00:58:39.730593 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 00:58:39.730647 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 00:58:39.730697 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 00:58:39.730745 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 00:58:39.730794 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2426 00:58:39.730842 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2427 00:58:39.730889 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2428 00:58:39.730937 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2429 00:58:39.730985 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2430 00:58:39.731033 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2431 00:58:39.731113 Total UI for P1: 0, mck2ui 16
2432 00:58:39.731161 best dqsien dly found for B0: ( 0, 15, 18)
2433 00:58:39.731209 Total UI for P1: 0, mck2ui 16
2434 00:58:39.731257 best dqsien dly found for B1: ( 0, 15, 20)
2435 00:58:39.731305 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2436 00:58:39.731354 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2437 00:58:39.731402
2438 00:58:39.731450 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2439 00:58:39.731498 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2440 00:58:39.731547 [Gating] SW calibration Done
2441 00:58:39.731594 ==
2442 00:58:39.731642 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 00:58:39.731691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2444 00:58:39.731740 ==
2445 00:58:39.731825 RX Vref Scan: 0
2446 00:58:39.731873
2447 00:58:39.731920 RX Vref 0 -> 0, step: 1
2448 00:58:39.731968
2449 00:58:39.732015 RX Delay -40 -> 252, step: 8
2450 00:58:39.732063 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2451 00:58:39.732112 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2452 00:58:39.732160 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2453 00:58:39.732208 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2454 00:58:39.732256 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2455 00:58:39.732303 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2456 00:58:39.732351 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2457 00:58:39.732399 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2458 00:58:39.732447 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2459 00:58:39.732495 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2460 00:58:39.732542 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2461 00:58:39.732589 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2462 00:58:39.732637 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2463 00:58:39.732684 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2464 00:58:39.732732 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2465 00:58:39.732794 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2466 00:58:39.732857 ==
2467 00:58:39.732905 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 00:58:39.732953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2469 00:58:39.733002 ==
2470 00:58:39.733049 DQS Delay:
2471 00:58:39.733096 DQS0 = 0, DQS1 = 0
2472 00:58:39.733145 DQM Delay:
2473 00:58:39.733192 DQM0 = 115, DQM1 = 106
2474 00:58:39.733239 DQ Delay:
2475 00:58:39.733286 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2476 00:58:39.733334 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2477 00:58:39.733382 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2478 00:58:39.733429 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2479 00:58:39.733477
2480 00:58:39.733524
2481 00:58:39.733571 ==
2482 00:58:39.733618 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 00:58:39.733666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2484 00:58:39.733714 ==
2485 00:58:39.733761
2486 00:58:39.733808
2487 00:58:39.733855 TX Vref Scan disable
2488 00:58:39.733903 == TX Byte 0 ==
2489 00:58:39.733951 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2490 00:58:39.733999 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2491 00:58:39.734047 == TX Byte 1 ==
2492 00:58:39.734094 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2493 00:58:39.734142 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2494 00:58:39.734189 ==
2495 00:58:39.734274 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 00:58:39.734323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2497 00:58:39.734371 ==
2498 00:58:39.734419 TX Vref=22, minBit 10, minWin=25, winSum=417
2499 00:58:39.734467 TX Vref=24, minBit 8, minWin=25, winSum=422
2500 00:58:39.734516 TX Vref=26, minBit 8, minWin=26, winSum=430
2501 00:58:39.734563 TX Vref=28, minBit 10, minWin=26, winSum=435
2502 00:58:39.734611 TX Vref=30, minBit 9, minWin=26, winSum=434
2503 00:58:39.734659 TX Vref=32, minBit 9, minWin=26, winSum=437
2504 00:58:39.734707 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 32
2505 00:58:39.734755
2506 00:58:39.734803 Final TX Range 1 Vref 32
2507 00:58:39.734851
2508 00:58:39.734898 ==
2509 00:58:39.734946 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 00:58:39.734994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2511 00:58:39.735042 ==
2512 00:58:39.735089
2513 00:58:39.735136
2514 00:58:39.735183 TX Vref Scan disable
2515 00:58:39.735231 == TX Byte 0 ==
2516 00:58:39.735279 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2517 00:58:39.735327 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2518 00:58:39.735375 == TX Byte 1 ==
2519 00:58:39.735422 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2520 00:58:39.735471 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2521 00:58:39.735519
2522 00:58:39.735566 [DATLAT]
2523 00:58:39.735613 Freq=1200, CH0 RK0
2524 00:58:39.735661
2525 00:58:39.735709 DATLAT Default: 0xd
2526 00:58:39.735757 0, 0xFFFF, sum = 0
2527 00:58:39.735806 1, 0xFFFF, sum = 0
2528 00:58:39.735855 2, 0xFFFF, sum = 0
2529 00:58:39.735904 3, 0xFFFF, sum = 0
2530 00:58:39.735952 4, 0xFFFF, sum = 0
2531 00:58:39.736001 5, 0xFFFF, sum = 0
2532 00:58:39.736049 6, 0xFFFF, sum = 0
2533 00:58:39.736097 7, 0xFFFF, sum = 0
2534 00:58:39.736145 8, 0xFFFF, sum = 0
2535 00:58:39.736194 9, 0xFFFF, sum = 0
2536 00:58:39.736242 10, 0xFFFF, sum = 0
2537 00:58:39.736291 11, 0x0, sum = 1
2538 00:58:39.736339 12, 0x0, sum = 2
2539 00:58:39.736388 13, 0x0, sum = 3
2540 00:58:39.736435 14, 0x0, sum = 4
2541 00:58:39.736483 best_step = 12
2542 00:58:39.736531
2543 00:58:39.736579 ==
2544 00:58:39.736626 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 00:58:39.736673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2546 00:58:39.736721 ==
2547 00:58:39.736769 RX Vref Scan: 1
2548 00:58:39.736816
2549 00:58:39.736863 Set Vref Range= 32 -> 127
2550 00:58:39.736911
2551 00:58:39.736958 RX Vref 32 -> 127, step: 1
2552 00:58:39.737007
2553 00:58:39.737054 RX Delay -21 -> 252, step: 4
2554 00:58:39.737101
2555 00:58:39.737148 Set Vref, RX VrefLevel [Byte0]: 32
2556 00:58:39.737196 [Byte1]: 32
2557 00:58:39.737243
2558 00:58:39.737291 Set Vref, RX VrefLevel [Byte0]: 33
2559 00:58:39.737338 [Byte1]: 33
2560 00:58:39.737386
2561 00:58:39.737433 Set Vref, RX VrefLevel [Byte0]: 34
2562 00:58:39.737481 [Byte1]: 34
2563 00:58:39.737528
2564 00:58:39.737576 Set Vref, RX VrefLevel [Byte0]: 35
2565 00:58:39.737813 [Byte1]: 35
2566 00:58:39.737867
2567 00:58:39.737916 Set Vref, RX VrefLevel [Byte0]: 36
2568 00:58:39.737995 [Byte1]: 36
2569 00:58:39.738060
2570 00:58:39.738110 Set Vref, RX VrefLevel [Byte0]: 37
2571 00:58:39.738160 [Byte1]: 37
2572 00:58:39.738214
2573 00:58:39.738279 Set Vref, RX VrefLevel [Byte0]: 38
2574 00:58:39.738327 [Byte1]: 38
2575 00:58:39.738376
2576 00:58:39.738424 Set Vref, RX VrefLevel [Byte0]: 39
2577 00:58:39.738472 [Byte1]: 39
2578 00:58:39.738519
2579 00:58:39.738567 Set Vref, RX VrefLevel [Byte0]: 40
2580 00:58:39.738615 [Byte1]: 40
2581 00:58:39.738663
2582 00:58:39.738711 Set Vref, RX VrefLevel [Byte0]: 41
2583 00:58:39.738759 [Byte1]: 41
2584 00:58:39.738806
2585 00:58:39.738854 Set Vref, RX VrefLevel [Byte0]: 42
2586 00:58:39.738902 [Byte1]: 42
2587 00:58:39.738949
2588 00:58:39.738997 Set Vref, RX VrefLevel [Byte0]: 43
2589 00:58:39.739045 [Byte1]: 43
2590 00:58:39.739093
2591 00:58:39.739140 Set Vref, RX VrefLevel [Byte0]: 44
2592 00:58:39.739189 [Byte1]: 44
2593 00:58:39.739237
2594 00:58:39.739284 Set Vref, RX VrefLevel [Byte0]: 45
2595 00:58:39.739332 [Byte1]: 45
2596 00:58:39.739379
2597 00:58:39.739427 Set Vref, RX VrefLevel [Byte0]: 46
2598 00:58:39.739475 [Byte1]: 46
2599 00:58:39.739522
2600 00:58:39.739569 Set Vref, RX VrefLevel [Byte0]: 47
2601 00:58:39.739617 [Byte1]: 47
2602 00:58:39.739665
2603 00:58:39.739713 Set Vref, RX VrefLevel [Byte0]: 48
2604 00:58:39.739761 [Byte1]: 48
2605 00:58:39.739809
2606 00:58:39.739856 Set Vref, RX VrefLevel [Byte0]: 49
2607 00:58:39.739905 [Byte1]: 49
2608 00:58:39.739953
2609 00:58:39.740017 Set Vref, RX VrefLevel [Byte0]: 50
2610 00:58:39.740079 [Byte1]: 50
2611 00:58:39.740127
2612 00:58:39.740191 Set Vref, RX VrefLevel [Byte0]: 51
2613 00:58:39.740284 [Byte1]: 51
2614 00:58:39.740332
2615 00:58:39.740418 Set Vref, RX VrefLevel [Byte0]: 52
2616 00:58:39.740466 [Byte1]: 52
2617 00:58:39.740514
2618 00:58:39.740591 Set Vref, RX VrefLevel [Byte0]: 53
2619 00:58:39.740638 [Byte1]: 53
2620 00:58:39.740686
2621 00:58:39.740748 Set Vref, RX VrefLevel [Byte0]: 54
2622 00:58:39.740812 [Byte1]: 54
2623 00:58:39.740860
2624 00:58:39.740906 Set Vref, RX VrefLevel [Byte0]: 55
2625 00:58:39.740954 [Byte1]: 55
2626 00:58:39.741002
2627 00:58:39.741049 Set Vref, RX VrefLevel [Byte0]: 56
2628 00:58:39.741097 [Byte1]: 56
2629 00:58:39.741145
2630 00:58:39.741192 Set Vref, RX VrefLevel [Byte0]: 57
2631 00:58:39.741239 [Byte1]: 57
2632 00:58:39.741287
2633 00:58:39.741368 Set Vref, RX VrefLevel [Byte0]: 58
2634 00:58:39.741416 [Byte1]: 58
2635 00:58:39.741464
2636 00:58:39.741549 Set Vref, RX VrefLevel [Byte0]: 59
2637 00:58:39.741598 [Byte1]: 59
2638 00:58:39.741646
2639 00:58:39.741716 Set Vref, RX VrefLevel [Byte0]: 60
2640 00:58:39.741778 [Byte1]: 60
2641 00:58:39.741826
2642 00:58:39.741873 Set Vref, RX VrefLevel [Byte0]: 61
2643 00:58:39.741921 [Byte1]: 61
2644 00:58:39.741969
2645 00:58:39.742015 Set Vref, RX VrefLevel [Byte0]: 62
2646 00:58:39.742063 [Byte1]: 62
2647 00:58:39.742110
2648 00:58:39.742158 Set Vref, RX VrefLevel [Byte0]: 63
2649 00:58:39.742205 [Byte1]: 63
2650 00:58:39.742285
2651 00:58:39.742332 Set Vref, RX VrefLevel [Byte0]: 64
2652 00:58:39.742380 [Byte1]: 64
2653 00:58:39.742428
2654 00:58:39.742476 Set Vref, RX VrefLevel [Byte0]: 65
2655 00:58:39.742525 [Byte1]: 65
2656 00:58:39.742573
2657 00:58:39.742621 Set Vref, RX VrefLevel [Byte0]: 66
2658 00:58:39.742669 [Byte1]: 66
2659 00:58:39.742716
2660 00:58:39.742763 Set Vref, RX VrefLevel [Byte0]: 67
2661 00:58:39.742811 [Byte1]: 67
2662 00:58:39.742859
2663 00:58:39.742907 Final RX Vref Byte 0 = 50 to rank0
2664 00:58:39.742955 Final RX Vref Byte 1 = 51 to rank0
2665 00:58:39.743004 Final RX Vref Byte 0 = 50 to rank1
2666 00:58:39.743052 Final RX Vref Byte 1 = 51 to rank1==
2667 00:58:39.743100 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 00:58:39.743149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2669 00:58:39.743197 ==
2670 00:58:39.743245 DQS Delay:
2671 00:58:39.743292 DQS0 = 0, DQS1 = 0
2672 00:58:39.743340 DQM Delay:
2673 00:58:39.743388 DQM0 = 114, DQM1 = 105
2674 00:58:39.743436 DQ Delay:
2675 00:58:39.743484 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2676 00:58:39.743532 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =122
2677 00:58:39.743581 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =98
2678 00:58:39.743629 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2679 00:58:39.743678
2680 00:58:39.743725
2681 00:58:39.743773 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2682 00:58:39.743822 CH0 RK0: MR19=404, MR18=D0D
2683 00:58:39.743871 CH0_RK0: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2684 00:58:39.743919
2685 00:58:39.744001 ----->DramcWriteLeveling(PI) begin...
2686 00:58:39.744050 ==
2687 00:58:39.744099 Dram Type= 6, Freq= 0, CH_0, rank 1
2688 00:58:39.744176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2689 00:58:39.744225 ==
2690 00:58:39.744273 Write leveling (Byte 0): 28 => 28
2691 00:58:39.744321 Write leveling (Byte 1): 25 => 25
2692 00:58:39.744369 DramcWriteLeveling(PI) end<-----
2693 00:58:39.744417
2694 00:58:39.744465 ==
2695 00:58:39.744514 Dram Type= 6, Freq= 0, CH_0, rank 1
2696 00:58:39.744563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2697 00:58:39.744611 ==
2698 00:58:39.744659 [Gating] SW mode calibration
2699 00:58:39.744707 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2700 00:58:39.744756 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2701 00:58:39.744804 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2702 00:58:39.744852 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2703 00:58:39.744901 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2704 00:58:39.744948 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2705 00:58:39.744996 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 0)
2706 00:58:39.745044 0 11 20 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
2707 00:58:39.745091 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2708 00:58:39.745138 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2709 00:58:39.745186 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2710 00:58:39.745425 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2711 00:58:39.745518 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2712 00:58:39.745568 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2713 00:58:39.745632 0 12 16 | B1->B0 | 2828 3737 | 0 0 | (1 1) (0 0)
2714 00:58:39.745681 0 12 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2715 00:58:39.745730 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2716 00:58:39.745779 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 00:58:39.745829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2718 00:58:39.745891 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2719 00:58:39.745939 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2720 00:58:39.745987 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2721 00:58:39.746035 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2722 00:58:39.746083 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2723 00:58:39.746131 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2724 00:58:39.746178 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 00:58:39.746248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 00:58:39.746310 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 00:58:39.746357 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 00:58:39.746405 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 00:58:39.746454 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 00:58:39.746503 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 00:58:39.746551 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 00:58:39.746599 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 00:58:39.746647 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2734 00:58:39.746695 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2735 00:58:39.746743 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2736 00:58:39.746791 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2737 00:58:39.746840 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2738 00:58:39.746888 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2739 00:58:39.746936 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2740 00:58:39.746984 Total UI for P1: 0, mck2ui 16
2741 00:58:39.747032 best dqsien dly found for B0: ( 0, 15, 16)
2742 00:58:39.747080 Total UI for P1: 0, mck2ui 16
2743 00:58:39.747129 best dqsien dly found for B1: ( 0, 15, 18)
2744 00:58:39.747177 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2745 00:58:39.747226 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2746 00:58:39.747273
2747 00:58:39.747321 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2748 00:58:39.747370 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2749 00:58:39.747417 [Gating] SW calibration Done
2750 00:58:39.747464 ==
2751 00:58:39.747512 Dram Type= 6, Freq= 0, CH_0, rank 1
2752 00:58:39.747561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2753 00:58:39.747634 ==
2754 00:58:39.747727 RX Vref Scan: 0
2755 00:58:39.747774
2756 00:58:39.747821 RX Vref 0 -> 0, step: 1
2757 00:58:39.747868
2758 00:58:39.747915 RX Delay -40 -> 252, step: 8
2759 00:58:39.747963 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2760 00:58:39.748011 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2761 00:58:39.748059 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2762 00:58:39.748107 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2763 00:58:39.748154 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2764 00:58:39.748201 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2765 00:58:39.748249 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2766 00:58:39.748297 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2767 00:58:39.748345 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2768 00:58:39.748393 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2769 00:58:39.748441 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2770 00:58:39.748489 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2771 00:58:39.748537 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2772 00:58:39.748617 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2773 00:58:39.748666 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2774 00:58:39.748714 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2775 00:58:39.748762 ==
2776 00:58:39.748810 Dram Type= 6, Freq= 0, CH_0, rank 1
2777 00:58:39.748858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2778 00:58:39.748906 ==
2779 00:58:39.748953 DQS Delay:
2780 00:58:39.749001 DQS0 = 0, DQS1 = 0
2781 00:58:39.749049 DQM Delay:
2782 00:58:39.749097 DQM0 = 114, DQM1 = 106
2783 00:58:39.749144 DQ Delay:
2784 00:58:39.749191 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2785 00:58:39.749240 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2786 00:58:39.749288 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
2787 00:58:39.749335 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2788 00:58:39.749383
2789 00:58:39.749430
2790 00:58:39.749477 ==
2791 00:58:39.749525 Dram Type= 6, Freq= 0, CH_0, rank 1
2792 00:58:39.749573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2793 00:58:39.749621 ==
2794 00:58:39.749668
2795 00:58:39.749716
2796 00:58:39.749763 TX Vref Scan disable
2797 00:58:39.749810 == TX Byte 0 ==
2798 00:58:39.749858 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2799 00:58:39.749906 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2800 00:58:39.749954 == TX Byte 1 ==
2801 00:58:39.750002 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2802 00:58:39.750049 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2803 00:58:39.750097 ==
2804 00:58:39.750145 Dram Type= 6, Freq= 0, CH_0, rank 1
2805 00:58:39.750193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2806 00:58:39.750278 ==
2807 00:58:39.750326 TX Vref=22, minBit 8, minWin=25, winSum=420
2808 00:58:39.750376 TX Vref=24, minBit 11, minWin=25, winSum=422
2809 00:58:39.750425 TX Vref=26, minBit 1, minWin=26, winSum=429
2810 00:58:39.750473 TX Vref=28, minBit 9, minWin=26, winSum=431
2811 00:58:39.750521 TX Vref=30, minBit 9, minWin=26, winSum=434
2812 00:58:39.750569 TX Vref=32, minBit 8, minWin=26, winSum=433
2813 00:58:39.750617 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
2814 00:58:39.750666
2815 00:58:39.750713 Final TX Range 1 Vref 30
2816 00:58:39.750761
2817 00:58:39.750808 ==
2818 00:58:39.750855 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 00:58:39.750904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2820 00:58:39.750952 ==
2821 00:58:39.751033
2822 00:58:39.751080
2823 00:58:39.751128 TX Vref Scan disable
2824 00:58:39.751176 == TX Byte 0 ==
2825 00:58:39.751410 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2826 00:58:39.751463 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2827 00:58:39.751513 == TX Byte 1 ==
2828 00:58:39.751561 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2829 00:58:39.751610 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2830 00:58:39.751658
2831 00:58:39.751705 [DATLAT]
2832 00:58:39.751753 Freq=1200, CH0 RK1
2833 00:58:39.751814
2834 00:58:39.751864 DATLAT Default: 0xc
2835 00:58:39.751912 0, 0xFFFF, sum = 0
2836 00:58:39.751962 1, 0xFFFF, sum = 0
2837 00:58:39.752011 2, 0xFFFF, sum = 0
2838 00:58:39.752060 3, 0xFFFF, sum = 0
2839 00:58:39.752108 4, 0xFFFF, sum = 0
2840 00:58:39.752156 5, 0xFFFF, sum = 0
2841 00:58:39.752205 6, 0xFFFF, sum = 0
2842 00:58:39.752253 7, 0xFFFF, sum = 0
2843 00:58:39.752301 8, 0xFFFF, sum = 0
2844 00:58:39.752349 9, 0xFFFF, sum = 0
2845 00:58:39.752397 10, 0xFFFF, sum = 0
2846 00:58:39.752446 11, 0x0, sum = 1
2847 00:58:39.752494 12, 0x0, sum = 2
2848 00:58:39.752543 13, 0x0, sum = 3
2849 00:58:39.752591 14, 0x0, sum = 4
2850 00:58:39.752639 best_step = 12
2851 00:58:39.752687
2852 00:58:39.752735 ==
2853 00:58:39.752783 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 00:58:39.752831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2855 00:58:39.752880 ==
2856 00:58:39.752927 RX Vref Scan: 0
2857 00:58:39.752975
2858 00:58:39.753023 RX Vref 0 -> 0, step: 1
2859 00:58:39.753070
2860 00:58:39.753117 RX Delay -21 -> 252, step: 4
2861 00:58:39.753165 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2862 00:58:39.753213 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2863 00:58:39.753262 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2864 00:58:39.753310 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2865 00:58:39.753358 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2866 00:58:39.753406 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2867 00:58:39.753454 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2868 00:58:39.753502 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2869 00:58:39.753550 iDelay=195, Bit 8, Center 96 (35 ~ 158) 124
2870 00:58:39.753598 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2871 00:58:39.753646 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2872 00:58:39.753694 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2873 00:58:39.753742 iDelay=195, Bit 12, Center 112 (51 ~ 174) 124
2874 00:58:39.753790 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2875 00:58:39.753838 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
2876 00:58:39.753886 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2877 00:58:39.753933 ==
2878 00:58:39.753981 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 00:58:39.754030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2880 00:58:39.754077 ==
2881 00:58:39.754125 DQS Delay:
2882 00:58:39.754174 DQS0 = 0, DQS1 = 0
2883 00:58:39.754263 DQM Delay:
2884 00:58:39.754312 DQM0 = 114, DQM1 = 105
2885 00:58:39.754360 DQ Delay:
2886 00:58:39.754408 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2887 00:58:39.754456 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2888 00:58:39.754504 DQ8 =96, DQ9 =90, DQ10 =110, DQ11 =96
2889 00:58:39.754551 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2890 00:58:39.754599
2891 00:58:39.754647
2892 00:58:39.754696 [DQSOSCAuto] RK1, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2893 00:58:39.754745 CH0 RK1: MR19=404, MR18=1313
2894 00:58:39.754793 CH0_RK1: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
2895 00:58:39.754841 [RxdqsGatingPostProcess] freq 1200
2896 00:58:39.754890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2897 00:58:39.754938 Pre-setting of DQS Precalculation
2898 00:58:39.754986 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2899 00:58:39.755034 ==
2900 00:58:39.755083 Dram Type= 6, Freq= 0, CH_1, rank 0
2901 00:58:39.755131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2902 00:58:39.755180 ==
2903 00:58:39.755227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2904 00:58:39.755276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2905 00:58:39.755324 [CA 0] Center 37 (7~68) winsize 62
2906 00:58:39.755372 [CA 1] Center 37 (6~68) winsize 63
2907 00:58:39.755420 [CA 2] Center 34 (4~65) winsize 62
2908 00:58:39.755468 [CA 3] Center 33 (3~64) winsize 62
2909 00:58:39.755516 [CA 4] Center 32 (2~63) winsize 62
2910 00:58:39.755565 [CA 5] Center 32 (2~63) winsize 62
2911 00:58:39.755612
2912 00:58:39.755661 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2913 00:58:39.755708
2914 00:58:39.755756 [CATrainingPosCal] consider 1 rank data
2915 00:58:39.755804 u2DelayCellTimex100 = 270/100 ps
2916 00:58:39.755851 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2917 00:58:39.755899 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2918 00:58:39.755947 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2919 00:58:39.755995 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2920 00:58:39.756043 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2921 00:58:39.756090 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2922 00:58:39.756137
2923 00:58:39.756185 CA PerBit enable=1, Macro0, CA PI delay=32
2924 00:58:39.756233
2925 00:58:39.756279 [CBTSetCACLKResult] CA Dly = 32
2926 00:58:39.756327 CS Dly: 6 (0~37)
2927 00:58:39.756374 ==
2928 00:58:39.756422 Dram Type= 6, Freq= 0, CH_1, rank 1
2929 00:58:39.756470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2930 00:58:39.882458 ==
2931 00:58:39.882576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2932 00:58:39.882638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2933 00:58:39.882694 [CA 0] Center 37 (7~68) winsize 62
2934 00:58:39.882749 [CA 1] Center 37 (7~68) winsize 62
2935 00:58:39.882800 [CA 2] Center 33 (3~64) winsize 62
2936 00:58:39.882850 [CA 3] Center 33 (3~64) winsize 62
2937 00:58:39.882900 [CA 4] Center 32 (2~63) winsize 62
2938 00:58:39.882950 [CA 5] Center 32 (1~63) winsize 63
2939 00:58:39.883000
2940 00:58:39.883050 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2941 00:58:39.883100
2942 00:58:39.883149 [CATrainingPosCal] consider 2 rank data
2943 00:58:39.883199 u2DelayCellTimex100 = 270/100 ps
2944 00:58:39.883248 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2945 00:58:39.883297 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2946 00:58:39.883348 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2947 00:58:39.883419 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2948 00:58:39.883469 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2949 00:58:39.883518 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2950 00:58:39.883567
2951 00:58:39.883615 CA PerBit enable=1, Macro0, CA PI delay=32
2952 00:58:39.883665
2953 00:58:39.883713 [CBTSetCACLKResult] CA Dly = 32
2954 00:58:39.883762 CS Dly: 6 (0~38)
2955 00:58:39.883811
2956 00:58:39.883859 ----->DramcWriteLeveling(PI) begin...
2957 00:58:39.883909 ==
2958 00:58:39.884154 Dram Type= 6, Freq= 0, CH_1, rank 0
2959 00:58:39.884209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2960 00:58:39.884260 ==
2961 00:58:39.884308 Write leveling (Byte 0): 22 => 22
2962 00:58:39.884409 Write leveling (Byte 1): 22 => 22
2963 00:58:39.884459 DramcWriteLeveling(PI) end<-----
2964 00:58:39.884538
2965 00:58:39.884615 ==
2966 00:58:39.884677 Dram Type= 6, Freq= 0, CH_1, rank 0
2967 00:58:39.884769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2968 00:58:39.884823 ==
2969 00:58:39.884886 [Gating] SW mode calibration
2970 00:58:39.884935 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2971 00:58:39.884985 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2972 00:58:39.885035 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2973 00:58:39.885084 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2974 00:58:39.885132 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2975 00:58:39.885180 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2976 00:58:39.885229 0 11 16 | B1->B0 | 2f2f 2626 | 0 1 | (0 0) (1 0)
2977 00:58:39.885277 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2978 00:58:39.885325 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 00:58:39.885372 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 00:58:39.885421 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2981 00:58:39.885469 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2982 00:58:39.885518 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2983 00:58:39.885565 0 12 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2984 00:58:39.885614 0 12 16 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
2985 00:58:39.885662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 00:58:39.885709 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 00:58:39.885757 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 00:58:39.885804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 00:58:39.885852 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 00:58:39.885900 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2991 00:58:39.885948 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2992 00:58:39.885996 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2993 00:58:39.886045 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2994 00:58:39.886093 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 00:58:39.886141 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 00:58:39.886189 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 00:58:39.886277 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 00:58:39.886326 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 00:58:39.886374 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 00:58:39.886422 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 00:58:39.886469 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 00:58:39.886517 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 00:58:39.886565 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 00:58:39.886613 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 00:58:39.886661 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 00:58:39.886708 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3007 00:58:39.886756 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3008 00:58:39.886803 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3009 00:58:39.886851 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3010 00:58:39.886899 Total UI for P1: 0, mck2ui 16
3011 00:58:39.886963 best dqsien dly found for B0: ( 0, 15, 16)
3012 00:58:39.887016 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3013 00:58:39.887065 Total UI for P1: 0, mck2ui 16
3014 00:58:39.887114 best dqsien dly found for B1: ( 0, 15, 20)
3015 00:58:39.887162 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3016 00:58:39.887210 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3017 00:58:39.887258
3018 00:58:39.887307 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3019 00:58:39.887355 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3020 00:58:39.887404 [Gating] SW calibration Done
3021 00:58:39.887466 ==
3022 00:58:39.887517 Dram Type= 6, Freq= 0, CH_1, rank 0
3023 00:58:39.887569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3024 00:58:39.887622 ==
3025 00:58:39.887674 RX Vref Scan: 0
3026 00:58:39.887726
3027 00:58:39.887778 RX Vref 0 -> 0, step: 1
3028 00:58:39.887830
3029 00:58:39.887881 RX Delay -40 -> 252, step: 8
3030 00:58:39.887933 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3031 00:58:39.887985 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3032 00:58:39.888037 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3033 00:58:39.888090 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3034 00:58:39.888142 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3035 00:58:39.888195 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3036 00:58:39.888247 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3037 00:58:39.888299 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3038 00:58:39.888351 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3039 00:58:39.888402 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3040 00:58:39.888454 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3041 00:58:39.888506 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3042 00:58:39.888557 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3043 00:58:39.888609 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3044 00:58:39.888661 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3045 00:58:39.888712 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3046 00:58:39.888764 ==
3047 00:58:39.888815 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 00:58:39.888867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3049 00:58:39.888919 ==
3050 00:58:39.888970 DQS Delay:
3051 00:58:39.889022 DQS0 = 0, DQS1 = 0
3052 00:58:39.889074 DQM Delay:
3053 00:58:39.889126 DQM0 = 116, DQM1 = 107
3054 00:58:39.889178 DQ Delay:
3055 00:58:39.889229 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3056 00:58:39.889281 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3057 00:58:39.889332 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3058 00:58:39.889384 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3059 00:58:39.889435
3060 00:58:39.889487
3061 00:58:39.889538 ==
3062 00:58:39.889589 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 00:58:39.889837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3064 00:58:39.889909 ==
3065 00:58:39.889963
3066 00:58:39.890015
3067 00:58:39.890066 TX Vref Scan disable
3068 00:58:39.890156 == TX Byte 0 ==
3069 00:58:39.890244 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3070 00:58:39.890301 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3071 00:58:39.890354 == TX Byte 1 ==
3072 00:58:39.890407 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3073 00:58:39.890459 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3074 00:58:39.890512 ==
3075 00:58:39.890564 Dram Type= 6, Freq= 0, CH_1, rank 0
3076 00:58:39.890617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3077 00:58:39.890670 ==
3078 00:58:39.890722 TX Vref=22, minBit 9, minWin=25, winSum=422
3079 00:58:39.890776 TX Vref=24, minBit 9, minWin=25, winSum=422
3080 00:58:39.890828 TX Vref=26, minBit 1, minWin=26, winSum=427
3081 00:58:39.890880 TX Vref=28, minBit 9, minWin=26, winSum=432
3082 00:58:39.890931 TX Vref=30, minBit 8, minWin=26, winSum=433
3083 00:58:39.890983 TX Vref=32, minBit 9, minWin=25, winSum=431
3084 00:58:39.891035 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3085 00:58:39.891087
3086 00:58:39.891139 Final TX Range 1 Vref 30
3087 00:58:39.891191
3088 00:58:39.891243 ==
3089 00:58:39.891294 Dram Type= 6, Freq= 0, CH_1, rank 0
3090 00:58:39.891346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3091 00:58:39.891398 ==
3092 00:58:39.891449
3093 00:58:39.891500
3094 00:58:39.891551 TX Vref Scan disable
3095 00:58:39.891604 == TX Byte 0 ==
3096 00:58:39.891656 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3097 00:58:39.891708 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3098 00:58:39.891760 == TX Byte 1 ==
3099 00:58:39.891811 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3100 00:58:39.891863 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3101 00:58:39.891915
3102 00:58:39.891966 [DATLAT]
3103 00:58:39.892017 Freq=1200, CH1 RK0
3104 00:58:39.892069
3105 00:58:39.892120 DATLAT Default: 0xd
3106 00:58:39.892172 0, 0xFFFF, sum = 0
3107 00:58:39.892225 1, 0xFFFF, sum = 0
3108 00:58:39.892278 2, 0xFFFF, sum = 0
3109 00:58:39.892331 3, 0xFFFF, sum = 0
3110 00:58:39.892384 4, 0xFFFF, sum = 0
3111 00:58:39.892452 5, 0xFFFF, sum = 0
3112 00:58:39.892508 6, 0xFFFF, sum = 0
3113 00:58:39.892564 7, 0xFFFF, sum = 0
3114 00:58:39.892621 8, 0xFFFF, sum = 0
3115 00:58:39.892678 9, 0xFFFF, sum = 0
3116 00:58:39.892735 10, 0xFFFF, sum = 0
3117 00:58:39.892792 11, 0x0, sum = 1
3118 00:58:39.892849 12, 0x0, sum = 2
3119 00:58:39.892905 13, 0x0, sum = 3
3120 00:58:39.892961 14, 0x0, sum = 4
3121 00:58:39.893018 best_step = 12
3122 00:58:39.893073
3123 00:58:39.893129 ==
3124 00:58:39.893184 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 00:58:39.893240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3126 00:58:39.893297 ==
3127 00:58:39.893352 RX Vref Scan: 1
3128 00:58:39.893408
3129 00:58:39.893463 Set Vref Range= 32 -> 127
3130 00:58:39.893546
3131 00:58:39.893608 RX Vref 32 -> 127, step: 1
3132 00:58:39.893665
3133 00:58:39.893721 RX Delay -29 -> 252, step: 4
3134 00:58:39.893777
3135 00:58:39.893833 Set Vref, RX VrefLevel [Byte0]: 32
3136 00:58:39.893890 [Byte1]: 32
3137 00:58:39.893946
3138 00:58:39.894000 Set Vref, RX VrefLevel [Byte0]: 33
3139 00:58:39.894056 [Byte1]: 33
3140 00:58:39.894112
3141 00:58:39.894168 Set Vref, RX VrefLevel [Byte0]: 34
3142 00:58:39.894233 [Byte1]: 34
3143 00:58:39.894290
3144 00:58:39.894346 Set Vref, RX VrefLevel [Byte0]: 35
3145 00:58:39.894403 [Byte1]: 35
3146 00:58:39.894459
3147 00:58:39.894514 Set Vref, RX VrefLevel [Byte0]: 36
3148 00:58:39.894570 [Byte1]: 36
3149 00:58:39.894626
3150 00:58:39.894682 Set Vref, RX VrefLevel [Byte0]: 37
3151 00:58:39.894738 [Byte1]: 37
3152 00:58:39.894795
3153 00:58:39.894851 Set Vref, RX VrefLevel [Byte0]: 38
3154 00:58:39.894907 [Byte1]: 38
3155 00:58:39.894964
3156 00:58:39.895020 Set Vref, RX VrefLevel [Byte0]: 39
3157 00:58:39.895080 [Byte1]: 39
3158 00:58:39.895152
3159 00:58:39.895209 Set Vref, RX VrefLevel [Byte0]: 40
3160 00:58:39.895265 [Byte1]: 40
3161 00:58:39.895322
3162 00:58:39.895378 Set Vref, RX VrefLevel [Byte0]: 41
3163 00:58:39.895435 [Byte1]: 41
3164 00:58:39.895490
3165 00:58:39.895545 Set Vref, RX VrefLevel [Byte0]: 42
3166 00:58:39.895601 [Byte1]: 42
3167 00:58:39.895656
3168 00:58:39.895711 Set Vref, RX VrefLevel [Byte0]: 43
3169 00:58:39.895768 [Byte1]: 43
3170 00:58:39.895823
3171 00:58:39.895878 Set Vref, RX VrefLevel [Byte0]: 44
3172 00:58:39.895935 [Byte1]: 44
3173 00:58:39.895990
3174 00:58:39.896045 Set Vref, RX VrefLevel [Byte0]: 45
3175 00:58:39.896101 [Byte1]: 45
3176 00:58:39.896157
3177 00:58:39.896212 Set Vref, RX VrefLevel [Byte0]: 46
3178 00:58:39.896267 [Byte1]: 46
3179 00:58:39.896322
3180 00:58:39.896377 Set Vref, RX VrefLevel [Byte0]: 47
3181 00:58:39.896433 [Byte1]: 47
3182 00:58:39.896489
3183 00:58:39.896544 Set Vref, RX VrefLevel [Byte0]: 48
3184 00:58:39.896600 [Byte1]: 48
3185 00:58:39.896656
3186 00:58:39.896711 Set Vref, RX VrefLevel [Byte0]: 49
3187 00:58:39.896767 [Byte1]: 49
3188 00:58:39.896835
3189 00:58:39.896905 Set Vref, RX VrefLevel [Byte0]: 50
3190 00:58:39.896962 [Byte1]: 50
3191 00:58:39.897019
3192 00:58:39.897074 Set Vref, RX VrefLevel [Byte0]: 51
3193 00:58:39.897131 [Byte1]: 51
3194 00:58:39.897188
3195 00:58:39.897243 Set Vref, RX VrefLevel [Byte0]: 52
3196 00:58:39.897299 [Byte1]: 52
3197 00:58:39.897355
3198 00:58:39.897409 Set Vref, RX VrefLevel [Byte0]: 53
3199 00:58:39.897466 [Byte1]: 53
3200 00:58:39.897523
3201 00:58:39.897579 Set Vref, RX VrefLevel [Byte0]: 54
3202 00:58:39.897636 [Byte1]: 54
3203 00:58:39.897692
3204 00:58:39.897747 Set Vref, RX VrefLevel [Byte0]: 55
3205 00:58:39.897803 [Byte1]: 55
3206 00:58:39.897859
3207 00:58:39.897914 Set Vref, RX VrefLevel [Byte0]: 56
3208 00:58:39.897969 [Byte1]: 56
3209 00:58:39.898026
3210 00:58:39.898081 Set Vref, RX VrefLevel [Byte0]: 57
3211 00:58:39.898138 [Byte1]: 57
3212 00:58:39.898194
3213 00:58:39.898261 Set Vref, RX VrefLevel [Byte0]: 58
3214 00:58:39.898319 [Byte1]: 58
3215 00:58:39.898375
3216 00:58:39.898431 Set Vref, RX VrefLevel [Byte0]: 59
3217 00:58:39.898487 [Byte1]: 59
3218 00:58:39.898542
3219 00:58:39.898598 Set Vref, RX VrefLevel [Byte0]: 60
3220 00:58:39.898654 [Byte1]: 60
3221 00:58:39.898710
3222 00:58:39.898766 Set Vref, RX VrefLevel [Byte0]: 61
3223 00:58:39.898822 [Byte1]: 61
3224 00:58:39.898878
3225 00:58:39.898934 Set Vref, RX VrefLevel [Byte0]: 62
3226 00:58:39.898990 [Byte1]: 62
3227 00:58:39.899045
3228 00:58:39.899100 Set Vref, RX VrefLevel [Byte0]: 63
3229 00:58:39.899354 [Byte1]: 63
3230 00:58:39.899435
3231 00:58:39.899494 Set Vref, RX VrefLevel [Byte0]: 64
3232 00:58:39.899551 [Byte1]: 64
3233 00:58:39.899608
3234 00:58:39.899664 Set Vref, RX VrefLevel [Byte0]: 65
3235 00:58:39.899720 [Byte1]: 65
3236 00:58:39.899776
3237 00:58:39.899831 Set Vref, RX VrefLevel [Byte0]: 66
3238 00:58:39.899887 [Byte1]: 66
3239 00:58:39.899943
3240 00:58:39.899999 Final RX Vref Byte 0 = 55 to rank0
3241 00:58:39.900055 Final RX Vref Byte 1 = 50 to rank0
3242 00:58:39.900147 Final RX Vref Byte 0 = 55 to rank1
3243 00:58:39.900208 Final RX Vref Byte 1 = 50 to rank1==
3244 00:58:39.900265 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 00:58:39.900335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3246 00:58:39.900397 ==
3247 00:58:39.900455 DQS Delay:
3248 00:58:39.900512 DQS0 = 0, DQS1 = 0
3249 00:58:39.900569 DQM Delay:
3250 00:58:39.900625 DQM0 = 115, DQM1 = 105
3251 00:58:39.900681 DQ Delay:
3252 00:58:39.900737 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3253 00:58:39.900793 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3254 00:58:39.900848 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3255 00:58:39.900904 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =114
3256 00:58:39.900961
3257 00:58:39.901016
3258 00:58:39.901072 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3259 00:58:39.901129 CH1 RK0: MR19=404, MR18=1818
3260 00:58:39.901185 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3261 00:58:39.901242
3262 00:58:39.901297 ----->DramcWriteLeveling(PI) begin...
3263 00:58:39.901354 ==
3264 00:58:39.901410 Dram Type= 6, Freq= 0, CH_1, rank 1
3265 00:58:39.901466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3266 00:58:39.901522 ==
3267 00:58:39.901578 Write leveling (Byte 0): 19 => 19
3268 00:58:39.901634 Write leveling (Byte 1): 22 => 22
3269 00:58:39.901690 DramcWriteLeveling(PI) end<-----
3270 00:58:39.901747
3271 00:58:39.901802 ==
3272 00:58:39.901857 Dram Type= 6, Freq= 0, CH_1, rank 1
3273 00:58:39.901913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3274 00:58:39.901969 ==
3275 00:58:39.902025 [Gating] SW mode calibration
3276 00:58:39.902083 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3277 00:58:39.902141 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3278 00:58:39.902198 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3279 00:58:39.902267 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3280 00:58:39.902324 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3281 00:58:39.902381 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3282 00:58:39.902437 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
3283 00:58:39.902493 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3284 00:58:39.902549 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3285 00:58:39.902605 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3286 00:58:39.902661 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3287 00:58:39.902717 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3288 00:58:39.902773 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3289 00:58:39.902829 0 12 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
3290 00:58:39.902885 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
3291 00:58:39.902941 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3292 00:58:39.902998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 00:58:39.903055 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3294 00:58:39.903111 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3295 00:58:39.903167 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3296 00:58:39.903223 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3297 00:58:39.903279 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3298 00:58:39.903335 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3299 00:58:39.903390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 00:58:39.903445 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 00:58:39.903532 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 00:58:39.903593 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 00:58:39.903650 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 00:58:39.903706 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 00:58:39.903762 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 00:58:39.903817 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 00:58:39.903873 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 00:58:39.903929 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 00:58:39.903984 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3310 00:58:39.904040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3311 00:58:39.904095 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3312 00:58:39.904151 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3313 00:58:39.904206 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3314 00:58:39.904260 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3315 00:58:39.904315 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3316 00:58:39.904370 Total UI for P1: 0, mck2ui 16
3317 00:58:39.904427 best dqsien dly found for B0: ( 0, 15, 14)
3318 00:58:39.904483 Total UI for P1: 0, mck2ui 16
3319 00:58:39.904539 best dqsien dly found for B1: ( 0, 15, 16)
3320 00:58:39.904594 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3321 00:58:39.904650 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3322 00:58:39.904705
3323 00:58:39.904760 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3324 00:58:39.904815 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3325 00:58:39.904870 [Gating] SW calibration Done
3326 00:58:39.904926 ==
3327 00:58:39.904982 Dram Type= 6, Freq= 0, CH_1, rank 1
3328 00:58:39.905037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3329 00:58:39.905095 ==
3330 00:58:39.905150 RX Vref Scan: 0
3331 00:58:39.905206
3332 00:58:39.905261 RX Vref 0 -> 0, step: 1
3333 00:58:39.905315
3334 00:58:39.905369 RX Delay -40 -> 252, step: 8
3335 00:58:39.905425 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3336 00:58:39.905481 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3337 00:58:39.905537 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3338 00:58:39.905612 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3339 00:58:39.905867 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3340 00:58:39.905929 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3341 00:58:39.905986 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3342 00:58:39.906042 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3343 00:58:39.906098 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3344 00:58:39.906154 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3345 00:58:39.906216 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3346 00:58:39.906277 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3347 00:58:39.906333 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3348 00:58:39.906388 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3349 00:58:39.906443 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3350 00:58:39.906499 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3351 00:58:39.906554 ==
3352 00:58:39.906609 Dram Type= 6, Freq= 0, CH_1, rank 1
3353 00:58:39.906666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3354 00:58:39.906722 ==
3355 00:58:39.906777 DQS Delay:
3356 00:58:39.906832 DQS0 = 0, DQS1 = 0
3357 00:58:39.906888 DQM Delay:
3358 00:58:39.906942 DQM0 = 116, DQM1 = 105
3359 00:58:39.906998 DQ Delay:
3360 00:58:39.907084 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3361 00:58:39.907144 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3362 00:58:39.907201 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3363 00:58:39.907257 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3364 00:58:39.907312
3365 00:58:39.907367
3366 00:58:39.907421 ==
3367 00:58:39.907475 Dram Type= 6, Freq= 0, CH_1, rank 1
3368 00:58:39.907531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3369 00:58:39.907588 ==
3370 00:58:39.907643
3371 00:58:39.907698
3372 00:58:39.907752 TX Vref Scan disable
3373 00:58:39.907808 == TX Byte 0 ==
3374 00:58:39.907863 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3375 00:58:39.907919 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3376 00:58:39.907975 == TX Byte 1 ==
3377 00:58:39.908030 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3378 00:58:39.908085 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3379 00:58:39.908140 ==
3380 00:58:39.908196 Dram Type= 6, Freq= 0, CH_1, rank 1
3381 00:58:39.908252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3382 00:58:39.908308 ==
3383 00:58:39.908363 TX Vref=22, minBit 3, minWin=25, winSum=423
3384 00:58:39.908419 TX Vref=24, minBit 9, minWin=25, winSum=426
3385 00:58:39.908474 TX Vref=26, minBit 8, minWin=26, winSum=433
3386 00:58:39.908529 TX Vref=28, minBit 8, minWin=26, winSum=433
3387 00:58:39.908584 TX Vref=30, minBit 8, minWin=26, winSum=433
3388 00:58:39.908639 TX Vref=32, minBit 9, minWin=26, winSum=434
3389 00:58:39.908695 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3390 00:58:39.908751
3391 00:58:39.908805 Final TX Range 1 Vref 32
3392 00:58:39.908861
3393 00:58:39.908915 ==
3394 00:58:39.908970 Dram Type= 6, Freq= 0, CH_1, rank 1
3395 00:58:39.909025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3396 00:58:39.909080 ==
3397 00:58:39.909134
3398 00:58:39.909188
3399 00:58:39.909243 TX Vref Scan disable
3400 00:58:39.909299 == TX Byte 0 ==
3401 00:58:39.909354 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3402 00:58:39.909410 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3403 00:58:39.909464 == TX Byte 1 ==
3404 00:58:39.909520 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3405 00:58:39.909574 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3406 00:58:39.909629
3407 00:58:39.909683 [DATLAT]
3408 00:58:39.909738 Freq=1200, CH1 RK1
3409 00:58:39.909793
3410 00:58:39.909849 DATLAT Default: 0xc
3411 00:58:39.909904 0, 0xFFFF, sum = 0
3412 00:58:39.909961 1, 0xFFFF, sum = 0
3413 00:58:39.910017 2, 0xFFFF, sum = 0
3414 00:58:39.910120 3, 0xFFFF, sum = 0
3415 00:58:39.910218 4, 0xFFFF, sum = 0
3416 00:58:39.910280 5, 0xFFFF, sum = 0
3417 00:58:39.910337 6, 0xFFFF, sum = 0
3418 00:58:39.910392 7, 0xFFFF, sum = 0
3419 00:58:39.910448 8, 0xFFFF, sum = 0
3420 00:58:39.910504 9, 0xFFFF, sum = 0
3421 00:58:39.910560 10, 0xFFFF, sum = 0
3422 00:58:39.910617 11, 0x0, sum = 1
3423 00:58:39.910673 12, 0x0, sum = 2
3424 00:58:39.910730 13, 0x0, sum = 3
3425 00:58:39.910785 14, 0x0, sum = 4
3426 00:58:39.910841 best_step = 12
3427 00:58:39.910895
3428 00:58:39.910950 ==
3429 00:58:39.911028 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 00:58:39.911086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3431 00:58:39.911142 ==
3432 00:58:39.911197 RX Vref Scan: 0
3433 00:58:39.911253
3434 00:58:39.911307 RX Vref 0 -> 0, step: 1
3435 00:58:39.911362
3436 00:58:39.911418 RX Delay -29 -> 252, step: 4
3437 00:58:39.911474 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3438 00:58:39.911530 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3439 00:58:39.911586 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3440 00:58:39.911640 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3441 00:58:39.911696 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3442 00:58:39.911752 iDelay=199, Bit 5, Center 126 (55 ~ 198) 144
3443 00:58:39.911808 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3444 00:58:39.911863 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3445 00:58:39.911919 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3446 00:58:39.911974 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3447 00:58:39.912030 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3448 00:58:39.912086 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3449 00:58:39.912141 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3450 00:58:39.912197 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3451 00:58:39.912252 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3452 00:58:39.912309 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3453 00:58:39.912364 ==
3454 00:58:39.912419 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 00:58:39.912474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3456 00:58:39.912530 ==
3457 00:58:39.912584 DQS Delay:
3458 00:58:39.912640 DQS0 = 0, DQS1 = 0
3459 00:58:39.912695 DQM Delay:
3460 00:58:39.912750 DQM0 = 115, DQM1 = 103
3461 00:58:39.912805 DQ Delay:
3462 00:58:39.912860 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3463 00:58:39.912916 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3464 00:58:39.912971 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3465 00:58:39.913026 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3466 00:58:39.913081
3467 00:58:39.913135
3468 00:58:39.913190 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3469 00:58:39.913246 CH1 RK1: MR19=404, MR18=909
3470 00:58:39.913301 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3471 00:58:39.913357 [RxdqsGatingPostProcess] freq 1200
3472 00:58:39.913430 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3473 00:58:39.913498 Pre-setting of DQS Precalculation
3474 00:58:39.913554 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3475 00:58:39.913806 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3476 00:58:39.913871 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3477 00:58:39.913928
3478 00:58:39.913982
3479 00:58:39.914037 [Calibration Summary] 2400 Mbps
3480 00:58:39.914093 CH 0, Rank 0
3481 00:58:39.914148 SW Impedance : PASS
3482 00:58:39.914204 DUTY Scan : NO K
3483 00:58:39.914274 ZQ Calibration : PASS
3484 00:58:39.914330 Jitter Meter : NO K
3485 00:58:39.914387 CBT Training : PASS
3486 00:58:39.914443 Write leveling : PASS
3487 00:58:39.914497 RX DQS gating : PASS
3488 00:58:39.914552 RX DQ/DQS(RDDQC) : PASS
3489 00:58:39.914608 TX DQ/DQS : PASS
3490 00:58:39.914663 RX DATLAT : PASS
3491 00:58:39.914718 RX DQ/DQS(Engine): PASS
3492 00:58:39.914774 TX OE : NO K
3493 00:58:39.914830 All Pass.
3494 00:58:39.914885
3495 00:58:39.914940 CH 0, Rank 1
3496 00:58:39.914995 SW Impedance : PASS
3497 00:58:39.915051 DUTY Scan : NO K
3498 00:58:39.915106 ZQ Calibration : PASS
3499 00:58:39.915162 Jitter Meter : NO K
3500 00:58:39.915218 CBT Training : PASS
3501 00:58:39.915274 Write leveling : PASS
3502 00:58:39.915328 RX DQS gating : PASS
3503 00:58:39.915383 RX DQ/DQS(RDDQC) : PASS
3504 00:58:39.915438 TX DQ/DQS : PASS
3505 00:58:39.915494 RX DATLAT : PASS
3506 00:58:39.915549 RX DQ/DQS(Engine): PASS
3507 00:58:39.915604 TX OE : NO K
3508 00:58:39.915660 All Pass.
3509 00:58:39.915715
3510 00:58:39.915769 CH 1, Rank 0
3511 00:58:39.915824 SW Impedance : PASS
3512 00:58:39.915878 DUTY Scan : NO K
3513 00:58:39.915932 ZQ Calibration : PASS
3514 00:58:39.915987 Jitter Meter : NO K
3515 00:58:39.916066 CBT Training : PASS
3516 00:58:39.916125 Write leveling : PASS
3517 00:58:39.916180 RX DQS gating : PASS
3518 00:58:39.916235 RX DQ/DQS(RDDQC) : PASS
3519 00:58:39.916291 TX DQ/DQS : PASS
3520 00:58:39.916346 RX DATLAT : PASS
3521 00:58:39.916402 RX DQ/DQS(Engine): PASS
3522 00:58:39.916456 TX OE : NO K
3523 00:58:39.916511 All Pass.
3524 00:58:39.916565
3525 00:58:39.916630 CH 1, Rank 1
3526 00:58:39.916703 SW Impedance : PASS
3527 00:58:39.916760 DUTY Scan : NO K
3528 00:58:39.916817 ZQ Calibration : PASS
3529 00:58:39.916874 Jitter Meter : NO K
3530 00:58:39.916930 CBT Training : PASS
3531 00:58:39.916986 Write leveling : PASS
3532 00:58:39.917040 RX DQS gating : PASS
3533 00:58:39.917096 RX DQ/DQS(RDDQC) : PASS
3534 00:58:39.917152 TX DQ/DQS : PASS
3535 00:58:39.917208 RX DATLAT : PASS
3536 00:58:39.917264 RX DQ/DQS(Engine): PASS
3537 00:58:39.917320 TX OE : NO K
3538 00:58:39.917376 All Pass.
3539 00:58:39.917444
3540 00:58:39.917493 DramC Write-DBI off
3541 00:58:39.917544 PER_BANK_REFRESH: Hybrid Mode
3542 00:58:39.917594 TX_TRACKING: ON
3543 00:58:39.917644 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3544 00:58:39.917696 [FAST_K] Save calibration result to emmc
3545 00:58:39.917747 dramc_set_vcore_voltage set vcore to 650000
3546 00:58:39.917798 Read voltage for 600, 5
3547 00:58:39.917848 Vio18 = 0
3548 00:58:39.917898 Vcore = 650000
3549 00:58:39.917948 Vdram = 0
3550 00:58:39.917998 Vddq = 0
3551 00:58:39.918048 Vmddr = 0
3552 00:58:39.918098 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3553 00:58:39.918149 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3554 00:58:39.918200 MEM_TYPE=3, freq_sel=19
3555 00:58:39.918260 sv_algorithm_assistance_LP4_1600
3556 00:58:39.918311 ============ PULL DRAM RESETB DOWN ============
3557 00:58:39.918362 ========== PULL DRAM RESETB DOWN end =========
3558 00:58:39.918413 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3559 00:58:39.918464 ===================================
3560 00:58:39.918531 LPDDR4 DRAM CONFIGURATION
3561 00:58:39.918585 ===================================
3562 00:58:39.918636 EX_ROW_EN[0] = 0x0
3563 00:58:39.918687 EX_ROW_EN[1] = 0x0
3564 00:58:39.918737 LP4Y_EN = 0x0
3565 00:58:39.918787 WORK_FSP = 0x0
3566 00:58:39.918837 WL = 0x2
3567 00:58:39.918888 RL = 0x2
3568 00:58:39.918938 BL = 0x2
3569 00:58:39.918988 RPST = 0x0
3570 00:58:39.919038 RD_PRE = 0x0
3571 00:58:39.919088 WR_PRE = 0x1
3572 00:58:39.919138 WR_PST = 0x0
3573 00:58:39.919188 DBI_WR = 0x0
3574 00:58:39.919238 DBI_RD = 0x0
3575 00:58:39.919288 OTF = 0x1
3576 00:58:39.919338 ===================================
3577 00:58:39.919389 ===================================
3578 00:58:39.919440 ANA top config
3579 00:58:39.919490 ===================================
3580 00:58:39.919540 DLL_ASYNC_EN = 0
3581 00:58:39.919590 ALL_SLAVE_EN = 1
3582 00:58:39.919641 NEW_RANK_MODE = 1
3583 00:58:39.919692 DLL_IDLE_MODE = 1
3584 00:58:39.919743 LP45_APHY_COMB_EN = 1
3585 00:58:39.919793 TX_ODT_DIS = 1
3586 00:58:39.919843 NEW_8X_MODE = 1
3587 00:58:39.919893 ===================================
3588 00:58:39.919943 ===================================
3589 00:58:39.919993 data_rate = 1200
3590 00:58:39.920077 CKR = 1
3591 00:58:39.920131 DQ_P2S_RATIO = 8
3592 00:58:39.920182 ===================================
3593 00:58:39.920233 CA_P2S_RATIO = 8
3594 00:58:39.920283 DQ_CA_OPEN = 0
3595 00:58:39.920333 DQ_SEMI_OPEN = 0
3596 00:58:39.920383 CA_SEMI_OPEN = 0
3597 00:58:39.920433 CA_FULL_RATE = 0
3598 00:58:39.920483 DQ_CKDIV4_EN = 1
3599 00:58:39.920532 CA_CKDIV4_EN = 1
3600 00:58:39.920582 CA_PREDIV_EN = 0
3601 00:58:39.920632 PH8_DLY = 0
3602 00:58:39.920681 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3603 00:58:39.920732 DQ_AAMCK_DIV = 4
3604 00:58:39.920781 CA_AAMCK_DIV = 4
3605 00:58:39.920832 CA_ADMCK_DIV = 4
3606 00:58:39.920881 DQ_TRACK_CA_EN = 0
3607 00:58:39.920931 CA_PICK = 600
3608 00:58:39.920981 CA_MCKIO = 600
3609 00:58:39.921031 MCKIO_SEMI = 0
3610 00:58:39.921080 PLL_FREQ = 2288
3611 00:58:39.921130 DQ_UI_PI_RATIO = 32
3612 00:58:39.921180 CA_UI_PI_RATIO = 0
3613 00:58:39.921231 ===================================
3614 00:58:39.921281 ===================================
3615 00:58:39.921332 memory_type:LPDDR4
3616 00:58:39.921383 GP_NUM : 10
3617 00:58:39.921463 SRAM_EN : 1
3618 00:58:39.921516 MD32_EN : 0
3619 00:58:39.921567 ===================================
3620 00:58:39.921619 [ANA_INIT] >>>>>>>>>>>>>>
3621 00:58:39.921669 <<<<<< [CONFIGURE PHASE]: ANA_TX
3622 00:58:39.921720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3623 00:58:39.921771 ===================================
3624 00:58:39.922017 data_rate = 1200,PCW = 0X5800
3625 00:58:39.922076 ===================================
3626 00:58:39.922129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3627 00:58:39.922181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3628 00:58:39.922242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3629 00:58:39.922295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3630 00:58:39.922346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3631 00:58:39.922396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3632 00:58:39.922459 [ANA_INIT] flow start
3633 00:58:39.922508 [ANA_INIT] PLL >>>>>>>>
3634 00:58:39.922556 [ANA_INIT] PLL <<<<<<<<
3635 00:58:39.922604 [ANA_INIT] MIDPI >>>>>>>>
3636 00:58:39.922652 [ANA_INIT] MIDPI <<<<<<<<
3637 00:58:39.922700 [ANA_INIT] DLL >>>>>>>>
3638 00:58:39.922748 [ANA_INIT] flow end
3639 00:58:39.922796 ============ LP4 DIFF to SE enter ============
3640 00:58:39.922845 ============ LP4 DIFF to SE exit ============
3641 00:58:39.922893 [ANA_INIT] <<<<<<<<<<<<<
3642 00:58:39.922941 [Flow] Enable top DCM control >>>>>
3643 00:58:39.922990 [Flow] Enable top DCM control <<<<<
3644 00:58:39.923039 Enable DLL master slave shuffle
3645 00:58:39.923087 ==============================================================
3646 00:58:39.923135 Gating Mode config
3647 00:58:39.923183 ==============================================================
3648 00:58:39.923245 Config description:
3649 00:58:39.923304 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3650 00:58:39.923355 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3651 00:58:39.923405 SELPH_MODE 0: By rank 1: By Phase
3652 00:58:39.923454 ==============================================================
3653 00:58:39.923504 GAT_TRACK_EN = 1
3654 00:58:39.923553 RX_GATING_MODE = 2
3655 00:58:39.923601 RX_GATING_TRACK_MODE = 2
3656 00:58:39.923649 SELPH_MODE = 1
3657 00:58:39.923697 PICG_EARLY_EN = 1
3658 00:58:39.923744 VALID_LAT_VALUE = 1
3659 00:58:39.923793 ==============================================================
3660 00:58:39.923841 Enter into Gating configuration >>>>
3661 00:58:39.923889 Exit from Gating configuration <<<<
3662 00:58:39.923938 Enter into DVFS_PRE_config >>>>>
3663 00:58:39.923986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3664 00:58:39.924037 Exit from DVFS_PRE_config <<<<<
3665 00:58:39.924084 Enter into PICG configuration >>>>
3666 00:58:39.924132 Exit from PICG configuration <<<<
3667 00:58:39.924180 [RX_INPUT] configuration >>>>>
3668 00:58:39.924228 [RX_INPUT] configuration <<<<<
3669 00:58:39.924276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3670 00:58:39.924324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3671 00:58:39.924372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3672 00:58:39.924420 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3673 00:58:39.924468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3674 00:58:39.924516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3675 00:58:39.924564 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3676 00:58:39.924612 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3677 00:58:39.924660 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3678 00:58:39.924708 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3679 00:58:39.924756 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3680 00:58:39.924804 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3681 00:58:39.924852 ===================================
3682 00:58:39.924900 LPDDR4 DRAM CONFIGURATION
3683 00:58:39.924948 ===================================
3684 00:58:39.924995 EX_ROW_EN[0] = 0x0
3685 00:58:39.925073 EX_ROW_EN[1] = 0x0
3686 00:58:39.925120 LP4Y_EN = 0x0
3687 00:58:39.925167 WORK_FSP = 0x0
3688 00:58:39.925232 WL = 0x2
3689 00:58:39.925293 RL = 0x2
3690 00:58:39.925340 BL = 0x2
3691 00:58:39.925388 RPST = 0x0
3692 00:58:39.925435 RD_PRE = 0x0
3693 00:58:39.925481 WR_PRE = 0x1
3694 00:58:39.925528 WR_PST = 0x0
3695 00:58:39.925575 DBI_WR = 0x0
3696 00:58:39.925622 DBI_RD = 0x0
3697 00:58:39.925670 OTF = 0x1
3698 00:58:39.925718 ===================================
3699 00:58:39.925766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3700 00:58:39.925831 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3701 00:58:39.925894 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3702 00:58:39.925942 ===================================
3703 00:58:39.925990 LPDDR4 DRAM CONFIGURATION
3704 00:58:39.926038 ===================================
3705 00:58:39.926087 EX_ROW_EN[0] = 0x10
3706 00:58:39.926135 EX_ROW_EN[1] = 0x0
3707 00:58:39.926183 LP4Y_EN = 0x0
3708 00:58:39.926259 WORK_FSP = 0x0
3709 00:58:39.926349 WL = 0x2
3710 00:58:39.926454 RL = 0x2
3711 00:58:39.926504 BL = 0x2
3712 00:58:39.926552 RPST = 0x0
3713 00:58:39.926631 RD_PRE = 0x0
3714 00:58:39.926684 WR_PRE = 0x1
3715 00:58:39.926772 WR_PST = 0x0
3716 00:58:39.926821 DBI_WR = 0x0
3717 00:58:39.926869 DBI_RD = 0x0
3718 00:58:39.926918 OTF = 0x1
3719 00:58:39.926966 ===================================
3720 00:58:39.927015 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3721 00:58:39.927064 nWR fixed to 30
3722 00:58:39.927113 [ModeRegInit_LP4] CH0 RK0
3723 00:58:39.927161 [ModeRegInit_LP4] CH0 RK1
3724 00:58:39.927209 [ModeRegInit_LP4] CH1 RK0
3725 00:58:39.927257 [ModeRegInit_LP4] CH1 RK1
3726 00:58:39.927304 match AC timing 16
3727 00:58:39.927352 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3728 00:58:39.927402 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3729 00:58:39.927450 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3730 00:58:39.927500 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3731 00:58:39.927737 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3732 00:58:39.927792 ==
3733 00:58:39.927842 Dram Type= 6, Freq= 0, CH_0, rank 0
3734 00:58:39.927891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3735 00:58:39.927940 ==
3736 00:58:39.927988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3737 00:58:39.928036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3738 00:58:39.928086 [CA 0] Center 35 (5~66) winsize 62
3739 00:58:39.928134 [CA 1] Center 35 (5~66) winsize 62
3740 00:58:39.928183 [CA 2] Center 34 (4~65) winsize 62
3741 00:58:39.928231 [CA 3] Center 34 (3~65) winsize 63
3742 00:58:39.928279 [CA 4] Center 33 (3~64) winsize 62
3743 00:58:39.928326 [CA 5] Center 33 (3~64) winsize 62
3744 00:58:39.928375
3745 00:58:39.928422 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3746 00:58:39.928470
3747 00:58:39.928518 [CATrainingPosCal] consider 1 rank data
3748 00:58:39.928565 u2DelayCellTimex100 = 270/100 ps
3749 00:58:39.928614 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3750 00:58:39.928663 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3751 00:58:39.928711 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3752 00:58:39.928758 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3753 00:58:39.928806 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3754 00:58:39.928853 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3755 00:58:39.928900
3756 00:58:39.928947 CA PerBit enable=1, Macro0, CA PI delay=33
3757 00:58:39.928996
3758 00:58:39.929043 [CBTSetCACLKResult] CA Dly = 33
3759 00:58:39.929091 CS Dly: 5 (0~36)
3760 00:58:39.929139 ==
3761 00:58:39.929187 Dram Type= 6, Freq= 0, CH_0, rank 1
3762 00:58:39.929236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3763 00:58:39.929284 ==
3764 00:58:39.929332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3765 00:58:39.929381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3766 00:58:39.929429 [CA 0] Center 35 (5~66) winsize 62
3767 00:58:39.929477 [CA 1] Center 35 (5~66) winsize 62
3768 00:58:39.929526 [CA 2] Center 34 (4~65) winsize 62
3769 00:58:39.929574 [CA 3] Center 34 (3~65) winsize 63
3770 00:58:39.929622 [CA 4] Center 33 (3~64) winsize 62
3771 00:58:39.929669 [CA 5] Center 33 (3~64) winsize 62
3772 00:58:39.929717
3773 00:58:39.929765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3774 00:58:39.929814
3775 00:58:39.929865 [CATrainingPosCal] consider 2 rank data
3776 00:58:39.929936 u2DelayCellTimex100 = 270/100 ps
3777 00:58:39.930015 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3778 00:58:39.930063 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3779 00:58:39.930112 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3780 00:58:39.930160 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3781 00:58:39.930209 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3782 00:58:39.930300 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3783 00:58:39.930348
3784 00:58:39.930396 CA PerBit enable=1, Macro0, CA PI delay=33
3785 00:58:39.930444
3786 00:58:39.930492 [CBTSetCACLKResult] CA Dly = 33
3787 00:58:39.930539 CS Dly: 5 (0~36)
3788 00:58:39.930587
3789 00:58:39.930635 ----->DramcWriteLeveling(PI) begin...
3790 00:58:39.930683 ==
3791 00:58:39.930732 Dram Type= 6, Freq= 0, CH_0, rank 0
3792 00:58:39.930779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3793 00:58:39.930828 ==
3794 00:58:39.930876 Write leveling (Byte 0): 30 => 30
3795 00:58:39.930924 Write leveling (Byte 1): 30 => 30
3796 00:58:39.930972 DramcWriteLeveling(PI) end<-----
3797 00:58:39.931019
3798 00:58:39.931067 ==
3799 00:58:39.931114 Dram Type= 6, Freq= 0, CH_0, rank 0
3800 00:58:39.931162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3801 00:58:39.931210 ==
3802 00:58:39.931258 [Gating] SW mode calibration
3803 00:58:39.931306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3804 00:58:39.931354 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3805 00:58:39.931405 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3806 00:58:39.931455 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3807 00:58:39.931544 0 5 8 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
3808 00:58:39.931593 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
3809 00:58:39.931642 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3810 00:58:39.931710 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3811 00:58:39.931760 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3812 00:58:39.931809 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3813 00:58:39.931857 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3814 00:58:39.931906 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3815 00:58:39.931954 0 6 8 | B1->B0 | 2828 3434 | 0 0 | (1 1) (0 0)
3816 00:58:39.932002 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3817 00:58:39.932050 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3818 00:58:39.932098 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3819 00:58:39.932146 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3820 00:58:39.932193 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3821 00:58:39.932242 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3822 00:58:39.932290 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3823 00:58:39.932338 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3824 00:58:39.932386 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3825 00:58:39.932435 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 00:58:39.932483 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 00:58:39.932531 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 00:58:39.932578 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 00:58:39.932626 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 00:58:39.932674 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 00:58:39.932722 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 00:58:39.932770 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 00:58:39.932818 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 00:58:39.932866 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 00:58:39.932914 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3836 00:58:39.932962 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3837 00:58:39.933009 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3838 00:58:39.933057 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3839 00:58:39.933328 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3840 00:58:39.933385 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3841 00:58:39.933436 Total UI for P1: 0, mck2ui 16
3842 00:58:39.933485 best dqsien dly found for B0: ( 0, 9, 8)
3843 00:58:39.933534 Total UI for P1: 0, mck2ui 16
3844 00:58:39.933594 best dqsien dly found for B1: ( 0, 9, 8)
3845 00:58:39.936855 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3846 00:58:39.940011 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3847 00:58:39.940086
3848 00:58:39.943411 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3849 00:58:39.946737 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3850 00:58:39.950004 [Gating] SW calibration Done
3851 00:58:39.950081 ==
3852 00:58:39.953313 Dram Type= 6, Freq= 0, CH_0, rank 0
3853 00:58:39.959850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3854 00:58:39.959927 ==
3855 00:58:39.959985 RX Vref Scan: 0
3856 00:58:39.960039
3857 00:58:39.963044 RX Vref 0 -> 0, step: 1
3858 00:58:39.963120
3859 00:58:39.966196 RX Delay -230 -> 252, step: 16
3860 00:58:39.969521 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3861 00:58:39.972941 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3862 00:58:39.976208 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3863 00:58:39.983086 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3864 00:58:39.986483 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3865 00:58:39.989769 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3866 00:58:39.992869 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3867 00:58:39.999605 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3868 00:58:40.003028 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3869 00:58:40.006181 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3870 00:58:40.009592 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3871 00:58:40.012876 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3872 00:58:40.019530 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3873 00:58:40.022791 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3874 00:58:40.025883 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3875 00:58:40.029221 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3876 00:58:40.032465 ==
3877 00:58:40.035947 Dram Type= 6, Freq= 0, CH_0, rank 0
3878 00:58:40.039121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3879 00:58:40.039200 ==
3880 00:58:40.039259 DQS Delay:
3881 00:58:40.042704 DQS0 = 0, DQS1 = 0
3882 00:58:40.042779 DQM Delay:
3883 00:58:40.045901 DQM0 = 37, DQM1 = 33
3884 00:58:40.045976 DQ Delay:
3885 00:58:40.049342 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3886 00:58:40.052457 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3887 00:58:40.055863 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3888 00:58:40.059127 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3889 00:58:40.059203
3890 00:58:40.059261
3891 00:58:40.059314 ==
3892 00:58:40.062527 Dram Type= 6, Freq= 0, CH_0, rank 0
3893 00:58:40.066006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3894 00:58:40.066083 ==
3895 00:58:40.066141
3896 00:58:40.066195
3897 00:58:40.069235 TX Vref Scan disable
3898 00:58:40.072608 == TX Byte 0 ==
3899 00:58:40.075889 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3900 00:58:40.079225 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3901 00:58:40.082586 == TX Byte 1 ==
3902 00:58:40.085812 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3903 00:58:40.089100 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3904 00:58:40.089176 ==
3905 00:58:40.092619 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 00:58:40.095826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3907 00:58:40.098954 ==
3908 00:58:40.099030
3909 00:58:40.099088
3910 00:58:40.099142 TX Vref Scan disable
3911 00:58:40.103049 == TX Byte 0 ==
3912 00:58:40.106308 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3913 00:58:40.112884 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3914 00:58:40.112962 == TX Byte 1 ==
3915 00:58:40.116140 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3916 00:58:40.122921 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3917 00:58:40.122997
3918 00:58:40.123056 [DATLAT]
3919 00:58:40.123111 Freq=600, CH0 RK0
3920 00:58:40.123163
3921 00:58:40.126095 DATLAT Default: 0x9
3922 00:58:40.159489 0, 0xFFFF, sum = 0
3923 00:58:40.159807 1, 0xFFFF, sum = 0
3924 00:58:40.159871 2, 0xFFFF, sum = 0
3925 00:58:40.159964 3, 0xFFFF, sum = 0
3926 00:58:40.160018 4, 0xFFFF, sum = 0
3927 00:58:40.160069 5, 0xFFFF, sum = 0
3928 00:58:40.160124 6, 0xFFFF, sum = 0
3929 00:58:40.160174 7, 0x0, sum = 1
3930 00:58:40.160224 8, 0x0, sum = 2
3931 00:58:40.160274 9, 0x0, sum = 3
3932 00:58:40.160323 10, 0x0, sum = 4
3933 00:58:40.160374 best_step = 8
3934 00:58:40.160423
3935 00:58:40.160470 ==
3936 00:58:40.160519 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 00:58:40.160567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3938 00:58:40.160617 ==
3939 00:58:40.160665 RX Vref Scan: 1
3940 00:58:40.160714
3941 00:58:40.160762 RX Vref 0 -> 0, step: 1
3942 00:58:40.160811
3943 00:58:40.160858 RX Delay -195 -> 252, step: 8
3944 00:58:40.160907
3945 00:58:40.162675 Set Vref, RX VrefLevel [Byte0]: 50
3946 00:58:40.165823 [Byte1]: 51
3947 00:58:40.169940
3948 00:58:40.170010 Final RX Vref Byte 0 = 50 to rank0
3949 00:58:40.173374 Final RX Vref Byte 1 = 51 to rank0
3950 00:58:40.176705 Final RX Vref Byte 0 = 50 to rank1
3951 00:58:40.179883 Final RX Vref Byte 1 = 51 to rank1==
3952 00:58:40.183571 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 00:58:40.189918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3954 00:58:40.189989 ==
3955 00:58:40.190047 DQS Delay:
3956 00:58:40.190100 DQS0 = 0, DQS1 = 0
3957 00:58:40.193203 DQM Delay:
3958 00:58:40.193269 DQM0 = 39, DQM1 = 30
3959 00:58:40.196413 DQ Delay:
3960 00:58:40.199844 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =40
3961 00:58:40.203195 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3962 00:58:40.203259 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
3963 00:58:40.209904 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3964 00:58:40.209971
3965 00:58:40.210025
3966 00:58:40.216508 [DQSOSCAuto] RK0, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
3967 00:58:40.219866 CH0 RK0: MR19=808, MR18=6060
3968 00:58:40.226665 CH0_RK0: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
3969 00:58:40.226729
3970 00:58:40.229769 ----->DramcWriteLeveling(PI) begin...
3971 00:58:40.229832 ==
3972 00:58:40.233143 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 00:58:40.236458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3974 00:58:40.236552 ==
3975 00:58:40.239763 Write leveling (Byte 0): 33 => 33
3976 00:58:40.243084 Write leveling (Byte 1): 33 => 33
3977 00:58:40.246363 DramcWriteLeveling(PI) end<-----
3978 00:58:40.246436
3979 00:58:40.246494 ==
3980 00:58:40.249671 Dram Type= 6, Freq= 0, CH_0, rank 1
3981 00:58:40.253246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3982 00:58:40.253337 ==
3983 00:58:40.256370 [Gating] SW mode calibration
3984 00:58:40.262995 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 00:58:40.269497 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3986 00:58:40.272776 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 00:58:40.279815 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 00:58:40.282995 0 5 8 | B1->B0 | 3434 3131 | 1 1 | (0 1) (0 0)
3989 00:58:40.286057 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3990 00:58:40.292674 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 00:58:40.295981 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 00:58:40.299546 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 00:58:40.302737 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 00:58:40.309162 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:58:40.312508 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:58:40.315762 0 6 8 | B1->B0 | 2a2a 3333 | 1 1 | (0 0) (0 0)
3997 00:58:40.322596 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3998 00:58:40.325860 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 00:58:40.329025 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 00:58:40.335829 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 00:58:40.338951 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 00:58:40.342292 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:58:40.348768 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:58:40.352321 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4005 00:58:40.355831 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4006 00:58:40.362365 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:58:40.365569 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:58:40.368884 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:58:40.375691 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:58:40.379148 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:58:40.382326 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:58:40.388907 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:58:40.392156 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:58:40.395430 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:58:40.402119 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:58:40.405478 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:58:40.408903 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:58:40.415627 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:58:40.419031 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:58:40.422075 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4021 00:58:40.425470 Total UI for P1: 0, mck2ui 16
4022 00:58:40.428682 best dqsien dly found for B0: ( 0, 9, 6)
4023 00:58:40.435409 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 00:58:40.435479 Total UI for P1: 0, mck2ui 16
4025 00:58:40.438748 best dqsien dly found for B1: ( 0, 9, 8)
4026 00:58:40.445124 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4027 00:58:40.448797 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4028 00:58:40.448894
4029 00:58:40.452009 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4030 00:58:40.455180 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4031 00:58:40.458757 [Gating] SW calibration Done
4032 00:58:40.458851 ==
4033 00:58:40.461770 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 00:58:40.465103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4035 00:58:40.465201 ==
4036 00:58:40.468558 RX Vref Scan: 0
4037 00:58:40.468638
4038 00:58:40.468702 RX Vref 0 -> 0, step: 1
4039 00:58:40.468756
4040 00:58:40.471650 RX Delay -230 -> 252, step: 16
4041 00:58:40.475041 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4042 00:58:40.481591 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4043 00:58:40.484882 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4044 00:58:40.489148 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4045 00:58:40.491472 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4046 00:58:40.498227 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4047 00:58:40.501587 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4048 00:58:40.504730 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4049 00:58:40.507914 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4050 00:58:40.511187 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4051 00:58:40.517849 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4052 00:58:40.521003 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4053 00:58:40.524321 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4054 00:58:40.527853 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4055 00:58:40.534507 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4056 00:58:40.537751 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4057 00:58:40.537861 ==
4058 00:58:40.541098 Dram Type= 6, Freq= 0, CH_0, rank 1
4059 00:58:40.544307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4060 00:58:40.544412 ==
4061 00:58:40.547756 DQS Delay:
4062 00:58:40.547851 DQS0 = 0, DQS1 = 0
4063 00:58:40.551020 DQM Delay:
4064 00:58:40.551123 DQM0 = 41, DQM1 = 33
4065 00:58:40.551213 DQ Delay:
4066 00:58:40.554129 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4067 00:58:40.557649 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4068 00:58:40.560869 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4069 00:58:40.564128 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4070 00:58:40.564204
4071 00:58:40.564277
4072 00:58:40.567598 ==
4073 00:58:40.567726 Dram Type= 6, Freq= 0, CH_0, rank 1
4074 00:58:40.574169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4075 00:58:40.574298 ==
4076 00:58:40.574360
4077 00:58:40.574416
4078 00:58:40.577432 TX Vref Scan disable
4079 00:58:40.577531 == TX Byte 0 ==
4080 00:58:40.580901 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4081 00:58:40.587361 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4082 00:58:40.587456 == TX Byte 1 ==
4083 00:58:40.590816 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4084 00:58:40.597340 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4085 00:58:40.597420 ==
4086 00:58:40.600660 Dram Type= 6, Freq= 0, CH_0, rank 1
4087 00:58:40.603954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4088 00:58:40.604030 ==
4089 00:58:40.604090
4090 00:58:40.604152
4091 00:58:40.607386 TX Vref Scan disable
4092 00:58:40.610541 == TX Byte 0 ==
4093 00:58:40.613705 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4094 00:58:40.617066 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4095 00:58:40.620416 == TX Byte 1 ==
4096 00:58:40.623624 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4097 00:58:40.626973 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4098 00:58:40.627050
4099 00:58:40.630530 [DATLAT]
4100 00:58:40.630607 Freq=600, CH0 RK1
4101 00:58:40.630686
4102 00:58:40.633771 DATLAT Default: 0x8
4103 00:58:40.633847 0, 0xFFFF, sum = 0
4104 00:58:40.636887 1, 0xFFFF, sum = 0
4105 00:58:40.636964 2, 0xFFFF, sum = 0
4106 00:58:40.640086 3, 0xFFFF, sum = 0
4107 00:58:40.640165 4, 0xFFFF, sum = 0
4108 00:58:40.643667 5, 0xFFFF, sum = 0
4109 00:58:40.643738 6, 0xFFFF, sum = 0
4110 00:58:40.646656 7, 0x0, sum = 1
4111 00:58:40.646732 8, 0x0, sum = 2
4112 00:58:40.649976 9, 0x0, sum = 3
4113 00:58:40.650056 10, 0x0, sum = 4
4114 00:58:40.653399 best_step = 8
4115 00:58:40.653515
4116 00:58:40.653617 ==
4117 00:58:40.656969 Dram Type= 6, Freq= 0, CH_0, rank 1
4118 00:58:40.660105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4119 00:58:40.660192 ==
4120 00:58:40.663233 RX Vref Scan: 0
4121 00:58:40.663308
4122 00:58:40.663376 RX Vref 0 -> 0, step: 1
4123 00:58:40.663434
4124 00:58:40.666739 RX Delay -195 -> 252, step: 8
4125 00:58:40.673354 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4126 00:58:40.676658 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4127 00:58:40.679792 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4128 00:58:40.683221 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4129 00:58:40.689738 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4130 00:58:40.693053 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4131 00:58:40.696642 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4132 00:58:40.699600 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4133 00:58:40.706318 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4134 00:58:40.709583 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4135 00:58:40.712795 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4136 00:58:40.716348 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4137 00:58:40.723060 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4138 00:58:40.726176 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4139 00:58:40.729419 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4140 00:58:40.733035 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4141 00:58:40.733104 ==
4142 00:58:40.735967 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 00:58:40.742818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4144 00:58:40.742901 ==
4145 00:58:40.742979 DQS Delay:
4146 00:58:40.745803 DQS0 = 0, DQS1 = 0
4147 00:58:40.745869 DQM Delay:
4148 00:58:40.745924 DQM0 = 42, DQM1 = 33
4149 00:58:40.749142 DQ Delay:
4150 00:58:40.752602 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4151 00:58:40.755886 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4152 00:58:40.759107 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4153 00:58:40.762342 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4154 00:58:40.762420
4155 00:58:40.762510
4156 00:58:40.769037 [DQSOSCAuto] RK1, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4157 00:58:40.772354 CH0 RK1: MR19=808, MR18=7474
4158 00:58:40.779157 CH0_RK1: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4159 00:58:40.782146 [RxdqsGatingPostProcess] freq 600
4160 00:58:40.785657 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4161 00:58:40.788918 Pre-setting of DQS Precalculation
4162 00:58:40.795686 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4163 00:58:40.795764 ==
4164 00:58:40.799039 Dram Type= 6, Freq= 0, CH_1, rank 0
4165 00:58:40.802384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4166 00:58:40.802461 ==
4167 00:58:40.808933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4168 00:58:40.815380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4169 00:58:40.818725 [CA 0] Center 35 (5~66) winsize 62
4170 00:58:40.822085 [CA 1] Center 35 (5~66) winsize 62
4171 00:58:40.825549 [CA 2] Center 33 (3~64) winsize 62
4172 00:58:40.828815 [CA 3] Center 33 (3~64) winsize 62
4173 00:58:40.832212 [CA 4] Center 33 (2~64) winsize 63
4174 00:58:40.835529 [CA 5] Center 33 (2~64) winsize 63
4175 00:58:40.835604
4176 00:58:40.838588 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4177 00:58:40.838665
4178 00:58:40.842082 [CATrainingPosCal] consider 1 rank data
4179 00:58:40.845169 u2DelayCellTimex100 = 270/100 ps
4180 00:58:40.848569 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4181 00:58:40.851811 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4182 00:58:40.855196 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4183 00:58:40.858393 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4184 00:58:40.861688 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4185 00:58:40.865262 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4186 00:58:40.865362
4187 00:58:40.871912 CA PerBit enable=1, Macro0, CA PI delay=33
4188 00:58:40.871988
4189 00:58:40.872047 [CBTSetCACLKResult] CA Dly = 33
4190 00:58:40.875117 CS Dly: 3 (0~34)
4191 00:58:40.875192 ==
4192 00:58:40.878231 Dram Type= 6, Freq= 0, CH_1, rank 1
4193 00:58:40.881701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4194 00:58:40.881778 ==
4195 00:58:40.888252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4196 00:58:40.894899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4197 00:58:40.898172 [CA 0] Center 35 (5~66) winsize 62
4198 00:58:40.901640 [CA 1] Center 34 (4~65) winsize 62
4199 00:58:40.904844 [CA 2] Center 33 (3~64) winsize 62
4200 00:58:40.908223 [CA 3] Center 33 (3~64) winsize 62
4201 00:58:40.911537 [CA 4] Center 33 (2~64) winsize 63
4202 00:58:40.914715 [CA 5] Center 32 (2~63) winsize 62
4203 00:58:40.914791
4204 00:58:40.918049 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4205 00:58:40.918125
4206 00:58:40.921390 [CATrainingPosCal] consider 2 rank data
4207 00:58:40.924627 u2DelayCellTimex100 = 270/100 ps
4208 00:58:40.927981 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4209 00:58:40.931273 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4210 00:58:40.934672 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4211 00:58:40.938192 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4212 00:58:40.941390 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4213 00:58:40.948016 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4214 00:58:40.948102
4215 00:58:40.951304 CA PerBit enable=1, Macro0, CA PI delay=32
4216 00:58:40.951384
4217 00:58:40.954634 [CBTSetCACLKResult] CA Dly = 32
4218 00:58:40.954714 CS Dly: 4 (0~36)
4219 00:58:40.954776
4220 00:58:40.958082 ----->DramcWriteLeveling(PI) begin...
4221 00:58:40.958162 ==
4222 00:58:40.961391 Dram Type= 6, Freq= 0, CH_1, rank 0
4223 00:58:40.964533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4224 00:58:40.967936 ==
4225 00:58:40.968050 Write leveling (Byte 0): 30 => 30
4226 00:58:40.971175 Write leveling (Byte 1): 29 => 29
4227 00:58:40.974710 DramcWriteLeveling(PI) end<-----
4228 00:58:40.974799
4229 00:58:40.974891 ==
4230 00:58:40.977807 Dram Type= 6, Freq= 0, CH_1, rank 0
4231 00:58:40.984122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4232 00:58:40.984251 ==
4233 00:58:40.987456 [Gating] SW mode calibration
4234 00:58:40.994176 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4235 00:58:40.997421 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4236 00:58:41.003831 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 00:58:41.007025 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
4238 00:58:41.010345 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4239 00:58:41.017232 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 00:58:41.020723 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 00:58:41.023734 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 00:58:41.030273 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 00:58:41.033929 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 00:58:41.037096 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 00:58:41.043458 0 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4246 00:58:41.046720 0 6 8 | B1->B0 | 3838 4545 | 0 0 | (1 1) (0 0)
4247 00:58:41.050113 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 00:58:41.056643 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 00:58:41.060342 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 00:58:41.063738 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 00:58:41.070440 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 00:58:41.073249 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 00:58:41.076677 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4254 00:58:41.083672 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4255 00:58:41.087003 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:58:41.090293 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:58:41.097063 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:58:41.100262 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:58:41.103487 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:58:41.110542 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:58:41.113567 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:58:41.116587 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:58:41.123082 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:58:41.126403 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:58:41.129699 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:58:41.136240 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:58:41.139570 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 00:58:41.142920 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 00:58:41.149824 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 00:58:41.153032 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4271 00:58:41.156241 Total UI for P1: 0, mck2ui 16
4272 00:58:41.159508 best dqsien dly found for B0: ( 0, 9, 6)
4273 00:58:41.162842 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 00:58:41.166330 Total UI for P1: 0, mck2ui 16
4275 00:58:41.169465 best dqsien dly found for B1: ( 0, 9, 10)
4276 00:58:41.172566 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4277 00:58:41.175848 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4278 00:58:41.175966
4279 00:58:41.179243 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4280 00:58:41.185947 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4281 00:58:41.186059 [Gating] SW calibration Done
4282 00:58:41.186148 ==
4283 00:58:41.189525 Dram Type= 6, Freq= 0, CH_1, rank 0
4284 00:58:41.196025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4285 00:58:41.196107 ==
4286 00:58:41.196166 RX Vref Scan: 0
4287 00:58:41.196220
4288 00:58:41.199362 RX Vref 0 -> 0, step: 1
4289 00:58:41.199438
4290 00:58:41.202584 RX Delay -230 -> 252, step: 16
4291 00:58:41.205793 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4292 00:58:41.209102 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4293 00:58:41.215663 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4294 00:58:41.218958 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4295 00:58:41.222357 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4296 00:58:41.225787 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4297 00:58:41.228845 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4298 00:58:41.235569 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4299 00:58:41.238779 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4300 00:58:41.242133 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4301 00:58:41.245565 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4302 00:58:41.252162 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4303 00:58:41.255346 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4304 00:58:41.258565 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4305 00:58:41.261868 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4306 00:58:41.268942 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4307 00:58:41.269026 ==
4308 00:58:41.271649 Dram Type= 6, Freq= 0, CH_1, rank 0
4309 00:58:41.274954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4310 00:58:41.275030 ==
4311 00:58:41.275089 DQS Delay:
4312 00:58:41.278180 DQS0 = 0, DQS1 = 0
4313 00:58:41.278298 DQM Delay:
4314 00:58:41.281469 DQM0 = 38, DQM1 = 30
4315 00:58:41.281560 DQ Delay:
4316 00:58:41.284846 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4317 00:58:41.288132 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4318 00:58:41.291561 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4319 00:58:41.294887 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4320 00:58:41.294962
4321 00:58:41.295021
4322 00:58:41.295074 ==
4323 00:58:41.298149 Dram Type= 6, Freq= 0, CH_1, rank 0
4324 00:58:41.301524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4325 00:58:41.301601 ==
4326 00:58:41.304730
4327 00:58:41.304806
4328 00:58:41.304865 TX Vref Scan disable
4329 00:58:41.308068 == TX Byte 0 ==
4330 00:58:41.311471 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4331 00:58:41.314754 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4332 00:58:41.317966 == TX Byte 1 ==
4333 00:58:41.321284 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4334 00:58:41.324758 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4335 00:58:41.327722 ==
4336 00:58:41.331071 Dram Type= 6, Freq= 0, CH_1, rank 0
4337 00:58:41.334203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4338 00:58:41.334331 ==
4339 00:58:41.334391
4340 00:58:41.334444
4341 00:58:41.337510 TX Vref Scan disable
4342 00:58:41.340922 == TX Byte 0 ==
4343 00:58:41.344055 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4344 00:58:41.347409 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4345 00:58:41.350663 == TX Byte 1 ==
4346 00:58:41.353951 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4347 00:58:41.357261 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4348 00:58:41.357339
4349 00:58:41.357396 [DATLAT]
4350 00:58:41.360930 Freq=600, CH1 RK0
4351 00:58:41.361010
4352 00:58:41.364026 DATLAT Default: 0x9
4353 00:58:41.364110 0, 0xFFFF, sum = 0
4354 00:58:41.367185 1, 0xFFFF, sum = 0
4355 00:58:41.367269 2, 0xFFFF, sum = 0
4356 00:58:41.370562 3, 0xFFFF, sum = 0
4357 00:58:41.370647 4, 0xFFFF, sum = 0
4358 00:58:41.373883 5, 0xFFFF, sum = 0
4359 00:58:41.373959 6, 0xFFFF, sum = 0
4360 00:58:41.377120 7, 0x0, sum = 1
4361 00:58:41.377196 8, 0x0, sum = 2
4362 00:58:41.380602 9, 0x0, sum = 3
4363 00:58:41.380680 10, 0x0, sum = 4
4364 00:58:41.380740 best_step = 8
4365 00:58:41.380793
4366 00:58:41.383783 ==
4367 00:58:41.383861 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 00:58:41.390699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4369 00:58:41.390777 ==
4370 00:58:41.390837 RX Vref Scan: 1
4371 00:58:41.390891
4372 00:58:41.393820 RX Vref 0 -> 0, step: 1
4373 00:58:41.393895
4374 00:58:41.397042 RX Delay -195 -> 252, step: 8
4375 00:58:41.397117
4376 00:58:41.400194 Set Vref, RX VrefLevel [Byte0]: 55
4377 00:58:41.403706 [Byte1]: 50
4378 00:58:41.403782
4379 00:58:41.406906 Final RX Vref Byte 0 = 55 to rank0
4380 00:58:41.410439 Final RX Vref Byte 1 = 50 to rank0
4381 00:58:41.413506 Final RX Vref Byte 0 = 55 to rank1
4382 00:58:41.416865 Final RX Vref Byte 1 = 50 to rank1==
4383 00:58:41.420274 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 00:58:41.423511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4385 00:58:41.426926 ==
4386 00:58:41.427000 DQS Delay:
4387 00:58:41.427057 DQS0 = 0, DQS1 = 0
4388 00:58:41.430180 DQM Delay:
4389 00:58:41.430264 DQM0 = 37, DQM1 = 30
4390 00:58:41.433389 DQ Delay:
4391 00:58:41.433464 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4392 00:58:41.436532 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4393 00:58:41.439799 DQ8 =8, DQ9 =20, DQ10 =32, DQ11 =24
4394 00:58:41.443227 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4395 00:58:41.443302
4396 00:58:41.446628
4397 00:58:41.453137 [DQSOSCAuto] RK0, (LSB)MR18= 0x7676, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4398 00:58:41.456541 CH1 RK0: MR19=808, MR18=7676
4399 00:58:41.463244 CH1_RK0: MR19=0x808, MR18=0x7676, DQSOSC=387, MR23=63, INC=175, DEC=116
4400 00:58:41.463357
4401 00:58:41.466241 ----->DramcWriteLeveling(PI) begin...
4402 00:58:41.466332 ==
4403 00:58:41.469472 Dram Type= 6, Freq= 0, CH_1, rank 1
4404 00:58:41.472814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4405 00:58:41.472892 ==
4406 00:58:41.476129 Write leveling (Byte 0): 28 => 28
4407 00:58:41.479526 Write leveling (Byte 1): 28 => 28
4408 00:58:41.482875 DramcWriteLeveling(PI) end<-----
4409 00:58:41.482952
4410 00:58:41.483010 ==
4411 00:58:41.486354 Dram Type= 6, Freq= 0, CH_1, rank 1
4412 00:58:41.489507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4413 00:58:41.489584 ==
4414 00:58:41.492821 [Gating] SW mode calibration
4415 00:58:41.499225 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4416 00:58:41.506105 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4417 00:58:41.509250 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 00:58:41.512564 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4419 00:58:41.519131 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4420 00:58:41.522762 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 00:58:41.525864 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 00:58:41.532267 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 00:58:41.535680 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 00:58:41.538878 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 00:58:41.545547 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 00:58:41.548776 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4427 00:58:41.552234 0 6 8 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4428 00:58:41.558771 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:58:41.562090 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 00:58:41.565619 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 00:58:41.572033 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 00:58:41.575364 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 00:58:41.578694 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 00:58:41.585463 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4435 00:58:41.588665 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4436 00:58:41.591988 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:58:41.598641 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:58:41.601886 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:58:41.605091 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:58:41.611710 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:58:41.615116 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:58:41.618252 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:58:41.624987 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:58:41.628371 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:58:41.631524 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:58:41.638407 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:58:41.641399 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:58:41.644730 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:58:41.651298 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:58:41.654630 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4451 00:58:41.658215 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4452 00:58:41.664359 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 00:58:41.667898 Total UI for P1: 0, mck2ui 16
4454 00:58:41.671341 best dqsien dly found for B0: ( 0, 9, 6)
4455 00:58:41.671416 Total UI for P1: 0, mck2ui 16
4456 00:58:41.677858 best dqsien dly found for B1: ( 0, 9, 10)
4457 00:58:41.680993 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4458 00:58:41.684281 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4459 00:58:41.684356
4460 00:58:41.687843 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4461 00:58:41.691127 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4462 00:58:41.694433 [Gating] SW calibration Done
4463 00:58:41.694509 ==
4464 00:58:41.697515 Dram Type= 6, Freq= 0, CH_1, rank 1
4465 00:58:41.700958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4466 00:58:41.701041 ==
4467 00:58:41.704182 RX Vref Scan: 0
4468 00:58:41.704258
4469 00:58:41.704316 RX Vref 0 -> 0, step: 1
4470 00:58:41.707377
4471 00:58:41.707452 RX Delay -230 -> 252, step: 16
4472 00:58:41.714321 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4473 00:58:41.717497 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4474 00:58:41.720762 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4475 00:58:41.724192 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4476 00:58:41.730575 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4477 00:58:41.733985 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4478 00:58:41.737253 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4479 00:58:41.740630 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4480 00:58:41.743871 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4481 00:58:41.750554 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4482 00:58:41.753940 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4483 00:58:41.757134 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4484 00:58:41.760533 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4485 00:58:41.767586 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4486 00:58:41.770593 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4487 00:58:41.773791 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4488 00:58:41.773867 ==
4489 00:58:41.777103 Dram Type= 6, Freq= 0, CH_1, rank 1
4490 00:58:41.780432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4491 00:58:41.783741 ==
4492 00:58:41.783816 DQS Delay:
4493 00:58:41.783875 DQS0 = 0, DQS1 = 0
4494 00:58:41.787218 DQM Delay:
4495 00:58:41.787292 DQM0 = 39, DQM1 = 33
4496 00:58:41.790251 DQ Delay:
4497 00:58:41.790327 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4498 00:58:41.793568 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4499 00:58:41.796987 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4500 00:58:41.800307 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4501 00:58:41.800406
4502 00:58:41.803550
4503 00:58:41.803648 ==
4504 00:58:41.807118 Dram Type= 6, Freq= 0, CH_1, rank 1
4505 00:58:41.810165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4506 00:58:41.810286 ==
4507 00:58:41.810359
4508 00:58:41.810426
4509 00:58:41.813420 TX Vref Scan disable
4510 00:58:41.813494 == TX Byte 0 ==
4511 00:58:41.820341 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4512 00:58:41.823604 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4513 00:58:41.823704 == TX Byte 1 ==
4514 00:58:41.830342 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4515 00:58:41.833840 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4516 00:58:41.833939 ==
4517 00:58:41.836845 Dram Type= 6, Freq= 0, CH_1, rank 1
4518 00:58:41.840048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4519 00:58:41.840134 ==
4520 00:58:41.840220
4521 00:58:41.840300
4522 00:58:41.843777 TX Vref Scan disable
4523 00:58:41.846828 == TX Byte 0 ==
4524 00:58:41.850014 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4525 00:58:41.853497 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4526 00:58:41.856791 == TX Byte 1 ==
4527 00:58:41.860101 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4528 00:58:41.863267 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4529 00:58:41.863342
4530 00:58:41.866572 [DATLAT]
4531 00:58:41.866659 Freq=600, CH1 RK1
4532 00:58:41.866718
4533 00:58:41.869882 DATLAT Default: 0x8
4534 00:58:41.869957 0, 0xFFFF, sum = 0
4535 00:58:41.873333 1, 0xFFFF, sum = 0
4536 00:58:41.873408 2, 0xFFFF, sum = 0
4537 00:58:41.876791 3, 0xFFFF, sum = 0
4538 00:58:41.876868 4, 0xFFFF, sum = 0
4539 00:58:41.879728 5, 0xFFFF, sum = 0
4540 00:58:41.879806 6, 0xFFFF, sum = 0
4541 00:58:41.883038 7, 0x0, sum = 1
4542 00:58:41.883116 8, 0x0, sum = 2
4543 00:58:41.886252 9, 0x0, sum = 3
4544 00:58:41.886345 10, 0x0, sum = 4
4545 00:58:41.889908 best_step = 8
4546 00:58:41.889984
4547 00:58:41.890043 ==
4548 00:58:41.892789 Dram Type= 6, Freq= 0, CH_1, rank 1
4549 00:58:41.896200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4550 00:58:41.896278 ==
4551 00:58:41.899539 RX Vref Scan: 0
4552 00:58:41.899615
4553 00:58:41.899673 RX Vref 0 -> 0, step: 1
4554 00:58:41.899729
4555 00:58:41.903023 RX Delay -195 -> 252, step: 8
4556 00:58:41.909833 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4557 00:58:41.913130 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4558 00:58:41.916693 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4559 00:58:41.919845 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4560 00:58:41.926640 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4561 00:58:41.929819 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4562 00:58:41.933090 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4563 00:58:41.936346 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4564 00:58:41.943034 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4565 00:58:41.946177 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4566 00:58:41.949642 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4567 00:58:41.952763 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4568 00:58:41.956163 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4569 00:58:41.962993 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4570 00:58:41.966166 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4571 00:58:41.969481 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4572 00:58:41.969557 ==
4573 00:58:41.972973 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 00:58:41.979457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4575 00:58:41.979533 ==
4576 00:58:41.979591 DQS Delay:
4577 00:58:41.979647 DQS0 = 0, DQS1 = 0
4578 00:58:41.982897 DQM Delay:
4579 00:58:41.982973 DQM0 = 37, DQM1 = 29
4580 00:58:41.986010 DQ Delay:
4581 00:58:41.989311 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4582 00:58:41.992613 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4583 00:58:41.995918 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4584 00:58:41.999415 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4585 00:58:41.999490
4586 00:58:41.999548
4587 00:58:42.005883 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4588 00:58:42.009048 CH1 RK1: MR19=808, MR18=6565
4589 00:58:42.015884 CH1_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4590 00:58:42.019403 [RxdqsGatingPostProcess] freq 600
4591 00:58:42.022553 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4592 00:58:42.025669 Pre-setting of DQS Precalculation
4593 00:58:42.032351 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4594 00:58:42.038990 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4595 00:58:42.045755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4596 00:58:42.045831
4597 00:58:42.045891
4598 00:58:42.049026 [Calibration Summary] 1200 Mbps
4599 00:58:42.049102 CH 0, Rank 0
4600 00:58:42.052324 SW Impedance : PASS
4601 00:58:42.055749 DUTY Scan : NO K
4602 00:58:42.055825 ZQ Calibration : PASS
4603 00:58:42.058924 Jitter Meter : NO K
4604 00:58:42.062130 CBT Training : PASS
4605 00:58:42.062267 Write leveling : PASS
4606 00:58:42.065495 RX DQS gating : PASS
4607 00:58:42.068879 RX DQ/DQS(RDDQC) : PASS
4608 00:58:42.068955 TX DQ/DQS : PASS
4609 00:58:42.072265 RX DATLAT : PASS
4610 00:58:42.075726 RX DQ/DQS(Engine): PASS
4611 00:58:42.075802 TX OE : NO K
4612 00:58:42.075861 All Pass.
4613 00:58:42.075916
4614 00:58:42.078838 CH 0, Rank 1
4615 00:58:42.082514 SW Impedance : PASS
4616 00:58:42.082590 DUTY Scan : NO K
4617 00:58:42.085581 ZQ Calibration : PASS
4618 00:58:42.085658 Jitter Meter : NO K
4619 00:58:42.088735 CBT Training : PASS
4620 00:58:42.092239 Write leveling : PASS
4621 00:58:42.092316 RX DQS gating : PASS
4622 00:58:42.095503 RX DQ/DQS(RDDQC) : PASS
4623 00:58:42.098577 TX DQ/DQS : PASS
4624 00:58:42.098654 RX DATLAT : PASS
4625 00:58:42.101884 RX DQ/DQS(Engine): PASS
4626 00:58:42.105480 TX OE : NO K
4627 00:58:42.105557 All Pass.
4628 00:58:42.105615
4629 00:58:42.105670 CH 1, Rank 0
4630 00:58:42.108500 SW Impedance : PASS
4631 00:58:42.111842 DUTY Scan : NO K
4632 00:58:42.111918 ZQ Calibration : PASS
4633 00:58:42.115491 Jitter Meter : NO K
4634 00:58:42.118623 CBT Training : PASS
4635 00:58:42.118721 Write leveling : PASS
4636 00:58:42.121772 RX DQS gating : PASS
4637 00:58:42.125230 RX DQ/DQS(RDDQC) : PASS
4638 00:58:42.125306 TX DQ/DQS : PASS
4639 00:58:42.128481 RX DATLAT : PASS
4640 00:58:42.131867 RX DQ/DQS(Engine): PASS
4641 00:58:42.131943 TX OE : NO K
4642 00:58:42.132004 All Pass.
4643 00:58:42.135176
4644 00:58:42.135252 CH 1, Rank 1
4645 00:58:42.138342 SW Impedance : PASS
4646 00:58:42.138418 DUTY Scan : NO K
4647 00:58:42.141794 ZQ Calibration : PASS
4648 00:58:42.141870 Jitter Meter : NO K
4649 00:58:42.145381 CBT Training : PASS
4650 00:58:42.148619 Write leveling : PASS
4651 00:58:42.148696 RX DQS gating : PASS
4652 00:58:42.151700 RX DQ/DQS(RDDQC) : PASS
4653 00:58:42.155022 TX DQ/DQS : PASS
4654 00:58:42.155102 RX DATLAT : PASS
4655 00:58:42.158460 RX DQ/DQS(Engine): PASS
4656 00:58:42.161883 TX OE : NO K
4657 00:58:42.161960 All Pass.
4658 00:58:42.162020
4659 00:58:42.162074 DramC Write-DBI off
4660 00:58:42.165369 PER_BANK_REFRESH: Hybrid Mode
4661 00:58:42.168449 TX_TRACKING: ON
4662 00:58:42.174991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4663 00:58:42.178358 [FAST_K] Save calibration result to emmc
4664 00:58:42.185102 dramc_set_vcore_voltage set vcore to 662500
4665 00:58:42.185179 Read voltage for 933, 3
4666 00:58:42.188174 Vio18 = 0
4667 00:58:42.188250 Vcore = 662500
4668 00:58:42.188309 Vdram = 0
4669 00:58:42.191483 Vddq = 0
4670 00:58:42.191559 Vmddr = 0
4671 00:58:42.194899 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4672 00:58:42.201626 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4673 00:58:42.204694 MEM_TYPE=3, freq_sel=17
4674 00:58:42.208176 sv_algorithm_assistance_LP4_1600
4675 00:58:42.211485 ============ PULL DRAM RESETB DOWN ============
4676 00:58:42.214771 ========== PULL DRAM RESETB DOWN end =========
4677 00:58:42.218100 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4678 00:58:42.221418 ===================================
4679 00:58:42.224771 LPDDR4 DRAM CONFIGURATION
4680 00:58:42.228220 ===================================
4681 00:58:42.231445 EX_ROW_EN[0] = 0x0
4682 00:58:42.231521 EX_ROW_EN[1] = 0x0
4683 00:58:42.234691 LP4Y_EN = 0x0
4684 00:58:42.234768 WORK_FSP = 0x0
4685 00:58:42.238031 WL = 0x3
4686 00:58:42.238107 RL = 0x3
4687 00:58:42.241518 BL = 0x2
4688 00:58:42.241594 RPST = 0x0
4689 00:58:42.244831 RD_PRE = 0x0
4690 00:58:42.244920 WR_PRE = 0x1
4691 00:58:42.248081 WR_PST = 0x0
4692 00:58:42.251397 DBI_WR = 0x0
4693 00:58:42.251474 DBI_RD = 0x0
4694 00:58:42.254811 OTF = 0x1
4695 00:58:42.258024 ===================================
4696 00:58:42.261311 ===================================
4697 00:58:42.261387 ANA top config
4698 00:58:42.264609 ===================================
4699 00:58:42.267878 DLL_ASYNC_EN = 0
4700 00:58:42.271133 ALL_SLAVE_EN = 1
4701 00:58:42.271209 NEW_RANK_MODE = 1
4702 00:58:42.274422 DLL_IDLE_MODE = 1
4703 00:58:42.277988 LP45_APHY_COMB_EN = 1
4704 00:58:42.281396 TX_ODT_DIS = 1
4705 00:58:42.281473 NEW_8X_MODE = 1
4706 00:58:42.284592 ===================================
4707 00:58:42.287745 ===================================
4708 00:58:42.291170 data_rate = 1866
4709 00:58:42.294565 CKR = 1
4710 00:58:42.297876 DQ_P2S_RATIO = 8
4711 00:58:42.301082 ===================================
4712 00:58:42.304389 CA_P2S_RATIO = 8
4713 00:58:42.307804 DQ_CA_OPEN = 0
4714 00:58:42.307879 DQ_SEMI_OPEN = 0
4715 00:58:42.311133 CA_SEMI_OPEN = 0
4716 00:58:42.314528 CA_FULL_RATE = 0
4717 00:58:42.317994 DQ_CKDIV4_EN = 1
4718 00:58:42.321207 CA_CKDIV4_EN = 1
4719 00:58:42.324430 CA_PREDIV_EN = 0
4720 00:58:42.324507 PH8_DLY = 0
4721 00:58:42.327719 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4722 00:58:42.331029 DQ_AAMCK_DIV = 4
4723 00:58:42.334411 CA_AAMCK_DIV = 4
4724 00:58:42.337656 CA_ADMCK_DIV = 4
4725 00:58:42.340966 DQ_TRACK_CA_EN = 0
4726 00:58:42.341061 CA_PICK = 933
4727 00:58:42.344259 CA_MCKIO = 933
4728 00:58:42.347753 MCKIO_SEMI = 0
4729 00:58:42.350801 PLL_FREQ = 3732
4730 00:58:42.354114 DQ_UI_PI_RATIO = 32
4731 00:58:42.357457 CA_UI_PI_RATIO = 0
4732 00:58:42.360804 ===================================
4733 00:58:42.364180 ===================================
4734 00:58:42.364257 memory_type:LPDDR4
4735 00:58:42.367520 GP_NUM : 10
4736 00:58:42.370856 SRAM_EN : 1
4737 00:58:42.370932 MD32_EN : 0
4738 00:58:42.374249 ===================================
4739 00:58:42.377792 [ANA_INIT] >>>>>>>>>>>>>>
4740 00:58:42.380833 <<<<<< [CONFIGURE PHASE]: ANA_TX
4741 00:58:42.384103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4742 00:58:42.387492 ===================================
4743 00:58:42.391052 data_rate = 1866,PCW = 0X8f00
4744 00:58:42.394086 ===================================
4745 00:58:42.397496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4746 00:58:42.400949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4747 00:58:42.407441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4748 00:58:42.410709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4749 00:58:42.414198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4750 00:58:42.417598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4751 00:58:42.420821 [ANA_INIT] flow start
4752 00:58:42.424196 [ANA_INIT] PLL >>>>>>>>
4753 00:58:42.424273 [ANA_INIT] PLL <<<<<<<<
4754 00:58:42.427542 [ANA_INIT] MIDPI >>>>>>>>
4755 00:58:42.430672 [ANA_INIT] MIDPI <<<<<<<<
4756 00:58:42.434114 [ANA_INIT] DLL >>>>>>>>
4757 00:58:42.434190 [ANA_INIT] flow end
4758 00:58:42.437376 ============ LP4 DIFF to SE enter ============
4759 00:58:42.444095 ============ LP4 DIFF to SE exit ============
4760 00:58:42.444172 [ANA_INIT] <<<<<<<<<<<<<
4761 00:58:42.447603 [Flow] Enable top DCM control >>>>>
4762 00:58:42.450705 [Flow] Enable top DCM control <<<<<
4763 00:58:42.454188 Enable DLL master slave shuffle
4764 00:58:42.460610 ==============================================================
4765 00:58:42.460687 Gating Mode config
4766 00:58:42.467147 ==============================================================
4767 00:58:42.470461 Config description:
4768 00:58:42.480403 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4769 00:58:42.487502 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4770 00:58:42.490225 SELPH_MODE 0: By rank 1: By Phase
4771 00:58:42.496885 ==============================================================
4772 00:58:42.500222 GAT_TRACK_EN = 1
4773 00:58:42.503361 RX_GATING_MODE = 2
4774 00:58:42.506760 RX_GATING_TRACK_MODE = 2
4775 00:58:42.506836 SELPH_MODE = 1
4776 00:58:42.510049 PICG_EARLY_EN = 1
4777 00:58:42.513130 VALID_LAT_VALUE = 1
4778 00:58:42.520204 ==============================================================
4779 00:58:42.523184 Enter into Gating configuration >>>>
4780 00:58:42.526456 Exit from Gating configuration <<<<
4781 00:58:42.529844 Enter into DVFS_PRE_config >>>>>
4782 00:58:42.540133 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4783 00:58:42.543475 Exit from DVFS_PRE_config <<<<<
4784 00:58:42.546560 Enter into PICG configuration >>>>
4785 00:58:42.549753 Exit from PICG configuration <<<<
4786 00:58:42.552928 [RX_INPUT] configuration >>>>>
4787 00:58:42.556020 [RX_INPUT] configuration <<<<<
4788 00:58:42.559827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4789 00:58:42.566046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4790 00:58:42.572836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4791 00:58:42.579500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4792 00:58:42.585998 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4793 00:58:42.589113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4794 00:58:42.595907 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4795 00:58:42.599199 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4796 00:58:42.602401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4797 00:58:42.606059 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4798 00:58:42.612513 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4799 00:58:42.616046 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4800 00:58:42.618990 ===================================
4801 00:58:42.622533 LPDDR4 DRAM CONFIGURATION
4802 00:58:42.625739 ===================================
4803 00:58:42.625815 EX_ROW_EN[0] = 0x0
4804 00:58:42.629293 EX_ROW_EN[1] = 0x0
4805 00:58:42.629369 LP4Y_EN = 0x0
4806 00:58:42.632280 WORK_FSP = 0x0
4807 00:58:42.632356 WL = 0x3
4808 00:58:42.635573 RL = 0x3
4809 00:58:42.635648 BL = 0x2
4810 00:58:42.638958 RPST = 0x0
4811 00:58:42.639033 RD_PRE = 0x0
4812 00:58:42.642154 WR_PRE = 0x1
4813 00:58:42.645648 WR_PST = 0x0
4814 00:58:42.645723 DBI_WR = 0x0
4815 00:58:42.649041 DBI_RD = 0x0
4816 00:58:42.649115 OTF = 0x1
4817 00:58:42.652049 ===================================
4818 00:58:42.655504 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4819 00:58:42.658952 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4820 00:58:42.665639 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4821 00:58:42.668709 ===================================
4822 00:58:42.672247 LPDDR4 DRAM CONFIGURATION
4823 00:58:42.675635 ===================================
4824 00:58:42.675711 EX_ROW_EN[0] = 0x10
4825 00:58:42.678880 EX_ROW_EN[1] = 0x0
4826 00:58:42.678954 LP4Y_EN = 0x0
4827 00:58:42.682237 WORK_FSP = 0x0
4828 00:58:42.682333 WL = 0x3
4829 00:58:42.685292 RL = 0x3
4830 00:58:42.685367 BL = 0x2
4831 00:58:42.688623 RPST = 0x0
4832 00:58:42.688698 RD_PRE = 0x0
4833 00:58:42.692098 WR_PRE = 0x1
4834 00:58:42.692172 WR_PST = 0x0
4835 00:58:42.695463 DBI_WR = 0x0
4836 00:58:42.695538 DBI_RD = 0x0
4837 00:58:42.698649 OTF = 0x1
4838 00:58:42.701925 ===================================
4839 00:58:42.708488 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4840 00:58:42.712020 nWR fixed to 30
4841 00:58:42.715203 [ModeRegInit_LP4] CH0 RK0
4842 00:58:42.715278 [ModeRegInit_LP4] CH0 RK1
4843 00:58:42.718670 [ModeRegInit_LP4] CH1 RK0
4844 00:58:42.721906 [ModeRegInit_LP4] CH1 RK1
4845 00:58:42.721981 match AC timing 8
4846 00:58:42.728455 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4847 00:58:42.731772 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4848 00:58:42.735137 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4849 00:58:42.741833 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4850 00:58:42.745151 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4851 00:58:42.745248 ==
4852 00:58:42.748462 Dram Type= 6, Freq= 0, CH_0, rank 0
4853 00:58:42.751681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4854 00:58:42.751757 ==
4855 00:58:42.758481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4856 00:58:42.765004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4857 00:58:42.768206 [CA 0] Center 38 (8~69) winsize 62
4858 00:58:42.771632 [CA 1] Center 38 (7~69) winsize 63
4859 00:58:42.775112 [CA 2] Center 36 (6~67) winsize 62
4860 00:58:42.778480 [CA 3] Center 36 (5~67) winsize 63
4861 00:58:42.781529 [CA 4] Center 35 (4~66) winsize 63
4862 00:58:42.785075 [CA 5] Center 34 (4~65) winsize 62
4863 00:58:42.785150
4864 00:58:42.788322 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4865 00:58:42.788396
4866 00:58:42.791471 [CATrainingPosCal] consider 1 rank data
4867 00:58:42.794859 u2DelayCellTimex100 = 270/100 ps
4868 00:58:42.798088 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4869 00:58:42.801389 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4870 00:58:42.804667 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4871 00:58:42.808232 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4872 00:58:42.811313 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
4873 00:58:42.818114 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4874 00:58:42.818247
4875 00:58:42.821481 CA PerBit enable=1, Macro0, CA PI delay=34
4876 00:58:42.821556
4877 00:58:42.824697 [CBTSetCACLKResult] CA Dly = 34
4878 00:58:42.824772 CS Dly: 7 (0~38)
4879 00:58:42.824831 ==
4880 00:58:42.828169 Dram Type= 6, Freq= 0, CH_0, rank 1
4881 00:58:42.831327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4882 00:58:42.834924 ==
4883 00:58:42.837960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4884 00:58:42.844709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4885 00:58:42.847873 [CA 0] Center 38 (8~69) winsize 62
4886 00:58:42.851164 [CA 1] Center 38 (8~69) winsize 62
4887 00:58:42.855022 [CA 2] Center 36 (6~67) winsize 62
4888 00:58:42.857853 [CA 3] Center 35 (5~66) winsize 62
4889 00:58:42.861159 [CA 4] Center 34 (4~65) winsize 62
4890 00:58:42.864412 [CA 5] Center 34 (4~65) winsize 62
4891 00:58:42.864538
4892 00:58:42.868015 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4893 00:58:42.868197
4894 00:58:42.871032 [CATrainingPosCal] consider 2 rank data
4895 00:58:42.874546 u2DelayCellTimex100 = 270/100 ps
4896 00:58:42.877897 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4897 00:58:42.881194 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4898 00:58:42.884222 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4899 00:58:42.887794 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4900 00:58:42.894311 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4901 00:58:42.897738 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4902 00:58:42.897814
4903 00:58:42.900839 CA PerBit enable=1, Macro0, CA PI delay=34
4904 00:58:42.900932
4905 00:58:42.904089 [CBTSetCACLKResult] CA Dly = 34
4906 00:58:42.904226 CS Dly: 7 (0~39)
4907 00:58:42.904315
4908 00:58:42.907444 ----->DramcWriteLeveling(PI) begin...
4909 00:58:42.907521 ==
4910 00:58:42.910595 Dram Type= 6, Freq= 0, CH_0, rank 0
4911 00:58:42.917292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4912 00:58:42.917373 ==
4913 00:58:42.920574 Write leveling (Byte 0): 31 => 31
4914 00:58:42.923922 Write leveling (Byte 1): 30 => 30
4915 00:58:42.923999 DramcWriteLeveling(PI) end<-----
4916 00:58:42.927284
4917 00:58:42.927360 ==
4918 00:58:42.930610 Dram Type= 6, Freq= 0, CH_0, rank 0
4919 00:58:42.933951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4920 00:58:42.934068 ==
4921 00:58:42.937244 [Gating] SW mode calibration
4922 00:58:42.943748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4923 00:58:42.947547 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4924 00:58:42.953713 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4925 00:58:42.957176 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4926 00:58:42.960273 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4927 00:58:42.966882 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4928 00:58:42.970239 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4929 00:58:42.973556 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4930 00:58:42.980618 0 10 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4931 00:58:42.983989 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4932 00:58:42.987030 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4933 00:58:42.993404 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4934 00:58:42.996840 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4935 00:58:43.000037 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4936 00:58:43.006836 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4937 00:58:43.010155 0 11 20 | B1->B0 | 2d2d 3737 | 0 0 | (1 1) (0 0)
4938 00:58:43.013458 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4939 00:58:43.019960 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4940 00:58:43.023362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4941 00:58:43.026630 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4942 00:58:43.033289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4943 00:58:43.036654 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4944 00:58:43.040116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4945 00:58:43.046538 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4946 00:58:43.049871 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 00:58:43.053399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 00:58:43.059854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 00:58:43.063026 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 00:58:43.066163 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 00:58:43.072806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 00:58:43.076070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 00:58:43.079475 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 00:58:43.086327 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 00:58:43.089476 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 00:58:43.092834 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 00:58:43.099724 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4958 00:58:43.102612 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4959 00:58:43.105939 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4960 00:58:43.112656 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4961 00:58:43.115866 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4962 00:58:43.119323 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4963 00:58:43.122596 Total UI for P1: 0, mck2ui 16
4964 00:58:43.125910 best dqsien dly found for B0: ( 0, 14, 20)
4965 00:58:43.129102 Total UI for P1: 0, mck2ui 16
4966 00:58:43.132602 best dqsien dly found for B1: ( 0, 14, 18)
4967 00:58:43.135843 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4968 00:58:43.139196 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
4969 00:58:43.139271
4970 00:58:43.142414 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4971 00:58:43.149054 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
4972 00:58:43.149129 [Gating] SW calibration Done
4973 00:58:43.152372 ==
4974 00:58:43.152447 Dram Type= 6, Freq= 0, CH_0, rank 0
4975 00:58:43.159158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4976 00:58:43.159234 ==
4977 00:58:43.159292 RX Vref Scan: 0
4978 00:58:43.159347
4979 00:58:43.162387 RX Vref 0 -> 0, step: 1
4980 00:58:43.162462
4981 00:58:43.165588 RX Delay -80 -> 252, step: 8
4982 00:58:43.168878 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4983 00:58:43.172734 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4984 00:58:43.175555 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4985 00:58:43.182136 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
4986 00:58:43.185457 iDelay=208, Bit 4, Center 95 (-8 ~ 199) 208
4987 00:58:43.188789 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4988 00:58:43.192140 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4989 00:58:43.195506 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4990 00:58:43.198654 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4991 00:58:43.205343 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4992 00:58:43.208650 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4993 00:58:43.212211 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4994 00:58:43.215134 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
4995 00:58:43.218612 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4996 00:58:43.225370 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
4997 00:58:43.228414 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4998 00:58:43.228488 ==
4999 00:58:43.231656 Dram Type= 6, Freq= 0, CH_0, rank 0
5000 00:58:43.235244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5001 00:58:43.235344 ==
5002 00:58:43.238390 DQS Delay:
5003 00:58:43.238465 DQS0 = 0, DQS1 = 0
5004 00:58:43.238523 DQM Delay:
5005 00:58:43.242023 DQM0 = 95, DQM1 = 86
5006 00:58:43.242098 DQ Delay:
5007 00:58:43.245084 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5008 00:58:43.248397 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5009 00:58:43.251685 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5010 00:58:43.254953 DQ12 =87, DQ13 =95, DQ14 =99, DQ15 =91
5011 00:58:43.255028
5012 00:58:43.255085
5013 00:58:43.255139 ==
5014 00:58:43.258247 Dram Type= 6, Freq= 0, CH_0, rank 0
5015 00:58:43.264874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5016 00:58:43.264950 ==
5017 00:58:43.265011
5018 00:58:43.265065
5019 00:58:43.265115 TX Vref Scan disable
5020 00:58:43.268599 == TX Byte 0 ==
5021 00:58:43.272026 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5022 00:58:43.278635 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5023 00:58:43.278710 == TX Byte 1 ==
5024 00:58:43.281980 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5025 00:58:43.288656 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5026 00:58:43.288731 ==
5027 00:58:43.291899 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 00:58:43.295306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5029 00:58:43.295382 ==
5030 00:58:43.295439
5031 00:58:43.295493
5032 00:58:43.298468 TX Vref Scan disable
5033 00:58:43.298543 == TX Byte 0 ==
5034 00:58:43.305186 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5035 00:58:43.308425 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5036 00:58:43.308499 == TX Byte 1 ==
5037 00:58:43.315067 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5038 00:58:43.318410 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5039 00:58:43.318485
5040 00:58:43.318543 [DATLAT]
5041 00:58:43.321715 Freq=933, CH0 RK0
5042 00:58:43.321789
5043 00:58:43.321847 DATLAT Default: 0xd
5044 00:58:43.324817 0, 0xFFFF, sum = 0
5045 00:58:43.324894 1, 0xFFFF, sum = 0
5046 00:58:43.328163 2, 0xFFFF, sum = 0
5047 00:58:43.328239 3, 0xFFFF, sum = 0
5048 00:58:43.331460 4, 0xFFFF, sum = 0
5049 00:58:43.334953 5, 0xFFFF, sum = 0
5050 00:58:43.335028 6, 0xFFFF, sum = 0
5051 00:58:43.338152 7, 0xFFFF, sum = 0
5052 00:58:43.338283 8, 0xFFFF, sum = 0
5053 00:58:43.341577 9, 0xFFFF, sum = 0
5054 00:58:43.341654 10, 0x0, sum = 1
5055 00:58:43.344688 11, 0x0, sum = 2
5056 00:58:43.344764 12, 0x0, sum = 3
5057 00:58:43.344825 13, 0x0, sum = 4
5058 00:58:43.348128 best_step = 11
5059 00:58:43.348203
5060 00:58:43.348260 ==
5061 00:58:43.351352 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 00:58:43.354613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5063 00:58:43.354688 ==
5064 00:58:43.358101 RX Vref Scan: 1
5065 00:58:43.358199
5066 00:58:43.361362 RX Vref 0 -> 0, step: 1
5067 00:58:43.361437
5068 00:58:43.361495 RX Delay -61 -> 252, step: 4
5069 00:58:43.361550
5070 00:58:43.364759 Set Vref, RX VrefLevel [Byte0]: 50
5071 00:58:43.367864 [Byte1]: 51
5072 00:58:43.372498
5073 00:58:43.372579 Final RX Vref Byte 0 = 50 to rank0
5074 00:58:43.375873 Final RX Vref Byte 1 = 51 to rank0
5075 00:58:43.379056 Final RX Vref Byte 0 = 50 to rank1
5076 00:58:43.382219 Final RX Vref Byte 1 = 51 to rank1==
5077 00:58:43.385541 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 00:58:43.392161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5079 00:58:43.392237 ==
5080 00:58:43.392296 DQS Delay:
5081 00:58:43.395763 DQS0 = 0, DQS1 = 0
5082 00:58:43.395837 DQM Delay:
5083 00:58:43.395895 DQM0 = 96, DQM1 = 87
5084 00:58:43.399001 DQ Delay:
5085 00:58:43.402122 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5086 00:58:43.405340 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5087 00:58:43.408837 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =80
5088 00:58:43.412071 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =96
5089 00:58:43.412155
5090 00:58:43.412227
5091 00:58:43.418377 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5092 00:58:43.421826 CH0 RK0: MR19=505, MR18=2727
5093 00:58:43.428581 CH0_RK0: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5094 00:58:43.428657
5095 00:58:43.431892 ----->DramcWriteLeveling(PI) begin...
5096 00:58:43.431969 ==
5097 00:58:43.435513 Dram Type= 6, Freq= 0, CH_0, rank 1
5098 00:58:43.438490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5099 00:58:43.438565 ==
5100 00:58:43.441755 Write leveling (Byte 0): 27 => 27
5101 00:58:43.445289 Write leveling (Byte 1): 26 => 26
5102 00:58:43.448374 DramcWriteLeveling(PI) end<-----
5103 00:58:43.448449
5104 00:58:43.448506 ==
5105 00:58:43.451655 Dram Type= 6, Freq= 0, CH_0, rank 1
5106 00:58:43.455238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5107 00:58:43.458502 ==
5108 00:58:43.458601 [Gating] SW mode calibration
5109 00:58:43.468227 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5110 00:58:43.471824 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5111 00:58:43.474968 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 00:58:43.481759 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 00:58:43.485001 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 00:58:43.488155 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 00:58:43.494813 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 00:58:43.498162 0 10 20 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (0 0)
5117 00:58:43.501423 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5118 00:58:43.508260 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 00:58:43.511430 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 00:58:43.514710 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 00:58:43.521357 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 00:58:43.524791 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 00:58:43.528163 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 00:58:43.534598 0 11 20 | B1->B0 | 3434 3a3a | 0 1 | (1 1) (0 0)
5125 00:58:43.537764 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5126 00:58:43.541277 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 00:58:43.547839 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 00:58:43.550870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 00:58:43.554217 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 00:58:43.561060 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 00:58:43.564345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 00:58:43.567789 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 00:58:43.574365 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5134 00:58:43.577466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:58:43.580858 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:58:43.587574 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:58:43.590880 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:58:43.594082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:58:43.601146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:58:43.604185 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:58:43.607309 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:58:43.614332 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:58:43.617494 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:58:43.620525 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:58:43.624343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:58:43.630590 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:58:43.633897 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:58:43.637266 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5149 00:58:43.643914 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5150 00:58:43.647415 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 00:58:43.650551 Total UI for P1: 0, mck2ui 16
5152 00:58:43.654048 best dqsien dly found for B0: ( 0, 14, 22)
5153 00:58:43.657355 Total UI for P1: 0, mck2ui 16
5154 00:58:43.660550 best dqsien dly found for B1: ( 0, 14, 22)
5155 00:58:43.663767 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5156 00:58:43.667061 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5157 00:58:43.667137
5158 00:58:43.670559 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5159 00:58:43.677196 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5160 00:58:43.677272 [Gating] SW calibration Done
5161 00:58:43.677330 ==
5162 00:58:43.680385 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 00:58:43.687044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5164 00:58:43.687120 ==
5165 00:58:43.687179 RX Vref Scan: 0
5166 00:58:43.687234
5167 00:58:43.690431 RX Vref 0 -> 0, step: 1
5168 00:58:43.690506
5169 00:58:43.693611 RX Delay -80 -> 252, step: 8
5170 00:58:43.696781 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5171 00:58:43.700456 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5172 00:58:43.703873 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5173 00:58:43.706825 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5174 00:58:43.713386 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5175 00:58:43.716992 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5176 00:58:43.720252 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5177 00:58:43.723519 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5178 00:58:43.727034 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5179 00:58:43.729966 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5180 00:58:43.736787 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5181 00:58:43.740141 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5182 00:58:43.743298 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5183 00:58:43.746572 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5184 00:58:43.749885 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5185 00:58:43.756545 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5186 00:58:43.756620 ==
5187 00:58:43.759745 Dram Type= 6, Freq= 0, CH_0, rank 1
5188 00:58:43.763068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5189 00:58:43.763144 ==
5190 00:58:43.763202 DQS Delay:
5191 00:58:43.766331 DQS0 = 0, DQS1 = 0
5192 00:58:43.766405 DQM Delay:
5193 00:58:43.769933 DQM0 = 97, DQM1 = 85
5194 00:58:43.770014 DQ Delay:
5195 00:58:43.772990 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5196 00:58:43.776316 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5197 00:58:43.779745 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5198 00:58:43.782947 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5199 00:58:43.783021
5200 00:58:43.783079
5201 00:58:43.783133 ==
5202 00:58:43.786327 Dram Type= 6, Freq= 0, CH_0, rank 1
5203 00:58:43.789495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5204 00:58:43.792970 ==
5205 00:58:43.793044
5206 00:58:43.793101
5207 00:58:43.793155 TX Vref Scan disable
5208 00:58:43.796226 == TX Byte 0 ==
5209 00:58:43.799574 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5210 00:58:43.802917 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5211 00:58:43.806092 == TX Byte 1 ==
5212 00:58:43.809701 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5213 00:58:43.812678 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5214 00:58:43.815937 ==
5215 00:58:43.819276 Dram Type= 6, Freq= 0, CH_0, rank 1
5216 00:58:43.822615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5217 00:58:43.822694 ==
5218 00:58:43.822770
5219 00:58:43.822842
5220 00:58:43.825960 TX Vref Scan disable
5221 00:58:43.826038 == TX Byte 0 ==
5222 00:58:43.832590 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5223 00:58:43.835799 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5224 00:58:43.835877 == TX Byte 1 ==
5225 00:58:43.842250 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5226 00:58:43.845812 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5227 00:58:43.845887
5228 00:58:43.845944 [DATLAT]
5229 00:58:43.848998 Freq=933, CH0 RK1
5230 00:58:43.849074
5231 00:58:43.849132 DATLAT Default: 0xb
5232 00:58:43.852103 0, 0xFFFF, sum = 0
5233 00:58:43.852179 1, 0xFFFF, sum = 0
5234 00:58:43.855582 2, 0xFFFF, sum = 0
5235 00:58:43.855658 3, 0xFFFF, sum = 0
5236 00:58:43.858833 4, 0xFFFF, sum = 0
5237 00:58:43.862234 5, 0xFFFF, sum = 0
5238 00:58:43.862324 6, 0xFFFF, sum = 0
5239 00:58:43.865392 7, 0xFFFF, sum = 0
5240 00:58:43.865468 8, 0xFFFF, sum = 0
5241 00:58:43.868932 9, 0xFFFF, sum = 0
5242 00:58:43.869008 10, 0x0, sum = 1
5243 00:58:43.872431 11, 0x0, sum = 2
5244 00:58:43.872507 12, 0x0, sum = 3
5245 00:58:43.872566 13, 0x0, sum = 4
5246 00:58:43.875374 best_step = 11
5247 00:58:43.875448
5248 00:58:43.875506 ==
5249 00:58:43.878616 Dram Type= 6, Freq= 0, CH_0, rank 1
5250 00:58:43.882012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5251 00:58:43.882088 ==
5252 00:58:43.885384 RX Vref Scan: 0
5253 00:58:43.885458
5254 00:58:43.888554 RX Vref 0 -> 0, step: 1
5255 00:58:43.888628
5256 00:58:43.888686 RX Delay -69 -> 252, step: 4
5257 00:58:43.896325 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5258 00:58:43.899552 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5259 00:58:43.902991 iDelay=203, Bit 2, Center 94 (-1 ~ 190) 192
5260 00:58:43.906159 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5261 00:58:43.909493 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5262 00:58:43.916430 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5263 00:58:43.919501 iDelay=203, Bit 6, Center 102 (11 ~ 194) 184
5264 00:58:43.922791 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5265 00:58:43.926479 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5266 00:58:43.929506 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5267 00:58:43.932854 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5268 00:58:43.939424 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5269 00:58:43.942991 iDelay=203, Bit 12, Center 90 (-1 ~ 182) 184
5270 00:58:43.946244 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5271 00:58:43.949522 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5272 00:58:43.952866 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5273 00:58:43.956379 ==
5274 00:58:43.956456 Dram Type= 6, Freq= 0, CH_0, rank 1
5275 00:58:43.962705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5276 00:58:43.962783 ==
5277 00:58:43.962860 DQS Delay:
5278 00:58:43.966033 DQS0 = 0, DQS1 = 0
5279 00:58:43.966110 DQM Delay:
5280 00:58:43.969503 DQM0 = 96, DQM1 = 86
5281 00:58:43.969580 DQ Delay:
5282 00:58:43.972692 DQ0 =92, DQ1 =96, DQ2 =94, DQ3 =90
5283 00:58:43.976071 DQ4 =102, DQ5 =90, DQ6 =102, DQ7 =108
5284 00:58:43.979398 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5285 00:58:43.982764 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =94
5286 00:58:43.982842
5287 00:58:43.982918
5288 00:58:43.989444 [DQSOSCAuto] RK1, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5289 00:58:43.992682 CH0 RK1: MR19=505, MR18=3333
5290 00:58:43.999226 CH0_RK1: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5291 00:58:44.002555 [RxdqsGatingPostProcess] freq 933
5292 00:58:44.009380 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5293 00:58:44.009457 Pre-setting of DQS Precalculation
5294 00:58:44.016004 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5295 00:58:44.016082 ==
5296 00:58:44.019280 Dram Type= 6, Freq= 0, CH_1, rank 0
5297 00:58:44.022519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5298 00:58:44.022595 ==
5299 00:58:44.029094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5300 00:58:44.035765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5301 00:58:44.039268 [CA 0] Center 37 (7~68) winsize 62
5302 00:58:44.042188 [CA 1] Center 37 (6~68) winsize 63
5303 00:58:44.045466 [CA 2] Center 34 (4~65) winsize 62
5304 00:58:44.049009 [CA 3] Center 34 (4~65) winsize 62
5305 00:58:44.052234 [CA 4] Center 33 (2~64) winsize 63
5306 00:58:44.055819 [CA 5] Center 33 (2~64) winsize 63
5307 00:58:44.055904
5308 00:58:44.058817 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5309 00:58:44.058892
5310 00:58:44.062172 [CATrainingPosCal] consider 1 rank data
5311 00:58:44.065654 u2DelayCellTimex100 = 270/100 ps
5312 00:58:44.068779 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5313 00:58:44.072101 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5314 00:58:44.075494 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5315 00:58:44.078880 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5316 00:58:44.081991 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5317 00:58:44.085237 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5318 00:58:44.088554
5319 00:58:44.092411 CA PerBit enable=1, Macro0, CA PI delay=33
5320 00:58:44.092486
5321 00:58:44.095472 [CBTSetCACLKResult] CA Dly = 33
5322 00:58:44.095547 CS Dly: 5 (0~36)
5323 00:58:44.095604 ==
5324 00:58:44.098823 Dram Type= 6, Freq= 0, CH_1, rank 1
5325 00:58:44.101885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5326 00:58:44.101959 ==
5327 00:58:44.108463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5328 00:58:44.115093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5329 00:58:44.118290 [CA 0] Center 37 (7~68) winsize 62
5330 00:58:44.121678 [CA 1] Center 37 (6~68) winsize 63
5331 00:58:44.125015 [CA 2] Center 34 (4~65) winsize 62
5332 00:58:44.128555 [CA 3] Center 34 (4~65) winsize 62
5333 00:58:44.131691 [CA 4] Center 33 (2~64) winsize 63
5334 00:58:44.135133 [CA 5] Center 33 (2~64) winsize 63
5335 00:58:44.135207
5336 00:58:44.138346 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5337 00:58:44.138420
5338 00:58:44.141875 [CATrainingPosCal] consider 2 rank data
5339 00:58:44.144932 u2DelayCellTimex100 = 270/100 ps
5340 00:58:44.148280 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5341 00:58:44.151513 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5342 00:58:44.155139 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5343 00:58:44.158343 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5344 00:58:44.161464 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5345 00:58:44.168472 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5346 00:58:44.168547
5347 00:58:44.171448 CA PerBit enable=1, Macro0, CA PI delay=33
5348 00:58:44.171524
5349 00:58:44.174585 [CBTSetCACLKResult] CA Dly = 33
5350 00:58:44.174660 CS Dly: 5 (0~37)
5351 00:58:44.174717
5352 00:58:44.178215 ----->DramcWriteLeveling(PI) begin...
5353 00:58:44.178294 ==
5354 00:58:44.181447 Dram Type= 6, Freq= 0, CH_1, rank 0
5355 00:58:44.188015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5356 00:58:44.188090 ==
5357 00:58:44.191279 Write leveling (Byte 0): 25 => 25
5358 00:58:44.191353 Write leveling (Byte 1): 25 => 25
5359 00:58:44.194582 DramcWriteLeveling(PI) end<-----
5360 00:58:44.194656
5361 00:58:44.198016 ==
5362 00:58:44.198089 Dram Type= 6, Freq= 0, CH_1, rank 0
5363 00:58:44.204444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5364 00:58:44.204519 ==
5365 00:58:44.208008 [Gating] SW mode calibration
5366 00:58:44.214391 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 00:58:44.217879 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5368 00:58:44.224458 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 00:58:44.227614 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 00:58:44.230814 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 00:58:44.237438 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5372 00:58:44.240572 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5373 00:58:44.244264 0 10 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
5374 00:58:44.250630 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5375 00:58:44.253913 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 00:58:44.257069 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 00:58:44.263932 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 00:58:44.267120 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 00:58:44.270584 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 00:58:44.277039 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5381 00:58:44.280308 0 11 20 | B1->B0 | 2a2a 4242 | 1 0 | (0 0) (0 0)
5382 00:58:44.283646 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
5383 00:58:44.290576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 00:58:44.293475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 00:58:44.297129 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:58:44.303613 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 00:58:44.306789 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 00:58:44.310009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5389 00:58:44.316989 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 00:58:44.319965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5391 00:58:44.323423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:58:44.330155 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:58:44.333256 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:58:44.336596 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:58:44.343181 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:58:44.346535 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:58:44.349724 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:58:44.356451 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:58:44.359708 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:58:44.363001 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:58:44.369690 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:58:44.373196 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:58:44.376192 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:58:44.382969 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5405 00:58:44.386150 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5406 00:58:44.389500 Total UI for P1: 0, mck2ui 16
5407 00:58:44.392826 best dqsien dly found for B0: ( 0, 14, 16)
5408 00:58:44.396044 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 00:58:44.399393 Total UI for P1: 0, mck2ui 16
5410 00:58:44.402517 best dqsien dly found for B1: ( 0, 14, 20)
5411 00:58:44.406062 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5412 00:58:44.409281 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5413 00:58:44.409358
5414 00:58:44.416100 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5415 00:58:44.419321 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5416 00:58:44.419397 [Gating] SW calibration Done
5417 00:58:44.422525 ==
5418 00:58:44.425722 Dram Type= 6, Freq= 0, CH_1, rank 0
5419 00:58:44.429105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5420 00:58:44.429182 ==
5421 00:58:44.429241 RX Vref Scan: 0
5422 00:58:44.429312
5423 00:58:44.432474 RX Vref 0 -> 0, step: 1
5424 00:58:44.432549
5425 00:58:44.435756 RX Delay -80 -> 252, step: 8
5426 00:58:44.439135 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5427 00:58:44.442191 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5428 00:58:44.445750 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5429 00:58:44.452638 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5430 00:58:44.455463 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5431 00:58:44.459143 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5432 00:58:44.462158 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5433 00:58:44.465502 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5434 00:58:44.472034 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5435 00:58:44.475178 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5436 00:58:44.478754 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5437 00:58:44.481948 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5438 00:58:44.485162 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5439 00:58:44.491687 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5440 00:58:44.495035 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5441 00:58:44.498247 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5442 00:58:44.498337 ==
5443 00:58:44.501786 Dram Type= 6, Freq= 0, CH_1, rank 0
5444 00:58:44.505208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5445 00:58:44.505284 ==
5446 00:58:44.508345 DQS Delay:
5447 00:58:44.508419 DQS0 = 0, DQS1 = 0
5448 00:58:44.508478 DQM Delay:
5449 00:58:44.511588 DQM0 = 93, DQM1 = 87
5450 00:58:44.511663 DQ Delay:
5451 00:58:44.515031 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5452 00:58:44.518204 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91
5453 00:58:44.521451 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5454 00:58:44.524715 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =91
5455 00:58:44.524789
5456 00:58:44.524847
5457 00:58:44.524901 ==
5458 00:58:44.528012 Dram Type= 6, Freq= 0, CH_1, rank 0
5459 00:58:44.534753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5460 00:58:44.534828 ==
5461 00:58:44.534887
5462 00:58:44.534941
5463 00:58:44.534992 TX Vref Scan disable
5464 00:58:44.538490 == TX Byte 0 ==
5465 00:58:44.541862 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5466 00:58:44.548662 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5467 00:58:44.548737 == TX Byte 1 ==
5468 00:58:44.551654 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5469 00:58:44.558459 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5470 00:58:44.558534 ==
5471 00:58:44.561837 Dram Type= 6, Freq= 0, CH_1, rank 0
5472 00:58:44.565165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5473 00:58:44.565241 ==
5474 00:58:44.565320
5475 00:58:44.565376
5476 00:58:44.568199 TX Vref Scan disable
5477 00:58:44.568308 == TX Byte 0 ==
5478 00:58:44.574938 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5479 00:58:44.578339 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5480 00:58:44.578434 == TX Byte 1 ==
5481 00:58:44.585039 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5482 00:58:44.588260 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5483 00:58:44.588336
5484 00:58:44.588394 [DATLAT]
5485 00:58:44.591800 Freq=933, CH1 RK0
5486 00:58:44.591875
5487 00:58:44.591933 DATLAT Default: 0xd
5488 00:58:44.594837 0, 0xFFFF, sum = 0
5489 00:58:44.594914 1, 0xFFFF, sum = 0
5490 00:58:44.598167 2, 0xFFFF, sum = 0
5491 00:58:44.598293 3, 0xFFFF, sum = 0
5492 00:58:44.601676 4, 0xFFFF, sum = 0
5493 00:58:44.604869 5, 0xFFFF, sum = 0
5494 00:58:44.604944 6, 0xFFFF, sum = 0
5495 00:58:44.608061 7, 0xFFFF, sum = 0
5496 00:58:44.608136 8, 0xFFFF, sum = 0
5497 00:58:44.611521 9, 0xFFFF, sum = 0
5498 00:58:44.611598 10, 0x0, sum = 1
5499 00:58:44.614814 11, 0x0, sum = 2
5500 00:58:44.614891 12, 0x0, sum = 3
5501 00:58:44.614951 13, 0x0, sum = 4
5502 00:58:44.618096 best_step = 11
5503 00:58:44.618194
5504 00:58:44.618264 ==
5505 00:58:44.621360 Dram Type= 6, Freq= 0, CH_1, rank 0
5506 00:58:44.624817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5507 00:58:44.624893 ==
5508 00:58:44.627889 RX Vref Scan: 1
5509 00:58:44.627964
5510 00:58:44.631195 RX Vref 0 -> 0, step: 1
5511 00:58:44.631270
5512 00:58:44.631327 RX Delay -69 -> 252, step: 4
5513 00:58:44.631404
5514 00:58:44.634542 Set Vref, RX VrefLevel [Byte0]: 55
5515 00:58:44.637809 [Byte1]: 50
5516 00:58:44.642701
5517 00:58:44.642776 Final RX Vref Byte 0 = 55 to rank0
5518 00:58:44.645883 Final RX Vref Byte 1 = 50 to rank0
5519 00:58:44.649095 Final RX Vref Byte 0 = 55 to rank1
5520 00:58:44.652537 Final RX Vref Byte 1 = 50 to rank1==
5521 00:58:44.655697 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 00:58:44.662252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5523 00:58:44.662328 ==
5524 00:58:44.662387 DQS Delay:
5525 00:58:44.662440 DQS0 = 0, DQS1 = 0
5526 00:58:44.665749 DQM Delay:
5527 00:58:44.665825 DQM0 = 94, DQM1 = 87
5528 00:58:44.669183 DQ Delay:
5529 00:58:44.672306 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5530 00:58:44.675695 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5531 00:58:44.679087 DQ8 =70, DQ9 =78, DQ10 =88, DQ11 =80
5532 00:58:44.682351 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =96
5533 00:58:44.682427
5534 00:58:44.682486
5535 00:58:44.689070 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5536 00:58:44.692247 CH1 RK0: MR19=505, MR18=3838
5537 00:58:44.698796 CH1_RK0: MR19=0x505, MR18=0x3838, DQSOSC=404, MR23=63, INC=66, DEC=44
5538 00:58:44.698871
5539 00:58:44.701964 ----->DramcWriteLeveling(PI) begin...
5540 00:58:44.702040 ==
5541 00:58:44.705399 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 00:58:44.708580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5543 00:58:44.708655 ==
5544 00:58:44.711854 Write leveling (Byte 0): 23 => 23
5545 00:58:44.715182 Write leveling (Byte 1): 23 => 23
5546 00:58:44.718503 DramcWriteLeveling(PI) end<-----
5547 00:58:44.718580
5548 00:58:44.718640 ==
5549 00:58:44.722156 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 00:58:44.725405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5551 00:58:44.725482 ==
5552 00:58:44.728630 [Gating] SW mode calibration
5553 00:58:44.735065 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 00:58:44.741687 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5555 00:58:44.745033 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 00:58:44.751729 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 00:58:44.755076 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 00:58:44.758326 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5559 00:58:44.765139 0 10 16 | B1->B0 | 3434 2525 | 0 0 | (1 0) (0 0)
5560 00:58:44.768363 0 10 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5561 00:58:44.771786 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 00:58:44.778153 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 00:58:44.781695 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 00:58:44.785055 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 00:58:44.791787 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 00:58:44.794900 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5567 00:58:44.798418 0 11 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5568 00:58:44.804854 0 11 20 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5569 00:58:44.808139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 00:58:44.811659 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 00:58:44.814863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 00:58:44.821351 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 00:58:44.824748 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 00:58:44.828105 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5575 00:58:44.834990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5576 00:58:44.837971 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5577 00:58:44.841177 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 00:58:44.847864 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 00:58:44.851186 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 00:58:44.854548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 00:58:44.861120 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 00:58:44.864441 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:58:44.867701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:58:44.874485 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:58:44.877892 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:58:44.881338 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:58:44.887788 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:58:44.891026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:58:44.894429 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:58:44.901262 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5591 00:58:44.904218 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5592 00:58:44.907515 Total UI for P1: 0, mck2ui 16
5593 00:58:44.910976 best dqsien dly found for B0: ( 0, 14, 12)
5594 00:58:44.914148 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 00:58:44.917553 Total UI for P1: 0, mck2ui 16
5596 00:58:44.920925 best dqsien dly found for B1: ( 0, 14, 14)
5597 00:58:44.924079 best DQS0 dly(MCK, UI, PI) = (0, 14, 12)
5598 00:58:44.927393 best DQS1 dly(MCK, UI, PI) = (0, 14, 14)
5599 00:58:44.927470
5600 00:58:44.933956 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)
5601 00:58:44.937277 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)
5602 00:58:44.940801 [Gating] SW calibration Done
5603 00:58:44.940878 ==
5604 00:58:44.944074 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 00:58:44.947409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5606 00:58:44.947487 ==
5607 00:58:44.947547 RX Vref Scan: 0
5608 00:58:44.947602
5609 00:58:44.950909 RX Vref 0 -> 0, step: 1
5610 00:58:44.950985
5611 00:58:44.954114 RX Delay -80 -> 252, step: 8
5612 00:58:44.957163 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5613 00:58:44.960679 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5614 00:58:44.967283 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5615 00:58:44.970580 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5616 00:58:44.973865 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5617 00:58:44.977283 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5618 00:58:44.980494 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5619 00:58:44.983911 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5620 00:58:44.990560 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5621 00:58:44.993696 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5622 00:58:44.997111 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5623 00:58:45.000301 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5624 00:58:45.003517 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5625 00:58:45.010356 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5626 00:58:45.013507 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5627 00:58:45.016879 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5628 00:58:45.016956 ==
5629 00:58:45.020255 Dram Type= 6, Freq= 0, CH_1, rank 1
5630 00:58:45.023371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5631 00:58:45.023451 ==
5632 00:58:45.026864 DQS Delay:
5633 00:58:45.026940 DQS0 = 0, DQS1 = 0
5634 00:58:45.030010 DQM Delay:
5635 00:58:45.030086 DQM0 = 96, DQM1 = 88
5636 00:58:45.030146 DQ Delay:
5637 00:58:45.033310 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5638 00:58:45.036756 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =91
5639 00:58:45.039925 DQ8 =75, DQ9 =75, DQ10 =83, DQ11 =83
5640 00:58:45.043477 DQ12 =95, DQ13 =103, DQ14 =91, DQ15 =99
5641 00:58:45.043553
5642 00:58:45.046628
5643 00:58:45.046704 ==
5644 00:58:45.049810 Dram Type= 6, Freq= 0, CH_1, rank 1
5645 00:58:45.053046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5646 00:58:45.053126 ==
5647 00:58:45.053185
5648 00:58:45.053239
5649 00:58:45.056685 TX Vref Scan disable
5650 00:58:45.056794 == TX Byte 0 ==
5651 00:58:45.063085 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5652 00:58:45.066243 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5653 00:58:45.066321 == TX Byte 1 ==
5654 00:58:45.073124 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5655 00:58:45.076404 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5656 00:58:45.076481 ==
5657 00:58:45.079583 Dram Type= 6, Freq= 0, CH_1, rank 1
5658 00:58:45.082946 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5659 00:58:45.083052 ==
5660 00:58:45.083115
5661 00:58:45.083170
5662 00:58:45.086174 TX Vref Scan disable
5663 00:58:45.089628 == TX Byte 0 ==
5664 00:58:45.093020 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5665 00:58:45.096222 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5666 00:58:45.099520 == TX Byte 1 ==
5667 00:58:45.102943 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5668 00:58:45.106026 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5669 00:58:45.106102
5670 00:58:45.109430 [DATLAT]
5671 00:58:45.109506 Freq=933, CH1 RK1
5672 00:58:45.109565
5673 00:58:45.112745 DATLAT Default: 0xb
5674 00:58:45.112821 0, 0xFFFF, sum = 0
5675 00:58:45.115983 1, 0xFFFF, sum = 0
5676 00:58:45.116061 2, 0xFFFF, sum = 0
5677 00:58:45.119360 3, 0xFFFF, sum = 0
5678 00:58:45.119437 4, 0xFFFF, sum = 0
5679 00:58:45.122611 5, 0xFFFF, sum = 0
5680 00:58:45.122689 6, 0xFFFF, sum = 0
5681 00:58:45.126094 7, 0xFFFF, sum = 0
5682 00:58:45.126171 8, 0xFFFF, sum = 0
5683 00:58:45.129186 9, 0xFFFF, sum = 0
5684 00:58:45.129263 10, 0x0, sum = 1
5685 00:58:45.132636 11, 0x0, sum = 2
5686 00:58:45.132713 12, 0x0, sum = 3
5687 00:58:45.136071 13, 0x0, sum = 4
5688 00:58:45.136146 best_step = 11
5689 00:58:45.136204
5690 00:58:45.136258 ==
5691 00:58:45.139059 Dram Type= 6, Freq= 0, CH_1, rank 1
5692 00:58:45.145738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5693 00:58:45.145814 ==
5694 00:58:45.145872 RX Vref Scan: 0
5695 00:58:45.145926
5696 00:58:45.148972 RX Vref 0 -> 0, step: 1
5697 00:58:45.149048
5698 00:58:45.152188 RX Delay -69 -> 252, step: 4
5699 00:58:45.155657 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5700 00:58:45.159306 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5701 00:58:45.165565 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5702 00:58:45.168936 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5703 00:58:45.172302 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5704 00:58:45.175680 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5705 00:58:45.178802 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5706 00:58:45.185426 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5707 00:58:45.188901 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5708 00:58:45.192073 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5709 00:58:45.195404 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5710 00:58:45.198625 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5711 00:58:45.205164 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5712 00:58:45.208482 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5713 00:58:45.211753 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5714 00:58:45.215141 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5715 00:58:45.215217 ==
5716 00:58:45.218546 Dram Type= 6, Freq= 0, CH_1, rank 1
5717 00:58:45.221677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5718 00:58:45.224952 ==
5719 00:58:45.225027 DQS Delay:
5720 00:58:45.225085 DQS0 = 0, DQS1 = 0
5721 00:58:45.228514 DQM Delay:
5722 00:58:45.228589 DQM0 = 95, DQM1 = 87
5723 00:58:45.231665 DQ Delay:
5724 00:58:45.234950 DQ0 =94, DQ1 =92, DQ2 =88, DQ3 =92
5725 00:58:45.235026 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5726 00:58:45.238206 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5727 00:58:45.244934 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5728 00:58:45.245009
5729 00:58:45.245075
5730 00:58:45.251461 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5731 00:58:45.254696 CH1 RK1: MR19=505, MR18=2727
5732 00:58:45.261325 CH1_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5733 00:58:45.264541 [RxdqsGatingPostProcess] freq 933
5734 00:58:45.267722 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5735 00:58:45.271062 Pre-setting of DQS Precalculation
5736 00:58:45.277621 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5737 00:58:45.284463 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5738 00:58:45.291002 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5739 00:58:45.291079
5740 00:58:45.291138
5741 00:58:45.294234 [Calibration Summary] 1866 Mbps
5742 00:58:45.294324 CH 0, Rank 0
5743 00:58:45.297673 SW Impedance : PASS
5744 00:58:45.301114 DUTY Scan : NO K
5745 00:58:45.301190 ZQ Calibration : PASS
5746 00:58:45.304398 Jitter Meter : NO K
5747 00:58:45.307434 CBT Training : PASS
5748 00:58:45.307510 Write leveling : PASS
5749 00:58:45.311245 RX DQS gating : PASS
5750 00:58:45.314220 RX DQ/DQS(RDDQC) : PASS
5751 00:58:45.314310 TX DQ/DQS : PASS
5752 00:58:45.317521 RX DATLAT : PASS
5753 00:58:45.320764 RX DQ/DQS(Engine): PASS
5754 00:58:45.320840 TX OE : NO K
5755 00:58:45.324273 All Pass.
5756 00:58:45.324349
5757 00:58:45.324408 CH 0, Rank 1
5758 00:58:45.327569 SW Impedance : PASS
5759 00:58:45.327645 DUTY Scan : NO K
5760 00:58:45.330618 ZQ Calibration : PASS
5761 00:58:45.334076 Jitter Meter : NO K
5762 00:58:45.334198 CBT Training : PASS
5763 00:58:45.337304 Write leveling : PASS
5764 00:58:45.337381 RX DQS gating : PASS
5765 00:58:45.340726 RX DQ/DQS(RDDQC) : PASS
5766 00:58:45.344076 TX DQ/DQS : PASS
5767 00:58:45.344153 RX DATLAT : PASS
5768 00:58:45.347748 RX DQ/DQS(Engine): PASS
5769 00:58:45.350794 TX OE : NO K
5770 00:58:45.350871 All Pass.
5771 00:58:45.350930
5772 00:58:45.350984 CH 1, Rank 0
5773 00:58:45.353942 SW Impedance : PASS
5774 00:58:45.357323 DUTY Scan : NO K
5775 00:58:45.357399 ZQ Calibration : PASS
5776 00:58:45.360678 Jitter Meter : NO K
5777 00:58:45.363772 CBT Training : PASS
5778 00:58:45.363848 Write leveling : PASS
5779 00:58:45.366923 RX DQS gating : PASS
5780 00:58:45.370190 RX DQ/DQS(RDDQC) : PASS
5781 00:58:45.370290 TX DQ/DQS : PASS
5782 00:58:45.373702 RX DATLAT : PASS
5783 00:58:45.376898 RX DQ/DQS(Engine): PASS
5784 00:58:45.376974 TX OE : NO K
5785 00:58:45.380244 All Pass.
5786 00:58:45.380320
5787 00:58:45.380379 CH 1, Rank 1
5788 00:58:45.383525 SW Impedance : PASS
5789 00:58:45.383625 DUTY Scan : NO K
5790 00:58:45.386916 ZQ Calibration : PASS
5791 00:58:45.390366 Jitter Meter : NO K
5792 00:58:45.390442 CBT Training : PASS
5793 00:58:45.393368 Write leveling : PASS
5794 00:58:45.396666 RX DQS gating : PASS
5795 00:58:45.396745 RX DQ/DQS(RDDQC) : PASS
5796 00:58:45.400039 TX DQ/DQS : PASS
5797 00:58:45.403286 RX DATLAT : PASS
5798 00:58:45.403363 RX DQ/DQS(Engine): PASS
5799 00:58:45.406710 TX OE : NO K
5800 00:58:45.406787 All Pass.
5801 00:58:45.406857
5802 00:58:45.409943 DramC Write-DBI off
5803 00:58:45.413151 PER_BANK_REFRESH: Hybrid Mode
5804 00:58:45.413227 TX_TRACKING: ON
5805 00:58:45.423186 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5806 00:58:45.426538 [FAST_K] Save calibration result to emmc
5807 00:58:45.429715 dramc_set_vcore_voltage set vcore to 650000
5808 00:58:45.433218 Read voltage for 400, 6
5809 00:58:45.433327 Vio18 = 0
5810 00:58:45.433424 Vcore = 650000
5811 00:58:45.436399 Vdram = 0
5812 00:58:45.436475 Vddq = 0
5813 00:58:45.436534 Vmddr = 0
5814 00:58:45.442982 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5815 00:58:45.446246 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5816 00:58:45.449589 MEM_TYPE=3, freq_sel=20
5817 00:58:45.452719 sv_algorithm_assistance_LP4_800
5818 00:58:45.456172 ============ PULL DRAM RESETB DOWN ============
5819 00:58:45.459425 ========== PULL DRAM RESETB DOWN end =========
5820 00:58:45.466183 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5821 00:58:45.469602 ===================================
5822 00:58:45.469679 LPDDR4 DRAM CONFIGURATION
5823 00:58:45.472747 ===================================
5824 00:58:45.476110 EX_ROW_EN[0] = 0x0
5825 00:58:45.479539 EX_ROW_EN[1] = 0x0
5826 00:58:45.479639 LP4Y_EN = 0x0
5827 00:58:45.482974 WORK_FSP = 0x0
5828 00:58:45.483052 WL = 0x2
5829 00:58:45.486250 RL = 0x2
5830 00:58:45.486341 BL = 0x2
5831 00:58:45.489561 RPST = 0x0
5832 00:58:45.489637 RD_PRE = 0x0
5833 00:58:45.492871 WR_PRE = 0x1
5834 00:58:45.492971 WR_PST = 0x0
5835 00:58:45.496178 DBI_WR = 0x0
5836 00:58:45.496257 DBI_RD = 0x0
5837 00:58:45.499582 OTF = 0x1
5838 00:58:45.502770 ===================================
5839 00:58:45.506087 ===================================
5840 00:58:45.506164 ANA top config
5841 00:58:45.509193 ===================================
5842 00:58:45.512842 DLL_ASYNC_EN = 0
5843 00:58:45.516087 ALL_SLAVE_EN = 1
5844 00:58:45.519134 NEW_RANK_MODE = 1
5845 00:58:45.519212 DLL_IDLE_MODE = 1
5846 00:58:45.522615 LP45_APHY_COMB_EN = 1
5847 00:58:45.525895 TX_ODT_DIS = 1
5848 00:58:45.529045 NEW_8X_MODE = 1
5849 00:58:45.532510 ===================================
5850 00:58:45.535799 ===================================
5851 00:58:45.539077 data_rate = 800
5852 00:58:45.539153 CKR = 1
5853 00:58:45.542441 DQ_P2S_RATIO = 4
5854 00:58:45.545727 ===================================
5855 00:58:45.549056 CA_P2S_RATIO = 4
5856 00:58:45.552408 DQ_CA_OPEN = 0
5857 00:58:45.555659 DQ_SEMI_OPEN = 1
5858 00:58:45.558883 CA_SEMI_OPEN = 1
5859 00:58:45.558958 CA_FULL_RATE = 0
5860 00:58:45.562086 DQ_CKDIV4_EN = 0
5861 00:58:45.565576 CA_CKDIV4_EN = 1
5862 00:58:45.569130 CA_PREDIV_EN = 0
5863 00:58:45.572053 PH8_DLY = 0
5864 00:58:45.575507 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5865 00:58:45.575583 DQ_AAMCK_DIV = 0
5866 00:58:45.578778 CA_AAMCK_DIV = 0
5867 00:58:45.582170 CA_ADMCK_DIV = 4
5868 00:58:45.585456 DQ_TRACK_CA_EN = 0
5869 00:58:45.588741 CA_PICK = 800
5870 00:58:45.592112 CA_MCKIO = 400
5871 00:58:45.595374 MCKIO_SEMI = 400
5872 00:58:45.595461 PLL_FREQ = 3016
5873 00:58:45.598640 DQ_UI_PI_RATIO = 32
5874 00:58:45.602135 CA_UI_PI_RATIO = 32
5875 00:58:45.605362 ===================================
5876 00:58:45.608875 ===================================
5877 00:58:45.611895 memory_type:LPDDR4
5878 00:58:45.615285 GP_NUM : 10
5879 00:58:45.615362 SRAM_EN : 1
5880 00:58:45.618570 MD32_EN : 0
5881 00:58:45.621849 ===================================
5882 00:58:45.621925 [ANA_INIT] >>>>>>>>>>>>>>
5883 00:58:45.625189 <<<<<< [CONFIGURE PHASE]: ANA_TX
5884 00:58:45.628572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5885 00:58:45.631926 ===================================
5886 00:58:45.635185 data_rate = 800,PCW = 0X7400
5887 00:58:45.638509 ===================================
5888 00:58:45.641759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5889 00:58:45.648609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5890 00:58:45.658405 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5891 00:58:45.665188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5892 00:58:45.668567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5893 00:58:45.671729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5894 00:58:45.671806 [ANA_INIT] flow start
5895 00:58:45.675028 [ANA_INIT] PLL >>>>>>>>
5896 00:58:45.678407 [ANA_INIT] PLL <<<<<<<<
5897 00:58:45.678484 [ANA_INIT] MIDPI >>>>>>>>
5898 00:58:45.681645 [ANA_INIT] MIDPI <<<<<<<<
5899 00:58:45.684979 [ANA_INIT] DLL >>>>>>>>
5900 00:58:45.685055 [ANA_INIT] flow end
5901 00:58:45.691554 ============ LP4 DIFF to SE enter ============
5902 00:58:45.694937 ============ LP4 DIFF to SE exit ============
5903 00:58:45.698110 [ANA_INIT] <<<<<<<<<<<<<
5904 00:58:45.701434 [Flow] Enable top DCM control >>>>>
5905 00:58:45.705072 [Flow] Enable top DCM control <<<<<
5906 00:58:45.705178 Enable DLL master slave shuffle
5907 00:58:45.711621 ==============================================================
5908 00:58:45.714715 Gating Mode config
5909 00:58:45.718249 ==============================================================
5910 00:58:45.721296 Config description:
5911 00:58:45.731312 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5912 00:58:45.738140 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5913 00:58:45.741542 SELPH_MODE 0: By rank 1: By Phase
5914 00:58:45.747991 ==============================================================
5915 00:58:45.751367 GAT_TRACK_EN = 0
5916 00:58:45.754660 RX_GATING_MODE = 2
5917 00:58:45.757961 RX_GATING_TRACK_MODE = 2
5918 00:58:45.761191 SELPH_MODE = 1
5919 00:58:45.761267 PICG_EARLY_EN = 1
5920 00:58:45.764484 VALID_LAT_VALUE = 1
5921 00:58:45.771052 ==============================================================
5922 00:58:45.774639 Enter into Gating configuration >>>>
5923 00:58:45.777831 Exit from Gating configuration <<<<
5924 00:58:45.781124 Enter into DVFS_PRE_config >>>>>
5925 00:58:45.791287 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5926 00:58:45.794491 Exit from DVFS_PRE_config <<<<<
5927 00:58:45.797693 Enter into PICG configuration >>>>
5928 00:58:45.801239 Exit from PICG configuration <<<<
5929 00:58:45.804637 [RX_INPUT] configuration >>>>>
5930 00:58:45.808015 [RX_INPUT] configuration <<<<<
5931 00:58:45.811286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5932 00:58:45.817724 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5933 00:58:45.824697 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5934 00:58:45.831158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5935 00:58:45.837596 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5936 00:58:45.840910 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5937 00:58:45.847489 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5938 00:58:45.850859 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5939 00:58:45.854070 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5940 00:58:45.857501 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5941 00:58:45.864200 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5942 00:58:45.867503 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5943 00:58:45.870695 ===================================
5944 00:58:45.873950 LPDDR4 DRAM CONFIGURATION
5945 00:58:45.877466 ===================================
5946 00:58:45.877543 EX_ROW_EN[0] = 0x0
5947 00:58:45.880610 EX_ROW_EN[1] = 0x0
5948 00:58:45.880686 LP4Y_EN = 0x0
5949 00:58:45.883950 WORK_FSP = 0x0
5950 00:58:45.884026 WL = 0x2
5951 00:58:45.887339 RL = 0x2
5952 00:58:45.887415 BL = 0x2
5953 00:58:45.890523 RPST = 0x0
5954 00:58:45.890598 RD_PRE = 0x0
5955 00:58:45.894064 WR_PRE = 0x1
5956 00:58:45.897209 WR_PST = 0x0
5957 00:58:45.897285 DBI_WR = 0x0
5958 00:58:45.900618 DBI_RD = 0x0
5959 00:58:45.900694 OTF = 0x1
5960 00:58:45.903789 ===================================
5961 00:58:45.907184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5962 00:58:45.910740 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5963 00:58:45.917202 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5964 00:58:45.920386 ===================================
5965 00:58:45.923929 LPDDR4 DRAM CONFIGURATION
5966 00:58:45.927067 ===================================
5967 00:58:45.927144 EX_ROW_EN[0] = 0x10
5968 00:58:45.930330 EX_ROW_EN[1] = 0x0
5969 00:58:45.930407 LP4Y_EN = 0x0
5970 00:58:45.933930 WORK_FSP = 0x0
5971 00:58:45.934006 WL = 0x2
5972 00:58:45.937381 RL = 0x2
5973 00:58:45.937457 BL = 0x2
5974 00:58:45.940460 RPST = 0x0
5975 00:58:45.940536 RD_PRE = 0x0
5976 00:58:45.943665 WR_PRE = 0x1
5977 00:58:45.943741 WR_PST = 0x0
5978 00:58:45.947545 DBI_WR = 0x0
5979 00:58:45.947621 DBI_RD = 0x0
5980 00:58:45.950250 OTF = 0x1
5981 00:58:45.953558 ===================================
5982 00:58:45.960067 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5983 00:58:45.963832 nWR fixed to 30
5984 00:58:45.966965 [ModeRegInit_LP4] CH0 RK0
5985 00:58:45.967041 [ModeRegInit_LP4] CH0 RK1
5986 00:58:45.970476 [ModeRegInit_LP4] CH1 RK0
5987 00:58:45.973660 [ModeRegInit_LP4] CH1 RK1
5988 00:58:45.973735 match AC timing 18
5989 00:58:45.980223 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5990 00:58:45.983491 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5991 00:58:45.986858 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5992 00:58:45.993515 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5993 00:58:45.997010 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5994 00:58:45.997085 ==
5995 00:58:46.000120 Dram Type= 6, Freq= 0, CH_0, rank 0
5996 00:58:46.003374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5997 00:58:46.003451 ==
5998 00:58:46.010011 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5999 00:58:46.016883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6000 00:58:46.019907 [CA 0] Center 36 (8~64) winsize 57
6001 00:58:46.023468 [CA 1] Center 36 (8~64) winsize 57
6002 00:58:46.026492 [CA 2] Center 36 (8~64) winsize 57
6003 00:58:46.029894 [CA 3] Center 36 (8~64) winsize 57
6004 00:58:46.029969 [CA 4] Center 36 (8~64) winsize 57
6005 00:58:46.033284 [CA 5] Center 36 (8~64) winsize 57
6006 00:58:46.033360
6007 00:58:46.039819 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6008 00:58:46.039893
6009 00:58:46.043174 [CATrainingPosCal] consider 1 rank data
6010 00:58:46.046522 u2DelayCellTimex100 = 270/100 ps
6011 00:58:46.049964 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 00:58:46.053096 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6013 00:58:46.056642 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6014 00:58:46.059839 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6015 00:58:46.063144 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 00:58:46.066483 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 00:58:46.066558
6018 00:58:46.069707 CA PerBit enable=1, Macro0, CA PI delay=36
6019 00:58:46.069782
6020 00:58:46.073021 [CBTSetCACLKResult] CA Dly = 36
6021 00:58:46.076366 CS Dly: 1 (0~32)
6022 00:58:46.076440 ==
6023 00:58:46.079673 Dram Type= 6, Freq= 0, CH_0, rank 1
6024 00:58:46.082972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6025 00:58:46.083048 ==
6026 00:58:46.089526 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6027 00:58:46.096347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6028 00:58:46.096422 [CA 0] Center 36 (8~64) winsize 57
6029 00:58:46.099610 [CA 1] Center 36 (8~64) winsize 57
6030 00:58:46.102739 [CA 2] Center 36 (8~64) winsize 57
6031 00:58:46.106129 [CA 3] Center 36 (8~64) winsize 57
6032 00:58:46.109525 [CA 4] Center 36 (8~64) winsize 57
6033 00:58:46.112812 [CA 5] Center 36 (8~64) winsize 57
6034 00:58:46.112886
6035 00:58:46.116055 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6036 00:58:46.116129
6037 00:58:46.119500 [CATrainingPosCal] consider 2 rank data
6038 00:58:46.122757 u2DelayCellTimex100 = 270/100 ps
6039 00:58:46.125991 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 00:58:46.129570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 00:58:46.135853 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 00:58:46.139361 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6043 00:58:46.142424 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6044 00:58:46.145894 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6045 00:58:46.145969
6046 00:58:46.149137 CA PerBit enable=1, Macro0, CA PI delay=36
6047 00:58:46.149213
6048 00:58:46.152527 [CBTSetCACLKResult] CA Dly = 36
6049 00:58:46.152604 CS Dly: 1 (0~32)
6050 00:58:46.152664
6051 00:58:46.155761 ----->DramcWriteLeveling(PI) begin...
6052 00:58:46.159207 ==
6053 00:58:46.162516 Dram Type= 6, Freq= 0, CH_0, rank 0
6054 00:58:46.165925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 00:58:46.166002 ==
6056 00:58:46.169142 Write leveling (Byte 0): 32 => 0
6057 00:58:46.172485 Write leveling (Byte 1): 32 => 0
6058 00:58:46.176086 DramcWriteLeveling(PI) end<-----
6059 00:58:46.176162
6060 00:58:46.176221 ==
6061 00:58:46.179146 Dram Type= 6, Freq= 0, CH_0, rank 0
6062 00:58:46.182492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6063 00:58:46.182569 ==
6064 00:58:46.185889 [Gating] SW mode calibration
6065 00:58:46.192384 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6066 00:58:46.195610 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6067 00:58:46.202438 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6068 00:58:46.205615 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6069 00:58:46.208853 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6070 00:58:46.215753 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6071 00:58:46.219011 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6072 00:58:46.222202 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6073 00:58:46.228769 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6074 00:58:46.232369 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6075 00:58:46.235554 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6076 00:58:46.238930 Total UI for P1: 0, mck2ui 16
6077 00:58:46.242089 best dqsien dly found for B0: ( 0, 10, 16)
6078 00:58:46.245635 Total UI for P1: 0, mck2ui 16
6079 00:58:46.248819 best dqsien dly found for B1: ( 0, 10, 24)
6080 00:58:46.252183 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6081 00:58:46.255686 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6082 00:58:46.255762
6083 00:58:46.262177 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6084 00:58:46.265680 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6085 00:58:46.268767 [Gating] SW calibration Done
6086 00:58:46.268843 ==
6087 00:58:46.272167 Dram Type= 6, Freq= 0, CH_0, rank 0
6088 00:58:46.275699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6089 00:58:46.275776 ==
6090 00:58:46.275835 RX Vref Scan: 0
6091 00:58:46.278786
6092 00:58:46.278862 RX Vref 0 -> 0, step: 1
6093 00:58:46.278922
6094 00:58:46.282103 RX Delay -410 -> 252, step: 16
6095 00:58:46.285390 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6096 00:58:46.292107 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6097 00:58:46.295258 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6098 00:58:46.298636 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6099 00:58:46.301907 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6100 00:58:46.308468 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6101 00:58:46.311882 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6102 00:58:46.315156 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6103 00:58:46.318516 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6104 00:58:46.324997 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6105 00:58:46.328602 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6106 00:58:46.331752 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6107 00:58:46.335288 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6108 00:58:46.341580 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6109 00:58:46.344945 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6110 00:58:46.348371 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6111 00:58:46.348464 ==
6112 00:58:46.351802 Dram Type= 6, Freq= 0, CH_0, rank 0
6113 00:58:46.358151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6114 00:58:46.358248 ==
6115 00:58:46.358321 DQS Delay:
6116 00:58:46.361676 DQS0 = 51, DQS1 = 59
6117 00:58:46.361753 DQM Delay:
6118 00:58:46.361811 DQM0 = 12, DQM1 = 15
6119 00:58:46.364932 DQ Delay:
6120 00:58:46.368207 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6121 00:58:46.371557 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6122 00:58:46.371633 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6123 00:58:46.374680 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6124 00:58:46.377947
6125 00:58:46.378023
6126 00:58:46.378082 ==
6127 00:58:46.381260 Dram Type= 6, Freq= 0, CH_0, rank 0
6128 00:58:46.384965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6129 00:58:46.385042 ==
6130 00:58:46.385103
6131 00:58:46.385174
6132 00:58:46.387869 TX Vref Scan disable
6133 00:58:46.387946 == TX Byte 0 ==
6134 00:58:46.391231 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6135 00:58:46.398043 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6136 00:58:46.398120 == TX Byte 1 ==
6137 00:58:46.401236 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6138 00:58:46.407842 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6139 00:58:46.407918 ==
6140 00:58:46.411205 Dram Type= 6, Freq= 0, CH_0, rank 0
6141 00:58:46.414654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6142 00:58:46.414730 ==
6143 00:58:46.414789
6144 00:58:46.414843
6145 00:58:46.417860 TX Vref Scan disable
6146 00:58:46.417935 == TX Byte 0 ==
6147 00:58:46.424438 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6148 00:58:46.427777 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6149 00:58:46.427853 == TX Byte 1 ==
6150 00:58:46.434531 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6151 00:58:46.437791 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6152 00:58:46.437871
6153 00:58:46.437931 [DATLAT]
6154 00:58:46.441008 Freq=400, CH0 RK0
6155 00:58:46.441084
6156 00:58:46.441143 DATLAT Default: 0xf
6157 00:58:46.444510 0, 0xFFFF, sum = 0
6158 00:58:46.444587 1, 0xFFFF, sum = 0
6159 00:58:46.447506 2, 0xFFFF, sum = 0
6160 00:58:46.447583 3, 0xFFFF, sum = 0
6161 00:58:46.450862 4, 0xFFFF, sum = 0
6162 00:58:46.450939 5, 0xFFFF, sum = 0
6163 00:58:46.454162 6, 0xFFFF, sum = 0
6164 00:58:46.454275 7, 0xFFFF, sum = 0
6165 00:58:46.457703 8, 0xFFFF, sum = 0
6166 00:58:46.460937 9, 0xFFFF, sum = 0
6167 00:58:46.461015 10, 0xFFFF, sum = 0
6168 00:58:46.464291 11, 0xFFFF, sum = 0
6169 00:58:46.464368 12, 0x0, sum = 1
6170 00:58:46.467780 13, 0x0, sum = 2
6171 00:58:46.467857 14, 0x0, sum = 3
6172 00:58:46.467917 15, 0x0, sum = 4
6173 00:58:46.470935 best_step = 13
6174 00:58:46.471012
6175 00:58:46.471071 ==
6176 00:58:46.474173 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 00:58:46.477505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 00:58:46.477581 ==
6179 00:58:46.480706 RX Vref Scan: 1
6180 00:58:46.480782
6181 00:58:46.484207 RX Vref 0 -> 0, step: 1
6182 00:58:46.484283
6183 00:58:46.484341 RX Delay -359 -> 252, step: 8
6184 00:58:46.484413
6185 00:58:46.487494 Set Vref, RX VrefLevel [Byte0]: 50
6186 00:58:46.490617 [Byte1]: 51
6187 00:58:46.496001
6188 00:58:46.496077 Final RX Vref Byte 0 = 50 to rank0
6189 00:58:46.499565 Final RX Vref Byte 1 = 51 to rank0
6190 00:58:46.502722 Final RX Vref Byte 0 = 50 to rank1
6191 00:58:46.505986 Final RX Vref Byte 1 = 51 to rank1==
6192 00:58:46.509377 Dram Type= 6, Freq= 0, CH_0, rank 0
6193 00:58:46.515881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6194 00:58:46.515957 ==
6195 00:58:46.516017 DQS Delay:
6196 00:58:46.519561 DQS0 = 52, DQS1 = 68
6197 00:58:46.519637 DQM Delay:
6198 00:58:46.519694 DQM0 = 9, DQM1 = 17
6199 00:58:46.522693 DQ Delay:
6200 00:58:46.525962 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6201 00:58:46.526038 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6202 00:58:46.529244 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6203 00:58:46.532456 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6204 00:58:46.532532
6205 00:58:46.532591
6206 00:58:46.542685 [DQSOSCAuto] RK0, (LSB)MR18= 0xa2a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6207 00:58:46.546056 CH0 RK0: MR19=C0C, MR18=A2A2
6208 00:58:46.552445 CH0_RK0: MR19=0xC0C, MR18=0xA2A2, DQSOSC=389, MR23=63, INC=390, DEC=260
6209 00:58:46.552543 ==
6210 00:58:46.555740 Dram Type= 6, Freq= 0, CH_0, rank 1
6211 00:58:46.559199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6212 00:58:46.559292 ==
6213 00:58:46.562493 [Gating] SW mode calibration
6214 00:58:46.569076 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6215 00:58:46.572385 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6216 00:58:46.579287 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6217 00:58:46.582493 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6218 00:58:46.585727 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6219 00:58:46.592191 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6220 00:58:46.595693 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6221 00:58:46.598863 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6222 00:58:46.605522 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6223 00:58:46.608858 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6224 00:58:46.612098 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6225 00:58:46.615585 Total UI for P1: 0, mck2ui 16
6226 00:58:46.619105 best dqsien dly found for B0: ( 0, 10, 16)
6227 00:58:46.622167 Total UI for P1: 0, mck2ui 16
6228 00:58:46.625598 best dqsien dly found for B1: ( 0, 10, 16)
6229 00:58:46.629298 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6230 00:58:46.632232 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6231 00:58:46.632308
6232 00:58:46.639096 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6233 00:58:46.642074 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6234 00:58:46.645677 [Gating] SW calibration Done
6235 00:58:46.645753 ==
6236 00:58:46.648759 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 00:58:46.652089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6238 00:58:46.652188 ==
6239 00:58:46.652275 RX Vref Scan: 0
6240 00:58:46.652356
6241 00:58:46.655524 RX Vref 0 -> 0, step: 1
6242 00:58:46.655601
6243 00:58:46.658722 RX Delay -410 -> 252, step: 16
6244 00:58:46.662062 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6245 00:58:46.669109 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6246 00:58:46.672075 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6247 00:58:46.675450 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6248 00:58:46.678928 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6249 00:58:46.685393 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6250 00:58:46.688569 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6251 00:58:46.691946 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6252 00:58:46.695315 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6253 00:58:46.702020 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6254 00:58:46.705537 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6255 00:58:46.708421 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6256 00:58:46.711817 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6257 00:58:46.718466 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6258 00:58:46.721746 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6259 00:58:46.725253 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6260 00:58:46.725345 ==
6261 00:58:46.728275 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 00:58:46.735112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6263 00:58:46.735204 ==
6264 00:58:46.735280 DQS Delay:
6265 00:58:46.738103 DQS0 = 43, DQS1 = 59
6266 00:58:46.738189 DQM Delay:
6267 00:58:46.738275 DQM0 = 7, DQM1 = 15
6268 00:58:46.741604 DQ Delay:
6269 00:58:46.744870 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6270 00:58:46.744955 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6271 00:58:46.748094 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6272 00:58:46.751417 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6273 00:58:46.751505
6274 00:58:46.754778
6275 00:58:46.754865 ==
6276 00:58:46.757974 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 00:58:46.761415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6278 00:58:46.761504 ==
6279 00:58:46.761579
6280 00:58:46.761650
6281 00:58:46.764986 TX Vref Scan disable
6282 00:58:46.765072 == TX Byte 0 ==
6283 00:58:46.767908 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6284 00:58:46.774554 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6285 00:58:46.774649 == TX Byte 1 ==
6286 00:58:46.777771 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6287 00:58:46.784476 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6288 00:58:46.784576 ==
6289 00:58:46.787763 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 00:58:46.791365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6291 00:58:46.791459 ==
6292 00:58:46.791537
6293 00:58:46.791609
6294 00:58:46.794427 TX Vref Scan disable
6295 00:58:46.794514 == TX Byte 0 ==
6296 00:58:46.797763 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6297 00:58:46.804348 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6298 00:58:46.804436 == TX Byte 1 ==
6299 00:58:46.807589 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6300 00:58:46.814268 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6301 00:58:46.814361
6302 00:58:46.814438 [DATLAT]
6303 00:58:46.814510 Freq=400, CH0 RK1
6304 00:58:46.817543
6305 00:58:46.817634 DATLAT Default: 0xd
6306 00:58:46.820835 0, 0xFFFF, sum = 0
6307 00:58:46.820929 1, 0xFFFF, sum = 0
6308 00:58:46.824240 2, 0xFFFF, sum = 0
6309 00:58:46.824337 3, 0xFFFF, sum = 0
6310 00:58:46.827311 4, 0xFFFF, sum = 0
6311 00:58:46.827393 5, 0xFFFF, sum = 0
6312 00:58:46.830859 6, 0xFFFF, sum = 0
6313 00:58:46.830936 7, 0xFFFF, sum = 0
6314 00:58:46.834098 8, 0xFFFF, sum = 0
6315 00:58:46.834236 9, 0xFFFF, sum = 0
6316 00:58:46.837280 10, 0xFFFF, sum = 0
6317 00:58:46.837357 11, 0xFFFF, sum = 0
6318 00:58:46.840658 12, 0x0, sum = 1
6319 00:58:46.840734 13, 0x0, sum = 2
6320 00:58:46.843889 14, 0x0, sum = 3
6321 00:58:46.843967 15, 0x0, sum = 4
6322 00:58:46.847154 best_step = 13
6323 00:58:46.847229
6324 00:58:46.847287 ==
6325 00:58:46.850539 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 00:58:46.854044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 00:58:46.854121 ==
6328 00:58:46.857326 RX Vref Scan: 0
6329 00:58:46.857401
6330 00:58:46.857459 RX Vref 0 -> 0, step: 1
6331 00:58:46.857514
6332 00:58:46.860757 RX Delay -359 -> 252, step: 8
6333 00:58:46.868557 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6334 00:58:46.871728 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6335 00:58:46.875152 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6336 00:58:46.878151 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6337 00:58:46.885013 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6338 00:58:46.888453 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6339 00:58:46.891707 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6340 00:58:46.894770 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6341 00:58:46.901546 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6342 00:58:46.904848 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6343 00:58:46.908133 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6344 00:58:46.914837 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6345 00:58:46.918035 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6346 00:58:46.921643 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6347 00:58:46.924657 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6348 00:58:46.931377 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6349 00:58:46.931453 ==
6350 00:58:46.934879 Dram Type= 6, Freq= 0, CH_0, rank 1
6351 00:58:46.938126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6352 00:58:46.938202 ==
6353 00:58:46.938269 DQS Delay:
6354 00:58:46.941284 DQS0 = 52, DQS1 = 60
6355 00:58:46.941359 DQM Delay:
6356 00:58:46.944721 DQM0 = 10, DQM1 = 9
6357 00:58:46.944796 DQ Delay:
6358 00:58:46.947999 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6359 00:58:46.951285 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6360 00:58:46.954597 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6361 00:58:46.957996 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6362 00:58:46.958071
6363 00:58:46.958129
6364 00:58:46.964457 [DQSOSCAuto] RK1, (LSB)MR18= 0xbebe, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6365 00:58:46.967830 CH0 RK1: MR19=C0C, MR18=BEBE
6366 00:58:46.974646 CH0_RK1: MR19=0xC0C, MR18=0xBEBE, DQSOSC=386, MR23=63, INC=396, DEC=264
6367 00:58:46.977787 [RxdqsGatingPostProcess] freq 400
6368 00:58:46.984610 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6369 00:58:46.984686 Pre-setting of DQS Precalculation
6370 00:58:46.991211 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6371 00:58:46.991286 ==
6372 00:58:46.994469 Dram Type= 6, Freq= 0, CH_1, rank 0
6373 00:58:46.997676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6374 00:58:46.997752 ==
6375 00:58:47.004277 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6376 00:58:47.010960 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6377 00:58:47.014434 [CA 0] Center 36 (8~64) winsize 57
6378 00:58:47.017503 [CA 1] Center 36 (8~64) winsize 57
6379 00:58:47.020738 [CA 2] Center 36 (8~64) winsize 57
6380 00:58:47.024461 [CA 3] Center 36 (8~64) winsize 57
6381 00:58:47.024537 [CA 4] Center 36 (8~64) winsize 57
6382 00:58:47.027495 [CA 5] Center 36 (8~64) winsize 57
6383 00:58:47.027571
6384 00:58:47.034363 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6385 00:58:47.034470
6386 00:58:47.037490 [CATrainingPosCal] consider 1 rank data
6387 00:58:47.040769 u2DelayCellTimex100 = 270/100 ps
6388 00:58:47.044041 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 00:58:47.047520 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6390 00:58:47.051190 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6391 00:58:47.054156 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6392 00:58:47.057285 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 00:58:47.060753 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 00:58:47.060829
6395 00:58:47.064120 CA PerBit enable=1, Macro0, CA PI delay=36
6396 00:58:47.064195
6397 00:58:47.067896 [CBTSetCACLKResult] CA Dly = 36
6398 00:58:47.070652 CS Dly: 1 (0~32)
6399 00:58:47.070729 ==
6400 00:58:47.073890 Dram Type= 6, Freq= 0, CH_1, rank 1
6401 00:58:47.077457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6402 00:58:47.077533 ==
6403 00:58:47.083850 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6404 00:58:47.090693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6405 00:58:47.090770 [CA 0] Center 36 (8~64) winsize 57
6406 00:58:47.093987 [CA 1] Center 36 (8~64) winsize 57
6407 00:58:47.097259 [CA 2] Center 36 (8~64) winsize 57
6408 00:58:47.100480 [CA 3] Center 36 (8~64) winsize 57
6409 00:58:47.103811 [CA 4] Center 36 (8~64) winsize 57
6410 00:58:47.106989 [CA 5] Center 36 (8~64) winsize 57
6411 00:58:47.107068
6412 00:58:47.110346 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6413 00:58:47.110422
6414 00:58:47.113813 [CATrainingPosCal] consider 2 rank data
6415 00:58:47.116988 u2DelayCellTimex100 = 270/100 ps
6416 00:58:47.120179 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 00:58:47.126945 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6418 00:58:47.130077 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6419 00:58:47.133360 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6420 00:58:47.136836 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6421 00:58:47.139999 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6422 00:58:47.140075
6423 00:58:47.143406 CA PerBit enable=1, Macro0, CA PI delay=36
6424 00:58:47.143484
6425 00:58:47.146784 [CBTSetCACLKResult] CA Dly = 36
6426 00:58:47.146859 CS Dly: 1 (0~32)
6427 00:58:47.150176
6428 00:58:47.153226 ----->DramcWriteLeveling(PI) begin...
6429 00:58:47.153303 ==
6430 00:58:47.156552 Dram Type= 6, Freq= 0, CH_1, rank 0
6431 00:58:47.160230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 00:58:47.160307 ==
6433 00:58:47.163057 Write leveling (Byte 0): 32 => 0
6434 00:58:47.166514 Write leveling (Byte 1): 32 => 0
6435 00:58:47.169727 DramcWriteLeveling(PI) end<-----
6436 00:58:47.169802
6437 00:58:47.169861 ==
6438 00:58:47.173188 Dram Type= 6, Freq= 0, CH_1, rank 0
6439 00:58:47.176414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6440 00:58:47.176490 ==
6441 00:58:47.179757 [Gating] SW mode calibration
6442 00:58:47.186560 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 00:58:47.193002 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6444 00:58:47.196453 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 00:58:47.199705 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 00:58:47.206133 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 00:58:47.209476 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6448 00:58:47.212946 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 00:58:47.219551 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 00:58:47.222800 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 00:58:47.226034 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6452 00:58:47.232812 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 00:58:47.232905 Total UI for P1: 0, mck2ui 16
6454 00:58:47.236059 best dqsien dly found for B0: ( 0, 10, 16)
6455 00:58:47.239580 Total UI for P1: 0, mck2ui 16
6456 00:58:47.242596 best dqsien dly found for B1: ( 0, 10, 16)
6457 00:58:47.249345 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6458 00:58:47.252475 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6459 00:58:47.252551
6460 00:58:47.255964 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6461 00:58:47.259185 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6462 00:58:47.262549 [Gating] SW calibration Done
6463 00:58:47.262625 ==
6464 00:58:47.265756 Dram Type= 6, Freq= 0, CH_1, rank 0
6465 00:58:47.269115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6466 00:58:47.269191 ==
6467 00:58:47.272485 RX Vref Scan: 0
6468 00:58:47.272561
6469 00:58:47.272620 RX Vref 0 -> 0, step: 1
6470 00:58:47.272675
6471 00:58:47.276252 RX Delay -410 -> 252, step: 16
6472 00:58:47.282484 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6473 00:58:47.285704 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6474 00:58:47.289202 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6475 00:58:47.292330 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6476 00:58:47.299104 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6477 00:58:47.302505 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6478 00:58:47.305613 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6479 00:58:47.309087 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6480 00:58:47.315511 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6481 00:58:47.318995 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6482 00:58:47.322512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6483 00:58:47.325667 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6484 00:58:47.331989 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6485 00:58:47.335440 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6486 00:58:47.338674 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6487 00:58:47.342124 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6488 00:58:47.345401 ==
6489 00:58:47.348702 Dram Type= 6, Freq= 0, CH_1, rank 0
6490 00:58:47.351933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6491 00:58:47.352009 ==
6492 00:58:47.352067 DQS Delay:
6493 00:58:47.355110 DQS0 = 43, DQS1 = 59
6494 00:58:47.355222 DQM Delay:
6495 00:58:47.358478 DQM0 = 8, DQM1 = 16
6496 00:58:47.358553 DQ Delay:
6497 00:58:47.361787 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6498 00:58:47.365268 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =8
6499 00:58:47.368445 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6500 00:58:47.371794 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6501 00:58:47.371869
6502 00:58:47.371927
6503 00:58:47.371980 ==
6504 00:58:47.375179 Dram Type= 6, Freq= 0, CH_1, rank 0
6505 00:58:47.378677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6506 00:58:47.378774 ==
6507 00:58:47.378881
6508 00:58:47.378963
6509 00:58:47.382008 TX Vref Scan disable
6510 00:58:47.382084 == TX Byte 0 ==
6511 00:58:47.388572 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6512 00:58:47.391680 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6513 00:58:47.391756 == TX Byte 1 ==
6514 00:58:47.398537 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6515 00:58:47.401844 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6516 00:58:47.401920 ==
6517 00:58:47.405096 Dram Type= 6, Freq= 0, CH_1, rank 0
6518 00:58:47.408399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6519 00:58:47.408475 ==
6520 00:58:47.408534
6521 00:58:47.408588
6522 00:58:47.411614 TX Vref Scan disable
6523 00:58:47.411690 == TX Byte 0 ==
6524 00:58:47.418577 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6525 00:58:47.421753 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6526 00:58:47.421829 == TX Byte 1 ==
6527 00:58:47.428254 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6528 00:58:47.431567 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6529 00:58:47.431643
6530 00:58:47.431702 [DATLAT]
6531 00:58:47.435080 Freq=400, CH1 RK0
6532 00:58:47.435156
6533 00:58:47.435215 DATLAT Default: 0xf
6534 00:58:47.438368 0, 0xFFFF, sum = 0
6535 00:58:47.438445 1, 0xFFFF, sum = 0
6536 00:58:47.441535 2, 0xFFFF, sum = 0
6537 00:58:47.445161 3, 0xFFFF, sum = 0
6538 00:58:47.445238 4, 0xFFFF, sum = 0
6539 00:58:47.445299 5, 0xFFFF, sum = 0
6540 00:58:47.448502 6, 0xFFFF, sum = 0
6541 00:58:47.451629 7, 0xFFFF, sum = 0
6542 00:58:47.451706 8, 0xFFFF, sum = 0
6543 00:58:47.454978 9, 0xFFFF, sum = 0
6544 00:58:47.455055 10, 0xFFFF, sum = 0
6545 00:58:47.458174 11, 0xFFFF, sum = 0
6546 00:58:47.458298 12, 0x0, sum = 1
6547 00:58:47.461443 13, 0x0, sum = 2
6548 00:58:47.461518 14, 0x0, sum = 3
6549 00:58:47.464966 15, 0x0, sum = 4
6550 00:58:47.465041 best_step = 13
6551 00:58:47.465099
6552 00:58:47.465153 ==
6553 00:58:47.468191 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 00:58:47.471608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 00:58:47.471684 ==
6556 00:58:47.474882 RX Vref Scan: 1
6557 00:58:47.474958
6558 00:58:47.478042 RX Vref 0 -> 0, step: 1
6559 00:58:47.478140
6560 00:58:47.478244 RX Delay -359 -> 252, step: 8
6561 00:58:47.481293
6562 00:58:47.481366 Set Vref, RX VrefLevel [Byte0]: 55
6563 00:58:47.484651 [Byte1]: 50
6564 00:58:47.490328
6565 00:58:47.490403 Final RX Vref Byte 0 = 55 to rank0
6566 00:58:47.493494 Final RX Vref Byte 1 = 50 to rank0
6567 00:58:47.496895 Final RX Vref Byte 0 = 55 to rank1
6568 00:58:47.500590 Final RX Vref Byte 1 = 50 to rank1==
6569 00:58:47.503531 Dram Type= 6, Freq= 0, CH_1, rank 0
6570 00:58:47.510171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6571 00:58:47.510295 ==
6572 00:58:47.510354 DQS Delay:
6573 00:58:47.513574 DQS0 = 48, DQS1 = 64
6574 00:58:47.513648 DQM Delay:
6575 00:58:47.513706 DQM0 = 7, DQM1 = 16
6576 00:58:47.516768 DQ Delay:
6577 00:58:47.520199 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6578 00:58:47.520273 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6579 00:58:47.523473 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6580 00:58:47.526796 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6581 00:58:47.526896
6582 00:58:47.526955
6583 00:58:47.536738 [DQSOSCAuto] RK0, (LSB)MR18= 0xd6d6, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6584 00:58:47.540039 CH1 RK0: MR19=C0C, MR18=D6D6
6585 00:58:47.546736 CH1_RK0: MR19=0xC0C, MR18=0xD6D6, DQSOSC=383, MR23=63, INC=402, DEC=268
6586 00:58:47.546816 ==
6587 00:58:47.549842 Dram Type= 6, Freq= 0, CH_1, rank 1
6588 00:58:47.553434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6589 00:58:47.553532 ==
6590 00:58:47.556626 [Gating] SW mode calibration
6591 00:58:47.563327 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6592 00:58:47.566520 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6593 00:58:47.573114 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6594 00:58:47.576372 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6595 00:58:47.579744 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6596 00:58:47.586343 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6597 00:58:47.589603 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6598 00:58:47.593246 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6599 00:58:47.599702 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6600 00:58:47.603109 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6601 00:58:47.606377 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6602 00:58:47.609683 Total UI for P1: 0, mck2ui 16
6603 00:58:47.612898 best dqsien dly found for B0: ( 0, 10, 16)
6604 00:58:47.616361 Total UI for P1: 0, mck2ui 16
6605 00:58:47.619561 best dqsien dly found for B1: ( 0, 10, 16)
6606 00:58:47.623032 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6607 00:58:47.626153 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6608 00:58:47.629701
6609 00:58:47.632830 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6610 00:58:47.636090 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6611 00:58:47.639502 [Gating] SW calibration Done
6612 00:58:47.639576 ==
6613 00:58:47.642897 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 00:58:47.646128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6615 00:58:47.646251 ==
6616 00:58:47.646326 RX Vref Scan: 0
6617 00:58:47.649505
6618 00:58:47.649579 RX Vref 0 -> 0, step: 1
6619 00:58:47.649637
6620 00:58:47.652775 RX Delay -410 -> 252, step: 16
6621 00:58:47.656074 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6622 00:58:47.662710 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6623 00:58:47.665923 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6624 00:58:47.669328 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6625 00:58:47.672624 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6626 00:58:47.679220 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6627 00:58:47.682601 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6628 00:58:47.686029 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6629 00:58:47.689497 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6630 00:58:47.695861 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6631 00:58:47.699047 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6632 00:58:47.702566 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6633 00:58:47.705848 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6634 00:58:47.712315 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6635 00:58:47.715657 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6636 00:58:47.718918 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6637 00:58:47.718994 ==
6638 00:58:47.722369 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 00:58:47.728882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6640 00:58:47.728958 ==
6641 00:58:47.729018 DQS Delay:
6642 00:58:47.732440 DQS0 = 43, DQS1 = 59
6643 00:58:47.732515 DQM Delay:
6644 00:58:47.732573 DQM0 = 9, DQM1 = 17
6645 00:58:47.735678 DQ Delay:
6646 00:58:47.738922 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6647 00:58:47.738998 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6648 00:58:47.742423 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6649 00:58:47.745684 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6650 00:58:47.745759
6651 00:58:47.745818
6652 00:58:47.748819 ==
6653 00:58:47.752565 Dram Type= 6, Freq= 0, CH_1, rank 1
6654 00:58:47.755566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6655 00:58:47.755643 ==
6656 00:58:47.755702
6657 00:58:47.755756
6658 00:58:47.758825 TX Vref Scan disable
6659 00:58:47.758901 == TX Byte 0 ==
6660 00:58:47.762138 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6661 00:58:47.768802 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6662 00:58:47.768878 == TX Byte 1 ==
6663 00:58:47.772068 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6664 00:58:47.778663 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6665 00:58:47.778739 ==
6666 00:58:47.782065 Dram Type= 6, Freq= 0, CH_1, rank 1
6667 00:58:47.785472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6668 00:58:47.785548 ==
6669 00:58:47.785606
6670 00:58:47.785660
6671 00:58:47.788971 TX Vref Scan disable
6672 00:58:47.789047 == TX Byte 0 ==
6673 00:58:47.792051 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6674 00:58:47.798443 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6675 00:58:47.798519 == TX Byte 1 ==
6676 00:58:47.801867 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6677 00:58:47.808253 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6678 00:58:47.808330
6679 00:58:47.808389 [DATLAT]
6680 00:58:47.808444 Freq=400, CH1 RK1
6681 00:58:47.811617
6682 00:58:47.811693 DATLAT Default: 0xd
6683 00:58:47.814787 0, 0xFFFF, sum = 0
6684 00:58:47.814865 1, 0xFFFF, sum = 0
6685 00:58:47.818174 2, 0xFFFF, sum = 0
6686 00:58:47.818290 3, 0xFFFF, sum = 0
6687 00:58:47.821724 4, 0xFFFF, sum = 0
6688 00:58:47.821801 5, 0xFFFF, sum = 0
6689 00:58:47.824837 6, 0xFFFF, sum = 0
6690 00:58:47.824907 7, 0xFFFF, sum = 0
6691 00:58:47.828039 8, 0xFFFF, sum = 0
6692 00:58:47.828117 9, 0xFFFF, sum = 0
6693 00:58:47.831335 10, 0xFFFF, sum = 0
6694 00:58:47.831413 11, 0xFFFF, sum = 0
6695 00:58:47.834680 12, 0x0, sum = 1
6696 00:58:47.834757 13, 0x0, sum = 2
6697 00:58:47.838035 14, 0x0, sum = 3
6698 00:58:47.838112 15, 0x0, sum = 4
6699 00:58:47.841201 best_step = 13
6700 00:58:47.841266
6701 00:58:47.841322 ==
6702 00:58:47.844538 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 00:58:47.848018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 00:58:47.848095 ==
6705 00:58:47.851247 RX Vref Scan: 0
6706 00:58:47.851325
6707 00:58:47.851383 RX Vref 0 -> 0, step: 1
6708 00:58:47.851438
6709 00:58:47.854478 RX Delay -359 -> 252, step: 8
6710 00:58:47.862524 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6711 00:58:47.865938 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6712 00:58:47.869170 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6713 00:58:47.872490 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6714 00:58:47.879009 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6715 00:58:47.882383 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6716 00:58:47.885664 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6717 00:58:47.888975 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6718 00:58:47.895529 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6719 00:58:47.899073 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6720 00:58:47.902129 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6721 00:58:47.909132 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6722 00:58:47.912207 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6723 00:58:47.915425 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6724 00:58:47.918705 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6725 00:58:47.925490 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6726 00:58:47.925566 ==
6727 00:58:47.928950 Dram Type= 6, Freq= 0, CH_1, rank 1
6728 00:58:47.932317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6729 00:58:47.932394 ==
6730 00:58:47.932452 DQS Delay:
6731 00:58:47.935302 DQS0 = 48, DQS1 = 64
6732 00:58:47.935377 DQM Delay:
6733 00:58:47.938599 DQM0 = 9, DQM1 = 15
6734 00:58:47.938674 DQ Delay:
6735 00:58:47.942026 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6736 00:58:47.945351 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6737 00:58:47.948635 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6738 00:58:47.952034 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6739 00:58:47.952109
6740 00:58:47.952168
6741 00:58:47.958501 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6742 00:58:47.961853 CH1 RK1: MR19=C0C, MR18=B5B5
6743 00:58:47.968922 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6744 00:58:47.972124 [RxdqsGatingPostProcess] freq 400
6745 00:58:47.978830 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6746 00:58:47.978907 Pre-setting of DQS Precalculation
6747 00:58:47.985183 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6748 00:58:47.991748 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6749 00:58:47.998382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6750 00:58:47.998459
6751 00:58:47.998518
6752 00:58:48.001556 [Calibration Summary] 800 Mbps
6753 00:58:48.004877 CH 0, Rank 0
6754 00:58:48.004953 SW Impedance : PASS
6755 00:58:48.008246 DUTY Scan : NO K
6756 00:58:48.011580 ZQ Calibration : PASS
6757 00:58:48.011658 Jitter Meter : NO K
6758 00:58:48.014784 CBT Training : PASS
6759 00:58:48.018277 Write leveling : PASS
6760 00:58:48.018353 RX DQS gating : PASS
6761 00:58:48.021506 RX DQ/DQS(RDDQC) : PASS
6762 00:58:48.021581 TX DQ/DQS : PASS
6763 00:58:48.024905 RX DATLAT : PASS
6764 00:58:48.028336 RX DQ/DQS(Engine): PASS
6765 00:58:48.028411 TX OE : NO K
6766 00:58:48.031517 All Pass.
6767 00:58:48.031592
6768 00:58:48.031650 CH 0, Rank 1
6769 00:58:48.034784 SW Impedance : PASS
6770 00:58:48.034860 DUTY Scan : NO K
6771 00:58:48.038165 ZQ Calibration : PASS
6772 00:58:48.041304 Jitter Meter : NO K
6773 00:58:48.041380 CBT Training : PASS
6774 00:58:48.044731 Write leveling : NO K
6775 00:58:48.048169 RX DQS gating : PASS
6776 00:58:48.048244 RX DQ/DQS(RDDQC) : PASS
6777 00:58:48.051151 TX DQ/DQS : PASS
6778 00:58:48.054594 RX DATLAT : PASS
6779 00:58:48.054669 RX DQ/DQS(Engine): PASS
6780 00:58:48.057933 TX OE : NO K
6781 00:58:48.058008 All Pass.
6782 00:58:48.058066
6783 00:58:48.061195 CH 1, Rank 0
6784 00:58:48.061270 SW Impedance : PASS
6785 00:58:48.064593 DUTY Scan : NO K
6786 00:58:48.067883 ZQ Calibration : PASS
6787 00:58:48.067959 Jitter Meter : NO K
6788 00:58:48.071246 CBT Training : PASS
6789 00:58:48.074416 Write leveling : PASS
6790 00:58:48.074491 RX DQS gating : PASS
6791 00:58:48.077766 RX DQ/DQS(RDDQC) : PASS
6792 00:58:48.077841 TX DQ/DQS : PASS
6793 00:58:48.081364 RX DATLAT : PASS
6794 00:58:48.084575 RX DQ/DQS(Engine): PASS
6795 00:58:48.084649 TX OE : NO K
6796 00:58:48.088042 All Pass.
6797 00:58:48.088116
6798 00:58:48.088174 CH 1, Rank 1
6799 00:58:48.091295 SW Impedance : PASS
6800 00:58:48.091370 DUTY Scan : NO K
6801 00:58:48.094561 ZQ Calibration : PASS
6802 00:58:48.097873 Jitter Meter : NO K
6803 00:58:48.097949 CBT Training : PASS
6804 00:58:48.101247 Write leveling : NO K
6805 00:58:48.104441 RX DQS gating : PASS
6806 00:58:48.104516 RX DQ/DQS(RDDQC) : PASS
6807 00:58:48.107845 TX DQ/DQS : PASS
6808 00:58:48.110995 RX DATLAT : PASS
6809 00:58:48.111071 RX DQ/DQS(Engine): PASS
6810 00:58:48.114248 TX OE : NO K
6811 00:58:48.114356 All Pass.
6812 00:58:48.114415
6813 00:58:48.117880 DramC Write-DBI off
6814 00:58:48.121034 PER_BANK_REFRESH: Hybrid Mode
6815 00:58:48.121109 TX_TRACKING: ON
6816 00:58:48.130948 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6817 00:58:48.134494 [FAST_K] Save calibration result to emmc
6818 00:58:48.137725 dramc_set_vcore_voltage set vcore to 725000
6819 00:58:48.141183 Read voltage for 1600, 0
6820 00:58:48.141259 Vio18 = 0
6821 00:58:48.141317 Vcore = 725000
6822 00:58:48.144418 Vdram = 0
6823 00:58:48.144494 Vddq = 0
6824 00:58:48.144552 Vmddr = 0
6825 00:58:48.151241 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6826 00:58:48.154160 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6827 00:58:48.157405 MEM_TYPE=3, freq_sel=13
6828 00:58:48.160897 sv_algorithm_assistance_LP4_3733
6829 00:58:48.164189 ============ PULL DRAM RESETB DOWN ============
6830 00:58:48.167408 ========== PULL DRAM RESETB DOWN end =========
6831 00:58:48.174151 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6832 00:58:48.177332 ===================================
6833 00:58:48.177408 LPDDR4 DRAM CONFIGURATION
6834 00:58:48.180717 ===================================
6835 00:58:48.183932 EX_ROW_EN[0] = 0x0
6836 00:58:48.187363 EX_ROW_EN[1] = 0x0
6837 00:58:48.187439 LP4Y_EN = 0x0
6838 00:58:48.190589 WORK_FSP = 0x1
6839 00:58:48.190665 WL = 0x5
6840 00:58:48.194111 RL = 0x5
6841 00:58:48.194217 BL = 0x2
6842 00:58:48.197349 RPST = 0x0
6843 00:58:48.197425 RD_PRE = 0x0
6844 00:58:48.200707 WR_PRE = 0x1
6845 00:58:48.200784 WR_PST = 0x1
6846 00:58:48.204122 DBI_WR = 0x0
6847 00:58:48.204196 DBI_RD = 0x0
6848 00:58:48.207364 OTF = 0x1
6849 00:58:48.210835 ===================================
6850 00:58:48.214016 ===================================
6851 00:58:48.214091 ANA top config
6852 00:58:48.217620 ===================================
6853 00:58:48.220555 DLL_ASYNC_EN = 0
6854 00:58:48.223910 ALL_SLAVE_EN = 0
6855 00:58:48.227235 NEW_RANK_MODE = 1
6856 00:58:48.227311 DLL_IDLE_MODE = 1
6857 00:58:48.230402 LP45_APHY_COMB_EN = 1
6858 00:58:48.233718 TX_ODT_DIS = 0
6859 00:58:48.237071 NEW_8X_MODE = 1
6860 00:58:48.240534 ===================================
6861 00:58:48.243738 ===================================
6862 00:58:48.246946 data_rate = 3200
6863 00:58:48.247024 CKR = 1
6864 00:58:48.250488 DQ_P2S_RATIO = 8
6865 00:58:48.253665 ===================================
6866 00:58:48.257108 CA_P2S_RATIO = 8
6867 00:58:48.260631 DQ_CA_OPEN = 0
6868 00:58:48.263642 DQ_SEMI_OPEN = 0
6869 00:58:48.266857 CA_SEMI_OPEN = 0
6870 00:58:48.266931 CA_FULL_RATE = 0
6871 00:58:48.270535 DQ_CKDIV4_EN = 0
6872 00:58:48.273672 CA_CKDIV4_EN = 0
6873 00:58:48.277010 CA_PREDIV_EN = 0
6874 00:58:48.280580 PH8_DLY = 12
6875 00:58:48.283671 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6876 00:58:48.283747 DQ_AAMCK_DIV = 4
6877 00:58:48.287105 CA_AAMCK_DIV = 4
6878 00:58:48.290249 CA_ADMCK_DIV = 4
6879 00:58:48.293546 DQ_TRACK_CA_EN = 0
6880 00:58:48.296991 CA_PICK = 1600
6881 00:58:48.300286 CA_MCKIO = 1600
6882 00:58:48.303599 MCKIO_SEMI = 0
6883 00:58:48.303675 PLL_FREQ = 3068
6884 00:58:48.306834 DQ_UI_PI_RATIO = 32
6885 00:58:48.310070 CA_UI_PI_RATIO = 0
6886 00:58:48.313583 ===================================
6887 00:58:48.316815 ===================================
6888 00:58:48.320054 memory_type:LPDDR4
6889 00:58:48.323325 GP_NUM : 10
6890 00:58:48.323401 SRAM_EN : 1
6891 00:58:48.326433 MD32_EN : 0
6892 00:58:48.330016 ===================================
6893 00:58:48.330092 [ANA_INIT] >>>>>>>>>>>>>>
6894 00:58:48.333318 <<<<<< [CONFIGURE PHASE]: ANA_TX
6895 00:58:48.336640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6896 00:58:48.339895 ===================================
6897 00:58:48.343106 data_rate = 3200,PCW = 0X7600
6898 00:58:48.346679 ===================================
6899 00:58:48.349856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6900 00:58:48.356807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6901 00:58:48.359913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6902 00:58:48.366767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6903 00:58:48.369727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6904 00:58:48.373202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6905 00:58:48.376381 [ANA_INIT] flow start
6906 00:58:48.376457 [ANA_INIT] PLL >>>>>>>>
6907 00:58:48.379723 [ANA_INIT] PLL <<<<<<<<
6908 00:58:48.383109 [ANA_INIT] MIDPI >>>>>>>>
6909 00:58:48.383185 [ANA_INIT] MIDPI <<<<<<<<
6910 00:58:48.386205 [ANA_INIT] DLL >>>>>>>>
6911 00:58:48.389799 [ANA_INIT] DLL <<<<<<<<
6912 00:58:48.389874 [ANA_INIT] flow end
6913 00:58:48.396255 ============ LP4 DIFF to SE enter ============
6914 00:58:48.399540 ============ LP4 DIFF to SE exit ============
6915 00:58:48.402804 [ANA_INIT] <<<<<<<<<<<<<
6916 00:58:48.406138 [Flow] Enable top DCM control >>>>>
6917 00:58:48.409469 [Flow] Enable top DCM control <<<<<
6918 00:58:48.409545 Enable DLL master slave shuffle
6919 00:58:48.416094 ==============================================================
6920 00:58:48.419280 Gating Mode config
6921 00:58:48.422649 ==============================================================
6922 00:58:48.425899 Config description:
6923 00:58:48.436043 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6924 00:58:48.442625 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6925 00:58:48.446104 SELPH_MODE 0: By rank 1: By Phase
6926 00:58:48.452516 ==============================================================
6927 00:58:48.455838 GAT_TRACK_EN = 1
6928 00:58:48.459039 RX_GATING_MODE = 2
6929 00:58:48.462497 RX_GATING_TRACK_MODE = 2
6930 00:58:48.465730 SELPH_MODE = 1
6931 00:58:48.465806 PICG_EARLY_EN = 1
6932 00:58:48.468838 VALID_LAT_VALUE = 1
6933 00:58:48.475607 ==============================================================
6934 00:58:48.478870 Enter into Gating configuration >>>>
6935 00:58:48.482067 Exit from Gating configuration <<<<
6936 00:58:48.485459 Enter into DVFS_PRE_config >>>>>
6937 00:58:48.495298 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6938 00:58:48.498577 Exit from DVFS_PRE_config <<<<<
6939 00:58:48.502053 Enter into PICG configuration >>>>
6940 00:58:48.505245 Exit from PICG configuration <<<<
6941 00:58:48.508563 [RX_INPUT] configuration >>>>>
6942 00:58:48.511840 [RX_INPUT] configuration <<<<<
6943 00:58:48.515362 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6944 00:58:48.521939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6945 00:58:48.528669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6946 00:58:48.535117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6947 00:58:48.541665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6948 00:58:48.548391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6949 00:58:48.551681 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6950 00:58:48.555301 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6951 00:58:48.558265 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6952 00:58:48.565116 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6953 00:58:48.568144 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6954 00:58:48.571502 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6955 00:58:48.574937 ===================================
6956 00:58:48.578254 LPDDR4 DRAM CONFIGURATION
6957 00:58:48.581460 ===================================
6958 00:58:48.581536 EX_ROW_EN[0] = 0x0
6959 00:58:48.584863 EX_ROW_EN[1] = 0x0
6960 00:58:48.584938 LP4Y_EN = 0x0
6961 00:58:48.588188 WORK_FSP = 0x1
6962 00:58:48.591539 WL = 0x5
6963 00:58:48.591616 RL = 0x5
6964 00:58:48.594764 BL = 0x2
6965 00:58:48.594840 RPST = 0x0
6966 00:58:48.598005 RD_PRE = 0x0
6967 00:58:48.598114 WR_PRE = 0x1
6968 00:58:48.601253 WR_PST = 0x1
6969 00:58:48.601329 DBI_WR = 0x0
6970 00:58:48.604575 DBI_RD = 0x0
6971 00:58:48.604651 OTF = 0x1
6972 00:58:48.608021 ===================================
6973 00:58:48.611209 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6974 00:58:48.617947 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6975 00:58:48.621011 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6976 00:58:48.624539 ===================================
6977 00:58:48.627720 LPDDR4 DRAM CONFIGURATION
6978 00:58:48.631157 ===================================
6979 00:58:48.631234 EX_ROW_EN[0] = 0x10
6980 00:58:48.634545 EX_ROW_EN[1] = 0x0
6981 00:58:48.634621 LP4Y_EN = 0x0
6982 00:58:48.637645 WORK_FSP = 0x1
6983 00:58:48.637720 WL = 0x5
6984 00:58:48.640866 RL = 0x5
6985 00:58:48.644473 BL = 0x2
6986 00:58:48.644549 RPST = 0x0
6987 00:58:48.647620 RD_PRE = 0x0
6988 00:58:48.647697 WR_PRE = 0x1
6989 00:58:48.650863 WR_PST = 0x1
6990 00:58:48.650939 DBI_WR = 0x0
6991 00:58:48.654338 DBI_RD = 0x0
6992 00:58:48.654432 OTF = 0x1
6993 00:58:48.657577 ===================================
6994 00:58:48.664165 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6995 00:58:48.664244 ==
6996 00:58:48.667451 Dram Type= 6, Freq= 0, CH_0, rank 0
6997 00:58:48.670843 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6998 00:58:48.670920 ==
6999 00:58:48.674142 [Duty_Offset_Calibration]
7000 00:58:48.677546 B0:0 B1:2 CA:1
7001 00:58:48.677622
7002 00:58:48.680619 [DutyScan_Calibration_Flow] k_type=0
7003 00:58:48.689161
7004 00:58:48.689240 ==CLK 0==
7005 00:58:48.692454 Final CLK duty delay cell = 0
7006 00:58:48.695801 [0] MAX Duty = 5156%(X100), DQS PI = 20
7007 00:58:48.699158 [0] MIN Duty = 4938%(X100), DQS PI = 50
7008 00:58:48.702299 [0] AVG Duty = 5047%(X100)
7009 00:58:48.702374
7010 00:58:48.705875 CH0 CLK Duty spec in!! Max-Min= 218%
7011 00:58:48.709171 [DutyScan_Calibration_Flow] ====Done====
7012 00:58:48.709247
7013 00:58:48.712494 [DutyScan_Calibration_Flow] k_type=1
7014 00:58:48.729229
7015 00:58:48.729304 ==DQS 0 ==
7016 00:58:48.732625 Final DQS duty delay cell = 0
7017 00:58:48.736091 [0] MAX Duty = 5156%(X100), DQS PI = 36
7018 00:58:48.739352 [0] MIN Duty = 5031%(X100), DQS PI = 8
7019 00:58:48.739428 [0] AVG Duty = 5093%(X100)
7020 00:58:48.742728
7021 00:58:48.742803 ==DQS 1 ==
7022 00:58:48.746234 Final DQS duty delay cell = 0
7023 00:58:48.749270 [0] MAX Duty = 5031%(X100), DQS PI = 2
7024 00:58:48.752593 [0] MIN Duty = 4876%(X100), DQS PI = 16
7025 00:58:48.752669 [0] AVG Duty = 4953%(X100)
7026 00:58:48.755732
7027 00:58:48.759327 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7028 00:58:48.759406
7029 00:58:48.762513 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7030 00:58:48.765988 [DutyScan_Calibration_Flow] ====Done====
7031 00:58:48.766063
7032 00:58:48.768893 [DutyScan_Calibration_Flow] k_type=3
7033 00:58:48.786189
7034 00:58:48.786307 ==DQM 0 ==
7035 00:58:48.789606 Final DQM duty delay cell = 0
7036 00:58:48.793030 [0] MAX Duty = 5187%(X100), DQS PI = 24
7037 00:58:48.796265 [0] MIN Duty = 4876%(X100), DQS PI = 56
7038 00:58:48.799495 [0] AVG Duty = 5031%(X100)
7039 00:58:48.799571
7040 00:58:48.799629 ==DQM 1 ==
7041 00:58:48.802887 Final DQM duty delay cell = 0
7042 00:58:48.806302 [0] MAX Duty = 5031%(X100), DQS PI = 4
7043 00:58:48.809494 [0] MIN Duty = 4782%(X100), DQS PI = 14
7044 00:58:48.812850 [0] AVG Duty = 4906%(X100)
7045 00:58:48.812929
7046 00:58:48.816074 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7047 00:58:48.816150
7048 00:58:48.819461 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7049 00:58:48.822497 [DutyScan_Calibration_Flow] ====Done====
7050 00:58:48.822573
7051 00:58:48.826026 [DutyScan_Calibration_Flow] k_type=2
7052 00:58:48.842616
7053 00:58:48.842697 ==DQ 0 ==
7054 00:58:48.845912 Final DQ duty delay cell = 0
7055 00:58:48.849239 [0] MAX Duty = 5218%(X100), DQS PI = 18
7056 00:58:48.852455 [0] MIN Duty = 4938%(X100), DQS PI = 56
7057 00:58:48.855793 [0] AVG Duty = 5078%(X100)
7058 00:58:48.855869
7059 00:58:48.855927 ==DQ 1 ==
7060 00:58:48.858979 Final DQ duty delay cell = -4
7061 00:58:48.862334 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7062 00:58:48.865614 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7063 00:58:48.869007 [-4] AVG Duty = 4953%(X100)
7064 00:58:48.869084
7065 00:58:48.872436 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7066 00:58:48.872512
7067 00:58:48.875721 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7068 00:58:48.878901 [DutyScan_Calibration_Flow] ====Done====
7069 00:58:48.878979 ==
7070 00:58:48.882141 Dram Type= 6, Freq= 0, CH_1, rank 0
7071 00:58:48.885523 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7072 00:58:48.885601 ==
7073 00:58:48.888961 [Duty_Offset_Calibration]
7074 00:58:48.889038 B0:0 B1:5 CA:-5
7075 00:58:48.889098
7076 00:58:48.892314 [DutyScan_Calibration_Flow] k_type=0
7077 00:58:48.903160
7078 00:58:48.903248 ==CLK 0==
7079 00:58:48.906452 Final CLK duty delay cell = 0
7080 00:58:48.910107 [0] MAX Duty = 5156%(X100), DQS PI = 20
7081 00:58:48.913176 [0] MIN Duty = 4906%(X100), DQS PI = 50
7082 00:58:48.916612 [0] AVG Duty = 5031%(X100)
7083 00:58:48.916689
7084 00:58:48.919826 CH1 CLK Duty spec in!! Max-Min= 250%
7085 00:58:48.923122 [DutyScan_Calibration_Flow] ====Done====
7086 00:58:48.923200
7087 00:58:48.926142 [DutyScan_Calibration_Flow] k_type=1
7088 00:58:48.942048
7089 00:58:48.942144 ==DQS 0 ==
7090 00:58:48.945418 Final DQS duty delay cell = 0
7091 00:58:48.948800 [0] MAX Duty = 5156%(X100), DQS PI = 18
7092 00:58:48.952076 [0] MIN Duty = 4907%(X100), DQS PI = 0
7093 00:58:48.955284 [0] AVG Duty = 5031%(X100)
7094 00:58:48.955361
7095 00:58:48.955421 ==DQS 1 ==
7096 00:58:48.958864 Final DQS duty delay cell = -4
7097 00:58:48.961803 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7098 00:58:48.965080 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7099 00:58:48.968673 [-4] AVG Duty = 4922%(X100)
7100 00:58:48.968751
7101 00:58:48.971927 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7102 00:58:48.972005
7103 00:58:48.975109 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7104 00:58:48.978359 [DutyScan_Calibration_Flow] ====Done====
7105 00:58:48.978437
7106 00:58:48.981740 [DutyScan_Calibration_Flow] k_type=3
7107 00:58:48.997693
7108 00:58:48.997774 ==DQM 0 ==
7109 00:58:49.001112 Final DQM duty delay cell = -4
7110 00:58:49.004444 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7111 00:58:49.007827 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7112 00:58:49.011061 [-4] AVG Duty = 4922%(X100)
7113 00:58:49.011137
7114 00:58:49.011196 ==DQM 1 ==
7115 00:58:49.014521 Final DQM duty delay cell = -4
7116 00:58:49.017766 [-4] MAX Duty = 5031%(X100), DQS PI = 0
7117 00:58:49.020964 [-4] MIN Duty = 4875%(X100), DQS PI = 36
7118 00:58:49.024485 [-4] AVG Duty = 4953%(X100)
7119 00:58:49.024561
7120 00:58:49.027474 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7121 00:58:49.027550
7122 00:58:49.030739 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7123 00:58:49.034000 [DutyScan_Calibration_Flow] ====Done====
7124 00:58:49.034076
7125 00:58:49.037507 [DutyScan_Calibration_Flow] k_type=2
7126 00:58:49.055295
7127 00:58:49.055375 ==DQ 0 ==
7128 00:58:49.058490 Final DQ duty delay cell = 0
7129 00:58:49.062195 [0] MAX Duty = 5093%(X100), DQS PI = 36
7130 00:58:49.065216 [0] MIN Duty = 4938%(X100), DQS PI = 48
7131 00:58:49.065292 [0] AVG Duty = 5015%(X100)
7132 00:58:49.068613
7133 00:58:49.068689 ==DQ 1 ==
7134 00:58:49.071889 Final DQ duty delay cell = 0
7135 00:58:49.075091 [0] MAX Duty = 5062%(X100), DQS PI = 6
7136 00:58:49.078291 [0] MIN Duty = 4876%(X100), DQS PI = 24
7137 00:58:49.078375 [0] AVG Duty = 4969%(X100)
7138 00:58:49.078433
7139 00:58:49.081801 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7140 00:58:49.085175
7141 00:58:49.088447 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7142 00:58:49.091803 [DutyScan_Calibration_Flow] ====Done====
7143 00:58:49.095006 nWR fixed to 30
7144 00:58:49.095087 [ModeRegInit_LP4] CH0 RK0
7145 00:58:49.098248 [ModeRegInit_LP4] CH0 RK1
7146 00:58:49.101555 [ModeRegInit_LP4] CH1 RK0
7147 00:58:49.105069 [ModeRegInit_LP4] CH1 RK1
7148 00:58:49.105172 match AC timing 4
7149 00:58:49.108157 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7150 00:58:49.114806 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7151 00:58:49.118189 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7152 00:58:49.124920 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7153 00:58:49.128146 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7154 00:58:49.128227 [MiockJmeterHQA]
7155 00:58:49.128286
7156 00:58:49.131436 [DramcMiockJmeter] u1RxGatingPI = 0
7157 00:58:49.134740 0 : 4255, 4029
7158 00:58:49.134822 4 : 4252, 4027
7159 00:58:49.138190 8 : 4252, 4027
7160 00:58:49.138313 12 : 4254, 4029
7161 00:58:49.138374 16 : 4363, 4137
7162 00:58:49.141156 20 : 4252, 4026
7163 00:58:49.141258 24 : 4252, 4027
7164 00:58:49.144652 28 : 4252, 4027
7165 00:58:49.144731 32 : 4255, 4029
7166 00:58:49.148122 36 : 4362, 4137
7167 00:58:49.148202 40 : 4252, 4027
7168 00:58:49.151306 44 : 4363, 4138
7169 00:58:49.151407 48 : 4252, 4030
7170 00:58:49.151518 52 : 4250, 4027
7171 00:58:49.154677 56 : 4249, 4027
7172 00:58:49.154756 60 : 4361, 4137
7173 00:58:49.158092 64 : 4250, 4027
7174 00:58:49.158199 68 : 4361, 4137
7175 00:58:49.161514 72 : 4250, 4026
7176 00:58:49.161593 76 : 4250, 4027
7177 00:58:49.161653 80 : 4249, 4027
7178 00:58:49.164639 84 : 4253, 4029
7179 00:58:49.164772 88 : 4360, 4137
7180 00:58:49.168043 92 : 4250, 4026
7181 00:58:49.168123 96 : 4360, 4138
7182 00:58:49.171564 100 : 4249, 1620
7183 00:58:49.171645 104 : 4361, 0
7184 00:58:49.174680 108 : 4361, 0
7185 00:58:49.174756 112 : 4361, 0
7186 00:58:49.174838 116 : 4250, 0
7187 00:58:49.177950 120 : 4250, 0
7188 00:58:49.178053 124 : 4363, 0
7189 00:58:49.178140 128 : 4250, 0
7190 00:58:49.181032 132 : 4250, 0
7191 00:58:49.181111 136 : 4250, 0
7192 00:58:49.184356 140 : 4253, 0
7193 00:58:49.184435 144 : 4250, 0
7194 00:58:49.184495 148 : 4249, 0
7195 00:58:49.187677 152 : 4253, 0
7196 00:58:49.187754 156 : 4250, 0
7197 00:58:49.190943 160 : 4361, 0
7198 00:58:49.191010 164 : 4250, 0
7199 00:58:49.191066 168 : 4250, 0
7200 00:58:49.194408 172 : 4249, 0
7201 00:58:49.194488 176 : 4363, 0
7202 00:58:49.197891 180 : 4250, 0
7203 00:58:49.197967 184 : 4249, 0
7204 00:58:49.198027 188 : 4250, 0
7205 00:58:49.201022 192 : 4253, 0
7206 00:58:49.201098 196 : 4360, 0
7207 00:58:49.201158 200 : 4250, 0
7208 00:58:49.204541 204 : 4250, 0
7209 00:58:49.204618 208 : 4250, 0
7210 00:58:49.207598 212 : 4360, 0
7211 00:58:49.207675 216 : 4361, 0
7212 00:58:49.207734 220 : 4250, 553
7213 00:58:49.211170 224 : 4250, 3966
7214 00:58:49.211247 228 : 4360, 4138
7215 00:58:49.214386 232 : 4360, 4137
7216 00:58:49.214463 236 : 4248, 4024
7217 00:58:49.217605 240 : 4363, 4140
7218 00:58:49.217681 244 : 4250, 4027
7219 00:58:49.221131 248 : 4249, 4027
7220 00:58:49.221208 252 : 4250, 4026
7221 00:58:49.224246 256 : 4253, 4029
7222 00:58:49.224322 260 : 4250, 4027
7223 00:58:49.227641 264 : 4249, 4027
7224 00:58:49.227717 268 : 4250, 4026
7225 00:58:49.231057 272 : 4253, 4029
7226 00:58:49.231133 276 : 4250, 4027
7227 00:58:49.231192 280 : 4360, 4138
7228 00:58:49.234221 284 : 4361, 4137
7229 00:58:49.234297 288 : 4250, 4026
7230 00:58:49.237908 292 : 4363, 4140
7231 00:58:49.237985 296 : 4250, 4027
7232 00:58:49.240824 300 : 4249, 4027
7233 00:58:49.240900 304 : 4250, 4026
7234 00:58:49.244598 308 : 4253, 4029
7235 00:58:49.244674 312 : 4250, 4027
7236 00:58:49.247534 316 : 4249, 4027
7237 00:58:49.247611 320 : 4250, 4026
7238 00:58:49.251206 324 : 4253, 4029
7239 00:58:49.251290 328 : 4250, 4027
7240 00:58:49.254249 332 : 4360, 4138
7241 00:58:49.254325 336 : 4360, 3995
7242 00:58:49.254384 340 : 4250, 1662
7243 00:58:49.257637
7244 00:58:49.257733 MIOCK jitter meter ch=0
7245 00:58:49.257816
7246 00:58:49.261050 1T = (340-100) = 240 dly cells
7247 00:58:49.267701 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7248 00:58:49.267776 ==
7249 00:58:49.270664 Dram Type= 6, Freq= 0, CH_0, rank 0
7250 00:58:49.274223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7251 00:58:49.274330 ==
7252 00:58:49.280668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7253 00:58:49.284160 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7254 00:58:49.287297 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7255 00:58:49.294087 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7256 00:58:49.302467 [CA 0] Center 42 (12~73) winsize 62
7257 00:58:49.305837 [CA 1] Center 42 (12~73) winsize 62
7258 00:58:49.309144 [CA 2] Center 39 (9~69) winsize 61
7259 00:58:49.312719 [CA 3] Center 38 (9~68) winsize 60
7260 00:58:49.315710 [CA 4] Center 37 (7~67) winsize 61
7261 00:58:49.319243 [CA 5] Center 36 (6~66) winsize 61
7262 00:58:49.319351
7263 00:58:49.322501 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7264 00:58:49.322577
7265 00:58:49.325558 [CATrainingPosCal] consider 1 rank data
7266 00:58:49.329051 u2DelayCellTimex100 = 271/100 ps
7267 00:58:49.335571 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7268 00:58:49.339221 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7269 00:58:49.342342 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7270 00:58:49.345595 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7271 00:58:49.349043 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7272 00:58:49.352313 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7273 00:58:49.352391
7274 00:58:49.355607 CA PerBit enable=1, Macro0, CA PI delay=36
7275 00:58:49.355684
7276 00:58:49.359008 [CBTSetCACLKResult] CA Dly = 36
7277 00:58:49.362334 CS Dly: 10 (0~41)
7278 00:58:49.365550 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7279 00:58:49.368945 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7280 00:58:49.369024 ==
7281 00:58:49.372366 Dram Type= 6, Freq= 0, CH_0, rank 1
7282 00:58:49.376113 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7283 00:58:49.378799 ==
7284 00:58:49.382255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7285 00:58:49.385714 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7286 00:58:49.392072 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7287 00:58:49.398605 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7288 00:58:49.405238 [CA 0] Center 42 (12~73) winsize 62
7289 00:58:49.408663 [CA 1] Center 42 (12~73) winsize 62
7290 00:58:49.412159 [CA 2] Center 38 (9~68) winsize 60
7291 00:58:49.415252 [CA 3] Center 37 (8~67) winsize 60
7292 00:58:49.418708 [CA 4] Center 36 (6~66) winsize 61
7293 00:58:49.422195 [CA 5] Center 36 (6~66) winsize 61
7294 00:58:49.422286
7295 00:58:49.425533 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7296 00:58:49.425610
7297 00:58:49.428508 [CATrainingPosCal] consider 2 rank data
7298 00:58:49.431674 u2DelayCellTimex100 = 271/100 ps
7299 00:58:49.434988 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7300 00:58:49.441651 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7301 00:58:49.444833 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7302 00:58:49.448365 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7303 00:58:49.451556 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7304 00:58:49.454907 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7305 00:58:49.454983
7306 00:58:49.458251 CA PerBit enable=1, Macro0, CA PI delay=36
7307 00:58:49.458327
7308 00:58:49.461589 [CBTSetCACLKResult] CA Dly = 36
7309 00:58:49.465077 CS Dly: 10 (0~42)
7310 00:58:49.468259 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7311 00:58:49.471756 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7312 00:58:49.471832
7313 00:58:49.474869 ----->DramcWriteLeveling(PI) begin...
7314 00:58:49.474945 ==
7315 00:58:49.478376 Dram Type= 6, Freq= 0, CH_0, rank 0
7316 00:58:49.484911 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7317 00:58:49.484987 ==
7318 00:58:49.488289 Write leveling (Byte 0): 31 => 31
7319 00:58:49.488366 Write leveling (Byte 1): 27 => 27
7320 00:58:49.491868 DramcWriteLeveling(PI) end<-----
7321 00:58:49.491944
7322 00:58:49.492002 ==
7323 00:58:49.494856 Dram Type= 6, Freq= 0, CH_0, rank 0
7324 00:58:49.501576 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7325 00:58:49.501660 ==
7326 00:58:49.504957 [Gating] SW mode calibration
7327 00:58:49.511480 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7328 00:58:49.514692 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7329 00:58:49.521412 0 12 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7330 00:58:49.524698 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7331 00:58:49.528189 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7332 00:58:49.534943 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7333 00:58:49.538138 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7334 00:58:49.541271 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7335 00:58:49.545135 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7336 00:58:49.551462 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7337 00:58:49.554693 0 13 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7338 00:58:49.558178 0 13 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
7339 00:58:49.564823 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 00:58:49.568030 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7341 00:58:49.571410 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7342 00:58:49.577775 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7343 00:58:49.581097 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7344 00:58:49.584684 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7345 00:58:49.591218 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
7346 00:58:49.594491 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7347 00:58:49.597674 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 00:58:49.604607 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 00:58:49.607830 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7350 00:58:49.611278 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7351 00:58:49.617503 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7352 00:58:49.620958 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7353 00:58:49.624141 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7354 00:58:49.630706 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7355 00:58:49.634056 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7356 00:58:49.637312 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 00:58:49.644011 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 00:58:49.647323 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 00:58:49.650750 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 00:58:49.657206 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 00:58:49.660566 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 00:58:49.664066 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 00:58:49.670553 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 00:58:49.673789 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 00:58:49.677135 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 00:58:49.683801 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 00:58:49.687039 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7368 00:58:49.690339 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7369 00:58:49.696995 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7370 00:58:49.700289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7371 00:58:49.703540 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7372 00:58:49.707009 Total UI for P1: 0, mck2ui 16
7373 00:58:49.710447 best dqsien dly found for B0: ( 1, 1, 0)
7374 00:58:49.713556 Total UI for P1: 0, mck2ui 16
7375 00:58:49.716887 best dqsien dly found for B1: ( 1, 1, 2)
7376 00:58:49.720548 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7377 00:58:49.723811 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7378 00:58:49.723915
7379 00:58:49.726708 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7380 00:58:49.733336 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7381 00:58:49.733412 [Gating] SW calibration Done
7382 00:58:49.733471 ==
7383 00:58:49.736780 Dram Type= 6, Freq= 0, CH_0, rank 0
7384 00:58:49.743379 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7385 00:58:49.743455 ==
7386 00:58:49.743514 RX Vref Scan: 0
7387 00:58:49.743569
7388 00:58:49.746520 RX Vref 0 -> 0, step: 1
7389 00:58:49.746595
7390 00:58:49.749870 RX Delay 0 -> 252, step: 8
7391 00:58:49.753203 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7392 00:58:49.756481 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7393 00:58:49.759894 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7394 00:58:49.766269 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7395 00:58:49.769687 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7396 00:58:49.773081 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7397 00:58:49.776155 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7398 00:58:49.779809 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7399 00:58:49.786154 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7400 00:58:49.789442 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7401 00:58:49.792642 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7402 00:58:49.796026 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7403 00:58:49.799510 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7404 00:58:49.806147 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7405 00:58:49.809334 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7406 00:58:49.812621 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7407 00:58:49.812698 ==
7408 00:58:49.816101 Dram Type= 6, Freq= 0, CH_0, rank 0
7409 00:58:49.819542 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7410 00:58:49.819618 ==
7411 00:58:49.822641 DQS Delay:
7412 00:58:49.822716 DQS0 = 0, DQS1 = 0
7413 00:58:49.826143 DQM Delay:
7414 00:58:49.826245 DQM0 = 130, DQM1 = 124
7415 00:58:49.829669 DQ Delay:
7416 00:58:49.832767 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7417 00:58:49.836323 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7418 00:58:49.839366 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7419 00:58:49.842687 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7420 00:58:49.842765
7421 00:58:49.842824
7422 00:58:49.842878 ==
7423 00:58:49.846079 Dram Type= 6, Freq= 0, CH_0, rank 0
7424 00:58:49.849289 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7425 00:58:49.849368 ==
7426 00:58:49.849429
7427 00:58:49.849483
7428 00:58:49.852854 TX Vref Scan disable
7429 00:58:49.856139 == TX Byte 0 ==
7430 00:58:49.859421 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7431 00:58:49.862736 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7432 00:58:49.865849 == TX Byte 1 ==
7433 00:58:49.869279 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7434 00:58:49.872473 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7435 00:58:49.872549 ==
7436 00:58:49.875917 Dram Type= 6, Freq= 0, CH_0, rank 0
7437 00:58:49.882420 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7438 00:58:49.882507 ==
7439 00:58:49.893790
7440 00:58:49.897546 TX Vref early break, caculate TX vref
7441 00:58:49.900543 TX Vref=16, minBit 8, minWin=21, winSum=374
7442 00:58:49.903752 TX Vref=18, minBit 9, minWin=22, winSum=381
7443 00:58:49.907049 TX Vref=20, minBit 9, minWin=22, winSum=392
7444 00:58:49.910512 TX Vref=22, minBit 8, minWin=24, winSum=404
7445 00:58:49.913767 TX Vref=24, minBit 8, minWin=24, winSum=400
7446 00:58:49.920427 TX Vref=26, minBit 7, minWin=25, winSum=418
7447 00:58:49.923741 TX Vref=28, minBit 3, minWin=25, winSum=411
7448 00:58:49.927032 TX Vref=30, minBit 8, minWin=24, winSum=411
7449 00:58:49.930510 TX Vref=32, minBit 8, minWin=23, winSum=399
7450 00:58:49.933713 TX Vref=34, minBit 8, minWin=23, winSum=396
7451 00:58:49.940434 [TxChooseVref] Worse bit 7, Min win 25, Win sum 418, Final Vref 26
7452 00:58:49.940512
7453 00:58:49.943868 Final TX Range 0 Vref 26
7454 00:58:49.943944
7455 00:58:49.944016 ==
7456 00:58:49.947003 Dram Type= 6, Freq= 0, CH_0, rank 0
7457 00:58:49.950325 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7458 00:58:49.950401 ==
7459 00:58:49.950459
7460 00:58:49.950513
7461 00:58:49.953756 TX Vref Scan disable
7462 00:58:49.960511 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7463 00:58:49.960590 == TX Byte 0 ==
7464 00:58:49.963724 u2DelayCellOfst[0]=14 cells (4 PI)
7465 00:58:49.967128 u2DelayCellOfst[1]=18 cells (5 PI)
7466 00:58:49.970502 u2DelayCellOfst[2]=14 cells (4 PI)
7467 00:58:49.973557 u2DelayCellOfst[3]=14 cells (4 PI)
7468 00:58:49.976771 u2DelayCellOfst[4]=7 cells (2 PI)
7469 00:58:49.980080 u2DelayCellOfst[5]=0 cells (0 PI)
7470 00:58:49.983526 u2DelayCellOfst[6]=18 cells (5 PI)
7471 00:58:49.986903 u2DelayCellOfst[7]=18 cells (5 PI)
7472 00:58:49.990171 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7473 00:58:49.993672 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7474 00:58:49.996901 == TX Byte 1 ==
7475 00:58:49.996978 u2DelayCellOfst[8]=0 cells (0 PI)
7476 00:58:50.000143 u2DelayCellOfst[9]=0 cells (0 PI)
7477 00:58:50.003466 u2DelayCellOfst[10]=10 cells (3 PI)
7478 00:58:50.006874 u2DelayCellOfst[11]=0 cells (0 PI)
7479 00:58:50.010138 u2DelayCellOfst[12]=10 cells (3 PI)
7480 00:58:50.013567 u2DelayCellOfst[13]=10 cells (3 PI)
7481 00:58:50.016661 u2DelayCellOfst[14]=14 cells (4 PI)
7482 00:58:50.020017 u2DelayCellOfst[15]=10 cells (3 PI)
7483 00:58:50.023358 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7484 00:58:50.030120 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7485 00:58:50.030232 DramC Write-DBI on
7486 00:58:50.030292 ==
7487 00:58:50.033238 Dram Type= 6, Freq= 0, CH_0, rank 0
7488 00:58:50.036650 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7489 00:58:50.039945 ==
7490 00:58:50.040020
7491 00:58:50.040079
7492 00:58:50.040133 TX Vref Scan disable
7493 00:58:50.043387 == TX Byte 0 ==
7494 00:58:50.046853 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7495 00:58:50.049935 == TX Byte 1 ==
7496 00:58:50.053198 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7497 00:58:50.056888 DramC Write-DBI off
7498 00:58:50.056965
7499 00:58:50.057025 [DATLAT]
7500 00:58:50.057079 Freq=1600, CH0 RK0
7501 00:58:50.057131
7502 00:58:50.059872 DATLAT Default: 0xf
7503 00:58:50.059949 0, 0xFFFF, sum = 0
7504 00:58:50.063539 1, 0xFFFF, sum = 0
7505 00:58:50.066584 2, 0xFFFF, sum = 0
7506 00:58:50.066661 3, 0xFFFF, sum = 0
7507 00:58:50.070032 4, 0xFFFF, sum = 0
7508 00:58:50.070134 5, 0xFFFF, sum = 0
7509 00:58:50.073575 6, 0xFFFF, sum = 0
7510 00:58:50.073652 7, 0xFFFF, sum = 0
7511 00:58:50.076480 8, 0xFFFF, sum = 0
7512 00:58:50.076558 9, 0xFFFF, sum = 0
7513 00:58:50.079954 10, 0xFFFF, sum = 0
7514 00:58:50.080033 11, 0xFFFF, sum = 0
7515 00:58:50.083333 12, 0xBFF, sum = 0
7516 00:58:50.083410 13, 0x0, sum = 1
7517 00:58:50.086562 14, 0x0, sum = 2
7518 00:58:50.086639 15, 0x0, sum = 3
7519 00:58:50.089971 16, 0x0, sum = 4
7520 00:58:50.090048 best_step = 14
7521 00:58:50.090108
7522 00:58:50.090163 ==
7523 00:58:50.093317 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 00:58:50.096918 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7525 00:58:50.096995 ==
7526 00:58:50.099971 RX Vref Scan: 1
7527 00:58:50.100046
7528 00:58:50.103219 Set Vref Range= 24 -> 127
7529 00:58:50.103295
7530 00:58:50.103353 RX Vref 24 -> 127, step: 1
7531 00:58:50.106654
7532 00:58:50.106729 RX Delay 11 -> 252, step: 4
7533 00:58:50.106788
7534 00:58:50.110122 Set Vref, RX VrefLevel [Byte0]: 24
7535 00:58:50.113222 [Byte1]: 24
7536 00:58:50.116826
7537 00:58:50.116903 Set Vref, RX VrefLevel [Byte0]: 25
7538 00:58:50.120205 [Byte1]: 25
7539 00:58:50.124500
7540 00:58:50.124576 Set Vref, RX VrefLevel [Byte0]: 26
7541 00:58:50.127738 [Byte1]: 26
7542 00:58:50.131866
7543 00:58:50.131944 Set Vref, RX VrefLevel [Byte0]: 27
7544 00:58:50.135191 [Byte1]: 27
7545 00:58:50.139508
7546 00:58:50.139585 Set Vref, RX VrefLevel [Byte0]: 28
7547 00:58:50.142902 [Byte1]: 28
7548 00:58:50.147096
7549 00:58:50.147171 Set Vref, RX VrefLevel [Byte0]: 29
7550 00:58:50.150526 [Byte1]: 29
7551 00:58:50.154766
7552 00:58:50.154841 Set Vref, RX VrefLevel [Byte0]: 30
7553 00:58:50.158188 [Byte1]: 30
7554 00:58:50.162417
7555 00:58:50.162494 Set Vref, RX VrefLevel [Byte0]: 31
7556 00:58:50.165662 [Byte1]: 31
7557 00:58:50.169871
7558 00:58:50.169970 Set Vref, RX VrefLevel [Byte0]: 32
7559 00:58:50.173207 [Byte1]: 32
7560 00:58:50.177602
7561 00:58:50.177679 Set Vref, RX VrefLevel [Byte0]: 33
7562 00:58:50.180948 [Byte1]: 33
7563 00:58:50.185371
7564 00:58:50.185446 Set Vref, RX VrefLevel [Byte0]: 34
7565 00:58:50.188574 [Byte1]: 34
7566 00:58:50.192824
7567 00:58:50.192901 Set Vref, RX VrefLevel [Byte0]: 35
7568 00:58:50.196117 [Byte1]: 35
7569 00:58:50.200444
7570 00:58:50.200521 Set Vref, RX VrefLevel [Byte0]: 36
7571 00:58:50.203691 [Byte1]: 36
7572 00:58:50.208328
7573 00:58:50.208436 Set Vref, RX VrefLevel [Byte0]: 37
7574 00:58:50.211492 [Byte1]: 37
7575 00:58:50.215915
7576 00:58:50.215991 Set Vref, RX VrefLevel [Byte0]: 38
7577 00:58:50.219024 [Byte1]: 38
7578 00:58:50.223217
7579 00:58:50.223293 Set Vref, RX VrefLevel [Byte0]: 39
7580 00:58:50.226629 [Byte1]: 39
7581 00:58:50.230850
7582 00:58:50.230927 Set Vref, RX VrefLevel [Byte0]: 40
7583 00:58:50.234179 [Byte1]: 40
7584 00:58:50.238438
7585 00:58:50.238516 Set Vref, RX VrefLevel [Byte0]: 41
7586 00:58:50.241877 [Byte1]: 41
7587 00:58:50.246123
7588 00:58:50.246253 Set Vref, RX VrefLevel [Byte0]: 42
7589 00:58:50.249484 [Byte1]: 42
7590 00:58:50.253730
7591 00:58:50.253806 Set Vref, RX VrefLevel [Byte0]: 43
7592 00:58:50.257060 [Byte1]: 43
7593 00:58:50.261241
7594 00:58:50.261318 Set Vref, RX VrefLevel [Byte0]: 44
7595 00:58:50.264526 [Byte1]: 44
7596 00:58:50.269065
7597 00:58:50.269147 Set Vref, RX VrefLevel [Byte0]: 45
7598 00:58:50.272211 [Byte1]: 45
7599 00:58:50.276597
7600 00:58:50.276678 Set Vref, RX VrefLevel [Byte0]: 46
7601 00:58:50.279761 [Byte1]: 46
7602 00:58:50.284223
7603 00:58:50.284303 Set Vref, RX VrefLevel [Byte0]: 47
7604 00:58:50.287745 [Byte1]: 47
7605 00:58:50.291669
7606 00:58:50.291750 Set Vref, RX VrefLevel [Byte0]: 48
7607 00:58:50.294997 [Byte1]: 48
7608 00:58:50.299392
7609 00:58:50.299470 Set Vref, RX VrefLevel [Byte0]: 49
7610 00:58:50.302611 [Byte1]: 49
7611 00:58:50.306838
7612 00:58:50.306916 Set Vref, RX VrefLevel [Byte0]: 50
7613 00:58:50.310121 [Byte1]: 50
7614 00:58:50.314455
7615 00:58:50.314533 Set Vref, RX VrefLevel [Byte0]: 51
7616 00:58:50.321097 [Byte1]: 51
7617 00:58:50.321220
7618 00:58:50.324540 Set Vref, RX VrefLevel [Byte0]: 52
7619 00:58:50.327709 [Byte1]: 52
7620 00:58:50.327786
7621 00:58:50.331051 Set Vref, RX VrefLevel [Byte0]: 53
7622 00:58:50.334163 [Byte1]: 53
7623 00:58:50.334278
7624 00:58:50.337616 Set Vref, RX VrefLevel [Byte0]: 54
7625 00:58:50.340843 [Byte1]: 54
7626 00:58:50.344991
7627 00:58:50.345068 Set Vref, RX VrefLevel [Byte0]: 55
7628 00:58:50.348366 [Byte1]: 55
7629 00:58:50.352650
7630 00:58:50.352727 Set Vref, RX VrefLevel [Byte0]: 56
7631 00:58:50.356096 [Byte1]: 56
7632 00:58:50.360553
7633 00:58:50.360633 Set Vref, RX VrefLevel [Byte0]: 57
7634 00:58:50.363483 [Byte1]: 57
7635 00:58:50.367857
7636 00:58:50.367935 Set Vref, RX VrefLevel [Byte0]: 58
7637 00:58:50.371074 [Byte1]: 58
7638 00:58:50.375382
7639 00:58:50.375459 Set Vref, RX VrefLevel [Byte0]: 59
7640 00:58:50.379023 [Byte1]: 59
7641 00:58:50.383508
7642 00:58:50.383590 Set Vref, RX VrefLevel [Byte0]: 60
7643 00:58:50.386477 [Byte1]: 60
7644 00:58:50.390662
7645 00:58:50.390740 Set Vref, RX VrefLevel [Byte0]: 61
7646 00:58:50.394065 [Byte1]: 61
7647 00:58:50.398214
7648 00:58:50.398323 Set Vref, RX VrefLevel [Byte0]: 62
7649 00:58:50.401469 [Byte1]: 62
7650 00:58:50.405868
7651 00:58:50.405946 Set Vref, RX VrefLevel [Byte0]: 63
7652 00:58:50.409578 [Byte1]: 63
7653 00:58:50.413722
7654 00:58:50.413799 Set Vref, RX VrefLevel [Byte0]: 64
7655 00:58:50.417206 [Byte1]: 64
7656 00:58:50.421189
7657 00:58:50.421266 Set Vref, RX VrefLevel [Byte0]: 65
7658 00:58:50.424369 [Byte1]: 65
7659 00:58:50.428753
7660 00:58:50.428831 Set Vref, RX VrefLevel [Byte0]: 66
7661 00:58:50.432012 [Byte1]: 66
7662 00:58:50.436589
7663 00:58:50.436666 Set Vref, RX VrefLevel [Byte0]: 67
7664 00:58:50.439651 [Byte1]: 67
7665 00:58:50.443976
7666 00:58:50.444053 Set Vref, RX VrefLevel [Byte0]: 68
7667 00:58:50.447336 [Byte1]: 68
7668 00:58:50.451574
7669 00:58:50.451651 Set Vref, RX VrefLevel [Byte0]: 69
7670 00:58:50.454934 [Byte1]: 69
7671 00:58:50.459219
7672 00:58:50.459296 Set Vref, RX VrefLevel [Byte0]: 70
7673 00:58:50.462504 [Byte1]: 70
7674 00:58:50.466933
7675 00:58:50.467015 Final RX Vref Byte 0 = 57 to rank0
7676 00:58:50.470112 Final RX Vref Byte 1 = 56 to rank0
7677 00:58:50.473469 Final RX Vref Byte 0 = 57 to rank1
7678 00:58:50.476825 Final RX Vref Byte 1 = 56 to rank1==
7679 00:58:50.480265 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 00:58:50.486659 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7681 00:58:50.486739 ==
7682 00:58:50.486799 DQS Delay:
7683 00:58:50.489852 DQS0 = 0, DQS1 = 0
7684 00:58:50.489929 DQM Delay:
7685 00:58:50.489989 DQM0 = 127, DQM1 = 121
7686 00:58:50.493459 DQ Delay:
7687 00:58:50.496720 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =124
7688 00:58:50.499843 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =136
7689 00:58:50.503120 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7690 00:58:50.506604 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7691 00:58:50.506681
7692 00:58:50.506741
7693 00:58:50.506796
7694 00:58:50.509827 [DramC_TX_OE_Calibration] TA2
7695 00:58:50.513142 Original DQ_B0 (3 6) =30, OEN = 27
7696 00:58:50.516666 Original DQ_B1 (3 6) =30, OEN = 27
7697 00:58:50.519878 24, 0x0, End_B0=24 End_B1=24
7698 00:58:50.519957 25, 0x0, End_B0=25 End_B1=25
7699 00:58:50.523336 26, 0x0, End_B0=26 End_B1=26
7700 00:58:50.526419 27, 0x0, End_B0=27 End_B1=27
7701 00:58:50.529652 28, 0x0, End_B0=28 End_B1=28
7702 00:58:50.533039 29, 0x0, End_B0=29 End_B1=29
7703 00:58:50.533117 30, 0x0, End_B0=30 End_B1=30
7704 00:58:50.536360 31, 0x4141, End_B0=30 End_B1=30
7705 00:58:50.539591 Byte0 end_step=30 best_step=27
7706 00:58:50.543216 Byte1 end_step=30 best_step=27
7707 00:58:50.546222 Byte0 TX OE(2T, 0.5T) = (3, 3)
7708 00:58:50.549573 Byte1 TX OE(2T, 0.5T) = (3, 3)
7709 00:58:50.549649
7710 00:58:50.549707
7711 00:58:50.556446 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7712 00:58:50.559259 CH0 RK0: MR19=303, MR18=1D1D
7713 00:58:50.566131 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7714 00:58:50.566299
7715 00:58:50.569130 ----->DramcWriteLeveling(PI) begin...
7716 00:58:50.569210 ==
7717 00:58:50.572678 Dram Type= 6, Freq= 0, CH_0, rank 1
7718 00:58:50.575934 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7719 00:58:50.576012 ==
7720 00:58:50.579074 Write leveling (Byte 0): 29 => 29
7721 00:58:50.582543 Write leveling (Byte 1): 26 => 26
7722 00:58:50.586135 DramcWriteLeveling(PI) end<-----
7723 00:58:50.586218
7724 00:58:50.586311 ==
7725 00:58:50.589180 Dram Type= 6, Freq= 0, CH_0, rank 1
7726 00:58:50.592707 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7727 00:58:50.592785 ==
7728 00:58:50.595940 [Gating] SW mode calibration
7729 00:58:50.602694 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7730 00:58:50.609066 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7731 00:58:50.612542 0 12 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7732 00:58:50.619113 0 12 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7733 00:58:50.622334 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 00:58:50.625739 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 00:58:50.632497 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7736 00:58:50.635511 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7737 00:58:50.639009 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7738 00:58:50.645614 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7739 00:58:50.648944 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7740 00:58:50.652160 0 13 4 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
7741 00:58:50.658790 0 13 8 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
7742 00:58:50.662086 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 00:58:50.665505 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7744 00:58:50.672192 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7745 00:58:50.675424 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7746 00:58:50.678778 0 13 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7747 00:58:50.681993 0 14 0 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
7748 00:58:50.688685 0 14 4 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7749 00:58:50.691922 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 00:58:50.695674 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 00:58:50.701958 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7752 00:58:50.705477 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7753 00:58:50.708716 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7754 00:58:50.715597 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7755 00:58:50.718694 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7756 00:58:50.722223 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7757 00:58:50.728640 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7758 00:58:50.731871 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 00:58:50.735435 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 00:58:50.741868 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 00:58:50.745340 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 00:58:50.748480 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 00:58:50.755241 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 00:58:50.758478 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 00:58:50.761652 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 00:58:50.768322 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 00:58:50.771864 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 00:58:50.774947 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 00:58:50.781779 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 00:58:50.785238 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7771 00:58:50.788256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7772 00:58:50.794976 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7773 00:58:50.795053 Total UI for P1: 0, mck2ui 16
7774 00:58:50.801496 best dqsien dly found for B0: ( 1, 0, 30)
7775 00:58:50.805005 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7776 00:58:50.808330 Total UI for P1: 0, mck2ui 16
7777 00:58:50.811540 best dqsien dly found for B1: ( 1, 1, 4)
7778 00:58:50.814839 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7779 00:58:50.818374 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7780 00:58:50.818450
7781 00:58:50.821534 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7782 00:58:50.824768 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7783 00:58:50.828190 [Gating] SW calibration Done
7784 00:58:50.828266 ==
7785 00:58:50.831476 Dram Type= 6, Freq= 0, CH_0, rank 1
7786 00:58:50.834842 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7787 00:58:50.834919 ==
7788 00:58:50.838371 RX Vref Scan: 0
7789 00:58:50.838447
7790 00:58:50.841352 RX Vref 0 -> 0, step: 1
7791 00:58:50.841428
7792 00:58:50.841488 RX Delay 0 -> 252, step: 8
7793 00:58:50.847984 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7794 00:58:50.851191 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7795 00:58:50.854640 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7796 00:58:50.857793 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7797 00:58:50.861148 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7798 00:58:50.867702 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7799 00:58:50.871024 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7800 00:58:50.874584 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7801 00:58:50.877859 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7802 00:58:50.880891 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7803 00:58:50.887560 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7804 00:58:50.890745 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7805 00:58:50.894047 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7806 00:58:50.897308 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7807 00:58:50.904086 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7808 00:58:50.907661 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7809 00:58:50.907738 ==
7810 00:58:50.910605 Dram Type= 6, Freq= 0, CH_0, rank 1
7811 00:58:50.913885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7812 00:58:50.913962 ==
7813 00:58:50.914022 DQS Delay:
7814 00:58:50.917172 DQS0 = 0, DQS1 = 0
7815 00:58:50.917248 DQM Delay:
7816 00:58:50.920644 DQM0 = 131, DQM1 = 124
7817 00:58:50.920719 DQ Delay:
7818 00:58:50.923845 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7819 00:58:50.927139 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7820 00:58:50.930545 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7821 00:58:50.936948 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7822 00:58:50.937024
7823 00:58:50.937082
7824 00:58:50.937137 ==
7825 00:58:50.940343 Dram Type= 6, Freq= 0, CH_0, rank 1
7826 00:58:50.943802 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7827 00:58:50.943878 ==
7828 00:58:50.943937
7829 00:58:50.943991
7830 00:58:50.947027 TX Vref Scan disable
7831 00:58:50.947103 == TX Byte 0 ==
7832 00:58:50.953726 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7833 00:58:50.957065 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7834 00:58:50.957140 == TX Byte 1 ==
7835 00:58:50.963638 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7836 00:58:50.966893 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7837 00:58:50.967024 ==
7838 00:58:50.970317 Dram Type= 6, Freq= 0, CH_0, rank 1
7839 00:58:50.973530 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7840 00:58:50.973605 ==
7841 00:58:50.988444
7842 00:58:50.991763 TX Vref early break, caculate TX vref
7843 00:58:50.995149 TX Vref=16, minBit 8, minWin=22, winSum=372
7844 00:58:50.998485 TX Vref=18, minBit 1, minWin=22, winSum=382
7845 00:58:51.001592 TX Vref=20, minBit 8, minWin=23, winSum=389
7846 00:58:51.005138 TX Vref=22, minBit 8, minWin=24, winSum=400
7847 00:58:51.008186 TX Vref=24, minBit 8, minWin=24, winSum=406
7848 00:58:51.015261 TX Vref=26, minBit 8, minWin=24, winSum=409
7849 00:58:51.018357 TX Vref=28, minBit 8, minWin=24, winSum=412
7850 00:58:51.021673 TX Vref=30, minBit 7, minWin=24, winSum=408
7851 00:58:51.025133 TX Vref=32, minBit 1, minWin=24, winSum=399
7852 00:58:51.028352 TX Vref=34, minBit 8, minWin=23, winSum=391
7853 00:58:51.031627 TX Vref=36, minBit 8, minWin=23, winSum=388
7854 00:58:51.038510 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 28
7855 00:58:51.038586
7856 00:58:51.041652 Final TX Range 0 Vref 28
7857 00:58:51.041727
7858 00:58:51.041785 ==
7859 00:58:51.044833 Dram Type= 6, Freq= 0, CH_0, rank 1
7860 00:58:51.048082 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7861 00:58:51.048158 ==
7862 00:58:51.048217
7863 00:58:51.048270
7864 00:58:51.051559 TX Vref Scan disable
7865 00:58:51.058100 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7866 00:58:51.058176 == TX Byte 0 ==
7867 00:58:51.061529 u2DelayCellOfst[0]=10 cells (3 PI)
7868 00:58:51.064754 u2DelayCellOfst[1]=18 cells (5 PI)
7869 00:58:51.068389 u2DelayCellOfst[2]=14 cells (4 PI)
7870 00:58:51.071456 u2DelayCellOfst[3]=14 cells (4 PI)
7871 00:58:51.075092 u2DelayCellOfst[4]=10 cells (3 PI)
7872 00:58:51.077911 u2DelayCellOfst[5]=0 cells (0 PI)
7873 00:58:51.081289 u2DelayCellOfst[6]=18 cells (5 PI)
7874 00:58:51.084861 u2DelayCellOfst[7]=18 cells (5 PI)
7875 00:58:51.087918 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7876 00:58:51.091324 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7877 00:58:51.094632 == TX Byte 1 ==
7878 00:58:51.097817 u2DelayCellOfst[8]=0 cells (0 PI)
7879 00:58:51.101254 u2DelayCellOfst[9]=0 cells (0 PI)
7880 00:58:51.101330 u2DelayCellOfst[10]=7 cells (2 PI)
7881 00:58:51.104416 u2DelayCellOfst[11]=3 cells (1 PI)
7882 00:58:51.108002 u2DelayCellOfst[12]=14 cells (4 PI)
7883 00:58:51.111227 u2DelayCellOfst[13]=14 cells (4 PI)
7884 00:58:51.114487 u2DelayCellOfst[14]=18 cells (5 PI)
7885 00:58:51.118480 u2DelayCellOfst[15]=14 cells (4 PI)
7886 00:58:51.125355 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7887 00:58:51.128149 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7888 00:58:51.128481 DramC Write-DBI on
7889 00:58:51.128721 ==
7890 00:58:51.131409 Dram Type= 6, Freq= 0, CH_0, rank 1
7891 00:58:51.137948 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7892 00:58:51.138126 ==
7893 00:58:51.138282
7894 00:58:51.138413
7895 00:58:51.138535 TX Vref Scan disable
7896 00:58:51.141798 == TX Byte 0 ==
7897 00:58:51.145230 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7898 00:58:51.148643 == TX Byte 1 ==
7899 00:58:51.151907 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7900 00:58:51.155111 DramC Write-DBI off
7901 00:58:51.155220
7902 00:58:51.155303 [DATLAT]
7903 00:58:51.155382 Freq=1600, CH0 RK1
7904 00:58:51.155458
7905 00:58:51.158536 DATLAT Default: 0xe
7906 00:58:51.158632 0, 0xFFFF, sum = 0
7907 00:58:51.161710 1, 0xFFFF, sum = 0
7908 00:58:51.164993 2, 0xFFFF, sum = 0
7909 00:58:51.165082 3, 0xFFFF, sum = 0
7910 00:58:51.168345 4, 0xFFFF, sum = 0
7911 00:58:51.168425 5, 0xFFFF, sum = 0
7912 00:58:51.171479 6, 0xFFFF, sum = 0
7913 00:58:51.171560 7, 0xFFFF, sum = 0
7914 00:58:51.175085 8, 0xFFFF, sum = 0
7915 00:58:51.175162 9, 0xFFFF, sum = 0
7916 00:58:51.178137 10, 0xFFFF, sum = 0
7917 00:58:51.178220 11, 0xFFFF, sum = 0
7918 00:58:51.181753 12, 0xFFF, sum = 0
7919 00:58:51.181829 13, 0x0, sum = 1
7920 00:58:51.185281 14, 0x0, sum = 2
7921 00:58:51.185358 15, 0x0, sum = 3
7922 00:58:51.188219 16, 0x0, sum = 4
7923 00:58:51.188297 best_step = 14
7924 00:58:51.188356
7925 00:58:51.188410 ==
7926 00:58:51.191410 Dram Type= 6, Freq= 0, CH_0, rank 1
7927 00:58:51.194817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7928 00:58:51.198161 ==
7929 00:58:51.198277 RX Vref Scan: 0
7930 00:58:51.198337
7931 00:58:51.201503 RX Vref 0 -> 0, step: 1
7932 00:58:51.201578
7933 00:58:51.201647 RX Delay 11 -> 252, step: 4
7934 00:58:51.208809 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7935 00:58:51.212022 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
7936 00:58:51.215366 iDelay=195, Bit 2, Center 128 (75 ~ 182) 108
7937 00:58:51.218718 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7938 00:58:51.222054 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7939 00:58:51.228594 iDelay=195, Bit 5, Center 118 (67 ~ 170) 104
7940 00:58:51.231980 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7941 00:58:51.235238 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7942 00:58:51.238615 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7943 00:58:51.242136 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7944 00:58:51.248470 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7945 00:58:51.251821 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7946 00:58:51.254964 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7947 00:58:51.258358 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7948 00:58:51.264859 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
7949 00:58:51.268462 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7950 00:58:51.268538 ==
7951 00:58:51.271801 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 00:58:51.274997 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7953 00:58:51.275074 ==
7954 00:58:51.278359 DQS Delay:
7955 00:58:51.278435 DQS0 = 0, DQS1 = 0
7956 00:58:51.278493 DQM Delay:
7957 00:58:51.281621 DQM0 = 128, DQM1 = 120
7958 00:58:51.281696 DQ Delay:
7959 00:58:51.285055 DQ0 =124, DQ1 =132, DQ2 =128, DQ3 =122
7960 00:58:51.288195 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7961 00:58:51.291467 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7962 00:58:51.298335 DQ12 =126, DQ13 =128, DQ14 =130, DQ15 =130
7963 00:58:51.298410
7964 00:58:51.298468
7965 00:58:51.298522
7966 00:58:51.301303 [DramC_TX_OE_Calibration] TA2
7967 00:58:51.304895 Original DQ_B0 (3 6) =30, OEN = 27
7968 00:58:51.304971 Original DQ_B1 (3 6) =30, OEN = 27
7969 00:58:51.307965 24, 0x0, End_B0=24 End_B1=24
7970 00:58:51.311274 25, 0x0, End_B0=25 End_B1=25
7971 00:58:51.314725 26, 0x0, End_B0=26 End_B1=26
7972 00:58:51.317940 27, 0x0, End_B0=27 End_B1=27
7973 00:58:51.318017 28, 0x0, End_B0=28 End_B1=28
7974 00:58:51.321356 29, 0x0, End_B0=29 End_B1=29
7975 00:58:51.324647 30, 0x0, End_B0=30 End_B1=30
7976 00:58:51.328033 31, 0x4141, End_B0=30 End_B1=30
7977 00:58:51.331330 Byte0 end_step=30 best_step=27
7978 00:58:51.331411 Byte1 end_step=30 best_step=27
7979 00:58:51.334578 Byte0 TX OE(2T, 0.5T) = (3, 3)
7980 00:58:51.337857 Byte1 TX OE(2T, 0.5T) = (3, 3)
7981 00:58:51.337933
7982 00:58:51.337992
7983 00:58:51.348193 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
7984 00:58:51.348270 CH0 RK1: MR19=303, MR18=2525
7985 00:58:51.354684 CH0_RK1: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
7986 00:58:51.357799 [RxdqsGatingPostProcess] freq 1600
7987 00:58:51.364566 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7988 00:58:51.367778 Pre-setting of DQS Precalculation
7989 00:58:51.371033 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7990 00:58:51.371109 ==
7991 00:58:51.374422 Dram Type= 6, Freq= 0, CH_1, rank 0
7992 00:58:51.381217 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7993 00:58:51.381295 ==
7994 00:58:51.384294 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7995 00:58:51.390922 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7996 00:58:51.394375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7997 00:58:51.400762 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7998 00:58:51.407757 [CA 0] Center 41 (11~71) winsize 61
7999 00:58:51.411044 [CA 1] Center 41 (10~72) winsize 63
8000 00:58:51.414384 [CA 2] Center 37 (7~67) winsize 61
8001 00:58:51.417708 [CA 3] Center 36 (7~66) winsize 60
8002 00:58:51.420939 [CA 4] Center 34 (4~64) winsize 61
8003 00:58:51.424604 [CA 5] Center 34 (5~64) winsize 60
8004 00:58:51.424680
8005 00:58:51.427608 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8006 00:58:51.427684
8007 00:58:51.431214 [CATrainingPosCal] consider 1 rank data
8008 00:58:51.434173 u2DelayCellTimex100 = 271/100 ps
8009 00:58:51.437654 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8010 00:58:51.444505 CA1 delay=41 (10~72),Diff = 7 PI (25 cell)
8011 00:58:51.447429 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8012 00:58:51.450832 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8013 00:58:51.454184 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8014 00:58:51.457424 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8015 00:58:51.457504
8016 00:58:51.460843 CA PerBit enable=1, Macro0, CA PI delay=34
8017 00:58:51.460918
8018 00:58:51.463951 [CBTSetCACLKResult] CA Dly = 34
8019 00:58:51.467316 CS Dly: 8 (0~39)
8020 00:58:51.470717 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8021 00:58:51.473891 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8022 00:58:51.473967 ==
8023 00:58:51.477268 Dram Type= 6, Freq= 0, CH_1, rank 1
8024 00:58:51.480736 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8025 00:58:51.483968 ==
8026 00:58:51.487260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8027 00:58:51.490544 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8028 00:58:51.497243 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8029 00:58:51.503530 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8030 00:58:51.510154 [CA 0] Center 41 (12~71) winsize 60
8031 00:58:51.513490 [CA 1] Center 41 (11~71) winsize 61
8032 00:58:51.516859 [CA 2] Center 36 (7~66) winsize 60
8033 00:58:51.520160 [CA 3] Center 36 (7~65) winsize 59
8034 00:58:51.523418 [CA 4] Center 34 (5~64) winsize 60
8035 00:58:51.526632 [CA 5] Center 34 (5~64) winsize 60
8036 00:58:51.526729
8037 00:58:51.530043 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8038 00:58:51.530140
8039 00:58:51.533393 [CATrainingPosCal] consider 2 rank data
8040 00:58:51.536760 u2DelayCellTimex100 = 271/100 ps
8041 00:58:51.539937 CA0 delay=41 (12~71),Diff = 7 PI (25 cell)
8042 00:58:51.546709 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8043 00:58:51.550043 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8044 00:58:51.553499 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8045 00:58:51.556583 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8046 00:58:51.559931 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8047 00:58:51.560029
8048 00:58:51.563309 CA PerBit enable=1, Macro0, CA PI delay=34
8049 00:58:51.563408
8050 00:58:51.566627 [CBTSetCACLKResult] CA Dly = 34
8051 00:58:51.569857 CS Dly: 9 (0~41)
8052 00:58:51.573331 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8053 00:58:51.576328 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8054 00:58:51.576421
8055 00:58:51.579765 ----->DramcWriteLeveling(PI) begin...
8056 00:58:51.579866 ==
8057 00:58:51.582962 Dram Type= 6, Freq= 0, CH_1, rank 0
8058 00:58:51.589688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8059 00:58:51.589788 ==
8060 00:58:51.592821 Write leveling (Byte 0): 22 => 22
8061 00:58:51.592918 Write leveling (Byte 1): 22 => 22
8062 00:58:51.596107 DramcWriteLeveling(PI) end<-----
8063 00:58:51.596204
8064 00:58:51.599421 ==
8065 00:58:51.599502 Dram Type= 6, Freq= 0, CH_1, rank 0
8066 00:58:51.606257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8067 00:58:51.606335 ==
8068 00:58:51.609455 [Gating] SW mode calibration
8069 00:58:51.616249 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8070 00:58:51.619432 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8071 00:58:51.626092 0 12 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
8072 00:58:51.629636 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 00:58:51.632666 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 00:58:51.639182 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 00:58:51.642556 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 00:58:51.645734 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 00:58:51.652592 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8078 00:58:51.655679 0 12 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
8079 00:58:51.659304 0 13 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8080 00:58:51.665611 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8081 00:58:51.669039 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 00:58:51.672293 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 00:58:51.679031 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 00:58:51.682304 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 00:58:51.685584 0 13 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8086 00:58:51.692198 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8087 00:58:51.695735 0 14 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8088 00:58:51.698656 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 00:58:51.705057 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 00:58:51.708536 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 00:58:51.711907 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 00:58:51.718461 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 00:58:51.721655 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 00:58:51.725030 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 00:58:51.731880 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8096 00:58:51.734879 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8097 00:58:51.738006 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 00:58:51.744667 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 00:58:51.748152 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 00:58:51.751237 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 00:58:51.757940 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 00:58:51.761271 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 00:58:51.764491 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 00:58:51.771053 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 00:58:51.774205 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 00:58:51.777673 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 00:58:51.784194 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 00:58:51.787612 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 00:58:51.791045 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8110 00:58:51.797508 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8111 00:58:51.800802 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8112 00:58:51.803973 Total UI for P1: 0, mck2ui 16
8113 00:58:51.807211 best dqsien dly found for B0: ( 1, 0, 26)
8114 00:58:51.810613 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 00:58:51.813838 Total UI for P1: 0, mck2ui 16
8116 00:58:51.817135 best dqsien dly found for B1: ( 1, 1, 0)
8117 00:58:51.820503 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8118 00:58:51.823884 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8119 00:58:51.823969
8120 00:58:51.830391 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8121 00:58:51.833752 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8122 00:58:51.833828 [Gating] SW calibration Done
8123 00:58:51.837141 ==
8124 00:58:51.840261 Dram Type= 6, Freq= 0, CH_1, rank 0
8125 00:58:51.843628 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8126 00:58:51.843704 ==
8127 00:58:51.843764 RX Vref Scan: 0
8128 00:58:51.843820
8129 00:58:51.846880 RX Vref 0 -> 0, step: 1
8130 00:58:51.846956
8131 00:58:51.850184 RX Delay 0 -> 252, step: 8
8132 00:58:51.853682 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8133 00:58:51.857084 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8134 00:58:51.860233 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8135 00:58:51.867299 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8136 00:58:51.870049 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8137 00:58:51.873282 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8138 00:58:51.876613 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8139 00:58:51.880050 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8140 00:58:51.886772 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8141 00:58:51.889742 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8142 00:58:51.893315 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8143 00:58:51.896345 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8144 00:58:51.903031 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8145 00:58:51.906522 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8146 00:58:51.909729 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8147 00:58:51.913239 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8148 00:58:51.913315 ==
8149 00:58:51.916206 Dram Type= 6, Freq= 0, CH_1, rank 0
8150 00:58:51.922973 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8151 00:58:51.923049 ==
8152 00:58:51.923109 DQS Delay:
8153 00:58:51.923163 DQS0 = 0, DQS1 = 0
8154 00:58:51.926201 DQM Delay:
8155 00:58:51.926307 DQM0 = 130, DQM1 = 124
8156 00:58:51.929482 DQ Delay:
8157 00:58:51.932677 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8158 00:58:51.936082 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8159 00:58:51.939391 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8160 00:58:51.942658 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8161 00:58:51.942734
8162 00:58:51.942793
8163 00:58:51.942846 ==
8164 00:58:51.946062 Dram Type= 6, Freq= 0, CH_1, rank 0
8165 00:58:51.949275 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8166 00:58:51.952668 ==
8167 00:58:51.952765
8168 00:58:51.952849
8169 00:58:51.952929 TX Vref Scan disable
8170 00:58:51.955739 == TX Byte 0 ==
8171 00:58:51.959323 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8172 00:58:51.962566 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8173 00:58:51.965727 == TX Byte 1 ==
8174 00:58:51.969135 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8175 00:58:51.972474 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8176 00:58:51.975729 ==
8177 00:58:51.975825 Dram Type= 6, Freq= 0, CH_1, rank 0
8178 00:58:51.982204 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8179 00:58:51.982339 ==
8180 00:58:51.993849
8181 00:58:51.997150 TX Vref early break, caculate TX vref
8182 00:58:52.000709 TX Vref=16, minBit 1, minWin=21, winSum=365
8183 00:58:52.004059 TX Vref=18, minBit 3, minWin=22, winSum=377
8184 00:58:52.007092 TX Vref=20, minBit 1, minWin=23, winSum=385
8185 00:58:52.010354 TX Vref=22, minBit 3, minWin=23, winSum=396
8186 00:58:52.013767 TX Vref=24, minBit 0, minWin=24, winSum=402
8187 00:58:52.020487 TX Vref=26, minBit 3, minWin=24, winSum=409
8188 00:58:52.023795 TX Vref=28, minBit 3, minWin=24, winSum=414
8189 00:58:52.026987 TX Vref=30, minBit 3, minWin=23, winSum=404
8190 00:58:52.030335 TX Vref=32, minBit 3, minWin=23, winSum=395
8191 00:58:52.033429 TX Vref=34, minBit 0, minWin=23, winSum=387
8192 00:58:52.040250 [TxChooseVref] Worse bit 3, Min win 24, Win sum 414, Final Vref 28
8193 00:58:52.040350
8194 00:58:52.043451 Final TX Range 0 Vref 28
8195 00:58:52.043548
8196 00:58:52.043631 ==
8197 00:58:52.046709 Dram Type= 6, Freq= 0, CH_1, rank 0
8198 00:58:52.050189 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8199 00:58:52.050322 ==
8200 00:58:52.050406
8201 00:58:52.050487
8202 00:58:52.053408 TX Vref Scan disable
8203 00:58:52.060102 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8204 00:58:52.060199 == TX Byte 0 ==
8205 00:58:52.063624 u2DelayCellOfst[0]=18 cells (5 PI)
8206 00:58:52.066775 u2DelayCellOfst[1]=14 cells (4 PI)
8207 00:58:52.070142 u2DelayCellOfst[2]=0 cells (0 PI)
8208 00:58:52.073609 u2DelayCellOfst[3]=7 cells (2 PI)
8209 00:58:52.076597 u2DelayCellOfst[4]=10 cells (3 PI)
8210 00:58:52.079797 u2DelayCellOfst[5]=18 cells (5 PI)
8211 00:58:52.083234 u2DelayCellOfst[6]=18 cells (5 PI)
8212 00:58:52.086638 u2DelayCellOfst[7]=10 cells (3 PI)
8213 00:58:52.089820 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8214 00:58:52.093092 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8215 00:58:52.096644 == TX Byte 1 ==
8216 00:58:52.096739 u2DelayCellOfst[8]=0 cells (0 PI)
8217 00:58:52.099865 u2DelayCellOfst[9]=3 cells (1 PI)
8218 00:58:52.103035 u2DelayCellOfst[10]=10 cells (3 PI)
8219 00:58:52.106369 u2DelayCellOfst[11]=3 cells (1 PI)
8220 00:58:52.109887 u2DelayCellOfst[12]=18 cells (5 PI)
8221 00:58:52.113214 u2DelayCellOfst[13]=21 cells (6 PI)
8222 00:58:52.116330 u2DelayCellOfst[14]=21 cells (6 PI)
8223 00:58:52.119647 u2DelayCellOfst[15]=18 cells (5 PI)
8224 00:58:52.122912 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8225 00:58:52.129536 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8226 00:58:52.129634 DramC Write-DBI on
8227 00:58:52.129718 ==
8228 00:58:52.132892 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 00:58:52.139662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8230 00:58:52.139762 ==
8231 00:58:52.139844
8232 00:58:52.139925
8233 00:58:52.140007 TX Vref Scan disable
8234 00:58:52.142964 == TX Byte 0 ==
8235 00:58:52.146319 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8236 00:58:52.149823 == TX Byte 1 ==
8237 00:58:52.152895 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8238 00:58:52.156309 DramC Write-DBI off
8239 00:58:52.156404
8240 00:58:52.156489 [DATLAT]
8241 00:58:52.156569 Freq=1600, CH1 RK0
8242 00:58:52.156648
8243 00:58:52.159577 DATLAT Default: 0xf
8244 00:58:52.162883 0, 0xFFFF, sum = 0
8245 00:58:52.162979 1, 0xFFFF, sum = 0
8246 00:58:52.166513 2, 0xFFFF, sum = 0
8247 00:58:52.166609 3, 0xFFFF, sum = 0
8248 00:58:52.169434 4, 0xFFFF, sum = 0
8249 00:58:52.169534 5, 0xFFFF, sum = 0
8250 00:58:52.172743 6, 0xFFFF, sum = 0
8251 00:58:52.172839 7, 0xFFFF, sum = 0
8252 00:58:52.176375 8, 0xFFFF, sum = 0
8253 00:58:52.176472 9, 0xFFFF, sum = 0
8254 00:58:52.179459 10, 0xFFFF, sum = 0
8255 00:58:52.179557 11, 0xFFFF, sum = 0
8256 00:58:52.182857 12, 0x8F7F, sum = 0
8257 00:58:52.182959 13, 0x0, sum = 1
8258 00:58:52.186156 14, 0x0, sum = 2
8259 00:58:52.186292 15, 0x0, sum = 3
8260 00:58:52.189604 16, 0x0, sum = 4
8261 00:58:52.189701 best_step = 14
8262 00:58:52.189785
8263 00:58:52.189864 ==
8264 00:58:52.192798 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 00:58:52.196322 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8266 00:58:52.199411 ==
8267 00:58:52.199509 RX Vref Scan: 1
8268 00:58:52.199592
8269 00:58:52.202675 Set Vref Range= 24 -> 127
8270 00:58:52.202769
8271 00:58:52.206050 RX Vref 24 -> 127, step: 1
8272 00:58:52.206142
8273 00:58:52.206244 RX Delay 3 -> 252, step: 4
8274 00:58:52.206341
8275 00:58:52.209196 Set Vref, RX VrefLevel [Byte0]: 24
8276 00:58:52.212850 [Byte1]: 24
8277 00:58:52.216751
8278 00:58:52.216846 Set Vref, RX VrefLevel [Byte0]: 25
8279 00:58:52.219598 [Byte1]: 25
8280 00:58:52.224057
8281 00:58:52.224152 Set Vref, RX VrefLevel [Byte0]: 26
8282 00:58:52.227435 [Byte1]: 26
8283 00:58:52.231743
8284 00:58:52.231839 Set Vref, RX VrefLevel [Byte0]: 27
8285 00:58:52.234986 [Byte1]: 27
8286 00:58:52.239473
8287 00:58:52.239591 Set Vref, RX VrefLevel [Byte0]: 28
8288 00:58:52.242659 [Byte1]: 28
8289 00:58:52.247137
8290 00:58:52.247232 Set Vref, RX VrefLevel [Byte0]: 29
8291 00:58:52.250306 [Byte1]: 29
8292 00:58:52.254779
8293 00:58:52.254875 Set Vref, RX VrefLevel [Byte0]: 30
8294 00:58:52.257937 [Byte1]: 30
8295 00:58:52.262437
8296 00:58:52.262589 Set Vref, RX VrefLevel [Byte0]: 31
8297 00:58:52.265470 [Byte1]: 31
8298 00:58:52.269894
8299 00:58:52.270016 Set Vref, RX VrefLevel [Byte0]: 32
8300 00:58:52.273119 [Byte1]: 32
8301 00:58:52.277563
8302 00:58:52.277658 Set Vref, RX VrefLevel [Byte0]: 33
8303 00:58:52.281007 [Byte1]: 33
8304 00:58:52.285223
8305 00:58:52.285317 Set Vref, RX VrefLevel [Byte0]: 34
8306 00:58:52.288512 [Byte1]: 34
8307 00:58:52.293058
8308 00:58:52.293133 Set Vref, RX VrefLevel [Byte0]: 35
8309 00:58:52.296526 [Byte1]: 35
8310 00:58:52.300572
8311 00:58:52.300647 Set Vref, RX VrefLevel [Byte0]: 36
8312 00:58:52.303829 [Byte1]: 36
8313 00:58:52.308414
8314 00:58:52.308490 Set Vref, RX VrefLevel [Byte0]: 37
8315 00:58:52.311571 [Byte1]: 37
8316 00:58:52.315875
8317 00:58:52.315951 Set Vref, RX VrefLevel [Byte0]: 38
8318 00:58:52.319292 [Byte1]: 38
8319 00:58:52.323584
8320 00:58:52.323660 Set Vref, RX VrefLevel [Byte0]: 39
8321 00:58:52.326877 [Byte1]: 39
8322 00:58:52.331130
8323 00:58:52.331214 Set Vref, RX VrefLevel [Byte0]: 40
8324 00:58:52.334410 [Byte1]: 40
8325 00:58:52.338812
8326 00:58:52.338887 Set Vref, RX VrefLevel [Byte0]: 41
8327 00:58:52.342167 [Byte1]: 41
8328 00:58:52.346643
8329 00:58:52.346723 Set Vref, RX VrefLevel [Byte0]: 42
8330 00:58:52.349708 [Byte1]: 42
8331 00:58:52.354178
8332 00:58:52.354298 Set Vref, RX VrefLevel [Byte0]: 43
8333 00:58:52.357415 [Byte1]: 43
8334 00:58:52.361949
8335 00:58:52.362028 Set Vref, RX VrefLevel [Byte0]: 44
8336 00:58:52.365288 [Byte1]: 44
8337 00:58:52.369454
8338 00:58:52.369530 Set Vref, RX VrefLevel [Byte0]: 45
8339 00:58:52.372884 [Byte1]: 45
8340 00:58:52.377104
8341 00:58:52.377179 Set Vref, RX VrefLevel [Byte0]: 46
8342 00:58:52.380415 [Byte1]: 46
8343 00:58:52.384799
8344 00:58:52.384874 Set Vref, RX VrefLevel [Byte0]: 47
8345 00:58:52.387908 [Byte1]: 47
8346 00:58:52.392297
8347 00:58:52.392373 Set Vref, RX VrefLevel [Byte0]: 48
8348 00:58:52.395682 [Byte1]: 48
8349 00:58:52.400195
8350 00:58:52.400271 Set Vref, RX VrefLevel [Byte0]: 49
8351 00:58:52.403261 [Byte1]: 49
8352 00:58:52.407831
8353 00:58:52.407907 Set Vref, RX VrefLevel [Byte0]: 50
8354 00:58:52.410999 [Byte1]: 50
8355 00:58:52.415344
8356 00:58:52.415419 Set Vref, RX VrefLevel [Byte0]: 51
8357 00:58:52.418800 [Byte1]: 51
8358 00:58:52.422957
8359 00:58:52.423033 Set Vref, RX VrefLevel [Byte0]: 52
8360 00:58:52.426355 [Byte1]: 52
8361 00:58:52.430830
8362 00:58:52.430907 Set Vref, RX VrefLevel [Byte0]: 53
8363 00:58:52.433933 [Byte1]: 53
8364 00:58:52.438346
8365 00:58:52.438422 Set Vref, RX VrefLevel [Byte0]: 54
8366 00:58:52.441505 [Byte1]: 54
8367 00:58:52.445915
8368 00:58:52.445991 Set Vref, RX VrefLevel [Byte0]: 55
8369 00:58:52.449448 [Byte1]: 55
8370 00:58:52.453607
8371 00:58:52.453686 Set Vref, RX VrefLevel [Byte0]: 56
8372 00:58:52.456870 [Byte1]: 56
8373 00:58:52.461183
8374 00:58:52.461260 Set Vref, RX VrefLevel [Byte0]: 57
8375 00:58:52.464625 [Byte1]: 57
8376 00:58:52.468991
8377 00:58:52.469067 Set Vref, RX VrefLevel [Byte0]: 58
8378 00:58:52.472467 [Byte1]: 58
8379 00:58:52.476547
8380 00:58:52.476623 Set Vref, RX VrefLevel [Byte0]: 59
8381 00:58:52.479918 [Byte1]: 59
8382 00:58:52.484269
8383 00:58:52.484345 Set Vref, RX VrefLevel [Byte0]: 60
8384 00:58:52.487562 [Byte1]: 60
8385 00:58:52.491889
8386 00:58:52.491964 Set Vref, RX VrefLevel [Byte0]: 61
8387 00:58:52.495268 [Byte1]: 61
8388 00:58:52.499498
8389 00:58:52.499574 Set Vref, RX VrefLevel [Byte0]: 62
8390 00:58:52.502816 [Byte1]: 62
8391 00:58:52.507097
8392 00:58:52.507194 Set Vref, RX VrefLevel [Byte0]: 63
8393 00:58:52.510510 [Byte1]: 63
8394 00:58:52.515173
8395 00:58:52.515298 Set Vref, RX VrefLevel [Byte0]: 64
8396 00:58:52.518354 [Byte1]: 64
8397 00:58:52.522463
8398 00:58:52.522565 Set Vref, RX VrefLevel [Byte0]: 65
8399 00:58:52.525795 [Byte1]: 65
8400 00:58:52.530318
8401 00:58:52.530414 Set Vref, RX VrefLevel [Byte0]: 66
8402 00:58:52.533441 [Byte1]: 66
8403 00:58:52.537781
8404 00:58:52.537878 Set Vref, RX VrefLevel [Byte0]: 67
8405 00:58:52.541028 [Byte1]: 67
8406 00:58:52.545421
8407 00:58:52.545517 Set Vref, RX VrefLevel [Byte0]: 68
8408 00:58:52.548785 [Byte1]: 68
8409 00:58:52.553113
8410 00:58:52.553209 Set Vref, RX VrefLevel [Byte0]: 69
8411 00:58:52.556287 [Byte1]: 69
8412 00:58:52.560791
8413 00:58:52.560888 Set Vref, RX VrefLevel [Byte0]: 70
8414 00:58:52.567382 [Byte1]: 70
8415 00:58:52.567481
8416 00:58:52.570443 Set Vref, RX VrefLevel [Byte0]: 71
8417 00:58:52.573871 [Byte1]: 71
8418 00:58:52.573967
8419 00:58:52.577037 Set Vref, RX VrefLevel [Byte0]: 72
8420 00:58:52.580229 [Byte1]: 72
8421 00:58:52.583626
8422 00:58:52.583722 Set Vref, RX VrefLevel [Byte0]: 73
8423 00:58:52.586914 [Byte1]: 73
8424 00:58:52.591254
8425 00:58:52.591351 Set Vref, RX VrefLevel [Byte0]: 74
8426 00:58:52.594670 [Byte1]: 74
8427 00:58:52.599048
8428 00:58:52.599148 Final RX Vref Byte 0 = 61 to rank0
8429 00:58:52.602348 Final RX Vref Byte 1 = 56 to rank0
8430 00:58:52.605489 Final RX Vref Byte 0 = 61 to rank1
8431 00:58:52.608812 Final RX Vref Byte 1 = 56 to rank1==
8432 00:58:52.612310 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 00:58:52.618808 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8434 00:58:52.618907 ==
8435 00:58:52.618993 DQS Delay:
8436 00:58:52.622050 DQS0 = 0, DQS1 = 0
8437 00:58:52.622146 DQM Delay:
8438 00:58:52.622254 DQM0 = 128, DQM1 = 122
8439 00:58:52.625420 DQ Delay:
8440 00:58:52.629078 DQ0 =134, DQ1 =122, DQ2 =116, DQ3 =126
8441 00:58:52.632155 DQ4 =130, DQ5 =138, DQ6 =136, DQ7 =126
8442 00:58:52.635411 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =110
8443 00:58:52.638696 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =132
8444 00:58:52.638800
8445 00:58:52.638885
8446 00:58:52.638966
8447 00:58:52.642078 [DramC_TX_OE_Calibration] TA2
8448 00:58:52.645443 Original DQ_B0 (3 6) =30, OEN = 27
8449 00:58:52.648734 Original DQ_B1 (3 6) =30, OEN = 27
8450 00:58:52.651623 24, 0x0, End_B0=24 End_B1=24
8451 00:58:52.651725 25, 0x0, End_B0=25 End_B1=25
8452 00:58:52.654945 26, 0x0, End_B0=26 End_B1=26
8453 00:58:52.658443 27, 0x0, End_B0=27 End_B1=27
8454 00:58:52.661761 28, 0x0, End_B0=28 End_B1=28
8455 00:58:52.664961 29, 0x0, End_B0=29 End_B1=29
8456 00:58:52.665061 30, 0x0, End_B0=30 End_B1=30
8457 00:58:52.668484 31, 0x4545, End_B0=30 End_B1=30
8458 00:58:52.671874 Byte0 end_step=30 best_step=27
8459 00:58:52.674957 Byte1 end_step=30 best_step=27
8460 00:58:52.678357 Byte0 TX OE(2T, 0.5T) = (3, 3)
8461 00:58:52.681875 Byte1 TX OE(2T, 0.5T) = (3, 3)
8462 00:58:52.681974
8463 00:58:52.682059
8464 00:58:52.688439 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8465 00:58:52.691862 CH1 RK0: MR19=303, MR18=2B2B
8466 00:58:52.698341 CH1_RK0: MR19=0x303, MR18=0x2B2B, DQSOSC=388, MR23=63, INC=24, DEC=16
8467 00:58:52.698442
8468 00:58:52.701727 ----->DramcWriteLeveling(PI) begin...
8469 00:58:52.701825 ==
8470 00:58:52.705011 Dram Type= 6, Freq= 0, CH_1, rank 1
8471 00:58:52.708272 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8472 00:58:52.708393 ==
8473 00:58:52.711714 Write leveling (Byte 0): 23 => 23
8474 00:58:52.714925 Write leveling (Byte 1): 21 => 21
8475 00:58:52.718259 DramcWriteLeveling(PI) end<-----
8476 00:58:52.718357
8477 00:58:52.718418 ==
8478 00:58:52.721676 Dram Type= 6, Freq= 0, CH_1, rank 1
8479 00:58:52.724958 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8480 00:58:52.725111 ==
8481 00:58:52.728442 [Gating] SW mode calibration
8482 00:58:52.734877 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8483 00:58:52.741780 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8484 00:58:52.745207 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8485 00:58:52.751568 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8486 00:58:52.754671 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8487 00:58:52.758205 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8488 00:58:52.764587 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8489 00:58:52.767825 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8490 00:58:52.771120 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8491 00:58:52.777838 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8492 00:58:52.781072 0 13 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8493 00:58:52.784768 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8494 00:58:52.790986 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8495 00:58:52.794501 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8496 00:58:52.797737 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8497 00:58:52.804371 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8498 00:58:52.807661 0 13 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8499 00:58:52.810925 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8500 00:58:52.814362 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8501 00:58:52.820845 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8502 00:58:52.824069 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8503 00:58:52.827687 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8504 00:58:52.834384 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8505 00:58:52.837566 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8506 00:58:52.840934 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8507 00:58:52.847534 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8508 00:58:52.851008 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8509 00:58:52.854100 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 00:58:52.860823 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 00:58:52.864174 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 00:58:52.867458 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 00:58:52.873959 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 00:58:52.877367 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 00:58:52.880747 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 00:58:52.887261 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 00:58:52.890460 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 00:58:52.893787 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 00:58:52.900501 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 00:58:52.903918 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 00:58:52.907058 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8522 00:58:52.913711 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8523 00:58:52.916960 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8524 00:58:52.920451 Total UI for P1: 0, mck2ui 16
8525 00:58:52.923798 best dqsien dly found for B0: ( 1, 0, 22)
8526 00:58:52.926886 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8527 00:58:52.930019 Total UI for P1: 0, mck2ui 16
8528 00:58:52.933505 best dqsien dly found for B1: ( 1, 0, 28)
8529 00:58:52.936630 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8530 00:58:52.940121 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8531 00:58:52.940201
8532 00:58:52.946618 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8533 00:58:52.950103 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8534 00:58:52.953398 [Gating] SW calibration Done
8535 00:58:52.953497 ==
8536 00:58:52.956383 Dram Type= 6, Freq= 0, CH_1, rank 1
8537 00:58:52.959954 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8538 00:58:52.960034 ==
8539 00:58:52.960094 RX Vref Scan: 0
8540 00:58:52.960149
8541 00:58:52.963356 RX Vref 0 -> 0, step: 1
8542 00:58:52.963438
8543 00:58:52.966495 RX Delay 0 -> 252, step: 8
8544 00:58:52.969904 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8545 00:58:52.973102 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8546 00:58:52.979613 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8547 00:58:52.983050 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8548 00:58:52.986291 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8549 00:58:52.989518 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8550 00:58:52.992914 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8551 00:58:52.996249 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8552 00:58:53.002950 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8553 00:58:53.006245 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8554 00:58:53.009429 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8555 00:58:53.013049 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8556 00:58:53.019435 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8557 00:58:53.022797 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8558 00:58:53.026181 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8559 00:58:53.029367 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8560 00:58:53.029448 ==
8561 00:58:53.032611 Dram Type= 6, Freq= 0, CH_1, rank 1
8562 00:58:53.039357 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8563 00:58:53.039453 ==
8564 00:58:53.039514 DQS Delay:
8565 00:58:53.039569 DQS0 = 0, DQS1 = 0
8566 00:58:53.042692 DQM Delay:
8567 00:58:53.042769 DQM0 = 131, DQM1 = 126
8568 00:58:53.046062 DQ Delay:
8569 00:58:53.049212 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8570 00:58:53.052525 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8571 00:58:53.055792 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8572 00:58:53.059341 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8573 00:58:53.059438
8574 00:58:53.059542
8575 00:58:53.059633 ==
8576 00:58:53.062485 Dram Type= 6, Freq= 0, CH_1, rank 1
8577 00:58:53.065660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8578 00:58:53.069091 ==
8579 00:58:53.069173
8580 00:58:53.069233
8581 00:58:53.069289 TX Vref Scan disable
8582 00:58:53.072351 == TX Byte 0 ==
8583 00:58:53.075623 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8584 00:58:53.079101 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8585 00:58:53.082448 == TX Byte 1 ==
8586 00:58:53.085695 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8587 00:58:53.089018 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8588 00:58:53.092381 ==
8589 00:58:53.092463 Dram Type= 6, Freq= 0, CH_1, rank 1
8590 00:58:53.098625 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8591 00:58:53.098731 ==
8592 00:58:53.111646
8593 00:58:53.114886 TX Vref early break, caculate TX vref
8594 00:58:53.118391 TX Vref=16, minBit 1, minWin=21, winSum=370
8595 00:58:53.121698 TX Vref=18, minBit 5, minWin=21, winSum=383
8596 00:58:53.125145 TX Vref=20, minBit 5, minWin=23, winSum=393
8597 00:58:53.128521 TX Vref=22, minBit 5, minWin=23, winSum=397
8598 00:58:53.131922 TX Vref=24, minBit 2, minWin=24, winSum=411
8599 00:58:53.138377 TX Vref=26, minBit 0, minWin=24, winSum=417
8600 00:58:53.141598 TX Vref=28, minBit 0, minWin=25, winSum=420
8601 00:58:53.144849 TX Vref=30, minBit 0, minWin=23, winSum=421
8602 00:58:53.148320 TX Vref=32, minBit 0, minWin=23, winSum=413
8603 00:58:53.151576 TX Vref=34, minBit 0, minWin=23, winSum=400
8604 00:58:53.154893 TX Vref=36, minBit 0, minWin=21, winSum=392
8605 00:58:53.161474 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8606 00:58:53.161566
8607 00:58:53.164762 Final TX Range 0 Vref 28
8608 00:58:53.164841
8609 00:58:53.164902 ==
8610 00:58:53.168432 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 00:58:53.171403 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 00:58:53.171483 ==
8613 00:58:53.171543
8614 00:58:53.171621
8615 00:58:53.174657 TX Vref Scan disable
8616 00:58:53.181403 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8617 00:58:53.181503 == TX Byte 0 ==
8618 00:58:53.184654 u2DelayCellOfst[0]=18 cells (5 PI)
8619 00:58:53.188124 u2DelayCellOfst[1]=10 cells (3 PI)
8620 00:58:53.191407 u2DelayCellOfst[2]=0 cells (0 PI)
8621 00:58:53.194623 u2DelayCellOfst[3]=10 cells (3 PI)
8622 00:58:53.197811 u2DelayCellOfst[4]=10 cells (3 PI)
8623 00:58:53.201380 u2DelayCellOfst[5]=18 cells (5 PI)
8624 00:58:53.204813 u2DelayCellOfst[6]=18 cells (5 PI)
8625 00:58:53.207743 u2DelayCellOfst[7]=7 cells (2 PI)
8626 00:58:53.211195 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8627 00:58:53.214241 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8628 00:58:53.218096 == TX Byte 1 ==
8629 00:58:53.221013 u2DelayCellOfst[8]=0 cells (0 PI)
8630 00:58:53.224567 u2DelayCellOfst[9]=3 cells (1 PI)
8631 00:58:53.224649 u2DelayCellOfst[10]=10 cells (3 PI)
8632 00:58:53.227746 u2DelayCellOfst[11]=3 cells (1 PI)
8633 00:58:53.231192 u2DelayCellOfst[12]=14 cells (4 PI)
8634 00:58:53.234377 u2DelayCellOfst[13]=18 cells (5 PI)
8635 00:58:53.237713 u2DelayCellOfst[14]=18 cells (5 PI)
8636 00:58:53.241311 u2DelayCellOfst[15]=18 cells (5 PI)
8637 00:58:53.247588 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8638 00:58:53.251031 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8639 00:58:53.251119 DramC Write-DBI on
8640 00:58:53.251179 ==
8641 00:58:53.254196 Dram Type= 6, Freq= 0, CH_1, rank 1
8642 00:58:53.260875 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8643 00:58:53.260980 ==
8644 00:58:53.261042
8645 00:58:53.261098
8646 00:58:53.261151 TX Vref Scan disable
8647 00:58:53.265011 == TX Byte 0 ==
8648 00:58:53.268327 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8649 00:58:53.271473 == TX Byte 1 ==
8650 00:58:53.274830 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8651 00:58:53.278205 DramC Write-DBI off
8652 00:58:53.278327
8653 00:58:53.278388 [DATLAT]
8654 00:58:53.278444 Freq=1600, CH1 RK1
8655 00:58:53.278498
8656 00:58:53.281718 DATLAT Default: 0xe
8657 00:58:53.281821 0, 0xFFFF, sum = 0
8658 00:58:53.284898 1, 0xFFFF, sum = 0
8659 00:58:53.284983 2, 0xFFFF, sum = 0
8660 00:58:53.288097 3, 0xFFFF, sum = 0
8661 00:58:53.291583 4, 0xFFFF, sum = 0
8662 00:58:53.291666 5, 0xFFFF, sum = 0
8663 00:58:53.294801 6, 0xFFFF, sum = 0
8664 00:58:53.294881 7, 0xFFFF, sum = 0
8665 00:58:53.298182 8, 0xFFFF, sum = 0
8666 00:58:53.298305 9, 0xFFFF, sum = 0
8667 00:58:53.301399 10, 0xFFFF, sum = 0
8668 00:58:53.301479 11, 0xFFFF, sum = 0
8669 00:58:53.304674 12, 0x8F7F, sum = 0
8670 00:58:53.304753 13, 0x0, sum = 1
8671 00:58:53.308233 14, 0x0, sum = 2
8672 00:58:53.308315 15, 0x0, sum = 3
8673 00:58:53.311560 16, 0x0, sum = 4
8674 00:58:53.311639 best_step = 14
8675 00:58:53.311699
8676 00:58:53.311753 ==
8677 00:58:53.314630 Dram Type= 6, Freq= 0, CH_1, rank 1
8678 00:58:53.317914 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8679 00:58:53.321275 ==
8680 00:58:53.321357 RX Vref Scan: 0
8681 00:58:53.321417
8682 00:58:53.324681 RX Vref 0 -> 0, step: 1
8683 00:58:53.324798
8684 00:58:53.324926 RX Delay 3 -> 252, step: 4
8685 00:58:53.332374 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8686 00:58:53.335151 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8687 00:58:53.338936 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8688 00:58:53.342004 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8689 00:58:53.345225 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8690 00:58:53.351777 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8691 00:58:53.355316 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8692 00:58:53.358287 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8693 00:58:53.361776 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8694 00:58:53.365159 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8695 00:58:53.371615 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8696 00:58:53.374815 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8697 00:58:53.378500 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8698 00:58:53.381722 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8699 00:58:53.388285 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8700 00:58:53.391597 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8701 00:58:53.391688 ==
8702 00:58:53.394798 Dram Type= 6, Freq= 0, CH_1, rank 1
8703 00:58:53.398055 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8704 00:58:53.398166 ==
8705 00:58:53.401912 DQS Delay:
8706 00:58:53.401990 DQS0 = 0, DQS1 = 0
8707 00:58:53.402049 DQM Delay:
8708 00:58:53.404783 DQM0 = 127, DQM1 = 123
8709 00:58:53.404862 DQ Delay:
8710 00:58:53.408206 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8711 00:58:53.411343 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8712 00:58:53.414673 DQ8 =104, DQ9 =112, DQ10 =126, DQ11 =114
8713 00:58:53.421307 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8714 00:58:53.421397
8715 00:58:53.421458
8716 00:58:53.421512
8717 00:58:53.424794 [DramC_TX_OE_Calibration] TA2
8718 00:58:53.427958 Original DQ_B0 (3 6) =30, OEN = 27
8719 00:58:53.428038 Original DQ_B1 (3 6) =30, OEN = 27
8720 00:58:53.431344 24, 0x0, End_B0=24 End_B1=24
8721 00:58:53.434697 25, 0x0, End_B0=25 End_B1=25
8722 00:58:53.437966 26, 0x0, End_B0=26 End_B1=26
8723 00:58:53.441249 27, 0x0, End_B0=27 End_B1=27
8724 00:58:53.441328 28, 0x0, End_B0=28 End_B1=28
8725 00:58:53.444619 29, 0x0, End_B0=29 End_B1=29
8726 00:58:53.447997 30, 0x0, End_B0=30 End_B1=30
8727 00:58:53.451384 31, 0x4545, End_B0=30 End_B1=30
8728 00:58:53.454881 Byte0 end_step=30 best_step=27
8729 00:58:53.454964 Byte1 end_step=30 best_step=27
8730 00:58:53.457914 Byte0 TX OE(2T, 0.5T) = (3, 3)
8731 00:58:53.461369 Byte1 TX OE(2T, 0.5T) = (3, 3)
8732 00:58:53.461451
8733 00:58:53.461511
8734 00:58:53.471395 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8735 00:58:53.471510 CH1 RK1: MR19=303, MR18=2121
8736 00:58:53.477772 CH1_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8737 00:58:53.481133 [RxdqsGatingPostProcess] freq 1600
8738 00:58:53.487760 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8739 00:58:53.491045 Pre-setting of DQS Precalculation
8740 00:58:53.494278 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8741 00:58:53.500999 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8742 00:58:53.511235 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8743 00:58:53.511354
8744 00:58:53.511416
8745 00:58:53.514485 [Calibration Summary] 3200 Mbps
8746 00:58:53.514567 CH 0, Rank 0
8747 00:58:53.517581 SW Impedance : PASS
8748 00:58:53.517659 DUTY Scan : NO K
8749 00:58:53.520889 ZQ Calibration : PASS
8750 00:58:53.524287 Jitter Meter : NO K
8751 00:58:53.524371 CBT Training : PASS
8752 00:58:53.527701 Write leveling : PASS
8753 00:58:53.530768 RX DQS gating : PASS
8754 00:58:53.530849 RX DQ/DQS(RDDQC) : PASS
8755 00:58:53.534128 TX DQ/DQS : PASS
8756 00:58:53.534236 RX DATLAT : PASS
8757 00:58:53.537653 RX DQ/DQS(Engine): PASS
8758 00:58:53.540605 TX OE : PASS
8759 00:58:53.540686 All Pass.
8760 00:58:53.540746
8761 00:58:53.543976 CH 0, Rank 1
8762 00:58:53.544054 SW Impedance : PASS
8763 00:58:53.547241 DUTY Scan : NO K
8764 00:58:53.547321 ZQ Calibration : PASS
8765 00:58:53.550560 Jitter Meter : NO K
8766 00:58:53.554141 CBT Training : PASS
8767 00:58:53.554246 Write leveling : PASS
8768 00:58:53.557291 RX DQS gating : PASS
8769 00:58:53.560649 RX DQ/DQS(RDDQC) : PASS
8770 00:58:53.560731 TX DQ/DQS : PASS
8771 00:58:53.564227 RX DATLAT : PASS
8772 00:58:53.567277 RX DQ/DQS(Engine): PASS
8773 00:58:53.567360 TX OE : PASS
8774 00:58:53.570841 All Pass.
8775 00:58:53.570921
8776 00:58:53.570982 CH 1, Rank 0
8777 00:58:53.573974 SW Impedance : PASS
8778 00:58:53.574052 DUTY Scan : NO K
8779 00:58:53.577330 ZQ Calibration : PASS
8780 00:58:53.580806 Jitter Meter : NO K
8781 00:58:53.580887 CBT Training : PASS
8782 00:58:53.583834 Write leveling : PASS
8783 00:58:53.587252 RX DQS gating : PASS
8784 00:58:53.587341 RX DQ/DQS(RDDQC) : PASS
8785 00:58:53.590650 TX DQ/DQS : PASS
8786 00:58:53.590730 RX DATLAT : PASS
8787 00:58:53.593920 RX DQ/DQS(Engine): PASS
8788 00:58:53.597044 TX OE : PASS
8789 00:58:53.597125 All Pass.
8790 00:58:53.597186
8791 00:58:53.597242 CH 1, Rank 1
8792 00:58:53.600598 SW Impedance : PASS
8793 00:58:53.603783 DUTY Scan : NO K
8794 00:58:53.603869 ZQ Calibration : PASS
8795 00:58:53.607002 Jitter Meter : NO K
8796 00:58:53.610270 CBT Training : PASS
8797 00:58:53.610351 Write leveling : PASS
8798 00:58:53.613657 RX DQS gating : PASS
8799 00:58:53.617166 RX DQ/DQS(RDDQC) : PASS
8800 00:58:53.617249 TX DQ/DQS : PASS
8801 00:58:53.620364 RX DATLAT : PASS
8802 00:58:53.623748 RX DQ/DQS(Engine): PASS
8803 00:58:53.623830 TX OE : PASS
8804 00:58:53.626907 All Pass.
8805 00:58:53.626985
8806 00:58:53.627045 DramC Write-DBI on
8807 00:58:53.630500 PER_BANK_REFRESH: Hybrid Mode
8808 00:58:53.630580 TX_TRACKING: ON
8809 00:58:53.640260 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8810 00:58:53.650256 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8811 00:58:53.657151 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8812 00:58:53.660357 [FAST_K] Save calibration result to emmc
8813 00:58:53.663495 sync common calibartion params.
8814 00:58:53.663581 sync cbt_mode0:0, 1:0
8815 00:58:53.667042 dram_init: ddr_geometry: 0
8816 00:58:53.670278 dram_init: ddr_geometry: 0
8817 00:58:53.670362 dram_init: ddr_geometry: 0
8818 00:58:53.673433 0:dram_rank_size:80000000
8819 00:58:53.676843 1:dram_rank_size:80000000
8820 00:58:53.680102 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8821 00:58:53.683389 DFS_SHUFFLE_HW_MODE: ON
8822 00:58:53.686503 dramc_set_vcore_voltage set vcore to 725000
8823 00:58:53.690004 Read voltage for 1600, 0
8824 00:58:53.690096 Vio18 = 0
8825 00:58:53.693215 Vcore = 725000
8826 00:58:53.693295 Vdram = 0
8827 00:58:53.693355 Vddq = 0
8828 00:58:53.693411 Vmddr = 0
8829 00:58:53.696608 switch to 3200 Mbps bootup
8830 00:58:53.699928 [DramcRunTimeConfig]
8831 00:58:53.700044 PHYPLL
8832 00:58:53.703033 DPM_CONTROL_AFTERK: ON
8833 00:58:53.703113 PER_BANK_REFRESH: ON
8834 00:58:53.706604 REFRESH_OVERHEAD_REDUCTION: ON
8835 00:58:53.709746 CMD_PICG_NEW_MODE: OFF
8836 00:58:53.709828 XRTWTW_NEW_MODE: ON
8837 00:58:53.713155 XRTRTR_NEW_MODE: ON
8838 00:58:53.713238 TX_TRACKING: ON
8839 00:58:53.716312 RDSEL_TRACKING: OFF
8840 00:58:53.719669 DQS Precalculation for DVFS: ON
8841 00:58:53.719752 RX_TRACKING: OFF
8842 00:58:53.723092 HW_GATING DBG: ON
8843 00:58:53.723174 ZQCS_ENABLE_LP4: ON
8844 00:58:53.726378 RX_PICG_NEW_MODE: ON
8845 00:58:53.726456 TX_PICG_NEW_MODE: ON
8846 00:58:53.729538 ENABLE_RX_DCM_DPHY: ON
8847 00:58:53.732902 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8848 00:58:53.736372 DUMMY_READ_FOR_TRACKING: OFF
8849 00:58:53.736457 !!! SPM_CONTROL_AFTERK: OFF
8850 00:58:53.739428 !!! SPM could not control APHY
8851 00:58:53.743028 IMPEDANCE_TRACKING: ON
8852 00:58:53.743130 TEMP_SENSOR: ON
8853 00:58:53.746077 HW_SAVE_FOR_SR: OFF
8854 00:58:53.749326 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8855 00:58:53.752801 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8856 00:58:53.752882 Read ODT Tracking: ON
8857 00:58:53.755977 Refresh Rate DeBounce: ON
8858 00:58:53.759440 DFS_NO_QUEUE_FLUSH: ON
8859 00:58:53.762807 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8860 00:58:53.762892 ENABLE_DFS_RUNTIME_MRW: OFF
8861 00:58:53.766015 DDR_RESERVE_NEW_MODE: ON
8862 00:58:53.769325 MR_CBT_SWITCH_FREQ: ON
8863 00:58:53.769408 =========================
8864 00:58:53.789603 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8865 00:58:53.792747 dram_init: ddr_geometry: 0
8866 00:58:53.810897 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8867 00:58:53.814182 dram_init: dram init end (result: 0)
8868 00:58:53.820930 DRAM-K: Full calibration passed in 23435 msecs
8869 00:58:53.824071 MRC: failed to locate region type 0.
8870 00:58:53.824166 DRAM rank0 size:0x80000000,
8871 00:58:53.827465 DRAM rank1 size=0x80000000
8872 00:58:53.837635 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8873 00:58:53.843856 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8874 00:58:53.850793 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8875 00:58:53.857146 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8876 00:58:53.860355 DRAM rank0 size:0x80000000,
8877 00:58:53.863721 DRAM rank1 size=0x80000000
8878 00:58:53.863808 CBMEM:
8879 00:58:53.866993 IMD: root @ 0xfffff000 254 entries.
8880 00:58:53.870355 IMD: root @ 0xffffec00 62 entries.
8881 00:58:53.873587 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8882 00:58:53.877099 WARNING: RO_VPD is uninitialized or empty.
8883 00:58:53.883739 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8884 00:58:53.890459 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8885 00:58:53.903195 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8886 00:58:53.914725 BS: romstage times (exec / console): total (unknown) / 22969 ms
8887 00:58:53.914843
8888 00:58:53.914907
8889 00:58:53.924558 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8890 00:58:53.927767 ARM64: Exception handlers installed.
8891 00:58:53.931001 ARM64: Testing exception
8892 00:58:53.934484 ARM64: Done test exception
8893 00:58:53.934569 Enumerating buses...
8894 00:58:53.937712 Show all devs... Before device enumeration.
8895 00:58:53.941076 Root Device: enabled 1
8896 00:58:53.944265 CPU_CLUSTER: 0: enabled 1
8897 00:58:53.944350 CPU: 00: enabled 1
8898 00:58:53.947812 Compare with tree...
8899 00:58:53.947894 Root Device: enabled 1
8900 00:58:53.950888 CPU_CLUSTER: 0: enabled 1
8901 00:58:53.954361 CPU: 00: enabled 1
8902 00:58:53.954445 Root Device scanning...
8903 00:58:53.957662 scan_static_bus for Root Device
8904 00:58:53.961112 CPU_CLUSTER: 0 enabled
8905 00:58:53.964231 scan_static_bus for Root Device done
8906 00:58:53.967519 scan_bus: bus Root Device finished in 8 msecs
8907 00:58:53.967604 done
8908 00:58:53.974063 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8909 00:58:53.977240 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8910 00:58:53.984314 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8911 00:58:53.987260 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8912 00:58:53.990856 Allocating resources...
8913 00:58:53.993777 Reading resources...
8914 00:58:53.997165 Root Device read_resources bus 0 link: 0
8915 00:58:53.997251 DRAM rank0 size:0x80000000,
8916 00:58:54.000533 DRAM rank1 size=0x80000000
8917 00:58:54.003818 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8918 00:58:54.007162 CPU: 00 missing read_resources
8919 00:58:54.013836 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8920 00:58:54.017091 Root Device read_resources bus 0 link: 0 done
8921 00:58:54.017178 Done reading resources.
8922 00:58:54.023841 Show resources in subtree (Root Device)...After reading.
8923 00:58:54.027138 Root Device child on link 0 CPU_CLUSTER: 0
8924 00:58:54.030461 CPU_CLUSTER: 0 child on link 0 CPU: 00
8925 00:58:54.040188 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8926 00:58:54.040299 CPU: 00
8927 00:58:54.043729 Root Device assign_resources, bus 0 link: 0
8928 00:58:54.046840 CPU_CLUSTER: 0 missing set_resources
8929 00:58:54.053528 Root Device assign_resources, bus 0 link: 0 done
8930 00:58:54.053623 Done setting resources.
8931 00:58:54.059992 Show resources in subtree (Root Device)...After assigning values.
8932 00:58:54.063307 Root Device child on link 0 CPU_CLUSTER: 0
8933 00:58:54.066736 CPU_CLUSTER: 0 child on link 0 CPU: 00
8934 00:58:54.076567 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8935 00:58:54.076685 CPU: 00
8936 00:58:54.079929 Done allocating resources.
8937 00:58:54.086389 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8938 00:58:54.086491 Enabling resources...
8939 00:58:54.086553 done.
8940 00:58:54.093008 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8941 00:58:54.093097 Initializing devices...
8942 00:58:54.096440 Root Device init
8943 00:58:54.099815 init hardware done!
8944 00:58:54.099895 0x00000018: ctrlr->caps
8945 00:58:54.102927 52.000 MHz: ctrlr->f_max
8946 00:58:54.103006 0.400 MHz: ctrlr->f_min
8947 00:58:54.106541 0x40ff8080: ctrlr->voltages
8948 00:58:54.109494 sclk: 390625
8949 00:58:54.109574 Bus Width = 1
8950 00:58:54.109633 sclk: 390625
8951 00:58:54.112906 Bus Width = 1
8952 00:58:54.112983 Early init status = 3
8953 00:58:54.119562 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8954 00:58:54.122849 in-header: 03 fc 00 00 01 00 00 00
8955 00:58:54.126352 in-data: 00
8956 00:58:54.129358 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8957 00:58:54.134260 in-header: 03 fd 00 00 00 00 00 00
8958 00:58:54.137581 in-data:
8959 00:58:54.141067 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8960 00:58:54.144852 in-header: 03 fc 00 00 01 00 00 00
8961 00:58:54.147981 in-data: 00
8962 00:58:54.151224 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8963 00:58:54.156343 in-header: 03 fd 00 00 00 00 00 00
8964 00:58:54.159749 in-data:
8965 00:58:54.162770 [SSUSB] Setting up USB HOST controller...
8966 00:58:54.166233 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8967 00:58:54.169547 [SSUSB] phy power-on done.
8968 00:58:54.172999 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8969 00:58:54.179586 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8970 00:58:54.183172 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8971 00:58:54.189538 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8972 00:58:54.196240 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8973 00:58:54.202838 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8974 00:58:54.209329 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8975 00:58:54.215991 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8976 00:58:54.219505 SPM: binary array size = 0x9dc
8977 00:58:54.222982 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8978 00:58:54.229366 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8979 00:58:54.235940 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8980 00:58:54.239202 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8981 00:58:54.245695 configure_display: Starting display init
8982 00:58:54.279459 anx7625_power_on_init: Init interface.
8983 00:58:54.282901 anx7625_disable_pd_protocol: Disabled PD feature.
8984 00:58:54.286053 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8985 00:58:54.313921 anx7625_start_dp_work: Secure OCM version=00
8986 00:58:54.317339 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8987 00:58:54.332057 sp_tx_get_edid_block: EDID Block = 1
8988 00:58:54.434591 Extracted contents:
8989 00:58:54.437980 header: 00 ff ff ff ff ff ff 00
8990 00:58:54.441159 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8991 00:58:54.444533 version: 01 04
8992 00:58:54.447693 basic params: 95 1f 11 78 0a
8993 00:58:54.451069 chroma info: 76 90 94 55 54 90 27 21 50 54
8994 00:58:54.454460 established: 00 00 00
8995 00:58:54.461267 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8996 00:58:54.464341 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8997 00:58:54.470961 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8998 00:58:54.477565 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8999 00:58:54.484360 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9000 00:58:54.487629 extensions: 00
9001 00:58:54.487721 checksum: fb
9002 00:58:54.487781
9003 00:58:54.490932 Manufacturer: IVO Model 57d Serial Number 0
9004 00:58:54.494207 Made week 0 of 2020
9005 00:58:54.494329 EDID version: 1.4
9006 00:58:54.497706 Digital display
9007 00:58:54.500842 6 bits per primary color channel
9008 00:58:54.500922 DisplayPort interface
9009 00:58:54.504095 Maximum image size: 31 cm x 17 cm
9010 00:58:54.507534 Gamma: 220%
9011 00:58:54.507612 Check DPMS levels
9012 00:58:54.510685 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9013 00:58:54.514089 First detailed timing is preferred timing
9014 00:58:54.517454 Established timings supported:
9015 00:58:54.521280 Standard timings supported:
9016 00:58:54.524330 Detailed timings
9017 00:58:54.527501 Hex of detail: 383680a07038204018303c0035ae10000019
9018 00:58:54.530787 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9019 00:58:54.537676 0780 0798 07c8 0820 hborder 0
9020 00:58:54.540689 0438 043b 0447 0458 vborder 0
9021 00:58:54.544117 -hsync -vsync
9022 00:58:54.544199 Did detailed timing
9023 00:58:54.550910 Hex of detail: 000000000000000000000000000000000000
9024 00:58:54.551005 Manufacturer-specified data, tag 0
9025 00:58:54.557163 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9026 00:58:54.560660 ASCII string: InfoVision
9027 00:58:54.564211 Hex of detail: 000000fe00523134304e574635205248200a
9028 00:58:54.567235 ASCII string: R140NWF5 RH
9029 00:58:54.567318 Checksum
9030 00:58:54.570610 Checksum: 0xfb (valid)
9031 00:58:54.574047 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9032 00:58:54.577477 DSI data_rate: 832800000 bps
9033 00:58:54.583713 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9034 00:58:54.587128 anx7625_parse_edid: pixelclock(138800).
9035 00:58:54.590523 hactive(1920), hsync(48), hfp(24), hbp(88)
9036 00:58:54.593660 vactive(1080), vsync(12), vfp(3), vbp(17)
9037 00:58:54.596997 anx7625_dsi_config: config dsi.
9038 00:58:54.603688 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9039 00:58:54.616565 anx7625_dsi_config: success to config DSI
9040 00:58:54.620084 anx7625_dp_start: MIPI phy setup OK.
9041 00:58:54.623203 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9042 00:58:54.626566 mtk_ddp_mode_set invalid vrefresh 60
9043 00:58:54.629924 main_disp_path_setup
9044 00:58:54.630031 ovl_layer_smi_id_en
9045 00:58:54.633226 ovl_layer_smi_id_en
9046 00:58:54.633303 ccorr_config
9047 00:58:54.633363 aal_config
9048 00:58:54.636509 gamma_config
9049 00:58:54.636587 postmask_config
9050 00:58:54.640011 dither_config
9051 00:58:54.643171 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9052 00:58:54.649950 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9053 00:58:54.653251 Root Device init finished in 553 msecs
9054 00:58:54.653335 CPU_CLUSTER: 0 init
9055 00:58:54.663185 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9056 00:58:54.666542 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9057 00:58:54.669785 APU_MBOX 0x190000b0 = 0x10001
9058 00:58:54.673313 APU_MBOX 0x190001b0 = 0x10001
9059 00:58:54.676550 APU_MBOX 0x190005b0 = 0x10001
9060 00:58:54.679873 APU_MBOX 0x190006b0 = 0x10001
9061 00:58:54.682923 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9062 00:58:54.695447 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9063 00:58:54.707964 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9064 00:58:54.714553 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9065 00:58:54.726202 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9066 00:58:54.735267 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9067 00:58:54.738607 CPU_CLUSTER: 0 init finished in 81 msecs
9068 00:58:54.741937 Devices initialized
9069 00:58:54.745170 Show all devs... After init.
9070 00:58:54.745251 Root Device: enabled 1
9071 00:58:54.748548 CPU_CLUSTER: 0: enabled 1
9072 00:58:54.751712 CPU: 00: enabled 1
9073 00:58:54.755139 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9074 00:58:54.758332 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9075 00:58:54.761633 ELOG: NV offset 0x57f000 size 0x1000
9076 00:58:54.768659 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9077 00:58:54.775245 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9078 00:58:54.778514 ELOG: Event(17) added with size 13 at 2024-06-16 00:58:54 UTC
9079 00:58:54.781731 out: cmd=0x121: 03 db 21 01 00 00 00 00
9080 00:58:54.785438 in-header: 03 10 00 00 2c 00 00 00
9081 00:58:54.798909 in-data: 32 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9082 00:58:54.805475 ELOG: Event(A1) added with size 10 at 2024-06-16 00:58:54 UTC
9083 00:58:54.812216 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9084 00:58:54.815712 ELOG: Event(A0) added with size 9 at 2024-06-16 00:58:54 UTC
9085 00:58:54.822269 elog_add_boot_reason: Logged dev mode boot
9086 00:58:54.825561 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9087 00:58:54.828683 Finalize devices...
9088 00:58:54.828780 Devices finalized
9089 00:58:54.835561 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9090 00:58:54.838653 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9091 00:58:54.841983 in-header: 03 07 00 00 08 00 00 00
9092 00:58:54.845327 in-data: aa e4 47 04 13 02 00 00
9093 00:58:54.845410 Chrome EC: UHEPI supported
9094 00:58:54.851969 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9095 00:58:54.855835 in-header: 03 a9 00 00 08 00 00 00
9096 00:58:54.858871 in-data: 84 60 60 08 00 00 00 00
9097 00:58:54.865726 ELOG: Event(91) added with size 10 at 2024-06-16 00:58:54 UTC
9098 00:58:54.868875 Chrome EC: clear events_b mask to 0x0000000020004000
9099 00:58:54.875510 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9100 00:58:54.879712 in-header: 03 fd 00 00 00 00 00 00
9101 00:58:54.883171 in-data:
9102 00:58:54.886429 BS: BS_WRITE_TABLES entry times (exec / console): 1 / 46 ms
9103 00:58:54.889698 Writing coreboot table at 0xffe64000
9104 00:58:54.893082 0. 000000000010a000-0000000000113fff: RAMSTAGE
9105 00:58:54.900036 1. 0000000040000000-00000000400fffff: RAM
9106 00:58:54.903095 2. 0000000040100000-000000004032afff: RAMSTAGE
9107 00:58:54.906504 3. 000000004032b000-00000000545fffff: RAM
9108 00:58:54.909680 4. 0000000054600000-000000005465ffff: BL31
9109 00:58:54.913385 5. 0000000054660000-00000000ffe63fff: RAM
9110 00:58:54.919658 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9111 00:58:54.923319 7. 0000000100000000-000000013fffffff: RAM
9112 00:58:54.926766 Passing 5 GPIOs to payload:
9113 00:58:54.930012 NAME | PORT | POLARITY | VALUE
9114 00:58:54.936431 EC in RW | 0x000000aa | low | undefined
9115 00:58:54.939730 EC interrupt | 0x00000005 | low | undefined
9116 00:58:54.942955 TPM interrupt | 0x000000ab | high | undefined
9117 00:58:54.949728 SD card detect | 0x00000011 | high | undefined
9118 00:58:54.952959 speaker enable | 0x00000093 | high | undefined
9119 00:58:54.956421 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9120 00:58:54.959670 in-header: 03 f8 00 00 02 00 00 00
9121 00:58:54.962993 in-data: 03 00
9122 00:58:54.966237 ADC[4]: Raw value=668958 ID=5
9123 00:58:54.966339 ADC[3]: Raw value=212549 ID=1
9124 00:58:54.969598 RAM Code: 0x51
9125 00:58:54.972888 ADC[6]: Raw value=74778 ID=0
9126 00:58:54.972971 ADC[5]: Raw value=211444 ID=1
9127 00:58:54.976305 SKU Code: 0x1
9128 00:58:54.982786 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7ad
9129 00:58:54.982885 coreboot table: 964 bytes.
9130 00:58:54.986040 IMD ROOT 0. 0xfffff000 0x00001000
9131 00:58:54.989665 IMD SMALL 1. 0xffffe000 0x00001000
9132 00:58:54.992824 RO MCACHE 2. 0xffffc000 0x00001104
9133 00:58:54.996078 CONSOLE 3. 0xfff7c000 0x00080000
9134 00:58:54.999393 FMAP 4. 0xfff7b000 0x00000452
9135 00:58:55.002532 TIME STAMP 5. 0xfff7a000 0x00000910
9136 00:58:55.005964 VBOOT WORK 6. 0xfff66000 0x00014000
9137 00:58:55.009117 RAMOOPS 7. 0xffe66000 0x00100000
9138 00:58:55.012521 COREBOOT 8. 0xffe64000 0x00002000
9139 00:58:55.016140 IMD small region:
9140 00:58:55.019169 IMD ROOT 0. 0xffffec00 0x00000400
9141 00:58:55.022513 VPD 1. 0xffffeb80 0x0000006c
9142 00:58:55.026029 MMC STATUS 2. 0xffffeb60 0x00000004
9143 00:58:55.029447 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9144 00:58:55.035954 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9145 00:58:55.076901 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9146 00:58:55.080085 Checking segment from ROM address 0x40100000
9147 00:58:55.083550 Checking segment from ROM address 0x4010001c
9148 00:58:55.090234 Loading segment from ROM address 0x40100000
9149 00:58:55.090358 code (compression=0)
9150 00:58:55.100188 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9151 00:58:55.106673 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9152 00:58:55.106803 it's not compressed!
9153 00:58:55.113279 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9154 00:58:55.119761 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9155 00:58:55.137129 Loading segment from ROM address 0x4010001c
9156 00:58:55.137256 Entry Point 0x80000000
9157 00:58:55.140403 Loaded segments
9158 00:58:55.143839 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9159 00:58:55.150440 Jumping to boot code at 0x80000000(0xffe64000)
9160 00:58:55.157075 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9161 00:58:55.163662 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9162 00:58:55.171570 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9163 00:58:55.174795 Checking segment from ROM address 0x40100000
9164 00:58:55.178109 Checking segment from ROM address 0x4010001c
9165 00:58:55.184726 Loading segment from ROM address 0x40100000
9166 00:58:55.184841 code (compression=1)
9167 00:58:55.191407 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9168 00:58:55.201312 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9169 00:58:55.201430 using LZMA
9170 00:58:55.209857 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9171 00:58:55.216543 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9172 00:58:55.219859 Loading segment from ROM address 0x4010001c
9173 00:58:55.219948 Entry Point 0x54601000
9174 00:58:55.223279 Loaded segments
9175 00:58:55.226572 NOTICE: MT8192 bl31_setup
9176 00:58:55.233483 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9177 00:58:55.237010 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9178 00:58:55.240151 WARNING: region 0:
9179 00:58:55.243460 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 00:58:55.243544 WARNING: region 1:
9181 00:58:55.250260 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9182 00:58:55.253406 WARNING: region 2:
9183 00:58:55.256760 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9184 00:58:55.259897 WARNING: region 3:
9185 00:58:55.263474 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9186 00:58:55.266602 WARNING: region 4:
9187 00:58:55.273607 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9188 00:58:55.273712 WARNING: region 5:
9189 00:58:55.276654 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9190 00:58:55.280001 WARNING: region 6:
9191 00:58:55.283223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9192 00:58:55.286436 WARNING: region 7:
9193 00:58:55.289906 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9194 00:58:55.296784 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9195 00:58:55.299947 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9196 00:58:55.303365 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9197 00:58:55.309849 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9198 00:58:55.313479 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9199 00:58:55.316555 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9200 00:58:55.323383 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9201 00:58:55.326530 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9202 00:58:55.333548 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9203 00:58:55.336633 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9204 00:58:55.339984 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9205 00:58:55.346737 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9206 00:58:55.349819 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9207 00:58:55.353283 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9208 00:58:55.360051 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9209 00:58:55.363059 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9210 00:58:55.369829 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9211 00:58:55.372866 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9212 00:58:55.376203 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9213 00:58:55.382927 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9214 00:58:55.386344 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9215 00:58:55.392707 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9216 00:58:55.396027 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9217 00:58:55.399487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9218 00:58:55.406353 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9219 00:58:55.409467 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9220 00:58:55.416158 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9221 00:58:55.419357 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9222 00:58:55.422714 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9223 00:58:55.429440 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9224 00:58:55.432627 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9225 00:58:55.439372 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9226 00:58:55.442824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9227 00:58:55.445974 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9228 00:58:55.449309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9229 00:58:55.456219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9230 00:58:55.459400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9231 00:58:55.462627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9232 00:58:55.465882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9233 00:58:55.469119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9234 00:58:55.475866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9235 00:58:55.479450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9236 00:58:55.482524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9237 00:58:55.489208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9238 00:58:55.492466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9239 00:58:55.496031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9240 00:58:55.499123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9241 00:58:55.505727 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9242 00:58:55.509391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9243 00:58:55.512400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9244 00:58:55.519183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9245 00:58:55.522562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9246 00:58:55.529284 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9247 00:58:55.532522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9248 00:58:55.539149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9249 00:58:55.542531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9250 00:58:55.545741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9251 00:58:55.552412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9252 00:58:55.555819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9253 00:58:55.562344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9254 00:58:55.565975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9255 00:58:55.572394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9256 00:58:55.575806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9257 00:58:55.582330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9258 00:58:55.585920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9259 00:58:55.589018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9260 00:58:55.595735 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9261 00:58:55.598983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9262 00:58:55.605755 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9263 00:58:55.608786 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9264 00:58:55.615397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9265 00:58:55.618673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9266 00:58:55.622080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9267 00:58:55.628774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9268 00:58:55.632028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9269 00:58:55.638717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9270 00:58:55.642096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9271 00:58:55.648686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9272 00:58:55.652048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9273 00:58:55.658795 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9274 00:58:55.662043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9275 00:58:55.665300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9276 00:58:55.672318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9277 00:58:55.675240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9278 00:58:55.681736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9279 00:58:55.685159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9280 00:58:55.691986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9281 00:58:55.695178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9282 00:58:55.698467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9283 00:58:55.705183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9284 00:58:55.708257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9285 00:58:55.715014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9286 00:58:55.718416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9287 00:58:55.724983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9288 00:58:55.728496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9289 00:58:55.734970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9290 00:58:55.738436 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9291 00:58:55.741590 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9292 00:58:55.744979 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9293 00:58:55.751435 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9294 00:58:55.754825 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9295 00:58:55.758345 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9296 00:58:55.764780 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9297 00:58:55.768181 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9298 00:58:55.774778 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9299 00:58:55.778080 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9300 00:58:55.781568 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9301 00:58:55.787987 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9302 00:58:55.791258 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9303 00:58:55.798003 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9304 00:58:55.801588 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9305 00:58:55.804812 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9306 00:58:55.811263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9307 00:58:55.814543 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9308 00:58:55.821212 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9309 00:58:55.824605 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9310 00:58:55.827823 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9311 00:58:55.831167 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9312 00:58:55.837896 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9313 00:58:55.841165 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9314 00:58:55.844497 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9315 00:58:55.847817 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9316 00:58:55.854768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9317 00:58:55.858153 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9318 00:58:55.861444 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9319 00:58:55.867801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9320 00:58:55.871118 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9321 00:58:55.878011 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9322 00:58:55.881086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9323 00:58:55.884319 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9324 00:58:55.891216 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9325 00:58:55.894295 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9326 00:58:55.897871 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9327 00:58:55.904276 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9328 00:58:55.907753 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9329 00:58:55.914509 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9330 00:58:55.917691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9331 00:58:55.920975 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9332 00:58:55.927551 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9333 00:58:55.930972 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9334 00:58:55.937502 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9335 00:58:55.941027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9336 00:58:55.944099 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9337 00:58:55.950896 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9338 00:58:55.954167 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9339 00:58:55.960960 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9340 00:58:55.964301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9341 00:58:55.967562 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9342 00:58:55.974018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9343 00:58:55.977507 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9344 00:58:55.984227 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9345 00:58:55.987489 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9346 00:58:55.991037 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9347 00:58:55.997328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9348 00:58:56.000704 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9349 00:58:56.004107 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9350 00:58:56.010903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9351 00:58:56.014349 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9352 00:58:56.020771 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9353 00:58:56.024081 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9354 00:58:56.027339 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9355 00:58:56.033994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9356 00:58:56.037381 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9357 00:58:56.044098 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9358 00:58:56.047206 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9359 00:58:56.050680 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9360 00:58:56.057441 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9361 00:58:56.060683 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9362 00:58:56.064091 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9363 00:58:56.070526 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9364 00:58:56.073817 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9365 00:58:56.080654 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9366 00:58:56.084185 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9367 00:58:56.087270 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9368 00:58:56.093985 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9369 00:58:56.097232 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9370 00:58:56.103670 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9371 00:58:56.107208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9372 00:58:56.110472 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9373 00:58:56.116964 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9374 00:58:56.120245 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9375 00:58:56.126860 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9376 00:58:56.130178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9377 00:58:56.133480 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9378 00:58:56.139977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9379 00:58:56.143432 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9380 00:58:56.150047 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9381 00:58:56.153285 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9382 00:58:56.156788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9383 00:58:56.163428 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9384 00:58:56.167006 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9385 00:58:56.173577 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9386 00:58:56.176528 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9387 00:58:56.180062 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9388 00:58:56.186525 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9389 00:58:56.189893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9390 00:58:56.196843 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9391 00:58:56.199920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9392 00:58:56.206444 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9393 00:58:56.209869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9394 00:58:56.213145 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9395 00:58:56.219858 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9396 00:58:56.223168 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9397 00:58:56.229778 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9398 00:58:56.233181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9399 00:58:56.236464 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9400 00:58:56.243168 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9401 00:58:56.246611 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9402 00:58:56.252988 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9403 00:58:56.256328 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9404 00:58:56.263080 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9405 00:58:56.266222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9406 00:58:56.269816 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9407 00:58:56.276303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9408 00:58:56.279761 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9409 00:58:56.286150 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9410 00:58:56.289468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9411 00:58:56.293216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9412 00:58:56.299345 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9413 00:58:56.302931 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9414 00:58:56.309403 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9415 00:58:56.312546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9416 00:58:56.319145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9417 00:58:56.322780 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9418 00:58:56.326317 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9419 00:58:56.332498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9420 00:58:56.335765 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9421 00:58:56.342690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9422 00:58:56.345995 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9423 00:58:56.349257 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9424 00:58:56.352518 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9425 00:58:56.359046 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9426 00:58:56.362539 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9427 00:58:56.365714 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9428 00:58:56.372641 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9429 00:58:56.376233 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9430 00:58:56.379163 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9431 00:58:56.385779 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9432 00:58:56.389301 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9433 00:58:56.392300 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9434 00:58:56.399249 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9435 00:58:56.402370 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9436 00:58:56.409062 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9437 00:58:56.412582 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9438 00:58:56.415832 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9439 00:58:56.422478 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9440 00:58:56.425574 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9441 00:58:56.428998 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9442 00:58:56.436002 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9443 00:58:56.438954 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9444 00:58:56.442324 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9445 00:58:56.448887 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9446 00:58:56.452217 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9447 00:58:56.455586 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9448 00:58:56.462141 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9449 00:58:56.465594 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9450 00:58:56.472017 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9451 00:58:56.475524 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9452 00:58:56.478932 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9453 00:58:56.485304 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9454 00:58:56.488998 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9455 00:58:56.492137 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9456 00:58:56.498881 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9457 00:58:56.502428 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9458 00:58:56.505655 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9459 00:58:56.512250 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9460 00:58:56.515452 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9461 00:58:56.522033 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9462 00:58:56.525323 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9463 00:58:56.528730 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9464 00:58:56.532008 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9465 00:58:56.535519 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9466 00:58:56.541982 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9467 00:58:56.545496 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9468 00:58:56.548676 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9469 00:58:56.552104 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9470 00:58:56.558725 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9471 00:58:56.562009 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9472 00:58:56.565348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9473 00:58:56.568815 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9474 00:58:56.575428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9475 00:58:56.578932 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9476 00:58:56.582009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9477 00:58:56.588775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9478 00:58:56.592169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9479 00:58:56.598862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9480 00:58:56.602235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9481 00:58:56.608781 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9482 00:58:56.612272 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9483 00:58:56.615367 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9484 00:58:56.622006 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9485 00:58:56.625271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9486 00:58:56.628587 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9487 00:58:56.635486 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9488 00:58:56.639032 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9489 00:58:56.645418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9490 00:58:56.648713 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9491 00:58:56.652046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9492 00:58:56.658816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9493 00:58:56.662196 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9494 00:58:56.668712 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9495 00:58:56.672159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9496 00:58:56.678884 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9497 00:58:56.682180 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9498 00:58:56.685636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9499 00:58:56.692280 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9500 00:58:56.695621 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9501 00:58:56.698870 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9502 00:58:56.705575 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9503 00:58:56.708786 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9504 00:58:56.715486 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9505 00:58:56.718844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9506 00:58:56.725385 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9507 00:58:56.728762 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9508 00:58:56.732000 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9509 00:58:56.738649 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9510 00:58:56.741982 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9511 00:58:56.748851 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9512 00:58:56.752203 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9513 00:58:56.755514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9514 00:58:56.761949 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9515 00:58:56.765483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9516 00:58:56.772072 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9517 00:58:56.775368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9518 00:58:56.778703 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9519 00:58:56.785392 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9520 00:58:56.788777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9521 00:58:56.795130 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9522 00:58:56.798556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9523 00:58:56.801958 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9524 00:58:56.808394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9525 00:58:56.811800 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9526 00:58:56.818340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9527 00:58:56.821802 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9528 00:58:56.825120 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9529 00:58:56.831654 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9530 00:58:56.834916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9531 00:58:56.841673 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9532 00:58:56.845132 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9533 00:58:56.848489 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9534 00:58:56.855089 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9535 00:58:56.858310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9536 00:58:56.865049 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9537 00:58:56.868106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9538 00:58:56.874808 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9539 00:58:56.878137 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9540 00:58:56.881506 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9541 00:58:56.887847 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9542 00:58:56.891626 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9543 00:58:56.897976 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9544 00:58:56.901458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9545 00:58:56.907969 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9546 00:58:56.911239 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9547 00:58:56.914583 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9548 00:58:56.921285 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9549 00:58:56.924422 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9550 00:58:56.931438 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9551 00:58:56.934500 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9552 00:58:56.937655 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9553 00:58:56.944415 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9554 00:58:56.947591 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9555 00:58:56.954352 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9556 00:58:56.957819 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9557 00:58:56.964151 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9558 00:58:56.967423 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9559 00:58:56.974318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9560 00:58:56.977493 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9561 00:58:56.980820 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9562 00:58:56.987563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9563 00:58:56.991006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9564 00:58:56.997590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9565 00:58:57.000863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9566 00:58:57.004238 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9567 00:58:57.011058 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9568 00:58:57.014186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9569 00:58:57.020823 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9570 00:58:57.024145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9571 00:58:57.030896 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9572 00:58:57.034341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9573 00:58:57.037584 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9574 00:58:57.043993 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9575 00:58:57.047474 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9576 00:58:57.054148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9577 00:58:57.057360 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9578 00:58:57.063910 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9579 00:58:57.067337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9580 00:58:57.073878 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9581 00:58:57.077257 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9582 00:58:57.080570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9583 00:58:57.087315 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9584 00:58:57.090442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9585 00:58:57.097252 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9586 00:58:57.100762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9587 00:58:57.107047 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9588 00:58:57.110595 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9589 00:58:57.113854 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9590 00:58:57.120238 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9591 00:58:57.123621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9592 00:58:57.130455 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9593 00:58:57.133744 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9594 00:58:57.140413 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9595 00:58:57.143723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9596 00:58:57.147243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9597 00:58:57.153864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9598 00:58:57.157142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9599 00:58:57.163739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9600 00:58:57.167312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9601 00:58:57.173553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9602 00:58:57.177034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9603 00:58:57.183742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9604 00:58:57.186979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9605 00:58:57.193677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9606 00:58:57.196904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9607 00:58:57.203763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9608 00:58:57.207181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9609 00:58:57.210176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9610 00:58:57.217088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9611 00:58:57.220256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9612 00:58:57.226850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9613 00:58:57.230267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9614 00:58:57.236737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9615 00:58:57.240088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9616 00:58:57.246546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9617 00:58:57.250019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9618 00:58:57.256696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9619 00:58:57.259766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9620 00:58:57.266453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9621 00:58:57.269948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9622 00:58:57.276456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9623 00:58:57.279902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9624 00:58:57.286467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9625 00:58:57.289874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9626 00:58:57.296654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9627 00:58:57.299636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9628 00:58:57.306220 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9629 00:58:57.306354 INFO: [APUAPC] vio 0
9630 00:58:57.313360 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9631 00:58:57.316818 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9632 00:58:57.319802 INFO: [APUAPC] D0_APC_0: 0x400510
9633 00:58:57.323223 INFO: [APUAPC] D0_APC_1: 0x0
9634 00:58:57.326520 INFO: [APUAPC] D0_APC_2: 0x1540
9635 00:58:57.330164 INFO: [APUAPC] D0_APC_3: 0x0
9636 00:58:57.333244 INFO: [APUAPC] D1_APC_0: 0xffffffff
9637 00:58:57.336448 INFO: [APUAPC] D1_APC_1: 0xffffffff
9638 00:58:57.339907 INFO: [APUAPC] D1_APC_2: 0x3fffff
9639 00:58:57.343134 INFO: [APUAPC] D1_APC_3: 0x0
9640 00:58:57.346653 INFO: [APUAPC] D2_APC_0: 0xffffffff
9641 00:58:57.349816 INFO: [APUAPC] D2_APC_1: 0xffffffff
9642 00:58:57.353235 INFO: [APUAPC] D2_APC_2: 0x3fffff
9643 00:58:57.356478 INFO: [APUAPC] D2_APC_3: 0x0
9644 00:58:57.359845 INFO: [APUAPC] D3_APC_0: 0xffffffff
9645 00:58:57.363155 INFO: [APUAPC] D3_APC_1: 0xffffffff
9646 00:58:57.366417 INFO: [APUAPC] D3_APC_2: 0x3fffff
9647 00:58:57.369593 INFO: [APUAPC] D3_APC_3: 0x0
9648 00:58:57.372916 INFO: [APUAPC] D4_APC_0: 0xffffffff
9649 00:58:57.376367 INFO: [APUAPC] D4_APC_1: 0xffffffff
9650 00:58:57.379545 INFO: [APUAPC] D4_APC_2: 0x3fffff
9651 00:58:57.379630 INFO: [APUAPC] D4_APC_3: 0x0
9652 00:58:57.386346 INFO: [APUAPC] D5_APC_0: 0xffffffff
9653 00:58:57.389805 INFO: [APUAPC] D5_APC_1: 0xffffffff
9654 00:58:57.392831 INFO: [APUAPC] D5_APC_2: 0x3fffff
9655 00:58:57.392920 INFO: [APUAPC] D5_APC_3: 0x0
9656 00:58:57.396155 INFO: [APUAPC] D6_APC_0: 0xffffffff
9657 00:58:57.399480 INFO: [APUAPC] D6_APC_1: 0xffffffff
9658 00:58:57.402881 INFO: [APUAPC] D6_APC_2: 0x3fffff
9659 00:58:57.406099 INFO: [APUAPC] D6_APC_3: 0x0
9660 00:58:57.409634 INFO: [APUAPC] D7_APC_0: 0xffffffff
9661 00:58:57.412898 INFO: [APUAPC] D7_APC_1: 0xffffffff
9662 00:58:57.416095 INFO: [APUAPC] D7_APC_2: 0x3fffff
9663 00:58:57.419445 INFO: [APUAPC] D7_APC_3: 0x0
9664 00:58:57.422694 INFO: [APUAPC] D8_APC_0: 0xffffffff
9665 00:58:57.425976 INFO: [APUAPC] D8_APC_1: 0xffffffff
9666 00:58:57.429423 INFO: [APUAPC] D8_APC_2: 0x3fffff
9667 00:58:57.432748 INFO: [APUAPC] D8_APC_3: 0x0
9668 00:58:57.436070 INFO: [APUAPC] D9_APC_0: 0xffffffff
9669 00:58:57.439267 INFO: [APUAPC] D9_APC_1: 0xffffffff
9670 00:58:57.442678 INFO: [APUAPC] D9_APC_2: 0x3fffff
9671 00:58:57.446003 INFO: [APUAPC] D9_APC_3: 0x0
9672 00:58:57.449250 INFO: [APUAPC] D10_APC_0: 0xffffffff
9673 00:58:57.452586 INFO: [APUAPC] D10_APC_1: 0xffffffff
9674 00:58:57.455857 INFO: [APUAPC] D10_APC_2: 0x3fffff
9675 00:58:57.459264 INFO: [APUAPC] D10_APC_3: 0x0
9676 00:58:57.462582 INFO: [APUAPC] D11_APC_0: 0xffffffff
9677 00:58:57.465786 INFO: [APUAPC] D11_APC_1: 0xffffffff
9678 00:58:57.469195 INFO: [APUAPC] D11_APC_2: 0x3fffff
9679 00:58:57.472430 INFO: [APUAPC] D11_APC_3: 0x0
9680 00:58:57.475713 INFO: [APUAPC] D12_APC_0: 0xffffffff
9681 00:58:57.479237 INFO: [APUAPC] D12_APC_1: 0xffffffff
9682 00:58:57.482356 INFO: [APUAPC] D12_APC_2: 0x3fffff
9683 00:58:57.485664 INFO: [APUAPC] D12_APC_3: 0x0
9684 00:58:57.489245 INFO: [APUAPC] D13_APC_0: 0xffffffff
9685 00:58:57.492544 INFO: [APUAPC] D13_APC_1: 0xffffffff
9686 00:58:57.495664 INFO: [APUAPC] D13_APC_2: 0x3fffff
9687 00:58:57.499040 INFO: [APUAPC] D13_APC_3: 0x0
9688 00:58:57.502422 INFO: [APUAPC] D14_APC_0: 0xffffffff
9689 00:58:57.505694 INFO: [APUAPC] D14_APC_1: 0xffffffff
9690 00:58:57.509031 INFO: [APUAPC] D14_APC_2: 0x3fffff
9691 00:58:57.512269 INFO: [APUAPC] D14_APC_3: 0x0
9692 00:58:57.515586 INFO: [APUAPC] D15_APC_0: 0xffffffff
9693 00:58:57.518917 INFO: [APUAPC] D15_APC_1: 0xffffffff
9694 00:58:57.522227 INFO: [APUAPC] D15_APC_2: 0x3fffff
9695 00:58:57.525586 INFO: [APUAPC] D15_APC_3: 0x0
9696 00:58:57.529538 INFO: [APUAPC] APC_CON: 0x4
9697 00:58:57.532687 INFO: [NOCDAPC] D0_APC_0: 0x0
9698 00:58:57.535717 INFO: [NOCDAPC] D0_APC_1: 0x0
9699 00:58:57.538862 INFO: [NOCDAPC] D1_APC_0: 0x0
9700 00:58:57.542235 INFO: [NOCDAPC] D1_APC_1: 0xfff
9701 00:58:57.545410 INFO: [NOCDAPC] D2_APC_0: 0x0
9702 00:58:57.545490 INFO: [NOCDAPC] D2_APC_1: 0xfff
9703 00:58:57.548856 INFO: [NOCDAPC] D3_APC_0: 0x0
9704 00:58:57.552141 INFO: [NOCDAPC] D3_APC_1: 0xfff
9705 00:58:57.555362 INFO: [NOCDAPC] D4_APC_0: 0x0
9706 00:58:57.558673 INFO: [NOCDAPC] D4_APC_1: 0xfff
9707 00:58:57.562254 INFO: [NOCDAPC] D5_APC_0: 0x0
9708 00:58:57.565397 INFO: [NOCDAPC] D5_APC_1: 0xfff
9709 00:58:57.568722 INFO: [NOCDAPC] D6_APC_0: 0x0
9710 00:58:57.572218 INFO: [NOCDAPC] D6_APC_1: 0xfff
9711 00:58:57.575383 INFO: [NOCDAPC] D7_APC_0: 0x0
9712 00:58:57.578641 INFO: [NOCDAPC] D7_APC_1: 0xfff
9713 00:58:57.578770 INFO: [NOCDAPC] D8_APC_0: 0x0
9714 00:58:57.582076 INFO: [NOCDAPC] D8_APC_1: 0xfff
9715 00:58:57.585236 INFO: [NOCDAPC] D9_APC_0: 0x0
9716 00:58:57.588921 INFO: [NOCDAPC] D9_APC_1: 0xfff
9717 00:58:57.591966 INFO: [NOCDAPC] D10_APC_0: 0x0
9718 00:58:57.595436 INFO: [NOCDAPC] D10_APC_1: 0xfff
9719 00:58:57.598746 INFO: [NOCDAPC] D11_APC_0: 0x0
9720 00:58:57.602351 INFO: [NOCDAPC] D11_APC_1: 0xfff
9721 00:58:57.605526 INFO: [NOCDAPC] D12_APC_0: 0x0
9722 00:58:57.608586 INFO: [NOCDAPC] D12_APC_1: 0xfff
9723 00:58:57.612170 INFO: [NOCDAPC] D13_APC_0: 0x0
9724 00:58:57.615286 INFO: [NOCDAPC] D13_APC_1: 0xfff
9725 00:58:57.618500 INFO: [NOCDAPC] D14_APC_0: 0x0
9726 00:58:57.618607 INFO: [NOCDAPC] D14_APC_1: 0xfff
9727 00:58:57.621886 INFO: [NOCDAPC] D15_APC_0: 0x0
9728 00:58:57.625281 INFO: [NOCDAPC] D15_APC_1: 0xfff
9729 00:58:57.628943 INFO: [NOCDAPC] APC_CON: 0x4
9730 00:58:57.632041 INFO: [APUAPC] set_apusys_apc done
9731 00:58:57.635293 INFO: [DEVAPC] devapc_init done
9732 00:58:57.638813 INFO: GICv3 without legacy support detected.
9733 00:58:57.645212 INFO: ARM GICv3 driver initialized in EL3
9734 00:58:57.648533 INFO: Maximum SPI INTID supported: 639
9735 00:58:57.651998 INFO: BL31: Initializing runtime services
9736 00:58:57.658522 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9737 00:58:57.661711 INFO: SPM: enable CPC mode
9738 00:58:57.665039 INFO: mcdi ready for mcusys-off-idle and system suspend
9739 00:58:57.668333 INFO: BL31: Preparing for EL3 exit to normal world
9740 00:58:57.675041 INFO: Entry point address = 0x80000000
9741 00:58:57.675142 INFO: SPSR = 0x8
9742 00:58:57.681800
9743 00:58:57.681908
9744 00:58:57.681970
9745 00:58:57.684827 Starting depthcharge on Spherion...
9746 00:58:57.684906
9747 00:58:57.684966 Wipe memory regions:
9748 00:58:57.685021
9749 00:58:57.685599 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9750 00:58:57.685692 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9751 00:58:57.685770 Setting prompt string to ['asurada:']
9752 00:58:57.685839 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9753 00:58:57.687909 [0x00000040000000, 0x00000054600000)
9754 00:58:57.810481
9755 00:58:57.810606 [0x00000054660000, 0x00000080000000)
9756 00:58:58.071049
9757 00:58:58.071291 [0x000000821a7280, 0x000000ffe64000)
9758 00:58:58.815938
9759 00:58:58.816074 [0x00000100000000, 0x00000140000000)
9760 00:58:59.196907
9761 00:58:59.200097 Initializing XHCI USB controller at 0x11200000.
9762 00:59:00.238479
9763 00:59:00.241931 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9764 00:59:00.242014
9765 00:59:00.242074
9766 00:59:00.242344 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9768 00:59:00.342696 asurada: tftpboot 192.168.201.1 14368627/tftp-deploy-szphy0p4/kernel/image.itb 14368627/tftp-deploy-szphy0p4/kernel/cmdline
9769 00:59:00.342911 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9770 00:59:00.342989 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
9771 00:59:00.347025 tftpboot 192.168.201.1 14368627/tftp-deploy-szphy0p4/kernel/image.ittp-deploy-szphy0p4/kernel/cmdline
9772 00:59:00.347107
9773 00:59:00.347166 Waiting for link
9774 00:59:00.505336
9775 00:59:00.505472 R8152: Initializing
9776 00:59:00.505532
9777 00:59:00.508464 Version 9 (ocp_data = 6010)
9778 00:59:00.508549
9779 00:59:00.511775 R8152: Done initializing
9780 00:59:00.511859
9781 00:59:00.511919 Adding net device
9782 00:59:02.526059
9783 00:59:02.526200 done.
9784 00:59:02.526303
9785 00:59:02.526360 MAC: 00:e0:4c:68:03:bd
9786 00:59:02.526417
9787 00:59:02.529368 Sending DHCP discover... done.
9788 00:59:02.529445
9789 00:59:02.532625 Waiting for reply... done.
9790 00:59:02.532705
9791 00:59:02.536060 Sending DHCP request... done.
9792 00:59:02.536140
9793 00:59:02.536199 Waiting for reply... done.
9794 00:59:02.536255
9795 00:59:02.539059 My ip is 192.168.201.16
9796 00:59:02.539136
9797 00:59:02.542435 The DHCP server ip is 192.168.201.1
9798 00:59:02.542513
9799 00:59:02.545748 TFTP server IP predefined by user: 192.168.201.1
9800 00:59:02.545826
9801 00:59:02.552367 Bootfile predefined by user: 14368627/tftp-deploy-szphy0p4/kernel/image.itb
9802 00:59:02.552451
9803 00:59:02.556081 Sending tftp read request... done.
9804 00:59:02.556159
9805 00:59:02.559166 Waiting for the transfer...
9806 00:59:02.559248
9807 00:59:02.856166 00000000 ################################################################
9808 00:59:02.856299
9809 00:59:03.154450 00080000 ################################################################
9810 00:59:03.154580
9811 00:59:03.451664 00100000 ################################################################
9812 00:59:03.451799
9813 00:59:03.731030 00180000 ################################################################
9814 00:59:03.731164
9815 00:59:03.982771 00200000 ################################################################
9816 00:59:03.982907
9817 00:59:04.249118 00280000 ################################################################
9818 00:59:04.249249
9819 00:59:04.524389 00300000 ################################################################
9820 00:59:04.524522
9821 00:59:04.779203 00380000 ################################################################
9822 00:59:04.779334
9823 00:59:05.035422 00400000 ################################################################
9824 00:59:05.035554
9825 00:59:05.302454 00480000 ################################################################
9826 00:59:05.302586
9827 00:59:05.563131 00500000 ################################################################
9828 00:59:05.563264
9829 00:59:05.830226 00580000 ################################################################
9830 00:59:05.830370
9831 00:59:06.101112 00600000 ################################################################
9832 00:59:06.101241
9833 00:59:06.384688 00680000 ################################################################
9834 00:59:06.384913
9835 00:59:06.675586 00700000 ################################################################
9836 00:59:06.675719
9837 00:59:06.960184 00780000 ################################################################
9838 00:59:06.960315
9839 00:59:07.247862 00800000 ################################################################
9840 00:59:07.247982
9841 00:59:07.508136 00880000 ################################################################
9842 00:59:07.508284
9843 00:59:07.758734 00900000 ################################################################
9844 00:59:07.758887
9845 00:59:08.016300 00980000 ################################################################
9846 00:59:08.016424
9847 00:59:08.296861 00a00000 ################################################################
9848 00:59:08.296983
9849 00:59:08.547436 00a80000 ################################################################
9850 00:59:08.547589
9851 00:59:08.820275 00b00000 ################################################################
9852 00:59:08.820424
9853 00:59:09.101349 00b80000 ################################################################
9854 00:59:09.101574
9855 00:59:09.343446 00c00000 ################################################################
9856 00:59:09.343577
9857 00:59:09.586579 00c80000 ################################################################
9858 00:59:09.586710
9859 00:59:09.848324 00d00000 ################################################################
9860 00:59:09.848450
9861 00:59:10.108098 00d80000 ################################################################
9862 00:59:10.108224
9863 00:59:10.365721 00e00000 ################################################################
9864 00:59:10.365843
9865 00:59:10.636224 00e80000 ################################################################
9866 00:59:10.636348
9867 00:59:10.912312 00f00000 ################################################################
9868 00:59:10.912442
9869 00:59:11.163926 00f80000 ################################################################
9870 00:59:11.164050
9871 00:59:11.440262 01000000 ################################################################
9872 00:59:11.440383
9873 00:59:11.719041 01080000 ################################################################
9874 00:59:11.719163
9875 00:59:11.998115 01100000 ################################################################
9876 00:59:11.998276
9877 00:59:12.266165 01180000 ################################################################
9878 00:59:12.266298
9879 00:59:12.518837 01200000 ################################################################
9880 00:59:12.518960
9881 00:59:12.802110 01280000 ################################################################
9882 00:59:12.802271
9883 00:59:13.054542 01300000 ################################################################
9884 00:59:13.054667
9885 00:59:13.309273 01380000 ################################################################
9886 00:59:13.309396
9887 00:59:13.561138 01400000 ################################################################
9888 00:59:13.561263
9889 00:59:13.818200 01480000 ################################################################
9890 00:59:13.818356
9891 00:59:14.094723 01500000 ################################################################
9892 00:59:14.094849
9893 00:59:14.372322 01580000 ################################################################
9894 00:59:14.372445
9895 00:59:14.638409 01600000 ################################################################
9896 00:59:14.638534
9897 00:59:14.898115 01680000 ################################################################
9898 00:59:14.898281
9899 00:59:15.168301 01700000 ################################################################
9900 00:59:15.168426
9901 00:59:15.438415 01780000 ################################################################
9902 00:59:15.438541
9903 00:59:15.708858 01800000 ################################################################
9904 00:59:15.709025
9905 00:59:15.984638 01880000 ################################################################
9906 00:59:15.984767
9907 00:59:16.261521 01900000 ################################################################
9908 00:59:16.261646
9909 00:59:16.550015 01980000 ################################################################
9910 00:59:16.550144
9911 00:59:16.834786 01a00000 ################################################################
9912 00:59:16.834913
9913 00:59:17.101026 01a80000 ################################################################
9914 00:59:17.101156
9915 00:59:17.357397 01b00000 ################################################################
9916 00:59:17.357522
9917 00:59:17.622469 01b80000 ################################################################
9918 00:59:17.622605
9919 00:59:17.903405 01c00000 ################################################################
9920 00:59:17.903532
9921 00:59:18.163753 01c80000 ################################################################
9922 00:59:18.163894
9923 00:59:18.428137 01d00000 ################################################################
9924 00:59:18.428267
9925 00:59:18.681301 01d80000 ################################################################
9926 00:59:18.681426
9927 00:59:18.938868 01e00000 ################################################################
9928 00:59:18.939005
9929 00:59:19.201599 01e80000 ################################################################
9930 00:59:19.201721
9931 00:59:19.473929 01f00000 ################################################################
9932 00:59:19.474053
9933 00:59:19.760895 01f80000 ################################################################
9934 00:59:19.761018
9935 00:59:20.007338 02000000 ################################################################
9936 00:59:20.007464
9937 00:59:20.230561 02080000 ########################################################## done.
9938 00:59:20.230681
9939 00:59:20.233995 The bootfile was 34548330 bytes long.
9940 00:59:20.234079
9941 00:59:20.237173 Sending tftp read request... done.
9942 00:59:20.237268
9943 00:59:20.240788 Waiting for the transfer...
9944 00:59:20.240938
9945 00:59:20.241017 00000000 # done.
9946 00:59:20.241105
9947 00:59:20.250130 Command line loaded dynamically from TFTP file: 14368627/tftp-deploy-szphy0p4/kernel/cmdline
9948 00:59:20.250259
9949 00:59:20.263734 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
9950 00:59:20.263947
9951 00:59:20.264102 Loading FIT.
9952 00:59:20.264239
9953 00:59:20.266854 Image ramdisk-1 has 21373997 bytes.
9954 00:59:20.266998
9955 00:59:20.270128 Image fdt-1 has 47258 bytes.
9956 00:59:20.270380
9957 00:59:20.274051 Image kernel-1 has 13125045 bytes.
9958 00:59:20.274336
9959 00:59:20.283761 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9960 00:59:20.284122
9961 00:59:20.300293 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9962 00:59:20.300848
9963 00:59:20.306521 Choosing best match conf-1 for compat google,spherion-rev3.
9964 00:59:20.307033
9965 00:59:20.310276 Connected to device vid:did:rid of 1ae0:0028:00
9966 00:59:20.321173
9967 00:59:20.324290 tpm_get_response: command 0x17b, return code 0x0
9968 00:59:20.324733
9969 00:59:20.327696 ec_init: CrosEC protocol v3 supported (256, 248)
9970 00:59:20.331420
9971 00:59:20.334742 tpm_cleanup: add release locality here.
9972 00:59:20.335195
9973 00:59:20.335623 Shutting down all USB controllers.
9974 00:59:20.338038
9975 00:59:20.338553 Removing current net device
9976 00:59:20.338983
9977 00:59:20.345336 Exiting depthcharge with code 4 at timestamp: 50909030
9978 00:59:20.345885
9979 00:59:20.348239 LZMA decompressing kernel-1 to 0x821a6718
9980 00:59:20.348802
9981 00:59:20.351277 LZMA decompressing kernel-1 to 0x40000000
9982 00:59:21.966875
9983 00:59:21.967461 jumping to kernel
9984 00:59:21.969286 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
9985 00:59:21.969839 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
9986 00:59:21.970329 Setting prompt string to ['Linux version [0-9]']
9987 00:59:21.970748 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9988 00:59:21.971171 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9989 00:59:22.017451
9990 00:59:22.020754 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9991 00:59:22.024597 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
9992 00:59:22.025232 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
9993 00:59:22.025661 Setting prompt string to []
9994 00:59:22.026171 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
9995 00:59:22.026643 Using line separator: #'\n'#
9996 00:59:22.027026 No login prompt set.
9997 00:59:22.027450 Parsing kernel messages
9998 00:59:22.027827 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
9999 00:59:22.028453 [login-action] Waiting for messages, (timeout 00:04:04)
10000 00:59:22.029041 Waiting using forced prompt support (timeout 00:02:02)
10001 00:59:22.043537 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10002 00:59:22.046764 [ 0.000000] random: crng init done
10003 00:59:22.053739 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10004 00:59:22.057225 [ 0.000000] efi: UEFI not found.
10005 00:59:22.063648 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10006 00:59:22.073613 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10007 00:59:22.079985 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10008 00:59:22.089800 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10009 00:59:22.096665 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10010 00:59:22.103132 [ 0.000000] printk: bootconsole [mtk8250] enabled
10011 00:59:22.109769 [ 0.000000] NUMA: No NUMA configuration found
10012 00:59:22.116300 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10013 00:59:22.119450 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10014 00:59:22.123067 [ 0.000000] Zone ranges:
10015 00:59:22.129547 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10016 00:59:22.132811 [ 0.000000] DMA32 empty
10017 00:59:22.139283 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10018 00:59:22.142756 [ 0.000000] Movable zone start for each node
10019 00:59:22.146032 [ 0.000000] Early memory node ranges
10020 00:59:22.152688 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10021 00:59:22.159359 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10022 00:59:22.166173 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10023 00:59:22.172929 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10024 00:59:22.179020 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10025 00:59:22.186048 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10026 00:59:22.215738 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10027 00:59:22.222414 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10028 00:59:22.229009 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10029 00:59:22.232133 [ 0.000000] psci: probing for conduit method from DT.
10030 00:59:22.238433 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10031 00:59:22.241796 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10032 00:59:22.248526 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10033 00:59:22.251980 [ 0.000000] psci: SMC Calling Convention v1.2
10034 00:59:22.258511 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10035 00:59:22.261613 [ 0.000000] Detected VIPT I-cache on CPU0
10036 00:59:22.268708 [ 0.000000] CPU features: detected: GIC system register CPU interface
10037 00:59:22.274908 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10038 00:59:22.281376 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10039 00:59:22.288084 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10040 00:59:22.298191 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10041 00:59:22.304537 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10042 00:59:22.307816 [ 0.000000] alternatives: applying boot alternatives
10043 00:59:22.314928 [ 0.000000] Fallback order for Node 0: 0
10044 00:59:22.321081 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10045 00:59:22.324635 [ 0.000000] Policy zone: Normal
10046 00:59:22.337744 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10047 00:59:22.347606 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10048 00:59:22.358526 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10049 00:59:22.368071 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10050 00:59:22.374973 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10051 00:59:22.378362 <6>[ 0.000000] software IO TLB: area num 8.
10052 00:59:22.434927 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10053 00:59:22.515219 <6>[ 0.000000] Memory: 3828772K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 329692K reserved, 32768K cma-reserved)
10054 00:59:22.521753 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10055 00:59:22.528581 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10056 00:59:22.531302 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10057 00:59:22.538062 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10058 00:59:22.547139 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10059 00:59:22.548121 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10060 00:59:22.558088 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10061 00:59:22.564671 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10062 00:59:22.571801 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10063 00:59:22.577560 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10064 00:59:22.581389 <6>[ 0.000000] GICv3: 608 SPIs implemented
10065 00:59:22.584775 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10066 00:59:22.591215 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10067 00:59:22.594362 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10068 00:59:22.601030 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10069 00:59:22.614142 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10070 00:59:22.627782 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10071 00:59:22.634076 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10072 00:59:22.641649 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10073 00:59:22.654759 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10074 00:59:22.661127 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10075 00:59:22.667731 <6>[ 0.009222] Console: colour dummy device 80x25
10076 00:59:22.678047 <6>[ 0.013947] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10077 00:59:22.684530 <6>[ 0.024388] pid_max: default: 32768 minimum: 301
10078 00:59:22.687740 <6>[ 0.029259] LSM: Security Framework initializing
10079 00:59:22.694427 <6>[ 0.034202] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10080 00:59:22.704082 <6>[ 0.041850] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10081 00:59:22.710722 <6>[ 0.051124] cblist_init_generic: Setting adjustable number of callback queues.
10082 00:59:22.717629 <6>[ 0.058564] cblist_init_generic: Setting shift to 3 and lim to 1.
10083 00:59:22.727634 <6>[ 0.064903] cblist_init_generic: Setting adjustable number of callback queues.
10084 00:59:22.734260 <6>[ 0.072352] cblist_init_generic: Setting shift to 3 and lim to 1.
10085 00:59:22.737335 <6>[ 0.078790] rcu: Hierarchical SRCU implementation.
10086 00:59:22.744273 <6>[ 0.083836] rcu: Max phase no-delay instances is 1000.
10087 00:59:22.750552 <6>[ 0.090890] EFI services will not be available.
10088 00:59:22.753951 <6>[ 0.095842] smp: Bringing up secondary CPUs ...
10089 00:59:22.761788 <6>[ 0.100894] Detected VIPT I-cache on CPU1
10090 00:59:22.768769 <6>[ 0.100963] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10091 00:59:22.775266 <6>[ 0.100995] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10092 00:59:22.778318 <6>[ 0.101328] Detected VIPT I-cache on CPU2
10093 00:59:22.785267 <6>[ 0.101380] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10094 00:59:22.795144 <6>[ 0.101399] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10095 00:59:22.798264 <6>[ 0.101656] Detected VIPT I-cache on CPU3
10096 00:59:22.805050 <6>[ 0.101704] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10097 00:59:22.811786 <6>[ 0.101719] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10098 00:59:22.814842 <6>[ 0.102023] CPU features: detected: Spectre-v4
10099 00:59:22.821347 <6>[ 0.102029] CPU features: detected: Spectre-BHB
10100 00:59:22.824820 <6>[ 0.102034] Detected PIPT I-cache on CPU4
10101 00:59:22.831545 <6>[ 0.102092] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10102 00:59:22.838052 <6>[ 0.102108] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10103 00:59:22.844716 <6>[ 0.102399] Detected PIPT I-cache on CPU5
10104 00:59:22.851392 <6>[ 0.102460] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10105 00:59:22.858058 <6>[ 0.102476] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10106 00:59:22.861225 <6>[ 0.102756] Detected PIPT I-cache on CPU6
10107 00:59:22.867795 <6>[ 0.102819] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10108 00:59:22.874445 <6>[ 0.102835] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10109 00:59:22.881128 <6>[ 0.103134] Detected PIPT I-cache on CPU7
10110 00:59:22.887981 <6>[ 0.103199] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10111 00:59:22.894312 <6>[ 0.103215] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10112 00:59:22.897393 <6>[ 0.103261] smp: Brought up 1 node, 8 CPUs
10113 00:59:22.904183 <6>[ 0.244497] SMP: Total of 8 processors activated.
10114 00:59:22.907377 <6>[ 0.249448] CPU features: detected: 32-bit EL0 Support
10115 00:59:22.917216 <6>[ 0.254811] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10116 00:59:22.924327 <6>[ 0.263611] CPU features: detected: Common not Private translations
10117 00:59:22.927715 <6>[ 0.270087] CPU features: detected: CRC32 instructions
10118 00:59:22.934100 <6>[ 0.275439] CPU features: detected: RCpc load-acquire (LDAPR)
10119 00:59:22.940903 <6>[ 0.281399] CPU features: detected: LSE atomic instructions
10120 00:59:22.947486 <6>[ 0.287180] CPU features: detected: Privileged Access Never
10121 00:59:22.950552 <6>[ 0.292960] CPU features: detected: RAS Extension Support
10122 00:59:22.960766 <6>[ 0.298568] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10123 00:59:22.963914 <6>[ 0.305834] CPU: All CPU(s) started at EL2
10124 00:59:22.970461 <6>[ 0.310151] alternatives: applying system-wide alternatives
10125 00:59:22.978747 <6>[ 0.320144] devtmpfs: initialized
10126 00:59:22.993386 <6>[ 0.328257] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10127 00:59:22.999722 <6>[ 0.338217] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10128 00:59:23.006498 <6>[ 0.346451] pinctrl core: initialized pinctrl subsystem
10129 00:59:23.009649 <6>[ 0.353134] DMI not present or invalid.
10130 00:59:23.016360 <6>[ 0.357538] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10131 00:59:23.026279 <6>[ 0.364398] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10132 00:59:23.032934 <6>[ 0.371846] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10133 00:59:23.042749 <6>[ 0.379938] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10134 00:59:23.046719 <6>[ 0.388094] audit: initializing netlink subsys (disabled)
10135 00:59:23.056175 <5>[ 0.393776] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10136 00:59:23.062956 <6>[ 0.394453] thermal_sys: Registered thermal governor 'step_wise'
10137 00:59:23.069430 <6>[ 0.401742] thermal_sys: Registered thermal governor 'power_allocator'
10138 00:59:23.072859 <6>[ 0.407996] cpuidle: using governor menu
10139 00:59:23.079362 <6>[ 0.418957] NET: Registered PF_QIPCRTR protocol family
10140 00:59:23.085973 <6>[ 0.424432] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10141 00:59:23.092218 <6>[ 0.431533] ASID allocator initialised with 32768 entries
10142 00:59:23.095297 <6>[ 0.438093] Serial: AMBA PL011 UART driver
10143 00:59:23.105345 <4>[ 0.446899] Trying to register duplicate clock ID: 134
10144 00:59:23.163546 <6>[ 0.508411] KASLR enabled
10145 00:59:23.177989 <6>[ 0.516131] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10146 00:59:23.185181 <6>[ 0.523145] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10147 00:59:23.191286 <6>[ 0.529632] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10148 00:59:23.198064 <6>[ 0.536637] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10149 00:59:23.204784 <6>[ 0.543126] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10150 00:59:23.211368 <6>[ 0.550130] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10151 00:59:23.217770 <6>[ 0.556618] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10152 00:59:23.224003 <6>[ 0.563622] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10153 00:59:23.227601 <6>[ 0.571134] ACPI: Interpreter disabled.
10154 00:59:23.236593 <6>[ 0.577551] iommu: Default domain type: Translated
10155 00:59:23.242780 <6>[ 0.582662] iommu: DMA domain TLB invalidation policy: strict mode
10156 00:59:23.245910 <5>[ 0.589320] SCSI subsystem initialized
10157 00:59:23.253103 <6>[ 0.593479] usbcore: registered new interface driver usbfs
10158 00:59:23.259928 <6>[ 0.599212] usbcore: registered new interface driver hub
10159 00:59:23.262579 <6>[ 0.604764] usbcore: registered new device driver usb
10160 00:59:23.269606 <6>[ 0.610860] pps_core: LinuxPPS API ver. 1 registered
10161 00:59:23.279237 <6>[ 0.616055] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10162 00:59:23.282854 <6>[ 0.625402] PTP clock support registered
10163 00:59:23.286257 <6>[ 0.629644] EDAC MC: Ver: 3.0.0
10164 00:59:23.294045 <6>[ 0.634790] FPGA manager framework
10165 00:59:23.297427 <6>[ 0.638474] Advanced Linux Sound Architecture Driver Initialized.
10166 00:59:23.300950 <6>[ 0.645242] vgaarb: loaded
10167 00:59:23.306951 <6>[ 0.648392] clocksource: Switched to clocksource arch_sys_counter
10168 00:59:23.313816 <5>[ 0.654829] VFS: Disk quotas dquot_6.6.0
10169 00:59:23.320524 <6>[ 0.659013] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10170 00:59:23.323606 <6>[ 0.666203] pnp: PnP ACPI: disabled
10171 00:59:23.331661 <6>[ 0.672934] NET: Registered PF_INET protocol family
10172 00:59:23.338108 <6>[ 0.678312] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10173 00:59:23.350567 <6>[ 0.688328] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10174 00:59:23.360630 <6>[ 0.697118] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10175 00:59:23.366916 <6>[ 0.705086] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10176 00:59:23.373423 <6>[ 0.713491] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10177 00:59:23.384388 <6>[ 0.722145] TCP: Hash tables configured (established 32768 bind 32768)
10178 00:59:23.391067 <6>[ 0.728945] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10179 00:59:23.397599 <6>[ 0.735965] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10180 00:59:23.404516 <6>[ 0.743487] NET: Registered PF_UNIX/PF_LOCAL protocol family
10181 00:59:23.410858 <6>[ 0.749610] RPC: Registered named UNIX socket transport module.
10182 00:59:23.413934 <6>[ 0.755767] RPC: Registered udp transport module.
10183 00:59:23.420391 <6>[ 0.760699] RPC: Registered tcp transport module.
10184 00:59:23.427263 <6>[ 0.765632] RPC: Registered tcp NFSv4.1 backchannel transport module.
10185 00:59:23.430675 <6>[ 0.772300] PCI: CLS 0 bytes, default 64
10186 00:59:23.433930 <6>[ 0.776700] Unpacking initramfs...
10187 00:59:23.443433 <6>[ 0.780411] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10188 00:59:23.450314 <6>[ 0.789037] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10189 00:59:23.457020 <6>[ 0.797846] kvm [1]: IPA Size Limit: 40 bits
10190 00:59:23.460233 <6>[ 0.802371] kvm [1]: GICv3: no GICV resource entry
10191 00:59:23.466555 <6>[ 0.807393] kvm [1]: disabling GICv2 emulation
10192 00:59:23.473459 <6>[ 0.812082] kvm [1]: GIC system register CPU interface enabled
10193 00:59:23.476450 <6>[ 0.818248] kvm [1]: vgic interrupt IRQ18
10194 00:59:23.482954 <6>[ 0.822609] kvm [1]: VHE mode initialized successfully
10195 00:59:23.486422 <5>[ 0.829015] Initialise system trusted keyrings
10196 00:59:23.492964 <6>[ 0.833837] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10197 00:59:23.502661 <6>[ 0.843892] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10198 00:59:23.508970 <5>[ 0.850287] NFS: Registering the id_resolver key type
10199 00:59:23.512403 <5>[ 0.855583] Key type id_resolver registered
10200 00:59:23.519184 <5>[ 0.859998] Key type id_legacy registered
10201 00:59:23.526326 <6>[ 0.864276] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10202 00:59:23.532363 <6>[ 0.871198] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10203 00:59:23.538430 <6>[ 0.878933] 9p: Installing v9fs 9p2000 file system support
10204 00:59:23.575583 <5>[ 0.917039] Key type asymmetric registered
10205 00:59:23.578914 <5>[ 0.921370] Asymmetric key parser 'x509' registered
10206 00:59:23.588999 <6>[ 0.926519] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10207 00:59:23.592123 <6>[ 0.934134] io scheduler mq-deadline registered
10208 00:59:23.595707 <6>[ 0.938896] io scheduler kyber registered
10209 00:59:23.614445 <6>[ 0.955892] EINJ: ACPI disabled.
10210 00:59:23.647177 <4>[ 0.981902] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10211 00:59:23.657268 <4>[ 0.992547] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10212 00:59:23.672503 <6>[ 1.013723] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10213 00:59:23.680279 <6>[ 1.021824] printk: console [ttyS0] disabled
10214 00:59:23.708765 <6>[ 1.046453] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10215 00:59:23.715130 <6>[ 1.055930] printk: console [ttyS0] enabled
10216 00:59:23.718994 <6>[ 1.055930] printk: console [ttyS0] enabled
10217 00:59:23.725047 <6>[ 1.064825] printk: bootconsole [mtk8250] disabled
10218 00:59:23.728591 <6>[ 1.064825] printk: bootconsole [mtk8250] disabled
10219 00:59:23.734992 <6>[ 1.076018] SuperH (H)SCI(F) driver initialized
10220 00:59:23.738665 <6>[ 1.081277] msm_serial: driver initialized
10221 00:59:23.752425 <6>[ 1.090288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10222 00:59:23.762088 <6>[ 1.098836] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10223 00:59:23.768644 <6>[ 1.107378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10224 00:59:23.779155 <6>[ 1.116010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10225 00:59:23.789167 <6>[ 1.124719] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10226 00:59:23.795219 <6>[ 1.133436] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10227 00:59:23.805378 <6>[ 1.141978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10228 00:59:23.812138 <6>[ 1.150782] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10229 00:59:23.821960 <6>[ 1.159327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10230 00:59:23.833834 <6>[ 1.175197] loop: module loaded
10231 00:59:23.841071 <6>[ 1.181116] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10232 00:59:23.862866 <4>[ 1.204510] mtk-pmic-keys: Failed to locate of_node [id: -1]
10233 00:59:23.870549 <6>[ 1.211562] megasas: 07.719.03.00-rc1
10234 00:59:23.879911 <6>[ 1.221289] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10235 00:59:23.886657 <6>[ 1.227818] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10236 00:59:23.903532 <6>[ 1.244486] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10237 00:59:23.959376 <6>[ 1.293876] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10238 00:59:24.334834 <6>[ 1.676191] Freeing initrd memory: 20868K
10239 00:59:24.350738 <6>[ 1.692030] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10240 00:59:24.361667 <6>[ 1.703023] tun: Universal TUN/TAP device driver, 1.6
10241 00:59:24.364640 <6>[ 1.709107] thunder_xcv, ver 1.0
10242 00:59:24.368028 <6>[ 1.712613] thunder_bgx, ver 1.0
10243 00:59:24.371211 <6>[ 1.716122] nicpf, ver 1.0
10244 00:59:24.382051 <6>[ 1.720139] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10245 00:59:24.385459 <6>[ 1.727616] hns3: Copyright (c) 2017 Huawei Corporation.
10246 00:59:24.392413 <6>[ 1.733203] hclge is initializing
10247 00:59:24.395003 <6>[ 1.736784] e1000: Intel(R) PRO/1000 Network Driver
10248 00:59:24.401906 <6>[ 1.741913] e1000: Copyright (c) 1999-2006 Intel Corporation.
10249 00:59:24.405471 <6>[ 1.747929] e1000e: Intel(R) PRO/1000 Network Driver
10250 00:59:24.412192 <6>[ 1.753144] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10251 00:59:24.418442 <6>[ 1.759330] igb: Intel(R) Gigabit Ethernet Network Driver
10252 00:59:24.425098 <6>[ 1.764980] igb: Copyright (c) 2007-2014 Intel Corporation.
10253 00:59:24.432093 <6>[ 1.770816] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10254 00:59:24.438308 <6>[ 1.777333] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10255 00:59:24.441519 <6>[ 1.783798] sky2: driver version 1.30
10256 00:59:24.447962 <6>[ 1.788729] usbcore: registered new device driver r8152-cfgselector
10257 00:59:24.454700 <6>[ 1.795268] usbcore: registered new interface driver r8152
10258 00:59:24.461671 <6>[ 1.801085] VFIO - User Level meta-driver version: 0.3
10259 00:59:24.467964 <6>[ 1.809335] usbcore: registered new interface driver usb-storage
10260 00:59:24.474872 <6>[ 1.815782] usbcore: registered new device driver onboard-usb-hub
10261 00:59:24.483738 <6>[ 1.824948] mt6397-rtc mt6359-rtc: registered as rtc0
10262 00:59:24.494042 <6>[ 1.830416] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:59:24 UTC (1718499564)
10263 00:59:24.497145 <6>[ 1.839981] i2c_dev: i2c /dev entries driver
10264 00:59:24.510626 <4>[ 1.852023] cpu cpu0: supply cpu not found, using dummy regulator
10265 00:59:24.517138 <4>[ 1.858444] cpu cpu1: supply cpu not found, using dummy regulator
10266 00:59:24.523542 <4>[ 1.864849] cpu cpu2: supply cpu not found, using dummy regulator
10267 00:59:24.530560 <4>[ 1.871288] cpu cpu3: supply cpu not found, using dummy regulator
10268 00:59:24.537450 <4>[ 1.877685] cpu cpu4: supply cpu not found, using dummy regulator
10269 00:59:24.543598 <4>[ 1.884083] cpu cpu5: supply cpu not found, using dummy regulator
10270 00:59:24.550317 <4>[ 1.890490] cpu cpu6: supply cpu not found, using dummy regulator
10271 00:59:24.556712 <4>[ 1.896889] cpu cpu7: supply cpu not found, using dummy regulator
10272 00:59:24.576104 <6>[ 1.917534] cpu cpu0: EM: created perf domain
10273 00:59:24.579272 <6>[ 1.922443] cpu cpu4: EM: created perf domain
10274 00:59:24.586522 <6>[ 1.927992] sdhci: Secure Digital Host Controller Interface driver
10275 00:59:24.593210 <6>[ 1.934421] sdhci: Copyright(c) Pierre Ossman
10276 00:59:24.599824 <6>[ 1.939330] Synopsys Designware Multimedia Card Interface Driver
10277 00:59:24.606497 <6>[ 1.945927] sdhci-pltfm: SDHCI platform and OF driver helper
10278 00:59:24.609929 <6>[ 1.946088] mmc0: CQHCI version 5.10
10279 00:59:24.616482 <6>[ 1.955884] ledtrig-cpu: registered to indicate activity on CPUs
10280 00:59:24.622897 <6>[ 1.962968] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10281 00:59:24.629785 <6>[ 1.969995] usbcore: registered new interface driver usbhid
10282 00:59:24.633047 <6>[ 1.975817] usbhid: USB HID core driver
10283 00:59:24.639748 <6>[ 1.980018] spi_master spi0: will run message pump with realtime priority
10284 00:59:24.688392 <6>[ 2.022881] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10285 00:59:24.706824 <6>[ 2.037848] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10286 00:59:24.710306 <3>[ 2.043493] mtk-msdc 11f60000.mmc: phase error: [map:0]
10287 00:59:24.716741 <3>[ 2.056736] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10288 00:59:24.723066 <3>[ 2.062670] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10289 00:59:24.726845 <3>[ 2.069030] mmc0: error -5 whilst initialising MMC card
10290 00:59:24.733222 <6>[ 2.069146] cros-ec-spi spi0.0: Chrome EC device registered
10291 00:59:24.754587 <6>[ 2.092671] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10292 00:59:24.761765 <6>[ 2.103118] NET: Registered PF_PACKET protocol family
10293 00:59:24.764726 <6>[ 2.108504] 9pnet: Installing 9P2000 support
10294 00:59:24.771560 <5>[ 2.113065] Key type dns_resolver registered
10295 00:59:24.775061 <6>[ 2.117997] registered taskstats version 1
10296 00:59:24.781755 <5>[ 2.122375] Loading compiled-in X.509 certificates
10297 00:59:24.811006 <4>[ 2.145663] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10298 00:59:24.821042 <4>[ 2.156592] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10299 00:59:24.838395 <6>[ 2.180060] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10300 00:59:24.845460 <6>[ 2.186969] xhci-mtk 11200000.usb: xHCI Host Controller
10301 00:59:24.851779 <6>[ 2.192506] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10302 00:59:24.858662 <3>[ 2.196552] mtk-msdc 11f60000.mmc: phase error: [map:0]
10303 00:59:24.868657 <6>[ 2.200387] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10304 00:59:24.875223 <3>[ 2.205634] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10305 00:59:24.882098 <6>[ 2.215066] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10306 00:59:24.885589 <3>[ 2.220920] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10307 00:59:24.892128 <6>[ 2.227100] xhci-mtk 11200000.usb: xHCI Host Controller
10308 00:59:24.898817 <3>[ 2.233272] mmc0: error -5 whilst initialising MMC card
10309 00:59:24.905386 <6>[ 2.244230] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10310 00:59:24.911906 <6>[ 2.251881] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10311 00:59:24.918793 <6>[ 2.259667] hub 1-0:1.0: USB hub found
10312 00:59:24.921928 <6>[ 2.263683] hub 1-0:1.0: 1 port detected
10313 00:59:24.928406 <6>[ 2.267957] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10314 00:59:24.935551 <6>[ 2.276662] hub 2-0:1.0: USB hub found
10315 00:59:24.938573 <6>[ 2.280680] hub 2-0:1.0: 1 port detected
10316 00:59:24.946026 <6>[ 2.287547] mtk-msdc 11f70000.mmc: Got CD GPIO
10317 00:59:24.963957 <6>[ 2.301880] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10318 00:59:24.973625 <6>[ 2.310256] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10319 00:59:24.980096 <6>[ 2.318595] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10320 00:59:24.990588 <6>[ 2.326935] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10321 00:59:24.996804 <6>[ 2.335272] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10322 00:59:25.003365 <3>[ 2.343279] mtk-msdc 11f60000.mmc: phase error: [map:0]
10323 00:59:25.010247 <6>[ 2.343609] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10324 00:59:25.016600 <3>[ 2.349090] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10325 00:59:25.027079 <6>[ 2.357416] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10326 00:59:25.033040 <6>[ 2.357419] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10327 00:59:25.039536 <3>[ 2.363329] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10328 00:59:25.049558 <6>[ 2.371661] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10329 00:59:25.056306 <6>[ 2.371663] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10330 00:59:25.062845 <3>[ 2.380005] mmc0: error -5 whilst initialising MMC card
10331 00:59:25.069373 <6>[ 2.386338] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10332 00:59:25.079311 <6>[ 2.386341] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10333 00:59:25.085810 <6>[ 2.386344] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10334 00:59:25.095893 <6>[ 2.386346] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10335 00:59:25.102256 <6>[ 2.441841] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10336 00:59:25.109353 <6>[ 2.450559] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10337 00:59:25.116276 <6>[ 2.457707] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10338 00:59:25.123155 <6>[ 2.464466] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10339 00:59:25.133269 <6>[ 2.471209] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10340 00:59:25.139220 <6>[ 2.478114] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10341 00:59:25.146072 <6>[ 2.484955] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10342 00:59:25.155964 <6>[ 2.494084] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10343 00:59:25.166067 <6>[ 2.503207] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10344 00:59:25.175478 <6>[ 2.512500] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10345 00:59:25.185400 <6>[ 2.521969] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10346 00:59:25.191997 <6>[ 2.531435] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10347 00:59:25.202110 <6>[ 2.540555] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10348 00:59:25.212060 <6>[ 2.550020] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10349 00:59:25.222196 <6>[ 2.559138] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10350 00:59:25.232050 <6>[ 2.568433] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10351 00:59:25.241729 <6>[ 2.578594] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10352 00:59:25.252118 <6>[ 2.590062] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10353 00:59:25.350780 <6>[ 2.688658] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10354 00:59:25.492647 <6>[ 2.834371] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10355 00:59:25.503406 <6>[ 2.844945] mmc0: Command Queue Engine enabled
10356 00:59:25.509826 <6>[ 2.849747] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10357 00:59:25.512964 <6>[ 2.849988] hub 1-1:1.0: USB hub found
10358 00:59:25.519849 <6>[ 2.857290] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10359 00:59:25.522982 <6>[ 2.865307] hub 1-1:1.0: 4 ports detected
10360 00:59:25.529894 <6>[ 2.869151] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10361 00:59:25.539147 <6>[ 2.880455] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10362 00:59:25.542087 <6>[ 2.885934] hub 1-1:1.0: USB hub found
10363 00:59:25.548759 <6>[ 2.886584] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10364 00:59:25.552202 <6>[ 2.895323] hub 1-1:1.0: 4 ports detected
10365 00:59:25.558593 <6>[ 2.895810] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10366 00:59:25.630450 <6>[ 2.968796] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10367 00:59:25.656451 <6>[ 2.997824] hub 2-1:1.0: USB hub found
10368 00:59:25.660133 <6>[ 3.002267] hub 2-1:1.0: 3 ports detected
10369 00:59:25.669357 <6>[ 3.011049] hub 2-1:1.0: USB hub found
10370 00:59:25.672942 <6>[ 3.015592] hub 2-1:1.0: 3 ports detected
10371 00:59:25.878515 <6>[ 3.216699] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10372 00:59:26.011132 <6>[ 3.352421] hub 1-1.4:1.0: USB hub found
10373 00:59:26.014075 <6>[ 3.357081] hub 1-1.4:1.0: 2 ports detected
10374 00:59:26.026252 <6>[ 3.367772] hub 1-1.4:1.0: USB hub found
10375 00:59:26.029873 <6>[ 3.372307] hub 1-1.4:1.0: 2 ports detected
10376 00:59:26.090588 <6>[ 3.428824] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10377 00:59:26.198872 <6>[ 3.537339] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10378 00:59:26.234913 <4>[ 3.572873] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10379 00:59:26.244549 <4>[ 3.582036] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10380 00:59:26.288888 <6>[ 3.630245] r8152 2-1.3:1.0 eth0: v1.12.13
10381 00:59:26.326184 <6>[ 3.664621] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10382 00:59:26.518134 <6>[ 3.856701] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10383 00:59:27.898157 <6>[ 5.240213] r8152 2-1.3:1.0 eth0: carrier on
10384 00:59:27.934523 <5>[ 5.260506] Sending DHCP requests ., OK
10385 00:59:27.941492 <6>[ 5.280741] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10386 00:59:27.944607 <6>[ 5.289030] IP-Config: Complete:
10387 00:59:27.957754 <6>[ 5.292528] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10388 00:59:27.964763 <6>[ 5.303238] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10389 00:59:27.971347 <6>[ 5.311855] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10390 00:59:27.977623 <6>[ 5.311864] nameserver0=192.168.201.1
10391 00:59:27.981200 <6>[ 5.323995] clk: Disabling unused clocks
10392 00:59:27.984413 <6>[ 5.329372] ALSA device list:
10393 00:59:27.990783 <6>[ 5.332789] No soundcards found.
10394 00:59:27.998464 <6>[ 5.340316] Freeing unused kernel memory: 8512K
10395 00:59:28.001676 <6>[ 5.345402] Run /init as init process
10396 00:59:28.022516 Starting syslogd: OK
10397 00:59:28.029264 Starting klogd: OK
10398 00:59:28.039124 Running sysctl: OK
10399 00:59:28.045848 Populating /dev using udev: <30>[ 5.389112] udevd[202]: starting version 3.2.9
10400 00:59:28.054190 <27>[ 5.395615] udevd[202]: specified user 'tss' unknown
10401 00:59:28.060350 <27>[ 5.400989] udevd[202]: specified group 'tss' unknown
10402 00:59:28.064093 <30>[ 5.407349] udevd[203]: starting eudev-3.2.9
10403 00:59:28.082441 <27>[ 5.423894] udevd[203]: specified user 'tss' unknown
10404 00:59:28.088678 <27>[ 5.429363] udevd[203]: specified group 'tss' unknown
10405 00:59:28.203756 <6>[ 5.542422] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10406 00:59:28.210578 <6>[ 5.550171] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10407 00:59:28.220261 <6>[ 5.555649] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10408 00:59:28.230244 <6>[ 5.567676] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10409 00:59:28.242533 <4>[ 5.580928] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10410 00:59:28.252840 <3>[ 5.583942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10411 00:59:28.255974 <6>[ 5.587968] remoteproc remoteproc0: scp is available
10412 00:59:28.262425 <6>[ 5.588034] remoteproc remoteproc0: powering up scp
10413 00:59:28.268671 <6>[ 5.588038] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10414 00:59:28.275533 <6>[ 5.588060] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10415 00:59:28.285349 <6>[ 5.590822] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10416 00:59:28.291724 <3>[ 5.598205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10417 00:59:28.298483 <6>[ 5.603507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10418 00:59:28.308750 <3>[ 5.608559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10419 00:59:28.314844 <3>[ 5.608710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 00:59:28.321931 <6>[ 5.609162] mc: Linux media interface: v0.10
10421 00:59:28.328573 <4>[ 5.614660] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10422 00:59:28.334764 <4>[ 5.614794] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10423 00:59:28.344946 <6>[ 5.617537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10424 00:59:28.351417 <3>[ 5.622655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 00:59:28.361354 <3>[ 5.622662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 00:59:28.367996 <3>[ 5.622673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 00:59:28.374353 <6>[ 5.630782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10428 00:59:28.381197 <6>[ 5.631423] videodev: Linux video capture interface: v2.00
10429 00:59:28.390735 <3>[ 5.638843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10430 00:59:28.397310 <3>[ 5.641158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10431 00:59:28.403901 <6>[ 5.642119] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10432 00:59:28.413894 <6>[ 5.646913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10433 00:59:28.420607 <3>[ 5.655699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10434 00:59:28.427373 <6>[ 5.658054] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10435 00:59:28.437939 <6>[ 5.658081] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10436 00:59:28.447184 <6>[ 5.658088] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10437 00:59:28.454274 <6>[ 5.663100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10438 00:59:28.464155 <6>[ 5.781896] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10439 00:59:28.470205 <6>[ 5.784856] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10440 00:59:28.476754 <6>[ 5.784856] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10441 00:59:28.487267 <3>[ 5.784864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10442 00:59:28.493484 <3>[ 5.784881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10443 00:59:28.503801 <3>[ 5.784971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10444 00:59:28.509977 <3>[ 5.784981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10445 00:59:28.519914 <3>[ 5.784987] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10446 00:59:28.526498 <3>[ 5.784998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10447 00:59:28.533148 <3>[ 5.785004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10448 00:59:28.542700 <3>[ 5.785042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10449 00:59:28.552709 <6>[ 5.786209] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10450 00:59:28.562396 <6>[ 5.787597] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10451 00:59:28.569267 <6>[ 5.787813] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10452 00:59:28.575720 <6>[ 5.794122] pci_bus 0000:00: root bus resource [bus 00-ff]
10453 00:59:28.586338 <6>[ 5.795513] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10454 00:59:28.593000 <6>[ 5.796811] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10455 00:59:28.599833 <6>[ 5.802696] remoteproc remoteproc0: remote processor scp is now up
10456 00:59:28.606232 <6>[ 5.811387] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10457 00:59:28.610297 <6>[ 5.828712] Bluetooth: Core ver 2.22
10458 00:59:28.620249 <6>[ 5.833378] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10459 00:59:28.626940 <6>[ 5.835966] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10460 00:59:28.640297 <6>[ 5.837290] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10461 00:59:28.646552 <6>[ 5.837442] usbcore: registered new interface driver uvcvideo
10462 00:59:28.650311 <6>[ 5.842446] NET: Registered PF_BLUETOOTH protocol family
10463 00:59:28.657048 <6>[ 5.849475] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10464 00:59:28.663286 <6>[ 5.857574] Bluetooth: HCI device and connection manager initialized
10465 00:59:28.673260 <6>[ 5.865616] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10466 00:59:28.679905 <6>[ 5.866206] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10467 00:59:28.683088 <6>[ 5.873779] Bluetooth: HCI socket layer initialized
10468 00:59:28.686561 <6>[ 5.881825] pci 0000:00:00.0: supports D1 D2
10469 00:59:28.693178 <6>[ 5.889952] Bluetooth: L2CAP socket layer initialized
10470 00:59:28.700006 <6>[ 5.899136] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10471 00:59:28.709862 <6>[ 5.900010] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10472 00:59:28.712933 <6>[ 5.909340] Bluetooth: SCO socket layer initialized
10473 00:59:28.722776 <4>[ 5.909775] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10474 00:59:28.726328 <4>[ 5.909775] Fallback method does not support PEC.
10475 00:59:28.732794 <6>[ 5.918386] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10476 00:59:28.742792 <3>[ 5.930974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10477 00:59:28.749563 <6>[ 5.932283] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10478 00:59:28.759162 <3>[ 5.961467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10479 00:59:28.765928 <6>[ 5.967791] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10480 00:59:28.772569 <6>[ 5.975336] usbcore: registered new interface driver btusb
10481 00:59:28.782303 <4>[ 5.975889] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10482 00:59:28.788813 <3>[ 5.975894] Bluetooth: hci0: Failed to load firmware file (-2)
10483 00:59:28.795420 <3>[ 5.975895] Bluetooth: hci0: Failed to set up firmware (-2)
10484 00:59:28.805491 <4>[ 5.975896] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10485 00:59:28.812088 <6>[ 5.987252] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10486 00:59:28.815361 <6>[ 5.987360] pci 0000:01:00.0: supports D1 D2
10487 00:59:28.821716 <6>[ 6.163695] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10488 00:59:28.841661 <6>[ 6.180603] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10489 00:59:28.848202 <6>[ 6.187501] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10490 00:59:28.854781 <6>[ 6.195583] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10491 00:59:28.864669 <6>[ 6.203579] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10492 00:59:28.871349 <6>[ 6.211579] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10493 00:59:28.881519 <6>[ 6.219578] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10494 00:59:28.884573 <6>[ 6.227577] pci 0000:00:00.0: PCI bridge to [bus 01]
10495 00:59:28.894795 <6>[ 6.232793] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10496 00:59:28.901301 <6>[ 6.240911] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10497 00:59:28.907889 <6>[ 6.247704] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10498 00:59:28.914662 <6>[ 6.254414] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10499 00:59:28.929055 <5>[ 6.268030] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10500 00:59:28.966328 <5>[ 6.304858] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10501 00:59:28.972495 <5>[ 6.312287] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10502 00:59:28.982598 <4>[ 6.320772] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10503 00:59:28.989095 <6>[ 6.329676] cfg80211: failed to load regulatory.db
10504 00:59:29.033299 <6>[ 6.372108] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10505 00:59:29.040044 <6>[ 6.379601] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10506 00:59:29.064532 <6>[ 6.406379] mt7921e 0000:01:00.0: ASIC revision: 79610010
10507 00:59:29.165616 <6>[ 6.503912] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10508 00:59:29.168511 <6>[ 6.503912]
10509 00:59:29.180369 done
10510 00:59:29.193199 Saving random seed: OK
10511 00:59:29.205190 Starting network: ip: RTNETLINK answers: File exists
10512 00:59:29.208081 FAIL
10513 00:59:29.252448 Starting dropbear sshd: <6>[ 6.594568] NET: Registered PF_INET6 protocol family
10514 00:59:29.259148 <6>[ 6.601502] Segment Routing with IPv6
10515 00:59:29.262705 <6>[ 6.605461] In-situ OAM (IOAM) with IPv6
10516 00:59:29.266599 OK
10517 00:59:29.280160 /bin/sh: can't access tty; job control turned off
10518 00:59:29.281217 Matched prompt #10: / #
10520 00:59:29.282376 Setting prompt string to ['/ #']
10521 00:59:29.282796 end: 2.2.5.1 login-action (duration 00:00:07) [common]
10523 00:59:29.283724 end: 2.2.5 auto-login-action (duration 00:00:07) [common]
10524 00:59:29.284165 start: 2.2.6 expect-shell-connection (timeout 00:03:56) [common]
10525 00:59:29.284519 Setting prompt string to ['/ #']
10526 00:59:29.284811 Forcing a shell prompt, looking for ['/ #']
10528 00:59:29.335534 / #
10529 00:59:29.336118 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10530 00:59:29.336531 Waiting using forced prompt support (timeout 00:02:30)
10531 00:59:29.341467
10532 00:59:29.342310 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10533 00:59:29.342780 start: 2.2.7 export-device-env (timeout 00:03:56) [common]
10534 00:59:29.343280 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10535 00:59:29.343671 end: 2.2 depthcharge-retry (duration 00:01:04) [common]
10536 00:59:29.344066 end: 2 depthcharge-action (duration 00:01:04) [common]
10537 00:59:29.344479 start: 3 lava-test-retry (timeout 00:01:00) [common]
10538 00:59:29.344913 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10539 00:59:29.345261 Using namespace: common
10541 00:59:29.446271 / # #
10542 00:59:29.446843 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10543 00:59:29.447327 #<6>[ 6.774355] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10544 00:59:29.452126
10545 00:59:29.452841 Using /lava-14368627
10547 00:59:29.553843 / # export SHELL=/bin/sh
10548 00:59:29.560386 export SHELL=/bin/sh
10550 00:59:29.661869 / # . /lava-14368627/environment
10551 00:59:29.668208 . /lava-14368627/environment
10553 00:59:29.769822 / # /lava-14368627/bin/lava-test-runner /lava-14368627/0
10554 00:59:29.770526 Test shell timeout: 10s (minimum of the action and connection timeout)
10555 00:59:29.776121 /lava-14368627/bin/lava-test-runner /lava-14368627/0
10556 00:59:29.795264 + export 'TESTRUN_ID=0_dmesg'
10557 00:59:29.802302 +<8>[ 7.143120] <LAVA_SIGNAL_STARTRUN 0_dmesg 14368627_1.5.2.3.1>
10558 00:59:29.803103 Received signal: <STARTRUN> 0_dmesg 14368627_1.5.2.3.1
10559 00:59:29.803482 Starting test lava.0_dmesg (14368627_1.5.2.3.1)
10560 00:59:29.803888 Skipping test definition patterns.
10561 00:59:29.805043 cd /lava-14368627/0/tests/0_dmesg
10562 00:59:29.805475 + cat uuid
10563 00:59:29.808479 + UUID=14368627_1.5.2.3.1
10564 00:59:29.808945 + set +x
10565 00:59:29.815210 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10566 00:59:29.821542 <8>[ 7.161097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10567 00:59:29.822367 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10569 00:59:29.842197 <8>[ 7.181059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10570 00:59:29.843043 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10572 00:59:29.864013 <8>[ 7.202955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10573 00:59:29.864757 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10575 00:59:29.867467 + set +x
10576 00:59:29.870817 <8>[ 7.212329] <LAVA_SIGNAL_ENDRUN 0_dmesg 14368627_1.5.2.3.1>
10577 00:59:29.871566 Received signal: <ENDRUN> 0_dmesg 14368627_1.5.2.3.1
10578 00:59:29.871981 Ending use of test pattern.
10579 00:59:29.872304 Ending test lava.0_dmesg (14368627_1.5.2.3.1), duration 0.07
10581 00:59:29.874725 <LAVA_TEST_RUNNER EXIT>
10582 00:59:29.875598 ok: lava_test_shell seems to have completed
10583 00:59:29.876346 alert: pass
crit: pass
emerg: pass
10584 00:59:29.876876 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10585 00:59:29.877336 end: 3 lava-test-retry (duration 00:00:01) [common]
10586 00:59:29.877793 start: 4 finalize (timeout 00:08:38) [common]
10587 00:59:29.878293 start: 4.1 power-off (timeout 00:00:30) [common]
10588 00:59:29.879042 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10589 00:59:30.135133 >> Command sent successfully.
10590 00:59:30.148780 Returned 0 in 0 seconds
10591 00:59:30.250024 end: 4.1 power-off (duration 00:00:00) [common]
10593 00:59:30.251530 start: 4.2 read-feedback (timeout 00:08:38) [common]
10594 00:59:30.252976 Listened to connection for namespace 'common' for up to 1s
10595 00:59:31.253616 Finalising connection for namespace 'common'
10596 00:59:31.254252 Disconnecting from shell: Finalise
10597 00:59:31.254680 / #
10598 00:59:31.355603 end: 4.2 read-feedback (duration 00:00:01) [common]
10599 00:59:31.356282 end: 4 finalize (duration 00:00:01) [common]
10600 00:59:31.356909 Cleaning after the job
10601 00:59:31.357420 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/ramdisk
10602 00:59:31.368973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/kernel
10603 00:59:31.395686 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/dtb
10604 00:59:31.396080 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368627/tftp-deploy-szphy0p4/modules
10605 00:59:31.406154 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368627
10606 00:59:31.448008 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368627
10607 00:59:31.448154 Job finished correctly