Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 00:58:13.071922 lava-dispatcher, installed at version: 2024.03
2 00:58:13.072184 start: 0 validate
3 00:58:13.072304 Start time: 2024-06-16 00:58:13.072298+00:00 (UTC)
4 00:58:13.072440 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:58:13.072579 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:58:13.338786 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:58:13.339027 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:58:13.589243 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:58:13.590046 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:58:13.848395 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:58:13.848599 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:58:14.098539 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:58:14.098697 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:58:14.348480 validate duration: 1.28
16 00:58:14.348891 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:58:14.348995 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:58:14.349086 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:58:14.349250 Not decompressing ramdisk as can be used compressed.
20 00:58:14.349347 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 00:58:14.349419 saving as /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/ramdisk/initrd.cpio.gz
22 00:58:14.349478 total size: 5628182 (5 MB)
23 00:58:14.350716 progress 0 % (0 MB)
24 00:58:14.352507 progress 5 % (0 MB)
25 00:58:14.354248 progress 10 % (0 MB)
26 00:58:14.355999 progress 15 % (0 MB)
27 00:58:14.357792 progress 20 % (1 MB)
28 00:58:14.359417 progress 25 % (1 MB)
29 00:58:14.361109 progress 30 % (1 MB)
30 00:58:14.362818 progress 35 % (1 MB)
31 00:58:14.364610 progress 40 % (2 MB)
32 00:58:14.366664 progress 45 % (2 MB)
33 00:58:14.368446 progress 50 % (2 MB)
34 00:58:14.370416 progress 55 % (2 MB)
35 00:58:14.372406 progress 60 % (3 MB)
36 00:58:14.374128 progress 65 % (3 MB)
37 00:58:14.375753 progress 70 % (3 MB)
38 00:58:14.377154 progress 75 % (4 MB)
39 00:58:14.378698 progress 80 % (4 MB)
40 00:58:14.380065 progress 85 % (4 MB)
41 00:58:14.381604 progress 90 % (4 MB)
42 00:58:14.383266 progress 95 % (5 MB)
43 00:58:14.384625 progress 100 % (5 MB)
44 00:58:14.384832 5 MB downloaded in 0.04 s (151.86 MB/s)
45 00:58:14.384989 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:58:14.385315 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:58:14.385418 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:58:14.385538 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:58:14.385699 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:58:14.385761 saving as /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/kernel/Image
52 00:58:14.385815 total size: 54813184 (52 MB)
53 00:58:14.385870 No compression specified
54 00:58:14.387192 progress 0 % (0 MB)
55 00:58:14.401953 progress 5 % (2 MB)
56 00:58:14.416453 progress 10 % (5 MB)
57 00:58:14.430468 progress 15 % (7 MB)
58 00:58:14.444540 progress 20 % (10 MB)
59 00:58:14.458698 progress 25 % (13 MB)
60 00:58:14.474790 progress 30 % (15 MB)
61 00:58:14.488792 progress 35 % (18 MB)
62 00:58:14.502744 progress 40 % (20 MB)
63 00:58:14.516432 progress 45 % (23 MB)
64 00:58:14.530130 progress 50 % (26 MB)
65 00:58:14.544646 progress 55 % (28 MB)
66 00:58:14.558440 progress 60 % (31 MB)
67 00:58:14.572055 progress 65 % (34 MB)
68 00:58:14.585565 progress 70 % (36 MB)
69 00:58:14.599135 progress 75 % (39 MB)
70 00:58:14.612755 progress 80 % (41 MB)
71 00:58:14.626213 progress 85 % (44 MB)
72 00:58:14.639731 progress 90 % (47 MB)
73 00:58:14.653190 progress 95 % (49 MB)
74 00:58:14.666487 progress 100 % (52 MB)
75 00:58:14.666700 52 MB downloaded in 0.28 s (186.11 MB/s)
76 00:58:14.666849 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:58:14.667050 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:58:14.667130 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:58:14.667204 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:58:14.667331 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:58:14.667396 saving as /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/dtb/mt8192-asurada-spherion-r0.dtb
83 00:58:14.667448 total size: 47258 (0 MB)
84 00:58:14.667499 No compression specified
85 00:58:14.668582 progress 69 % (0 MB)
86 00:58:14.668836 progress 100 % (0 MB)
87 00:58:14.668982 0 MB downloaded in 0.00 s (29.42 MB/s)
88 00:58:14.669092 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:58:14.669290 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:58:14.669365 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:58:14.669440 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:58:14.669541 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 00:58:14.669645 saving as /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/nfsrootfs/full.rootfs.tar
95 00:58:14.669697 total size: 107552908 (102 MB)
96 00:58:14.669749 Using unxz to decompress xz
97 00:58:14.670893 progress 0 % (0 MB)
98 00:58:14.944768 progress 5 % (5 MB)
99 00:58:15.268443 progress 10 % (10 MB)
100 00:58:15.588343 progress 15 % (15 MB)
101 00:58:15.922693 progress 20 % (20 MB)
102 00:58:16.200850 progress 25 % (25 MB)
103 00:58:16.496648 progress 30 % (30 MB)
104 00:58:16.795659 progress 35 % (35 MB)
105 00:58:16.971605 progress 40 % (41 MB)
106 00:58:17.170402 progress 45 % (46 MB)
107 00:58:17.469901 progress 50 % (51 MB)
108 00:58:17.763990 progress 55 % (56 MB)
109 00:58:18.090170 progress 60 % (61 MB)
110 00:58:18.398880 progress 65 % (66 MB)
111 00:58:18.703503 progress 70 % (71 MB)
112 00:58:19.013250 progress 75 % (76 MB)
113 00:58:19.318636 progress 80 % (82 MB)
114 00:58:19.627630 progress 85 % (87 MB)
115 00:58:19.910322 progress 90 % (92 MB)
116 00:58:20.202229 progress 95 % (97 MB)
117 00:58:20.511865 progress 100 % (102 MB)
118 00:58:20.516951 102 MB downloaded in 5.85 s (17.54 MB/s)
119 00:58:20.517111 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:58:20.517322 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:58:20.517400 start: 1.5 download-retry (timeout 00:09:54) [common]
123 00:58:20.517475 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 00:58:20.517643 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:58:20.517726 saving as /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/modules/modules.tar
126 00:58:20.517782 total size: 8617404 (8 MB)
127 00:58:20.517837 Using unxz to decompress xz
128 00:58:20.519587 progress 0 % (0 MB)
129 00:58:20.537912 progress 5 % (0 MB)
130 00:58:20.564712 progress 10 % (0 MB)
131 00:58:20.591689 progress 15 % (1 MB)
132 00:58:20.614869 progress 20 % (1 MB)
133 00:58:20.637826 progress 25 % (2 MB)
134 00:58:20.660492 progress 30 % (2 MB)
135 00:58:20.685982 progress 35 % (2 MB)
136 00:58:20.709552 progress 40 % (3 MB)
137 00:58:20.731628 progress 45 % (3 MB)
138 00:58:20.755060 progress 50 % (4 MB)
139 00:58:20.779185 progress 55 % (4 MB)
140 00:58:20.802684 progress 60 % (4 MB)
141 00:58:20.825879 progress 65 % (5 MB)
142 00:58:20.851274 progress 70 % (5 MB)
143 00:58:20.874552 progress 75 % (6 MB)
144 00:58:20.899604 progress 80 % (6 MB)
145 00:58:20.923007 progress 85 % (7 MB)
146 00:58:20.946887 progress 90 % (7 MB)
147 00:58:20.970969 progress 95 % (7 MB)
148 00:58:20.994927 progress 100 % (8 MB)
149 00:58:21.000567 8 MB downloaded in 0.48 s (17.02 MB/s)
150 00:58:21.000724 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:58:21.000934 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:58:21.001013 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:58:21.001091 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:58:23.104324 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw
156 00:58:23.104500 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:58:23.104591 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 00:58:23.104744 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt
159 00:58:23.104861 makedir: /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin
160 00:58:23.104951 makedir: /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/tests
161 00:58:23.105038 makedir: /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/results
162 00:58:23.105118 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-add-keys
163 00:58:23.105241 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-add-sources
164 00:58:23.105358 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-background-process-start
165 00:58:23.105490 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-background-process-stop
166 00:58:23.105633 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-common-functions
167 00:58:23.105748 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-echo-ipv4
168 00:58:23.105860 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-install-packages
169 00:58:23.105971 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-installed-packages
170 00:58:23.106080 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-os-build
171 00:58:23.106191 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-probe-channel
172 00:58:23.106301 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-probe-ip
173 00:58:23.106412 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-target-ip
174 00:58:23.106522 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-target-mac
175 00:58:23.106632 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-target-storage
176 00:58:23.106746 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-case
177 00:58:23.106857 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-event
178 00:58:23.106967 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-feedback
179 00:58:23.107076 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-raise
180 00:58:23.107184 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-reference
181 00:58:23.107294 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-runner
182 00:58:23.107403 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-set
183 00:58:23.107513 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-test-shell
184 00:58:23.107624 Updating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-install-packages (oe)
185 00:58:23.107760 Updating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/bin/lava-installed-packages (oe)
186 00:58:23.107870 Creating /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/environment
187 00:58:23.107954 LAVA metadata
188 00:58:23.108018 - LAVA_JOB_ID=14368619
189 00:58:23.108074 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:58:23.108164 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 00:58:23.108220 skipped lava-vland-overlay
192 00:58:23.108285 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:58:23.108356 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 00:58:23.108408 skipped lava-multinode-overlay
195 00:58:23.108471 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:58:23.108540 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 00:58:23.108600 Loading test definitions
198 00:58:23.108683 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 00:58:23.108741 Using /lava-14368619 at stage 0
200 00:58:23.109026 uuid=14368619_1.6.2.3.1 testdef=None
201 00:58:23.109106 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:58:23.109178 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 00:58:23.109660 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:58:23.109863 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 00:58:23.110431 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:58:23.110634 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 00:58:23.111187 runner path: /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/0/tests/0_dmesg test_uuid 14368619_1.6.2.3.1
210 00:58:23.111330 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:58:23.111509 Creating lava-test-runner.conf files
213 00:58:23.111563 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368619/lava-overlay-bbogr_yt/lava-14368619/0 for stage 0
214 00:58:23.111642 - 0_dmesg
215 00:58:23.111731 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:58:23.111806 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 00:58:23.117234 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:58:23.117326 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 00:58:23.117403 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:58:23.117479 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:58:23.117707 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 00:58:23.274410 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:58:23.274569 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 00:58:23.274663 extracting modules file /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw
225 00:58:23.505145 extracting modules file /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368619/extract-overlay-ramdisk-cx6thpf2/ramdisk
226 00:58:23.728079 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:58:23.728218 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 00:58:23.728315 [common] Applying overlay to NFS
229 00:58:23.728384 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368619/compress-overlay-8yk71ugl/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw
230 00:58:23.734693 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:58:23.734798 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 00:58:23.734890 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:58:23.734983 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 00:58:23.735061 Building ramdisk /var/lib/lava/dispatcher/tmp/14368619/extract-overlay-ramdisk-cx6thpf2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368619/extract-overlay-ramdisk-cx6thpf2/ramdisk
235 00:58:24.031836 >> 130405 blocks
236 00:58:26.102423 rename /var/lib/lava/dispatcher/tmp/14368619/extract-overlay-ramdisk-cx6thpf2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/ramdisk/ramdisk.cpio.gz
237 00:58:26.102594 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:58:26.102684 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 00:58:26.102764 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 00:58:26.102844 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/kernel/Image']
241 00:58:40.265000 Returned 0 in 14 seconds
242 00:58:40.365497 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/kernel/image.itb
243 00:58:40.776635 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:58:40.776763 output: Created: Sun Jun 16 01:58:40 2024
245 00:58:40.776836 output: Image 0 (kernel-1)
246 00:58:40.776933 output: Description:
247 00:58:40.777022 output: Created: Sun Jun 16 01:58:40 2024
248 00:58:40.777108 output: Type: Kernel Image
249 00:58:40.777188 output: Compression: lzma compressed
250 00:58:40.777277 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
251 00:58:40.777359 output: Architecture: AArch64
252 00:58:40.777442 output: OS: Linux
253 00:58:40.777532 output: Load Address: 0x00000000
254 00:58:40.777629 output: Entry Point: 0x00000000
255 00:58:40.777712 output: Hash algo: crc32
256 00:58:40.777799 output: Hash value: f6f06660
257 00:58:40.777879 output: Image 1 (fdt-1)
258 00:58:40.777955 output: Description: mt8192-asurada-spherion-r0
259 00:58:40.778036 output: Created: Sun Jun 16 01:58:40 2024
260 00:58:40.778115 output: Type: Flat Device Tree
261 00:58:40.778193 output: Compression: uncompressed
262 00:58:40.778260 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 00:58:40.778315 output: Architecture: AArch64
264 00:58:40.778369 output: Hash algo: crc32
265 00:58:40.778419 output: Hash value: 0f8e4d2e
266 00:58:40.778468 output: Image 2 (ramdisk-1)
267 00:58:40.778546 output: Description: unavailable
268 00:58:40.778622 output: Created: Sun Jun 16 01:58:40 2024
269 00:58:40.778698 output: Type: RAMDisk Image
270 00:58:40.778776 output: Compression: uncompressed
271 00:58:40.778852 output: Data Size: 18737541 Bytes = 18298.38 KiB = 17.87 MiB
272 00:58:40.778928 output: Architecture: AArch64
273 00:58:40.779007 output: OS: Linux
274 00:58:40.779083 output: Load Address: unavailable
275 00:58:40.779158 output: Entry Point: unavailable
276 00:58:40.779236 output: Hash algo: crc32
277 00:58:40.779311 output: Hash value: 67c49807
278 00:58:40.779389 output: Default Configuration: 'conf-1'
279 00:58:40.779480 output: Configuration 0 (conf-1)
280 00:58:40.779558 output: Description: mt8192-asurada-spherion-r0
281 00:58:40.779634 output: Kernel: kernel-1
282 00:58:40.779710 output: Init Ramdisk: ramdisk-1
283 00:58:40.779788 output: FDT: fdt-1
284 00:58:40.779864 output: Loadables: kernel-1
285 00:58:40.779940 output:
286 00:58:40.780110 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 00:58:40.780229 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 00:58:40.780359 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 00:58:40.780483 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 00:58:40.780583 No LXC device requested
291 00:58:40.780688 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:58:40.780800 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 00:58:40.780899 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:58:40.780988 Checking files for TFTP limit of 4294967296 bytes.
295 00:58:40.781803 end: 1 tftp-deploy (duration 00:00:26) [common]
296 00:58:40.781913 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:58:40.782001 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:58:40.782117 substitutions:
299 00:58:40.782178 - {DTB}: 14368619/tftp-deploy-trdb_me4/dtb/mt8192-asurada-spherion-r0.dtb
300 00:58:40.782240 - {INITRD}: 14368619/tftp-deploy-trdb_me4/ramdisk/ramdisk.cpio.gz
301 00:58:40.782295 - {KERNEL}: 14368619/tftp-deploy-trdb_me4/kernel/Image
302 00:58:40.782346 - {LAVA_MAC}: None
303 00:58:40.782397 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw
304 00:58:40.782447 - {NFS_SERVER_IP}: 192.168.201.1
305 00:58:40.782501 - {PRESEED_CONFIG}: None
306 00:58:40.782559 - {PRESEED_LOCAL}: None
307 00:58:40.782610 - {RAMDISK}: 14368619/tftp-deploy-trdb_me4/ramdisk/ramdisk.cpio.gz
308 00:58:40.782660 - {ROOT_PART}: None
309 00:58:40.782709 - {ROOT}: None
310 00:58:40.782762 - {SERVER_IP}: 192.168.201.1
311 00:58:40.782811 - {TEE}: None
312 00:58:40.782859 Parsed boot commands:
313 00:58:40.782907 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:58:40.783061 Parsed boot commands: tftpboot 192.168.201.1 14368619/tftp-deploy-trdb_me4/kernel/image.itb 14368619/tftp-deploy-trdb_me4/kernel/cmdline
315 00:58:40.783146 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:58:40.783227 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:58:40.783311 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:58:40.783384 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:58:40.783447 Not connected, no need to disconnect.
320 00:58:40.783520 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:58:40.783607 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:58:40.783672 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 00:58:40.787139 Setting prompt string to ['lava-test: # ']
324 00:58:40.787475 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:58:40.787604 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:58:40.787726 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:58:40.787843 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:58:40.788141 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
329 00:58:49.934773 >> Command sent successfully.
330 00:58:49.938624 Returned 0 in 9 seconds
331 00:58:50.038954 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 00:58:50.039333 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 00:58:50.039476 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 00:58:50.039608 Setting prompt string to 'Starting depthcharge on Spherion...'
336 00:58:50.039718 Changing prompt to 'Starting depthcharge on Spherion...'
337 00:58:50.039827 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 00:58:50.040357 [Enter `^Ec?' for help]
339 00:58:51.546520
340 00:58:51.546638
341 00:58:51.546711 F0: 102B 0000
342 00:58:51.546775
343 00:58:51.546832 F3: 1001 0000 [0200]
344 00:58:51.550339
345 00:58:51.550419 F3: 1001 0000
346 00:58:51.550490
347 00:58:51.550552 F7: 102D 0000
348 00:58:51.550616
349 00:58:51.550670 F1: 0000 0000
350 00:58:51.554129
351 00:58:51.554200 V0: 0000 0000 [0001]
352 00:58:51.554256
353 00:58:51.554313 00: 0007 8000
354 00:58:51.554366
355 00:58:51.557807 01: 0000 0000
356 00:58:51.557878
357 00:58:51.557934 BP: 0C00 0209 [0000]
358 00:58:51.557990
359 00:58:51.561391 G0: 1182 0000
360 00:58:51.561485
361 00:58:51.561570 EC: 0000 0021 [4000]
362 00:58:51.561626
363 00:58:51.565973 S7: 0000 0000 [0000]
364 00:58:51.566042
365 00:58:51.566103 CC: 0000 0000 [0001]
366 00:58:51.566155
367 00:58:51.569301 T0: 0000 0040 [010F]
368 00:58:51.569397
369 00:58:51.569477 Jump to BL
370 00:58:51.569563
371 00:58:51.593612
372 00:58:51.593717
373 00:58:51.600207 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 00:58:51.603656 ARM64: Exception handlers installed.
375 00:58:51.607711 ARM64: Testing exception
376 00:58:51.611102 ARM64: Done test exception
377 00:58:51.618300 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 00:58:51.628219 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 00:58:51.635303 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 00:58:51.645406 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 00:58:51.652057 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 00:58:51.658321 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 00:58:51.670201 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 00:58:51.676300 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 00:58:51.696479 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 00:58:51.699712 WDT: Last reset was cold boot
387 00:58:51.703045 SPI1(PAD0) initialized at 2873684 Hz
388 00:58:51.706380 SPI5(PAD0) initialized at 992727 Hz
389 00:58:51.709714 VBOOT: Loading verstage.
390 00:58:51.716487 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 00:58:51.719829 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 00:58:51.723303 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 00:58:51.726625 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 00:58:51.733889 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 00:58:51.740630 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 00:58:51.751176 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
397 00:58:51.751284
398 00:58:51.751376
399 00:58:51.761537 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 00:58:51.764811 ARM64: Exception handlers installed.
401 00:58:51.767982 ARM64: Testing exception
402 00:58:51.768079 ARM64: Done test exception
403 00:58:51.774639 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 00:58:51.777969 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 00:58:51.792765 Probing TPM: . done!
406 00:58:51.792865 TPM ready after 0 ms
407 00:58:51.799251 Connected to device vid:did:rid of 1ae0:0028:00
408 00:58:51.805736 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 00:58:51.809670 Initialized TPM device CR50 revision 0
410 00:58:51.858104 tlcl_send_startup: Startup return code is 0
411 00:58:51.858211 TPM: setup succeeded
412 00:58:51.869194 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 00:58:51.878056 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 00:58:51.888460 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 00:58:51.897343 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 00:58:51.900436 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 00:58:51.904061 in-header: 03 07 00 00 08 00 00 00
418 00:58:51.907351 in-data: aa e4 47 04 13 02 00 00
419 00:58:51.910870 Chrome EC: UHEPI supported
420 00:58:51.917563 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 00:58:51.920964 in-header: 03 a9 00 00 08 00 00 00
422 00:58:51.923632 in-data: 84 60 60 08 00 00 00 00
423 00:58:51.923725 Phase 1
424 00:58:51.926992 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 00:58:51.933802 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 00:58:51.940570 VB2:vb2_check_recovery() Recovery was requested manually
427 00:58:51.943899 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 00:58:51.947260 Recovery requested (1009000e)
429 00:58:51.956035 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 00:58:51.961422 tlcl_extend: response is 0
431 00:58:51.971645 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 00:58:51.975105 tlcl_extend: response is 0
433 00:58:51.981865 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 00:58:52.002499 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 00:58:52.009907 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 00:58:52.009984
437 00:58:52.010047
438 00:58:52.020235 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 00:58:52.023719 ARM64: Exception handlers installed.
440 00:58:52.023814 ARM64: Testing exception
441 00:58:52.026895 ARM64: Done test exception
442 00:58:52.047250 pmic_efuse_setting: Set efuses in 11 msecs
443 00:58:52.050624 pmwrap_interface_init: Select PMIF_VLD_RDY
444 00:58:52.057403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 00:58:52.060705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 00:58:52.067405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 00:58:52.070659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 00:58:52.077349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 00:58:52.081240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 00:58:52.084565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 00:58:52.091023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 00:58:52.094549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 00:58:52.100864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 00:58:52.104330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 00:58:52.108105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 00:58:52.114620 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 00:58:52.121463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 00:58:52.124220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 00:58:52.130980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 00:58:52.137923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 00:58:52.141090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 00:58:52.148118 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 00:58:52.154346 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 00:58:52.158293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 00:58:52.164476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 00:58:52.171087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 00:58:52.174435 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 00:58:52.181216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 00:58:52.187825 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 00:58:52.191148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 00:58:52.197990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 00:58:52.201243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 00:58:52.204912 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 00:58:52.211402 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 00:58:52.215087 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 00:58:52.221493 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 00:58:52.228355 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 00:58:52.231621 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 00:58:52.235263 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 00:58:52.241558 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 00:58:52.244920 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 00:58:52.252617 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 00:58:52.255848 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 00:58:52.259425 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 00:58:52.262444 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 00:58:52.269038 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 00:58:52.272494 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 00:58:52.275840 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 00:58:52.282532 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 00:58:52.285962 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 00:58:52.289177 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 00:58:52.295991 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 00:58:52.299254 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 00:58:52.302655 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 00:58:52.309257 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 00:58:52.319533 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 00:58:52.322223 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 00:58:52.332257 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 00:58:52.339104 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 00:58:52.345989 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 00:58:52.349083 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:58:52.352528 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 00:58:52.360151 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
504 00:58:52.367020 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 00:58:52.370281 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 00:58:52.373469 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 00:58:52.384757 [RTC]rtc_get_frequency_meter,154: input=15, output=760
508 00:58:52.394297 [RTC]rtc_get_frequency_meter,154: input=23, output=943
509 00:58:52.403630 [RTC]rtc_get_frequency_meter,154: input=19, output=850
510 00:58:52.413643 [RTC]rtc_get_frequency_meter,154: input=17, output=804
511 00:58:52.423205 [RTC]rtc_get_frequency_meter,154: input=16, output=781
512 00:58:52.432336 [RTC]rtc_get_frequency_meter,154: input=16, output=782
513 00:58:52.442137 [RTC]rtc_get_frequency_meter,154: input=17, output=805
514 00:58:52.444797 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 00:58:52.452705 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 00:58:52.455986 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 00:58:52.459149 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
518 00:58:52.465582 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 00:58:52.469190 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
520 00:58:52.472843 ADC[4]: Raw value=906203 ID=7
521 00:58:52.472910 ADC[3]: Raw value=213441 ID=1
522 00:58:52.475764 RAM Code: 0x71
523 00:58:52.479611 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 00:58:52.486027 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 00:58:52.492982 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 00:58:52.499567 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 00:58:52.502943 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 00:58:52.506180 in-header: 03 07 00 00 08 00 00 00
529 00:58:52.509436 in-data: aa e4 47 04 13 02 00 00
530 00:58:52.512908 Chrome EC: UHEPI supported
531 00:58:52.519709 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 00:58:52.522962 in-header: 03 a9 00 00 08 00 00 00
533 00:58:52.526031 in-data: 84 60 60 08 00 00 00 00
534 00:58:52.529157 MRC: failed to locate region type 0.
535 00:58:52.536312 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 00:58:52.539612 DRAM-K: Running full calibration
537 00:58:52.545881 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 00:58:52.545972 header.status = 0x0
539 00:58:52.549195 header.version = 0x6 (expected: 0x6)
540 00:58:52.552499 header.size = 0xd00 (expected: 0xd00)
541 00:58:52.556425 header.flags = 0x0
542 00:58:52.562964 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 00:58:52.579487 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
544 00:58:52.585875 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 00:58:52.589713 dram_init: ddr_geometry: 2
546 00:58:52.592688 [EMI] MDL number = 2
547 00:58:52.592779 [EMI] Get MDL freq = 0
548 00:58:52.595719 dram_init: ddr_type: 0
549 00:58:52.595807 is_discrete_lpddr4: 1
550 00:58:52.599082 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 00:58:52.599147
552 00:58:52.599201
553 00:58:52.602828 [Bian_co] ETT version 0.0.0.1
554 00:58:52.609016 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 00:58:52.609107
556 00:58:52.612836 dramc_set_vcore_voltage set vcore to 650000
557 00:58:52.612930 Read voltage for 800, 4
558 00:58:52.616245 Vio18 = 0
559 00:58:52.616341 Vcore = 650000
560 00:58:52.616425 Vdram = 0
561 00:58:52.619076 Vddq = 0
562 00:58:52.619163 Vmddr = 0
563 00:58:52.623057 dram_init: config_dvfs: 1
564 00:58:52.625748 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 00:58:52.632955 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 00:58:52.636181 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 00:58:52.639672 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 00:58:52.642951 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 00:58:52.646297 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 00:58:52.649422 MEM_TYPE=3, freq_sel=18
571 00:58:52.652650 sv_algorithm_assistance_LP4_1600
572 00:58:52.656374 ============ PULL DRAM RESETB DOWN ============
573 00:58:52.659549 ========== PULL DRAM RESETB DOWN end =========
574 00:58:52.666547 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 00:58:52.670793 ===================================
576 00:58:52.670887 LPDDR4 DRAM CONFIGURATION
577 00:58:52.674843 ===================================
578 00:58:52.674912 EX_ROW_EN[0] = 0x0
579 00:58:52.678431 EX_ROW_EN[1] = 0x0
580 00:58:52.678499 LP4Y_EN = 0x0
581 00:58:52.682546 WORK_FSP = 0x0
582 00:58:52.682612 WL = 0x2
583 00:58:52.686030 RL = 0x2
584 00:58:52.686124 BL = 0x2
585 00:58:52.690006 RPST = 0x0
586 00:58:52.690108 RD_PRE = 0x0
587 00:58:52.693983 WR_PRE = 0x1
588 00:58:52.694082 WR_PST = 0x0
589 00:58:52.694170 DBI_WR = 0x0
590 00:58:52.697460 DBI_RD = 0x0
591 00:58:52.700932 OTF = 0x1
592 00:58:52.703569 ===================================
593 00:58:52.706963 ===================================
594 00:58:52.707056 ANA top config
595 00:58:52.710891 ===================================
596 00:58:52.714201 DLL_ASYNC_EN = 0
597 00:58:52.714293 ALL_SLAVE_EN = 1
598 00:58:52.717238 NEW_RANK_MODE = 1
599 00:58:52.720459 DLL_IDLE_MODE = 1
600 00:58:52.723656 LP45_APHY_COMB_EN = 1
601 00:58:52.727021 TX_ODT_DIS = 1
602 00:58:52.727113 NEW_8X_MODE = 1
603 00:58:52.730318 ===================================
604 00:58:52.733500 ===================================
605 00:58:52.737013 data_rate = 1600
606 00:58:52.740308 CKR = 1
607 00:58:52.743609 DQ_P2S_RATIO = 8
608 00:58:52.747219 ===================================
609 00:58:52.750305 CA_P2S_RATIO = 8
610 00:58:52.753689 DQ_CA_OPEN = 0
611 00:58:52.753803 DQ_SEMI_OPEN = 0
612 00:58:52.757099 CA_SEMI_OPEN = 0
613 00:58:52.760428 CA_FULL_RATE = 0
614 00:58:52.764034 DQ_CKDIV4_EN = 1
615 00:58:52.767126 CA_CKDIV4_EN = 1
616 00:58:52.767224 CA_PREDIV_EN = 0
617 00:58:52.770349 PH8_DLY = 0
618 00:58:52.774049 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 00:58:52.777406 DQ_AAMCK_DIV = 4
620 00:58:52.780733 CA_AAMCK_DIV = 4
621 00:58:52.784199 CA_ADMCK_DIV = 4
622 00:58:52.784295 DQ_TRACK_CA_EN = 0
623 00:58:52.786992 CA_PICK = 800
624 00:58:52.790451 CA_MCKIO = 800
625 00:58:52.793674 MCKIO_SEMI = 0
626 00:58:52.796929 PLL_FREQ = 3068
627 00:58:52.800289 DQ_UI_PI_RATIO = 32
628 00:58:52.803634 CA_UI_PI_RATIO = 0
629 00:58:52.806996 ===================================
630 00:58:52.810356 ===================================
631 00:58:52.810427 memory_type:LPDDR4
632 00:58:52.813750 GP_NUM : 10
633 00:58:52.817131 SRAM_EN : 1
634 00:58:52.817233 MD32_EN : 0
635 00:58:52.820352 ===================================
636 00:58:52.823799 [ANA_INIT] >>>>>>>>>>>>>>
637 00:58:52.827137 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 00:58:52.830552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 00:58:52.833907 ===================================
640 00:58:52.837055 data_rate = 1600,PCW = 0X7600
641 00:58:52.840402 ===================================
642 00:58:52.844004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 00:58:52.847328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:58:52.853786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 00:58:52.857265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 00:58:52.860612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:58:52.863956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 00:58:52.867428 [ANA_INIT] flow start
649 00:58:52.870555 [ANA_INIT] PLL >>>>>>>>
650 00:58:52.870643 [ANA_INIT] PLL <<<<<<<<
651 00:58:52.874197 [ANA_INIT] MIDPI >>>>>>>>
652 00:58:52.877251 [ANA_INIT] MIDPI <<<<<<<<
653 00:58:52.877355 [ANA_INIT] DLL >>>>>>>>
654 00:58:52.880798 [ANA_INIT] flow end
655 00:58:52.883950 ============ LP4 DIFF to SE enter ============
656 00:58:52.887028 ============ LP4 DIFF to SE exit ============
657 00:58:52.890384 [ANA_INIT] <<<<<<<<<<<<<
658 00:58:52.893715 [Flow] Enable top DCM control >>>>>
659 00:58:52.897079 [Flow] Enable top DCM control <<<<<
660 00:58:52.900928 Enable DLL master slave shuffle
661 00:58:52.907578 ==============================================================
662 00:58:52.907651 Gating Mode config
663 00:58:52.913724 ==============================================================
664 00:58:52.913802 Config description:
665 00:58:52.923970 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 00:58:52.930658 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 00:58:52.937447 SELPH_MODE 0: By rank 1: By Phase
668 00:58:52.940923 ==============================================================
669 00:58:52.944220 GAT_TRACK_EN = 1
670 00:58:52.947611 RX_GATING_MODE = 2
671 00:58:52.950928 RX_GATING_TRACK_MODE = 2
672 00:58:52.954139 SELPH_MODE = 1
673 00:58:52.957308 PICG_EARLY_EN = 1
674 00:58:52.960443 VALID_LAT_VALUE = 1
675 00:58:52.964419 ==============================================================
676 00:58:52.967627 Enter into Gating configuration >>>>
677 00:58:52.970829 Exit from Gating configuration <<<<
678 00:58:52.974298 Enter into DVFS_PRE_config >>>>>
679 00:58:52.987690 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 00:58:52.991060 Exit from DVFS_PRE_config <<<<<
681 00:58:52.991148 Enter into PICG configuration >>>>
682 00:58:52.993844 Exit from PICG configuration <<<<
683 00:58:52.997275 [RX_INPUT] configuration >>>>>
684 00:58:53.000847 [RX_INPUT] configuration <<<<<
685 00:58:53.007564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 00:58:53.011232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 00:58:53.017639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 00:58:53.024422 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 00:58:53.031046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 00:58:53.037809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 00:58:53.041140 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 00:58:53.044550 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 00:58:53.047835 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 00:58:53.054673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 00:58:53.058012 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 00:58:53.061179 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 00:58:53.064983 ===================================
698 00:58:53.067706 LPDDR4 DRAM CONFIGURATION
699 00:58:53.071142 ===================================
700 00:58:53.071209 EX_ROW_EN[0] = 0x0
701 00:58:53.074589 EX_ROW_EN[1] = 0x0
702 00:58:53.074679 LP4Y_EN = 0x0
703 00:58:53.078032 WORK_FSP = 0x0
704 00:58:53.078141 WL = 0x2
705 00:58:53.081180 RL = 0x2
706 00:58:53.081248 BL = 0x2
707 00:58:53.084579 RPST = 0x0
708 00:58:53.084655 RD_PRE = 0x0
709 00:58:53.087965 WR_PRE = 0x1
710 00:58:53.091050 WR_PST = 0x0
711 00:58:53.091114 DBI_WR = 0x0
712 00:58:53.094750 DBI_RD = 0x0
713 00:58:53.094841 OTF = 0x1
714 00:58:53.098433 ===================================
715 00:58:53.101541 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 00:58:53.104813 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 00:58:53.111524 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 00:58:53.114359 ===================================
719 00:58:53.117810 LPDDR4 DRAM CONFIGURATION
720 00:58:53.121222 ===================================
721 00:58:53.121317 EX_ROW_EN[0] = 0x10
722 00:58:53.124599 EX_ROW_EN[1] = 0x0
723 00:58:53.124694 LP4Y_EN = 0x0
724 00:58:53.128031 WORK_FSP = 0x0
725 00:58:53.128116 WL = 0x2
726 00:58:53.131373 RL = 0x2
727 00:58:53.131469 BL = 0x2
728 00:58:53.134472 RPST = 0x0
729 00:58:53.134566 RD_PRE = 0x0
730 00:58:53.137831 WR_PRE = 0x1
731 00:58:53.137917 WR_PST = 0x0
732 00:58:53.141200 DBI_WR = 0x0
733 00:58:53.141292 DBI_RD = 0x0
734 00:58:53.144651 OTF = 0x1
735 00:58:53.147968 ===================================
736 00:58:53.154673 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 00:58:53.157972 nWR fixed to 40
738 00:58:53.161402 [ModeRegInit_LP4] CH0 RK0
739 00:58:53.161493 [ModeRegInit_LP4] CH0 RK1
740 00:58:53.164655 [ModeRegInit_LP4] CH1 RK0
741 00:58:53.167973 [ModeRegInit_LP4] CH1 RK1
742 00:58:53.168049 match AC timing 13
743 00:58:53.174989 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 00:58:53.177758 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 00:58:53.181706 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 00:58:53.188275 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 00:58:53.191630 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 00:58:53.191698 [EMI DOE] emi_dcm 0
749 00:58:53.198307 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 00:58:53.198387 ==
751 00:58:53.201593 Dram Type= 6, Freq= 0, CH_0, rank 0
752 00:58:53.204713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 00:58:53.204781 ==
754 00:58:53.211919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 00:58:53.214613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 00:58:53.225192 [CA 0] Center 36 (6~67) winsize 62
757 00:58:53.228794 [CA 1] Center 36 (6~67) winsize 62
758 00:58:53.231759 [CA 2] Center 34 (4~65) winsize 62
759 00:58:53.235411 [CA 3] Center 33 (3~64) winsize 62
760 00:58:53.239093 [CA 4] Center 33 (2~64) winsize 63
761 00:58:53.242772 [CA 5] Center 32 (2~62) winsize 61
762 00:58:53.242866
763 00:58:53.246285 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 00:58:53.246354
765 00:58:53.249829 [CATrainingPosCal] consider 1 rank data
766 00:58:53.252971 u2DelayCellTimex100 = 270/100 ps
767 00:58:53.256296 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 00:58:53.259744 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 00:58:53.263136 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 00:58:53.266516 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
771 00:58:53.269771 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
772 00:58:53.273550 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
773 00:58:53.273644
774 00:58:53.280042 CA PerBit enable=1, Macro0, CA PI delay=32
775 00:58:53.280125
776 00:58:53.280186 [CBTSetCACLKResult] CA Dly = 32
777 00:58:53.283443 CS Dly: 5 (0~36)
778 00:58:53.283534 ==
779 00:58:53.286746 Dram Type= 6, Freq= 0, CH_0, rank 1
780 00:58:53.290191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:58:53.290261 ==
782 00:58:53.296546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 00:58:53.303269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 00:58:53.311287 [CA 0] Center 36 (6~67) winsize 62
785 00:58:53.314519 [CA 1] Center 36 (6~67) winsize 62
786 00:58:53.318248 [CA 2] Center 34 (4~65) winsize 62
787 00:58:53.321699 [CA 3] Center 33 (3~64) winsize 62
788 00:58:53.325080 [CA 4] Center 32 (2~63) winsize 62
789 00:58:53.327730 [CA 5] Center 32 (2~63) winsize 62
790 00:58:53.327794
791 00:58:53.331031 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 00:58:53.331099
793 00:58:53.335038 [CATrainingPosCal] consider 2 rank data
794 00:58:53.338261 u2DelayCellTimex100 = 270/100 ps
795 00:58:53.341214 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 00:58:53.344966 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 00:58:53.351520 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
798 00:58:53.354632 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
799 00:58:53.358417 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
800 00:58:53.361473 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
801 00:58:53.361571
802 00:58:53.364495 CA PerBit enable=1, Macro0, CA PI delay=32
803 00:58:53.364558
804 00:58:53.368119 [CBTSetCACLKResult] CA Dly = 32
805 00:58:53.368183 CS Dly: 5 (0~36)
806 00:58:53.368240
807 00:58:53.371398 ----->DramcWriteLeveling(PI) begin...
808 00:58:53.374687 ==
809 00:58:53.374754 Dram Type= 6, Freq= 0, CH_0, rank 0
810 00:58:53.381197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 00:58:53.381267 ==
812 00:58:53.384468 Write leveling (Byte 0): 32 => 32
813 00:58:53.388163 Write leveling (Byte 1): 30 => 30
814 00:58:53.391587 DramcWriteLeveling(PI) end<-----
815 00:58:53.391696
816 00:58:53.391781 ==
817 00:58:53.395002 Dram Type= 6, Freq= 0, CH_0, rank 0
818 00:58:53.398185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 00:58:53.398265 ==
820 00:58:53.401353 [Gating] SW mode calibration
821 00:58:53.408583 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 00:58:53.411432 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 00:58:53.418104 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 00:58:53.421435 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 00:58:53.424477 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 00:58:53.431619 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:58:53.435010 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:58:53.437815 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:58:53.444532 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:58:53.447711 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:58:53.451353 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:58:53.458521 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:58:53.461211 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 00:58:53.465057 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 00:58:53.471555 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 00:58:53.474735 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 00:58:53.478332 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:58:53.481335 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 00:58:53.488193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 00:58:53.491548 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 00:58:53.494765 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 00:58:53.501445 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 00:58:53.504813 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:58:53.508016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:58:53.515136 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:58:53.518469 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:58:53.521827 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 00:58:53.528562 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 00:58:53.531673 0 9 8 | B1->B0 | 2424 2e2e | 1 1 | (1 1) (1 1)
850 00:58:53.534814 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
851 00:58:53.541430 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 00:58:53.544924 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 00:58:53.548299 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 00:58:53.554934 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 00:58:53.557999 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 00:58:53.561824 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
857 00:58:53.564995 0 10 8 | B1->B0 | 3232 2626 | 1 0 | (1 1) (1 1)
858 00:58:53.571620 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:58:53.575020 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:58:53.578376 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:58:53.584870 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:58:53.588752 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:58:53.591716 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:58:53.598127 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
865 00:58:53.601706 0 11 8 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
866 00:58:53.605306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:58:53.612077 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:58:53.615425 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 00:58:53.618632 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 00:58:53.622277 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 00:58:53.628985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 00:58:53.632295 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 00:58:53.635686 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
874 00:58:53.642005 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:58:53.645648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:58:53.649062 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:58:53.655196 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:58:53.658620 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:58:53.661969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:58:53.669109 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:58:53.672292 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:58:53.675523 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:58:53.682400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:58:53.685768 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 00:58:53.689165 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 00:58:53.692627 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 00:58:53.699041 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 00:58:53.702177 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 00:58:53.705326 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 00:58:53.709088 Total UI for P1: 0, mck2ui 16
891 00:58:53.712249 best dqsien dly found for B0: ( 0, 14, 4)
892 00:58:53.719178 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 00:58:53.719256 Total UI for P1: 0, mck2ui 16
894 00:58:53.725770 best dqsien dly found for B1: ( 0, 14, 8)
895 00:58:53.729031 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
896 00:58:53.732664 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 00:58:53.732743
898 00:58:53.735949 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
899 00:58:53.739258 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 00:58:53.742749 [Gating] SW calibration Done
901 00:58:53.742827 ==
902 00:58:53.746082 Dram Type= 6, Freq= 0, CH_0, rank 0
903 00:58:53.749307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 00:58:53.749386 ==
905 00:58:53.752464 RX Vref Scan: 0
906 00:58:53.752543
907 00:58:53.752603 RX Vref 0 -> 0, step: 1
908 00:58:53.752661
909 00:58:53.756213 RX Delay -130 -> 252, step: 16
910 00:58:53.759524 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 00:58:53.766122 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
912 00:58:53.769327 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 00:58:53.772625 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 00:58:53.775979 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 00:58:53.779166 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 00:58:53.785670 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
917 00:58:53.789349 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
918 00:58:53.792639 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 00:58:53.796063 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
920 00:58:53.799395 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
921 00:58:53.805977 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
922 00:58:53.809119 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 00:58:53.812402 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 00:58:53.816364 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
925 00:58:53.819093 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 00:58:53.819173 ==
927 00:58:53.823006 Dram Type= 6, Freq= 0, CH_0, rank 0
928 00:58:53.829468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 00:58:53.829554 ==
930 00:58:53.829617 DQS Delay:
931 00:58:53.832565 DQS0 = 0, DQS1 = 0
932 00:58:53.832644 DQM Delay:
933 00:58:53.832705 DQM0 = 89, DQM1 = 80
934 00:58:53.836432 DQ Delay:
935 00:58:53.839578 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
936 00:58:53.842550 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
937 00:58:53.846267 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
938 00:58:53.849482 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
939 00:58:53.849567
940 00:58:53.849629
941 00:58:53.849685 ==
942 00:58:53.852628 Dram Type= 6, Freq= 0, CH_0, rank 0
943 00:58:53.855983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 00:58:53.856062 ==
945 00:58:53.856122
946 00:58:53.856178
947 00:58:53.859107 TX Vref Scan disable
948 00:58:53.859185 == TX Byte 0 ==
949 00:58:53.865996 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
950 00:58:53.869338 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
951 00:58:53.869415 == TX Byte 1 ==
952 00:58:53.875979 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
953 00:58:53.879724 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
954 00:58:53.879803 ==
955 00:58:53.883067 Dram Type= 6, Freq= 0, CH_0, rank 0
956 00:58:53.886307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 00:58:53.886386 ==
958 00:58:53.900125 TX Vref=22, minBit 8, minWin=27, winSum=449
959 00:58:53.903523 TX Vref=24, minBit 8, minWin=27, winSum=453
960 00:58:53.906989 TX Vref=26, minBit 10, minWin=27, winSum=454
961 00:58:53.910224 TX Vref=28, minBit 8, minWin=28, winSum=459
962 00:58:53.913707 TX Vref=30, minBit 8, minWin=28, winSum=459
963 00:58:53.916977 TX Vref=32, minBit 8, minWin=28, winSum=456
964 00:58:53.923530 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
965 00:58:53.923606
966 00:58:53.926930 Final TX Range 1 Vref 28
967 00:58:53.927001
968 00:58:53.927067 ==
969 00:58:53.930254 Dram Type= 6, Freq= 0, CH_0, rank 0
970 00:58:53.933500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 00:58:53.933617 ==
972 00:58:53.933680
973 00:58:53.936735
974 00:58:53.936810 TX Vref Scan disable
975 00:58:53.940133 == TX Byte 0 ==
976 00:58:53.943585 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 00:58:53.946773 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 00:58:53.950601 == TX Byte 1 ==
979 00:58:53.953729 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 00:58:53.957381 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 00:58:53.957475
982 00:58:53.960432 [DATLAT]
983 00:58:53.960503 Freq=800, CH0 RK0
984 00:58:53.960560
985 00:58:53.963660 DATLAT Default: 0xa
986 00:58:53.963727 0, 0xFFFF, sum = 0
987 00:58:53.967406 1, 0xFFFF, sum = 0
988 00:58:53.967473 2, 0xFFFF, sum = 0
989 00:58:53.970398 3, 0xFFFF, sum = 0
990 00:58:53.970471 4, 0xFFFF, sum = 0
991 00:58:53.973926 5, 0xFFFF, sum = 0
992 00:58:53.973996 6, 0xFFFF, sum = 0
993 00:58:53.977237 7, 0xFFFF, sum = 0
994 00:58:53.980298 8, 0xFFFF, sum = 0
995 00:58:53.980375 9, 0x0, sum = 1
996 00:58:53.980435 10, 0x0, sum = 2
997 00:58:53.983598 11, 0x0, sum = 3
998 00:58:53.983678 12, 0x0, sum = 4
999 00:58:53.986984 best_step = 10
1000 00:58:53.987063
1001 00:58:53.987123 ==
1002 00:58:53.990296 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 00:58:53.993457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 00:58:53.993536 ==
1005 00:58:53.997435 RX Vref Scan: 1
1006 00:58:53.997513
1007 00:58:53.997586 Set Vref Range= 32 -> 127
1008 00:58:53.997645
1009 00:58:54.000740 RX Vref 32 -> 127, step: 1
1010 00:58:54.000817
1011 00:58:54.003959 RX Delay -95 -> 252, step: 8
1012 00:58:54.004046
1013 00:58:54.007205 Set Vref, RX VrefLevel [Byte0]: 32
1014 00:58:54.010736 [Byte1]: 32
1015 00:58:54.010814
1016 00:58:54.014096 Set Vref, RX VrefLevel [Byte0]: 33
1017 00:58:54.016888 [Byte1]: 33
1018 00:58:54.020850
1019 00:58:54.020928 Set Vref, RX VrefLevel [Byte0]: 34
1020 00:58:54.024091 [Byte1]: 34
1021 00:58:54.027985
1022 00:58:54.028073 Set Vref, RX VrefLevel [Byte0]: 35
1023 00:58:54.031393 [Byte1]: 35
1024 00:58:54.035551
1025 00:58:54.035622 Set Vref, RX VrefLevel [Byte0]: 36
1026 00:58:54.038763 [Byte1]: 36
1027 00:58:54.043728
1028 00:58:54.043822 Set Vref, RX VrefLevel [Byte0]: 37
1029 00:58:54.046444 [Byte1]: 37
1030 00:58:54.051147
1031 00:58:54.051218 Set Vref, RX VrefLevel [Byte0]: 38
1032 00:58:54.054574 [Byte1]: 38
1033 00:58:54.058723
1034 00:58:54.058817 Set Vref, RX VrefLevel [Byte0]: 39
1035 00:58:54.061909 [Byte1]: 39
1036 00:58:54.066333
1037 00:58:54.066426 Set Vref, RX VrefLevel [Byte0]: 40
1038 00:58:54.069458 [Byte1]: 40
1039 00:58:54.073554
1040 00:58:54.073624 Set Vref, RX VrefLevel [Byte0]: 41
1041 00:58:54.076852 [Byte1]: 41
1042 00:58:54.081653
1043 00:58:54.081730 Set Vref, RX VrefLevel [Byte0]: 42
1044 00:58:54.084720 [Byte1]: 42
1045 00:58:54.089060
1046 00:58:54.089138 Set Vref, RX VrefLevel [Byte0]: 43
1047 00:58:54.092136 [Byte1]: 43
1048 00:58:54.096571
1049 00:58:54.096648 Set Vref, RX VrefLevel [Byte0]: 44
1050 00:58:54.099957 [Byte1]: 44
1051 00:58:54.103976
1052 00:58:54.104081 Set Vref, RX VrefLevel [Byte0]: 45
1053 00:58:54.107764 [Byte1]: 45
1054 00:58:54.111573
1055 00:58:54.111668 Set Vref, RX VrefLevel [Byte0]: 46
1056 00:58:54.114950 [Byte1]: 46
1057 00:58:54.119576
1058 00:58:54.119674 Set Vref, RX VrefLevel [Byte0]: 47
1059 00:58:54.122947 [Byte1]: 47
1060 00:58:54.126950
1061 00:58:54.127027 Set Vref, RX VrefLevel [Byte0]: 48
1062 00:58:54.130096 [Byte1]: 48
1063 00:58:54.134531
1064 00:58:54.134602 Set Vref, RX VrefLevel [Byte0]: 49
1065 00:58:54.137959 [Byte1]: 49
1066 00:58:54.141998
1067 00:58:54.142088 Set Vref, RX VrefLevel [Byte0]: 50
1068 00:58:54.145354 [Byte1]: 50
1069 00:58:54.149722
1070 00:58:54.149795 Set Vref, RX VrefLevel [Byte0]: 51
1071 00:58:54.152932 [Byte1]: 51
1072 00:58:54.157070
1073 00:58:54.157156 Set Vref, RX VrefLevel [Byte0]: 52
1074 00:58:54.160365 [Byte1]: 52
1075 00:58:54.165013
1076 00:58:54.165087 Set Vref, RX VrefLevel [Byte0]: 53
1077 00:58:54.168392 [Byte1]: 53
1078 00:58:54.172433
1079 00:58:54.172510 Set Vref, RX VrefLevel [Byte0]: 54
1080 00:58:54.175666 [Byte1]: 54
1081 00:58:54.180037
1082 00:58:54.180108 Set Vref, RX VrefLevel [Byte0]: 55
1083 00:58:54.183708 [Byte1]: 55
1084 00:58:54.187670
1085 00:58:54.187747 Set Vref, RX VrefLevel [Byte0]: 56
1086 00:58:54.191130 [Byte1]: 56
1087 00:58:54.195167
1088 00:58:54.195244 Set Vref, RX VrefLevel [Byte0]: 57
1089 00:58:54.198502 [Byte1]: 57
1090 00:58:54.202968
1091 00:58:54.203062 Set Vref, RX VrefLevel [Byte0]: 58
1092 00:58:54.206058 [Byte1]: 58
1093 00:58:54.210815
1094 00:58:54.210892 Set Vref, RX VrefLevel [Byte0]: 59
1095 00:58:54.213701 [Byte1]: 59
1096 00:58:54.218277
1097 00:58:54.218355 Set Vref, RX VrefLevel [Byte0]: 60
1098 00:58:54.221737 [Byte1]: 60
1099 00:58:54.225947
1100 00:58:54.226025 Set Vref, RX VrefLevel [Byte0]: 61
1101 00:58:54.228816 [Byte1]: 61
1102 00:58:54.233343
1103 00:58:54.233445 Set Vref, RX VrefLevel [Byte0]: 62
1104 00:58:54.236630 [Byte1]: 62
1105 00:58:54.241149
1106 00:58:54.241244 Set Vref, RX VrefLevel [Byte0]: 63
1107 00:58:54.244552 [Byte1]: 63
1108 00:58:54.248518
1109 00:58:54.248609 Set Vref, RX VrefLevel [Byte0]: 64
1110 00:58:54.251945 [Byte1]: 64
1111 00:58:54.256513
1112 00:58:54.256604 Set Vref, RX VrefLevel [Byte0]: 65
1113 00:58:54.259718 [Byte1]: 65
1114 00:58:54.263460
1115 00:58:54.263530 Set Vref, RX VrefLevel [Byte0]: 66
1116 00:58:54.266951 [Byte1]: 66
1117 00:58:54.271589
1118 00:58:54.271688 Set Vref, RX VrefLevel [Byte0]: 67
1119 00:58:54.275000 [Byte1]: 67
1120 00:58:54.279029
1121 00:58:54.279098 Set Vref, RX VrefLevel [Byte0]: 68
1122 00:58:54.282328 [Byte1]: 68
1123 00:58:54.286338
1124 00:58:54.286407 Set Vref, RX VrefLevel [Byte0]: 69
1125 00:58:54.289722 [Byte1]: 69
1126 00:58:54.294082
1127 00:58:54.294151 Set Vref, RX VrefLevel [Byte0]: 70
1128 00:58:54.297223 [Byte1]: 70
1129 00:58:54.301991
1130 00:58:54.302062 Set Vref, RX VrefLevel [Byte0]: 71
1131 00:58:54.305280 [Byte1]: 71
1132 00:58:54.309277
1133 00:58:54.309354 Set Vref, RX VrefLevel [Byte0]: 72
1134 00:58:54.312591 [Byte1]: 72
1135 00:58:54.317363
1136 00:58:54.317440 Set Vref, RX VrefLevel [Byte0]: 73
1137 00:58:54.320598 [Byte1]: 73
1138 00:58:54.324627
1139 00:58:54.324704 Set Vref, RX VrefLevel [Byte0]: 74
1140 00:58:54.327715 [Byte1]: 74
1141 00:58:54.332256
1142 00:58:54.332333 Set Vref, RX VrefLevel [Byte0]: 75
1143 00:58:54.335344 [Byte1]: 75
1144 00:58:54.339777
1145 00:58:54.339854 Set Vref, RX VrefLevel [Byte0]: 76
1146 00:58:54.342847 [Byte1]: 76
1147 00:58:54.347572
1148 00:58:54.347650 Set Vref, RX VrefLevel [Byte0]: 77
1149 00:58:54.350574 [Byte1]: 77
1150 00:58:54.354635
1151 00:58:54.354712 Final RX Vref Byte 0 = 62 to rank0
1152 00:58:54.358607 Final RX Vref Byte 1 = 59 to rank0
1153 00:58:54.361329 Final RX Vref Byte 0 = 62 to rank1
1154 00:58:54.365240 Final RX Vref Byte 1 = 59 to rank1==
1155 00:58:54.368336 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 00:58:54.374965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 00:58:54.375043 ==
1158 00:58:54.375105 DQS Delay:
1159 00:58:54.375161 DQS0 = 0, DQS1 = 0
1160 00:58:54.378316 DQM Delay:
1161 00:58:54.378392 DQM0 = 92, DQM1 = 84
1162 00:58:54.381650 DQ Delay:
1163 00:58:54.384987 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1164 00:58:54.388343 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1165 00:58:54.388421 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1166 00:58:54.394977 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1167 00:58:54.395054
1168 00:58:54.395114
1169 00:58:54.401988 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1170 00:58:54.405219 CH0 RK0: MR19=606, MR18=4C42
1171 00:58:54.411801 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1172 00:58:54.411880
1173 00:58:54.415034 ----->DramcWriteLeveling(PI) begin...
1174 00:58:54.415114 ==
1175 00:58:54.418490 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 00:58:54.421827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 00:58:54.421906 ==
1178 00:58:54.425027 Write leveling (Byte 0): 34 => 34
1179 00:58:54.428316 Write leveling (Byte 1): 31 => 31
1180 00:58:54.431745 DramcWriteLeveling(PI) end<-----
1181 00:58:54.431821
1182 00:58:54.431878 ==
1183 00:58:54.434965 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 00:58:54.438125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 00:58:54.438204 ==
1186 00:58:54.441680 [Gating] SW mode calibration
1187 00:58:54.448375 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 00:58:54.454951 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 00:58:54.458244 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 00:58:54.502254 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1191 00:58:54.502525 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1192 00:58:54.502591 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:58:54.502649 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:58:54.502705 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:58:54.502768 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:58:54.503006 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 00:58:54.503068 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 00:58:54.503122 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:58:54.503184 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:58:54.518396 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:58:54.519001 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 00:58:54.521970 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 00:58:54.522080 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 00:58:54.525278 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:58:54.528583 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 00:58:54.531988 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1207 00:58:54.538131 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1208 00:58:54.541523 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 00:58:54.545282 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 00:58:54.551470 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 00:58:54.554684 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 00:58:54.558170 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 00:58:54.564838 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 00:58:54.568259 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 00:58:54.571621 0 9 8 | B1->B0 | 2f2f 2c2c | 0 0 | (1 1) (1 0)
1216 00:58:54.578269 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 00:58:54.581370 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 00:58:54.585022 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 00:58:54.591614 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 00:58:54.594972 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 00:58:54.598273 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 00:58:54.604562 0 10 4 | B1->B0 | 3030 3434 | 0 0 | (0 1) (0 0)
1223 00:58:54.607951 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
1224 00:58:54.611345 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:58:54.617850 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:58:54.621762 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:58:54.625106 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:58:54.631315 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:58:54.634540 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:58:54.638370 0 11 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1231 00:58:54.641692 0 11 8 | B1->B0 | 4242 3737 | 0 0 | (0 0) (0 0)
1232 00:58:54.648256 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 00:58:54.651615 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 00:58:54.654831 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 00:58:54.661497 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 00:58:54.664681 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 00:58:54.668614 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 00:58:54.674682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 00:58:54.678069 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1240 00:58:54.681406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1241 00:58:54.688629 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 00:58:54.691931 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 00:58:54.695299 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 00:58:54.701973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 00:58:54.705095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 00:58:54.708230 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 00:58:54.711701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 00:58:54.718256 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 00:58:54.721642 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 00:58:54.724793 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 00:58:54.731841 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 00:58:54.735085 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 00:58:54.738662 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 00:58:54.745476 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 00:58:54.748672 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1256 00:58:54.752035 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:58:54.755362 Total UI for P1: 0, mck2ui 16
1258 00:58:54.758702 best dqsien dly found for B0: ( 0, 14, 8)
1259 00:58:54.762026 Total UI for P1: 0, mck2ui 16
1260 00:58:54.765367 best dqsien dly found for B1: ( 0, 14, 8)
1261 00:58:54.768563 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1262 00:58:54.772114 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1263 00:58:54.772192
1264 00:58:54.775768 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1265 00:58:54.779077 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1266 00:58:54.782388 [Gating] SW calibration Done
1267 00:58:54.782469 ==
1268 00:58:54.785147 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 00:58:54.792440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 00:58:54.792521 ==
1271 00:58:54.792582 RX Vref Scan: 0
1272 00:58:54.792639
1273 00:58:54.795732 RX Vref 0 -> 0, step: 1
1274 00:58:54.795794
1275 00:58:54.799152 RX Delay -130 -> 252, step: 16
1276 00:58:54.802547 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1277 00:58:54.805869 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1278 00:58:54.808620 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1279 00:58:54.811985 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1280 00:58:54.819183 iDelay=222, Bit 4, Center 101 (-2 ~ 205) 208
1281 00:58:54.822560 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1282 00:58:54.826015 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1283 00:58:54.829272 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1284 00:58:54.832464 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1285 00:58:54.839174 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1286 00:58:54.842614 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1287 00:58:54.845853 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1288 00:58:54.849055 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1289 00:58:54.852295 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1290 00:58:54.858926 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1291 00:58:54.862557 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1292 00:58:54.862632 ==
1293 00:58:54.866057 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 00:58:54.869330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 00:58:54.869405 ==
1296 00:58:54.872798 DQS Delay:
1297 00:58:54.872863 DQS0 = 0, DQS1 = 0
1298 00:58:54.872927 DQM Delay:
1299 00:58:54.876221 DQM0 = 95, DQM1 = 81
1300 00:58:54.876286 DQ Delay:
1301 00:58:54.879779 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1302 00:58:54.882777 DQ4 =101, DQ5 =85, DQ6 =101, DQ7 =109
1303 00:58:54.885957 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1304 00:58:54.889315 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1305 00:58:54.889378
1306 00:58:54.889439
1307 00:58:54.889491 ==
1308 00:58:54.892623 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 00:58:54.899217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 00:58:54.899299 ==
1311 00:58:54.899358
1312 00:58:54.899412
1313 00:58:54.899464 TX Vref Scan disable
1314 00:58:54.902701 == TX Byte 0 ==
1315 00:58:54.905941 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1316 00:58:54.909273 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1317 00:58:54.912586 == TX Byte 1 ==
1318 00:58:54.916005 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1319 00:58:54.919224 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1320 00:58:54.922499 ==
1321 00:58:54.925829 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 00:58:54.929094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 00:58:54.929160 ==
1324 00:58:54.941848 TX Vref=22, minBit 8, minWin=27, winSum=446
1325 00:58:54.945362 TX Vref=24, minBit 1, minWin=28, winSum=452
1326 00:58:54.948702 TX Vref=26, minBit 1, minWin=28, winSum=457
1327 00:58:54.952104 TX Vref=28, minBit 1, minWin=28, winSum=459
1328 00:58:54.955216 TX Vref=30, minBit 7, minWin=28, winSum=462
1329 00:58:54.958857 TX Vref=32, minBit 1, minWin=28, winSum=452
1330 00:58:54.965474 [TxChooseVref] Worse bit 7, Min win 28, Win sum 462, Final Vref 30
1331 00:58:54.965583
1332 00:58:54.968576 Final TX Range 1 Vref 30
1333 00:58:54.968644
1334 00:58:54.968700 ==
1335 00:58:54.972254 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 00:58:54.975255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 00:58:54.975344 ==
1338 00:58:54.975426
1339 00:58:54.978581
1340 00:58:54.978645 TX Vref Scan disable
1341 00:58:54.981877 == TX Byte 0 ==
1342 00:58:54.985353 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1343 00:58:54.988288 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1344 00:58:54.991789 == TX Byte 1 ==
1345 00:58:54.995339 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 00:58:54.998926 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 00:58:55.001851
1348 00:58:55.001922 [DATLAT]
1349 00:58:55.001984 Freq=800, CH0 RK1
1350 00:58:55.002039
1351 00:58:55.005541 DATLAT Default: 0xa
1352 00:58:55.005625 0, 0xFFFF, sum = 0
1353 00:58:55.008733 1, 0xFFFF, sum = 0
1354 00:58:55.008806 2, 0xFFFF, sum = 0
1355 00:58:55.012005 3, 0xFFFF, sum = 0
1356 00:58:55.012071 4, 0xFFFF, sum = 0
1357 00:58:55.015444 5, 0xFFFF, sum = 0
1358 00:58:55.015510 6, 0xFFFF, sum = 0
1359 00:58:55.018814 7, 0xFFFF, sum = 0
1360 00:58:55.022277 8, 0xFFFF, sum = 0
1361 00:58:55.022354 9, 0x0, sum = 1
1362 00:58:55.022414 10, 0x0, sum = 2
1363 00:58:55.024970 11, 0x0, sum = 3
1364 00:58:55.025036 12, 0x0, sum = 4
1365 00:58:55.028822 best_step = 10
1366 00:58:55.028902
1367 00:58:55.028959 ==
1368 00:58:55.032155 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 00:58:55.035501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 00:58:55.035580 ==
1371 00:58:55.038939 RX Vref Scan: 0
1372 00:58:55.039014
1373 00:58:55.039084 RX Vref 0 -> 0, step: 1
1374 00:58:55.039146
1375 00:58:55.042376 RX Delay -95 -> 252, step: 8
1376 00:58:55.048465 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1377 00:58:55.051835 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1378 00:58:55.055205 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1379 00:58:55.058568 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1380 00:58:55.061957 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1381 00:58:55.068686 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1382 00:58:55.071972 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1383 00:58:55.075303 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1384 00:58:55.078656 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1385 00:58:55.082078 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1386 00:58:55.085418 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1387 00:58:55.092046 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1388 00:58:55.095161 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1389 00:58:55.098646 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1390 00:58:55.102211 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1391 00:58:55.108631 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1392 00:58:55.108709 ==
1393 00:58:55.112048 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 00:58:55.115409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 00:58:55.115481 ==
1396 00:58:55.115540 DQS Delay:
1397 00:58:55.118667 DQS0 = 0, DQS1 = 0
1398 00:58:55.118740 DQM Delay:
1399 00:58:55.121646 DQM0 = 92, DQM1 = 82
1400 00:58:55.121718 DQ Delay:
1401 00:58:55.125482 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1402 00:58:55.128344 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1403 00:58:55.132209 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1404 00:58:55.135327 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1405 00:58:55.135400
1406 00:58:55.135458
1407 00:58:55.142034 [DQSOSCAuto] RK1, (LSB)MR18= 0x4515, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1408 00:58:55.145373 CH0 RK1: MR19=606, MR18=4515
1409 00:58:55.152132 CH0_RK1: MR19=0x606, MR18=0x4515, DQSOSC=392, MR23=63, INC=96, DEC=64
1410 00:58:55.155518 [RxdqsGatingPostProcess] freq 800
1411 00:58:55.162396 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 00:58:55.165667 Pre-setting of DQS Precalculation
1413 00:58:55.169041 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 00:58:55.169142 ==
1415 00:58:55.172255 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 00:58:55.175429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 00:58:55.175501 ==
1418 00:58:55.182248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 00:58:55.188319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 00:58:55.196969 [CA 0] Center 36 (6~67) winsize 62
1421 00:58:55.200384 [CA 1] Center 36 (6~67) winsize 62
1422 00:58:55.203439 [CA 2] Center 35 (4~66) winsize 63
1423 00:58:55.206600 [CA 3] Center 34 (4~65) winsize 62
1424 00:58:55.209978 [CA 4] Center 34 (4~65) winsize 62
1425 00:58:55.213312 [CA 5] Center 34 (4~64) winsize 61
1426 00:58:55.213389
1427 00:58:55.216529 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 00:58:55.216606
1429 00:58:55.220471 [CATrainingPosCal] consider 1 rank data
1430 00:58:55.223127 u2DelayCellTimex100 = 270/100 ps
1431 00:58:55.226466 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 00:58:55.233313 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 00:58:55.236998 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1434 00:58:55.240383 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 00:58:55.243578 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 00:58:55.247009 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1437 00:58:55.247086
1438 00:58:55.250592 CA PerBit enable=1, Macro0, CA PI delay=34
1439 00:58:55.250663
1440 00:58:55.253502 [CBTSetCACLKResult] CA Dly = 34
1441 00:58:55.253594 CS Dly: 5 (0~36)
1442 00:58:55.253655 ==
1443 00:58:55.256929 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 00:58:55.263954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 00:58:55.264032 ==
1446 00:58:55.266786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 00:58:55.273467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 00:58:55.282958 [CA 0] Center 36 (6~67) winsize 62
1449 00:58:55.286648 [CA 1] Center 37 (6~68) winsize 63
1450 00:58:55.289585 [CA 2] Center 35 (4~66) winsize 63
1451 00:58:55.293366 [CA 3] Center 34 (4~65) winsize 62
1452 00:58:55.296707 [CA 4] Center 35 (5~66) winsize 62
1453 00:58:55.299443 [CA 5] Center 34 (4~65) winsize 62
1454 00:58:55.299514
1455 00:58:55.302907 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1456 00:58:55.302981
1457 00:58:55.306292 [CATrainingPosCal] consider 2 rank data
1458 00:58:55.309476 u2DelayCellTimex100 = 270/100 ps
1459 00:58:55.313307 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 00:58:55.316517 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 00:58:55.323214 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1462 00:58:55.326554 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 00:58:55.329998 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 00:58:55.333324 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 00:58:55.333394
1466 00:58:55.336663 CA PerBit enable=1, Macro0, CA PI delay=34
1467 00:58:55.336752
1468 00:58:55.339426 [CBTSetCACLKResult] CA Dly = 34
1469 00:58:55.339548 CS Dly: 6 (0~38)
1470 00:58:55.339620
1471 00:58:55.343009 ----->DramcWriteLeveling(PI) begin...
1472 00:58:55.346240 ==
1473 00:58:55.346306 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 00:58:55.352995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 00:58:55.353065 ==
1476 00:58:55.356294 Write leveling (Byte 0): 27 => 27
1477 00:58:55.360043 Write leveling (Byte 1): 28 => 28
1478 00:58:55.360111 DramcWriteLeveling(PI) end<-----
1479 00:58:55.363197
1480 00:58:55.363268 ==
1481 00:58:55.366503 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 00:58:55.370239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 00:58:55.370341 ==
1484 00:58:55.373197 [Gating] SW mode calibration
1485 00:58:55.379886 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 00:58:55.383407 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 00:58:55.390048 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 00:58:55.393133 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1489 00:58:55.396840 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1490 00:58:55.403090 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:58:55.406778 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:58:55.410142 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:58:55.416727 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:58:55.419920 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 00:58:55.423304 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 00:58:55.429954 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 00:58:55.433301 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 00:58:55.436664 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 00:58:55.442914 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 00:58:55.446301 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 00:58:55.449695 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:58:55.452944 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:58:55.459844 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1504 00:58:55.463129 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1505 00:58:55.466352 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 00:58:55.472817 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 00:58:55.476183 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 00:58:55.479583 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 00:58:55.486261 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 00:58:55.490043 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 00:58:55.493313 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 00:58:55.499739 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1513 00:58:55.502932 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1514 00:58:55.506501 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 00:58:55.513353 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 00:58:55.516332 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 00:58:55.519595 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 00:58:55.526558 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 00:58:55.529933 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 1)
1520 00:58:55.533240 0 10 4 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 1)
1521 00:58:55.540254 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:58:55.542936 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:58:55.546282 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:58:55.549703 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:58:55.556317 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:58:55.559668 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:58:55.562975 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1528 00:58:55.570243 0 11 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (0 0)
1529 00:58:55.573342 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1530 00:58:55.576571 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 00:58:55.583302 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 00:58:55.586633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 00:58:55.590022 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 00:58:55.596845 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 00:58:55.599972 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 00:58:55.603331 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1537 00:58:55.609909 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 00:58:55.613189 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 00:58:55.616540 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 00:58:55.619978 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 00:58:55.626514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 00:58:55.630272 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 00:58:55.633225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 00:58:55.639961 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 00:58:55.643484 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 00:58:55.646993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 00:58:55.653267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 00:58:55.656808 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 00:58:55.659873 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 00:58:55.666539 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 00:58:55.670501 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 00:58:55.673178 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1553 00:58:55.677017 Total UI for P1: 0, mck2ui 16
1554 00:58:55.680107 best dqsien dly found for B0: ( 0, 14, 2)
1555 00:58:55.686741 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 00:58:55.686816 Total UI for P1: 0, mck2ui 16
1557 00:58:55.690139 best dqsien dly found for B1: ( 0, 14, 4)
1558 00:58:55.696952 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1559 00:58:55.700304 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1560 00:58:55.700375
1561 00:58:55.703518 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1562 00:58:55.706687 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1563 00:58:55.709939 [Gating] SW calibration Done
1564 00:58:55.710015 ==
1565 00:58:55.713917 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 00:58:55.716611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 00:58:55.716682 ==
1568 00:58:55.716741 RX Vref Scan: 0
1569 00:58:55.720417
1570 00:58:55.720489 RX Vref 0 -> 0, step: 1
1571 00:58:55.720547
1572 00:58:55.723838 RX Delay -130 -> 252, step: 16
1573 00:58:55.726637 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1574 00:58:55.730008 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1575 00:58:55.736775 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1576 00:58:55.740566 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1577 00:58:55.743363 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1578 00:58:55.747219 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1579 00:58:55.750632 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1580 00:58:55.756746 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1581 00:58:55.760538 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1582 00:58:55.763587 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1583 00:58:55.767077 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1584 00:58:55.770425 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1585 00:58:55.777065 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1586 00:58:55.780250 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1587 00:58:55.783451 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1588 00:58:55.787234 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1589 00:58:55.787333 ==
1590 00:58:55.790114 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 00:58:55.797345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 00:58:55.797436 ==
1593 00:58:55.797497 DQS Delay:
1594 00:58:55.797563 DQS0 = 0, DQS1 = 0
1595 00:58:55.800711 DQM Delay:
1596 00:58:55.800780 DQM0 = 94, DQM1 = 90
1597 00:58:55.803388 DQ Delay:
1598 00:58:55.806818 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1599 00:58:55.810041 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1600 00:58:55.813924 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1601 00:58:55.816840 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1602 00:58:55.816909
1603 00:58:55.816979
1604 00:58:55.817051 ==
1605 00:58:55.820563 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 00:58:55.823859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 00:58:55.823963 ==
1608 00:58:55.824023
1609 00:58:55.824089
1610 00:58:55.827118 TX Vref Scan disable
1611 00:58:55.827229 == TX Byte 0 ==
1612 00:58:55.833677 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1613 00:58:55.837053 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1614 00:58:55.840355 == TX Byte 1 ==
1615 00:58:55.843663 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1616 00:58:55.847096 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1617 00:58:55.847183 ==
1618 00:58:55.850412 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 00:58:55.853680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 00:58:55.853764 ==
1621 00:58:55.867943 TX Vref=22, minBit 1, minWin=26, winSum=438
1622 00:58:55.871316 TX Vref=24, minBit 1, minWin=26, winSum=443
1623 00:58:55.874679 TX Vref=26, minBit 1, minWin=27, winSum=446
1624 00:58:55.877523 TX Vref=28, minBit 2, minWin=27, winSum=450
1625 00:58:55.881321 TX Vref=30, minBit 1, minWin=27, winSum=449
1626 00:58:55.884470 TX Vref=32, minBit 7, minWin=26, winSum=448
1627 00:58:55.891129 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
1628 00:58:55.891257
1629 00:58:55.894559 Final TX Range 1 Vref 28
1630 00:58:55.894699
1631 00:58:55.894786 ==
1632 00:58:55.897960 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 00:58:55.901281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 00:58:55.901398 ==
1635 00:58:55.901491
1636 00:58:55.901624
1637 00:58:55.904498 TX Vref Scan disable
1638 00:58:55.907969 == TX Byte 0 ==
1639 00:58:55.911210 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1640 00:58:55.914562 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1641 00:58:55.918041 == TX Byte 1 ==
1642 00:58:55.921414 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 00:58:55.924683 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 00:58:55.924793
1645 00:58:55.927781 [DATLAT]
1646 00:58:55.927902 Freq=800, CH1 RK0
1647 00:58:55.928001
1648 00:58:55.931015 DATLAT Default: 0xa
1649 00:58:55.931120 0, 0xFFFF, sum = 0
1650 00:58:55.934432 1, 0xFFFF, sum = 0
1651 00:58:55.934525 2, 0xFFFF, sum = 0
1652 00:58:55.937644 3, 0xFFFF, sum = 0
1653 00:58:55.937727 4, 0xFFFF, sum = 0
1654 00:58:55.941103 5, 0xFFFF, sum = 0
1655 00:58:55.941210 6, 0xFFFF, sum = 0
1656 00:58:55.944346 7, 0xFFFF, sum = 0
1657 00:58:55.944463 8, 0xFFFF, sum = 0
1658 00:58:55.947727 9, 0x0, sum = 1
1659 00:58:55.947854 10, 0x0, sum = 2
1660 00:58:55.951059 11, 0x0, sum = 3
1661 00:58:55.951168 12, 0x0, sum = 4
1662 00:58:55.954470 best_step = 10
1663 00:58:55.954554
1664 00:58:55.954615 ==
1665 00:58:55.957868 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 00:58:55.961201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 00:58:55.961283 ==
1668 00:58:55.964478 RX Vref Scan: 1
1669 00:58:55.964557
1670 00:58:55.964618 Set Vref Range= 32 -> 127
1671 00:58:55.964675
1672 00:58:55.968376 RX Vref 32 -> 127, step: 1
1673 00:58:55.968456
1674 00:58:55.971377 RX Delay -79 -> 252, step: 8
1675 00:58:55.971462
1676 00:58:55.974846 Set Vref, RX VrefLevel [Byte0]: 32
1677 00:58:55.978088 [Byte1]: 32
1678 00:58:55.978169
1679 00:58:55.981441 Set Vref, RX VrefLevel [Byte0]: 33
1680 00:58:55.984707 [Byte1]: 33
1681 00:58:55.984788
1682 00:58:55.988088 Set Vref, RX VrefLevel [Byte0]: 34
1683 00:58:55.991303 [Byte1]: 34
1684 00:58:55.995296
1685 00:58:55.995374 Set Vref, RX VrefLevel [Byte0]: 35
1686 00:58:55.998600 [Byte1]: 35
1687 00:58:56.003148
1688 00:58:56.003227 Set Vref, RX VrefLevel [Byte0]: 36
1689 00:58:56.006422 [Byte1]: 36
1690 00:58:56.010154
1691 00:58:56.010232 Set Vref, RX VrefLevel [Byte0]: 37
1692 00:58:56.013854 [Byte1]: 37
1693 00:58:56.017823
1694 00:58:56.017908 Set Vref, RX VrefLevel [Byte0]: 38
1695 00:58:56.021668 [Byte1]: 38
1696 00:58:56.025302
1697 00:58:56.025385 Set Vref, RX VrefLevel [Byte0]: 39
1698 00:58:56.029029 [Byte1]: 39
1699 00:58:56.033334
1700 00:58:56.033416 Set Vref, RX VrefLevel [Byte0]: 40
1701 00:58:56.036176 [Byte1]: 40
1702 00:58:56.040787
1703 00:58:56.040906 Set Vref, RX VrefLevel [Byte0]: 41
1704 00:58:56.044199 [Byte1]: 41
1705 00:58:56.048087
1706 00:58:56.048176 Set Vref, RX VrefLevel [Byte0]: 42
1707 00:58:56.051610 [Byte1]: 42
1708 00:58:56.055502
1709 00:58:56.055621 Set Vref, RX VrefLevel [Byte0]: 43
1710 00:58:56.058774 [Byte1]: 43
1711 00:58:56.063544
1712 00:58:56.063652 Set Vref, RX VrefLevel [Byte0]: 44
1713 00:58:56.066834 [Byte1]: 44
1714 00:58:56.070942
1715 00:58:56.071035 Set Vref, RX VrefLevel [Byte0]: 45
1716 00:58:56.074283 [Byte1]: 45
1717 00:58:56.078339
1718 00:58:56.078434 Set Vref, RX VrefLevel [Byte0]: 46
1719 00:58:56.081483 [Byte1]: 46
1720 00:58:56.086025
1721 00:58:56.086104 Set Vref, RX VrefLevel [Byte0]: 47
1722 00:58:56.089283 [Byte1]: 47
1723 00:58:56.093419
1724 00:58:56.093512 Set Vref, RX VrefLevel [Byte0]: 48
1725 00:58:56.096745 [Byte1]: 48
1726 00:58:56.101299
1727 00:58:56.101408 Set Vref, RX VrefLevel [Byte0]: 49
1728 00:58:56.104524 [Byte1]: 49
1729 00:58:56.108406
1730 00:58:56.108515 Set Vref, RX VrefLevel [Byte0]: 50
1731 00:58:56.111805 [Byte1]: 50
1732 00:58:56.116294
1733 00:58:56.116396 Set Vref, RX VrefLevel [Byte0]: 51
1734 00:58:56.119301 [Byte1]: 51
1735 00:58:56.123630
1736 00:58:56.123729 Set Vref, RX VrefLevel [Byte0]: 52
1737 00:58:56.127133 [Byte1]: 52
1738 00:58:56.131035
1739 00:58:56.131107 Set Vref, RX VrefLevel [Byte0]: 53
1740 00:58:56.134262 [Byte1]: 53
1741 00:58:56.138830
1742 00:58:56.138941 Set Vref, RX VrefLevel [Byte0]: 54
1743 00:58:56.142263 [Byte1]: 54
1744 00:58:56.146250
1745 00:58:56.146342 Set Vref, RX VrefLevel [Byte0]: 55
1746 00:58:56.149413 [Byte1]: 55
1747 00:58:56.154033
1748 00:58:56.154127 Set Vref, RX VrefLevel [Byte0]: 56
1749 00:58:56.156934 [Byte1]: 56
1750 00:58:56.161366
1751 00:58:56.161491 Set Vref, RX VrefLevel [Byte0]: 57
1752 00:58:56.164849 [Byte1]: 57
1753 00:58:56.168810
1754 00:58:56.168926 Set Vref, RX VrefLevel [Byte0]: 58
1755 00:58:56.172487 [Byte1]: 58
1756 00:58:56.176520
1757 00:58:56.176603 Set Vref, RX VrefLevel [Byte0]: 59
1758 00:58:56.179951 [Byte1]: 59
1759 00:58:56.183932
1760 00:58:56.184004 Set Vref, RX VrefLevel [Byte0]: 60
1761 00:58:56.187361 [Byte1]: 60
1762 00:58:56.191840
1763 00:58:56.191941 Set Vref, RX VrefLevel [Byte0]: 61
1764 00:58:56.194768 [Byte1]: 61
1765 00:58:56.199446
1766 00:58:56.199526 Set Vref, RX VrefLevel [Byte0]: 62
1767 00:58:56.202656 [Byte1]: 62
1768 00:58:56.206766
1769 00:58:56.206867 Set Vref, RX VrefLevel [Byte0]: 63
1770 00:58:56.210009 [Byte1]: 63
1771 00:58:56.214250
1772 00:58:56.214387 Set Vref, RX VrefLevel [Byte0]: 64
1773 00:58:56.217681 [Byte1]: 64
1774 00:58:56.221711
1775 00:58:56.221807 Set Vref, RX VrefLevel [Byte0]: 65
1776 00:58:56.225060 [Byte1]: 65
1777 00:58:56.229467
1778 00:58:56.229536 Set Vref, RX VrefLevel [Byte0]: 66
1779 00:58:56.232348 [Byte1]: 66
1780 00:58:56.236970
1781 00:58:56.237050 Set Vref, RX VrefLevel [Byte0]: 67
1782 00:58:56.240216 [Byte1]: 67
1783 00:58:56.244746
1784 00:58:56.244836 Set Vref, RX VrefLevel [Byte0]: 68
1785 00:58:56.247490 [Byte1]: 68
1786 00:58:56.252340
1787 00:58:56.252488 Set Vref, RX VrefLevel [Byte0]: 69
1788 00:58:56.254997 [Byte1]: 69
1789 00:58:56.259749
1790 00:58:56.259847 Set Vref, RX VrefLevel [Byte0]: 70
1791 00:58:56.263120 [Byte1]: 70
1792 00:58:56.266899
1793 00:58:56.267002 Set Vref, RX VrefLevel [Byte0]: 71
1794 00:58:56.270591 [Byte1]: 71
1795 00:58:56.274830
1796 00:58:56.274940 Set Vref, RX VrefLevel [Byte0]: 72
1797 00:58:56.277743 [Byte1]: 72
1798 00:58:56.281965
1799 00:58:56.282085 Set Vref, RX VrefLevel [Byte0]: 73
1800 00:58:56.285302 [Byte1]: 73
1801 00:58:56.289541
1802 00:58:56.289655 Set Vref, RX VrefLevel [Byte0]: 74
1803 00:58:56.292830 [Byte1]: 74
1804 00:58:56.296973
1805 00:58:56.297075 Set Vref, RX VrefLevel [Byte0]: 75
1806 00:58:56.300322 [Byte1]: 75
1807 00:58:56.304777
1808 00:58:56.304860 Final RX Vref Byte 0 = 61 to rank0
1809 00:58:56.308546 Final RX Vref Byte 1 = 55 to rank0
1810 00:58:56.311549 Final RX Vref Byte 0 = 61 to rank1
1811 00:58:56.314955 Final RX Vref Byte 1 = 55 to rank1==
1812 00:58:56.317932 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 00:58:56.324612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 00:58:56.324693 ==
1815 00:58:56.324765 DQS Delay:
1816 00:58:56.324829 DQS0 = 0, DQS1 = 0
1817 00:58:56.328056 DQM Delay:
1818 00:58:56.328152 DQM0 = 95, DQM1 = 90
1819 00:58:56.331396 DQ Delay:
1820 00:58:56.334686 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1821 00:58:56.337835 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
1822 00:58:56.341422 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1823 00:58:56.344994 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1824 00:58:56.345101
1825 00:58:56.345192
1826 00:58:56.351411 [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1827 00:58:56.354808 CH1 RK0: MR19=606, MR18=304C
1828 00:58:56.361632 CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64
1829 00:58:56.361740
1830 00:58:56.365066 ----->DramcWriteLeveling(PI) begin...
1831 00:58:56.365172 ==
1832 00:58:56.368468 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 00:58:56.371802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 00:58:56.371968 ==
1835 00:58:56.375036 Write leveling (Byte 0): 28 => 28
1836 00:58:56.378265 Write leveling (Byte 1): 28 => 28
1837 00:58:56.381504 DramcWriteLeveling(PI) end<-----
1838 00:58:56.381654
1839 00:58:56.381784 ==
1840 00:58:56.384793 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 00:58:56.388026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 00:58:56.388167 ==
1843 00:58:56.391928 [Gating] SW mode calibration
1844 00:58:56.398523 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 00:58:56.405247 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 00:58:56.408278 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1847 00:58:56.411647 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1848 00:58:56.418351 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:58:56.422176 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 00:58:56.425358 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 00:58:56.431725 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 00:58:56.435369 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 00:58:56.438687 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 00:58:56.442097 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 00:58:56.448437 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 00:58:56.452224 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 00:58:56.455276 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 00:58:56.462065 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 00:58:56.465566 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:58:56.468995 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:58:56.475698 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:58:56.479113 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1863 00:58:56.482523 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:58:56.488933 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:58:56.492394 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 00:58:56.495686 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 00:58:56.502289 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 00:58:56.505969 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 00:58:56.509219 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 00:58:56.512494 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 00:58:56.519170 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1872 00:58:56.522398 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1873 00:58:56.525663 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 00:58:56.532331 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 00:58:56.535483 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 00:58:56.539308 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 00:58:56.545401 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 00:58:56.549065 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 00:58:56.552327 0 10 4 | B1->B0 | 2a2a 3131 | 0 0 | (0 0) (1 0)
1880 00:58:56.559092 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:58:56.562553 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:58:56.565749 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:58:56.572169 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:58:56.575564 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:58:56.578882 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:58:56.585552 0 11 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1887 00:58:56.589048 0 11 4 | B1->B0 | 3a3a 2c2c | 0 0 | (1 1) (0 0)
1888 00:58:56.592230 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 00:58:56.596045 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 00:58:56.602779 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 00:58:56.606167 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 00:58:56.609430 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 00:58:56.615700 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 00:58:56.619129 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 00:58:56.622397 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1896 00:58:56.629230 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 00:58:56.632860 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 00:58:56.635573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 00:58:56.642514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 00:58:56.645825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 00:58:56.648974 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 00:58:56.655715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 00:58:56.659442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 00:58:56.662943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 00:58:56.669009 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 00:58:56.672462 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 00:58:56.675700 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 00:58:56.679341 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 00:58:56.686163 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 00:58:56.689331 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 00:58:56.692659 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1912 00:58:56.699270 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 00:58:56.702689 Total UI for P1: 0, mck2ui 16
1914 00:58:56.706117 best dqsien dly found for B0: ( 0, 14, 4)
1915 00:58:56.706250 Total UI for P1: 0, mck2ui 16
1916 00:58:56.712406 best dqsien dly found for B1: ( 0, 14, 4)
1917 00:58:56.715735 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1918 00:58:56.719020 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1919 00:58:56.719092
1920 00:58:56.722907 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1921 00:58:56.726118 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1922 00:58:56.729474 [Gating] SW calibration Done
1923 00:58:56.729580 ==
1924 00:58:56.732812 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 00:58:56.736030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 00:58:56.736127 ==
1927 00:58:56.739162 RX Vref Scan: 0
1928 00:58:56.739254
1929 00:58:56.739342 RX Vref 0 -> 0, step: 1
1930 00:58:56.739424
1931 00:58:56.742725 RX Delay -130 -> 252, step: 16
1932 00:58:56.746434 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1933 00:58:56.752531 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1934 00:58:56.755966 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1935 00:58:56.759831 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1936 00:58:56.762555 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1937 00:58:56.766308 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1938 00:58:56.769627 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1939 00:58:56.775974 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1940 00:58:56.779672 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1941 00:58:56.782622 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1942 00:58:56.786043 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1943 00:58:56.789847 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1944 00:58:56.796505 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1945 00:58:56.799485 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1946 00:58:56.802611 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1947 00:58:56.806300 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1948 00:58:56.806373 ==
1949 00:58:56.809530 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 00:58:56.816346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 00:58:56.816442 ==
1952 00:58:56.816531 DQS Delay:
1953 00:58:56.819746 DQS0 = 0, DQS1 = 0
1954 00:58:56.819838 DQM Delay:
1955 00:58:56.819922 DQM0 = 94, DQM1 = 91
1956 00:58:56.823043 DQ Delay:
1957 00:58:56.826477 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1958 00:58:56.829762 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =101
1959 00:58:56.832843 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1960 00:58:56.836361 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1961 00:58:56.836456
1962 00:58:56.836541
1963 00:58:56.836608 ==
1964 00:58:56.839815 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 00:58:56.843315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 00:58:56.843389 ==
1967 00:58:56.843447
1968 00:58:56.843501
1969 00:58:56.845947 TX Vref Scan disable
1970 00:58:56.849247 == TX Byte 0 ==
1971 00:58:56.852968 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1972 00:58:56.856490 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1973 00:58:56.859863 == TX Byte 1 ==
1974 00:58:56.863032 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 00:58:56.866473 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 00:58:56.866545 ==
1977 00:58:56.869705 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 00:58:56.872989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 00:58:56.876335 ==
1980 00:58:56.887506 TX Vref=22, minBit 2, minWin=26, winSum=442
1981 00:58:56.890811 TX Vref=24, minBit 1, minWin=27, winSum=449
1982 00:58:56.894147 TX Vref=26, minBit 2, minWin=27, winSum=450
1983 00:58:56.897328 TX Vref=28, minBit 2, minWin=27, winSum=451
1984 00:58:56.900794 TX Vref=30, minBit 2, minWin=27, winSum=450
1985 00:58:56.904106 TX Vref=32, minBit 2, minWin=27, winSum=448
1986 00:58:56.910794 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1987 00:58:56.910894
1988 00:58:56.914368 Final TX Range 1 Vref 28
1989 00:58:56.914468
1990 00:58:56.914554 ==
1991 00:58:56.917470 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 00:58:56.920601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 00:58:56.920697 ==
1994 00:58:56.920787
1995 00:58:56.923819
1996 00:58:56.923920 TX Vref Scan disable
1997 00:58:56.927172 == TX Byte 0 ==
1998 00:58:56.930685 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1999 00:58:56.934046 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2000 00:58:56.937286 == TX Byte 1 ==
2001 00:58:56.940973 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2002 00:58:56.944333 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2003 00:58:56.944427
2004 00:58:56.947787 [DATLAT]
2005 00:58:56.947875 Freq=800, CH1 RK1
2006 00:58:56.947957
2007 00:58:56.951224 DATLAT Default: 0xa
2008 00:58:56.951317 0, 0xFFFF, sum = 0
2009 00:58:56.953963 1, 0xFFFF, sum = 0
2010 00:58:56.954033 2, 0xFFFF, sum = 0
2011 00:58:56.957321 3, 0xFFFF, sum = 0
2012 00:58:56.957415 4, 0xFFFF, sum = 0
2013 00:58:56.961137 5, 0xFFFF, sum = 0
2014 00:58:56.961209 6, 0xFFFF, sum = 0
2015 00:58:56.964246 7, 0xFFFF, sum = 0
2016 00:58:56.964315 8, 0xFFFF, sum = 0
2017 00:58:56.967785 9, 0x0, sum = 1
2018 00:58:56.967880 10, 0x0, sum = 2
2019 00:58:56.971363 11, 0x0, sum = 3
2020 00:58:56.971459 12, 0x0, sum = 4
2021 00:58:56.974446 best_step = 10
2022 00:58:56.974541
2023 00:58:56.974625 ==
2024 00:58:56.977556 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 00:58:56.981499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 00:58:56.981601 ==
2027 00:58:56.984205 RX Vref Scan: 0
2028 00:58:56.984295
2029 00:58:56.984380 RX Vref 0 -> 0, step: 1
2030 00:58:56.984460
2031 00:58:56.987467 RX Delay -79 -> 252, step: 8
2032 00:58:56.994692 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2033 00:58:56.998054 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2034 00:58:57.001465 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2035 00:58:57.004587 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2036 00:58:57.007881 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2037 00:58:57.010884 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2038 00:58:57.018102 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2039 00:58:57.021265 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2040 00:58:57.024312 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2041 00:58:57.027753 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2042 00:58:57.031446 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2043 00:58:57.034607 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2044 00:58:57.041136 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2045 00:58:57.044462 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2046 00:58:57.048235 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2047 00:58:57.050987 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2048 00:58:57.051112 ==
2049 00:58:57.054386 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 00:58:57.061035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 00:58:57.061133 ==
2052 00:58:57.061219 DQS Delay:
2053 00:58:57.061319 DQS0 = 0, DQS1 = 0
2054 00:58:57.064371 DQM Delay:
2055 00:58:57.064460 DQM0 = 97, DQM1 = 91
2056 00:58:57.067764 DQ Delay:
2057 00:58:57.071600 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2058 00:58:57.074912 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2059 00:58:57.078072 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2060 00:58:57.081168 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2061 00:58:57.081234
2062 00:58:57.081288
2063 00:58:57.088158 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2064 00:58:57.091505 CH1 RK1: MR19=606, MR18=4C16
2065 00:58:57.097896 CH1_RK1: MR19=0x606, MR18=0x4C16, DQSOSC=390, MR23=63, INC=97, DEC=64
2066 00:58:57.101169 [RxdqsGatingPostProcess] freq 800
2067 00:58:57.104619 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2068 00:58:57.107996 Pre-setting of DQS Precalculation
2069 00:58:57.114752 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2070 00:58:57.121485 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2071 00:58:57.127651 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2072 00:58:57.127734
2073 00:58:57.127795
2074 00:58:57.131504 [Calibration Summary] 1600 Mbps
2075 00:58:57.131605 CH 0, Rank 0
2076 00:58:57.134712 SW Impedance : PASS
2077 00:58:57.137605 DUTY Scan : NO K
2078 00:58:57.137674 ZQ Calibration : PASS
2079 00:58:57.141297 Jitter Meter : NO K
2080 00:58:57.144847 CBT Training : PASS
2081 00:58:57.144943 Write leveling : PASS
2082 00:58:57.148004 RX DQS gating : PASS
2083 00:58:57.151027 RX DQ/DQS(RDDQC) : PASS
2084 00:58:57.151127 TX DQ/DQS : PASS
2085 00:58:57.154660 RX DATLAT : PASS
2086 00:58:57.154729 RX DQ/DQS(Engine): PASS
2087 00:58:57.157711 TX OE : NO K
2088 00:58:57.157778 All Pass.
2089 00:58:57.157840
2090 00:58:57.161263 CH 0, Rank 1
2091 00:58:57.161358 SW Impedance : PASS
2092 00:58:57.164666 DUTY Scan : NO K
2093 00:58:57.167968 ZQ Calibration : PASS
2094 00:58:57.168044 Jitter Meter : NO K
2095 00:58:57.171336 CBT Training : PASS
2096 00:58:57.174760 Write leveling : PASS
2097 00:58:57.174829 RX DQS gating : PASS
2098 00:58:57.178193 RX DQ/DQS(RDDQC) : PASS
2099 00:58:57.181604 TX DQ/DQS : PASS
2100 00:58:57.181672 RX DATLAT : PASS
2101 00:58:57.184962 RX DQ/DQS(Engine): PASS
2102 00:58:57.187718 TX OE : NO K
2103 00:58:57.187791 All Pass.
2104 00:58:57.187848
2105 00:58:57.187900 CH 1, Rank 0
2106 00:58:57.191211 SW Impedance : PASS
2107 00:58:57.194413 DUTY Scan : NO K
2108 00:58:57.194488 ZQ Calibration : PASS
2109 00:58:57.197491 Jitter Meter : NO K
2110 00:58:57.201064 CBT Training : PASS
2111 00:58:57.201135 Write leveling : PASS
2112 00:58:57.204433 RX DQS gating : PASS
2113 00:58:57.204518 RX DQ/DQS(RDDQC) : PASS
2114 00:58:57.207858 TX DQ/DQS : PASS
2115 00:58:57.211335 RX DATLAT : PASS
2116 00:58:57.211411 RX DQ/DQS(Engine): PASS
2117 00:58:57.214670 TX OE : NO K
2118 00:58:57.214748 All Pass.
2119 00:58:57.214808
2120 00:58:57.217973 CH 1, Rank 1
2121 00:58:57.218038 SW Impedance : PASS
2122 00:58:57.221216 DUTY Scan : NO K
2123 00:58:57.224743 ZQ Calibration : PASS
2124 00:58:57.224812 Jitter Meter : NO K
2125 00:58:57.227995 CBT Training : PASS
2126 00:58:57.231328 Write leveling : PASS
2127 00:58:57.231400 RX DQS gating : PASS
2128 00:58:57.234604 RX DQ/DQS(RDDQC) : PASS
2129 00:58:57.237665 TX DQ/DQS : PASS
2130 00:58:57.237761 RX DATLAT : PASS
2131 00:58:57.241373 RX DQ/DQS(Engine): PASS
2132 00:58:57.241467 TX OE : NO K
2133 00:58:57.244485 All Pass.
2134 00:58:57.244581
2135 00:58:57.244641 DramC Write-DBI off
2136 00:58:57.247545 PER_BANK_REFRESH: Hybrid Mode
2137 00:58:57.250833 TX_TRACKING: ON
2138 00:58:57.254547 [GetDramInforAfterCalByMRR] Vendor 6.
2139 00:58:57.257536 [GetDramInforAfterCalByMRR] Revision 606.
2140 00:58:57.260767 [GetDramInforAfterCalByMRR] Revision 2 0.
2141 00:58:57.260858 MR0 0x3b3b
2142 00:58:57.264656 MR8 0x5151
2143 00:58:57.267832 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2144 00:58:57.267922
2145 00:58:57.268006 MR0 0x3b3b
2146 00:58:57.268085 MR8 0x5151
2147 00:58:57.270740 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 00:58:57.270813
2149 00:58:57.280834 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2150 00:58:57.284124 [FAST_K] Save calibration result to emmc
2151 00:58:57.287565 [FAST_K] Save calibration result to emmc
2152 00:58:57.291080 dram_init: config_dvfs: 1
2153 00:58:57.294392 dramc_set_vcore_voltage set vcore to 662500
2154 00:58:57.297655 Read voltage for 1200, 2
2155 00:58:57.297727 Vio18 = 0
2156 00:58:57.297811 Vcore = 662500
2157 00:58:57.301171 Vdram = 0
2158 00:58:57.301265 Vddq = 0
2159 00:58:57.301347 Vmddr = 0
2160 00:58:57.307655 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2161 00:58:57.310738 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2162 00:58:57.314584 MEM_TYPE=3, freq_sel=15
2163 00:58:57.317942 sv_algorithm_assistance_LP4_1600
2164 00:58:57.321116 ============ PULL DRAM RESETB DOWN ============
2165 00:58:57.327788 ========== PULL DRAM RESETB DOWN end =========
2166 00:58:57.331212 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 00:58:57.334654 ===================================
2168 00:58:57.337457 LPDDR4 DRAM CONFIGURATION
2169 00:58:57.340823 ===================================
2170 00:58:57.340919 EX_ROW_EN[0] = 0x0
2171 00:58:57.344262 EX_ROW_EN[1] = 0x0
2172 00:58:57.344354 LP4Y_EN = 0x0
2173 00:58:57.347551 WORK_FSP = 0x0
2174 00:58:57.347640 WL = 0x4
2175 00:58:57.351159 RL = 0x4
2176 00:58:57.351250 BL = 0x2
2177 00:58:57.354679 RPST = 0x0
2178 00:58:57.354768 RD_PRE = 0x0
2179 00:58:57.357925 WR_PRE = 0x1
2180 00:58:57.357995 WR_PST = 0x0
2181 00:58:57.360954 DBI_WR = 0x0
2182 00:58:57.361044 DBI_RD = 0x0
2183 00:58:57.364765 OTF = 0x1
2184 00:58:57.367743 ===================================
2185 00:58:57.371508 ===================================
2186 00:58:57.371573 ANA top config
2187 00:58:57.374914 ===================================
2188 00:58:57.378075 DLL_ASYNC_EN = 0
2189 00:58:57.381288 ALL_SLAVE_EN = 0
2190 00:58:57.384973 NEW_RANK_MODE = 1
2191 00:58:57.385068 DLL_IDLE_MODE = 1
2192 00:58:57.388309 LP45_APHY_COMB_EN = 1
2193 00:58:57.391686 TX_ODT_DIS = 1
2194 00:58:57.394372 NEW_8X_MODE = 1
2195 00:58:57.397742 ===================================
2196 00:58:57.401072 ===================================
2197 00:58:57.404493 data_rate = 2400
2198 00:58:57.404585 CKR = 1
2199 00:58:57.407981 DQ_P2S_RATIO = 8
2200 00:58:57.411315 ===================================
2201 00:58:57.414595 CA_P2S_RATIO = 8
2202 00:58:57.417703 DQ_CA_OPEN = 0
2203 00:58:57.421600 DQ_SEMI_OPEN = 0
2204 00:58:57.421699 CA_SEMI_OPEN = 0
2205 00:58:57.424840 CA_FULL_RATE = 0
2206 00:58:57.428233 DQ_CKDIV4_EN = 0
2207 00:58:57.431586 CA_CKDIV4_EN = 0
2208 00:58:57.434970 CA_PREDIV_EN = 0
2209 00:58:57.437674 PH8_DLY = 17
2210 00:58:57.437772 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2211 00:58:57.441413 DQ_AAMCK_DIV = 4
2212 00:58:57.444432 CA_AAMCK_DIV = 4
2213 00:58:57.447969 CA_ADMCK_DIV = 4
2214 00:58:57.451089 DQ_TRACK_CA_EN = 0
2215 00:58:57.454956 CA_PICK = 1200
2216 00:58:57.458286 CA_MCKIO = 1200
2217 00:58:57.458367 MCKIO_SEMI = 0
2218 00:58:57.461680 PLL_FREQ = 2366
2219 00:58:57.464866 DQ_UI_PI_RATIO = 32
2220 00:58:57.467880 CA_UI_PI_RATIO = 0
2221 00:58:57.471289 ===================================
2222 00:58:57.474556 ===================================
2223 00:58:57.477995 memory_type:LPDDR4
2224 00:58:57.478102 GP_NUM : 10
2225 00:58:57.481589 SRAM_EN : 1
2226 00:58:57.481671 MD32_EN : 0
2227 00:58:57.484632 ===================================
2228 00:58:57.488154 [ANA_INIT] >>>>>>>>>>>>>>
2229 00:58:57.491110 <<<<<< [CONFIGURE PHASE]: ANA_TX
2230 00:58:57.494842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2231 00:58:57.497862 ===================================
2232 00:58:57.501217 data_rate = 2400,PCW = 0X5b00
2233 00:58:57.504730 ===================================
2234 00:58:57.508050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2235 00:58:57.514937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 00:58:57.517729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2237 00:58:57.524684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2238 00:58:57.527984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2239 00:58:57.531292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2240 00:58:57.531362 [ANA_INIT] flow start
2241 00:58:57.534691 [ANA_INIT] PLL >>>>>>>>
2242 00:58:57.538141 [ANA_INIT] PLL <<<<<<<<
2243 00:58:57.538209 [ANA_INIT] MIDPI >>>>>>>>
2244 00:58:57.541495 [ANA_INIT] MIDPI <<<<<<<<
2245 00:58:57.544878 [ANA_INIT] DLL >>>>>>>>
2246 00:58:57.544948 [ANA_INIT] DLL <<<<<<<<
2247 00:58:57.547590 [ANA_INIT] flow end
2248 00:58:57.551056 ============ LP4 DIFF to SE enter ============
2249 00:58:57.557975 ============ LP4 DIFF to SE exit ============
2250 00:58:57.558052 [ANA_INIT] <<<<<<<<<<<<<
2251 00:58:57.560985 [Flow] Enable top DCM control >>>>>
2252 00:58:57.564779 [Flow] Enable top DCM control <<<<<
2253 00:58:57.567780 Enable DLL master slave shuffle
2254 00:58:57.574485 ==============================================================
2255 00:58:57.574581 Gating Mode config
2256 00:58:57.581179 ==============================================================
2257 00:58:57.581250 Config description:
2258 00:58:57.590922 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2259 00:58:57.597952 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2260 00:58:57.604350 SELPH_MODE 0: By rank 1: By Phase
2261 00:58:57.607688 ==============================================================
2262 00:58:57.611336 GAT_TRACK_EN = 1
2263 00:58:57.614397 RX_GATING_MODE = 2
2264 00:58:57.618133 RX_GATING_TRACK_MODE = 2
2265 00:58:57.621492 SELPH_MODE = 1
2266 00:58:57.624775 PICG_EARLY_EN = 1
2267 00:58:57.628002 VALID_LAT_VALUE = 1
2268 00:58:57.634488 ==============================================================
2269 00:58:57.637845 Enter into Gating configuration >>>>
2270 00:58:57.641152 Exit from Gating configuration <<<<
2271 00:58:57.641249 Enter into DVFS_PRE_config >>>>>
2272 00:58:57.654812 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2273 00:58:57.658359 Exit from DVFS_PRE_config <<<<<
2274 00:58:57.661040 Enter into PICG configuration >>>>
2275 00:58:57.664945 Exit from PICG configuration <<<<
2276 00:58:57.665039 [RX_INPUT] configuration >>>>>
2277 00:58:57.668075 [RX_INPUT] configuration <<<<<
2278 00:58:57.674868 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2279 00:58:57.677970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2280 00:58:57.684556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 00:58:57.691269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 00:58:57.698197 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 00:58:57.704958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 00:58:57.708085 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2285 00:58:57.711574 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2286 00:58:57.714962 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2287 00:58:57.721215 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2288 00:58:57.724687 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2289 00:58:57.728018 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 00:58:57.731303 ===================================
2291 00:58:57.734987 LPDDR4 DRAM CONFIGURATION
2292 00:58:57.737802 ===================================
2293 00:58:57.741199 EX_ROW_EN[0] = 0x0
2294 00:58:57.741310 EX_ROW_EN[1] = 0x0
2295 00:58:57.744751 LP4Y_EN = 0x0
2296 00:58:57.744873 WORK_FSP = 0x0
2297 00:58:57.748057 WL = 0x4
2298 00:58:57.748149 RL = 0x4
2299 00:58:57.751137 BL = 0x2
2300 00:58:57.751231 RPST = 0x0
2301 00:58:57.754498 RD_PRE = 0x0
2302 00:58:57.754567 WR_PRE = 0x1
2303 00:58:57.758028 WR_PST = 0x0
2304 00:58:57.758120 DBI_WR = 0x0
2305 00:58:57.761458 DBI_RD = 0x0
2306 00:58:57.761555 OTF = 0x1
2307 00:58:57.764731 ===================================
2308 00:58:57.768106 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2309 00:58:57.774658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2310 00:58:57.777856 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 00:58:57.781230 ===================================
2312 00:58:57.784477 LPDDR4 DRAM CONFIGURATION
2313 00:58:57.788246 ===================================
2314 00:58:57.788340 EX_ROW_EN[0] = 0x10
2315 00:58:57.791333 EX_ROW_EN[1] = 0x0
2316 00:58:57.794704 LP4Y_EN = 0x0
2317 00:58:57.794803 WORK_FSP = 0x0
2318 00:58:57.797929 WL = 0x4
2319 00:58:57.798040 RL = 0x4
2320 00:58:57.801683 BL = 0x2
2321 00:58:57.801788 RPST = 0x0
2322 00:58:57.804805 RD_PRE = 0x0
2323 00:58:57.804922 WR_PRE = 0x1
2324 00:58:57.808150 WR_PST = 0x0
2325 00:58:57.808230 DBI_WR = 0x0
2326 00:58:57.811378 DBI_RD = 0x0
2327 00:58:57.811443 OTF = 0x1
2328 00:58:57.814643 ===================================
2329 00:58:57.821533 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2330 00:58:57.821613 ==
2331 00:58:57.824853 Dram Type= 6, Freq= 0, CH_0, rank 0
2332 00:58:57.828171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2333 00:58:57.828265 ==
2334 00:58:57.831621 [Duty_Offset_Calibration]
2335 00:58:57.835047 B0:2 B1:1 CA:1
2336 00:58:57.835116
2337 00:58:57.838173 [DutyScan_Calibration_Flow] k_type=0
2338 00:58:57.846111
2339 00:58:57.846186 ==CLK 0==
2340 00:58:57.849594 Final CLK duty delay cell = 0
2341 00:58:57.852521 [0] MAX Duty = 5218%(X100), DQS PI = 24
2342 00:58:57.856018 [0] MIN Duty = 4875%(X100), DQS PI = 0
2343 00:58:57.856089 [0] AVG Duty = 5046%(X100)
2344 00:58:57.859537
2345 00:58:57.859633 CH0 CLK Duty spec in!! Max-Min= 343%
2346 00:58:57.865945 [DutyScan_Calibration_Flow] ====Done====
2347 00:58:57.866018
2348 00:58:57.869105 [DutyScan_Calibration_Flow] k_type=1
2349 00:58:57.884774
2350 00:58:57.884870 ==DQS 0 ==
2351 00:58:57.888191 Final DQS duty delay cell = -4
2352 00:58:57.891593 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2353 00:58:57.894732 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2354 00:58:57.898335 [-4] AVG Duty = 4937%(X100)
2355 00:58:57.898407
2356 00:58:57.898488 ==DQS 1 ==
2357 00:58:57.901348 Final DQS duty delay cell = 0
2358 00:58:57.904909 [0] MAX Duty = 5156%(X100), DQS PI = 62
2359 00:58:57.907963 [0] MIN Duty = 5000%(X100), DQS PI = 32
2360 00:58:57.911559 [0] AVG Duty = 5078%(X100)
2361 00:58:57.911627
2362 00:58:57.914518 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2363 00:58:57.914587
2364 00:58:57.918372 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2365 00:58:57.921703 [DutyScan_Calibration_Flow] ====Done====
2366 00:58:57.921772
2367 00:58:57.925058 [DutyScan_Calibration_Flow] k_type=3
2368 00:58:57.941718
2369 00:58:57.941796 ==DQM 0 ==
2370 00:58:57.944997 Final DQM duty delay cell = 0
2371 00:58:57.948381 [0] MAX Duty = 5156%(X100), DQS PI = 30
2372 00:58:57.951425 [0] MIN Duty = 4875%(X100), DQS PI = 58
2373 00:58:57.951520 [0] AVG Duty = 5015%(X100)
2374 00:58:57.955194
2375 00:58:57.955289 ==DQM 1 ==
2376 00:58:57.958437 Final DQM duty delay cell = 0
2377 00:58:57.961787 [0] MAX Duty = 5093%(X100), DQS PI = 0
2378 00:58:57.964988 [0] MIN Duty = 5031%(X100), DQS PI = 14
2379 00:58:57.965088 [0] AVG Duty = 5062%(X100)
2380 00:58:57.968156
2381 00:58:57.971660 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2382 00:58:57.971761
2383 00:58:57.975173 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2384 00:58:57.978594 [DutyScan_Calibration_Flow] ====Done====
2385 00:58:57.978693
2386 00:58:57.981577 [DutyScan_Calibration_Flow] k_type=2
2387 00:58:57.997740
2388 00:58:57.997850 ==DQ 0 ==
2389 00:58:58.001670 Final DQ duty delay cell = 0
2390 00:58:58.005042 [0] MAX Duty = 5062%(X100), DQS PI = 32
2391 00:58:58.008366 [0] MIN Duty = 4875%(X100), DQS PI = 62
2392 00:58:58.008468 [0] AVG Duty = 4968%(X100)
2393 00:58:58.008557
2394 00:58:58.011511 ==DQ 1 ==
2395 00:58:58.011603 Final DQ duty delay cell = 0
2396 00:58:58.018359 [0] MAX Duty = 5093%(X100), DQS PI = 24
2397 00:58:58.021425 [0] MIN Duty = 4907%(X100), DQS PI = 36
2398 00:58:58.021517 [0] AVG Duty = 5000%(X100)
2399 00:58:58.021611
2400 00:58:58.025088 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2401 00:58:58.025182
2402 00:58:58.028545 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2403 00:58:58.031553 [DutyScan_Calibration_Flow] ====Done====
2404 00:58:58.035218 ==
2405 00:58:58.038466 Dram Type= 6, Freq= 0, CH_1, rank 0
2406 00:58:58.041800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2407 00:58:58.041871 ==
2408 00:58:58.045212 [Duty_Offset_Calibration]
2409 00:58:58.045302 B0:1 B1:0 CA:0
2410 00:58:58.045386
2411 00:58:58.048477 [DutyScan_Calibration_Flow] k_type=0
2412 00:58:58.057237
2413 00:58:58.057327 ==CLK 0==
2414 00:58:58.060429 Final CLK duty delay cell = -4
2415 00:58:58.063591 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2416 00:58:58.067026 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2417 00:58:58.070414 [-4] AVG Duty = 4953%(X100)
2418 00:58:58.070507
2419 00:58:58.073832 CH1 CLK Duty spec in!! Max-Min= 93%
2420 00:58:58.077122 [DutyScan_Calibration_Flow] ====Done====
2421 00:58:58.077211
2422 00:58:58.080290 [DutyScan_Calibration_Flow] k_type=1
2423 00:58:58.097096
2424 00:58:58.097192 ==DQS 0 ==
2425 00:58:58.100098 Final DQS duty delay cell = 0
2426 00:58:58.103849 [0] MAX Duty = 5062%(X100), DQS PI = 22
2427 00:58:58.107135 [0] MIN Duty = 4844%(X100), DQS PI = 0
2428 00:58:58.107206 [0] AVG Duty = 4953%(X100)
2429 00:58:58.107264
2430 00:58:58.110604 ==DQS 1 ==
2431 00:58:58.113827 Final DQS duty delay cell = 0
2432 00:58:58.117176 [0] MAX Duty = 5187%(X100), DQS PI = 20
2433 00:58:58.120539 [0] MIN Duty = 4969%(X100), DQS PI = 10
2434 00:58:58.120627 [0] AVG Duty = 5078%(X100)
2435 00:58:58.120687
2436 00:58:58.123772 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2437 00:58:58.123866
2438 00:58:58.130445 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2439 00:58:58.134236 [DutyScan_Calibration_Flow] ====Done====
2440 00:58:58.134335
2441 00:58:58.137251 [DutyScan_Calibration_Flow] k_type=3
2442 00:58:58.153842
2443 00:58:58.153956 ==DQM 0 ==
2444 00:58:58.156793 Final DQM duty delay cell = 0
2445 00:58:58.160141 [0] MAX Duty = 5156%(X100), DQS PI = 8
2446 00:58:58.163394 [0] MIN Duty = 5000%(X100), DQS PI = 48
2447 00:58:58.163458 [0] AVG Duty = 5078%(X100)
2448 00:58:58.167139
2449 00:58:58.167229 ==DQM 1 ==
2450 00:58:58.170462 Final DQM duty delay cell = 0
2451 00:58:58.173732 [0] MAX Duty = 5031%(X100), DQS PI = 26
2452 00:58:58.176429 [0] MIN Duty = 4875%(X100), DQS PI = 36
2453 00:58:58.179848 [0] AVG Duty = 4953%(X100)
2454 00:58:58.179940
2455 00:58:58.183183 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2456 00:58:58.183250
2457 00:58:58.186542 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2458 00:58:58.189832 [DutyScan_Calibration_Flow] ====Done====
2459 00:58:58.189897
2460 00:58:58.193677 [DutyScan_Calibration_Flow] k_type=2
2461 00:58:58.209196
2462 00:58:58.209295 ==DQ 0 ==
2463 00:58:58.212785 Final DQ duty delay cell = -4
2464 00:58:58.215850 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2465 00:58:58.219204 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2466 00:58:58.222642 [-4] AVG Duty = 4984%(X100)
2467 00:58:58.222741
2468 00:58:58.222828 ==DQ 1 ==
2469 00:58:58.226006 Final DQ duty delay cell = 0
2470 00:58:58.229758 [0] MAX Duty = 5125%(X100), DQS PI = 20
2471 00:58:58.233149 [0] MIN Duty = 4938%(X100), DQS PI = 34
2472 00:58:58.233217 [0] AVG Duty = 5031%(X100)
2473 00:58:58.233275
2474 00:58:58.239207 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2475 00:58:58.239274
2476 00:58:58.242495 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2477 00:58:58.246270 [DutyScan_Calibration_Flow] ====Done====
2478 00:58:58.249589 nWR fixed to 30
2479 00:58:58.249658 [ModeRegInit_LP4] CH0 RK0
2480 00:58:58.252962 [ModeRegInit_LP4] CH0 RK1
2481 00:58:58.256306 [ModeRegInit_LP4] CH1 RK0
2482 00:58:58.259698 [ModeRegInit_LP4] CH1 RK1
2483 00:58:58.259784 match AC timing 7
2484 00:58:58.262872 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2485 00:58:58.266129 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2486 00:58:58.272856 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2487 00:58:58.275993 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2488 00:58:58.283351 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2489 00:58:58.283426 ==
2490 00:58:58.286708 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 00:58:58.289464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 00:58:58.289529 ==
2493 00:58:58.296302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 00:58:58.299549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 00:58:58.309704 [CA 0] Center 39 (8~70) winsize 63
2496 00:58:58.313021 [CA 1] Center 39 (8~70) winsize 63
2497 00:58:58.316389 [CA 2] Center 35 (5~66) winsize 62
2498 00:58:58.319576 [CA 3] Center 34 (4~65) winsize 62
2499 00:58:58.322669 [CA 4] Center 33 (3~64) winsize 62
2500 00:58:58.326172 [CA 5] Center 32 (3~62) winsize 60
2501 00:58:58.326249
2502 00:58:58.329408 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2503 00:58:58.329481
2504 00:58:58.332741 [CATrainingPosCal] consider 1 rank data
2505 00:58:58.336583 u2DelayCellTimex100 = 270/100 ps
2506 00:58:58.340038 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2507 00:58:58.343283 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2508 00:58:58.349892 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2509 00:58:58.353148 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2510 00:58:58.356460 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2511 00:58:58.359627 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2512 00:58:58.359700
2513 00:58:58.363034 CA PerBit enable=1, Macro0, CA PI delay=32
2514 00:58:58.363104
2515 00:58:58.366395 [CBTSetCACLKResult] CA Dly = 32
2516 00:58:58.366471 CS Dly: 6 (0~37)
2517 00:58:58.366532 ==
2518 00:58:58.369751 Dram Type= 6, Freq= 0, CH_0, rank 1
2519 00:58:58.376346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 00:58:58.376420 ==
2521 00:58:58.379577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 00:58:58.386379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 00:58:58.395086 [CA 0] Center 38 (8~69) winsize 62
2524 00:58:58.398489 [CA 1] Center 38 (8~69) winsize 62
2525 00:58:58.401964 [CA 2] Center 34 (4~65) winsize 62
2526 00:58:58.405170 [CA 3] Center 34 (4~65) winsize 62
2527 00:58:58.409019 [CA 4] Center 33 (3~63) winsize 61
2528 00:58:58.412289 [CA 5] Center 32 (3~62) winsize 60
2529 00:58:58.412393
2530 00:58:58.415592 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2531 00:58:58.415690
2532 00:58:58.418667 [CATrainingPosCal] consider 2 rank data
2533 00:58:58.421957 u2DelayCellTimex100 = 270/100 ps
2534 00:58:58.425363 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2535 00:58:58.428884 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2536 00:58:58.435591 CA2 delay=35 (5~65),Diff = 3 PI (14 cell)
2537 00:58:58.438499 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2538 00:58:58.441820 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2539 00:58:58.445483 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2540 00:58:58.445581
2541 00:58:58.448817 CA PerBit enable=1, Macro0, CA PI delay=32
2542 00:58:58.448888
2543 00:58:58.452243 [CBTSetCACLKResult] CA Dly = 32
2544 00:58:58.452334 CS Dly: 6 (0~38)
2545 00:58:58.452419
2546 00:58:58.455576 ----->DramcWriteLeveling(PI) begin...
2547 00:58:58.458863 ==
2548 00:58:58.458955 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 00:58:58.465411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 00:58:58.465504 ==
2551 00:58:58.468722 Write leveling (Byte 0): 33 => 33
2552 00:58:58.472145 Write leveling (Byte 1): 28 => 28
2553 00:58:58.475403 DramcWriteLeveling(PI) end<-----
2554 00:58:58.475472
2555 00:58:58.475531 ==
2556 00:58:58.478777 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 00:58:58.482314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 00:58:58.482383 ==
2559 00:58:58.485649 [Gating] SW mode calibration
2560 00:58:58.492357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2561 00:58:58.495372 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2562 00:58:58.502267 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2563 00:58:58.505649 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2564 00:58:58.508942 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 00:58:58.515611 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 00:58:58.518979 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 00:58:58.522254 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 00:58:58.529125 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2569 00:58:58.532479 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2570 00:58:58.536005 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2571 00:58:58.542616 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 00:58:58.546014 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 00:58:58.549151 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 00:58:58.552233 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 00:58:58.559364 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 00:58:58.562939 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2577 00:58:58.566071 1 0 28 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2578 00:58:58.572436 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2579 00:58:58.575585 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 00:58:58.578906 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 00:58:58.585946 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 00:58:58.589403 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 00:58:58.592833 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 00:58:58.599515 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 00:58:58.602763 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 00:58:58.605989 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2587 00:58:58.612767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 00:58:58.616135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 00:58:58.619390 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 00:58:58.622607 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 00:58:58.629363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 00:58:58.632450 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 00:58:58.636117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 00:58:58.642872 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 00:58:58.646316 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 00:58:58.649061 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 00:58:58.655792 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 00:58:58.659154 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 00:58:58.662667 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 00:58:58.669209 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 00:58:58.672558 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2602 00:58:58.675956 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2603 00:58:58.679139 Total UI for P1: 0, mck2ui 16
2604 00:58:58.682688 best dqsien dly found for B0: ( 1, 3, 28)
2605 00:58:58.689412 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 00:58:58.689511 Total UI for P1: 0, mck2ui 16
2607 00:58:58.692463 best dqsien dly found for B1: ( 1, 3, 30)
2608 00:58:58.699304 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2609 00:58:58.702409 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2610 00:58:58.702504
2611 00:58:58.705782 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2612 00:58:58.709081 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2613 00:58:58.712898 [Gating] SW calibration Done
2614 00:58:58.712964 ==
2615 00:58:58.715893 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 00:58:58.719534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 00:58:58.719602 ==
2618 00:58:58.722715 RX Vref Scan: 0
2619 00:58:58.722781
2620 00:58:58.722836 RX Vref 0 -> 0, step: 1
2621 00:58:58.722889
2622 00:58:58.725912 RX Delay -40 -> 252, step: 8
2623 00:58:58.729160 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2624 00:58:58.735986 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2625 00:58:58.739240 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2626 00:58:58.742864 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2627 00:58:58.746249 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2628 00:58:58.749656 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2629 00:58:58.753000 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2630 00:58:58.759165 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2631 00:58:58.762556 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2632 00:58:58.765889 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2633 00:58:58.769231 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2634 00:58:58.772596 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2635 00:58:58.779323 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2636 00:58:58.782680 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2637 00:58:58.786071 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2638 00:58:58.789306 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2639 00:58:58.789399 ==
2640 00:58:58.792995 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 00:58:58.799759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 00:58:58.799865 ==
2643 00:58:58.799952 DQS Delay:
2644 00:58:58.800034 DQS0 = 0, DQS1 = 0
2645 00:58:58.803307 DQM Delay:
2646 00:58:58.803403 DQM0 = 121, DQM1 = 113
2647 00:58:58.806174 DQ Delay:
2648 00:58:58.809720 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2649 00:58:58.813017 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2650 00:58:58.816288 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2651 00:58:58.819549 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2652 00:58:58.819642
2653 00:58:58.819726
2654 00:58:58.819810 ==
2655 00:58:58.823076 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 00:58:58.826081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 00:58:58.826183 ==
2658 00:58:58.826269
2659 00:58:58.829535
2660 00:58:58.829611 TX Vref Scan disable
2661 00:58:58.832984 == TX Byte 0 ==
2662 00:58:58.836252 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2663 00:58:58.839410 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2664 00:58:58.843161 == TX Byte 1 ==
2665 00:58:58.846519 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2666 00:58:58.849648 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2667 00:58:58.849721 ==
2668 00:58:58.853236 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 00:58:58.859767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 00:58:58.859873 ==
2671 00:58:58.870602 TX Vref=22, minBit 0, minWin=25, winSum=407
2672 00:58:58.874029 TX Vref=24, minBit 0, minWin=25, winSum=414
2673 00:58:58.877261 TX Vref=26, minBit 2, minWin=25, winSum=418
2674 00:58:58.880691 TX Vref=28, minBit 0, minWin=26, winSum=422
2675 00:58:58.883982 TX Vref=30, minBit 1, minWin=26, winSum=427
2676 00:58:58.887446 TX Vref=32, minBit 0, minWin=26, winSum=423
2677 00:58:58.893653 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2678 00:58:58.893759
2679 00:58:58.897092 Final TX Range 1 Vref 30
2680 00:58:58.897177
2681 00:58:58.897238 ==
2682 00:58:58.900437 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 00:58:58.903783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 00:58:58.903868 ==
2685 00:58:58.903929
2686 00:58:58.903985
2687 00:58:58.907192 TX Vref Scan disable
2688 00:58:58.910506 == TX Byte 0 ==
2689 00:58:58.913779 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2690 00:58:58.917236 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2691 00:58:58.920455 == TX Byte 1 ==
2692 00:58:58.923738 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2693 00:58:58.927403 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2694 00:58:58.927506
2695 00:58:58.930342 [DATLAT]
2696 00:58:58.930436 Freq=1200, CH0 RK0
2697 00:58:58.930531
2698 00:58:58.933911 DATLAT Default: 0xd
2699 00:58:58.934002 0, 0xFFFF, sum = 0
2700 00:58:58.937594 1, 0xFFFF, sum = 0
2701 00:58:58.937693 2, 0xFFFF, sum = 0
2702 00:58:58.940940 3, 0xFFFF, sum = 0
2703 00:58:58.941036 4, 0xFFFF, sum = 0
2704 00:58:58.943956 5, 0xFFFF, sum = 0
2705 00:58:58.944057 6, 0xFFFF, sum = 0
2706 00:58:58.947647 7, 0xFFFF, sum = 0
2707 00:58:58.947745 8, 0xFFFF, sum = 0
2708 00:58:58.950945 9, 0xFFFF, sum = 0
2709 00:58:58.951028 10, 0xFFFF, sum = 0
2710 00:58:58.954104 11, 0xFFFF, sum = 0
2711 00:58:58.954179 12, 0x0, sum = 1
2712 00:58:58.957227 13, 0x0, sum = 2
2713 00:58:58.957303 14, 0x0, sum = 3
2714 00:58:58.960441 15, 0x0, sum = 4
2715 00:58:58.960514 best_step = 13
2716 00:58:58.960572
2717 00:58:58.960626 ==
2718 00:58:58.963984 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 00:58:58.970879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 00:58:58.970969 ==
2721 00:58:58.971030 RX Vref Scan: 1
2722 00:58:58.971086
2723 00:58:58.974216 Set Vref Range= 32 -> 127
2724 00:58:58.974295
2725 00:58:58.977531 RX Vref 32 -> 127, step: 1
2726 00:58:58.977622
2727 00:58:58.980638 RX Delay -13 -> 252, step: 4
2728 00:58:58.980719
2729 00:58:58.984116 Set Vref, RX VrefLevel [Byte0]: 32
2730 00:58:58.984196 [Byte1]: 32
2731 00:58:58.988830
2732 00:58:58.988937 Set Vref, RX VrefLevel [Byte0]: 33
2733 00:58:58.992336 [Byte1]: 33
2734 00:58:58.996414
2735 00:58:58.996521 Set Vref, RX VrefLevel [Byte0]: 34
2736 00:58:58.999664 [Byte1]: 34
2737 00:58:59.004177
2738 00:58:59.004292 Set Vref, RX VrefLevel [Byte0]: 35
2739 00:58:59.007599 [Byte1]: 35
2740 00:58:59.012422
2741 00:58:59.012537 Set Vref, RX VrefLevel [Byte0]: 36
2742 00:58:59.015639 [Byte1]: 36
2743 00:58:59.020281
2744 00:58:59.020385 Set Vref, RX VrefLevel [Byte0]: 37
2745 00:58:59.023697 [Byte1]: 37
2746 00:58:59.027785
2747 00:58:59.027879 Set Vref, RX VrefLevel [Byte0]: 38
2748 00:58:59.031179 [Byte1]: 38
2749 00:58:59.036254
2750 00:58:59.036337 Set Vref, RX VrefLevel [Byte0]: 39
2751 00:58:59.039360 [Byte1]: 39
2752 00:58:59.044054
2753 00:58:59.044141 Set Vref, RX VrefLevel [Byte0]: 40
2754 00:58:59.047024 [Byte1]: 40
2755 00:58:59.051847
2756 00:58:59.051930 Set Vref, RX VrefLevel [Byte0]: 41
2757 00:58:59.055210 [Byte1]: 41
2758 00:58:59.059834
2759 00:58:59.059921 Set Vref, RX VrefLevel [Byte0]: 42
2760 00:58:59.063067 [Byte1]: 42
2761 00:58:59.067706
2762 00:58:59.067789 Set Vref, RX VrefLevel [Byte0]: 43
2763 00:58:59.071012 [Byte1]: 43
2764 00:58:59.075264
2765 00:58:59.075348 Set Vref, RX VrefLevel [Byte0]: 44
2766 00:58:59.079056 [Byte1]: 44
2767 00:58:59.083729
2768 00:58:59.083811 Set Vref, RX VrefLevel [Byte0]: 45
2769 00:58:59.086633 [Byte1]: 45
2770 00:58:59.091248
2771 00:58:59.091332 Set Vref, RX VrefLevel [Byte0]: 46
2772 00:58:59.094736 [Byte1]: 46
2773 00:58:59.099043
2774 00:58:59.099156 Set Vref, RX VrefLevel [Byte0]: 47
2775 00:58:59.102545 [Byte1]: 47
2776 00:58:59.106778
2777 00:58:59.106862 Set Vref, RX VrefLevel [Byte0]: 48
2778 00:58:59.110016 [Byte1]: 48
2779 00:58:59.114740
2780 00:58:59.114818 Set Vref, RX VrefLevel [Byte0]: 49
2781 00:58:59.118159 [Byte1]: 49
2782 00:58:59.122596
2783 00:58:59.122706 Set Vref, RX VrefLevel [Byte0]: 50
2784 00:58:59.125901 [Byte1]: 50
2785 00:58:59.130543
2786 00:58:59.130648 Set Vref, RX VrefLevel [Byte0]: 51
2787 00:58:59.133884 [Byte1]: 51
2788 00:58:59.138546
2789 00:58:59.138626 Set Vref, RX VrefLevel [Byte0]: 52
2790 00:58:59.141957 [Byte1]: 52
2791 00:58:59.146617
2792 00:58:59.146719 Set Vref, RX VrefLevel [Byte0]: 53
2793 00:58:59.149864 [Byte1]: 53
2794 00:58:59.154318
2795 00:58:59.154420 Set Vref, RX VrefLevel [Byte0]: 54
2796 00:58:59.157848 [Byte1]: 54
2797 00:58:59.162391
2798 00:58:59.162497 Set Vref, RX VrefLevel [Byte0]: 55
2799 00:58:59.165596 [Byte1]: 55
2800 00:58:59.170066
2801 00:58:59.170148 Set Vref, RX VrefLevel [Byte0]: 56
2802 00:58:59.173464 [Byte1]: 56
2803 00:58:59.178133
2804 00:58:59.178233 Set Vref, RX VrefLevel [Byte0]: 57
2805 00:58:59.181430 [Byte1]: 57
2806 00:58:59.186073
2807 00:58:59.186171 Set Vref, RX VrefLevel [Byte0]: 58
2808 00:58:59.189497 [Byte1]: 58
2809 00:58:59.194093
2810 00:58:59.194171 Set Vref, RX VrefLevel [Byte0]: 59
2811 00:58:59.197397 [Byte1]: 59
2812 00:58:59.201423
2813 00:58:59.201523 Set Vref, RX VrefLevel [Byte0]: 60
2814 00:58:59.205011 [Byte1]: 60
2815 00:58:59.209738
2816 00:58:59.209819 Set Vref, RX VrefLevel [Byte0]: 61
2817 00:58:59.212989 [Byte1]: 61
2818 00:58:59.217200
2819 00:58:59.217300 Set Vref, RX VrefLevel [Byte0]: 62
2820 00:58:59.220447 [Byte1]: 62
2821 00:58:59.225623
2822 00:58:59.225715 Set Vref, RX VrefLevel [Byte0]: 63
2823 00:58:59.228423 [Byte1]: 63
2824 00:58:59.233048
2825 00:58:59.233126 Set Vref, RX VrefLevel [Byte0]: 64
2826 00:58:59.236341 [Byte1]: 64
2827 00:58:59.241107
2828 00:58:59.241194 Set Vref, RX VrefLevel [Byte0]: 65
2829 00:58:59.244436 [Byte1]: 65
2830 00:58:59.249132
2831 00:58:59.249225 Set Vref, RX VrefLevel [Byte0]: 66
2832 00:58:59.252482 [Byte1]: 66
2833 00:58:59.257149
2834 00:58:59.257232 Set Vref, RX VrefLevel [Byte0]: 67
2835 00:58:59.260564 [Byte1]: 67
2836 00:58:59.264929
2837 00:58:59.265011 Set Vref, RX VrefLevel [Byte0]: 68
2838 00:58:59.268031 [Byte1]: 68
2839 00:58:59.272627
2840 00:58:59.272726 Set Vref, RX VrefLevel [Byte0]: 69
2841 00:58:59.276008 [Byte1]: 69
2842 00:58:59.281051
2843 00:58:59.281148 Final RX Vref Byte 0 = 56 to rank0
2844 00:58:59.284284 Final RX Vref Byte 1 = 50 to rank0
2845 00:58:59.287043 Final RX Vref Byte 0 = 56 to rank1
2846 00:58:59.290415 Final RX Vref Byte 1 = 50 to rank1==
2847 00:58:59.293767 Dram Type= 6, Freq= 0, CH_0, rank 0
2848 00:58:59.300526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 00:58:59.300622 ==
2850 00:58:59.300684 DQS Delay:
2851 00:58:59.300740 DQS0 = 0, DQS1 = 0
2852 00:58:59.304030 DQM Delay:
2853 00:58:59.304113 DQM0 = 120, DQM1 = 112
2854 00:58:59.307432 DQ Delay:
2855 00:58:59.310745 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =120
2856 00:58:59.313890 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2857 00:58:59.316976 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2858 00:58:59.320225 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =120
2859 00:58:59.320327
2860 00:58:59.320424
2861 00:58:59.330227 [DQSOSCAuto] RK0, (LSB)MR18= 0x1912, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2862 00:58:59.330356 CH0 RK0: MR19=404, MR18=1912
2863 00:58:59.337016 CH0_RK0: MR19=0x404, MR18=0x1912, DQSOSC=400, MR23=63, INC=40, DEC=27
2864 00:58:59.337127
2865 00:58:59.340164 ----->DramcWriteLeveling(PI) begin...
2866 00:58:59.340266 ==
2867 00:58:59.343804 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 00:58:59.350201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 00:58:59.350314 ==
2870 00:58:59.353601 Write leveling (Byte 0): 34 => 34
2871 00:58:59.353702 Write leveling (Byte 1): 29 => 29
2872 00:58:59.356657 DramcWriteLeveling(PI) end<-----
2873 00:58:59.356754
2874 00:58:59.360587 ==
2875 00:58:59.360686 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 00:58:59.367210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 00:58:59.367300 ==
2878 00:58:59.370632 [Gating] SW mode calibration
2879 00:58:59.376704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2880 00:58:59.380009 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2881 00:58:59.386843 0 15 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2882 00:58:59.390245 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 00:58:59.393556 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 00:58:59.400107 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 00:58:59.403976 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 00:58:59.406736 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 00:58:59.410151 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 00:58:59.416850 0 15 28 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (0 0)
2889 00:58:59.420189 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 00:58:59.423427 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 00:58:59.429963 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 00:58:59.433423 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 00:58:59.436641 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 00:58:59.443726 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 00:58:59.447056 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2896 00:58:59.450279 1 0 28 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (0 0)
2897 00:58:59.456987 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 00:58:59.460297 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 00:58:59.464015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 00:58:59.470312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 00:58:59.473567 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 00:58:59.476737 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 00:58:59.483504 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 00:58:59.486838 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2905 00:58:59.490380 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2906 00:58:59.496931 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 00:58:59.500149 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 00:58:59.503858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 00:58:59.506857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 00:58:59.514132 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 00:58:59.517360 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 00:58:59.520682 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 00:58:59.527376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 00:58:59.530612 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 00:58:59.533809 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 00:58:59.540373 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 00:58:59.543597 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 00:58:59.547009 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 00:58:59.553980 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 00:58:59.557318 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2921 00:58:59.560665 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2922 00:58:59.567423 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 00:58:59.567516 Total UI for P1: 0, mck2ui 16
2924 00:58:59.570789 best dqsien dly found for B0: ( 1, 3, 30)
2925 00:58:59.574253 Total UI for P1: 0, mck2ui 16
2926 00:58:59.577683 best dqsien dly found for B1: ( 1, 3, 30)
2927 00:58:59.580306 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2928 00:58:59.587530 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2929 00:58:59.587636
2930 00:58:59.590278 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2931 00:58:59.593741 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2932 00:58:59.597448 [Gating] SW calibration Done
2933 00:58:59.597535 ==
2934 00:58:59.600847 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 00:58:59.604207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 00:58:59.604290 ==
2937 00:58:59.604351 RX Vref Scan: 0
2938 00:58:59.606981
2939 00:58:59.607060 RX Vref 0 -> 0, step: 1
2940 00:58:59.607120
2941 00:58:59.610414 RX Delay -40 -> 252, step: 8
2942 00:58:59.613737 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2943 00:58:59.617088 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2944 00:58:59.623562 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2945 00:58:59.626787 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2946 00:58:59.630241 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2947 00:58:59.633334 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2948 00:58:59.636944 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2949 00:58:59.643697 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2950 00:58:59.647075 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2951 00:58:59.650273 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2952 00:58:59.653525 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2953 00:58:59.656757 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2954 00:58:59.663108 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2955 00:58:59.666468 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2956 00:58:59.669827 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2957 00:58:59.673143 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2958 00:58:59.676468 ==
2959 00:58:59.676548 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 00:58:59.683343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 00:58:59.683429 ==
2962 00:58:59.683487 DQS Delay:
2963 00:58:59.686708 DQS0 = 0, DQS1 = 0
2964 00:58:59.686784 DQM Delay:
2965 00:58:59.690073 DQM0 = 122, DQM1 = 112
2966 00:58:59.690159 DQ Delay:
2967 00:58:59.692729 DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119
2968 00:58:59.696136 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2969 00:58:59.699463 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2970 00:58:59.703441 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2971 00:58:59.703520
2972 00:58:59.703579
2973 00:58:59.703638 ==
2974 00:58:59.706399 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 00:58:59.713132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 00:58:59.713243 ==
2977 00:58:59.713334
2978 00:58:59.713394
2979 00:58:59.713446 TX Vref Scan disable
2980 00:58:59.716440 == TX Byte 0 ==
2981 00:58:59.720014 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2982 00:58:59.726583 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2983 00:58:59.726677 == TX Byte 1 ==
2984 00:58:59.729845 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2985 00:58:59.736527 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2986 00:58:59.736623 ==
2987 00:58:59.739486 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 00:58:59.742854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 00:58:59.742942 ==
2990 00:58:59.755091 TX Vref=22, minBit 1, minWin=25, winSum=416
2991 00:58:59.757970 TX Vref=24, minBit 1, minWin=25, winSum=417
2992 00:58:59.761726 TX Vref=26, minBit 0, minWin=26, winSum=424
2993 00:58:59.765000 TX Vref=28, minBit 1, minWin=26, winSum=427
2994 00:58:59.768249 TX Vref=30, minBit 1, minWin=26, winSum=427
2995 00:58:59.774821 TX Vref=32, minBit 0, minWin=26, winSum=427
2996 00:58:59.778267 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
2997 00:58:59.778359
2998 00:58:59.781409 Final TX Range 1 Vref 28
2999 00:58:59.781491
3000 00:58:59.781558 ==
3001 00:58:59.784780 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 00:58:59.788170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 00:58:59.788252 ==
3004 00:58:59.791606
3005 00:58:59.791677
3006 00:58:59.791734 TX Vref Scan disable
3007 00:58:59.794775 == TX Byte 0 ==
3008 00:58:59.798188 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3009 00:58:59.801522 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3010 00:58:59.804301 == TX Byte 1 ==
3011 00:58:59.807714 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3012 00:58:59.814321 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3013 00:58:59.814411
3014 00:58:59.814471 [DATLAT]
3015 00:58:59.814526 Freq=1200, CH0 RK1
3016 00:58:59.814582
3017 00:58:59.817652 DATLAT Default: 0xd
3018 00:58:59.817716 0, 0xFFFF, sum = 0
3019 00:58:59.821024 1, 0xFFFF, sum = 0
3020 00:58:59.824739 2, 0xFFFF, sum = 0
3021 00:58:59.824835 3, 0xFFFF, sum = 0
3022 00:58:59.824924 4, 0xFFFF, sum = 0
3023 00:58:59.828298 5, 0xFFFF, sum = 0
3024 00:58:59.831123 6, 0xFFFF, sum = 0
3025 00:58:59.831200 7, 0xFFFF, sum = 0
3026 00:58:59.834408 8, 0xFFFF, sum = 0
3027 00:58:59.834479 9, 0xFFFF, sum = 0
3028 00:58:59.837825 10, 0xFFFF, sum = 0
3029 00:58:59.837909 11, 0xFFFF, sum = 0
3030 00:58:59.841204 12, 0x0, sum = 1
3031 00:58:59.841277 13, 0x0, sum = 2
3032 00:58:59.844481 14, 0x0, sum = 3
3033 00:58:59.844557 15, 0x0, sum = 4
3034 00:58:59.844636 best_step = 13
3035 00:58:59.847645
3036 00:58:59.847714 ==
3037 00:58:59.851360 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 00:58:59.854800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 00:58:59.854878 ==
3040 00:58:59.854939 RX Vref Scan: 0
3041 00:58:59.854994
3042 00:58:59.858258 RX Vref 0 -> 0, step: 1
3043 00:58:59.858328
3044 00:58:59.860988 RX Delay -13 -> 252, step: 4
3045 00:58:59.864401 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3046 00:58:59.871595 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3047 00:58:59.874949 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3048 00:58:59.878036 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3049 00:58:59.881035 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3050 00:58:59.884591 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3051 00:58:59.890957 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3052 00:58:59.894362 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3053 00:58:59.897656 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3054 00:58:59.901055 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3055 00:58:59.903929 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3056 00:58:59.911050 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3057 00:58:59.914454 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3058 00:58:59.917926 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3059 00:58:59.921198 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3060 00:58:59.924052 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3061 00:58:59.927451 ==
3062 00:58:59.927562 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 00:58:59.934182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 00:58:59.934301 ==
3065 00:58:59.934368 DQS Delay:
3066 00:58:59.937554 DQS0 = 0, DQS1 = 0
3067 00:58:59.937636 DQM Delay:
3068 00:58:59.940942 DQM0 = 120, DQM1 = 110
3069 00:58:59.941023 DQ Delay:
3070 00:58:59.944626 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3071 00:58:59.947461 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3072 00:58:59.950947 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3073 00:58:59.954446 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3074 00:58:59.954537
3075 00:58:59.954597
3076 00:58:59.963845 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3077 00:58:59.967649 CH0 RK1: MR19=403, MR18=11F2
3078 00:58:59.970847 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3079 00:58:59.974162 [RxdqsGatingPostProcess] freq 1200
3080 00:58:59.980980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3081 00:58:59.983655 best DQS0 dly(2T, 0.5T) = (0, 11)
3082 00:58:59.987002 best DQS1 dly(2T, 0.5T) = (0, 11)
3083 00:58:59.990413 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3084 00:58:59.993790 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3085 00:58:59.997057 best DQS0 dly(2T, 0.5T) = (0, 11)
3086 00:59:00.000622 best DQS1 dly(2T, 0.5T) = (0, 11)
3087 00:59:00.003900 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3088 00:59:00.007070 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3089 00:59:00.007148 Pre-setting of DQS Precalculation
3090 00:59:00.014429 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3091 00:59:00.014515 ==
3092 00:59:00.017366 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 00:59:00.020900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 00:59:00.020984 ==
3095 00:59:00.027406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 00:59:00.034232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3097 00:59:00.040999 [CA 0] Center 37 (7~68) winsize 62
3098 00:59:00.044429 [CA 1] Center 37 (7~68) winsize 62
3099 00:59:00.047744 [CA 2] Center 35 (5~65) winsize 61
3100 00:59:00.051121 [CA 3] Center 34 (4~64) winsize 61
3101 00:59:00.054411 [CA 4] Center 34 (4~64) winsize 61
3102 00:59:00.057734 [CA 5] Center 33 (3~63) winsize 61
3103 00:59:00.057829
3104 00:59:00.061041 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3105 00:59:00.061118
3106 00:59:00.064802 [CATrainingPosCal] consider 1 rank data
3107 00:59:00.068158 u2DelayCellTimex100 = 270/100 ps
3108 00:59:00.071378 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 00:59:00.074432 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3110 00:59:00.081505 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3111 00:59:00.084658 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 00:59:00.087831 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 00:59:00.091022 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3114 00:59:00.091109
3115 00:59:00.094863 CA PerBit enable=1, Macro0, CA PI delay=33
3116 00:59:00.094951
3117 00:59:00.098197 [CBTSetCACLKResult] CA Dly = 33
3118 00:59:00.098279 CS Dly: 7 (0~38)
3119 00:59:00.098340 ==
3120 00:59:00.101461 Dram Type= 6, Freq= 0, CH_1, rank 1
3121 00:59:00.107632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 00:59:00.107726 ==
3123 00:59:00.111541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3124 00:59:00.117719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3125 00:59:00.126691 [CA 0] Center 37 (7~68) winsize 62
3126 00:59:00.129933 [CA 1] Center 37 (7~68) winsize 62
3127 00:59:00.133730 [CA 2] Center 35 (5~65) winsize 61
3128 00:59:00.136790 [CA 3] Center 34 (4~65) winsize 62
3129 00:59:00.140397 [CA 4] Center 35 (5~65) winsize 61
3130 00:59:00.143330 [CA 5] Center 34 (4~64) winsize 61
3131 00:59:00.143419
3132 00:59:00.146386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3133 00:59:00.146488
3134 00:59:00.149829 [CATrainingPosCal] consider 2 rank data
3135 00:59:00.153242 u2DelayCellTimex100 = 270/100 ps
3136 00:59:00.156667 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3137 00:59:00.163438 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3138 00:59:00.166760 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3139 00:59:00.170028 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 00:59:00.173465 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3141 00:59:00.176220 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3142 00:59:00.176306
3143 00:59:00.179653 CA PerBit enable=1, Macro0, CA PI delay=33
3144 00:59:00.179736
3145 00:59:00.183050 [CBTSetCACLKResult] CA Dly = 33
3146 00:59:00.183134 CS Dly: 8 (0~41)
3147 00:59:00.186490
3148 00:59:00.189744 ----->DramcWriteLeveling(PI) begin...
3149 00:59:00.189832 ==
3150 00:59:00.192830 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 00:59:00.196541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 00:59:00.196619 ==
3153 00:59:00.200254 Write leveling (Byte 0): 25 => 25
3154 00:59:00.203024 Write leveling (Byte 1): 28 => 28
3155 00:59:00.206464 DramcWriteLeveling(PI) end<-----
3156 00:59:00.206575
3157 00:59:00.206661 ==
3158 00:59:00.209677 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 00:59:00.212962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 00:59:00.213045 ==
3161 00:59:00.216309 [Gating] SW mode calibration
3162 00:59:00.222768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3163 00:59:00.229656 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3164 00:59:00.232825 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 00:59:00.236327 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 00:59:00.243069 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 00:59:00.246359 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 00:59:00.249543 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 00:59:00.256220 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 00:59:00.259595 0 15 24 | B1->B0 | 3131 2929 | 0 0 | (0 0) (0 0)
3171 00:59:00.262664 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3172 00:59:00.269360 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 00:59:00.272583 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 00:59:00.275985 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 00:59:00.279334 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 00:59:00.286179 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 00:59:00.289461 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 00:59:00.296211 1 0 24 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
3179 00:59:00.299546 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 00:59:00.302205 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 00:59:00.306123 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 00:59:00.312511 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 00:59:00.315709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 00:59:00.318877 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 00:59:00.325376 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 00:59:00.328743 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3187 00:59:00.332489 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3188 00:59:00.338904 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 00:59:00.342112 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 00:59:00.345140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 00:59:00.352106 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 00:59:00.355522 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 00:59:00.358663 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 00:59:00.365556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 00:59:00.368746 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 00:59:00.372001 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 00:59:00.378740 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 00:59:00.381697 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 00:59:00.385752 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 00:59:00.391966 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 00:59:00.395335 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 00:59:00.398762 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3203 00:59:00.405527 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3204 00:59:00.408834 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 00:59:00.412088 Total UI for P1: 0, mck2ui 16
3206 00:59:00.415463 best dqsien dly found for B0: ( 1, 3, 26)
3207 00:59:00.418708 Total UI for P1: 0, mck2ui 16
3208 00:59:00.421986 best dqsien dly found for B1: ( 1, 3, 26)
3209 00:59:00.425021 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3210 00:59:00.428818 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3211 00:59:00.428903
3212 00:59:00.431635 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3213 00:59:00.435036 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3214 00:59:00.438430 [Gating] SW calibration Done
3215 00:59:00.438525 ==
3216 00:59:00.441850 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 00:59:00.445264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 00:59:00.445341 ==
3219 00:59:00.448609 RX Vref Scan: 0
3220 00:59:00.448677
3221 00:59:00.451751 RX Vref 0 -> 0, step: 1
3222 00:59:00.451828
3223 00:59:00.451885 RX Delay -40 -> 252, step: 8
3224 00:59:00.458844 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3225 00:59:00.461870 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3226 00:59:00.465390 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3227 00:59:00.468240 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3228 00:59:00.472005 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3229 00:59:00.478096 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3230 00:59:00.481441 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3231 00:59:00.485273 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3232 00:59:00.488046 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3233 00:59:00.491752 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3234 00:59:00.498437 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3235 00:59:00.501411 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3236 00:59:00.505031 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3237 00:59:00.508298 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3238 00:59:00.515035 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3239 00:59:00.518352 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3240 00:59:00.518432 ==
3241 00:59:00.521704 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 00:59:00.525165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 00:59:00.525251 ==
3244 00:59:00.525312 DQS Delay:
3245 00:59:00.528490 DQS0 = 0, DQS1 = 0
3246 00:59:00.528567 DQM Delay:
3247 00:59:00.531669 DQM0 = 119, DQM1 = 116
3248 00:59:00.531741 DQ Delay:
3249 00:59:00.534725 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3250 00:59:00.538080 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3251 00:59:00.541485 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3252 00:59:00.548239 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3253 00:59:00.548333
3254 00:59:00.548397
3255 00:59:00.548452 ==
3256 00:59:00.551561 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 00:59:00.554868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 00:59:00.554946 ==
3259 00:59:00.555004
3260 00:59:00.555056
3261 00:59:00.558146 TX Vref Scan disable
3262 00:59:00.558229 == TX Byte 0 ==
3263 00:59:00.565019 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3264 00:59:00.568389 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3265 00:59:00.568465 == TX Byte 1 ==
3266 00:59:00.575079 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 00:59:00.578486 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 00:59:00.578560 ==
3269 00:59:00.581667 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 00:59:00.584997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 00:59:00.585070 ==
3272 00:59:00.597084 TX Vref=22, minBit 9, minWin=24, winSum=413
3273 00:59:00.600873 TX Vref=24, minBit 9, minWin=25, winSum=421
3274 00:59:00.604132 TX Vref=26, minBit 10, minWin=25, winSum=425
3275 00:59:00.606929 TX Vref=28, minBit 10, minWin=25, winSum=428
3276 00:59:00.610851 TX Vref=30, minBit 2, minWin=26, winSum=428
3277 00:59:00.617520 TX Vref=32, minBit 10, minWin=26, winSum=431
3278 00:59:00.620662 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 32
3279 00:59:00.620742
3280 00:59:00.623721 Final TX Range 1 Vref 32
3281 00:59:00.623792
3282 00:59:00.623847 ==
3283 00:59:00.626973 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 00:59:00.630720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 00:59:00.633673 ==
3286 00:59:00.633777
3287 00:59:00.633870
3288 00:59:00.633956 TX Vref Scan disable
3289 00:59:00.637099 == TX Byte 0 ==
3290 00:59:00.640799 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3291 00:59:00.647264 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3292 00:59:00.647359 == TX Byte 1 ==
3293 00:59:00.650622 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3294 00:59:00.656918 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3295 00:59:00.657008
3296 00:59:00.657072 [DATLAT]
3297 00:59:00.657127 Freq=1200, CH1 RK0
3298 00:59:00.657179
3299 00:59:00.660308 DATLAT Default: 0xd
3300 00:59:00.663609 0, 0xFFFF, sum = 0
3301 00:59:00.663684 1, 0xFFFF, sum = 0
3302 00:59:00.666939 2, 0xFFFF, sum = 0
3303 00:59:00.667007 3, 0xFFFF, sum = 0
3304 00:59:00.670340 4, 0xFFFF, sum = 0
3305 00:59:00.670406 5, 0xFFFF, sum = 0
3306 00:59:00.673591 6, 0xFFFF, sum = 0
3307 00:59:00.673661 7, 0xFFFF, sum = 0
3308 00:59:00.677028 8, 0xFFFF, sum = 0
3309 00:59:00.677108 9, 0xFFFF, sum = 0
3310 00:59:00.680435 10, 0xFFFF, sum = 0
3311 00:59:00.680503 11, 0xFFFF, sum = 0
3312 00:59:00.683762 12, 0x0, sum = 1
3313 00:59:00.683836 13, 0x0, sum = 2
3314 00:59:00.687061 14, 0x0, sum = 3
3315 00:59:00.687135 15, 0x0, sum = 4
3316 00:59:00.690273 best_step = 13
3317 00:59:00.690350
3318 00:59:00.690429 ==
3319 00:59:00.693737 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 00:59:00.696994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 00:59:00.697084 ==
3322 00:59:00.697147 RX Vref Scan: 1
3323 00:59:00.700242
3324 00:59:00.700322 Set Vref Range= 32 -> 127
3325 00:59:00.700390
3326 00:59:00.703422 RX Vref 32 -> 127, step: 1
3327 00:59:00.703503
3328 00:59:00.706968 RX Delay -5 -> 252, step: 4
3329 00:59:00.707050
3330 00:59:00.710297 Set Vref, RX VrefLevel [Byte0]: 32
3331 00:59:00.713668 [Byte1]: 32
3332 00:59:00.713752
3333 00:59:00.717035 Set Vref, RX VrefLevel [Byte0]: 33
3334 00:59:00.720324 [Byte1]: 33
3335 00:59:00.723680
3336 00:59:00.723792 Set Vref, RX VrefLevel [Byte0]: 34
3337 00:59:00.727053 [Byte1]: 34
3338 00:59:00.731657
3339 00:59:00.731757 Set Vref, RX VrefLevel [Byte0]: 35
3340 00:59:00.734781 [Byte1]: 35
3341 00:59:00.739471
3342 00:59:00.739562 Set Vref, RX VrefLevel [Byte0]: 36
3343 00:59:00.742393 [Byte1]: 36
3344 00:59:00.747042
3345 00:59:00.747138 Set Vref, RX VrefLevel [Byte0]: 37
3346 00:59:00.750443 [Byte1]: 37
3347 00:59:00.754647
3348 00:59:00.754736 Set Vref, RX VrefLevel [Byte0]: 38
3349 00:59:00.758098 [Byte1]: 38
3350 00:59:00.762983
3351 00:59:00.763072 Set Vref, RX VrefLevel [Byte0]: 39
3352 00:59:00.765824 [Byte1]: 39
3353 00:59:00.770765
3354 00:59:00.770852 Set Vref, RX VrefLevel [Byte0]: 40
3355 00:59:00.774013 [Byte1]: 40
3356 00:59:00.778166
3357 00:59:00.778242 Set Vref, RX VrefLevel [Byte0]: 41
3358 00:59:00.781509 [Byte1]: 41
3359 00:59:00.786168
3360 00:59:00.786254 Set Vref, RX VrefLevel [Byte0]: 42
3361 00:59:00.789376 [Byte1]: 42
3362 00:59:00.794016
3363 00:59:00.794105 Set Vref, RX VrefLevel [Byte0]: 43
3364 00:59:00.797416 [Byte1]: 43
3365 00:59:00.802024
3366 00:59:00.802107 Set Vref, RX VrefLevel [Byte0]: 44
3367 00:59:00.805321 [Byte1]: 44
3368 00:59:00.810112
3369 00:59:00.810199 Set Vref, RX VrefLevel [Byte0]: 45
3370 00:59:00.813197 [Byte1]: 45
3371 00:59:00.817465
3372 00:59:00.817558 Set Vref, RX VrefLevel [Byte0]: 46
3373 00:59:00.821351 [Byte1]: 46
3374 00:59:00.826029
3375 00:59:00.826116 Set Vref, RX VrefLevel [Byte0]: 47
3376 00:59:00.828679 [Byte1]: 47
3377 00:59:00.833425
3378 00:59:00.833515 Set Vref, RX VrefLevel [Byte0]: 48
3379 00:59:00.836795 [Byte1]: 48
3380 00:59:00.841613
3381 00:59:00.841702 Set Vref, RX VrefLevel [Byte0]: 49
3382 00:59:00.844305 [Byte1]: 49
3383 00:59:00.848976
3384 00:59:00.849063 Set Vref, RX VrefLevel [Byte0]: 50
3385 00:59:00.852145 [Byte1]: 50
3386 00:59:00.857237
3387 00:59:00.857334 Set Vref, RX VrefLevel [Byte0]: 51
3388 00:59:00.860410 [Byte1]: 51
3389 00:59:00.864749
3390 00:59:00.864834 Set Vref, RX VrefLevel [Byte0]: 52
3391 00:59:00.868447 [Byte1]: 52
3392 00:59:00.872901
3393 00:59:00.872989 Set Vref, RX VrefLevel [Byte0]: 53
3394 00:59:00.875880 [Byte1]: 53
3395 00:59:00.880467
3396 00:59:00.880553 Set Vref, RX VrefLevel [Byte0]: 54
3397 00:59:00.884007 [Byte1]: 54
3398 00:59:00.888549
3399 00:59:00.888642 Set Vref, RX VrefLevel [Byte0]: 55
3400 00:59:00.891661 [Byte1]: 55
3401 00:59:00.896231
3402 00:59:00.896319 Set Vref, RX VrefLevel [Byte0]: 56
3403 00:59:00.899407 [Byte1]: 56
3404 00:59:00.903989
3405 00:59:00.904075 Set Vref, RX VrefLevel [Byte0]: 57
3406 00:59:00.907282 [Byte1]: 57
3407 00:59:00.912024
3408 00:59:00.912100 Set Vref, RX VrefLevel [Byte0]: 58
3409 00:59:00.915440 [Byte1]: 58
3410 00:59:00.920084
3411 00:59:00.920169 Set Vref, RX VrefLevel [Byte0]: 59
3412 00:59:00.923310 [Byte1]: 59
3413 00:59:00.927621
3414 00:59:00.927729 Set Vref, RX VrefLevel [Byte0]: 60
3415 00:59:00.930774 [Byte1]: 60
3416 00:59:00.935900
3417 00:59:00.936008 Set Vref, RX VrefLevel [Byte0]: 61
3418 00:59:00.938943 [Byte1]: 61
3419 00:59:00.943425
3420 00:59:00.943517 Set Vref, RX VrefLevel [Byte0]: 62
3421 00:59:00.946860 [Byte1]: 62
3422 00:59:00.951541
3423 00:59:00.951668 Set Vref, RX VrefLevel [Byte0]: 63
3424 00:59:00.954275 [Byte1]: 63
3425 00:59:00.959353
3426 00:59:00.959459 Set Vref, RX VrefLevel [Byte0]: 64
3427 00:59:00.962618 [Byte1]: 64
3428 00:59:00.966512
3429 00:59:00.970224 Set Vref, RX VrefLevel [Byte0]: 65
3430 00:59:00.970303 [Byte1]: 65
3431 00:59:00.974665
3432 00:59:00.974750 Set Vref, RX VrefLevel [Byte0]: 66
3433 00:59:00.978116 [Byte1]: 66
3434 00:59:00.982727
3435 00:59:00.982820 Set Vref, RX VrefLevel [Byte0]: 67
3436 00:59:00.986001 [Byte1]: 67
3437 00:59:00.990408
3438 00:59:00.990488 Set Vref, RX VrefLevel [Byte0]: 68
3439 00:59:00.993985 [Byte1]: 68
3440 00:59:00.998090
3441 00:59:00.998190 Final RX Vref Byte 0 = 55 to rank0
3442 00:59:01.001788 Final RX Vref Byte 1 = 48 to rank0
3443 00:59:01.004691 Final RX Vref Byte 0 = 55 to rank1
3444 00:59:01.008097 Final RX Vref Byte 1 = 48 to rank1==
3445 00:59:01.011823 Dram Type= 6, Freq= 0, CH_1, rank 0
3446 00:59:01.018499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 00:59:01.018598 ==
3448 00:59:01.018659 DQS Delay:
3449 00:59:01.018715 DQS0 = 0, DQS1 = 0
3450 00:59:01.021750 DQM Delay:
3451 00:59:01.021829 DQM0 = 119, DQM1 = 116
3452 00:59:01.025179 DQ Delay:
3453 00:59:01.027866 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3454 00:59:01.031221 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3455 00:59:01.034561 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3456 00:59:01.037868 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3457 00:59:01.037976
3458 00:59:01.038060
3459 00:59:01.047928 [DQSOSCAuto] RK0, (LSB)MR18= 0x315, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3460 00:59:01.048067 CH1 RK0: MR19=404, MR18=315
3461 00:59:01.054598 CH1_RK0: MR19=0x404, MR18=0x315, DQSOSC=401, MR23=63, INC=40, DEC=27
3462 00:59:01.054754
3463 00:59:01.058543 ----->DramcWriteLeveling(PI) begin...
3464 00:59:01.058673 ==
3465 00:59:01.061256 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 00:59:01.065033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 00:59:01.068138 ==
3468 00:59:01.068327 Write leveling (Byte 0): 26 => 26
3469 00:59:01.071453 Write leveling (Byte 1): 29 => 29
3470 00:59:01.074628 DramcWriteLeveling(PI) end<-----
3471 00:59:01.074728
3472 00:59:01.074791 ==
3473 00:59:01.078240 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 00:59:01.084471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 00:59:01.084600 ==
3476 00:59:01.084688 [Gating] SW mode calibration
3477 00:59:01.094585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3478 00:59:01.097990 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3479 00:59:01.104479 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3480 00:59:01.108209 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 00:59:01.111436 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 00:59:01.114663 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 00:59:01.121398 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 00:59:01.124337 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3485 00:59:01.128083 0 15 24 | B1->B0 | 2727 3434 | 1 0 | (1 0) (0 0)
3486 00:59:01.134804 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3487 00:59:01.137507 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 00:59:01.140984 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 00:59:01.147714 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 00:59:01.150987 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 00:59:01.154181 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 00:59:01.160731 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3493 00:59:01.164479 1 0 24 | B1->B0 | 4242 2d2d | 0 0 | (0 0) (0 0)
3494 00:59:01.167635 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 00:59:01.174276 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 00:59:01.177375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 00:59:01.180556 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 00:59:01.187122 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 00:59:01.190713 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 00:59:01.193832 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3501 00:59:01.200499 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3502 00:59:01.203838 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3503 00:59:01.207048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 00:59:01.214226 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 00:59:01.217098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 00:59:01.220510 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 00:59:01.227013 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 00:59:01.230399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 00:59:01.234162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 00:59:01.240487 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 00:59:01.243841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 00:59:01.247153 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 00:59:01.254020 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 00:59:01.257378 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 00:59:01.260544 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 00:59:01.267243 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3517 00:59:01.270576 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3518 00:59:01.273769 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3519 00:59:01.276996 Total UI for P1: 0, mck2ui 16
3520 00:59:01.280116 best dqsien dly found for B1: ( 1, 3, 22)
3521 00:59:01.283847 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 00:59:01.286856 Total UI for P1: 0, mck2ui 16
3523 00:59:01.290061 best dqsien dly found for B0: ( 1, 3, 26)
3524 00:59:01.293846 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3525 00:59:01.300265 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3526 00:59:01.300366
3527 00:59:01.303412 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3528 00:59:01.307010 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3529 00:59:01.310139 [Gating] SW calibration Done
3530 00:59:01.310223 ==
3531 00:59:01.313428 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 00:59:01.316675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 00:59:01.316759 ==
3534 00:59:01.319998 RX Vref Scan: 0
3535 00:59:01.320080
3536 00:59:01.320140 RX Vref 0 -> 0, step: 1
3537 00:59:01.320197
3538 00:59:01.323383 RX Delay -40 -> 252, step: 8
3539 00:59:01.326813 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3540 00:59:01.330073 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3541 00:59:01.336732 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3542 00:59:01.340301 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3543 00:59:01.343625 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3544 00:59:01.346826 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3545 00:59:01.350022 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3546 00:59:01.357139 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3547 00:59:01.360609 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3548 00:59:01.363884 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3549 00:59:01.367003 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3550 00:59:01.370398 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3551 00:59:01.377032 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3552 00:59:01.380327 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3553 00:59:01.383805 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3554 00:59:01.386447 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3555 00:59:01.386524 ==
3556 00:59:01.390204 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 00:59:01.396596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 00:59:01.396715 ==
3559 00:59:01.396803 DQS Delay:
3560 00:59:01.399765 DQS0 = 0, DQS1 = 0
3561 00:59:01.399854 DQM Delay:
3562 00:59:01.403499 DQM0 = 120, DQM1 = 118
3563 00:59:01.403600 DQ Delay:
3564 00:59:01.406467 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3565 00:59:01.409456 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3566 00:59:01.413350 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3567 00:59:01.416256 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3568 00:59:01.416352
3569 00:59:01.416411
3570 00:59:01.416465 ==
3571 00:59:01.419658 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 00:59:01.426256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 00:59:01.426357 ==
3574 00:59:01.426418
3575 00:59:01.426473
3576 00:59:01.426526 TX Vref Scan disable
3577 00:59:01.429469 == TX Byte 0 ==
3578 00:59:01.432905 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 00:59:01.436691 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 00:59:01.439379 == TX Byte 1 ==
3581 00:59:01.442668 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3582 00:59:01.449357 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3583 00:59:01.449476 ==
3584 00:59:01.452558 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 00:59:01.455927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 00:59:01.456034 ==
3587 00:59:01.467773 TX Vref=22, minBit 9, minWin=25, winSum=420
3588 00:59:01.471081 TX Vref=24, minBit 1, minWin=26, winSum=426
3589 00:59:01.474330 TX Vref=26, minBit 1, minWin=26, winSum=431
3590 00:59:01.477770 TX Vref=28, minBit 2, minWin=26, winSum=430
3591 00:59:01.481093 TX Vref=30, minBit 9, minWin=26, winSum=434
3592 00:59:01.484420 TX Vref=32, minBit 9, minWin=26, winSum=438
3593 00:59:01.491367 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 32
3594 00:59:01.491561
3595 00:59:01.494661 Final TX Range 1 Vref 32
3596 00:59:01.494820
3597 00:59:01.494917 ==
3598 00:59:01.497874 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 00:59:01.501328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 00:59:01.501492 ==
3601 00:59:01.501614
3602 00:59:01.501707
3603 00:59:01.504646 TX Vref Scan disable
3604 00:59:01.507953 == TX Byte 0 ==
3605 00:59:01.511030 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3606 00:59:01.514019 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3607 00:59:01.517842 == TX Byte 1 ==
3608 00:59:01.521222 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 00:59:01.524422 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 00:59:01.524506
3611 00:59:01.527449 [DATLAT]
3612 00:59:01.527537 Freq=1200, CH1 RK1
3613 00:59:01.527625
3614 00:59:01.531162 DATLAT Default: 0xd
3615 00:59:01.531246 0, 0xFFFF, sum = 0
3616 00:59:01.534046 1, 0xFFFF, sum = 0
3617 00:59:01.534127 2, 0xFFFF, sum = 0
3618 00:59:01.537604 3, 0xFFFF, sum = 0
3619 00:59:01.537689 4, 0xFFFF, sum = 0
3620 00:59:01.541183 5, 0xFFFF, sum = 0
3621 00:59:01.541267 6, 0xFFFF, sum = 0
3622 00:59:01.544442 7, 0xFFFF, sum = 0
3623 00:59:01.544525 8, 0xFFFF, sum = 0
3624 00:59:01.547746 9, 0xFFFF, sum = 0
3625 00:59:01.551198 10, 0xFFFF, sum = 0
3626 00:59:01.551327 11, 0xFFFF, sum = 0
3627 00:59:01.553956 12, 0x0, sum = 1
3628 00:59:01.554048 13, 0x0, sum = 2
3629 00:59:01.554119 14, 0x0, sum = 3
3630 00:59:01.557464 15, 0x0, sum = 4
3631 00:59:01.557545 best_step = 13
3632 00:59:01.557618
3633 00:59:01.560855 ==
3634 00:59:01.560934 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 00:59:01.567567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 00:59:01.567661 ==
3637 00:59:01.567724 RX Vref Scan: 0
3638 00:59:01.567780
3639 00:59:01.570911 RX Vref 0 -> 0, step: 1
3640 00:59:01.570993
3641 00:59:01.574095 RX Delay -5 -> 252, step: 4
3642 00:59:01.577077 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3643 00:59:01.580930 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3644 00:59:01.587291 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3645 00:59:01.590471 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3646 00:59:01.593975 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3647 00:59:01.597391 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3648 00:59:01.600659 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3649 00:59:01.607385 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3650 00:59:01.610872 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3651 00:59:01.614138 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3652 00:59:01.617435 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3653 00:59:01.620496 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3654 00:59:01.627002 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3655 00:59:01.630684 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3656 00:59:01.633762 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3657 00:59:01.637145 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3658 00:59:01.637304 ==
3659 00:59:01.640341 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 00:59:01.647311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 00:59:01.647430 ==
3662 00:59:01.647568 DQS Delay:
3663 00:59:01.650162 DQS0 = 0, DQS1 = 0
3664 00:59:01.650257 DQM Delay:
3665 00:59:01.653726 DQM0 = 120, DQM1 = 116
3666 00:59:01.653809 DQ Delay:
3667 00:59:01.656988 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3668 00:59:01.660467 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3669 00:59:01.663982 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3670 00:59:01.667348 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3671 00:59:01.667441
3672 00:59:01.667532
3673 00:59:01.676964 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3674 00:59:01.677085 CH1 RK1: MR19=403, MR18=10EE
3675 00:59:01.683607 CH1_RK1: MR19=0x403, MR18=0x10EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3676 00:59:01.686790 [RxdqsGatingPostProcess] freq 1200
3677 00:59:01.693444 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3678 00:59:01.697165 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 00:59:01.700068 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 00:59:01.703772 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 00:59:01.706845 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 00:59:01.710339 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 00:59:01.710415 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 00:59:01.713389 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 00:59:01.716707 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 00:59:01.720671 Pre-setting of DQS Precalculation
3687 00:59:01.726790 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3688 00:59:01.733360 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3689 00:59:01.740604 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3690 00:59:01.740734
3691 00:59:01.740833
3692 00:59:01.743843 [Calibration Summary] 2400 Mbps
3693 00:59:01.743950 CH 0, Rank 0
3694 00:59:01.747082 SW Impedance : PASS
3695 00:59:01.750351 DUTY Scan : NO K
3696 00:59:01.750454 ZQ Calibration : PASS
3697 00:59:01.753374 Jitter Meter : NO K
3698 00:59:01.756995 CBT Training : PASS
3699 00:59:01.757070 Write leveling : PASS
3700 00:59:01.759990 RX DQS gating : PASS
3701 00:59:01.763590 RX DQ/DQS(RDDQC) : PASS
3702 00:59:01.763675 TX DQ/DQS : PASS
3703 00:59:01.766671 RX DATLAT : PASS
3704 00:59:01.770523 RX DQ/DQS(Engine): PASS
3705 00:59:01.770609 TX OE : NO K
3706 00:59:01.773376 All Pass.
3707 00:59:01.773478
3708 00:59:01.773572 CH 0, Rank 1
3709 00:59:01.776679 SW Impedance : PASS
3710 00:59:01.776758 DUTY Scan : NO K
3711 00:59:01.780065 ZQ Calibration : PASS
3712 00:59:01.783485 Jitter Meter : NO K
3713 00:59:01.783571 CBT Training : PASS
3714 00:59:01.786778 Write leveling : PASS
3715 00:59:01.790185 RX DQS gating : PASS
3716 00:59:01.790270 RX DQ/DQS(RDDQC) : PASS
3717 00:59:01.793514 TX DQ/DQS : PASS
3718 00:59:01.793628 RX DATLAT : PASS
3719 00:59:01.796817 RX DQ/DQS(Engine): PASS
3720 00:59:01.800040 TX OE : NO K
3721 00:59:01.800151 All Pass.
3722 00:59:01.800238
3723 00:59:01.800329 CH 1, Rank 0
3724 00:59:01.803222 SW Impedance : PASS
3725 00:59:01.806462 DUTY Scan : NO K
3726 00:59:01.806558 ZQ Calibration : PASS
3727 00:59:01.809706 Jitter Meter : NO K
3728 00:59:01.813035 CBT Training : PASS
3729 00:59:01.813138 Write leveling : PASS
3730 00:59:01.816960 RX DQS gating : PASS
3731 00:59:01.820044 RX DQ/DQS(RDDQC) : PASS
3732 00:59:01.820114 TX DQ/DQS : PASS
3733 00:59:01.823603 RX DATLAT : PASS
3734 00:59:01.826746 RX DQ/DQS(Engine): PASS
3735 00:59:01.826817 TX OE : NO K
3736 00:59:01.830088 All Pass.
3737 00:59:01.830172
3738 00:59:01.830232 CH 1, Rank 1
3739 00:59:01.833485 SW Impedance : PASS
3740 00:59:01.833576 DUTY Scan : NO K
3741 00:59:01.836842 ZQ Calibration : PASS
3742 00:59:01.840078 Jitter Meter : NO K
3743 00:59:01.840161 CBT Training : PASS
3744 00:59:01.843287 Write leveling : PASS
3745 00:59:01.843372 RX DQS gating : PASS
3746 00:59:01.846572 RX DQ/DQS(RDDQC) : PASS
3747 00:59:01.850187 TX DQ/DQS : PASS
3748 00:59:01.850298 RX DATLAT : PASS
3749 00:59:01.853624 RX DQ/DQS(Engine): PASS
3750 00:59:01.856716 TX OE : NO K
3751 00:59:01.856791 All Pass.
3752 00:59:01.856857
3753 00:59:01.859804 DramC Write-DBI off
3754 00:59:01.859875 PER_BANK_REFRESH: Hybrid Mode
3755 00:59:01.863524 TX_TRACKING: ON
3756 00:59:01.873373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3757 00:59:01.876552 [FAST_K] Save calibration result to emmc
3758 00:59:01.879854 dramc_set_vcore_voltage set vcore to 650000
3759 00:59:01.879954 Read voltage for 600, 5
3760 00:59:01.883231 Vio18 = 0
3761 00:59:01.883306 Vcore = 650000
3762 00:59:01.883365 Vdram = 0
3763 00:59:01.886635 Vddq = 0
3764 00:59:01.886706 Vmddr = 0
3765 00:59:01.889979 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3766 00:59:01.896586 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3767 00:59:01.899995 MEM_TYPE=3, freq_sel=19
3768 00:59:01.903328 sv_algorithm_assistance_LP4_1600
3769 00:59:01.906561 ============ PULL DRAM RESETB DOWN ============
3770 00:59:01.909795 ========== PULL DRAM RESETB DOWN end =========
3771 00:59:01.916208 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3772 00:59:01.919443 ===================================
3773 00:59:01.919523 LPDDR4 DRAM CONFIGURATION
3774 00:59:01.922867 ===================================
3775 00:59:01.926037 EX_ROW_EN[0] = 0x0
3776 00:59:01.926139 EX_ROW_EN[1] = 0x0
3777 00:59:01.929820 LP4Y_EN = 0x0
3778 00:59:01.929900 WORK_FSP = 0x0
3779 00:59:01.933532 WL = 0x2
3780 00:59:01.933626 RL = 0x2
3781 00:59:01.936596 BL = 0x2
3782 00:59:01.936689 RPST = 0x0
3783 00:59:01.939975 RD_PRE = 0x0
3784 00:59:01.943299 WR_PRE = 0x1
3785 00:59:01.943395 WR_PST = 0x0
3786 00:59:01.946610 DBI_WR = 0x0
3787 00:59:01.946680 DBI_RD = 0x0
3788 00:59:01.949916 OTF = 0x1
3789 00:59:01.953353 ===================================
3790 00:59:01.956608 ===================================
3791 00:59:01.956707 ANA top config
3792 00:59:01.959668 ===================================
3793 00:59:01.963325 DLL_ASYNC_EN = 0
3794 00:59:01.966108 ALL_SLAVE_EN = 1
3795 00:59:01.966181 NEW_RANK_MODE = 1
3796 00:59:01.969257 DLL_IDLE_MODE = 1
3797 00:59:01.972695 LP45_APHY_COMB_EN = 1
3798 00:59:01.976148 TX_ODT_DIS = 1
3799 00:59:01.976246 NEW_8X_MODE = 1
3800 00:59:01.979463 ===================================
3801 00:59:01.983010 ===================================
3802 00:59:01.985853 data_rate = 1200
3803 00:59:01.989673 CKR = 1
3804 00:59:01.993029 DQ_P2S_RATIO = 8
3805 00:59:01.995784 ===================================
3806 00:59:01.999222 CA_P2S_RATIO = 8
3807 00:59:02.002594 DQ_CA_OPEN = 0
3808 00:59:02.005955 DQ_SEMI_OPEN = 0
3809 00:59:02.006030 CA_SEMI_OPEN = 0
3810 00:59:02.009324 CA_FULL_RATE = 0
3811 00:59:02.012538 DQ_CKDIV4_EN = 1
3812 00:59:02.015923 CA_CKDIV4_EN = 1
3813 00:59:02.019230 CA_PREDIV_EN = 0
3814 00:59:02.022453 PH8_DLY = 0
3815 00:59:02.022536 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3816 00:59:02.025642 DQ_AAMCK_DIV = 4
3817 00:59:02.029058 CA_AAMCK_DIV = 4
3818 00:59:02.032431 CA_ADMCK_DIV = 4
3819 00:59:02.035646 DQ_TRACK_CA_EN = 0
3820 00:59:02.039480 CA_PICK = 600
3821 00:59:02.039579 CA_MCKIO = 600
3822 00:59:02.042518 MCKIO_SEMI = 0
3823 00:59:02.045793 PLL_FREQ = 2288
3824 00:59:02.048954 DQ_UI_PI_RATIO = 32
3825 00:59:02.052264 CA_UI_PI_RATIO = 0
3826 00:59:02.055635 ===================================
3827 00:59:02.058950 ===================================
3828 00:59:02.062396 memory_type:LPDDR4
3829 00:59:02.062468 GP_NUM : 10
3830 00:59:02.065749 SRAM_EN : 1
3831 00:59:02.065821 MD32_EN : 0
3832 00:59:02.068969 ===================================
3833 00:59:02.072220 [ANA_INIT] >>>>>>>>>>>>>>
3834 00:59:02.075244 <<<<<< [CONFIGURE PHASE]: ANA_TX
3835 00:59:02.079126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3836 00:59:02.082306 ===================================
3837 00:59:02.085412 data_rate = 1200,PCW = 0X5800
3838 00:59:02.088949 ===================================
3839 00:59:02.092401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3840 00:59:02.098475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 00:59:02.101753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 00:59:02.108109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3843 00:59:02.111491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3844 00:59:02.114793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3845 00:59:02.114912 [ANA_INIT] flow start
3846 00:59:02.118085 [ANA_INIT] PLL >>>>>>>>
3847 00:59:02.121839 [ANA_INIT] PLL <<<<<<<<
3848 00:59:02.121917 [ANA_INIT] MIDPI >>>>>>>>
3849 00:59:02.125159 [ANA_INIT] MIDPI <<<<<<<<
3850 00:59:02.128520 [ANA_INIT] DLL >>>>>>>>
3851 00:59:02.128642 [ANA_INIT] flow end
3852 00:59:02.135040 ============ LP4 DIFF to SE enter ============
3853 00:59:02.138499 ============ LP4 DIFF to SE exit ============
3854 00:59:02.141979 [ANA_INIT] <<<<<<<<<<<<<
3855 00:59:02.145276 [Flow] Enable top DCM control >>>>>
3856 00:59:02.148302 [Flow] Enable top DCM control <<<<<
3857 00:59:02.148386 Enable DLL master slave shuffle
3858 00:59:02.155045 ==============================================================
3859 00:59:02.158179 Gating Mode config
3860 00:59:02.161284 ==============================================================
3861 00:59:02.164710 Config description:
3862 00:59:02.174788 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3863 00:59:02.181160 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3864 00:59:02.184989 SELPH_MODE 0: By rank 1: By Phase
3865 00:59:02.191230 ==============================================================
3866 00:59:02.194603 GAT_TRACK_EN = 1
3867 00:59:02.197759 RX_GATING_MODE = 2
3868 00:59:02.201162 RX_GATING_TRACK_MODE = 2
3869 00:59:02.204382 SELPH_MODE = 1
3870 00:59:02.204467 PICG_EARLY_EN = 1
3871 00:59:02.208076 VALID_LAT_VALUE = 1
3872 00:59:02.214565 ==============================================================
3873 00:59:02.218214 Enter into Gating configuration >>>>
3874 00:59:02.221136 Exit from Gating configuration <<<<
3875 00:59:02.224310 Enter into DVFS_PRE_config >>>>>
3876 00:59:02.234509 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3877 00:59:02.237684 Exit from DVFS_PRE_config <<<<<
3878 00:59:02.241125 Enter into PICG configuration >>>>
3879 00:59:02.244498 Exit from PICG configuration <<<<
3880 00:59:02.247942 [RX_INPUT] configuration >>>>>
3881 00:59:02.251264 [RX_INPUT] configuration <<<<<
3882 00:59:02.254560 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3883 00:59:02.261505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3884 00:59:02.267900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 00:59:02.274403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 00:59:02.281198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 00:59:02.284539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 00:59:02.291114 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3889 00:59:02.294523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3890 00:59:02.297856 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3891 00:59:02.301177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3892 00:59:02.307595 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3893 00:59:02.310950 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 00:59:02.314162 ===================================
3895 00:59:02.317772 LPDDR4 DRAM CONFIGURATION
3896 00:59:02.321067 ===================================
3897 00:59:02.321148 EX_ROW_EN[0] = 0x0
3898 00:59:02.324356 EX_ROW_EN[1] = 0x0
3899 00:59:02.324461 LP4Y_EN = 0x0
3900 00:59:02.327520 WORK_FSP = 0x0
3901 00:59:02.327614 WL = 0x2
3902 00:59:02.331187 RL = 0x2
3903 00:59:02.331295 BL = 0x2
3904 00:59:02.334181 RPST = 0x0
3905 00:59:02.334264 RD_PRE = 0x0
3906 00:59:02.337430 WR_PRE = 0x1
3907 00:59:02.337534 WR_PST = 0x0
3908 00:59:02.341212 DBI_WR = 0x0
3909 00:59:02.341308 DBI_RD = 0x0
3910 00:59:02.344164 OTF = 0x1
3911 00:59:02.347919 ===================================
3912 00:59:02.351032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3913 00:59:02.354406 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3914 00:59:02.361237 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 00:59:02.364547 ===================================
3916 00:59:02.364642 LPDDR4 DRAM CONFIGURATION
3917 00:59:02.367720 ===================================
3918 00:59:02.370972 EX_ROW_EN[0] = 0x10
3919 00:59:02.374203 EX_ROW_EN[1] = 0x0
3920 00:59:02.374282 LP4Y_EN = 0x0
3921 00:59:02.377438 WORK_FSP = 0x0
3922 00:59:02.377510 WL = 0x2
3923 00:59:02.380622 RL = 0x2
3924 00:59:02.380696 BL = 0x2
3925 00:59:02.383979 RPST = 0x0
3926 00:59:02.384091 RD_PRE = 0x0
3927 00:59:02.387374 WR_PRE = 0x1
3928 00:59:02.387471 WR_PST = 0x0
3929 00:59:02.391127 DBI_WR = 0x0
3930 00:59:02.391215 DBI_RD = 0x0
3931 00:59:02.394419 OTF = 0x1
3932 00:59:02.397173 ===================================
3933 00:59:02.403787 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3934 00:59:02.407278 nWR fixed to 30
3935 00:59:02.410683 [ModeRegInit_LP4] CH0 RK0
3936 00:59:02.410784 [ModeRegInit_LP4] CH0 RK1
3937 00:59:02.413989 [ModeRegInit_LP4] CH1 RK0
3938 00:59:02.417331 [ModeRegInit_LP4] CH1 RK1
3939 00:59:02.417441 match AC timing 17
3940 00:59:02.423680 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3941 00:59:02.426969 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3942 00:59:02.430336 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3943 00:59:02.436993 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3944 00:59:02.440671 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3945 00:59:02.440785 ==
3946 00:59:02.443562 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 00:59:02.446926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 00:59:02.447036 ==
3949 00:59:02.454165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 00:59:02.460341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3951 00:59:02.463957 [CA 0] Center 35 (5~66) winsize 62
3952 00:59:02.467240 [CA 1] Center 35 (5~66) winsize 62
3953 00:59:02.470575 [CA 2] Center 33 (3~64) winsize 62
3954 00:59:02.473907 [CA 3] Center 33 (3~64) winsize 62
3955 00:59:02.477029 [CA 4] Center 33 (2~64) winsize 63
3956 00:59:02.480333 [CA 5] Center 32 (2~63) winsize 62
3957 00:59:02.480442
3958 00:59:02.484144 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3959 00:59:02.484243
3960 00:59:02.487292 [CATrainingPosCal] consider 1 rank data
3961 00:59:02.490754 u2DelayCellTimex100 = 270/100 ps
3962 00:59:02.493966 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3963 00:59:02.497259 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3964 00:59:02.500667 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3965 00:59:02.504011 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3966 00:59:02.507250 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3967 00:59:02.510560 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3968 00:59:02.510646
3969 00:59:02.517282 CA PerBit enable=1, Macro0, CA PI delay=32
3970 00:59:02.517386
3971 00:59:02.517479 [CBTSetCACLKResult] CA Dly = 32
3972 00:59:02.520624 CS Dly: 4 (0~35)
3973 00:59:02.520706 ==
3974 00:59:02.523994 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 00:59:02.527237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 00:59:02.527321 ==
3977 00:59:02.533703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 00:59:02.540377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3979 00:59:02.543800 [CA 0] Center 35 (5~66) winsize 62
3980 00:59:02.547147 [CA 1] Center 35 (5~66) winsize 62
3981 00:59:02.550458 [CA 2] Center 34 (3~65) winsize 63
3982 00:59:02.553693 [CA 3] Center 33 (3~64) winsize 62
3983 00:59:02.556905 [CA 4] Center 32 (2~63) winsize 62
3984 00:59:02.560400 [CA 5] Center 32 (2~63) winsize 62
3985 00:59:02.560503
3986 00:59:02.563404 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3987 00:59:02.563486
3988 00:59:02.566634 [CATrainingPosCal] consider 2 rank data
3989 00:59:02.570463 u2DelayCellTimex100 = 270/100 ps
3990 00:59:02.573524 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3991 00:59:02.576576 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3992 00:59:02.580522 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3993 00:59:02.583666 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3994 00:59:02.586781 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3995 00:59:02.593038 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3996 00:59:02.593166
3997 00:59:02.596662 CA PerBit enable=1, Macro0, CA PI delay=32
3998 00:59:02.596768
3999 00:59:02.600416 [CBTSetCACLKResult] CA Dly = 32
4000 00:59:02.600522 CS Dly: 4 (0~36)
4001 00:59:02.600611
4002 00:59:02.603636 ----->DramcWriteLeveling(PI) begin...
4003 00:59:02.603740 ==
4004 00:59:02.606911 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 00:59:02.610207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 00:59:02.613361 ==
4007 00:59:02.613463 Write leveling (Byte 0): 34 => 34
4008 00:59:02.616679 Write leveling (Byte 1): 30 => 30
4009 00:59:02.620033 DramcWriteLeveling(PI) end<-----
4010 00:59:02.620134
4011 00:59:02.620238 ==
4012 00:59:02.623483 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 00:59:02.629713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 00:59:02.629828 ==
4015 00:59:02.633016 [Gating] SW mode calibration
4016 00:59:02.640171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4017 00:59:02.642928 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4018 00:59:02.649645 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 00:59:02.652996 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 00:59:02.656318 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 00:59:02.663155 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
4022 00:59:02.666556 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4023 00:59:02.669786 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 00:59:02.673002 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 00:59:02.679596 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 00:59:02.682992 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 00:59:02.686281 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 00:59:02.693262 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 00:59:02.696195 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4030 00:59:02.699546 0 10 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4031 00:59:02.706197 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 00:59:02.709662 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 00:59:02.713106 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 00:59:02.719338 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 00:59:02.722869 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 00:59:02.726406 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 00:59:02.732532 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4038 00:59:02.735912 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4039 00:59:02.739817 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 00:59:02.746468 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 00:59:02.749227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 00:59:02.752651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 00:59:02.759458 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 00:59:02.762840 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 00:59:02.766163 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 00:59:02.772874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 00:59:02.776229 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 00:59:02.779671 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 00:59:02.786354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 00:59:02.789362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 00:59:02.792473 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 00:59:02.795878 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 00:59:02.803151 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4054 00:59:02.805759 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4055 00:59:02.809050 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 00:59:02.812986 Total UI for P1: 0, mck2ui 16
4057 00:59:02.815949 best dqsien dly found for B0: ( 0, 13, 14)
4058 00:59:02.819532 Total UI for P1: 0, mck2ui 16
4059 00:59:02.822443 best dqsien dly found for B1: ( 0, 13, 14)
4060 00:59:02.826205 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4061 00:59:02.832837 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4062 00:59:02.832936
4063 00:59:02.835791 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4064 00:59:02.839226 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4065 00:59:02.842420 [Gating] SW calibration Done
4066 00:59:02.842507 ==
4067 00:59:02.845740 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 00:59:02.849102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 00:59:02.849205 ==
4070 00:59:02.849296 RX Vref Scan: 0
4071 00:59:02.852388
4072 00:59:02.852455 RX Vref 0 -> 0, step: 1
4073 00:59:02.852510
4074 00:59:02.856257 RX Delay -230 -> 252, step: 16
4075 00:59:02.859165 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4076 00:59:02.862445 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4077 00:59:02.869136 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4078 00:59:02.872524 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4079 00:59:02.876045 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4080 00:59:02.879427 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4081 00:59:02.886308 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4082 00:59:02.889006 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4083 00:59:02.892328 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4084 00:59:02.895729 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4085 00:59:02.902318 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4086 00:59:02.906020 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4087 00:59:02.909035 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4088 00:59:02.912455 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4089 00:59:02.915679 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4090 00:59:02.922284 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4091 00:59:02.922387 ==
4092 00:59:02.925611 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 00:59:02.928810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 00:59:02.928884 ==
4095 00:59:02.928954 DQS Delay:
4096 00:59:02.932061 DQS0 = 0, DQS1 = 0
4097 00:59:02.932151 DQM Delay:
4098 00:59:02.935700 DQM0 = 49, DQM1 = 44
4099 00:59:02.935796 DQ Delay:
4100 00:59:02.938921 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4101 00:59:02.942687 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4102 00:59:02.945687 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4103 00:59:02.948684 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4104 00:59:02.948769
4105 00:59:02.948828
4106 00:59:02.948887 ==
4107 00:59:02.952321 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 00:59:02.955280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 00:59:02.958955 ==
4110 00:59:02.959043
4111 00:59:02.959122
4112 00:59:02.959193 TX Vref Scan disable
4113 00:59:02.962055 == TX Byte 0 ==
4114 00:59:02.965622 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4115 00:59:02.968636 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4116 00:59:02.972106 == TX Byte 1 ==
4117 00:59:02.975446 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4118 00:59:02.981789 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4119 00:59:02.981894 ==
4120 00:59:02.985139 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 00:59:02.988536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 00:59:02.988612 ==
4123 00:59:02.988691
4124 00:59:02.988761
4125 00:59:02.992005 TX Vref Scan disable
4126 00:59:02.995269 == TX Byte 0 ==
4127 00:59:02.998602 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4128 00:59:03.002049 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4129 00:59:03.002127 == TX Byte 1 ==
4130 00:59:03.008502 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4131 00:59:03.011975 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4132 00:59:03.012052
4133 00:59:03.012124 [DATLAT]
4134 00:59:03.015044 Freq=600, CH0 RK0
4135 00:59:03.015152
4136 00:59:03.015225 DATLAT Default: 0x9
4137 00:59:03.018744 0, 0xFFFF, sum = 0
4138 00:59:03.018816 1, 0xFFFF, sum = 0
4139 00:59:03.021867 2, 0xFFFF, sum = 0
4140 00:59:03.025420 3, 0xFFFF, sum = 0
4141 00:59:03.025522 4, 0xFFFF, sum = 0
4142 00:59:03.028713 5, 0xFFFF, sum = 0
4143 00:59:03.028784 6, 0xFFFF, sum = 0
4144 00:59:03.032195 7, 0xFFFF, sum = 0
4145 00:59:03.032315 8, 0x0, sum = 1
4146 00:59:03.032421 9, 0x0, sum = 2
4147 00:59:03.035612 10, 0x0, sum = 3
4148 00:59:03.035703 11, 0x0, sum = 4
4149 00:59:03.038327 best_step = 9
4150 00:59:03.038399
4151 00:59:03.038460 ==
4152 00:59:03.041712 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 00:59:03.045128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 00:59:03.045258 ==
4155 00:59:03.048536 RX Vref Scan: 1
4156 00:59:03.048708
4157 00:59:03.048798 RX Vref 0 -> 0, step: 1
4158 00:59:03.048886
4159 00:59:03.051808 RX Delay -163 -> 252, step: 8
4160 00:59:03.051920
4161 00:59:03.055122 Set Vref, RX VrefLevel [Byte0]: 56
4162 00:59:03.058375 [Byte1]: 50
4163 00:59:03.062915
4164 00:59:03.063053 Final RX Vref Byte 0 = 56 to rank0
4165 00:59:03.065624 Final RX Vref Byte 1 = 50 to rank0
4166 00:59:03.069003 Final RX Vref Byte 0 = 56 to rank1
4167 00:59:03.072768 Final RX Vref Byte 1 = 50 to rank1==
4168 00:59:03.076162 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 00:59:03.082623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 00:59:03.082722 ==
4171 00:59:03.082784 DQS Delay:
4172 00:59:03.082837 DQS0 = 0, DQS1 = 0
4173 00:59:03.085818 DQM Delay:
4174 00:59:03.085911 DQM0 = 52, DQM1 = 46
4175 00:59:03.088878 DQ Delay:
4176 00:59:03.092577 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4177 00:59:03.092659 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4178 00:59:03.095631 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4179 00:59:03.102692 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4180 00:59:03.102781
4181 00:59:03.102840
4182 00:59:03.109343 [DQSOSCAuto] RK0, (LSB)MR18= 0x776a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4183 00:59:03.112724 CH0 RK0: MR19=808, MR18=776A
4184 00:59:03.119361 CH0_RK0: MR19=0x808, MR18=0x776A, DQSOSC=387, MR23=63, INC=175, DEC=116
4185 00:59:03.119475
4186 00:59:03.122664 ----->DramcWriteLeveling(PI) begin...
4187 00:59:03.122738 ==
4188 00:59:03.126021 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 00:59:03.129248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 00:59:03.129332 ==
4191 00:59:03.132221 Write leveling (Byte 0): 34 => 34
4192 00:59:03.135957 Write leveling (Byte 1): 31 => 31
4193 00:59:03.139012 DramcWriteLeveling(PI) end<-----
4194 00:59:03.139095
4195 00:59:03.139159 ==
4196 00:59:03.142309 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 00:59:03.145707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 00:59:03.145785 ==
4199 00:59:03.149071 [Gating] SW mode calibration
4200 00:59:03.155633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4201 00:59:03.162327 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4202 00:59:03.165632 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 00:59:03.168660 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 00:59:03.175620 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 00:59:03.178643 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
4206 00:59:03.182089 0 9 16 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (1 0)
4207 00:59:03.189248 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 00:59:03.192574 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 00:59:03.195626 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 00:59:03.202015 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 00:59:03.205768 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 00:59:03.208803 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 00:59:03.215351 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4214 00:59:03.218701 0 10 16 | B1->B0 | 3e3e 4141 | 0 1 | (0 0) (0 0)
4215 00:59:03.222107 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 00:59:03.228831 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 00:59:03.232187 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 00:59:03.235607 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 00:59:03.241659 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 00:59:03.245545 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 00:59:03.248637 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4222 00:59:03.255211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 00:59:03.258370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 00:59:03.261736 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 00:59:03.268864 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 00:59:03.272211 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 00:59:03.275374 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 00:59:03.281954 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 00:59:03.285254 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 00:59:03.287931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 00:59:03.294742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 00:59:03.298139 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 00:59:03.301591 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 00:59:03.308232 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 00:59:03.311628 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 00:59:03.314931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 00:59:03.321303 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4238 00:59:03.324646 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4239 00:59:03.327991 Total UI for P1: 0, mck2ui 16
4240 00:59:03.331343 best dqsien dly found for B0: ( 0, 13, 12)
4241 00:59:03.334751 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 00:59:03.338078 Total UI for P1: 0, mck2ui 16
4243 00:59:03.341380 best dqsien dly found for B1: ( 0, 13, 14)
4244 00:59:03.344646 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4245 00:59:03.348012 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4246 00:59:03.348090
4247 00:59:03.351356 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4248 00:59:03.358403 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4249 00:59:03.358503 [Gating] SW calibration Done
4250 00:59:03.358573 ==
4251 00:59:03.361607 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 00:59:03.368007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 00:59:03.368127 ==
4254 00:59:03.368215 RX Vref Scan: 0
4255 00:59:03.368315
4256 00:59:03.371383 RX Vref 0 -> 0, step: 1
4257 00:59:03.371473
4258 00:59:03.374548 RX Delay -230 -> 252, step: 16
4259 00:59:03.378332 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4260 00:59:03.381489 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4261 00:59:03.384828 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4262 00:59:03.391066 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4263 00:59:03.394377 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4264 00:59:03.397709 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4265 00:59:03.401104 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4266 00:59:03.408007 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4267 00:59:03.411038 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4268 00:59:03.414645 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4269 00:59:03.417758 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4270 00:59:03.421238 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4271 00:59:03.427881 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4272 00:59:03.431191 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4273 00:59:03.435173 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4274 00:59:03.438271 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4275 00:59:03.441413 ==
4276 00:59:03.441513 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 00:59:03.448097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 00:59:03.448279 ==
4279 00:59:03.448339 DQS Delay:
4280 00:59:03.451470 DQS0 = 0, DQS1 = 0
4281 00:59:03.451538 DQM Delay:
4282 00:59:03.454783 DQM0 = 50, DQM1 = 42
4283 00:59:03.454850 DQ Delay:
4284 00:59:03.458278 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4285 00:59:03.461652 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4286 00:59:03.464467 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4287 00:59:03.467714 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4288 00:59:03.467829
4289 00:59:03.467908
4290 00:59:03.467973 ==
4291 00:59:03.471026 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 00:59:03.474318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 00:59:03.474385 ==
4294 00:59:03.474439
4295 00:59:03.474495
4296 00:59:03.478033 TX Vref Scan disable
4297 00:59:03.481463 == TX Byte 0 ==
4298 00:59:03.484320 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4299 00:59:03.487769 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4300 00:59:03.491183 == TX Byte 1 ==
4301 00:59:03.494707 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4302 00:59:03.498046 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4303 00:59:03.498154 ==
4304 00:59:03.501113 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 00:59:03.504394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 00:59:03.507812 ==
4307 00:59:03.507901
4308 00:59:03.507985
4309 00:59:03.508085 TX Vref Scan disable
4310 00:59:03.511817 == TX Byte 0 ==
4311 00:59:03.515097 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4312 00:59:03.521456 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4313 00:59:03.521575 == TX Byte 1 ==
4314 00:59:03.524833 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4315 00:59:03.531372 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4316 00:59:03.531455
4317 00:59:03.531515 [DATLAT]
4318 00:59:03.531575 Freq=600, CH0 RK1
4319 00:59:03.531628
4320 00:59:03.534418 DATLAT Default: 0x9
4321 00:59:03.534499 0, 0xFFFF, sum = 0
4322 00:59:03.538019 1, 0xFFFF, sum = 0
4323 00:59:03.538089 2, 0xFFFF, sum = 0
4324 00:59:03.541535 3, 0xFFFF, sum = 0
4325 00:59:03.544755 4, 0xFFFF, sum = 0
4326 00:59:03.544828 5, 0xFFFF, sum = 0
4327 00:59:03.548534 6, 0xFFFF, sum = 0
4328 00:59:03.548605 7, 0xFFFF, sum = 0
4329 00:59:03.548662 8, 0x0, sum = 1
4330 00:59:03.551569 9, 0x0, sum = 2
4331 00:59:03.551636 10, 0x0, sum = 3
4332 00:59:03.555041 11, 0x0, sum = 4
4333 00:59:03.555118 best_step = 9
4334 00:59:03.555174
4335 00:59:03.555227 ==
4336 00:59:03.558019 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 00:59:03.564879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 00:59:03.564982 ==
4339 00:59:03.565043 RX Vref Scan: 0
4340 00:59:03.565098
4341 00:59:03.568295 RX Vref 0 -> 0, step: 1
4342 00:59:03.568364
4343 00:59:03.571714 RX Delay -163 -> 252, step: 8
4344 00:59:03.574537 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4345 00:59:03.581266 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4346 00:59:03.584662 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4347 00:59:03.588027 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4348 00:59:03.591248 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4349 00:59:03.594544 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4350 00:59:03.601314 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4351 00:59:03.604275 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4352 00:59:03.607923 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4353 00:59:03.611029 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4354 00:59:03.614222 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4355 00:59:03.621129 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4356 00:59:03.624252 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4357 00:59:03.627482 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4358 00:59:03.630998 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4359 00:59:03.634413 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4360 00:59:03.637690 ==
4361 00:59:03.640996 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 00:59:03.644112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 00:59:03.644214 ==
4364 00:59:03.644280 DQS Delay:
4365 00:59:03.647387 DQS0 = 0, DQS1 = 0
4366 00:59:03.647458 DQM Delay:
4367 00:59:03.651173 DQM0 = 54, DQM1 = 46
4368 00:59:03.651246 DQ Delay:
4369 00:59:03.654486 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4370 00:59:03.657802 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4371 00:59:03.661178 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4372 00:59:03.663940 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4373 00:59:03.664016
4374 00:59:03.664073
4375 00:59:03.671038 [DQSOSCAuto] RK1, (LSB)MR18= 0x6626, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4376 00:59:03.674103 CH0 RK1: MR19=808, MR18=6626
4377 00:59:03.680639 CH0_RK1: MR19=0x808, MR18=0x6626, DQSOSC=390, MR23=63, INC=172, DEC=114
4378 00:59:03.684004 [RxdqsGatingPostProcess] freq 600
4379 00:59:03.690757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4380 00:59:03.694092 Pre-setting of DQS Precalculation
4381 00:59:03.697420 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4382 00:59:03.697494 ==
4383 00:59:03.700835 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 00:59:03.704186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 00:59:03.704262 ==
4386 00:59:03.710791 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 00:59:03.717451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4388 00:59:03.720780 [CA 0] Center 35 (5~66) winsize 62
4389 00:59:03.723956 [CA 1] Center 35 (5~66) winsize 62
4390 00:59:03.727548 [CA 2] Center 34 (4~65) winsize 62
4391 00:59:03.730393 [CA 3] Center 34 (3~65) winsize 63
4392 00:59:03.734013 [CA 4] Center 34 (4~65) winsize 62
4393 00:59:03.737092 [CA 5] Center 33 (3~64) winsize 62
4394 00:59:03.737174
4395 00:59:03.740394 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4396 00:59:03.740496
4397 00:59:03.743789 [CATrainingPosCal] consider 1 rank data
4398 00:59:03.747098 u2DelayCellTimex100 = 270/100 ps
4399 00:59:03.750286 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 00:59:03.753668 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 00:59:03.757540 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 00:59:03.760716 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4403 00:59:03.764026 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 00:59:03.767459 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 00:59:03.767553
4406 00:59:03.773691 CA PerBit enable=1, Macro0, CA PI delay=33
4407 00:59:03.773779
4408 00:59:03.777073 [CBTSetCACLKResult] CA Dly = 33
4409 00:59:03.777144 CS Dly: 6 (0~37)
4410 00:59:03.777202 ==
4411 00:59:03.780571 Dram Type= 6, Freq= 0, CH_1, rank 1
4412 00:59:03.784043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 00:59:03.784127 ==
4414 00:59:03.790188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 00:59:03.797080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4416 00:59:03.800320 [CA 0] Center 36 (5~67) winsize 63
4417 00:59:03.803749 [CA 1] Center 36 (5~67) winsize 63
4418 00:59:03.807049 [CA 2] Center 34 (4~65) winsize 62
4419 00:59:03.810398 [CA 3] Center 35 (4~66) winsize 63
4420 00:59:03.813777 [CA 4] Center 35 (4~66) winsize 63
4421 00:59:03.817232 [CA 5] Center 34 (4~65) winsize 62
4422 00:59:03.817337
4423 00:59:03.820489 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4424 00:59:03.820567
4425 00:59:03.823643 [CATrainingPosCal] consider 2 rank data
4426 00:59:03.827238 u2DelayCellTimex100 = 270/100 ps
4427 00:59:03.830481 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4428 00:59:03.833888 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4429 00:59:03.837147 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4430 00:59:03.840192 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4431 00:59:03.843438 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4432 00:59:03.847283 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4433 00:59:03.847372
4434 00:59:03.853656 CA PerBit enable=1, Macro0, CA PI delay=34
4435 00:59:03.853753
4436 00:59:03.856798 [CBTSetCACLKResult] CA Dly = 34
4437 00:59:03.856889 CS Dly: 6 (0~38)
4438 00:59:03.856961
4439 00:59:03.860181 ----->DramcWriteLeveling(PI) begin...
4440 00:59:03.860253 ==
4441 00:59:03.863435 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 00:59:03.867266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 00:59:03.867354 ==
4444 00:59:03.870448 Write leveling (Byte 0): 30 => 30
4445 00:59:03.873686 Write leveling (Byte 1): 30 => 30
4446 00:59:03.877034 DramcWriteLeveling(PI) end<-----
4447 00:59:03.877139
4448 00:59:03.877239 ==
4449 00:59:03.880541 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 00:59:03.886823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 00:59:03.886922 ==
4452 00:59:03.887004 [Gating] SW mode calibration
4453 00:59:03.896972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4454 00:59:03.900082 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4455 00:59:03.903861 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 00:59:03.909978 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 00:59:03.913719 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 00:59:03.917146 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 1)
4459 00:59:03.923204 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 00:59:03.926695 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 00:59:03.929994 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 00:59:03.936982 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 00:59:03.940304 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 00:59:03.943716 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 00:59:03.950374 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 00:59:03.953583 0 10 12 | B1->B0 | 2a2a 3838 | 0 0 | (0 0) (0 0)
4467 00:59:03.957042 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4468 00:59:03.963565 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 00:59:03.966921 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 00:59:03.970010 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 00:59:03.976521 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 00:59:03.979790 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 00:59:03.983603 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4474 00:59:03.989980 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4475 00:59:03.993450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 00:59:03.996720 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 00:59:04.002953 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 00:59:04.006342 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:59:04.009804 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 00:59:04.016487 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 00:59:04.019438 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 00:59:04.023257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 00:59:04.029579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 00:59:04.032956 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 00:59:04.036262 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 00:59:04.039478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 00:59:04.046636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 00:59:04.050088 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 00:59:04.052784 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 00:59:04.059686 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4491 00:59:04.063145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 00:59:04.066542 Total UI for P1: 0, mck2ui 16
4493 00:59:04.070019 best dqsien dly found for B0: ( 0, 13, 12)
4494 00:59:04.072595 Total UI for P1: 0, mck2ui 16
4495 00:59:04.075964 best dqsien dly found for B1: ( 0, 13, 14)
4496 00:59:04.079819 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4497 00:59:04.083023 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4498 00:59:04.083106
4499 00:59:04.086090 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4500 00:59:04.089674 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4501 00:59:04.092636 [Gating] SW calibration Done
4502 00:59:04.092725 ==
4503 00:59:04.096339 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 00:59:04.102560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 00:59:04.102689 ==
4506 00:59:04.102783 RX Vref Scan: 0
4507 00:59:04.102869
4508 00:59:04.106251 RX Vref 0 -> 0, step: 1
4509 00:59:04.106354
4510 00:59:04.109144 RX Delay -230 -> 252, step: 16
4511 00:59:04.112929 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4512 00:59:04.116223 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4513 00:59:04.119652 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4514 00:59:04.125745 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4515 00:59:04.129142 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4516 00:59:04.132548 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4517 00:59:04.135841 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4518 00:59:04.142505 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4519 00:59:04.145580 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4520 00:59:04.149262 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4521 00:59:04.152498 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4522 00:59:04.159120 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4523 00:59:04.162561 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4524 00:59:04.165389 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4525 00:59:04.168903 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4526 00:59:04.172396 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4527 00:59:04.175835 ==
4528 00:59:04.179294 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 00:59:04.182740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 00:59:04.182816 ==
4531 00:59:04.182879 DQS Delay:
4532 00:59:04.185323 DQS0 = 0, DQS1 = 0
4533 00:59:04.185400 DQM Delay:
4534 00:59:04.188753 DQM0 = 47, DQM1 = 46
4535 00:59:04.188829 DQ Delay:
4536 00:59:04.192076 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4537 00:59:04.195500 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4538 00:59:04.198998 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4539 00:59:04.202367 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4540 00:59:04.202484
4541 00:59:04.202576
4542 00:59:04.202660 ==
4543 00:59:04.205599 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 00:59:04.208561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 00:59:04.208674 ==
4546 00:59:04.208765
4547 00:59:04.208849
4548 00:59:04.212062 TX Vref Scan disable
4549 00:59:04.215298 == TX Byte 0 ==
4550 00:59:04.218956 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4551 00:59:04.221977 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4552 00:59:04.225465 == TX Byte 1 ==
4553 00:59:04.228732 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4554 00:59:04.231994 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4555 00:59:04.232107 ==
4556 00:59:04.235707 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 00:59:04.241831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 00:59:04.241933 ==
4559 00:59:04.241997
4560 00:59:04.242059
4561 00:59:04.242118 TX Vref Scan disable
4562 00:59:04.245821 == TX Byte 0 ==
4563 00:59:04.249260 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4564 00:59:04.255923 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4565 00:59:04.256018 == TX Byte 1 ==
4566 00:59:04.259164 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 00:59:04.265993 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 00:59:04.266115
4569 00:59:04.266204 [DATLAT]
4570 00:59:04.266288 Freq=600, CH1 RK0
4571 00:59:04.266372
4572 00:59:04.269693 DATLAT Default: 0x9
4573 00:59:04.269799 0, 0xFFFF, sum = 0
4574 00:59:04.272362 1, 0xFFFF, sum = 0
4575 00:59:04.272466 2, 0xFFFF, sum = 0
4576 00:59:04.275762 3, 0xFFFF, sum = 0
4577 00:59:04.279103 4, 0xFFFF, sum = 0
4578 00:59:04.279213 5, 0xFFFF, sum = 0
4579 00:59:04.282393 6, 0xFFFF, sum = 0
4580 00:59:04.282498 7, 0xFFFF, sum = 0
4581 00:59:04.282588 8, 0x0, sum = 1
4582 00:59:04.285760 9, 0x0, sum = 2
4583 00:59:04.285862 10, 0x0, sum = 3
4584 00:59:04.289130 11, 0x0, sum = 4
4585 00:59:04.289235 best_step = 9
4586 00:59:04.289324
4587 00:59:04.289409 ==
4588 00:59:04.292457 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 00:59:04.299265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 00:59:04.299384 ==
4591 00:59:04.299475 RX Vref Scan: 1
4592 00:59:04.299560
4593 00:59:04.302647 RX Vref 0 -> 0, step: 1
4594 00:59:04.302747
4595 00:59:04.306019 RX Delay -163 -> 252, step: 8
4596 00:59:04.306119
4597 00:59:04.309268 Set Vref, RX VrefLevel [Byte0]: 55
4598 00:59:04.312676 [Byte1]: 48
4599 00:59:04.312780
4600 00:59:04.315731 Final RX Vref Byte 0 = 55 to rank0
4601 00:59:04.319404 Final RX Vref Byte 1 = 48 to rank0
4602 00:59:04.322700 Final RX Vref Byte 0 = 55 to rank1
4603 00:59:04.326000 Final RX Vref Byte 1 = 48 to rank1==
4604 00:59:04.329312 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 00:59:04.332293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 00:59:04.332397 ==
4607 00:59:04.335530 DQS Delay:
4608 00:59:04.335635 DQS0 = 0, DQS1 = 0
4609 00:59:04.335722 DQM Delay:
4610 00:59:04.339147 DQM0 = 48, DQM1 = 44
4611 00:59:04.339248 DQ Delay:
4612 00:59:04.342109 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4613 00:59:04.345816 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4614 00:59:04.349149 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4615 00:59:04.352069 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4616 00:59:04.352177
4617 00:59:04.352264
4618 00:59:04.362006 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f75, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4619 00:59:04.366005 CH1 RK0: MR19=808, MR18=4F75
4620 00:59:04.369161 CH1_RK0: MR19=0x808, MR18=0x4F75, DQSOSC=387, MR23=63, INC=175, DEC=116
4621 00:59:04.369272
4622 00:59:04.375433 ----->DramcWriteLeveling(PI) begin...
4623 00:59:04.375551 ==
4624 00:59:04.379003 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 00:59:04.381893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 00:59:04.381999 ==
4627 00:59:04.385316 Write leveling (Byte 0): 29 => 29
4628 00:59:04.389066 Write leveling (Byte 1): 30 => 30
4629 00:59:04.391740 DramcWriteLeveling(PI) end<-----
4630 00:59:04.391844
4631 00:59:04.391931 ==
4632 00:59:04.395626 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 00:59:04.399063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 00:59:04.399170 ==
4635 00:59:04.401770 [Gating] SW mode calibration
4636 00:59:04.408542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4637 00:59:04.415404 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4638 00:59:04.418039 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4639 00:59:04.421983 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 00:59:04.428422 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 00:59:04.431471 0 9 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 1)
4642 00:59:04.435127 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4643 00:59:04.441721 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 00:59:04.445103 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 00:59:04.448437 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 00:59:04.454533 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 00:59:04.458270 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 00:59:04.461326 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4649 00:59:04.467923 0 10 12 | B1->B0 | 3636 3232 | 0 0 | (0 0) (0 0)
4650 00:59:04.471552 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4651 00:59:04.474381 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 00:59:04.481002 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 00:59:04.484240 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 00:59:04.487580 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 00:59:04.494636 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 00:59:04.497468 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4657 00:59:04.500978 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4658 00:59:04.507742 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 00:59:04.510965 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 00:59:04.514393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 00:59:04.517726 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 00:59:04.524415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 00:59:04.527793 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 00:59:04.531183 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 00:59:04.537940 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 00:59:04.541054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 00:59:04.544061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 00:59:04.550996 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 00:59:04.554301 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 00:59:04.557814 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 00:59:04.564109 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 00:59:04.567458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4673 00:59:04.570770 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4674 00:59:04.574085 Total UI for P1: 0, mck2ui 16
4675 00:59:04.577395 best dqsien dly found for B1: ( 0, 13, 8)
4676 00:59:04.584064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 00:59:04.584163 Total UI for P1: 0, mck2ui 16
4678 00:59:04.590365 best dqsien dly found for B0: ( 0, 13, 14)
4679 00:59:04.593941 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4680 00:59:04.597008 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4681 00:59:04.597090
4682 00:59:04.600534 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4683 00:59:04.603948 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4684 00:59:04.607526 [Gating] SW calibration Done
4685 00:59:04.607629 ==
4686 00:59:04.610949 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 00:59:04.614070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 00:59:04.614156 ==
4689 00:59:04.617134 RX Vref Scan: 0
4690 00:59:04.617215
4691 00:59:04.617275 RX Vref 0 -> 0, step: 1
4692 00:59:04.617329
4693 00:59:04.620733 RX Delay -230 -> 252, step: 16
4694 00:59:04.627132 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4695 00:59:04.630588 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4696 00:59:04.634037 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4697 00:59:04.637435 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4698 00:59:04.640137 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4699 00:59:04.647168 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4700 00:59:04.650390 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4701 00:59:04.653675 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4702 00:59:04.656756 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4703 00:59:04.660716 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4704 00:59:04.667262 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4705 00:59:04.670656 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4706 00:59:04.674036 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4707 00:59:04.676726 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4708 00:59:04.683951 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4709 00:59:04.686719 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4710 00:59:04.686804 ==
4711 00:59:04.690227 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 00:59:04.693700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 00:59:04.693785 ==
4714 00:59:04.697108 DQS Delay:
4715 00:59:04.697189 DQS0 = 0, DQS1 = 0
4716 00:59:04.700345 DQM Delay:
4717 00:59:04.700419 DQM0 = 51, DQM1 = 47
4718 00:59:04.700477 DQ Delay:
4719 00:59:04.703578 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4720 00:59:04.707064 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4721 00:59:04.709980 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4722 00:59:04.713441 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4723 00:59:04.713568
4724 00:59:04.713632
4725 00:59:04.713688 ==
4726 00:59:04.716781 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 00:59:04.723658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 00:59:04.723758 ==
4729 00:59:04.723821
4730 00:59:04.723877
4731 00:59:04.723931 TX Vref Scan disable
4732 00:59:04.727148 == TX Byte 0 ==
4733 00:59:04.730998 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 00:59:04.737187 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 00:59:04.737328 == TX Byte 1 ==
4736 00:59:04.740672 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4737 00:59:04.747515 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4738 00:59:04.747646 ==
4739 00:59:04.750340 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 00:59:04.753799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 00:59:04.753905 ==
4742 00:59:04.753969
4743 00:59:04.754025
4744 00:59:04.757017 TX Vref Scan disable
4745 00:59:04.757095 == TX Byte 0 ==
4746 00:59:04.763617 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4747 00:59:04.767651 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4748 00:59:04.767764 == TX Byte 1 ==
4749 00:59:04.773996 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4750 00:59:04.777219 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4751 00:59:04.777309
4752 00:59:04.777373 [DATLAT]
4753 00:59:04.780482 Freq=600, CH1 RK1
4754 00:59:04.780586
4755 00:59:04.780673 DATLAT Default: 0x9
4756 00:59:04.783918 0, 0xFFFF, sum = 0
4757 00:59:04.784018 1, 0xFFFF, sum = 0
4758 00:59:04.787340 2, 0xFFFF, sum = 0
4759 00:59:04.787446 3, 0xFFFF, sum = 0
4760 00:59:04.790719 4, 0xFFFF, sum = 0
4761 00:59:04.794148 5, 0xFFFF, sum = 0
4762 00:59:04.794229 6, 0xFFFF, sum = 0
4763 00:59:04.797528 7, 0xFFFF, sum = 0
4764 00:59:04.797646 8, 0x0, sum = 1
4765 00:59:04.797733 9, 0x0, sum = 2
4766 00:59:04.800264 10, 0x0, sum = 3
4767 00:59:04.800350 11, 0x0, sum = 4
4768 00:59:04.803761 best_step = 9
4769 00:59:04.803845
4770 00:59:04.803906 ==
4771 00:59:04.807261 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 00:59:04.810075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 00:59:04.810152 ==
4774 00:59:04.813307 RX Vref Scan: 0
4775 00:59:04.813380
4776 00:59:04.813438 RX Vref 0 -> 0, step: 1
4777 00:59:04.813513
4778 00:59:04.817208 RX Delay -163 -> 252, step: 8
4779 00:59:04.824217 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4780 00:59:04.827356 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4781 00:59:04.830608 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4782 00:59:04.833908 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4783 00:59:04.841378 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4784 00:59:04.843925 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4785 00:59:04.847521 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4786 00:59:04.851033 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4787 00:59:04.854453 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4788 00:59:04.860490 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4789 00:59:04.864308 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4790 00:59:04.867627 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4791 00:59:04.870473 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4792 00:59:04.873963 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4793 00:59:04.880561 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4794 00:59:04.883664 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4795 00:59:04.883758 ==
4796 00:59:04.887045 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 00:59:04.890685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 00:59:04.890767 ==
4799 00:59:04.893672 DQS Delay:
4800 00:59:04.893756 DQS0 = 0, DQS1 = 0
4801 00:59:04.893816 DQM Delay:
4802 00:59:04.896944 DQM0 = 49, DQM1 = 44
4803 00:59:04.897045 DQ Delay:
4804 00:59:04.900353 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4805 00:59:04.903688 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =52
4806 00:59:04.907323 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4807 00:59:04.910825 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4808 00:59:04.910934
4809 00:59:04.911032
4810 00:59:04.920367 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4811 00:59:04.923793 CH1 RK1: MR19=808, MR18=6E25
4812 00:59:04.927174 CH1_RK1: MR19=0x808, MR18=0x6E25, DQSOSC=389, MR23=63, INC=173, DEC=115
4813 00:59:04.930554 [RxdqsGatingPostProcess] freq 600
4814 00:59:04.937271 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4815 00:59:04.940471 Pre-setting of DQS Precalculation
4816 00:59:04.943963 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4817 00:59:04.953414 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4818 00:59:04.960376 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4819 00:59:04.960504
4820 00:59:04.960606
4821 00:59:04.963334 [Calibration Summary] 1200 Mbps
4822 00:59:04.963442 CH 0, Rank 0
4823 00:59:04.967071 SW Impedance : PASS
4824 00:59:04.967179 DUTY Scan : NO K
4825 00:59:04.970262 ZQ Calibration : PASS
4826 00:59:04.973666 Jitter Meter : NO K
4827 00:59:04.973753 CBT Training : PASS
4828 00:59:04.976579 Write leveling : PASS
4829 00:59:04.980048 RX DQS gating : PASS
4830 00:59:04.980164 RX DQ/DQS(RDDQC) : PASS
4831 00:59:04.983503 TX DQ/DQS : PASS
4832 00:59:04.983583 RX DATLAT : PASS
4833 00:59:04.986842 RX DQ/DQS(Engine): PASS
4834 00:59:04.990238 TX OE : NO K
4835 00:59:04.990317 All Pass.
4836 00:59:04.990376
4837 00:59:04.990439 CH 0, Rank 1
4838 00:59:04.993045 SW Impedance : PASS
4839 00:59:04.996451 DUTY Scan : NO K
4840 00:59:04.996544 ZQ Calibration : PASS
4841 00:59:04.999925 Jitter Meter : NO K
4842 00:59:05.003085 CBT Training : PASS
4843 00:59:05.003193 Write leveling : PASS
4844 00:59:05.006651 RX DQS gating : PASS
4845 00:59:05.009644 RX DQ/DQS(RDDQC) : PASS
4846 00:59:05.009718 TX DQ/DQS : PASS
4847 00:59:05.012923 RX DATLAT : PASS
4848 00:59:05.016253 RX DQ/DQS(Engine): PASS
4849 00:59:05.016351 TX OE : NO K
4850 00:59:05.019576 All Pass.
4851 00:59:05.019673
4852 00:59:05.019771 CH 1, Rank 0
4853 00:59:05.023407 SW Impedance : PASS
4854 00:59:05.023500 DUTY Scan : NO K
4855 00:59:05.026745 ZQ Calibration : PASS
4856 00:59:05.030103 Jitter Meter : NO K
4857 00:59:05.030212 CBT Training : PASS
4858 00:59:05.033324 Write leveling : PASS
4859 00:59:05.036609 RX DQS gating : PASS
4860 00:59:05.036692 RX DQ/DQS(RDDQC) : PASS
4861 00:59:05.039834 TX DQ/DQS : PASS
4862 00:59:05.039942 RX DATLAT : PASS
4863 00:59:05.043264 RX DQ/DQS(Engine): PASS
4864 00:59:05.046561 TX OE : NO K
4865 00:59:05.046650 All Pass.
4866 00:59:05.046711
4867 00:59:05.046767 CH 1, Rank 1
4868 00:59:05.049920 SW Impedance : PASS
4869 00:59:05.053205 DUTY Scan : NO K
4870 00:59:05.053283 ZQ Calibration : PASS
4871 00:59:05.056589 Jitter Meter : NO K
4872 00:59:05.059441 CBT Training : PASS
4873 00:59:05.059549 Write leveling : PASS
4874 00:59:05.062734 RX DQS gating : PASS
4875 00:59:05.066159 RX DQ/DQS(RDDQC) : PASS
4876 00:59:05.066234 TX DQ/DQS : PASS
4877 00:59:05.069511 RX DATLAT : PASS
4878 00:59:05.073280 RX DQ/DQS(Engine): PASS
4879 00:59:05.073364 TX OE : NO K
4880 00:59:05.076621 All Pass.
4881 00:59:05.076698
4882 00:59:05.076762 DramC Write-DBI off
4883 00:59:05.079904 PER_BANK_REFRESH: Hybrid Mode
4884 00:59:05.079978 TX_TRACKING: ON
4885 00:59:05.089688 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4886 00:59:05.092910 [FAST_K] Save calibration result to emmc
4887 00:59:05.096311 dramc_set_vcore_voltage set vcore to 662500
4888 00:59:05.099779 Read voltage for 933, 3
4889 00:59:05.099858 Vio18 = 0
4890 00:59:05.103139 Vcore = 662500
4891 00:59:05.103234 Vdram = 0
4892 00:59:05.103324 Vddq = 0
4893 00:59:05.103409 Vmddr = 0
4894 00:59:05.110023 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4895 00:59:05.116342 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4896 00:59:05.116441 MEM_TYPE=3, freq_sel=17
4897 00:59:05.119602 sv_algorithm_assistance_LP4_1600
4898 00:59:05.123392 ============ PULL DRAM RESETB DOWN ============
4899 00:59:05.129977 ========== PULL DRAM RESETB DOWN end =========
4900 00:59:05.132683 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4901 00:59:05.136578 ===================================
4902 00:59:05.139984 LPDDR4 DRAM CONFIGURATION
4903 00:59:05.143262 ===================================
4904 00:59:05.143336 EX_ROW_EN[0] = 0x0
4905 00:59:05.146440 EX_ROW_EN[1] = 0x0
4906 00:59:05.146516 LP4Y_EN = 0x0
4907 00:59:05.149742 WORK_FSP = 0x0
4908 00:59:05.149813 WL = 0x3
4909 00:59:05.152905 RL = 0x3
4910 00:59:05.152986 BL = 0x2
4911 00:59:05.156246 RPST = 0x0
4912 00:59:05.159597 RD_PRE = 0x0
4913 00:59:05.159704 WR_PRE = 0x1
4914 00:59:05.162967 WR_PST = 0x0
4915 00:59:05.163038 DBI_WR = 0x0
4916 00:59:05.166386 DBI_RD = 0x0
4917 00:59:05.166458 OTF = 0x1
4918 00:59:05.169621 ===================================
4919 00:59:05.173004 ===================================
4920 00:59:05.173075 ANA top config
4921 00:59:05.176375 ===================================
4922 00:59:05.179637 DLL_ASYNC_EN = 0
4923 00:59:05.182950 ALL_SLAVE_EN = 1
4924 00:59:05.186057 NEW_RANK_MODE = 1
4925 00:59:05.189675 DLL_IDLE_MODE = 1
4926 00:59:05.189751 LP45_APHY_COMB_EN = 1
4927 00:59:05.192520 TX_ODT_DIS = 1
4928 00:59:05.195913 NEW_8X_MODE = 1
4929 00:59:05.199039 ===================================
4930 00:59:05.202474 ===================================
4931 00:59:05.206175 data_rate = 1866
4932 00:59:05.209620 CKR = 1
4933 00:59:05.209697 DQ_P2S_RATIO = 8
4934 00:59:05.212384 ===================================
4935 00:59:05.216317 CA_P2S_RATIO = 8
4936 00:59:05.219662 DQ_CA_OPEN = 0
4937 00:59:05.222986 DQ_SEMI_OPEN = 0
4938 00:59:05.226252 CA_SEMI_OPEN = 0
4939 00:59:05.228938 CA_FULL_RATE = 0
4940 00:59:05.232232 DQ_CKDIV4_EN = 1
4941 00:59:05.232315 CA_CKDIV4_EN = 1
4942 00:59:05.235788 CA_PREDIV_EN = 0
4943 00:59:05.239199 PH8_DLY = 0
4944 00:59:05.242446 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4945 00:59:05.245712 DQ_AAMCK_DIV = 4
4946 00:59:05.248928 CA_AAMCK_DIV = 4
4947 00:59:05.249013 CA_ADMCK_DIV = 4
4948 00:59:05.252110 DQ_TRACK_CA_EN = 0
4949 00:59:05.255397 CA_PICK = 933
4950 00:59:05.258769 CA_MCKIO = 933
4951 00:59:05.262030 MCKIO_SEMI = 0
4952 00:59:05.265177 PLL_FREQ = 3732
4953 00:59:05.268527 DQ_UI_PI_RATIO = 32
4954 00:59:05.268644 CA_UI_PI_RATIO = 0
4955 00:59:05.271776 ===================================
4956 00:59:05.275251 ===================================
4957 00:59:05.278595 memory_type:LPDDR4
4958 00:59:05.282021 GP_NUM : 10
4959 00:59:05.282120 SRAM_EN : 1
4960 00:59:05.285565 MD32_EN : 0
4961 00:59:05.288308 ===================================
4962 00:59:05.291733 [ANA_INIT] >>>>>>>>>>>>>>
4963 00:59:05.295180 <<<<<< [CONFIGURE PHASE]: ANA_TX
4964 00:59:05.298521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4965 00:59:05.301844 ===================================
4966 00:59:05.301941 data_rate = 1866,PCW = 0X8f00
4967 00:59:05.305217 ===================================
4968 00:59:05.308331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4969 00:59:05.314860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 00:59:05.321295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 00:59:05.325142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4972 00:59:05.328323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4973 00:59:05.332016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4974 00:59:05.334995 [ANA_INIT] flow start
4975 00:59:05.335102 [ANA_INIT] PLL >>>>>>>>
4976 00:59:05.338114 [ANA_INIT] PLL <<<<<<<<
4977 00:59:05.341829 [ANA_INIT] MIDPI >>>>>>>>
4978 00:59:05.345003 [ANA_INIT] MIDPI <<<<<<<<
4979 00:59:05.345079 [ANA_INIT] DLL >>>>>>>>
4980 00:59:05.348057 [ANA_INIT] flow end
4981 00:59:05.351732 ============ LP4 DIFF to SE enter ============
4982 00:59:05.355062 ============ LP4 DIFF to SE exit ============
4983 00:59:05.358293 [ANA_INIT] <<<<<<<<<<<<<
4984 00:59:05.361522 [Flow] Enable top DCM control >>>>>
4985 00:59:05.364839 [Flow] Enable top DCM control <<<<<
4986 00:59:05.368211 Enable DLL master slave shuffle
4987 00:59:05.374778 ==============================================================
4988 00:59:05.374871 Gating Mode config
4989 00:59:05.381441 ==============================================================
4990 00:59:05.381532 Config description:
4991 00:59:05.391657 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4992 00:59:05.398048 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4993 00:59:05.404592 SELPH_MODE 0: By rank 1: By Phase
4994 00:59:05.408004 ==============================================================
4995 00:59:05.411504 GAT_TRACK_EN = 1
4996 00:59:05.414829 RX_GATING_MODE = 2
4997 00:59:05.418102 RX_GATING_TRACK_MODE = 2
4998 00:59:05.420931 SELPH_MODE = 1
4999 00:59:05.424233 PICG_EARLY_EN = 1
5000 00:59:05.427666 VALID_LAT_VALUE = 1
5001 00:59:05.434391 ==============================================================
5002 00:59:05.437691 Enter into Gating configuration >>>>
5003 00:59:05.441201 Exit from Gating configuration <<<<
5004 00:59:05.441305 Enter into DVFS_PRE_config >>>>>
5005 00:59:05.454567 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5006 00:59:05.457742 Exit from DVFS_PRE_config <<<<<
5007 00:59:05.460996 Enter into PICG configuration >>>>
5008 00:59:05.464731 Exit from PICG configuration <<<<
5009 00:59:05.464817 [RX_INPUT] configuration >>>>>
5010 00:59:05.467942 [RX_INPUT] configuration <<<<<
5011 00:59:05.474437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5012 00:59:05.477760 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5013 00:59:05.484144 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5014 00:59:05.490852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5015 00:59:05.497931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 00:59:05.504683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 00:59:05.508009 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5018 00:59:05.511353 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5019 00:59:05.517526 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5020 00:59:05.520964 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5021 00:59:05.524482 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5022 00:59:05.527905 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 00:59:05.531384 ===================================
5024 00:59:05.534184 LPDDR4 DRAM CONFIGURATION
5025 00:59:05.537634 ===================================
5026 00:59:05.541097 EX_ROW_EN[0] = 0x0
5027 00:59:05.541204 EX_ROW_EN[1] = 0x0
5028 00:59:05.544639 LP4Y_EN = 0x0
5029 00:59:05.544738 WORK_FSP = 0x0
5030 00:59:05.547392 WL = 0x3
5031 00:59:05.547493 RL = 0x3
5032 00:59:05.550751 BL = 0x2
5033 00:59:05.550852 RPST = 0x0
5034 00:59:05.554645 RD_PRE = 0x0
5035 00:59:05.554754 WR_PRE = 0x1
5036 00:59:05.557750 WR_PST = 0x0
5037 00:59:05.557858 DBI_WR = 0x0
5038 00:59:05.560938 DBI_RD = 0x0
5039 00:59:05.561042 OTF = 0x1
5040 00:59:05.564288 ===================================
5041 00:59:05.570955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5042 00:59:05.574220 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5043 00:59:05.577383 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 00:59:05.581017 ===================================
5045 00:59:05.584017 LPDDR4 DRAM CONFIGURATION
5046 00:59:05.587485 ===================================
5047 00:59:05.590986 EX_ROW_EN[0] = 0x10
5048 00:59:05.591068 EX_ROW_EN[1] = 0x0
5049 00:59:05.594509 LP4Y_EN = 0x0
5050 00:59:05.594579 WORK_FSP = 0x0
5051 00:59:05.598043 WL = 0x3
5052 00:59:05.598155 RL = 0x3
5053 00:59:05.601121 BL = 0x2
5054 00:59:05.601232 RPST = 0x0
5055 00:59:05.604479 RD_PRE = 0x0
5056 00:59:05.604549 WR_PRE = 0x1
5057 00:59:05.608327 WR_PST = 0x0
5058 00:59:05.608411 DBI_WR = 0x0
5059 00:59:05.611050 DBI_RD = 0x0
5060 00:59:05.611121 OTF = 0x1
5061 00:59:05.614498 ===================================
5062 00:59:05.621351 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5063 00:59:05.625491 nWR fixed to 30
5064 00:59:05.628709 [ModeRegInit_LP4] CH0 RK0
5065 00:59:05.628801 [ModeRegInit_LP4] CH0 RK1
5066 00:59:05.631797 [ModeRegInit_LP4] CH1 RK0
5067 00:59:05.635364 [ModeRegInit_LP4] CH1 RK1
5068 00:59:05.635438 match AC timing 9
5069 00:59:05.642018 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5070 00:59:05.645422 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5071 00:59:05.648708 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5072 00:59:05.655534 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5073 00:59:05.658204 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5074 00:59:05.658313 ==
5075 00:59:05.661694 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 00:59:05.664943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 00:59:05.665053 ==
5078 00:59:05.671849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 00:59:05.678589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5080 00:59:05.681940 [CA 0] Center 37 (6~68) winsize 63
5081 00:59:05.685309 [CA 1] Center 37 (7~68) winsize 62
5082 00:59:05.688646 [CA 2] Center 34 (4~65) winsize 62
5083 00:59:05.691721 [CA 3] Center 33 (3~64) winsize 62
5084 00:59:05.694947 [CA 4] Center 33 (3~64) winsize 62
5085 00:59:05.698355 [CA 5] Center 32 (2~62) winsize 61
5086 00:59:05.698434
5087 00:59:05.701708 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5088 00:59:05.701786
5089 00:59:05.704962 [CATrainingPosCal] consider 1 rank data
5090 00:59:05.708379 u2DelayCellTimex100 = 270/100 ps
5091 00:59:05.711595 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5092 00:59:05.715133 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5093 00:59:05.718272 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5094 00:59:05.721536 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5095 00:59:05.724742 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5096 00:59:05.728558 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5097 00:59:05.731565
5098 00:59:05.734693 CA PerBit enable=1, Macro0, CA PI delay=32
5099 00:59:05.734789
5100 00:59:05.738331 [CBTSetCACLKResult] CA Dly = 32
5101 00:59:05.738415 CS Dly: 5 (0~36)
5102 00:59:05.738477 ==
5103 00:59:05.741329 Dram Type= 6, Freq= 0, CH_0, rank 1
5104 00:59:05.744783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 00:59:05.744852 ==
5106 00:59:05.751201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 00:59:05.757927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5108 00:59:05.761359 [CA 0] Center 37 (6~68) winsize 63
5109 00:59:05.764690 [CA 1] Center 37 (6~68) winsize 63
5110 00:59:05.768061 [CA 2] Center 34 (4~65) winsize 62
5111 00:59:05.771393 [CA 3] Center 34 (3~65) winsize 63
5112 00:59:05.774484 [CA 4] Center 32 (2~63) winsize 62
5113 00:59:05.778165 [CA 5] Center 32 (2~62) winsize 61
5114 00:59:05.778278
5115 00:59:05.781452 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5116 00:59:05.781556
5117 00:59:05.784217 [CATrainingPosCal] consider 2 rank data
5118 00:59:05.787631 u2DelayCellTimex100 = 270/100 ps
5119 00:59:05.791019 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5120 00:59:05.794340 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5121 00:59:05.798072 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5122 00:59:05.800992 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5123 00:59:05.807652 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5124 00:59:05.811003 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5125 00:59:05.811086
5126 00:59:05.814343 CA PerBit enable=1, Macro0, CA PI delay=32
5127 00:59:05.814451
5128 00:59:05.817600 [CBTSetCACLKResult] CA Dly = 32
5129 00:59:05.817672 CS Dly: 5 (0~37)
5130 00:59:05.817737
5131 00:59:05.821491 ----->DramcWriteLeveling(PI) begin...
5132 00:59:05.821593 ==
5133 00:59:05.824618 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 00:59:05.831190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 00:59:05.831312 ==
5136 00:59:05.834584 Write leveling (Byte 0): 32 => 32
5137 00:59:05.834669 Write leveling (Byte 1): 28 => 28
5138 00:59:05.838024 DramcWriteLeveling(PI) end<-----
5139 00:59:05.838105
5140 00:59:05.838177 ==
5141 00:59:05.841188 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 00:59:05.847974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 00:59:05.848096 ==
5144 00:59:05.851267 [Gating] SW mode calibration
5145 00:59:05.857605 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5146 00:59:05.860936 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5147 00:59:05.867739 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5148 00:59:05.871018 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 00:59:05.874561 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 00:59:05.881206 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 00:59:05.884329 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 00:59:05.887436 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 00:59:05.891155 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
5154 00:59:05.897920 0 14 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
5155 00:59:05.901352 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5156 00:59:05.904753 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 00:59:05.910965 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 00:59:05.914553 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 00:59:05.917929 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 00:59:05.924557 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 00:59:05.927670 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5162 00:59:05.931135 0 15 28 | B1->B0 | 2727 3838 | 1 1 | (0 0) (1 1)
5163 00:59:05.937949 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5164 00:59:05.941109 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 00:59:05.944459 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 00:59:05.950963 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 00:59:05.954363 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 00:59:05.957962 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 00:59:05.963994 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5170 00:59:05.967335 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5171 00:59:05.970698 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 00:59:05.977395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 00:59:05.981174 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 00:59:05.983967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 00:59:05.991073 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 00:59:05.994250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 00:59:05.997949 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 00:59:06.000811 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 00:59:06.007520 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 00:59:06.010912 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 00:59:06.014136 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 00:59:06.020629 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 00:59:06.024361 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 00:59:06.027436 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 00:59:06.034193 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5186 00:59:06.037442 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5187 00:59:06.040725 Total UI for P1: 0, mck2ui 16
5188 00:59:06.043921 best dqsien dly found for B0: ( 1, 2, 24)
5189 00:59:06.047728 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5190 00:59:06.054207 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 00:59:06.054289 Total UI for P1: 0, mck2ui 16
5192 00:59:06.060859 best dqsien dly found for B1: ( 1, 3, 0)
5193 00:59:06.064200 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5194 00:59:06.067597 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5195 00:59:06.067666
5196 00:59:06.070324 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5197 00:59:06.073771 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5198 00:59:06.077153 [Gating] SW calibration Done
5199 00:59:06.077250 ==
5200 00:59:06.080562 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 00:59:06.083958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 00:59:06.084025 ==
5203 00:59:06.087268 RX Vref Scan: 0
5204 00:59:06.087334
5205 00:59:06.087391 RX Vref 0 -> 0, step: 1
5206 00:59:06.087443
5207 00:59:06.090443 RX Delay -80 -> 252, step: 8
5208 00:59:06.094207 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5209 00:59:06.100884 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5210 00:59:06.103698 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5211 00:59:06.107411 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5212 00:59:06.110342 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5213 00:59:06.114047 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5214 00:59:06.117027 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5215 00:59:06.124033 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5216 00:59:06.127449 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5217 00:59:06.130760 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5218 00:59:06.134020 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5219 00:59:06.137280 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5220 00:59:06.140403 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5221 00:59:06.147223 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5222 00:59:06.150472 iDelay=200, Bit 14, Center 103 (16 ~ 191) 176
5223 00:59:06.153566 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5224 00:59:06.153668 ==
5225 00:59:06.157381 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 00:59:06.160513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 00:59:06.160591 ==
5228 00:59:06.163705 DQS Delay:
5229 00:59:06.163782 DQS0 = 0, DQS1 = 0
5230 00:59:06.167101 DQM Delay:
5231 00:59:06.167201 DQM0 = 103, DQM1 = 94
5232 00:59:06.167287 DQ Delay:
5233 00:59:06.170450 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5234 00:59:06.173754 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5235 00:59:06.177212 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5236 00:59:06.184021 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5237 00:59:06.184100
5238 00:59:06.184161
5239 00:59:06.184215 ==
5240 00:59:06.186755 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 00:59:06.190164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 00:59:06.190242 ==
5243 00:59:06.190302
5244 00:59:06.190357
5245 00:59:06.193486 TX Vref Scan disable
5246 00:59:06.193569 == TX Byte 0 ==
5247 00:59:06.200233 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5248 00:59:06.203523 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5249 00:59:06.203603 == TX Byte 1 ==
5250 00:59:06.210136 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5251 00:59:06.213444 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5252 00:59:06.213523 ==
5253 00:59:06.216869 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 00:59:06.220210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 00:59:06.220290 ==
5256 00:59:06.220350
5257 00:59:06.220405
5258 00:59:06.223409 TX Vref Scan disable
5259 00:59:06.226535 == TX Byte 0 ==
5260 00:59:06.230056 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5261 00:59:06.233556 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5262 00:59:06.236866 == TX Byte 1 ==
5263 00:59:06.240280 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5264 00:59:06.243289 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5265 00:59:06.243368
5266 00:59:06.246698 [DATLAT]
5267 00:59:06.246776 Freq=933, CH0 RK0
5268 00:59:06.246852
5269 00:59:06.250094 DATLAT Default: 0xd
5270 00:59:06.250172 0, 0xFFFF, sum = 0
5271 00:59:06.253428 1, 0xFFFF, sum = 0
5272 00:59:06.253507 2, 0xFFFF, sum = 0
5273 00:59:06.256863 3, 0xFFFF, sum = 0
5274 00:59:06.256980 4, 0xFFFF, sum = 0
5275 00:59:06.260482 5, 0xFFFF, sum = 0
5276 00:59:06.260562 6, 0xFFFF, sum = 0
5277 00:59:06.263332 7, 0xFFFF, sum = 0
5278 00:59:06.263411 8, 0xFFFF, sum = 0
5279 00:59:06.266800 9, 0xFFFF, sum = 0
5280 00:59:06.266884 10, 0x0, sum = 1
5281 00:59:06.270214 11, 0x0, sum = 2
5282 00:59:06.270294 12, 0x0, sum = 3
5283 00:59:06.273617 13, 0x0, sum = 4
5284 00:59:06.273695 best_step = 11
5285 00:59:06.273755
5286 00:59:06.273810 ==
5287 00:59:06.276599 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 00:59:06.283358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 00:59:06.283444 ==
5290 00:59:06.283504 RX Vref Scan: 1
5291 00:59:06.283559
5292 00:59:06.286676 RX Vref 0 -> 0, step: 1
5293 00:59:06.286754
5294 00:59:06.290107 RX Delay -53 -> 252, step: 4
5295 00:59:06.290184
5296 00:59:06.293473 Set Vref, RX VrefLevel [Byte0]: 56
5297 00:59:06.296843 [Byte1]: 50
5298 00:59:06.296921
5299 00:59:06.300164 Final RX Vref Byte 0 = 56 to rank0
5300 00:59:06.303488 Final RX Vref Byte 1 = 50 to rank0
5301 00:59:06.306786 Final RX Vref Byte 0 = 56 to rank1
5302 00:59:06.310048 Final RX Vref Byte 1 = 50 to rank1==
5303 00:59:06.313440 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 00:59:06.316727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 00:59:06.316825 ==
5306 00:59:06.320159 DQS Delay:
5307 00:59:06.320256 DQS0 = 0, DQS1 = 0
5308 00:59:06.323494 DQM Delay:
5309 00:59:06.323587 DQM0 = 104, DQM1 = 96
5310 00:59:06.323672 DQ Delay:
5311 00:59:06.326779 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5312 00:59:06.329612 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5313 00:59:06.333050 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5314 00:59:06.339777 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5315 00:59:06.339854
5316 00:59:06.339915
5317 00:59:06.346445 [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5318 00:59:06.349568 CH0 RK0: MR19=505, MR18=342C
5319 00:59:06.356543 CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44
5320 00:59:06.356642
5321 00:59:06.359662 ----->DramcWriteLeveling(PI) begin...
5322 00:59:06.359757 ==
5323 00:59:06.362664 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 00:59:06.366284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 00:59:06.366381 ==
5326 00:59:06.369251 Write leveling (Byte 0): 33 => 33
5327 00:59:06.372829 Write leveling (Byte 1): 33 => 33
5328 00:59:06.376400 DramcWriteLeveling(PI) end<-----
5329 00:59:06.376480
5330 00:59:06.376541 ==
5331 00:59:06.379227 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 00:59:06.382745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 00:59:06.382816 ==
5334 00:59:06.386227 [Gating] SW mode calibration
5335 00:59:06.392645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5336 00:59:06.399791 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5337 00:59:06.402546 0 14 0 | B1->B0 | 3232 3333 | 1 1 | (0 0) (1 1)
5338 00:59:06.409240 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 00:59:06.412672 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 00:59:06.416082 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 00:59:06.422691 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 00:59:06.426084 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 00:59:06.429449 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 00:59:06.432948 0 14 28 | B1->B0 | 2e2e 2d2d | 1 0 | (1 1) (0 0)
5345 00:59:06.439604 0 15 0 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
5346 00:59:06.442364 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 00:59:06.446258 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 00:59:06.452436 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 00:59:06.455694 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 00:59:06.458997 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 00:59:06.465806 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5352 00:59:06.469004 0 15 28 | B1->B0 | 3d3d 3838 | 1 1 | (1 1) (0 0)
5353 00:59:06.472218 1 0 0 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
5354 00:59:06.479412 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 00:59:06.482718 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 00:59:06.485932 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 00:59:06.492278 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 00:59:06.496019 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 00:59:06.499202 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 00:59:06.505842 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5361 00:59:06.509257 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5362 00:59:06.512183 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 00:59:06.519245 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 00:59:06.522715 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 00:59:06.525386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 00:59:06.532060 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 00:59:06.535489 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 00:59:06.538913 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 00:59:06.545642 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 00:59:06.549163 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 00:59:06.552458 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 00:59:06.559238 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 00:59:06.562442 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 00:59:06.565631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 00:59:06.572275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 00:59:06.576859 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5377 00:59:06.578774 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 00:59:06.581996 Total UI for P1: 0, mck2ui 16
5379 00:59:06.585224 best dqsien dly found for B0: ( 1, 2, 28)
5380 00:59:06.588541 Total UI for P1: 0, mck2ui 16
5381 00:59:06.591976 best dqsien dly found for B1: ( 1, 2, 30)
5382 00:59:06.595381 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5383 00:59:06.598524 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5384 00:59:06.598600
5385 00:59:06.601745 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5386 00:59:06.608424 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5387 00:59:06.608504 [Gating] SW calibration Done
5388 00:59:06.608584 ==
5389 00:59:06.611803 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 00:59:06.618807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 00:59:06.618892 ==
5392 00:59:06.618953 RX Vref Scan: 0
5393 00:59:06.619009
5394 00:59:06.622100 RX Vref 0 -> 0, step: 1
5395 00:59:06.622171
5396 00:59:06.625164 RX Delay -80 -> 252, step: 8
5397 00:59:06.628524 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5398 00:59:06.632260 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5399 00:59:06.635349 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5400 00:59:06.638612 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5401 00:59:06.645360 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5402 00:59:06.648822 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5403 00:59:06.652113 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5404 00:59:06.655412 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5405 00:59:06.658597 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5406 00:59:06.662054 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5407 00:59:06.668666 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5408 00:59:06.671961 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5409 00:59:06.675294 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5410 00:59:06.678495 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5411 00:59:06.681823 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5412 00:59:06.685113 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5413 00:59:06.688347 ==
5414 00:59:06.692072 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 00:59:06.695354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 00:59:06.695439 ==
5417 00:59:06.695500 DQS Delay:
5418 00:59:06.698716 DQS0 = 0, DQS1 = 0
5419 00:59:06.698788 DQM Delay:
5420 00:59:06.702015 DQM0 = 104, DQM1 = 94
5421 00:59:06.702090 DQ Delay:
5422 00:59:06.705329 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5423 00:59:06.708497 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5424 00:59:06.711839 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5425 00:59:06.715130 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5426 00:59:06.715217
5427 00:59:06.715288
5428 00:59:06.715344 ==
5429 00:59:06.718531 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 00:59:06.721954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 00:59:06.722057 ==
5432 00:59:06.725353
5433 00:59:06.725445
5434 00:59:06.725533 TX Vref Scan disable
5435 00:59:06.728739 == TX Byte 0 ==
5436 00:59:06.732022 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5437 00:59:06.735092 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5438 00:59:06.738683 == TX Byte 1 ==
5439 00:59:06.741819 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5440 00:59:06.744832 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5441 00:59:06.744928 ==
5442 00:59:06.748510 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 00:59:06.755332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 00:59:06.755448 ==
5445 00:59:06.755538
5446 00:59:06.755622
5447 00:59:06.755703 TX Vref Scan disable
5448 00:59:06.759386 == TX Byte 0 ==
5449 00:59:06.762689 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5450 00:59:06.766125 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5451 00:59:06.769498 == TX Byte 1 ==
5452 00:59:06.772685 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5453 00:59:06.779234 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5454 00:59:06.779338
5455 00:59:06.779399 [DATLAT]
5456 00:59:06.779459 Freq=933, CH0 RK1
5457 00:59:06.779514
5458 00:59:06.782476 DATLAT Default: 0xb
5459 00:59:06.782558 0, 0xFFFF, sum = 0
5460 00:59:06.785933 1, 0xFFFF, sum = 0
5461 00:59:06.786002 2, 0xFFFF, sum = 0
5462 00:59:06.789253 3, 0xFFFF, sum = 0
5463 00:59:06.792625 4, 0xFFFF, sum = 0
5464 00:59:06.792726 5, 0xFFFF, sum = 0
5465 00:59:06.795800 6, 0xFFFF, sum = 0
5466 00:59:06.795905 7, 0xFFFF, sum = 0
5467 00:59:06.798965 8, 0xFFFF, sum = 0
5468 00:59:06.799065 9, 0xFFFF, sum = 0
5469 00:59:06.802923 10, 0x0, sum = 1
5470 00:59:06.803025 11, 0x0, sum = 2
5471 00:59:06.803119 12, 0x0, sum = 3
5472 00:59:06.805974 13, 0x0, sum = 4
5473 00:59:06.806073 best_step = 11
5474 00:59:06.806161
5475 00:59:06.809436 ==
5476 00:59:06.809532 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 00:59:06.816042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 00:59:06.816148 ==
5479 00:59:06.816241 RX Vref Scan: 0
5480 00:59:06.816323
5481 00:59:06.819395 RX Vref 0 -> 0, step: 1
5482 00:59:06.819497
5483 00:59:06.822656 RX Delay -45 -> 252, step: 4
5484 00:59:06.825956 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5485 00:59:06.832505 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5486 00:59:06.835945 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5487 00:59:06.839272 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5488 00:59:06.842592 iDelay=199, Bit 4, Center 108 (23 ~ 194) 172
5489 00:59:06.845962 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5490 00:59:06.852553 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5491 00:59:06.855641 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5492 00:59:06.858775 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5493 00:59:06.862358 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5494 00:59:06.865511 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5495 00:59:06.869017 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5496 00:59:06.875934 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5497 00:59:06.879007 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5498 00:59:06.882216 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5499 00:59:06.885860 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5500 00:59:06.885950 ==
5501 00:59:06.889074 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 00:59:06.895711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 00:59:06.895838 ==
5504 00:59:06.895905 DQS Delay:
5505 00:59:06.895961 DQS0 = 0, DQS1 = 0
5506 00:59:06.899197 DQM Delay:
5507 00:59:06.899269 DQM0 = 105, DQM1 = 93
5508 00:59:06.902524 DQ Delay:
5509 00:59:06.905746 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5510 00:59:06.908995 DQ4 =108, DQ5 =98, DQ6 =110, DQ7 =112
5511 00:59:06.912318 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =86
5512 00:59:06.915639 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5513 00:59:06.915724
5514 00:59:06.915781
5515 00:59:06.922181 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5516 00:59:06.925423 CH0 RK1: MR19=505, MR18=2A03
5517 00:59:06.932048 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5518 00:59:06.935859 [RxdqsGatingPostProcess] freq 933
5519 00:59:06.942098 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 00:59:06.942223 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 00:59:06.945433 best DQS1 dly(2T, 0.5T) = (0, 11)
5522 00:59:06.948889 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 00:59:06.952178 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5524 00:59:06.955509 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 00:59:06.958898 best DQS1 dly(2T, 0.5T) = (0, 10)
5526 00:59:06.962279 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 00:59:06.965414 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5528 00:59:06.968554 Pre-setting of DQS Precalculation
5529 00:59:06.971947 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 00:59:06.975193 ==
5531 00:59:06.978955 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 00:59:06.981844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 00:59:06.981940 ==
5534 00:59:06.988512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 00:59:06.991631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5536 00:59:06.995819 [CA 0] Center 36 (6~67) winsize 62
5537 00:59:06.999244 [CA 1] Center 36 (6~67) winsize 62
5538 00:59:07.002576 [CA 2] Center 34 (4~65) winsize 62
5539 00:59:07.005564 [CA 3] Center 34 (4~65) winsize 62
5540 00:59:07.008810 [CA 4] Center 34 (4~64) winsize 61
5541 00:59:07.012609 [CA 5] Center 33 (3~64) winsize 62
5542 00:59:07.012706
5543 00:59:07.015679 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5544 00:59:07.015783
5545 00:59:07.018835 [CATrainingPosCal] consider 1 rank data
5546 00:59:07.022299 u2DelayCellTimex100 = 270/100 ps
5547 00:59:07.025536 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 00:59:07.028797 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 00:59:07.035662 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5550 00:59:07.038815 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 00:59:07.042047 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 00:59:07.045490 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 00:59:07.045610
5554 00:59:07.048946 CA PerBit enable=1, Macro0, CA PI delay=33
5555 00:59:07.049061
5556 00:59:07.052262 [CBTSetCACLKResult] CA Dly = 33
5557 00:59:07.052380 CS Dly: 6 (0~37)
5558 00:59:07.055651 ==
5559 00:59:07.055740 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 00:59:07.062479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 00:59:07.062558 ==
5562 00:59:07.065742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 00:59:07.072307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5564 00:59:07.075932 [CA 0] Center 37 (6~68) winsize 63
5565 00:59:07.078693 [CA 1] Center 37 (6~68) winsize 63
5566 00:59:07.082148 [CA 2] Center 35 (5~66) winsize 62
5567 00:59:07.085545 [CA 3] Center 34 (4~65) winsize 62
5568 00:59:07.089014 [CA 4] Center 34 (4~65) winsize 62
5569 00:59:07.092128 [CA 5] Center 34 (4~64) winsize 61
5570 00:59:07.092240
5571 00:59:07.095459 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5572 00:59:07.095556
5573 00:59:07.099050 [CATrainingPosCal] consider 2 rank data
5574 00:59:07.102178 u2DelayCellTimex100 = 270/100 ps
5575 00:59:07.105444 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5576 00:59:07.112173 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5577 00:59:07.115332 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5578 00:59:07.118762 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5579 00:59:07.122253 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5580 00:59:07.125184 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 00:59:07.125258
5582 00:59:07.128595 CA PerBit enable=1, Macro0, CA PI delay=34
5583 00:59:07.128668
5584 00:59:07.132297 [CBTSetCACLKResult] CA Dly = 34
5585 00:59:07.132369 CS Dly: 7 (0~40)
5586 00:59:07.132425
5587 00:59:07.135793 ----->DramcWriteLeveling(PI) begin...
5588 00:59:07.138939 ==
5589 00:59:07.142324 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 00:59:07.145591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 00:59:07.145693 ==
5592 00:59:07.149001 Write leveling (Byte 0): 26 => 26
5593 00:59:07.152315 Write leveling (Byte 1): 27 => 27
5594 00:59:07.155482 DramcWriteLeveling(PI) end<-----
5595 00:59:07.155575
5596 00:59:07.155663 ==
5597 00:59:07.158750 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 00:59:07.162089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 00:59:07.162191 ==
5600 00:59:07.165481 [Gating] SW mode calibration
5601 00:59:07.172097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 00:59:07.178628 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 00:59:07.181872 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 00:59:07.185251 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 00:59:07.192150 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 00:59:07.195449 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 00:59:07.198734 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 00:59:07.202035 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 00:59:07.208363 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5610 00:59:07.212103 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5611 00:59:07.215226 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 00:59:07.221963 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 00:59:07.225035 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 00:59:07.228314 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 00:59:07.235383 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 00:59:07.238603 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 00:59:07.241661 0 15 24 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5618 00:59:07.248881 0 15 28 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5619 00:59:07.251618 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 00:59:07.255540 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 00:59:07.261663 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 00:59:07.265261 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 00:59:07.268371 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 00:59:07.275045 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 00:59:07.278476 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5626 00:59:07.281761 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 00:59:07.288305 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 00:59:07.291732 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 00:59:07.295120 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 00:59:07.301920 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 00:59:07.305343 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 00:59:07.308691 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 00:59:07.315215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 00:59:07.318494 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 00:59:07.321740 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 00:59:07.324956 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 00:59:07.331657 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 00:59:07.334929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 00:59:07.338128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 00:59:07.344839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 00:59:07.348213 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5642 00:59:07.351620 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5643 00:59:07.358219 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 00:59:07.361831 Total UI for P1: 0, mck2ui 16
5645 00:59:07.364726 best dqsien dly found for B0: ( 1, 2, 28)
5646 00:59:07.364826 Total UI for P1: 0, mck2ui 16
5647 00:59:07.371739 best dqsien dly found for B1: ( 1, 2, 26)
5648 00:59:07.374771 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5649 00:59:07.378408 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5650 00:59:07.378482
5651 00:59:07.381398 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5652 00:59:07.385035 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5653 00:59:07.388272 [Gating] SW calibration Done
5654 00:59:07.388344 ==
5655 00:59:07.391614 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 00:59:07.394860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 00:59:07.394959 ==
5658 00:59:07.398291 RX Vref Scan: 0
5659 00:59:07.398360
5660 00:59:07.398416 RX Vref 0 -> 0, step: 1
5661 00:59:07.398469
5662 00:59:07.401596 RX Delay -80 -> 252, step: 8
5663 00:59:07.405069 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5664 00:59:07.411687 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5665 00:59:07.415034 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5666 00:59:07.418324 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5667 00:59:07.421624 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5668 00:59:07.424735 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5669 00:59:07.428022 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5670 00:59:07.435093 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5671 00:59:07.438163 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5672 00:59:07.441481 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5673 00:59:07.445098 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5674 00:59:07.448381 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5675 00:59:07.451687 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5676 00:59:07.458448 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5677 00:59:07.461862 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5678 00:59:07.465264 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5679 00:59:07.465359 ==
5680 00:59:07.468016 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 00:59:07.471923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 00:59:07.472026 ==
5683 00:59:07.475075 DQS Delay:
5684 00:59:07.475167 DQS0 = 0, DQS1 = 0
5685 00:59:07.478232 DQM Delay:
5686 00:59:07.478323 DQM0 = 102, DQM1 = 98
5687 00:59:07.478401 DQ Delay:
5688 00:59:07.481791 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5689 00:59:07.484961 DQ4 =99, DQ5 =115, DQ6 =107, DQ7 =103
5690 00:59:07.488230 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5691 00:59:07.491348 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5692 00:59:07.491443
5693 00:59:07.495018
5694 00:59:07.495092 ==
5695 00:59:07.498189 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 00:59:07.501555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 00:59:07.501627 ==
5698 00:59:07.501686
5699 00:59:07.501741
5700 00:59:07.504969 TX Vref Scan disable
5701 00:59:07.505065 == TX Byte 0 ==
5702 00:59:07.511431 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5703 00:59:07.514769 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5704 00:59:07.514842 == TX Byte 1 ==
5705 00:59:07.521048 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5706 00:59:07.525049 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5707 00:59:07.525121 ==
5708 00:59:07.528225 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 00:59:07.531311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 00:59:07.531382 ==
5711 00:59:07.531439
5712 00:59:07.531494
5713 00:59:07.534471 TX Vref Scan disable
5714 00:59:07.537783 == TX Byte 0 ==
5715 00:59:07.541098 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5716 00:59:07.544315 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5717 00:59:07.547884 == TX Byte 1 ==
5718 00:59:07.551013 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 00:59:07.554190 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 00:59:07.554274
5721 00:59:07.558214 [DATLAT]
5722 00:59:07.558311 Freq=933, CH1 RK0
5723 00:59:07.558396
5724 00:59:07.560913 DATLAT Default: 0xd
5725 00:59:07.561000 0, 0xFFFF, sum = 0
5726 00:59:07.564249 1, 0xFFFF, sum = 0
5727 00:59:07.564346 2, 0xFFFF, sum = 0
5728 00:59:07.567747 3, 0xFFFF, sum = 0
5729 00:59:07.567840 4, 0xFFFF, sum = 0
5730 00:59:07.571200 5, 0xFFFF, sum = 0
5731 00:59:07.571290 6, 0xFFFF, sum = 0
5732 00:59:07.574519 7, 0xFFFF, sum = 0
5733 00:59:07.574608 8, 0xFFFF, sum = 0
5734 00:59:07.577889 9, 0xFFFF, sum = 0
5735 00:59:07.577957 10, 0x0, sum = 1
5736 00:59:07.581235 11, 0x0, sum = 2
5737 00:59:07.581333 12, 0x0, sum = 3
5738 00:59:07.584445 13, 0x0, sum = 4
5739 00:59:07.584540 best_step = 11
5740 00:59:07.584627
5741 00:59:07.584707 ==
5742 00:59:07.587710 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 00:59:07.594290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 00:59:07.594384 ==
5745 00:59:07.594463 RX Vref Scan: 1
5746 00:59:07.594521
5747 00:59:07.597321 RX Vref 0 -> 0, step: 1
5748 00:59:07.597389
5749 00:59:07.601114 RX Delay -45 -> 252, step: 4
5750 00:59:07.601210
5751 00:59:07.604498 Set Vref, RX VrefLevel [Byte0]: 55
5752 00:59:07.607775 [Byte1]: 48
5753 00:59:07.607876
5754 00:59:07.610982 Final RX Vref Byte 0 = 55 to rank0
5755 00:59:07.614729 Final RX Vref Byte 1 = 48 to rank0
5756 00:59:07.617562 Final RX Vref Byte 0 = 55 to rank1
5757 00:59:07.620969 Final RX Vref Byte 1 = 48 to rank1==
5758 00:59:07.624663 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 00:59:07.627453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 00:59:07.627560 ==
5761 00:59:07.630804 DQS Delay:
5762 00:59:07.630872 DQS0 = 0, DQS1 = 0
5763 00:59:07.630930 DQM Delay:
5764 00:59:07.634265 DQM0 = 103, DQM1 = 99
5765 00:59:07.634360 DQ Delay:
5766 00:59:07.637573 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =100
5767 00:59:07.640743 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5768 00:59:07.644290 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5769 00:59:07.647748 DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =110
5770 00:59:07.650979
5771 00:59:07.651072
5772 00:59:07.657426 [DQSOSCAuto] RK0, (LSB)MR18= 0x182f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5773 00:59:07.660521 CH1 RK0: MR19=505, MR18=182F
5774 00:59:07.667690 CH1_RK0: MR19=0x505, MR18=0x182F, DQSOSC=407, MR23=63, INC=65, DEC=43
5775 00:59:07.667800
5776 00:59:07.670487 ----->DramcWriteLeveling(PI) begin...
5777 00:59:07.670564 ==
5778 00:59:07.673832 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 00:59:07.677266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 00:59:07.677358 ==
5781 00:59:07.680604 Write leveling (Byte 0): 27 => 27
5782 00:59:07.684074 Write leveling (Byte 1): 26 => 26
5783 00:59:07.687550 DramcWriteLeveling(PI) end<-----
5784 00:59:07.687647
5785 00:59:07.687733 ==
5786 00:59:07.690828 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 00:59:07.694208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 00:59:07.694309 ==
5789 00:59:07.697414 [Gating] SW mode calibration
5790 00:59:07.703721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5791 00:59:07.710079 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5792 00:59:07.713557 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 00:59:07.717313 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 00:59:07.723378 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 00:59:07.726617 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 00:59:07.730221 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 00:59:07.736644 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5798 00:59:07.740433 0 14 24 | B1->B0 | 2d2d 3131 | 0 0 | (0 1) (0 1)
5799 00:59:07.743802 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
5800 00:59:07.750235 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 00:59:07.753345 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 00:59:07.756985 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 00:59:07.763266 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 00:59:07.767005 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 00:59:07.770306 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 00:59:07.776742 0 15 24 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
5807 00:59:07.780013 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5808 00:59:07.783463 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 00:59:07.790255 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 00:59:07.792970 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 00:59:07.796431 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 00:59:07.802999 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 00:59:07.806351 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 00:59:07.809715 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5815 00:59:07.816322 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 00:59:07.819518 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 00:59:07.823112 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 00:59:07.829892 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 00:59:07.833020 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 00:59:07.836465 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 00:59:07.843123 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 00:59:07.846632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 00:59:07.850036 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 00:59:07.853185 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 00:59:07.859762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 00:59:07.863066 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 00:59:07.866889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 00:59:07.872935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 00:59:07.876758 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 00:59:07.880071 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5831 00:59:07.886935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 00:59:07.887091 Total UI for P1: 0, mck2ui 16
5833 00:59:07.893151 best dqsien dly found for B0: ( 1, 2, 26)
5834 00:59:07.893289 Total UI for P1: 0, mck2ui 16
5835 00:59:07.899973 best dqsien dly found for B1: ( 1, 2, 24)
5836 00:59:07.903400 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5837 00:59:07.906861 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5838 00:59:07.906950
5839 00:59:07.909581 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5840 00:59:07.913066 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5841 00:59:07.916372 [Gating] SW calibration Done
5842 00:59:07.916441 ==
5843 00:59:07.919661 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 00:59:07.923005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 00:59:07.923079 ==
5846 00:59:07.926354 RX Vref Scan: 0
5847 00:59:07.926424
5848 00:59:07.926480 RX Vref 0 -> 0, step: 1
5849 00:59:07.926534
5850 00:59:07.929600 RX Delay -80 -> 252, step: 8
5851 00:59:07.932947 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5852 00:59:07.939708 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5853 00:59:07.943241 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5854 00:59:07.946367 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5855 00:59:07.949734 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5856 00:59:07.953068 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5857 00:59:07.956232 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5858 00:59:07.962813 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5859 00:59:07.966216 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5860 00:59:07.969839 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5861 00:59:07.972698 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5862 00:59:07.976216 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5863 00:59:07.979245 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5864 00:59:07.985848 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5865 00:59:07.989599 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5866 00:59:07.992747 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5867 00:59:07.992825 ==
5868 00:59:07.995996 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 00:59:07.999415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 00:59:07.999495 ==
5871 00:59:08.002769 DQS Delay:
5872 00:59:08.002848 DQS0 = 0, DQS1 = 0
5873 00:59:08.006255 DQM Delay:
5874 00:59:08.006355 DQM0 = 101, DQM1 = 98
5875 00:59:08.006450 DQ Delay:
5876 00:59:08.009543 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5877 00:59:08.012995 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5878 00:59:08.015719 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5879 00:59:08.022421 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5880 00:59:08.022506
5881 00:59:08.022565
5882 00:59:08.022620 ==
5883 00:59:08.025800 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 00:59:08.029066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 00:59:08.029157 ==
5886 00:59:08.029239
5887 00:59:08.029325
5888 00:59:08.032969 TX Vref Scan disable
5889 00:59:08.033056 == TX Byte 0 ==
5890 00:59:08.039617 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5891 00:59:08.042920 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5892 00:59:08.042996 == TX Byte 1 ==
5893 00:59:08.049086 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5894 00:59:08.052994 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5895 00:59:08.053073 ==
5896 00:59:08.056194 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 00:59:08.058936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 00:59:08.059009 ==
5899 00:59:08.059084
5900 00:59:08.059148
5901 00:59:08.062345 TX Vref Scan disable
5902 00:59:08.065755 == TX Byte 0 ==
5903 00:59:08.069041 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5904 00:59:08.072128 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5905 00:59:08.075742 == TX Byte 1 ==
5906 00:59:08.079365 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5907 00:59:08.082413 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5908 00:59:08.082487
5909 00:59:08.085911 [DATLAT]
5910 00:59:08.085990 Freq=933, CH1 RK1
5911 00:59:08.086064
5912 00:59:08.088877 DATLAT Default: 0xb
5913 00:59:08.088949 0, 0xFFFF, sum = 0
5914 00:59:08.092431 1, 0xFFFF, sum = 0
5915 00:59:08.092512 2, 0xFFFF, sum = 0
5916 00:59:08.095305 3, 0xFFFF, sum = 0
5917 00:59:08.095389 4, 0xFFFF, sum = 0
5918 00:59:08.098694 5, 0xFFFF, sum = 0
5919 00:59:08.098802 6, 0xFFFF, sum = 0
5920 00:59:08.102358 7, 0xFFFF, sum = 0
5921 00:59:08.102439 8, 0xFFFF, sum = 0
5922 00:59:08.105502 9, 0xFFFF, sum = 0
5923 00:59:08.105613 10, 0x0, sum = 1
5924 00:59:08.108998 11, 0x0, sum = 2
5925 00:59:08.109076 12, 0x0, sum = 3
5926 00:59:08.112046 13, 0x0, sum = 4
5927 00:59:08.112117 best_step = 11
5928 00:59:08.112174
5929 00:59:08.112228 ==
5930 00:59:08.115380 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 00:59:08.122099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 00:59:08.122173 ==
5933 00:59:08.122232 RX Vref Scan: 0
5934 00:59:08.122288
5935 00:59:08.125423 RX Vref 0 -> 0, step: 1
5936 00:59:08.125517
5937 00:59:08.128837 RX Delay -45 -> 252, step: 4
5938 00:59:08.132360 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5939 00:59:08.139072 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5940 00:59:08.142187 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5941 00:59:08.145501 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5942 00:59:08.148903 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5943 00:59:08.152266 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5944 00:59:08.158487 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5945 00:59:08.162202 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5946 00:59:08.165436 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5947 00:59:08.168628 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5948 00:59:08.172110 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5949 00:59:08.175467 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5950 00:59:08.182056 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5951 00:59:08.185228 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5952 00:59:08.188518 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5953 00:59:08.191747 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5954 00:59:08.191824 ==
5955 00:59:08.195314 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 00:59:08.201617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 00:59:08.201720 ==
5958 00:59:08.201797 DQS Delay:
5959 00:59:08.201854 DQS0 = 0, DQS1 = 0
5960 00:59:08.205318 DQM Delay:
5961 00:59:08.205419 DQM0 = 104, DQM1 = 99
5962 00:59:08.208342 DQ Delay:
5963 00:59:08.212001 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5964 00:59:08.215009 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5965 00:59:08.218742 DQ8 =92, DQ9 =88, DQ10 =98, DQ11 =94
5966 00:59:08.221949 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5967 00:59:08.222027
5968 00:59:08.222086
5969 00:59:08.228691 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5970 00:59:08.232110 CH1 RK1: MR19=505, MR18=2E01
5971 00:59:08.238222 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5972 00:59:08.241510 [RxdqsGatingPostProcess] freq 933
5973 00:59:08.248708 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5974 00:59:08.251855 best DQS0 dly(2T, 0.5T) = (0, 10)
5975 00:59:08.251959 best DQS1 dly(2T, 0.5T) = (0, 10)
5976 00:59:08.255237 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5977 00:59:08.258653 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5978 00:59:08.261967 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 00:59:08.265264 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 00:59:08.268335 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 00:59:08.271321 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 00:59:08.275204 Pre-setting of DQS Precalculation
5983 00:59:08.281260 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5984 00:59:08.288044 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5985 00:59:08.294482 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5986 00:59:08.294572
5987 00:59:08.294632
5988 00:59:08.298518 [Calibration Summary] 1866 Mbps
5989 00:59:08.298597 CH 0, Rank 0
5990 00:59:08.301733 SW Impedance : PASS
5991 00:59:08.305121 DUTY Scan : NO K
5992 00:59:08.305201 ZQ Calibration : PASS
5993 00:59:08.308301 Jitter Meter : NO K
5994 00:59:08.311627 CBT Training : PASS
5995 00:59:08.311706 Write leveling : PASS
5996 00:59:08.314921 RX DQS gating : PASS
5997 00:59:08.315017 RX DQ/DQS(RDDQC) : PASS
5998 00:59:08.318235 TX DQ/DQS : PASS
5999 00:59:08.321341 RX DATLAT : PASS
6000 00:59:08.321419 RX DQ/DQS(Engine): PASS
6001 00:59:08.324974 TX OE : NO K
6002 00:59:08.325053 All Pass.
6003 00:59:08.325147
6004 00:59:08.328199 CH 0, Rank 1
6005 00:59:08.328278 SW Impedance : PASS
6006 00:59:08.331495 DUTY Scan : NO K
6007 00:59:08.334732 ZQ Calibration : PASS
6008 00:59:08.334811 Jitter Meter : NO K
6009 00:59:08.337655 CBT Training : PASS
6010 00:59:08.341388 Write leveling : PASS
6011 00:59:08.341472 RX DQS gating : PASS
6012 00:59:08.344702 RX DQ/DQS(RDDQC) : PASS
6013 00:59:08.348093 TX DQ/DQS : PASS
6014 00:59:08.348175 RX DATLAT : PASS
6015 00:59:08.351482 RX DQ/DQS(Engine): PASS
6016 00:59:08.354813 TX OE : NO K
6017 00:59:08.354894 All Pass.
6018 00:59:08.354954
6019 00:59:08.355009 CH 1, Rank 0
6020 00:59:08.357885 SW Impedance : PASS
6021 00:59:08.361061 DUTY Scan : NO K
6022 00:59:08.361136 ZQ Calibration : PASS
6023 00:59:08.364473 Jitter Meter : NO K
6024 00:59:08.367925 CBT Training : PASS
6025 00:59:08.368006 Write leveling : PASS
6026 00:59:08.371372 RX DQS gating : PASS
6027 00:59:08.371456 RX DQ/DQS(RDDQC) : PASS
6028 00:59:08.374657 TX DQ/DQS : PASS
6029 00:59:08.377648 RX DATLAT : PASS
6030 00:59:08.377738 RX DQ/DQS(Engine): PASS
6031 00:59:08.381244 TX OE : NO K
6032 00:59:08.381354 All Pass.
6033 00:59:08.381453
6034 00:59:08.384337 CH 1, Rank 1
6035 00:59:08.384442 SW Impedance : PASS
6036 00:59:08.387629 DUTY Scan : NO K
6037 00:59:08.390974 ZQ Calibration : PASS
6038 00:59:08.391074 Jitter Meter : NO K
6039 00:59:08.394267 CBT Training : PASS
6040 00:59:08.397593 Write leveling : PASS
6041 00:59:08.397694 RX DQS gating : PASS
6042 00:59:08.401320 RX DQ/DQS(RDDQC) : PASS
6043 00:59:08.404656 TX DQ/DQS : PASS
6044 00:59:08.404751 RX DATLAT : PASS
6045 00:59:08.407985 RX DQ/DQS(Engine): PASS
6046 00:59:08.408085 TX OE : NO K
6047 00:59:08.411369 All Pass.
6048 00:59:08.411462
6049 00:59:08.411556 DramC Write-DBI off
6050 00:59:08.414620 PER_BANK_REFRESH: Hybrid Mode
6051 00:59:08.417835 TX_TRACKING: ON
6052 00:59:08.424299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6053 00:59:08.427561 [FAST_K] Save calibration result to emmc
6054 00:59:08.434185 dramc_set_vcore_voltage set vcore to 650000
6055 00:59:08.434300 Read voltage for 400, 6
6056 00:59:08.437439 Vio18 = 0
6057 00:59:08.437542 Vcore = 650000
6058 00:59:08.437637 Vdram = 0
6059 00:59:08.437723 Vddq = 0
6060 00:59:08.440803 Vmddr = 0
6061 00:59:08.444060 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6062 00:59:08.450992 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6063 00:59:08.454158 MEM_TYPE=3, freq_sel=20
6064 00:59:08.454232 sv_algorithm_assistance_LP4_800
6065 00:59:08.460940 ============ PULL DRAM RESETB DOWN ============
6066 00:59:08.464179 ========== PULL DRAM RESETB DOWN end =========
6067 00:59:08.467214 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6068 00:59:08.470621 ===================================
6069 00:59:08.474007 LPDDR4 DRAM CONFIGURATION
6070 00:59:08.477359 ===================================
6071 00:59:08.480718 EX_ROW_EN[0] = 0x0
6072 00:59:08.480791 EX_ROW_EN[1] = 0x0
6073 00:59:08.483971 LP4Y_EN = 0x0
6074 00:59:08.484038 WORK_FSP = 0x0
6075 00:59:08.486999 WL = 0x2
6076 00:59:08.487068 RL = 0x2
6077 00:59:08.490564 BL = 0x2
6078 00:59:08.490636 RPST = 0x0
6079 00:59:08.494235 RD_PRE = 0x0
6080 00:59:08.494314 WR_PRE = 0x1
6081 00:59:08.497406 WR_PST = 0x0
6082 00:59:08.497524 DBI_WR = 0x0
6083 00:59:08.500709 DBI_RD = 0x0
6084 00:59:08.500773 OTF = 0x1
6085 00:59:08.504017 ===================================
6086 00:59:08.507252 ===================================
6087 00:59:08.510374 ANA top config
6088 00:59:08.514085 ===================================
6089 00:59:08.517487 DLL_ASYNC_EN = 0
6090 00:59:08.517562 ALL_SLAVE_EN = 1
6091 00:59:08.520884 NEW_RANK_MODE = 1
6092 00:59:08.523561 DLL_IDLE_MODE = 1
6093 00:59:08.527189 LP45_APHY_COMB_EN = 1
6094 00:59:08.527262 TX_ODT_DIS = 1
6095 00:59:08.530202 NEW_8X_MODE = 1
6096 00:59:08.533534 ===================================
6097 00:59:08.536827 ===================================
6098 00:59:08.540511 data_rate = 800
6099 00:59:08.543604 CKR = 1
6100 00:59:08.546983 DQ_P2S_RATIO = 4
6101 00:59:08.550393 ===================================
6102 00:59:08.553700 CA_P2S_RATIO = 4
6103 00:59:08.553771 DQ_CA_OPEN = 0
6104 00:59:08.557124 DQ_SEMI_OPEN = 1
6105 00:59:08.560333 CA_SEMI_OPEN = 1
6106 00:59:08.563972 CA_FULL_RATE = 0
6107 00:59:08.567045 DQ_CKDIV4_EN = 0
6108 00:59:08.570420 CA_CKDIV4_EN = 1
6109 00:59:08.570490 CA_PREDIV_EN = 0
6110 00:59:08.573634 PH8_DLY = 0
6111 00:59:08.577397 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6112 00:59:08.580121 DQ_AAMCK_DIV = 0
6113 00:59:08.583512 CA_AAMCK_DIV = 0
6114 00:59:08.587071 CA_ADMCK_DIV = 4
6115 00:59:08.587142 DQ_TRACK_CA_EN = 0
6116 00:59:08.590431 CA_PICK = 800
6117 00:59:08.593740 CA_MCKIO = 400
6118 00:59:08.596958 MCKIO_SEMI = 400
6119 00:59:08.600074 PLL_FREQ = 3016
6120 00:59:08.603684 DQ_UI_PI_RATIO = 32
6121 00:59:08.607050 CA_UI_PI_RATIO = 32
6122 00:59:08.610285 ===================================
6123 00:59:08.613709 ===================================
6124 00:59:08.613796 memory_type:LPDDR4
6125 00:59:08.617053 GP_NUM : 10
6126 00:59:08.620200 SRAM_EN : 1
6127 00:59:08.620281 MD32_EN : 0
6128 00:59:08.623312 ===================================
6129 00:59:08.626611 [ANA_INIT] >>>>>>>>>>>>>>
6130 00:59:08.629942 <<<<<< [CONFIGURE PHASE]: ANA_TX
6131 00:59:08.633187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6132 00:59:08.636892 ===================================
6133 00:59:08.640001 data_rate = 800,PCW = 0X7400
6134 00:59:08.643052 ===================================
6135 00:59:08.646763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6136 00:59:08.649968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 00:59:08.663199 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 00:59:08.666466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6139 00:59:08.669950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6140 00:59:08.673136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6141 00:59:08.676214 [ANA_INIT] flow start
6142 00:59:08.679832 [ANA_INIT] PLL >>>>>>>>
6143 00:59:08.679916 [ANA_INIT] PLL <<<<<<<<
6144 00:59:08.682908 [ANA_INIT] MIDPI >>>>>>>>
6145 00:59:08.686068 [ANA_INIT] MIDPI <<<<<<<<
6146 00:59:08.686147 [ANA_INIT] DLL >>>>>>>>
6147 00:59:08.689402 [ANA_INIT] flow end
6148 00:59:08.692745 ============ LP4 DIFF to SE enter ============
6149 00:59:08.696111 ============ LP4 DIFF to SE exit ============
6150 00:59:08.699409 [ANA_INIT] <<<<<<<<<<<<<
6151 00:59:08.702772 [Flow] Enable top DCM control >>>>>
6152 00:59:08.706166 [Flow] Enable top DCM control <<<<<
6153 00:59:08.709236 Enable DLL master slave shuffle
6154 00:59:08.716485 ==============================================================
6155 00:59:08.716576 Gating Mode config
6156 00:59:08.723045 ==============================================================
6157 00:59:08.723127 Config description:
6158 00:59:08.732697 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6159 00:59:08.739379 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6160 00:59:08.746377 SELPH_MODE 0: By rank 1: By Phase
6161 00:59:08.749601 ==============================================================
6162 00:59:08.752835 GAT_TRACK_EN = 0
6163 00:59:08.756148 RX_GATING_MODE = 2
6164 00:59:08.759196 RX_GATING_TRACK_MODE = 2
6165 00:59:08.762516 SELPH_MODE = 1
6166 00:59:08.765961 PICG_EARLY_EN = 1
6167 00:59:08.769275 VALID_LAT_VALUE = 1
6168 00:59:08.775997 ==============================================================
6169 00:59:08.779387 Enter into Gating configuration >>>>
6170 00:59:08.782636 Exit from Gating configuration <<<<
6171 00:59:08.785716 Enter into DVFS_PRE_config >>>>>
6172 00:59:08.795413 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6173 00:59:08.798971 Exit from DVFS_PRE_config <<<<<
6174 00:59:08.802229 Enter into PICG configuration >>>>
6175 00:59:08.805542 Exit from PICG configuration <<<<
6176 00:59:08.809109 [RX_INPUT] configuration >>>>>
6177 00:59:08.809182 [RX_INPUT] configuration <<<<<
6178 00:59:08.815807 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6179 00:59:08.822629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6180 00:59:08.825876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6181 00:59:08.832313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6182 00:59:08.839326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 00:59:08.845775 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 00:59:08.848913 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6185 00:59:08.852183 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6186 00:59:08.859103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6187 00:59:08.862247 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6188 00:59:08.865651 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6189 00:59:08.868665 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 00:59:08.872208 ===================================
6191 00:59:08.875603 LPDDR4 DRAM CONFIGURATION
6192 00:59:08.878995 ===================================
6193 00:59:08.882419 EX_ROW_EN[0] = 0x0
6194 00:59:08.882491 EX_ROW_EN[1] = 0x0
6195 00:59:08.885747 LP4Y_EN = 0x0
6196 00:59:08.885814 WORK_FSP = 0x0
6197 00:59:08.889099 WL = 0x2
6198 00:59:08.889166 RL = 0x2
6199 00:59:08.892316 BL = 0x2
6200 00:59:08.892409 RPST = 0x0
6201 00:59:08.895508 RD_PRE = 0x0
6202 00:59:08.895596 WR_PRE = 0x1
6203 00:59:08.898930 WR_PST = 0x0
6204 00:59:08.902262 DBI_WR = 0x0
6205 00:59:08.902352 DBI_RD = 0x0
6206 00:59:08.905330 OTF = 0x1
6207 00:59:08.909009 ===================================
6208 00:59:08.912221 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6209 00:59:08.915491 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6210 00:59:08.918827 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 00:59:08.922153 ===================================
6212 00:59:08.925414 LPDDR4 DRAM CONFIGURATION
6213 00:59:08.929121 ===================================
6214 00:59:08.932226 EX_ROW_EN[0] = 0x10
6215 00:59:08.932321 EX_ROW_EN[1] = 0x0
6216 00:59:08.935688 LP4Y_EN = 0x0
6217 00:59:08.935784 WORK_FSP = 0x0
6218 00:59:08.938968 WL = 0x2
6219 00:59:08.939041 RL = 0x2
6220 00:59:08.942171 BL = 0x2
6221 00:59:08.942246 RPST = 0x0
6222 00:59:08.945415 RD_PRE = 0x0
6223 00:59:08.945506 WR_PRE = 0x1
6224 00:59:08.948624 WR_PST = 0x0
6225 00:59:08.948697 DBI_WR = 0x0
6226 00:59:08.951978 DBI_RD = 0x0
6227 00:59:08.952072 OTF = 0x1
6228 00:59:08.955671 ===================================
6229 00:59:08.961938 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6230 00:59:08.967168 nWR fixed to 30
6231 00:59:08.970332 [ModeRegInit_LP4] CH0 RK0
6232 00:59:08.970402 [ModeRegInit_LP4] CH0 RK1
6233 00:59:08.973366 [ModeRegInit_LP4] CH1 RK0
6234 00:59:08.977045 [ModeRegInit_LP4] CH1 RK1
6235 00:59:08.977116 match AC timing 19
6236 00:59:08.983414 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6237 00:59:08.986866 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6238 00:59:08.990246 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6239 00:59:08.997060 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6240 00:59:09.000272 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6241 00:59:09.000374 ==
6242 00:59:09.003715 Dram Type= 6, Freq= 0, CH_0, rank 0
6243 00:59:09.007022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 00:59:09.007092 ==
6245 00:59:09.013571 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 00:59:09.020349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6247 00:59:09.023528 [CA 0] Center 36 (8~64) winsize 57
6248 00:59:09.026796 [CA 1] Center 36 (8~64) winsize 57
6249 00:59:09.030214 [CA 2] Center 36 (8~64) winsize 57
6250 00:59:09.030296 [CA 3] Center 36 (8~64) winsize 57
6251 00:59:09.033519 [CA 4] Center 36 (8~64) winsize 57
6252 00:59:09.036610 [CA 5] Center 36 (8~64) winsize 57
6253 00:59:09.036700
6254 00:59:09.043226 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6255 00:59:09.043311
6256 00:59:09.046635 [CATrainingPosCal] consider 1 rank data
6257 00:59:09.049966 u2DelayCellTimex100 = 270/100 ps
6258 00:59:09.053228 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:59:09.056512 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:59:09.060056 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:59:09.063115 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 00:59:09.066817 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 00:59:09.070025 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 00:59:09.070132
6265 00:59:09.073299 CA PerBit enable=1, Macro0, CA PI delay=36
6266 00:59:09.073397
6267 00:59:09.076591 [CBTSetCACLKResult] CA Dly = 36
6268 00:59:09.079699 CS Dly: 1 (0~32)
6269 00:59:09.079773 ==
6270 00:59:09.083044 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 00:59:09.086739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 00:59:09.086812 ==
6273 00:59:09.093085 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6274 00:59:09.096576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6275 00:59:09.099926 [CA 0] Center 36 (8~64) winsize 57
6276 00:59:09.103219 [CA 1] Center 36 (8~64) winsize 57
6277 00:59:09.106955 [CA 2] Center 36 (8~64) winsize 57
6278 00:59:09.110315 [CA 3] Center 36 (8~64) winsize 57
6279 00:59:09.113080 [CA 4] Center 36 (8~64) winsize 57
6280 00:59:09.116513 [CA 5] Center 36 (8~64) winsize 57
6281 00:59:09.116582
6282 00:59:09.119896 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6283 00:59:09.119970
6284 00:59:09.123287 [CATrainingPosCal] consider 2 rank data
6285 00:59:09.127054 u2DelayCellTimex100 = 270/100 ps
6286 00:59:09.130105 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 00:59:09.133303 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 00:59:09.136492 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 00:59:09.140320 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 00:59:09.146559 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 00:59:09.149988 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 00:59:09.150062
6293 00:59:09.153309 CA PerBit enable=1, Macro0, CA PI delay=36
6294 00:59:09.153402
6295 00:59:09.156664 [CBTSetCACLKResult] CA Dly = 36
6296 00:59:09.156757 CS Dly: 1 (0~32)
6297 00:59:09.156847
6298 00:59:09.160025 ----->DramcWriteLeveling(PI) begin...
6299 00:59:09.160117 ==
6300 00:59:09.163432 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 00:59:09.170451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 00:59:09.170534 ==
6303 00:59:09.173569 Write leveling (Byte 0): 40 => 8
6304 00:59:09.173638 Write leveling (Byte 1): 40 => 8
6305 00:59:09.176541 DramcWriteLeveling(PI) end<-----
6306 00:59:09.176606
6307 00:59:09.176660 ==
6308 00:59:09.180216 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 00:59:09.186464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 00:59:09.186570 ==
6311 00:59:09.190245 [Gating] SW mode calibration
6312 00:59:09.196586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6313 00:59:09.200158 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6314 00:59:09.206204 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 00:59:09.210193 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 00:59:09.213465 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 00:59:09.219412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 00:59:09.222779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 00:59:09.226187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 00:59:09.232923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 00:59:09.236116 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 00:59:09.239739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 00:59:09.242836 Total UI for P1: 0, mck2ui 16
6324 00:59:09.246592 best dqsien dly found for B0: ( 0, 14, 24)
6325 00:59:09.249612 Total UI for P1: 0, mck2ui 16
6326 00:59:09.253032 best dqsien dly found for B1: ( 0, 14, 24)
6327 00:59:09.256082 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6328 00:59:09.259389 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6329 00:59:09.259461
6330 00:59:09.262740 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 00:59:09.269441 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 00:59:09.269543 [Gating] SW calibration Done
6333 00:59:09.269614 ==
6334 00:59:09.272786 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 00:59:09.279385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 00:59:09.279472 ==
6337 00:59:09.279534 RX Vref Scan: 0
6338 00:59:09.279596
6339 00:59:09.282563 RX Vref 0 -> 0, step: 1
6340 00:59:09.282637
6341 00:59:09.286413 RX Delay -410 -> 252, step: 16
6342 00:59:09.289502 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6343 00:59:09.292709 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6344 00:59:09.299359 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6345 00:59:09.303080 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6346 00:59:09.306289 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6347 00:59:09.309272 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6348 00:59:09.316151 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6349 00:59:09.319400 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6350 00:59:09.322655 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6351 00:59:09.326025 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6352 00:59:09.332811 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6353 00:59:09.336183 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6354 00:59:09.339480 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6355 00:59:09.343006 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6356 00:59:09.349483 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6357 00:59:09.352738 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6358 00:59:09.352812 ==
6359 00:59:09.356153 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 00:59:09.359393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 00:59:09.359492 ==
6362 00:59:09.363158 DQS Delay:
6363 00:59:09.363261 DQS0 = 27, DQS1 = 35
6364 00:59:09.363353 DQM Delay:
6365 00:59:09.366120 DQM0 = 9, DQM1 = 11
6366 00:59:09.366245 DQ Delay:
6367 00:59:09.369738 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6368 00:59:09.373018 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6369 00:59:09.376381 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6370 00:59:09.379686 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6371 00:59:09.379772
6372 00:59:09.379830
6373 00:59:09.379882 ==
6374 00:59:09.382469 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 00:59:09.385712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 00:59:09.389082 ==
6377 00:59:09.389158
6378 00:59:09.389235
6379 00:59:09.389296 TX Vref Scan disable
6380 00:59:09.392294 == TX Byte 0 ==
6381 00:59:09.396288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 00:59:09.399550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 00:59:09.402883 == TX Byte 1 ==
6384 00:59:09.406014 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 00:59:09.409156 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 00:59:09.409246 ==
6387 00:59:09.412388 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 00:59:09.416104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 00:59:09.419019 ==
6390 00:59:09.419107
6391 00:59:09.419179
6392 00:59:09.419252 TX Vref Scan disable
6393 00:59:09.422795 == TX Byte 0 ==
6394 00:59:09.425665 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 00:59:09.429168 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 00:59:09.432628 == TX Byte 1 ==
6397 00:59:09.435682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 00:59:09.439033 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 00:59:09.439108
6400 00:59:09.442415 [DATLAT]
6401 00:59:09.442522 Freq=400, CH0 RK0
6402 00:59:09.442612
6403 00:59:09.445738 DATLAT Default: 0xf
6404 00:59:09.445815 0, 0xFFFF, sum = 0
6405 00:59:09.449083 1, 0xFFFF, sum = 0
6406 00:59:09.449164 2, 0xFFFF, sum = 0
6407 00:59:09.452478 3, 0xFFFF, sum = 0
6408 00:59:09.452555 4, 0xFFFF, sum = 0
6409 00:59:09.455656 5, 0xFFFF, sum = 0
6410 00:59:09.455737 6, 0xFFFF, sum = 0
6411 00:59:09.458837 7, 0xFFFF, sum = 0
6412 00:59:09.458917 8, 0xFFFF, sum = 0
6413 00:59:09.462143 9, 0xFFFF, sum = 0
6414 00:59:09.462217 10, 0xFFFF, sum = 0
6415 00:59:09.465488 11, 0xFFFF, sum = 0
6416 00:59:09.465591 12, 0xFFFF, sum = 0
6417 00:59:09.468789 13, 0x0, sum = 1
6418 00:59:09.468886 14, 0x0, sum = 2
6419 00:59:09.472404 15, 0x0, sum = 3
6420 00:59:09.472501 16, 0x0, sum = 4
6421 00:59:09.475308 best_step = 14
6422 00:59:09.475378
6423 00:59:09.475440 ==
6424 00:59:09.479172 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 00:59:09.482361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 00:59:09.482448 ==
6427 00:59:09.485522 RX Vref Scan: 1
6428 00:59:09.485628
6429 00:59:09.485720 RX Vref 0 -> 0, step: 1
6430 00:59:09.485803
6431 00:59:09.488984 RX Delay -311 -> 252, step: 8
6432 00:59:09.489057
6433 00:59:09.492388 Set Vref, RX VrefLevel [Byte0]: 56
6434 00:59:09.495585 [Byte1]: 50
6435 00:59:09.500157
6436 00:59:09.500265 Final RX Vref Byte 0 = 56 to rank0
6437 00:59:09.503384 Final RX Vref Byte 1 = 50 to rank0
6438 00:59:09.506727 Final RX Vref Byte 0 = 56 to rank1
6439 00:59:09.510118 Final RX Vref Byte 1 = 50 to rank1==
6440 00:59:09.513367 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 00:59:09.520506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 00:59:09.520649 ==
6443 00:59:09.520720 DQS Delay:
6444 00:59:09.523641 DQS0 = 28, DQS1 = 36
6445 00:59:09.523715 DQM Delay:
6446 00:59:09.523774 DQM0 = 10, DQM1 = 13
6447 00:59:09.527108 DQ Delay:
6448 00:59:09.530451 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6449 00:59:09.530580 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6450 00:59:09.533242 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6451 00:59:09.537138 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6452 00:59:09.537258
6453 00:59:09.537351
6454 00:59:09.546690 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfbb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6455 00:59:09.550261 CH0 RK0: MR19=C0C, MR18=CFBB
6456 00:59:09.556427 CH0_RK0: MR19=0xC0C, MR18=0xCFBB, DQSOSC=384, MR23=63, INC=400, DEC=267
6457 00:59:09.556556 ==
6458 00:59:09.559846 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 00:59:09.563076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 00:59:09.563180 ==
6461 00:59:09.566402 [Gating] SW mode calibration
6462 00:59:09.573048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6463 00:59:09.577023 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6464 00:59:09.583155 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 00:59:09.586694 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 00:59:09.590060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 00:59:09.596838 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 00:59:09.600159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 00:59:09.603510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 00:59:09.609843 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 00:59:09.613244 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 00:59:09.616735 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 00:59:09.619972 Total UI for P1: 0, mck2ui 16
6474 00:59:09.623350 best dqsien dly found for B0: ( 0, 14, 24)
6475 00:59:09.626514 Total UI for P1: 0, mck2ui 16
6476 00:59:09.629678 best dqsien dly found for B1: ( 0, 14, 24)
6477 00:59:09.633008 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6478 00:59:09.636180 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6479 00:59:09.639459
6480 00:59:09.642754 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 00:59:09.646098 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 00:59:09.649344 [Gating] SW calibration Done
6483 00:59:09.649420 ==
6484 00:59:09.652678 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 00:59:09.656465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 00:59:09.656538 ==
6487 00:59:09.656597 RX Vref Scan: 0
6488 00:59:09.659456
6489 00:59:09.659548 RX Vref 0 -> 0, step: 1
6490 00:59:09.659630
6491 00:59:09.662839 RX Delay -410 -> 252, step: 16
6492 00:59:09.666295 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6493 00:59:09.673176 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6494 00:59:09.676338 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6495 00:59:09.679645 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6496 00:59:09.683017 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6497 00:59:09.689668 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6498 00:59:09.693057 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6499 00:59:09.696404 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6500 00:59:09.699695 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6501 00:59:09.706065 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6502 00:59:09.709771 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6503 00:59:09.712902 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6504 00:59:09.716298 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6505 00:59:09.723031 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6506 00:59:09.726252 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6507 00:59:09.729658 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6508 00:59:09.729737 ==
6509 00:59:09.732926 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 00:59:09.736145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 00:59:09.739500 ==
6512 00:59:09.739575 DQS Delay:
6513 00:59:09.739634 DQS0 = 27, DQS1 = 35
6514 00:59:09.742671 DQM Delay:
6515 00:59:09.742742 DQM0 = 11, DQM1 = 10
6516 00:59:09.746048 DQ Delay:
6517 00:59:09.746129 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6518 00:59:09.749351 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6519 00:59:09.752753 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6520 00:59:09.756109 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6521 00:59:09.756192
6522 00:59:09.756273
6523 00:59:09.756366 ==
6524 00:59:09.759445 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 00:59:09.766117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 00:59:09.766206 ==
6527 00:59:09.766307
6528 00:59:09.766367
6529 00:59:09.766432 TX Vref Scan disable
6530 00:59:09.769263 == TX Byte 0 ==
6531 00:59:09.773143 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6532 00:59:09.776164 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6533 00:59:09.779654 == TX Byte 1 ==
6534 00:59:09.782580 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6535 00:59:09.786089 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6536 00:59:09.786170 ==
6537 00:59:09.789397 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 00:59:09.795730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 00:59:09.795813 ==
6540 00:59:09.795890
6541 00:59:09.795961
6542 00:59:09.799139 TX Vref Scan disable
6543 00:59:09.799220 == TX Byte 0 ==
6544 00:59:09.802782 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 00:59:09.806018 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 00:59:09.809405 == TX Byte 1 ==
6547 00:59:09.812605 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6548 00:59:09.815822 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6549 00:59:09.819023
6550 00:59:09.819105 [DATLAT]
6551 00:59:09.819184 Freq=400, CH0 RK1
6552 00:59:09.819259
6553 00:59:09.822117 DATLAT Default: 0xe
6554 00:59:09.822198 0, 0xFFFF, sum = 0
6555 00:59:09.826056 1, 0xFFFF, sum = 0
6556 00:59:09.826139 2, 0xFFFF, sum = 0
6557 00:59:09.829289 3, 0xFFFF, sum = 0
6558 00:59:09.829371 4, 0xFFFF, sum = 0
6559 00:59:09.832678 5, 0xFFFF, sum = 0
6560 00:59:09.832761 6, 0xFFFF, sum = 0
6561 00:59:09.835418 7, 0xFFFF, sum = 0
6562 00:59:09.839395 8, 0xFFFF, sum = 0
6563 00:59:09.839482 9, 0xFFFF, sum = 0
6564 00:59:09.842586 10, 0xFFFF, sum = 0
6565 00:59:09.842692 11, 0xFFFF, sum = 0
6566 00:59:09.845694 12, 0xFFFF, sum = 0
6567 00:59:09.845781 13, 0x0, sum = 1
6568 00:59:09.848934 14, 0x0, sum = 2
6569 00:59:09.849017 15, 0x0, sum = 3
6570 00:59:09.852212 16, 0x0, sum = 4
6571 00:59:09.852321 best_step = 14
6572 00:59:09.852419
6573 00:59:09.852513 ==
6574 00:59:09.855650 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 00:59:09.858930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 00:59:09.859020 ==
6577 00:59:09.862123 RX Vref Scan: 0
6578 00:59:09.862204
6579 00:59:09.865450 RX Vref 0 -> 0, step: 1
6580 00:59:09.865565
6581 00:59:09.865646 RX Delay -311 -> 252, step: 8
6582 00:59:09.874206 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6583 00:59:09.877694 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6584 00:59:09.881051 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6585 00:59:09.884379 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6586 00:59:09.890954 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6587 00:59:09.894283 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6588 00:59:09.897542 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6589 00:59:09.900661 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6590 00:59:09.907696 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6591 00:59:09.911032 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6592 00:59:09.914139 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6593 00:59:09.917592 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6594 00:59:09.924255 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6595 00:59:09.927543 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6596 00:59:09.931210 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6597 00:59:09.934516 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6598 00:59:09.937577 ==
6599 00:59:09.940682 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 00:59:09.943885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 00:59:09.943970 ==
6602 00:59:09.944030 DQS Delay:
6603 00:59:09.947917 DQS0 = 24, DQS1 = 32
6604 00:59:09.947993 DQM Delay:
6605 00:59:09.950579 DQM0 = 9, DQM1 = 9
6606 00:59:09.950646 DQ Delay:
6607 00:59:09.954380 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6608 00:59:09.957585 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6609 00:59:09.960773 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6610 00:59:09.964163 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6611 00:59:09.964241
6612 00:59:09.964315
6613 00:59:09.970322 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6614 00:59:09.973703 CH0 RK1: MR19=C0C, MR18=BA5B
6615 00:59:09.980302 CH0_RK1: MR19=0xC0C, MR18=0xBA5B, DQSOSC=386, MR23=63, INC=396, DEC=264
6616 00:59:09.983632 [RxdqsGatingPostProcess] freq 400
6617 00:59:09.987060 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6618 00:59:09.990472 best DQS0 dly(2T, 0.5T) = (0, 10)
6619 00:59:09.993723 best DQS1 dly(2T, 0.5T) = (0, 10)
6620 00:59:09.997095 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6621 00:59:10.000384 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6622 00:59:10.003769 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 00:59:10.007139 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 00:59:10.009866 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 00:59:10.013219 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 00:59:10.016570 Pre-setting of DQS Precalculation
6627 00:59:10.023362 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6628 00:59:10.023440 ==
6629 00:59:10.026516 Dram Type= 6, Freq= 0, CH_1, rank 0
6630 00:59:10.030108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 00:59:10.030177 ==
6632 00:59:10.036452 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 00:59:10.040118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6634 00:59:10.043691 [CA 0] Center 36 (8~64) winsize 57
6635 00:59:10.046675 [CA 1] Center 36 (8~64) winsize 57
6636 00:59:10.049969 [CA 2] Center 36 (8~64) winsize 57
6637 00:59:10.053653 [CA 3] Center 36 (8~64) winsize 57
6638 00:59:10.056502 [CA 4] Center 36 (8~64) winsize 57
6639 00:59:10.060062 [CA 5] Center 36 (8~64) winsize 57
6640 00:59:10.060138
6641 00:59:10.063611 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6642 00:59:10.063684
6643 00:59:10.066775 [CATrainingPosCal] consider 1 rank data
6644 00:59:10.070088 u2DelayCellTimex100 = 270/100 ps
6645 00:59:10.073579 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:59:10.077173 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:59:10.080189 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:59:10.083352 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 00:59:10.086830 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 00:59:10.093579 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 00:59:10.093708
6652 00:59:10.097053 CA PerBit enable=1, Macro0, CA PI delay=36
6653 00:59:10.097146
6654 00:59:10.100335 [CBTSetCACLKResult] CA Dly = 36
6655 00:59:10.100411 CS Dly: 1 (0~32)
6656 00:59:10.100470 ==
6657 00:59:10.103721 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 00:59:10.107000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 00:59:10.110372 ==
6660 00:59:10.113529 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6661 00:59:10.120332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6662 00:59:10.123653 [CA 0] Center 36 (8~64) winsize 57
6663 00:59:10.127002 [CA 1] Center 36 (8~64) winsize 57
6664 00:59:10.130346 [CA 2] Center 36 (8~64) winsize 57
6665 00:59:10.133739 [CA 3] Center 36 (8~64) winsize 57
6666 00:59:10.137039 [CA 4] Center 36 (8~64) winsize 57
6667 00:59:10.140186 [CA 5] Center 36 (8~64) winsize 57
6668 00:59:10.140259
6669 00:59:10.143202 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6670 00:59:10.143269
6671 00:59:10.146664 [CATrainingPosCal] consider 2 rank data
6672 00:59:10.150486 u2DelayCellTimex100 = 270/100 ps
6673 00:59:10.153151 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 00:59:10.156576 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 00:59:10.159899 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 00:59:10.163146 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 00:59:10.166787 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 00:59:10.170255 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 00:59:10.170322
6680 00:59:10.173322 CA PerBit enable=1, Macro0, CA PI delay=36
6681 00:59:10.173394
6682 00:59:10.176389 [CBTSetCACLKResult] CA Dly = 36
6683 00:59:10.179778 CS Dly: 1 (0~32)
6684 00:59:10.179845
6685 00:59:10.183146 ----->DramcWriteLeveling(PI) begin...
6686 00:59:10.183223 ==
6687 00:59:10.186720 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 00:59:10.189724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 00:59:10.189796 ==
6690 00:59:10.193211 Write leveling (Byte 0): 40 => 8
6691 00:59:10.196650 Write leveling (Byte 1): 40 => 8
6692 00:59:10.200348 DramcWriteLeveling(PI) end<-----
6693 00:59:10.200453
6694 00:59:10.200536 ==
6695 00:59:10.203496 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 00:59:10.206387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 00:59:10.206461 ==
6698 00:59:10.210263 [Gating] SW mode calibration
6699 00:59:10.216681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6700 00:59:10.223451 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6701 00:59:10.226760 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 00:59:10.230086 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 00:59:10.236672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 00:59:10.240007 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 00:59:10.243378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 00:59:10.250128 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 00:59:10.253315 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 00:59:10.256429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 00:59:10.263161 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 00:59:10.266362 Total UI for P1: 0, mck2ui 16
6711 00:59:10.269632 best dqsien dly found for B0: ( 0, 14, 24)
6712 00:59:10.272910 Total UI for P1: 0, mck2ui 16
6713 00:59:10.275990 best dqsien dly found for B1: ( 0, 14, 24)
6714 00:59:10.279743 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6715 00:59:10.283192 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6716 00:59:10.283264
6717 00:59:10.286451 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 00:59:10.289721 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 00:59:10.292736 [Gating] SW calibration Done
6720 00:59:10.292828 ==
6721 00:59:10.296080 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 00:59:10.299341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 00:59:10.299440 ==
6724 00:59:10.302722 RX Vref Scan: 0
6725 00:59:10.302792
6726 00:59:10.302849 RX Vref 0 -> 0, step: 1
6727 00:59:10.306116
6728 00:59:10.306183 RX Delay -410 -> 252, step: 16
6729 00:59:10.312696 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6730 00:59:10.315948 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6731 00:59:10.319813 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6732 00:59:10.322795 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6733 00:59:10.329407 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6734 00:59:10.332629 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6735 00:59:10.335925 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6736 00:59:10.339285 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6737 00:59:10.346070 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6738 00:59:10.349540 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6739 00:59:10.353007 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6740 00:59:10.356464 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6741 00:59:10.363033 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6742 00:59:10.366258 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6743 00:59:10.369258 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6744 00:59:10.372690 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6745 00:59:10.375761 ==
6746 00:59:10.379412 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 00:59:10.382612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 00:59:10.382702 ==
6749 00:59:10.382764 DQS Delay:
6750 00:59:10.386167 DQS0 = 35, DQS1 = 35
6751 00:59:10.386246 DQM Delay:
6752 00:59:10.389479 DQM0 = 18, DQM1 = 13
6753 00:59:10.389565 DQ Delay:
6754 00:59:10.392259 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6755 00:59:10.395991 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6756 00:59:10.399024 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6757 00:59:10.402603 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6758 00:59:10.402680
6759 00:59:10.402739
6760 00:59:10.402793 ==
6761 00:59:10.405872 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 00:59:10.409343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 00:59:10.409421 ==
6764 00:59:10.409482
6765 00:59:10.409537
6766 00:59:10.412738 TX Vref Scan disable
6767 00:59:10.412816 == TX Byte 0 ==
6768 00:59:10.419195 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 00:59:10.422544 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 00:59:10.422624 == TX Byte 1 ==
6771 00:59:10.429315 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 00:59:10.432719 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 00:59:10.432801 ==
6774 00:59:10.436011 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 00:59:10.439407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 00:59:10.439513 ==
6777 00:59:10.439609
6778 00:59:10.439670
6779 00:59:10.442570 TX Vref Scan disable
6780 00:59:10.442663 == TX Byte 0 ==
6781 00:59:10.449126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 00:59:10.452420 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 00:59:10.452509 == TX Byte 1 ==
6784 00:59:10.459439 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 00:59:10.462788 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 00:59:10.462872
6787 00:59:10.462932 [DATLAT]
6788 00:59:10.466233 Freq=400, CH1 RK0
6789 00:59:10.466314
6790 00:59:10.466394 DATLAT Default: 0xf
6791 00:59:10.468844 0, 0xFFFF, sum = 0
6792 00:59:10.468925 1, 0xFFFF, sum = 0
6793 00:59:10.472780 2, 0xFFFF, sum = 0
6794 00:59:10.472861 3, 0xFFFF, sum = 0
6795 00:59:10.476086 4, 0xFFFF, sum = 0
6796 00:59:10.476168 5, 0xFFFF, sum = 0
6797 00:59:10.479277 6, 0xFFFF, sum = 0
6798 00:59:10.479359 7, 0xFFFF, sum = 0
6799 00:59:10.482315 8, 0xFFFF, sum = 0
6800 00:59:10.482398 9, 0xFFFF, sum = 0
6801 00:59:10.486002 10, 0xFFFF, sum = 0
6802 00:59:10.489093 11, 0xFFFF, sum = 0
6803 00:59:10.489167 12, 0xFFFF, sum = 0
6804 00:59:10.492589 13, 0x0, sum = 1
6805 00:59:10.492668 14, 0x0, sum = 2
6806 00:59:10.492726 15, 0x0, sum = 3
6807 00:59:10.495555 16, 0x0, sum = 4
6808 00:59:10.495627 best_step = 14
6809 00:59:10.495685
6810 00:59:10.499064 ==
6811 00:59:10.499132 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 00:59:10.505956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 00:59:10.506028 ==
6814 00:59:10.506086 RX Vref Scan: 1
6815 00:59:10.506146
6816 00:59:10.508898 RX Vref 0 -> 0, step: 1
6817 00:59:10.508964
6818 00:59:10.512568 RX Delay -311 -> 252, step: 8
6819 00:59:10.512636
6820 00:59:10.515557 Set Vref, RX VrefLevel [Byte0]: 55
6821 00:59:10.518862 [Byte1]: 48
6822 00:59:10.522310
6823 00:59:10.522390 Final RX Vref Byte 0 = 55 to rank0
6824 00:59:10.525532 Final RX Vref Byte 1 = 48 to rank0
6825 00:59:10.528930 Final RX Vref Byte 0 = 55 to rank1
6826 00:59:10.532308 Final RX Vref Byte 1 = 48 to rank1==
6827 00:59:10.535579 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 00:59:10.542289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 00:59:10.542371 ==
6830 00:59:10.542433 DQS Delay:
6831 00:59:10.542487 DQS0 = 32, DQS1 = 32
6832 00:59:10.545635 DQM Delay:
6833 00:59:10.545707 DQM0 = 13, DQM1 = 10
6834 00:59:10.549039 DQ Delay:
6835 00:59:10.552407 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6836 00:59:10.552480 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6837 00:59:10.555711 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6838 00:59:10.559053 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6839 00:59:10.559129
6840 00:59:10.559186
6841 00:59:10.569290 [DQSOSCAuto] RK0, (LSB)MR18= 0x95ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6842 00:59:10.572263 CH1 RK0: MR19=C0C, MR18=95CE
6843 00:59:10.579268 CH1_RK0: MR19=0xC0C, MR18=0x95CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6844 00:59:10.579344 ==
6845 00:59:10.582671 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 00:59:10.585535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 00:59:10.585632 ==
6848 00:59:10.589335 [Gating] SW mode calibration
6849 00:59:10.596007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6850 00:59:10.599316 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6851 00:59:10.605600 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 00:59:10.609079 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 00:59:10.612765 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 00:59:10.619212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 00:59:10.622368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 00:59:10.625399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 00:59:10.632183 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 00:59:10.635352 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 00:59:10.638757 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 00:59:10.642029 Total UI for P1: 0, mck2ui 16
6861 00:59:10.645370 best dqsien dly found for B0: ( 0, 14, 24)
6862 00:59:10.648742 Total UI for P1: 0, mck2ui 16
6863 00:59:10.652099 best dqsien dly found for B1: ( 0, 14, 24)
6864 00:59:10.655486 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6865 00:59:10.658785 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6866 00:59:10.658882
6867 00:59:10.665500 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 00:59:10.668919 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 00:59:10.672285 [Gating] SW calibration Done
6870 00:59:10.672367 ==
6871 00:59:10.675568 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 00:59:10.678987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 00:59:10.679074 ==
6874 00:59:10.679179 RX Vref Scan: 0
6875 00:59:10.679250
6876 00:59:10.682163 RX Vref 0 -> 0, step: 1
6877 00:59:10.682335
6878 00:59:10.685241 RX Delay -410 -> 252, step: 16
6879 00:59:10.688911 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6880 00:59:10.695486 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6881 00:59:10.698733 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6882 00:59:10.702017 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6883 00:59:10.705392 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6884 00:59:10.712008 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6885 00:59:10.715150 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6886 00:59:10.718828 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6887 00:59:10.721811 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6888 00:59:10.724979 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6889 00:59:10.731642 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6890 00:59:10.735238 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6891 00:59:10.738421 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6892 00:59:10.745010 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6893 00:59:10.748253 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6894 00:59:10.751629 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6895 00:59:10.751711 ==
6896 00:59:10.754980 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 00:59:10.758237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 00:59:10.761609 ==
6899 00:59:10.761713 DQS Delay:
6900 00:59:10.761797 DQS0 = 35, DQS1 = 35
6901 00:59:10.764944 DQM Delay:
6902 00:59:10.765025 DQM0 = 18, DQM1 = 13
6903 00:59:10.768292 DQ Delay:
6904 00:59:10.768373 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6905 00:59:10.771761 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6906 00:59:10.775006 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6907 00:59:10.778300 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6908 00:59:10.778381
6909 00:59:10.778460
6910 00:59:10.782196 ==
6911 00:59:10.785005 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 00:59:10.788493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 00:59:10.788594 ==
6914 00:59:10.788690
6915 00:59:10.788775
6916 00:59:10.791878 TX Vref Scan disable
6917 00:59:10.791962 == TX Byte 0 ==
6918 00:59:10.795158 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6919 00:59:10.801332 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6920 00:59:10.801402 == TX Byte 1 ==
6921 00:59:10.804753 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6922 00:59:10.808154 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6923 00:59:10.811299 ==
6924 00:59:10.815190 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 00:59:10.818151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 00:59:10.818256 ==
6927 00:59:10.818354
6928 00:59:10.818435
6929 00:59:10.821589 TX Vref Scan disable
6930 00:59:10.821689 == TX Byte 0 ==
6931 00:59:10.824657 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 00:59:10.831595 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 00:59:10.831697 == TX Byte 1 ==
6934 00:59:10.834809 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6935 00:59:10.841433 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6936 00:59:10.841507
6937 00:59:10.841576 [DATLAT]
6938 00:59:10.841633 Freq=400, CH1 RK1
6939 00:59:10.841692
6940 00:59:10.844539 DATLAT Default: 0xe
6941 00:59:10.844633 0, 0xFFFF, sum = 0
6942 00:59:10.848220 1, 0xFFFF, sum = 0
6943 00:59:10.851542 2, 0xFFFF, sum = 0
6944 00:59:10.851650 3, 0xFFFF, sum = 0
6945 00:59:10.854707 4, 0xFFFF, sum = 0
6946 00:59:10.854819 5, 0xFFFF, sum = 0
6947 00:59:10.858035 6, 0xFFFF, sum = 0
6948 00:59:10.858147 7, 0xFFFF, sum = 0
6949 00:59:10.861383 8, 0xFFFF, sum = 0
6950 00:59:10.861484 9, 0xFFFF, sum = 0
6951 00:59:10.864704 10, 0xFFFF, sum = 0
6952 00:59:10.864779 11, 0xFFFF, sum = 0
6953 00:59:10.867943 12, 0xFFFF, sum = 0
6954 00:59:10.868017 13, 0x0, sum = 1
6955 00:59:10.871510 14, 0x0, sum = 2
6956 00:59:10.871597 15, 0x0, sum = 3
6957 00:59:10.874931 16, 0x0, sum = 4
6958 00:59:10.875003 best_step = 14
6959 00:59:10.875096
6960 00:59:10.875178 ==
6961 00:59:10.878281 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 00:59:10.881732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 00:59:10.881823 ==
6964 00:59:10.884390 RX Vref Scan: 0
6965 00:59:10.884485
6966 00:59:10.887703 RX Vref 0 -> 0, step: 1
6967 00:59:10.887803
6968 00:59:10.887888 RX Delay -311 -> 252, step: 8
6969 00:59:10.896580 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6970 00:59:10.899971 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6971 00:59:10.903311 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6972 00:59:10.906655 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6973 00:59:10.913504 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6974 00:59:10.916985 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6975 00:59:10.920409 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6976 00:59:10.923662 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6977 00:59:10.930432 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6978 00:59:10.933784 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6979 00:59:10.937082 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6980 00:59:10.940466 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6981 00:59:10.947223 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6982 00:59:10.950391 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6983 00:59:10.953625 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6984 00:59:10.956812 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6985 00:59:10.959782 ==
6986 00:59:10.963159 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 00:59:10.966399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 00:59:10.966494 ==
6989 00:59:10.966588 DQS Delay:
6990 00:59:10.970066 DQS0 = 32, DQS1 = 36
6991 00:59:10.970163 DQM Delay:
6992 00:59:10.973585 DQM0 = 14, DQM1 = 14
6993 00:59:10.973684 DQ Delay:
6994 00:59:10.976443 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6995 00:59:10.979984 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =16
6996 00:59:10.983341 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6997 00:59:10.986767 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6998 00:59:10.986876
6999 00:59:10.986964
7000 00:59:10.993467 [DQSOSCAuto] RK1, (LSB)MR18= 0xc657, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7001 00:59:10.996390 CH1 RK1: MR19=C0C, MR18=C657
7002 00:59:11.003240 CH1_RK1: MR19=0xC0C, MR18=0xC657, DQSOSC=385, MR23=63, INC=398, DEC=265
7003 00:59:11.006612 [RxdqsGatingPostProcess] freq 400
7004 00:59:11.013383 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7005 00:59:11.013504 best DQS0 dly(2T, 0.5T) = (0, 10)
7006 00:59:11.016134 best DQS1 dly(2T, 0.5T) = (0, 10)
7007 00:59:11.019574 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7008 00:59:11.022961 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7009 00:59:11.026314 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 00:59:11.029659 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 00:59:11.033141 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 00:59:11.036576 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 00:59:11.039313 Pre-setting of DQS Precalculation
7014 00:59:11.046042 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7015 00:59:11.053161 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7016 00:59:11.059702 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7017 00:59:11.059814
7018 00:59:11.059899
7019 00:59:11.063094 [Calibration Summary] 800 Mbps
7020 00:59:11.063191 CH 0, Rank 0
7021 00:59:11.066424 SW Impedance : PASS
7022 00:59:11.066524 DUTY Scan : NO K
7023 00:59:11.069208 ZQ Calibration : PASS
7024 00:59:11.072714 Jitter Meter : NO K
7025 00:59:11.072782 CBT Training : PASS
7026 00:59:11.075975 Write leveling : PASS
7027 00:59:11.079776 RX DQS gating : PASS
7028 00:59:11.079877 RX DQ/DQS(RDDQC) : PASS
7029 00:59:11.082891 TX DQ/DQS : PASS
7030 00:59:11.085792 RX DATLAT : PASS
7031 00:59:11.085899 RX DQ/DQS(Engine): PASS
7032 00:59:11.089247 TX OE : NO K
7033 00:59:11.089319 All Pass.
7034 00:59:11.089376
7035 00:59:11.092800 CH 0, Rank 1
7036 00:59:11.092890 SW Impedance : PASS
7037 00:59:11.095884 DUTY Scan : NO K
7038 00:59:11.099313 ZQ Calibration : PASS
7039 00:59:11.099381 Jitter Meter : NO K
7040 00:59:11.102762 CBT Training : PASS
7041 00:59:11.105693 Write leveling : NO K
7042 00:59:11.105795 RX DQS gating : PASS
7043 00:59:11.109166 RX DQ/DQS(RDDQC) : PASS
7044 00:59:11.112581 TX DQ/DQS : PASS
7045 00:59:11.112660 RX DATLAT : PASS
7046 00:59:11.116208 RX DQ/DQS(Engine): PASS
7047 00:59:11.116278 TX OE : NO K
7048 00:59:11.119158 All Pass.
7049 00:59:11.119222
7050 00:59:11.119283 CH 1, Rank 0
7051 00:59:11.122662 SW Impedance : PASS
7052 00:59:11.122760 DUTY Scan : NO K
7053 00:59:11.126128 ZQ Calibration : PASS
7054 00:59:11.129177 Jitter Meter : NO K
7055 00:59:11.129285 CBT Training : PASS
7056 00:59:11.132545 Write leveling : PASS
7057 00:59:11.135963 RX DQS gating : PASS
7058 00:59:11.136039 RX DQ/DQS(RDDQC) : PASS
7059 00:59:11.139350 TX DQ/DQS : PASS
7060 00:59:11.142771 RX DATLAT : PASS
7061 00:59:11.142849 RX DQ/DQS(Engine): PASS
7062 00:59:11.145593 TX OE : NO K
7063 00:59:11.145664 All Pass.
7064 00:59:11.145722
7065 00:59:11.149009 CH 1, Rank 1
7066 00:59:11.149076 SW Impedance : PASS
7067 00:59:11.152312 DUTY Scan : NO K
7068 00:59:11.155603 ZQ Calibration : PASS
7069 00:59:11.155673 Jitter Meter : NO K
7070 00:59:11.159437 CBT Training : PASS
7071 00:59:11.162247 Write leveling : NO K
7072 00:59:11.162320 RX DQS gating : PASS
7073 00:59:11.165574 RX DQ/DQS(RDDQC) : PASS
7074 00:59:11.165673 TX DQ/DQS : PASS
7075 00:59:11.168985 RX DATLAT : PASS
7076 00:59:11.172336 RX DQ/DQS(Engine): PASS
7077 00:59:11.172416 TX OE : NO K
7078 00:59:11.175670 All Pass.
7079 00:59:11.175747
7080 00:59:11.175806 DramC Write-DBI off
7081 00:59:11.178987 PER_BANK_REFRESH: Hybrid Mode
7082 00:59:11.182348 TX_TRACKING: ON
7083 00:59:11.188937 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7084 00:59:11.192723 [FAST_K] Save calibration result to emmc
7085 00:59:11.195741 dramc_set_vcore_voltage set vcore to 725000
7086 00:59:11.199483 Read voltage for 1600, 0
7087 00:59:11.199554 Vio18 = 0
7088 00:59:11.202620 Vcore = 725000
7089 00:59:11.202702 Vdram = 0
7090 00:59:11.202762 Vddq = 0
7091 00:59:11.205790 Vmddr = 0
7092 00:59:11.208957 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7093 00:59:11.215427 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7094 00:59:11.215535 MEM_TYPE=3, freq_sel=13
7095 00:59:11.219287 sv_algorithm_assistance_LP4_3733
7096 00:59:11.225723 ============ PULL DRAM RESETB DOWN ============
7097 00:59:11.229116 ========== PULL DRAM RESETB DOWN end =========
7098 00:59:11.232383 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7099 00:59:11.235598 ===================================
7100 00:59:11.238681 LPDDR4 DRAM CONFIGURATION
7101 00:59:11.242262 ===================================
7102 00:59:11.245537 EX_ROW_EN[0] = 0x0
7103 00:59:11.245644 EX_ROW_EN[1] = 0x0
7104 00:59:11.248715 LP4Y_EN = 0x0
7105 00:59:11.248789 WORK_FSP = 0x1
7106 00:59:11.252090 WL = 0x5
7107 00:59:11.252159 RL = 0x5
7108 00:59:11.255515 BL = 0x2
7109 00:59:11.255581 RPST = 0x0
7110 00:59:11.258837 RD_PRE = 0x0
7111 00:59:11.258905 WR_PRE = 0x1
7112 00:59:11.262170 WR_PST = 0x1
7113 00:59:11.262237 DBI_WR = 0x0
7114 00:59:11.265357 DBI_RD = 0x0
7115 00:59:11.265427 OTF = 0x1
7116 00:59:11.268409 ===================================
7117 00:59:11.271758 ===================================
7118 00:59:11.275202 ANA top config
7119 00:59:11.278620 ===================================
7120 00:59:11.281933 DLL_ASYNC_EN = 0
7121 00:59:11.282001 ALL_SLAVE_EN = 0
7122 00:59:11.284797 NEW_RANK_MODE = 1
7123 00:59:11.288271 DLL_IDLE_MODE = 1
7124 00:59:11.291598 LP45_APHY_COMB_EN = 1
7125 00:59:11.294975 TX_ODT_DIS = 0
7126 00:59:11.295050 NEW_8X_MODE = 1
7127 00:59:11.298055 ===================================
7128 00:59:11.301460 ===================================
7129 00:59:11.305180 data_rate = 3200
7130 00:59:11.308342 CKR = 1
7131 00:59:11.311433 DQ_P2S_RATIO = 8
7132 00:59:11.314696 ===================================
7133 00:59:11.318408 CA_P2S_RATIO = 8
7134 00:59:11.321525 DQ_CA_OPEN = 0
7135 00:59:11.321614 DQ_SEMI_OPEN = 0
7136 00:59:11.324509 CA_SEMI_OPEN = 0
7137 00:59:11.327681 CA_FULL_RATE = 0
7138 00:59:11.331446 DQ_CKDIV4_EN = 0
7139 00:59:11.334801 CA_CKDIV4_EN = 0
7140 00:59:11.337599 CA_PREDIV_EN = 0
7141 00:59:11.337709 PH8_DLY = 12
7142 00:59:11.340890 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7143 00:59:11.344768 DQ_AAMCK_DIV = 4
7144 00:59:11.348134 CA_AAMCK_DIV = 4
7145 00:59:11.351310 CA_ADMCK_DIV = 4
7146 00:59:11.354501 DQ_TRACK_CA_EN = 0
7147 00:59:11.354569 CA_PICK = 1600
7148 00:59:11.358042 CA_MCKIO = 1600
7149 00:59:11.361275 MCKIO_SEMI = 0
7150 00:59:11.364359 PLL_FREQ = 3068
7151 00:59:11.367830 DQ_UI_PI_RATIO = 32
7152 00:59:11.371205 CA_UI_PI_RATIO = 0
7153 00:59:11.374286 ===================================
7154 00:59:11.378243 ===================================
7155 00:59:11.378315 memory_type:LPDDR4
7156 00:59:11.381611 GP_NUM : 10
7157 00:59:11.384331 SRAM_EN : 1
7158 00:59:11.384433 MD32_EN : 0
7159 00:59:11.387766 ===================================
7160 00:59:11.391183 [ANA_INIT] >>>>>>>>>>>>>>
7161 00:59:11.394573 <<<<<< [CONFIGURE PHASE]: ANA_TX
7162 00:59:11.397970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7163 00:59:11.401214 ===================================
7164 00:59:11.404566 data_rate = 3200,PCW = 0X7600
7165 00:59:11.407570 ===================================
7166 00:59:11.410942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7167 00:59:11.414262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 00:59:11.420780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 00:59:11.424165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7170 00:59:11.427958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7171 00:59:11.434056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7172 00:59:11.434140 [ANA_INIT] flow start
7173 00:59:11.437979 [ANA_INIT] PLL >>>>>>>>
7174 00:59:11.438050 [ANA_INIT] PLL <<<<<<<<
7175 00:59:11.441148 [ANA_INIT] MIDPI >>>>>>>>
7176 00:59:11.444317 [ANA_INIT] MIDPI <<<<<<<<
7177 00:59:11.447627 [ANA_INIT] DLL >>>>>>>>
7178 00:59:11.447703 [ANA_INIT] DLL <<<<<<<<
7179 00:59:11.451106 [ANA_INIT] flow end
7180 00:59:11.454400 ============ LP4 DIFF to SE enter ============
7181 00:59:11.457628 ============ LP4 DIFF to SE exit ============
7182 00:59:11.461048 [ANA_INIT] <<<<<<<<<<<<<
7183 00:59:11.464372 [Flow] Enable top DCM control >>>>>
7184 00:59:11.467673 [Flow] Enable top DCM control <<<<<
7185 00:59:11.470843 Enable DLL master slave shuffle
7186 00:59:11.477267 ==============================================================
7187 00:59:11.477352 Gating Mode config
7188 00:59:11.484462 ==============================================================
7189 00:59:11.484643 Config description:
7190 00:59:11.494590 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7191 00:59:11.500788 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7192 00:59:11.507579 SELPH_MODE 0: By rank 1: By Phase
7193 00:59:11.510917 ==============================================================
7194 00:59:11.513964 GAT_TRACK_EN = 1
7195 00:59:11.517675 RX_GATING_MODE = 2
7196 00:59:11.520953 RX_GATING_TRACK_MODE = 2
7197 00:59:11.524164 SELPH_MODE = 1
7198 00:59:11.527584 PICG_EARLY_EN = 1
7199 00:59:11.530958 VALID_LAT_VALUE = 1
7200 00:59:11.534343 ==============================================================
7201 00:59:11.537459 Enter into Gating configuration >>>>
7202 00:59:11.540603 Exit from Gating configuration <<<<
7203 00:59:11.543810 Enter into DVFS_PRE_config >>>>>
7204 00:59:11.557171 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7205 00:59:11.560658 Exit from DVFS_PRE_config <<<<<
7206 00:59:11.564095 Enter into PICG configuration >>>>
7207 00:59:11.567400 Exit from PICG configuration <<<<
7208 00:59:11.567478 [RX_INPUT] configuration >>>>>
7209 00:59:11.570786 [RX_INPUT] configuration <<<<<
7210 00:59:11.577018 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7211 00:59:11.580323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7212 00:59:11.587489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7213 00:59:11.594035 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7214 00:59:11.600451 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 00:59:11.607339 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 00:59:11.610807 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7217 00:59:11.613516 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7218 00:59:11.616958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7219 00:59:11.623406 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7220 00:59:11.627104 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7221 00:59:11.630255 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 00:59:11.633993 ===================================
7223 00:59:11.637300 LPDDR4 DRAM CONFIGURATION
7224 00:59:11.639989 ===================================
7225 00:59:11.643910 EX_ROW_EN[0] = 0x0
7226 00:59:11.643991 EX_ROW_EN[1] = 0x0
7227 00:59:11.646683 LP4Y_EN = 0x0
7228 00:59:11.646766 WORK_FSP = 0x1
7229 00:59:11.650002 WL = 0x5
7230 00:59:11.650080 RL = 0x5
7231 00:59:11.653502 BL = 0x2
7232 00:59:11.653596 RPST = 0x0
7233 00:59:11.656720 RD_PRE = 0x0
7234 00:59:11.656798 WR_PRE = 0x1
7235 00:59:11.660381 WR_PST = 0x1
7236 00:59:11.660460 DBI_WR = 0x0
7237 00:59:11.663362 DBI_RD = 0x0
7238 00:59:11.663439 OTF = 0x1
7239 00:59:11.666974 ===================================
7240 00:59:11.673674 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7241 00:59:11.677146 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7242 00:59:11.679828 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 00:59:11.683276 ===================================
7244 00:59:11.686642 LPDDR4 DRAM CONFIGURATION
7245 00:59:11.690016 ===================================
7246 00:59:11.693437 EX_ROW_EN[0] = 0x10
7247 00:59:11.693512 EX_ROW_EN[1] = 0x0
7248 00:59:11.696727 LP4Y_EN = 0x0
7249 00:59:11.696801 WORK_FSP = 0x1
7250 00:59:11.700093 WL = 0x5
7251 00:59:11.700164 RL = 0x5
7252 00:59:11.703132 BL = 0x2
7253 00:59:11.703212 RPST = 0x0
7254 00:59:11.706867 RD_PRE = 0x0
7255 00:59:11.706950 WR_PRE = 0x1
7256 00:59:11.709968 WR_PST = 0x1
7257 00:59:11.710071 DBI_WR = 0x0
7258 00:59:11.713595 DBI_RD = 0x0
7259 00:59:11.713677 OTF = 0x1
7260 00:59:11.716500 ===================================
7261 00:59:11.723541 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7262 00:59:11.723625 ==
7263 00:59:11.727036 Dram Type= 6, Freq= 0, CH_0, rank 0
7264 00:59:11.730172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7265 00:59:11.733764 ==
7266 00:59:11.733844 [Duty_Offset_Calibration]
7267 00:59:11.736795 B0:2 B1:1 CA:1
7268 00:59:11.736874
7269 00:59:11.739965 [DutyScan_Calibration_Flow] k_type=0
7270 00:59:11.749052
7271 00:59:11.749140 ==CLK 0==
7272 00:59:11.752403 Final CLK duty delay cell = 0
7273 00:59:11.755439 [0] MAX Duty = 5156%(X100), DQS PI = 22
7274 00:59:11.758838 [0] MIN Duty = 4907%(X100), DQS PI = 0
7275 00:59:11.758920 [0] AVG Duty = 5031%(X100)
7276 00:59:11.762337
7277 00:59:11.765647 CH0 CLK Duty spec in!! Max-Min= 249%
7278 00:59:11.769103 [DutyScan_Calibration_Flow] ====Done====
7279 00:59:11.769182
7280 00:59:11.772056 [DutyScan_Calibration_Flow] k_type=1
7281 00:59:11.788145
7282 00:59:11.788242 ==DQS 0 ==
7283 00:59:11.791516 Final DQS duty delay cell = -4
7284 00:59:11.794863 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7285 00:59:11.798355 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7286 00:59:11.801752 [-4] AVG Duty = 4891%(X100)
7287 00:59:11.801833
7288 00:59:11.801913 ==DQS 1 ==
7289 00:59:11.804988 Final DQS duty delay cell = 0
7290 00:59:11.808115 [0] MAX Duty = 5187%(X100), DQS PI = 20
7291 00:59:11.811366 [0] MIN Duty = 5031%(X100), DQS PI = 52
7292 00:59:11.814773 [0] AVG Duty = 5109%(X100)
7293 00:59:11.814853
7294 00:59:11.818133 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7295 00:59:11.818212
7296 00:59:11.821348 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7297 00:59:11.824510 [DutyScan_Calibration_Flow] ====Done====
7298 00:59:11.824591
7299 00:59:11.828069 [DutyScan_Calibration_Flow] k_type=3
7300 00:59:11.845707
7301 00:59:11.845802 ==DQM 0 ==
7302 00:59:11.848912 Final DQM duty delay cell = 0
7303 00:59:11.852029 [0] MAX Duty = 5187%(X100), DQS PI = 32
7304 00:59:11.855560 [0] MIN Duty = 4876%(X100), DQS PI = 60
7305 00:59:11.858613 [0] AVG Duty = 5031%(X100)
7306 00:59:11.858696
7307 00:59:11.858775 ==DQM 1 ==
7308 00:59:11.862318 Final DQM duty delay cell = 0
7309 00:59:11.865345 [0] MAX Duty = 5187%(X100), DQS PI = 20
7310 00:59:11.868877 [0] MIN Duty = 5031%(X100), DQS PI = 48
7311 00:59:11.872236 [0] AVG Duty = 5109%(X100)
7312 00:59:11.872323
7313 00:59:11.875702 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7314 00:59:11.875782
7315 00:59:11.879012 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7316 00:59:11.882165 [DutyScan_Calibration_Flow] ====Done====
7317 00:59:11.882233
7318 00:59:11.885135 [DutyScan_Calibration_Flow] k_type=2
7319 00:59:11.902976
7320 00:59:11.903074 ==DQ 0 ==
7321 00:59:11.906425 Final DQ duty delay cell = 0
7322 00:59:11.909079 [0] MAX Duty = 5062%(X100), DQS PI = 24
7323 00:59:11.912442 [0] MIN Duty = 4907%(X100), DQS PI = 0
7324 00:59:11.912544 [0] AVG Duty = 4984%(X100)
7325 00:59:11.912629
7326 00:59:11.916340 ==DQ 1 ==
7327 00:59:11.919710 Final DQ duty delay cell = 0
7328 00:59:11.923010 [0] MAX Duty = 5156%(X100), DQS PI = 22
7329 00:59:11.925783 [0] MIN Duty = 4938%(X100), DQS PI = 34
7330 00:59:11.925866 [0] AVG Duty = 5047%(X100)
7331 00:59:11.925933
7332 00:59:11.929138 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7333 00:59:11.932905
7334 00:59:11.935952 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7335 00:59:11.939313 [DutyScan_Calibration_Flow] ====Done====
7336 00:59:11.939415 ==
7337 00:59:11.942598 Dram Type= 6, Freq= 0, CH_1, rank 0
7338 00:59:11.946234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7339 00:59:11.946315 ==
7340 00:59:11.949151 [Duty_Offset_Calibration]
7341 00:59:11.949258 B0:1 B1:0 CA:0
7342 00:59:11.949348
7343 00:59:11.952911 [DutyScan_Calibration_Flow] k_type=0
7344 00:59:11.962057
7345 00:59:11.962164 ==CLK 0==
7346 00:59:11.965252 Final CLK duty delay cell = -4
7347 00:59:11.969053 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7348 00:59:11.972289 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7349 00:59:11.975420 [-4] AVG Duty = 4906%(X100)
7350 00:59:11.975495
7351 00:59:11.978866 CH1 CLK Duty spec in!! Max-Min= 125%
7352 00:59:11.982245 [DutyScan_Calibration_Flow] ====Done====
7353 00:59:11.982322
7354 00:59:11.985624 [DutyScan_Calibration_Flow] k_type=1
7355 00:59:12.002065
7356 00:59:12.002155 ==DQS 0 ==
7357 00:59:12.005301 Final DQS duty delay cell = 0
7358 00:59:12.008731 [0] MAX Duty = 5094%(X100), DQS PI = 34
7359 00:59:12.012221 [0] MIN Duty = 4844%(X100), DQS PI = 0
7360 00:59:12.015615 [0] AVG Duty = 4969%(X100)
7361 00:59:12.015685
7362 00:59:12.015742 ==DQS 1 ==
7363 00:59:12.018994 Final DQS duty delay cell = 0
7364 00:59:12.022148 [0] MAX Duty = 5249%(X100), DQS PI = 18
7365 00:59:12.025484 [0] MIN Duty = 4938%(X100), DQS PI = 8
7366 00:59:12.028936 [0] AVG Duty = 5093%(X100)
7367 00:59:12.029012
7368 00:59:12.032288 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7369 00:59:12.032365
7370 00:59:12.035120 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7371 00:59:12.038397 [DutyScan_Calibration_Flow] ====Done====
7372 00:59:12.038473
7373 00:59:12.041596 [DutyScan_Calibration_Flow] k_type=3
7374 00:59:12.059242
7375 00:59:12.059347 ==DQM 0 ==
7376 00:59:12.062197 Final DQM duty delay cell = 0
7377 00:59:12.065914 [0] MAX Duty = 5187%(X100), DQS PI = 8
7378 00:59:12.069477 [0] MIN Duty = 4969%(X100), DQS PI = 48
7379 00:59:12.069563 [0] AVG Duty = 5078%(X100)
7380 00:59:12.069625
7381 00:59:12.072648 ==DQM 1 ==
7382 00:59:12.075655 Final DQM duty delay cell = 0
7383 00:59:12.078821 [0] MAX Duty = 5093%(X100), DQS PI = 16
7384 00:59:12.082469 [0] MIN Duty = 4876%(X100), DQS PI = 52
7385 00:59:12.082548 [0] AVG Duty = 4984%(X100)
7386 00:59:12.085505
7387 00:59:12.089090 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7388 00:59:12.089158
7389 00:59:12.092311 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7390 00:59:12.095769 [DutyScan_Calibration_Flow] ====Done====
7391 00:59:12.095836
7392 00:59:12.099135 [DutyScan_Calibration_Flow] k_type=2
7393 00:59:12.114724
7394 00:59:12.114850 ==DQ 0 ==
7395 00:59:12.118353 Final DQ duty delay cell = -4
7396 00:59:12.121672 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7397 00:59:12.124857 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7398 00:59:12.128020 [-4] AVG Duty = 4953%(X100)
7399 00:59:12.128093
7400 00:59:12.128149 ==DQ 1 ==
7401 00:59:12.131384 Final DQ duty delay cell = 0
7402 00:59:12.134712 [0] MAX Duty = 5124%(X100), DQS PI = 16
7403 00:59:12.138078 [0] MIN Duty = 4938%(X100), DQS PI = 10
7404 00:59:12.141366 [0] AVG Duty = 5031%(X100)
7405 00:59:12.141466
7406 00:59:12.144771 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7407 00:59:12.144863
7408 00:59:12.148069 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7409 00:59:12.151716 [DutyScan_Calibration_Flow] ====Done====
7410 00:59:12.155091 nWR fixed to 30
7411 00:59:12.155187 [ModeRegInit_LP4] CH0 RK0
7412 00:59:12.158479 [ModeRegInit_LP4] CH0 RK1
7413 00:59:12.161237 [ModeRegInit_LP4] CH1 RK0
7414 00:59:12.164598 [ModeRegInit_LP4] CH1 RK1
7415 00:59:12.164690 match AC timing 5
7416 00:59:12.171807 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7417 00:59:12.175060 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7418 00:59:12.178179 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7419 00:59:12.184812 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7420 00:59:12.188135 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7421 00:59:12.188245 [MiockJmeterHQA]
7422 00:59:12.188329
7423 00:59:12.191257 [DramcMiockJmeter] u1RxGatingPI = 0
7424 00:59:12.194343 0 : 4253, 4027
7425 00:59:12.194417 4 : 4363, 4138
7426 00:59:12.197649 8 : 4252, 4027
7427 00:59:12.197730 12 : 4255, 4029
7428 00:59:12.197826 16 : 4366, 4140
7429 00:59:12.201386 20 : 4252, 4027
7430 00:59:12.201506 24 : 4252, 4027
7431 00:59:12.204578 28 : 4253, 4027
7432 00:59:12.204659 32 : 4363, 4138
7433 00:59:12.208041 36 : 4363, 4138
7434 00:59:12.208136 40 : 4252, 4027
7435 00:59:12.211345 44 : 4252, 4027
7436 00:59:12.211427 48 : 4253, 4026
7437 00:59:12.211529 52 : 4252, 4027
7438 00:59:12.214770 56 : 4255, 4029
7439 00:59:12.214851 60 : 4363, 4138
7440 00:59:12.218211 64 : 4253, 4026
7441 00:59:12.218294 68 : 4250, 4027
7442 00:59:12.221403 72 : 4250, 4027
7443 00:59:12.221484 76 : 4252, 4029
7444 00:59:12.224558 80 : 4250, 4027
7445 00:59:12.224640 84 : 4361, 4138
7446 00:59:12.224720 88 : 4360, 101
7447 00:59:12.228020 92 : 4250, 0
7448 00:59:12.228102 96 : 4253, 0
7449 00:59:12.231412 100 : 4250, 0
7450 00:59:12.231496 104 : 4252, 0
7451 00:59:12.231577 108 : 4361, 0
7452 00:59:12.234458 112 : 4361, 0
7453 00:59:12.234541 116 : 4363, 0
7454 00:59:12.234621 120 : 4250, 0
7455 00:59:12.237487 124 : 4250, 0
7456 00:59:12.237575 128 : 4250, 0
7457 00:59:12.241377 132 : 4250, 0
7458 00:59:12.241475 136 : 4250, 0
7459 00:59:12.241571 140 : 4360, 0
7460 00:59:12.244153 144 : 4250, 0
7461 00:59:12.244257 148 : 4250, 0
7462 00:59:12.247490 152 : 4250, 0
7463 00:59:12.247588 156 : 4250, 0
7464 00:59:12.247684 160 : 4252, 0
7465 00:59:12.251046 164 : 4361, 0
7466 00:59:12.251145 168 : 4361, 0
7467 00:59:12.254310 172 : 4250, 0
7468 00:59:12.254403 176 : 4250, 0
7469 00:59:12.254488 180 : 4250, 0
7470 00:59:12.258009 184 : 4250, 0
7471 00:59:12.258103 188 : 4250, 0
7472 00:59:12.258172 192 : 4250, 0
7473 00:59:12.261113 196 : 4252, 0
7474 00:59:12.261206 200 : 4250, 0
7475 00:59:12.264357 204 : 4250, 1046
7476 00:59:12.264454 208 : 4250, 3999
7477 00:59:12.267701 212 : 4250, 4027
7478 00:59:12.267794 216 : 4250, 4027
7479 00:59:12.270966 220 : 4250, 4026
7480 00:59:12.271035 224 : 4250, 4027
7481 00:59:12.274276 228 : 4363, 4140
7482 00:59:12.274375 232 : 4250, 4027
7483 00:59:12.274461 236 : 4250, 4026
7484 00:59:12.277803 240 : 4361, 4137
7485 00:59:12.277903 244 : 4250, 4027
7486 00:59:12.281133 248 : 4250, 4027
7487 00:59:12.281201 252 : 4363, 4140
7488 00:59:12.284113 256 : 4250, 4027
7489 00:59:12.284211 260 : 4252, 4027
7490 00:59:12.287807 264 : 4250, 4027
7491 00:59:12.287880 268 : 4252, 4029
7492 00:59:12.291097 272 : 4250, 4027
7493 00:59:12.291192 276 : 4250, 4027
7494 00:59:12.294187 280 : 4361, 4138
7495 00:59:12.294257 284 : 4250, 4027
7496 00:59:12.297326 288 : 4250, 4027
7497 00:59:12.297392 292 : 4361, 4137
7498 00:59:12.297446 296 : 4250, 4027
7499 00:59:12.300826 300 : 4249, 4027
7500 00:59:12.300910 304 : 4363, 4140
7501 00:59:12.304113 308 : 4250, 4007
7502 00:59:12.304196 312 : 4252, 2030
7503 00:59:12.304277
7504 00:59:12.307474 MIOCK jitter meter ch=0
7505 00:59:12.307554
7506 00:59:12.310493 1T = (312-88) = 224 dly cells
7507 00:59:12.317458 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7508 00:59:12.317575 ==
7509 00:59:12.320961 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 00:59:12.324343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 00:59:12.324425 ==
7512 00:59:12.330503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 00:59:12.333739 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 00:59:12.337520 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 00:59:12.343971 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 00:59:12.352654 [CA 0] Center 42 (12~73) winsize 62
7517 00:59:12.355814 [CA 1] Center 42 (12~73) winsize 62
7518 00:59:12.359178 [CA 2] Center 37 (8~67) winsize 60
7519 00:59:12.362508 [CA 3] Center 37 (7~67) winsize 61
7520 00:59:12.365722 [CA 4] Center 36 (6~66) winsize 61
7521 00:59:12.369480 [CA 5] Center 34 (5~64) winsize 60
7522 00:59:12.369590
7523 00:59:12.372729 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 00:59:12.372811
7525 00:59:12.375857 [CATrainingPosCal] consider 1 rank data
7526 00:59:12.379159 u2DelayCellTimex100 = 290/100 ps
7527 00:59:12.382438 CA0 delay=42 (12~73),Diff = 8 PI (26 cell)
7528 00:59:12.389178 CA1 delay=42 (12~73),Diff = 8 PI (26 cell)
7529 00:59:12.392458 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7530 00:59:12.395640 CA3 delay=37 (7~67),Diff = 3 PI (10 cell)
7531 00:59:12.399459 CA4 delay=36 (6~66),Diff = 2 PI (6 cell)
7532 00:59:12.402440 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7533 00:59:12.402522
7534 00:59:12.405567 CA PerBit enable=1, Macro0, CA PI delay=34
7535 00:59:12.405648
7536 00:59:12.408992 [CBTSetCACLKResult] CA Dly = 34
7537 00:59:12.412285 CS Dly: 9 (0~40)
7538 00:59:12.416224 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 00:59:12.419322 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 00:59:12.419403 ==
7541 00:59:12.422433 Dram Type= 6, Freq= 0, CH_0, rank 1
7542 00:59:12.425664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 00:59:12.428994 ==
7544 00:59:12.432307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 00:59:12.435776 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 00:59:12.442415 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 00:59:12.445671 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 00:59:12.456341 [CA 0] Center 42 (12~73) winsize 62
7549 00:59:12.459393 [CA 1] Center 42 (12~73) winsize 62
7550 00:59:12.462439 [CA 2] Center 38 (8~68) winsize 61
7551 00:59:12.465970 [CA 3] Center 38 (8~68) winsize 61
7552 00:59:12.469292 [CA 4] Center 36 (6~66) winsize 61
7553 00:59:12.472750 [CA 5] Center 35 (5~65) winsize 61
7554 00:59:12.472832
7555 00:59:12.476023 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7556 00:59:12.476092
7557 00:59:12.479247 [CATrainingPosCal] consider 2 rank data
7558 00:59:12.482315 u2DelayCellTimex100 = 290/100 ps
7559 00:59:12.485539 CA0 delay=42 (12~73),Diff = 8 PI (26 cell)
7560 00:59:12.492282 CA1 delay=42 (12~73),Diff = 8 PI (26 cell)
7561 00:59:12.495654 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7562 00:59:12.499017 CA3 delay=37 (8~67),Diff = 3 PI (10 cell)
7563 00:59:12.502771 CA4 delay=36 (6~66),Diff = 2 PI (6 cell)
7564 00:59:12.506136 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7565 00:59:12.506203
7566 00:59:12.509463 CA PerBit enable=1, Macro0, CA PI delay=34
7567 00:59:12.509562
7568 00:59:12.512574 [CBTSetCACLKResult] CA Dly = 34
7569 00:59:12.515725 CS Dly: 9 (0~41)
7570 00:59:12.519102 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 00:59:12.522462 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 00:59:12.522542
7573 00:59:12.525756 ----->DramcWriteLeveling(PI) begin...
7574 00:59:12.525836 ==
7575 00:59:12.528976 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 00:59:12.532700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 00:59:12.535870 ==
7578 00:59:12.536010 Write leveling (Byte 0): 36 => 36
7579 00:59:12.539122 Write leveling (Byte 1): 25 => 25
7580 00:59:12.542652 DramcWriteLeveling(PI) end<-----
7581 00:59:12.542729
7582 00:59:12.542805 ==
7583 00:59:12.546145 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 00:59:12.552520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 00:59:12.552601 ==
7586 00:59:12.555771 [Gating] SW mode calibration
7587 00:59:12.562669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7588 00:59:12.566085 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7589 00:59:12.572447 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7590 00:59:12.575680 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 00:59:12.579328 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7592 00:59:12.582559 1 4 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7593 00:59:12.589014 1 4 16 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
7594 00:59:12.592551 1 4 20 | B1->B0 | 3333 3535 | 1 1 | (1 1) (1 1)
7595 00:59:12.596022 1 4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7596 00:59:12.602172 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7597 00:59:12.606199 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7598 00:59:12.609352 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7599 00:59:12.616244 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7600 00:59:12.618946 1 5 12 | B1->B0 | 3434 2e2d | 1 1 | (1 1) (1 0)
7601 00:59:12.622671 1 5 16 | B1->B0 | 3333 2827 | 1 1 | (1 1) (0 0)
7602 00:59:12.629191 1 5 20 | B1->B0 | 2727 2727 | 0 0 | (1 0) (0 0)
7603 00:59:12.632592 1 5 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7604 00:59:12.636012 1 5 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7605 00:59:12.642452 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7606 00:59:12.645749 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7607 00:59:12.649083 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7608 00:59:12.655500 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7609 00:59:12.658815 1 6 16 | B1->B0 | 2a2a 4645 | 0 1 | (0 0) (0 0)
7610 00:59:12.662263 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7611 00:59:12.669153 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 00:59:12.672499 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 00:59:12.675840 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 00:59:12.679046 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 00:59:12.685734 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 00:59:12.688798 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 00:59:12.692606 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7618 00:59:12.699157 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 00:59:12.702294 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 00:59:12.705985 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 00:59:12.711977 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 00:59:12.715928 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 00:59:12.719293 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 00:59:12.725393 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 00:59:12.728737 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 00:59:12.732038 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 00:59:12.739037 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 00:59:12.742394 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 00:59:12.745608 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 00:59:12.752048 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 00:59:12.755327 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 00:59:12.759204 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 00:59:12.766020 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 00:59:12.766101 Total UI for P1: 0, mck2ui 16
7635 00:59:12.772050 best dqsien dly found for B0: ( 1, 9, 10)
7636 00:59:12.775219 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 00:59:12.779081 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 00:59:12.782340 Total UI for P1: 0, mck2ui 16
7639 00:59:12.785762 best dqsien dly found for B1: ( 1, 9, 18)
7640 00:59:12.789084 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7641 00:59:12.792557 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7642 00:59:12.792637
7643 00:59:12.795792 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7644 00:59:12.801993 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7645 00:59:12.802075 [Gating] SW calibration Done
7646 00:59:12.802172 ==
7647 00:59:12.805676 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 00:59:12.812231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 00:59:12.812315 ==
7650 00:59:12.812395 RX Vref Scan: 0
7651 00:59:12.812468
7652 00:59:12.815520 RX Vref 0 -> 0, step: 1
7653 00:59:12.815601
7654 00:59:12.819090 RX Delay 0 -> 252, step: 8
7655 00:59:12.822275 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7656 00:59:12.825497 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7657 00:59:12.828947 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7658 00:59:12.835772 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7659 00:59:12.839132 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7660 00:59:12.842413 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7661 00:59:12.845555 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7662 00:59:12.848797 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7663 00:59:12.852002 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7664 00:59:12.858330 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7665 00:59:12.862112 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7666 00:59:12.865234 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7667 00:59:12.868633 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7668 00:59:12.872133 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7669 00:59:12.878337 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7670 00:59:12.882062 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7671 00:59:12.882145 ==
7672 00:59:12.885178 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 00:59:12.888332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 00:59:12.888417 ==
7675 00:59:12.891653 DQS Delay:
7676 00:59:12.891733 DQS0 = 0, DQS1 = 0
7677 00:59:12.891813 DQM Delay:
7678 00:59:12.895209 DQM0 = 136, DQM1 = 129
7679 00:59:12.895307 DQ Delay:
7680 00:59:12.898451 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7681 00:59:12.901771 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7682 00:59:12.908760 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7683 00:59:12.911988 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7684 00:59:12.912096
7685 00:59:12.912165
7686 00:59:12.912221 ==
7687 00:59:12.915079 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 00:59:12.918649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 00:59:12.918728 ==
7690 00:59:12.918788
7691 00:59:12.918844
7692 00:59:12.921606 TX Vref Scan disable
7693 00:59:12.925344 == TX Byte 0 ==
7694 00:59:12.928379 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7695 00:59:12.931940 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7696 00:59:12.935316 == TX Byte 1 ==
7697 00:59:12.938566 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7698 00:59:12.941778 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7699 00:59:12.941852 ==
7700 00:59:12.945103 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 00:59:12.948396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 00:59:12.951534 ==
7703 00:59:12.962766
7704 00:59:12.965768 TX Vref early break, caculate TX vref
7705 00:59:12.969061 TX Vref=16, minBit 3, minWin=22, winSum=378
7706 00:59:12.972701 TX Vref=18, minBit 7, minWin=22, winSum=386
7707 00:59:12.975768 TX Vref=20, minBit 0, minWin=24, winSum=406
7708 00:59:12.979094 TX Vref=22, minBit 3, minWin=24, winSum=410
7709 00:59:12.982502 TX Vref=24, minBit 0, minWin=25, winSum=417
7710 00:59:12.989268 TX Vref=26, minBit 2, minWin=25, winSum=429
7711 00:59:12.992488 TX Vref=28, minBit 0, minWin=25, winSum=422
7712 00:59:12.995632 TX Vref=30, minBit 1, minWin=24, winSum=413
7713 00:59:12.998991 TX Vref=32, minBit 6, minWin=23, winSum=403
7714 00:59:13.005964 [TxChooseVref] Worse bit 2, Min win 25, Win sum 429, Final Vref 26
7715 00:59:13.006090
7716 00:59:13.009379 Final TX Range 0 Vref 26
7717 00:59:13.009489
7718 00:59:13.009559 ==
7719 00:59:13.012121 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 00:59:13.015477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 00:59:13.015560 ==
7722 00:59:13.015620
7723 00:59:13.015674
7724 00:59:13.018910 TX Vref Scan disable
7725 00:59:13.022422 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7726 00:59:13.025674 == TX Byte 0 ==
7727 00:59:13.028764 u2DelayCellOfst[0]=13 cells (4 PI)
7728 00:59:13.032189 u2DelayCellOfst[1]=16 cells (5 PI)
7729 00:59:13.035511 u2DelayCellOfst[2]=10 cells (3 PI)
7730 00:59:13.038849 u2DelayCellOfst[3]=10 cells (3 PI)
7731 00:59:13.042443 u2DelayCellOfst[4]=10 cells (3 PI)
7732 00:59:13.042567 u2DelayCellOfst[5]=0 cells (0 PI)
7733 00:59:13.045985 u2DelayCellOfst[6]=16 cells (5 PI)
7734 00:59:13.048869 u2DelayCellOfst[7]=16 cells (5 PI)
7735 00:59:13.055782 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7736 00:59:13.059163 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7737 00:59:13.059238 == TX Byte 1 ==
7738 00:59:13.062497 u2DelayCellOfst[8]=3 cells (1 PI)
7739 00:59:13.065996 u2DelayCellOfst[9]=0 cells (0 PI)
7740 00:59:13.069067 u2DelayCellOfst[10]=6 cells (2 PI)
7741 00:59:13.072252 u2DelayCellOfst[11]=6 cells (2 PI)
7742 00:59:13.075303 u2DelayCellOfst[12]=10 cells (3 PI)
7743 00:59:13.078769 u2DelayCellOfst[13]=10 cells (3 PI)
7744 00:59:13.082107 u2DelayCellOfst[14]=13 cells (4 PI)
7745 00:59:13.085928 u2DelayCellOfst[15]=10 cells (3 PI)
7746 00:59:13.088659 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7747 00:59:13.092000 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7748 00:59:13.095340 DramC Write-DBI on
7749 00:59:13.095415 ==
7750 00:59:13.098765 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 00:59:13.101896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 00:59:13.101974 ==
7753 00:59:13.102033
7754 00:59:13.102088
7755 00:59:13.105686 TX Vref Scan disable
7756 00:59:13.109311 == TX Byte 0 ==
7757 00:59:13.112134 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7758 00:59:13.115442 == TX Byte 1 ==
7759 00:59:13.118745 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7760 00:59:13.118817 DramC Write-DBI off
7761 00:59:13.118877
7762 00:59:13.122001 [DATLAT]
7763 00:59:13.122069 Freq=1600, CH0 RK0
7764 00:59:13.122126
7765 00:59:13.125456 DATLAT Default: 0xf
7766 00:59:13.125555 0, 0xFFFF, sum = 0
7767 00:59:13.128763 1, 0xFFFF, sum = 0
7768 00:59:13.128831 2, 0xFFFF, sum = 0
7769 00:59:13.132099 3, 0xFFFF, sum = 0
7770 00:59:13.132170 4, 0xFFFF, sum = 0
7771 00:59:13.135134 5, 0xFFFF, sum = 0
7772 00:59:13.135235 6, 0xFFFF, sum = 0
7773 00:59:13.138613 7, 0xFFFF, sum = 0
7774 00:59:13.138710 8, 0xFFFF, sum = 0
7775 00:59:13.142048 9, 0xFFFF, sum = 0
7776 00:59:13.142142 10, 0xFFFF, sum = 0
7777 00:59:13.145414 11, 0xFFFF, sum = 0
7778 00:59:13.148916 12, 0xFFFF, sum = 0
7779 00:59:13.149017 13, 0xFFFF, sum = 0
7780 00:59:13.152171 14, 0x0, sum = 1
7781 00:59:13.152282 15, 0x0, sum = 2
7782 00:59:13.155542 16, 0x0, sum = 3
7783 00:59:13.155619 17, 0x0, sum = 4
7784 00:59:13.155680 best_step = 15
7785 00:59:13.155735
7786 00:59:13.159003 ==
7787 00:59:13.162007 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 00:59:13.165183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 00:59:13.165285 ==
7790 00:59:13.165369 RX Vref Scan: 1
7791 00:59:13.165456
7792 00:59:13.168809 Set Vref Range= 24 -> 127
7793 00:59:13.168898
7794 00:59:13.171848 RX Vref 24 -> 127, step: 1
7795 00:59:13.171958
7796 00:59:13.175350 RX Delay 19 -> 252, step: 4
7797 00:59:13.175454
7798 00:59:13.178719 Set Vref, RX VrefLevel [Byte0]: 24
7799 00:59:13.182002 [Byte1]: 24
7800 00:59:13.182102
7801 00:59:13.185154 Set Vref, RX VrefLevel [Byte0]: 25
7802 00:59:13.188331 [Byte1]: 25
7803 00:59:13.188403
7804 00:59:13.192018 Set Vref, RX VrefLevel [Byte0]: 26
7805 00:59:13.194905 [Byte1]: 26
7806 00:59:13.198369
7807 00:59:13.198467 Set Vref, RX VrefLevel [Byte0]: 27
7808 00:59:13.201896 [Byte1]: 27
7809 00:59:13.206296
7810 00:59:13.206367 Set Vref, RX VrefLevel [Byte0]: 28
7811 00:59:13.209347 [Byte1]: 28
7812 00:59:13.213795
7813 00:59:13.213914 Set Vref, RX VrefLevel [Byte0]: 29
7814 00:59:13.217148 [Byte1]: 29
7815 00:59:13.221257
7816 00:59:13.221359 Set Vref, RX VrefLevel [Byte0]: 30
7817 00:59:13.224758 [Byte1]: 30
7818 00:59:13.228803
7819 00:59:13.228896 Set Vref, RX VrefLevel [Byte0]: 31
7820 00:59:13.232142 [Byte1]: 31
7821 00:59:13.236155
7822 00:59:13.236264 Set Vref, RX VrefLevel [Byte0]: 32
7823 00:59:13.239563 [Byte1]: 32
7824 00:59:13.244100
7825 00:59:13.244180 Set Vref, RX VrefLevel [Byte0]: 33
7826 00:59:13.247351 [Byte1]: 33
7827 00:59:13.251466
7828 00:59:13.251543 Set Vref, RX VrefLevel [Byte0]: 34
7829 00:59:13.254884 [Byte1]: 34
7830 00:59:13.258893
7831 00:59:13.258987 Set Vref, RX VrefLevel [Byte0]: 35
7832 00:59:13.262168 [Byte1]: 35
7833 00:59:13.266611
7834 00:59:13.266714 Set Vref, RX VrefLevel [Byte0]: 36
7835 00:59:13.270010 [Byte1]: 36
7836 00:59:13.273993
7837 00:59:13.274063 Set Vref, RX VrefLevel [Byte0]: 37
7838 00:59:13.277835 [Byte1]: 37
7839 00:59:13.281583
7840 00:59:13.281692 Set Vref, RX VrefLevel [Byte0]: 38
7841 00:59:13.285279 [Byte1]: 38
7842 00:59:13.289401
7843 00:59:13.289497 Set Vref, RX VrefLevel [Byte0]: 39
7844 00:59:13.292605 [Byte1]: 39
7845 00:59:13.296681
7846 00:59:13.296757 Set Vref, RX VrefLevel [Byte0]: 40
7847 00:59:13.299979 [Byte1]: 40
7848 00:59:13.304424
7849 00:59:13.304497 Set Vref, RX VrefLevel [Byte0]: 41
7850 00:59:13.308006 [Byte1]: 41
7851 00:59:13.311758
7852 00:59:13.311859 Set Vref, RX VrefLevel [Byte0]: 42
7853 00:59:13.315455 [Byte1]: 42
7854 00:59:13.319609
7855 00:59:13.319716 Set Vref, RX VrefLevel [Byte0]: 43
7856 00:59:13.323029 [Byte1]: 43
7857 00:59:13.327378
7858 00:59:13.327456 Set Vref, RX VrefLevel [Byte0]: 44
7859 00:59:13.330393 [Byte1]: 44
7860 00:59:13.334958
7861 00:59:13.337748 Set Vref, RX VrefLevel [Byte0]: 45
7862 00:59:13.341249 [Byte1]: 45
7863 00:59:13.341350
7864 00:59:13.344530 Set Vref, RX VrefLevel [Byte0]: 46
7865 00:59:13.347588 [Byte1]: 46
7866 00:59:13.347661
7867 00:59:13.351028 Set Vref, RX VrefLevel [Byte0]: 47
7868 00:59:13.354405 [Byte1]: 47
7869 00:59:13.354488
7870 00:59:13.357841 Set Vref, RX VrefLevel [Byte0]: 48
7871 00:59:13.361259 [Byte1]: 48
7872 00:59:13.365386
7873 00:59:13.365491 Set Vref, RX VrefLevel [Byte0]: 49
7874 00:59:13.368104 [Byte1]: 49
7875 00:59:13.372502
7876 00:59:13.372585 Set Vref, RX VrefLevel [Byte0]: 50
7877 00:59:13.375884 [Byte1]: 50
7878 00:59:13.379971
7879 00:59:13.380057 Set Vref, RX VrefLevel [Byte0]: 51
7880 00:59:13.383447 [Byte1]: 51
7881 00:59:13.388223
7882 00:59:13.388321 Set Vref, RX VrefLevel [Byte0]: 52
7883 00:59:13.391497 [Byte1]: 52
7884 00:59:13.395403
7885 00:59:13.395481 Set Vref, RX VrefLevel [Byte0]: 53
7886 00:59:13.398466 [Byte1]: 53
7887 00:59:13.403170
7888 00:59:13.403253 Set Vref, RX VrefLevel [Byte0]: 54
7889 00:59:13.406153 [Byte1]: 54
7890 00:59:13.410826
7891 00:59:13.410952 Set Vref, RX VrefLevel [Byte0]: 55
7892 00:59:13.413818 [Byte1]: 55
7893 00:59:13.418331
7894 00:59:13.418475 Set Vref, RX VrefLevel [Byte0]: 56
7895 00:59:13.421372 [Byte1]: 56
7896 00:59:13.425403
7897 00:59:13.425539 Set Vref, RX VrefLevel [Byte0]: 57
7898 00:59:13.429365 [Byte1]: 57
7899 00:59:13.433293
7900 00:59:13.436707 Set Vref, RX VrefLevel [Byte0]: 58
7901 00:59:13.440061 [Byte1]: 58
7902 00:59:13.440149
7903 00:59:13.443407 Set Vref, RX VrefLevel [Byte0]: 59
7904 00:59:13.446491 [Byte1]: 59
7905 00:59:13.446568
7906 00:59:13.449438 Set Vref, RX VrefLevel [Byte0]: 60
7907 00:59:13.453245 [Byte1]: 60
7908 00:59:13.453331
7909 00:59:13.456368 Set Vref, RX VrefLevel [Byte0]: 61
7910 00:59:13.459717 [Byte1]: 61
7911 00:59:13.463831
7912 00:59:13.463931 Set Vref, RX VrefLevel [Byte0]: 62
7913 00:59:13.467263 [Byte1]: 62
7914 00:59:13.471403
7915 00:59:13.471491 Set Vref, RX VrefLevel [Byte0]: 63
7916 00:59:13.474579 [Byte1]: 63
7917 00:59:13.478972
7918 00:59:13.479085 Set Vref, RX VrefLevel [Byte0]: 64
7919 00:59:13.481740 [Byte1]: 64
7920 00:59:13.486039
7921 00:59:13.486152 Set Vref, RX VrefLevel [Byte0]: 65
7922 00:59:13.489236 [Byte1]: 65
7923 00:59:13.494188
7924 00:59:13.494314 Set Vref, RX VrefLevel [Byte0]: 66
7925 00:59:13.496999 [Byte1]: 66
7926 00:59:13.501132
7927 00:59:13.501249 Set Vref, RX VrefLevel [Byte0]: 67
7928 00:59:13.504452 [Byte1]: 67
7929 00:59:13.508947
7930 00:59:13.509076 Set Vref, RX VrefLevel [Byte0]: 68
7931 00:59:13.512301 [Byte1]: 68
7932 00:59:13.516376
7933 00:59:13.516496 Set Vref, RX VrefLevel [Byte0]: 69
7934 00:59:13.520169 [Byte1]: 69
7935 00:59:13.524326
7936 00:59:13.524442 Set Vref, RX VrefLevel [Byte0]: 70
7937 00:59:13.527305 [Byte1]: 70
7938 00:59:13.532093
7939 00:59:13.532184 Set Vref, RX VrefLevel [Byte0]: 71
7940 00:59:13.535003 [Byte1]: 71
7941 00:59:13.539672
7942 00:59:13.539758 Set Vref, RX VrefLevel [Byte0]: 72
7943 00:59:13.542275 [Byte1]: 72
7944 00:59:13.546838
7945 00:59:13.546919 Set Vref, RX VrefLevel [Byte0]: 73
7946 00:59:13.550193 [Byte1]: 73
7947 00:59:13.554504
7948 00:59:13.554634 Set Vref, RX VrefLevel [Byte0]: 74
7949 00:59:13.557678 [Byte1]: 74
7950 00:59:13.561790
7951 00:59:13.561930 Set Vref, RX VrefLevel [Byte0]: 75
7952 00:59:13.565484 [Byte1]: 75
7953 00:59:13.569938
7954 00:59:13.570095 Final RX Vref Byte 0 = 59 to rank0
7955 00:59:13.572703 Final RX Vref Byte 1 = 61 to rank0
7956 00:59:13.576012 Final RX Vref Byte 0 = 59 to rank1
7957 00:59:13.579389 Final RX Vref Byte 1 = 61 to rank1==
7958 00:59:13.582621 Dram Type= 6, Freq= 0, CH_0, rank 0
7959 00:59:13.589745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 00:59:13.589906 ==
7961 00:59:13.590012 DQS Delay:
7962 00:59:13.590118 DQS0 = 0, DQS1 = 0
7963 00:59:13.593204 DQM Delay:
7964 00:59:13.593323 DQM0 = 134, DQM1 = 127
7965 00:59:13.595993 DQ Delay:
7966 00:59:13.599500 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7967 00:59:13.602981 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7968 00:59:13.606495 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7969 00:59:13.609773 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =134
7970 00:59:13.609855
7971 00:59:13.609915
7972 00:59:13.609971
7973 00:59:13.613071 [DramC_TX_OE_Calibration] TA2
7974 00:59:13.616388 Original DQ_B0 (3 6) =30, OEN = 27
7975 00:59:13.619832 Original DQ_B1 (3 6) =30, OEN = 27
7976 00:59:13.623175 24, 0x0, End_B0=24 End_B1=24
7977 00:59:13.623255 25, 0x0, End_B0=25 End_B1=25
7978 00:59:13.626079 26, 0x0, End_B0=26 End_B1=26
7979 00:59:13.629443 27, 0x0, End_B0=27 End_B1=27
7980 00:59:13.632755 28, 0x0, End_B0=28 End_B1=28
7981 00:59:13.632842 29, 0x0, End_B0=29 End_B1=29
7982 00:59:13.636222 30, 0x0, End_B0=30 End_B1=30
7983 00:59:13.639439 31, 0x4141, End_B0=30 End_B1=30
7984 00:59:13.642671 Byte0 end_step=30 best_step=27
7985 00:59:13.645774 Byte1 end_step=30 best_step=27
7986 00:59:13.649378 Byte0 TX OE(2T, 0.5T) = (3, 3)
7987 00:59:13.652514 Byte1 TX OE(2T, 0.5T) = (3, 3)
7988 00:59:13.652588
7989 00:59:13.652647
7990 00:59:13.659135 [DQSOSCAuto] RK0, (LSB)MR18= 0x2621, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
7991 00:59:13.662291 CH0 RK0: MR19=303, MR18=2621
7992 00:59:13.669387 CH0_RK0: MR19=0x303, MR18=0x2621, DQSOSC=390, MR23=63, INC=24, DEC=16
7993 00:59:13.669491
7994 00:59:13.672352 ----->DramcWriteLeveling(PI) begin...
7995 00:59:13.672432 ==
7996 00:59:13.676070 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 00:59:13.679253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 00:59:13.679332 ==
7999 00:59:13.682086 Write leveling (Byte 0): 38 => 38
8000 00:59:13.685372 Write leveling (Byte 1): 27 => 27
8001 00:59:13.688994 DramcWriteLeveling(PI) end<-----
8002 00:59:13.689095
8003 00:59:13.689183 ==
8004 00:59:13.692139 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 00:59:13.695507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 00:59:13.695586 ==
8007 00:59:13.699072 [Gating] SW mode calibration
8008 00:59:13.705958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8009 00:59:13.711987 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8010 00:59:13.715449 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8011 00:59:13.718740 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8012 00:59:13.725596 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 00:59:13.729025 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8014 00:59:13.732433 1 4 16 | B1->B0 | 3333 3535 | 1 0 | (1 1) (0 0)
8015 00:59:13.738433 1 4 20 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8016 00:59:13.741981 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8017 00:59:13.745553 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8018 00:59:13.752312 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8019 00:59:13.755681 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8020 00:59:13.758369 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
8021 00:59:13.765012 1 5 12 | B1->B0 | 3434 3332 | 1 1 | (1 0) (0 0)
8022 00:59:13.768346 1 5 16 | B1->B0 | 2a2a 2e2e | 0 1 | (0 1) (1 0)
8023 00:59:13.771635 1 5 20 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8024 00:59:13.778787 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8025 00:59:13.782249 1 5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8026 00:59:13.785384 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8027 00:59:13.791585 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8028 00:59:13.795605 1 6 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8029 00:59:13.798931 1 6 12 | B1->B0 | 2727 3535 | 0 0 | (0 0) (1 1)
8030 00:59:13.805287 1 6 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
8031 00:59:13.808397 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8032 00:59:13.811815 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 00:59:13.818846 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8034 00:59:13.822315 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 00:59:13.825112 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 00:59:13.832097 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 00:59:13.835485 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8038 00:59:13.838075 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 00:59:13.844722 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 00:59:13.848071 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 00:59:13.851535 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 00:59:13.857966 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 00:59:13.861244 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 00:59:13.864570 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 00:59:13.871296 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 00:59:13.874418 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 00:59:13.877819 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 00:59:13.884976 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 00:59:13.887690 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 00:59:13.891119 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 00:59:13.898082 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 00:59:13.901516 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 00:59:13.904783 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8054 00:59:13.908088 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 00:59:13.911021 Total UI for P1: 0, mck2ui 16
8056 00:59:13.914456 best dqsien dly found for B0: ( 1, 9, 12)
8057 00:59:13.921326 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 00:59:13.924497 Total UI for P1: 0, mck2ui 16
8059 00:59:13.927859 best dqsien dly found for B1: ( 1, 9, 14)
8060 00:59:13.931221 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8061 00:59:13.934589 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8062 00:59:13.934659
8063 00:59:13.937890 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8064 00:59:13.941157 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8065 00:59:13.944499 [Gating] SW calibration Done
8066 00:59:13.944577 ==
8067 00:59:13.947810 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 00:59:13.951275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 00:59:13.951347 ==
8070 00:59:13.953940 RX Vref Scan: 0
8071 00:59:13.954007
8072 00:59:13.957321 RX Vref 0 -> 0, step: 1
8073 00:59:13.957415
8074 00:59:13.957498 RX Delay 0 -> 252, step: 8
8075 00:59:13.963925 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8076 00:59:13.967359 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8077 00:59:13.970858 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8078 00:59:13.974409 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8079 00:59:13.977728 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8080 00:59:13.980856 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8081 00:59:13.987602 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8082 00:59:13.990985 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8083 00:59:13.994065 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8084 00:59:13.997742 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8085 00:59:14.001003 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8086 00:59:14.007817 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8087 00:59:14.011224 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8088 00:59:14.014136 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8089 00:59:14.017623 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8090 00:59:14.024316 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8091 00:59:14.024418 ==
8092 00:59:14.027826 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 00:59:14.031062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 00:59:14.031139 ==
8095 00:59:14.031217 DQS Delay:
8096 00:59:14.034109 DQS0 = 0, DQS1 = 0
8097 00:59:14.034185 DQM Delay:
8098 00:59:14.037733 DQM0 = 137, DQM1 = 129
8099 00:59:14.037809 DQ Delay:
8100 00:59:14.040729 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8101 00:59:14.044191 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8102 00:59:14.047391 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8103 00:59:14.050854 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8104 00:59:14.050935
8105 00:59:14.051024
8106 00:59:14.051109 ==
8107 00:59:14.054287 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 00:59:14.060811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 00:59:14.060905 ==
8110 00:59:14.060980
8111 00:59:14.061034
8112 00:59:14.061085 TX Vref Scan disable
8113 00:59:14.064666 == TX Byte 0 ==
8114 00:59:14.067911 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8115 00:59:14.074827 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8116 00:59:14.074909 == TX Byte 1 ==
8117 00:59:14.078247 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8118 00:59:14.084849 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8119 00:59:14.084925 ==
8120 00:59:14.088093 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 00:59:14.091250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 00:59:14.091371 ==
8123 00:59:14.106035
8124 00:59:14.109271 TX Vref early break, caculate TX vref
8125 00:59:14.113136 TX Vref=16, minBit 1, minWin=22, winSum=385
8126 00:59:14.116624 TX Vref=18, minBit 1, minWin=24, winSum=401
8127 00:59:14.119352 TX Vref=20, minBit 3, minWin=23, winSum=401
8128 00:59:14.122803 TX Vref=22, minBit 1, minWin=24, winSum=412
8129 00:59:14.126260 TX Vref=24, minBit 0, minWin=25, winSum=421
8130 00:59:14.132768 TX Vref=26, minBit 2, minWin=25, winSum=422
8131 00:59:14.136132 TX Vref=28, minBit 1, minWin=25, winSum=421
8132 00:59:14.139567 TX Vref=30, minBit 2, minWin=25, winSum=415
8133 00:59:14.142755 TX Vref=32, minBit 0, minWin=25, winSum=411
8134 00:59:14.145819 TX Vref=34, minBit 4, minWin=24, winSum=406
8135 00:59:14.149609 TX Vref=36, minBit 0, minWin=24, winSum=396
8136 00:59:14.156348 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 26
8137 00:59:14.156427
8138 00:59:14.159723 Final TX Range 0 Vref 26
8139 00:59:14.159835
8140 00:59:14.159893 ==
8141 00:59:14.162357 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 00:59:14.166263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 00:59:14.166340 ==
8144 00:59:14.166400
8145 00:59:14.166455
8146 00:59:14.169336 TX Vref Scan disable
8147 00:59:14.175736 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8148 00:59:14.175818 == TX Byte 0 ==
8149 00:59:14.178946 u2DelayCellOfst[0]=13 cells (4 PI)
8150 00:59:14.182773 u2DelayCellOfst[1]=13 cells (4 PI)
8151 00:59:14.185859 u2DelayCellOfst[2]=10 cells (3 PI)
8152 00:59:14.189343 u2DelayCellOfst[3]=10 cells (3 PI)
8153 00:59:14.192801 u2DelayCellOfst[4]=10 cells (3 PI)
8154 00:59:14.196017 u2DelayCellOfst[5]=0 cells (0 PI)
8155 00:59:14.199239 u2DelayCellOfst[6]=16 cells (5 PI)
8156 00:59:14.202634 u2DelayCellOfst[7]=16 cells (5 PI)
8157 00:59:14.206041 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8158 00:59:14.209344 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8159 00:59:14.212422 == TX Byte 1 ==
8160 00:59:14.215815 u2DelayCellOfst[8]=3 cells (1 PI)
8161 00:59:14.218969 u2DelayCellOfst[9]=0 cells (0 PI)
8162 00:59:14.219070 u2DelayCellOfst[10]=6 cells (2 PI)
8163 00:59:14.222246 u2DelayCellOfst[11]=3 cells (1 PI)
8164 00:59:14.225528 u2DelayCellOfst[12]=10 cells (3 PI)
8165 00:59:14.229227 u2DelayCellOfst[13]=13 cells (4 PI)
8166 00:59:14.232558 u2DelayCellOfst[14]=16 cells (5 PI)
8167 00:59:14.235867 u2DelayCellOfst[15]=10 cells (3 PI)
8168 00:59:14.242719 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8169 00:59:14.245400 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8170 00:59:14.245508 DramC Write-DBI on
8171 00:59:14.245633 ==
8172 00:59:14.248763 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 00:59:14.255827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 00:59:14.255931 ==
8175 00:59:14.256015
8176 00:59:14.256104
8177 00:59:14.256183 TX Vref Scan disable
8178 00:59:14.259683 == TX Byte 0 ==
8179 00:59:14.263129 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8180 00:59:14.266583 == TX Byte 1 ==
8181 00:59:14.270009 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8182 00:59:14.273309 DramC Write-DBI off
8183 00:59:14.273422
8184 00:59:14.273505 [DATLAT]
8185 00:59:14.273629 Freq=1600, CH0 RK1
8186 00:59:14.273686
8187 00:59:14.276061 DATLAT Default: 0xf
8188 00:59:14.276158 0, 0xFFFF, sum = 0
8189 00:59:14.279467 1, 0xFFFF, sum = 0
8190 00:59:14.282909 2, 0xFFFF, sum = 0
8191 00:59:14.283034 3, 0xFFFF, sum = 0
8192 00:59:14.286143 4, 0xFFFF, sum = 0
8193 00:59:14.286214 5, 0xFFFF, sum = 0
8194 00:59:14.289977 6, 0xFFFF, sum = 0
8195 00:59:14.290047 7, 0xFFFF, sum = 0
8196 00:59:14.293103 8, 0xFFFF, sum = 0
8197 00:59:14.293195 9, 0xFFFF, sum = 0
8198 00:59:14.296490 10, 0xFFFF, sum = 0
8199 00:59:14.296557 11, 0xFFFF, sum = 0
8200 00:59:14.299876 12, 0xFFFF, sum = 0
8201 00:59:14.299953 13, 0xFFFF, sum = 0
8202 00:59:14.303208 14, 0x0, sum = 1
8203 00:59:14.303284 15, 0x0, sum = 2
8204 00:59:14.306362 16, 0x0, sum = 3
8205 00:59:14.306439 17, 0x0, sum = 4
8206 00:59:14.309863 best_step = 15
8207 00:59:14.309971
8208 00:59:14.310163 ==
8209 00:59:14.313166 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 00:59:14.316589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 00:59:14.316666 ==
8212 00:59:14.316725 RX Vref Scan: 0
8213 00:59:14.316779
8214 00:59:14.320021 RX Vref 0 -> 0, step: 1
8215 00:59:14.320126
8216 00:59:14.323012 RX Delay 19 -> 252, step: 4
8217 00:59:14.326720 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8218 00:59:14.332978 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8219 00:59:14.336176 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8220 00:59:14.339641 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8221 00:59:14.342961 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8222 00:59:14.346209 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8223 00:59:14.353085 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8224 00:59:14.355809 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8225 00:59:14.359193 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8226 00:59:14.362481 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8227 00:59:14.366137 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8228 00:59:14.372673 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8229 00:59:14.376269 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8230 00:59:14.379617 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8231 00:59:14.382394 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8232 00:59:14.385875 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8233 00:59:14.389361 ==
8234 00:59:14.392658 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 00:59:14.395506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 00:59:14.395607 ==
8237 00:59:14.395695 DQS Delay:
8238 00:59:14.398891 DQS0 = 0, DQS1 = 0
8239 00:59:14.398990 DQM Delay:
8240 00:59:14.402387 DQM0 = 135, DQM1 = 127
8241 00:59:14.402464 DQ Delay:
8242 00:59:14.405976 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =134
8243 00:59:14.408659 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8244 00:59:14.412072 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8245 00:59:14.415331 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8246 00:59:14.415401
8247 00:59:14.415458
8248 00:59:14.415518
8249 00:59:14.418557 [DramC_TX_OE_Calibration] TA2
8250 00:59:14.422109 Original DQ_B0 (3 6) =30, OEN = 27
8251 00:59:14.425681 Original DQ_B1 (3 6) =30, OEN = 27
8252 00:59:14.428673 24, 0x0, End_B0=24 End_B1=24
8253 00:59:14.432156 25, 0x0, End_B0=25 End_B1=25
8254 00:59:14.432264 26, 0x0, End_B0=26 End_B1=26
8255 00:59:14.435651 27, 0x0, End_B0=27 End_B1=27
8256 00:59:14.438571 28, 0x0, End_B0=28 End_B1=28
8257 00:59:14.442356 29, 0x0, End_B0=29 End_B1=29
8258 00:59:14.445062 30, 0x0, End_B0=30 End_B1=30
8259 00:59:14.445138 31, 0x4141, End_B0=30 End_B1=30
8260 00:59:14.448817 Byte0 end_step=30 best_step=27
8261 00:59:14.452084 Byte1 end_step=30 best_step=27
8262 00:59:14.455292 Byte0 TX OE(2T, 0.5T) = (3, 3)
8263 00:59:14.458641 Byte1 TX OE(2T, 0.5T) = (3, 3)
8264 00:59:14.458734
8265 00:59:14.458816
8266 00:59:14.465208 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8267 00:59:14.468245 CH0 RK1: MR19=303, MR18=2008
8268 00:59:14.475421 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8269 00:59:14.478522 [RxdqsGatingPostProcess] freq 1600
8270 00:59:14.485340 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8271 00:59:14.485446 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 00:59:14.488728 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 00:59:14.491569 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 00:59:14.494822 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 00:59:14.498244 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 00:59:14.501718 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 00:59:14.505070 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 00:59:14.508378 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 00:59:14.511832 Pre-setting of DQS Precalculation
8280 00:59:14.514653 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8281 00:59:14.514726 ==
8282 00:59:14.518100 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 00:59:14.525075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 00:59:14.525161 ==
8285 00:59:14.528318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 00:59:14.534904 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 00:59:14.538322 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 00:59:14.544946 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 00:59:14.552303 [CA 0] Center 41 (12~71) winsize 60
8290 00:59:14.555708 [CA 1] Center 41 (12~71) winsize 60
8291 00:59:14.558931 [CA 2] Center 38 (9~68) winsize 60
8292 00:59:14.562677 [CA 3] Center 37 (8~66) winsize 59
8293 00:59:14.565744 [CA 4] Center 38 (9~67) winsize 59
8294 00:59:14.569152 [CA 5] Center 36 (7~66) winsize 60
8295 00:59:14.569226
8296 00:59:14.572630 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8297 00:59:14.572706
8298 00:59:14.576080 [CATrainingPosCal] consider 1 rank data
8299 00:59:14.579170 u2DelayCellTimex100 = 290/100 ps
8300 00:59:14.582605 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8301 00:59:14.589320 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8302 00:59:14.592565 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8303 00:59:14.595924 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8304 00:59:14.599333 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8305 00:59:14.603069 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 00:59:14.603245
8307 00:59:14.606206 CA PerBit enable=1, Macro0, CA PI delay=36
8308 00:59:14.606346
8309 00:59:14.609598 [CBTSetCACLKResult] CA Dly = 36
8310 00:59:14.609668 CS Dly: 11 (0~42)
8311 00:59:14.615770 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 00:59:14.619107 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 00:59:14.619184 ==
8314 00:59:14.622475 Dram Type= 6, Freq= 0, CH_1, rank 1
8315 00:59:14.625974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 00:59:14.626069 ==
8317 00:59:14.632442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 00:59:14.635712 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 00:59:14.642405 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 00:59:14.645806 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 00:59:14.655805 [CA 0] Center 42 (13~72) winsize 60
8322 00:59:14.659326 [CA 1] Center 41 (12~71) winsize 60
8323 00:59:14.662714 [CA 2] Center 38 (9~68) winsize 60
8324 00:59:14.665500 [CA 3] Center 37 (8~67) winsize 60
8325 00:59:14.669034 [CA 4] Center 38 (8~68) winsize 61
8326 00:59:14.672495 [CA 5] Center 37 (8~67) winsize 60
8327 00:59:14.672633
8328 00:59:14.675769 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8329 00:59:14.675850
8330 00:59:14.679340 [CATrainingPosCal] consider 2 rank data
8331 00:59:14.682624 u2DelayCellTimex100 = 290/100 ps
8332 00:59:14.685784 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8333 00:59:14.692111 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8334 00:59:14.695987 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8335 00:59:14.698989 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8336 00:59:14.702397 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8337 00:59:14.705527 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8338 00:59:14.705661
8339 00:59:14.709155 CA PerBit enable=1, Macro0, CA PI delay=37
8340 00:59:14.709220
8341 00:59:14.712402 [CBTSetCACLKResult] CA Dly = 37
8342 00:59:14.715265 CS Dly: 12 (0~44)
8343 00:59:14.718830 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 00:59:14.721953 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 00:59:14.722028
8346 00:59:14.725683 ----->DramcWriteLeveling(PI) begin...
8347 00:59:14.725758 ==
8348 00:59:14.728847 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 00:59:14.735311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 00:59:14.735393 ==
8351 00:59:14.738708 Write leveling (Byte 0): 25 => 25
8352 00:59:14.738777 Write leveling (Byte 1): 26 => 26
8353 00:59:14.742012 DramcWriteLeveling(PI) end<-----
8354 00:59:14.742101
8355 00:59:14.742161 ==
8356 00:59:14.745416 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 00:59:14.752107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 00:59:14.752217 ==
8359 00:59:14.755405 [Gating] SW mode calibration
8360 00:59:14.761802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8361 00:59:14.765342 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8362 00:59:14.772202 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 00:59:14.774971 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 00:59:14.778524 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8365 00:59:14.785296 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8366 00:59:14.788723 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 00:59:14.792037 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 00:59:14.798514 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 00:59:14.802034 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 00:59:14.805331 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 00:59:14.808571 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 00:59:14.815288 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8373 00:59:14.818598 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8374 00:59:14.822100 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8375 00:59:14.828212 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 00:59:14.831559 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 00:59:14.835202 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 00:59:14.841887 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 00:59:14.844976 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 00:59:14.848375 1 6 8 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
8381 00:59:14.855349 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 00:59:14.858278 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 00:59:14.861516 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 00:59:14.868691 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 00:59:14.871973 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 00:59:14.875322 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 00:59:14.881492 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 00:59:14.884942 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 00:59:14.888396 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 00:59:14.894578 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 00:59:14.898006 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 00:59:14.901244 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 00:59:14.908337 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 00:59:14.911079 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 00:59:14.914951 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 00:59:14.921542 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 00:59:14.924715 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 00:59:14.927994 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 00:59:14.934915 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 00:59:14.937565 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 00:59:14.941420 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 00:59:14.947525 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 00:59:14.950929 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 00:59:14.954380 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8405 00:59:14.961169 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 00:59:14.964472 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 00:59:14.967626 Total UI for P1: 0, mck2ui 16
8408 00:59:14.971298 best dqsien dly found for B0: ( 1, 9, 10)
8409 00:59:14.974310 Total UI for P1: 0, mck2ui 16
8410 00:59:14.977748 best dqsien dly found for B1: ( 1, 9, 10)
8411 00:59:14.981511 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8412 00:59:14.984647 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8413 00:59:14.984714
8414 00:59:14.987421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8415 00:59:14.990986 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8416 00:59:14.994037 [Gating] SW calibration Done
8417 00:59:14.994116 ==
8418 00:59:14.997675 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 00:59:15.001062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 00:59:15.001171 ==
8421 00:59:15.004338 RX Vref Scan: 0
8422 00:59:15.004414
8423 00:59:15.007760 RX Vref 0 -> 0, step: 1
8424 00:59:15.007862
8425 00:59:15.007963 RX Delay 0 -> 252, step: 8
8426 00:59:15.014166 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8427 00:59:15.017413 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8428 00:59:15.020788 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8429 00:59:15.024271 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8430 00:59:15.027637 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8431 00:59:15.034011 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8432 00:59:15.037224 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8433 00:59:15.040594 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8434 00:59:15.043909 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8435 00:59:15.047309 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8436 00:59:15.053977 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8437 00:59:15.057366 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8438 00:59:15.060686 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8439 00:59:15.064133 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8440 00:59:15.067549 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8441 00:59:15.073717 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8442 00:59:15.073797 ==
8443 00:59:15.077142 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 00:59:15.080499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 00:59:15.080602 ==
8446 00:59:15.080690 DQS Delay:
8447 00:59:15.083997 DQS0 = 0, DQS1 = 0
8448 00:59:15.084101 DQM Delay:
8449 00:59:15.087319 DQM0 = 136, DQM1 = 133
8450 00:59:15.087394 DQ Delay:
8451 00:59:15.090614 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8452 00:59:15.093993 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8453 00:59:15.097303 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127
8454 00:59:15.100430 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8455 00:59:15.100528
8456 00:59:15.100619
8457 00:59:15.104161 ==
8458 00:59:15.107472 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 00:59:15.110468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 00:59:15.110558 ==
8461 00:59:15.110649
8462 00:59:15.110745
8463 00:59:15.113525 TX Vref Scan disable
8464 00:59:15.113665 == TX Byte 0 ==
8465 00:59:15.120114 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8466 00:59:15.123753 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8467 00:59:15.123829 == TX Byte 1 ==
8468 00:59:15.130027 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8469 00:59:15.133930 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8470 00:59:15.134001 ==
8471 00:59:15.137071 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 00:59:15.140218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 00:59:15.140299 ==
8474 00:59:15.153267
8475 00:59:15.156585 TX Vref early break, caculate TX vref
8476 00:59:15.160099 TX Vref=16, minBit 0, minWin=22, winSum=378
8477 00:59:15.162728 TX Vref=18, minBit 1, minWin=23, winSum=393
8478 00:59:15.166227 TX Vref=20, minBit 0, minWin=24, winSum=402
8479 00:59:15.169635 TX Vref=22, minBit 0, minWin=25, winSum=411
8480 00:59:15.173005 TX Vref=24, minBit 1, minWin=25, winSum=415
8481 00:59:15.179403 TX Vref=26, minBit 1, minWin=25, winSum=427
8482 00:59:15.182674 TX Vref=28, minBit 0, minWin=25, winSum=429
8483 00:59:15.185946 TX Vref=30, minBit 0, minWin=24, winSum=417
8484 00:59:15.189332 TX Vref=32, minBit 0, minWin=24, winSum=413
8485 00:59:15.192641 TX Vref=34, minBit 0, minWin=24, winSum=405
8486 00:59:15.199328 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8487 00:59:15.199440
8488 00:59:15.202717 Final TX Range 0 Vref 28
8489 00:59:15.202787
8490 00:59:15.202846 ==
8491 00:59:15.206363 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 00:59:15.209719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 00:59:15.209817 ==
8494 00:59:15.209905
8495 00:59:15.209997
8496 00:59:15.212786 TX Vref Scan disable
8497 00:59:15.219464 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8498 00:59:15.219542 == TX Byte 0 ==
8499 00:59:15.222963 u2DelayCellOfst[0]=16 cells (5 PI)
8500 00:59:15.226303 u2DelayCellOfst[1]=10 cells (3 PI)
8501 00:59:15.229530 u2DelayCellOfst[2]=0 cells (0 PI)
8502 00:59:15.232672 u2DelayCellOfst[3]=3 cells (1 PI)
8503 00:59:15.236253 u2DelayCellOfst[4]=6 cells (2 PI)
8504 00:59:15.239118 u2DelayCellOfst[5]=16 cells (5 PI)
8505 00:59:15.242997 u2DelayCellOfst[6]=16 cells (5 PI)
8506 00:59:15.243097 u2DelayCellOfst[7]=3 cells (1 PI)
8507 00:59:15.249374 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8508 00:59:15.252458 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8509 00:59:15.252552 == TX Byte 1 ==
8510 00:59:15.256100 u2DelayCellOfst[8]=0 cells (0 PI)
8511 00:59:15.258980 u2DelayCellOfst[9]=3 cells (1 PI)
8512 00:59:15.262480 u2DelayCellOfst[10]=13 cells (4 PI)
8513 00:59:15.265940 u2DelayCellOfst[11]=6 cells (2 PI)
8514 00:59:15.268919 u2DelayCellOfst[12]=16 cells (5 PI)
8515 00:59:15.272418 u2DelayCellOfst[13]=16 cells (5 PI)
8516 00:59:15.275903 u2DelayCellOfst[14]=16 cells (5 PI)
8517 00:59:15.279352 u2DelayCellOfst[15]=16 cells (5 PI)
8518 00:59:15.282690 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8519 00:59:15.289298 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8520 00:59:15.289373 DramC Write-DBI on
8521 00:59:15.289433 ==
8522 00:59:15.292714 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 00:59:15.295444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 00:59:15.298789 ==
8525 00:59:15.298858
8526 00:59:15.298913
8527 00:59:15.298964 TX Vref Scan disable
8528 00:59:15.302177 == TX Byte 0 ==
8529 00:59:15.305967 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8530 00:59:15.309331 == TX Byte 1 ==
8531 00:59:15.312042 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8532 00:59:15.312132 DramC Write-DBI off
8533 00:59:15.315510
8534 00:59:15.315581 [DATLAT]
8535 00:59:15.315637 Freq=1600, CH1 RK0
8536 00:59:15.315697
8537 00:59:15.318878 DATLAT Default: 0xf
8538 00:59:15.318958 0, 0xFFFF, sum = 0
8539 00:59:15.322117 1, 0xFFFF, sum = 0
8540 00:59:15.322217 2, 0xFFFF, sum = 0
8541 00:59:15.325408 3, 0xFFFF, sum = 0
8542 00:59:15.325496 4, 0xFFFF, sum = 0
8543 00:59:15.328785 5, 0xFFFF, sum = 0
8544 00:59:15.332164 6, 0xFFFF, sum = 0
8545 00:59:15.332232 7, 0xFFFF, sum = 0
8546 00:59:15.335568 8, 0xFFFF, sum = 0
8547 00:59:15.335636 9, 0xFFFF, sum = 0
8548 00:59:15.338937 10, 0xFFFF, sum = 0
8549 00:59:15.339002 11, 0xFFFF, sum = 0
8550 00:59:15.342406 12, 0xFFFF, sum = 0
8551 00:59:15.342473 13, 0xFFFF, sum = 0
8552 00:59:15.345763 14, 0x0, sum = 1
8553 00:59:15.345829 15, 0x0, sum = 2
8554 00:59:15.349210 16, 0x0, sum = 3
8555 00:59:15.349303 17, 0x0, sum = 4
8556 00:59:15.352511 best_step = 15
8557 00:59:15.352607
8558 00:59:15.352683 ==
8559 00:59:15.355940 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 00:59:15.359188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 00:59:15.359265 ==
8562 00:59:15.359333 RX Vref Scan: 1
8563 00:59:15.359390
8564 00:59:15.362323 Set Vref Range= 24 -> 127
8565 00:59:15.362409
8566 00:59:15.365888 RX Vref 24 -> 127, step: 1
8567 00:59:15.365979
8568 00:59:15.368832 RX Delay 27 -> 252, step: 4
8569 00:59:15.368940
8570 00:59:15.372142 Set Vref, RX VrefLevel [Byte0]: 24
8571 00:59:15.375833 [Byte1]: 24
8572 00:59:15.375920
8573 00:59:15.379050 Set Vref, RX VrefLevel [Byte0]: 25
8574 00:59:15.401118 [Byte1]: 25
8575 00:59:15.401229
8576 00:59:15.401301 Set Vref, RX VrefLevel [Byte0]: 26
8577 00:59:15.401362 [Byte1]: 26
8578 00:59:15.401417
8579 00:59:15.401475 Set Vref, RX VrefLevel [Byte0]: 27
8580 00:59:15.401526 [Byte1]: 27
8581 00:59:15.401627
8582 00:59:15.401678 Set Vref, RX VrefLevel [Byte0]: 28
8583 00:59:15.403510 [Byte1]: 28
8584 00:59:15.407273
8585 00:59:15.407353 Set Vref, RX VrefLevel [Byte0]: 29
8586 00:59:15.410790 [Byte1]: 29
8587 00:59:15.415201
8588 00:59:15.415272 Set Vref, RX VrefLevel [Byte0]: 30
8589 00:59:15.418658 [Byte1]: 30
8590 00:59:15.422733
8591 00:59:15.422842 Set Vref, RX VrefLevel [Byte0]: 31
8592 00:59:15.426151 [Byte1]: 31
8593 00:59:15.430158
8594 00:59:15.430258 Set Vref, RX VrefLevel [Byte0]: 32
8595 00:59:15.433437 [Byte1]: 32
8596 00:59:15.437298
8597 00:59:15.437374 Set Vref, RX VrefLevel [Byte0]: 33
8598 00:59:15.440657 [Byte1]: 33
8599 00:59:15.445421
8600 00:59:15.445487 Set Vref, RX VrefLevel [Byte0]: 34
8601 00:59:15.448809 [Byte1]: 34
8602 00:59:15.452865
8603 00:59:15.452963 Set Vref, RX VrefLevel [Byte0]: 35
8604 00:59:15.456266 [Byte1]: 35
8605 00:59:15.460260
8606 00:59:15.460353 Set Vref, RX VrefLevel [Byte0]: 36
8607 00:59:15.463621 [Byte1]: 36
8608 00:59:15.467768
8609 00:59:15.467857 Set Vref, RX VrefLevel [Byte0]: 37
8610 00:59:15.471139 [Byte1]: 37
8611 00:59:15.475328
8612 00:59:15.475444 Set Vref, RX VrefLevel [Byte0]: 38
8613 00:59:15.478751 [Byte1]: 38
8614 00:59:15.482798
8615 00:59:15.482907 Set Vref, RX VrefLevel [Byte0]: 39
8616 00:59:15.486191 [Byte1]: 39
8617 00:59:15.490646
8618 00:59:15.490732 Set Vref, RX VrefLevel [Byte0]: 40
8619 00:59:15.493832 [Byte1]: 40
8620 00:59:15.498107
8621 00:59:15.498208 Set Vref, RX VrefLevel [Byte0]: 41
8622 00:59:15.501098 [Byte1]: 41
8623 00:59:15.505189
8624 00:59:15.505293 Set Vref, RX VrefLevel [Byte0]: 42
8625 00:59:15.508653 [Byte1]: 42
8626 00:59:15.512790
8627 00:59:15.512889 Set Vref, RX VrefLevel [Byte0]: 43
8628 00:59:15.516170 [Byte1]: 43
8629 00:59:15.520473
8630 00:59:15.520547 Set Vref, RX VrefLevel [Byte0]: 44
8631 00:59:15.524017 [Byte1]: 44
8632 00:59:15.528040
8633 00:59:15.528130 Set Vref, RX VrefLevel [Byte0]: 45
8634 00:59:15.531105 [Byte1]: 45
8635 00:59:15.535625
8636 00:59:15.535721 Set Vref, RX VrefLevel [Byte0]: 46
8637 00:59:15.538917 [Byte1]: 46
8638 00:59:15.543466
8639 00:59:15.543561 Set Vref, RX VrefLevel [Byte0]: 47
8640 00:59:15.546416 [Byte1]: 47
8641 00:59:15.550727
8642 00:59:15.550822 Set Vref, RX VrefLevel [Byte0]: 48
8643 00:59:15.554146 [Byte1]: 48
8644 00:59:15.558252
8645 00:59:15.558344 Set Vref, RX VrefLevel [Byte0]: 49
8646 00:59:15.561711 [Byte1]: 49
8647 00:59:15.565514
8648 00:59:15.565645 Set Vref, RX VrefLevel [Byte0]: 50
8649 00:59:15.568997 [Byte1]: 50
8650 00:59:15.573142
8651 00:59:15.573233 Set Vref, RX VrefLevel [Byte0]: 51
8652 00:59:15.576483 [Byte1]: 51
8653 00:59:15.581063
8654 00:59:15.581186 Set Vref, RX VrefLevel [Byte0]: 52
8655 00:59:15.584347 [Byte1]: 52
8656 00:59:15.588377
8657 00:59:15.588475 Set Vref, RX VrefLevel [Byte0]: 53
8658 00:59:15.591721 [Byte1]: 53
8659 00:59:15.595668
8660 00:59:15.595770 Set Vref, RX VrefLevel [Byte0]: 54
8661 00:59:15.599058 [Byte1]: 54
8662 00:59:15.603108
8663 00:59:15.603205 Set Vref, RX VrefLevel [Byte0]: 55
8664 00:59:15.606365 [Byte1]: 55
8665 00:59:15.610681
8666 00:59:15.610751 Set Vref, RX VrefLevel [Byte0]: 56
8667 00:59:15.614538 [Byte1]: 56
8668 00:59:15.618442
8669 00:59:15.618546 Set Vref, RX VrefLevel [Byte0]: 57
8670 00:59:15.621794 [Byte1]: 57
8671 00:59:15.625970
8672 00:59:15.626069 Set Vref, RX VrefLevel [Byte0]: 58
8673 00:59:15.629202 [Byte1]: 58
8674 00:59:15.633347
8675 00:59:15.633435 Set Vref, RX VrefLevel [Byte0]: 59
8676 00:59:15.636780 [Byte1]: 59
8677 00:59:15.641136
8678 00:59:15.641231 Set Vref, RX VrefLevel [Byte0]: 60
8679 00:59:15.643962 [Byte1]: 60
8680 00:59:15.648287
8681 00:59:15.648392 Set Vref, RX VrefLevel [Byte0]: 61
8682 00:59:15.651954 [Byte1]: 61
8683 00:59:15.655983
8684 00:59:15.656080 Set Vref, RX VrefLevel [Byte0]: 62
8685 00:59:15.659229 [Byte1]: 62
8686 00:59:15.663762
8687 00:59:15.663853 Set Vref, RX VrefLevel [Byte0]: 63
8688 00:59:15.667067 [Byte1]: 63
8689 00:59:15.670928
8690 00:59:15.671025 Set Vref, RX VrefLevel [Byte0]: 64
8691 00:59:15.674401 [Byte1]: 64
8692 00:59:15.678591
8693 00:59:15.678683 Set Vref, RX VrefLevel [Byte0]: 65
8694 00:59:15.682031 [Byte1]: 65
8695 00:59:15.685953
8696 00:59:15.686049 Set Vref, RX VrefLevel [Byte0]: 66
8697 00:59:15.689909 [Byte1]: 66
8698 00:59:15.693945
8699 00:59:15.694037 Set Vref, RX VrefLevel [Byte0]: 67
8700 00:59:15.697341 [Byte1]: 67
8701 00:59:15.701372
8702 00:59:15.701466 Set Vref, RX VrefLevel [Byte0]: 68
8703 00:59:15.704762 [Byte1]: 68
8704 00:59:15.708770
8705 00:59:15.708863 Set Vref, RX VrefLevel [Byte0]: 69
8706 00:59:15.712092 [Byte1]: 69
8707 00:59:15.716079
8708 00:59:15.716162 Set Vref, RX VrefLevel [Byte0]: 70
8709 00:59:15.719967 [Byte1]: 70
8710 00:59:15.723580
8711 00:59:15.723686 Set Vref, RX VrefLevel [Byte0]: 71
8712 00:59:15.727335 [Byte1]: 71
8713 00:59:15.731488
8714 00:59:15.731556 Set Vref, RX VrefLevel [Byte0]: 72
8715 00:59:15.734761 [Byte1]: 72
8716 00:59:15.738998
8717 00:59:15.739068 Set Vref, RX VrefLevel [Byte0]: 73
8718 00:59:15.742438 [Byte1]: 73
8719 00:59:15.746356
8720 00:59:15.746429 Set Vref, RX VrefLevel [Byte0]: 74
8721 00:59:15.749628 [Byte1]: 74
8722 00:59:15.753807
8723 00:59:15.753880 Set Vref, RX VrefLevel [Byte0]: 75
8724 00:59:15.757633 [Byte1]: 75
8725 00:59:15.761663
8726 00:59:15.761734 Set Vref, RX VrefLevel [Byte0]: 76
8727 00:59:15.764950 [Byte1]: 76
8728 00:59:15.768795
8729 00:59:15.768892 Set Vref, RX VrefLevel [Byte0]: 77
8730 00:59:15.772451 [Byte1]: 77
8731 00:59:15.776725
8732 00:59:15.776821 Final RX Vref Byte 0 = 59 to rank0
8733 00:59:15.779703 Final RX Vref Byte 1 = 55 to rank0
8734 00:59:15.783181 Final RX Vref Byte 0 = 59 to rank1
8735 00:59:15.786607 Final RX Vref Byte 1 = 55 to rank1==
8736 00:59:15.790203 Dram Type= 6, Freq= 0, CH_1, rank 0
8737 00:59:15.793812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 00:59:15.796859 ==
8739 00:59:15.796962 DQS Delay:
8740 00:59:15.797059 DQS0 = 0, DQS1 = 0
8741 00:59:15.800280 DQM Delay:
8742 00:59:15.800349 DQM0 = 134, DQM1 = 131
8743 00:59:15.803610 DQ Delay:
8744 00:59:15.806384 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8745 00:59:15.809957 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8746 00:59:15.813387 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8747 00:59:15.816781 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8748 00:59:15.816849
8749 00:59:15.816919
8750 00:59:15.817009
8751 00:59:15.820250 [DramC_TX_OE_Calibration] TA2
8752 00:59:15.823738 Original DQ_B0 (3 6) =30, OEN = 27
8753 00:59:15.826408 Original DQ_B1 (3 6) =30, OEN = 27
8754 00:59:15.830439 24, 0x0, End_B0=24 End_B1=24
8755 00:59:15.830527 25, 0x0, End_B0=25 End_B1=25
8756 00:59:15.833498 26, 0x0, End_B0=26 End_B1=26
8757 00:59:15.836568 27, 0x0, End_B0=27 End_B1=27
8758 00:59:15.840307 28, 0x0, End_B0=28 End_B1=28
8759 00:59:15.840421 29, 0x0, End_B0=29 End_B1=29
8760 00:59:15.843023 30, 0x0, End_B0=30 End_B1=30
8761 00:59:15.846476 31, 0x4141, End_B0=30 End_B1=30
8762 00:59:15.849948 Byte0 end_step=30 best_step=27
8763 00:59:15.853159 Byte1 end_step=30 best_step=27
8764 00:59:15.856467 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 00:59:15.856543 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 00:59:15.856606
8767 00:59:15.860113
8768 00:59:15.866627 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8769 00:59:15.869962 CH1 RK0: MR19=303, MR18=1927
8770 00:59:15.876743 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8771 00:59:15.876847
8772 00:59:15.880090 ----->DramcWriteLeveling(PI) begin...
8773 00:59:15.880159 ==
8774 00:59:15.883507 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 00:59:15.886807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 00:59:15.886879 ==
8777 00:59:15.890062 Write leveling (Byte 0): 26 => 26
8778 00:59:15.893322 Write leveling (Byte 1): 30 => 30
8779 00:59:15.896624 DramcWriteLeveling(PI) end<-----
8780 00:59:15.896735
8781 00:59:15.896865 ==
8782 00:59:15.899757 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 00:59:15.903352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 00:59:15.903444 ==
8785 00:59:15.906219 [Gating] SW mode calibration
8786 00:59:15.913341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8787 00:59:15.919692 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8788 00:59:15.922810 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 00:59:15.926146 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 00:59:15.932950 1 4 8 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
8791 00:59:15.936420 1 4 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
8792 00:59:15.939741 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 00:59:15.946183 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 00:59:15.949170 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 00:59:15.952987 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 00:59:15.959204 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 00:59:15.962754 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8798 00:59:15.966257 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8799 00:59:15.972761 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8800 00:59:15.975904 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8801 00:59:15.979386 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 00:59:15.986020 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 00:59:15.989469 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 00:59:15.992814 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 00:59:15.999502 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 00:59:16.002439 1 6 8 | B1->B0 | 3635 2323 | 1 0 | (0 0) (0 0)
8807 00:59:16.005883 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 00:59:16.009432 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 00:59:16.015803 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 00:59:16.019067 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 00:59:16.022812 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 00:59:16.029339 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 00:59:16.032716 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8814 00:59:16.036354 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8815 00:59:16.042808 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8816 00:59:16.045932 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8817 00:59:16.049323 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 00:59:16.056034 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 00:59:16.059198 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 00:59:16.062952 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 00:59:16.068979 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 00:59:16.072324 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 00:59:16.075828 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 00:59:16.082650 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 00:59:16.086376 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 00:59:16.089481 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 00:59:16.096142 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 00:59:16.099516 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 00:59:16.102928 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8830 00:59:16.109063 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8831 00:59:16.112447 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8832 00:59:16.115819 Total UI for P1: 0, mck2ui 16
8833 00:59:16.119112 best dqsien dly found for B1: ( 1, 9, 6)
8834 00:59:16.122485 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 00:59:16.125908 Total UI for P1: 0, mck2ui 16
8836 00:59:16.129378 best dqsien dly found for B0: ( 1, 9, 10)
8837 00:59:16.132696 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8838 00:59:16.136131 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8839 00:59:16.136225
8840 00:59:16.139265 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8841 00:59:16.145411 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8842 00:59:16.145508 [Gating] SW calibration Done
8843 00:59:16.145602 ==
8844 00:59:16.149301 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 00:59:16.155740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 00:59:16.155840 ==
8847 00:59:16.155928 RX Vref Scan: 0
8848 00:59:16.156010
8849 00:59:16.159027 RX Vref 0 -> 0, step: 1
8850 00:59:16.159123
8851 00:59:16.162026 RX Delay 0 -> 252, step: 8
8852 00:59:16.165683 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8853 00:59:16.168713 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8854 00:59:16.172378 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8855 00:59:16.175503 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8856 00:59:16.182182 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8857 00:59:16.185395 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8858 00:59:16.188742 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8859 00:59:16.192041 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8860 00:59:16.195458 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8861 00:59:16.202392 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8862 00:59:16.205324 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8863 00:59:16.208360 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8864 00:59:16.211764 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8865 00:59:16.218955 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8866 00:59:16.221666 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8867 00:59:16.225085 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8868 00:59:16.225181 ==
8869 00:59:16.228437 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 00:59:16.231857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 00:59:16.231948 ==
8872 00:59:16.235224 DQS Delay:
8873 00:59:16.235325 DQS0 = 0, DQS1 = 0
8874 00:59:16.238645 DQM Delay:
8875 00:59:16.238741 DQM0 = 136, DQM1 = 133
8876 00:59:16.238827 DQ Delay:
8877 00:59:16.242238 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8878 00:59:16.245499 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8879 00:59:16.252239 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8880 00:59:16.255317 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8881 00:59:16.255418
8882 00:59:16.255505
8883 00:59:16.255589 ==
8884 00:59:16.258741 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 00:59:16.262196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 00:59:16.262294 ==
8887 00:59:16.262381
8888 00:59:16.262462
8889 00:59:16.264878 TX Vref Scan disable
8890 00:59:16.268172 == TX Byte 0 ==
8891 00:59:16.271574 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8892 00:59:16.274888 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8893 00:59:16.278504 == TX Byte 1 ==
8894 00:59:16.281527 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8895 00:59:16.285457 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8896 00:59:16.285561 ==
8897 00:59:16.288348 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 00:59:16.291663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 00:59:16.295001 ==
8900 00:59:16.307249
8901 00:59:16.310582 TX Vref early break, caculate TX vref
8902 00:59:16.314044 TX Vref=16, minBit 0, minWin=23, winSum=383
8903 00:59:16.317371 TX Vref=18, minBit 0, minWin=24, winSum=393
8904 00:59:16.320569 TX Vref=20, minBit 0, minWin=24, winSum=401
8905 00:59:16.323984 TX Vref=22, minBit 0, minWin=24, winSum=408
8906 00:59:16.327554 TX Vref=24, minBit 0, minWin=25, winSum=420
8907 00:59:16.334162 TX Vref=26, minBit 0, minWin=25, winSum=426
8908 00:59:16.337555 TX Vref=28, minBit 0, minWin=25, winSum=423
8909 00:59:16.340972 TX Vref=30, minBit 6, minWin=24, winSum=416
8910 00:59:16.343795 TX Vref=32, minBit 6, minWin=24, winSum=409
8911 00:59:16.347359 TX Vref=34, minBit 0, minWin=24, winSum=405
8912 00:59:16.350662 TX Vref=36, minBit 5, minWin=23, winSum=396
8913 00:59:16.357244 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8914 00:59:16.357326
8915 00:59:16.360517 Final TX Range 0 Vref 26
8916 00:59:16.360591
8917 00:59:16.360649 ==
8918 00:59:16.363823 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 00:59:16.367263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 00:59:16.367339 ==
8921 00:59:16.367415
8922 00:59:16.367494
8923 00:59:16.370895 TX Vref Scan disable
8924 00:59:16.377011 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8925 00:59:16.377085 == TX Byte 0 ==
8926 00:59:16.380479 u2DelayCellOfst[0]=16 cells (5 PI)
8927 00:59:16.383784 u2DelayCellOfst[1]=10 cells (3 PI)
8928 00:59:16.387057 u2DelayCellOfst[2]=0 cells (0 PI)
8929 00:59:16.390609 u2DelayCellOfst[3]=3 cells (1 PI)
8930 00:59:16.394003 u2DelayCellOfst[4]=6 cells (2 PI)
8931 00:59:16.397287 u2DelayCellOfst[5]=16 cells (5 PI)
8932 00:59:16.400484 u2DelayCellOfst[6]=16 cells (5 PI)
8933 00:59:16.403799 u2DelayCellOfst[7]=3 cells (1 PI)
8934 00:59:16.406976 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8935 00:59:16.410579 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8936 00:59:16.413889 == TX Byte 1 ==
8937 00:59:16.413970 u2DelayCellOfst[8]=0 cells (0 PI)
8938 00:59:16.417318 u2DelayCellOfst[9]=3 cells (1 PI)
8939 00:59:16.420740 u2DelayCellOfst[10]=10 cells (3 PI)
8940 00:59:16.423422 u2DelayCellOfst[11]=6 cells (2 PI)
8941 00:59:16.427049 u2DelayCellOfst[12]=13 cells (4 PI)
8942 00:59:16.430632 u2DelayCellOfst[13]=13 cells (4 PI)
8943 00:59:16.433784 u2DelayCellOfst[14]=16 cells (5 PI)
8944 00:59:16.436672 u2DelayCellOfst[15]=16 cells (5 PI)
8945 00:59:16.440421 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8946 00:59:16.446956 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8947 00:59:16.447057 DramC Write-DBI on
8948 00:59:16.447155 ==
8949 00:59:16.450357 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 00:59:16.453634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 00:59:16.457054 ==
8952 00:59:16.457132
8953 00:59:16.457226
8954 00:59:16.457318 TX Vref Scan disable
8955 00:59:16.460524 == TX Byte 0 ==
8956 00:59:16.463776 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8957 00:59:16.466947 == TX Byte 1 ==
8958 00:59:16.470150 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8959 00:59:16.473466 DramC Write-DBI off
8960 00:59:16.473571
8961 00:59:16.473634 [DATLAT]
8962 00:59:16.473691 Freq=1600, CH1 RK1
8963 00:59:16.473746
8964 00:59:16.476919 DATLAT Default: 0xf
8965 00:59:16.477019 0, 0xFFFF, sum = 0
8966 00:59:16.480360 1, 0xFFFF, sum = 0
8967 00:59:16.483828 2, 0xFFFF, sum = 0
8968 00:59:16.483932 3, 0xFFFF, sum = 0
8969 00:59:16.487147 4, 0xFFFF, sum = 0
8970 00:59:16.487252 5, 0xFFFF, sum = 0
8971 00:59:16.489845 6, 0xFFFF, sum = 0
8972 00:59:16.489926 7, 0xFFFF, sum = 0
8973 00:59:16.493733 8, 0xFFFF, sum = 0
8974 00:59:16.493811 9, 0xFFFF, sum = 0
8975 00:59:16.496522 10, 0xFFFF, sum = 0
8976 00:59:16.496624 11, 0xFFFF, sum = 0
8977 00:59:16.500017 12, 0xFFFF, sum = 0
8978 00:59:16.500096 13, 0xFFFF, sum = 0
8979 00:59:16.503493 14, 0x0, sum = 1
8980 00:59:16.503571 15, 0x0, sum = 2
8981 00:59:16.506758 16, 0x0, sum = 3
8982 00:59:16.506838 17, 0x0, sum = 4
8983 00:59:16.510163 best_step = 15
8984 00:59:16.510244
8985 00:59:16.510304 ==
8986 00:59:16.513517 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 00:59:16.516823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 00:59:16.516924 ==
8989 00:59:16.520340 RX Vref Scan: 0
8990 00:59:16.520417
8991 00:59:16.520476 RX Vref 0 -> 0, step: 1
8992 00:59:16.520531
8993 00:59:16.523059 RX Delay 19 -> 252, step: 4
8994 00:59:16.526913 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8995 00:59:16.533250 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8996 00:59:16.536905 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
8997 00:59:16.540021 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8998 00:59:16.543063 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8999 00:59:16.546634 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9000 00:59:16.553209 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9001 00:59:16.556560 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9002 00:59:16.560044 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9003 00:59:16.563241 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9004 00:59:16.566303 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9005 00:59:16.573170 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9006 00:59:16.576156 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9007 00:59:16.579936 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9008 00:59:16.583079 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9009 00:59:16.586427 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9010 00:59:16.589815 ==
9011 00:59:16.589889 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 00:59:16.596741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 00:59:16.596816 ==
9014 00:59:16.596891 DQS Delay:
9015 00:59:16.599993 DQS0 = 0, DQS1 = 0
9016 00:59:16.600065 DQM Delay:
9017 00:59:16.602829 DQM0 = 134, DQM1 = 130
9018 00:59:16.602897 DQ Delay:
9019 00:59:16.606331 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =130
9020 00:59:16.609704 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9021 00:59:16.613079 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9022 00:59:16.616417 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9023 00:59:16.616485
9024 00:59:16.616574
9025 00:59:16.616668
9026 00:59:16.619735 [DramC_TX_OE_Calibration] TA2
9027 00:59:16.623202 Original DQ_B0 (3 6) =30, OEN = 27
9028 00:59:16.625990 Original DQ_B1 (3 6) =30, OEN = 27
9029 00:59:16.629257 24, 0x0, End_B0=24 End_B1=24
9030 00:59:16.632749 25, 0x0, End_B0=25 End_B1=25
9031 00:59:16.632827 26, 0x0, End_B0=26 End_B1=26
9032 00:59:16.636029 27, 0x0, End_B0=27 End_B1=27
9033 00:59:16.639278 28, 0x0, End_B0=28 End_B1=28
9034 00:59:16.642599 29, 0x0, End_B0=29 End_B1=29
9035 00:59:16.642677 30, 0x0, End_B0=30 End_B1=30
9036 00:59:16.646134 31, 0x4141, End_B0=30 End_B1=30
9037 00:59:16.649321 Byte0 end_step=30 best_step=27
9038 00:59:16.653269 Byte1 end_step=30 best_step=27
9039 00:59:16.656055 Byte0 TX OE(2T, 0.5T) = (3, 3)
9040 00:59:16.659299 Byte1 TX OE(2T, 0.5T) = (3, 3)
9041 00:59:16.659386
9042 00:59:16.659459
9043 00:59:16.666053 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9044 00:59:16.669363 CH1 RK1: MR19=303, MR18=2409
9045 00:59:16.675842 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9046 00:59:16.679413 [RxdqsGatingPostProcess] freq 1600
9047 00:59:16.686154 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9048 00:59:16.686231 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 00:59:16.688976 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 00:59:16.692167 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 00:59:16.695666 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 00:59:16.699067 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 00:59:16.702526 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 00:59:16.705402 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 00:59:16.709062 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 00:59:16.712310 Pre-setting of DQS Precalculation
9057 00:59:16.715602 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9058 00:59:16.725705 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9059 00:59:16.732489 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9060 00:59:16.732567
9061 00:59:16.732672
9062 00:59:16.735369 [Calibration Summary] 3200 Mbps
9063 00:59:16.735450 CH 0, Rank 0
9064 00:59:16.738787 SW Impedance : PASS
9065 00:59:16.738877 DUTY Scan : NO K
9066 00:59:16.742270 ZQ Calibration : PASS
9067 00:59:16.745459 Jitter Meter : NO K
9068 00:59:16.745580 CBT Training : PASS
9069 00:59:16.748934 Write leveling : PASS
9070 00:59:16.752218 RX DQS gating : PASS
9071 00:59:16.752294 RX DQ/DQS(RDDQC) : PASS
9072 00:59:16.755566 TX DQ/DQS : PASS
9073 00:59:16.759150 RX DATLAT : PASS
9074 00:59:16.759227 RX DQ/DQS(Engine): PASS
9075 00:59:16.761889 TX OE : PASS
9076 00:59:16.761966 All Pass.
9077 00:59:16.762041
9078 00:59:16.762111 CH 0, Rank 1
9079 00:59:16.765253 SW Impedance : PASS
9080 00:59:16.768505 DUTY Scan : NO K
9081 00:59:16.768581 ZQ Calibration : PASS
9082 00:59:16.772239 Jitter Meter : NO K
9083 00:59:16.775588 CBT Training : PASS
9084 00:59:16.775664 Write leveling : PASS
9085 00:59:16.778455 RX DQS gating : PASS
9086 00:59:16.781763 RX DQ/DQS(RDDQC) : PASS
9087 00:59:16.781840 TX DQ/DQS : PASS
9088 00:59:16.785176 RX DATLAT : PASS
9089 00:59:16.788462 RX DQ/DQS(Engine): PASS
9090 00:59:16.788538 TX OE : PASS
9091 00:59:16.791642 All Pass.
9092 00:59:16.791718
9093 00:59:16.791803 CH 1, Rank 0
9094 00:59:16.795019 SW Impedance : PASS
9095 00:59:16.795096 DUTY Scan : NO K
9096 00:59:16.798191 ZQ Calibration : PASS
9097 00:59:16.802077 Jitter Meter : NO K
9098 00:59:16.802153 CBT Training : PASS
9099 00:59:16.805434 Write leveling : PASS
9100 00:59:16.808655 RX DQS gating : PASS
9101 00:59:16.808732 RX DQ/DQS(RDDQC) : PASS
9102 00:59:16.811780 TX DQ/DQS : PASS
9103 00:59:16.811856 RX DATLAT : PASS
9104 00:59:16.815450 RX DQ/DQS(Engine): PASS
9105 00:59:16.818439 TX OE : PASS
9106 00:59:16.818515 All Pass.
9107 00:59:16.818573
9108 00:59:16.818627 CH 1, Rank 1
9109 00:59:16.822049 SW Impedance : PASS
9110 00:59:16.824996 DUTY Scan : NO K
9111 00:59:16.825071 ZQ Calibration : PASS
9112 00:59:16.828397 Jitter Meter : NO K
9113 00:59:16.832064 CBT Training : PASS
9114 00:59:16.832142 Write leveling : PASS
9115 00:59:16.835488 RX DQS gating : PASS
9116 00:59:16.838194 RX DQ/DQS(RDDQC) : PASS
9117 00:59:16.838271 TX DQ/DQS : PASS
9118 00:59:16.841532 RX DATLAT : PASS
9119 00:59:16.844909 RX DQ/DQS(Engine): PASS
9120 00:59:16.844987 TX OE : PASS
9121 00:59:16.848245 All Pass.
9122 00:59:16.848322
9123 00:59:16.848399 DramC Write-DBI on
9124 00:59:16.851616 PER_BANK_REFRESH: Hybrid Mode
9125 00:59:16.851694 TX_TRACKING: ON
9126 00:59:16.861822 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9127 00:59:16.868105 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9128 00:59:16.878214 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9129 00:59:16.881631 [FAST_K] Save calibration result to emmc
9130 00:59:16.884984 sync common calibartion params.
9131 00:59:16.885084 sync cbt_mode0:1, 1:1
9132 00:59:16.887889 dram_init: ddr_geometry: 2
9133 00:59:16.891336 dram_init: ddr_geometry: 2
9134 00:59:16.891430 dram_init: ddr_geometry: 2
9135 00:59:16.894588 0:dram_rank_size:100000000
9136 00:59:16.898570 1:dram_rank_size:100000000
9137 00:59:16.904795 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9138 00:59:16.904909 DFS_SHUFFLE_HW_MODE: ON
9139 00:59:16.908062 dramc_set_vcore_voltage set vcore to 725000
9140 00:59:16.911576 Read voltage for 1600, 0
9141 00:59:16.911669 Vio18 = 0
9142 00:59:16.915007 Vcore = 725000
9143 00:59:16.915075 Vdram = 0
9144 00:59:16.915130 Vddq = 0
9145 00:59:16.918265 Vmddr = 0
9146 00:59:16.918329 switch to 3200 Mbps bootup
9147 00:59:16.921623 [DramcRunTimeConfig]
9148 00:59:16.921692 PHYPLL
9149 00:59:16.924773 DPM_CONTROL_AFTERK: ON
9150 00:59:16.924869 PER_BANK_REFRESH: ON
9151 00:59:16.928127 REFRESH_OVERHEAD_REDUCTION: ON
9152 00:59:16.931445 CMD_PICG_NEW_MODE: OFF
9153 00:59:16.931541 XRTWTW_NEW_MODE: ON
9154 00:59:16.934640 XRTRTR_NEW_MODE: ON
9155 00:59:16.934718 TX_TRACKING: ON
9156 00:59:16.937747 RDSEL_TRACKING: OFF
9157 00:59:16.941319 DQS Precalculation for DVFS: ON
9158 00:59:16.941390 RX_TRACKING: OFF
9159 00:59:16.944962 HW_GATING DBG: ON
9160 00:59:16.945063 ZQCS_ENABLE_LP4: ON
9161 00:59:16.947949 RX_PICG_NEW_MODE: ON
9162 00:59:16.948039 TX_PICG_NEW_MODE: ON
9163 00:59:16.951350 ENABLE_RX_DCM_DPHY: ON
9164 00:59:16.955004 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9165 00:59:16.958369 DUMMY_READ_FOR_TRACKING: OFF
9166 00:59:16.958467 !!! SPM_CONTROL_AFTERK: OFF
9167 00:59:16.961696 !!! SPM could not control APHY
9168 00:59:16.964975 IMPEDANCE_TRACKING: ON
9169 00:59:16.965066 TEMP_SENSOR: ON
9170 00:59:16.968449 HW_SAVE_FOR_SR: OFF
9171 00:59:16.971151 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9172 00:59:16.975206 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9173 00:59:16.975297 Read ODT Tracking: ON
9174 00:59:16.977943 Refresh Rate DeBounce: ON
9175 00:59:16.981376 DFS_NO_QUEUE_FLUSH: ON
9176 00:59:16.984924 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9177 00:59:16.985020 ENABLE_DFS_RUNTIME_MRW: OFF
9178 00:59:16.988532 DDR_RESERVE_NEW_MODE: ON
9179 00:59:16.991589 MR_CBT_SWITCH_FREQ: ON
9180 00:59:16.991657 =========================
9181 00:59:17.011235 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9182 00:59:17.014496 dram_init: ddr_geometry: 2
9183 00:59:17.032947 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9184 00:59:17.036345 dram_init: dram init end (result: 0)
9185 00:59:17.043281 DRAM-K: Full calibration passed in 24491 msecs
9186 00:59:17.046531 MRC: failed to locate region type 0.
9187 00:59:17.046629 DRAM rank0 size:0x100000000,
9188 00:59:17.049703 DRAM rank1 size=0x100000000
9189 00:59:17.059475 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9190 00:59:17.066331 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9191 00:59:17.072641 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9192 00:59:17.079232 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9193 00:59:17.082682 DRAM rank0 size:0x100000000,
9194 00:59:17.086035 DRAM rank1 size=0x100000000
9195 00:59:17.086111 CBMEM:
9196 00:59:17.089502 IMD: root @ 0xfffff000 254 entries.
9197 00:59:17.092983 IMD: root @ 0xffffec00 62 entries.
9198 00:59:17.096338 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9199 00:59:17.099605 WARNING: RO_VPD is uninitialized or empty.
9200 00:59:17.106071 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9201 00:59:17.113156 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9202 00:59:17.125650 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9203 00:59:17.136978 BS: romstage times (exec / console): total (unknown) / 24015 ms
9204 00:59:17.137081
9205 00:59:17.137174
9206 00:59:17.147103 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9207 00:59:17.150415 ARM64: Exception handlers installed.
9208 00:59:17.153815 ARM64: Testing exception
9209 00:59:17.157130 ARM64: Done test exception
9210 00:59:17.157227 Enumerating buses...
9211 00:59:17.160473 Show all devs... Before device enumeration.
9212 00:59:17.163862 Root Device: enabled 1
9213 00:59:17.167211 CPU_CLUSTER: 0: enabled 1
9214 00:59:17.167302 CPU: 00: enabled 1
9215 00:59:17.170693 Compare with tree...
9216 00:59:17.170783 Root Device: enabled 1
9217 00:59:17.174183 CPU_CLUSTER: 0: enabled 1
9218 00:59:17.176807 CPU: 00: enabled 1
9219 00:59:17.176898 Root Device scanning...
9220 00:59:17.180602 scan_static_bus for Root Device
9221 00:59:17.183640 CPU_CLUSTER: 0 enabled
9222 00:59:17.187311 scan_static_bus for Root Device done
9223 00:59:17.190410 scan_bus: bus Root Device finished in 8 msecs
9224 00:59:17.190507 done
9225 00:59:17.197102 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9226 00:59:17.200496 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9227 00:59:17.206788 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9228 00:59:17.210200 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9229 00:59:17.213483 Allocating resources...
9230 00:59:17.216741 Reading resources...
9231 00:59:17.220682 Root Device read_resources bus 0 link: 0
9232 00:59:17.220778 DRAM rank0 size:0x100000000,
9233 00:59:17.223734 DRAM rank1 size=0x100000000
9234 00:59:17.226560 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9235 00:59:17.230183 CPU: 00 missing read_resources
9236 00:59:17.233723 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9237 00:59:17.240306 Root Device read_resources bus 0 link: 0 done
9238 00:59:17.240378 Done reading resources.
9239 00:59:17.246840 Show resources in subtree (Root Device)...After reading.
9240 00:59:17.250216 Root Device child on link 0 CPU_CLUSTER: 0
9241 00:59:17.253658 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 00:59:17.263692 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 00:59:17.263804 CPU: 00
9244 00:59:17.267021 Root Device assign_resources, bus 0 link: 0
9245 00:59:17.269746 CPU_CLUSTER: 0 missing set_resources
9246 00:59:17.276593 Root Device assign_resources, bus 0 link: 0 done
9247 00:59:17.276665 Done setting resources.
9248 00:59:17.283514 Show resources in subtree (Root Device)...After assigning values.
9249 00:59:17.286221 Root Device child on link 0 CPU_CLUSTER: 0
9250 00:59:17.290154 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 00:59:17.299719 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 00:59:17.299797 CPU: 00
9253 00:59:17.302899 Done allocating resources.
9254 00:59:17.306694 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9255 00:59:17.309702 Enabling resources...
9256 00:59:17.309807 done.
9257 00:59:17.316430 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9258 00:59:17.316503 Initializing devices...
9259 00:59:17.319916 Root Device init
9260 00:59:17.319986 init hardware done!
9261 00:59:17.322651 0x00000018: ctrlr->caps
9262 00:59:17.326086 52.000 MHz: ctrlr->f_max
9263 00:59:17.326172 0.400 MHz: ctrlr->f_min
9264 00:59:17.329398 0x40ff8080: ctrlr->voltages
9265 00:59:17.329518 sclk: 390625
9266 00:59:17.332693 Bus Width = 1
9267 00:59:17.332765 sclk: 390625
9268 00:59:17.336039 Bus Width = 1
9269 00:59:17.336108 Early init status = 3
9270 00:59:17.342603 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9271 00:59:17.345587 in-header: 03 fc 00 00 01 00 00 00
9272 00:59:17.349195 in-data: 00
9273 00:59:17.352233 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9274 00:59:17.356996 in-header: 03 fd 00 00 00 00 00 00
9275 00:59:17.360130 in-data:
9276 00:59:17.363583 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9277 00:59:17.368185 in-header: 03 fc 00 00 01 00 00 00
9278 00:59:17.371364 in-data: 00
9279 00:59:17.374428 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9280 00:59:17.380031 in-header: 03 fd 00 00 00 00 00 00
9281 00:59:17.383407 in-data:
9282 00:59:17.386907 [SSUSB] Setting up USB HOST controller...
9283 00:59:17.390311 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9284 00:59:17.393680 [SSUSB] phy power-on done.
9285 00:59:17.396710 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9286 00:59:17.403372 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9287 00:59:17.406669 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9288 00:59:17.413330 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9289 00:59:17.419660 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9290 00:59:17.426786 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9291 00:59:17.433454 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9292 00:59:17.440223 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9293 00:59:17.443550 SPM: binary array size = 0x9dc
9294 00:59:17.446737 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9295 00:59:17.453082 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9296 00:59:17.459897 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9297 00:59:17.463072 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9298 00:59:17.466779 configure_display: Starting display init
9299 00:59:17.503620 anx7625_power_on_init: Init interface.
9300 00:59:17.506991 anx7625_disable_pd_protocol: Disabled PD feature.
9301 00:59:17.510277 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9302 00:59:17.538067 anx7625_start_dp_work: Secure OCM version=00
9303 00:59:17.541438 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9304 00:59:17.555784 sp_tx_get_edid_block: EDID Block = 1
9305 00:59:17.658611 Extracted contents:
9306 00:59:17.661865 header: 00 ff ff ff ff ff ff 00
9307 00:59:17.665231 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9308 00:59:17.668242 version: 01 04
9309 00:59:17.671980 basic params: 95 1f 11 78 0a
9310 00:59:17.675288 chroma info: 76 90 94 55 54 90 27 21 50 54
9311 00:59:17.678720 established: 00 00 00
9312 00:59:17.685358 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9313 00:59:17.688481 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9314 00:59:17.694771 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9315 00:59:17.701973 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9316 00:59:17.708152 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9317 00:59:17.711944 extensions: 00
9318 00:59:17.712019 checksum: fb
9319 00:59:17.712083
9320 00:59:17.714927 Manufacturer: IVO Model 57d Serial Number 0
9321 00:59:17.718127 Made week 0 of 2020
9322 00:59:17.718231 EDID version: 1.4
9323 00:59:17.721356 Digital display
9324 00:59:17.724754 6 bits per primary color channel
9325 00:59:17.724832 DisplayPort interface
9326 00:59:17.728298 Maximum image size: 31 cm x 17 cm
9327 00:59:17.731727 Gamma: 220%
9328 00:59:17.731831 Check DPMS levels
9329 00:59:17.735121 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9330 00:59:17.738496 First detailed timing is preferred timing
9331 00:59:17.741934 Established timings supported:
9332 00:59:17.744812 Standard timings supported:
9333 00:59:17.744882 Detailed timings
9334 00:59:17.751644 Hex of detail: 383680a07038204018303c0035ae10000019
9335 00:59:17.754866 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9336 00:59:17.761732 0780 0798 07c8 0820 hborder 0
9337 00:59:17.765419 0438 043b 0447 0458 vborder 0
9338 00:59:17.765536 -hsync -vsync
9339 00:59:17.768190 Did detailed timing
9340 00:59:17.771636 Hex of detail: 000000000000000000000000000000000000
9341 00:59:17.774948 Manufacturer-specified data, tag 0
9342 00:59:17.781712 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9343 00:59:17.781843 ASCII string: InfoVision
9344 00:59:17.788347 Hex of detail: 000000fe00523134304e574635205248200a
9345 00:59:17.788459 ASCII string: R140NWF5 RH
9346 00:59:17.791724 Checksum
9347 00:59:17.791801 Checksum: 0xfb (valid)
9348 00:59:17.798244 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9349 00:59:17.801380 DSI data_rate: 832800000 bps
9350 00:59:17.804977 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9351 00:59:17.808259 anx7625_parse_edid: pixelclock(138800).
9352 00:59:17.814615 hactive(1920), hsync(48), hfp(24), hbp(88)
9353 00:59:17.818078 vactive(1080), vsync(12), vfp(3), vbp(17)
9354 00:59:17.821347 anx7625_dsi_config: config dsi.
9355 00:59:17.828101 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9356 00:59:17.840450 anx7625_dsi_config: success to config DSI
9357 00:59:17.843900 anx7625_dp_start: MIPI phy setup OK.
9358 00:59:17.847249 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9359 00:59:17.850742 mtk_ddp_mode_set invalid vrefresh 60
9360 00:59:17.853531 main_disp_path_setup
9361 00:59:17.853623 ovl_layer_smi_id_en
9362 00:59:17.856969 ovl_layer_smi_id_en
9363 00:59:17.857045 ccorr_config
9364 00:59:17.857104 aal_config
9365 00:59:17.860384 gamma_config
9366 00:59:17.860466 postmask_config
9367 00:59:17.863738 dither_config
9368 00:59:17.867006 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9369 00:59:17.873407 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9370 00:59:17.877033 Root Device init finished in 554 msecs
9371 00:59:17.880620 CPU_CLUSTER: 0 init
9372 00:59:17.887321 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9373 00:59:17.890360 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9374 00:59:17.893494 APU_MBOX 0x190000b0 = 0x10001
9375 00:59:17.896759 APU_MBOX 0x190001b0 = 0x10001
9376 00:59:17.900157 APU_MBOX 0x190005b0 = 0x10001
9377 00:59:17.903599 APU_MBOX 0x190006b0 = 0x10001
9378 00:59:17.906798 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9379 00:59:17.919330 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9380 00:59:17.932028 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9381 00:59:17.938608 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9382 00:59:17.950073 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9383 00:59:17.959116 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9384 00:59:17.962620 CPU_CLUSTER: 0 init finished in 81 msecs
9385 00:59:17.966069 Devices initialized
9386 00:59:17.969617 Show all devs... After init.
9387 00:59:17.969689 Root Device: enabled 1
9388 00:59:17.973044 CPU_CLUSTER: 0: enabled 1
9389 00:59:17.975693 CPU: 00: enabled 1
9390 00:59:17.978989 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9391 00:59:17.982293 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9392 00:59:17.985553 ELOG: NV offset 0x57f000 size 0x1000
9393 00:59:17.992383 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9394 00:59:17.999037 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9395 00:59:18.002487 ELOG: Event(17) added with size 13 at 2024-06-16 00:59:17 UTC
9396 00:59:18.009188 out: cmd=0x121: 03 db 21 01 00 00 00 00
9397 00:59:18.012263 in-header: 03 51 00 00 2c 00 00 00
9398 00:59:18.022206 in-data: ec 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9399 00:59:18.029149 ELOG: Event(A1) added with size 10 at 2024-06-16 00:59:18 UTC
9400 00:59:18.035407 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9401 00:59:18.042039 ELOG: Event(A0) added with size 9 at 2024-06-16 00:59:18 UTC
9402 00:59:18.045464 elog_add_boot_reason: Logged dev mode boot
9403 00:59:18.049335 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9404 00:59:18.052411 Finalize devices...
9405 00:59:18.052517 Devices finalized
9406 00:59:18.058676 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9407 00:59:18.062166 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9408 00:59:18.065498 in-header: 03 07 00 00 08 00 00 00
9409 00:59:18.068846 in-data: aa e4 47 04 13 02 00 00
9410 00:59:18.072349 Chrome EC: UHEPI supported
9411 00:59:18.078514 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9412 00:59:18.081936 in-header: 03 a9 00 00 08 00 00 00
9413 00:59:18.085365 in-data: 84 60 60 08 00 00 00 00
9414 00:59:18.088897 ELOG: Event(91) added with size 10 at 2024-06-16 00:59:18 UTC
9415 00:59:18.095076 Chrome EC: clear events_b mask to 0x0000000020004000
9416 00:59:18.102493 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9417 00:59:18.105798 in-header: 03 fd 00 00 00 00 00 00
9418 00:59:18.105875 in-data:
9419 00:59:18.112353 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9420 00:59:18.115818 Writing coreboot table at 0xffe64000
9421 00:59:18.119268 0. 000000000010a000-0000000000113fff: RAMSTAGE
9422 00:59:18.122667 1. 0000000040000000-00000000400fffff: RAM
9423 00:59:18.128938 2. 0000000040100000-000000004032afff: RAMSTAGE
9424 00:59:18.132573 3. 000000004032b000-00000000545fffff: RAM
9425 00:59:18.135799 4. 0000000054600000-000000005465ffff: BL31
9426 00:59:18.139120 5. 0000000054660000-00000000ffe63fff: RAM
9427 00:59:18.145527 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9428 00:59:18.149160 7. 0000000100000000-000000023fffffff: RAM
9429 00:59:18.149236 Passing 5 GPIOs to payload:
9430 00:59:18.155614 NAME | PORT | POLARITY | VALUE
9431 00:59:18.158890 EC in RW | 0x000000aa | low | undefined
9432 00:59:18.165520 EC interrupt | 0x00000005 | low | undefined
9433 00:59:18.168705 TPM interrupt | 0x000000ab | high | undefined
9434 00:59:18.172014 SD card detect | 0x00000011 | high | undefined
9435 00:59:18.178775 speaker enable | 0x00000093 | high | undefined
9436 00:59:18.182247 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9437 00:59:18.185718 in-header: 03 f9 00 00 02 00 00 00
9438 00:59:18.185789 in-data: 02 00
9439 00:59:18.189045 ADC[4]: Raw value=905096 ID=7
9440 00:59:18.192509 ADC[3]: Raw value=213441 ID=1
9441 00:59:18.192577 RAM Code: 0x71
9442 00:59:18.195262 ADC[6]: Raw value=75701 ID=0
9443 00:59:18.198600 ADC[5]: Raw value=212703 ID=1
9444 00:59:18.198665 SKU Code: 0x1
9445 00:59:18.205465 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5242
9446 00:59:18.208720 coreboot table: 964 bytes.
9447 00:59:18.212129 IMD ROOT 0. 0xfffff000 0x00001000
9448 00:59:18.215498 IMD SMALL 1. 0xffffe000 0x00001000
9449 00:59:18.218961 RO MCACHE 2. 0xffffc000 0x00001104
9450 00:59:18.222524 CONSOLE 3. 0xfff7c000 0x00080000
9451 00:59:18.225672 FMAP 4. 0xfff7b000 0x00000452
9452 00:59:18.228936 TIME STAMP 5. 0xfff7a000 0x00000910
9453 00:59:18.231898 VBOOT WORK 6. 0xfff66000 0x00014000
9454 00:59:18.235496 RAMOOPS 7. 0xffe66000 0x00100000
9455 00:59:18.238616 COREBOOT 8. 0xffe64000 0x00002000
9456 00:59:18.238719 IMD small region:
9457 00:59:18.241914 IMD ROOT 0. 0xffffec00 0x00000400
9458 00:59:18.245629 VPD 1. 0xffffeb80 0x0000006c
9459 00:59:18.248770 MMC STATUS 2. 0xffffeb60 0x00000004
9460 00:59:18.255354 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9461 00:59:18.261851 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9462 00:59:18.301227 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9463 00:59:18.304639 Checking segment from ROM address 0x40100000
9464 00:59:18.308153 Checking segment from ROM address 0x4010001c
9465 00:59:18.314581 Loading segment from ROM address 0x40100000
9466 00:59:18.314653 code (compression=0)
9467 00:59:18.324763 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9468 00:59:18.331473 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9469 00:59:18.331547 it's not compressed!
9470 00:59:18.338129 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9471 00:59:18.344485 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9472 00:59:18.362022 Loading segment from ROM address 0x4010001c
9473 00:59:18.362106 Entry Point 0x80000000
9474 00:59:18.365431 Loaded segments
9475 00:59:18.368745 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9476 00:59:18.375371 Jumping to boot code at 0x80000000(0xffe64000)
9477 00:59:18.382210 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9478 00:59:18.388737 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9479 00:59:18.395982 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9480 00:59:18.399351 Checking segment from ROM address 0x40100000
9481 00:59:18.403003 Checking segment from ROM address 0x4010001c
9482 00:59:18.409694 Loading segment from ROM address 0x40100000
9483 00:59:18.409772 code (compression=1)
9484 00:59:18.416020 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9485 00:59:18.426206 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9486 00:59:18.426298 using LZMA
9487 00:59:18.434545 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9488 00:59:18.441400 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9489 00:59:18.444856 Loading segment from ROM address 0x4010001c
9490 00:59:18.444932 Entry Point 0x54601000
9491 00:59:18.448096 Loaded segments
9492 00:59:18.451487 NOTICE: MT8192 bl31_setup
9493 00:59:18.458268 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9494 00:59:18.461508 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9495 00:59:18.464548 WARNING: region 0:
9496 00:59:18.468153 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 00:59:18.468257 WARNING: region 1:
9498 00:59:18.474521 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9499 00:59:18.477978 WARNING: region 2:
9500 00:59:18.481237 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9501 00:59:18.484614 WARNING: region 3:
9502 00:59:18.487972 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 00:59:18.491645 WARNING: region 4:
9504 00:59:18.497800 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 00:59:18.497878 WARNING: region 5:
9506 00:59:18.501168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 00:59:18.504915 WARNING: region 6:
9508 00:59:18.508036 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 00:59:18.511255 WARNING: region 7:
9510 00:59:18.514418 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 00:59:18.521453 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9512 00:59:18.524889 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9513 00:59:18.527583 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9514 00:59:18.534498 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9515 00:59:18.537955 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9516 00:59:18.544748 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9517 00:59:18.547495 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9518 00:59:18.550809 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9519 00:59:18.557578 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9520 00:59:18.561119 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9521 00:59:18.563899 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9522 00:59:18.570864 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9523 00:59:18.574172 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9524 00:59:18.580886 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9525 00:59:18.583990 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9526 00:59:18.587504 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9527 00:59:18.594015 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9528 00:59:18.597816 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9529 00:59:18.601068 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9530 00:59:18.607767 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9531 00:59:18.611060 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9532 00:59:18.617725 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9533 00:59:18.621064 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9534 00:59:18.624377 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9535 00:59:18.631184 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9536 00:59:18.634274 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9537 00:59:18.641071 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9538 00:59:18.644554 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9539 00:59:18.647975 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9540 00:59:18.654126 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9541 00:59:18.657900 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9542 00:59:18.664000 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9543 00:59:18.668038 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9544 00:59:18.670791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9545 00:59:18.674118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9546 00:59:18.677455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9547 00:59:18.684300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9548 00:59:18.687524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9549 00:59:18.690811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9550 00:59:18.694663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9551 00:59:18.701223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9552 00:59:18.704268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9553 00:59:18.707750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9554 00:59:18.711411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9555 00:59:18.717518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9556 00:59:18.721009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9557 00:59:18.724612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9558 00:59:18.728013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9559 00:59:18.734208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9560 00:59:18.737448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9561 00:59:18.744772 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9562 00:59:18.747839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9563 00:59:18.754797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9564 00:59:18.757502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9565 00:59:18.760992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9566 00:59:18.767627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9567 00:59:18.770847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9568 00:59:18.777643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9569 00:59:18.781094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9570 00:59:18.788076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9571 00:59:18.791364 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9572 00:59:18.794189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9573 00:59:18.800964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9574 00:59:18.804381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9575 00:59:18.811013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9576 00:59:18.814141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9577 00:59:18.821128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9578 00:59:18.824069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9579 00:59:18.827666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9580 00:59:18.834183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9581 00:59:18.837517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9582 00:59:18.844198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9583 00:59:18.847825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9584 00:59:18.854349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9585 00:59:18.857412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9586 00:59:18.861206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9587 00:59:18.867437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9588 00:59:18.870702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9589 00:59:18.877524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9590 00:59:18.880790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9591 00:59:18.887639 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9592 00:59:18.891049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9593 00:59:18.897561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9594 00:59:18.900998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9595 00:59:18.904419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9596 00:59:18.911114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9597 00:59:18.914568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9598 00:59:18.920788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9599 00:59:18.924317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9600 00:59:18.930770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9601 00:59:18.934574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9602 00:59:18.937378 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9603 00:59:18.944345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9604 00:59:18.947297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9605 00:59:18.954359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9606 00:59:18.957905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9607 00:59:18.961172 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9608 00:59:18.967430 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9609 00:59:18.971174 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9610 00:59:18.974173 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9611 00:59:18.977659 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9612 00:59:18.984559 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9613 00:59:18.987634 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9614 00:59:18.994367 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9615 00:59:18.997635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9616 00:59:19.000855 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9617 00:59:19.007726 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9618 00:59:19.011182 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9619 00:59:19.017495 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9620 00:59:19.021018 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9621 00:59:19.024428 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9622 00:59:19.030582 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9623 00:59:19.034085 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9624 00:59:19.040609 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9625 00:59:19.044669 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9626 00:59:19.047432 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9627 00:59:19.054232 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9628 00:59:19.057432 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9629 00:59:19.061077 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9630 00:59:19.067331 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9631 00:59:19.070984 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9632 00:59:19.073973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9633 00:59:19.077659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9634 00:59:19.080863 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9635 00:59:19.087177 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9636 00:59:19.091117 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9637 00:59:19.097119 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9638 00:59:19.100450 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9639 00:59:19.103988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9640 00:59:19.110975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9641 00:59:19.113684 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9642 00:59:19.120620 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9643 00:59:19.123905 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9644 00:59:19.127408 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9645 00:59:19.134253 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9646 00:59:19.137046 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9647 00:59:19.143705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9648 00:59:19.147671 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9649 00:59:19.150334 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9650 00:59:19.157118 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9651 00:59:19.160624 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9652 00:59:19.167418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9653 00:59:19.170764 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9654 00:59:19.174317 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9655 00:59:19.180845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9656 00:59:19.184081 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9657 00:59:19.187251 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9658 00:59:19.194155 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9659 00:59:19.197327 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9660 00:59:19.203873 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9661 00:59:19.207019 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9662 00:59:19.210716 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9663 00:59:19.217074 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9664 00:59:19.220468 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9665 00:59:19.227182 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9666 00:59:19.230469 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9667 00:59:19.233896 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9668 00:59:19.240700 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9669 00:59:19.243403 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9670 00:59:19.246761 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9671 00:59:19.253400 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9672 00:59:19.257216 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9673 00:59:19.263991 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9674 00:59:19.266790 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9675 00:59:19.270222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9676 00:59:19.276906 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9677 00:59:19.280194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9678 00:59:19.286994 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9679 00:59:19.290212 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9680 00:59:19.293526 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9681 00:59:19.300299 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9682 00:59:19.303455 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9683 00:59:19.310132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9684 00:59:19.313396 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9685 00:59:19.316685 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9686 00:59:19.323414 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9687 00:59:19.326549 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9688 00:59:19.333353 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9689 00:59:19.336817 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9690 00:59:19.340190 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9691 00:59:19.346500 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9692 00:59:19.350367 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9693 00:59:19.353060 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9694 00:59:19.360255 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9695 00:59:19.363521 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9696 00:59:19.369812 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9697 00:59:19.373314 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9698 00:59:19.376444 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9699 00:59:19.383347 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9700 00:59:19.386766 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9701 00:59:19.393493 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9702 00:59:19.396779 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9703 00:59:19.402935 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9704 00:59:19.406439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9705 00:59:19.409904 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9706 00:59:19.416693 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9707 00:59:19.420024 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9708 00:59:19.426507 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9709 00:59:19.429570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9710 00:59:19.432911 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9711 00:59:19.439688 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9712 00:59:19.443053 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9713 00:59:19.449653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9714 00:59:19.452835 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9715 00:59:19.459664 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9716 00:59:19.463090 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9717 00:59:19.465977 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9718 00:59:19.472682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9719 00:59:19.475912 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9720 00:59:19.482567 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9721 00:59:19.486072 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9722 00:59:19.489753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9723 00:59:19.496446 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9724 00:59:19.499242 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9725 00:59:19.506017 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9726 00:59:19.509436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9727 00:59:19.512882 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9728 00:59:19.519122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9729 00:59:19.522459 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9730 00:59:19.529141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9731 00:59:19.532652 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9732 00:59:19.539251 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9733 00:59:19.542482 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9734 00:59:19.545930 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9735 00:59:19.552882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9736 00:59:19.555543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9737 00:59:19.562586 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9738 00:59:19.565407 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9739 00:59:19.569333 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9740 00:59:19.575657 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9741 00:59:19.578856 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9742 00:59:19.582606 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9743 00:59:19.585706 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9744 00:59:19.592121 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9745 00:59:19.595614 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9746 00:59:19.598984 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9747 00:59:19.605706 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9748 00:59:19.608934 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9749 00:59:19.611963 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9750 00:59:19.618731 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9751 00:59:19.622228 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9752 00:59:19.628584 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9753 00:59:19.632088 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9754 00:59:19.635632 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9755 00:59:19.642381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9756 00:59:19.645626 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9757 00:59:19.648975 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9758 00:59:19.655645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9759 00:59:19.659008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9760 00:59:19.662592 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9761 00:59:19.668890 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9762 00:59:19.672254 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9763 00:59:19.675666 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9764 00:59:19.682321 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9765 00:59:19.685690 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9766 00:59:19.688936 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9767 00:59:19.695819 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9768 00:59:19.699215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9769 00:59:19.706082 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9770 00:59:19.709274 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9771 00:59:19.712245 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9772 00:59:19.718671 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9773 00:59:19.722114 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9774 00:59:19.725471 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9775 00:59:19.732310 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9776 00:59:19.735886 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9777 00:59:19.742369 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9778 00:59:19.745667 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9779 00:59:19.749084 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9780 00:59:19.752402 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9781 00:59:19.758726 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9782 00:59:19.762212 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9783 00:59:19.765605 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9784 00:59:19.769061 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9785 00:59:19.775628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9786 00:59:19.779104 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9787 00:59:19.781897 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9788 00:59:19.785865 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9789 00:59:19.789151 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9790 00:59:19.795173 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9791 00:59:19.798687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9792 00:59:19.802002 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9793 00:59:19.808823 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9794 00:59:19.812295 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9795 00:59:19.819073 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9796 00:59:19.821900 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9797 00:59:19.825152 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9798 00:59:19.831882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9799 00:59:19.835411 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9800 00:59:19.841889 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9801 00:59:19.845647 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9802 00:59:19.848402 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9803 00:59:19.855235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9804 00:59:19.858853 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9805 00:59:19.865474 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9806 00:59:19.868868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9807 00:59:19.875084 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9808 00:59:19.878716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9809 00:59:19.882035 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9810 00:59:19.888917 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9811 00:59:19.892273 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9812 00:59:19.898942 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9813 00:59:19.902275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9814 00:59:19.905536 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9815 00:59:19.911713 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9816 00:59:19.915131 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9817 00:59:19.918625 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9818 00:59:19.925354 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9819 00:59:19.928550 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9820 00:59:19.935163 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9821 00:59:19.938653 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9822 00:59:19.944906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9823 00:59:19.948293 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9824 00:59:19.951661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9825 00:59:19.958529 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9826 00:59:19.961756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9827 00:59:19.968513 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9828 00:59:19.971682 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9829 00:59:19.975011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9830 00:59:19.981826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9831 00:59:19.984769 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9832 00:59:19.991361 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9833 00:59:19.994981 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9834 00:59:19.998271 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9835 00:59:20.004796 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9836 00:59:20.008386 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9837 00:59:20.015012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9838 00:59:20.018159 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9839 00:59:20.024736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9840 00:59:20.028156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9841 00:59:20.031503 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9842 00:59:20.038020 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9843 00:59:20.041453 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9844 00:59:20.044964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9845 00:59:20.051784 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9846 00:59:20.055195 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9847 00:59:20.061899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9848 00:59:20.065285 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9849 00:59:20.068434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9850 00:59:20.075181 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9851 00:59:20.078531 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9852 00:59:20.085179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9853 00:59:20.088642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9854 00:59:20.095290 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9855 00:59:20.098719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9856 00:59:20.102152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9857 00:59:20.108343 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9858 00:59:20.111654 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9859 00:59:20.115484 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9860 00:59:20.122036 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9861 00:59:20.125124 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9862 00:59:20.131777 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9863 00:59:20.135296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9864 00:59:20.138083 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9865 00:59:20.145123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9866 00:59:20.148541 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9867 00:59:20.155205 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9868 00:59:20.158803 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9869 00:59:20.165210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9870 00:59:20.168525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9871 00:59:20.174843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9872 00:59:20.178159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9873 00:59:20.181659 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9874 00:59:20.188540 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9875 00:59:20.191952 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9876 00:59:20.198734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9877 00:59:20.201935 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9878 00:59:20.208681 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9879 00:59:20.211395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9880 00:59:20.215411 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9881 00:59:20.221465 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9882 00:59:20.224750 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9883 00:59:20.231604 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9884 00:59:20.235048 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9885 00:59:20.241187 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9886 00:59:20.244560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9887 00:59:20.251384 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9888 00:59:20.254616 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9889 00:59:20.258377 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9890 00:59:20.264964 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9891 00:59:20.268372 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9892 00:59:20.274527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9893 00:59:20.278110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9894 00:59:20.281483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9895 00:59:20.288385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9896 00:59:20.291490 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9897 00:59:20.298371 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9898 00:59:20.301701 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9899 00:59:20.307884 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9900 00:59:20.311252 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9901 00:59:20.314443 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9902 00:59:20.321330 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9903 00:59:20.324739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9904 00:59:20.331299 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9905 00:59:20.334783 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9906 00:59:20.340959 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9907 00:59:20.344475 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9908 00:59:20.347898 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9909 00:59:20.354371 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9910 00:59:20.357869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9911 00:59:20.364483 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9912 00:59:20.367763 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9913 00:59:20.371197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9914 00:59:20.377670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9915 00:59:20.381450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9916 00:59:20.388212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9917 00:59:20.391502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9918 00:59:20.398300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9919 00:59:20.401193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9920 00:59:20.408211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9921 00:59:20.411434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9922 00:59:20.417994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9923 00:59:20.421229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9924 00:59:20.427911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9925 00:59:20.431275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9926 00:59:20.434632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9927 00:59:20.441347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9928 00:59:20.444721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9929 00:59:20.451516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9930 00:59:20.454877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9931 00:59:20.461565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9932 00:59:20.464315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9933 00:59:20.471125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9934 00:59:20.474480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9935 00:59:20.481321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9936 00:59:20.484681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9937 00:59:20.491050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9938 00:59:20.494490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9939 00:59:20.501221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9940 00:59:20.503950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9941 00:59:20.510815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9942 00:59:20.513988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9943 00:59:20.520750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9944 00:59:20.527332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9945 00:59:20.530506 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9946 00:59:20.530631 INFO: [APUAPC] vio 0
9947 00:59:20.538080 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9948 00:59:20.541558 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9949 00:59:20.544679 INFO: [APUAPC] D0_APC_0: 0x400510
9950 00:59:20.548259 INFO: [APUAPC] D0_APC_1: 0x0
9951 00:59:20.551521 INFO: [APUAPC] D0_APC_2: 0x1540
9952 00:59:20.554367 INFO: [APUAPC] D0_APC_3: 0x0
9953 00:59:20.557754 INFO: [APUAPC] D1_APC_0: 0xffffffff
9954 00:59:20.561169 INFO: [APUAPC] D1_APC_1: 0xffffffff
9955 00:59:20.564369 INFO: [APUAPC] D1_APC_2: 0x3fffff
9956 00:59:20.567734 INFO: [APUAPC] D1_APC_3: 0x0
9957 00:59:20.571066 INFO: [APUAPC] D2_APC_0: 0xffffffff
9958 00:59:20.574714 INFO: [APUAPC] D2_APC_1: 0xffffffff
9959 00:59:20.578086 INFO: [APUAPC] D2_APC_2: 0x3fffff
9960 00:59:20.581446 INFO: [APUAPC] D2_APC_3: 0x0
9961 00:59:20.584818 INFO: [APUAPC] D3_APC_0: 0xffffffff
9962 00:59:20.588139 INFO: [APUAPC] D3_APC_1: 0xffffffff
9963 00:59:20.590965 INFO: [APUAPC] D3_APC_2: 0x3fffff
9964 00:59:20.591060 INFO: [APUAPC] D3_APC_3: 0x0
9965 00:59:20.598001 INFO: [APUAPC] D4_APC_0: 0xffffffff
9966 00:59:20.601376 INFO: [APUAPC] D4_APC_1: 0xffffffff
9967 00:59:20.604652 INFO: [APUAPC] D4_APC_2: 0x3fffff
9968 00:59:20.604730 INFO: [APUAPC] D4_APC_3: 0x0
9969 00:59:20.608219 INFO: [APUAPC] D5_APC_0: 0xffffffff
9970 00:59:20.611657 INFO: [APUAPC] D5_APC_1: 0xffffffff
9971 00:59:20.614343 INFO: [APUAPC] D5_APC_2: 0x3fffff
9972 00:59:20.617739 INFO: [APUAPC] D5_APC_3: 0x0
9973 00:59:20.621156 INFO: [APUAPC] D6_APC_0: 0xffffffff
9974 00:59:20.624737 INFO: [APUAPC] D6_APC_1: 0xffffffff
9975 00:59:20.628134 INFO: [APUAPC] D6_APC_2: 0x3fffff
9976 00:59:20.631628 INFO: [APUAPC] D6_APC_3: 0x0
9977 00:59:20.635006 INFO: [APUAPC] D7_APC_0: 0xffffffff
9978 00:59:20.638019 INFO: [APUAPC] D7_APC_1: 0xffffffff
9979 00:59:20.641600 INFO: [APUAPC] D7_APC_2: 0x3fffff
9980 00:59:20.644861 INFO: [APUAPC] D7_APC_3: 0x0
9981 00:59:20.648160 INFO: [APUAPC] D8_APC_0: 0xffffffff
9982 00:59:20.651272 INFO: [APUAPC] D8_APC_1: 0xffffffff
9983 00:59:20.654933 INFO: [APUAPC] D8_APC_2: 0x3fffff
9984 00:59:20.658250 INFO: [APUAPC] D8_APC_3: 0x0
9985 00:59:20.661707 INFO: [APUAPC] D9_APC_0: 0xffffffff
9986 00:59:20.664950 INFO: [APUAPC] D9_APC_1: 0xffffffff
9987 00:59:20.668085 INFO: [APUAPC] D9_APC_2: 0x3fffff
9988 00:59:20.671648 INFO: [APUAPC] D9_APC_3: 0x0
9989 00:59:20.674680 INFO: [APUAPC] D10_APC_0: 0xffffffff
9990 00:59:20.678011 INFO: [APUAPC] D10_APC_1: 0xffffffff
9991 00:59:20.681393 INFO: [APUAPC] D10_APC_2: 0x3fffff
9992 00:59:20.685240 INFO: [APUAPC] D10_APC_3: 0x0
9993 00:59:20.687954 INFO: [APUAPC] D11_APC_0: 0xffffffff
9994 00:59:20.691349 INFO: [APUAPC] D11_APC_1: 0xffffffff
9995 00:59:20.694710 INFO: [APUAPC] D11_APC_2: 0x3fffff
9996 00:59:20.698257 INFO: [APUAPC] D11_APC_3: 0x0
9997 00:59:20.701376 INFO: [APUAPC] D12_APC_0: 0xffffffff
9998 00:59:20.704695 INFO: [APUAPC] D12_APC_1: 0xffffffff
9999 00:59:20.708185 INFO: [APUAPC] D12_APC_2: 0x3fffff
10000 00:59:20.711633 INFO: [APUAPC] D12_APC_3: 0x0
10001 00:59:20.715138 INFO: [APUAPC] D13_APC_0: 0xffffffff
10002 00:59:20.717896 INFO: [APUAPC] D13_APC_1: 0xffffffff
10003 00:59:20.721264 INFO: [APUAPC] D13_APC_2: 0x3fffff
10004 00:59:20.724679 INFO: [APUAPC] D13_APC_3: 0x0
10005 00:59:20.728161 INFO: [APUAPC] D14_APC_0: 0xffffffff
10006 00:59:20.731421 INFO: [APUAPC] D14_APC_1: 0xffffffff
10007 00:59:20.734912 INFO: [APUAPC] D14_APC_2: 0x3fffff
10008 00:59:20.738291 INFO: [APUAPC] D14_APC_3: 0x0
10009 00:59:20.741662 INFO: [APUAPC] D15_APC_0: 0xffffffff
10010 00:59:20.745051 INFO: [APUAPC] D15_APC_1: 0xffffffff
10011 00:59:20.748020 INFO: [APUAPC] D15_APC_2: 0x3fffff
10012 00:59:20.751407 INFO: [APUAPC] D15_APC_3: 0x0
10013 00:59:20.754789 INFO: [APUAPC] APC_CON: 0x4
10014 00:59:20.758083 INFO: [NOCDAPC] D0_APC_0: 0x0
10015 00:59:20.758153 INFO: [NOCDAPC] D0_APC_1: 0x0
10016 00:59:20.761466 INFO: [NOCDAPC] D1_APC_0: 0x0
10017 00:59:20.764947 INFO: [NOCDAPC] D1_APC_1: 0xfff
10018 00:59:20.768323 INFO: [NOCDAPC] D2_APC_0: 0x0
10019 00:59:20.771569 INFO: [NOCDAPC] D2_APC_1: 0xfff
10020 00:59:20.774892 INFO: [NOCDAPC] D3_APC_0: 0x0
10021 00:59:20.778075 INFO: [NOCDAPC] D3_APC_1: 0xfff
10022 00:59:20.781328 INFO: [NOCDAPC] D4_APC_0: 0x0
10023 00:59:20.785189 INFO: [NOCDAPC] D4_APC_1: 0xfff
10024 00:59:20.788309 INFO: [NOCDAPC] D5_APC_0: 0x0
10025 00:59:20.791162 INFO: [NOCDAPC] D5_APC_1: 0xfff
10026 00:59:20.791228 INFO: [NOCDAPC] D6_APC_0: 0x0
10027 00:59:20.794828 INFO: [NOCDAPC] D6_APC_1: 0xfff
10028 00:59:20.797900 INFO: [NOCDAPC] D7_APC_0: 0x0
10029 00:59:20.801297 INFO: [NOCDAPC] D7_APC_1: 0xfff
10030 00:59:20.804613 INFO: [NOCDAPC] D8_APC_0: 0x0
10031 00:59:20.807663 INFO: [NOCDAPC] D8_APC_1: 0xfff
10032 00:59:20.811247 INFO: [NOCDAPC] D9_APC_0: 0x0
10033 00:59:20.814663 INFO: [NOCDAPC] D9_APC_1: 0xfff
10034 00:59:20.818077 INFO: [NOCDAPC] D10_APC_0: 0x0
10035 00:59:20.821048 INFO: [NOCDAPC] D10_APC_1: 0xfff
10036 00:59:20.824417 INFO: [NOCDAPC] D11_APC_0: 0x0
10037 00:59:20.827925 INFO: [NOCDAPC] D11_APC_1: 0xfff
10038 00:59:20.828024 INFO: [NOCDAPC] D12_APC_0: 0x0
10039 00:59:20.831460 INFO: [NOCDAPC] D12_APC_1: 0xfff
10040 00:59:20.834151 INFO: [NOCDAPC] D13_APC_0: 0x0
10041 00:59:20.837535 INFO: [NOCDAPC] D13_APC_1: 0xfff
10042 00:59:20.841030 INFO: [NOCDAPC] D14_APC_0: 0x0
10043 00:59:20.844498 INFO: [NOCDAPC] D14_APC_1: 0xfff
10044 00:59:20.848000 INFO: [NOCDAPC] D15_APC_0: 0x0
10045 00:59:20.851275 INFO: [NOCDAPC] D15_APC_1: 0xfff
10046 00:59:20.854571 INFO: [NOCDAPC] APC_CON: 0x4
10047 00:59:20.857285 INFO: [APUAPC] set_apusys_apc done
10048 00:59:20.860666 INFO: [DEVAPC] devapc_init done
10049 00:59:20.864016 INFO: GICv3 without legacy support detected.
10050 00:59:20.867421 INFO: ARM GICv3 driver initialized in EL3
10051 00:59:20.870948 INFO: Maximum SPI INTID supported: 639
10052 00:59:20.877854 INFO: BL31: Initializing runtime services
10053 00:59:20.881098 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10054 00:59:20.884309 INFO: SPM: enable CPC mode
10055 00:59:20.891075 INFO: mcdi ready for mcusys-off-idle and system suspend
10056 00:59:20.894134 INFO: BL31: Preparing for EL3 exit to normal world
10057 00:59:20.897478 INFO: Entry point address = 0x80000000
10058 00:59:20.900717 INFO: SPSR = 0x8
10059 00:59:20.906265
10060 00:59:20.906362
10061 00:59:20.906447
10062 00:59:20.909671 Starting depthcharge on Spherion...
10063 00:59:20.909736
10064 00:59:20.909793 Wipe memory regions:
10065 00:59:20.909876
10066 00:59:20.910689 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10067 00:59:20.910811 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10068 00:59:20.910913 Setting prompt string to ['asurada:']
10069 00:59:20.911016 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10070 00:59:20.912936 [0x00000040000000, 0x00000054600000)
10071 00:59:21.035006
10072 00:59:21.035140 [0x00000054660000, 0x00000080000000)
10073 00:59:21.295695
10074 00:59:21.295828 [0x000000821a7280, 0x000000ffe64000)
10075 00:59:22.040136
10076 00:59:22.040280 [0x00000100000000, 0x00000240000000)
10077 00:59:23.929585
10078 00:59:23.932960 Initializing XHCI USB controller at 0x11200000.
10079 00:59:24.972494
10080 00:59:24.975160 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10081 00:59:24.975261
10082 00:59:24.975348
10083 00:59:24.975648 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10085 00:59:25.076013 asurada: tftpboot 192.168.201.1 14368619/tftp-deploy-trdb_me4/kernel/image.itb 14368619/tftp-deploy-trdb_me4/kernel/cmdline
10086 00:59:25.076239 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10087 00:59:25.076368 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10088 00:59:25.080810 tftpboot 192.168.201.1 14368619/tftp-deploy-trdb_me4/kernel/image.itp-deploy-trdb_me4/kernel/cmdline
10089 00:59:25.080889
10090 00:59:25.080949 Waiting for link
10091 00:59:25.239303
10092 00:59:25.239422 R8152: Initializing
10093 00:59:25.239484
10094 00:59:25.242099 Version 9 (ocp_data = 6010)
10095 00:59:25.242176
10096 00:59:25.245536 R8152: Done initializing
10097 00:59:25.245655
10098 00:59:25.245715 Adding net device
10099 00:59:27.194068
10100 00:59:27.194192 done.
10101 00:59:27.194254
10102 00:59:27.194310 MAC: 00:e0:4c:78:7a:aa
10103 00:59:27.194363
10104 00:59:27.196671 Sending DHCP discover... done.
10105 00:59:27.196750
10106 00:59:27.200521 Waiting for reply... done.
10107 00:59:27.200602
10108 00:59:27.204031 Sending DHCP request... done.
10109 00:59:27.204110
10110 00:59:27.204171 Waiting for reply... done.
10111 00:59:27.206722
10112 00:59:27.206798 My ip is 192.168.201.12
10113 00:59:27.206858
10114 00:59:27.209934 The DHCP server ip is 192.168.201.1
10115 00:59:27.210016
10116 00:59:27.213846 TFTP server IP predefined by user: 192.168.201.1
10117 00:59:27.213933
10118 00:59:27.220485 Bootfile predefined by user: 14368619/tftp-deploy-trdb_me4/kernel/image.itb
10119 00:59:27.220587
10120 00:59:27.223801 Sending tftp read request... done.
10121 00:59:27.223902
10122 00:59:27.227061 Waiting for the transfer...
10123 00:59:27.227138
10124 00:59:27.525489 00000000 ################################################################
10125 00:59:27.525664
10126 00:59:27.778711 00080000 ################################################################
10127 00:59:27.778862
10128 00:59:28.028000 00100000 ################################################################
10129 00:59:28.028139
10130 00:59:28.286328 00180000 ################################################################
10131 00:59:28.286470
10132 00:59:28.581010 00200000 ################################################################
10133 00:59:28.581206
10134 00:59:28.872245 00280000 ################################################################
10135 00:59:28.872379
10136 00:59:29.221302 00300000 ################################################################
10137 00:59:29.221443
10138 00:59:29.509059 00380000 ################################################################
10139 00:59:29.509177
10140 00:59:29.805674 00400000 ################################################################
10141 00:59:29.805818
10142 00:59:30.090981 00480000 ################################################################
10143 00:59:30.091106
10144 00:59:30.351130 00500000 ################################################################
10145 00:59:30.351262
10146 00:59:30.629852 00580000 ################################################################
10147 00:59:30.629982
10148 00:59:30.906906 00600000 ################################################################
10149 00:59:30.907044
10150 00:59:31.173187 00680000 ################################################################
10151 00:59:31.173302
10152 00:59:31.426801 00700000 ################################################################
10153 00:59:31.426911
10154 00:59:31.697849 00780000 ################################################################
10155 00:59:31.697989
10156 00:59:31.963795 00800000 ################################################################
10157 00:59:31.963915
10158 00:59:32.218226 00880000 ################################################################
10159 00:59:32.218384
10160 00:59:32.467094 00900000 ################################################################
10161 00:59:32.467250
10162 00:59:32.723708 00980000 ################################################################
10163 00:59:32.723854
10164 00:59:32.984128 00a00000 ################################################################
10165 00:59:32.984275
10166 00:59:33.250170 00a80000 ################################################################
10167 00:59:33.250294
10168 00:59:33.497651 00b00000 ################################################################
10169 00:59:33.497767
10170 00:59:33.742505 00b80000 ################################################################
10171 00:59:33.742644
10172 00:59:33.986772 00c00000 ################################################################
10173 00:59:33.986914
10174 00:59:34.231497 00c80000 ################################################################
10175 00:59:34.231637
10176 00:59:34.481801 00d00000 ################################################################
10177 00:59:34.481925
10178 00:59:34.724447 00d80000 ################################################################
10179 00:59:34.724572
10180 00:59:34.974049 00e00000 ################################################################
10181 00:59:34.974175
10182 00:59:35.230866 00e80000 ################################################################
10183 00:59:35.230980
10184 00:59:35.481311 00f00000 ################################################################
10185 00:59:35.481440
10186 00:59:35.728189 00f80000 ################################################################
10187 00:59:35.728312
10188 00:59:35.975056 01000000 ################################################################
10189 00:59:35.975227
10190 00:59:36.222501 01080000 ################################################################
10191 00:59:36.222615
10192 00:59:36.474248 01100000 ################################################################
10193 00:59:36.474360
10194 00:59:36.726914 01180000 ################################################################
10195 00:59:36.727027
10196 00:59:36.979869 01200000 ################################################################
10197 00:59:36.979980
10198 00:59:37.234111 01280000 ################################################################
10199 00:59:37.234223
10200 00:59:37.477777 01300000 ################################################################
10201 00:59:37.477912
10202 00:59:37.731876 01380000 ################################################################
10203 00:59:37.731990
10204 00:59:37.986082 01400000 ################################################################
10205 00:59:37.986192
10206 00:59:38.258656 01480000 ################################################################
10207 00:59:38.258798
10208 00:59:38.514821 01500000 ################################################################
10209 00:59:38.514935
10210 00:59:38.775538 01580000 ################################################################
10211 00:59:38.775712
10212 00:59:39.041210 01600000 ################################################################
10213 00:59:39.041349
10214 00:59:39.312626 01680000 ################################################################
10215 00:59:39.312741
10216 00:59:39.585015 01700000 ################################################################
10217 00:59:39.585128
10218 00:59:39.839192 01780000 ################################################################
10219 00:59:39.839328
10220 00:59:40.090534 01800000 ################################################################
10221 00:59:40.090650
10222 00:59:40.350819 01880000 ################################################################
10223 00:59:40.350932
10224 00:59:40.622145 01900000 ################################################################
10225 00:59:40.622257
10226 00:59:40.885829 01980000 ################################################################
10227 00:59:40.885941
10228 00:59:41.154788 01a00000 ################################################################
10229 00:59:41.154914
10230 00:59:41.432078 01a80000 ################################################################
10231 00:59:41.432190
10232 00:59:41.713579 01b00000 ################################################################
10233 00:59:41.713701
10234 00:59:41.996420 01b80000 ################################################################
10235 00:59:41.996559
10236 00:59:42.244916 01c00000 ################################################################
10237 00:59:42.245043
10238 00:59:42.501098 01c80000 ################################################################
10239 00:59:42.501209
10240 00:59:42.764869 01d00000 ################################################################
10241 00:59:42.764997
10242 00:59:43.012362 01d80000 ################################################################
10243 00:59:43.012474
10244 00:59:43.233177 01e00000 ######################################################## done.
10245 00:59:43.233284
10246 00:59:43.236508 The bootfile was 31911874 bytes long.
10247 00:59:43.236585
10248 00:59:43.239605 Sending tftp read request... done.
10249 00:59:43.239682
10250 00:59:43.242943 Waiting for the transfer...
10251 00:59:43.243019
10252 00:59:43.243077 00000000 # done.
10253 00:59:43.243133
10254 00:59:43.253089 Command line loaded dynamically from TFTP file: 14368619/tftp-deploy-trdb_me4/kernel/cmdline
10255 00:59:43.253164
10256 00:59:43.276096 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10257 00:59:43.276176
10258 00:59:43.276234 Loading FIT.
10259 00:59:43.276288
10260 00:59:43.279899 Image ramdisk-1 has 18737541 bytes.
10261 00:59:43.279975
10262 00:59:43.282870 Image fdt-1 has 47258 bytes.
10263 00:59:43.282945
10264 00:59:43.286448 Image kernel-1 has 13125045 bytes.
10265 00:59:43.286523
10266 00:59:43.292894 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10267 00:59:43.292969
10268 00:59:43.312687 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10269 00:59:43.312769
10270 00:59:43.315923 Choosing best match conf-1 for compat google,spherion-rev2.
10271 00:59:43.321133
10272 00:59:43.325630 Connected to device vid:did:rid of 1ae0:0028:00
10273 00:59:43.333466
10274 00:59:43.336764 tpm_get_response: command 0x17b, return code 0x0
10275 00:59:43.336840
10276 00:59:43.340002 ec_init: CrosEC protocol v3 supported (256, 248)
10277 00:59:43.345045
10278 00:59:43.348231 tpm_cleanup: add release locality here.
10279 00:59:43.348302
10280 00:59:43.348361 Shutting down all USB controllers.
10281 00:59:43.351562
10282 00:59:43.351655 Removing current net device
10283 00:59:43.351737
10284 00:59:43.358415 Exiting depthcharge with code 4 at timestamp: 51760984
10285 00:59:43.358488
10286 00:59:43.361603 LZMA decompressing kernel-1 to 0x821a6718
10287 00:59:43.361702
10288 00:59:43.364884 LZMA decompressing kernel-1 to 0x40000000
10289 00:59:44.980476
10290 00:59:44.980592 jumping to kernel
10291 00:59:44.981211 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10292 00:59:44.981312 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10293 00:59:44.981393 Setting prompt string to ['Linux version [0-9]']
10294 00:59:44.981460 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10295 00:59:44.981542 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10296 00:59:45.064003
10297 00:59:45.067201 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10298 00:59:45.070757 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10299 00:59:45.070846 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10300 00:59:45.070913 Setting prompt string to []
10301 00:59:45.070988 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10302 00:59:45.071055 Using line separator: #'\n'#
10303 00:59:45.071109 No login prompt set.
10304 00:59:45.071166 Parsing kernel messages
10305 00:59:45.071218 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10306 00:59:45.071315 [login-action] Waiting for messages, (timeout 00:03:56)
10307 00:59:45.071375 Waiting using forced prompt support (timeout 00:01:58)
10308 00:59:45.090362 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10309 00:59:45.093993 [ 0.000000] random: crng init done
10310 00:59:45.100366 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10311 00:59:45.103322 [ 0.000000] efi: UEFI not found.
10312 00:59:45.110123 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10313 00:59:45.116753 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10314 00:59:45.126884 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10315 00:59:45.137094 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10316 00:59:45.143593 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10317 00:59:45.146889 [ 0.000000] printk: bootconsole [mtk8250] enabled
10318 00:59:45.155701 [ 0.000000] NUMA: No NUMA configuration found
10319 00:59:45.162469 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10320 00:59:45.169092 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10321 00:59:45.169168 [ 0.000000] Zone ranges:
10322 00:59:45.175167 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10323 00:59:45.179058 [ 0.000000] DMA32 empty
10324 00:59:45.185467 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10325 00:59:45.188545 [ 0.000000] Movable zone start for each node
10326 00:59:45.191778 [ 0.000000] Early memory node ranges
10327 00:59:45.198997 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10328 00:59:45.205493 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10329 00:59:45.211796 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10330 00:59:45.218839 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10331 00:59:45.225676 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10332 00:59:45.231766 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10333 00:59:45.287931 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10334 00:59:45.294209 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10335 00:59:45.301280 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10336 00:59:45.304688 [ 0.000000] psci: probing for conduit method from DT.
10337 00:59:45.311203 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10338 00:59:45.314568 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10339 00:59:45.321185 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10340 00:59:45.324480 [ 0.000000] psci: SMC Calling Convention v1.2
10341 00:59:45.330939 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10342 00:59:45.333996 [ 0.000000] Detected VIPT I-cache on CPU0
10343 00:59:45.341320 [ 0.000000] CPU features: detected: GIC system register CPU interface
10344 00:59:45.347594 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10345 00:59:45.354314 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10346 00:59:45.361155 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10347 00:59:45.367364 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10348 00:59:45.374049 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10349 00:59:45.380705 [ 0.000000] alternatives: applying boot alternatives
10350 00:59:45.387423 [ 0.000000] Fallback order for Node 0: 0
10351 00:59:45.393721 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10352 00:59:45.397411 [ 0.000000] Policy zone: Normal
10353 00:59:45.420621 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10354 00:59:45.430433 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10355 00:59:45.440646 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10356 00:59:45.450656 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10357 00:59:45.457307 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10358 00:59:45.460680 <6>[ 0.000000] software IO TLB: area num 8.
10359 00:59:45.517408 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10360 00:59:45.666369 <6>[ 0.000000] Memory: 7945764K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407004K reserved, 32768K cma-reserved)
10361 00:59:45.673058 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10362 00:59:45.679525 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10363 00:59:45.683268 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10364 00:59:45.689966 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10365 00:59:45.696624 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10366 00:59:45.699891 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10367 00:59:45.709792 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10368 00:59:45.716368 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10369 00:59:45.722867 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10370 00:59:45.729403 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10371 00:59:45.733149 <6>[ 0.000000] GICv3: 608 SPIs implemented
10372 00:59:45.736252 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10373 00:59:45.742628 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10374 00:59:45.745912 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10375 00:59:45.753278 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10376 00:59:45.766134 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10377 00:59:45.776447 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10378 00:59:45.786234 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10379 00:59:45.793210 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10380 00:59:45.806477 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10381 00:59:45.812691 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10382 00:59:45.819621 <6>[ 0.009183] Console: colour dummy device 80x25
10383 00:59:45.830075 <6>[ 0.013943] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10384 00:59:45.833440 <6>[ 0.024384] pid_max: default: 32768 minimum: 301
10385 00:59:45.840082 <6>[ 0.029256] LSM: Security Framework initializing
10386 00:59:45.846208 <6>[ 0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 00:59:45.856676 <6>[ 0.042084] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 00:59:45.863248 <6>[ 0.051559] cblist_init_generic: Setting adjustable number of callback queues.
10389 00:59:45.869849 <6>[ 0.059039] cblist_init_generic: Setting shift to 3 and lim to 1.
10390 00:59:45.879432 <6>[ 0.065378] cblist_init_generic: Setting adjustable number of callback queues.
10391 00:59:45.886171 <6>[ 0.072805] cblist_init_generic: Setting shift to 3 and lim to 1.
10392 00:59:45.889522 <6>[ 0.079206] rcu: Hierarchical SRCU implementation.
10393 00:59:45.896127 <6>[ 0.084252] rcu: Max phase no-delay instances is 1000.
10394 00:59:45.902538 <6>[ 0.091324] EFI services will not be available.
10395 00:59:45.906364 <6>[ 0.096280] smp: Bringing up secondary CPUs ...
10396 00:59:45.914039 <6>[ 0.101332] Detected VIPT I-cache on CPU1
10397 00:59:45.920837 <6>[ 0.101404] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10398 00:59:45.927814 <6>[ 0.101434] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10399 00:59:45.930970 <6>[ 0.101771] Detected VIPT I-cache on CPU2
10400 00:59:45.937393 <6>[ 0.101824] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10401 00:59:45.944049 <6>[ 0.101841] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10402 00:59:45.951038 <6>[ 0.102101] Detected VIPT I-cache on CPU3
10403 00:59:45.957252 <6>[ 0.102147] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10404 00:59:45.963871 <6>[ 0.102161] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10405 00:59:45.967249 <6>[ 0.102471] CPU features: detected: Spectre-v4
10406 00:59:45.973873 <6>[ 0.102477] CPU features: detected: Spectre-BHB
10407 00:59:45.977560 <6>[ 0.102482] Detected PIPT I-cache on CPU4
10408 00:59:45.983929 <6>[ 0.102542] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10409 00:59:45.990474 <6>[ 0.102559] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10410 00:59:45.997159 <6>[ 0.102852] Detected PIPT I-cache on CPU5
10411 00:59:46.003912 <6>[ 0.102916] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10412 00:59:46.010324 <6>[ 0.102932] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10413 00:59:46.013742 <6>[ 0.103218] Detected PIPT I-cache on CPU6
10414 00:59:46.020326 <6>[ 0.103286] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10415 00:59:46.026928 <6>[ 0.103302] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10416 00:59:46.033574 <6>[ 0.103599] Detected PIPT I-cache on CPU7
10417 00:59:46.040177 <6>[ 0.103666] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10418 00:59:46.047083 <6>[ 0.103681] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10419 00:59:46.050142 <6>[ 0.103728] smp: Brought up 1 node, 8 CPUs
10420 00:59:46.056931 <6>[ 0.245178] SMP: Total of 8 processors activated.
10421 00:59:46.060043 <6>[ 0.250099] CPU features: detected: 32-bit EL0 Support
10422 00:59:46.069953 <6>[ 0.255462] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10423 00:59:46.076745 <6>[ 0.264263] CPU features: detected: Common not Private translations
10424 00:59:46.079981 <6>[ 0.270779] CPU features: detected: CRC32 instructions
10425 00:59:46.087004 <6>[ 0.276164] CPU features: detected: RCpc load-acquire (LDAPR)
10426 00:59:46.093726 <6>[ 0.282161] CPU features: detected: LSE atomic instructions
10427 00:59:46.100118 <6>[ 0.287968] CPU features: detected: Privileged Access Never
10428 00:59:46.103418 <6>[ 0.293748] CPU features: detected: RAS Extension Support
10429 00:59:46.113269 <6>[ 0.299357] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10430 00:59:46.116979 <6>[ 0.306576] CPU: All CPU(s) started at EL2
10431 00:59:46.122945 <6>[ 0.310893] alternatives: applying system-wide alternatives
10432 00:59:46.132134 <6>[ 0.321737] devtmpfs: initialized
10433 00:59:46.144781 <6>[ 0.330676] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10434 00:59:46.154827 <6>[ 0.340642] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10435 00:59:46.157903 <6>[ 0.348463] pinctrl core: initialized pinctrl subsystem
10436 00:59:46.166004 <6>[ 0.355272] DMI not present or invalid.
10437 00:59:46.172780 <6>[ 0.359684] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10438 00:59:46.179206 <6>[ 0.366543] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10439 00:59:46.189251 <6>[ 0.374132] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10440 00:59:46.195713 <6>[ 0.382352] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10441 00:59:46.202490 <6>[ 0.390595] audit: initializing netlink subsys (disabled)
10442 00:59:46.208755 <5>[ 0.396289] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10443 00:59:46.215376 <6>[ 0.397056] thermal_sys: Registered thermal governor 'step_wise'
10444 00:59:46.221888 <6>[ 0.404258] thermal_sys: Registered thermal governor 'power_allocator'
10445 00:59:46.225415 <6>[ 0.410512] cpuidle: using governor menu
10446 00:59:46.232178 <6>[ 0.421473] NET: Registered PF_QIPCRTR protocol family
10447 00:59:46.238691 <6>[ 0.426963] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10448 00:59:46.245373 <6>[ 0.434066] ASID allocator initialised with 32768 entries
10449 00:59:46.252100 <6>[ 0.440703] Serial: AMBA PL011 UART driver
10450 00:59:46.260419 <4>[ 0.449907] Trying to register duplicate clock ID: 134
10451 00:59:46.320892 <6>[ 0.513797] KASLR enabled
10452 00:59:46.335288 <6>[ 0.521589] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10453 00:59:46.341839 <6>[ 0.528602] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10454 00:59:46.348756 <6>[ 0.535091] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10455 00:59:46.355034 <6>[ 0.542095] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10456 00:59:46.361919 <6>[ 0.548581] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10457 00:59:46.368678 <6>[ 0.555584] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10458 00:59:46.374793 <6>[ 0.562071] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10459 00:59:46.381832 <6>[ 0.569077] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10460 00:59:46.384835 <6>[ 0.576619] ACPI: Interpreter disabled.
10461 00:59:46.393451 <6>[ 0.583130] iommu: Default domain type: Translated
10462 00:59:46.400433 <6>[ 0.588243] iommu: DMA domain TLB invalidation policy: strict mode
10463 00:59:46.403726 <5>[ 0.594906] SCSI subsystem initialized
10464 00:59:46.410366 <6>[ 0.599074] usbcore: registered new interface driver usbfs
10465 00:59:46.417017 <6>[ 0.604806] usbcore: registered new interface driver hub
10466 00:59:46.419794 <6>[ 0.610361] usbcore: registered new device driver usb
10467 00:59:46.426964 <6>[ 0.616505] pps_core: LinuxPPS API ver. 1 registered
10468 00:59:46.436787 <6>[ 0.621700] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10469 00:59:46.440118 <6>[ 0.631046] PTP clock support registered
10470 00:59:46.443455 <6>[ 0.635292] EDAC MC: Ver: 3.0.0
10471 00:59:46.450785 <6>[ 0.640486] FPGA manager framework
10472 00:59:46.457433 <6>[ 0.644173] Advanced Linux Sound Architecture Driver Initialized.
10473 00:59:46.460484 <6>[ 0.650951] vgaarb: loaded
10474 00:59:46.467023 <6>[ 0.654112] clocksource: Switched to clocksource arch_sys_counter
10475 00:59:46.470886 <5>[ 0.660555] VFS: Disk quotas dquot_6.6.0
10476 00:59:46.477448 <6>[ 0.664743] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10477 00:59:46.480556 <6>[ 0.671935] pnp: PnP ACPI: disabled
10478 00:59:46.488970 <6>[ 0.678682] NET: Registered PF_INET protocol family
10479 00:59:46.495785 <6>[ 0.684277] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10480 00:59:46.510577 <6>[ 0.696583] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10481 00:59:46.520573 <6>[ 0.705397] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10482 00:59:46.527226 <6>[ 0.713368] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10483 00:59:46.533707 <6>[ 0.722069] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10484 00:59:46.545485 <6>[ 0.731820] TCP: Hash tables configured (established 65536 bind 65536)
10485 00:59:46.552638 <6>[ 0.738684] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10486 00:59:46.558734 <6>[ 0.745883] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 00:59:46.565862 <6>[ 0.753587] NET: Registered PF_UNIX/PF_LOCAL protocol family
10488 00:59:46.572555 <6>[ 0.759745] RPC: Registered named UNIX socket transport module.
10489 00:59:46.575673 <6>[ 0.765897] RPC: Registered udp transport module.
10490 00:59:46.581923 <6>[ 0.770830] RPC: Registered tcp transport module.
10491 00:59:46.588610 <6>[ 0.775761] RPC: Registered tcp NFSv4.1 backchannel transport module.
10492 00:59:46.592167 <6>[ 0.782428] PCI: CLS 0 bytes, default 64
10493 00:59:46.595677 <6>[ 0.786749] Unpacking initramfs...
10494 00:59:46.616516 <6>[ 0.802660] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10495 00:59:46.626197 <6>[ 0.811302] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10496 00:59:46.629612 <6>[ 0.820140] kvm [1]: IPA Size Limit: 40 bits
10497 00:59:46.636612 <6>[ 0.824667] kvm [1]: GICv3: no GICV resource entry
10498 00:59:46.639850 <6>[ 0.829689] kvm [1]: disabling GICv2 emulation
10499 00:59:46.646440 <6>[ 0.834374] kvm [1]: GIC system register CPU interface enabled
10500 00:59:46.649734 <6>[ 0.840525] kvm [1]: vgic interrupt IRQ18
10501 00:59:46.656370 <6>[ 0.844877] kvm [1]: VHE mode initialized successfully
10502 00:59:46.663070 <5>[ 0.851188] Initialise system trusted keyrings
10503 00:59:46.669450 <6>[ 0.855949] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10504 00:59:46.676130 <6>[ 0.865927] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10505 00:59:46.683041 <5>[ 0.872293] NFS: Registering the id_resolver key type
10506 00:59:46.686396 <5>[ 0.877588] Key type id_resolver registered
10507 00:59:46.692964 <5>[ 0.882003] Key type id_legacy registered
10508 00:59:46.699458 <6>[ 0.886279] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10509 00:59:46.706209 <6>[ 0.893202] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10510 00:59:46.712633 <6>[ 0.900909] 9p: Installing v9fs 9p2000 file system support
10511 00:59:46.749660 <5>[ 0.939241] Key type asymmetric registered
10512 00:59:46.752493 <5>[ 0.943575] Asymmetric key parser 'x509' registered
10513 00:59:46.762797 <6>[ 0.948712] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10514 00:59:46.766198 <6>[ 0.956325] io scheduler mq-deadline registered
10515 00:59:46.769415 <6>[ 0.961087] io scheduler kyber registered
10516 00:59:46.785819 <6>[ 0.978333] EINJ: ACPI disabled.
10517 00:59:46.821994 <4>[ 1.004896] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 00:59:46.831967 <4>[ 1.015617] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 00:59:46.847479 <6>[ 1.036697] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10520 00:59:46.854768 <6>[ 1.044698] printk: console [ttyS0] disabled
10521 00:59:46.882808 <6>[ 1.069332] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10522 00:59:46.889425 <6>[ 1.078811] printk: console [ttyS0] enabled
10523 00:59:46.893254 <6>[ 1.078811] printk: console [ttyS0] enabled
10524 00:59:46.899376 <6>[ 1.087707] printk: bootconsole [mtk8250] disabled
10525 00:59:46.903296 <6>[ 1.087707] printk: bootconsole [mtk8250] disabled
10526 00:59:46.909927 <6>[ 1.099018] SuperH (H)SCI(F) driver initialized
10527 00:59:46.912683 <6>[ 1.104318] msm_serial: driver initialized
10528 00:59:46.927393 <6>[ 1.113509] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10529 00:59:46.936976 <6>[ 1.122059] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10530 00:59:46.943578 <6>[ 1.130602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10531 00:59:46.953530 <6>[ 1.139230] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10532 00:59:46.963501 <6>[ 1.147937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10533 00:59:46.970094 <6>[ 1.156651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10534 00:59:46.980458 <6>[ 1.165191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10535 00:59:46.986747 <6>[ 1.173997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10536 00:59:46.996720 <6>[ 1.182545] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10537 00:59:47.008705 <6>[ 1.198662] loop: module loaded
10538 00:59:47.015875 <6>[ 1.204432] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10539 00:59:47.038370 <4>[ 1.228056] mtk-pmic-keys: Failed to locate of_node [id: -1]
10540 00:59:47.045267 <6>[ 1.234987] megasas: 07.719.03.00-rc1
10541 00:59:47.055182 <6>[ 1.244696] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10542 00:59:47.064493 <6>[ 1.253477] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10543 00:59:47.080232 <6>[ 1.269518] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10544 00:59:47.133996 <6>[ 1.317294] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10545 00:59:47.414562 <6>[ 1.604234] Freeing initrd memory: 18292K
10546 00:59:47.426018 <6>[ 1.615906] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10547 00:59:47.437277 <6>[ 1.627056] tun: Universal TUN/TAP device driver, 1.6
10548 00:59:47.441004 <6>[ 1.633160] thunder_xcv, ver 1.0
10549 00:59:47.444208 <6>[ 1.636663] thunder_bgx, ver 1.0
10550 00:59:47.447425 <6>[ 1.640165] nicpf, ver 1.0
10551 00:59:47.457741 <6>[ 1.644224] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10552 00:59:47.461418 <6>[ 1.651700] hns3: Copyright (c) 2017 Huawei Corporation.
10553 00:59:47.467625 <6>[ 1.657287] hclge is initializing
10554 00:59:47.470927 <6>[ 1.660872] e1000: Intel(R) PRO/1000 Network Driver
10555 00:59:47.478225 <6>[ 1.666001] e1000: Copyright (c) 1999-2006 Intel Corporation.
10556 00:59:47.481692 <6>[ 1.672017] e1000e: Intel(R) PRO/1000 Network Driver
10557 00:59:47.487949 <6>[ 1.677232] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10558 00:59:47.494433 <6>[ 1.683416] igb: Intel(R) Gigabit Ethernet Network Driver
10559 00:59:47.501077 <6>[ 1.689066] igb: Copyright (c) 2007-2014 Intel Corporation.
10560 00:59:47.507708 <6>[ 1.694903] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10561 00:59:47.511669 <6>[ 1.701421] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10562 00:59:47.518462 <6>[ 1.707887] sky2: driver version 1.30
10563 00:59:47.525249 <6>[ 1.712865] usbcore: registered new device driver r8152-cfgselector
10564 00:59:47.531658 <6>[ 1.719403] usbcore: registered new interface driver r8152
10565 00:59:47.534747 <6>[ 1.725224] VFIO - User Level meta-driver version: 0.3
10566 00:59:47.543716 <6>[ 1.733572] usbcore: registered new interface driver usb-storage
10567 00:59:47.550373 <6>[ 1.740028] usbcore: registered new device driver onboard-usb-hub
10568 00:59:47.559621 <6>[ 1.749275] mt6397-rtc mt6359-rtc: registered as rtc0
10569 00:59:47.569941 <6>[ 1.754742] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:59:47 UTC (1718499587)
10570 00:59:47.573354 <6>[ 1.764331] i2c_dev: i2c /dev entries driver
10571 00:59:47.587084 <4>[ 1.776655] cpu cpu0: supply cpu not found, using dummy regulator
10572 00:59:47.593480 <4>[ 1.783079] cpu cpu1: supply cpu not found, using dummy regulator
10573 00:59:47.600592 <4>[ 1.789477] cpu cpu2: supply cpu not found, using dummy regulator
10574 00:59:47.607310 <4>[ 1.795881] cpu cpu3: supply cpu not found, using dummy regulator
10575 00:59:47.613415 <4>[ 1.802284] cpu cpu4: supply cpu not found, using dummy regulator
10576 00:59:47.620102 <4>[ 1.808698] cpu cpu5: supply cpu not found, using dummy regulator
10577 00:59:47.626912 <4>[ 1.815095] cpu cpu6: supply cpu not found, using dummy regulator
10578 00:59:47.633723 <4>[ 1.821496] cpu cpu7: supply cpu not found, using dummy regulator
10579 00:59:47.652877 <6>[ 1.842139] cpu cpu0: EM: created perf domain
10580 00:59:47.655500 <6>[ 1.847060] cpu cpu4: EM: created perf domain
10581 00:59:47.663265 <6>[ 1.852682] sdhci: Secure Digital Host Controller Interface driver
10582 00:59:47.669409 <6>[ 1.859114] sdhci: Copyright(c) Pierre Ossman
10583 00:59:47.676582 <6>[ 1.864081] Synopsys Designware Multimedia Card Interface Driver
10584 00:59:47.683214 <6>[ 1.870731] sdhci-pltfm: SDHCI platform and OF driver helper
10585 00:59:47.686483 <6>[ 1.870833] mmc0: CQHCI version 5.10
10586 00:59:47.693219 <6>[ 1.880736] ledtrig-cpu: registered to indicate activity on CPUs
10587 00:59:47.699655 <6>[ 1.887650] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 00:59:47.706340 <6>[ 1.894717] usbcore: registered new interface driver usbhid
10589 00:59:47.710021 <6>[ 1.900539] usbhid: USB HID core driver
10590 00:59:47.716451 <6>[ 1.904739] spi_master spi0: will run message pump with realtime priority
10591 00:59:47.763174 <6>[ 1.946433] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10592 00:59:47.782402 <6>[ 1.962126] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10593 00:59:47.785523 <6>[ 1.971240] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10594 00:59:47.794267 <6>[ 1.984096] cros-ec-spi spi0.0: Chrome EC device registered
10595 00:59:47.801141 <6>[ 1.990085] mmc0: Command Queue Engine enabled
10596 00:59:47.807675 <6>[ 1.994826] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 00:59:47.810954 <6>[ 2.002633] mmcblk0: mmc0:0001 DA4128 116 GiB
10598 00:59:47.823517 <6>[ 2.013359] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10599 00:59:47.831582 <6>[ 2.021197] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10600 00:59:47.841980 <6>[ 2.025043] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10601 00:59:47.845044 <6>[ 2.027188] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10602 00:59:47.852187 <6>[ 2.037113] NET: Registered PF_PACKET protocol family
10603 00:59:47.858260 <6>[ 2.041726] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10604 00:59:47.862069 <6>[ 2.046362] 9pnet: Installing 9P2000 support
10605 00:59:47.868722 <5>[ 2.057372] Key type dns_resolver registered
10606 00:59:47.872084 <6>[ 2.062501] registered taskstats version 1
10607 00:59:47.878758 <5>[ 2.066885] Loading compiled-in X.509 certificates
10608 00:59:47.908336 <4>[ 2.091197] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 00:59:47.917831 <4>[ 2.101966] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 00:59:47.933171 <6>[ 2.122699] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10611 00:59:47.939746 <6>[ 2.129602] xhci-mtk 11200000.usb: xHCI Host Controller
10612 00:59:47.946356 <6>[ 2.135124] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10613 00:59:47.956950 <6>[ 2.142980] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10614 00:59:47.963453 <6>[ 2.152410] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10615 00:59:47.970347 <6>[ 2.158498] xhci-mtk 11200000.usb: xHCI Host Controller
10616 00:59:47.976822 <6>[ 2.163984] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10617 00:59:47.983514 <6>[ 2.171763] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10618 00:59:47.990437 <6>[ 2.179594] hub 1-0:1.0: USB hub found
10619 00:59:47.993625 <6>[ 2.183621] hub 1-0:1.0: 1 port detected
10620 00:59:47.999729 <6>[ 2.187945] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10621 00:59:48.006965 <6>[ 2.196680] hub 2-0:1.0: USB hub found
10622 00:59:48.009942 <6>[ 2.200705] hub 2-0:1.0: 1 port detected
10623 00:59:48.018354 <6>[ 2.207848] mtk-msdc 11f70000.mmc: Got CD GPIO
10624 00:59:48.032741 <6>[ 2.219348] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10625 00:59:48.040048 <6>[ 2.227741] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10626 00:59:48.049945 <6>[ 2.236080] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10627 00:59:48.056568 <6>[ 2.244421] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10628 00:59:48.066574 <6>[ 2.252760] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10629 00:59:48.076458 <6>[ 2.261098] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10630 00:59:48.083036 <6>[ 2.269436] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10631 00:59:48.093031 <6>[ 2.277775] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10632 00:59:48.099444 <6>[ 2.286117] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10633 00:59:48.109335 <6>[ 2.294455] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10634 00:59:48.116350 <6>[ 2.302793] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10635 00:59:48.126342 <6>[ 2.311137] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10636 00:59:48.132656 <6>[ 2.319475] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10637 00:59:48.143029 <6>[ 2.327813] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10638 00:59:48.149614 <6>[ 2.336151] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10639 00:59:48.156217 <6>[ 2.344851] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10640 00:59:48.162871 <6>[ 2.352004] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10641 00:59:48.169004 <6>[ 2.358820] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10642 00:59:48.176278 <6>[ 2.365590] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10643 00:59:48.186028 <6>[ 2.372522] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10644 00:59:48.192782 <6>[ 2.379395] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10645 00:59:48.202630 <6>[ 2.388528] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10646 00:59:48.212906 <6>[ 2.397647] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10647 00:59:48.222337 <6>[ 2.406940] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10648 00:59:48.232597 <6>[ 2.416408] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10649 00:59:48.239405 <6>[ 2.425875] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10650 00:59:48.249368 <6>[ 2.434994] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10651 00:59:48.259192 <6>[ 2.444461] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10652 00:59:48.268952 <6>[ 2.453583] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10653 00:59:48.279281 <6>[ 2.462876] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10654 00:59:48.288952 <6>[ 2.473036] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10655 00:59:48.298758 <6>[ 2.485065] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10656 00:59:48.306253 <6>[ 2.495996] Trying to probe devices needed for running init ...
10657 00:59:48.316920 <3>[ 2.503197] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10658 00:59:48.424080 <6>[ 2.610393] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10659 00:59:48.578437 <6>[ 2.768260] hub 1-1:1.0: USB hub found
10660 00:59:48.581690 <6>[ 2.772777] hub 1-1:1.0: 4 ports detected
10661 00:59:48.593816 <6>[ 2.783424] hub 1-1:1.0: USB hub found
10662 00:59:48.597149 <6>[ 2.787838] hub 1-1:1.0: 4 ports detected
10663 00:59:48.704105 <6>[ 2.890621] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10664 00:59:48.730939 <6>[ 2.920403] hub 2-1:1.0: USB hub found
10665 00:59:48.734134 <6>[ 2.924901] hub 2-1:1.0: 3 ports detected
10666 00:59:48.746081 <6>[ 2.936012] hub 2-1:1.0: USB hub found
10667 00:59:48.749854 <6>[ 2.940445] hub 2-1:1.0: 3 ports detected
10668 00:59:48.920120 <6>[ 3.106431] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10669 00:59:49.052461 <6>[ 3.242388] hub 1-1.4:1.0: USB hub found
10670 00:59:49.055675 <6>[ 3.247060] hub 1-1.4:1.0: 2 ports detected
10671 00:59:49.068200 <6>[ 3.258082] hub 1-1.4:1.0: USB hub found
10672 00:59:49.071480 <6>[ 3.262657] hub 1-1.4:1.0: 2 ports detected
10673 00:59:49.132346 <6>[ 3.318654] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10674 00:59:49.240504 <6>[ 3.427071] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10675 00:59:49.276027 <4>[ 3.462502] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10676 00:59:49.285434 <4>[ 3.471598] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10677 00:59:49.330569 <6>[ 3.520404] r8152 2-1.3:1.0 eth0: v1.12.13
10678 00:59:49.371441 <6>[ 3.558314] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10679 00:59:49.568061 <6>[ 3.754448] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10680 00:59:50.986071 <6>[ 5.175973] r8152 2-1.3:1.0 eth0: carrier on
10681 00:59:53.483828 <5>[ 5.202225] Sending DHCP requests .., OK
10682 00:59:53.490699 <6>[ 7.678567] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10683 00:59:53.493922 <6>[ 7.686860] IP-Config: Complete:
10684 00:59:53.506873 <6>[ 7.690350] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10685 00:59:53.513368 <6>[ 7.701100] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10686 00:59:53.523888 <6>[ 7.709724] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10687 00:59:53.527067 <6>[ 7.709733] nameserver0=192.168.201.1
10688 00:59:53.530306 <6>[ 7.721877] clk: Disabling unused clocks
10689 00:59:53.533539 <6>[ 7.727402] ALSA device list:
10690 00:59:53.540063 <6>[ 7.730681] No soundcards found.
10691 00:59:53.548501 <6>[ 7.738435] Freeing unused kernel memory: 8512K
10692 00:59:53.551602 <6>[ 7.743344] Run /init as init process
10693 00:59:53.561026 Loading, please wait...
10694 00:59:53.593080 Starting systemd-udevd version 252.22-1~deb12u1
10695 00:59:53.834011 <6>[ 8.020917] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10696 00:59:53.850448 <6>[ 8.037365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10697 00:59:53.856951 <6>[ 8.045471] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10698 00:59:53.867158 <4>[ 8.054093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10699 00:59:53.876942 <6>[ 8.063912] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10700 00:59:53.883505 <6>[ 8.072084] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10701 00:59:53.893732 <6>[ 8.080539] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10702 00:59:53.897182 <6>[ 8.080806] mc: Linux media interface: v0.10
10703 00:59:53.907180 <6>[ 8.081294] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10704 00:59:53.913435 <6>[ 8.088500] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10705 00:59:53.919956 <6>[ 8.088503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10706 00:59:53.930187 <6>[ 8.088507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10707 00:59:53.936578 <6>[ 8.102917] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10708 00:59:53.943192 <6>[ 8.108964] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10709 00:59:53.953130 <4>[ 8.111291] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10710 00:59:53.959885 <4>[ 8.127649] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 00:59:53.969928 <6>[ 8.132886] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10712 00:59:53.973124 <6>[ 8.140917] remoteproc remoteproc0: scp is available
10713 00:59:53.983283 <6>[ 8.147841] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10714 00:59:53.990061 <3>[ 8.149687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 00:59:53.996491 <6>[ 8.155556] remoteproc remoteproc0: powering up scp
10716 00:59:54.003526 <3>[ 8.164213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 00:59:54.013086 <6>[ 8.169220] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10718 00:59:54.016762 <6>[ 8.169257] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10719 00:59:54.026553 <3>[ 8.177943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 00:59:54.036500 <6>[ 8.198593] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10721 00:59:54.042655 <3>[ 8.199307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 00:59:54.052768 <6>[ 8.208092] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10723 00:59:54.062903 <3>[ 8.213319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 00:59:54.069464 <3>[ 8.213323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 00:59:54.079327 <3>[ 8.213330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 00:59:54.085862 <3>[ 8.213334] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 00:59:54.092458 <3>[ 8.213361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 00:59:54.102005 <3>[ 8.213400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 00:59:54.108726 <3>[ 8.213403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 00:59:54.118836 <3>[ 8.213405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 00:59:54.125694 <3>[ 8.213431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 00:59:54.135490 <6>[ 8.245904] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10733 00:59:54.141842 <3>[ 8.248719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 00:59:54.151750 <6>[ 8.270270] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10735 00:59:54.158210 <3>[ 8.272974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 00:59:54.164896 <6>[ 8.273376] videodev: Linux video capture interface: v2.00
10737 00:59:54.171248 <6>[ 8.281148] pci_bus 0000:00: root bus resource [bus 00-ff]
10738 00:59:54.178235 <3>[ 8.289124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 00:59:54.184565 <6>[ 8.297218] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10740 00:59:54.194781 <3>[ 8.305294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 00:59:54.201165 <6>[ 8.313478] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10742 00:59:54.207583 <6>[ 8.313489] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10743 00:59:54.218407 <6>[ 8.313612] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10744 00:59:54.225441 <6>[ 8.313653] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10745 00:59:54.232207 <6>[ 8.313673] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10746 00:59:54.238962 <6>[ 8.313756] pci 0000:00:00.0: supports D1 D2
10747 00:59:54.245307 <6>[ 8.313759] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 00:59:54.251839 <6>[ 8.315466] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10749 00:59:54.258594 <6>[ 8.315590] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10750 00:59:54.264859 <6>[ 8.315623] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10751 00:59:54.274837 <6>[ 8.315643] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10752 00:59:54.281982 <6>[ 8.315661] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10753 00:59:54.285694 <6>[ 8.315789] pci 0000:01:00.0: supports D1 D2
10754 00:59:54.291834 <6>[ 8.315792] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10755 00:59:54.302045 <3>[ 8.321522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 00:59:54.308505 <6>[ 8.323603] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10757 00:59:54.314839 <6>[ 8.326012] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10758 00:59:54.321917 <6>[ 8.330786] remoteproc remoteproc0: remote processor scp is now up
10759 00:59:54.328302 <6>[ 8.331476] Bluetooth: Core ver 2.22
10760 00:59:54.334640 <6>[ 8.334199] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10761 00:59:54.341617 <6>[ 8.334238] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10762 00:59:54.351468 <6>[ 8.334247] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10763 00:59:54.358026 <6>[ 8.334262] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10764 00:59:54.364981 <6>[ 8.334280] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10765 00:59:54.375058 <6>[ 8.334297] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10766 00:59:54.378225 <6>[ 8.334315] pci 0000:00:00.0: PCI bridge to [bus 01]
10767 00:59:54.388249 <6>[ 8.334325] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10768 00:59:54.394509 <6>[ 8.334488] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10769 00:59:54.397746 <6>[ 8.335565] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10770 00:59:54.404716 <6>[ 8.335810] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10771 00:59:54.411580 <6>[ 8.340968] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10772 00:59:54.418014 <6>[ 8.345902] NET: Registered PF_BLUETOOTH protocol family
10773 00:59:54.424496 <5>[ 8.348315] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10774 00:59:54.437601 <6>[ 8.356402] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10775 00:59:54.444494 <6>[ 8.359634] Bluetooth: HCI device and connection manager initialized
10776 00:59:54.451065 <6>[ 8.359675] Bluetooth: HCI socket layer initialized
10777 00:59:54.457505 <5>[ 8.361134] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10778 00:59:54.463981 <5>[ 8.361581] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10779 00:59:54.473988 <4>[ 8.361659] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10780 00:59:54.477735 <6>[ 8.361667] cfg80211: failed to load regulatory.db
10781 00:59:54.484102 <6>[ 8.365652] usbcore: registered new interface driver uvcvideo
10782 00:59:54.490857 <6>[ 8.373459] Bluetooth: L2CAP socket layer initialized
10783 00:59:54.497728 <4>[ 8.382561] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10784 00:59:54.503947 <4>[ 8.382561] Fallback method does not support PEC.
10785 00:59:54.510698 <6>[ 8.383090] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10786 00:59:54.517410 <6>[ 8.388666] Bluetooth: SCO socket layer initialized
10787 00:59:54.523865 <3>[ 8.413653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10788 00:59:54.530800 <6>[ 8.459773] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10789 00:59:54.537080 <6>[ 8.461783] usbcore: registered new interface driver btusb
10790 00:59:54.547155 <4>[ 8.462583] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10791 00:59:54.553894 <3>[ 8.462598] Bluetooth: hci0: Failed to load firmware file (-2)
10792 00:59:54.560438 <3>[ 8.462602] Bluetooth: hci0: Failed to set up firmware (-2)
10793 00:59:54.570280 <4>[ 8.462607] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10794 00:59:54.577288 <6>[ 8.468835] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10795 00:59:54.587228 <3>[ 8.482843] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10796 00:59:54.589829 <6>[ 8.507974] mt7921e 0000:01:00.0: ASIC revision: 79610010
10797 00:59:54.695488 <6>[ 8.882846] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10798 00:59:54.698674 <6>[ 8.882846]
10799 00:59:54.712573 Begin: Loading essential drivers ... done.
10800 00:59:54.716337 Begin: Running /scripts/init-premount ... done.
10801 00:59:54.722820 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10802 00:59:54.732804 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10803 00:59:54.735941 Device /sys/class/net/eth0 found
10804 00:59:54.736042 done.
10805 00:59:54.767796 Begin: Waiting up to 180 secs for any network device to become available ... done.
10806 00:59:54.827985 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10807 00:59:54.834535 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10808 00:59:54.841484 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10809 00:59:54.847940 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10810 00:59:54.854671 host : mt8192-asurada-spherion-r0-cbg-0
10811 00:59:54.861371 domain : lava-rack
10812 00:59:54.864566 rootserver: 192.168.201.1 rootpath:
10813 00:59:54.864672 filename :
10814 00:59:54.864761 done.
10815 00:59:54.871103 Begin: Running /scripts/nfs-bottom ... done.
10816 00:59:54.889923 Begin: Running /scripts/init-bottom ... done.
10817 00:59:54.965945 <6>[ 9.152920] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10818 00:59:56.193035 <6>[ 10.383347] NET: Registered PF_INET6 protocol family
10819 00:59:56.200175 <6>[ 10.390711] Segment Routing with IPv6
10820 00:59:56.203635 <6>[ 10.394688] In-situ OAM (IOAM) with IPv6
10821 00:59:56.364543 <30>[ 10.528808] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10822 00:59:56.371117 <30>[ 10.561943] systemd[1]: Detected architecture arm64.
10823 00:59:56.377481
10824 00:59:56.380707 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10825 00:59:56.380783
10826 00:59:56.404382 <30>[ 10.595157] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10827 00:59:57.308133 <30>[ 11.495590] systemd[1]: Queued start job for default target graphical.target.
10828 00:59:57.360219 <30>[ 11.547285] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10829 00:59:57.366585 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10830 00:59:57.388843 <30>[ 11.576151] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10831 00:59:57.398330 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10832 00:59:57.416536 <30>[ 11.604150] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10833 00:59:57.426881 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10834 00:59:57.444679 <30>[ 11.631803] systemd[1]: Created slice user.slice - User and Session Slice.
10835 00:59:57.451133 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10836 00:59:57.475460 <30>[ 11.659284] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10837 00:59:57.485353 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10838 00:59:57.502454 <30>[ 11.686638] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10839 00:59:57.508921 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10840 00:59:57.537468 <30>[ 11.715031] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10841 00:59:57.547338 <30>[ 11.734931] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10842 00:59:57.554178 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10843 00:59:57.571368 <30>[ 11.758820] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10844 00:59:57.581298 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10845 00:59:57.599854 <30>[ 11.786924] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10846 00:59:57.609598 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10847 00:59:57.624062 <30>[ 11.814928] systemd[1]: Reached target paths.target - Path Units.
10848 00:59:57.633924 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10849 00:59:57.651477 <30>[ 11.838884] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10850 00:59:57.657847 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10851 00:59:57.671779 <30>[ 11.862389] systemd[1]: Reached target slices.target - Slice Units.
10852 00:59:57.681599 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10853 00:59:57.696246 <30>[ 11.886882] systemd[1]: Reached target swap.target - Swaps.
10854 00:59:57.702787 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10855 00:59:57.723341 <30>[ 11.910918] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10856 00:59:57.733499 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10857 00:59:57.752142 <30>[ 11.939407] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10858 00:59:57.762080 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10859 00:59:57.780820 <30>[ 11.968376] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10860 00:59:57.790393 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10861 00:59:57.808320 <30>[ 11.995569] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10862 00:59:57.817986 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10863 00:59:57.835326 <30>[ 12.023094] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10864 00:59:57.842192 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10865 00:59:57.860025 <30>[ 12.047728] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10866 00:59:57.870470 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10867 00:59:57.889046 <30>[ 12.076724] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10868 00:59:57.899301 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10869 00:59:57.916123 <30>[ 12.103407] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10870 00:59:57.925896 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10871 00:59:57.979444 <30>[ 12.166622] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10872 00:59:57.985871 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10873 00:59:58.007449 <30>[ 12.195164] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10874 00:59:58.014612 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10875 00:59:58.059494 <30>[ 12.246791] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10876 00:59:58.066155 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10877 00:59:58.093855 <30>[ 12.275002] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10878 00:59:58.109104 <30>[ 12.296807] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10879 00:59:58.118989 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10880 00:59:58.140562 <30>[ 12.327927] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10881 00:59:58.146994 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10882 00:59:58.172863 <30>[ 12.360155] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10883 00:59:58.179447 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10884 00:59:58.210390 <6>[ 12.398034] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10885 00:59:58.231993 <30>[ 12.419279] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10886 00:59:58.238503 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10887 00:59:58.262518 <30>[ 12.449716] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10888 00:59:58.271760 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10889 00:59:58.296908 <30>[ 12.484355] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10890 00:59:58.303847 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10891 00:59:58.329799 <30>[ 12.517028] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10892 00:59:58.339592 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.530092] fuse: init (API version 7.37)
10893 00:59:58.342882 el Module loop...
10894 00:59:58.369117 <30>[ 12.556170] systemd[1]: Starting systemd-journald.service - Journal Service...
10895 00:59:58.375033 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10896 00:59:58.427418 <30>[ 12.615093] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10897 00:59:58.434148 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10898 00:59:58.464211 <30>[ 12.648406] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10899 00:59:58.470864 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10900 00:59:58.496535 <30>[ 12.683760] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10901 00:59:58.513020 Starting [0;1;39msystemd-remount-f…nt Root and Kerne<3>[ 12.697777] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 00:59:58.513106 l File Systems...
10903 00:59:58.536426 <30>[ 12.723071] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10904 00:59:58.546808 Startin<3>[ 12.732393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 00:59:58.553037 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10906 00:59:58.579788 <30>[ 12.767455] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10907 00:59:58.587044 <3>[ 12.768159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 00:59:58.596706 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10909 00:59:58.615627 <30>[ 12.802973] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10910 00:59:58.625528 <3>[ 12.807429] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 00:59:58.632003 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10912 00:59:58.651601 <30>[ 12.838956] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10913 00:59:58.658168 <3>[ 12.843717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 00:59:58.668280 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10915 00:59:58.688514 <30>[ 12.875614] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10916 00:59:58.698559 <3>[ 12.884365] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 00:59:58.705149 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10918 00:59:58.722123 <30>[ 12.911974] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10919 00:59:58.731945 <3>[ 12.919411] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 00:59:58.742410 <30>[ 12.928939] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10921 00:59:58.756779 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 12.943662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 00:59:58.760026 le configfs.
10923 00:59:58.775728 <30>[ 12.963319] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10924 00:59:58.783029 <30>[ 12.971566] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10925 00:59:58.792984 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10926 00:59:58.813055 <30>[ 13.000497] systemd[1]: modprobe@drm.service: Deactivated successfully.
10927 00:59:58.819489 <30>[ 13.008440] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10928 00:59:58.829200 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10929 00:59:58.847716 <30>[ 13.035158] systemd[1]: Started systemd-journald.service - Journal Service.
10930 00:59:58.854266 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10931 00:59:58.876381 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10932 00:59:58.897727 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10933 00:59:58.918126 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10934 00:59:58.937750 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10935 00:59:58.957219 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10936 00:59:58.973945 <4>[ 13.154916] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10937 00:59:58.983724 <3>[ 13.170577] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10938 00:59:58.990749 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10939 00:59:59.011077 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10940 00:59:59.030193 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10941 00:59:59.087528 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10942 00:59:59.107964 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10943 00:59:59.132135 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10944 00:59:59.154935 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10945 00:59:59.190102 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<46>[ 13.377550] systemd-journald[313]: Received client request to flush runtime journal.
10946 00:59:59.190193 .
10947 00:59:59.215462 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10948 00:59:59.242541 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10949 00:59:59.263858 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10950 00:59:59.284287 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10951 01:00:00.288736 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10952 01:00:00.317223 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10953 01:00:00.371765 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10954 01:00:00.610659 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10955 01:00:00.706605 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10956 01:00:00.723335 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10957 01:00:00.747245 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10958 01:00:00.799824 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10959 01:00:00.823313 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10960 01:00:00.997213 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10961 01:00:01.060830 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10962 01:00:01.081887 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10963 01:00:01.119902 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10964 01:00:01.300239 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10965 01:00:01.330625 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10966 01:00:01.399511 <6>[ 15.590548] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10967 01:00:01.495841 <4>[ 15.686574] power_supply_show_property: 4 callbacks suppressed
10968 01:00:01.505742 <3>[ 15.686584] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 01:00:01.512253 <3>[ 15.687365] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10970 01:00:01.524393 <3>[ 15.712253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 01:00:01.553500 <3>[ 15.741225] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 01:00:01.571315 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10973 01:00:01.586516 <3>[ 15.774330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 01:00:01.619392 [[0;32m OK [0m] Created slice [0;1;39msyste<3>[ 15.806335] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 01:00:01.625934 m-syste…- Slice /system/systemd-backlight.
10976 01:00:01.644925 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10977 01:00:01.652020 <3>[ 15.840266] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 01:00:01.666855 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10979 01:00:01.683643 <3>[ 15.871306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 01:00:01.712297 <3>[ 15.899983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 01:00:01.722157 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10982 01:00:01.742686 [[0;32m OK [0m] Started [0;<3>[ 15.929761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 01:00:01.749529 1;39msystemd-networkd.service[0m - Network Configuration.
10984 01:00:01.768177 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10985 01:00:01.788930 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10986 01:00:01.819537 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10987 01:00:01.838710 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10988 01:00:01.858775 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10989 01:00:01.878575 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10990 01:00:01.901706 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10991 01:00:01.925534 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10992 01:00:01.946717 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10993 01:00:01.969370 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10994 01:00:01.993768 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10995 01:00:02.014556 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10996 01:00:02.032476 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10997 01:00:02.055048 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10998 01:00:02.061557 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10999 01:00:02.099640 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11000 01:00:02.208291 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11001 01:00:02.273927 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11002 01:00:02.299181 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11003 01:00:02.319590 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11004 01:00:02.384149 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11005 01:00:02.409245 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11006 01:00:02.458769 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11007 01:00:02.485527 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11008 01:00:02.503343 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11009 01:00:02.524069 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11010 01:00:02.565667 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11011 01:00:02.618803 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11012 01:00:02.641168 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11013 01:00:02.658695 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11014 01:00:02.702060 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11015 01:00:02.750262 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11016 01:00:02.811842
11017 01:00:02.815035 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11018 01:00:02.815151
11019 01:00:02.818854 debian-bookworm-arm64 login: root (automatic login)
11020 01:00:02.818938
11021 01:00:03.038235 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11022 01:00:03.038372
11023 01:00:03.044507 The programs included with the Debian GNU/Linux system are free software;
11024 01:00:03.051391 the exact distribution terms for each program are described in the
11025 01:00:03.054735 individual files in /usr/share/doc/*/copyright.
11026 01:00:03.054852
11027 01:00:03.060790 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11028 01:00:03.064394 permitted by applicable law.
11029 01:00:03.131824 Matched prompt #10: / #
11031 01:00:03.132082 Setting prompt string to ['/ #']
11032 01:00:03.132177 end: 2.2.5.1 login-action (duration 00:00:18) [common]
11034 01:00:03.132358 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
11035 01:00:03.132442 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11036 01:00:03.132509 Setting prompt string to ['/ #']
11037 01:00:03.132569 Forcing a shell prompt, looking for ['/ #']
11039 01:00:03.182798 / #
11040 01:00:03.183021 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11041 01:00:03.183096 Waiting using forced prompt support (timeout 00:02:30)
11042 01:00:03.187977
11043 01:00:03.188260 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11044 01:00:03.188355 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11046 01:00:03.288691 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw'
11047 01:00:03.294632 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368619/extract-nfsrootfs-jj3gjcjw'
11049 01:00:03.395172 / # export NFS_SERVER_IP='192.168.201.1'
11050 01:00:03.400317 export NFS_SERVER_IP='192.168.201.1'
11051 01:00:03.400610 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11052 01:00:03.400699 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11053 01:00:03.400787 end: 2 depthcharge-action (duration 00:01:23) [common]
11054 01:00:03.400872 start: 3 lava-test-retry (timeout 00:01:00) [common]
11055 01:00:03.400958 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11056 01:00:03.401026 Using namespace: common
11058 01:00:03.501353 / # #
11059 01:00:03.501601 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11060 01:00:03.506853 #
11061 01:00:03.507123 Using /lava-14368619
11063 01:00:03.607476 / # export SHELL=/bin/sh
11064 01:00:03.612603 export SHELL=/bin/sh
11066 01:00:03.713134 / # . /lava-14368619/environment
11067 01:00:03.718067 . /lava-14368619/environment
11069 01:00:03.824235 / # /lava-14368619/bin/lava-test-runner /lava-14368619/0
11070 01:00:03.824480 Test shell timeout: 10s (minimum of the action and connection timeout)
11071 01:00:03.830097 /lava-14368619/bin/lava-test-runner /lava-14368619/0
11072 01:00:04.011168 + export TESTRUN_ID=0_dmesg
11073 01:00:04.014179 + cd /lava-14368619/0/tests/0_dmesg
11074 01:00:04.017336 + cat uuid
11075 01:00:04.024292 + UUID=14368619_1.<8>[ 18.214477] <LAVA_SIGNAL_STARTRUN 0_dmesg 14368619_1.6.2.3.1>
11076 01:00:04.024591 Received signal: <STARTRUN> 0_dmesg 14368619_1.6.2.3.1
11077 01:00:04.024690 Starting test lava.0_dmesg (14368619_1.6.2.3.1)
11078 01:00:04.024787 Skipping test definition patterns.
11079 01:00:04.027584 6.2.3.1
11080 01:00:04.027677 + set +x
11081 01:00:04.030955 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11082 01:00:04.115960 <8>[ 18.303994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11083 01:00:04.116262 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11085 01:00:04.169314 <8>[ 18.357598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11086 01:00:04.169573 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11088 01:00:04.230362 <8>[ 18.418311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11089 01:00:04.230655 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11091 01:00:04.233514 + set +x
11092 01:00:04.236728 Received signal: <ENDRUN> 0_dmesg 14368619_1.6.2.3.1
11093 01:00:04.236823 Ending use of test pattern.
11094 01:00:04.236885 Ending test lava.0_dmesg (14368619_1.6.2.3.1), duration 0.21
11096 01:00:04.240232 <8>[ 18.428210] <LAVA_SIGNAL_ENDRUN 0_dmesg 14368619_1.6.2.3.1>
11097 01:00:04.243333 <LAVA_TEST_RUNNER EXIT>
11098 01:00:04.243586 ok: lava_test_shell seems to have completed
11099 01:00:04.243689 alert: pass
crit: pass
emerg: pass
11100 01:00:04.243775 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11101 01:00:04.243854 end: 3 lava-test-retry (duration 00:00:01) [common]
11102 01:00:04.243939 start: 4 finalize (timeout 00:08:10) [common]
11103 01:00:04.244017 start: 4.1 power-off (timeout 00:00:30) [common]
11104 01:00:04.244151 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11105 01:00:06.330931 >> Command sent successfully.
11106 01:00:06.334065 Returned 0 in 2 seconds
11107 01:00:06.434422 end: 4.1 power-off (duration 00:00:02) [common]
11109 01:00:06.434732 start: 4.2 read-feedback (timeout 00:08:08) [common]
11110 01:00:06.434961 Listened to connection for namespace 'common' for up to 1s
11111 01:00:07.435958 Finalising connection for namespace 'common'
11112 01:00:07.436125 Disconnecting from shell: Finalise
11113 01:00:07.436202 / #
11114 01:00:07.536485 end: 4.2 read-feedback (duration 00:00:01) [common]
11115 01:00:07.536650 end: 4 finalize (duration 00:00:03) [common]
11116 01:00:07.536764 Cleaning after the job
11117 01:00:07.536859 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/ramdisk
11118 01:00:07.539035 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/kernel
11119 01:00:07.549730 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/dtb
11120 01:00:07.549947 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/nfsrootfs
11121 01:00:07.606931 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368619/tftp-deploy-trdb_me4/modules
11122 01:00:07.612646 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368619
11123 01:00:07.929705 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368619
11124 01:00:07.929881 Job finished correctly