Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:58:24.583592 lava-dispatcher, installed at version: 2024.03
2 00:58:24.583827 start: 0 validate
3 00:58:24.583951 Start time: 2024-06-16 00:58:24.583943+00:00 (UTC)
4 00:58:24.584082 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:58:24.584221 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:58:24.853713 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:58:24.853880 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:58:25.102738 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:58:25.102925 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:58:25.352828 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:58:25.352976 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:58:25.604152 validate duration: 1.02
14 00:58:25.604430 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:58:25.604543 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:58:25.604637 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:58:25.604846 Not decompressing ramdisk as can be used compressed.
18 00:58:25.604941 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 00:58:25.605016 saving as /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/ramdisk/rootfs.cpio.gz
20 00:58:25.605088 total size: 39026414 (37 MB)
21 00:58:25.606191 progress 0 % (0 MB)
22 00:58:25.616833 progress 5 % (1 MB)
23 00:58:25.627182 progress 10 % (3 MB)
24 00:58:25.637196 progress 15 % (5 MB)
25 00:58:25.647328 progress 20 % (7 MB)
26 00:58:25.657360 progress 25 % (9 MB)
27 00:58:25.667532 progress 30 % (11 MB)
28 00:58:25.677619 progress 35 % (13 MB)
29 00:58:25.687784 progress 40 % (14 MB)
30 00:58:25.698011 progress 45 % (16 MB)
31 00:58:25.708139 progress 50 % (18 MB)
32 00:58:25.718207 progress 55 % (20 MB)
33 00:58:25.728079 progress 60 % (22 MB)
34 00:58:25.738028 progress 65 % (24 MB)
35 00:58:25.747913 progress 70 % (26 MB)
36 00:58:25.758035 progress 75 % (27 MB)
37 00:58:25.767775 progress 80 % (29 MB)
38 00:58:25.777609 progress 85 % (31 MB)
39 00:58:25.787256 progress 90 % (33 MB)
40 00:58:25.796863 progress 95 % (35 MB)
41 00:58:25.806377 progress 100 % (37 MB)
42 00:58:25.806722 37 MB downloaded in 0.20 s (184.59 MB/s)
43 00:58:25.806880 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:58:25.807104 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:58:25.807185 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:58:25.807260 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:58:25.807394 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:58:25.807456 saving as /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/kernel/Image
50 00:58:25.807509 total size: 54813184 (52 MB)
51 00:58:25.807563 No compression specified
52 00:58:25.808656 progress 0 % (0 MB)
53 00:58:25.822686 progress 5 % (2 MB)
54 00:58:25.836599 progress 10 % (5 MB)
55 00:58:25.850346 progress 15 % (7 MB)
56 00:58:25.864530 progress 20 % (10 MB)
57 00:58:25.878768 progress 25 % (13 MB)
58 00:58:25.892816 progress 30 % (15 MB)
59 00:58:25.906783 progress 35 % (18 MB)
60 00:58:25.920894 progress 40 % (20 MB)
61 00:58:25.934884 progress 45 % (23 MB)
62 00:58:25.949025 progress 50 % (26 MB)
63 00:58:25.963198 progress 55 % (28 MB)
64 00:58:25.977195 progress 60 % (31 MB)
65 00:58:25.991276 progress 65 % (34 MB)
66 00:58:26.005370 progress 70 % (36 MB)
67 00:58:26.019696 progress 75 % (39 MB)
68 00:58:26.033930 progress 80 % (41 MB)
69 00:58:26.048284 progress 85 % (44 MB)
70 00:58:26.062341 progress 90 % (47 MB)
71 00:58:26.076564 progress 95 % (49 MB)
72 00:58:26.090358 progress 100 % (52 MB)
73 00:58:26.090616 52 MB downloaded in 0.28 s (184.65 MB/s)
74 00:58:26.090775 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:58:26.090979 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:58:26.091069 start: 1.3 download-retry (timeout 00:10:00) [common]
78 00:58:26.091174 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 00:58:26.091344 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:58:26.091439 saving as /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/dtb/mt8192-asurada-spherion-r0.dtb
81 00:58:26.091511 total size: 47258 (0 MB)
82 00:58:26.091568 No compression specified
83 00:58:26.092541 progress 69 % (0 MB)
84 00:58:26.092838 progress 100 % (0 MB)
85 00:58:26.092984 0 MB downloaded in 0.00 s (30.64 MB/s)
86 00:58:26.093098 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:58:26.093298 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:58:26.093374 start: 1.4 download-retry (timeout 00:10:00) [common]
90 00:58:26.093449 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 00:58:26.093551 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:58:26.093613 saving as /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/modules/modules.tar
93 00:58:26.093667 total size: 8617404 (8 MB)
94 00:58:26.093721 Using unxz to decompress xz
95 00:58:26.095153 progress 0 % (0 MB)
96 00:58:26.113832 progress 5 % (0 MB)
97 00:58:26.140383 progress 10 % (0 MB)
98 00:58:26.168843 progress 15 % (1 MB)
99 00:58:26.192455 progress 20 % (1 MB)
100 00:58:26.216199 progress 25 % (2 MB)
101 00:58:26.239443 progress 30 % (2 MB)
102 00:58:26.265857 progress 35 % (2 MB)
103 00:58:26.289762 progress 40 % (3 MB)
104 00:58:26.312242 progress 45 % (3 MB)
105 00:58:26.335742 progress 50 % (4 MB)
106 00:58:26.360383 progress 55 % (4 MB)
107 00:58:26.385227 progress 60 % (4 MB)
108 00:58:26.409564 progress 65 % (5 MB)
109 00:58:26.435458 progress 70 % (5 MB)
110 00:58:26.458784 progress 75 % (6 MB)
111 00:58:26.486138 progress 80 % (6 MB)
112 00:58:26.510631 progress 85 % (7 MB)
113 00:58:26.535959 progress 90 % (7 MB)
114 00:58:26.560358 progress 95 % (7 MB)
115 00:58:26.584344 progress 100 % (8 MB)
116 00:58:26.589965 8 MB downloaded in 0.50 s (16.56 MB/s)
117 00:58:26.590180 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:58:26.590504 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:58:26.590621 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:58:26.590737 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:58:26.590845 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:58:26.590957 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:58:26.591179 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0
125 00:58:26.591346 makedir: /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin
126 00:58:26.591478 makedir: /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/tests
127 00:58:26.591608 makedir: /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/results
128 00:58:26.591729 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-add-keys
129 00:58:26.591909 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-add-sources
130 00:58:26.592074 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-background-process-start
131 00:58:26.592239 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-background-process-stop
132 00:58:26.592415 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-common-functions
133 00:58:26.592578 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-echo-ipv4
134 00:58:26.592750 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-install-packages
135 00:58:26.592912 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-installed-packages
136 00:58:26.593075 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-os-build
137 00:58:26.593242 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-probe-channel
138 00:58:26.593408 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-probe-ip
139 00:58:26.593571 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-target-ip
140 00:58:26.593735 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-target-mac
141 00:58:26.593900 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-target-storage
142 00:58:26.594068 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-case
143 00:58:26.594231 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-event
144 00:58:26.594395 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-feedback
145 00:58:26.594561 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-raise
146 00:58:26.594726 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-reference
147 00:58:26.594896 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-runner
148 00:58:26.595062 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-set
149 00:58:26.595222 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-test-shell
150 00:58:26.595385 Updating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-install-packages (oe)
151 00:58:26.595579 Updating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/bin/lava-installed-packages (oe)
152 00:58:26.595739 Creating /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/environment
153 00:58:26.595864 LAVA metadata
154 00:58:26.595962 - LAVA_JOB_ID=14368605
155 00:58:26.596050 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:58:26.596186 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:58:26.596273 skipped lava-vland-overlay
158 00:58:26.596377 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:58:26.596485 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:58:26.596569 skipped lava-multinode-overlay
161 00:58:26.596687 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:58:26.596784 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:58:26.596856 Loading test definitions
164 00:58:26.596942 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:58:26.597009 Using /lava-14368605 at stage 0
166 00:58:26.597314 uuid=14368605_1.5.2.3.1 testdef=None
167 00:58:26.597399 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:58:26.597475 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:58:26.598040 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:58:26.598370 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:58:26.599171 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:58:26.599510 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:58:26.600133 runner path: /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/0/tests/0_cros-ec test_uuid 14368605_1.5.2.3.1
176 00:58:26.600310 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:58:26.600626 Creating lava-test-runner.conf files
179 00:58:26.600733 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368605/lava-overlay-rtxj_5h0/lava-14368605/0 for stage 0
180 00:58:26.600815 - 0_cros-ec
181 00:58:26.600906 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:58:26.600984 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:58:26.608696 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:58:26.608821 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:58:26.608928 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:58:26.609035 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:58:26.609140 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:58:27.793812 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:58:27.793958 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:58:27.794042 extracting modules file /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368605/extract-overlay-ramdisk-i9dnijzp/ramdisk
191 00:58:28.065218 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:58:28.065355 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:58:28.065433 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368605/compress-overlay-_jmtwaz1/overlay-1.5.2.4.tar.gz to ramdisk
194 00:58:28.065495 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368605/compress-overlay-_jmtwaz1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368605/extract-overlay-ramdisk-i9dnijzp/ramdisk
195 00:58:28.071678 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:58:28.071779 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:58:28.071860 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:58:28.071938 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:58:28.072005 Building ramdisk /var/lib/lava/dispatcher/tmp/14368605/extract-overlay-ramdisk-i9dnijzp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368605/extract-overlay-ramdisk-i9dnijzp/ramdisk
200 00:58:28.933189 >> 335941 blocks
201 00:58:34.213969 rename /var/lib/lava/dispatcher/tmp/14368605/extract-overlay-ramdisk-i9dnijzp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/ramdisk/ramdisk.cpio.gz
202 00:58:34.214168 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 00:58:34.214284 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 00:58:34.214392 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 00:58:34.214504 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/kernel/Image']
206 00:58:47.627253 Returned 0 in 13 seconds
207 00:58:47.727797 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/kernel/image.itb
208 00:58:48.574042 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:58:48.574192 output: Created: Sun Jun 16 01:58:48 2024
210 00:58:48.574285 output: Image 0 (kernel-1)
211 00:58:48.574369 output: Description:
212 00:58:48.574455 output: Created: Sun Jun 16 01:58:48 2024
213 00:58:48.574540 output: Type: Kernel Image
214 00:58:48.574618 output: Compression: lzma compressed
215 00:58:48.574711 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
216 00:58:48.574792 output: Architecture: AArch64
217 00:58:48.574875 output: OS: Linux
218 00:58:48.574959 output: Load Address: 0x00000000
219 00:58:48.575041 output: Entry Point: 0x00000000
220 00:58:48.575121 output: Hash algo: crc32
221 00:58:48.575206 output: Hash value: f6f06660
222 00:58:48.575289 output: Image 1 (fdt-1)
223 00:58:48.575368 output: Description: mt8192-asurada-spherion-r0
224 00:58:48.575454 output: Created: Sun Jun 16 01:58:48 2024
225 00:58:48.575533 output: Type: Flat Device Tree
226 00:58:48.575613 output: Compression: uncompressed
227 00:58:48.575696 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:58:48.575778 output: Architecture: AArch64
229 00:58:48.575856 output: Hash algo: crc32
230 00:58:48.575933 output: Hash value: 0f8e4d2e
231 00:58:48.576010 output: Image 2 (ramdisk-1)
232 00:58:48.576085 output: Description: unavailable
233 00:58:48.576160 output: Created: Sun Jun 16 01:58:48 2024
234 00:58:48.576239 output: Type: RAMDisk Image
235 00:58:48.576315 output: Compression: uncompressed
236 00:58:48.576390 output: Data Size: 52137544 Bytes = 50915.57 KiB = 49.72 MiB
237 00:58:48.576468 output: Architecture: AArch64
238 00:58:48.576553 output: OS: Linux
239 00:58:48.576649 output: Load Address: unavailable
240 00:58:48.576722 output: Entry Point: unavailable
241 00:58:48.576773 output: Hash algo: crc32
242 00:58:48.576849 output: Hash value: 9e831de1
243 00:58:48.576923 output: Default Configuration: 'conf-1'
244 00:58:48.576997 output: Configuration 0 (conf-1)
245 00:58:48.577055 output: Description: mt8192-asurada-spherion-r0
246 00:58:48.577108 output: Kernel: kernel-1
247 00:58:48.577156 output: Init Ramdisk: ramdisk-1
248 00:58:48.577204 output: FDT: fdt-1
249 00:58:48.577252 output: Loadables: kernel-1
250 00:58:48.577305 output:
251 00:58:48.577452 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:58:48.577567 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:58:48.577654 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 00:58:48.577738 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 00:58:48.577811 No LXC device requested
256 00:58:48.577916 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:58:48.578023 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 00:58:48.578118 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:58:48.578209 Checking files for TFTP limit of 4294967296 bytes.
260 00:58:48.578786 end: 1 tftp-deploy (duration 00:00:23) [common]
261 00:58:48.578906 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:58:48.579018 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:58:48.579163 substitutions:
264 00:58:48.579254 - {DTB}: 14368605/tftp-deploy-djasquo9/dtb/mt8192-asurada-spherion-r0.dtb
265 00:58:48.579339 - {INITRD}: 14368605/tftp-deploy-djasquo9/ramdisk/ramdisk.cpio.gz
266 00:58:48.579419 - {KERNEL}: 14368605/tftp-deploy-djasquo9/kernel/Image
267 00:58:48.579501 - {LAVA_MAC}: None
268 00:58:48.579580 - {PRESEED_CONFIG}: None
269 00:58:48.579658 - {PRESEED_LOCAL}: None
270 00:58:48.579739 - {RAMDISK}: 14368605/tftp-deploy-djasquo9/ramdisk/ramdisk.cpio.gz
271 00:58:48.579825 - {ROOT_PART}: None
272 00:58:48.579903 - {ROOT}: None
273 00:58:48.579979 - {SERVER_IP}: 192.168.201.1
274 00:58:48.580058 - {TEE}: None
275 00:58:48.580138 Parsed boot commands:
276 00:58:48.580213 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:58:48.580399 Parsed boot commands: tftpboot 192.168.201.1 14368605/tftp-deploy-djasquo9/kernel/image.itb 14368605/tftp-deploy-djasquo9/kernel/cmdline
278 00:58:48.580504 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:58:48.580614 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:58:48.580763 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:58:48.580870 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:58:48.580956 Not connected, no need to disconnect.
283 00:58:48.581052 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:58:48.581139 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:58:48.581210 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 00:58:48.584566 Setting prompt string to ['lava-test: # ']
287 00:58:48.585136 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:58:48.585259 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:58:48.585455 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:58:48.585643 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:58:48.585933 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
292 00:59:02.395098 Returned 0 in 13 seconds
293 00:59:02.495662 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:59:02.495935 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:59:02.496030 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:59:02.496139 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:59:02.496240 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:59:02.496344 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:59:02.496892 [Enter `^Ec?' for help]
301 00:59:02.496989
302 00:59:02.497083
303 00:59:02.497168 F0: 102B 0000
304 00:59:02.497250
305 00:59:02.497329 F3: 1001 0000 [0200]
306 00:59:02.497409
307 00:59:02.497490 F3: 1001 0000
308 00:59:02.497560
309 00:59:02.497632 F7: 102D 0000
310 00:59:02.497710
311 00:59:02.497792 F1: 0000 0000
312 00:59:02.497876
313 00:59:02.497956 V0: 0000 0000 [0001]
314 00:59:02.498038
315 00:59:02.498118 00: 0007 8000
316 00:59:02.498198
317 00:59:02.498274 01: 0000 0000
318 00:59:02.498354
319 00:59:02.498431 BP: 0C00 0209 [0000]
320 00:59:02.498510
321 00:59:02.498585 G0: 1182 0000
322 00:59:02.498663
323 00:59:02.498741 EC: 0000 0021 [4000]
324 00:59:02.498817
325 00:59:02.498893 S7: 0000 0000 [0000]
326 00:59:02.498968
327 00:59:02.499044 CC: 0000 0000 [0001]
328 00:59:02.499119
329 00:59:02.499195 T0: 0000 0040 [010F]
330 00:59:02.499284
331 00:59:02.499368 Jump to BL
332 00:59:02.499448
333 00:59:02.499528
334 00:59:02.499607
335 00:59:02.499691 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:59:02.499773 ARM64: Exception handlers installed.
337 00:59:02.499855 ARM64: Testing exception
338 00:59:02.499932 ARM64: Done test exception
339 00:59:02.500019 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:59:02.500102 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:59:02.500192 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:59:02.500273 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:59:02.500351 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:59:02.500404 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:59:02.500455 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:59:02.500505 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:59:02.500554 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:59:02.500612 WDT: Last reset was cold boot
349 00:59:02.500734 SPI1(PAD0) initialized at 2873684 Hz
350 00:59:02.500814 SPI5(PAD0) initialized at 992727 Hz
351 00:59:02.500894 VBOOT: Loading verstage.
352 00:59:02.500971 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:59:02.501049 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:59:02.501133 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:59:02.501226 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:59:02.501278 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:59:02.501328 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:59:02.501399 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 00:59:02.501477
360 00:59:02.501547
361 00:59:02.501597 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:59:02.501653 ARM64: Exception handlers installed.
363 00:59:02.501730 ARM64: Testing exception
364 00:59:02.501806 ARM64: Done test exception
365 00:59:02.501883 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:59:02.501968 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:59:02.502048 Probing TPM: . done!
368 00:59:02.502125 TPM ready after 0 ms
369 00:59:02.502196 Connected to device vid:did:rid of 1ae0:0028:00
370 00:59:02.502255 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 00:59:02.502333 Initialized TPM device CR50 revision 0
372 00:59:02.502410 tlcl_send_startup: Startup return code is 0
373 00:59:02.502478 TPM: setup succeeded
374 00:59:02.502528 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:59:02.502578 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:59:02.502627 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:59:02.502677 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:59:02.502730 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:59:02.502782 in-header: 03 07 00 00 08 00 00 00
380 00:59:02.502832 in-data: aa e4 47 04 13 02 00 00
381 00:59:02.502881 Chrome EC: UHEPI supported
382 00:59:02.502929 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:59:02.503000 in-header: 03 a9 00 00 08 00 00 00
384 00:59:02.503057 in-data: 84 60 60 08 00 00 00 00
385 00:59:02.503133 Phase 1
386 00:59:02.503216 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:59:02.503299 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:59:02.503381 VB2:vb2_check_recovery() Recovery was requested manually
389 00:59:02.503440 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:59:02.503490 Recovery requested (1009000e)
391 00:59:02.503555 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:59:02.503632 tlcl_extend: response is 0
393 00:59:02.503710 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:59:02.503789 tlcl_extend: response is 0
395 00:59:02.503869 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:59:02.503947 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:59:02.504024 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:59:02.504103
399 00:59:02.504178
400 00:59:02.504257 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:59:02.504337 ARM64: Exception handlers installed.
402 00:59:02.504416 ARM64: Testing exception
403 00:59:02.504492 ARM64: Done test exception
404 00:59:02.504569 pmic_efuse_setting: Set efuses in 11 msecs
405 00:59:02.504690 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:59:02.504771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:59:02.504848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:59:02.505125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:59:02.505240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:59:02.505350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:59:02.505460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:59:02.505571 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:59:02.505682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:59:02.505791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:59:02.505901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:59:02.506012 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:59:02.506121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:59:02.506231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:59:02.506339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:59:02.506419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:59:02.506502 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:59:02.506581 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:59:02.506659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:59:02.506739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:59:02.506816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:59:02.506893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:59:02.506974 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:59:02.507053 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:59:02.507131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:59:02.507211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:59:02.507289 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:59:02.507366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:59:02.507446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:59:02.507525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:59:02.507603 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:59:02.507682 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:59:02.507760 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:59:02.507838 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:59:02.507916 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:59:02.507995 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:59:02.508073 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:59:02.508150 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:59:02.508230 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:59:02.508307 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:59:02.508384 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:59:02.508463 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:59:02.508541 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:59:02.508617 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:59:02.508726 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:59:02.508780 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:59:02.508830 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:59:02.508879 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:59:02.508932 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:59:02.508984 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:59:02.509033 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:59:02.509088 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:59:02.509184 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:59:02.509330 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:59:02.509398 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:59:02.509453 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:59:02.509505 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:59:02.509556 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:59:02.509605 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:59:02.509655 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:59:02.509709 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
466 00:59:02.509759 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:59:02.509809 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 00:59:02.509858 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:59:02.509910 [RTC]rtc_get_frequency_meter,154: input=15, output=794
470 00:59:02.509965 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 00:59:02.510017 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 00:59:02.510067 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
473 00:59:02.510117 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 00:59:02.510167 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
475 00:59:02.510220 ADC[4]: Raw value=894821 ID=7
476 00:59:02.510270 ADC[3]: Raw value=212700 ID=1
477 00:59:02.510318 RAM Code: 0x71
478 00:59:02.510367 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 00:59:02.510417 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 00:59:02.510660 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 00:59:02.510781 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 00:59:02.510901 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 00:59:02.511012 in-header: 03 07 00 00 08 00 00 00
484 00:59:02.511123 in-data: aa e4 47 04 13 02 00 00
485 00:59:02.511233 Chrome EC: UHEPI supported
486 00:59:02.511316 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 00:59:02.511369 in-header: 03 a9 00 00 08 00 00 00
488 00:59:02.511419 in-data: 84 60 60 08 00 00 00 00
489 00:59:02.511469 MRC: failed to locate region type 0.
490 00:59:02.511518 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 00:59:02.511573 DRAM-K: Running full calibration
492 00:59:02.511625 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 00:59:02.511675 header.status = 0x0
494 00:59:02.511724 header.version = 0x6 (expected: 0x6)
495 00:59:02.511773 header.size = 0xd00 (expected: 0xd00)
496 00:59:02.511826 header.flags = 0x0
497 00:59:02.511875 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 00:59:02.511925 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
499 00:59:02.511974 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 00:59:02.512023 dram_init: ddr_geometry: 2
501 00:59:02.512076 [EMI] MDL number = 2
502 00:59:02.512128 [EMI] Get MDL freq = 0
503 00:59:02.512177 dram_init: ddr_type: 0
504 00:59:02.512226 is_discrete_lpddr4: 1
505 00:59:02.512275 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 00:59:02.512349
507 00:59:02.512425
508 00:59:02.512501 [Bian_co] ETT version 0.0.0.1
509 00:59:02.512609 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 00:59:02.512717
511 00:59:02.512800 dramc_set_vcore_voltage set vcore to 650000
512 00:59:02.512881 Read voltage for 800, 4
513 00:59:02.512957 Vio18 = 0
514 00:59:02.513035 Vcore = 650000
515 00:59:02.513114 Vdram = 0
516 00:59:02.513190 Vddq = 0
517 00:59:02.513268 Vmddr = 0
518 00:59:02.513344 dram_init: config_dvfs: 1
519 00:59:02.513422 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 00:59:02.513501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 00:59:02.513581 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 00:59:02.513658 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 00:59:02.513739 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 00:59:02.513816 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 00:59:02.513893 MEM_TYPE=3, freq_sel=18
526 00:59:02.513971 sv_algorithm_assistance_LP4_1600
527 00:59:02.514049 ============ PULL DRAM RESETB DOWN ============
528 00:59:02.514131 ========== PULL DRAM RESETB DOWN end =========
529 00:59:02.514209 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 00:59:02.514287 ===================================
531 00:59:02.514364 LPDDR4 DRAM CONFIGURATION
532 00:59:02.514440 ===================================
533 00:59:02.514519 EX_ROW_EN[0] = 0x0
534 00:59:02.514595 EX_ROW_EN[1] = 0x0
535 00:59:02.514670 LP4Y_EN = 0x0
536 00:59:02.514748 WORK_FSP = 0x0
537 00:59:02.514825 WL = 0x2
538 00:59:02.514901 RL = 0x2
539 00:59:02.514979 BL = 0x2
540 00:59:02.515055 RPST = 0x0
541 00:59:02.515131 RD_PRE = 0x0
542 00:59:02.515208 WR_PRE = 0x1
543 00:59:02.515284 WR_PST = 0x0
544 00:59:02.515360 DBI_WR = 0x0
545 00:59:02.515435 DBI_RD = 0x0
546 00:59:02.515513 OTF = 0x1
547 00:59:02.515590 ===================================
548 00:59:02.515667 ===================================
549 00:59:02.515750 ANA top config
550 00:59:02.515838 ===================================
551 00:59:02.515916 DLL_ASYNC_EN = 0
552 00:59:02.515995 ALL_SLAVE_EN = 1
553 00:59:02.516072 NEW_RANK_MODE = 1
554 00:59:02.516150 DLL_IDLE_MODE = 1
555 00:59:02.516226 LP45_APHY_COMB_EN = 1
556 00:59:02.516304 TX_ODT_DIS = 1
557 00:59:02.516381 NEW_8X_MODE = 1
558 00:59:02.516458 ===================================
559 00:59:02.516537 ===================================
560 00:59:02.516614 data_rate = 1600
561 00:59:02.516737 CKR = 1
562 00:59:02.516817 DQ_P2S_RATIO = 8
563 00:59:02.516894 ===================================
564 00:59:02.516971 CA_P2S_RATIO = 8
565 00:59:02.517047 DQ_CA_OPEN = 0
566 00:59:02.517126 DQ_SEMI_OPEN = 0
567 00:59:02.517202 CA_SEMI_OPEN = 0
568 00:59:02.517278 CA_FULL_RATE = 0
569 00:59:02.517355 DQ_CKDIV4_EN = 1
570 00:59:02.517418 CA_CKDIV4_EN = 1
571 00:59:02.517468 CA_PREDIV_EN = 0
572 00:59:02.517517 PH8_DLY = 0
573 00:59:02.517566 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 00:59:02.517614 DQ_AAMCK_DIV = 4
575 00:59:02.517663 CA_AAMCK_DIV = 4
576 00:59:02.517711 CA_ADMCK_DIV = 4
577 00:59:02.517763 DQ_TRACK_CA_EN = 0
578 00:59:02.517811 CA_PICK = 800
579 00:59:02.517859 CA_MCKIO = 800
580 00:59:02.517908 MCKIO_SEMI = 0
581 00:59:02.517957 PLL_FREQ = 3068
582 00:59:02.518006 DQ_UI_PI_RATIO = 32
583 00:59:02.518058 CA_UI_PI_RATIO = 0
584 00:59:02.518107 ===================================
585 00:59:02.518156 ===================================
586 00:59:02.518205 memory_type:LPDDR4
587 00:59:02.518253 GP_NUM : 10
588 00:59:02.518305 SRAM_EN : 1
589 00:59:02.518355 MD32_EN : 0
590 00:59:02.518404 ===================================
591 00:59:02.518453 [ANA_INIT] >>>>>>>>>>>>>>
592 00:59:02.518502 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 00:59:02.518557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 00:59:02.518611 ===================================
595 00:59:02.518661 data_rate = 1600,PCW = 0X7600
596 00:59:02.518710 ===================================
597 00:59:02.518758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 00:59:02.518806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 00:59:02.518855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 00:59:02.519147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 00:59:02.519276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 00:59:02.519388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 00:59:02.519499 [ANA_INIT] flow start
604 00:59:02.519609 [ANA_INIT] PLL >>>>>>>>
605 00:59:02.519718 [ANA_INIT] PLL <<<<<<<<
606 00:59:02.519802 [ANA_INIT] MIDPI >>>>>>>>
607 00:59:02.519855 [ANA_INIT] MIDPI <<<<<<<<
608 00:59:02.519904 [ANA_INIT] DLL >>>>>>>>
609 00:59:02.519953 [ANA_INIT] flow end
610 00:59:02.520004 ============ LP4 DIFF to SE enter ============
611 00:59:02.520057 ============ LP4 DIFF to SE exit ============
612 00:59:02.520106 [ANA_INIT] <<<<<<<<<<<<<
613 00:59:02.520155 [Flow] Enable top DCM control >>>>>
614 00:59:02.520204 [Flow] Enable top DCM control <<<<<
615 00:59:02.520252 Enable DLL master slave shuffle
616 00:59:02.520319 ==============================================================
617 00:59:02.520398 Gating Mode config
618 00:59:02.520476 ==============================================================
619 00:59:02.520554 Config description:
620 00:59:02.520633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 00:59:02.520727 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 00:59:02.520778 SELPH_MODE 0: By rank 1: By Phase
623 00:59:02.520829 ==============================================================
624 00:59:02.520881 GAT_TRACK_EN = 1
625 00:59:02.520933 RX_GATING_MODE = 2
626 00:59:02.520982 RX_GATING_TRACK_MODE = 2
627 00:59:02.521031 SELPH_MODE = 1
628 00:59:02.521079 PICG_EARLY_EN = 1
629 00:59:02.521131 VALID_LAT_VALUE = 1
630 00:59:02.521181 ==============================================================
631 00:59:02.521230 Enter into Gating configuration >>>>
632 00:59:02.521279 Exit from Gating configuration <<<<
633 00:59:02.521349 Enter into DVFS_PRE_config >>>>>
634 00:59:02.521403 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 00:59:02.521458 Exit from DVFS_PRE_config <<<<<
636 00:59:02.521509 Enter into PICG configuration >>>>
637 00:59:02.521558 Exit from PICG configuration <<<<
638 00:59:02.521607 [RX_INPUT] configuration >>>>>
639 00:59:02.521656 [RX_INPUT] configuration <<<<<
640 00:59:02.521709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 00:59:02.521758 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 00:59:02.521808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 00:59:02.521857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 00:59:02.521904 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 00:59:02.521955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 00:59:02.522005 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 00:59:02.522056 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 00:59:02.522105 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 00:59:02.522154 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 00:59:02.522205 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 00:59:02.522257 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 00:59:02.522306 ===================================
653 00:59:02.522355 LPDDR4 DRAM CONFIGURATION
654 00:59:02.522404 ===================================
655 00:59:02.522452 EX_ROW_EN[0] = 0x0
656 00:59:02.522524 EX_ROW_EN[1] = 0x0
657 00:59:02.522605 LP4Y_EN = 0x0
658 00:59:02.522680 WORK_FSP = 0x0
659 00:59:02.522759 WL = 0x2
660 00:59:02.522835 RL = 0x2
661 00:59:02.522910 BL = 0x2
662 00:59:02.522986 RPST = 0x0
663 00:59:02.523063 RD_PRE = 0x0
664 00:59:02.523141 WR_PRE = 0x1
665 00:59:02.523219 WR_PST = 0x0
666 00:59:02.523295 DBI_WR = 0x0
667 00:59:02.523373 DBI_RD = 0x0
668 00:59:02.523450 OTF = 0x1
669 00:59:02.523527 ===================================
670 00:59:02.523606 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 00:59:02.523686 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 00:59:02.523765 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 00:59:02.523844 ===================================
674 00:59:02.523922 LPDDR4 DRAM CONFIGURATION
675 00:59:02.524000 ===================================
676 00:59:02.524077 EX_ROW_EN[0] = 0x10
677 00:59:02.524153 EX_ROW_EN[1] = 0x0
678 00:59:02.524231 LP4Y_EN = 0x0
679 00:59:02.524307 WORK_FSP = 0x0
680 00:59:02.524383 WL = 0x2
681 00:59:02.524459 RL = 0x2
682 00:59:02.524537 BL = 0x2
683 00:59:02.524613 RPST = 0x0
684 00:59:02.524728 RD_PRE = 0x0
685 00:59:02.524806 WR_PRE = 0x1
686 00:59:02.524883 WR_PST = 0x0
687 00:59:02.524959 DBI_WR = 0x0
688 00:59:02.525035 DBI_RD = 0x0
689 00:59:02.525113 OTF = 0x1
690 00:59:02.525190 ===================================
691 00:59:02.525268 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 00:59:02.525345 nWR fixed to 40
693 00:59:02.525424 [ModeRegInit_LP4] CH0 RK0
694 00:59:02.525501 [ModeRegInit_LP4] CH0 RK1
695 00:59:02.525577 [ModeRegInit_LP4] CH1 RK0
696 00:59:02.525664 [ModeRegInit_LP4] CH1 RK1
697 00:59:02.525743 match AC timing 13
698 00:59:02.525820 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 00:59:02.525930 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 00:59:02.526016 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 00:59:02.526096 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 00:59:02.526176 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 00:59:02.526253 [EMI DOE] emi_dcm 0
704 00:59:02.526330 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 00:59:02.526406 ==
706 00:59:02.526473 Dram Type= 6, Freq= 0, CH_0, rank 0
707 00:59:02.526524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 00:59:02.526574 ==
709 00:59:02.526822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 00:59:02.526905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 00:59:02.526984 [CA 0] Center 38 (7~69) winsize 63
712 00:59:02.527063 [CA 1] Center 38 (7~69) winsize 63
713 00:59:02.527141 [CA 2] Center 35 (5~66) winsize 62
714 00:59:02.527215 [CA 3] Center 35 (5~66) winsize 62
715 00:59:02.527275 [CA 4] Center 34 (4~65) winsize 62
716 00:59:02.527329 [CA 5] Center 34 (3~65) winsize 63
717 00:59:02.527378
718 00:59:02.527427 [CmdBusTrainingLP45] Vref(ca) range 1: 34
719 00:59:02.527477
720 00:59:02.527525 [CATrainingPosCal] consider 1 rank data
721 00:59:02.527577 u2DelayCellTimex100 = 270/100 ps
722 00:59:02.527626 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 00:59:02.527676 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
724 00:59:02.527725 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 00:59:02.527773 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 00:59:02.527825 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 00:59:02.527874 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
728 00:59:02.527923
729 00:59:02.527971 CA PerBit enable=1, Macro0, CA PI delay=34
730 00:59:02.528020
731 00:59:02.528068 [CBTSetCACLKResult] CA Dly = 34
732 00:59:02.528121 CS Dly: 6 (0~37)
733 00:59:02.528169 ==
734 00:59:02.528218 Dram Type= 6, Freq= 0, CH_0, rank 1
735 00:59:02.528267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 00:59:02.528315 ==
737 00:59:02.528368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 00:59:02.528418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 00:59:02.528467 [CA 0] Center 38 (7~69) winsize 63
740 00:59:02.528516 [CA 1] Center 37 (7~68) winsize 62
741 00:59:02.528564 [CA 2] Center 35 (5~66) winsize 62
742 00:59:02.528613 [CA 3] Center 35 (5~66) winsize 62
743 00:59:02.528698 [CA 4] Center 34 (4~65) winsize 62
744 00:59:02.528750 [CA 5] Center 34 (4~65) winsize 62
745 00:59:02.528800
746 00:59:02.528850 [CmdBusTrainingLP45] Vref(ca) range 1: 30
747 00:59:02.528898
748 00:59:02.528952 [CATrainingPosCal] consider 2 rank data
749 00:59:02.529002 u2DelayCellTimex100 = 270/100 ps
750 00:59:02.529051 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 00:59:02.529101 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
752 00:59:02.529149 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 00:59:02.529198 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 00:59:02.529250 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 00:59:02.529301 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 00:59:02.529349
757 00:59:02.529398 CA PerBit enable=1, Macro0, CA PI delay=34
758 00:59:02.529447
759 00:59:02.529496 [CBTSetCACLKResult] CA Dly = 34
760 00:59:02.529545 CS Dly: 6 (0~37)
761 00:59:02.529610
762 00:59:02.529687 ----->DramcWriteLeveling(PI) begin...
763 00:59:02.529767 ==
764 00:59:02.529844 Dram Type= 6, Freq= 0, CH_0, rank 0
765 00:59:02.529924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 00:59:02.530001 ==
767 00:59:02.530077 Write leveling (Byte 0): 33 => 33
768 00:59:02.530154 Write leveling (Byte 1): 31 => 31
769 00:59:02.530230 DramcWriteLeveling(PI) end<-----
770 00:59:02.530281
771 00:59:02.530333 ==
772 00:59:02.530419 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:59:02.530497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:59:02.530577 ==
775 00:59:02.530654 [Gating] SW mode calibration
776 00:59:02.530732 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 00:59:02.530811 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 00:59:02.530890 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 00:59:02.530968 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 00:59:02.531045 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
781 00:59:02.531122 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 00:59:02.531200 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 00:59:02.531282 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 00:59:02.531360 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 00:59:02.531437 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 00:59:02.531517 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 00:59:02.531594 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:59:02.531671 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:59:02.531747 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:59:02.531827 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:59:02.531904 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:59:02.531993 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:59:02.532074 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:59:02.532151 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:59:02.532229 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:59:02.532306 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
797 00:59:02.532385 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 00:59:02.532462 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:59:02.532540 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:59:02.532617 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:59:02.532727 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:59:02.532778 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:59:02.532828 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:59:02.532877 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
805 00:59:02.532925 0 9 12 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
806 00:59:02.532973 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 00:59:02.533026 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 00:59:02.533076 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 00:59:02.533125 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 00:59:02.533174 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 00:59:02.533223 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 00:59:02.533291 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
813 00:59:02.533372 0 10 12 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
814 00:59:02.533439 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 00:59:02.533692 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:59:02.533809 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:59:02.533921 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:59:02.534032 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 00:59:02.534142 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 00:59:02.534251 0 11 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
821 00:59:02.534362 0 11 12 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
822 00:59:02.534472 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 00:59:02.534581 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 00:59:02.534691 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 00:59:02.534801 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 00:59:02.534896 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 00:59:02.534950 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
828 00:59:02.535001 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
829 00:59:02.535056 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
830 00:59:02.535107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 00:59:02.535157 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 00:59:02.535206 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 00:59:02.535299 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 00:59:02.535400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 00:59:02.535451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 00:59:02.535500 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:59:02.535550 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:59:02.535604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:59:02.535653 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:59:02.535702 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:59:02.535752 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:59:02.535802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:59:02.535855 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:59:02.535904 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
845 00:59:02.535953 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 00:59:02.536002 Total UI for P1: 0, mck2ui 16
847 00:59:02.536052 best dqsien dly found for B0: ( 0, 14, 8)
848 00:59:02.536104 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 00:59:02.536155 Total UI for P1: 0, mck2ui 16
850 00:59:02.536204 best dqsien dly found for B1: ( 0, 14, 10)
851 00:59:02.536253 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 00:59:02.536302 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 00:59:02.536351
854 00:59:02.536405 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 00:59:02.536455 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 00:59:02.536505 [Gating] SW calibration Done
857 00:59:02.536554 ==
858 00:59:02.536603 Dram Type= 6, Freq= 0, CH_0, rank 0
859 00:59:02.536677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 00:59:02.536743 ==
861 00:59:02.536791 RX Vref Scan: 0
862 00:59:02.536840
863 00:59:02.536889 RX Vref 0 -> 0, step: 1
864 00:59:02.536938
865 00:59:02.536990 RX Delay -130 -> 252, step: 16
866 00:59:02.537039 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 00:59:02.537089 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
868 00:59:02.537138 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 00:59:02.537187 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 00:59:02.537236 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
871 00:59:02.537289 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 00:59:02.537338 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 00:59:02.537390 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 00:59:02.537439 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 00:59:02.537488 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 00:59:02.537537 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 00:59:02.537590 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 00:59:02.537640 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 00:59:02.537689 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 00:59:02.537737 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 00:59:02.537786 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 00:59:02.537835 ==
883 00:59:02.537913 Dram Type= 6, Freq= 0, CH_0, rank 0
884 00:59:02.537991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 00:59:02.538068 ==
886 00:59:02.538146 DQS Delay:
887 00:59:02.538222 DQS0 = 0, DQS1 = 0
888 00:59:02.538298 DQM Delay:
889 00:59:02.538374 DQM0 = 79, DQM1 = 69
890 00:59:02.538452 DQ Delay:
891 00:59:02.538528 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
892 00:59:02.538613 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
893 00:59:02.538674 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 00:59:02.538728 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 00:59:02.538778
896 00:59:02.538827
897 00:59:02.538877 ==
898 00:59:02.538925 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:59:02.538974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 00:59:02.539026 ==
901 00:59:02.539076
902 00:59:02.539123
903 00:59:02.539172 TX Vref Scan disable
904 00:59:02.539220 == TX Byte 0 ==
905 00:59:02.539269 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
906 00:59:02.539322 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
907 00:59:02.539372 == TX Byte 1 ==
908 00:59:02.539421 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 00:59:02.539470 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 00:59:02.539518 ==
911 00:59:02.539567 Dram Type= 6, Freq= 0, CH_0, rank 0
912 00:59:02.539621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 00:59:02.539670 ==
914 00:59:02.539718 TX Vref=22, minBit 14, minWin=26, winSum=434
915 00:59:02.539768 TX Vref=24, minBit 11, minWin=26, winSum=436
916 00:59:02.539818 TX Vref=26, minBit 11, minWin=26, winSum=440
917 00:59:02.539867 TX Vref=28, minBit 9, minWin=27, winSum=443
918 00:59:02.539922 TX Vref=30, minBit 9, minWin=27, winSum=442
919 00:59:02.539971 TX Vref=32, minBit 9, minWin=26, winSum=438
920 00:59:02.540021 [TxChooseVref] Worse bit 9, Min win 27, Win sum 443, Final Vref 28
921 00:59:02.540070
922 00:59:02.540118 Final TX Range 1 Vref 28
923 00:59:02.540167
924 00:59:02.540220 ==
925 00:59:02.540270 Dram Type= 6, Freq= 0, CH_0, rank 0
926 00:59:02.540517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 00:59:02.540598 ==
928 00:59:02.540709
929 00:59:02.540762
930 00:59:02.540813 TX Vref Scan disable
931 00:59:02.540863 == TX Byte 0 ==
932 00:59:02.540913 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
933 00:59:02.540964 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
934 00:59:02.541013 == TX Byte 1 ==
935 00:59:02.541067 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 00:59:02.541116 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 00:59:02.541165
938 00:59:02.541214 [DATLAT]
939 00:59:02.541262 Freq=800, CH0 RK0
940 00:59:02.541312
941 00:59:02.541365 DATLAT Default: 0xa
942 00:59:02.541414 0, 0xFFFF, sum = 0
943 00:59:02.541464 1, 0xFFFF, sum = 0
944 00:59:02.541514 2, 0xFFFF, sum = 0
945 00:59:02.541563 3, 0xFFFF, sum = 0
946 00:59:02.541620 4, 0xFFFF, sum = 0
947 00:59:02.541670 5, 0xFFFF, sum = 0
948 00:59:02.541720 6, 0xFFFF, sum = 0
949 00:59:02.541770 7, 0xFFFF, sum = 0
950 00:59:02.541820 8, 0xFFFF, sum = 0
951 00:59:02.541875 9, 0x0, sum = 1
952 00:59:02.541926 10, 0x0, sum = 2
953 00:59:02.541976 11, 0x0, sum = 3
954 00:59:02.542025 12, 0x0, sum = 4
955 00:59:02.542105 best_step = 10
956 00:59:02.542160
957 00:59:02.542210 ==
958 00:59:02.542258 Dram Type= 6, Freq= 0, CH_0, rank 0
959 00:59:02.542308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 00:59:02.542357 ==
961 00:59:02.542406 RX Vref Scan: 1
962 00:59:02.542457
963 00:59:02.542506 Set Vref Range= 32 -> 127
964 00:59:02.542557
965 00:59:02.542606 RX Vref 32 -> 127, step: 1
966 00:59:02.542655
967 00:59:02.542703 RX Delay -111 -> 252, step: 8
968 00:59:02.542756
969 00:59:02.542806 Set Vref, RX VrefLevel [Byte0]: 32
970 00:59:02.542855 [Byte1]: 32
971 00:59:02.542904
972 00:59:02.542952 Set Vref, RX VrefLevel [Byte0]: 33
973 00:59:02.543001 [Byte1]: 33
974 00:59:02.543053
975 00:59:02.543102 Set Vref, RX VrefLevel [Byte0]: 34
976 00:59:02.543152 [Byte1]: 34
977 00:59:02.543201
978 00:59:02.543249 Set Vref, RX VrefLevel [Byte0]: 35
979 00:59:02.543298 [Byte1]: 35
980 00:59:02.543352
981 00:59:02.543402 Set Vref, RX VrefLevel [Byte0]: 36
982 00:59:02.543450 [Byte1]: 36
983 00:59:02.543498
984 00:59:02.543547 Set Vref, RX VrefLevel [Byte0]: 37
985 00:59:02.543596 [Byte1]: 37
986 00:59:02.543649
987 00:59:02.543698 Set Vref, RX VrefLevel [Byte0]: 38
988 00:59:02.543747 [Byte1]: 38
989 00:59:02.543795
990 00:59:02.543844 Set Vref, RX VrefLevel [Byte0]: 39
991 00:59:02.543892 [Byte1]: 39
992 00:59:02.543945
993 00:59:02.543993 Set Vref, RX VrefLevel [Byte0]: 40
994 00:59:02.544042 [Byte1]: 40
995 00:59:02.544091
996 00:59:02.544139 Set Vref, RX VrefLevel [Byte0]: 41
997 00:59:02.544188 [Byte1]: 41
998 00:59:02.544241
999 00:59:02.544289 Set Vref, RX VrefLevel [Byte0]: 42
1000 00:59:02.544338 [Byte1]: 42
1001 00:59:02.544386
1002 00:59:02.544435 Set Vref, RX VrefLevel [Byte0]: 43
1003 00:59:02.544483 [Byte1]: 43
1004 00:59:02.544549
1005 00:59:02.544626 Set Vref, RX VrefLevel [Byte0]: 44
1006 00:59:02.544721 [Byte1]: 44
1007 00:59:02.544771
1008 00:59:02.544825 Set Vref, RX VrefLevel [Byte0]: 45
1009 00:59:02.544876 [Byte1]: 45
1010 00:59:02.544926
1011 00:59:02.544979 Set Vref, RX VrefLevel [Byte0]: 46
1012 00:59:02.545051 [Byte1]: 46
1013 00:59:02.545108
1014 00:59:02.545159 Set Vref, RX VrefLevel [Byte0]: 47
1015 00:59:02.545209 [Byte1]: 47
1016 00:59:02.545259
1017 00:59:02.545308 Set Vref, RX VrefLevel [Byte0]: 48
1018 00:59:02.545357 [Byte1]: 48
1019 00:59:02.545412
1020 00:59:02.545460 Set Vref, RX VrefLevel [Byte0]: 49
1021 00:59:02.545509 [Byte1]: 49
1022 00:59:02.545560
1023 00:59:02.545610 Set Vref, RX VrefLevel [Byte0]: 50
1024 00:59:02.545661 [Byte1]: 50
1025 00:59:02.545713
1026 00:59:02.545762 Set Vref, RX VrefLevel [Byte0]: 51
1027 00:59:02.545814 [Byte1]: 51
1028 00:59:02.545864
1029 00:59:02.545912 Set Vref, RX VrefLevel [Byte0]: 52
1030 00:59:02.545961 [Byte1]: 52
1031 00:59:02.546013
1032 00:59:02.546062 Set Vref, RX VrefLevel [Byte0]: 53
1033 00:59:02.546111 [Byte1]: 53
1034 00:59:02.546160
1035 00:59:02.546208 Set Vref, RX VrefLevel [Byte0]: 54
1036 00:59:02.546257 [Byte1]: 54
1037 00:59:02.546310
1038 00:59:02.546359 Set Vref, RX VrefLevel [Byte0]: 55
1039 00:59:02.546408 [Byte1]: 55
1040 00:59:02.546457
1041 00:59:02.546505 Set Vref, RX VrefLevel [Byte0]: 56
1042 00:59:02.546553 [Byte1]: 56
1043 00:59:02.546606
1044 00:59:02.546654 Set Vref, RX VrefLevel [Byte0]: 57
1045 00:59:02.546703 [Byte1]: 57
1046 00:59:02.546751
1047 00:59:02.546800 Set Vref, RX VrefLevel [Byte0]: 58
1048 00:59:02.546851 [Byte1]: 58
1049 00:59:02.546901
1050 00:59:02.546949 Set Vref, RX VrefLevel [Byte0]: 59
1051 00:59:02.546997 [Byte1]: 59
1052 00:59:02.547046
1053 00:59:02.547094 Set Vref, RX VrefLevel [Byte0]: 60
1054 00:59:02.547146 [Byte1]: 60
1055 00:59:02.547195
1056 00:59:02.547244 Set Vref, RX VrefLevel [Byte0]: 61
1057 00:59:02.547293 [Byte1]: 61
1058 00:59:02.547342
1059 00:59:02.547390 Set Vref, RX VrefLevel [Byte0]: 62
1060 00:59:02.547443 [Byte1]: 62
1061 00:59:02.547520
1062 00:59:02.547597 Set Vref, RX VrefLevel [Byte0]: 63
1063 00:59:02.547673 [Byte1]: 63
1064 00:59:02.547750
1065 00:59:02.547827 Set Vref, RX VrefLevel [Byte0]: 64
1066 00:59:02.547904 [Byte1]: 64
1067 00:59:02.547979
1068 00:59:02.548050 Set Vref, RX VrefLevel [Byte0]: 65
1069 00:59:02.548101 [Byte1]: 65
1070 00:59:02.548150
1071 00:59:02.548198 Set Vref, RX VrefLevel [Byte0]: 66
1072 00:59:02.548247 [Byte1]: 66
1073 00:59:02.548295
1074 00:59:02.548348 Set Vref, RX VrefLevel [Byte0]: 67
1075 00:59:02.548397 [Byte1]: 67
1076 00:59:02.548445
1077 00:59:02.548522 Set Vref, RX VrefLevel [Byte0]: 68
1078 00:59:02.548602 [Byte1]: 68
1079 00:59:02.548685
1080 00:59:02.548736 Set Vref, RX VrefLevel [Byte0]: 69
1081 00:59:02.548786 [Byte1]: 69
1082 00:59:02.548834
1083 00:59:02.548882 Set Vref, RX VrefLevel [Byte0]: 70
1084 00:59:02.548936 [Byte1]: 70
1085 00:59:02.548985
1086 00:59:02.549034 Set Vref, RX VrefLevel [Byte0]: 71
1087 00:59:02.549084 [Byte1]: 71
1088 00:59:02.549132
1089 00:59:02.549180 Set Vref, RX VrefLevel [Byte0]: 72
1090 00:59:02.549234 [Byte1]: 72
1091 00:59:02.549283
1092 00:59:02.549332 Set Vref, RX VrefLevel [Byte0]: 73
1093 00:59:02.549381 [Byte1]: 73
1094 00:59:02.549429
1095 00:59:02.549478 Set Vref, RX VrefLevel [Byte0]: 74
1096 00:59:02.549531 [Byte1]: 74
1097 00:59:02.549580
1098 00:59:02.549821 Set Vref, RX VrefLevel [Byte0]: 75
1099 00:59:02.549933 [Byte1]: 75
1100 00:59:02.550041
1101 00:59:02.550151 Set Vref, RX VrefLevel [Byte0]: 76
1102 00:59:02.550261 [Byte1]: 76
1103 00:59:02.550369
1104 00:59:02.550480 Set Vref, RX VrefLevel [Byte0]: 77
1105 00:59:02.550590 [Byte1]: 77
1106 00:59:02.550699
1107 00:59:02.550808 Set Vref, RX VrefLevel [Byte0]: 78
1108 00:59:02.550918 [Byte1]: 78
1109 00:59:02.551019
1110 00:59:02.551075 Final RX Vref Byte 0 = 60 to rank0
1111 00:59:02.551127 Final RX Vref Byte 1 = 54 to rank0
1112 00:59:02.551176 Final RX Vref Byte 0 = 60 to rank1
1113 00:59:02.551226 Final RX Vref Byte 1 = 54 to rank1==
1114 00:59:02.551318 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 00:59:02.551370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 00:59:02.551420 ==
1117 00:59:02.551469 DQS Delay:
1118 00:59:02.551520 DQS0 = 0, DQS1 = 0
1119 00:59:02.551570 DQM Delay:
1120 00:59:02.551619 DQM0 = 81, DQM1 = 67
1121 00:59:02.551669 DQ Delay:
1122 00:59:02.551726 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1123 00:59:02.551795 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1124 00:59:02.551846 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1125 00:59:02.551895 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1126 00:59:02.551944
1127 00:59:02.551992
1128 00:59:02.552045 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1129 00:59:02.552096 CH0 RK0: MR19=606, MR18=2E2D
1130 00:59:02.552145 CH0_RK0: MR19=0x606, MR18=0x2E2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1131 00:59:02.552194
1132 00:59:02.552246 ----->DramcWriteLeveling(PI) begin...
1133 00:59:02.552297 ==
1134 00:59:02.552347 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 00:59:02.552397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 00:59:02.552446 ==
1137 00:59:02.552500 Write leveling (Byte 0): 34 => 34
1138 00:59:02.552578 Write leveling (Byte 1): 29 => 29
1139 00:59:02.552660 DramcWriteLeveling(PI) end<-----
1140 00:59:02.552713
1141 00:59:02.552762 ==
1142 00:59:02.552816 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 00:59:02.552866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 00:59:02.552916 ==
1145 00:59:02.552965 [Gating] SW mode calibration
1146 00:59:02.553014 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 00:59:02.553064 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 00:59:02.553116 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 00:59:02.553166 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 00:59:02.553215 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 00:59:02.553265 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 00:59:02.553372 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 00:59:02.553458 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 00:59:02.553514 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:59:02.553563 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:59:02.553612 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:59:02.553666 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:59:02.553715 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:59:02.553764 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:59:02.553813 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:59:02.553862 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:59:02.553915 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:59:02.553965 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:59:02.554014 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:59:02.554063 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1166 00:59:02.554112 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1167 00:59:02.554171 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:59:02.554249 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:59:02.554326 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:59:02.554406 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:59:02.554483 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:59:02.554560 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:59:02.554639 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:59:02.554716 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
1175 00:59:02.554793 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1176 00:59:02.554870 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 00:59:02.554950 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 00:59:02.555027 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 00:59:02.555117 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:59:02.555199 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:59:02.555276 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1182 00:59:02.555353 0 10 8 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
1183 00:59:02.555433 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:59:02.555510 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:59:02.555590 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:59:02.555669 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:59:02.555746 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:59:02.555824 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:59:02.555888 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1190 00:59:02.555938 0 11 8 | B1->B0 | 2d2d 3f3f | 1 0 | (0 0) (0 0)
1191 00:59:02.555989 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
1192 00:59:02.556037 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 00:59:02.556086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 00:59:02.556156 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 00:59:02.556234 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:59:02.556311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:59:02.556390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1198 00:59:02.556467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 00:59:02.556741 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 00:59:02.556856 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:59:02.556967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:59:02.557076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:59:02.557186 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:59:02.557296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:59:02.557407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:59:02.557494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:59:02.557544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:59:02.557597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:59:02.557647 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:59:02.557696 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:59:02.557745 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:59:02.557794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:59:02.557848 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:59:02.557898 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 00:59:02.557947 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 00:59:02.557996 Total UI for P1: 0, mck2ui 16
1217 00:59:02.558045 best dqsien dly found for B0: ( 0, 14, 8)
1218 00:59:02.558099 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 00:59:02.558149 Total UI for P1: 0, mck2ui 16
1220 00:59:02.558198 best dqsien dly found for B1: ( 0, 14, 10)
1221 00:59:02.558247 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 00:59:02.558297 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1223 00:59:02.558362
1224 00:59:02.558440 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 00:59:02.558517 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1226 00:59:02.558595 [Gating] SW calibration Done
1227 00:59:02.558672 ==
1228 00:59:02.558753 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 00:59:02.558842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 00:59:02.558920 ==
1231 00:59:02.559026 RX Vref Scan: 0
1232 00:59:02.559104
1233 00:59:02.559181 RX Vref 0 -> 0, step: 1
1234 00:59:02.559256
1235 00:59:02.559334 RX Delay -130 -> 252, step: 16
1236 00:59:02.559412 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 00:59:02.559489 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 00:59:02.559568 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1239 00:59:02.559645 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1240 00:59:02.559722 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1241 00:59:02.559798 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1242 00:59:02.559854 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1243 00:59:02.559903 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1244 00:59:02.559952 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1245 00:59:02.560001 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1246 00:59:02.560049 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 00:59:02.560102 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1248 00:59:02.560151 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1249 00:59:02.560200 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1250 00:59:02.560248 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 00:59:02.560297 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1252 00:59:02.560375 ==
1253 00:59:02.560452 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 00:59:02.560529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 00:59:02.560608 ==
1256 00:59:02.560727 DQS Delay:
1257 00:59:02.560779 DQS0 = 0, DQS1 = 0
1258 00:59:02.560832 DQM Delay:
1259 00:59:02.560881 DQM0 = 79, DQM1 = 70
1260 00:59:02.560930 DQ Delay:
1261 00:59:02.560980 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =69
1262 00:59:02.561029 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1263 00:59:02.561083 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1264 00:59:02.561132 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1265 00:59:02.561181
1266 00:59:02.561241
1267 00:59:02.561293 ==
1268 00:59:02.561343 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 00:59:02.561393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 00:59:02.561442 ==
1271 00:59:02.561498
1272 00:59:02.561615
1273 00:59:02.561692 TX Vref Scan disable
1274 00:59:02.561769 == TX Byte 0 ==
1275 00:59:02.561848 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1276 00:59:02.561926 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1277 00:59:02.562003 == TX Byte 1 ==
1278 00:59:02.562082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1279 00:59:02.562160 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1280 00:59:02.562236 ==
1281 00:59:02.562314 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 00:59:02.562392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 00:59:02.562469 ==
1284 00:59:02.562547 TX Vref=22, minBit 5, minWin=26, winSum=433
1285 00:59:02.562625 TX Vref=24, minBit 1, minWin=27, winSum=440
1286 00:59:02.562703 TX Vref=26, minBit 1, minWin=27, winSum=442
1287 00:59:02.562780 TX Vref=28, minBit 1, minWin=27, winSum=445
1288 00:59:02.562859 TX Vref=30, minBit 9, minWin=27, winSum=446
1289 00:59:02.562937 TX Vref=32, minBit 9, minWin=27, winSum=444
1290 00:59:02.563016 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 30
1291 00:59:02.563095
1292 00:59:02.563172 Final TX Range 1 Vref 30
1293 00:59:02.563248
1294 00:59:02.563326 ==
1295 00:59:02.563402 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 00:59:02.563479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 00:59:02.563557 ==
1298 00:59:02.563633
1299 00:59:02.563708
1300 00:59:02.563783 TX Vref Scan disable
1301 00:59:02.563860 == TX Byte 0 ==
1302 00:59:02.563937 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1303 00:59:02.564014 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1304 00:59:02.564091 == TX Byte 1 ==
1305 00:59:02.564168 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1306 00:59:02.564244 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1307 00:59:02.564322
1308 00:59:02.564397 [DATLAT]
1309 00:59:02.564472 Freq=800, CH0 RK1
1310 00:59:02.564549
1311 00:59:02.564628 DATLAT Default: 0xa
1312 00:59:02.564729 0, 0xFFFF, sum = 0
1313 00:59:02.564780 1, 0xFFFF, sum = 0
1314 00:59:02.564834 2, 0xFFFF, sum = 0
1315 00:59:02.564884 3, 0xFFFF, sum = 0
1316 00:59:02.564932 4, 0xFFFF, sum = 0
1317 00:59:02.564982 5, 0xFFFF, sum = 0
1318 00:59:02.565032 6, 0xFFFF, sum = 0
1319 00:59:02.565082 7, 0xFFFF, sum = 0
1320 00:59:02.565130 8, 0xFFFF, sum = 0
1321 00:59:02.565180 9, 0x0, sum = 1
1322 00:59:02.565229 10, 0x0, sum = 2
1323 00:59:02.565280 11, 0x0, sum = 3
1324 00:59:02.565330 12, 0x0, sum = 4
1325 00:59:02.565399 best_step = 10
1326 00:59:02.565483
1327 00:59:02.565536 ==
1328 00:59:02.565585 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 00:59:02.565634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 00:59:02.565683 ==
1331 00:59:02.565731 RX Vref Scan: 0
1332 00:59:02.565782
1333 00:59:02.566025 RX Vref 0 -> 0, step: 1
1334 00:59:02.566082
1335 00:59:02.566131 RX Delay -111 -> 252, step: 8
1336 00:59:02.566179 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1337 00:59:02.566228 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1338 00:59:02.566280 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1339 00:59:02.566330 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1340 00:59:02.566391 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1341 00:59:02.566442 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1342 00:59:02.566491 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1343 00:59:02.566559 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1344 00:59:02.566635 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1345 00:59:02.566712 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1346 00:59:02.566782 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1347 00:59:02.566832 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1348 00:59:02.566881 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1349 00:59:02.566929 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1350 00:59:02.566977 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1351 00:59:02.567029 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1352 00:59:02.567078 ==
1353 00:59:02.567127 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 00:59:02.567176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 00:59:02.567224 ==
1356 00:59:02.567276 DQS Delay:
1357 00:59:02.567324 DQS0 = 0, DQS1 = 0
1358 00:59:02.567372 DQM Delay:
1359 00:59:02.567420 DQM0 = 79, DQM1 = 69
1360 00:59:02.567468 DQ Delay:
1361 00:59:02.567521 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1362 00:59:02.567570 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1363 00:59:02.567618 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1364 00:59:02.567666 DQ12 =76, DQ13 =80, DQ14 =80, DQ15 =76
1365 00:59:02.567714
1366 00:59:02.567767
1367 00:59:02.567816 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1368 00:59:02.567865 CH0 RK1: MR19=606, MR18=4E29
1369 00:59:02.567913 CH0_RK1: MR19=0x606, MR18=0x4E29, DQSOSC=390, MR23=63, INC=97, DEC=64
1370 00:59:02.567961 [RxdqsGatingPostProcess] freq 800
1371 00:59:02.568013 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 00:59:02.568089 Pre-setting of DQS Precalculation
1373 00:59:02.568140 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 00:59:02.568189 ==
1375 00:59:02.568242 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 00:59:02.568293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 00:59:02.568343 ==
1378 00:59:02.568416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 00:59:02.568504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 00:59:02.568582 [CA 0] Center 37 (7~67) winsize 61
1381 00:59:02.568686 [CA 1] Center 37 (7~67) winsize 61
1382 00:59:02.568755 [CA 2] Center 34 (5~64) winsize 60
1383 00:59:02.568804 [CA 3] Center 34 (4~64) winsize 61
1384 00:59:02.568853 [CA 4] Center 34 (4~64) winsize 61
1385 00:59:02.568901 [CA 5] Center 34 (4~64) winsize 61
1386 00:59:02.568949
1387 00:59:02.569002 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1388 00:59:02.569051
1389 00:59:02.569100 [CATrainingPosCal] consider 1 rank data
1390 00:59:02.569149 u2DelayCellTimex100 = 270/100 ps
1391 00:59:02.569197 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1392 00:59:02.569250 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1393 00:59:02.569299 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1394 00:59:02.569348 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1395 00:59:02.569396 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1396 00:59:02.569445 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 00:59:02.569497
1398 00:59:02.569546 CA PerBit enable=1, Macro0, CA PI delay=34
1399 00:59:02.569594
1400 00:59:02.569642 [CBTSetCACLKResult] CA Dly = 34
1401 00:59:02.569690 CS Dly: 5 (0~36)
1402 00:59:02.569742 ==
1403 00:59:02.569791 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 00:59:02.569840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 00:59:02.569888 ==
1406 00:59:02.569936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 00:59:02.569989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 00:59:02.570039 [CA 0] Center 36 (6~67) winsize 62
1409 00:59:02.570086 [CA 1] Center 36 (6~67) winsize 62
1410 00:59:02.570134 [CA 2] Center 35 (5~65) winsize 61
1411 00:59:02.570182 [CA 3] Center 34 (4~65) winsize 62
1412 00:59:02.570235 [CA 4] Center 34 (4~65) winsize 62
1413 00:59:02.570283 [CA 5] Center 33 (3~64) winsize 62
1414 00:59:02.570331
1415 00:59:02.570379 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 00:59:02.570428
1417 00:59:02.570480 [CATrainingPosCal] consider 2 rank data
1418 00:59:02.570530 u2DelayCellTimex100 = 270/100 ps
1419 00:59:02.570577 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1420 00:59:02.570625 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1421 00:59:02.570673 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1422 00:59:02.570728 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 00:59:02.570805 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 00:59:02.570881 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 00:59:02.570958
1426 00:59:02.571017 CA PerBit enable=1, Macro0, CA PI delay=34
1427 00:59:02.571084
1428 00:59:02.571140 [CBTSetCACLKResult] CA Dly = 34
1429 00:59:02.571192 CS Dly: 6 (0~38)
1430 00:59:02.571241
1431 00:59:02.571289 ----->DramcWriteLeveling(PI) begin...
1432 00:59:02.571344 ==
1433 00:59:02.571393 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 00:59:02.571446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 00:59:02.571495 ==
1436 00:59:02.571553 Write leveling (Byte 0): 28 => 28
1437 00:59:02.571642 Write leveling (Byte 1): 30 => 30
1438 00:59:02.571719 DramcWriteLeveling(PI) end<-----
1439 00:59:02.571796
1440 00:59:02.571874 ==
1441 00:59:02.571950 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 00:59:02.572027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 00:59:02.572090 ==
1444 00:59:02.572140 [Gating] SW mode calibration
1445 00:59:02.572189 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 00:59:02.572239 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 00:59:02.572287 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 00:59:02.572340 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 00:59:02.572388 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 00:59:02.572437 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 00:59:02.572485 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:59:02.572717 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:59:02.572829 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:59:02.572939 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:59:02.573048 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:59:02.573157 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:59:02.573266 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:59:02.573375 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:59:02.573484 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:59:02.573592 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:59:02.573700 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:59:02.573808 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:59:02.573907 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:59:02.573961 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 00:59:02.574010 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:59:02.574063 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:59:02.574112 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:59:02.574160 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:59:02.574208 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:59:02.574257 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:59:02.574310 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:59:02.574358 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:59:02.574406 0 9 8 | B1->B0 | 2929 2929 | 0 0 | (1 0) (0 0)
1474 00:59:02.574455 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 00:59:02.574503 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 00:59:02.574555 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 00:59:02.574604 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:59:02.574668 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:59:02.574727 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:59:02.574778 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
1481 00:59:02.574828 0 10 8 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
1482 00:59:02.574877 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:59:02.574924 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:59:02.574972 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:59:02.575023 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:59:02.575072 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:59:02.575120 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:59:02.575169 0 11 4 | B1->B0 | 2424 2524 | 0 1 | (0 0) (0 0)
1489 00:59:02.575218 0 11 8 | B1->B0 | 3939 3939 | 0 0 | (0 0) (0 0)
1490 00:59:02.575270 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 00:59:02.575318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 00:59:02.575365 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 00:59:02.575413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:59:02.575461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:59:02.575513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:59:02.575562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:59:02.575610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 00:59:02.575658 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 00:59:02.575707 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 00:59:02.575758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:59:02.575807 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:59:02.575855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:59:02.575902 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:59:02.575951 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:59:02.576002 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:59:02.576051 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:59:02.576099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:59:02.576147 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:59:02.576195 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:59:02.576247 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:59:02.576296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:59:02.576344 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:59:02.576394 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 00:59:02.576442 Total UI for P1: 0, mck2ui 16
1515 00:59:02.576498 best dqsien dly found for B0: ( 0, 14, 6)
1516 00:59:02.576575 Total UI for P1: 0, mck2ui 16
1517 00:59:02.576658 best dqsien dly found for B1: ( 0, 14, 6)
1518 00:59:02.576762 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1519 00:59:02.576813 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1520 00:59:02.576862
1521 00:59:02.576911 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 00:59:02.576960 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 00:59:02.577013 [Gating] SW calibration Done
1524 00:59:02.577062 ==
1525 00:59:02.577110 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 00:59:02.577158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 00:59:02.577207 ==
1528 00:59:02.577260 RX Vref Scan: 0
1529 00:59:02.577308
1530 00:59:02.577356 RX Vref 0 -> 0, step: 1
1531 00:59:02.577404
1532 00:59:02.577451 RX Delay -130 -> 252, step: 16
1533 00:59:02.577504 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1534 00:59:02.577555 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1535 00:59:02.577604 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1536 00:59:02.577651 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1537 00:59:02.577698 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1538 00:59:02.577751 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1539 00:59:02.577800 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1540 00:59:02.577848 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1541 00:59:02.577896 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1542 00:59:02.578140 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1543 00:59:02.578253 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1544 00:59:02.578365 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1545 00:59:02.578474 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1546 00:59:02.578585 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1547 00:59:02.578694 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1548 00:59:02.578787 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1549 00:59:02.578866 ==
1550 00:59:02.578942 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 00:59:02.579019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 00:59:02.579098 ==
1553 00:59:02.579173 DQS Delay:
1554 00:59:02.579248 DQS0 = 0, DQS1 = 0
1555 00:59:02.579326 DQM Delay:
1556 00:59:02.579403 DQM0 = 80, DQM1 = 70
1557 00:59:02.579478 DQ Delay:
1558 00:59:02.579554 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1559 00:59:02.579633 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1560 00:59:02.579709 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1561 00:59:02.579786 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1562 00:59:02.579864
1563 00:59:02.579939
1564 00:59:02.580013 ==
1565 00:59:02.580090 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 00:59:02.580169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 00:59:02.580244 ==
1568 00:59:02.580319
1569 00:59:02.580392
1570 00:59:02.580443 TX Vref Scan disable
1571 00:59:02.580491 == TX Byte 0 ==
1572 00:59:02.580540 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1573 00:59:02.580589 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1574 00:59:02.580637 == TX Byte 1 ==
1575 00:59:02.580761 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1576 00:59:02.580838 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1577 00:59:02.580914 ==
1578 00:59:02.580992 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 00:59:02.581068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 00:59:02.581144 ==
1581 00:59:02.581229 TX Vref=22, minBit 1, minWin=27, winSum=439
1582 00:59:02.581308 TX Vref=24, minBit 0, minWin=27, winSum=439
1583 00:59:02.581386 TX Vref=26, minBit 1, minWin=27, winSum=445
1584 00:59:02.581448 TX Vref=28, minBit 1, minWin=27, winSum=446
1585 00:59:02.581500 TX Vref=30, minBit 5, minWin=27, winSum=448
1586 00:59:02.581550 TX Vref=32, minBit 5, minWin=27, winSum=448
1587 00:59:02.581599 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 30
1588 00:59:02.581679
1589 00:59:02.581731 Final TX Range 1 Vref 30
1590 00:59:02.581784
1591 00:59:02.581832 ==
1592 00:59:02.581880 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 00:59:02.581929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 00:59:02.581978 ==
1595 00:59:02.582026
1596 00:59:02.582078
1597 00:59:02.582127 TX Vref Scan disable
1598 00:59:02.582175 == TX Byte 0 ==
1599 00:59:02.582224 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 00:59:02.582273 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1601 00:59:02.582322 == TX Byte 1 ==
1602 00:59:02.582374 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 00:59:02.582424 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 00:59:02.582473
1605 00:59:02.582521 [DATLAT]
1606 00:59:02.582570 Freq=800, CH1 RK0
1607 00:59:02.582621
1608 00:59:02.582669 DATLAT Default: 0xa
1609 00:59:02.582717 0, 0xFFFF, sum = 0
1610 00:59:02.582766 1, 0xFFFF, sum = 0
1611 00:59:02.582815 2, 0xFFFF, sum = 0
1612 00:59:02.582864 3, 0xFFFF, sum = 0
1613 00:59:02.582917 4, 0xFFFF, sum = 0
1614 00:59:02.582966 5, 0xFFFF, sum = 0
1615 00:59:02.583015 6, 0xFFFF, sum = 0
1616 00:59:02.583063 7, 0xFFFF, sum = 0
1617 00:59:02.583112 8, 0xFFFF, sum = 0
1618 00:59:02.583161 9, 0x0, sum = 1
1619 00:59:02.583214 10, 0x0, sum = 2
1620 00:59:02.583285 11, 0x0, sum = 3
1621 00:59:02.583336 12, 0x0, sum = 4
1622 00:59:02.583385 best_step = 10
1623 00:59:02.583436
1624 00:59:02.583485 ==
1625 00:59:02.583534 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 00:59:02.583583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 00:59:02.583631 ==
1628 00:59:02.583682 RX Vref Scan: 1
1629 00:59:02.583738
1630 00:59:02.583806 Set Vref Range= 32 -> 127
1631 00:59:02.583887
1632 00:59:02.583962 RX Vref 32 -> 127, step: 1
1633 00:59:02.584042
1634 00:59:02.584119 RX Delay -111 -> 252, step: 8
1635 00:59:02.584198
1636 00:59:02.584276 Set Vref, RX VrefLevel [Byte0]: 32
1637 00:59:02.584352 [Byte1]: 32
1638 00:59:02.584432
1639 00:59:02.584509 Set Vref, RX VrefLevel [Byte0]: 33
1640 00:59:02.584589 [Byte1]: 33
1641 00:59:02.584691
1642 00:59:02.584761 Set Vref, RX VrefLevel [Byte0]: 34
1643 00:59:02.584811 [Byte1]: 34
1644 00:59:02.584860
1645 00:59:02.584913 Set Vref, RX VrefLevel [Byte0]: 35
1646 00:59:02.584984 [Byte1]: 35
1647 00:59:02.585036
1648 00:59:02.585087 Set Vref, RX VrefLevel [Byte0]: 36
1649 00:59:02.585136 [Byte1]: 36
1650 00:59:02.585184
1651 00:59:02.585232 Set Vref, RX VrefLevel [Byte0]: 37
1652 00:59:02.585308 [Byte1]: 37
1653 00:59:02.585385
1654 00:59:02.585436 Set Vref, RX VrefLevel [Byte0]: 38
1655 00:59:02.585485 [Byte1]: 38
1656 00:59:02.585533
1657 00:59:02.585585 Set Vref, RX VrefLevel [Byte0]: 39
1658 00:59:02.585635 [Byte1]: 39
1659 00:59:02.585683
1660 00:59:02.585731 Set Vref, RX VrefLevel [Byte0]: 40
1661 00:59:02.585779 [Byte1]: 40
1662 00:59:02.585827
1663 00:59:02.585878 Set Vref, RX VrefLevel [Byte0]: 41
1664 00:59:02.585926 [Byte1]: 41
1665 00:59:02.585974
1666 00:59:02.586021 Set Vref, RX VrefLevel [Byte0]: 42
1667 00:59:02.586069 [Byte1]: 42
1668 00:59:02.586117
1669 00:59:02.586168 Set Vref, RX VrefLevel [Byte0]: 43
1670 00:59:02.586216 [Byte1]: 43
1671 00:59:02.586264
1672 00:59:02.586311 Set Vref, RX VrefLevel [Byte0]: 44
1673 00:59:02.586359 [Byte1]: 44
1674 00:59:02.586406
1675 00:59:02.586458 Set Vref, RX VrefLevel [Byte0]: 45
1676 00:59:02.586506 [Byte1]: 45
1677 00:59:02.586553
1678 00:59:02.586601 Set Vref, RX VrefLevel [Byte0]: 46
1679 00:59:02.586649 [Byte1]: 46
1680 00:59:02.586697
1681 00:59:02.586748 Set Vref, RX VrefLevel [Byte0]: 47
1682 00:59:02.586796 [Byte1]: 47
1683 00:59:02.586844
1684 00:59:02.586891 Set Vref, RX VrefLevel [Byte0]: 48
1685 00:59:02.586939 [Byte1]: 48
1686 00:59:02.586991
1687 00:59:02.587039 Set Vref, RX VrefLevel [Byte0]: 49
1688 00:59:02.587087 [Byte1]: 49
1689 00:59:02.587135
1690 00:59:02.587183 Set Vref, RX VrefLevel [Byte0]: 50
1691 00:59:02.587232 [Byte1]: 50
1692 00:59:02.587300
1693 00:59:02.587375 Set Vref, RX VrefLevel [Byte0]: 51
1694 00:59:02.587451 [Byte1]: 51
1695 00:59:02.587530
1696 00:59:02.587608 Set Vref, RX VrefLevel [Byte0]: 52
1697 00:59:02.587690 [Byte1]: 52
1698 00:59:02.587752
1699 00:59:02.587804 Set Vref, RX VrefLevel [Byte0]: 53
1700 00:59:02.587854 [Byte1]: 53
1701 00:59:02.587902
1702 00:59:02.587950 Set Vref, RX VrefLevel [Byte0]: 54
1703 00:59:02.587999 [Byte1]: 54
1704 00:59:02.588047
1705 00:59:02.588296 Set Vref, RX VrefLevel [Byte0]: 55
1706 00:59:02.588408 [Byte1]: 55
1707 00:59:02.588517
1708 00:59:02.588624 Set Vref, RX VrefLevel [Byte0]: 56
1709 00:59:02.588780 [Byte1]: 56
1710 00:59:02.588888
1711 00:59:02.588968 Set Vref, RX VrefLevel [Byte0]: 57
1712 00:59:02.589020 [Byte1]: 57
1713 00:59:02.589069
1714 00:59:02.589118 Set Vref, RX VrefLevel [Byte0]: 58
1715 00:59:02.589168 [Byte1]: 58
1716 00:59:02.589219
1717 00:59:02.589267 Set Vref, RX VrefLevel [Byte0]: 59
1718 00:59:02.589316 [Byte1]: 59
1719 00:59:02.589364
1720 00:59:02.589411 Set Vref, RX VrefLevel [Byte0]: 60
1721 00:59:02.589461 [Byte1]: 60
1722 00:59:02.589510
1723 00:59:02.589559 Set Vref, RX VrefLevel [Byte0]: 61
1724 00:59:02.589607 [Byte1]: 61
1725 00:59:02.589655
1726 00:59:02.589703 Set Vref, RX VrefLevel [Byte0]: 62
1727 00:59:02.589756 [Byte1]: 62
1728 00:59:02.589804
1729 00:59:02.589852 Set Vref, RX VrefLevel [Byte0]: 63
1730 00:59:02.589900 [Byte1]: 63
1731 00:59:02.589948
1732 00:59:02.589995 Set Vref, RX VrefLevel [Byte0]: 64
1733 00:59:02.590047 [Byte1]: 64
1734 00:59:02.590097
1735 00:59:02.590144 Set Vref, RX VrefLevel [Byte0]: 65
1736 00:59:02.590192 [Byte1]: 65
1737 00:59:02.590240
1738 00:59:02.590287 Set Vref, RX VrefLevel [Byte0]: 66
1739 00:59:02.590340 [Byte1]: 66
1740 00:59:02.590388
1741 00:59:02.590435 Set Vref, RX VrefLevel [Byte0]: 67
1742 00:59:02.590482 [Byte1]: 67
1743 00:59:02.590530
1744 00:59:02.590577 Set Vref, RX VrefLevel [Byte0]: 68
1745 00:59:02.590646 [Byte1]: 68
1746 00:59:02.590721
1747 00:59:02.590796 Set Vref, RX VrefLevel [Byte0]: 69
1748 00:59:02.590872 [Byte1]: 69
1749 00:59:02.590948
1750 00:59:02.591028 Set Vref, RX VrefLevel [Byte0]: 70
1751 00:59:02.591095 [Byte1]: 70
1752 00:59:02.591144
1753 00:59:02.591210 Set Vref, RX VrefLevel [Byte0]: 71
1754 00:59:02.591286 [Byte1]: 71
1755 00:59:02.591361
1756 00:59:02.591437 Set Vref, RX VrefLevel [Byte0]: 72
1757 00:59:02.591514 [Byte1]: 72
1758 00:59:02.591589
1759 00:59:02.591665 Set Vref, RX VrefLevel [Byte0]: 73
1760 00:59:02.591743 [Byte1]: 73
1761 00:59:02.591818
1762 00:59:02.591893 Final RX Vref Byte 0 = 62 to rank0
1763 00:59:02.591969 Final RX Vref Byte 1 = 52 to rank0
1764 00:59:02.592048 Final RX Vref Byte 0 = 62 to rank1
1765 00:59:02.592125 Final RX Vref Byte 1 = 52 to rank1==
1766 00:59:02.592201 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 00:59:02.592280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 00:59:02.592356 ==
1769 00:59:02.592431 DQS Delay:
1770 00:59:02.592507 DQS0 = 0, DQS1 = 0
1771 00:59:02.592585 DQM Delay:
1772 00:59:02.592664 DQM0 = 80, DQM1 = 71
1773 00:59:02.592716 DQ Delay:
1774 00:59:02.592765 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1775 00:59:02.592817 DQ4 =76, DQ5 =92, DQ6 =96, DQ7 =76
1776 00:59:02.592866 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1777 00:59:02.592914 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1778 00:59:02.592962
1779 00:59:02.593010
1780 00:59:02.593058 [DQSOSCAuto] RK0, (LSB)MR18= 0x1720, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1781 00:59:02.593109 CH1 RK0: MR19=606, MR18=1720
1782 00:59:02.593158 CH1_RK0: MR19=0x606, MR18=0x1720, DQSOSC=401, MR23=63, INC=91, DEC=61
1783 00:59:02.593207
1784 00:59:02.593254 ----->DramcWriteLeveling(PI) begin...
1785 00:59:02.593303 ==
1786 00:59:02.593351 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 00:59:02.593404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 00:59:02.593453 ==
1789 00:59:02.593500 Write leveling (Byte 0): 26 => 26
1790 00:59:02.593548 Write leveling (Byte 1): 31 => 31
1791 00:59:02.593596 DramcWriteLeveling(PI) end<-----
1792 00:59:02.593647
1793 00:59:02.593696 ==
1794 00:59:02.593744 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 00:59:02.593792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 00:59:02.593839 ==
1797 00:59:02.593886 [Gating] SW mode calibration
1798 00:59:02.593937 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 00:59:02.593987 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 00:59:02.594035 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 00:59:02.594083 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1802 00:59:02.594132 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:59:02.594180 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:59:02.594244 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:59:02.594321 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:59:02.594405 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:59:02.594458 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:59:02.594511 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:59:02.594560 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:59:02.594608 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:59:02.594656 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:59:02.594705 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:59:02.594757 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:59:02.594806 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:59:02.594855 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:59:02.594903 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1817 00:59:02.594951 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1818 00:59:02.595000 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:59:02.595051 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:59:02.595099 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:59:02.595148 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:59:02.595196 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:59:02.595243 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:59:02.595291 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:59:02.595343 0 9 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
1826 00:59:02.595392 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1827 00:59:02.595440 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 00:59:02.595487 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 00:59:02.595726 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 00:59:02.595783 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 00:59:02.595835 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 00:59:02.595884 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 00:59:02.595933 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (1 0) (0 1)
1834 00:59:02.595981 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
1835 00:59:02.596029 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:59:02.596076 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:59:02.596128 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:59:02.596177 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:59:02.596225 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:59:02.596273 0 11 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
1841 00:59:02.596321 0 11 4 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
1842 00:59:02.596372 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1843 00:59:02.596425 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 00:59:02.596482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 00:59:02.596567 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 00:59:02.596657 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 00:59:02.596803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 00:59:02.596880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 00:59:02.596943 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1850 00:59:02.596993 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:59:02.597041 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:59:02.597100 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:59:02.597150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:59:02.597199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:59:02.597248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:59:02.597302 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:59:02.597350 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:59:02.597399 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:59:02.597452 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:59:02.597501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:59:02.597549 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:59:02.597600 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:59:02.597657 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:59:02.597726 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:59:02.597776 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1866 00:59:02.597827 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 00:59:02.597876 Total UI for P1: 0, mck2ui 16
1868 00:59:02.597926 best dqsien dly found for B0: ( 0, 14, 4)
1869 00:59:02.597974 Total UI for P1: 0, mck2ui 16
1870 00:59:02.598027 best dqsien dly found for B1: ( 0, 14, 6)
1871 00:59:02.598075 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1872 00:59:02.598124 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1873 00:59:02.598176
1874 00:59:02.598226 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 00:59:02.598275 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1876 00:59:02.598323 [Gating] SW calibration Done
1877 00:59:02.598371 ==
1878 00:59:02.598419 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 00:59:02.598472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 00:59:02.598522 ==
1881 00:59:02.598571 RX Vref Scan: 0
1882 00:59:02.598619
1883 00:59:02.598666 RX Vref 0 -> 0, step: 1
1884 00:59:02.598716
1885 00:59:02.598765 RX Delay -130 -> 252, step: 16
1886 00:59:02.598816 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1887 00:59:02.598865 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1888 00:59:02.598913 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1889 00:59:02.598961 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1890 00:59:02.599012 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1891 00:59:02.599061 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1892 00:59:02.599109 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1893 00:59:02.599157 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1894 00:59:02.599204 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1895 00:59:02.599253 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1896 00:59:02.599303 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1897 00:59:02.599355 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1898 00:59:02.599403 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1899 00:59:02.599451 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1900 00:59:02.599502 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1901 00:59:02.599552 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1902 00:59:02.599599 ==
1903 00:59:02.599646 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 00:59:02.599694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 00:59:02.599744 ==
1906 00:59:02.599794 DQS Delay:
1907 00:59:02.599845 DQS0 = 0, DQS1 = 0
1908 00:59:02.599894 DQM Delay:
1909 00:59:02.599942 DQM0 = 77, DQM1 = 71
1910 00:59:02.599990 DQ Delay:
1911 00:59:02.600040 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =69
1912 00:59:02.600089 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1913 00:59:02.600136 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1914 00:59:02.600184 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1915 00:59:02.600232
1916 00:59:02.600279
1917 00:59:02.600330 ==
1918 00:59:02.600381 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 00:59:02.600430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 00:59:02.854775 ==
1921 00:59:02.854907
1922 00:59:02.854993
1923 00:59:02.855077 TX Vref Scan disable
1924 00:59:02.855158 == TX Byte 0 ==
1925 00:59:02.855238 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1926 00:59:02.855319 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1927 00:59:02.855397 == TX Byte 1 ==
1928 00:59:02.855474 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1929 00:59:02.855554 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1930 00:59:02.855632 ==
1931 00:59:02.855709 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 00:59:02.855787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 00:59:02.855866 ==
1934 00:59:02.855943 TX Vref=22, minBit 1, minWin=28, winSum=452
1935 00:59:02.856021 TX Vref=24, minBit 9, minWin=27, winSum=454
1936 00:59:02.856312 TX Vref=26, minBit 1, minWin=28, winSum=458
1937 00:59:02.856466 TX Vref=28, minBit 1, minWin=28, winSum=463
1938 00:59:02.856581 TX Vref=30, minBit 1, minWin=28, winSum=462
1939 00:59:02.856730 TX Vref=32, minBit 1, minWin=28, winSum=465
1940 00:59:02.856843 [TxChooseVref] Worse bit 1, Min win 28, Win sum 465, Final Vref 32
1941 00:59:02.856957
1942 00:59:02.857069 Final TX Range 1 Vref 32
1943 00:59:02.857198
1944 00:59:02.857310 ==
1945 00:59:02.857423 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 00:59:02.857550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 00:59:02.857663 ==
1948 00:59:02.857758
1949 00:59:02.857837
1950 00:59:02.857913 TX Vref Scan disable
1951 00:59:02.857990 == TX Byte 0 ==
1952 00:59:02.858069 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1953 00:59:02.858148 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1954 00:59:02.858224 == TX Byte 1 ==
1955 00:59:02.858332 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1956 00:59:02.858409 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1957 00:59:02.858484
1958 00:59:02.858561 [DATLAT]
1959 00:59:02.858638 Freq=800, CH1 RK1
1960 00:59:02.858713
1961 00:59:02.858791 DATLAT Default: 0xa
1962 00:59:02.858867 0, 0xFFFF, sum = 0
1963 00:59:02.858945 1, 0xFFFF, sum = 0
1964 00:59:02.859024 2, 0xFFFF, sum = 0
1965 00:59:02.859103 3, 0xFFFF, sum = 0
1966 00:59:02.859181 4, 0xFFFF, sum = 0
1967 00:59:02.859259 5, 0xFFFF, sum = 0
1968 00:59:02.859337 6, 0xFFFF, sum = 0
1969 00:59:02.859414 7, 0xFFFF, sum = 0
1970 00:59:02.859511 8, 0xFFFF, sum = 0
1971 00:59:02.859641 9, 0x0, sum = 1
1972 00:59:02.859749 10, 0x0, sum = 2
1973 00:59:02.859892 11, 0x0, sum = 3
1974 00:59:02.859985 12, 0x0, sum = 4
1975 00:59:02.860064 best_step = 10
1976 00:59:02.860142
1977 00:59:02.860220 ==
1978 00:59:02.860298 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 00:59:02.860376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 00:59:02.860454 ==
1981 00:59:02.860530 RX Vref Scan: 0
1982 00:59:02.860606
1983 00:59:02.860716 RX Vref 0 -> 0, step: 1
1984 00:59:02.860767
1985 00:59:02.860816 RX Delay -111 -> 252, step: 8
1986 00:59:02.860872 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1987 00:59:02.860949 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1988 00:59:02.861026 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1989 00:59:02.861104 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1990 00:59:02.861184 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
1991 00:59:02.861261 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1992 00:59:02.861338 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1993 00:59:02.861417 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1994 00:59:02.861494 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1995 00:59:02.861572 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1996 00:59:02.861629 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1997 00:59:02.861686 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1998 00:59:02.861763 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1999 00:59:02.861840 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2000 00:59:02.861918 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2001 00:59:02.861995 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2002 00:59:02.862070 ==
2003 00:59:02.862149 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 00:59:02.862227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 00:59:02.862303 ==
2006 00:59:02.862381 DQS Delay:
2007 00:59:02.862457 DQS0 = 0, DQS1 = 0
2008 00:59:02.862533 DQM Delay:
2009 00:59:02.862611 DQM0 = 77, DQM1 = 74
2010 00:59:02.862688 DQ Delay:
2011 00:59:02.862765 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2012 00:59:02.862846 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2013 00:59:02.862933 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2014 00:59:02.863010 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2015 00:59:02.863087
2016 00:59:02.863164
2017 00:59:02.863243 [DQSOSCAuto] RK1, (LSB)MR18= 0x263f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2018 00:59:02.863323 CH1 RK1: MR19=606, MR18=263F
2019 00:59:02.863401 CH1_RK1: MR19=0x606, MR18=0x263F, DQSOSC=393, MR23=63, INC=95, DEC=63
2020 00:59:02.863478 [RxdqsGatingPostProcess] freq 800
2021 00:59:02.863555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 00:59:02.863636 Pre-setting of DQS Precalculation
2023 00:59:02.863714 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 00:59:02.863792 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 00:59:02.863873 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 00:59:02.863949
2027 00:59:02.864025
2028 00:59:02.864089 [Calibration Summary] 1600 Mbps
2029 00:59:02.864141 CH 0, Rank 0
2030 00:59:02.864191 SW Impedance : PASS
2031 00:59:02.864240 DUTY Scan : NO K
2032 00:59:02.864289 ZQ Calibration : PASS
2033 00:59:02.864362 Jitter Meter : NO K
2034 00:59:02.864439 CBT Training : PASS
2035 00:59:02.864515 Write leveling : PASS
2036 00:59:02.864593 RX DQS gating : PASS
2037 00:59:02.864699 RX DQ/DQS(RDDQC) : PASS
2038 00:59:02.864790 TX DQ/DQS : PASS
2039 00:59:02.864869 RX DATLAT : PASS
2040 00:59:02.864937 RX DQ/DQS(Engine): PASS
2041 00:59:02.864988 TX OE : NO K
2042 00:59:02.865036 All Pass.
2043 00:59:02.865090
2044 00:59:02.865142 CH 0, Rank 1
2045 00:59:02.865193 SW Impedance : PASS
2046 00:59:02.865242 DUTY Scan : NO K
2047 00:59:02.865291 ZQ Calibration : PASS
2048 00:59:02.865344 Jitter Meter : NO K
2049 00:59:02.865393 CBT Training : PASS
2050 00:59:02.865444 Write leveling : PASS
2051 00:59:02.865492 RX DQS gating : PASS
2052 00:59:02.865540 RX DQ/DQS(RDDQC) : PASS
2053 00:59:02.865592 TX DQ/DQS : PASS
2054 00:59:02.865664 RX DATLAT : PASS
2055 00:59:02.865740 RX DQ/DQS(Engine): PASS
2056 00:59:02.865830 TX OE : NO K
2057 00:59:02.865908 All Pass.
2058 00:59:02.865984
2059 00:59:02.866063 CH 1, Rank 0
2060 00:59:02.866141 SW Impedance : PASS
2061 00:59:02.866218 DUTY Scan : NO K
2062 00:59:02.866295 ZQ Calibration : PASS
2063 00:59:02.866372 Jitter Meter : NO K
2064 00:59:02.866448 CBT Training : PASS
2065 00:59:02.866525 Write leveling : PASS
2066 00:59:02.866604 RX DQS gating : PASS
2067 00:59:02.866681 RX DQ/DQS(RDDQC) : PASS
2068 00:59:02.866757 TX DQ/DQS : PASS
2069 00:59:02.866835 RX DATLAT : PASS
2070 00:59:02.866911 RX DQ/DQS(Engine): PASS
2071 00:59:02.866987 TX OE : NO K
2072 00:59:02.867065 All Pass.
2073 00:59:02.867172
2074 00:59:02.867248 CH 1, Rank 1
2075 00:59:02.867326 SW Impedance : PASS
2076 00:59:02.867402 DUTY Scan : NO K
2077 00:59:02.867478 ZQ Calibration : PASS
2078 00:59:02.867602 Jitter Meter : NO K
2079 00:59:02.867684 CBT Training : PASS
2080 00:59:02.867751 Write leveling : PASS
2081 00:59:02.867804 RX DQS gating : PASS
2082 00:59:02.867853 RX DQ/DQS(RDDQC) : PASS
2083 00:59:02.867901 TX DQ/DQS : PASS
2084 00:59:02.867950 RX DATLAT : PASS
2085 00:59:02.867998 RX DQ/DQS(Engine): PASS
2086 00:59:02.868077 TX OE : NO K
2087 00:59:02.868154 All Pass.
2088 00:59:02.868229
2089 00:59:02.868307 DramC Write-DBI off
2090 00:59:02.868581 PER_BANK_REFRESH: Hybrid Mode
2091 00:59:02.868699 TX_TRACKING: ON
2092 00:59:02.868756 [GetDramInforAfterCalByMRR] Vendor 6.
2093 00:59:02.868808 [GetDramInforAfterCalByMRR] Revision 606.
2094 00:59:02.868857 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 00:59:02.868907 MR0 0x3b3b
2096 00:59:02.868956 MR8 0x5151
2097 00:59:02.869010 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 00:59:02.869062
2099 00:59:02.869111 MR0 0x3b3b
2100 00:59:02.869159 MR8 0x5151
2101 00:59:02.869209 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 00:59:02.869262
2103 00:59:02.869311 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 00:59:02.869361 [FAST_K] Save calibration result to emmc
2105 00:59:02.869410 [FAST_K] Save calibration result to emmc
2106 00:59:02.869459 dram_init: config_dvfs: 1
2107 00:59:02.869534 dramc_set_vcore_voltage set vcore to 662500
2108 00:59:02.869639 Read voltage for 1200, 2
2109 00:59:02.869720 Vio18 = 0
2110 00:59:02.869797 Vcore = 662500
2111 00:59:02.869872 Vdram = 0
2112 00:59:02.869948 Vddq = 0
2113 00:59:02.870027 Vmddr = 0
2114 00:59:02.870104 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 00:59:02.870182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 00:59:02.870261 MEM_TYPE=3, freq_sel=15
2117 00:59:02.870337 sv_algorithm_assistance_LP4_1600
2118 00:59:02.870415 ============ PULL DRAM RESETB DOWN ============
2119 00:59:02.870494 ========== PULL DRAM RESETB DOWN end =========
2120 00:59:02.870574 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 00:59:02.870651 ===================================
2122 00:59:02.870730 LPDDR4 DRAM CONFIGURATION
2123 00:59:02.870807 ===================================
2124 00:59:02.870884 EX_ROW_EN[0] = 0x0
2125 00:59:02.870961 EX_ROW_EN[1] = 0x0
2126 00:59:02.871039 LP4Y_EN = 0x0
2127 00:59:02.871114 WORK_FSP = 0x0
2128 00:59:02.871191 WL = 0x4
2129 00:59:02.871269 RL = 0x4
2130 00:59:02.871344 BL = 0x2
2131 00:59:02.871420 RPST = 0x0
2132 00:59:02.871501 RD_PRE = 0x0
2133 00:59:02.871615 WR_PRE = 0x1
2134 00:59:02.871691 WR_PST = 0x0
2135 00:59:02.871768 DBI_WR = 0x0
2136 00:59:02.871844 DBI_RD = 0x0
2137 00:59:02.871919 OTF = 0x1
2138 00:59:02.871983 ===================================
2139 00:59:02.872036 ===================================
2140 00:59:02.872086 ANA top config
2141 00:59:02.872134 ===================================
2142 00:59:02.872185 DLL_ASYNC_EN = 0
2143 00:59:02.872235 ALL_SLAVE_EN = 0
2144 00:59:02.872283 NEW_RANK_MODE = 1
2145 00:59:02.872333 DLL_IDLE_MODE = 1
2146 00:59:02.872381 LP45_APHY_COMB_EN = 1
2147 00:59:02.872433 TX_ODT_DIS = 1
2148 00:59:02.872483 NEW_8X_MODE = 1
2149 00:59:02.872560 ===================================
2150 00:59:02.872637 ===================================
2151 00:59:02.872743 data_rate = 2400
2152 00:59:02.872815 CKR = 1
2153 00:59:02.872870 DQ_P2S_RATIO = 8
2154 00:59:02.872921 ===================================
2155 00:59:02.872974 CA_P2S_RATIO = 8
2156 00:59:02.873034 DQ_CA_OPEN = 0
2157 00:59:02.873110 DQ_SEMI_OPEN = 0
2158 00:59:02.873188 CA_SEMI_OPEN = 0
2159 00:59:02.873264 CA_FULL_RATE = 0
2160 00:59:02.873340 DQ_CKDIV4_EN = 0
2161 00:59:02.873416 CA_CKDIV4_EN = 0
2162 00:59:02.873472 CA_PREDIV_EN = 0
2163 00:59:02.873546 PH8_DLY = 17
2164 00:59:02.873622 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 00:59:02.873696 DQ_AAMCK_DIV = 4
2166 00:59:02.873747 CA_AAMCK_DIV = 4
2167 00:59:02.873795 CA_ADMCK_DIV = 4
2168 00:59:02.873843 DQ_TRACK_CA_EN = 0
2169 00:59:02.873891 CA_PICK = 1200
2170 00:59:02.873942 CA_MCKIO = 1200
2171 00:59:02.873993 MCKIO_SEMI = 0
2172 00:59:02.874042 PLL_FREQ = 2366
2173 00:59:02.874090 DQ_UI_PI_RATIO = 32
2174 00:59:02.874138 CA_UI_PI_RATIO = 0
2175 00:59:02.874189 ===================================
2176 00:59:02.874238 ===================================
2177 00:59:02.874287 memory_type:LPDDR4
2178 00:59:02.874335 GP_NUM : 10
2179 00:59:02.874383 SRAM_EN : 1
2180 00:59:02.874435 MD32_EN : 0
2181 00:59:02.874484 ===================================
2182 00:59:02.874535 [ANA_INIT] >>>>>>>>>>>>>>
2183 00:59:02.874583 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 00:59:02.874633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 00:59:02.874686 ===================================
2186 00:59:02.874736 data_rate = 2400,PCW = 0X5b00
2187 00:59:02.874785 ===================================
2188 00:59:02.874833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 00:59:02.874882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 00:59:02.874935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 00:59:02.874988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 00:59:02.875066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 00:59:02.875143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 00:59:02.875222 [ANA_INIT] flow start
2195 00:59:02.875298 [ANA_INIT] PLL >>>>>>>>
2196 00:59:02.875374 [ANA_INIT] PLL <<<<<<<<
2197 00:59:02.875452 [ANA_INIT] MIDPI >>>>>>>>
2198 00:59:02.875531 [ANA_INIT] MIDPI <<<<<<<<
2199 00:59:02.875607 [ANA_INIT] DLL >>>>>>>>
2200 00:59:02.875685 [ANA_INIT] DLL <<<<<<<<
2201 00:59:02.875761 [ANA_INIT] flow end
2202 00:59:02.875841 ============ LP4 DIFF to SE enter ============
2203 00:59:02.875931 ============ LP4 DIFF to SE exit ============
2204 00:59:02.876011 [ANA_INIT] <<<<<<<<<<<<<
2205 00:59:02.876089 [Flow] Enable top DCM control >>>>>
2206 00:59:02.876168 [Flow] Enable top DCM control <<<<<
2207 00:59:02.876245 Enable DLL master slave shuffle
2208 00:59:02.876323 ==============================================================
2209 00:59:02.876401 Gating Mode config
2210 00:59:02.876480 ==============================================================
2211 00:59:02.876557 Config description:
2212 00:59:02.876636 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 00:59:02.876743 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 00:59:02.876988 SELPH_MODE 0: By rank 1: By Phase
2215 00:59:02.877102 ==============================================================
2216 00:59:02.877215 GAT_TRACK_EN = 1
2217 00:59:02.877325 RX_GATING_MODE = 2
2218 00:59:02.877439 RX_GATING_TRACK_MODE = 2
2219 00:59:02.877582 SELPH_MODE = 1
2220 00:59:02.877692 PICG_EARLY_EN = 1
2221 00:59:02.877801 VALID_LAT_VALUE = 1
2222 00:59:02.877912 ==============================================================
2223 00:59:02.878023 Enter into Gating configuration >>>>
2224 00:59:02.878133 Exit from Gating configuration <<<<
2225 00:59:02.878232 Enter into DVFS_PRE_config >>>>>
2226 00:59:02.878288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 00:59:02.878341 Exit from DVFS_PRE_config <<<<<
2228 00:59:02.878395 Enter into PICG configuration >>>>
2229 00:59:02.878448 Exit from PICG configuration <<<<
2230 00:59:02.878497 [RX_INPUT] configuration >>>>>
2231 00:59:02.878546 [RX_INPUT] configuration <<<<<
2232 00:59:02.878594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 00:59:02.878647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 00:59:02.878697 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 00:59:02.878747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 00:59:02.878796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 00:59:02.878846 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 00:59:02.878899 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 00:59:02.878974 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 00:59:02.879051 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 00:59:02.879131 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 00:59:02.879208 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 00:59:02.879295 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 00:59:02.879380 ===================================
2245 00:59:02.879459 LPDDR4 DRAM CONFIGURATION
2246 00:59:02.879536 ===================================
2247 00:59:02.879615 EX_ROW_EN[0] = 0x0
2248 00:59:02.879692 EX_ROW_EN[1] = 0x0
2249 00:59:02.879768 LP4Y_EN = 0x0
2250 00:59:02.879846 WORK_FSP = 0x0
2251 00:59:02.879924 WL = 0x4
2252 00:59:02.880000 RL = 0x4
2253 00:59:02.880075 BL = 0x2
2254 00:59:02.880153 RPST = 0x0
2255 00:59:02.880229 RD_PRE = 0x0
2256 00:59:02.880305 WR_PRE = 0x1
2257 00:59:02.880382 WR_PST = 0x0
2258 00:59:02.880460 DBI_WR = 0x0
2259 00:59:02.880536 DBI_RD = 0x0
2260 00:59:02.880614 OTF = 0x1
2261 00:59:02.880736 ===================================
2262 00:59:02.880845 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 00:59:02.880930 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 00:59:02.880979 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 00:59:02.881029 ===================================
2266 00:59:02.881080 LPDDR4 DRAM CONFIGURATION
2267 00:59:02.881158 ===================================
2268 00:59:02.881234 EX_ROW_EN[0] = 0x10
2269 00:59:02.881311 EX_ROW_EN[1] = 0x0
2270 00:59:02.881391 LP4Y_EN = 0x0
2271 00:59:02.881467 WORK_FSP = 0x0
2272 00:59:02.881587 WL = 0x4
2273 00:59:02.881709 RL = 0x4
2274 00:59:02.881804 BL = 0x2
2275 00:59:02.881883 RPST = 0x0
2276 00:59:02.881960 RD_PRE = 0x0
2277 00:59:02.882036 WR_PRE = 0x1
2278 00:59:02.882114 WR_PST = 0x0
2279 00:59:02.882190 DBI_WR = 0x0
2280 00:59:02.882266 DBI_RD = 0x0
2281 00:59:02.882354 OTF = 0x1
2282 00:59:02.882435 ===================================
2283 00:59:02.882514 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 00:59:02.882593 ==
2285 00:59:02.882671 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 00:59:02.882748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 00:59:02.882827 ==
2288 00:59:02.882905 [Duty_Offset_Calibration]
2289 00:59:02.882982 B0:2 B1:0 CA:3
2290 00:59:02.883058
2291 00:59:02.883136 [DutyScan_Calibration_Flow] k_type=0
2292 00:59:02.883212
2293 00:59:02.883287 ==CLK 0==
2294 00:59:02.883366 Final CLK duty delay cell = 0
2295 00:59:02.883444 [0] MAX Duty = 5062%(X100), DQS PI = 20
2296 00:59:02.883557 [0] MIN Duty = 4906%(X100), DQS PI = 54
2297 00:59:02.883613 [0] AVG Duty = 4984%(X100)
2298 00:59:02.883662
2299 00:59:02.883710 CH0 CLK Duty spec in!! Max-Min= 156%
2300 00:59:02.883759 [DutyScan_Calibration_Flow] ====Done====
2301 00:59:02.883808
2302 00:59:02.883859 [DutyScan_Calibration_Flow] k_type=1
2303 00:59:02.883910
2304 00:59:02.883958 ==DQS 0 ==
2305 00:59:02.884006 Final DQS duty delay cell = 0
2306 00:59:02.884054 [0] MAX Duty = 5031%(X100), DQS PI = 10
2307 00:59:02.884107 [0] MIN Duty = 4907%(X100), DQS PI = 2
2308 00:59:02.884155 [0] AVG Duty = 4969%(X100)
2309 00:59:02.884203
2310 00:59:02.884251 ==DQS 1 ==
2311 00:59:02.884299 Final DQS duty delay cell = -4
2312 00:59:02.884351 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2313 00:59:02.884403 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2314 00:59:02.884451 [-4] AVG Duty = 4922%(X100)
2315 00:59:02.884499
2316 00:59:02.884546 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2317 00:59:02.884623
2318 00:59:02.884690 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2319 00:59:02.884740 [DutyScan_Calibration_Flow] ====Done====
2320 00:59:02.884812
2321 00:59:02.884879 [DutyScan_Calibration_Flow] k_type=3
2322 00:59:02.884929
2323 00:59:02.884978 ==DQM 0 ==
2324 00:59:02.885026 Final DQM duty delay cell = 0
2325 00:59:02.885074 [0] MAX Duty = 5124%(X100), DQS PI = 12
2326 00:59:02.885123 [0] MIN Duty = 4876%(X100), DQS PI = 0
2327 00:59:02.885176 [0] AVG Duty = 5000%(X100)
2328 00:59:02.885224
2329 00:59:02.885271 ==DQM 1 ==
2330 00:59:02.885319 Final DQM duty delay cell = 4
2331 00:59:02.885368 [4] MAX Duty = 5093%(X100), DQS PI = 48
2332 00:59:02.885415 [4] MIN Duty = 5000%(X100), DQS PI = 10
2333 00:59:02.885469 [4] AVG Duty = 5046%(X100)
2334 00:59:02.885520
2335 00:59:02.885569 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2336 00:59:02.885618
2337 00:59:02.885665 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2338 00:59:02.885745 [DutyScan_Calibration_Flow] ====Done====
2339 00:59:02.885796
2340 00:59:02.885845 [DutyScan_Calibration_Flow] k_type=2
2341 00:59:02.885892
2342 00:59:02.885939 ==DQ 0 ==
2343 00:59:02.885988 Final DQ duty delay cell = -4
2344 00:59:02.886040 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2345 00:59:02.886288 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2346 00:59:02.886345 [-4] AVG Duty = 4953%(X100)
2347 00:59:02.886395
2348 00:59:02.886443 ==DQ 1 ==
2349 00:59:02.886492 Final DQ duty delay cell = -4
2350 00:59:02.886540 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2351 00:59:02.886593 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2352 00:59:02.886645 [-4] AVG Duty = 4938%(X100)
2353 00:59:02.886695
2354 00:59:02.886743 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2355 00:59:02.886792
2356 00:59:02.886842 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2357 00:59:02.886891 [DutyScan_Calibration_Flow] ====Done====
2358 00:59:02.886939 ==
2359 00:59:02.886987 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 00:59:02.887035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 00:59:02.887086 ==
2362 00:59:02.887138 [Duty_Offset_Calibration]
2363 00:59:02.887214 B0:1 B1:-2 CA:0
2364 00:59:02.887289
2365 00:59:02.887367 [DutyScan_Calibration_Flow] k_type=0
2366 00:59:02.887443
2367 00:59:02.887542 ==CLK 0==
2368 00:59:02.887672 Final CLK duty delay cell = 0
2369 00:59:02.887779 [0] MAX Duty = 5031%(X100), DQS PI = 20
2370 00:59:02.887857 [0] MIN Duty = 4844%(X100), DQS PI = 58
2371 00:59:02.887933 [0] AVG Duty = 4937%(X100)
2372 00:59:02.888009
2373 00:59:02.888086 CH1 CLK Duty spec in!! Max-Min= 187%
2374 00:59:02.888164 [DutyScan_Calibration_Flow] ====Done====
2375 00:59:02.888243
2376 00:59:02.888323 [DutyScan_Calibration_Flow] k_type=1
2377 00:59:02.888400
2378 00:59:02.888475 ==DQS 0 ==
2379 00:59:02.888552 Final DQS duty delay cell = -4
2380 00:59:02.888634 [-4] MAX Duty = 4969%(X100), DQS PI = 16
2381 00:59:02.888757 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2382 00:59:02.888834 [-4] AVG Duty = 4922%(X100)
2383 00:59:02.888909
2384 00:59:02.888973 ==DQS 1 ==
2385 00:59:02.889048 Final DQS duty delay cell = 0
2386 00:59:02.889099 [0] MAX Duty = 5062%(X100), DQS PI = 0
2387 00:59:02.889154 [0] MIN Duty = 4875%(X100), DQS PI = 26
2388 00:59:02.889203 [0] AVG Duty = 4968%(X100)
2389 00:59:02.889251
2390 00:59:02.889302 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2391 00:59:02.889351
2392 00:59:02.889399 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2393 00:59:02.889447 [DutyScan_Calibration_Flow] ====Done====
2394 00:59:02.889543
2395 00:59:02.889642 [DutyScan_Calibration_Flow] k_type=3
2396 00:59:02.889741
2397 00:59:02.889820 ==DQM 0 ==
2398 00:59:02.889899 Final DQM duty delay cell = 0
2399 00:59:02.889976 [0] MAX Duty = 5000%(X100), DQS PI = 22
2400 00:59:02.890052 [0] MIN Duty = 4876%(X100), DQS PI = 4
2401 00:59:02.890128 [0] AVG Duty = 4938%(X100)
2402 00:59:02.890206
2403 00:59:02.890281 ==DQM 1 ==
2404 00:59:02.890357 Final DQM duty delay cell = 0
2405 00:59:02.890436 [0] MAX Duty = 5031%(X100), DQS PI = 36
2406 00:59:02.890512 [0] MIN Duty = 4907%(X100), DQS PI = 2
2407 00:59:02.890587 [0] AVG Duty = 4969%(X100)
2408 00:59:02.890663
2409 00:59:02.890738 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2410 00:59:02.890813
2411 00:59:02.890890 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2412 00:59:02.890966 [DutyScan_Calibration_Flow] ====Done====
2413 00:59:02.891041
2414 00:59:02.891116 [DutyScan_Calibration_Flow] k_type=2
2415 00:59:02.891192
2416 00:59:02.891267 ==DQ 0 ==
2417 00:59:02.891342 Final DQ duty delay cell = 0
2418 00:59:02.891418 [0] MAX Duty = 5062%(X100), DQS PI = 12
2419 00:59:02.891495 [0] MIN Duty = 4938%(X100), DQS PI = 44
2420 00:59:02.891570 [0] AVG Duty = 5000%(X100)
2421 00:59:02.891645
2422 00:59:02.891721 ==DQ 1 ==
2423 00:59:02.891797 Final DQ duty delay cell = 0
2424 00:59:02.891873 [0] MAX Duty = 5125%(X100), DQS PI = 36
2425 00:59:02.891948 [0] MIN Duty = 4969%(X100), DQS PI = 26
2426 00:59:02.892025 [0] AVG Duty = 5047%(X100)
2427 00:59:02.892103
2428 00:59:02.892190 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2429 00:59:02.892266
2430 00:59:02.892345 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2431 00:59:02.892421 [DutyScan_Calibration_Flow] ====Done====
2432 00:59:02.892496 nWR fixed to 30
2433 00:59:02.892574 [ModeRegInit_LP4] CH0 RK0
2434 00:59:02.892673 [ModeRegInit_LP4] CH0 RK1
2435 00:59:02.892738 [ModeRegInit_LP4] CH1 RK0
2436 00:59:02.892787 [ModeRegInit_LP4] CH1 RK1
2437 00:59:02.892835 match AC timing 7
2438 00:59:02.892912 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 00:59:02.892988 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 00:59:02.893064 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 00:59:02.893142 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 00:59:02.893219 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 00:59:02.893294 ==
2444 00:59:02.893370 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 00:59:02.893448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 00:59:02.893524 ==
2447 00:59:02.893610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 00:59:02.893689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 00:59:02.893766 [CA 0] Center 40 (10~71) winsize 62
2450 00:59:02.893842 [CA 1] Center 39 (9~70) winsize 62
2451 00:59:02.893919 [CA 2] Center 36 (6~66) winsize 61
2452 00:59:02.893997 [CA 3] Center 35 (5~66) winsize 62
2453 00:59:02.894073 [CA 4] Center 34 (4~65) winsize 62
2454 00:59:02.894148 [CA 5] Center 33 (3~63) winsize 61
2455 00:59:02.894224
2456 00:59:02.894301 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2457 00:59:02.894377
2458 00:59:02.894452 [CATrainingPosCal] consider 1 rank data
2459 00:59:02.894530 u2DelayCellTimex100 = 270/100 ps
2460 00:59:02.894606 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2461 00:59:02.894683 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2462 00:59:02.894759 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2463 00:59:02.894837 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2464 00:59:02.894912 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2465 00:59:02.894988 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2466 00:59:02.895063
2467 00:59:02.895141 CA PerBit enable=1, Macro0, CA PI delay=33
2468 00:59:02.895216
2469 00:59:02.895291 [CBTSetCACLKResult] CA Dly = 33
2470 00:59:02.895368 CS Dly: 7 (0~38)
2471 00:59:02.895443 ==
2472 00:59:02.895519 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 00:59:02.895611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 00:59:02.895702 ==
2475 00:59:02.895780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 00:59:02.895858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2477 00:59:02.895936 [CA 0] Center 40 (10~70) winsize 61
2478 00:59:02.896011 [CA 1] Center 39 (9~70) winsize 62
2479 00:59:02.896087 [CA 2] Center 35 (5~66) winsize 62
2480 00:59:02.896166 [CA 3] Center 35 (5~66) winsize 62
2481 00:59:02.896242 [CA 4] Center 34 (4~65) winsize 62
2482 00:59:02.896318 [CA 5] Center 33 (3~63) winsize 61
2483 00:59:02.896393
2484 00:59:02.896470 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2485 00:59:02.896546
2486 00:59:02.896621 [CATrainingPosCal] consider 2 rank data
2487 00:59:02.896722 u2DelayCellTimex100 = 270/100 ps
2488 00:59:02.896773 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2489 00:59:02.897015 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2490 00:59:02.897126 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2491 00:59:02.897242 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 00:59:02.897357 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2493 00:59:02.897469 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2494 00:59:02.897576
2495 00:59:02.897685 CA PerBit enable=1, Macro0, CA PI delay=33
2496 00:59:02.897794
2497 00:59:02.897902 [CBTSetCACLKResult] CA Dly = 33
2498 00:59:02.898010 CS Dly: 7 (0~39)
2499 00:59:02.898118
2500 00:59:02.898225 ----->DramcWriteLeveling(PI) begin...
2501 00:59:02.898305 ==
2502 00:59:02.898357 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 00:59:02.898406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 00:59:02.898459 ==
2505 00:59:02.898507 Write leveling (Byte 0): 32 => 32
2506 00:59:02.898555 Write leveling (Byte 1): 30 => 30
2507 00:59:02.898604 DramcWriteLeveling(PI) end<-----
2508 00:59:02.898651
2509 00:59:02.898701 ==
2510 00:59:02.898749 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 00:59:02.898797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 00:59:02.898845 ==
2513 00:59:02.898893 [Gating] SW mode calibration
2514 00:59:02.898946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 00:59:02.898995 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 00:59:02.899057 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2517 00:59:02.899117 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2518 00:59:02.899169 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 00:59:02.899218 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 00:59:02.899266 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 00:59:02.899315 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 00:59:02.899364 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 00:59:02.899415 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2524 00:59:02.899464 1 0 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
2525 00:59:02.899512 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2526 00:59:02.899560 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 00:59:02.899607 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 00:59:02.899658 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 00:59:02.899708 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 00:59:02.899756 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 00:59:02.899804 1 0 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2532 00:59:02.899852 1 1 0 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2533 00:59:02.899902 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2534 00:59:02.899951 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 00:59:02.899999 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 00:59:02.900047 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 00:59:02.900096 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 00:59:02.900145 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 00:59:02.900196 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 00:59:02.900245 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 00:59:02.900293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:59:02.900341 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:59:02.900390 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:59:02.900437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:59:02.900515 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:59:02.900591 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:59:02.900691 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:59:02.900760 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:59:02.900813 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:59:02.900866 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:59:02.900918 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:59:02.900971 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:59:02.901020 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:59:02.901068 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:59:02.901117 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 00:59:02.901173 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2557 00:59:02.901222 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 00:59:02.901270 Total UI for P1: 0, mck2ui 16
2559 00:59:02.901322 best dqsien dly found for B0: ( 1, 3, 30)
2560 00:59:02.901375 Total UI for P1: 0, mck2ui 16
2561 00:59:02.901424 best dqsien dly found for B1: ( 1, 4, 0)
2562 00:59:02.901472 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2563 00:59:02.901525 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2564 00:59:02.901574
2565 00:59:02.901622 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2566 00:59:02.901670 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2567 00:59:02.901721 [Gating] SW calibration Done
2568 00:59:02.901769 ==
2569 00:59:02.901817 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 00:59:02.901869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 00:59:02.901918 ==
2572 00:59:02.901966 RX Vref Scan: 0
2573 00:59:02.902014
2574 00:59:02.902077 RX Vref 0 -> 0, step: 1
2575 00:59:02.902138
2576 00:59:02.902186 RX Delay -40 -> 252, step: 8
2577 00:59:02.902235 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2578 00:59:02.902297 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2579 00:59:02.902363 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2580 00:59:02.902411 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2581 00:59:02.902459 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2582 00:59:02.902507 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2583 00:59:02.902555 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2584 00:59:02.902606 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2585 00:59:02.902654 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2586 00:59:02.902702 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2587 00:59:02.902749 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2588 00:59:02.902798 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2589 00:59:02.902849 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2590 00:59:02.903088 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2591 00:59:02.903146 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2592 00:59:02.903195 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2593 00:59:02.903244 ==
2594 00:59:02.903293 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 00:59:02.903346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 00:59:02.903423 ==
2597 00:59:02.903498 DQS Delay:
2598 00:59:02.903575 DQS0 = 0, DQS1 = 0
2599 00:59:02.903651 DQM Delay:
2600 00:59:02.903727 DQM0 = 112, DQM1 = 103
2601 00:59:02.903802 DQ Delay:
2602 00:59:02.903881 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2603 00:59:02.903957 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2604 00:59:02.904033 DQ8 =95, DQ9 =87, DQ10 =107, DQ11 =99
2605 00:59:02.904110 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2606 00:59:02.904187
2607 00:59:02.904262
2608 00:59:02.904337 ==
2609 00:59:02.904415 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 00:59:02.904492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 00:59:02.904568 ==
2612 00:59:02.904649
2613 00:59:02.904737
2614 00:59:02.904786 TX Vref Scan disable
2615 00:59:02.904835 == TX Byte 0 ==
2616 00:59:02.904884 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2617 00:59:02.904933 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2618 00:59:02.904986 == TX Byte 1 ==
2619 00:59:02.905035 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2620 00:59:02.905091 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2621 00:59:02.905157 ==
2622 00:59:02.905207 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 00:59:02.905260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 00:59:02.905310 ==
2625 00:59:02.905358 TX Vref=22, minBit 12, minWin=25, winSum=420
2626 00:59:02.905407 TX Vref=24, minBit 11, minWin=25, winSum=422
2627 00:59:02.905456 TX Vref=26, minBit 1, minWin=26, winSum=427
2628 00:59:02.905504 TX Vref=28, minBit 12, minWin=26, winSum=436
2629 00:59:02.905557 TX Vref=30, minBit 8, minWin=26, winSum=436
2630 00:59:02.905606 TX Vref=32, minBit 10, minWin=25, winSum=430
2631 00:59:02.905654 [TxChooseVref] Worse bit 12, Min win 26, Win sum 436, Final Vref 28
2632 00:59:02.905702
2633 00:59:02.905751 Final TX Range 1 Vref 28
2634 00:59:02.905802
2635 00:59:02.905850 ==
2636 00:59:02.905897 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 00:59:02.905945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 00:59:02.905994 ==
2639 00:59:02.906041
2640 00:59:02.906091
2641 00:59:02.906139 TX Vref Scan disable
2642 00:59:02.906188 == TX Byte 0 ==
2643 00:59:02.906237 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2644 00:59:02.906286 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2645 00:59:02.906334 == TX Byte 1 ==
2646 00:59:02.906386 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2647 00:59:02.906436 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2648 00:59:02.906485
2649 00:59:02.906532 [DATLAT]
2650 00:59:02.906580 Freq=1200, CH0 RK0
2651 00:59:02.906631
2652 00:59:02.906679 DATLAT Default: 0xd
2653 00:59:02.906728 0, 0xFFFF, sum = 0
2654 00:59:02.906777 1, 0xFFFF, sum = 0
2655 00:59:02.906827 2, 0xFFFF, sum = 0
2656 00:59:02.906876 3, 0xFFFF, sum = 0
2657 00:59:02.906928 4, 0xFFFF, sum = 0
2658 00:59:02.906977 5, 0xFFFF, sum = 0
2659 00:59:02.907025 6, 0xFFFF, sum = 0
2660 00:59:02.907074 7, 0xFFFF, sum = 0
2661 00:59:02.907124 8, 0xFFFF, sum = 0
2662 00:59:02.907179 9, 0xFFFF, sum = 0
2663 00:59:02.907257 10, 0xFFFF, sum = 0
2664 00:59:02.907334 11, 0xFFFF, sum = 0
2665 00:59:02.907414 12, 0x0, sum = 1
2666 00:59:02.907491 13, 0x0, sum = 2
2667 00:59:02.907568 14, 0x0, sum = 3
2668 00:59:02.907646 15, 0x0, sum = 4
2669 00:59:02.907725 best_step = 13
2670 00:59:02.907799
2671 00:59:02.907874 ==
2672 00:59:02.907951 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 00:59:02.908028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 00:59:02.908103 ==
2675 00:59:02.908180 RX Vref Scan: 1
2676 00:59:02.908256
2677 00:59:02.908331 Set Vref Range= 32 -> 127
2678 00:59:02.908406
2679 00:59:02.908486 RX Vref 32 -> 127, step: 1
2680 00:59:02.908574
2681 00:59:02.908678 RX Delay -37 -> 252, step: 4
2682 00:59:02.908759
2683 00:59:02.908809 Set Vref, RX VrefLevel [Byte0]: 32
2684 00:59:02.908858 [Byte1]: 32
2685 00:59:02.908906
2686 00:59:02.908954 Set Vref, RX VrefLevel [Byte0]: 33
2687 00:59:02.909003 [Byte1]: 33
2688 00:59:02.909055
2689 00:59:02.909104 Set Vref, RX VrefLevel [Byte0]: 34
2690 00:59:02.909152 [Byte1]: 34
2691 00:59:02.909200
2692 00:59:02.909248 Set Vref, RX VrefLevel [Byte0]: 35
2693 00:59:02.909296 [Byte1]: 35
2694 00:59:02.909373
2695 00:59:02.909449 Set Vref, RX VrefLevel [Byte0]: 36
2696 00:59:02.909525 [Byte1]: 36
2697 00:59:02.909602
2698 00:59:02.909678 Set Vref, RX VrefLevel [Byte0]: 37
2699 00:59:02.909742 [Byte1]: 37
2700 00:59:02.909793
2701 00:59:02.909841 Set Vref, RX VrefLevel [Byte0]: 38
2702 00:59:02.909894 [Byte1]: 38
2703 00:59:02.909943
2704 00:59:02.909991 Set Vref, RX VrefLevel [Byte0]: 39
2705 00:59:02.910039 [Byte1]: 39
2706 00:59:02.910088
2707 00:59:02.910136 Set Vref, RX VrefLevel [Byte0]: 40
2708 00:59:02.910188 [Byte1]: 40
2709 00:59:02.910236
2710 00:59:02.910283 Set Vref, RX VrefLevel [Byte0]: 41
2711 00:59:02.910332 [Byte1]: 41
2712 00:59:02.910380
2713 00:59:02.910431 Set Vref, RX VrefLevel [Byte0]: 42
2714 00:59:02.910480 [Byte1]: 42
2715 00:59:02.910528
2716 00:59:02.910576 Set Vref, RX VrefLevel [Byte0]: 43
2717 00:59:02.910624 [Byte1]: 43
2718 00:59:02.910673
2719 00:59:02.910724 Set Vref, RX VrefLevel [Byte0]: 44
2720 00:59:02.910772 [Byte1]: 44
2721 00:59:02.910820
2722 00:59:02.910867 Set Vref, RX VrefLevel [Byte0]: 45
2723 00:59:02.910915 [Byte1]: 45
2724 00:59:02.910965
2725 00:59:02.911014 Set Vref, RX VrefLevel [Byte0]: 46
2726 00:59:02.911062 [Byte1]: 46
2727 00:59:02.911110
2728 00:59:02.911157 Set Vref, RX VrefLevel [Byte0]: 47
2729 00:59:02.911208 [Byte1]: 47
2730 00:59:02.911257
2731 00:59:02.911306 Set Vref, RX VrefLevel [Byte0]: 48
2732 00:59:02.911354 [Byte1]: 48
2733 00:59:02.911402
2734 00:59:02.911452 Set Vref, RX VrefLevel [Byte0]: 49
2735 00:59:02.911501 [Byte1]: 49
2736 00:59:02.911549
2737 00:59:02.911597 Set Vref, RX VrefLevel [Byte0]: 50
2738 00:59:02.911645 [Byte1]: 50
2739 00:59:02.911693
2740 00:59:02.911768 Set Vref, RX VrefLevel [Byte0]: 51
2741 00:59:02.911820 [Byte1]: 51
2742 00:59:02.911871
2743 00:59:02.911919 Set Vref, RX VrefLevel [Byte0]: 52
2744 00:59:02.911967 [Byte1]: 52
2745 00:59:02.912033
2746 00:59:02.912109 Set Vref, RX VrefLevel [Byte0]: 53
2747 00:59:02.912185 [Byte1]: 53
2748 00:59:02.912261
2749 00:59:02.912337 Set Vref, RX VrefLevel [Byte0]: 54
2750 00:59:02.912413 [Byte1]: 54
2751 00:59:02.912487
2752 00:59:02.912565 Set Vref, RX VrefLevel [Byte0]: 55
2753 00:59:02.912641 [Byte1]: 55
2754 00:59:02.912756
2755 00:59:02.912831 Set Vref, RX VrefLevel [Byte0]: 56
2756 00:59:02.913076 [Byte1]: 56
2757 00:59:02.913187
2758 00:59:02.913295 Set Vref, RX VrefLevel [Byte0]: 57
2759 00:59:02.913404 [Byte1]: 57
2760 00:59:02.913512
2761 00:59:02.913619 Set Vref, RX VrefLevel [Byte0]: 58
2762 00:59:02.913726 [Byte1]: 58
2763 00:59:02.913889
2764 00:59:02.914039 Set Vref, RX VrefLevel [Byte0]: 59
2765 00:59:02.914146 [Byte1]: 59
2766 00:59:02.914252
2767 00:59:02.914359 Set Vref, RX VrefLevel [Byte0]: 60
2768 00:59:02.914417 [Byte1]: 60
2769 00:59:02.914467
2770 00:59:02.914516 Set Vref, RX VrefLevel [Byte0]: 61
2771 00:59:02.914566 [Byte1]: 61
2772 00:59:02.914616
2773 00:59:02.914665 Set Vref, RX VrefLevel [Byte0]: 62
2774 00:59:02.914714 [Byte1]: 62
2775 00:59:02.914762
2776 00:59:02.914810 Set Vref, RX VrefLevel [Byte0]: 63
2777 00:59:02.914858 [Byte1]: 63
2778 00:59:02.914910
2779 00:59:02.914958 Set Vref, RX VrefLevel [Byte0]: 64
2780 00:59:02.915005 [Byte1]: 64
2781 00:59:02.915059
2782 00:59:02.915132 Set Vref, RX VrefLevel [Byte0]: 65
2783 00:59:02.915183 [Byte1]: 65
2784 00:59:02.915232
2785 00:59:02.915281 Set Vref, RX VrefLevel [Byte0]: 66
2786 00:59:02.915329 [Byte1]: 66
2787 00:59:02.915382
2788 00:59:02.915431 Set Vref, RX VrefLevel [Byte0]: 67
2789 00:59:02.915479 [Byte1]: 67
2790 00:59:02.915527
2791 00:59:02.915575 Set Vref, RX VrefLevel [Byte0]: 68
2792 00:59:02.915628 [Byte1]: 68
2793 00:59:02.915675
2794 00:59:02.915723 Set Vref, RX VrefLevel [Byte0]: 69
2795 00:59:02.915772 [Byte1]: 69
2796 00:59:02.915820
2797 00:59:02.915872 Set Vref, RX VrefLevel [Byte0]: 70
2798 00:59:02.915921 [Byte1]: 70
2799 00:59:02.915969
2800 00:59:02.916016 Set Vref, RX VrefLevel [Byte0]: 71
2801 00:59:02.916064 [Byte1]: 71
2802 00:59:02.916116
2803 00:59:02.916164 Set Vref, RX VrefLevel [Byte0]: 72
2804 00:59:02.916212 [Byte1]: 72
2805 00:59:02.916260
2806 00:59:02.916308 Set Vref, RX VrefLevel [Byte0]: 73
2807 00:59:02.916360 [Byte1]: 73
2808 00:59:02.916408
2809 00:59:02.916455 Set Vref, RX VrefLevel [Byte0]: 74
2810 00:59:02.916503 [Byte1]: 74
2811 00:59:02.916551
2812 00:59:02.916619 Set Vref, RX VrefLevel [Byte0]: 75
2813 00:59:02.916721 [Byte1]: 75
2814 00:59:02.916772
2815 00:59:02.916821 Final RX Vref Byte 0 = 64 to rank0
2816 00:59:02.916883 Final RX Vref Byte 1 = 49 to rank0
2817 00:59:02.916959 Final RX Vref Byte 0 = 64 to rank1
2818 00:59:02.917036 Final RX Vref Byte 1 = 49 to rank1==
2819 00:59:02.917112 Dram Type= 6, Freq= 0, CH_0, rank 0
2820 00:59:02.917190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 00:59:02.917266 ==
2822 00:59:02.917342 DQS Delay:
2823 00:59:02.917419 DQS0 = 0, DQS1 = 0
2824 00:59:02.917494 DQM Delay:
2825 00:59:02.917569 DQM0 = 112, DQM1 = 100
2826 00:59:02.917645 DQ Delay:
2827 00:59:02.917703 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =106
2828 00:59:02.917752 DQ4 =114, DQ5 =104, DQ6 =120, DQ7 =120
2829 00:59:02.917801 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =92
2830 00:59:02.917849 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2831 00:59:02.917897
2832 00:59:02.917947
2833 00:59:02.917996 [DQSOSCAuto] RK0, (LSB)MR18= 0x201, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
2834 00:59:02.918054 CH0 RK0: MR19=404, MR18=201
2835 00:59:02.918117 CH0_RK0: MR19=0x404, MR18=0x201, DQSOSC=409, MR23=63, INC=39, DEC=26
2836 00:59:02.918166
2837 00:59:02.918214 ----->DramcWriteLeveling(PI) begin...
2838 00:59:02.918268 ==
2839 00:59:02.918317 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 00:59:02.918365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 00:59:02.918413 ==
2842 00:59:02.918460 Write leveling (Byte 0): 32 => 32
2843 00:59:02.918508 Write leveling (Byte 1): 30 => 30
2844 00:59:02.918585 DramcWriteLeveling(PI) end<-----
2845 00:59:02.918660
2846 00:59:02.918734 ==
2847 00:59:02.918812 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 00:59:02.918888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 00:59:02.918963 ==
2850 00:59:02.919038 [Gating] SW mode calibration
2851 00:59:02.919117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2852 00:59:02.919195 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2853 00:59:02.919271 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2854 00:59:02.919349 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 00:59:02.919425 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 00:59:02.919501 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 00:59:02.919579 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 00:59:02.919656 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 00:59:02.919732 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
2860 00:59:02.919808 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2861 00:59:02.919871 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2862 00:59:02.919921 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 00:59:02.919970 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 00:59:02.920020 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 00:59:02.920068 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 00:59:02.920118 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 00:59:02.920170 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2868 00:59:02.920219 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2869 00:59:02.920267 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
2870 00:59:02.920315 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 00:59:02.920372 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 00:59:02.920449 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 00:59:02.920525 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 00:59:02.920603 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 00:59:02.920686 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 00:59:02.920738 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2877 00:59:02.920787 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 00:59:02.920836 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 00:59:02.920888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:59:02.920937 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:59:02.921177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:59:02.921233 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:59:02.921283 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:59:02.921332 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:59:02.921381 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:59:02.921433 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:59:02.921482 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:59:02.921530 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:59:02.921603 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:59:02.921656 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:59:02.921705 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:59:02.921758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 00:59:02.921837 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2894 00:59:02.921886 Total UI for P1: 0, mck2ui 16
2895 00:59:02.921935 best dqsien dly found for B0: ( 1, 3, 28)
2896 00:59:02.921984 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 00:59:02.922035 Total UI for P1: 0, mck2ui 16
2898 00:59:02.922085 best dqsien dly found for B1: ( 1, 4, 0)
2899 00:59:02.922134 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2900 00:59:02.922183 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2901 00:59:02.922232
2902 00:59:02.922282 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2903 00:59:02.922332 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2904 00:59:02.922381 [Gating] SW calibration Done
2905 00:59:02.922429 ==
2906 00:59:02.922478 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 00:59:02.922527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 00:59:02.922578 ==
2909 00:59:02.922627 RX Vref Scan: 0
2910 00:59:02.922675
2911 00:59:02.922722 RX Vref 0 -> 0, step: 1
2912 00:59:02.922770
2913 00:59:02.922818 RX Delay -40 -> 252, step: 8
2914 00:59:02.922871 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2915 00:59:02.922920 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2916 00:59:02.922968 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2917 00:59:02.923015 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2918 00:59:02.923063 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2919 00:59:02.923111 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2920 00:59:02.923164 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2921 00:59:02.923212 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2922 00:59:02.923260 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2923 00:59:02.923308 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2924 00:59:02.923357 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2925 00:59:02.923405 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2926 00:59:02.923457 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2927 00:59:02.923506 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2928 00:59:02.923554 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2929 00:59:02.923602 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2930 00:59:02.923650 ==
2931 00:59:02.923697 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 00:59:02.923749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 00:59:02.923798 ==
2934 00:59:02.923846 DQS Delay:
2935 00:59:02.923894 DQS0 = 0, DQS1 = 0
2936 00:59:02.923972 DQM Delay:
2937 00:59:03.130642 DQM0 = 111, DQM1 = 101
2938 00:59:03.130772 DQ Delay:
2939 00:59:03.130862 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2940 00:59:03.130946 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2941 00:59:03.131028 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2942 00:59:03.131114 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =111
2943 00:59:03.131192
2944 00:59:03.131273
2945 00:59:03.131351 ==
2946 00:59:03.131430 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 00:59:03.131511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 00:59:03.131589 ==
2949 00:59:03.131668
2950 00:59:03.131747
2951 00:59:03.131824 TX Vref Scan disable
2952 00:59:03.131904 == TX Byte 0 ==
2953 00:59:03.131983 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2954 00:59:03.132065 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2955 00:59:03.132142 == TX Byte 1 ==
2956 00:59:03.132220 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2957 00:59:03.132300 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2958 00:59:03.132376 ==
2959 00:59:03.132454 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 00:59:03.132534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 00:59:03.132611 ==
2962 00:59:03.132719 TX Vref=22, minBit 5, minWin=26, winSum=427
2963 00:59:03.132773 TX Vref=24, minBit 5, minWin=26, winSum=430
2964 00:59:03.132843 TX Vref=26, minBit 8, minWin=26, winSum=437
2965 00:59:03.132899 TX Vref=28, minBit 0, minWin=27, winSum=439
2966 00:59:03.132952 TX Vref=30, minBit 10, minWin=26, winSum=441
2967 00:59:03.133011 TX Vref=32, minBit 8, minWin=26, winSum=438
2968 00:59:03.133064 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 28
2969 00:59:03.133117
2970 00:59:03.133174 Final TX Range 1 Vref 28
2971 00:59:03.133235
2972 00:59:03.133288 ==
2973 00:59:03.133340 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 00:59:03.133392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 00:59:03.133449 ==
2976 00:59:03.133507
2977 00:59:03.133559
2978 00:59:03.133610 TX Vref Scan disable
2979 00:59:03.133662 == TX Byte 0 ==
2980 00:59:03.133726 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2981 00:59:03.133811 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2982 00:59:03.133893 == TX Byte 1 ==
2983 00:59:03.133978 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2984 00:59:03.134063 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2985 00:59:03.134144
2986 00:59:03.134228 [DATLAT]
2987 00:59:03.134310 Freq=1200, CH0 RK1
2988 00:59:03.134393
2989 00:59:03.134478 DATLAT Default: 0xd
2990 00:59:03.134559 0, 0xFFFF, sum = 0
2991 00:59:03.134642 1, 0xFFFF, sum = 0
2992 00:59:03.134730 2, 0xFFFF, sum = 0
2993 00:59:03.134814 3, 0xFFFF, sum = 0
2994 00:59:03.134897 4, 0xFFFF, sum = 0
2995 00:59:03.134985 5, 0xFFFF, sum = 0
2996 00:59:03.135069 6, 0xFFFF, sum = 0
2997 00:59:03.135152 7, 0xFFFF, sum = 0
2998 00:59:03.135239 8, 0xFFFF, sum = 0
2999 00:59:03.135325 9, 0xFFFF, sum = 0
3000 00:59:03.135409 10, 0xFFFF, sum = 0
3001 00:59:03.135496 11, 0xFFFF, sum = 0
3002 00:59:03.135582 12, 0x0, sum = 1
3003 00:59:03.135667 13, 0x0, sum = 2
3004 00:59:03.135728 14, 0x0, sum = 3
3005 00:59:03.135782 15, 0x0, sum = 4
3006 00:59:03.135839 best_step = 13
3007 00:59:03.135921
3008 00:59:03.136006 ==
3009 00:59:03.136061 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 00:59:03.136114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 00:59:03.136172 ==
3012 00:59:03.136258 RX Vref Scan: 0
3013 00:59:03.136339
3014 00:59:03.136424 RX Vref 0 -> 0, step: 1
3015 00:59:03.136507
3016 00:59:03.136589 RX Delay -37 -> 252, step: 4
3017 00:59:03.136678 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3018 00:59:03.136945 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3019 00:59:03.137068 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3020 00:59:03.137187 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3021 00:59:03.137305 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3022 00:59:03.137422 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3023 00:59:03.137540 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3024 00:59:03.137658 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3025 00:59:03.137797 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3026 00:59:03.137926 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3027 00:59:03.138053 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3028 00:59:03.138179 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3029 00:59:03.138306 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3030 00:59:03.138379 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3031 00:59:03.138440 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3032 00:59:03.138504 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3033 00:59:03.138562 ==
3034 00:59:03.138619 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 00:59:03.138684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 00:59:03.138741 ==
3037 00:59:03.138801 DQS Delay:
3038 00:59:03.138858 DQS0 = 0, DQS1 = 0
3039 00:59:03.138949 DQM Delay:
3040 00:59:03.139038 DQM0 = 110, DQM1 = 100
3041 00:59:03.139101 DQ Delay:
3042 00:59:03.139182 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3043 00:59:03.139272 DQ4 =110, DQ5 =100, DQ6 =120, DQ7 =120
3044 00:59:03.139361 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3045 00:59:03.139455 DQ12 =108, DQ13 =106, DQ14 =114, DQ15 =108
3046 00:59:03.139544
3047 00:59:03.139632
3048 00:59:03.139697 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3049 00:59:03.139756 CH0 RK1: MR19=403, MR18=14FC
3050 00:59:03.139814 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3051 00:59:03.139881 [RxdqsGatingPostProcess] freq 1200
3052 00:59:03.139981 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3053 00:59:03.140082 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 00:59:03.140187 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 00:59:03.140278 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 00:59:03.140369 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 00:59:03.140462 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 00:59:03.140551 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 00:59:03.140647 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 00:59:03.140716 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 00:59:03.140773 Pre-setting of DQS Precalculation
3062 00:59:03.140830 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3063 00:59:03.140891 ==
3064 00:59:03.140957 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 00:59:03.141016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 00:59:03.141073 ==
3067 00:59:03.141130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3068 00:59:03.141198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3069 00:59:03.141256 [CA 0] Center 37 (8~67) winsize 60
3070 00:59:03.141313 [CA 1] Center 37 (7~68) winsize 62
3071 00:59:03.141369 [CA 2] Center 34 (4~64) winsize 61
3072 00:59:03.141435 [CA 3] Center 34 (4~64) winsize 61
3073 00:59:03.141494 [CA 4] Center 34 (4~64) winsize 61
3074 00:59:03.141550 [CA 5] Center 33 (3~63) winsize 61
3075 00:59:03.141606
3076 00:59:03.141671 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3077 00:59:03.141730
3078 00:59:03.141786 [CATrainingPosCal] consider 1 rank data
3079 00:59:03.141842 u2DelayCellTimex100 = 270/100 ps
3080 00:59:03.141906 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3081 00:59:03.141967 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3082 00:59:03.142023 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 00:59:03.142079 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 00:59:03.142143 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 00:59:03.142235 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3086 00:59:03.142322
3087 00:59:03.142414 CA PerBit enable=1, Macro0, CA PI delay=33
3088 00:59:03.142506
3089 00:59:03.142593 [CBTSetCACLKResult] CA Dly = 33
3090 00:59:03.142685 CS Dly: 6 (0~37)
3091 00:59:03.142774 ==
3092 00:59:03.142865 Dram Type= 6, Freq= 0, CH_1, rank 1
3093 00:59:03.142955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 00:59:03.143045 ==
3095 00:59:03.143139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 00:59:03.143230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3097 00:59:03.143320 [CA 0] Center 37 (8~67) winsize 60
3098 00:59:03.143413 [CA 1] Center 37 (7~68) winsize 62
3099 00:59:03.143501 [CA 2] Center 34 (4~65) winsize 62
3100 00:59:03.143591 [CA 3] Center 33 (3~64) winsize 62
3101 00:59:03.143683 [CA 4] Center 34 (4~64) winsize 61
3102 00:59:03.143771 [CA 5] Center 33 (3~64) winsize 62
3103 00:59:03.143861
3104 00:59:03.143952 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3105 00:59:03.144040
3106 00:59:03.144131 [CATrainingPosCal] consider 2 rank data
3107 00:59:03.144222 u2DelayCellTimex100 = 270/100 ps
3108 00:59:03.144310 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3109 00:59:03.144403 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3110 00:59:03.144494 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 00:59:03.144585 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 00:59:03.144682 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 00:59:03.144773 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3114 00:59:03.144866
3115 00:59:03.144954 CA PerBit enable=1, Macro0, CA PI delay=33
3116 00:59:03.145045
3117 00:59:03.145137 [CBTSetCACLKResult] CA Dly = 33
3118 00:59:03.145225 CS Dly: 7 (0~39)
3119 00:59:03.145314
3120 00:59:03.145405 ----->DramcWriteLeveling(PI) begin...
3121 00:59:03.145494 ==
3122 00:59:03.145586 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 00:59:03.145678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 00:59:03.145766 ==
3125 00:59:03.145858 Write leveling (Byte 0): 26 => 26
3126 00:59:03.145949 Write leveling (Byte 1): 30 => 30
3127 00:59:03.146037 DramcWriteLeveling(PI) end<-----
3128 00:59:03.146128
3129 00:59:03.146215 ==
3130 00:59:03.146308 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 00:59:03.146398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 00:59:03.146486 ==
3133 00:59:03.146567 [Gating] SW mode calibration
3134 00:59:03.146630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3135 00:59:03.146688 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3136 00:59:03.146745 0 15 0 | B1->B0 | 3232 3030 | 1 0 | (1 1) (0 0)
3137 00:59:03.147009 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 00:59:03.147108 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 00:59:03.147201 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 00:59:03.147292 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 00:59:03.147388 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 00:59:03.147481 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 00:59:03.147575 0 15 28 | B1->B0 | 2929 2a2a | 0 0 | (0 0) (0 1)
3144 00:59:03.147665 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3145 00:59:03.147752 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 00:59:03.147820 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 00:59:03.147879 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 00:59:03.147936 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 00:59:03.147993 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 00:59:03.148078 1 0 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
3151 00:59:03.148169 1 0 28 | B1->B0 | 4242 4040 | 0 0 | (0 0) (0 0)
3152 00:59:03.148258 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3153 00:59:03.148352 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 00:59:03.148442 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 00:59:03.148534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 00:59:03.148624 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 00:59:03.148703 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 00:59:03.148762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:59:03.148856 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 00:59:03.148945 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 00:59:03.149040 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:59:03.149130 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:59:03.149219 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:59:03.149313 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:59:03.149403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:59:03.149492 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:59:03.149587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:59:03.149676 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:59:03.149768 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:59:03.149859 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:59:03.149949 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:59:03.150042 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:59:03.150131 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:59:03.150222 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:59:03.150315 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3176 00:59:03.150403 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 00:59:03.150494 Total UI for P1: 0, mck2ui 16
3178 00:59:03.150586 best dqsien dly found for B0: ( 1, 3, 28)
3179 00:59:03.150675 Total UI for P1: 0, mck2ui 16
3180 00:59:03.150768 best dqsien dly found for B1: ( 1, 3, 28)
3181 00:59:03.150860 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3182 00:59:03.150949 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3183 00:59:03.151037
3184 00:59:03.151131 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3185 00:59:03.151221 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3186 00:59:03.151310 [Gating] SW calibration Done
3187 00:59:03.151399 ==
3188 00:59:03.151487 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 00:59:03.151579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 00:59:03.151668 ==
3191 00:59:03.151758 RX Vref Scan: 0
3192 00:59:03.151849
3193 00:59:03.151939 RX Vref 0 -> 0, step: 1
3194 00:59:03.152026
3195 00:59:03.152094 RX Delay -40 -> 252, step: 8
3196 00:59:03.152153 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3197 00:59:03.152211 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3198 00:59:03.152268 iDelay=208, Bit 2, Center 99 (24 ~ 175) 152
3199 00:59:03.152332 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3200 00:59:03.152391 iDelay=208, Bit 4, Center 107 (32 ~ 183) 152
3201 00:59:03.152452 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3202 00:59:03.152544 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3203 00:59:03.152635 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3204 00:59:03.152701 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3205 00:59:03.152762 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3206 00:59:03.152826 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3207 00:59:03.152885 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3208 00:59:03.152942 iDelay=208, Bit 12, Center 111 (40 ~ 183) 144
3209 00:59:03.152999 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
3210 00:59:03.153064 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3211 00:59:03.153125 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3212 00:59:03.153182 ==
3213 00:59:03.153238 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 00:59:03.153304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 00:59:03.153365 ==
3216 00:59:03.153423 DQS Delay:
3217 00:59:03.153478 DQS0 = 0, DQS1 = 0
3218 00:59:03.153540 DQM Delay:
3219 00:59:03.153598 DQM0 = 113, DQM1 = 105
3220 00:59:03.153655 DQ Delay:
3221 00:59:03.153714 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3222 00:59:03.153776 DQ4 =107, DQ5 =127, DQ6 =123, DQ7 =115
3223 00:59:03.153835 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3224 00:59:03.153892 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3225 00:59:03.153948
3226 00:59:03.154008
3227 00:59:03.154071 ==
3228 00:59:03.154127 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 00:59:03.154184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 00:59:03.154240 ==
3231 00:59:03.154305
3232 00:59:03.154393
3233 00:59:03.154481 TX Vref Scan disable
3234 00:59:03.154555 == TX Byte 0 ==
3235 00:59:03.154614 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3236 00:59:03.154671 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3237 00:59:03.154728 == TX Byte 1 ==
3238 00:59:03.154791 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3239 00:59:03.154849 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3240 00:59:03.154936 ==
3241 00:59:03.155028 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 00:59:03.155117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 00:59:03.155208 ==
3244 00:59:03.155301 TX Vref=22, minBit 8, minWin=25, winSum=415
3245 00:59:03.155588 TX Vref=24, minBit 8, minWin=25, winSum=420
3246 00:59:03.155720 TX Vref=26, minBit 10, minWin=25, winSum=423
3247 00:59:03.155848 TX Vref=28, minBit 1, minWin=26, winSum=434
3248 00:59:03.155975 TX Vref=30, minBit 1, minWin=26, winSum=430
3249 00:59:03.156096 TX Vref=32, minBit 9, minWin=25, winSum=426
3250 00:59:03.156189 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
3251 00:59:03.156288
3252 00:59:03.156381 Final TX Range 1 Vref 28
3253 00:59:03.156470
3254 00:59:03.156562 ==
3255 00:59:03.156666 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 00:59:03.156733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 00:59:03.156794 ==
3258 00:59:03.156852
3259 00:59:03.156907
3260 00:59:03.156966 TX Vref Scan disable
3261 00:59:03.157028 == TX Byte 0 ==
3262 00:59:03.157087 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3263 00:59:03.157144 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3264 00:59:03.157200 == TX Byte 1 ==
3265 00:59:03.157265 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3266 00:59:03.157324 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3267 00:59:03.157380
3268 00:59:03.157436 [DATLAT]
3269 00:59:03.157500 Freq=1200, CH1 RK0
3270 00:59:03.157557
3271 00:59:03.157617 DATLAT Default: 0xd
3272 00:59:03.157673 0, 0xFFFF, sum = 0
3273 00:59:03.157740 1, 0xFFFF, sum = 0
3274 00:59:03.157799 2, 0xFFFF, sum = 0
3275 00:59:03.157856 3, 0xFFFF, sum = 0
3276 00:59:03.157917 4, 0xFFFF, sum = 0
3277 00:59:03.157992 5, 0xFFFF, sum = 0
3278 00:59:03.158083 6, 0xFFFF, sum = 0
3279 00:59:03.158175 7, 0xFFFF, sum = 0
3280 00:59:03.158270 8, 0xFFFF, sum = 0
3281 00:59:03.158361 9, 0xFFFF, sum = 0
3282 00:59:03.158454 10, 0xFFFF, sum = 0
3283 00:59:03.158548 11, 0xFFFF, sum = 0
3284 00:59:03.158638 12, 0x0, sum = 1
3285 00:59:03.158734 13, 0x0, sum = 2
3286 00:59:03.158827 14, 0x0, sum = 3
3287 00:59:03.158917 15, 0x0, sum = 4
3288 00:59:03.159011 best_step = 13
3289 00:59:03.159101
3290 00:59:03.159189 ==
3291 00:59:03.159285 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 00:59:03.159384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 00:59:03.159478 ==
3294 00:59:03.159567 RX Vref Scan: 1
3295 00:59:03.159654
3296 00:59:03.159747 Set Vref Range= 32 -> 127
3297 00:59:03.159835
3298 00:59:03.159924 RX Vref 32 -> 127, step: 1
3299 00:59:03.160015
3300 00:59:03.160102 RX Delay -21 -> 252, step: 4
3301 00:59:03.160191
3302 00:59:03.160281 Set Vref, RX VrefLevel [Byte0]: 32
3303 00:59:03.160369 [Byte1]: 32
3304 00:59:03.160459
3305 00:59:03.160547 Set Vref, RX VrefLevel [Byte0]: 33
3306 00:59:03.160638 [Byte1]: 33
3307 00:59:03.160737
3308 00:59:03.160825 Set Vref, RX VrefLevel [Byte0]: 34
3309 00:59:03.160910 [Byte1]: 34
3310 00:59:03.160974
3311 00:59:03.161032 Set Vref, RX VrefLevel [Byte0]: 35
3312 00:59:03.161088 [Byte1]: 35
3313 00:59:03.161144
3314 00:59:03.161232 Set Vref, RX VrefLevel [Byte0]: 36
3315 00:59:03.161321 [Byte1]: 36
3316 00:59:03.161411
3317 00:59:03.161500 Set Vref, RX VrefLevel [Byte0]: 37
3318 00:59:03.161589 [Byte1]: 37
3319 00:59:03.161678
3320 00:59:03.161768 Set Vref, RX VrefLevel [Byte0]: 38
3321 00:59:03.161868 [Byte1]: 38
3322 00:59:03.161963
3323 00:59:03.162052 Set Vref, RX VrefLevel [Byte0]: 39
3324 00:59:03.162143 [Byte1]: 39
3325 00:59:03.162234
3326 00:59:03.162322 Set Vref, RX VrefLevel [Byte0]: 40
3327 00:59:03.162412 [Byte1]: 40
3328 00:59:03.162503
3329 00:59:03.162591 Set Vref, RX VrefLevel [Byte0]: 41
3330 00:59:03.162683 [Byte1]: 41
3331 00:59:03.162773
3332 00:59:03.162876 Set Vref, RX VrefLevel [Byte0]: 42
3333 00:59:03.162959 [Byte1]: 42
3334 00:59:03.163038
3335 00:59:03.163122 Set Vref, RX VrefLevel [Byte0]: 43
3336 00:59:03.163202 [Byte1]: 43
3337 00:59:03.163283
3338 00:59:03.163364 Set Vref, RX VrefLevel [Byte0]: 44
3339 00:59:03.163447 [Byte1]: 44
3340 00:59:03.163526
3341 00:59:03.163609 Set Vref, RX VrefLevel [Byte0]: 45
3342 00:59:03.163692 [Byte1]: 45
3343 00:59:03.163771
3344 00:59:03.163853 Set Vref, RX VrefLevel [Byte0]: 46
3345 00:59:03.163946 [Byte1]: 46
3346 00:59:03.164027
3347 00:59:03.164110 Set Vref, RX VrefLevel [Byte0]: 47
3348 00:59:03.164191 [Byte1]: 47
3349 00:59:03.164269
3350 00:59:03.164343 Set Vref, RX VrefLevel [Byte0]: 48
3351 00:59:03.164399 [Byte1]: 48
3352 00:59:03.164451
3353 00:59:03.164501 Set Vref, RX VrefLevel [Byte0]: 49
3354 00:59:03.164553 [Byte1]: 49
3355 00:59:03.164635
3356 00:59:03.164723 Set Vref, RX VrefLevel [Byte0]: 50
3357 00:59:03.164815 [Byte1]: 50
3358 00:59:03.164893
3359 00:59:03.164973 Set Vref, RX VrefLevel [Byte0]: 51
3360 00:59:03.165051 [Byte1]: 51
3361 00:59:03.165137
3362 00:59:03.165216 Set Vref, RX VrefLevel [Byte0]: 52
3363 00:59:03.165298 [Byte1]: 52
3364 00:59:03.165381
3365 00:59:03.165459 Set Vref, RX VrefLevel [Byte0]: 53
3366 00:59:03.165535 [Byte1]: 53
3367 00:59:03.165617
3368 00:59:03.165693 Set Vref, RX VrefLevel [Byte0]: 54
3369 00:59:03.165776 [Byte1]: 54
3370 00:59:03.165852
3371 00:59:03.165935 Set Vref, RX VrefLevel [Byte0]: 55
3372 00:59:03.166019 [Byte1]: 55
3373 00:59:03.166072
3374 00:59:03.166147 Set Vref, RX VrefLevel [Byte0]: 56
3375 00:59:03.166199 [Byte1]: 56
3376 00:59:03.166249
3377 00:59:03.166301 Set Vref, RX VrefLevel [Byte0]: 57
3378 00:59:03.166351 [Byte1]: 57
3379 00:59:03.166401
3380 00:59:03.166453 Set Vref, RX VrefLevel [Byte0]: 58
3381 00:59:03.166503 [Byte1]: 58
3382 00:59:03.166552
3383 00:59:03.166600 Set Vref, RX VrefLevel [Byte0]: 59
3384 00:59:03.166657 [Byte1]: 59
3385 00:59:03.166706
3386 00:59:03.166754 Set Vref, RX VrefLevel [Byte0]: 60
3387 00:59:03.166810 [Byte1]: 60
3388 00:59:03.166863
3389 00:59:03.166912 Set Vref, RX VrefLevel [Byte0]: 61
3390 00:59:03.166960 [Byte1]: 61
3391 00:59:03.167008
3392 00:59:03.167062 Set Vref, RX VrefLevel [Byte0]: 62
3393 00:59:03.167114 [Byte1]: 62
3394 00:59:03.167164
3395 00:59:03.167212 Set Vref, RX VrefLevel [Byte0]: 63
3396 00:59:03.167261 [Byte1]: 63
3397 00:59:03.167315
3398 00:59:03.167364 Set Vref, RX VrefLevel [Byte0]: 64
3399 00:59:03.167423 [Byte1]: 64
3400 00:59:03.167498
3401 00:59:03.167578 Final RX Vref Byte 0 = 54 to rank0
3402 00:59:03.167655 Final RX Vref Byte 1 = 54 to rank0
3403 00:59:03.167733 Final RX Vref Byte 0 = 54 to rank1
3404 00:59:03.167813 Final RX Vref Byte 1 = 54 to rank1==
3405 00:59:03.167891 Dram Type= 6, Freq= 0, CH_1, rank 0
3406 00:59:03.167967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3407 00:59:03.168048 ==
3408 00:59:03.168124 DQS Delay:
3409 00:59:03.168200 DQS0 = 0, DQS1 = 0
3410 00:59:03.168278 DQM Delay:
3411 00:59:03.168356 DQM0 = 114, DQM1 = 106
3412 00:59:03.168431 DQ Delay:
3413 00:59:03.168699 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3414 00:59:03.168760 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3415 00:59:03.168813 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =100
3416 00:59:03.168863 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114
3417 00:59:03.168915
3418 00:59:03.168963
3419 00:59:03.169019 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 415 ps
3420 00:59:03.169070 CH1 RK0: MR19=303, MR18=F2F8
3421 00:59:03.169120 CH1_RK0: MR19=0x303, MR18=0xF2F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3422 00:59:03.169172
3423 00:59:03.169251 ----->DramcWriteLeveling(PI) begin...
3424 00:59:03.169330 ==
3425 00:59:03.169406 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 00:59:03.169484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 00:59:03.169563 ==
3428 00:59:03.169643 Write leveling (Byte 0): 24 => 24
3429 00:59:03.169727 Write leveling (Byte 1): 28 => 28
3430 00:59:03.169809 DramcWriteLeveling(PI) end<-----
3431 00:59:03.169886
3432 00:59:03.169961 ==
3433 00:59:03.170017 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 00:59:03.170071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 00:59:03.170121 ==
3436 00:59:03.170169 [Gating] SW mode calibration
3437 00:59:03.170218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3438 00:59:03.170300 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3439 00:59:03.170379 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3440 00:59:03.170456 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 00:59:03.170536 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 00:59:03.170612 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 00:59:03.170691 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 00:59:03.170770 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3445 00:59:03.170848 0 15 24 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
3446 00:59:03.170929 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3447 00:59:03.171008 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 00:59:03.171087 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 00:59:03.171165 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 00:59:03.171242 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 00:59:03.171321 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 00:59:03.171398 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3453 00:59:03.171474 1 0 24 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
3454 00:59:03.171554 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 00:59:03.171634 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 00:59:03.171710 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 00:59:03.171790 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 00:59:03.171868 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 00:59:03.171945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 00:59:03.172023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 00:59:03.172103 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3462 00:59:03.172181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3463 00:59:03.172258 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:59:03.172339 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:59:03.172416 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:59:03.172492 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:59:03.172573 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:59:03.172681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:59:03.172775 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 00:59:03.172852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 00:59:03.172931 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:59:03.173007 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:59:03.173095 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:59:03.173174 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:59:03.173253 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:59:03.173333 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:59:03.173410 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3478 00:59:03.173486 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 00:59:03.173567 Total UI for P1: 0, mck2ui 16
3480 00:59:03.173645 best dqsien dly found for B0: ( 1, 3, 24)
3481 00:59:03.173721 Total UI for P1: 0, mck2ui 16
3482 00:59:03.173801 best dqsien dly found for B1: ( 1, 3, 24)
3483 00:59:03.173880 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3484 00:59:03.173956 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3485 00:59:03.174031
3486 00:59:03.174111 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3487 00:59:03.174189 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3488 00:59:03.174267 [Gating] SW calibration Done
3489 00:59:03.174344 ==
3490 00:59:03.174421 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 00:59:03.174499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 00:59:03.174579 ==
3493 00:59:03.174655 RX Vref Scan: 0
3494 00:59:03.174732
3495 00:59:03.174811 RX Vref 0 -> 0, step: 1
3496 00:59:03.174887
3497 00:59:03.174962 RX Delay -40 -> 252, step: 8
3498 00:59:03.175044 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3499 00:59:03.175121 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3500 00:59:03.175197 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3501 00:59:03.175277 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3502 00:59:03.175355 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3503 00:59:03.175431 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3504 00:59:03.175511 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3505 00:59:03.175590 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3506 00:59:03.175667 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3507 00:59:03.175745 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3508 00:59:03.175824 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3509 00:59:03.175880 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3510 00:59:03.175929 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3511 00:59:03.175982 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3512 00:59:03.176237 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3513 00:59:03.176297 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3514 00:59:03.176346 ==
3515 00:59:03.176396 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 00:59:03.176448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 00:59:03.176505 ==
3518 00:59:03.176582 DQS Delay:
3519 00:59:03.176661 DQS0 = 0, DQS1 = 0
3520 00:59:03.176790 DQM Delay:
3521 00:59:03.176867 DQM0 = 110, DQM1 = 107
3522 00:59:03.176942 DQ Delay:
3523 00:59:03.177002 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3524 00:59:03.177052 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3525 00:59:03.177105 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3526 00:59:03.177153 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3527 00:59:03.177201
3528 00:59:03.177254
3529 00:59:03.177302 ==
3530 00:59:03.177350 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 00:59:03.177428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 00:59:03.177509 ==
3533 00:59:03.177587
3534 00:59:03.177665
3535 00:59:03.177741 TX Vref Scan disable
3536 00:59:03.177820 == TX Byte 0 ==
3537 00:59:03.177897 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3538 00:59:03.177975 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3539 00:59:03.178054 == TX Byte 1 ==
3540 00:59:03.178132 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3541 00:59:03.178209 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3542 00:59:03.178289 ==
3543 00:59:03.178368 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 00:59:03.178445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 00:59:03.178523 ==
3546 00:59:03.178600 TX Vref=22, minBit 11, minWin=25, winSum=423
3547 00:59:03.178683 TX Vref=24, minBit 9, minWin=25, winSum=429
3548 00:59:03.178762 TX Vref=26, minBit 0, minWin=26, winSum=430
3549 00:59:03.178842 TX Vref=28, minBit 8, minWin=26, winSum=432
3550 00:59:03.178920 TX Vref=30, minBit 1, minWin=26, winSum=436
3551 00:59:03.179000 TX Vref=32, minBit 4, minWin=26, winSum=434
3552 00:59:03.179079 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
3553 00:59:03.179155
3554 00:59:03.179235 Final TX Range 1 Vref 30
3555 00:59:03.179312
3556 00:59:03.179386 ==
3557 00:59:03.179465 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 00:59:03.179543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 00:59:03.179629 ==
3560 00:59:03.179708
3561 00:59:03.179787
3562 00:59:03.179863 TX Vref Scan disable
3563 00:59:03.179939 == TX Byte 0 ==
3564 00:59:03.180018 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3565 00:59:03.180098 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3566 00:59:03.180173 == TX Byte 1 ==
3567 00:59:03.180253 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3568 00:59:03.180331 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3569 00:59:03.180407
3570 00:59:03.180486 [DATLAT]
3571 00:59:03.180562 Freq=1200, CH1 RK1
3572 00:59:03.180640
3573 00:59:03.180760 DATLAT Default: 0xd
3574 00:59:03.180837 0, 0xFFFF, sum = 0
3575 00:59:03.180915 1, 0xFFFF, sum = 0
3576 00:59:03.180998 2, 0xFFFF, sum = 0
3577 00:59:03.181076 3, 0xFFFF, sum = 0
3578 00:59:03.181154 4, 0xFFFF, sum = 0
3579 00:59:03.181223 5, 0xFFFF, sum = 0
3580 00:59:03.181302 6, 0xFFFF, sum = 0
3581 00:59:03.181380 7, 0xFFFF, sum = 0
3582 00:59:03.181461 8, 0xFFFF, sum = 0
3583 00:59:03.181541 9, 0xFFFF, sum = 0
3584 00:59:03.181618 10, 0xFFFF, sum = 0
3585 00:59:03.181699 11, 0xFFFF, sum = 0
3586 00:59:03.181777 12, 0x0, sum = 1
3587 00:59:03.181857 13, 0x0, sum = 2
3588 00:59:03.181937 14, 0x0, sum = 3
3589 00:59:03.182015 15, 0x0, sum = 4
3590 00:59:03.182092 best_step = 13
3591 00:59:03.182143
3592 00:59:03.182199 ==
3593 00:59:03.182249 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 00:59:03.182298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 00:59:03.182346 ==
3596 00:59:03.182398 RX Vref Scan: 0
3597 00:59:03.182465
3598 00:59:03.182550 RX Vref 0 -> 0, step: 1
3599 00:59:03.182627
3600 00:59:03.182708 RX Delay -21 -> 252, step: 4
3601 00:59:03.182785 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3602 00:59:03.182862 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3603 00:59:03.182942 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3604 00:59:03.183020 iDelay=195, Bit 3, Center 106 (35 ~ 178) 144
3605 00:59:03.183097 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3606 00:59:03.183176 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3607 00:59:03.183253 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3608 00:59:03.183331 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3609 00:59:03.183409 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3610 00:59:03.183486 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3611 00:59:03.183564 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3612 00:59:03.183641 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3613 00:59:03.183721 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3614 00:59:03.183798 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3615 00:59:03.183877 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3616 00:59:03.183958 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3617 00:59:03.184033 ==
3618 00:59:03.184110 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 00:59:03.184191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 00:59:03.184269 ==
3621 00:59:03.184345 DQS Delay:
3622 00:59:03.184424 DQS0 = 0, DQS1 = 0
3623 00:59:03.184502 DQM Delay:
3624 00:59:03.184578 DQM0 = 111, DQM1 = 110
3625 00:59:03.184658 DQ Delay:
3626 00:59:03.184739 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =106
3627 00:59:03.184792 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =110
3628 00:59:03.184842 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =104
3629 00:59:03.184898 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3630 00:59:03.184949
3631 00:59:03.184997
3632 00:59:03.185045 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3633 00:59:03.185098 CH1 RK1: MR19=304, MR18=F808
3634 00:59:03.185152 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3635 00:59:03.185203 [RxdqsGatingPostProcess] freq 1200
3636 00:59:03.185252 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3637 00:59:03.185301 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 00:59:03.185349 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 00:59:03.185403 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 00:59:03.185455 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 00:59:03.185503 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 00:59:03.185552 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 00:59:03.185599 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 00:59:03.185653 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 00:59:03.185704 Pre-setting of DQS Precalculation
3646 00:59:03.185754 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3647 00:59:03.185803 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3648 00:59:03.185852 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3649 00:59:03.185907
3650 00:59:03.185954
3651 00:59:03.186218 [Calibration Summary] 2400 Mbps
3652 00:59:03.186292 CH 0, Rank 0
3653 00:59:03.186345 SW Impedance : PASS
3654 00:59:03.186425 DUTY Scan : NO K
3655 00:59:03.186502 ZQ Calibration : PASS
3656 00:59:03.186576 Jitter Meter : NO K
3657 00:59:03.186636 CBT Training : PASS
3658 00:59:03.186712 Write leveling : PASS
3659 00:59:03.186788 RX DQS gating : PASS
3660 00:59:03.186861 RX DQ/DQS(RDDQC) : PASS
3661 00:59:03.186915 TX DQ/DQS : PASS
3662 00:59:03.186964 RX DATLAT : PASS
3663 00:59:03.187012 RX DQ/DQS(Engine): PASS
3664 00:59:03.187060 TX OE : NO K
3665 00:59:03.187115 All Pass.
3666 00:59:03.187166
3667 00:59:03.187215 CH 0, Rank 1
3668 00:59:03.187264 SW Impedance : PASS
3669 00:59:03.187312 DUTY Scan : NO K
3670 00:59:03.187367 ZQ Calibration : PASS
3671 00:59:03.187416 Jitter Meter : NO K
3672 00:59:03.187471 CBT Training : PASS
3673 00:59:03.187547 Write leveling : PASS
3674 00:59:03.187626 RX DQS gating : PASS
3675 00:59:03.187701 RX DQ/DQS(RDDQC) : PASS
3676 00:59:03.187779 TX DQ/DQS : PASS
3677 00:59:03.187859 RX DATLAT : PASS
3678 00:59:03.187934 RX DQ/DQS(Engine): PASS
3679 00:59:03.188009 TX OE : NO K
3680 00:59:03.188088 All Pass.
3681 00:59:03.188165
3682 00:59:03.188240 CH 1, Rank 0
3683 00:59:03.188318 SW Impedance : PASS
3684 00:59:03.188396 DUTY Scan : NO K
3685 00:59:03.188472 ZQ Calibration : PASS
3686 00:59:03.188548 Jitter Meter : NO K
3687 00:59:03.188627 CBT Training : PASS
3688 00:59:03.188731 Write leveling : PASS
3689 00:59:03.188781 RX DQS gating : PASS
3690 00:59:03.188838 RX DQ/DQS(RDDQC) : PASS
3691 00:59:03.188888 TX DQ/DQS : PASS
3692 00:59:03.188941 RX DATLAT : PASS
3693 00:59:03.188990 RX DQ/DQS(Engine): PASS
3694 00:59:03.189038 TX OE : NO K
3695 00:59:03.189093 All Pass.
3696 00:59:03.189141
3697 00:59:03.189191 CH 1, Rank 1
3698 00:59:03.189267 SW Impedance : PASS
3699 00:59:03.189351 DUTY Scan : NO K
3700 00:59:03.189431 ZQ Calibration : PASS
3701 00:59:03.189510 Jitter Meter : NO K
3702 00:59:03.189586 CBT Training : PASS
3703 00:59:03.189662 Write leveling : PASS
3704 00:59:03.189738 RX DQS gating : PASS
3705 00:59:03.189815 RX DQ/DQS(RDDQC) : PASS
3706 00:59:03.189895 TX DQ/DQS : PASS
3707 00:59:03.189971 RX DATLAT : PASS
3708 00:59:03.190047 RX DQ/DQS(Engine): PASS
3709 00:59:03.190125 TX OE : NO K
3710 00:59:03.190189 All Pass.
3711 00:59:03.190239
3712 00:59:03.190287 DramC Write-DBI off
3713 00:59:03.190336 PER_BANK_REFRESH: Hybrid Mode
3714 00:59:03.190391 TX_TRACKING: ON
3715 00:59:03.190439 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3716 00:59:03.190489 [FAST_K] Save calibration result to emmc
3717 00:59:03.190542 dramc_set_vcore_voltage set vcore to 650000
3718 00:59:03.190590 Read voltage for 600, 5
3719 00:59:03.190645 Vio18 = 0
3720 00:59:03.190695 Vcore = 650000
3721 00:59:03.190743 Vdram = 0
3722 00:59:03.190791 Vddq = 0
3723 00:59:03.190839 Vmddr = 0
3724 00:59:03.190895 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3725 00:59:03.190945 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3726 00:59:03.190995 MEM_TYPE=3, freq_sel=19
3727 00:59:03.191043 sv_algorithm_assistance_LP4_1600
3728 00:59:03.191096 ============ PULL DRAM RESETB DOWN ============
3729 00:59:03.191146 ========== PULL DRAM RESETB DOWN end =========
3730 00:59:03.191198 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 00:59:03.191247 ===================================
3732 00:59:03.191295 LPDDR4 DRAM CONFIGURATION
3733 00:59:03.191348 ===================================
3734 00:59:03.191398 EX_ROW_EN[0] = 0x0
3735 00:59:03.191446 EX_ROW_EN[1] = 0x0
3736 00:59:03.191515 LP4Y_EN = 0x0
3737 00:59:03.191591 WORK_FSP = 0x0
3738 00:59:03.191643 WL = 0x2
3739 00:59:03.191693 RL = 0x2
3740 00:59:03.191746 BL = 0x2
3741 00:59:03.191822 RPST = 0x0
3742 00:59:03.191901 RD_PRE = 0x0
3743 00:59:03.191977 WR_PRE = 0x1
3744 00:59:03.192054 WR_PST = 0x0
3745 00:59:03.192158 DBI_WR = 0x0
3746 00:59:03.192260 DBI_RD = 0x0
3747 00:59:03.192353 OTF = 0x1
3748 00:59:03.192432 ===================================
3749 00:59:03.192509 ===================================
3750 00:59:03.192588 ANA top config
3751 00:59:03.192703 ===================================
3752 00:59:03.192755 DLL_ASYNC_EN = 0
3753 00:59:03.192817 ALL_SLAVE_EN = 1
3754 00:59:03.192876 NEW_RANK_MODE = 1
3755 00:59:03.192927 DLL_IDLE_MODE = 1
3756 00:59:03.192976 LP45_APHY_COMB_EN = 1
3757 00:59:03.193025 TX_ODT_DIS = 1
3758 00:59:03.193082 NEW_8X_MODE = 1
3759 00:59:03.193135 ===================================
3760 00:59:03.193185 ===================================
3761 00:59:03.193233 data_rate = 1200
3762 00:59:03.193282 CKR = 1
3763 00:59:03.193337 DQ_P2S_RATIO = 8
3764 00:59:03.193390 ===================================
3765 00:59:03.193439 CA_P2S_RATIO = 8
3766 00:59:03.193487 DQ_CA_OPEN = 0
3767 00:59:03.193536 DQ_SEMI_OPEN = 0
3768 00:59:03.193591 CA_SEMI_OPEN = 0
3769 00:59:03.193641 CA_FULL_RATE = 0
3770 00:59:03.193689 DQ_CKDIV4_EN = 1
3771 00:59:03.193737 CA_CKDIV4_EN = 1
3772 00:59:03.193785 CA_PREDIV_EN = 0
3773 00:59:03.193842 PH8_DLY = 0
3774 00:59:03.193892 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3775 00:59:03.193941 DQ_AAMCK_DIV = 4
3776 00:59:03.193988 CA_AAMCK_DIV = 4
3777 00:59:03.194036 CA_ADMCK_DIV = 4
3778 00:59:03.194091 DQ_TRACK_CA_EN = 0
3779 00:59:03.194143 CA_PICK = 600
3780 00:59:03.194191 CA_MCKIO = 600
3781 00:59:03.194240 MCKIO_SEMI = 0
3782 00:59:03.194288 PLL_FREQ = 2288
3783 00:59:03.194344 DQ_UI_PI_RATIO = 32
3784 00:59:03.194394 CA_UI_PI_RATIO = 0
3785 00:59:03.194443 ===================================
3786 00:59:03.194491 ===================================
3787 00:59:03.194540 memory_type:LPDDR4
3788 00:59:03.194595 GP_NUM : 10
3789 00:59:03.194644 SRAM_EN : 1
3790 00:59:03.194692 MD32_EN : 0
3791 00:59:03.194740 ===================================
3792 00:59:03.194791 [ANA_INIT] >>>>>>>>>>>>>>
3793 00:59:03.194843 <<<<<< [CONFIGURE PHASE]: ANA_TX
3794 00:59:03.194893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3795 00:59:03.194942 ===================================
3796 00:59:03.194990 data_rate = 1200,PCW = 0X5800
3797 00:59:03.195042 ===================================
3798 00:59:03.195099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3799 00:59:03.195366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 00:59:03.195451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 00:59:03.195530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3802 00:59:03.195612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3803 00:59:03.195689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3804 00:59:03.195766 [ANA_INIT] flow start
3805 00:59:03.195847 [ANA_INIT] PLL >>>>>>>>
3806 00:59:03.195923 [ANA_INIT] PLL <<<<<<<<
3807 00:59:03.195998 [ANA_INIT] MIDPI >>>>>>>>
3808 00:59:03.196079 [ANA_INIT] MIDPI <<<<<<<<
3809 00:59:03.196155 [ANA_INIT] DLL >>>>>>>>
3810 00:59:03.196230 [ANA_INIT] flow end
3811 00:59:03.196318 ============ LP4 DIFF to SE enter ============
3812 00:59:03.196399 ============ LP4 DIFF to SE exit ============
3813 00:59:03.196475 [ANA_INIT] <<<<<<<<<<<<<
3814 00:59:03.196555 [Flow] Enable top DCM control >>>>>
3815 00:59:03.196633 [Flow] Enable top DCM control <<<<<
3816 00:59:03.196727 Enable DLL master slave shuffle
3817 00:59:03.196785 ==============================================================
3818 00:59:03.196841 Gating Mode config
3819 00:59:03.196891 ==============================================================
3820 00:59:03.196939 Config description:
3821 00:59:03.196988 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3822 00:59:03.197045 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3823 00:59:03.197095 SELPH_MODE 0: By rank 1: By Phase
3824 00:59:03.197147 ==============================================================
3825 00:59:03.197197 GAT_TRACK_EN = 1
3826 00:59:03.197249 RX_GATING_MODE = 2
3827 00:59:03.197300 RX_GATING_TRACK_MODE = 2
3828 00:59:03.197352 SELPH_MODE = 1
3829 00:59:03.197429 PICG_EARLY_EN = 1
3830 00:59:03.197506 VALID_LAT_VALUE = 1
3831 00:59:03.197559 ==============================================================
3832 00:59:03.197609 Enter into Gating configuration >>>>
3833 00:59:03.197675 Exit from Gating configuration <<<<
3834 00:59:03.197752 Enter into DVFS_PRE_config >>>>>
3835 00:59:03.197805 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3836 00:59:03.197855 Exit from DVFS_PRE_config <<<<<
3837 00:59:03.197904 Enter into PICG configuration >>>>
3838 00:59:03.197979 Exit from PICG configuration <<<<
3839 00:59:03.198059 [RX_INPUT] configuration >>>>>
3840 00:59:03.198135 [RX_INPUT] configuration <<<<<
3841 00:59:03.198213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3842 00:59:03.198294 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3843 00:59:03.198371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 00:59:03.198448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 00:59:03.198512 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 00:59:03.198567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 00:59:03.198617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3848 00:59:03.198665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3849 00:59:03.198718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3850 00:59:03.198773 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3851 00:59:03.198823 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3852 00:59:03.198871 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 00:59:03.198920 ===================================
3854 00:59:03.198973 LPDDR4 DRAM CONFIGURATION
3855 00:59:03.199029 ===================================
3856 00:59:03.199106 EX_ROW_EN[0] = 0x0
3857 00:59:03.199182 EX_ROW_EN[1] = 0x0
3858 00:59:03.199262 LP4Y_EN = 0x0
3859 00:59:03.199339 WORK_FSP = 0x0
3860 00:59:03.199427 WL = 0x2
3861 00:59:03.199509 RL = 0x2
3862 00:59:03.199775 BL = 0x2
3863 00:59:03.199862 RPST = 0x0
3864 00:59:03.202775 RD_PRE = 0x0
3865 00:59:03.202875 WR_PRE = 0x1
3866 00:59:03.206307 WR_PST = 0x0
3867 00:59:03.206402 DBI_WR = 0x0
3868 00:59:03.209383 DBI_RD = 0x0
3869 00:59:03.209482 OTF = 0x1
3870 00:59:03.212849 ===================================
3871 00:59:03.215813 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3872 00:59:03.222706 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3873 00:59:03.226175 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 00:59:03.229059 ===================================
3875 00:59:03.232414 LPDDR4 DRAM CONFIGURATION
3876 00:59:03.235887 ===================================
3877 00:59:03.235988 EX_ROW_EN[0] = 0x10
3878 00:59:03.239250 EX_ROW_EN[1] = 0x0
3879 00:59:03.242673 LP4Y_EN = 0x0
3880 00:59:03.242766 WORK_FSP = 0x0
3881 00:59:03.246080 WL = 0x2
3882 00:59:03.246170 RL = 0x2
3883 00:59:03.249116 BL = 0x2
3884 00:59:03.249180 RPST = 0x0
3885 00:59:03.252490 RD_PRE = 0x0
3886 00:59:03.252575 WR_PRE = 0x1
3887 00:59:03.255725 WR_PST = 0x0
3888 00:59:03.255814 DBI_WR = 0x0
3889 00:59:03.258960 DBI_RD = 0x0
3890 00:59:03.259049 OTF = 0x1
3891 00:59:03.262720 ===================================
3892 00:59:03.269321 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3893 00:59:03.273329 nWR fixed to 30
3894 00:59:03.276616 [ModeRegInit_LP4] CH0 RK0
3895 00:59:03.276729 [ModeRegInit_LP4] CH0 RK1
3896 00:59:03.279513 [ModeRegInit_LP4] CH1 RK0
3897 00:59:03.283180 [ModeRegInit_LP4] CH1 RK1
3898 00:59:03.283276 match AC timing 17
3899 00:59:03.289749 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3900 00:59:03.293219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3901 00:59:03.296520 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3902 00:59:03.302884 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3903 00:59:03.306616 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3904 00:59:03.306703 ==
3905 00:59:03.309706 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 00:59:03.313514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3907 00:59:03.313634 ==
3908 00:59:03.320047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3909 00:59:03.326553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3910 00:59:03.329691 [CA 0] Center 37 (7~67) winsize 61
3911 00:59:03.333388 [CA 1] Center 37 (7~67) winsize 61
3912 00:59:03.336351 [CA 2] Center 35 (5~65) winsize 61
3913 00:59:03.339918 [CA 3] Center 35 (5~65) winsize 61
3914 00:59:03.342926 [CA 4] Center 34 (4~65) winsize 62
3915 00:59:03.346348 [CA 5] Center 34 (4~65) winsize 62
3916 00:59:03.346416
3917 00:59:03.349567 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3918 00:59:03.349633
3919 00:59:03.353096 [CATrainingPosCal] consider 1 rank data
3920 00:59:03.356364 u2DelayCellTimex100 = 270/100 ps
3921 00:59:03.359880 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3922 00:59:03.363152 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3923 00:59:03.366359 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3924 00:59:03.369457 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3925 00:59:03.372873 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3926 00:59:03.376208 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3927 00:59:03.379795
3928 00:59:03.382915 CA PerBit enable=1, Macro0, CA PI delay=34
3929 00:59:03.494761
3930 00:59:03.495054 [CBTSetCACLKResult] CA Dly = 34
3931 00:59:03.495131 CS Dly: 6 (0~37)
3932 00:59:03.495185 ==
3933 00:59:03.495238 Dram Type= 6, Freq= 0, CH_0, rank 1
3934 00:59:03.495291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 00:59:03.495342 ==
3936 00:59:03.495392 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 00:59:03.495442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3938 00:59:03.495492 [CA 0] Center 37 (7~67) winsize 61
3939 00:59:03.495540 [CA 1] Center 37 (7~67) winsize 61
3940 00:59:03.495589 [CA 2] Center 35 (5~65) winsize 61
3941 00:59:03.495637 [CA 3] Center 34 (4~65) winsize 62
3942 00:59:03.495685 [CA 4] Center 34 (4~65) winsize 62
3943 00:59:03.495733 [CA 5] Center 34 (3~65) winsize 63
3944 00:59:03.495781
3945 00:59:03.495829 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3946 00:59:03.495877
3947 00:59:03.495952 [CATrainingPosCal] consider 2 rank data
3948 00:59:03.496016 u2DelayCellTimex100 = 270/100 ps
3949 00:59:03.496115 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3950 00:59:03.496167 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3951 00:59:03.496217 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3952 00:59:03.496272 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3953 00:59:03.496322 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3954 00:59:03.496399 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3955 00:59:03.496461
3956 00:59:03.496526 CA PerBit enable=1, Macro0, CA PI delay=34
3957 00:59:03.496575
3958 00:59:03.496624 [CBTSetCACLKResult] CA Dly = 34
3959 00:59:03.496696 CS Dly: 6 (0~38)
3960 00:59:03.496744
3961 00:59:03.496790 ----->DramcWriteLeveling(PI) begin...
3962 00:59:03.496839 ==
3963 00:59:03.496888 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 00:59:03.496936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 00:59:03.496984 ==
3966 00:59:03.497031 Write leveling (Byte 0): 32 => 32
3967 00:59:03.497078 Write leveling (Byte 1): 31 => 31
3968 00:59:03.497125 DramcWriteLeveling(PI) end<-----
3969 00:59:03.497172
3970 00:59:03.497218 ==
3971 00:59:03.497266 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 00:59:03.497325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 00:59:03.497379 ==
3974 00:59:03.498874 [Gating] SW mode calibration
3975 00:59:03.505626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3976 00:59:03.508767 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3977 00:59:03.515370 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 00:59:03.518831 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 00:59:03.522120 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 00:59:03.528822 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3981 00:59:03.532276 0 9 16 | B1->B0 | 3232 2626 | 1 0 | (1 1) (0 0)
3982 00:59:03.535601 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3983 00:59:03.541894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 00:59:03.545398 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:59:03.548778 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 00:59:03.555117 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 00:59:03.558671 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 00:59:03.561685 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3989 00:59:03.568582 0 10 16 | B1->B0 | 3232 3939 | 1 0 | (0 0) (0 0)
3990 00:59:03.572008 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:59:03.575506 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 00:59:03.578963 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 00:59:03.585469 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 00:59:03.588472 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:59:03.591984 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 00:59:03.598603 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3997 00:59:03.602045 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3998 00:59:03.605056 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:59:03.611909 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:59:03.615368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:59:03.618761 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:59:03.625243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:59:03.628248 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:59:03.631698 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:59:03.638820 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:59:03.641653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:59:03.644792 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:59:03.651431 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:59:03.655175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:59:03.658148 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:59:03.664776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:59:03.668231 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4013 00:59:03.671769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4014 00:59:03.678187 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 00:59:03.678280 Total UI for P1: 0, mck2ui 16
4016 00:59:03.684701 best dqsien dly found for B0: ( 0, 13, 14)
4017 00:59:03.684779 Total UI for P1: 0, mck2ui 16
4018 00:59:03.691822 best dqsien dly found for B1: ( 0, 13, 18)
4019 00:59:03.694741 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4020 00:59:03.698217 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4021 00:59:03.698293
4022 00:59:03.701151 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4023 00:59:03.704855 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4024 00:59:03.707738 [Gating] SW calibration Done
4025 00:59:03.707837 ==
4026 00:59:03.711073 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 00:59:03.714523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 00:59:03.714601 ==
4029 00:59:03.717969 RX Vref Scan: 0
4030 00:59:03.718044
4031 00:59:03.718104 RX Vref 0 -> 0, step: 1
4032 00:59:03.718158
4033 00:59:03.721039 RX Delay -230 -> 252, step: 16
4034 00:59:03.728055 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4035 00:59:03.731006 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4036 00:59:03.734486 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4037 00:59:03.737916 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4038 00:59:03.741416 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4039 00:59:03.747810 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4040 00:59:03.751319 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4041 00:59:03.754409 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4042 00:59:03.757540 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4043 00:59:03.764118 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4044 00:59:03.767933 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4045 00:59:03.770839 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4046 00:59:03.774587 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4047 00:59:03.780605 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4048 00:59:03.784500 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4049 00:59:03.787303 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4050 00:59:03.787401 ==
4051 00:59:03.790811 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 00:59:03.794487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 00:59:03.794580 ==
4054 00:59:03.797163 DQS Delay:
4055 00:59:03.797266 DQS0 = 0, DQS1 = 0
4056 00:59:03.800795 DQM Delay:
4057 00:59:03.800895 DQM0 = 38, DQM1 = 30
4058 00:59:03.800988 DQ Delay:
4059 00:59:03.803897 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4060 00:59:03.807037 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4061 00:59:03.810770 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4062 00:59:03.813786 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4063 00:59:03.813876
4064 00:59:03.817019
4065 00:59:03.817097 ==
4066 00:59:03.820558 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 00:59:03.824154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 00:59:03.824229 ==
4069 00:59:03.824346
4070 00:59:03.824426
4071 00:59:03.827115 TX Vref Scan disable
4072 00:59:03.827220 == TX Byte 0 ==
4073 00:59:03.833836 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4074 00:59:03.836922 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4075 00:59:03.837001 == TX Byte 1 ==
4076 00:59:03.843388 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 00:59:03.846995 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 00:59:03.847088 ==
4079 00:59:03.850440 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 00:59:03.853466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 00:59:03.853532 ==
4082 00:59:03.853589
4083 00:59:03.853648
4084 00:59:03.856864 TX Vref Scan disable
4085 00:59:03.859914 == TX Byte 0 ==
4086 00:59:03.863516 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4087 00:59:03.866479 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4088 00:59:03.870038 == TX Byte 1 ==
4089 00:59:03.873583 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 00:59:03.876653 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 00:59:03.880246
4092 00:59:03.880348 [DATLAT]
4093 00:59:03.880435 Freq=600, CH0 RK0
4094 00:59:03.880520
4095 00:59:03.883476 DATLAT Default: 0x9
4096 00:59:03.883577 0, 0xFFFF, sum = 0
4097 00:59:03.886915 1, 0xFFFF, sum = 0
4098 00:59:03.886994 2, 0xFFFF, sum = 0
4099 00:59:03.889910 3, 0xFFFF, sum = 0
4100 00:59:03.889987 4, 0xFFFF, sum = 0
4101 00:59:03.893280 5, 0xFFFF, sum = 0
4102 00:59:03.893358 6, 0xFFFF, sum = 0
4103 00:59:03.896846 7, 0xFFFF, sum = 0
4104 00:59:03.896923 8, 0x0, sum = 1
4105 00:59:03.900175 9, 0x0, sum = 2
4106 00:59:03.900276 10, 0x0, sum = 3
4107 00:59:03.903496 11, 0x0, sum = 4
4108 00:59:03.903573 best_step = 9
4109 00:59:03.903636
4110 00:59:03.903809 ==
4111 00:59:03.906557 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 00:59:03.913109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 00:59:03.913211 ==
4114 00:59:03.913300 RX Vref Scan: 1
4115 00:59:03.913385
4116 00:59:03.916278 RX Vref 0 -> 0, step: 1
4117 00:59:03.916354
4118 00:59:03.920141 RX Delay -195 -> 252, step: 8
4119 00:59:03.920216
4120 00:59:03.923053 Set Vref, RX VrefLevel [Byte0]: 64
4121 00:59:03.926524 [Byte1]: 49
4122 00:59:03.926615
4123 00:59:03.929711 Final RX Vref Byte 0 = 64 to rank0
4124 00:59:03.933038 Final RX Vref Byte 1 = 49 to rank0
4125 00:59:03.936407 Final RX Vref Byte 0 = 64 to rank1
4126 00:59:03.939846 Final RX Vref Byte 1 = 49 to rank1==
4127 00:59:03.943218 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 00:59:03.946370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 00:59:03.946447 ==
4130 00:59:03.949246 DQS Delay:
4131 00:59:03.949324 DQS0 = 0, DQS1 = 0
4132 00:59:03.952687 DQM Delay:
4133 00:59:03.952778 DQM0 = 35, DQM1 = 29
4134 00:59:03.952839 DQ Delay:
4135 00:59:03.956391 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4136 00:59:03.959476 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4137 00:59:03.963000 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =20
4138 00:59:03.965942 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4139 00:59:03.966019
4140 00:59:03.966079
4141 00:59:03.975796 [DQSOSCAuto] RK0, (LSB)MR18= 0x4948, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4142 00:59:03.979493 CH0 RK0: MR19=808, MR18=4948
4143 00:59:03.986130 CH0_RK0: MR19=0x808, MR18=0x4948, DQSOSC=396, MR23=63, INC=167, DEC=111
4144 00:59:03.986238
4145 00:59:03.989304 ----->DramcWriteLeveling(PI) begin...
4146 00:59:03.989383 ==
4147 00:59:03.992843 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 00:59:03.995793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 00:59:03.995871 ==
4150 00:59:03.999153 Write leveling (Byte 0): 33 => 33
4151 00:59:04.002839 Write leveling (Byte 1): 32 => 32
4152 00:59:04.005860 DramcWriteLeveling(PI) end<-----
4153 00:59:04.005929
4154 00:59:04.005986 ==
4155 00:59:04.009423 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 00:59:04.012417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 00:59:04.012478 ==
4158 00:59:04.016058 [Gating] SW mode calibration
4159 00:59:04.022831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 00:59:04.029447 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 00:59:04.032886 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 00:59:04.035701 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 00:59:04.042672 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 00:59:04.045930 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4165 00:59:04.049358 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4166 00:59:04.055742 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 00:59:04.059050 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 00:59:04.062070 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 00:59:04.069270 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 00:59:04.072547 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 00:59:04.075372 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 00:59:04.082229 0 10 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
4173 00:59:04.085239 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
4174 00:59:04.088842 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 00:59:04.092459 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 00:59:04.099064 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 00:59:04.102022 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 00:59:04.105965 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 00:59:04.112487 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 00:59:04.115512 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4181 00:59:04.119148 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:59:04.125553 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:59:04.128615 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:59:04.132182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:59:04.138408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:59:04.141964 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:59:04.145621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:59:04.151929 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:59:04.155543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:59:04.158547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:59:04.165440 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:59:04.168749 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:59:04.171775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:59:04.178184 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:59:04.181503 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:59:04.185055 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:59:04.191600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4198 00:59:04.191677 Total UI for P1: 0, mck2ui 16
4199 00:59:04.198409 best dqsien dly found for B0: ( 0, 13, 14)
4200 00:59:04.201499 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 00:59:04.204827 Total UI for P1: 0, mck2ui 16
4202 00:59:04.208222 best dqsien dly found for B1: ( 0, 13, 16)
4203 00:59:04.211544 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4204 00:59:04.214975 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4205 00:59:04.215069
4206 00:59:04.217797 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4207 00:59:04.221249 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4208 00:59:04.224913 [Gating] SW calibration Done
4209 00:59:04.224983 ==
4210 00:59:04.227880 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 00:59:04.234315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 00:59:04.234409 ==
4213 00:59:04.234499 RX Vref Scan: 0
4214 00:59:04.234581
4215 00:59:04.238010 RX Vref 0 -> 0, step: 1
4216 00:59:04.238085
4217 00:59:04.240938 RX Delay -230 -> 252, step: 16
4218 00:59:04.244564 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4219 00:59:04.247600 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4220 00:59:04.251105 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4221 00:59:04.257631 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4222 00:59:04.261265 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4223 00:59:04.264123 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4224 00:59:04.267224 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4225 00:59:04.273744 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4226 00:59:04.277428 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4227 00:59:04.280575 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4228 00:59:04.283973 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4229 00:59:04.287533 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4230 00:59:04.294012 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4231 00:59:04.297522 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4232 00:59:04.300451 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4233 00:59:04.303867 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4234 00:59:04.306864 ==
4235 00:59:04.310308 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 00:59:04.313667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 00:59:04.313769 ==
4238 00:59:04.313856 DQS Delay:
4239 00:59:04.317014 DQS0 = 0, DQS1 = 0
4240 00:59:04.317085 DQM Delay:
4241 00:59:04.320158 DQM0 = 36, DQM1 = 28
4242 00:59:04.320240 DQ Delay:
4243 00:59:04.323595 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4244 00:59:04.327369 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4245 00:59:04.330274 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4246 00:59:04.333586 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4247 00:59:04.333659
4248 00:59:04.333718
4249 00:59:04.333774 ==
4250 00:59:04.336710 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 00:59:04.340256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 00:59:04.340376 ==
4253 00:59:04.340437
4254 00:59:04.340491
4255 00:59:04.343751 TX Vref Scan disable
4256 00:59:04.346633 == TX Byte 0 ==
4257 00:59:04.350358 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4258 00:59:04.353368 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4259 00:59:04.356729 == TX Byte 1 ==
4260 00:59:04.360056 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4261 00:59:04.363061 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4262 00:59:04.363134 ==
4263 00:59:04.366563 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 00:59:04.372987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 00:59:04.373062 ==
4266 00:59:04.373120
4267 00:59:04.373172
4268 00:59:04.373222 TX Vref Scan disable
4269 00:59:04.377716 == TX Byte 0 ==
4270 00:59:04.381238 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4271 00:59:04.387478 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4272 00:59:04.387552 == TX Byte 1 ==
4273 00:59:04.390778 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4274 00:59:04.397300 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4275 00:59:04.397400
4276 00:59:04.397489 [DATLAT]
4277 00:59:04.397579 Freq=600, CH0 RK1
4278 00:59:04.397665
4279 00:59:04.400790 DATLAT Default: 0x9
4280 00:59:04.400880 0, 0xFFFF, sum = 0
4281 00:59:04.404293 1, 0xFFFF, sum = 0
4282 00:59:04.404367 2, 0xFFFF, sum = 0
4283 00:59:04.407666 3, 0xFFFF, sum = 0
4284 00:59:04.410573 4, 0xFFFF, sum = 0
4285 00:59:04.410643 5, 0xFFFF, sum = 0
4286 00:59:04.414208 6, 0xFFFF, sum = 0
4287 00:59:04.414283 7, 0xFFFF, sum = 0
4288 00:59:04.417266 8, 0x0, sum = 1
4289 00:59:04.417342 9, 0x0, sum = 2
4290 00:59:04.417401 10, 0x0, sum = 3
4291 00:59:04.421024 11, 0x0, sum = 4
4292 00:59:04.421101 best_step = 9
4293 00:59:04.421182
4294 00:59:04.421256 ==
4295 00:59:04.424042 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 00:59:04.430812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 00:59:04.430888 ==
4298 00:59:04.430946 RX Vref Scan: 0
4299 00:59:04.431000
4300 00:59:04.433648 RX Vref 0 -> 0, step: 1
4301 00:59:04.433718
4302 00:59:04.437368 RX Delay -195 -> 252, step: 8
4303 00:59:04.440524 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4304 00:59:04.446894 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4305 00:59:04.450529 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4306 00:59:04.453937 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4307 00:59:04.457057 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4308 00:59:04.463883 iDelay=205, Bit 5, Center 20 (-131 ~ 172) 304
4309 00:59:04.467383 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4310 00:59:04.470227 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4311 00:59:04.473861 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4312 00:59:04.476807 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4313 00:59:04.483653 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4314 00:59:04.487069 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4315 00:59:04.490547 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4316 00:59:04.493786 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4317 00:59:04.500197 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4318 00:59:04.503353 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4319 00:59:04.503445 ==
4320 00:59:04.506738 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 00:59:04.510016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 00:59:04.510110 ==
4323 00:59:04.513239 DQS Delay:
4324 00:59:04.513310 DQS0 = 0, DQS1 = 0
4325 00:59:04.516745 DQM Delay:
4326 00:59:04.516817 DQM0 = 33, DQM1 = 28
4327 00:59:04.516874 DQ Delay:
4328 00:59:04.520290 DQ0 =32, DQ1 =32, DQ2 =32, DQ3 =28
4329 00:59:04.523220 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4330 00:59:04.526711 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4331 00:59:04.530216 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4332 00:59:04.530274
4333 00:59:04.530331
4334 00:59:04.539575 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4335 00:59:04.543625 CH0 RK1: MR19=808, MR18=6E3D
4336 00:59:04.549527 CH0_RK1: MR19=0x808, MR18=0x6E3D, DQSOSC=389, MR23=63, INC=173, DEC=115
4337 00:59:04.549634 [RxdqsGatingPostProcess] freq 600
4338 00:59:04.556337 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4339 00:59:04.559637 Pre-setting of DQS Precalculation
4340 00:59:04.563241 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4341 00:59:04.566374 ==
4342 00:59:04.566448 Dram Type= 6, Freq= 0, CH_1, rank 0
4343 00:59:04.573147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 00:59:04.573222 ==
4345 00:59:04.576306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4346 00:59:04.582912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4347 00:59:04.586632 [CA 0] Center 36 (6~66) winsize 61
4348 00:59:04.589739 [CA 1] Center 36 (6~66) winsize 61
4349 00:59:04.593247 [CA 2] Center 34 (4~65) winsize 62
4350 00:59:04.596844 [CA 3] Center 34 (4~65) winsize 62
4351 00:59:04.599757 [CA 4] Center 34 (3~65) winsize 63
4352 00:59:04.603419 [CA 5] Center 33 (3~64) winsize 62
4353 00:59:04.603512
4354 00:59:04.606326 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4355 00:59:04.606399
4356 00:59:04.609792 [CATrainingPosCal] consider 1 rank data
4357 00:59:04.612913 u2DelayCellTimex100 = 270/100 ps
4358 00:59:04.616517 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4359 00:59:04.622770 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4360 00:59:04.626528 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4361 00:59:04.629491 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4362 00:59:04.633111 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4363 00:59:04.636051 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4364 00:59:04.636120
4365 00:59:04.639590 CA PerBit enable=1, Macro0, CA PI delay=33
4366 00:59:04.639663
4367 00:59:04.642688 [CBTSetCACLKResult] CA Dly = 33
4368 00:59:04.646304 CS Dly: 4 (0~35)
4369 00:59:04.646399 ==
4370 00:59:04.649628 Dram Type= 6, Freq= 0, CH_1, rank 1
4371 00:59:04.652962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 00:59:04.653070 ==
4373 00:59:04.659672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4374 00:59:04.662530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4375 00:59:04.666675 [CA 0] Center 36 (6~66) winsize 61
4376 00:59:04.670349 [CA 1] Center 36 (6~67) winsize 62
4377 00:59:04.673233 [CA 2] Center 34 (4~65) winsize 62
4378 00:59:04.676783 [CA 3] Center 34 (3~65) winsize 63
4379 00:59:04.679862 [CA 4] Center 34 (4~65) winsize 62
4380 00:59:04.683339 [CA 5] Center 34 (3~65) winsize 63
4381 00:59:04.683473
4382 00:59:04.686695 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4383 00:59:04.686796
4384 00:59:04.689884 [CATrainingPosCal] consider 2 rank data
4385 00:59:04.693442 u2DelayCellTimex100 = 270/100 ps
4386 00:59:04.696897 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4387 00:59:04.699744 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4388 00:59:04.706784 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 00:59:04.709849 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 00:59:04.713420 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 00:59:04.716795 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4392 00:59:04.716872
4393 00:59:04.719647 CA PerBit enable=1, Macro0, CA PI delay=33
4394 00:59:04.719748
4395 00:59:04.723118 [CBTSetCACLKResult] CA Dly = 33
4396 00:59:04.723224 CS Dly: 4 (0~36)
4397 00:59:04.723284
4398 00:59:04.726446 ----->DramcWriteLeveling(PI) begin...
4399 00:59:04.729826 ==
4400 00:59:04.732882 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 00:59:04.736191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 00:59:04.736285 ==
4403 00:59:04.739472 Write leveling (Byte 0): 28 => 28
4404 00:59:04.743142 Write leveling (Byte 1): 29 => 29
4405 00:59:04.746094 DramcWriteLeveling(PI) end<-----
4406 00:59:04.746171
4407 00:59:04.746232 ==
4408 00:59:04.749587 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 00:59:04.753100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 00:59:04.753178 ==
4411 00:59:04.756496 [Gating] SW mode calibration
4412 00:59:04.763034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4413 00:59:04.769255 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4414 00:59:04.772711 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 00:59:04.776072 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 00:59:04.782646 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 00:59:04.786088 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4418 00:59:04.789642 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4419 00:59:04.795956 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 00:59:04.799227 0 9 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4421 00:59:04.802780 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 00:59:04.809181 0 10 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4423 00:59:04.812338 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 00:59:04.815642 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 00:59:04.822645 0 10 12 | B1->B0 | 3030 3535 | 1 0 | (0 0) (0 0)
4426 00:59:04.825529 0 10 16 | B1->B0 | 3f3f 4040 | 0 0 | (1 1) (0 0)
4427 00:59:04.829050 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 00:59:04.832554 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:59:04.839190 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 00:59:04.842894 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 00:59:04.845656 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 00:59:04.852551 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 00:59:04.855516 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4434 00:59:04.858999 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4435 00:59:04.865254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:59:04.868810 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:59:04.871865 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:59:04.878450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:59:04.881784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:59:04.885235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:59:04.891848 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:59:04.895533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:59:04.899016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:59:04.905114 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:59:04.908861 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:59:04.911653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:59:04.918481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:59:04.921759 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:59:04.925094 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:59:04.932036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4451 00:59:04.935308 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 00:59:04.938335 Total UI for P1: 0, mck2ui 16
4453 00:59:04.941722 best dqsien dly found for B0: ( 0, 13, 16)
4454 00:59:04.945083 Total UI for P1: 0, mck2ui 16
4455 00:59:04.948617 best dqsien dly found for B1: ( 0, 13, 18)
4456 00:59:04.951896 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4457 00:59:04.955317 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4458 00:59:04.955398
4459 00:59:04.958446 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4460 00:59:04.961333 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4461 00:59:04.964820 [Gating] SW calibration Done
4462 00:59:04.964900 ==
4463 00:59:04.968428 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 00:59:04.974980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 00:59:04.975061 ==
4466 00:59:04.975140 RX Vref Scan: 0
4467 00:59:04.975214
4468 00:59:04.977950 RX Vref 0 -> 0, step: 1
4469 00:59:04.978030
4470 00:59:04.981650 RX Delay -230 -> 252, step: 16
4471 00:59:04.984791 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4472 00:59:04.987875 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4473 00:59:04.991283 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4474 00:59:04.997961 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4475 00:59:05.001523 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4476 00:59:05.004522 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4477 00:59:05.008017 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4478 00:59:05.011256 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4479 00:59:05.018101 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4480 00:59:05.021227 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4481 00:59:05.024811 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4482 00:59:05.027614 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4483 00:59:05.034146 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4484 00:59:05.037810 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4485 00:59:05.041316 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4486 00:59:05.044972 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4487 00:59:05.047863 ==
4488 00:59:05.047939 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 00:59:05.054293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 00:59:05.054369 ==
4491 00:59:05.054428 DQS Delay:
4492 00:59:05.057828 DQS0 = 0, DQS1 = 0
4493 00:59:05.057920 DQM Delay:
4494 00:59:05.060748 DQM0 = 38, DQM1 = 28
4495 00:59:05.060825 DQ Delay:
4496 00:59:05.064489 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4497 00:59:05.067468 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4498 00:59:05.071298 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4499 00:59:05.074132 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4500 00:59:05.074208
4501 00:59:05.074267
4502 00:59:05.074322 ==
4503 00:59:05.077492 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 00:59:05.080533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 00:59:05.080633 ==
4506 00:59:05.080759
4507 00:59:05.080840
4508 00:59:05.084247 TX Vref Scan disable
4509 00:59:05.087264 == TX Byte 0 ==
4510 00:59:05.090814 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4511 00:59:05.094371 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4512 00:59:05.097204 == TX Byte 1 ==
4513 00:59:05.100731 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4514 00:59:05.104066 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4515 00:59:05.104164 ==
4516 00:59:05.107270 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 00:59:05.113894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 00:59:05.113973 ==
4519 00:59:05.114050
4520 00:59:05.114122
4521 00:59:05.114192 TX Vref Scan disable
4522 00:59:05.118281 == TX Byte 0 ==
4523 00:59:05.121596 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4524 00:59:05.128306 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4525 00:59:05.128385 == TX Byte 1 ==
4526 00:59:05.131526 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4527 00:59:05.138000 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4528 00:59:05.138082
4529 00:59:05.138175 [DATLAT]
4530 00:59:05.138265 Freq=600, CH1 RK0
4531 00:59:05.138354
4532 00:59:05.141466 DATLAT Default: 0x9
4533 00:59:05.141553 0, 0xFFFF, sum = 0
4534 00:59:05.144582 1, 0xFFFF, sum = 0
4535 00:59:05.144691 2, 0xFFFF, sum = 0
4536 00:59:05.147673 3, 0xFFFF, sum = 0
4537 00:59:05.151258 4, 0xFFFF, sum = 0
4538 00:59:05.151339 5, 0xFFFF, sum = 0
4539 00:59:05.154660 6, 0xFFFF, sum = 0
4540 00:59:05.154740 7, 0xFFFF, sum = 0
4541 00:59:05.157612 8, 0x0, sum = 1
4542 00:59:05.157692 9, 0x0, sum = 2
4543 00:59:05.157770 10, 0x0, sum = 3
4544 00:59:05.161013 11, 0x0, sum = 4
4545 00:59:05.161093 best_step = 9
4546 00:59:05.161170
4547 00:59:05.161242 ==
4548 00:59:05.164393 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 00:59:05.171227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 00:59:05.171306 ==
4551 00:59:05.171384 RX Vref Scan: 1
4552 00:59:05.171457
4553 00:59:05.174485 RX Vref 0 -> 0, step: 1
4554 00:59:05.174563
4555 00:59:05.177959 RX Delay -195 -> 252, step: 8
4556 00:59:05.178037
4557 00:59:05.180934 Set Vref, RX VrefLevel [Byte0]: 54
4558 00:59:05.184168 [Byte1]: 54
4559 00:59:05.184316
4560 00:59:05.187647 Final RX Vref Byte 0 = 54 to rank0
4561 00:59:05.191359 Final RX Vref Byte 1 = 54 to rank0
4562 00:59:05.194608 Final RX Vref Byte 0 = 54 to rank1
4563 00:59:05.197546 Final RX Vref Byte 1 = 54 to rank1==
4564 00:59:05.201017 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 00:59:05.204115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 00:59:05.204194 ==
4567 00:59:05.207766 DQS Delay:
4568 00:59:05.207844 DQS0 = 0, DQS1 = 0
4569 00:59:05.211096 DQM Delay:
4570 00:59:05.211174 DQM0 = 38, DQM1 = 28
4571 00:59:05.211251 DQ Delay:
4572 00:59:05.214359 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4573 00:59:05.217345 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4574 00:59:05.220822 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4575 00:59:05.224252 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4576 00:59:05.224361
4577 00:59:05.224438
4578 00:59:05.234048 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4579 00:59:05.237505 CH1 RK0: MR19=808, MR18=2A37
4580 00:59:05.244047 CH1_RK0: MR19=0x808, MR18=0x2A37, DQSOSC=399, MR23=63, INC=164, DEC=109
4581 00:59:05.244128
4582 00:59:05.247180 ----->DramcWriteLeveling(PI) begin...
4583 00:59:05.247285 ==
4584 00:59:05.250291 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 00:59:05.253763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 00:59:05.253842 ==
4587 00:59:05.257186 Write leveling (Byte 0): 28 => 28
4588 00:59:05.260544 Write leveling (Byte 1): 32 => 32
4589 00:59:05.264079 DramcWriteLeveling(PI) end<-----
4590 00:59:05.264158
4591 00:59:05.264250 ==
4592 00:59:05.267044 Dram Type= 6, Freq= 0, CH_1, rank 1
4593 00:59:05.270663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 00:59:05.270741 ==
4595 00:59:05.273680 [Gating] SW mode calibration
4596 00:59:05.280132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4597 00:59:05.287013 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4598 00:59:05.290170 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 00:59:05.293552 0 9 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
4600 00:59:05.300023 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 00:59:05.303547 0 9 12 | B1->B0 | 3131 2a2a | 0 1 | (0 0) (1 0)
4602 00:59:05.306570 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4603 00:59:05.313319 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 00:59:05.316789 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 00:59:05.320165 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 00:59:05.326247 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 00:59:05.329775 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 00:59:05.333038 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4609 00:59:05.340048 0 10 12 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
4610 00:59:05.343052 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
4611 00:59:05.346654 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 00:59:05.353206 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 00:59:05.356784 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 00:59:05.359674 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 00:59:05.366732 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 00:59:05.369581 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 00:59:05.373112 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4618 00:59:05.379785 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:59:05.382782 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:59:05.386301 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:59:05.392828 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:59:05.396532 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:59:05.399660 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:59:05.406099 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:59:05.409749 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:59:05.412955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:59:05.419373 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:59:05.422726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:59:05.426252 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:59:05.429347 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:59:05.436440 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:59:05.439446 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:59:05.442824 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 00:59:05.446321 Total UI for P1: 0, mck2ui 16
4635 00:59:05.449184 best dqsien dly found for B0: ( 0, 13, 10)
4636 00:59:05.452596 Total UI for P1: 0, mck2ui 16
4637 00:59:05.455869 best dqsien dly found for B1: ( 0, 13, 10)
4638 00:59:05.459200 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4639 00:59:05.465746 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4640 00:59:05.465824
4641 00:59:05.469216 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4642 00:59:05.472779 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4643 00:59:05.475799 [Gating] SW calibration Done
4644 00:59:05.475890 ==
4645 00:59:05.479358 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 00:59:05.482363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 00:59:05.482438 ==
4648 00:59:05.482496 RX Vref Scan: 0
4649 00:59:05.485806
4650 00:59:05.485873 RX Vref 0 -> 0, step: 1
4651 00:59:05.485929
4652 00:59:05.489334 RX Delay -230 -> 252, step: 16
4653 00:59:05.492238 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4654 00:59:05.499273 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4655 00:59:05.502266 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4656 00:59:05.505855 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4657 00:59:05.509490 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4658 00:59:05.512409 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4659 00:59:05.519328 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4660 00:59:05.522323 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4661 00:59:05.525719 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4662 00:59:05.529030 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4663 00:59:05.535285 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4664 00:59:05.538804 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4665 00:59:05.542345 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4666 00:59:05.545243 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4667 00:59:05.551947 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4668 00:59:05.555335 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4669 00:59:05.555412 ==
4670 00:59:05.558396 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 00:59:05.561894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 00:59:05.561971 ==
4673 00:59:05.565423 DQS Delay:
4674 00:59:05.565500 DQS0 = 0, DQS1 = 0
4675 00:59:05.565560 DQM Delay:
4676 00:59:05.568709 DQM0 = 40, DQM1 = 34
4677 00:59:05.568786 DQ Delay:
4678 00:59:05.572068 DQ0 =41, DQ1 =41, DQ2 =17, DQ3 =41
4679 00:59:05.575318 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4680 00:59:05.578397 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4681 00:59:05.581690 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4682 00:59:05.581767
4683 00:59:05.581827
4684 00:59:05.581882 ==
4685 00:59:05.585359 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 00:59:05.591978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 00:59:05.592077 ==
4688 00:59:05.592162
4689 00:59:05.592243
4690 00:59:05.592324 TX Vref Scan disable
4691 00:59:05.595571 == TX Byte 0 ==
4692 00:59:05.599079 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4693 00:59:05.605630 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4694 00:59:05.605698 == TX Byte 1 ==
4695 00:59:05.608534 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4696 00:59:05.615089 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4697 00:59:05.615185 ==
4698 00:59:05.618629 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 00:59:05.622089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 00:59:05.622165 ==
4701 00:59:05.622224
4702 00:59:05.622277
4703 00:59:05.625574 TX Vref Scan disable
4704 00:59:05.628569 == TX Byte 0 ==
4705 00:59:05.631848 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4706 00:59:05.635245 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4707 00:59:05.638800 == TX Byte 1 ==
4708 00:59:05.641568 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4709 00:59:05.645026 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4710 00:59:05.645102
4711 00:59:05.645161 [DATLAT]
4712 00:59:05.648569 Freq=600, CH1 RK1
4713 00:59:05.648649
4714 00:59:05.652122 DATLAT Default: 0x9
4715 00:59:05.652197 0, 0xFFFF, sum = 0
4716 00:59:05.655201 1, 0xFFFF, sum = 0
4717 00:59:05.655278 2, 0xFFFF, sum = 0
4718 00:59:05.658358 3, 0xFFFF, sum = 0
4719 00:59:05.658435 4, 0xFFFF, sum = 0
4720 00:59:05.661947 5, 0xFFFF, sum = 0
4721 00:59:05.662024 6, 0xFFFF, sum = 0
4722 00:59:05.665074 7, 0xFFFF, sum = 0
4723 00:59:05.665150 8, 0x0, sum = 1
4724 00:59:05.668504 9, 0x0, sum = 2
4725 00:59:05.668580 10, 0x0, sum = 3
4726 00:59:05.671405 11, 0x0, sum = 4
4727 00:59:05.671482 best_step = 9
4728 00:59:05.671540
4729 00:59:05.671593 ==
4730 00:59:05.674882 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 00:59:05.678485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 00:59:05.678561 ==
4733 00:59:05.681584 RX Vref Scan: 0
4734 00:59:05.681659
4735 00:59:05.684533 RX Vref 0 -> 0, step: 1
4736 00:59:05.684608
4737 00:59:05.684703 RX Delay -195 -> 252, step: 8
4738 00:59:05.692540 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4739 00:59:05.696001 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4740 00:59:05.699251 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4741 00:59:05.702398 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4742 00:59:05.709085 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4743 00:59:05.712797 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4744 00:59:05.715541 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4745 00:59:05.719058 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4746 00:59:05.725990 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4747 00:59:05.729455 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4748 00:59:05.732298 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4749 00:59:05.735763 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4750 00:59:05.739008 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4751 00:59:05.745281 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4752 00:59:05.748902 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4753 00:59:05.752454 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4754 00:59:05.752545 ==
4755 00:59:05.755363 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 00:59:05.762576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 00:59:05.762651 ==
4758 00:59:05.762710 DQS Delay:
4759 00:59:05.762765 DQS0 = 0, DQS1 = 0
4760 00:59:05.765619 DQM Delay:
4761 00:59:05.765686 DQM0 = 36, DQM1 = 29
4762 00:59:05.768838 DQ Delay:
4763 00:59:05.772351 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4764 00:59:05.772446 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4765 00:59:05.775190 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4766 00:59:05.782010 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4767 00:59:05.782084
4768 00:59:05.782142
4769 00:59:05.788578 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4770 00:59:05.792363 CH1 RK1: MR19=808, MR18=3959
4771 00:59:05.799041 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4772 00:59:05.801905 [RxdqsGatingPostProcess] freq 600
4773 00:59:05.805528 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4774 00:59:05.808901 Pre-setting of DQS Precalculation
4775 00:59:05.815360 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4776 00:59:05.822142 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4777 00:59:05.828941 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4778 00:59:05.829034
4779 00:59:05.829108
4780 00:59:05.832023 [Calibration Summary] 1200 Mbps
4781 00:59:05.832098 CH 0, Rank 0
4782 00:59:05.835318 SW Impedance : PASS
4783 00:59:05.838568 DUTY Scan : NO K
4784 00:59:05.838644 ZQ Calibration : PASS
4785 00:59:05.841615 Jitter Meter : NO K
4786 00:59:05.845063 CBT Training : PASS
4787 00:59:05.845161 Write leveling : PASS
4788 00:59:05.848468 RX DQS gating : PASS
4789 00:59:05.851997 RX DQ/DQS(RDDQC) : PASS
4790 00:59:05.852074 TX DQ/DQS : PASS
4791 00:59:05.855152 RX DATLAT : PASS
4792 00:59:05.855227 RX DQ/DQS(Engine): PASS
4793 00:59:05.858599 TX OE : NO K
4794 00:59:05.858693 All Pass.
4795 00:59:05.858778
4796 00:59:05.861727 CH 0, Rank 1
4797 00:59:05.861798 SW Impedance : PASS
4798 00:59:05.865281 DUTY Scan : NO K
4799 00:59:05.868233 ZQ Calibration : PASS
4800 00:59:05.868302 Jitter Meter : NO K
4801 00:59:05.871741 CBT Training : PASS
4802 00:59:05.874847 Write leveling : PASS
4803 00:59:05.874939 RX DQS gating : PASS
4804 00:59:05.878307 RX DQ/DQS(RDDQC) : PASS
4805 00:59:05.881650 TX DQ/DQS : PASS
4806 00:59:05.881726 RX DATLAT : PASS
4807 00:59:05.885086 RX DQ/DQS(Engine): PASS
4808 00:59:05.888040 TX OE : NO K
4809 00:59:05.888133 All Pass.
4810 00:59:05.888224
4811 00:59:05.888306 CH 1, Rank 0
4812 00:59:05.891710 SW Impedance : PASS
4813 00:59:05.894684 DUTY Scan : NO K
4814 00:59:05.894774 ZQ Calibration : PASS
4815 00:59:05.898299 Jitter Meter : NO K
4816 00:59:05.901288 CBT Training : PASS
4817 00:59:05.901394 Write leveling : PASS
4818 00:59:05.904823 RX DQS gating : PASS
4819 00:59:05.907770 RX DQ/DQS(RDDQC) : PASS
4820 00:59:05.907867 TX DQ/DQS : PASS
4821 00:59:05.911291 RX DATLAT : PASS
4822 00:59:05.914753 RX DQ/DQS(Engine): PASS
4823 00:59:05.914850 TX OE : NO K
4824 00:59:05.914916 All Pass.
4825 00:59:05.914970
4826 00:59:05.917706 CH 1, Rank 1
4827 00:59:05.921280 SW Impedance : PASS
4828 00:59:05.921346 DUTY Scan : NO K
4829 00:59:05.924640 ZQ Calibration : PASS
4830 00:59:05.924772 Jitter Meter : NO K
4831 00:59:05.928183 CBT Training : PASS
4832 00:59:05.931415 Write leveling : PASS
4833 00:59:05.931487 RX DQS gating : PASS
4834 00:59:05.934639 RX DQ/DQS(RDDQC) : PASS
4835 00:59:05.937917 TX DQ/DQS : PASS
4836 00:59:05.938008 RX DATLAT : PASS
4837 00:59:05.941395 RX DQ/DQS(Engine): PASS
4838 00:59:05.944620 TX OE : NO K
4839 00:59:05.944752 All Pass.
4840 00:59:05.944811
4841 00:59:05.947951 DramC Write-DBI off
4842 00:59:05.948020 PER_BANK_REFRESH: Hybrid Mode
4843 00:59:05.950973 TX_TRACKING: ON
4844 00:59:05.957641 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4845 00:59:05.961026 [FAST_K] Save calibration result to emmc
4846 00:59:05.967680 dramc_set_vcore_voltage set vcore to 662500
4847 00:59:05.967777 Read voltage for 933, 3
4848 00:59:05.970904 Vio18 = 0
4849 00:59:05.970994 Vcore = 662500
4850 00:59:05.971078 Vdram = 0
4851 00:59:05.974371 Vddq = 0
4852 00:59:05.974460 Vmddr = 0
4853 00:59:05.977926 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4854 00:59:05.984573 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4855 00:59:05.987507 MEM_TYPE=3, freq_sel=17
4856 00:59:05.991020 sv_algorithm_assistance_LP4_1600
4857 00:59:05.994037 ============ PULL DRAM RESETB DOWN ============
4858 00:59:05.997574 ========== PULL DRAM RESETB DOWN end =========
4859 00:59:06.004078 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 00:59:06.007680 ===================================
4861 00:59:06.007750 LPDDR4 DRAM CONFIGURATION
4862 00:59:06.010558 ===================================
4863 00:59:06.014100 EX_ROW_EN[0] = 0x0
4864 00:59:06.014168 EX_ROW_EN[1] = 0x0
4865 00:59:06.017599 LP4Y_EN = 0x0
4866 00:59:06.017665 WORK_FSP = 0x0
4867 00:59:06.020502 WL = 0x3
4868 00:59:06.023933 RL = 0x3
4869 00:59:06.024002 BL = 0x2
4870 00:59:06.026983 RPST = 0x0
4871 00:59:06.027048 RD_PRE = 0x0
4872 00:59:06.030533 WR_PRE = 0x1
4873 00:59:06.030598 WR_PST = 0x0
4874 00:59:06.033948 DBI_WR = 0x0
4875 00:59:06.034011 DBI_RD = 0x0
4876 00:59:06.036819 OTF = 0x1
4877 00:59:06.040228 ===================================
4878 00:59:06.043897 ===================================
4879 00:59:06.043988 ANA top config
4880 00:59:06.047009 ===================================
4881 00:59:06.050575 DLL_ASYNC_EN = 0
4882 00:59:06.053427 ALL_SLAVE_EN = 1
4883 00:59:06.053518 NEW_RANK_MODE = 1
4884 00:59:06.056976 DLL_IDLE_MODE = 1
4885 00:59:06.059995 LP45_APHY_COMB_EN = 1
4886 00:59:06.063509 TX_ODT_DIS = 1
4887 00:59:06.066775 NEW_8X_MODE = 1
4888 00:59:06.070287 ===================================
4889 00:59:06.073315 ===================================
4890 00:59:06.073405 data_rate = 1866
4891 00:59:06.076586 CKR = 1
4892 00:59:06.080020 DQ_P2S_RATIO = 8
4893 00:59:06.083350 ===================================
4894 00:59:06.086660 CA_P2S_RATIO = 8
4895 00:59:06.089957 DQ_CA_OPEN = 0
4896 00:59:06.093276 DQ_SEMI_OPEN = 0
4897 00:59:06.093370 CA_SEMI_OPEN = 0
4898 00:59:06.096875 CA_FULL_RATE = 0
4899 00:59:06.100002 DQ_CKDIV4_EN = 1
4900 00:59:06.103165 CA_CKDIV4_EN = 1
4901 00:59:06.106299 CA_PREDIV_EN = 0
4902 00:59:06.109908 PH8_DLY = 0
4903 00:59:06.110004 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4904 00:59:06.113473 DQ_AAMCK_DIV = 4
4905 00:59:06.116390 CA_AAMCK_DIV = 4
4906 00:59:06.119359 CA_ADMCK_DIV = 4
4907 00:59:06.122844 DQ_TRACK_CA_EN = 0
4908 00:59:06.126200 CA_PICK = 933
4909 00:59:06.129705 CA_MCKIO = 933
4910 00:59:06.129802 MCKIO_SEMI = 0
4911 00:59:06.133145 PLL_FREQ = 3732
4912 00:59:06.136083 DQ_UI_PI_RATIO = 32
4913 00:59:06.139376 CA_UI_PI_RATIO = 0
4914 00:59:06.142926 ===================================
4915 00:59:06.146420 ===================================
4916 00:59:06.149225 memory_type:LPDDR4
4917 00:59:06.149308 GP_NUM : 10
4918 00:59:06.152414 SRAM_EN : 1
4919 00:59:06.156124 MD32_EN : 0
4920 00:59:06.159669 ===================================
4921 00:59:06.159766 [ANA_INIT] >>>>>>>>>>>>>>
4922 00:59:06.162697 <<<<<< [CONFIGURE PHASE]: ANA_TX
4923 00:59:06.166222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4924 00:59:06.169163 ===================================
4925 00:59:06.172688 data_rate = 1866,PCW = 0X8f00
4926 00:59:06.176118 ===================================
4927 00:59:06.179364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4928 00:59:06.186221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 00:59:06.189102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 00:59:06.196080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4931 00:59:06.199317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4932 00:59:06.202469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4933 00:59:06.202564 [ANA_INIT] flow start
4934 00:59:06.206076 [ANA_INIT] PLL >>>>>>>>
4935 00:59:06.208961 [ANA_INIT] PLL <<<<<<<<
4936 00:59:06.209110 [ANA_INIT] MIDPI >>>>>>>>
4937 00:59:06.212529 [ANA_INIT] MIDPI <<<<<<<<
4938 00:59:06.215844 [ANA_INIT] DLL >>>>>>>>
4939 00:59:06.215938 [ANA_INIT] flow end
4940 00:59:06.222610 ============ LP4 DIFF to SE enter ============
4941 00:59:06.225552 ============ LP4 DIFF to SE exit ============
4942 00:59:06.228832 [ANA_INIT] <<<<<<<<<<<<<
4943 00:59:06.232511 [Flow] Enable top DCM control >>>>>
4944 00:59:06.235509 [Flow] Enable top DCM control <<<<<
4945 00:59:06.235602 Enable DLL master slave shuffle
4946 00:59:06.242725 ==============================================================
4947 00:59:06.245632 Gating Mode config
4948 00:59:06.249310 ==============================================================
4949 00:59:06.252255 Config description:
4950 00:59:06.262445 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4951 00:59:06.268850 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4952 00:59:06.272401 SELPH_MODE 0: By rank 1: By Phase
4953 00:59:06.279204 ==============================================================
4954 00:59:06.282130 GAT_TRACK_EN = 1
4955 00:59:06.285337 RX_GATING_MODE = 2
4956 00:59:06.289199 RX_GATING_TRACK_MODE = 2
4957 00:59:06.292337 SELPH_MODE = 1
4958 00:59:06.292458 PICG_EARLY_EN = 1
4959 00:59:06.295758 VALID_LAT_VALUE = 1
4960 00:59:06.302084 ==============================================================
4961 00:59:06.305654 Enter into Gating configuration >>>>
4962 00:59:06.309074 Exit from Gating configuration <<<<
4963 00:59:06.312143 Enter into DVFS_PRE_config >>>>>
4964 00:59:06.322319 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4965 00:59:06.325315 Exit from DVFS_PRE_config <<<<<
4966 00:59:06.328635 Enter into PICG configuration >>>>
4967 00:59:06.332188 Exit from PICG configuration <<<<
4968 00:59:06.335674 [RX_INPUT] configuration >>>>>
4969 00:59:06.339019 [RX_INPUT] configuration <<<<<
4970 00:59:06.342393 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4971 00:59:06.348848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4972 00:59:06.355790 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 00:59:06.361712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 00:59:06.368813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 00:59:06.372160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 00:59:06.378430 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4977 00:59:06.381695 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4978 00:59:06.385247 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4979 00:59:06.388735 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4980 00:59:06.394870 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4981 00:59:06.398561 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 00:59:06.401876 ===================================
4983 00:59:06.405289 LPDDR4 DRAM CONFIGURATION
4984 00:59:06.408249 ===================================
4985 00:59:06.408339 EX_ROW_EN[0] = 0x0
4986 00:59:06.411805 EX_ROW_EN[1] = 0x0
4987 00:59:06.411873 LP4Y_EN = 0x0
4988 00:59:06.415245 WORK_FSP = 0x0
4989 00:59:06.415318 WL = 0x3
4990 00:59:06.418110 RL = 0x3
4991 00:59:06.418178 BL = 0x2
4992 00:59:06.421575 RPST = 0x0
4993 00:59:06.425151 RD_PRE = 0x0
4994 00:59:06.425219 WR_PRE = 0x1
4995 00:59:06.428198 WR_PST = 0x0
4996 00:59:06.428288 DBI_WR = 0x0
4997 00:59:06.431773 DBI_RD = 0x0
4998 00:59:06.431841 OTF = 0x1
4999 00:59:06.434491 ===================================
5000 00:59:06.438413 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5001 00:59:06.444599 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5002 00:59:06.448120 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 00:59:06.451160 ===================================
5004 00:59:06.454564 LPDDR4 DRAM CONFIGURATION
5005 00:59:06.458238 ===================================
5006 00:59:06.458310 EX_ROW_EN[0] = 0x10
5007 00:59:06.461452 EX_ROW_EN[1] = 0x0
5008 00:59:06.461521 LP4Y_EN = 0x0
5009 00:59:06.464487 WORK_FSP = 0x0
5010 00:59:06.464581 WL = 0x3
5011 00:59:06.468025 RL = 0x3
5012 00:59:06.468116 BL = 0x2
5013 00:59:06.470965 RPST = 0x0
5014 00:59:06.471032 RD_PRE = 0x0
5015 00:59:06.474437 WR_PRE = 0x1
5016 00:59:06.474527 WR_PST = 0x0
5017 00:59:06.477858 DBI_WR = 0x0
5018 00:59:06.481256 DBI_RD = 0x0
5019 00:59:06.481323 OTF = 0x1
5020 00:59:06.484316 ===================================
5021 00:59:06.491083 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5022 00:59:06.494783 nWR fixed to 30
5023 00:59:06.497724 [ModeRegInit_LP4] CH0 RK0
5024 00:59:06.497797 [ModeRegInit_LP4] CH0 RK1
5025 00:59:06.501210 [ModeRegInit_LP4] CH1 RK0
5026 00:59:06.504423 [ModeRegInit_LP4] CH1 RK1
5027 00:59:06.504521 match AC timing 9
5028 00:59:06.511233 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5029 00:59:06.514858 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5030 00:59:06.517755 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5031 00:59:06.524338 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5032 00:59:06.527831 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5033 00:59:06.527923 ==
5034 00:59:06.531468 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 00:59:06.534397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5036 00:59:06.534496 ==
5037 00:59:06.541312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5038 00:59:06.547407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5039 00:59:06.550917 [CA 0] Center 38 (8~69) winsize 62
5040 00:59:06.554393 [CA 1] Center 38 (7~69) winsize 63
5041 00:59:06.557506 [CA 2] Center 35 (5~66) winsize 62
5042 00:59:06.560805 [CA 3] Center 35 (5~66) winsize 62
5043 00:59:06.564428 [CA 4] Center 34 (4~65) winsize 62
5044 00:59:06.567371 [CA 5] Center 33 (3~64) winsize 62
5045 00:59:06.567462
5046 00:59:06.570603 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5047 00:59:06.570688
5048 00:59:06.573937 [CATrainingPosCal] consider 1 rank data
5049 00:59:06.577819 u2DelayCellTimex100 = 270/100 ps
5050 00:59:06.580870 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5051 00:59:06.584300 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5052 00:59:06.587497 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5053 00:59:06.590950 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5054 00:59:06.593900 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5055 00:59:06.601009 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5056 00:59:06.601124
5057 00:59:06.604031 CA PerBit enable=1, Macro0, CA PI delay=33
5058 00:59:06.604123
5059 00:59:06.607585 [CBTSetCACLKResult] CA Dly = 33
5060 00:59:06.607674 CS Dly: 7 (0~38)
5061 00:59:06.607755 ==
5062 00:59:06.610492 Dram Type= 6, Freq= 0, CH_0, rank 1
5063 00:59:06.614035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 00:59:06.617194 ==
5065 00:59:06.620852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 00:59:06.627417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5067 00:59:06.630326 [CA 0] Center 38 (8~69) winsize 62
5068 00:59:06.633991 [CA 1] Center 38 (7~69) winsize 63
5069 00:59:06.637077 [CA 2] Center 35 (5~66) winsize 62
5070 00:59:06.640194 [CA 3] Center 35 (5~66) winsize 62
5071 00:59:06.643824 [CA 4] Center 34 (4~65) winsize 62
5072 00:59:06.647239 [CA 5] Center 34 (4~64) winsize 61
5073 00:59:06.647307
5074 00:59:06.650627 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5075 00:59:06.650693
5076 00:59:06.654004 [CATrainingPosCal] consider 2 rank data
5077 00:59:06.657008 u2DelayCellTimex100 = 270/100 ps
5078 00:59:06.660569 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5079 00:59:06.663461 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5080 00:59:06.666863 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5081 00:59:06.673700 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5082 00:59:06.677047 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 00:59:06.680402 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 00:59:06.680473
5085 00:59:06.683690 CA PerBit enable=1, Macro0, CA PI delay=34
5086 00:59:06.683780
5087 00:59:06.687100 [CBTSetCACLKResult] CA Dly = 34
5088 00:59:06.687197 CS Dly: 7 (0~38)
5089 00:59:06.687281
5090 00:59:06.690575 ----->DramcWriteLeveling(PI) begin...
5091 00:59:06.690666 ==
5092 00:59:06.693762 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 00:59:06.699959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 00:59:06.700051 ==
5095 00:59:06.703569 Write leveling (Byte 0): 31 => 31
5096 00:59:06.707075 Write leveling (Byte 1): 29 => 29
5097 00:59:06.707164 DramcWriteLeveling(PI) end<-----
5098 00:59:06.707275
5099 00:59:06.709932 ==
5100 00:59:06.713434 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 00:59:06.716587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 00:59:06.716683 ==
5103 00:59:06.720301 [Gating] SW mode calibration
5104 00:59:06.726869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 00:59:06.730109 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5106 00:59:06.736672 0 14 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5107 00:59:06.740107 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5108 00:59:06.743721 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 00:59:06.749921 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 00:59:06.753546 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 00:59:06.756921 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 00:59:06.763521 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 00:59:06.767098 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5114 00:59:06.769998 0 15 0 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (1 1)
5115 00:59:06.776555 0 15 4 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5116 00:59:06.779814 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 00:59:06.783394 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 00:59:06.789798 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 00:59:06.793114 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 00:59:06.796916 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 00:59:06.803230 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5122 00:59:06.806842 1 0 0 | B1->B0 | 2828 3e3e | 0 0 | (0 0) (0 0)
5123 00:59:06.809968 1 0 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5124 00:59:06.816282 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 00:59:06.819787 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 00:59:06.822909 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 00:59:06.829537 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 00:59:06.832640 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 00:59:06.836291 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 00:59:06.842683 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5131 00:59:06.845777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 00:59:06.849237 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:59:06.855847 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:59:06.859356 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:59:06.862823 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:59:06.866154 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:59:06.872570 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:59:06.875771 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:59:06.882325 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:59:06.885482 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:59:06.889159 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:59:06.895582 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:59:06.898867 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:59:06.902020 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:59:06.905450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5146 00:59:06.912050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5147 00:59:06.915544 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5148 00:59:06.918636 Total UI for P1: 0, mck2ui 16
5149 00:59:06.922070 best dqsien dly found for B0: ( 1, 2, 30)
5150 00:59:06.925100 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 00:59:06.928813 Total UI for P1: 0, mck2ui 16
5152 00:59:06.931902 best dqsien dly found for B1: ( 1, 3, 2)
5153 00:59:06.934973 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5154 00:59:06.938784 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5155 00:59:06.941859
5156 00:59:06.944967 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5157 00:59:06.948651 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5158 00:59:06.951626 [Gating] SW calibration Done
5159 00:59:06.951725 ==
5160 00:59:06.955073 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 00:59:06.958404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 00:59:06.958495 ==
5163 00:59:06.958579 RX Vref Scan: 0
5164 00:59:06.958703
5165 00:59:06.961810 RX Vref 0 -> 0, step: 1
5166 00:59:06.961876
5167 00:59:06.964862 RX Delay -80 -> 252, step: 8
5168 00:59:06.968609 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5169 00:59:06.971510 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5170 00:59:06.974877 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5171 00:59:06.981495 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5172 00:59:06.984968 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5173 00:59:06.988016 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5174 00:59:06.991657 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5175 00:59:06.994829 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5176 00:59:07.001329 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5177 00:59:07.004838 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5178 00:59:07.007970 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5179 00:59:07.011228 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5180 00:59:07.014598 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5181 00:59:07.021509 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5182 00:59:07.024605 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5183 00:59:07.028137 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5184 00:59:07.028234 ==
5185 00:59:07.031189 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 00:59:07.034290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 00:59:07.034448 ==
5188 00:59:07.038068 DQS Delay:
5189 00:59:07.038177 DQS0 = 0, DQS1 = 0
5190 00:59:07.041038 DQM Delay:
5191 00:59:07.041123 DQM0 = 95, DQM1 = 83
5192 00:59:07.041178 DQ Delay:
5193 00:59:07.044209 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5194 00:59:07.047362 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =111
5195 00:59:07.050977 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5196 00:59:07.054570 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5197 00:59:07.057613
5198 00:59:07.057695
5199 00:59:07.057770 ==
5200 00:59:07.061125 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 00:59:07.063937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 00:59:07.064030 ==
5203 00:59:07.064121
5204 00:59:07.064202
5205 00:59:07.067795 TX Vref Scan disable
5206 00:59:07.067891 == TX Byte 0 ==
5207 00:59:07.074368 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5208 00:59:07.077712 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5209 00:59:07.077804 == TX Byte 1 ==
5210 00:59:07.084488 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5211 00:59:07.087395 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5212 00:59:07.087491 ==
5213 00:59:07.090873 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 00:59:07.094055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 00:59:07.094149 ==
5216 00:59:07.094241
5217 00:59:07.094322
5218 00:59:07.097567 TX Vref Scan disable
5219 00:59:07.100790 == TX Byte 0 ==
5220 00:59:07.104452 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5221 00:59:07.107582 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5222 00:59:07.110500 == TX Byte 1 ==
5223 00:59:07.113886 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5224 00:59:07.117339 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5225 00:59:07.117410
5226 00:59:07.120995 [DATLAT]
5227 00:59:07.121066 Freq=933, CH0 RK0
5228 00:59:07.121130
5229 00:59:07.123914 DATLAT Default: 0xd
5230 00:59:07.124003 0, 0xFFFF, sum = 0
5231 00:59:07.127345 1, 0xFFFF, sum = 0
5232 00:59:07.127434 2, 0xFFFF, sum = 0
5233 00:59:07.130806 3, 0xFFFF, sum = 0
5234 00:59:07.130909 4, 0xFFFF, sum = 0
5235 00:59:07.133562 5, 0xFFFF, sum = 0
5236 00:59:07.133641 6, 0xFFFF, sum = 0
5237 00:59:07.137308 7, 0xFFFF, sum = 0
5238 00:59:07.137399 8, 0xFFFF, sum = 0
5239 00:59:07.140389 9, 0xFFFF, sum = 0
5240 00:59:07.140487 10, 0x0, sum = 1
5241 00:59:07.143493 11, 0x0, sum = 2
5242 00:59:07.143619 12, 0x0, sum = 3
5243 00:59:07.147091 13, 0x0, sum = 4
5244 00:59:07.147185 best_step = 11
5245 00:59:07.147266
5246 00:59:07.147344 ==
5247 00:59:07.150693 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 00:59:07.156828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 00:59:07.156937 ==
5250 00:59:07.157052 RX Vref Scan: 1
5251 00:59:07.157165
5252 00:59:07.160379 RX Vref 0 -> 0, step: 1
5253 00:59:07.160469
5254 00:59:07.163395 RX Delay -69 -> 252, step: 4
5255 00:59:07.163501
5256 00:59:07.166964 Set Vref, RX VrefLevel [Byte0]: 64
5257 00:59:07.169935 [Byte1]: 49
5258 00:59:07.170038
5259 00:59:07.173546 Final RX Vref Byte 0 = 64 to rank0
5260 00:59:07.176568 Final RX Vref Byte 1 = 49 to rank0
5261 00:59:07.180276 Final RX Vref Byte 0 = 64 to rank1
5262 00:59:07.183211 Final RX Vref Byte 1 = 49 to rank1==
5263 00:59:07.186894 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 00:59:07.189715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 00:59:07.189801 ==
5266 00:59:07.193260 DQS Delay:
5267 00:59:07.193343 DQS0 = 0, DQS1 = 0
5268 00:59:07.196869 DQM Delay:
5269 00:59:07.196948 DQM0 = 96, DQM1 = 83
5270 00:59:07.197053 DQ Delay:
5271 00:59:07.199983 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5272 00:59:07.203360 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5273 00:59:07.206568 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5274 00:59:07.209563 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5275 00:59:07.209630
5276 00:59:07.212775
5277 00:59:07.219669 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5278 00:59:07.222915 CH0 RK0: MR19=505, MR18=1312
5279 00:59:07.229420 CH0_RK0: MR19=0x505, MR18=0x1312, DQSOSC=415, MR23=63, INC=62, DEC=41
5280 00:59:07.229494
5281 00:59:07.232995 ----->DramcWriteLeveling(PI) begin...
5282 00:59:07.233068 ==
5283 00:59:07.236493 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 00:59:07.239307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 00:59:07.239401 ==
5286 00:59:07.242690 Write leveling (Byte 0): 33 => 33
5287 00:59:07.246280 Write leveling (Byte 1): 33 => 33
5288 00:59:07.249768 DramcWriteLeveling(PI) end<-----
5289 00:59:07.249863
5290 00:59:07.249947 ==
5291 00:59:07.252763 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 00:59:07.256128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:59:07.256223 ==
5294 00:59:07.259626 [Gating] SW mode calibration
5295 00:59:07.266054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 00:59:07.272432 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 00:59:07.275765 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5298 00:59:07.279357 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 00:59:07.285803 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 00:59:07.289376 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 00:59:07.292388 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 00:59:07.299297 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 00:59:07.302691 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5304 00:59:07.305998 0 14 28 | B1->B0 | 3131 2424 | 1 0 | (1 1) (0 0)
5305 00:59:07.312222 0 15 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
5306 00:59:07.315704 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 00:59:07.318741 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 00:59:07.325776 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 00:59:07.328748 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 00:59:07.332467 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 00:59:07.338915 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 00:59:07.342428 0 15 28 | B1->B0 | 2424 3e3e | 0 1 | (0 0) (0 0)
5313 00:59:07.345436 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5314 00:59:07.352324 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 00:59:07.355609 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 00:59:07.358740 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 00:59:07.365363 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 00:59:07.368790 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 00:59:07.372419 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 00:59:07.378877 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5321 00:59:07.382454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5322 00:59:07.385343 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:59:07.388901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:59:07.395443 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:59:07.398813 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:59:07.402090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:59:07.408586 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 00:59:07.412114 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 00:59:07.415514 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:59:07.422136 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:59:07.425437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:59:07.428841 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:59:07.435326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:59:07.438710 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:59:07.441792 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5336 00:59:07.448596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 00:59:07.451835 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 00:59:07.455364 Total UI for P1: 0, mck2ui 16
5339 00:59:07.458326 best dqsien dly found for B0: ( 1, 2, 26)
5340 00:59:07.461938 Total UI for P1: 0, mck2ui 16
5341 00:59:07.465265 best dqsien dly found for B1: ( 1, 2, 28)
5342 00:59:07.468559 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5343 00:59:07.471733 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5344 00:59:07.471829
5345 00:59:07.475005 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5346 00:59:07.478225 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5347 00:59:07.481901 [Gating] SW calibration Done
5348 00:59:07.481993 ==
5349 00:59:07.484750 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 00:59:07.488411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 00:59:07.491568 ==
5352 00:59:07.491659 RX Vref Scan: 0
5353 00:59:07.491744
5354 00:59:07.494729 RX Vref 0 -> 0, step: 1
5355 00:59:07.494815
5356 00:59:07.498346 RX Delay -80 -> 252, step: 8
5357 00:59:07.501476 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5358 00:59:07.504953 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5359 00:59:07.508311 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5360 00:59:07.511351 iDelay=208, Bit 3, Center 83 (-16 ~ 183) 200
5361 00:59:07.518127 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5362 00:59:07.521617 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5363 00:59:07.524583 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5364 00:59:07.528430 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5365 00:59:07.531287 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5366 00:59:07.534833 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5367 00:59:07.541182 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5368 00:59:07.544622 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5369 00:59:07.547916 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5370 00:59:07.551484 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5371 00:59:07.554593 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5372 00:59:07.561385 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5373 00:59:07.561478 ==
5374 00:59:07.565030 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 00:59:07.567906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 00:59:07.567975 ==
5377 00:59:07.568033 DQS Delay:
5378 00:59:07.571511 DQS0 = 0, DQS1 = 0
5379 00:59:07.571602 DQM Delay:
5380 00:59:07.574424 DQM0 = 91, DQM1 = 84
5381 00:59:07.574488 DQ Delay:
5382 00:59:07.577838 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =83
5383 00:59:07.581535 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5384 00:59:07.584824 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5385 00:59:07.587786 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5386 00:59:07.587894
5387 00:59:07.588005
5388 00:59:07.588117 ==
5389 00:59:07.590938 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 00:59:07.594654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 00:59:07.597738 ==
5392 00:59:07.597876
5393 00:59:07.597987
5394 00:59:07.598099 TX Vref Scan disable
5395 00:59:07.601363 == TX Byte 0 ==
5396 00:59:07.604405 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5397 00:59:07.608058 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5398 00:59:07.610932 == TX Byte 1 ==
5399 00:59:07.614408 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5400 00:59:07.617925 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5401 00:59:07.618029 ==
5402 00:59:07.620831 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 00:59:07.627686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 00:59:07.627791 ==
5405 00:59:07.627874
5406 00:59:07.627953
5407 00:59:07.628031 TX Vref Scan disable
5408 00:59:07.632221 == TX Byte 0 ==
5409 00:59:07.635016 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5410 00:59:07.641743 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5411 00:59:07.641839 == TX Byte 1 ==
5412 00:59:07.645373 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5413 00:59:07.651802 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5414 00:59:07.651875
5415 00:59:07.651935 [DATLAT]
5416 00:59:07.651990 Freq=933, CH0 RK1
5417 00:59:07.652042
5418 00:59:07.655279 DATLAT Default: 0xb
5419 00:59:07.655370 0, 0xFFFF, sum = 0
5420 00:59:07.658796 1, 0xFFFF, sum = 0
5421 00:59:07.658889 2, 0xFFFF, sum = 0
5422 00:59:07.661582 3, 0xFFFF, sum = 0
5423 00:59:07.664978 4, 0xFFFF, sum = 0
5424 00:59:07.665044 5, 0xFFFF, sum = 0
5425 00:59:07.668741 6, 0xFFFF, sum = 0
5426 00:59:07.668830 7, 0xFFFF, sum = 0
5427 00:59:07.671394 8, 0xFFFF, sum = 0
5428 00:59:07.671487 9, 0xFFFF, sum = 0
5429 00:59:07.674865 10, 0x0, sum = 1
5430 00:59:07.674959 11, 0x0, sum = 2
5431 00:59:07.678340 12, 0x0, sum = 3
5432 00:59:07.678406 13, 0x0, sum = 4
5433 00:59:07.678462 best_step = 11
5434 00:59:07.681426
5435 00:59:07.681507 ==
5436 00:59:07.684756 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 00:59:07.687995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 00:59:07.688096 ==
5439 00:59:07.688183 RX Vref Scan: 0
5440 00:59:07.688269
5441 00:59:07.691491 RX Vref 0 -> 0, step: 1
5442 00:59:07.691568
5443 00:59:07.694977 RX Delay -69 -> 252, step: 4
5444 00:59:07.701810 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5445 00:59:07.704870 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5446 00:59:07.707852 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5447 00:59:07.711408 iDelay=199, Bit 3, Center 88 (-5 ~ 182) 188
5448 00:59:07.714302 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5449 00:59:07.718044 iDelay=199, Bit 5, Center 78 (-13 ~ 170) 184
5450 00:59:07.724753 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5451 00:59:07.727575 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5452 00:59:07.731110 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5453 00:59:07.734201 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5454 00:59:07.737919 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5455 00:59:07.744160 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5456 00:59:07.748026 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5457 00:59:07.751172 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5458 00:59:07.754416 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5459 00:59:07.758059 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5460 00:59:07.758128 ==
5461 00:59:07.761009 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 00:59:07.767867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 00:59:07.767937 ==
5464 00:59:07.767995 DQS Delay:
5465 00:59:07.770886 DQS0 = 0, DQS1 = 0
5466 00:59:07.770961 DQM Delay:
5467 00:59:07.771019 DQM0 = 92, DQM1 = 84
5468 00:59:07.774356 DQ Delay:
5469 00:59:07.777450 DQ0 =88, DQ1 =96, DQ2 =86, DQ3 =88
5470 00:59:07.781491 DQ4 =90, DQ5 =78, DQ6 =106, DQ7 =104
5471 00:59:07.784059 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5472 00:59:07.787294 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5473 00:59:07.787371
5474 00:59:07.787467
5475 00:59:07.793962 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5476 00:59:07.797343 CH0 RK1: MR19=505, MR18=2E0F
5477 00:59:07.804290 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5478 00:59:07.807383 [RxdqsGatingPostProcess] freq 933
5479 00:59:07.813914 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 00:59:07.813992 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 00:59:07.817481 best DQS1 dly(2T, 0.5T) = (0, 11)
5482 00:59:07.820619 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 00:59:07.823995 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5484 00:59:07.827280 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 00:59:07.830234 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 00:59:07.833747 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 00:59:07.837285 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 00:59:07.840431 Pre-setting of DQS Precalculation
5489 00:59:07.847122 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 00:59:07.847198 ==
5491 00:59:07.850624 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 00:59:07.853906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 00:59:07.853983 ==
5494 00:59:07.860277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 00:59:07.863496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5496 00:59:07.867723 [CA 0] Center 37 (7~67) winsize 61
5497 00:59:07.871112 [CA 1] Center 37 (7~68) winsize 62
5498 00:59:07.874111 [CA 2] Center 34 (5~64) winsize 60
5499 00:59:07.877879 [CA 3] Center 34 (5~64) winsize 60
5500 00:59:07.880987 [CA 4] Center 34 (5~64) winsize 60
5501 00:59:07.884546 [CA 5] Center 34 (4~64) winsize 61
5502 00:59:07.884614
5503 00:59:07.887810 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5504 00:59:07.887900
5505 00:59:07.891052 [CATrainingPosCal] consider 1 rank data
5506 00:59:07.894371 u2DelayCellTimex100 = 270/100 ps
5507 00:59:07.897404 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5508 00:59:07.900754 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5509 00:59:07.907759 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5510 00:59:07.910864 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5511 00:59:07.914040 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5512 00:59:07.917555 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5513 00:59:07.917627
5514 00:59:07.920715 CA PerBit enable=1, Macro0, CA PI delay=34
5515 00:59:07.920791
5516 00:59:07.923926 [CBTSetCACLKResult] CA Dly = 34
5517 00:59:07.924003 CS Dly: 6 (0~37)
5518 00:59:07.927802 ==
5519 00:59:07.927878 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 00:59:07.933829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 00:59:07.933906 ==
5522 00:59:07.937505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 00:59:07.944070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5524 00:59:07.947632 [CA 0] Center 38 (8~68) winsize 61
5525 00:59:07.950547 [CA 1] Center 37 (7~68) winsize 62
5526 00:59:07.954034 [CA 2] Center 35 (6~65) winsize 60
5527 00:59:07.957506 [CA 3] Center 34 (4~64) winsize 61
5528 00:59:07.960511 [CA 4] Center 35 (5~65) winsize 61
5529 00:59:07.964357 [CA 5] Center 34 (4~64) winsize 61
5530 00:59:07.964455
5531 00:59:07.967421 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5532 00:59:07.967522
5533 00:59:07.970551 [CATrainingPosCal] consider 2 rank data
5534 00:59:07.974065 u2DelayCellTimex100 = 270/100 ps
5535 00:59:07.977410 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5536 00:59:07.984068 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5537 00:59:07.987510 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5538 00:59:07.990400 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5539 00:59:07.993765 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5540 00:59:07.997361 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 00:59:07.997453
5542 00:59:08.000369 CA PerBit enable=1, Macro0, CA PI delay=34
5543 00:59:08.000457
5544 00:59:08.004283 [CBTSetCACLKResult] CA Dly = 34
5545 00:59:08.004372 CS Dly: 7 (0~39)
5546 00:59:08.004452
5547 00:59:08.007656 ----->DramcWriteLeveling(PI) begin...
5548 00:59:08.010396 ==
5549 00:59:08.013910 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 00:59:08.017336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 00:59:08.017435 ==
5552 00:59:08.020654 Write leveling (Byte 0): 24 => 24
5553 00:59:08.023753 Write leveling (Byte 1): 30 => 30
5554 00:59:08.027479 DramcWriteLeveling(PI) end<-----
5555 00:59:08.027571
5556 00:59:08.027631 ==
5557 00:59:08.030441 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 00:59:08.033614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 00:59:08.033681 ==
5560 00:59:08.037184 [Gating] SW mode calibration
5561 00:59:08.043915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 00:59:08.050427 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 00:59:08.053529 0 14 0 | B1->B0 | 3030 3232 | 1 0 | (1 1) (0 0)
5564 00:59:08.057001 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 00:59:08.063526 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 00:59:08.067200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 00:59:08.070144 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 00:59:08.073709 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 00:59:08.080327 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5570 00:59:08.083942 0 14 28 | B1->B0 | 3030 3232 | 0 0 | (0 0) (1 0)
5571 00:59:08.086849 0 15 0 | B1->B0 | 2727 2424 | 0 0 | (1 0) (1 0)
5572 00:59:08.093788 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 00:59:08.096976 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 00:59:08.100531 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 00:59:08.106868 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 00:59:08.110343 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 00:59:08.113912 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 00:59:08.120050 0 15 28 | B1->B0 | 3535 3636 | 1 0 | (0 0) (1 1)
5579 00:59:08.123372 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 00:59:08.126780 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 00:59:08.133635 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 00:59:08.137222 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 00:59:08.140463 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 00:59:08.147173 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 00:59:08.150695 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 00:59:08.153628 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5587 00:59:08.160143 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5588 00:59:08.163615 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:59:08.167204 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:59:08.173808 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:59:08.176754 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:59:08.180444 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:59:08.186889 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:59:08.189766 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:59:08.193562 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:59:08.199514 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:59:08.203127 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:59:08.206241 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:59:08.213224 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:59:08.216323 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:59:08.219750 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:59:08.226566 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5603 00:59:08.229318 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 00:59:08.232935 Total UI for P1: 0, mck2ui 16
5605 00:59:08.235822 best dqsien dly found for B0: ( 1, 2, 28)
5606 00:59:08.239199 Total UI for P1: 0, mck2ui 16
5607 00:59:08.242443 best dqsien dly found for B1: ( 1, 2, 28)
5608 00:59:08.245909 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5609 00:59:08.249190 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5610 00:59:08.249261
5611 00:59:08.252958 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5612 00:59:08.256001 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5613 00:59:08.258923 [Gating] SW calibration Done
5614 00:59:08.259012 ==
5615 00:59:08.262528 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 00:59:08.265442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 00:59:08.269010 ==
5618 00:59:08.269076 RX Vref Scan: 0
5619 00:59:08.269133
5620 00:59:08.272496 RX Vref 0 -> 0, step: 1
5621 00:59:08.272586
5622 00:59:08.275477 RX Delay -80 -> 252, step: 8
5623 00:59:08.278972 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5624 00:59:08.281957 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5625 00:59:08.285487 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5626 00:59:08.289085 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5627 00:59:08.292153 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5628 00:59:08.298520 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5629 00:59:08.301950 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5630 00:59:08.305397 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5631 00:59:08.308932 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5632 00:59:08.311923 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5633 00:59:08.318908 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5634 00:59:08.321855 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5635 00:59:08.325158 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5636 00:59:08.328637 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5637 00:59:08.331715 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5638 00:59:08.338813 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5639 00:59:08.338907 ==
5640 00:59:08.342312 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 00:59:08.345161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 00:59:08.345230 ==
5643 00:59:08.345290 DQS Delay:
5644 00:59:08.348448 DQS0 = 0, DQS1 = 0
5645 00:59:08.348533 DQM Delay:
5646 00:59:08.351923 DQM0 = 94, DQM1 = 86
5647 00:59:08.352011 DQ Delay:
5648 00:59:08.355446 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5649 00:59:08.358334 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5650 00:59:08.361735 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5651 00:59:08.364835 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5652 00:59:08.364907
5653 00:59:08.364963
5654 00:59:08.365015 ==
5655 00:59:08.368640 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 00:59:08.371637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 00:59:08.374610 ==
5658 00:59:08.374690
5659 00:59:08.374751
5660 00:59:08.374806 TX Vref Scan disable
5661 00:59:08.378315 == TX Byte 0 ==
5662 00:59:08.381907 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5663 00:59:08.384845 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5664 00:59:08.388465 == TX Byte 1 ==
5665 00:59:08.391413 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5666 00:59:08.394972 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5667 00:59:08.395062 ==
5668 00:59:08.397977 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 00:59:08.404898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 00:59:08.404982 ==
5671 00:59:08.405058
5672 00:59:08.405115
5673 00:59:08.407756 TX Vref Scan disable
5674 00:59:08.407832 == TX Byte 0 ==
5675 00:59:08.414613 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5676 00:59:08.417645 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5677 00:59:08.417721 == TX Byte 1 ==
5678 00:59:08.424227 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5679 00:59:08.427721 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5680 00:59:08.427822
5681 00:59:08.427911 [DATLAT]
5682 00:59:08.431156 Freq=933, CH1 RK0
5683 00:59:08.431248
5684 00:59:08.431331 DATLAT Default: 0xd
5685 00:59:08.434355 0, 0xFFFF, sum = 0
5686 00:59:08.434449 1, 0xFFFF, sum = 0
5687 00:59:08.437388 2, 0xFFFF, sum = 0
5688 00:59:08.437481 3, 0xFFFF, sum = 0
5689 00:59:08.440635 4, 0xFFFF, sum = 0
5690 00:59:08.440754 5, 0xFFFF, sum = 0
5691 00:59:08.444325 6, 0xFFFF, sum = 0
5692 00:59:08.447390 7, 0xFFFF, sum = 0
5693 00:59:08.447483 8, 0xFFFF, sum = 0
5694 00:59:08.450592 9, 0xFFFF, sum = 0
5695 00:59:08.450688 10, 0x0, sum = 1
5696 00:59:08.450774 11, 0x0, sum = 2
5697 00:59:08.454075 12, 0x0, sum = 3
5698 00:59:08.454164 13, 0x0, sum = 4
5699 00:59:08.457311 best_step = 11
5700 00:59:08.457374
5701 00:59:08.457426 ==
5702 00:59:08.460753 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 00:59:08.464224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 00:59:08.464316 ==
5705 00:59:08.467107 RX Vref Scan: 1
5706 00:59:08.467198
5707 00:59:08.467282 RX Vref 0 -> 0, step: 1
5708 00:59:08.470503
5709 00:59:08.470601 RX Delay -69 -> 252, step: 4
5710 00:59:08.470686
5711 00:59:08.474227 Set Vref, RX VrefLevel [Byte0]: 54
5712 00:59:08.477447 [Byte1]: 54
5713 00:59:08.481590
5714 00:59:08.481685 Final RX Vref Byte 0 = 54 to rank0
5715 00:59:08.485181 Final RX Vref Byte 1 = 54 to rank0
5716 00:59:08.488757 Final RX Vref Byte 0 = 54 to rank1
5717 00:59:08.491731 Final RX Vref Byte 1 = 54 to rank1==
5718 00:59:08.495356 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 00:59:08.501890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 00:59:08.501965 ==
5721 00:59:08.502024 DQS Delay:
5722 00:59:08.502078 DQS0 = 0, DQS1 = 0
5723 00:59:08.505371 DQM Delay:
5724 00:59:08.505446 DQM0 = 96, DQM1 = 88
5725 00:59:08.508271 DQ Delay:
5726 00:59:08.511788 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =94
5727 00:59:08.515116 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5728 00:59:08.518151 DQ8 =76, DQ9 =80, DQ10 =90, DQ11 =82
5729 00:59:08.521631 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5730 00:59:08.521707
5731 00:59:08.521766
5732 00:59:08.528193 [DQSOSCAuto] RK0, (LSB)MR18= 0x10a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5733 00:59:08.531741 CH1 RK0: MR19=505, MR18=10A
5734 00:59:08.538287 CH1_RK0: MR19=0x505, MR18=0x10A, DQSOSC=418, MR23=63, INC=62, DEC=41
5735 00:59:08.538384
5736 00:59:08.541663 ----->DramcWriteLeveling(PI) begin...
5737 00:59:08.541764 ==
5738 00:59:08.544944 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 00:59:08.548328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 00:59:08.548425 ==
5741 00:59:08.551558 Write leveling (Byte 0): 26 => 26
5742 00:59:08.554812 Write leveling (Byte 1): 27 => 27
5743 00:59:08.558261 DramcWriteLeveling(PI) end<-----
5744 00:59:08.558353
5745 00:59:08.558438 ==
5746 00:59:08.561577 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 00:59:08.564877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 00:59:08.564950 ==
5749 00:59:08.568487 [Gating] SW mode calibration
5750 00:59:08.574877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5751 00:59:08.581169 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5752 00:59:08.584570 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 00:59:08.588158 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 00:59:08.594666 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 00:59:08.597820 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 00:59:08.600906 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 00:59:08.607725 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5758 00:59:08.611144 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
5759 00:59:08.614619 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
5760 00:59:08.620919 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5761 00:59:08.624580 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 00:59:08.627546 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 00:59:08.634622 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 00:59:08.637701 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 00:59:08.641121 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5766 00:59:08.647746 0 15 24 | B1->B0 | 2626 3838 | 1 0 | (0 0) (0 0)
5767 00:59:08.651078 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5768 00:59:08.654532 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 00:59:08.660869 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 00:59:08.664515 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 00:59:08.667679 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 00:59:08.674293 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 00:59:08.677690 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 00:59:08.681057 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5775 00:59:08.687397 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:59:08.690619 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5777 00:59:08.693978 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:59:08.700907 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:59:08.704294 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:59:08.707432 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:59:08.714266 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:59:08.717717 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 00:59:08.720625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:59:08.727655 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:59:08.731013 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:59:08.733893 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:59:08.737417 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:59:08.743806 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:59:08.747384 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5790 00:59:08.750912 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5791 00:59:08.757015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 00:59:08.760522 Total UI for P1: 0, mck2ui 16
5793 00:59:08.764026 best dqsien dly found for B0: ( 1, 2, 22)
5794 00:59:08.767349 Total UI for P1: 0, mck2ui 16
5795 00:59:08.770616 best dqsien dly found for B1: ( 1, 2, 26)
5796 00:59:08.773895 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5797 00:59:08.777476 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5798 00:59:08.777537
5799 00:59:08.780527 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5800 00:59:08.783843 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5801 00:59:08.787108 [Gating] SW calibration Done
5802 00:59:08.787201 ==
5803 00:59:08.790421 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 00:59:08.793846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 00:59:08.793913 ==
5806 00:59:08.797370 RX Vref Scan: 0
5807 00:59:08.797438
5808 00:59:08.797494 RX Vref 0 -> 0, step: 1
5809 00:59:08.800316
5810 00:59:08.800391 RX Delay -80 -> 252, step: 8
5811 00:59:08.806900 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5812 00:59:08.810793 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5813 00:59:08.813462 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5814 00:59:08.816787 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5815 00:59:08.820330 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5816 00:59:08.823695 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5817 00:59:08.830034 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5818 00:59:08.833705 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5819 00:59:08.837190 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5820 00:59:08.840374 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5821 00:59:08.843402 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5822 00:59:08.850262 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5823 00:59:08.853465 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5824 00:59:08.856485 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5825 00:59:08.860441 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5826 00:59:08.863333 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5827 00:59:08.863404 ==
5828 00:59:08.867031 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 00:59:08.873435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 00:59:08.873516 ==
5831 00:59:08.873577 DQS Delay:
5832 00:59:08.876322 DQS0 = 0, DQS1 = 0
5833 00:59:08.876391 DQM Delay:
5834 00:59:08.876448 DQM0 = 94, DQM1 = 89
5835 00:59:08.879703 DQ Delay:
5836 00:59:08.883232 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5837 00:59:08.886868 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5838 00:59:08.889896 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =87
5839 00:59:08.893168 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5840 00:59:08.893237
5841 00:59:08.893293
5842 00:59:08.893347 ==
5843 00:59:08.896354 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 00:59:08.899631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 00:59:08.899700 ==
5846 00:59:08.899775
5847 00:59:08.899829
5848 00:59:08.903052 TX Vref Scan disable
5849 00:59:08.906521 == TX Byte 0 ==
5850 00:59:08.909872 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5851 00:59:08.913408 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5852 00:59:08.916350 == TX Byte 1 ==
5853 00:59:08.919905 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5854 00:59:08.922847 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5855 00:59:08.922917 ==
5856 00:59:08.926277 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 00:59:08.929507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 00:59:08.932877 ==
5859 00:59:08.932965
5860 00:59:08.933046
5861 00:59:08.933129 TX Vref Scan disable
5862 00:59:08.936603 == TX Byte 0 ==
5863 00:59:08.939917 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5864 00:59:08.943452 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5865 00:59:08.946497 == TX Byte 1 ==
5866 00:59:08.949633 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 00:59:08.956506 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 00:59:08.956603
5869 00:59:08.956712 [DATLAT]
5870 00:59:08.956768 Freq=933, CH1 RK1
5871 00:59:08.956822
5872 00:59:08.959558 DATLAT Default: 0xb
5873 00:59:08.959645 0, 0xFFFF, sum = 0
5874 00:59:08.963075 1, 0xFFFF, sum = 0
5875 00:59:08.963150 2, 0xFFFF, sum = 0
5876 00:59:08.966464 3, 0xFFFF, sum = 0
5877 00:59:08.969387 4, 0xFFFF, sum = 0
5878 00:59:08.969458 5, 0xFFFF, sum = 0
5879 00:59:08.972923 6, 0xFFFF, sum = 0
5880 00:59:08.973017 7, 0xFFFF, sum = 0
5881 00:59:08.976427 8, 0xFFFF, sum = 0
5882 00:59:08.976520 9, 0xFFFF, sum = 0
5883 00:59:08.979366 10, 0x0, sum = 1
5884 00:59:08.979449 11, 0x0, sum = 2
5885 00:59:08.982806 12, 0x0, sum = 3
5886 00:59:08.982949 13, 0x0, sum = 4
5887 00:59:08.983008 best_step = 11
5888 00:59:08.983060
5889 00:59:08.986236 ==
5890 00:59:08.989684 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 00:59:08.992589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 00:59:08.992717 ==
5893 00:59:08.992793 RX Vref Scan: 0
5894 00:59:08.992848
5895 00:59:08.996011 RX Vref 0 -> 0, step: 1
5896 00:59:08.996097
5897 00:59:08.999450 RX Delay -69 -> 252, step: 4
5898 00:59:09.005782 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5899 00:59:09.009034 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5900 00:59:09.012410 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5901 00:59:09.015761 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5902 00:59:09.019305 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5903 00:59:09.022384 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5904 00:59:09.029208 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5905 00:59:09.032636 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5906 00:59:09.035879 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5907 00:59:09.039151 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5908 00:59:09.042244 iDelay=203, Bit 10, Center 94 (-1 ~ 190) 192
5909 00:59:09.045987 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5910 00:59:09.052528 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5911 00:59:09.055306 iDelay=203, Bit 13, Center 96 (-1 ~ 194) 196
5912 00:59:09.058657 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5913 00:59:09.062360 iDelay=203, Bit 15, Center 96 (-1 ~ 194) 196
5914 00:59:09.062429 ==
5915 00:59:09.065912 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 00:59:09.071847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 00:59:09.071919 ==
5918 00:59:09.071979 DQS Delay:
5919 00:59:09.075147 DQS0 = 0, DQS1 = 0
5920 00:59:09.075233 DQM Delay:
5921 00:59:09.075316 DQM0 = 92, DQM1 = 91
5922 00:59:09.078366 DQ Delay:
5923 00:59:09.081977 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
5924 00:59:09.085434 DQ4 =90, DQ5 =102, DQ6 =106, DQ7 =88
5925 00:59:09.088918 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
5926 00:59:09.091750 DQ12 =100, DQ13 =96, DQ14 =94, DQ15 =96
5927 00:59:09.091825
5928 00:59:09.091881
5929 00:59:09.098586 [DQSOSCAuto] RK1, (LSB)MR18= 0x1024, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5930 00:59:09.102088 CH1 RK1: MR19=505, MR18=1024
5931 00:59:09.108729 CH1_RK1: MR19=0x505, MR18=0x1024, DQSOSC=410, MR23=63, INC=64, DEC=42
5932 00:59:09.111994 [RxdqsGatingPostProcess] freq 933
5933 00:59:09.118293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5934 00:59:09.118381 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 00:59:09.121616 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 00:59:09.125066 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 00:59:09.128719 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 00:59:09.131622 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 00:59:09.134978 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 00:59:09.138483 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 00:59:09.141890 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 00:59:09.144763 Pre-setting of DQS Precalculation
5943 00:59:09.151918 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5944 00:59:09.157941 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5945 00:59:09.164774 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5946 00:59:09.164843
5947 00:59:09.164900
5948 00:59:09.168178 [Calibration Summary] 1866 Mbps
5949 00:59:09.168265 CH 0, Rank 0
5950 00:59:09.171536 SW Impedance : PASS
5951 00:59:09.171611 DUTY Scan : NO K
5952 00:59:09.175064 ZQ Calibration : PASS
5953 00:59:09.177851 Jitter Meter : NO K
5954 00:59:09.177939 CBT Training : PASS
5955 00:59:09.181206 Write leveling : PASS
5956 00:59:09.184790 RX DQS gating : PASS
5957 00:59:09.184860 RX DQ/DQS(RDDQC) : PASS
5958 00:59:09.187972 TX DQ/DQS : PASS
5959 00:59:09.191543 RX DATLAT : PASS
5960 00:59:09.191609 RX DQ/DQS(Engine): PASS
5961 00:59:09.194446 TX OE : NO K
5962 00:59:09.194539 All Pass.
5963 00:59:09.194624
5964 00:59:09.198225 CH 0, Rank 1
5965 00:59:09.198311 SW Impedance : PASS
5966 00:59:09.200939 DUTY Scan : NO K
5967 00:59:09.204454 ZQ Calibration : PASS
5968 00:59:09.204513 Jitter Meter : NO K
5969 00:59:09.207989 CBT Training : PASS
5970 00:59:09.210951 Write leveling : PASS
5971 00:59:09.211035 RX DQS gating : PASS
5972 00:59:09.214536 RX DQ/DQS(RDDQC) : PASS
5973 00:59:09.217781 TX DQ/DQS : PASS
5974 00:59:09.217869 RX DATLAT : PASS
5975 00:59:09.221106 RX DQ/DQS(Engine): PASS
5976 00:59:09.224398 TX OE : NO K
5977 00:59:09.224464 All Pass.
5978 00:59:09.224519
5979 00:59:09.224594 CH 1, Rank 0
5980 00:59:09.227402 SW Impedance : PASS
5981 00:59:09.230924 DUTY Scan : NO K
5982 00:59:09.231015 ZQ Calibration : PASS
5983 00:59:09.233968 Jitter Meter : NO K
5984 00:59:09.237554 CBT Training : PASS
5985 00:59:09.237614 Write leveling : PASS
5986 00:59:09.241024 RX DQS gating : PASS
5987 00:59:09.241124 RX DQ/DQS(RDDQC) : PASS
5988 00:59:09.244524 TX DQ/DQS : PASS
5989 00:59:09.247461 RX DATLAT : PASS
5990 00:59:09.247550 RX DQ/DQS(Engine): PASS
5991 00:59:09.251021 TX OE : NO K
5992 00:59:09.251085 All Pass.
5993 00:59:09.251139
5994 00:59:09.253987 CH 1, Rank 1
5995 00:59:09.254073 SW Impedance : PASS
5996 00:59:09.257083 DUTY Scan : NO K
5997 00:59:09.260673 ZQ Calibration : PASS
5998 00:59:09.260766 Jitter Meter : NO K
5999 00:59:09.263670 CBT Training : PASS
6000 00:59:09.267230 Write leveling : PASS
6001 00:59:09.267322 RX DQS gating : PASS
6002 00:59:09.270210 RX DQ/DQS(RDDQC) : PASS
6003 00:59:09.273711 TX DQ/DQS : PASS
6004 00:59:09.273777 RX DATLAT : PASS
6005 00:59:09.277199 RX DQ/DQS(Engine): PASS
6006 00:59:09.280216 TX OE : NO K
6007 00:59:09.280295 All Pass.
6008 00:59:09.280352
6009 00:59:09.283714 DramC Write-DBI off
6010 00:59:09.283781 PER_BANK_REFRESH: Hybrid Mode
6011 00:59:09.286744 TX_TRACKING: ON
6012 00:59:09.293335 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6013 00:59:09.300342 [FAST_K] Save calibration result to emmc
6014 00:59:09.303264 dramc_set_vcore_voltage set vcore to 650000
6015 00:59:09.303357 Read voltage for 400, 6
6016 00:59:09.306942 Vio18 = 0
6017 00:59:09.307008 Vcore = 650000
6018 00:59:09.307076 Vdram = 0
6019 00:59:09.310397 Vddq = 0
6020 00:59:09.310464 Vmddr = 0
6021 00:59:09.313245 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6022 00:59:09.320327 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6023 00:59:09.323596 MEM_TYPE=3, freq_sel=20
6024 00:59:09.326595 sv_algorithm_assistance_LP4_800
6025 00:59:09.329972 ============ PULL DRAM RESETB DOWN ============
6026 00:59:09.333186 ========== PULL DRAM RESETB DOWN end =========
6027 00:59:09.339963 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6028 00:59:09.343391 ===================================
6029 00:59:09.343484 LPDDR4 DRAM CONFIGURATION
6030 00:59:09.346430 ===================================
6031 00:59:09.349894 EX_ROW_EN[0] = 0x0
6032 00:59:09.349972 EX_ROW_EN[1] = 0x0
6033 00:59:09.352889 LP4Y_EN = 0x0
6034 00:59:09.353003 WORK_FSP = 0x0
6035 00:59:09.356345 WL = 0x2
6036 00:59:09.356412 RL = 0x2
6037 00:59:09.359848 BL = 0x2
6038 00:59:09.362810 RPST = 0x0
6039 00:59:09.362872 RD_PRE = 0x0
6040 00:59:09.366387 WR_PRE = 0x1
6041 00:59:09.366448 WR_PST = 0x0
6042 00:59:09.369955 DBI_WR = 0x0
6043 00:59:09.370044 DBI_RD = 0x0
6044 00:59:09.372706 OTF = 0x1
6045 00:59:09.376349 ===================================
6046 00:59:09.379701 ===================================
6047 00:59:09.379795 ANA top config
6048 00:59:09.383323 ===================================
6049 00:59:09.386336 DLL_ASYNC_EN = 0
6050 00:59:09.389429 ALL_SLAVE_EN = 1
6051 00:59:09.389493 NEW_RANK_MODE = 1
6052 00:59:09.392952 DLL_IDLE_MODE = 1
6053 00:59:09.396550 LP45_APHY_COMB_EN = 1
6054 00:59:09.399603 TX_ODT_DIS = 1
6055 00:59:09.399671 NEW_8X_MODE = 1
6056 00:59:09.403083 ===================================
6057 00:59:09.406433 ===================================
6058 00:59:09.409654 data_rate = 800
6059 00:59:09.412946 CKR = 1
6060 00:59:09.416274 DQ_P2S_RATIO = 4
6061 00:59:09.419375 ===================================
6062 00:59:09.422574 CA_P2S_RATIO = 4
6063 00:59:09.426400 DQ_CA_OPEN = 0
6064 00:59:09.429257 DQ_SEMI_OPEN = 1
6065 00:59:09.429323 CA_SEMI_OPEN = 1
6066 00:59:09.432688 CA_FULL_RATE = 0
6067 00:59:09.436292 DQ_CKDIV4_EN = 0
6068 00:59:09.439149 CA_CKDIV4_EN = 1
6069 00:59:09.442449 CA_PREDIV_EN = 0
6070 00:59:09.442544 PH8_DLY = 0
6071 00:59:09.445968 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6072 00:59:09.449454 DQ_AAMCK_DIV = 0
6073 00:59:09.452590 CA_AAMCK_DIV = 0
6074 00:59:09.455947 CA_ADMCK_DIV = 4
6075 00:59:09.459221 DQ_TRACK_CA_EN = 0
6076 00:59:09.462843 CA_PICK = 800
6077 00:59:09.462913 CA_MCKIO = 400
6078 00:59:09.466028 MCKIO_SEMI = 400
6079 00:59:09.469726 PLL_FREQ = 3016
6080 00:59:09.472683 DQ_UI_PI_RATIO = 32
6081 00:59:09.476133 CA_UI_PI_RATIO = 32
6082 00:59:09.479088 ===================================
6083 00:59:09.482655 ===================================
6084 00:59:09.486076 memory_type:LPDDR4
6085 00:59:09.486166 GP_NUM : 10
6086 00:59:09.489031 SRAM_EN : 1
6087 00:59:09.489121 MD32_EN : 0
6088 00:59:09.492547 ===================================
6089 00:59:09.496110 [ANA_INIT] >>>>>>>>>>>>>>
6090 00:59:09.499107 <<<<<< [CONFIGURE PHASE]: ANA_TX
6091 00:59:09.502738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6092 00:59:09.505627 ===================================
6093 00:59:09.509144 data_rate = 800,PCW = 0X7400
6094 00:59:09.512485 ===================================
6095 00:59:09.515582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6096 00:59:09.522585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 00:59:09.532505 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 00:59:09.535674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6099 00:59:09.538917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6100 00:59:09.542048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6101 00:59:09.545512 [ANA_INIT] flow start
6102 00:59:09.549038 [ANA_INIT] PLL >>>>>>>>
6103 00:59:09.549130 [ANA_INIT] PLL <<<<<<<<
6104 00:59:09.552053 [ANA_INIT] MIDPI >>>>>>>>
6105 00:59:09.555348 [ANA_INIT] MIDPI <<<<<<<<
6106 00:59:09.558843 [ANA_INIT] DLL >>>>>>>>
6107 00:59:09.558910 [ANA_INIT] flow end
6108 00:59:09.562314 ============ LP4 DIFF to SE enter ============
6109 00:59:09.568582 ============ LP4 DIFF to SE exit ============
6110 00:59:09.568705 [ANA_INIT] <<<<<<<<<<<<<
6111 00:59:09.571899 [Flow] Enable top DCM control >>>>>
6112 00:59:09.575381 [Flow] Enable top DCM control <<<<<
6113 00:59:09.578848 Enable DLL master slave shuffle
6114 00:59:09.585283 ==============================================================
6115 00:59:09.585353 Gating Mode config
6116 00:59:09.592331 ==============================================================
6117 00:59:09.595321 Config description:
6118 00:59:09.601786 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6119 00:59:09.608946 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6120 00:59:09.615481 SELPH_MODE 0: By rank 1: By Phase
6121 00:59:09.621890 ==============================================================
6122 00:59:09.625276 GAT_TRACK_EN = 0
6123 00:59:09.625346 RX_GATING_MODE = 2
6124 00:59:09.628811 RX_GATING_TRACK_MODE = 2
6125 00:59:09.631819 SELPH_MODE = 1
6126 00:59:09.635230 PICG_EARLY_EN = 1
6127 00:59:09.638240 VALID_LAT_VALUE = 1
6128 00:59:09.645493 ==============================================================
6129 00:59:09.648253 Enter into Gating configuration >>>>
6130 00:59:09.652209 Exit from Gating configuration <<<<
6131 00:59:09.654852 Enter into DVFS_PRE_config >>>>>
6132 00:59:09.664892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6133 00:59:09.668415 Exit from DVFS_PRE_config <<<<<
6134 00:59:09.671835 Enter into PICG configuration >>>>
6135 00:59:09.675113 Exit from PICG configuration <<<<
6136 00:59:09.678237 [RX_INPUT] configuration >>>>>
6137 00:59:09.681629 [RX_INPUT] configuration <<<<<
6138 00:59:09.685032 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6139 00:59:09.691641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6140 00:59:09.698478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 00:59:09.701459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 00:59:09.708100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 00:59:09.714591 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 00:59:09.718052 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6145 00:59:09.721585 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6146 00:59:09.728456 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6147 00:59:09.731193 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6148 00:59:09.734651 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6149 00:59:09.741576 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6150 00:59:09.744564 ===================================
6151 00:59:09.744682 LPDDR4 DRAM CONFIGURATION
6152 00:59:09.747735 ===================================
6153 00:59:09.751238 EX_ROW_EN[0] = 0x0
6154 00:59:09.754550 EX_ROW_EN[1] = 0x0
6155 00:59:09.754642 LP4Y_EN = 0x0
6156 00:59:09.758068 WORK_FSP = 0x0
6157 00:59:09.758156 WL = 0x2
6158 00:59:09.760808 RL = 0x2
6159 00:59:09.760872 BL = 0x2
6160 00:59:09.764245 RPST = 0x0
6161 00:59:09.764331 RD_PRE = 0x0
6162 00:59:09.767668 WR_PRE = 0x1
6163 00:59:09.767782 WR_PST = 0x0
6164 00:59:09.770982 DBI_WR = 0x0
6165 00:59:09.771068 DBI_RD = 0x0
6166 00:59:09.774258 OTF = 0x1
6167 00:59:09.777617 ===================================
6168 00:59:09.781119 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6169 00:59:09.784535 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6170 00:59:09.791302 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 00:59:09.794650 ===================================
6172 00:59:09.794719 LPDDR4 DRAM CONFIGURATION
6173 00:59:09.798276 ===================================
6174 00:59:09.801091 EX_ROW_EN[0] = 0x10
6175 00:59:09.801156 EX_ROW_EN[1] = 0x0
6176 00:59:09.804765 LP4Y_EN = 0x0
6177 00:59:09.804852 WORK_FSP = 0x0
6178 00:59:09.807714 WL = 0x2
6179 00:59:09.811495 RL = 0x2
6180 00:59:09.811582 BL = 0x2
6181 00:59:09.814412 RPST = 0x0
6182 00:59:09.814475 RD_PRE = 0x0
6183 00:59:09.817953 WR_PRE = 0x1
6184 00:59:09.818036 WR_PST = 0x0
6185 00:59:09.820961 DBI_WR = 0x0
6186 00:59:09.821025 DBI_RD = 0x0
6187 00:59:09.824484 OTF = 0x1
6188 00:59:09.827826 ===================================
6189 00:59:09.834347 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6190 00:59:09.837756 nWR fixed to 30
6191 00:59:09.837821 [ModeRegInit_LP4] CH0 RK0
6192 00:59:09.840992 [ModeRegInit_LP4] CH0 RK1
6193 00:59:09.844618 [ModeRegInit_LP4] CH1 RK0
6194 00:59:09.844753 [ModeRegInit_LP4] CH1 RK1
6195 00:59:09.847578 match AC timing 19
6196 00:59:09.851202 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6197 00:59:09.854200 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6198 00:59:09.860775 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6199 00:59:09.863942 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6200 00:59:09.871002 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6201 00:59:09.871070 ==
6202 00:59:09.874402 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 00:59:09.877699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6204 00:59:09.877774 ==
6205 00:59:09.884070 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6206 00:59:09.890639 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6207 00:59:09.890732 [CA 0] Center 36 (8~64) winsize 57
6208 00:59:09.893914 [CA 1] Center 36 (8~64) winsize 57
6209 00:59:09.897537 [CA 2] Center 36 (8~64) winsize 57
6210 00:59:09.900560 [CA 3] Center 36 (8~64) winsize 57
6211 00:59:09.904164 [CA 4] Center 36 (8~64) winsize 57
6212 00:59:09.907479 [CA 5] Center 36 (8~64) winsize 57
6213 00:59:09.907554
6214 00:59:09.910743 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6215 00:59:09.910819
6216 00:59:09.914116 [CATrainingPosCal] consider 1 rank data
6217 00:59:09.917272 u2DelayCellTimex100 = 270/100 ps
6218 00:59:09.920138 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 00:59:09.923468 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 00:59:09.930388 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 00:59:09.933871 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 00:59:09.936914 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 00:59:09.940504 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 00:59:09.940596
6225 00:59:09.943347 CA PerBit enable=1, Macro0, CA PI delay=36
6226 00:59:09.943438
6227 00:59:09.947183 [CBTSetCACLKResult] CA Dly = 36
6228 00:59:09.947278 CS Dly: 1 (0~32)
6229 00:59:09.950380 ==
6230 00:59:09.950492 Dram Type= 6, Freq= 0, CH_0, rank 1
6231 00:59:09.957018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 00:59:09.957091 ==
6233 00:59:09.960451 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 00:59:09.966943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6235 00:59:09.969905 [CA 0] Center 36 (8~64) winsize 57
6236 00:59:09.973429 [CA 1] Center 36 (8~64) winsize 57
6237 00:59:09.977045 [CA 2] Center 36 (8~64) winsize 57
6238 00:59:09.979968 [CA 3] Center 36 (8~64) winsize 57
6239 00:59:09.983469 [CA 4] Center 36 (8~64) winsize 57
6240 00:59:09.986365 [CA 5] Center 36 (8~64) winsize 57
6241 00:59:09.986433
6242 00:59:09.989918 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6243 00:59:09.990012
6244 00:59:09.993388 [CATrainingPosCal] consider 2 rank data
6245 00:59:09.996611 u2DelayCellTimex100 = 270/100 ps
6246 00:59:09.999807 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 00:59:10.003124 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 00:59:10.006738 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 00:59:10.010150 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 00:59:10.016266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 00:59:10.019770 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 00:59:10.019845
6253 00:59:10.023266 CA PerBit enable=1, Macro0, CA PI delay=36
6254 00:59:10.023358
6255 00:59:10.026176 [CBTSetCACLKResult] CA Dly = 36
6256 00:59:10.026241 CS Dly: 1 (0~32)
6257 00:59:10.026321
6258 00:59:10.029572 ----->DramcWriteLeveling(PI) begin...
6259 00:59:10.029637 ==
6260 00:59:10.032752 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 00:59:10.039539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 00:59:10.039608 ==
6263 00:59:10.042861 Write leveling (Byte 0): 40 => 8
6264 00:59:10.042928 Write leveling (Byte 1): 40 => 8
6265 00:59:10.046405 DramcWriteLeveling(PI) end<-----
6266 00:59:10.046496
6267 00:59:10.049495 ==
6268 00:59:10.049585 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 00:59:10.056187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 00:59:10.056285 ==
6271 00:59:10.059408 [Gating] SW mode calibration
6272 00:59:10.066253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 00:59:10.069242 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6274 00:59:10.076365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 00:59:10.079343 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 00:59:10.082890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 00:59:10.089414 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 00:59:10.092794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 00:59:10.095752 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 00:59:10.102894 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 00:59:10.105871 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 00:59:10.109310 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 00:59:10.112499 Total UI for P1: 0, mck2ui 16
6284 00:59:10.115793 best dqsien dly found for B0: ( 0, 14, 24)
6285 00:59:10.119118 Total UI for P1: 0, mck2ui 16
6286 00:59:10.122698 best dqsien dly found for B1: ( 0, 14, 24)
6287 00:59:10.126044 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6288 00:59:10.129186 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6289 00:59:10.129252
6290 00:59:10.133009 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 00:59:10.139619 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 00:59:10.139689 [Gating] SW calibration Done
6293 00:59:10.139747 ==
6294 00:59:10.142716 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 00:59:10.148958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 00:59:10.149039 ==
6297 00:59:10.149098 RX Vref Scan: 0
6298 00:59:10.149152
6299 00:59:10.152318 RX Vref 0 -> 0, step: 1
6300 00:59:10.152382
6301 00:59:10.155533 RX Delay -410 -> 252, step: 16
6302 00:59:10.158932 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6303 00:59:10.162207 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6304 00:59:10.169276 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6305 00:59:10.172376 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6306 00:59:10.175725 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6307 00:59:10.179206 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6308 00:59:10.185661 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6309 00:59:10.188654 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6310 00:59:10.192213 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6311 00:59:10.195325 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6312 00:59:10.202505 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6313 00:59:10.205521 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6314 00:59:10.209069 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6315 00:59:10.212553 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6316 00:59:10.218880 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6317 00:59:10.221965 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6318 00:59:10.222042 ==
6319 00:59:10.225576 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 00:59:10.229134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 00:59:10.229209 ==
6322 00:59:10.231855 DQS Delay:
6323 00:59:10.231943 DQS0 = 59, DQS1 = 59
6324 00:59:10.235787 DQM Delay:
6325 00:59:10.235878 DQM0 = 17, DQM1 = 10
6326 00:59:10.238736 DQ Delay:
6327 00:59:10.238835 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6328 00:59:10.241910 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6329 00:59:10.245810 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6330 00:59:10.248805 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6331 00:59:10.248899
6332 00:59:10.248986
6333 00:59:10.251903 ==
6334 00:59:10.251997 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 00:59:10.258612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 00:59:10.258711 ==
6337 00:59:10.258798
6338 00:59:10.258886
6339 00:59:10.261825 TX Vref Scan disable
6340 00:59:10.261889 == TX Byte 0 ==
6341 00:59:10.264883 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 00:59:10.271699 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 00:59:10.271834 == TX Byte 1 ==
6344 00:59:10.275156 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 00:59:10.278386 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 00:59:10.281512 ==
6347 00:59:10.285138 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 00:59:10.288211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 00:59:10.288302 ==
6350 00:59:10.288388
6351 00:59:10.288468
6352 00:59:10.291530 TX Vref Scan disable
6353 00:59:10.291624 == TX Byte 0 ==
6354 00:59:10.294915 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 00:59:10.301246 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 00:59:10.301314 == TX Byte 1 ==
6357 00:59:10.304847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 00:59:10.311473 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 00:59:10.311568
6360 00:59:10.311652 [DATLAT]
6361 00:59:10.311733 Freq=400, CH0 RK0
6362 00:59:10.311800
6363 00:59:10.314912 DATLAT Default: 0xf
6364 00:59:10.317905 0, 0xFFFF, sum = 0
6365 00:59:10.317997 1, 0xFFFF, sum = 0
6366 00:59:10.321502 2, 0xFFFF, sum = 0
6367 00:59:10.321568 3, 0xFFFF, sum = 0
6368 00:59:10.324354 4, 0xFFFF, sum = 0
6369 00:59:10.324419 5, 0xFFFF, sum = 0
6370 00:59:10.327637 6, 0xFFFF, sum = 0
6371 00:59:10.327702 7, 0xFFFF, sum = 0
6372 00:59:10.331452 8, 0xFFFF, sum = 0
6373 00:59:10.331530 9, 0xFFFF, sum = 0
6374 00:59:10.334440 10, 0xFFFF, sum = 0
6375 00:59:10.334514 11, 0xFFFF, sum = 0
6376 00:59:10.337629 12, 0xFFFF, sum = 0
6377 00:59:10.337705 13, 0x0, sum = 1
6378 00:59:10.340972 14, 0x0, sum = 2
6379 00:59:10.341047 15, 0x0, sum = 3
6380 00:59:10.344633 16, 0x0, sum = 4
6381 00:59:10.344734 best_step = 14
6382 00:59:10.344827
6383 00:59:10.344907 ==
6384 00:59:10.347707 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 00:59:10.354849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 00:59:10.354918 ==
6387 00:59:10.354977 RX Vref Scan: 1
6388 00:59:10.355034
6389 00:59:10.357482 RX Vref 0 -> 0, step: 1
6390 00:59:10.357545
6391 00:59:10.360941 RX Delay -359 -> 252, step: 8
6392 00:59:10.361006
6393 00:59:10.364535 Set Vref, RX VrefLevel [Byte0]: 64
6394 00:59:10.367401 [Byte1]: 49
6395 00:59:10.367490
6396 00:59:10.371003 Final RX Vref Byte 0 = 64 to rank0
6397 00:59:10.373878 Final RX Vref Byte 1 = 49 to rank0
6398 00:59:10.377229 Final RX Vref Byte 0 = 64 to rank1
6399 00:59:10.380759 Final RX Vref Byte 1 = 49 to rank1==
6400 00:59:10.384223 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 00:59:10.387493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 00:59:10.390670 ==
6403 00:59:10.390735 DQS Delay:
6404 00:59:10.390791 DQS0 = 60, DQS1 = 68
6405 00:59:10.394048 DQM Delay:
6406 00:59:10.394145 DQM0 = 14, DQM1 = 14
6407 00:59:10.397186 DQ Delay:
6408 00:59:10.397254 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =8
6409 00:59:10.400619 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6410 00:59:10.403827 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6411 00:59:10.407294 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6412 00:59:10.407385
6413 00:59:10.407474
6414 00:59:10.417146 [DQSOSCAuto] RK0, (LSB)MR18= 0x8987, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6415 00:59:10.420640 CH0 RK0: MR19=C0C, MR18=8987
6416 00:59:10.427216 CH0_RK0: MR19=0xC0C, MR18=0x8987, DQSOSC=392, MR23=63, INC=384, DEC=256
6417 00:59:10.427308 ==
6418 00:59:10.430180 Dram Type= 6, Freq= 0, CH_0, rank 1
6419 00:59:10.433582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 00:59:10.433647 ==
6421 00:59:10.436925 [Gating] SW mode calibration
6422 00:59:10.443626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 00:59:10.450089 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6424 00:59:10.453606 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 00:59:10.457187 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 00:59:10.463421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 00:59:10.466624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 00:59:10.470073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 00:59:10.473552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 00:59:10.480346 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 00:59:10.483275 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 00:59:10.486842 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 00:59:10.489921 Total UI for P1: 0, mck2ui 16
6434 00:59:10.493576 best dqsien dly found for B0: ( 0, 14, 24)
6435 00:59:10.496554 Total UI for P1: 0, mck2ui 16
6436 00:59:10.500235 best dqsien dly found for B1: ( 0, 14, 24)
6437 00:59:10.503131 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6438 00:59:10.509859 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6439 00:59:10.509952
6440 00:59:10.513597 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 00:59:10.516549 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 00:59:10.520090 [Gating] SW calibration Done
6443 00:59:10.520187 ==
6444 00:59:10.523462 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 00:59:10.526361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 00:59:10.526425 ==
6447 00:59:10.529738 RX Vref Scan: 0
6448 00:59:10.529802
6449 00:59:10.529856 RX Vref 0 -> 0, step: 1
6450 00:59:10.529909
6451 00:59:10.533309 RX Delay -410 -> 252, step: 16
6452 00:59:10.536953 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6453 00:59:10.543489 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6454 00:59:10.546721 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6455 00:59:10.549785 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6456 00:59:10.553686 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6457 00:59:10.559733 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6458 00:59:10.563313 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6459 00:59:10.566247 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6460 00:59:10.569817 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6461 00:59:10.576527 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6462 00:59:10.579545 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6463 00:59:10.583599 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6464 00:59:10.586453 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6465 00:59:10.592580 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6466 00:59:10.596178 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6467 00:59:10.599142 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6468 00:59:10.599229 ==
6469 00:59:10.602653 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 00:59:10.609479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 00:59:10.609549 ==
6472 00:59:10.609606 DQS Delay:
6473 00:59:10.612475 DQS0 = 59, DQS1 = 59
6474 00:59:10.612562 DQM Delay:
6475 00:59:10.612658 DQM0 = 16, DQM1 = 10
6476 00:59:10.616126 DQ Delay:
6477 00:59:10.619077 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6478 00:59:10.622894 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6479 00:59:10.626329 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6480 00:59:10.629585 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6481 00:59:10.629658
6482 00:59:10.629716
6483 00:59:10.629782 ==
6484 00:59:10.632612 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 00:59:10.635670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 00:59:10.635762 ==
6487 00:59:10.635844
6488 00:59:10.635923
6489 00:59:10.639060 TX Vref Scan disable
6490 00:59:10.639138 == TX Byte 0 ==
6491 00:59:10.645949 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6492 00:59:10.648861 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6493 00:59:10.648937 == TX Byte 1 ==
6494 00:59:10.655810 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6495 00:59:10.659024 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6496 00:59:10.659101 ==
6497 00:59:10.662092 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 00:59:10.665787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 00:59:10.665864 ==
6500 00:59:10.665924
6501 00:59:10.665979
6502 00:59:10.668778 TX Vref Scan disable
6503 00:59:10.668855 == TX Byte 0 ==
6504 00:59:10.675759 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6505 00:59:10.678702 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6506 00:59:10.678779 == TX Byte 1 ==
6507 00:59:10.685303 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6508 00:59:10.688913 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6509 00:59:10.688989
6510 00:59:10.689049 [DATLAT]
6511 00:59:10.692336 Freq=400, CH0 RK1
6512 00:59:10.692412
6513 00:59:10.692472 DATLAT Default: 0xe
6514 00:59:10.695597 0, 0xFFFF, sum = 0
6515 00:59:10.695674 1, 0xFFFF, sum = 0
6516 00:59:10.698729 2, 0xFFFF, sum = 0
6517 00:59:10.698806 3, 0xFFFF, sum = 0
6518 00:59:10.701829 4, 0xFFFF, sum = 0
6519 00:59:10.701917 5, 0xFFFF, sum = 0
6520 00:59:10.705805 6, 0xFFFF, sum = 0
6521 00:59:10.705882 7, 0xFFFF, sum = 0
6522 00:59:10.708383 8, 0xFFFF, sum = 0
6523 00:59:10.708492 9, 0xFFFF, sum = 0
6524 00:59:10.712060 10, 0xFFFF, sum = 0
6525 00:59:10.715016 11, 0xFFFF, sum = 0
6526 00:59:10.715093 12, 0xFFFF, sum = 0
6527 00:59:10.718571 13, 0x0, sum = 1
6528 00:59:10.718648 14, 0x0, sum = 2
6529 00:59:10.718708 15, 0x0, sum = 3
6530 00:59:10.722072 16, 0x0, sum = 4
6531 00:59:10.722149 best_step = 14
6532 00:59:10.722208
6533 00:59:10.725043 ==
6534 00:59:10.725119 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 00:59:10.731596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 00:59:10.731673 ==
6537 00:59:10.731732 RX Vref Scan: 0
6538 00:59:10.731786
6539 00:59:10.735138 RX Vref 0 -> 0, step: 1
6540 00:59:10.735214
6541 00:59:10.738599 RX Delay -359 -> 252, step: 8
6542 00:59:10.745278 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6543 00:59:10.748412 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6544 00:59:10.752037 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6545 00:59:10.755006 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6546 00:59:10.761576 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6547 00:59:10.765069 iDelay=217, Bit 5, Center -64 (-311 ~ 184) 496
6548 00:59:10.768475 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6549 00:59:10.771718 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6550 00:59:10.778402 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6551 00:59:10.781991 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6552 00:59:10.784874 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6553 00:59:10.791936 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6554 00:59:10.794906 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6555 00:59:10.798467 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6556 00:59:10.801406 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6557 00:59:10.807951 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6558 00:59:10.808028 ==
6559 00:59:10.811263 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 00:59:10.814557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 00:59:10.814634 ==
6562 00:59:10.814693 DQS Delay:
6563 00:59:10.817874 DQS0 = 64, DQS1 = 72
6564 00:59:10.817988 DQM Delay:
6565 00:59:10.821496 DQM0 = 15, DQM1 = 16
6566 00:59:10.821574 DQ Delay:
6567 00:59:10.824887 DQ0 =16, DQ1 =20, DQ2 =8, DQ3 =12
6568 00:59:10.828307 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =28
6569 00:59:10.831466 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6570 00:59:10.834430 DQ12 =20, DQ13 =24, DQ14 =28, DQ15 =24
6571 00:59:10.834507
6572 00:59:10.834567
6573 00:59:10.841523 [DQSOSCAuto] RK1, (LSB)MR18= 0xd689, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 383 ps
6574 00:59:10.844379 CH0 RK1: MR19=C0C, MR18=D689
6575 00:59:10.851364 CH0_RK1: MR19=0xC0C, MR18=0xD689, DQSOSC=383, MR23=63, INC=402, DEC=268
6576 00:59:10.854788 [RxdqsGatingPostProcess] freq 400
6577 00:59:10.861368 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6578 00:59:10.864601 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 00:59:10.867716 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 00:59:10.870802 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 00:59:10.874156 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 00:59:10.874263 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 00:59:10.877706 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 00:59:10.880948 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 00:59:10.884209 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 00:59:10.887717 Pre-setting of DQS Precalculation
6587 00:59:10.894444 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6588 00:59:10.894522 ==
6589 00:59:10.897409 Dram Type= 6, Freq= 0, CH_1, rank 0
6590 00:59:10.900754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 00:59:10.900831 ==
6592 00:59:10.907419 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6593 00:59:10.914080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6594 00:59:10.917550 [CA 0] Center 36 (8~64) winsize 57
6595 00:59:10.917643 [CA 1] Center 36 (8~64) winsize 57
6596 00:59:10.920577 [CA 2] Center 36 (8~64) winsize 57
6597 00:59:10.924053 [CA 3] Center 36 (8~64) winsize 57
6598 00:59:10.927050 [CA 4] Center 36 (8~64) winsize 57
6599 00:59:10.930341 [CA 5] Center 36 (8~64) winsize 57
6600 00:59:10.930418
6601 00:59:10.933709 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6602 00:59:10.933786
6603 00:59:10.940512 [CATrainingPosCal] consider 1 rank data
6604 00:59:10.940612 u2DelayCellTimex100 = 270/100 ps
6605 00:59:10.944148 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 00:59:10.950349 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 00:59:10.953799 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 00:59:10.957371 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 00:59:10.960304 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 00:59:10.963714 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 00:59:10.963790
6612 00:59:10.967092 CA PerBit enable=1, Macro0, CA PI delay=36
6613 00:59:10.967168
6614 00:59:10.970660 [CBTSetCACLKResult] CA Dly = 36
6615 00:59:10.970736 CS Dly: 1 (0~32)
6616 00:59:10.973919 ==
6617 00:59:10.977074 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 00:59:10.980359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 00:59:10.980436 ==
6620 00:59:10.983596 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 00:59:10.990728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6622 00:59:10.993532 [CA 0] Center 36 (8~64) winsize 57
6623 00:59:10.997238 [CA 1] Center 36 (8~64) winsize 57
6624 00:59:11.000240 [CA 2] Center 36 (8~64) winsize 57
6625 00:59:11.003575 [CA 3] Center 36 (8~64) winsize 57
6626 00:59:11.006571 [CA 4] Center 36 (8~64) winsize 57
6627 00:59:11.010228 [CA 5] Center 36 (8~64) winsize 57
6628 00:59:11.010312
6629 00:59:11.013792 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6630 00:59:11.013859
6631 00:59:11.016727 [CATrainingPosCal] consider 2 rank data
6632 00:59:11.020226 u2DelayCellTimex100 = 270/100 ps
6633 00:59:11.023779 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 00:59:11.026724 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 00:59:11.030104 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 00:59:11.033734 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 00:59:11.040022 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 00:59:11.043329 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 00:59:11.043420
6640 00:59:11.046873 CA PerBit enable=1, Macro0, CA PI delay=36
6641 00:59:11.046963
6642 00:59:11.050245 [CBTSetCACLKResult] CA Dly = 36
6643 00:59:11.050332 CS Dly: 1 (0~32)
6644 00:59:11.050411
6645 00:59:11.053568 ----->DramcWriteLeveling(PI) begin...
6646 00:59:11.053644 ==
6647 00:59:11.057489 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 00:59:11.063691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 00:59:11.063770 ==
6650 00:59:11.066574 Write leveling (Byte 0): 40 => 8
6651 00:59:11.066650 Write leveling (Byte 1): 40 => 8
6652 00:59:11.069914 DramcWriteLeveling(PI) end<-----
6653 00:59:11.069990
6654 00:59:11.070048 ==
6655 00:59:11.073380 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 00:59:11.079863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 00:59:11.079961 ==
6658 00:59:11.083247 [Gating] SW mode calibration
6659 00:59:11.089875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6660 00:59:11.093000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6661 00:59:11.099709 0 11 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
6662 00:59:11.103162 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 00:59:11.106987 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 00:59:11.113315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 00:59:11.116712 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 00:59:11.119763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 00:59:11.126609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 00:59:11.129602 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 00:59:11.132949 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 00:59:11.136379 Total UI for P1: 0, mck2ui 16
6671 00:59:11.139806 best dqsien dly found for B0: ( 0, 14, 24)
6672 00:59:11.142714 Total UI for P1: 0, mck2ui 16
6673 00:59:11.146137 best dqsien dly found for B1: ( 0, 14, 24)
6674 00:59:11.149752 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6675 00:59:11.153249 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6676 00:59:11.153338
6677 00:59:11.156355 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 00:59:11.163168 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 00:59:11.163236 [Gating] SW calibration Done
6680 00:59:11.166393 ==
6681 00:59:11.166465 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 00:59:11.172849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 00:59:11.172919 ==
6684 00:59:11.172976 RX Vref Scan: 0
6685 00:59:11.173028
6686 00:59:11.176294 RX Vref 0 -> 0, step: 1
6687 00:59:11.176380
6688 00:59:11.179827 RX Delay -410 -> 252, step: 16
6689 00:59:11.182613 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6690 00:59:11.186078 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6691 00:59:11.192914 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6692 00:59:11.196222 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6693 00:59:11.199343 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6694 00:59:11.202744 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6695 00:59:11.209745 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6696 00:59:11.212575 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6697 00:59:11.216012 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6698 00:59:11.219249 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6699 00:59:11.225845 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6700 00:59:11.229727 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6701 00:59:11.232599 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6702 00:59:11.236094 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6703 00:59:11.242863 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6704 00:59:11.245782 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6705 00:59:11.245857 ==
6706 00:59:11.249735 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 00:59:11.252746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 00:59:11.252822 ==
6709 00:59:11.255745 DQS Delay:
6710 00:59:11.255820 DQS0 = 51, DQS1 = 67
6711 00:59:11.259164 DQM Delay:
6712 00:59:11.259239 DQM0 = 13, DQM1 = 20
6713 00:59:11.259298 DQ Delay:
6714 00:59:11.262799 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6715 00:59:11.265740 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6716 00:59:11.269338 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6717 00:59:11.272563 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6718 00:59:11.272638
6719 00:59:11.272741
6720 00:59:11.272801 ==
6721 00:59:11.276069 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 00:59:11.282604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 00:59:11.282679 ==
6724 00:59:11.282737
6725 00:59:11.282798
6726 00:59:11.282850 TX Vref Scan disable
6727 00:59:11.286014 == TX Byte 0 ==
6728 00:59:11.289201 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 00:59:11.292239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 00:59:11.295574 == TX Byte 1 ==
6731 00:59:11.298827 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 00:59:11.302247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 00:59:11.302323 ==
6734 00:59:11.306016 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 00:59:11.312003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 00:59:11.312102 ==
6737 00:59:11.312188
6738 00:59:11.312276
6739 00:59:11.312358 TX Vref Scan disable
6740 00:59:11.315569 == TX Byte 0 ==
6741 00:59:11.318605 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 00:59:11.322215 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 00:59:11.325421 == TX Byte 1 ==
6744 00:59:11.328813 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 00:59:11.332201 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 00:59:11.332277
6747 00:59:11.335226 [DATLAT]
6748 00:59:11.335302 Freq=400, CH1 RK0
6749 00:59:11.335361
6750 00:59:11.338630 DATLAT Default: 0xf
6751 00:59:11.338705 0, 0xFFFF, sum = 0
6752 00:59:11.341981 1, 0xFFFF, sum = 0
6753 00:59:11.342058 2, 0xFFFF, sum = 0
6754 00:59:11.345108 3, 0xFFFF, sum = 0
6755 00:59:11.345226 4, 0xFFFF, sum = 0
6756 00:59:11.348976 5, 0xFFFF, sum = 0
6757 00:59:11.349053 6, 0xFFFF, sum = 0
6758 00:59:11.351826 7, 0xFFFF, sum = 0
6759 00:59:11.355213 8, 0xFFFF, sum = 0
6760 00:59:11.355290 9, 0xFFFF, sum = 0
6761 00:59:11.358698 10, 0xFFFF, sum = 0
6762 00:59:11.358776 11, 0xFFFF, sum = 0
6763 00:59:11.362199 12, 0xFFFF, sum = 0
6764 00:59:11.362298 13, 0x0, sum = 1
6765 00:59:11.365107 14, 0x0, sum = 2
6766 00:59:11.365185 15, 0x0, sum = 3
6767 00:59:11.368667 16, 0x0, sum = 4
6768 00:59:11.368745 best_step = 14
6769 00:59:11.368804
6770 00:59:11.368859 ==
6771 00:59:11.372192 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 00:59:11.375033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 00:59:11.375134 ==
6774 00:59:11.378296 RX Vref Scan: 1
6775 00:59:11.378362
6776 00:59:11.381866 RX Vref 0 -> 0, step: 1
6777 00:59:11.381930
6778 00:59:11.381997 RX Delay -375 -> 252, step: 8
6779 00:59:11.382050
6780 00:59:11.385334 Set Vref, RX VrefLevel [Byte0]: 54
6781 00:59:11.388300 [Byte1]: 54
6782 00:59:11.394160
6783 00:59:11.394254 Final RX Vref Byte 0 = 54 to rank0
6784 00:59:11.397562 Final RX Vref Byte 1 = 54 to rank0
6785 00:59:11.400847 Final RX Vref Byte 0 = 54 to rank1
6786 00:59:11.403781 Final RX Vref Byte 1 = 54 to rank1==
6787 00:59:11.407420 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 00:59:11.414069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 00:59:11.414161 ==
6790 00:59:11.414244 DQS Delay:
6791 00:59:11.417102 DQS0 = 52, DQS1 = 64
6792 00:59:11.417218 DQM Delay:
6793 00:59:11.417288 DQM0 = 9, DQM1 = 10
6794 00:59:11.420231 DQ Delay:
6795 00:59:11.423530 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6796 00:59:11.423607 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6797 00:59:11.427206 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6798 00:59:11.430182 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6799 00:59:11.430263
6800 00:59:11.433657
6801 00:59:11.440229 [DQSOSCAuto] RK0, (LSB)MR18= 0x6679, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 396 ps
6802 00:59:11.443559 CH1 RK0: MR19=C0C, MR18=6679
6803 00:59:11.450419 CH1_RK0: MR19=0xC0C, MR18=0x6679, DQSOSC=394, MR23=63, INC=380, DEC=253
6804 00:59:11.450495 ==
6805 00:59:11.453524 Dram Type= 6, Freq= 0, CH_1, rank 1
6806 00:59:11.456865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 00:59:11.456941 ==
6808 00:59:11.460237 [Gating] SW mode calibration
6809 00:59:11.466957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6810 00:59:11.473605 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6811 00:59:11.476481 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6812 00:59:11.480001 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 00:59:11.486841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 00:59:11.489796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 00:59:11.493311 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 00:59:11.496928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 00:59:11.503258 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 00:59:11.506761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 00:59:11.509810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 00:59:11.513361 Total UI for P1: 0, mck2ui 16
6821 00:59:11.516809 best dqsien dly found for B0: ( 0, 14, 24)
6822 00:59:11.519959 Total UI for P1: 0, mck2ui 16
6823 00:59:11.523228 best dqsien dly found for B1: ( 0, 14, 24)
6824 00:59:11.526453 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6825 00:59:11.533209 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6826 00:59:11.533285
6827 00:59:11.536610 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 00:59:11.539692 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 00:59:11.543342 [Gating] SW calibration Done
6830 00:59:11.543418 ==
6831 00:59:11.546294 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 00:59:11.549870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 00:59:11.549946 ==
6834 00:59:11.553153 RX Vref Scan: 0
6835 00:59:11.553229
6836 00:59:11.553288 RX Vref 0 -> 0, step: 1
6837 00:59:11.553342
6838 00:59:11.556662 RX Delay -410 -> 252, step: 16
6839 00:59:11.559922 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6840 00:59:11.566426 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6841 00:59:11.569560 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6842 00:59:11.572755 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6843 00:59:11.576259 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6844 00:59:11.583060 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6845 00:59:11.586436 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6846 00:59:11.589925 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6847 00:59:11.592790 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6848 00:59:11.599365 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6849 00:59:11.602910 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6850 00:59:11.606464 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6851 00:59:11.609293 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6852 00:59:11.616372 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6853 00:59:11.619377 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6854 00:59:11.622953 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6855 00:59:11.623029 ==
6856 00:59:11.625940 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 00:59:11.632808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 00:59:11.632884 ==
6859 00:59:11.632942 DQS Delay:
6860 00:59:11.635963 DQS0 = 59, DQS1 = 59
6861 00:59:11.636038 DQM Delay:
6862 00:59:11.636097 DQM0 = 19, DQM1 = 14
6863 00:59:11.639363 DQ Delay:
6864 00:59:11.642858 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6865 00:59:11.646144 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6866 00:59:11.646220 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6867 00:59:11.649388 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6868 00:59:11.652857
6869 00:59:11.652932
6870 00:59:11.652991 ==
6871 00:59:11.656058 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 00:59:11.659499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 00:59:11.659574 ==
6874 00:59:11.659633
6875 00:59:11.659687
6876 00:59:11.662424 TX Vref Scan disable
6877 00:59:11.662499 == TX Byte 0 ==
6878 00:59:11.666337 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6879 00:59:11.672656 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6880 00:59:11.672763 == TX Byte 1 ==
6881 00:59:11.676061 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6882 00:59:11.682656 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6883 00:59:11.682732 ==
6884 00:59:11.685760 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 00:59:11.689403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 00:59:11.689511 ==
6887 00:59:11.689585
6888 00:59:11.689639
6889 00:59:11.692761 TX Vref Scan disable
6890 00:59:11.692839 == TX Byte 0 ==
6891 00:59:11.695576 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6892 00:59:11.702751 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6893 00:59:11.702835 == TX Byte 1 ==
6894 00:59:11.705739 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6895 00:59:11.712603 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6896 00:59:11.712718
6897 00:59:11.712779 [DATLAT]
6898 00:59:11.712834 Freq=400, CH1 RK1
6899 00:59:11.715649
6900 00:59:11.715728 DATLAT Default: 0xe
6901 00:59:11.719251 0, 0xFFFF, sum = 0
6902 00:59:11.719328 1, 0xFFFF, sum = 0
6903 00:59:11.722773 2, 0xFFFF, sum = 0
6904 00:59:11.722850 3, 0xFFFF, sum = 0
6905 00:59:11.725716 4, 0xFFFF, sum = 0
6906 00:59:11.725794 5, 0xFFFF, sum = 0
6907 00:59:11.729269 6, 0xFFFF, sum = 0
6908 00:59:11.729347 7, 0xFFFF, sum = 0
6909 00:59:11.732256 8, 0xFFFF, sum = 0
6910 00:59:11.732333 9, 0xFFFF, sum = 0
6911 00:59:11.735823 10, 0xFFFF, sum = 0
6912 00:59:11.735900 11, 0xFFFF, sum = 0
6913 00:59:11.739238 12, 0xFFFF, sum = 0
6914 00:59:11.739316 13, 0x0, sum = 1
6915 00:59:11.742465 14, 0x0, sum = 2
6916 00:59:11.742543 15, 0x0, sum = 3
6917 00:59:11.745775 16, 0x0, sum = 4
6918 00:59:11.745852 best_step = 14
6919 00:59:11.745911
6920 00:59:11.745964 ==
6921 00:59:11.749208 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 00:59:11.755837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 00:59:11.755916 ==
6924 00:59:11.755976 RX Vref Scan: 0
6925 00:59:11.756031
6926 00:59:11.758730 RX Vref 0 -> 0, step: 1
6927 00:59:11.758806
6928 00:59:11.762408 RX Delay -359 -> 252, step: 8
6929 00:59:11.769103 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6930 00:59:11.772316 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6931 00:59:11.775270 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6932 00:59:11.778714 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6933 00:59:11.785593 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6934 00:59:11.788940 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6935 00:59:11.792276 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6936 00:59:11.795330 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6937 00:59:11.801889 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6938 00:59:11.805310 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6939 00:59:11.808753 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6940 00:59:11.811832 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
6941 00:59:11.818676 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6942 00:59:11.822240 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6943 00:59:11.825061 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6944 00:59:11.828629 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6945 00:59:11.832230 ==
6946 00:59:11.835267 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 00:59:11.838677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 00:59:11.838754 ==
6949 00:59:11.838814 DQS Delay:
6950 00:59:11.841633 DQS0 = 60, DQS1 = 64
6951 00:59:11.841709 DQM Delay:
6952 00:59:11.845138 DQM0 = 12, DQM1 = 10
6953 00:59:11.845214 DQ Delay:
6954 00:59:11.848611 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6955 00:59:11.851880 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6956 00:59:11.855534 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6957 00:59:11.858513 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6958 00:59:11.858589
6959 00:59:11.858647
6960 00:59:11.864962 [DQSOSCAuto] RK1, (LSB)MR18= 0x81b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6961 00:59:11.868477 CH1 RK1: MR19=C0C, MR18=81B1
6962 00:59:11.875248 CH1_RK1: MR19=0xC0C, MR18=0x81B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6963 00:59:11.878424 [RxdqsGatingPostProcess] freq 400
6964 00:59:11.881426 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6965 00:59:11.884812 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 00:59:11.888410 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 00:59:11.891433 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 00:59:11.894802 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 00:59:11.898159 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 00:59:11.901528 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 00:59:11.904770 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 00:59:11.907806 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 00:59:11.911628 Pre-setting of DQS Precalculation
6974 00:59:11.914767 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6975 00:59:11.924767 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6976 00:59:11.931468 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6977 00:59:11.931545
6978 00:59:11.931605
6979 00:59:11.934544 [Calibration Summary] 800 Mbps
6980 00:59:11.934621 CH 0, Rank 0
6981 00:59:11.938076 SW Impedance : PASS
6982 00:59:11.938153 DUTY Scan : NO K
6983 00:59:11.941019 ZQ Calibration : PASS
6984 00:59:11.944588 Jitter Meter : NO K
6985 00:59:11.944674 CBT Training : PASS
6986 00:59:11.947584 Write leveling : PASS
6987 00:59:11.951138 RX DQS gating : PASS
6988 00:59:11.951214 RX DQ/DQS(RDDQC) : PASS
6989 00:59:11.954622 TX DQ/DQS : PASS
6990 00:59:11.957993 RX DATLAT : PASS
6991 00:59:11.958070 RX DQ/DQS(Engine): PASS
6992 00:59:11.961247 TX OE : NO K
6993 00:59:11.961323 All Pass.
6994 00:59:11.961383
6995 00:59:11.964479 CH 0, Rank 1
6996 00:59:11.964555 SW Impedance : PASS
6997 00:59:11.968075 DUTY Scan : NO K
6998 00:59:11.971107 ZQ Calibration : PASS
6999 00:59:11.971183 Jitter Meter : NO K
7000 00:59:11.974593 CBT Training : PASS
7001 00:59:11.977563 Write leveling : NO K
7002 00:59:11.977640 RX DQS gating : PASS
7003 00:59:11.981230 RX DQ/DQS(RDDQC) : PASS
7004 00:59:11.984150 TX DQ/DQS : PASS
7005 00:59:11.984226 RX DATLAT : PASS
7006 00:59:11.987494 RX DQ/DQS(Engine): PASS
7007 00:59:11.987571 TX OE : NO K
7008 00:59:11.990784 All Pass.
7009 00:59:11.990860
7010 00:59:11.990919 CH 1, Rank 0
7011 00:59:11.994097 SW Impedance : PASS
7012 00:59:11.994174 DUTY Scan : NO K
7013 00:59:11.997470 ZQ Calibration : PASS
7014 00:59:12.001143 Jitter Meter : NO K
7015 00:59:12.001219 CBT Training : PASS
7016 00:59:12.004225 Write leveling : PASS
7017 00:59:12.007334 RX DQS gating : PASS
7018 00:59:12.007427 RX DQ/DQS(RDDQC) : PASS
7019 00:59:12.010828 TX DQ/DQS : PASS
7020 00:59:12.014136 RX DATLAT : PASS
7021 00:59:12.014203 RX DQ/DQS(Engine): PASS
7022 00:59:12.017429 TX OE : NO K
7023 00:59:12.017503 All Pass.
7024 00:59:12.017559
7025 00:59:12.020754 CH 1, Rank 1
7026 00:59:12.020841 SW Impedance : PASS
7027 00:59:12.023823 DUTY Scan : NO K
7028 00:59:12.027199 ZQ Calibration : PASS
7029 00:59:12.027289 Jitter Meter : NO K
7030 00:59:12.030411 CBT Training : PASS
7031 00:59:12.034200 Write leveling : NO K
7032 00:59:12.034272 RX DQS gating : PASS
7033 00:59:12.037162 RX DQ/DQS(RDDQC) : PASS
7034 00:59:12.040802 TX DQ/DQS : PASS
7035 00:59:12.040879 RX DATLAT : PASS
7036 00:59:12.043694 RX DQ/DQS(Engine): PASS
7037 00:59:12.043769 TX OE : NO K
7038 00:59:12.047335 All Pass.
7039 00:59:12.047411
7040 00:59:12.047470 DramC Write-DBI off
7041 00:59:12.050956 PER_BANK_REFRESH: Hybrid Mode
7042 00:59:12.053898 TX_TRACKING: ON
7043 00:59:12.060803 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7044 00:59:12.063733 [FAST_K] Save calibration result to emmc
7045 00:59:12.067127 dramc_set_vcore_voltage set vcore to 725000
7046 00:59:12.070713 Read voltage for 1600, 0
7047 00:59:12.070797 Vio18 = 0
7048 00:59:12.074036 Vcore = 725000
7049 00:59:12.074113 Vdram = 0
7050 00:59:12.074172 Vddq = 0
7051 00:59:12.077160 Vmddr = 0
7052 00:59:12.080740 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7053 00:59:12.087273 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7054 00:59:12.090162 MEM_TYPE=3, freq_sel=13
7055 00:59:12.090237 sv_algorithm_assistance_LP4_3733
7056 00:59:12.096909 ============ PULL DRAM RESETB DOWN ============
7057 00:59:12.100493 ========== PULL DRAM RESETB DOWN end =========
7058 00:59:12.103983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7059 00:59:12.107526 ===================================
7060 00:59:12.110278 LPDDR4 DRAM CONFIGURATION
7061 00:59:12.113689 ===================================
7062 00:59:12.116973 EX_ROW_EN[0] = 0x0
7063 00:59:12.117050 EX_ROW_EN[1] = 0x0
7064 00:59:12.120155 LP4Y_EN = 0x0
7065 00:59:12.120230 WORK_FSP = 0x1
7066 00:59:12.123606 WL = 0x5
7067 00:59:12.123695 RL = 0x5
7068 00:59:12.126860 BL = 0x2
7069 00:59:12.126936 RPST = 0x0
7070 00:59:12.130449 RD_PRE = 0x0
7071 00:59:12.130552 WR_PRE = 0x1
7072 00:59:12.133240 WR_PST = 0x1
7073 00:59:12.133334 DBI_WR = 0x0
7074 00:59:12.137031 DBI_RD = 0x0
7075 00:59:12.137106 OTF = 0x1
7076 00:59:12.139931 ===================================
7077 00:59:12.143662 ===================================
7078 00:59:12.146774 ANA top config
7079 00:59:12.150489 ===================================
7080 00:59:12.153454 DLL_ASYNC_EN = 0
7081 00:59:12.153531 ALL_SLAVE_EN = 0
7082 00:59:12.156933 NEW_RANK_MODE = 1
7083 00:59:12.159886 DLL_IDLE_MODE = 1
7084 00:59:12.163424 LP45_APHY_COMB_EN = 1
7085 00:59:12.163500 TX_ODT_DIS = 0
7086 00:59:12.166929 NEW_8X_MODE = 1
7087 00:59:12.169827 ===================================
7088 00:59:12.173360 ===================================
7089 00:59:12.177112 data_rate = 3200
7090 00:59:12.179843 CKR = 1
7091 00:59:12.183134 DQ_P2S_RATIO = 8
7092 00:59:12.186637 ===================================
7093 00:59:12.189766 CA_P2S_RATIO = 8
7094 00:59:12.189863 DQ_CA_OPEN = 0
7095 00:59:12.193328 DQ_SEMI_OPEN = 0
7096 00:59:12.196802 CA_SEMI_OPEN = 0
7097 00:59:12.200068 CA_FULL_RATE = 0
7098 00:59:12.203025 DQ_CKDIV4_EN = 0
7099 00:59:12.206633 CA_CKDIV4_EN = 0
7100 00:59:12.206733 CA_PREDIV_EN = 0
7101 00:59:12.210282 PH8_DLY = 12
7102 00:59:12.213140 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7103 00:59:12.216477 DQ_AAMCK_DIV = 4
7104 00:59:12.219988 CA_AAMCK_DIV = 4
7105 00:59:12.223332 CA_ADMCK_DIV = 4
7106 00:59:12.223408 DQ_TRACK_CA_EN = 0
7107 00:59:12.226733 CA_PICK = 1600
7108 00:59:12.229756 CA_MCKIO = 1600
7109 00:59:12.233120 MCKIO_SEMI = 0
7110 00:59:12.236531 PLL_FREQ = 3068
7111 00:59:12.239822 DQ_UI_PI_RATIO = 32
7112 00:59:12.243276 CA_UI_PI_RATIO = 0
7113 00:59:12.246577 ===================================
7114 00:59:12.250086 ===================================
7115 00:59:12.250178 memory_type:LPDDR4
7116 00:59:12.252907 GP_NUM : 10
7117 00:59:12.256498 SRAM_EN : 1
7118 00:59:12.256587 MD32_EN : 0
7119 00:59:12.259996 ===================================
7120 00:59:12.262884 [ANA_INIT] >>>>>>>>>>>>>>
7121 00:59:12.266564 <<<<<< [CONFIGURE PHASE]: ANA_TX
7122 00:59:12.269507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7123 00:59:12.272973 ===================================
7124 00:59:12.276420 data_rate = 3200,PCW = 0X7600
7125 00:59:12.279923 ===================================
7126 00:59:12.282917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7127 00:59:12.286393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 00:59:12.292742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 00:59:12.296506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7130 00:59:12.299511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7131 00:59:12.302660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7132 00:59:12.306128 [ANA_INIT] flow start
7133 00:59:12.309715 [ANA_INIT] PLL >>>>>>>>
7134 00:59:12.309795 [ANA_INIT] PLL <<<<<<<<
7135 00:59:12.312539 [ANA_INIT] MIDPI >>>>>>>>
7136 00:59:12.316122 [ANA_INIT] MIDPI <<<<<<<<
7137 00:59:12.319157 [ANA_INIT] DLL >>>>>>>>
7138 00:59:12.319247 [ANA_INIT] DLL <<<<<<<<
7139 00:59:12.322567 [ANA_INIT] flow end
7140 00:59:12.326072 ============ LP4 DIFF to SE enter ============
7141 00:59:12.329597 ============ LP4 DIFF to SE exit ============
7142 00:59:12.332427 [ANA_INIT] <<<<<<<<<<<<<
7143 00:59:12.335801 [Flow] Enable top DCM control >>>>>
7144 00:59:12.339488 [Flow] Enable top DCM control <<<<<
7145 00:59:12.342721 Enable DLL master slave shuffle
7146 00:59:12.349542 ==============================================================
7147 00:59:12.349618 Gating Mode config
7148 00:59:12.355834 ==============================================================
7149 00:59:12.355911 Config description:
7150 00:59:12.365605 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7151 00:59:12.372266 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7152 00:59:12.379049 SELPH_MODE 0: By rank 1: By Phase
7153 00:59:12.382603 ==============================================================
7154 00:59:12.385640 GAT_TRACK_EN = 1
7155 00:59:12.389022 RX_GATING_MODE = 2
7156 00:59:12.392501 RX_GATING_TRACK_MODE = 2
7157 00:59:12.395294 SELPH_MODE = 1
7158 00:59:12.398715 PICG_EARLY_EN = 1
7159 00:59:12.402283 VALID_LAT_VALUE = 1
7160 00:59:12.409102 ==============================================================
7161 00:59:12.412184 Enter into Gating configuration >>>>
7162 00:59:12.415163 Exit from Gating configuration <<<<
7163 00:59:12.415239 Enter into DVFS_PRE_config >>>>>
7164 00:59:12.428798 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7165 00:59:12.431816 Exit from DVFS_PRE_config <<<<<
7166 00:59:12.435307 Enter into PICG configuration >>>>
7167 00:59:12.438681 Exit from PICG configuration <<<<
7168 00:59:12.438758 [RX_INPUT] configuration >>>>>
7169 00:59:12.441682 [RX_INPUT] configuration <<<<<
7170 00:59:12.448423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7171 00:59:12.455095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7172 00:59:12.458849 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 00:59:12.465262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 00:59:12.471879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 00:59:12.478332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 00:59:12.482146 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7177 00:59:12.485105 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7178 00:59:12.491712 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7179 00:59:12.495007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7180 00:59:12.498496 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7181 00:59:12.501533 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 00:59:12.504917 ===================================
7183 00:59:12.508133 LPDDR4 DRAM CONFIGURATION
7184 00:59:12.511543 ===================================
7185 00:59:12.514852 EX_ROW_EN[0] = 0x0
7186 00:59:12.514928 EX_ROW_EN[1] = 0x0
7187 00:59:12.518250 LP4Y_EN = 0x0
7188 00:59:12.518326 WORK_FSP = 0x1
7189 00:59:12.521293 WL = 0x5
7190 00:59:12.521369 RL = 0x5
7191 00:59:12.524806 BL = 0x2
7192 00:59:12.524890 RPST = 0x0
7193 00:59:12.528306 RD_PRE = 0x0
7194 00:59:12.531498 WR_PRE = 0x1
7195 00:59:12.531597 WR_PST = 0x1
7196 00:59:12.534927 DBI_WR = 0x0
7197 00:59:12.535010 DBI_RD = 0x0
7198 00:59:12.537817 OTF = 0x1
7199 00:59:12.541204 ===================================
7200 00:59:12.544518 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7201 00:59:12.547911 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7202 00:59:12.551469 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 00:59:12.554887 ===================================
7204 00:59:12.558048 LPDDR4 DRAM CONFIGURATION
7205 00:59:12.561347 ===================================
7206 00:59:12.564597 EX_ROW_EN[0] = 0x10
7207 00:59:12.564684 EX_ROW_EN[1] = 0x0
7208 00:59:12.567902 LP4Y_EN = 0x0
7209 00:59:12.567966 WORK_FSP = 0x1
7210 00:59:12.570808 WL = 0x5
7211 00:59:12.570874 RL = 0x5
7212 00:59:12.574189 BL = 0x2
7213 00:59:12.574269 RPST = 0x0
7214 00:59:12.577774 RD_PRE = 0x0
7215 00:59:12.581301 WR_PRE = 0x1
7216 00:59:12.581376 WR_PST = 0x1
7217 00:59:12.584330 DBI_WR = 0x0
7218 00:59:12.584406 DBI_RD = 0x0
7219 00:59:12.587879 OTF = 0x1
7220 00:59:12.590802 ===================================
7221 00:59:12.593924 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7222 00:59:12.597522 ==
7223 00:59:12.600679 Dram Type= 6, Freq= 0, CH_0, rank 0
7224 00:59:12.603746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7225 00:59:12.603819 ==
7226 00:59:12.607530 [Duty_Offset_Calibration]
7227 00:59:12.607604 B0:2 B1:0 CA:3
7228 00:59:12.607662
7229 00:59:12.610801 [DutyScan_Calibration_Flow] k_type=0
7230 00:59:12.620586
7231 00:59:12.620699 ==CLK 0==
7232 00:59:12.623999 Final CLK duty delay cell = 0
7233 00:59:12.627004 [0] MAX Duty = 5062%(X100), DQS PI = 20
7234 00:59:12.630451 [0] MIN Duty = 4875%(X100), DQS PI = 54
7235 00:59:12.634057 [0] AVG Duty = 4968%(X100)
7236 00:59:12.634132
7237 00:59:12.636951 CH0 CLK Duty spec in!! Max-Min= 187%
7238 00:59:12.640405 [DutyScan_Calibration_Flow] ====Done====
7239 00:59:12.640481
7240 00:59:12.643926 [DutyScan_Calibration_Flow] k_type=1
7241 00:59:12.660425
7242 00:59:12.660501 ==DQS 0 ==
7243 00:59:12.663933 Final DQS duty delay cell = 0
7244 00:59:12.667529 [0] MAX Duty = 5094%(X100), DQS PI = 28
7245 00:59:12.670291 [0] MIN Duty = 4875%(X100), DQS PI = 48
7246 00:59:12.674058 [0] AVG Duty = 4984%(X100)
7247 00:59:12.674134
7248 00:59:12.674193 ==DQS 1 ==
7249 00:59:12.676865 Final DQS duty delay cell = 0
7250 00:59:12.680255 [0] MAX Duty = 5156%(X100), DQS PI = 32
7251 00:59:12.683864 [0] MIN Duty = 5062%(X100), DQS PI = 0
7252 00:59:12.686928 [0] AVG Duty = 5109%(X100)
7253 00:59:12.687004
7254 00:59:12.690339 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7255 00:59:12.690415
7256 00:59:12.693932 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7257 00:59:12.696888 [DutyScan_Calibration_Flow] ====Done====
7258 00:59:12.696965
7259 00:59:12.700368 [DutyScan_Calibration_Flow] k_type=3
7260 00:59:12.718612
7261 00:59:12.718691 ==DQM 0 ==
7262 00:59:12.721911 Final DQM duty delay cell = 0
7263 00:59:12.725290 [0] MAX Duty = 5156%(X100), DQS PI = 14
7264 00:59:12.728753 [0] MIN Duty = 4844%(X100), DQS PI = 52
7265 00:59:12.731946 [0] AVG Duty = 5000%(X100)
7266 00:59:12.732013
7267 00:59:12.732106 ==DQM 1 ==
7268 00:59:12.735232 Final DQM duty delay cell = 4
7269 00:59:12.738259 [4] MAX Duty = 5187%(X100), DQS PI = 62
7270 00:59:12.741812 [4] MIN Duty = 5000%(X100), DQS PI = 40
7271 00:59:12.745304 [4] AVG Duty = 5093%(X100)
7272 00:59:12.745380
7273 00:59:12.748626 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7274 00:59:12.748763
7275 00:59:12.751719 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7276 00:59:12.754995 [DutyScan_Calibration_Flow] ====Done====
7277 00:59:12.755071
7278 00:59:12.758467 [DutyScan_Calibration_Flow] k_type=2
7279 00:59:12.775250
7280 00:59:12.775325 ==DQ 0 ==
7281 00:59:12.777977 Final DQ duty delay cell = -4
7282 00:59:12.781723 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7283 00:59:12.785092 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7284 00:59:12.788374 [-4] AVG Duty = 4938%(X100)
7285 00:59:12.788449
7286 00:59:12.788507 ==DQ 1 ==
7287 00:59:12.791741 Final DQ duty delay cell = 0
7288 00:59:12.794698 [0] MAX Duty = 5156%(X100), DQS PI = 60
7289 00:59:12.798223 [0] MIN Duty = 5000%(X100), DQS PI = 16
7290 00:59:12.801735 [0] AVG Duty = 5078%(X100)
7291 00:59:12.801809
7292 00:59:12.804707 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7293 00:59:12.804806
7294 00:59:12.808221 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7295 00:59:12.811284 [DutyScan_Calibration_Flow] ====Done====
7296 00:59:12.811359 ==
7297 00:59:12.814717 Dram Type= 6, Freq= 0, CH_1, rank 0
7298 00:59:12.818050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 00:59:12.818126 ==
7300 00:59:12.821603 [Duty_Offset_Calibration]
7301 00:59:12.821678 B0:1 B1:-2 CA:0
7302 00:59:12.821737
7303 00:59:12.824500 [DutyScan_Calibration_Flow] k_type=0
7304 00:59:12.835602
7305 00:59:12.835684 ==CLK 0==
7306 00:59:12.838809 Final CLK duty delay cell = 0
7307 00:59:12.842200 [0] MAX Duty = 5031%(X100), DQS PI = 52
7308 00:59:12.845642 [0] MIN Duty = 4876%(X100), DQS PI = 26
7309 00:59:12.845718 [0] AVG Duty = 4953%(X100)
7310 00:59:12.848629
7311 00:59:12.852032 CH1 CLK Duty spec in!! Max-Min= 155%
7312 00:59:12.855571 [DutyScan_Calibration_Flow] ====Done====
7313 00:59:12.855640
7314 00:59:12.858949 [DutyScan_Calibration_Flow] k_type=1
7315 00:59:12.875445
7316 00:59:12.875549 ==DQS 0 ==
7317 00:59:12.878396 Final DQS duty delay cell = 0
7318 00:59:12.882147 [0] MAX Duty = 5156%(X100), DQS PI = 38
7319 00:59:12.885146 [0] MIN Duty = 5062%(X100), DQS PI = 14
7320 00:59:12.885212 [0] AVG Duty = 5109%(X100)
7321 00:59:12.888513
7322 00:59:12.888576 ==DQS 1 ==
7323 00:59:12.891880 Final DQS duty delay cell = 0
7324 00:59:12.895448 [0] MAX Duty = 5093%(X100), DQS PI = 24
7325 00:59:12.898918 [0] MIN Duty = 4813%(X100), DQS PI = 58
7326 00:59:12.901808 [0] AVG Duty = 4953%(X100)
7327 00:59:12.901922
7328 00:59:12.905460 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7329 00:59:12.905562
7330 00:59:12.908793 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7331 00:59:12.911779 [DutyScan_Calibration_Flow] ====Done====
7332 00:59:12.911854
7333 00:59:12.915324 [DutyScan_Calibration_Flow] k_type=3
7334 00:59:12.932027
7335 00:59:12.932101 ==DQM 0 ==
7336 00:59:12.935508 Final DQM duty delay cell = 0
7337 00:59:12.938867 [0] MAX Duty = 5000%(X100), DQS PI = 58
7338 00:59:12.942393 [0] MIN Duty = 4844%(X100), DQS PI = 22
7339 00:59:12.945383 [0] AVG Duty = 4922%(X100)
7340 00:59:12.945463
7341 00:59:12.945521 ==DQM 1 ==
7342 00:59:12.948782 Final DQM duty delay cell = 0
7343 00:59:12.952391 [0] MAX Duty = 5031%(X100), DQS PI = 2
7344 00:59:12.955396 [0] MIN Duty = 4875%(X100), DQS PI = 34
7345 00:59:12.958797 [0] AVG Duty = 4953%(X100)
7346 00:59:12.958872
7347 00:59:12.962481 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7348 00:59:12.962607
7349 00:59:12.965305 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7350 00:59:12.968870 [DutyScan_Calibration_Flow] ====Done====
7351 00:59:12.968946
7352 00:59:12.972280 [DutyScan_Calibration_Flow] k_type=2
7353 00:59:12.988747
7354 00:59:12.988822 ==DQ 0 ==
7355 00:59:12.992241 Final DQ duty delay cell = 0
7356 00:59:12.995761 [0] MAX Duty = 5062%(X100), DQS PI = 0
7357 00:59:12.998960 [0] MIN Duty = 4938%(X100), DQS PI = 24
7358 00:59:12.999037 [0] AVG Duty = 5000%(X100)
7359 00:59:13.002603
7360 00:59:13.002705 ==DQ 1 ==
7361 00:59:13.005634 Final DQ duty delay cell = 0
7362 00:59:13.008541 [0] MAX Duty = 5156%(X100), DQS PI = 26
7363 00:59:13.012191 [0] MIN Duty = 4938%(X100), DQS PI = 56
7364 00:59:13.012266 [0] AVG Duty = 5047%(X100)
7365 00:59:13.015696
7366 00:59:13.018643 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7367 00:59:13.018734
7368 00:59:13.022303 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7369 00:59:13.025162 [DutyScan_Calibration_Flow] ====Done====
7370 00:59:13.028585 nWR fixed to 30
7371 00:59:13.028699 [ModeRegInit_LP4] CH0 RK0
7372 00:59:13.032157 [ModeRegInit_LP4] CH0 RK1
7373 00:59:13.035708 [ModeRegInit_LP4] CH1 RK0
7374 00:59:13.038724 [ModeRegInit_LP4] CH1 RK1
7375 00:59:13.038799 match AC timing 5
7376 00:59:13.042157 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7377 00:59:13.048559 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7378 00:59:13.052245 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7379 00:59:13.058438 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7380 00:59:13.062115 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7381 00:59:13.062204 [MiockJmeterHQA]
7382 00:59:13.062262
7383 00:59:13.065414 [DramcMiockJmeter] u1RxGatingPI = 0
7384 00:59:13.068553 0 : 4253, 4026
7385 00:59:13.068629 4 : 4255, 4029
7386 00:59:13.071570 8 : 4257, 4029
7387 00:59:13.071647 12 : 4253, 4026
7388 00:59:13.071706 16 : 4252, 4027
7389 00:59:13.075280 20 : 4363, 4137
7390 00:59:13.075356 24 : 4252, 4026
7391 00:59:13.078508 28 : 4363, 4138
7392 00:59:13.078585 32 : 4252, 4027
7393 00:59:13.082244 36 : 4252, 4027
7394 00:59:13.082375 40 : 4253, 4027
7395 00:59:13.082462 44 : 4254, 4029
7396 00:59:13.085833 48 : 4363, 4137
7397 00:59:13.085908 52 : 4252, 4027
7398 00:59:13.088532 56 : 4363, 4137
7399 00:59:13.088608 60 : 4252, 4027
7400 00:59:13.091704 64 : 4250, 4027
7401 00:59:13.091781 68 : 4250, 4027
7402 00:59:13.094981 72 : 4361, 4137
7403 00:59:13.095081 76 : 4250, 4027
7404 00:59:13.095172 80 : 4361, 4137
7405 00:59:13.098305 84 : 4250, 4027
7406 00:59:13.098382 88 : 4250, 4026
7407 00:59:13.101795 92 : 4250, 4027
7408 00:59:13.101890 96 : 4252, 4029
7409 00:59:13.105045 100 : 4361, 4137
7410 00:59:13.105141 104 : 4250, 3391
7411 00:59:13.108470 108 : 4250, 1
7412 00:59:13.108561 112 : 4250, 0
7413 00:59:13.108650 116 : 4253, 0
7414 00:59:13.111873 120 : 4250, 0
7415 00:59:13.111950 124 : 4250, 0
7416 00:59:13.114832 128 : 4250, 0
7417 00:59:13.114908 132 : 4252, 0
7418 00:59:13.114968 136 : 4361, 0
7419 00:59:13.118366 140 : 4250, 0
7420 00:59:13.118466 144 : 4250, 0
7421 00:59:13.118554 148 : 4250, 0
7422 00:59:13.122046 152 : 4360, 0
7423 00:59:13.122122 156 : 4361, 0
7424 00:59:13.125078 160 : 4250, 0
7425 00:59:13.125155 164 : 4250, 0
7426 00:59:13.125215 168 : 4363, 0
7427 00:59:13.128524 172 : 4250, 0
7428 00:59:13.128600 176 : 4250, 0
7429 00:59:13.131873 180 : 4250, 0
7430 00:59:13.131941 184 : 4252, 0
7431 00:59:13.131998 188 : 4361, 0
7432 00:59:13.134767 192 : 4250, 0
7433 00:59:13.134840 196 : 4250, 0
7434 00:59:13.138153 200 : 4360, 0
7435 00:59:13.138216 204 : 4360, 0
7436 00:59:13.138268 208 : 4363, 0
7437 00:59:13.141501 212 : 4250, 0
7438 00:59:13.141577 216 : 4361, 0
7439 00:59:13.141637 220 : 4250, 0
7440 00:59:13.144944 224 : 4250, 0
7441 00:59:13.145021 228 : 4250, 0
7442 00:59:13.148360 232 : 4250, 0
7443 00:59:13.148436 236 : 4252, 1332
7444 00:59:13.151502 240 : 4252, 4029
7445 00:59:13.151578 244 : 4363, 4140
7446 00:59:13.151638 248 : 4361, 4137
7447 00:59:13.154506 252 : 4248, 4024
7448 00:59:13.154607 256 : 4363, 4140
7449 00:59:13.158211 260 : 4361, 4137
7450 00:59:13.158287 264 : 4250, 4027
7451 00:59:13.161225 268 : 4250, 4027
7452 00:59:13.161303 272 : 4253, 4029
7453 00:59:13.164820 276 : 4250, 4027
7454 00:59:13.164911 280 : 4250, 4027
7455 00:59:13.167777 284 : 4250, 4027
7456 00:59:13.167854 288 : 4252, 4029
7457 00:59:13.171299 292 : 4250, 4027
7458 00:59:13.171375 296 : 4360, 4138
7459 00:59:13.174677 300 : 4361, 4137
7460 00:59:13.174753 304 : 4250, 4027
7461 00:59:13.177970 308 : 4363, 4140
7462 00:59:13.178070 312 : 4250, 4027
7463 00:59:13.178157 316 : 4250, 4027
7464 00:59:13.181128 320 : 4250, 4027
7465 00:59:13.181261 324 : 4252, 4029
7466 00:59:13.184222 328 : 4250, 4027
7467 00:59:13.184312 332 : 4250, 4027
7468 00:59:13.187769 336 : 4250, 4026
7469 00:59:13.187846 340 : 4252, 4029
7470 00:59:13.191205 344 : 4250, 4027
7471 00:59:13.191282 348 : 4360, 4138
7472 00:59:13.194150 352 : 4361, 4130
7473 00:59:13.194227 356 : 4250, 2625
7474 00:59:13.197560 360 : 4363, 0
7475 00:59:13.197637
7476 00:59:13.197695 MIOCK jitter meter ch=0
7477 00:59:13.197750
7478 00:59:13.201431 1T = (360-108) = 252 dly cells
7479 00:59:13.207677 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7480 00:59:13.207753 ==
7481 00:59:13.211218 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 00:59:13.214459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7483 00:59:13.214543 ==
7484 00:59:13.221024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7485 00:59:13.224309 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7486 00:59:13.227652 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7487 00:59:13.234370 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7488 00:59:13.244006 [CA 0] Center 44 (14~74) winsize 61
7489 00:59:13.247146 [CA 1] Center 43 (13~74) winsize 62
7490 00:59:13.250549 [CA 2] Center 39 (10~68) winsize 59
7491 00:59:13.254115 [CA 3] Center 39 (10~68) winsize 59
7492 00:59:13.257113 [CA 4] Center 37 (8~66) winsize 59
7493 00:59:13.260600 [CA 5] Center 36 (7~66) winsize 60
7494 00:59:13.260715
7495 00:59:13.263609 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7496 00:59:13.263707
7497 00:59:13.270520 [CATrainingPosCal] consider 1 rank data
7498 00:59:13.270596 u2DelayCellTimex100 = 258/100 ps
7499 00:59:13.276938 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7500 00:59:13.280536 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7501 00:59:13.283952 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7502 00:59:13.287141 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7503 00:59:13.290477 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7504 00:59:13.293638 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7505 00:59:13.293714
7506 00:59:13.296743 CA PerBit enable=1, Macro0, CA PI delay=36
7507 00:59:13.296822
7508 00:59:13.300277 [CBTSetCACLKResult] CA Dly = 36
7509 00:59:13.303743 CS Dly: 11 (0~42)
7510 00:59:13.306663 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7511 00:59:13.310124 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7512 00:59:13.310200 ==
7513 00:59:13.313642 Dram Type= 6, Freq= 0, CH_0, rank 1
7514 00:59:13.320130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7515 00:59:13.320230 ==
7516 00:59:13.323585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7517 00:59:13.329770 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7518 00:59:13.333269 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7519 00:59:13.339786 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7520 00:59:13.348153 [CA 0] Center 43 (13~74) winsize 62
7521 00:59:13.351241 [CA 1] Center 43 (13~74) winsize 62
7522 00:59:13.354247 [CA 2] Center 39 (10~68) winsize 59
7523 00:59:13.357875 [CA 3] Center 39 (10~68) winsize 59
7524 00:59:13.361085 [CA 4] Center 36 (6~66) winsize 61
7525 00:59:13.364292 [CA 5] Center 36 (6~66) winsize 61
7526 00:59:13.364373
7527 00:59:13.367822 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7528 00:59:13.367900
7529 00:59:13.374404 [CATrainingPosCal] consider 2 rank data
7530 00:59:13.374482 u2DelayCellTimex100 = 258/100 ps
7531 00:59:13.380870 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7532 00:59:13.384292 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7533 00:59:13.387615 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7534 00:59:13.391007 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7535 00:59:13.394454 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7536 00:59:13.397295 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7537 00:59:13.397372
7538 00:59:13.400988 CA PerBit enable=1, Macro0, CA PI delay=36
7539 00:59:13.401065
7540 00:59:13.403912 [CBTSetCACLKResult] CA Dly = 36
7541 00:59:13.407495 CS Dly: 11 (0~43)
7542 00:59:13.410487 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7543 00:59:13.414037 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7544 00:59:13.414115
7545 00:59:13.417649 ----->DramcWriteLeveling(PI) begin...
7546 00:59:13.420394 ==
7547 00:59:13.420471 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 00:59:13.427563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 00:59:13.427640 ==
7550 00:59:13.430522 Write leveling (Byte 0): 35 => 35
7551 00:59:13.434019 Write leveling (Byte 1): 28 => 28
7552 00:59:13.437031 DramcWriteLeveling(PI) end<-----
7553 00:59:13.437108
7554 00:59:13.437172 ==
7555 00:59:13.440655 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 00:59:13.443614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 00:59:13.443713 ==
7558 00:59:13.447143 [Gating] SW mode calibration
7559 00:59:13.453620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7560 00:59:13.460382 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7561 00:59:13.463565 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 00:59:13.467201 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 00:59:13.470604 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 00:59:13.477171 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 00:59:13.480361 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7566 00:59:13.483631 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7567 00:59:13.489865 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7568 00:59:13.493247 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 00:59:13.496808 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 00:59:13.503296 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 00:59:13.506716 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 00:59:13.509915 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7573 00:59:13.516871 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7574 00:59:13.519893 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7575 00:59:13.523408 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7576 00:59:13.529728 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 00:59:13.533432 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 00:59:13.536432 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 00:59:13.543114 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 00:59:13.546547 1 6 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7581 00:59:13.550227 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
7582 00:59:13.556567 1 6 20 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
7583 00:59:13.559798 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7584 00:59:13.563096 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 00:59:13.569584 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 00:59:13.573053 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 00:59:13.576520 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 00:59:13.582968 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 00:59:13.586423 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7590 00:59:13.589753 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 00:59:13.596769 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7592 00:59:13.599524 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 00:59:13.602933 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 00:59:13.609769 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 00:59:13.613089 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 00:59:13.616423 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 00:59:13.619754 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 00:59:13.626374 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 00:59:13.629827 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:59:13.632812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:59:13.639537 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:59:13.642764 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:59:13.646245 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 00:59:13.652713 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 00:59:13.656166 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 00:59:13.659765 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 00:59:13.662720 Total UI for P1: 0, mck2ui 16
7608 00:59:13.666065 best dqsien dly found for B0: ( 1, 9, 16)
7609 00:59:13.672818 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 00:59:13.676009 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 00:59:13.679424 Total UI for P1: 0, mck2ui 16
7612 00:59:13.682414 best dqsien dly found for B1: ( 1, 9, 22)
7613 00:59:13.685996 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7614 00:59:13.689580 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7615 00:59:13.689655
7616 00:59:13.692491 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7617 00:59:13.696012 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7618 00:59:13.699664 [Gating] SW calibration Done
7619 00:59:13.699739 ==
7620 00:59:13.702657 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 00:59:13.709104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 00:59:13.709179 ==
7623 00:59:13.709238 RX Vref Scan: 0
7624 00:59:13.709292
7625 00:59:13.712840 RX Vref 0 -> 0, step: 1
7626 00:59:13.712914
7627 00:59:13.712972 RX Delay 0 -> 252, step: 8
7628 00:59:13.719598 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7629 00:59:13.723184 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7630 00:59:13.726400 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7631 00:59:13.729264 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7632 00:59:13.732778 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7633 00:59:13.739398 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7634 00:59:13.742496 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7635 00:59:13.745762 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7636 00:59:13.749323 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7637 00:59:13.752929 iDelay=192, Bit 9, Center 107 (48 ~ 167) 120
7638 00:59:13.759028 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7639 00:59:13.762547 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7640 00:59:13.766076 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7641 00:59:13.769055 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7642 00:59:13.775696 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7643 00:59:13.779492 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7644 00:59:13.779568 ==
7645 00:59:13.782276 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 00:59:13.785948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 00:59:13.786023 ==
7648 00:59:13.786082 DQS Delay:
7649 00:59:13.789466 DQS0 = 0, DQS1 = 0
7650 00:59:13.789541 DQM Delay:
7651 00:59:13.792371 DQM0 = 127, DQM1 = 123
7652 00:59:13.792446 DQ Delay:
7653 00:59:13.795882 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7654 00:59:13.799256 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7655 00:59:13.802639 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7656 00:59:13.809108 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7657 00:59:13.809183
7658 00:59:13.809240
7659 00:59:13.809294 ==
7660 00:59:13.812775 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 00:59:13.815687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 00:59:13.815763 ==
7663 00:59:13.815822
7664 00:59:13.815876
7665 00:59:13.819159 TX Vref Scan disable
7666 00:59:13.819234 == TX Byte 0 ==
7667 00:59:13.825862 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7668 00:59:13.829251 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7669 00:59:13.829327 == TX Byte 1 ==
7670 00:59:13.835641 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7671 00:59:13.838967 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7672 00:59:13.839043 ==
7673 00:59:13.842236 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 00:59:13.845458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 00:59:13.845534 ==
7676 00:59:13.860081
7677 00:59:13.863393 TX Vref early break, caculate TX vref
7678 00:59:13.867014 TX Vref=16, minBit 4, minWin=21, winSum=359
7679 00:59:13.869831 TX Vref=18, minBit 8, minWin=22, winSum=369
7680 00:59:13.873335 TX Vref=20, minBit 8, minWin=22, winSum=376
7681 00:59:13.876497 TX Vref=22, minBit 4, minWin=23, winSum=389
7682 00:59:13.880016 TX Vref=24, minBit 8, minWin=23, winSum=396
7683 00:59:13.886467 TX Vref=26, minBit 8, minWin=24, winSum=407
7684 00:59:13.890210 TX Vref=28, minBit 8, minWin=23, winSum=405
7685 00:59:13.893127 TX Vref=30, minBit 8, minWin=23, winSum=398
7686 00:59:13.896746 TX Vref=32, minBit 8, minWin=22, winSum=390
7687 00:59:13.900335 TX Vref=34, minBit 8, minWin=21, winSum=380
7688 00:59:13.906829 [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 26
7689 00:59:13.906904
7690 00:59:13.910332 Final TX Range 0 Vref 26
7691 00:59:13.910398
7692 00:59:13.910453 ==
7693 00:59:13.913269 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 00:59:13.916800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 00:59:13.916866 ==
7696 00:59:13.916923
7697 00:59:13.916978
7698 00:59:13.919763 TX Vref Scan disable
7699 00:59:13.926724 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7700 00:59:13.926794 == TX Byte 0 ==
7701 00:59:13.929905 u2DelayCellOfst[0]=15 cells (4 PI)
7702 00:59:13.933200 u2DelayCellOfst[1]=18 cells (5 PI)
7703 00:59:13.936276 u2DelayCellOfst[2]=15 cells (4 PI)
7704 00:59:13.939733 u2DelayCellOfst[3]=11 cells (3 PI)
7705 00:59:13.943286 u2DelayCellOfst[4]=7 cells (2 PI)
7706 00:59:13.946421 u2DelayCellOfst[5]=0 cells (0 PI)
7707 00:59:13.949709 u2DelayCellOfst[6]=18 cells (5 PI)
7708 00:59:13.953139 u2DelayCellOfst[7]=22 cells (6 PI)
7709 00:59:13.956576 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7710 00:59:13.959867 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7711 00:59:13.962826 == TX Byte 1 ==
7712 00:59:13.962891 u2DelayCellOfst[8]=0 cells (0 PI)
7713 00:59:13.966389 u2DelayCellOfst[9]=0 cells (0 PI)
7714 00:59:13.969785 u2DelayCellOfst[10]=7 cells (2 PI)
7715 00:59:13.972744 u2DelayCellOfst[11]=3 cells (1 PI)
7716 00:59:13.976229 u2DelayCellOfst[12]=11 cells (3 PI)
7717 00:59:13.979472 u2DelayCellOfst[13]=11 cells (3 PI)
7718 00:59:13.982989 u2DelayCellOfst[14]=15 cells (4 PI)
7719 00:59:13.986343 u2DelayCellOfst[15]=11 cells (3 PI)
7720 00:59:13.989290 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7721 00:59:13.996103 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7722 00:59:13.996176 DramC Write-DBI on
7723 00:59:13.996233 ==
7724 00:59:13.999395 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 00:59:14.002795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 00:59:14.006071 ==
7727 00:59:14.006135
7728 00:59:14.006190
7729 00:59:14.006242 TX Vref Scan disable
7730 00:59:14.009868 == TX Byte 0 ==
7731 00:59:14.012860 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7732 00:59:14.016358 == TX Byte 1 ==
7733 00:59:14.019926 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7734 00:59:14.019994 DramC Write-DBI off
7735 00:59:14.022691
7736 00:59:14.022756 [DATLAT]
7737 00:59:14.022811 Freq=1600, CH0 RK0
7738 00:59:14.022867
7739 00:59:14.026280 DATLAT Default: 0xf
7740 00:59:14.026346 0, 0xFFFF, sum = 0
7741 00:59:14.029816 1, 0xFFFF, sum = 0
7742 00:59:14.029882 2, 0xFFFF, sum = 0
7743 00:59:14.032764 3, 0xFFFF, sum = 0
7744 00:59:14.036085 4, 0xFFFF, sum = 0
7745 00:59:14.036174 5, 0xFFFF, sum = 0
7746 00:59:14.039227 6, 0xFFFF, sum = 0
7747 00:59:14.039291 7, 0xFFFF, sum = 0
7748 00:59:14.042640 8, 0xFFFF, sum = 0
7749 00:59:14.042707 9, 0xFFFF, sum = 0
7750 00:59:14.046136 10, 0xFFFF, sum = 0
7751 00:59:14.046200 11, 0xFFFF, sum = 0
7752 00:59:14.049054 12, 0xFFFF, sum = 0
7753 00:59:14.049118 13, 0xEFFF, sum = 0
7754 00:59:14.052540 14, 0x0, sum = 1
7755 00:59:14.052629 15, 0x0, sum = 2
7756 00:59:14.055841 16, 0x0, sum = 3
7757 00:59:14.055906 17, 0x0, sum = 4
7758 00:59:14.059509 best_step = 15
7759 00:59:14.059572
7760 00:59:14.059648 ==
7761 00:59:14.062667 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 00:59:14.065984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 00:59:14.066053 ==
7764 00:59:14.069122 RX Vref Scan: 1
7765 00:59:14.069189
7766 00:59:14.069248 Set Vref Range= 24 -> 127
7767 00:59:14.069300
7768 00:59:14.072613 RX Vref 24 -> 127, step: 1
7769 00:59:14.072736
7770 00:59:14.076104 RX Delay 3 -> 252, step: 4
7771 00:59:14.076167
7772 00:59:14.078975 Set Vref, RX VrefLevel [Byte0]: 24
7773 00:59:14.082504 [Byte1]: 24
7774 00:59:14.082567
7775 00:59:14.085398 Set Vref, RX VrefLevel [Byte0]: 25
7776 00:59:14.088962 [Byte1]: 25
7777 00:59:14.092546
7778 00:59:14.092633 Set Vref, RX VrefLevel [Byte0]: 26
7779 00:59:14.095784 [Byte1]: 26
7780 00:59:14.100264
7781 00:59:14.100333 Set Vref, RX VrefLevel [Byte0]: 27
7782 00:59:14.103141 [Byte1]: 27
7783 00:59:14.107431
7784 00:59:14.107496 Set Vref, RX VrefLevel [Byte0]: 28
7785 00:59:14.110862 [Byte1]: 28
7786 00:59:14.115425
7787 00:59:14.115490 Set Vref, RX VrefLevel [Byte0]: 29
7788 00:59:14.118615 [Byte1]: 29
7789 00:59:14.123127
7790 00:59:14.123196 Set Vref, RX VrefLevel [Byte0]: 30
7791 00:59:14.126136 [Byte1]: 30
7792 00:59:14.130878
7793 00:59:14.130947 Set Vref, RX VrefLevel [Byte0]: 31
7794 00:59:14.133867 [Byte1]: 31
7795 00:59:14.138039
7796 00:59:14.138108 Set Vref, RX VrefLevel [Byte0]: 32
7797 00:59:14.141500 [Byte1]: 32
7798 00:59:14.145775
7799 00:59:14.145840 Set Vref, RX VrefLevel [Byte0]: 33
7800 00:59:14.148947 [Byte1]: 33
7801 00:59:14.153580
7802 00:59:14.153646 Set Vref, RX VrefLevel [Byte0]: 34
7803 00:59:14.157132 [Byte1]: 34
7804 00:59:14.161323
7805 00:59:14.161388 Set Vref, RX VrefLevel [Byte0]: 35
7806 00:59:14.164638 [Byte1]: 35
7807 00:59:14.168681
7808 00:59:14.168747 Set Vref, RX VrefLevel [Byte0]: 36
7809 00:59:14.171915 [Byte1]: 36
7810 00:59:14.176578
7811 00:59:14.176716 Set Vref, RX VrefLevel [Byte0]: 37
7812 00:59:14.179828 [Byte1]: 37
7813 00:59:14.184337
7814 00:59:14.184403 Set Vref, RX VrefLevel [Byte0]: 38
7815 00:59:14.187231 [Byte1]: 38
7816 00:59:14.191906
7817 00:59:14.191971 Set Vref, RX VrefLevel [Byte0]: 39
7818 00:59:14.194825 [Byte1]: 39
7819 00:59:14.199423
7820 00:59:14.199489 Set Vref, RX VrefLevel [Byte0]: 40
7821 00:59:14.202722 [Byte1]: 40
7822 00:59:14.207329
7823 00:59:14.207396 Set Vref, RX VrefLevel [Byte0]: 41
7824 00:59:14.210264 [Byte1]: 41
7825 00:59:14.215060
7826 00:59:14.215130 Set Vref, RX VrefLevel [Byte0]: 42
7827 00:59:14.218014 [Byte1]: 42
7828 00:59:14.222178
7829 00:59:14.222249 Set Vref, RX VrefLevel [Byte0]: 43
7830 00:59:14.225584 [Byte1]: 43
7831 00:59:14.229968
7832 00:59:14.230034 Set Vref, RX VrefLevel [Byte0]: 44
7833 00:59:14.233334 [Byte1]: 44
7834 00:59:14.237700
7835 00:59:14.237766 Set Vref, RX VrefLevel [Byte0]: 45
7836 00:59:14.240791 [Byte1]: 45
7837 00:59:14.245567
7838 00:59:14.245637 Set Vref, RX VrefLevel [Byte0]: 46
7839 00:59:14.248898 [Byte1]: 46
7840 00:59:14.253288
7841 00:59:14.253356 Set Vref, RX VrefLevel [Byte0]: 47
7842 00:59:14.256370 [Byte1]: 47
7843 00:59:14.260870
7844 00:59:14.260936 Set Vref, RX VrefLevel [Byte0]: 48
7845 00:59:14.263848 [Byte1]: 48
7846 00:59:14.268125
7847 00:59:14.268194 Set Vref, RX VrefLevel [Byte0]: 49
7848 00:59:14.271626 [Byte1]: 49
7849 00:59:14.276197
7850 00:59:14.276265 Set Vref, RX VrefLevel [Byte0]: 50
7851 00:59:14.279532 [Byte1]: 50
7852 00:59:14.283331
7853 00:59:14.283401 Set Vref, RX VrefLevel [Byte0]: 51
7854 00:59:14.286775 [Byte1]: 51
7855 00:59:14.291169
7856 00:59:14.291242 Set Vref, RX VrefLevel [Byte0]: 52
7857 00:59:14.294670 [Byte1]: 52
7858 00:59:14.298796
7859 00:59:14.298917 Set Vref, RX VrefLevel [Byte0]: 53
7860 00:59:14.302353 [Byte1]: 53
7861 00:59:14.306393
7862 00:59:14.306456 Set Vref, RX VrefLevel [Byte0]: 54
7863 00:59:14.310086 [Byte1]: 54
7864 00:59:14.314251
7865 00:59:14.314319 Set Vref, RX VrefLevel [Byte0]: 55
7866 00:59:14.317244 [Byte1]: 55
7867 00:59:14.321909
7868 00:59:14.321973 Set Vref, RX VrefLevel [Byte0]: 56
7869 00:59:14.324878 [Byte1]: 56
7870 00:59:14.329703
7871 00:59:14.329771 Set Vref, RX VrefLevel [Byte0]: 57
7872 00:59:14.332652 [Byte1]: 57
7873 00:59:14.337333
7874 00:59:14.337397 Set Vref, RX VrefLevel [Byte0]: 58
7875 00:59:14.340221 [Byte1]: 58
7876 00:59:14.344840
7877 00:59:14.344902 Set Vref, RX VrefLevel [Byte0]: 59
7878 00:59:14.348223 [Byte1]: 59
7879 00:59:14.352459
7880 00:59:14.352547 Set Vref, RX VrefLevel [Byte0]: 60
7881 00:59:14.355923 [Byte1]: 60
7882 00:59:14.360219
7883 00:59:14.360287 Set Vref, RX VrefLevel [Byte0]: 61
7884 00:59:14.363475 [Byte1]: 61
7885 00:59:14.367718
7886 00:59:14.367781 Set Vref, RX VrefLevel [Byte0]: 62
7887 00:59:14.371066 [Byte1]: 62
7888 00:59:14.375193
7889 00:59:14.375263 Set Vref, RX VrefLevel [Byte0]: 63
7890 00:59:14.378896 [Byte1]: 63
7891 00:59:14.383343
7892 00:59:14.383413 Set Vref, RX VrefLevel [Byte0]: 64
7893 00:59:14.386282 [Byte1]: 64
7894 00:59:14.390843
7895 00:59:14.390910 Set Vref, RX VrefLevel [Byte0]: 65
7896 00:59:14.394220 [Byte1]: 65
7897 00:59:14.398268
7898 00:59:14.398346 Set Vref, RX VrefLevel [Byte0]: 66
7899 00:59:14.401653 [Byte1]: 66
7900 00:59:14.406347
7901 00:59:14.406422 Set Vref, RX VrefLevel [Byte0]: 67
7902 00:59:14.409164 [Byte1]: 67
7903 00:59:14.413804
7904 00:59:14.413876 Set Vref, RX VrefLevel [Byte0]: 68
7905 00:59:14.416899 [Byte1]: 68
7906 00:59:14.421582
7907 00:59:14.421653 Set Vref, RX VrefLevel [Byte0]: 69
7908 00:59:14.424447 [Byte1]: 69
7909 00:59:14.429186
7910 00:59:14.429257 Set Vref, RX VrefLevel [Byte0]: 70
7911 00:59:14.432060 [Byte1]: 70
7912 00:59:14.436891
7913 00:59:14.436958 Set Vref, RX VrefLevel [Byte0]: 71
7914 00:59:14.439900 [Byte1]: 71
7915 00:59:14.444476
7916 00:59:14.444546 Set Vref, RX VrefLevel [Byte0]: 72
7917 00:59:14.447519 [Byte1]: 72
7918 00:59:14.451720
7919 00:59:14.451796 Set Vref, RX VrefLevel [Byte0]: 73
7920 00:59:14.455308 [Byte1]: 73
7921 00:59:14.459389
7922 00:59:14.459495 Set Vref, RX VrefLevel [Byte0]: 74
7923 00:59:14.462735 [Byte1]: 74
7924 00:59:14.467448
7925 00:59:14.467548 Set Vref, RX VrefLevel [Byte0]: 75
7926 00:59:14.470844 [Byte1]: 75
7927 00:59:14.475056
7928 00:59:14.475127 Final RX Vref Byte 0 = 64 to rank0
7929 00:59:14.478212 Final RX Vref Byte 1 = 58 to rank0
7930 00:59:14.481333 Final RX Vref Byte 0 = 64 to rank1
7931 00:59:14.485020 Final RX Vref Byte 1 = 58 to rank1==
7932 00:59:14.488457 Dram Type= 6, Freq= 0, CH_0, rank 0
7933 00:59:14.494931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7934 00:59:14.495003 ==
7935 00:59:14.495063 DQS Delay:
7936 00:59:14.495123 DQS0 = 0, DQS1 = 0
7937 00:59:14.498421 DQM Delay:
7938 00:59:14.498487 DQM0 = 126, DQM1 = 119
7939 00:59:14.501471 DQ Delay:
7940 00:59:14.504490 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7941 00:59:14.507872 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7942 00:59:14.511322 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7943 00:59:14.514509 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7944 00:59:14.514579
7945 00:59:14.514637
7946 00:59:14.514691
7947 00:59:14.517890 [DramC_TX_OE_Calibration] TA2
7948 00:59:14.521344 Original DQ_B0 (3 6) =30, OEN = 27
7949 00:59:14.524852 Original DQ_B1 (3 6) =30, OEN = 27
7950 00:59:14.527602 24, 0x0, End_B0=24 End_B1=24
7951 00:59:14.527701 25, 0x0, End_B0=25 End_B1=25
7952 00:59:14.531157 26, 0x0, End_B0=26 End_B1=26
7953 00:59:14.534622 27, 0x0, End_B0=27 End_B1=27
7954 00:59:14.537533 28, 0x0, End_B0=28 End_B1=28
7955 00:59:14.541041 29, 0x0, End_B0=29 End_B1=29
7956 00:59:14.541113 30, 0x0, End_B0=30 End_B1=30
7957 00:59:14.544581 31, 0x4141, End_B0=30 End_B1=30
7958 00:59:14.547545 Byte0 end_step=30 best_step=27
7959 00:59:14.551205 Byte1 end_step=30 best_step=27
7960 00:59:14.554104 Byte0 TX OE(2T, 0.5T) = (3, 3)
7961 00:59:14.557717 Byte1 TX OE(2T, 0.5T) = (3, 3)
7962 00:59:14.557791
7963 00:59:14.557848
7964 00:59:14.564156 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7965 00:59:14.567342 CH0 RK0: MR19=303, MR18=1717
7966 00:59:14.573865 CH0_RK0: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
7967 00:59:14.573932
7968 00:59:14.577363 ----->DramcWriteLeveling(PI) begin...
7969 00:59:14.577427 ==
7970 00:59:14.580241 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 00:59:14.583902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 00:59:14.583967 ==
7973 00:59:14.586880 Write leveling (Byte 0): 36 => 36
7974 00:59:14.590421 Write leveling (Byte 1): 28 => 28
7975 00:59:14.593925 DramcWriteLeveling(PI) end<-----
7976 00:59:14.593991
7977 00:59:14.594059 ==
7978 00:59:14.596861 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 00:59:14.600235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 00:59:14.603447 ==
7981 00:59:14.603511 [Gating] SW mode calibration
7982 00:59:14.613372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7983 00:59:14.616597 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7984 00:59:14.620239 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 00:59:14.626821 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 00:59:14.630048 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 00:59:14.633742 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7988 00:59:14.640419 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7989 00:59:14.643308 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 00:59:14.646371 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 00:59:14.653521 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 00:59:14.656333 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 00:59:14.659949 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7994 00:59:14.666469 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 00:59:14.669884 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7996 00:59:14.672796 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7997 00:59:14.679832 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7998 00:59:14.682828 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 00:59:14.686245 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 00:59:14.693354 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 00:59:14.696214 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 00:59:14.699793 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8003 00:59:14.706177 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8004 00:59:14.709531 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
8005 00:59:14.712927 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8006 00:59:14.719121 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 00:59:14.722653 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 00:59:14.725624 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 00:59:14.732300 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 00:59:14.735828 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 00:59:14.739146 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8012 00:59:14.745808 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8013 00:59:14.748873 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8014 00:59:14.752419 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 00:59:14.758849 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 00:59:14.762410 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 00:59:14.765471 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 00:59:14.771835 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 00:59:14.775266 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 00:59:14.778770 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 00:59:14.785211 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:59:14.788716 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:59:14.792201 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:59:14.798840 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 00:59:14.801937 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8026 00:59:14.805543 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8027 00:59:14.811960 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8028 00:59:14.815384 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8029 00:59:14.818316 Total UI for P1: 0, mck2ui 16
8030 00:59:14.821618 best dqsien dly found for B0: ( 1, 9, 8)
8031 00:59:14.825455 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8032 00:59:14.828363 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 00:59:14.831909 Total UI for P1: 0, mck2ui 16
8034 00:59:14.834827 best dqsien dly found for B1: ( 1, 9, 18)
8035 00:59:14.838224 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8036 00:59:14.844975 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8037 00:59:14.845043
8038 00:59:14.848379 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8039 00:59:14.851409 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8040 00:59:14.854969 [Gating] SW calibration Done
8041 00:59:14.855032 ==
8042 00:59:14.858372 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 00:59:14.861748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 00:59:14.861814 ==
8045 00:59:14.865017 RX Vref Scan: 0
8046 00:59:14.865083
8047 00:59:14.865139 RX Vref 0 -> 0, step: 1
8048 00:59:14.865191
8049 00:59:14.868225 RX Delay 0 -> 252, step: 8
8050 00:59:14.871299 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8051 00:59:14.874638 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8052 00:59:14.881368 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8053 00:59:14.884893 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8054 00:59:14.888311 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8055 00:59:14.891294 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8056 00:59:14.894888 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8057 00:59:14.901435 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8058 00:59:14.904512 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8059 00:59:14.907753 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8060 00:59:14.911453 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8061 00:59:14.914389 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8062 00:59:14.921392 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8063 00:59:14.924349 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8064 00:59:14.927713 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8065 00:59:14.931541 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8066 00:59:14.931610 ==
8067 00:59:14.934527 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 00:59:14.941065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 00:59:14.941136 ==
8070 00:59:14.941213 DQS Delay:
8071 00:59:14.944361 DQS0 = 0, DQS1 = 0
8072 00:59:14.944453 DQM Delay:
8073 00:59:14.947818 DQM0 = 127, DQM1 = 121
8074 00:59:14.947891 DQ Delay:
8075 00:59:14.951236 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8076 00:59:14.954870 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8077 00:59:14.957785 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8078 00:59:14.960673 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8079 00:59:14.960741
8080 00:59:14.960816
8081 00:59:14.960885 ==
8082 00:59:14.964110 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 00:59:14.971030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 00:59:14.971102 ==
8085 00:59:14.971178
8086 00:59:14.971247
8087 00:59:14.971315 TX Vref Scan disable
8088 00:59:14.974023 == TX Byte 0 ==
8089 00:59:14.977510 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8090 00:59:14.980860 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8091 00:59:14.983967 == TX Byte 1 ==
8092 00:59:14.987358 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8093 00:59:14.994247 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8094 00:59:14.994323 ==
8095 00:59:14.997515 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 00:59:15.000555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 00:59:15.000663 ==
8098 00:59:15.015425
8099 00:59:15.018635 TX Vref early break, caculate TX vref
8100 00:59:15.021654 TX Vref=16, minBit 9, minWin=21, winSum=369
8101 00:59:15.024993 TX Vref=18, minBit 8, minWin=22, winSum=379
8102 00:59:15.028596 TX Vref=20, minBit 8, minWin=22, winSum=388
8103 00:59:15.031971 TX Vref=22, minBit 8, minWin=23, winSum=395
8104 00:59:15.035206 TX Vref=24, minBit 8, minWin=24, winSum=403
8105 00:59:15.042151 TX Vref=26, minBit 8, minWin=24, winSum=405
8106 00:59:15.045072 TX Vref=28, minBit 9, minWin=24, winSum=413
8107 00:59:15.048686 TX Vref=30, minBit 8, minWin=24, winSum=410
8108 00:59:15.051942 TX Vref=32, minBit 8, minWin=23, winSum=402
8109 00:59:15.055265 TX Vref=34, minBit 8, minWin=23, winSum=394
8110 00:59:15.058539 TX Vref=36, minBit 8, minWin=22, winSum=387
8111 00:59:15.064974 [TxChooseVref] Worse bit 9, Min win 24, Win sum 413, Final Vref 28
8112 00:59:15.065046
8113 00:59:15.068491 Final TX Range 0 Vref 28
8114 00:59:15.068560
8115 00:59:15.068654 ==
8116 00:59:15.071868 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 00:59:15.074865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 00:59:15.074933 ==
8119 00:59:15.075006
8120 00:59:15.078345
8121 00:59:15.078412 TX Vref Scan disable
8122 00:59:15.085177 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8123 00:59:15.085251 == TX Byte 0 ==
8124 00:59:15.087997 u2DelayCellOfst[0]=11 cells (3 PI)
8125 00:59:15.091528 u2DelayCellOfst[1]=18 cells (5 PI)
8126 00:59:15.095082 u2DelayCellOfst[2]=11 cells (3 PI)
8127 00:59:15.098037 u2DelayCellOfst[3]=11 cells (3 PI)
8128 00:59:15.101357 u2DelayCellOfst[4]=7 cells (2 PI)
8129 00:59:15.104676 u2DelayCellOfst[5]=0 cells (0 PI)
8130 00:59:15.108397 u2DelayCellOfst[6]=18 cells (5 PI)
8131 00:59:15.111560 u2DelayCellOfst[7]=15 cells (4 PI)
8132 00:59:15.114762 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8133 00:59:15.118381 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8134 00:59:15.121384 == TX Byte 1 ==
8135 00:59:15.124807 u2DelayCellOfst[8]=0 cells (0 PI)
8136 00:59:15.127950 u2DelayCellOfst[9]=3 cells (1 PI)
8137 00:59:15.128020 u2DelayCellOfst[10]=7 cells (2 PI)
8138 00:59:15.131466 u2DelayCellOfst[11]=7 cells (2 PI)
8139 00:59:15.135133 u2DelayCellOfst[12]=11 cells (3 PI)
8140 00:59:15.138468 u2DelayCellOfst[13]=11 cells (3 PI)
8141 00:59:15.141199 u2DelayCellOfst[14]=15 cells (4 PI)
8142 00:59:15.144598 u2DelayCellOfst[15]=15 cells (4 PI)
8143 00:59:15.151552 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8144 00:59:15.154472 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8145 00:59:15.154541 DramC Write-DBI on
8146 00:59:15.154619 ==
8147 00:59:15.158366 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 00:59:15.164209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 00:59:15.164284 ==
8150 00:59:15.164358
8151 00:59:15.164428
8152 00:59:15.164520 TX Vref Scan disable
8153 00:59:15.168587 == TX Byte 0 ==
8154 00:59:15.172176 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8155 00:59:15.175555 == TX Byte 1 ==
8156 00:59:15.178513 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8157 00:59:15.182176 DramC Write-DBI off
8158 00:59:15.182244
8159 00:59:15.182320 [DATLAT]
8160 00:59:15.182388 Freq=1600, CH0 RK1
8161 00:59:15.182456
8162 00:59:15.185557 DATLAT Default: 0xf
8163 00:59:15.185623 0, 0xFFFF, sum = 0
8164 00:59:15.188424 1, 0xFFFF, sum = 0
8165 00:59:15.191898 2, 0xFFFF, sum = 0
8166 00:59:15.191966 3, 0xFFFF, sum = 0
8167 00:59:15.195296 4, 0xFFFF, sum = 0
8168 00:59:15.195366 5, 0xFFFF, sum = 0
8169 00:59:15.198311 6, 0xFFFF, sum = 0
8170 00:59:15.198379 7, 0xFFFF, sum = 0
8171 00:59:15.201880 8, 0xFFFF, sum = 0
8172 00:59:15.201948 9, 0xFFFF, sum = 0
8173 00:59:15.205377 10, 0xFFFF, sum = 0
8174 00:59:15.205445 11, 0xFFFF, sum = 0
8175 00:59:15.208353 12, 0xFFFF, sum = 0
8176 00:59:15.208420 13, 0xCFFF, sum = 0
8177 00:59:15.211976 14, 0x0, sum = 1
8178 00:59:15.212043 15, 0x0, sum = 2
8179 00:59:15.214974 16, 0x0, sum = 3
8180 00:59:15.215056 17, 0x0, sum = 4
8181 00:59:15.218360 best_step = 15
8182 00:59:15.218426
8183 00:59:15.218487 ==
8184 00:59:15.221648 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 00:59:15.225593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 00:59:15.225662 ==
8187 00:59:15.225720 RX Vref Scan: 0
8188 00:59:15.228190
8189 00:59:15.228274 RX Vref 0 -> 0, step: 1
8190 00:59:15.228331
8191 00:59:15.231701 RX Delay 3 -> 252, step: 4
8192 00:59:15.235089 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8193 00:59:15.241973 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8194 00:59:15.244853 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8195 00:59:15.248213 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8196 00:59:15.251791 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8197 00:59:15.254988 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8198 00:59:15.261609 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8199 00:59:15.265013 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8200 00:59:15.268473 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8201 00:59:15.271830 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8202 00:59:15.274951 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8203 00:59:15.281634 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8204 00:59:15.284617 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8205 00:59:15.288172 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8206 00:59:15.291492 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8207 00:59:15.294958 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8208 00:59:15.298390 ==
8209 00:59:15.301884 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 00:59:15.304881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 00:59:15.304952 ==
8212 00:59:15.305026 DQS Delay:
8213 00:59:15.307891 DQS0 = 0, DQS1 = 0
8214 00:59:15.307958 DQM Delay:
8215 00:59:15.311503 DQM0 = 124, DQM1 = 118
8216 00:59:15.311571 DQ Delay:
8217 00:59:15.314856 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8218 00:59:15.318357 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =134
8219 00:59:15.321230 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8220 00:59:15.324721 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8221 00:59:15.324790
8222 00:59:15.324863
8223 00:59:15.324938
8224 00:59:15.328277 [DramC_TX_OE_Calibration] TA2
8225 00:59:15.331613 Original DQ_B0 (3 6) =30, OEN = 27
8226 00:59:15.334694 Original DQ_B1 (3 6) =30, OEN = 27
8227 00:59:15.338471 24, 0x0, End_B0=24 End_B1=24
8228 00:59:15.341304 25, 0x0, End_B0=25 End_B1=25
8229 00:59:15.341379 26, 0x0, End_B0=26 End_B1=26
8230 00:59:15.344842 27, 0x0, End_B0=27 End_B1=27
8231 00:59:15.347757 28, 0x0, End_B0=28 End_B1=28
8232 00:59:15.351128 29, 0x0, End_B0=29 End_B1=29
8233 00:59:15.354285 30, 0x0, End_B0=30 End_B1=30
8234 00:59:15.354357 31, 0x4545, End_B0=30 End_B1=30
8235 00:59:15.357734 Byte0 end_step=30 best_step=27
8236 00:59:15.361056 Byte1 end_step=30 best_step=27
8237 00:59:15.364556 Byte0 TX OE(2T, 0.5T) = (3, 3)
8238 00:59:15.367673 Byte1 TX OE(2T, 0.5T) = (3, 3)
8239 00:59:15.367742
8240 00:59:15.367814
8241 00:59:15.374282 [DQSOSCAuto] RK1, (LSB)MR18= 0x2311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8242 00:59:15.377659 CH0 RK1: MR19=303, MR18=2311
8243 00:59:15.384296 CH0_RK1: MR19=0x303, MR18=0x2311, DQSOSC=392, MR23=63, INC=24, DEC=16
8244 00:59:15.387288 [RxdqsGatingPostProcess] freq 1600
8245 00:59:15.394255 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8246 00:59:15.397679 best DQS0 dly(2T, 0.5T) = (1, 1)
8247 00:59:15.397752 best DQS1 dly(2T, 0.5T) = (1, 1)
8248 00:59:15.400945 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8249 00:59:15.403967 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8250 00:59:15.407474 best DQS0 dly(2T, 0.5T) = (1, 1)
8251 00:59:15.410392 best DQS1 dly(2T, 0.5T) = (1, 1)
8252 00:59:15.413891 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8253 00:59:15.417444 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8254 00:59:15.420744 Pre-setting of DQS Precalculation
8255 00:59:15.423638 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8256 00:59:15.427186 ==
8257 00:59:15.427256 Dram Type= 6, Freq= 0, CH_1, rank 0
8258 00:59:15.434139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 00:59:15.434215 ==
8260 00:59:15.436988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8261 00:59:15.443912 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8262 00:59:15.447111 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8263 00:59:15.453769 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8264 00:59:15.461860 [CA 0] Center 41 (12~70) winsize 59
8265 00:59:15.465234 [CA 1] Center 42 (12~72) winsize 61
8266 00:59:15.468397 [CA 2] Center 37 (8~66) winsize 59
8267 00:59:15.471595 [CA 3] Center 37 (8~66) winsize 59
8268 00:59:15.475142 [CA 4] Center 37 (8~67) winsize 60
8269 00:59:15.478038 [CA 5] Center 35 (6~65) winsize 60
8270 00:59:15.478110
8271 00:59:15.481595 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8272 00:59:15.481669
8273 00:59:15.484607 [CATrainingPosCal] consider 1 rank data
8274 00:59:15.488434 u2DelayCellTimex100 = 258/100 ps
8275 00:59:15.491257 CA0 delay=41 (12~70),Diff = 6 PI (22 cell)
8276 00:59:15.497780 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8277 00:59:15.501479 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8278 00:59:15.504715 CA3 delay=37 (8~66),Diff = 2 PI (7 cell)
8279 00:59:15.508262 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8280 00:59:15.511332 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8281 00:59:15.511406
8282 00:59:15.514843 CA PerBit enable=1, Macro0, CA PI delay=35
8283 00:59:15.514914
8284 00:59:15.517815 [CBTSetCACLKResult] CA Dly = 35
8285 00:59:15.521453 CS Dly: 10 (0~41)
8286 00:59:15.524906 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8287 00:59:15.528154 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8288 00:59:15.528223 ==
8289 00:59:15.531052 Dram Type= 6, Freq= 0, CH_1, rank 1
8290 00:59:15.534543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 00:59:15.538132 ==
8292 00:59:15.541146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8293 00:59:15.544749 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8294 00:59:15.551164 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8295 00:59:15.557883 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8296 00:59:15.565071 [CA 0] Center 42 (13~72) winsize 60
8297 00:59:15.568578 [CA 1] Center 42 (12~72) winsize 61
8298 00:59:15.571442 [CA 2] Center 38 (9~67) winsize 59
8299 00:59:15.574778 [CA 3] Center 36 (7~66) winsize 60
8300 00:59:15.578203 [CA 4] Center 38 (8~68) winsize 61
8301 00:59:15.581758 [CA 5] Center 36 (6~66) winsize 61
8302 00:59:15.581827
8303 00:59:15.585013 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8304 00:59:15.585078
8305 00:59:15.588265 [CATrainingPosCal] consider 2 rank data
8306 00:59:15.591390 u2DelayCellTimex100 = 258/100 ps
8307 00:59:15.594811 CA0 delay=41 (13~70),Diff = 6 PI (22 cell)
8308 00:59:15.601627 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8309 00:59:15.604916 CA2 delay=37 (9~66),Diff = 2 PI (7 cell)
8310 00:59:15.608302 CA3 delay=37 (8~66),Diff = 2 PI (7 cell)
8311 00:59:15.611283 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8312 00:59:15.614820 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8313 00:59:15.614894
8314 00:59:15.618413 CA PerBit enable=1, Macro0, CA PI delay=35
8315 00:59:15.618484
8316 00:59:15.621402 [CBTSetCACLKResult] CA Dly = 35
8317 00:59:15.624929 CS Dly: 11 (0~43)
8318 00:59:15.628382 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8319 00:59:15.631671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8320 00:59:15.631742
8321 00:59:15.634761 ----->DramcWriteLeveling(PI) begin...
8322 00:59:15.634834 ==
8323 00:59:15.638241 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 00:59:15.641792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 00:59:15.644858 ==
8326 00:59:15.644929 Write leveling (Byte 0): 27 => 27
8327 00:59:15.648465 Write leveling (Byte 1): 29 => 29
8328 00:59:15.651491 DramcWriteLeveling(PI) end<-----
8329 00:59:15.651556
8330 00:59:15.651610 ==
8331 00:59:15.655024 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 00:59:15.661509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 00:59:15.661577 ==
8334 00:59:15.661634 [Gating] SW mode calibration
8335 00:59:15.671549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8336 00:59:15.674714 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8337 00:59:15.681385 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 00:59:15.684987 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 00:59:15.687940 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 00:59:15.691357 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 00:59:15.697630 1 4 16 | B1->B0 | 3333 3433 | 1 1 | (1 1) (1 1)
8342 00:59:15.701214 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 00:59:15.704524 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 00:59:15.711069 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 00:59:15.714592 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 00:59:15.717945 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 00:59:15.724391 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 00:59:15.727800 1 5 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
8349 00:59:15.731159 1 5 16 | B1->B0 | 2525 2525 | 0 0 | (0 0) (1 0)
8350 00:59:15.737653 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8351 00:59:15.741293 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 00:59:15.744245 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 00:59:15.750796 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 00:59:15.754363 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 00:59:15.757419 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 00:59:15.764458 1 6 12 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
8357 00:59:15.767485 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8358 00:59:15.770955 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 00:59:15.777387 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 00:59:15.781071 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 00:59:15.784132 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 00:59:15.790676 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 00:59:15.794260 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 00:59:15.797342 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 00:59:15.804124 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8366 00:59:15.807121 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 00:59:15.810673 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 00:59:15.817312 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 00:59:15.820465 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 00:59:15.823624 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 00:59:15.830457 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 00:59:15.833661 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 00:59:15.837046 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:59:15.843619 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 00:59:15.846706 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 00:59:15.850009 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:59:15.857048 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:59:15.860088 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 00:59:15.863738 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 00:59:15.870228 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 00:59:15.873804 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8382 00:59:15.877255 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 00:59:15.880258 Total UI for P1: 0, mck2ui 16
8384 00:59:15.883251 best dqsien dly found for B0: ( 1, 9, 14)
8385 00:59:15.886804 Total UI for P1: 0, mck2ui 16
8386 00:59:15.890302 best dqsien dly found for B1: ( 1, 9, 14)
8387 00:59:15.893196 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8388 00:59:15.896536 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8389 00:59:15.896637
8390 00:59:15.900103 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8391 00:59:15.906680 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8392 00:59:15.906751 [Gating] SW calibration Done
8393 00:59:15.906810 ==
8394 00:59:15.909788 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 00:59:15.916805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 00:59:15.916877 ==
8397 00:59:15.916935 RX Vref Scan: 0
8398 00:59:15.916989
8399 00:59:15.919701 RX Vref 0 -> 0, step: 1
8400 00:59:15.919765
8401 00:59:15.923230 RX Delay 0 -> 252, step: 8
8402 00:59:15.926515 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8403 00:59:15.929829 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8404 00:59:15.933070 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8405 00:59:15.939885 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8406 00:59:15.943399 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8407 00:59:15.946287 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8408 00:59:15.949595 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8409 00:59:15.953277 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8410 00:59:15.959360 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8411 00:59:15.962721 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8412 00:59:15.966298 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8413 00:59:15.969872 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8414 00:59:15.972885 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8415 00:59:15.979544 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8416 00:59:15.983094 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8417 00:59:15.986106 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8418 00:59:15.986176 ==
8419 00:59:15.989144 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 00:59:15.992637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 00:59:15.996223 ==
8422 00:59:15.996308 DQS Delay:
8423 00:59:15.996380 DQS0 = 0, DQS1 = 0
8424 00:59:15.999757 DQM Delay:
8425 00:59:15.999824 DQM0 = 132, DQM1 = 125
8426 00:59:16.002696 DQ Delay:
8427 00:59:16.006320 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8428 00:59:16.009615 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8429 00:59:16.012794 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8430 00:59:16.016119 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8431 00:59:16.016186
8432 00:59:16.016247
8433 00:59:16.016299 ==
8434 00:59:16.019442 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 00:59:16.022474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 00:59:16.022539 ==
8437 00:59:16.022593
8438 00:59:16.022650
8439 00:59:16.025984 TX Vref Scan disable
8440 00:59:16.029109 == TX Byte 0 ==
8441 00:59:16.032529 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8442 00:59:16.036269 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8443 00:59:16.039598 == TX Byte 1 ==
8444 00:59:16.042638 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8445 00:59:16.045746 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8446 00:59:16.045814 ==
8447 00:59:16.048890 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 00:59:16.055740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 00:59:16.055815 ==
8450 00:59:16.068110
8451 00:59:16.071246 TX Vref early break, caculate TX vref
8452 00:59:16.075094 TX Vref=16, minBit 9, minWin=20, winSum=360
8453 00:59:16.078036 TX Vref=18, minBit 8, minWin=21, winSum=370
8454 00:59:16.081603 TX Vref=20, minBit 11, minWin=21, winSum=374
8455 00:59:16.084594 TX Vref=22, minBit 9, minWin=22, winSum=388
8456 00:59:16.088208 TX Vref=24, minBit 8, minWin=24, winSum=402
8457 00:59:16.094716 TX Vref=26, minBit 10, minWin=24, winSum=410
8458 00:59:16.098204 TX Vref=28, minBit 9, minWin=24, winSum=411
8459 00:59:16.101196 TX Vref=30, minBit 0, minWin=25, winSum=412
8460 00:59:16.104867 TX Vref=32, minBit 8, minWin=24, winSum=402
8461 00:59:16.107857 TX Vref=34, minBit 8, minWin=23, winSum=392
8462 00:59:16.111385 TX Vref=36, minBit 0, minWin=23, winSum=384
8463 00:59:16.118021 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 30
8464 00:59:16.118090
8465 00:59:16.121087 Final TX Range 0 Vref 30
8466 00:59:16.121151
8467 00:59:16.121229 ==
8468 00:59:16.124545 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 00:59:16.128411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 00:59:16.128480 ==
8471 00:59:16.128542
8472 00:59:16.131268
8473 00:59:16.131331 TX Vref Scan disable
8474 00:59:16.138100 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8475 00:59:16.138172 == TX Byte 0 ==
8476 00:59:16.141266 u2DelayCellOfst[0]=18 cells (5 PI)
8477 00:59:16.144272 u2DelayCellOfst[1]=11 cells (3 PI)
8478 00:59:16.147818 u2DelayCellOfst[2]=0 cells (0 PI)
8479 00:59:16.150977 u2DelayCellOfst[3]=7 cells (2 PI)
8480 00:59:16.154359 u2DelayCellOfst[4]=7 cells (2 PI)
8481 00:59:16.157885 u2DelayCellOfst[5]=22 cells (6 PI)
8482 00:59:16.161253 u2DelayCellOfst[6]=18 cells (5 PI)
8483 00:59:16.164350 u2DelayCellOfst[7]=7 cells (2 PI)
8484 00:59:16.167665 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8485 00:59:16.171073 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8486 00:59:16.174509 == TX Byte 1 ==
8487 00:59:16.178190 u2DelayCellOfst[8]=0 cells (0 PI)
8488 00:59:16.178314 u2DelayCellOfst[9]=7 cells (2 PI)
8489 00:59:16.180829 u2DelayCellOfst[10]=11 cells (3 PI)
8490 00:59:16.184737 u2DelayCellOfst[11]=7 cells (2 PI)
8491 00:59:16.187663 u2DelayCellOfst[12]=15 cells (4 PI)
8492 00:59:16.190727 u2DelayCellOfst[13]=18 cells (5 PI)
8493 00:59:16.194284 u2DelayCellOfst[14]=18 cells (5 PI)
8494 00:59:16.197896 u2DelayCellOfst[15]=18 cells (5 PI)
8495 00:59:16.204301 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8496 00:59:16.207808 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8497 00:59:16.207877 DramC Write-DBI on
8498 00:59:16.207935 ==
8499 00:59:16.210759 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 00:59:16.217249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 00:59:16.217318 ==
8502 00:59:16.217379
8503 00:59:16.217432
8504 00:59:16.217483 TX Vref Scan disable
8505 00:59:16.221363 == TX Byte 0 ==
8506 00:59:16.225036 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8507 00:59:16.227884 == TX Byte 1 ==
8508 00:59:16.231936 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8509 00:59:16.234627 DramC Write-DBI off
8510 00:59:16.234693
8511 00:59:16.234749 [DATLAT]
8512 00:59:16.234838 Freq=1600, CH1 RK0
8513 00:59:16.234891
8514 00:59:16.238387 DATLAT Default: 0xf
8515 00:59:16.238499 0, 0xFFFF, sum = 0
8516 00:59:16.241267 1, 0xFFFF, sum = 0
8517 00:59:16.244795 2, 0xFFFF, sum = 0
8518 00:59:16.244860 3, 0xFFFF, sum = 0
8519 00:59:16.248104 4, 0xFFFF, sum = 0
8520 00:59:16.248171 5, 0xFFFF, sum = 0
8521 00:59:16.251572 6, 0xFFFF, sum = 0
8522 00:59:16.251634 7, 0xFFFF, sum = 0
8523 00:59:16.254385 8, 0xFFFF, sum = 0
8524 00:59:16.254448 9, 0xFFFF, sum = 0
8525 00:59:16.257911 10, 0xFFFF, sum = 0
8526 00:59:16.257976 11, 0xFFFF, sum = 0
8527 00:59:16.261278 12, 0xFFFF, sum = 0
8528 00:59:16.261345 13, 0x8FFF, sum = 0
8529 00:59:16.264769 14, 0x0, sum = 1
8530 00:59:16.264834 15, 0x0, sum = 2
8531 00:59:16.268014 16, 0x0, sum = 3
8532 00:59:16.268077 17, 0x0, sum = 4
8533 00:59:16.271092 best_step = 15
8534 00:59:16.271158
8535 00:59:16.271211 ==
8536 00:59:16.274655 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 00:59:16.277964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 00:59:16.278030 ==
8539 00:59:16.281217 RX Vref Scan: 1
8540 00:59:16.281284
8541 00:59:16.281339 Set Vref Range= 24 -> 127
8542 00:59:16.281392
8543 00:59:16.284304 RX Vref 24 -> 127, step: 1
8544 00:59:16.284370
8545 00:59:16.288003 RX Delay 11 -> 252, step: 4
8546 00:59:16.288068
8547 00:59:16.291118 Set Vref, RX VrefLevel [Byte0]: 24
8548 00:59:16.294303 [Byte1]: 24
8549 00:59:16.294378
8550 00:59:16.297529 Set Vref, RX VrefLevel [Byte0]: 25
8551 00:59:16.301093 [Byte1]: 25
8552 00:59:16.304070
8553 00:59:16.304141 Set Vref, RX VrefLevel [Byte0]: 26
8554 00:59:16.307707 [Byte1]: 26
8555 00:59:16.311893
8556 00:59:16.311962 Set Vref, RX VrefLevel [Byte0]: 27
8557 00:59:16.314863 [Byte1]: 27
8558 00:59:16.319538
8559 00:59:16.319607 Set Vref, RX VrefLevel [Byte0]: 28
8560 00:59:16.323228 [Byte1]: 28
8561 00:59:16.327284
8562 00:59:16.327353 Set Vref, RX VrefLevel [Byte0]: 29
8563 00:59:16.330269 [Byte1]: 29
8564 00:59:16.334926
8565 00:59:16.334994 Set Vref, RX VrefLevel [Byte0]: 30
8566 00:59:16.337894 [Byte1]: 30
8567 00:59:16.342388
8568 00:59:16.342485 Set Vref, RX VrefLevel [Byte0]: 31
8569 00:59:16.345519 [Byte1]: 31
8570 00:59:16.349855
8571 00:59:16.349922 Set Vref, RX VrefLevel [Byte0]: 32
8572 00:59:16.353137 [Byte1]: 32
8573 00:59:16.357449
8574 00:59:16.357520 Set Vref, RX VrefLevel [Byte0]: 33
8575 00:59:16.360984 [Byte1]: 33
8576 00:59:16.364843
8577 00:59:16.364914 Set Vref, RX VrefLevel [Byte0]: 34
8578 00:59:16.368288 [Byte1]: 34
8579 00:59:16.372930
8580 00:59:16.373001 Set Vref, RX VrefLevel [Byte0]: 35
8581 00:59:16.375961 [Byte1]: 35
8582 00:59:16.380391
8583 00:59:16.380459 Set Vref, RX VrefLevel [Byte0]: 36
8584 00:59:16.383486 [Byte1]: 36
8585 00:59:16.387728
8586 00:59:16.387801 Set Vref, RX VrefLevel [Byte0]: 37
8587 00:59:16.391262 [Byte1]: 37
8588 00:59:16.395444
8589 00:59:16.395515 Set Vref, RX VrefLevel [Byte0]: 38
8590 00:59:16.398810 [Byte1]: 38
8591 00:59:16.403267
8592 00:59:16.403339 Set Vref, RX VrefLevel [Byte0]: 39
8593 00:59:16.406326 [Byte1]: 39
8594 00:59:16.410553
8595 00:59:16.410627 Set Vref, RX VrefLevel [Byte0]: 40
8596 00:59:16.414352 [Byte1]: 40
8597 00:59:16.418487
8598 00:59:16.418560 Set Vref, RX VrefLevel [Byte0]: 41
8599 00:59:16.421554 [Byte1]: 41
8600 00:59:16.426296
8601 00:59:16.426365 Set Vref, RX VrefLevel [Byte0]: 42
8602 00:59:16.429238 [Byte1]: 42
8603 00:59:16.433887
8604 00:59:16.433957 Set Vref, RX VrefLevel [Byte0]: 43
8605 00:59:16.436899 [Byte1]: 43
8606 00:59:16.441500
8607 00:59:16.441568 Set Vref, RX VrefLevel [Byte0]: 44
8608 00:59:16.444416 [Byte1]: 44
8609 00:59:16.449067
8610 00:59:16.449135 Set Vref, RX VrefLevel [Byte0]: 45
8611 00:59:16.452347 [Byte1]: 45
8612 00:59:16.456769
8613 00:59:16.456838 Set Vref, RX VrefLevel [Byte0]: 46
8614 00:59:16.459987 [Byte1]: 46
8615 00:59:16.464333
8616 00:59:16.464424 Set Vref, RX VrefLevel [Byte0]: 47
8617 00:59:16.467241 [Byte1]: 47
8618 00:59:16.471670
8619 00:59:16.471738 Set Vref, RX VrefLevel [Byte0]: 48
8620 00:59:16.475032 [Byte1]: 48
8621 00:59:16.479257
8622 00:59:16.479327 Set Vref, RX VrefLevel [Byte0]: 49
8623 00:59:16.482798 [Byte1]: 49
8624 00:59:16.486766
8625 00:59:16.486837 Set Vref, RX VrefLevel [Byte0]: 50
8626 00:59:16.490192 [Byte1]: 50
8627 00:59:16.494308
8628 00:59:16.494380 Set Vref, RX VrefLevel [Byte0]: 51
8629 00:59:16.497701 [Byte1]: 51
8630 00:59:16.502031
8631 00:59:16.502105 Set Vref, RX VrefLevel [Byte0]: 52
8632 00:59:16.505373 [Byte1]: 52
8633 00:59:16.509891
8634 00:59:16.509978 Set Vref, RX VrefLevel [Byte0]: 53
8635 00:59:16.513213 [Byte1]: 53
8636 00:59:16.517310
8637 00:59:16.517382 Set Vref, RX VrefLevel [Byte0]: 54
8638 00:59:16.520471 [Byte1]: 54
8639 00:59:16.524890
8640 00:59:16.524964 Set Vref, RX VrefLevel [Byte0]: 55
8641 00:59:16.528346 [Byte1]: 55
8642 00:59:16.532417
8643 00:59:16.532491 Set Vref, RX VrefLevel [Byte0]: 56
8644 00:59:16.535835 [Byte1]: 56
8645 00:59:16.539944
8646 00:59:16.540017 Set Vref, RX VrefLevel [Byte0]: 57
8647 00:59:16.543414 [Byte1]: 57
8648 00:59:16.548193
8649 00:59:16.548264 Set Vref, RX VrefLevel [Byte0]: 58
8650 00:59:16.551083 [Byte1]: 58
8651 00:59:16.555174
8652 00:59:16.555245 Set Vref, RX VrefLevel [Byte0]: 59
8653 00:59:16.558584 [Byte1]: 59
8654 00:59:16.563001
8655 00:59:16.563070 Set Vref, RX VrefLevel [Byte0]: 60
8656 00:59:16.566450 [Byte1]: 60
8657 00:59:16.570759
8658 00:59:16.570827 Set Vref, RX VrefLevel [Byte0]: 61
8659 00:59:16.573924 [Byte1]: 61
8660 00:59:16.578372
8661 00:59:16.578440 Set Vref, RX VrefLevel [Byte0]: 62
8662 00:59:16.581463 [Byte1]: 62
8663 00:59:16.585625
8664 00:59:16.585697 Set Vref, RX VrefLevel [Byte0]: 63
8665 00:59:16.589023 [Byte1]: 63
8666 00:59:16.593773
8667 00:59:16.593846 Set Vref, RX VrefLevel [Byte0]: 64
8668 00:59:16.596599 [Byte1]: 64
8669 00:59:16.600810
8670 00:59:16.600908 Set Vref, RX VrefLevel [Byte0]: 65
8671 00:59:16.604328 [Byte1]: 65
8672 00:59:16.608424
8673 00:59:16.608516 Set Vref, RX VrefLevel [Byte0]: 66
8674 00:59:16.612019 [Byte1]: 66
8675 00:59:16.616561
8676 00:59:16.616678 Set Vref, RX VrefLevel [Byte0]: 67
8677 00:59:16.619514 [Byte1]: 67
8678 00:59:16.623826
8679 00:59:16.623926 Set Vref, RX VrefLevel [Byte0]: 68
8680 00:59:16.626997 [Byte1]: 68
8681 00:59:16.631535
8682 00:59:16.631610 Set Vref, RX VrefLevel [Byte0]: 69
8683 00:59:16.634684 [Byte1]: 69
8684 00:59:16.639452
8685 00:59:16.639524 Set Vref, RX VrefLevel [Byte0]: 70
8686 00:59:16.642438 [Byte1]: 70
8687 00:59:16.647014
8688 00:59:16.647088 Final RX Vref Byte 0 = 59 to rank0
8689 00:59:16.650038 Final RX Vref Byte 1 = 57 to rank0
8690 00:59:16.653598 Final RX Vref Byte 0 = 59 to rank1
8691 00:59:16.656716 Final RX Vref Byte 1 = 57 to rank1==
8692 00:59:16.660086 Dram Type= 6, Freq= 0, CH_1, rank 0
8693 00:59:16.666507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8694 00:59:16.666590 ==
8695 00:59:16.666665 DQS Delay:
8696 00:59:16.666736 DQS0 = 0, DQS1 = 0
8697 00:59:16.670457 DQM Delay:
8698 00:59:16.670533 DQM0 = 131, DQM1 = 123
8699 00:59:16.673380 DQ Delay:
8700 00:59:16.676771 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8701 00:59:16.680095 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8702 00:59:16.683372 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8703 00:59:16.686348 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8704 00:59:16.686425
8705 00:59:16.686500
8706 00:59:16.686569
8707 00:59:16.690089 [DramC_TX_OE_Calibration] TA2
8708 00:59:16.693338 Original DQ_B0 (3 6) =30, OEN = 27
8709 00:59:16.696853 Original DQ_B1 (3 6) =30, OEN = 27
8710 00:59:16.699732 24, 0x0, End_B0=24 End_B1=24
8711 00:59:16.699808 25, 0x0, End_B0=25 End_B1=25
8712 00:59:16.703350 26, 0x0, End_B0=26 End_B1=26
8713 00:59:16.706309 27, 0x0, End_B0=27 End_B1=27
8714 00:59:16.709882 28, 0x0, End_B0=28 End_B1=28
8715 00:59:16.712822 29, 0x0, End_B0=29 End_B1=29
8716 00:59:16.712901 30, 0x0, End_B0=30 End_B1=30
8717 00:59:16.716197 31, 0x4141, End_B0=30 End_B1=30
8718 00:59:16.719748 Byte0 end_step=30 best_step=27
8719 00:59:16.722679 Byte1 end_step=30 best_step=27
8720 00:59:16.726256 Byte0 TX OE(2T, 0.5T) = (3, 3)
8721 00:59:16.729376 Byte1 TX OE(2T, 0.5T) = (3, 3)
8722 00:59:16.729453
8723 00:59:16.729534
8724 00:59:16.736054 [DQSOSCAuto] RK0, (LSB)MR18= 0xa10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
8725 00:59:16.739388 CH1 RK0: MR19=303, MR18=A10
8726 00:59:16.746267 CH1_RK0: MR19=0x303, MR18=0xA10, DQSOSC=401, MR23=63, INC=22, DEC=15
8727 00:59:16.746341
8728 00:59:16.749347 ----->DramcWriteLeveling(PI) begin...
8729 00:59:16.749421 ==
8730 00:59:16.752874 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 00:59:16.756383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 00:59:16.756455 ==
8733 00:59:16.759340 Write leveling (Byte 0): 22 => 22
8734 00:59:16.762823 Write leveling (Byte 1): 28 => 28
8735 00:59:16.766256 DramcWriteLeveling(PI) end<-----
8736 00:59:16.766329
8737 00:59:16.766403 ==
8738 00:59:16.769185 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 00:59:16.772745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 00:59:16.772816 ==
8741 00:59:16.775833 [Gating] SW mode calibration
8742 00:59:16.782421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8743 00:59:16.789296 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8744 00:59:16.792613 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 00:59:16.795746 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 00:59:16.802138 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8747 00:59:16.806039 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8748 00:59:16.808994 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 00:59:16.815999 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 00:59:16.819038 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 00:59:16.822570 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 00:59:16.829355 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 00:59:16.832302 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 00:59:16.835839 1 5 8 | B1->B0 | 3434 2626 | 0 0 | (0 1) (1 0)
8755 00:59:16.842706 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 00:59:16.845564 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 00:59:16.849082 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 00:59:16.855471 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 00:59:16.858961 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 00:59:16.862576 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 00:59:16.868842 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 00:59:16.872396 1 6 8 | B1->B0 | 2727 4141 | 1 0 | (0 0) (0 0)
8763 00:59:16.875319 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8764 00:59:16.882189 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 00:59:16.885288 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 00:59:16.888883 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 00:59:16.895342 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 00:59:16.898867 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 00:59:16.902239 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 00:59:16.908642 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8771 00:59:16.911831 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8772 00:59:16.915207 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 00:59:16.922006 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 00:59:16.924879 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:59:16.928416 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:59:16.934915 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:59:16.938274 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:59:16.941590 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:59:16.948401 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:59:16.951632 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 00:59:16.954796 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 00:59:16.961688 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 00:59:16.964615 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:59:16.968426 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:59:16.974636 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8786 00:59:16.978196 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8787 00:59:16.981151 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8788 00:59:16.984616 Total UI for P1: 0, mck2ui 16
8789 00:59:16.988142 best dqsien dly found for B0: ( 1, 9, 6)
8790 00:59:16.991577 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 00:59:16.994921 Total UI for P1: 0, mck2ui 16
8792 00:59:16.997907 best dqsien dly found for B1: ( 1, 9, 10)
8793 00:59:17.001566 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8794 00:59:17.007875 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8795 00:59:17.007955
8796 00:59:17.011436 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8797 00:59:17.014750 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8798 00:59:17.018005 [Gating] SW calibration Done
8799 00:59:17.018079 ==
8800 00:59:17.021226 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 00:59:17.024573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 00:59:17.024694 ==
8803 00:59:17.027490 RX Vref Scan: 0
8804 00:59:17.027564
8805 00:59:17.027623 RX Vref 0 -> 0, step: 1
8806 00:59:17.027679
8807 00:59:17.031000 RX Delay 0 -> 252, step: 8
8808 00:59:17.034576 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8809 00:59:17.037635 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8810 00:59:17.044390 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8811 00:59:17.047695 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8812 00:59:17.051214 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8813 00:59:17.054233 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8814 00:59:17.057770 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8815 00:59:17.064278 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8816 00:59:17.067690 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8817 00:59:17.070706 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8818 00:59:17.074155 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8819 00:59:17.077643 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8820 00:59:17.084220 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8821 00:59:17.087304 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8822 00:59:17.091040 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8823 00:59:17.093988 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8824 00:59:17.094063 ==
8825 00:59:17.097459 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 00:59:17.103849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 00:59:17.103932 ==
8828 00:59:17.103993 DQS Delay:
8829 00:59:17.107358 DQS0 = 0, DQS1 = 0
8830 00:59:17.107431 DQM Delay:
8831 00:59:17.110766 DQM0 = 129, DQM1 = 128
8832 00:59:17.110833 DQ Delay:
8833 00:59:17.113669 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8834 00:59:17.117215 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8835 00:59:17.120560 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8836 00:59:17.123876 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =139
8837 00:59:17.123950
8838 00:59:17.124008
8839 00:59:17.124060 ==
8840 00:59:17.127099 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 00:59:17.133820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 00:59:17.133902 ==
8843 00:59:17.133961
8844 00:59:17.134015
8845 00:59:17.134069 TX Vref Scan disable
8846 00:59:17.136840 == TX Byte 0 ==
8847 00:59:17.140409 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8848 00:59:17.146768 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8849 00:59:17.146839 == TX Byte 1 ==
8850 00:59:17.150502 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8851 00:59:17.153985 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8852 00:59:17.156819 ==
8853 00:59:17.160479 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 00:59:17.163896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 00:59:17.163965 ==
8856 00:59:17.176230
8857 00:59:17.179809 TX Vref early break, caculate TX vref
8858 00:59:17.183220 TX Vref=16, minBit 0, minWin=22, winSum=374
8859 00:59:17.186722 TX Vref=18, minBit 0, minWin=22, winSum=383
8860 00:59:17.189472 TX Vref=20, minBit 0, minWin=24, winSum=397
8861 00:59:17.192946 TX Vref=22, minBit 0, minWin=24, winSum=404
8862 00:59:17.196279 TX Vref=24, minBit 0, minWin=25, winSum=413
8863 00:59:17.203047 TX Vref=26, minBit 0, minWin=24, winSum=417
8864 00:59:17.206581 TX Vref=28, minBit 1, minWin=25, winSum=421
8865 00:59:17.209575 TX Vref=30, minBit 5, minWin=24, winSum=414
8866 00:59:17.212886 TX Vref=32, minBit 5, minWin=24, winSum=407
8867 00:59:17.216306 TX Vref=34, minBit 1, minWin=22, winSum=396
8868 00:59:17.222610 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8869 00:59:17.222680
8870 00:59:17.226147 Final TX Range 0 Vref 28
8871 00:59:17.226217
8872 00:59:17.226281 ==
8873 00:59:17.229648 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 00:59:17.232874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 00:59:17.232951 ==
8876 00:59:17.233007
8877 00:59:17.233059
8878 00:59:17.236192 TX Vref Scan disable
8879 00:59:17.242654 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8880 00:59:17.242733 == TX Byte 0 ==
8881 00:59:17.246201 u2DelayCellOfst[0]=18 cells (5 PI)
8882 00:59:17.249691 u2DelayCellOfst[1]=11 cells (3 PI)
8883 00:59:17.252516 u2DelayCellOfst[2]=0 cells (0 PI)
8884 00:59:17.255760 u2DelayCellOfst[3]=3 cells (1 PI)
8885 00:59:17.259458 u2DelayCellOfst[4]=7 cells (2 PI)
8886 00:59:17.262317 u2DelayCellOfst[5]=18 cells (5 PI)
8887 00:59:17.265934 u2DelayCellOfst[6]=18 cells (5 PI)
8888 00:59:17.269419 u2DelayCellOfst[7]=3 cells (1 PI)
8889 00:59:17.272346 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8890 00:59:17.275859 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8891 00:59:17.279397 == TX Byte 1 ==
8892 00:59:17.279467 u2DelayCellOfst[8]=0 cells (0 PI)
8893 00:59:17.282428 u2DelayCellOfst[9]=7 cells (2 PI)
8894 00:59:17.285882 u2DelayCellOfst[10]=15 cells (4 PI)
8895 00:59:17.289402 u2DelayCellOfst[11]=7 cells (2 PI)
8896 00:59:17.292413 u2DelayCellOfst[12]=18 cells (5 PI)
8897 00:59:17.295985 u2DelayCellOfst[13]=18 cells (5 PI)
8898 00:59:17.298907 u2DelayCellOfst[14]=22 cells (6 PI)
8899 00:59:17.302473 u2DelayCellOfst[15]=22 cells (6 PI)
8900 00:59:17.305880 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8901 00:59:17.312199 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8902 00:59:17.312269 DramC Write-DBI on
8903 00:59:17.312334 ==
8904 00:59:17.315729 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 00:59:17.319154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 00:59:17.322131 ==
8907 00:59:17.322195
8908 00:59:17.322249
8909 00:59:17.322307 TX Vref Scan disable
8910 00:59:17.325721 == TX Byte 0 ==
8911 00:59:17.329062 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8912 00:59:17.332499 == TX Byte 1 ==
8913 00:59:17.335604 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8914 00:59:17.338986 DramC Write-DBI off
8915 00:59:17.339051
8916 00:59:17.339107 [DATLAT]
8917 00:59:17.339158 Freq=1600, CH1 RK1
8918 00:59:17.339217
8919 00:59:17.342155 DATLAT Default: 0xf
8920 00:59:17.342222 0, 0xFFFF, sum = 0
8921 00:59:17.345370 1, 0xFFFF, sum = 0
8922 00:59:17.349064 2, 0xFFFF, sum = 0
8923 00:59:17.349139 3, 0xFFFF, sum = 0
8924 00:59:17.352234 4, 0xFFFF, sum = 0
8925 00:59:17.352321 5, 0xFFFF, sum = 0
8926 00:59:17.355829 6, 0xFFFF, sum = 0
8927 00:59:17.355897 7, 0xFFFF, sum = 0
8928 00:59:17.358751 8, 0xFFFF, sum = 0
8929 00:59:17.358820 9, 0xFFFF, sum = 0
8930 00:59:17.362022 10, 0xFFFF, sum = 0
8931 00:59:17.362088 11, 0xFFFF, sum = 0
8932 00:59:17.365730 12, 0xFFFF, sum = 0
8933 00:59:17.365792 13, 0x8FFF, sum = 0
8934 00:59:17.368614 14, 0x0, sum = 1
8935 00:59:17.368692 15, 0x0, sum = 2
8936 00:59:17.372278 16, 0x0, sum = 3
8937 00:59:17.372355 17, 0x0, sum = 4
8938 00:59:17.375087 best_step = 15
8939 00:59:17.375154
8940 00:59:17.375215 ==
8941 00:59:17.378776 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 00:59:17.382235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 00:59:17.382310 ==
8944 00:59:17.385149 RX Vref Scan: 0
8945 00:59:17.385214
8946 00:59:17.385270 RX Vref 0 -> 0, step: 1
8947 00:59:17.385328
8948 00:59:17.388705 RX Delay 3 -> 252, step: 4
8949 00:59:17.395102 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8950 00:59:17.398486 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8951 00:59:17.401583 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8952 00:59:17.405229 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8953 00:59:17.408220 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
8954 00:59:17.411782 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8955 00:59:17.418648 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8956 00:59:17.421435 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8957 00:59:17.424765 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8958 00:59:17.428504 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8959 00:59:17.434644 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8960 00:59:17.438032 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
8961 00:59:17.441582 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8962 00:59:17.445071 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8963 00:59:17.448377 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8964 00:59:17.454633 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8965 00:59:17.454707 ==
8966 00:59:17.458368 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 00:59:17.461362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 00:59:17.461442 ==
8969 00:59:17.461503 DQS Delay:
8970 00:59:17.464585 DQS0 = 0, DQS1 = 0
8971 00:59:17.464718 DQM Delay:
8972 00:59:17.468002 DQM0 = 127, DQM1 = 125
8973 00:59:17.468079 DQ Delay:
8974 00:59:17.471202 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =124
8975 00:59:17.474707 DQ4 =122, DQ5 =138, DQ6 =138, DQ7 =124
8976 00:59:17.477933 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =122
8977 00:59:17.481507 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =134
8978 00:59:17.481577
8979 00:59:17.481672
8980 00:59:17.484453
8981 00:59:17.484526 [DramC_TX_OE_Calibration] TA2
8982 00:59:17.488057 Original DQ_B0 (3 6) =30, OEN = 27
8983 00:59:17.491582 Original DQ_B1 (3 6) =30, OEN = 27
8984 00:59:17.494967 24, 0x0, End_B0=24 End_B1=24
8985 00:59:17.497859 25, 0x0, End_B0=25 End_B1=25
8986 00:59:17.501443 26, 0x0, End_B0=26 End_B1=26
8987 00:59:17.501514 27, 0x0, End_B0=27 End_B1=27
8988 00:59:17.505014 28, 0x0, End_B0=28 End_B1=28
8989 00:59:17.507974 29, 0x0, End_B0=29 End_B1=29
8990 00:59:17.511663 30, 0x0, End_B0=30 End_B1=30
8991 00:59:17.515073 31, 0x4141, End_B0=30 End_B1=30
8992 00:59:17.515142 Byte0 end_step=30 best_step=27
8993 00:59:17.517928 Byte1 end_step=30 best_step=27
8994 00:59:17.520924 Byte0 TX OE(2T, 0.5T) = (3, 3)
8995 00:59:17.524330 Byte1 TX OE(2T, 0.5T) = (3, 3)
8996 00:59:17.524426
8997 00:59:17.524520
8998 00:59:17.531242 [DQSOSCAuto] RK1, (LSB)MR18= 0x141f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
8999 00:59:17.534465 CH1 RK1: MR19=303, MR18=141F
9000 00:59:17.540802 CH1_RK1: MR19=0x303, MR18=0x141F, DQSOSC=394, MR23=63, INC=23, DEC=15
9001 00:59:17.544437 [RxdqsGatingPostProcess] freq 1600
9002 00:59:17.550949 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9003 00:59:17.553910 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 00:59:17.557335 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 00:59:17.560734 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 00:59:17.560807 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 00:59:17.563710 best DQS0 dly(2T, 0.5T) = (1, 1)
9008 00:59:17.567253 best DQS1 dly(2T, 0.5T) = (1, 1)
9009 00:59:17.570630 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9010 00:59:17.574271 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9011 00:59:17.577127 Pre-setting of DQS Precalculation
9012 00:59:17.583753 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9013 00:59:17.590624 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9014 00:59:17.596860 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9015 00:59:17.596930
9016 00:59:17.597005
9017 00:59:17.600286 [Calibration Summary] 3200 Mbps
9018 00:59:17.600368 CH 0, Rank 0
9019 00:59:17.603856 SW Impedance : PASS
9020 00:59:17.607377 DUTY Scan : NO K
9021 00:59:17.607451 ZQ Calibration : PASS
9022 00:59:17.610420 Jitter Meter : NO K
9023 00:59:17.613999 CBT Training : PASS
9024 00:59:17.614068 Write leveling : PASS
9025 00:59:17.616975 RX DQS gating : PASS
9026 00:59:17.617045 RX DQ/DQS(RDDQC) : PASS
9027 00:59:17.620386 TX DQ/DQS : PASS
9028 00:59:17.624003 RX DATLAT : PASS
9029 00:59:17.624069 RX DQ/DQS(Engine): PASS
9030 00:59:17.627250 TX OE : PASS
9031 00:59:17.627318 All Pass.
9032 00:59:17.627389
9033 00:59:17.630275 CH 0, Rank 1
9034 00:59:17.630344 SW Impedance : PASS
9035 00:59:17.633736 DUTY Scan : NO K
9036 00:59:17.636955 ZQ Calibration : PASS
9037 00:59:17.637023 Jitter Meter : NO K
9038 00:59:17.640343 CBT Training : PASS
9039 00:59:17.643614 Write leveling : PASS
9040 00:59:17.643684 RX DQS gating : PASS
9041 00:59:17.646815 RX DQ/DQS(RDDQC) : PASS
9042 00:59:17.650398 TX DQ/DQS : PASS
9043 00:59:17.650471 RX DATLAT : PASS
9044 00:59:17.653309 RX DQ/DQS(Engine): PASS
9045 00:59:17.656865 TX OE : PASS
9046 00:59:17.656933 All Pass.
9047 00:59:17.657004
9048 00:59:17.657076 CH 1, Rank 0
9049 00:59:17.660305 SW Impedance : PASS
9050 00:59:17.663500 DUTY Scan : NO K
9051 00:59:17.663571 ZQ Calibration : PASS
9052 00:59:17.666982 Jitter Meter : NO K
9053 00:59:17.667054 CBT Training : PASS
9054 00:59:17.669990 Write leveling : PASS
9055 00:59:17.673502 RX DQS gating : PASS
9056 00:59:17.673571 RX DQ/DQS(RDDQC) : PASS
9057 00:59:17.676441 TX DQ/DQS : PASS
9058 00:59:17.679814 RX DATLAT : PASS
9059 00:59:17.679880 RX DQ/DQS(Engine): PASS
9060 00:59:17.683237 TX OE : PASS
9061 00:59:17.683302 All Pass.
9062 00:59:17.683371
9063 00:59:17.686715 CH 1, Rank 1
9064 00:59:17.686778 SW Impedance : PASS
9065 00:59:17.690151 DUTY Scan : NO K
9066 00:59:17.693374 ZQ Calibration : PASS
9067 00:59:17.693441 Jitter Meter : NO K
9068 00:59:17.696746 CBT Training : PASS
9069 00:59:17.699856 Write leveling : PASS
9070 00:59:17.699927 RX DQS gating : PASS
9071 00:59:17.702864 RX DQ/DQS(RDDQC) : PASS
9072 00:59:17.706152 TX DQ/DQS : PASS
9073 00:59:17.706224 RX DATLAT : PASS
9074 00:59:17.709439 RX DQ/DQS(Engine): PASS
9075 00:59:17.712769 TX OE : PASS
9076 00:59:17.712844 All Pass.
9077 00:59:17.712918
9078 00:59:17.716483 DramC Write-DBI on
9079 00:59:17.716553 PER_BANK_REFRESH: Hybrid Mode
9080 00:59:17.719348 TX_TRACKING: ON
9081 00:59:17.726511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9082 00:59:17.736107 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9083 00:59:17.742358 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 00:59:17.746055 [FAST_K] Save calibration result to emmc
9085 00:59:17.749214 sync common calibartion params.
9086 00:59:17.752365 sync cbt_mode0:1, 1:1
9087 00:59:17.752432 dram_init: ddr_geometry: 2
9088 00:59:17.755698 dram_init: ddr_geometry: 2
9089 00:59:17.759213 dram_init: ddr_geometry: 2
9090 00:59:17.762179 0:dram_rank_size:100000000
9091 00:59:17.762250 1:dram_rank_size:100000000
9092 00:59:17.769190 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9093 00:59:17.772549 DFS_SHUFFLE_HW_MODE: ON
9094 00:59:17.775571 dramc_set_vcore_voltage set vcore to 725000
9095 00:59:17.779125 Read voltage for 1600, 0
9096 00:59:17.779196 Vio18 = 0
9097 00:59:17.779272 Vcore = 725000
9098 00:59:17.782559 Vdram = 0
9099 00:59:17.782630 Vddq = 0
9100 00:59:17.782719 Vmddr = 0
9101 00:59:17.785306 switch to 3200 Mbps bootup
9102 00:59:17.785377 [DramcRunTimeConfig]
9103 00:59:17.788689 PHYPLL
9104 00:59:17.788755 DPM_CONTROL_AFTERK: ON
9105 00:59:17.792265 PER_BANK_REFRESH: ON
9106 00:59:17.795752 REFRESH_OVERHEAD_REDUCTION: ON
9107 00:59:17.795819 CMD_PICG_NEW_MODE: OFF
9108 00:59:17.798636 XRTWTW_NEW_MODE: ON
9109 00:59:17.798702 XRTRTR_NEW_MODE: ON
9110 00:59:17.802022 TX_TRACKING: ON
9111 00:59:17.802093 RDSEL_TRACKING: OFF
9112 00:59:17.805511 DQS Precalculation for DVFS: ON
9113 00:59:17.808538 RX_TRACKING: OFF
9114 00:59:17.808609 HW_GATING DBG: ON
9115 00:59:17.811869 ZQCS_ENABLE_LP4: ON
9116 00:59:17.811960 RX_PICG_NEW_MODE: ON
9117 00:59:17.815728 TX_PICG_NEW_MODE: ON
9118 00:59:17.815795 ENABLE_RX_DCM_DPHY: ON
9119 00:59:17.818835 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9120 00:59:17.821900 DUMMY_READ_FOR_TRACKING: OFF
9121 00:59:17.825037 !!! SPM_CONTROL_AFTERK: OFF
9122 00:59:17.828490 !!! SPM could not control APHY
9123 00:59:17.828560 IMPEDANCE_TRACKING: ON
9124 00:59:17.831875 TEMP_SENSOR: ON
9125 00:59:17.831945 HW_SAVE_FOR_SR: OFF
9126 00:59:17.835440 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9127 00:59:17.838519 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9128 00:59:17.841520 Read ODT Tracking: ON
9129 00:59:17.845045 Refresh Rate DeBounce: ON
9130 00:59:17.845111 DFS_NO_QUEUE_FLUSH: ON
9131 00:59:17.848517 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9132 00:59:17.851864 ENABLE_DFS_RUNTIME_MRW: OFF
9133 00:59:17.854804 DDR_RESERVE_NEW_MODE: ON
9134 00:59:17.854875 MR_CBT_SWITCH_FREQ: ON
9135 00:59:17.858201 =========================
9136 00:59:17.877330 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9137 00:59:17.880312 dram_init: ddr_geometry: 2
9138 00:59:17.898871 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9139 00:59:17.901897 dram_init: dram init end (result: 0)
9140 00:59:17.908780 DRAM-K: Full calibration passed in 24514 msecs
9141 00:59:17.911762 MRC: failed to locate region type 0.
9142 00:59:17.911830 DRAM rank0 size:0x100000000,
9143 00:59:17.915347 DRAM rank1 size=0x100000000
9144 00:59:17.925233 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9145 00:59:17.931692 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9146 00:59:17.938741 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9147 00:59:17.945311 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9148 00:59:17.948260 DRAM rank0 size:0x100000000,
9149 00:59:17.951511 DRAM rank1 size=0x100000000
9150 00:59:17.951580 CBMEM:
9151 00:59:17.954941 IMD: root @ 0xfffff000 254 entries.
9152 00:59:17.958563 IMD: root @ 0xffffec00 62 entries.
9153 00:59:17.961369 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9154 00:59:17.964901 WARNING: RO_VPD is uninitialized or empty.
9155 00:59:17.971255 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9156 00:59:17.979021 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9157 00:59:17.991342 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9158 00:59:18.002945 BS: romstage times (exec / console): total (unknown) / 23982 ms
9159 00:59:18.003020
9160 00:59:18.003079
9161 00:59:18.013224 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9162 00:59:18.016193 ARM64: Exception handlers installed.
9163 00:59:18.019757 ARM64: Testing exception
9164 00:59:18.022694 ARM64: Done test exception
9165 00:59:18.022765 Enumerating buses...
9166 00:59:18.026049 Show all devs... Before device enumeration.
9167 00:59:18.029378 Root Device: enabled 1
9168 00:59:18.032871 CPU_CLUSTER: 0: enabled 1
9169 00:59:18.032944 CPU: 00: enabled 1
9170 00:59:18.035790 Compare with tree...
9171 00:59:18.035861 Root Device: enabled 1
9172 00:59:18.039314 CPU_CLUSTER: 0: enabled 1
9173 00:59:18.042930 CPU: 00: enabled 1
9174 00:59:18.042999 Root Device scanning...
9175 00:59:18.045564 scan_static_bus for Root Device
9176 00:59:18.048921 CPU_CLUSTER: 0 enabled
9177 00:59:18.052357 scan_static_bus for Root Device done
9178 00:59:18.055945 scan_bus: bus Root Device finished in 8 msecs
9179 00:59:18.056014 done
9180 00:59:18.062165 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9181 00:59:18.065674 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9182 00:59:18.072034 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9183 00:59:18.075687 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9184 00:59:18.078889 Allocating resources...
9185 00:59:18.082288 Reading resources...
9186 00:59:18.085470 Root Device read_resources bus 0 link: 0
9187 00:59:18.088937 DRAM rank0 size:0x100000000,
9188 00:59:18.089023 DRAM rank1 size=0x100000000
9189 00:59:18.092379 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9190 00:59:18.095467 CPU: 00 missing read_resources
9191 00:59:18.102202 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9192 00:59:18.105678 Root Device read_resources bus 0 link: 0 done
9193 00:59:18.105762 Done reading resources.
9194 00:59:18.112168 Show resources in subtree (Root Device)...After reading.
9195 00:59:18.115500 Root Device child on link 0 CPU_CLUSTER: 0
9196 00:59:18.118352 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 00:59:18.128475 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 00:59:18.128559 CPU: 00
9199 00:59:18.131892 Root Device assign_resources, bus 0 link: 0
9200 00:59:18.135434 CPU_CLUSTER: 0 missing set_resources
9201 00:59:18.141927 Root Device assign_resources, bus 0 link: 0 done
9202 00:59:18.142003 Done setting resources.
9203 00:59:18.148329 Show resources in subtree (Root Device)...After assigning values.
9204 00:59:18.151703 Root Device child on link 0 CPU_CLUSTER: 0
9205 00:59:18.154970 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 00:59:18.164796 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 00:59:18.164873 CPU: 00
9208 00:59:18.168178 Done allocating resources.
9209 00:59:18.174687 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9210 00:59:18.174760 Enabling resources...
9211 00:59:18.174836 done.
9212 00:59:18.181706 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9213 00:59:18.184972 Initializing devices...
9214 00:59:18.185043 Root Device init
9215 00:59:18.187842 init hardware done!
9216 00:59:18.187913 0x00000018: ctrlr->caps
9217 00:59:18.191503 52.000 MHz: ctrlr->f_max
9218 00:59:18.194806 0.400 MHz: ctrlr->f_min
9219 00:59:18.194878 0x40ff8080: ctrlr->voltages
9220 00:59:18.197909 sclk: 390625
9221 00:59:18.197981 Bus Width = 1
9222 00:59:18.198053 sclk: 390625
9223 00:59:18.201453 Bus Width = 1
9224 00:59:18.201535 Early init status = 3
9225 00:59:18.207739 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9226 00:59:18.211168 in-header: 03 fc 00 00 01 00 00 00
9227 00:59:18.214638 in-data: 00
9228 00:59:18.217743 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9229 00:59:18.223545 in-header: 03 fd 00 00 00 00 00 00
9230 00:59:18.226874 in-data:
9231 00:59:18.230155 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9232 00:59:18.234379 in-header: 03 fc 00 00 01 00 00 00
9233 00:59:18.237655 in-data: 00
9234 00:59:18.240747 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9235 00:59:18.246550 in-header: 03 fd 00 00 00 00 00 00
9236 00:59:18.250155 in-data:
9237 00:59:18.253155 [SSUSB] Setting up USB HOST controller...
9238 00:59:18.256570 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9239 00:59:18.259796 [SSUSB] phy power-on done.
9240 00:59:18.263470 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9241 00:59:18.269936 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9242 00:59:18.273464 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9243 00:59:18.279817 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9244 00:59:18.286608 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9245 00:59:18.292999 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9246 00:59:18.300081 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9247 00:59:18.306392 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9248 00:59:18.309936 SPM: binary array size = 0x9dc
9249 00:59:18.312894 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9250 00:59:18.319313 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9251 00:59:18.326149 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9252 00:59:18.332730 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9253 00:59:18.335791 configure_display: Starting display init
9254 00:59:18.370087 anx7625_power_on_init: Init interface.
9255 00:59:18.372941 anx7625_disable_pd_protocol: Disabled PD feature.
9256 00:59:18.376359 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9257 00:59:18.404228 anx7625_start_dp_work: Secure OCM version=00
9258 00:59:18.407741 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9259 00:59:18.422669 sp_tx_get_edid_block: EDID Block = 1
9260 00:59:18.525197 Extracted contents:
9261 00:59:18.528470 header: 00 ff ff ff ff ff ff 00
9262 00:59:18.531439 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9263 00:59:18.534989 version: 01 04
9264 00:59:18.538511 basic params: 95 1f 11 78 0a
9265 00:59:18.541395 chroma info: 76 90 94 55 54 90 27 21 50 54
9266 00:59:18.544807 established: 00 00 00
9267 00:59:18.551784 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9268 00:59:18.554698 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9269 00:59:18.561214 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9270 00:59:18.568095 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9271 00:59:18.574401 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9272 00:59:18.577776 extensions: 00
9273 00:59:18.577846 checksum: fb
9274 00:59:18.577925
9275 00:59:18.581308 Manufacturer: IVO Model 57d Serial Number 0
9276 00:59:18.584203 Made week 0 of 2020
9277 00:59:18.587529 EDID version: 1.4
9278 00:59:18.587602 Digital display
9279 00:59:18.591259 6 bits per primary color channel
9280 00:59:18.591330 DisplayPort interface
9281 00:59:18.594250 Maximum image size: 31 cm x 17 cm
9282 00:59:18.597968 Gamma: 220%
9283 00:59:18.598038 Check DPMS levels
9284 00:59:18.600935 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9285 00:59:18.607502 First detailed timing is preferred timing
9286 00:59:18.607579 Established timings supported:
9287 00:59:18.610750 Standard timings supported:
9288 00:59:18.614330 Detailed timings
9289 00:59:18.617197 Hex of detail: 383680a07038204018303c0035ae10000019
9290 00:59:18.624145 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9291 00:59:18.627720 0780 0798 07c8 0820 hborder 0
9292 00:59:18.630520 0438 043b 0447 0458 vborder 0
9293 00:59:18.633980 -hsync -vsync
9294 00:59:18.634047 Did detailed timing
9295 00:59:18.640778 Hex of detail: 000000000000000000000000000000000000
9296 00:59:18.643659 Manufacturer-specified data, tag 0
9297 00:59:18.647233 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9298 00:59:18.650593 ASCII string: InfoVision
9299 00:59:18.653600 Hex of detail: 000000fe00523134304e574635205248200a
9300 00:59:18.657196 ASCII string: R140NWF5 RH
9301 00:59:18.657261 Checksum
9302 00:59:18.660019 Checksum: 0xfb (valid)
9303 00:59:18.663450 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9304 00:59:18.667028 DSI data_rate: 832800000 bps
9305 00:59:18.673389 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9306 00:59:18.676783 anx7625_parse_edid: pixelclock(138800).
9307 00:59:18.680376 hactive(1920), hsync(48), hfp(24), hbp(88)
9308 00:59:18.683364 vactive(1080), vsync(12), vfp(3), vbp(17)
9309 00:59:18.686658 anx7625_dsi_config: config dsi.
9310 00:59:18.693286 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9311 00:59:18.707277 anx7625_dsi_config: success to config DSI
9312 00:59:18.710559 anx7625_dp_start: MIPI phy setup OK.
9313 00:59:18.713618 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9314 00:59:18.716906 mtk_ddp_mode_set invalid vrefresh 60
9315 00:59:18.720327 main_disp_path_setup
9316 00:59:18.720393 ovl_layer_smi_id_en
9317 00:59:18.723734 ovl_layer_smi_id_en
9318 00:59:18.723800 ccorr_config
9319 00:59:18.723855 aal_config
9320 00:59:18.726568 gamma_config
9321 00:59:18.726634 postmask_config
9322 00:59:18.730022 dither_config
9323 00:59:18.733377 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9324 00:59:18.740134 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9325 00:59:18.743390 Root Device init finished in 555 msecs
9326 00:59:18.746872 CPU_CLUSTER: 0 init
9327 00:59:18.753372 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9328 00:59:18.759708 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9329 00:59:18.759779 APU_MBOX 0x190000b0 = 0x10001
9330 00:59:18.763114 APU_MBOX 0x190001b0 = 0x10001
9331 00:59:18.766555 APU_MBOX 0x190005b0 = 0x10001
9332 00:59:18.770103 APU_MBOX 0x190006b0 = 0x10001
9333 00:59:18.776419 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9334 00:59:18.786250 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9335 00:59:18.798333 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9336 00:59:18.805368 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9337 00:59:18.816558 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9338 00:59:18.825830 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9339 00:59:18.829359 CPU_CLUSTER: 0 init finished in 81 msecs
9340 00:59:18.832270 Devices initialized
9341 00:59:18.835649 Show all devs... After init.
9342 00:59:18.835722 Root Device: enabled 1
9343 00:59:18.838938 CPU_CLUSTER: 0: enabled 1
9344 00:59:18.842541 CPU: 00: enabled 1
9345 00:59:18.845473 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9346 00:59:18.849140 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9347 00:59:18.852384 ELOG: NV offset 0x57f000 size 0x1000
9348 00:59:18.858887 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9349 00:59:18.865484 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9350 00:59:18.868843 ELOG: Event(17) added with size 13 at 2024-06-16 00:59:18 UTC
9351 00:59:18.875428 out: cmd=0x121: 03 db 21 01 00 00 00 00
9352 00:59:18.878881 in-header: 03 c4 00 00 2c 00 00 00
9353 00:59:18.888558 in-data: 79 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9354 00:59:18.895193 ELOG: Event(A1) added with size 10 at 2024-06-16 00:59:18 UTC
9355 00:59:18.901562 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9356 00:59:18.908302 ELOG: Event(A0) added with size 9 at 2024-06-16 00:59:18 UTC
9357 00:59:18.911916 elog_add_boot_reason: Logged dev mode boot
9358 00:59:18.918368 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9359 00:59:18.918438 Finalize devices...
9360 00:59:18.921855 Devices finalized
9361 00:59:18.924873 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9362 00:59:18.927877 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9363 00:59:18.931487 in-header: 03 07 00 00 08 00 00 00
9364 00:59:18.934407 in-data: aa e4 47 04 13 02 00 00
9365 00:59:18.937768 Chrome EC: UHEPI supported
9366 00:59:18.944889 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9367 00:59:18.947838 in-header: 03 a9 00 00 08 00 00 00
9368 00:59:18.951393 in-data: 84 60 60 08 00 00 00 00
9369 00:59:18.957924 ELOG: Event(91) added with size 10 at 2024-06-16 00:59:18 UTC
9370 00:59:18.961072 Chrome EC: clear events_b mask to 0x0000000020004000
9371 00:59:18.967736 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9372 00:59:18.971471 in-header: 03 fd 00 00 00 00 00 00
9373 00:59:18.971545 in-data:
9374 00:59:18.978299 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9375 00:59:18.981158 Writing coreboot table at 0xffe64000
9376 00:59:18.984782 0. 000000000010a000-0000000000113fff: RAMSTAGE
9377 00:59:18.987949 1. 0000000040000000-00000000400fffff: RAM
9378 00:59:18.994770 2. 0000000040100000-000000004032afff: RAMSTAGE
9379 00:59:18.997707 3. 000000004032b000-00000000545fffff: RAM
9380 00:59:19.001392 4. 0000000054600000-000000005465ffff: BL31
9381 00:59:19.004274 5. 0000000054660000-00000000ffe63fff: RAM
9382 00:59:19.010930 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9383 00:59:19.014303 7. 0000000100000000-000000023fffffff: RAM
9384 00:59:19.017835 Passing 5 GPIOs to payload:
9385 00:59:19.020835 NAME | PORT | POLARITY | VALUE
9386 00:59:19.027832 EC in RW | 0x000000aa | low | undefined
9387 00:59:19.030730 EC interrupt | 0x00000005 | low | undefined
9388 00:59:19.034415 TPM interrupt | 0x000000ab | high | undefined
9389 00:59:19.040904 SD card detect | 0x00000011 | high | undefined
9390 00:59:19.044350 speaker enable | 0x00000093 | high | undefined
9391 00:59:19.047292 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9392 00:59:19.050908 in-header: 03 f9 00 00 02 00 00 00
9393 00:59:19.053954 in-data: 02 00
9394 00:59:19.057503 ADC[4]: Raw value=894821 ID=7
9395 00:59:19.057569 ADC[3]: Raw value=213440 ID=1
9396 00:59:19.061026 RAM Code: 0x71
9397 00:59:19.063913 ADC[6]: Raw value=74722 ID=0
9398 00:59:19.063980 ADC[5]: Raw value=212700 ID=1
9399 00:59:19.067482 SKU Code: 0x1
9400 00:59:19.070969 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 27a
9401 00:59:19.073895 coreboot table: 964 bytes.
9402 00:59:19.077389 IMD ROOT 0. 0xfffff000 0x00001000
9403 00:59:19.080586 IMD SMALL 1. 0xffffe000 0x00001000
9404 00:59:19.083695 RO MCACHE 2. 0xffffc000 0x00001104
9405 00:59:19.087112 CONSOLE 3. 0xfff7c000 0x00080000
9406 00:59:19.090279 FMAP 4. 0xfff7b000 0x00000452
9407 00:59:19.093642 TIME STAMP 5. 0xfff7a000 0x00000910
9408 00:59:19.097206 VBOOT WORK 6. 0xfff66000 0x00014000
9409 00:59:19.100471 RAMOOPS 7. 0xffe66000 0x00100000
9410 00:59:19.103615 COREBOOT 8. 0xffe64000 0x00002000
9411 00:59:19.107179 IMD small region:
9412 00:59:19.110269 IMD ROOT 0. 0xffffec00 0x00000400
9413 00:59:19.113823 VPD 1. 0xffffeb80 0x0000006c
9414 00:59:19.116946 MMC STATUS 2. 0xffffeb60 0x00000004
9415 00:59:19.120315 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9416 00:59:19.126559 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9417 00:59:19.167762 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9418 00:59:19.170748 Checking segment from ROM address 0x40100000
9419 00:59:19.174192 Checking segment from ROM address 0x4010001c
9420 00:59:19.180654 Loading segment from ROM address 0x40100000
9421 00:59:19.180726 code (compression=0)
9422 00:59:19.190667 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9423 00:59:19.197493 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9424 00:59:19.197567 it's not compressed!
9425 00:59:19.203796 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9426 00:59:19.210303 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9427 00:59:19.228047 Loading segment from ROM address 0x4010001c
9428 00:59:19.228123 Entry Point 0x80000000
9429 00:59:19.231212 Loaded segments
9430 00:59:19.234978 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9431 00:59:19.241199 Jumping to boot code at 0x80000000(0xffe64000)
9432 00:59:19.247939 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9433 00:59:19.254154 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9434 00:59:19.262531 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9435 00:59:19.266092 Checking segment from ROM address 0x40100000
9436 00:59:19.269021 Checking segment from ROM address 0x4010001c
9437 00:59:19.275948 Loading segment from ROM address 0x40100000
9438 00:59:19.276026 code (compression=1)
9439 00:59:19.282414 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9440 00:59:19.292349 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9441 00:59:19.292429 using LZMA
9442 00:59:19.301009 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9443 00:59:19.307383 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9444 00:59:19.310957 Loading segment from ROM address 0x4010001c
9445 00:59:19.311030 Entry Point 0x54601000
9446 00:59:19.313877 Loaded segments
9447 00:59:19.317277 NOTICE: MT8192 bl31_setup
9448 00:59:19.324612 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9449 00:59:19.328067 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9450 00:59:19.331011 WARNING: region 0:
9451 00:59:19.334375 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 00:59:19.334448 WARNING: region 1:
9453 00:59:19.341090 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9454 00:59:19.344458 WARNING: region 2:
9455 00:59:19.347584 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9456 00:59:19.350902 WARNING: region 3:
9457 00:59:19.354692 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 00:59:19.357942 WARNING: region 4:
9459 00:59:19.364144 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 00:59:19.364214 WARNING: region 5:
9461 00:59:19.367378 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 00:59:19.370756 WARNING: region 6:
9463 00:59:19.374392 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 00:59:19.377459 WARNING: region 7:
9465 00:59:19.380940 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 00:59:19.387288 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9467 00:59:19.390675 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9468 00:59:19.394279 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9469 00:59:19.400600 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9470 00:59:19.404014 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9471 00:59:19.410778 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9472 00:59:19.413781 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9473 00:59:19.417270 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9474 00:59:19.424159 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9475 00:59:19.427047 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9476 00:59:19.430338 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9477 00:59:19.436991 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9478 00:59:19.440572 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9479 00:59:19.447189 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9480 00:59:19.450611 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9481 00:59:19.453400 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9482 00:59:19.460334 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9483 00:59:19.463267 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9484 00:59:19.469925 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9485 00:59:19.473367 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9486 00:59:19.477235 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9487 00:59:19.483394 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9488 00:59:19.486736 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9489 00:59:19.489826 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9490 00:59:19.496743 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9491 00:59:19.499697 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9492 00:59:19.506694 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9493 00:59:19.510202 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9494 00:59:19.516375 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9495 00:59:19.519862 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9496 00:59:19.523416 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9497 00:59:19.529740 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9498 00:59:19.533196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9499 00:59:19.536625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9500 00:59:19.540198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9501 00:59:19.546744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9502 00:59:19.549746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9503 00:59:19.553242 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9504 00:59:19.556794 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9505 00:59:19.563185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9506 00:59:19.566542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9507 00:59:19.569674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9508 00:59:19.573158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9509 00:59:19.579812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9510 00:59:19.583310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9511 00:59:19.586095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9512 00:59:19.589503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9513 00:59:19.596003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9514 00:59:19.599947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9515 00:59:19.606192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9516 00:59:19.609472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9517 00:59:19.612976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9518 00:59:19.619423 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9519 00:59:19.622762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9520 00:59:19.629659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9521 00:59:19.633015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9522 00:59:19.639313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9523 00:59:19.642847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9524 00:59:19.649420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9525 00:59:19.652377 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9526 00:59:19.655865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9527 00:59:19.662374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9528 00:59:19.665906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9529 00:59:19.672415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9530 00:59:19.675887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9531 00:59:19.682242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9532 00:59:19.685919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9533 00:59:19.692298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9534 00:59:19.695497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9535 00:59:19.698908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9536 00:59:19.705297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9537 00:59:19.708903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9538 00:59:19.715305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9539 00:59:19.718641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9540 00:59:19.725751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9541 00:59:19.728582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9542 00:59:19.735517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9543 00:59:19.738555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9544 00:59:19.741974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9545 00:59:19.748443 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9546 00:59:19.752169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9547 00:59:19.758670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9548 00:59:19.762098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9549 00:59:19.768090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9550 00:59:19.771686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9551 00:59:19.778060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9552 00:59:19.781529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9553 00:59:19.784460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9554 00:59:19.791063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9555 00:59:19.794433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9556 00:59:19.800850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9557 00:59:19.804641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9558 00:59:19.810979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9559 00:59:19.814104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9560 00:59:19.820639 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9561 00:59:19.824252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9562 00:59:19.827732 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9563 00:59:19.834177 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9564 00:59:19.837599 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9565 00:59:19.840828 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9566 00:59:19.843999 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9567 00:59:19.850654 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9568 00:59:19.854400 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9569 00:59:19.860737 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9570 00:59:19.863801 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9571 00:59:19.866957 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9572 00:59:19.873703 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9573 00:59:19.877345 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9574 00:59:19.883738 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9575 00:59:19.886746 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9576 00:59:19.890301 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9577 00:59:19.896629 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9578 00:59:19.900372 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9579 00:59:19.906762 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9580 00:59:19.909791 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9581 00:59:19.916889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9582 00:59:19.920308 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9583 00:59:19.923464 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9584 00:59:19.926612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9585 00:59:19.933254 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9586 00:59:19.936527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9587 00:59:19.940068 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9588 00:59:19.943075 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9589 00:59:19.950102 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9590 00:59:19.952815 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9591 00:59:19.956264 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9592 00:59:19.962823 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9593 00:59:19.966064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9594 00:59:19.972993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9595 00:59:19.976345 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9596 00:59:19.979532 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9597 00:59:19.986230 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9598 00:59:19.989368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9599 00:59:19.996217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9600 00:59:19.999122 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9601 00:59:20.002686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9602 00:59:20.009159 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9603 00:59:20.012779 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9604 00:59:20.019114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9605 00:59:20.022595 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9606 00:59:20.025550 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9607 00:59:20.032448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9608 00:59:20.035938 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9609 00:59:20.042191 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9610 00:59:20.045700 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9611 00:59:20.049314 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9612 00:59:20.055642 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9613 00:59:20.058862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9614 00:59:20.065522 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9615 00:59:20.068859 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9616 00:59:20.072235 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9617 00:59:20.078607 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9618 00:59:20.082192 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9619 00:59:20.088746 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9620 00:59:20.092106 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9621 00:59:20.095330 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9622 00:59:20.101735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9623 00:59:20.105045 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9624 00:59:20.108747 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9625 00:59:20.115442 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9626 00:59:20.118545 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9627 00:59:20.125018 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9628 00:59:20.128607 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9629 00:59:20.135061 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9630 00:59:20.138547 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9631 00:59:20.141526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9632 00:59:20.148545 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9633 00:59:20.151619 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9634 00:59:20.155030 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9635 00:59:20.161389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9636 00:59:20.164605 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9637 00:59:20.171593 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9638 00:59:20.174755 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9639 00:59:20.177826 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9640 00:59:20.184505 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9641 00:59:20.187833 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9642 00:59:20.194880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9643 00:59:20.197901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9644 00:59:20.201430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9645 00:59:20.207720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9646 00:59:20.211313 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9647 00:59:20.217994 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9648 00:59:20.220927 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9649 00:59:20.224586 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9650 00:59:20.231335 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9651 00:59:20.234317 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9652 00:59:20.240777 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9653 00:59:20.244304 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9654 00:59:20.247293 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9655 00:59:20.254467 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9656 00:59:20.257479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9657 00:59:20.264066 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9658 00:59:20.267691 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9659 00:59:20.274074 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9660 00:59:20.277433 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9661 00:59:20.280947 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9662 00:59:20.287552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9663 00:59:20.290642 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9664 00:59:20.296884 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9665 00:59:20.300525 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9666 00:59:20.307034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9667 00:59:20.309992 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9668 00:59:20.313491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9669 00:59:20.320034 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9670 00:59:20.323226 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9671 00:59:20.329948 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9672 00:59:20.333243 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9673 00:59:20.336725 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9674 00:59:20.343259 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9675 00:59:20.346572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9676 00:59:20.353621 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9677 00:59:20.356544 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9678 00:59:20.363156 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9679 00:59:20.366630 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9680 00:59:20.370229 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9681 00:59:20.376648 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9682 00:59:20.379694 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9683 00:59:20.386549 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9684 00:59:20.389548 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9685 00:59:20.396443 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9686 00:59:20.399364 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9687 00:59:20.402956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9688 00:59:20.409631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9689 00:59:20.412672 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9690 00:59:20.419687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9691 00:59:20.422763 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9692 00:59:20.429310 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9693 00:59:20.432768 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9694 00:59:20.435726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9695 00:59:20.442244 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9696 00:59:20.445842 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9697 00:59:20.449257 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9698 00:59:20.452173 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9699 00:59:20.455417 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9700 00:59:20.462424 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9701 00:59:20.465423 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9702 00:59:20.472567 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9703 00:59:20.475567 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9704 00:59:20.479064 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9705 00:59:20.485331 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9706 00:59:20.488940 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9707 00:59:20.495427 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9708 00:59:20.498375 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9709 00:59:20.501724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9710 00:59:20.508158 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9711 00:59:20.511802 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9712 00:59:20.514751 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9713 00:59:20.521714 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9714 00:59:20.524622 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9715 00:59:20.531309 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9716 00:59:20.534684 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9717 00:59:20.537872 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9718 00:59:20.544310 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9719 00:59:20.547452 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9720 00:59:20.550758 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9721 00:59:20.557708 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9722 00:59:20.560956 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9723 00:59:20.567668 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9724 00:59:20.571233 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9725 00:59:20.574529 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9726 00:59:20.580491 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9727 00:59:20.584003 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9728 00:59:20.590371 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9729 00:59:20.593933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9730 00:59:20.597509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9731 00:59:20.603997 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9732 00:59:20.607336 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9733 00:59:20.610330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9734 00:59:20.616808 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9735 00:59:20.620255 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9736 00:59:20.623770 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9737 00:59:20.627168 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9738 00:59:20.633643 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9739 00:59:20.637071 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9740 00:59:20.640379 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9741 00:59:20.643648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9742 00:59:20.649914 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9743 00:59:20.653370 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9744 00:59:20.656686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9745 00:59:20.659560 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9746 00:59:20.666404 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9747 00:59:20.669804 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9748 00:59:20.673160 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9749 00:59:20.679818 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9750 00:59:20.682911 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9751 00:59:20.689369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9752 00:59:20.692748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9753 00:59:20.699706 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9754 00:59:20.702697 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9755 00:59:20.706168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9756 00:59:20.713185 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9757 00:59:20.716131 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9758 00:59:20.722717 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9759 00:59:20.725749 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9760 00:59:20.729198 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9761 00:59:20.736153 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9762 00:59:20.738989 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9763 00:59:20.745962 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9764 00:59:20.748823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9765 00:59:20.752033 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9766 00:59:20.759195 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9767 00:59:20.762102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9768 00:59:20.768608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9769 00:59:20.772216 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9770 00:59:20.778915 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9771 00:59:20.781712 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9772 00:59:20.785208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9773 00:59:20.791904 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9774 00:59:20.795105 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9775 00:59:20.801516 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9776 00:59:20.805213 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9777 00:59:20.811724 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9778 00:59:20.815076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9779 00:59:20.818616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9780 00:59:20.825229 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9781 00:59:20.828086 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9782 00:59:20.834920 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9783 00:59:20.838428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9784 00:59:20.841430 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9785 00:59:20.847786 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9786 00:59:20.851333 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9787 00:59:20.857663 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9788 00:59:20.861321 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9789 00:59:20.864683 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9790 00:59:20.871271 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9791 00:59:20.874192 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9792 00:59:20.881202 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9793 00:59:20.884159 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9794 00:59:20.890685 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9795 00:59:20.894046 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9796 00:59:20.897735 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9797 00:59:20.904238 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9798 00:59:20.907268 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9799 00:59:20.914342 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9800 00:59:20.917229 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9801 00:59:20.923973 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9802 00:59:20.927485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9803 00:59:20.930506 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9804 00:59:20.936959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9805 00:59:20.940214 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9806 00:59:20.946740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9807 00:59:20.950142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9808 00:59:20.953499 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9809 00:59:20.960006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9810 00:59:20.963668 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9811 00:59:20.969758 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9812 00:59:20.973044 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9813 00:59:20.979770 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9814 00:59:20.983179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9815 00:59:20.986357 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9816 00:59:20.993297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9817 00:59:20.996512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9818 00:59:21.002591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9819 00:59:21.006286 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9820 00:59:21.009832 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9821 00:59:21.016318 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9822 00:59:21.019831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9823 00:59:21.026059 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9824 00:59:21.029328 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9825 00:59:21.036011 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9826 00:59:21.039436 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9827 00:59:21.045729 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9828 00:59:21.049163 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9829 00:59:21.052695 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9830 00:59:21.059492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9831 00:59:21.062539 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9832 00:59:21.068963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9833 00:59:21.072258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9834 00:59:21.079258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9835 00:59:21.082486 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9836 00:59:21.085782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9837 00:59:21.092141 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9838 00:59:21.095388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9839 00:59:21.102037 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9840 00:59:21.105366 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9841 00:59:21.112167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9842 00:59:21.115053 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9843 00:59:21.122136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9844 00:59:21.124904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9845 00:59:21.128507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9846 00:59:21.135027 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9847 00:59:21.138544 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9848 00:59:21.144905 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9849 00:59:21.148334 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9850 00:59:21.155191 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9851 00:59:21.158474 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9852 00:59:21.164863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9853 00:59:21.168402 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9854 00:59:21.171455 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9855 00:59:21.178433 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9856 00:59:21.181373 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9857 00:59:21.188351 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9858 00:59:21.191503 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9859 00:59:21.198029 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9860 00:59:21.201495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9861 00:59:21.204731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9862 00:59:21.211585 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9863 00:59:21.214490 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9864 00:59:21.221286 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9865 00:59:21.224867 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9866 00:59:21.231196 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9867 00:59:21.234712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9868 00:59:21.237548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9869 00:59:21.244462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9870 00:59:21.247409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9871 00:59:21.254335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9872 00:59:21.257323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9873 00:59:21.263996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9874 00:59:21.267743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9875 00:59:21.274298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9876 00:59:21.277232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9877 00:59:21.284136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9878 00:59:21.287730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9879 00:59:21.294149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9880 00:59:21.297464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9881 00:59:21.303929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9882 00:59:21.307330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9883 00:59:21.313840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9884 00:59:21.317419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9885 00:59:21.323598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9886 00:59:21.327051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9887 00:59:21.334050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9888 00:59:21.337090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9889 00:59:21.343636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9890 00:59:21.347220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9891 00:59:21.353504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9892 00:59:21.356929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9893 00:59:21.363409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9894 00:59:21.366939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9895 00:59:21.373494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9896 00:59:21.376429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9897 00:59:21.383555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9898 00:59:21.386646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9899 00:59:21.393078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9900 00:59:21.396432 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9901 00:59:21.399868 INFO: [APUAPC] vio 0
9902 00:59:21.403036 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9903 00:59:21.406326 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9904 00:59:21.409606 INFO: [APUAPC] D0_APC_0: 0x400510
9905 00:59:21.413255 INFO: [APUAPC] D0_APC_1: 0x0
9906 00:59:21.416216 INFO: [APUAPC] D0_APC_2: 0x1540
9907 00:59:21.419617 INFO: [APUAPC] D0_APC_3: 0x0
9908 00:59:21.422809 INFO: [APUAPC] D1_APC_0: 0xffffffff
9909 00:59:21.426394 INFO: [APUAPC] D1_APC_1: 0xffffffff
9910 00:59:21.429551 INFO: [APUAPC] D1_APC_2: 0x3fffff
9911 00:59:21.432772 INFO: [APUAPC] D1_APC_3: 0x0
9912 00:59:21.436385 INFO: [APUAPC] D2_APC_0: 0xffffffff
9913 00:59:21.439794 INFO: [APUAPC] D2_APC_1: 0xffffffff
9914 00:59:21.442761 INFO: [APUAPC] D2_APC_2: 0x3fffff
9915 00:59:21.446292 INFO: [APUAPC] D2_APC_3: 0x0
9916 00:59:21.449246 INFO: [APUAPC] D3_APC_0: 0xffffffff
9917 00:59:21.452779 INFO: [APUAPC] D3_APC_1: 0xffffffff
9918 00:59:21.456372 INFO: [APUAPC] D3_APC_2: 0x3fffff
9919 00:59:21.459119 INFO: [APUAPC] D3_APC_3: 0x0
9920 00:59:21.462565 INFO: [APUAPC] D4_APC_0: 0xffffffff
9921 00:59:21.466200 INFO: [APUAPC] D4_APC_1: 0xffffffff
9922 00:59:21.469188 INFO: [APUAPC] D4_APC_2: 0x3fffff
9923 00:59:21.472726 INFO: [APUAPC] D4_APC_3: 0x0
9924 00:59:21.475719 INFO: [APUAPC] D5_APC_0: 0xffffffff
9925 00:59:21.479313 INFO: [APUAPC] D5_APC_1: 0xffffffff
9926 00:59:21.482295 INFO: [APUAPC] D5_APC_2: 0x3fffff
9927 00:59:21.485827 INFO: [APUAPC] D5_APC_3: 0x0
9928 00:59:21.488857 INFO: [APUAPC] D6_APC_0: 0xffffffff
9929 00:59:21.492398 INFO: [APUAPC] D6_APC_1: 0xffffffff
9930 00:59:21.495686 INFO: [APUAPC] D6_APC_2: 0x3fffff
9931 00:59:21.498951 INFO: [APUAPC] D6_APC_3: 0x0
9932 00:59:21.502222 INFO: [APUAPC] D7_APC_0: 0xffffffff
9933 00:59:21.506098 INFO: [APUAPC] D7_APC_1: 0xffffffff
9934 00:59:21.509174 INFO: [APUAPC] D7_APC_2: 0x3fffff
9935 00:59:21.512443 INFO: [APUAPC] D7_APC_3: 0x0
9936 00:59:21.515407 INFO: [APUAPC] D8_APC_0: 0xffffffff
9937 00:59:21.519106 INFO: [APUAPC] D8_APC_1: 0xffffffff
9938 00:59:21.522139 INFO: [APUAPC] D8_APC_2: 0x3fffff
9939 00:59:21.525343 INFO: [APUAPC] D8_APC_3: 0x0
9940 00:59:21.528824 INFO: [APUAPC] D9_APC_0: 0xffffffff
9941 00:59:21.531803 INFO: [APUAPC] D9_APC_1: 0xffffffff
9942 00:59:21.535442 INFO: [APUAPC] D9_APC_2: 0x3fffff
9943 00:59:21.538589 INFO: [APUAPC] D9_APC_3: 0x0
9944 00:59:21.541921 INFO: [APUAPC] D10_APC_0: 0xffffffff
9945 00:59:21.545512 INFO: [APUAPC] D10_APC_1: 0xffffffff
9946 00:59:21.548749 INFO: [APUAPC] D10_APC_2: 0x3fffff
9947 00:59:21.551553 INFO: [APUAPC] D10_APC_3: 0x0
9948 00:59:21.555148 INFO: [APUAPC] D11_APC_0: 0xffffffff
9949 00:59:21.558704 INFO: [APUAPC] D11_APC_1: 0xffffffff
9950 00:59:21.561704 INFO: [APUAPC] D11_APC_2: 0x3fffff
9951 00:59:21.564944 INFO: [APUAPC] D11_APC_3: 0x0
9952 00:59:21.568477 INFO: [APUAPC] D12_APC_0: 0xffffffff
9953 00:59:21.571982 INFO: [APUAPC] D12_APC_1: 0xffffffff
9954 00:59:21.575011 INFO: [APUAPC] D12_APC_2: 0x3fffff
9955 00:59:21.578553 INFO: [APUAPC] D12_APC_3: 0x0
9956 00:59:21.581465 INFO: [APUAPC] D13_APC_0: 0xffffffff
9957 00:59:21.585177 INFO: [APUAPC] D13_APC_1: 0xffffffff
9958 00:59:21.588182 INFO: [APUAPC] D13_APC_2: 0x3fffff
9959 00:59:21.591709 INFO: [APUAPC] D13_APC_3: 0x0
9960 00:59:21.594666 INFO: [APUAPC] D14_APC_0: 0xffffffff
9961 00:59:21.598180 INFO: [APUAPC] D14_APC_1: 0xffffffff
9962 00:59:21.601605 INFO: [APUAPC] D14_APC_2: 0x3fffff
9963 00:59:21.604431 INFO: [APUAPC] D14_APC_3: 0x0
9964 00:59:21.607875 INFO: [APUAPC] D15_APC_0: 0xffffffff
9965 00:59:21.611410 INFO: [APUAPC] D15_APC_1: 0xffffffff
9966 00:59:21.614591 INFO: [APUAPC] D15_APC_2: 0x3fffff
9967 00:59:21.617993 INFO: [APUAPC] D15_APC_3: 0x0
9968 00:59:21.621548 INFO: [APUAPC] APC_CON: 0x4
9969 00:59:21.624481 INFO: [NOCDAPC] D0_APC_0: 0x0
9970 00:59:21.624575 INFO: [NOCDAPC] D0_APC_1: 0x0
9971 00:59:21.627932 INFO: [NOCDAPC] D1_APC_0: 0x0
9972 00:59:21.631273 INFO: [NOCDAPC] D1_APC_1: 0xfff
9973 00:59:21.634511 INFO: [NOCDAPC] D2_APC_0: 0x0
9974 00:59:21.637629 INFO: [NOCDAPC] D2_APC_1: 0xfff
9975 00:59:21.641055 INFO: [NOCDAPC] D3_APC_0: 0x0
9976 00:59:21.644686 INFO: [NOCDAPC] D3_APC_1: 0xfff
9977 00:59:21.647584 INFO: [NOCDAPC] D4_APC_0: 0x0
9978 00:59:21.650953 INFO: [NOCDAPC] D4_APC_1: 0xfff
9979 00:59:21.654668 INFO: [NOCDAPC] D5_APC_0: 0x0
9980 00:59:21.657706 INFO: [NOCDAPC] D5_APC_1: 0xfff
9981 00:59:21.657798 INFO: [NOCDAPC] D6_APC_0: 0x0
9982 00:59:21.660952 INFO: [NOCDAPC] D6_APC_1: 0xfff
9983 00:59:21.664428 INFO: [NOCDAPC] D7_APC_0: 0x0
9984 00:59:21.667363 INFO: [NOCDAPC] D7_APC_1: 0xfff
9985 00:59:21.670987 INFO: [NOCDAPC] D8_APC_0: 0x0
9986 00:59:21.674183 INFO: [NOCDAPC] D8_APC_1: 0xfff
9987 00:59:21.677204 INFO: [NOCDAPC] D9_APC_0: 0x0
9988 00:59:21.680757 INFO: [NOCDAPC] D9_APC_1: 0xfff
9989 00:59:21.684221 INFO: [NOCDAPC] D10_APC_0: 0x0
9990 00:59:21.687220 INFO: [NOCDAPC] D10_APC_1: 0xfff
9991 00:59:21.690812 INFO: [NOCDAPC] D11_APC_0: 0x0
9992 00:59:21.694421 INFO: [NOCDAPC] D11_APC_1: 0xfff
9993 00:59:21.694498 INFO: [NOCDAPC] D12_APC_0: 0x0
9994 00:59:21.697375 INFO: [NOCDAPC] D12_APC_1: 0xfff
9995 00:59:21.700831 INFO: [NOCDAPC] D13_APC_0: 0x0
9996 00:59:21.703795 INFO: [NOCDAPC] D13_APC_1: 0xfff
9997 00:59:21.707144 INFO: [NOCDAPC] D14_APC_0: 0x0
9998 00:59:21.710567 INFO: [NOCDAPC] D14_APC_1: 0xfff
9999 00:59:21.714088 INFO: [NOCDAPC] D15_APC_0: 0x0
10000 00:59:21.717514 INFO: [NOCDAPC] D15_APC_1: 0xfff
10001 00:59:21.720661 INFO: [NOCDAPC] APC_CON: 0x4
10002 00:59:21.723617 INFO: [APUAPC] set_apusys_apc done
10003 00:59:21.727119 INFO: [DEVAPC] devapc_init done
10004 00:59:21.730654 INFO: GICv3 without legacy support detected.
10005 00:59:21.733717 INFO: ARM GICv3 driver initialized in EL3
10006 00:59:21.737270 INFO: Maximum SPI INTID supported: 639
10007 00:59:21.743820 INFO: BL31: Initializing runtime services
10008 00:59:21.747275 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10009 00:59:21.750408 INFO: SPM: enable CPC mode
10010 00:59:21.756882 INFO: mcdi ready for mcusys-off-idle and system suspend
10011 00:59:21.760557 INFO: BL31: Preparing for EL3 exit to normal world
10012 00:59:21.763916 INFO: Entry point address = 0x80000000
10013 00:59:21.766706 INFO: SPSR = 0x8
10014 00:59:21.772794
10015 00:59:21.772870
10016 00:59:21.772931
10017 00:59:21.775753 Starting depthcharge on Spherion...
10018 00:59:21.775830
10019 00:59:21.775890 Wipe memory regions:
10020 00:59:21.775945
10021 00:59:21.776517 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10022 00:59:21.776609 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10023 00:59:21.776729 Setting prompt string to ['asurada:']
10024 00:59:21.776799 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10025 00:59:21.778731 [0x00000040000000, 0x00000054600000)
10026 00:59:21.901576
10027 00:59:21.901682 [0x00000054660000, 0x00000080000000)
10028 00:59:22.162396
10029 00:59:22.162835 [0x000000821a7280, 0x000000ffe64000)
10030 00:59:22.907239
10031 00:59:22.907733 [0x00000100000000, 0x00000240000000)
10032 00:59:24.796973
10033 00:59:24.799843 Initializing XHCI USB controller at 0x11200000.
10034 00:59:25.838161
10035 00:59:25.841741 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10036 00:59:25.841837
10037 00:59:25.841922
10038 00:59:25.842236 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 00:59:25.942601 asurada: tftpboot 192.168.201.1 14368605/tftp-deploy-djasquo9/kernel/image.itb 14368605/tftp-deploy-djasquo9/kernel/cmdline
10041 00:59:25.942793 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 00:59:25.942886 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10043 00:59:25.947197 tftpboot 192.168.201.1 14368605/tftp-deploy-djasquo9/kernel/image.ittp-deploy-djasquo9/kernel/cmdline
10044 00:59:25.947272
10045 00:59:25.947339 Waiting for link
10046 00:59:26.105243
10047 00:59:26.105345 R8152: Initializing
10048 00:59:26.105407
10049 00:59:26.108758 Version 6 (ocp_data = 5c30)
10050 00:59:26.108826
10051 00:59:26.111691 R8152: Done initializing
10052 00:59:26.111782
10053 00:59:26.111864 Adding net device
10054 00:59:28.017688
10055 00:59:28.017828 done.
10056 00:59:28.017915
10057 00:59:28.017997 MAC: 00:24:32:30:78:ff
10058 00:59:28.018079
10059 00:59:28.020946 Sending DHCP discover... done.
10060 00:59:28.021019
10061 00:59:40.051557 Waiting for reply... R8152: Bulk read error 0xffffffbf
10062 00:59:40.052070
10063 00:59:40.054685 Receive failed.
10064 00:59:40.055094
10065 00:59:40.055483 done.
10066 00:59:40.055768
10067 00:59:40.057840 Sending DHCP request... done.
10068 00:59:40.058338
10069 00:59:40.064681 Waiting for reply... done.
10070 00:59:40.065218
10071 00:59:40.065534 My ip is 192.168.201.21
10072 00:59:40.065814
10073 00:59:40.067757 The DHCP server ip is 192.168.201.1
10074 00:59:40.068146
10075 00:59:40.074183 TFTP server IP predefined by user: 192.168.201.1
10076 00:59:40.074572
10077 00:59:40.080710 Bootfile predefined by user: 14368605/tftp-deploy-djasquo9/kernel/image.itb
10078 00:59:40.081105
10079 00:59:40.084410 Sending tftp read request... done.
10080 00:59:40.084844
10081 00:59:40.091395 Waiting for the transfer...
10082 00:59:40.091792
10083 00:59:40.805690 00000000 ################################################################
10084 00:59:40.806177
10085 00:59:41.452071 00080000 ################################################################
10086 00:59:41.452227
10087 00:59:42.132318 00100000 ################################################################
10088 00:59:42.132529
10089 00:59:42.772691 00180000 ################################################################
10090 00:59:42.773141
10091 00:59:43.510333 00200000 ################################################################
10092 00:59:43.510859
10093 00:59:44.232836 00280000 ################################################################
10094 00:59:44.233294
10095 00:59:44.945330 00300000 ################################################################
10096 00:59:44.945787
10097 00:59:45.635977 00380000 ################################################################
10098 00:59:45.636478
10099 00:59:46.276878 00400000 ################################################################
10100 00:59:46.277357
10101 00:59:46.974100 00480000 ################################################################
10102 00:59:46.974551
10103 00:59:47.649678 00500000 ################################################################
10104 00:59:47.649791
10105 00:59:48.276127 00580000 ################################################################
10106 00:59:48.276244
10107 00:59:48.888057 00600000 ################################################################
10108 00:59:48.888713
10109 00:59:49.529708 00680000 ################################################################
10110 00:59:49.530179
10111 00:59:50.177490 00700000 ################################################################
10112 00:59:50.177940
10113 00:59:50.836274 00780000 ################################################################
10114 00:59:50.836740
10115 00:59:51.441177 00800000 ################################################################
10116 00:59:51.441616
10117 00:59:52.057193 00880000 ################################################################
10118 00:59:52.057307
10119 00:59:52.697182 00900000 ################################################################
10120 00:59:52.697716
10121 00:59:53.377849 00980000 ################################################################
10122 00:59:53.378293
10123 00:59:53.972911 00a00000 ################################################################
10124 00:59:53.973578
10125 00:59:54.628264 00a80000 ################################################################
10126 00:59:54.628753
10127 00:59:55.345145 00b00000 ################################################################
10128 00:59:55.345649
10129 00:59:56.053094 00b80000 ################################################################
10130 00:59:56.053564
10131 00:59:56.759338 00c00000 ################################################################
10132 00:59:56.759793
10133 00:59:57.468308 00c80000 ################################################################
10134 00:59:57.468816
10135 00:59:58.103570 00d00000 ################################################################
10136 00:59:58.104216
10137 00:59:58.725895 00d80000 ################################################################
10138 00:59:58.726338
10139 00:59:59.422059 00e00000 ################################################################
10140 00:59:59.422499
10141 01:00:00.098388 00e80000 ################################################################
10142 01:00:00.098880
10143 01:00:00.765533 00f00000 ################################################################
10144 01:00:00.765857
10145 01:00:01.424728 00f80000 ################################################################
10146 01:00:01.425233
10147 01:00:02.086823 01000000 ################################################################
10148 01:00:02.087273
10149 01:00:02.780231 01080000 ################################################################
10150 01:00:02.780751
10151 01:00:03.469921 01100000 ################################################################
10152 01:00:03.470451
10153 01:00:04.165983 01180000 ################################################################
10154 01:00:04.166504
10155 01:00:04.830600 01200000 ################################################################
10156 01:00:04.831204
10157 01:00:05.531398 01280000 ################################################################
10158 01:00:05.531950
10159 01:00:06.225077 01300000 ################################################################
10160 01:00:06.225487
10161 01:00:06.902169 01380000 ################################################################
10162 01:00:06.902625
10163 01:00:07.551269 01400000 ################################################################
10164 01:00:07.551889
10165 01:00:08.206441 01480000 ################################################################
10166 01:00:08.206560
10167 01:00:08.840950 01500000 ################################################################
10168 01:00:08.841420
10169 01:00:09.525906 01580000 ################################################################
10170 01:00:09.526466
10171 01:00:10.223125 01600000 ################################################################
10172 01:00:10.223632
10173 01:00:10.930996 01680000 ################################################################
10174 01:00:10.931439
10175 01:00:11.651480 01700000 ################################################################
10176 01:00:11.651806
10177 01:00:12.361358 01780000 ################################################################
10178 01:00:12.361856
10179 01:00:13.093949 01800000 ################################################################
10180 01:00:13.094394
10181 01:00:13.808156 01880000 ################################################################
10182 01:00:13.808626
10183 01:00:14.543081 01900000 ################################################################
10184 01:00:14.543566
10185 01:00:15.270898 01980000 ################################################################
10186 01:00:15.271450
10187 01:00:15.943744 01a00000 ################################################################
10188 01:00:15.944193
10189 01:00:16.616057 01a80000 ################################################################
10190 01:00:16.616172
10191 01:00:17.309625 01b00000 ################################################################
10192 01:00:17.310139
10193 01:00:18.048034 01b80000 ################################################################
10194 01:00:18.048485
10195 01:00:18.777247 01c00000 ################################################################
10196 01:00:18.777741
10197 01:00:19.494655 01c80000 ################################################################
10198 01:00:19.495162
10199 01:00:20.237863 01d00000 ################################################################
10200 01:00:20.238370
10201 01:00:20.946302 01d80000 ################################################################
10202 01:00:20.946760
10203 01:00:21.671900 01e00000 ################################################################
10204 01:00:21.672448
10205 01:00:22.404229 01e80000 ################################################################
10206 01:00:22.404794
10207 01:00:23.119807 01f00000 ################################################################
10208 01:00:23.120244
10209 01:00:23.802353 01f80000 ################################################################
10210 01:00:23.802823
10211 01:00:24.485416 02000000 ################################################################
10212 01:00:24.485860
10213 01:00:25.180968 02080000 ################################################################
10214 01:00:25.181413
10215 01:00:25.885622 02100000 ################################################################
10216 01:00:25.886193
10217 01:00:26.609553 02180000 ################################################################
10218 01:00:26.610008
10219 01:00:27.335996 02200000 ################################################################
10220 01:00:27.336446
10221 01:00:28.033590 02280000 ################################################################
10222 01:00:28.034035
10223 01:00:28.746280 02300000 ################################################################
10224 01:00:28.746824
10225 01:00:29.419977 02380000 ################################################################
10226 01:00:29.420527
10227 01:00:30.077621 02400000 ################################################################
10228 01:00:30.078068
10229 01:00:30.759916 02480000 ################################################################
10230 01:00:30.760364
10231 01:00:31.440561 02500000 ################################################################
10232 01:00:31.441290
10233 01:00:32.059189 02580000 ################################################################
10234 01:00:32.059324
10235 01:00:32.699927 02600000 ################################################################
10236 01:00:32.700416
10237 01:00:33.377415 02680000 ################################################################
10238 01:00:33.377994
10239 01:00:34.060373 02700000 ################################################################
10240 01:00:34.061017
10241 01:00:34.766192 02780000 ################################################################
10242 01:00:34.766751
10243 01:00:35.367040 02800000 ################################################################
10244 01:00:35.367591
10245 01:00:36.062693 02880000 ################################################################
10246 01:00:36.063138
10247 01:00:36.781933 02900000 ################################################################
10248 01:00:36.782374
10249 01:00:37.495737 02980000 ################################################################
10250 01:00:37.496423
10251 01:00:38.187503 02a00000 ################################################################
10252 01:00:38.187651
10253 01:00:38.874580 02a80000 ################################################################
10254 01:00:38.875052
10255 01:00:39.573481 02b00000 ################################################################
10256 01:00:39.574015
10257 01:00:40.257745 02b80000 ################################################################
10258 01:00:40.258349
10259 01:00:40.955661 02c00000 ################################################################
10260 01:00:40.956192
10261 01:00:41.659532 02c80000 ################################################################
10262 01:00:41.660018
10263 01:00:42.379217 02d00000 ################################################################
10264 01:00:42.379746
10265 01:00:43.108358 02d80000 ################################################################
10266 01:00:43.108888
10267 01:00:43.831883 02e00000 ################################################################
10268 01:00:43.832341
10269 01:00:44.521822 02e80000 ################################################################
10270 01:00:44.522287
10271 01:00:45.226905 02f00000 ################################################################
10272 01:00:45.227367
10273 01:00:45.936309 02f80000 ################################################################
10274 01:00:45.936974
10275 01:00:46.653977 03000000 ################################################################
10276 01:00:46.654425
10277 01:00:47.363869 03080000 ################################################################
10278 01:00:47.364319
10279 01:00:48.079546 03100000 ################################################################
10280 01:00:48.080046
10281 01:00:48.777606 03180000 ################################################################
10282 01:00:48.778050
10283 01:00:49.509376 03200000 ################################################################
10284 01:00:49.509868
10285 01:00:50.218770 03280000 ################################################################
10286 01:00:50.219212
10287 01:00:50.940503 03300000 ################################################################
10288 01:00:50.941000
10289 01:00:51.661281 03380000 ################################################################
10290 01:00:51.661749
10291 01:00:52.368640 03400000 ################################################################
10292 01:00:52.369295
10293 01:00:53.090486 03480000 ################################################################
10294 01:00:53.090939
10295 01:00:53.822396 03500000 ################################################################
10296 01:00:53.822891
10297 01:00:54.546450 03580000 ################################################################
10298 01:00:54.546909
10299 01:00:55.226209 03600000 ################################################################
10300 01:00:55.226348
10301 01:00:55.895134 03680000 ################################################################
10302 01:00:55.895612
10303 01:00:56.627202 03700000 ################################################################
10304 01:00:56.627691
10305 01:00:57.331301 03780000 ################################################################
10306 01:00:57.331924
10307 01:00:58.032464 03800000 ################################################################
10308 01:00:58.032987
10309 01:00:58.737557 03880000 ################################################################
10310 01:00:58.738039
10311 01:00:59.458233 03900000 ################################################################
10312 01:00:59.458766
10313 01:01:00.198758 03980000 ################################################################
10314 01:01:00.199208
10315 01:01:00.893343 03a00000 ################################################################
10316 01:01:00.893782
10317 01:01:01.608008 03a80000 ################################################################
10318 01:01:01.608462
10319 01:01:02.297728 03b00000 ################################################################
10320 01:01:02.297975
10321 01:01:02.976536 03b80000 ################################################################
10322 01:01:02.976705
10323 01:01:03.676727 03c00000 ################################################################
10324 01:01:03.677234
10325 01:01:04.395622 03c80000 ################################################################
10326 01:01:04.396122
10327 01:01:05.113274 03d00000 ################################################################
10328 01:01:05.113755
10329 01:01:05.814207 03d80000 ################################################################
10330 01:01:05.814675
10331 01:01:06.238185 03e00000 ##################################### done.
10332 01:01:06.238651
10333 01:01:06.241432 The bootfile was 65311874 bytes long.
10334 01:01:06.241851
10335 01:01:06.244995 Sending tftp read request... done.
10336 01:01:06.245383
10337 01:01:06.248937 Waiting for the transfer...
10338 01:01:06.249329
10339 01:01:06.249634 00000000 # done.
10340 01:01:06.249927
10341 01:01:06.255465 Command line loaded dynamically from TFTP file: 14368605/tftp-deploy-djasquo9/kernel/cmdline
10342 01:01:06.255862
10343 01:01:06.272217 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10344 01:01:06.272722
10345 01:01:06.273030 Loading FIT.
10346 01:01:06.273307
10347 01:01:06.275457 Image ramdisk-1 has 52137544 bytes.
10348 01:01:06.275842
10349 01:01:06.278509 Image fdt-1 has 47258 bytes.
10350 01:01:06.278895
10351 01:01:06.281909 Image kernel-1 has 13125045 bytes.
10352 01:01:06.282296
10353 01:01:06.288638 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10354 01:01:06.289130
10355 01:01:06.308451 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10356 01:01:06.309030
10357 01:01:06.312157 Choosing best match conf-1 for compat google,spherion-rev2.
10358 01:01:06.316595
10359 01:01:06.321216 Connected to device vid:did:rid of 1ae0:0028:00
10360 01:01:06.328341
10361 01:01:06.331792 tpm_get_response: command 0x17b, return code 0x0
10362 01:01:06.332423
10363 01:01:06.337951 ec_init: CrosEC protocol v3 supported (256, 248)
10364 01:01:06.338338
10365 01:01:06.341415 tpm_cleanup: add release locality here.
10366 01:01:06.341802
10367 01:01:06.344626 Shutting down all USB controllers.
10368 01:01:06.345052
10369 01:01:06.348033 Removing current net device
10370 01:01:06.348417
10371 01:01:06.351700 Exiting depthcharge with code 4 at timestamp: 133863291
10372 01:01:06.352356
10373 01:01:06.355056 LZMA decompressing kernel-1 to 0x821a6718
10374 01:01:06.355541
10375 01:01:06.358454 LZMA decompressing kernel-1 to 0x40000000
10376 01:01:07.975772
10377 01:01:07.976239 jumping to kernel
10378 01:01:07.978126 end: 2.2.4 bootloader-commands (duration 00:01:46) [common]
10379 01:01:07.978562 start: 2.2.5 auto-login-action (timeout 00:02:41) [common]
10380 01:01:07.978897 Setting prompt string to ['Linux version [0-9]']
10381 01:01:07.979209 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10382 01:01:07.979524 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10383 01:01:08.057752
10384 01:01:08.060812 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10385 01:01:08.064778 start: 2.2.5.1 login-action (timeout 00:02:41) [common]
10386 01:01:08.065241 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10387 01:01:08.065576 Setting prompt string to []
10388 01:01:08.065931 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10389 01:01:08.066247 Using line separator: #'\n'#
10390 01:01:08.066517 No login prompt set.
10391 01:01:08.066806 Parsing kernel messages
10392 01:01:08.067125 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10393 01:01:08.067622 [login-action] Waiting for messages, (timeout 00:02:41)
10394 01:01:08.067936 Waiting using forced prompt support (timeout 00:01:20)
10395 01:01:08.084183 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10396 01:01:08.087284 [ 0.000000] random: crng init done
10397 01:01:08.094084 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10398 01:01:08.097589 [ 0.000000] efi: UEFI not found.
10399 01:01:08.103832 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10400 01:01:08.110300 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10401 01:01:08.120622 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10402 01:01:08.130399 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10403 01:01:08.137041 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10404 01:01:08.143632 [ 0.000000] printk: bootconsole [mtk8250] enabled
10405 01:01:08.150059 [ 0.000000] NUMA: No NUMA configuration found
10406 01:01:08.156559 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10407 01:01:08.160008 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10408 01:01:08.163584 [ 0.000000] Zone ranges:
10409 01:01:08.170211 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10410 01:01:08.173253 [ 0.000000] DMA32 empty
10411 01:01:08.180204 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10412 01:01:08.183418 [ 0.000000] Movable zone start for each node
10413 01:01:08.186606 [ 0.000000] Early memory node ranges
10414 01:01:08.193086 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10415 01:01:08.200502 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10416 01:01:08.206480 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10417 01:01:08.213007 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10418 01:01:08.219796 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10419 01:01:08.226134 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10420 01:01:08.282302 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10421 01:01:08.288877 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10422 01:01:08.295329 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10423 01:01:08.299212 [ 0.000000] psci: probing for conduit method from DT.
10424 01:01:08.305381 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10425 01:01:08.309025 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10426 01:01:08.315344 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10427 01:01:08.318685 [ 0.000000] psci: SMC Calling Convention v1.2
10428 01:01:08.325367 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10429 01:01:08.328800 [ 0.000000] Detected VIPT I-cache on CPU0
10430 01:01:08.336137 [ 0.000000] CPU features: detected: GIC system register CPU interface
10431 01:01:08.342134 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10432 01:01:08.348518 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10433 01:01:08.355708 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10434 01:01:08.364872 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10435 01:01:08.371848 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10436 01:01:08.375361 [ 0.000000] alternatives: applying boot alternatives
10437 01:01:08.381984 [ 0.000000] Fallback order for Node 0: 0
10438 01:01:08.388305 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10439 01:01:08.392233 [ 0.000000] Policy zone: Normal
10440 01:01:08.405272 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10441 01:01:08.414695 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10442 01:01:08.426983 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10443 01:01:08.436795 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10444 01:01:08.443652 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10445 01:01:08.446476 <6>[ 0.000000] software IO TLB: area num 8.
10446 01:01:08.503455 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10447 01:01:08.652574 <6>[ 0.000000] Memory: 7913148K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 439620K reserved, 32768K cma-reserved)
10448 01:01:08.659157 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10449 01:01:08.666430 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10450 01:01:08.669652 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10451 01:01:08.676130 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10452 01:01:08.682572 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10453 01:01:08.686100 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10454 01:01:08.695975 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10455 01:01:08.702287 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10456 01:01:08.709573 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10457 01:01:08.716011 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10458 01:01:08.718926 <6>[ 0.000000] GICv3: 608 SPIs implemented
10459 01:01:08.722408 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10460 01:01:08.729353 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10461 01:01:08.732587 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10462 01:01:08.738994 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10463 01:01:08.751867 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10464 01:01:08.765592 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10465 01:01:08.771956 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10466 01:01:08.779801 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10467 01:01:08.793089 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10468 01:01:08.799877 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10469 01:01:08.806410 <6>[ 0.009230] Console: colour dummy device 80x25
10470 01:01:08.816253 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10471 01:01:08.822841 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10472 01:01:08.825745 <6>[ 0.029303] LSM: Security Framework initializing
10473 01:01:08.832885 <6>[ 0.034243] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10474 01:01:08.842896 <6>[ 0.042059] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10475 01:01:08.849520 <6>[ 0.051483] cblist_init_generic: Setting adjustable number of callback queues.
10476 01:01:08.855770 <6>[ 0.058927] cblist_init_generic: Setting shift to 3 and lim to 1.
10477 01:01:08.865619 <6>[ 0.065268] cblist_init_generic: Setting adjustable number of callback queues.
10478 01:01:08.868760 <6>[ 0.072740] cblist_init_generic: Setting shift to 3 and lim to 1.
10479 01:01:08.875515 <6>[ 0.079139] rcu: Hierarchical SRCU implementation.
10480 01:01:08.882639 <6>[ 0.084185] rcu: Max phase no-delay instances is 1000.
10481 01:01:08.889194 <6>[ 0.091243] EFI services will not be available.
10482 01:01:08.892437 <6>[ 0.096198] smp: Bringing up secondary CPUs ...
10483 01:01:08.900233 <6>[ 0.101249] Detected VIPT I-cache on CPU1
10484 01:01:08.906600 <6>[ 0.101319] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10485 01:01:08.913757 <6>[ 0.101350] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10486 01:01:08.916781 <6>[ 0.101686] Detected VIPT I-cache on CPU2
10487 01:01:08.923449 <6>[ 0.101740] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10488 01:01:08.930083 <6>[ 0.101758] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10489 01:01:08.936589 <6>[ 0.102017] Detected VIPT I-cache on CPU3
10490 01:01:08.943407 <6>[ 0.102063] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10491 01:01:08.949917 <6>[ 0.102077] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10492 01:01:08.953568 <6>[ 0.102380] CPU features: detected: Spectre-v4
10493 01:01:08.960061 <6>[ 0.102386] CPU features: detected: Spectre-BHB
10494 01:01:08.963391 <6>[ 0.102391] Detected PIPT I-cache on CPU4
10495 01:01:08.969604 <6>[ 0.102450] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10496 01:01:08.976642 <6>[ 0.102467] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10497 01:01:08.982913 <6>[ 0.102750] Detected PIPT I-cache on CPU5
10498 01:01:08.989760 <6>[ 0.102805] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10499 01:01:08.995907 <6>[ 0.102821] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10500 01:01:08.999334 <6>[ 0.103092] Detected PIPT I-cache on CPU6
10501 01:01:09.006636 <6>[ 0.103157] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10502 01:01:09.012526 <6>[ 0.103173] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10503 01:01:09.019132 <6>[ 0.103473] Detected PIPT I-cache on CPU7
10504 01:01:09.025936 <6>[ 0.103538] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10505 01:01:09.032602 <6>[ 0.103554] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10506 01:01:09.035740 <6>[ 0.103601] smp: Brought up 1 node, 8 CPUs
10507 01:01:09.042014 <6>[ 0.244956] SMP: Total of 8 processors activated.
10508 01:01:09.045490 <6>[ 0.249908] CPU features: detected: 32-bit EL0 Support
10509 01:01:09.055453 <6>[ 0.255272] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10510 01:01:09.062266 <6>[ 0.264072] CPU features: detected: Common not Private translations
10511 01:01:09.068987 <6>[ 0.270548] CPU features: detected: CRC32 instructions
10512 01:01:09.071833 <6>[ 0.275933] CPU features: detected: RCpc load-acquire (LDAPR)
10513 01:01:09.078586 <6>[ 0.281893] CPU features: detected: LSE atomic instructions
10514 01:01:09.085180 <6>[ 0.287674] CPU features: detected: Privileged Access Never
10515 01:01:09.091745 <6>[ 0.293454] CPU features: detected: RAS Extension Support
10516 01:01:09.098423 <6>[ 0.299062] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10517 01:01:09.101770 <6>[ 0.306282] CPU: All CPU(s) started at EL2
10518 01:01:09.108353 <6>[ 0.310599] alternatives: applying system-wide alternatives
10519 01:01:09.118169 <6>[ 0.321481] devtmpfs: initialized
10520 01:01:09.130136 <6>[ 0.330392] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10521 01:01:09.140271 <6>[ 0.340354] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10522 01:01:09.146978 <6>[ 0.348368] pinctrl core: initialized pinctrl subsystem
10523 01:01:09.150488 <6>[ 0.355039] DMI not present or invalid.
10524 01:01:09.157014 <6>[ 0.359449] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10525 01:01:09.166956 <6>[ 0.366296] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10526 01:01:09.173506 <6>[ 0.373884] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10527 01:01:09.183572 <6>[ 0.382106] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10528 01:01:09.186514 <6>[ 0.390348] audit: initializing netlink subsys (disabled)
10529 01:01:09.196787 <5>[ 0.396044] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10530 01:01:09.203909 <6>[ 0.396765] thermal_sys: Registered thermal governor 'step_wise'
10531 01:01:09.209689 <6>[ 0.404010] thermal_sys: Registered thermal governor 'power_allocator'
10532 01:01:09.213286 <6>[ 0.410267] cpuidle: using governor menu
10533 01:01:09.219875 <6>[ 0.421223] NET: Registered PF_QIPCRTR protocol family
10534 01:01:09.226396 <6>[ 0.426701] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10535 01:01:09.229519 <6>[ 0.433805] ASID allocator initialised with 32768 entries
10536 01:01:09.236900 <6>[ 0.440393] Serial: AMBA PL011 UART driver
10537 01:01:09.245801 <4>[ 0.449232] Trying to register duplicate clock ID: 134
10538 01:01:09.304232 <6>[ 0.510734] KASLR enabled
10539 01:01:09.318948 <6>[ 0.518484] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10540 01:01:09.325451 <6>[ 0.525501] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10541 01:01:09.332118 <6>[ 0.531991] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10542 01:01:09.338118 <6>[ 0.538999] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10543 01:01:09.345305 <6>[ 0.545483] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10544 01:01:09.351689 <6>[ 0.552488] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10545 01:01:09.358303 <6>[ 0.558974] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10546 01:01:09.364862 <6>[ 0.565982] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10547 01:01:09.368009 <6>[ 0.573509] ACPI: Interpreter disabled.
10548 01:01:09.376776 <6>[ 0.579938] iommu: Default domain type: Translated
10549 01:01:09.382973 <6>[ 0.585050] iommu: DMA domain TLB invalidation policy: strict mode
10550 01:01:09.386468 <5>[ 0.591711] SCSI subsystem initialized
10551 01:01:09.393117 <6>[ 0.595879] usbcore: registered new interface driver usbfs
10552 01:01:09.399671 <6>[ 0.601613] usbcore: registered new interface driver hub
10553 01:01:09.403191 <6>[ 0.607165] usbcore: registered new device driver usb
10554 01:01:09.410137 <6>[ 0.613259] pps_core: LinuxPPS API ver. 1 registered
10555 01:01:09.420125 <6>[ 0.618452] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10556 01:01:09.423642 <6>[ 0.627800] PTP clock support registered
10557 01:01:09.426586 <6>[ 0.632044] EDAC MC: Ver: 3.0.0
10558 01:01:09.434054 <6>[ 0.637193] FPGA manager framework
10559 01:01:09.440362 <6>[ 0.640878] Advanced Linux Sound Architecture Driver Initialized.
10560 01:01:09.443551 <6>[ 0.647659] vgaarb: loaded
10561 01:01:09.450168 <6>[ 0.650811] clocksource: Switched to clocksource arch_sys_counter
10562 01:01:09.452976 <5>[ 0.657253] VFS: Disk quotas dquot_6.6.0
10563 01:01:09.459744 <6>[ 0.661439] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10564 01:01:09.463214 <6>[ 0.668632] pnp: PnP ACPI: disabled
10565 01:01:09.471952 <6>[ 0.675359] NET: Registered PF_INET protocol family
10566 01:01:09.481585 <6>[ 0.680953] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10567 01:01:09.493003 <6>[ 0.693279] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10568 01:01:09.503289 <6>[ 0.702097] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10569 01:01:09.509610 <6>[ 0.710067] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10570 01:01:09.516354 <6>[ 0.718767] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10571 01:01:09.528831 <6>[ 0.728525] TCP: Hash tables configured (established 65536 bind 65536)
10572 01:01:09.535093 <6>[ 0.735390] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10573 01:01:09.541641 <6>[ 0.742589] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10574 01:01:09.548665 <6>[ 0.750293] NET: Registered PF_UNIX/PF_LOCAL protocol family
10575 01:01:09.555301 <6>[ 0.756392] RPC: Registered named UNIX socket transport module.
10576 01:01:09.558056 <6>[ 0.762542] RPC: Registered udp transport module.
10577 01:01:09.565328 <6>[ 0.767474] RPC: Registered tcp transport module.
10578 01:01:09.571886 <6>[ 0.772407] RPC: Registered tcp NFSv4.1 backchannel transport module.
10579 01:01:09.575329 <6>[ 0.779074] PCI: CLS 0 bytes, default 64
10580 01:01:09.578501 <6>[ 0.783398] Unpacking initramfs...
10581 01:01:09.602915 <6>[ 0.802931] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10582 01:01:09.612790 <6>[ 0.811596] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10583 01:01:09.616440 <6>[ 0.820411] kvm [1]: IPA Size Limit: 40 bits
10584 01:01:09.622785 <6>[ 0.824936] kvm [1]: GICv3: no GICV resource entry
10585 01:01:09.625973 <6>[ 0.829957] kvm [1]: disabling GICv2 emulation
10586 01:01:09.632521 <6>[ 0.834642] kvm [1]: GIC system register CPU interface enabled
10587 01:01:09.636125 <6>[ 0.840791] kvm [1]: vgic interrupt IRQ18
10588 01:01:09.642640 <6>[ 0.845143] kvm [1]: VHE mode initialized successfully
10589 01:01:09.649100 <5>[ 0.851484] Initialise system trusted keyrings
10590 01:01:09.656048 <6>[ 0.856260] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10591 01:01:09.663103 <6>[ 0.866302] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10592 01:01:09.669639 <5>[ 0.872777] NFS: Registering the id_resolver key type
10593 01:01:09.673198 <5>[ 0.878087] Key type id_resolver registered
10594 01:01:09.679749 <5>[ 0.882504] Key type id_legacy registered
10595 01:01:09.686357 <6>[ 0.886783] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10596 01:01:09.692753 <6>[ 0.893705] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10597 01:01:09.699206 <6>[ 0.901447] 9p: Installing v9fs 9p2000 file system support
10598 01:01:09.735684 <5>[ 0.939015] Key type asymmetric registered
10599 01:01:09.739014 <5>[ 0.943346] Asymmetric key parser 'x509' registered
10600 01:01:09.748769 <6>[ 0.948483] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10601 01:01:09.751848 <6>[ 0.956098] io scheduler mq-deadline registered
10602 01:01:09.755304 <6>[ 0.960857] io scheduler kyber registered
10603 01:01:09.773703 <6>[ 0.977571] EINJ: ACPI disabled.
10604 01:01:09.806527 <4>[ 1.003195] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 01:01:09.816449 <4>[ 1.013819] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10606 01:01:09.831149 <6>[ 1.034729] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10607 01:01:09.839487 <6>[ 1.042594] printk: console [ttyS0] disabled
10608 01:01:09.867402 <6>[ 1.067223] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10609 01:01:09.873877 <6>[ 1.076698] printk: console [ttyS0] enabled
10610 01:01:09.877351 <6>[ 1.076698] printk: console [ttyS0] enabled
10611 01:01:09.883960 <6>[ 1.085593] printk: bootconsole [mtk8250] disabled
10612 01:01:09.887279 <6>[ 1.085593] printk: bootconsole [mtk8250] disabled
10613 01:01:09.893738 <6>[ 1.096624] SuperH (H)SCI(F) driver initialized
10614 01:01:09.896987 <6>[ 1.101904] msm_serial: driver initialized
10615 01:01:09.911051 <6>[ 1.110882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10616 01:01:09.920996 <6>[ 1.119431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10617 01:01:09.927490 <6>[ 1.127972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10618 01:01:09.937575 <6>[ 1.136600] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10619 01:01:09.947444 <6>[ 1.145306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10620 01:01:09.954460 <6>[ 1.154027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10621 01:01:09.963999 <6>[ 1.162567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10622 01:01:09.970734 <6>[ 1.171365] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10623 01:01:09.980446 <6>[ 1.179907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10624 01:01:09.991876 <6>[ 1.195185] loop: module loaded
10625 01:01:09.998724 <6>[ 1.201271] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10626 01:01:10.021556 <4>[ 1.224716] mtk-pmic-keys: Failed to locate of_node [id: -1]
10627 01:01:10.028173 <6>[ 1.231629] megasas: 07.719.03.00-rc1
10628 01:01:10.037831 <6>[ 1.241366] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10629 01:01:10.046882 <6>[ 1.250197] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10630 01:01:10.063829 <6>[ 1.266899] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10631 01:01:10.119548 <6>[ 1.316333] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10632 01:01:11.820951 <6>[ 3.024415] Freeing initrd memory: 50908K
10633 01:01:11.832584 <6>[ 3.035940] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10634 01:01:11.843580 <6>[ 3.047109] tun: Universal TUN/TAP device driver, 1.6
10635 01:01:11.846584 <6>[ 3.053158] thunder_xcv, ver 1.0
10636 01:01:11.850341 <6>[ 3.056668] thunder_bgx, ver 1.0
10637 01:01:11.853200 <6>[ 3.060163] nicpf, ver 1.0
10638 01:01:11.863752 <6>[ 3.064185] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10639 01:01:11.867656 <6>[ 3.071661] hns3: Copyright (c) 2017 Huawei Corporation.
10640 01:01:11.874186 <6>[ 3.077253] hclge is initializing
10641 01:01:11.876923 <6>[ 3.080836] e1000: Intel(R) PRO/1000 Network Driver
10642 01:01:11.883996 <6>[ 3.085965] e1000: Copyright (c) 1999-2006 Intel Corporation.
10643 01:01:11.887132 <6>[ 3.091979] e1000e: Intel(R) PRO/1000 Network Driver
10644 01:01:11.894152 <6>[ 3.097194] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10645 01:01:11.900481 <6>[ 3.103379] igb: Intel(R) Gigabit Ethernet Network Driver
10646 01:01:11.907465 <6>[ 3.109028] igb: Copyright (c) 2007-2014 Intel Corporation.
10647 01:01:11.913617 <6>[ 3.114867] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10648 01:01:11.919891 <6>[ 3.121384] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10649 01:01:11.923299 <6>[ 3.127845] sky2: driver version 1.30
10650 01:01:11.930363 <6>[ 3.132771] usbcore: registered new device driver r8152-cfgselector
10651 01:01:11.936388 <6>[ 3.139305] usbcore: registered new interface driver r8152
10652 01:01:11.943327 <6>[ 3.145122] VFIO - User Level meta-driver version: 0.3
10653 01:01:11.949605 <6>[ 3.153377] usbcore: registered new interface driver usb-storage
10654 01:01:11.956419 <6>[ 3.159821] usbcore: registered new device driver onboard-usb-hub
10655 01:01:11.965615 <6>[ 3.169026] mt6397-rtc mt6359-rtc: registered as rtc0
10656 01:01:11.975912 <6>[ 3.174513] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T01:01:11 UTC (1718499671)
10657 01:01:11.978762 <6>[ 3.184129] i2c_dev: i2c /dev entries driver
10658 01:01:11.992610 <4>[ 3.196088] cpu cpu0: supply cpu not found, using dummy regulator
10659 01:01:11.999351 <4>[ 3.202516] cpu cpu1: supply cpu not found, using dummy regulator
10660 01:01:12.005661 <4>[ 3.208920] cpu cpu2: supply cpu not found, using dummy regulator
10661 01:01:12.012258 <4>[ 3.215338] cpu cpu3: supply cpu not found, using dummy regulator
10662 01:01:12.019057 <4>[ 3.221739] cpu cpu4: supply cpu not found, using dummy regulator
10663 01:01:12.025670 <4>[ 3.228136] cpu cpu5: supply cpu not found, using dummy regulator
10664 01:01:12.032220 <4>[ 3.234541] cpu cpu6: supply cpu not found, using dummy regulator
10665 01:01:12.038925 <4>[ 3.240935] cpu cpu7: supply cpu not found, using dummy regulator
10666 01:01:12.058497 <6>[ 3.261581] cpu cpu0: EM: created perf domain
10667 01:01:12.061159 <6>[ 3.266494] cpu cpu4: EM: created perf domain
10668 01:01:12.068680 <6>[ 3.272058] sdhci: Secure Digital Host Controller Interface driver
10669 01:01:12.075518 <6>[ 3.278489] sdhci: Copyright(c) Pierre Ossman
10670 01:01:12.081743 <6>[ 3.283446] Synopsys Designware Multimedia Card Interface Driver
10671 01:01:12.088388 <6>[ 3.290082] sdhci-pltfm: SDHCI platform and OF driver helper
10672 01:01:12.091943 <6>[ 3.290130] mmc0: CQHCI version 5.10
10673 01:01:12.098328 <6>[ 3.300406] ledtrig-cpu: registered to indicate activity on CPUs
10674 01:01:12.104800 <6>[ 3.307342] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10675 01:01:12.111616 <6>[ 3.314397] usbcore: registered new interface driver usbhid
10676 01:01:12.114598 <6>[ 3.320221] usbhid: USB HID core driver
10677 01:01:12.121597 <6>[ 3.324426] spi_master spi0: will run message pump with realtime priority
10678 01:01:12.166779 <6>[ 3.363725] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10679 01:01:12.185083 <6>[ 3.378790] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10680 01:01:12.188363 <6>[ 3.389900] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10681 01:01:12.196733 <6>[ 3.400037] cros-ec-spi spi0.0: Chrome EC device registered
10682 01:01:12.203850 <6>[ 3.406066] mmc0: Command Queue Engine enabled
10683 01:01:12.209955 <6>[ 3.410827] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10684 01:01:12.213265 <6>[ 3.418515] mmcblk0: mmc0:0001 DA4128 116 GiB
10685 01:01:12.224181 <6>[ 3.427647] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10686 01:01:12.232241 <6>[ 3.435529] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10687 01:01:12.242436 <6>[ 3.439471] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10688 01:01:12.245536 <6>[ 3.441439] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10689 01:01:12.252264 <6>[ 3.451325] NET: Registered PF_PACKET protocol family
10690 01:01:12.258776 <6>[ 3.456023] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10691 01:01:12.261953 <6>[ 3.460643] 9pnet: Installing 9P2000 support
10692 01:01:12.268590 <5>[ 3.471660] Key type dns_resolver registered
10693 01:01:12.271902 <6>[ 3.476650] registered taskstats version 1
10694 01:01:12.278561 <5>[ 3.481040] Loading compiled-in X.509 certificates
10695 01:01:12.308069 <4>[ 3.504596] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10696 01:01:12.317231 <4>[ 3.515486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10697 01:01:12.332607 <6>[ 3.536126] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10698 01:01:12.339710 <6>[ 3.543006] xhci-mtk 11200000.usb: xHCI Host Controller
10699 01:01:12.346330 <6>[ 3.548499] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10700 01:01:12.356073 <6>[ 3.556339] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10701 01:01:12.363042 <6>[ 3.565772] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10702 01:01:12.369515 <6>[ 3.571829] xhci-mtk 11200000.usb: xHCI Host Controller
10703 01:01:12.375891 <6>[ 3.577313] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10704 01:01:12.382254 <6>[ 3.584961] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10705 01:01:12.388963 <6>[ 3.592602] hub 1-0:1.0: USB hub found
10706 01:01:12.392391 <6>[ 3.596629] hub 1-0:1.0: 1 port detected
10707 01:01:12.399090 <6>[ 3.600921] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10708 01:01:12.406307 <6>[ 3.609454] hub 2-0:1.0: USB hub found
10709 01:01:12.409252 <6>[ 3.613475] hub 2-0:1.0: 1 port detected
10710 01:01:12.417480 <6>[ 3.620755] mtk-msdc 11f70000.mmc: Got CD GPIO
10711 01:01:12.435140 <6>[ 3.635220] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10712 01:01:12.445117 <6>[ 3.643693] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10713 01:01:12.451587 <6>[ 3.652037] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10714 01:01:12.461599 <6>[ 3.660395] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10715 01:01:12.468608 <6>[ 3.668735] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10716 01:01:12.477930 <6>[ 3.677091] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10717 01:01:12.484616 <6>[ 3.685430] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10718 01:01:12.494930 <6>[ 3.693780] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10719 01:01:12.501216 <6>[ 3.702119] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10720 01:01:12.511404 <6>[ 3.710468] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10721 01:01:12.517608 <6>[ 3.718813] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10722 01:01:12.527950 <6>[ 3.727162] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10723 01:01:12.534235 <6>[ 3.735501] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10724 01:01:12.544082 <6>[ 3.743852] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10725 01:01:12.550558 <6>[ 3.752191] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10726 01:01:12.557076 <6>[ 3.760947] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10727 01:01:12.564281 <6>[ 3.768132] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10728 01:01:12.571080 <6>[ 3.774936] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10729 01:01:12.581756 <6>[ 3.781700] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10730 01:01:12.588592 <6>[ 3.788636] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10731 01:01:12.595150 <6>[ 3.795481] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10732 01:01:12.605006 <6>[ 3.804612] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10733 01:01:12.614689 <6>[ 3.813732] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10734 01:01:12.624039 <6>[ 3.823026] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10735 01:01:12.634320 <6>[ 3.832493] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10736 01:01:12.640708 <6>[ 3.841961] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10737 01:01:12.650408 <6>[ 3.851080] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10738 01:01:12.660218 <6>[ 3.860549] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10739 01:01:12.670631 <6>[ 3.869668] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10740 01:01:12.680514 <6>[ 3.878966] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10741 01:01:12.690240 <6>[ 3.889153] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10742 01:01:12.700945 <6>[ 3.901130] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10743 01:01:12.798652 <6>[ 3.999366] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10744 01:01:12.827081 <6>[ 4.030284] hub 2-1:1.0: USB hub found
10745 01:01:12.829763 <6>[ 4.034733] hub 2-1:1.0: 3 ports detected
10746 01:01:12.839055 <6>[ 4.042506] hub 2-1:1.0: USB hub found
10747 01:01:12.842101 <6>[ 4.046945] hub 2-1:1.0: 3 ports detected
10748 01:01:12.950809 <6>[ 4.151030] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10749 01:01:13.105084 <6>[ 4.308997] hub 1-1:1.0: USB hub found
10750 01:01:13.108564 <6>[ 4.313467] hub 1-1:1.0: 4 ports detected
10751 01:01:13.121370 <6>[ 4.325144] hub 1-1:1.0: USB hub found
10752 01:01:13.124794 <6>[ 4.329550] hub 1-1:1.0: 4 ports detected
10753 01:01:13.182697 <6>[ 4.383197] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10754 01:01:13.291200 <6>[ 4.491514] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10755 01:01:13.323437 <4>[ 4.523621] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10756 01:01:13.332977 <4>[ 4.532729] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10757 01:01:13.368490 <6>[ 4.571835] r8152 2-1.3:1.0 eth0: v1.12.13
10758 01:01:13.446767 <6>[ 4.647127] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10759 01:01:13.579600 <6>[ 4.782961] hub 1-1.4:1.0: USB hub found
10760 01:01:13.582665 <6>[ 4.787627] hub 1-1.4:1.0: 2 ports detected
10761 01:01:13.596260 <6>[ 4.799491] hub 1-1.4:1.0: USB hub found
10762 01:01:13.599042 <6>[ 4.804075] hub 1-1.4:1.0: 2 ports detected
10763 01:01:13.894621 <6>[ 5.095125] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10764 01:01:14.090873 <6>[ 5.291052] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10765 01:01:14.950861 <6>[ 6.155005] r8152 2-1.3:1.0 eth0: carrier on
10766 01:01:17.906384 <5>[ 6.174923] Sending DHCP requests .., OK
10767 01:01:17.913082 <6>[ 9.115226] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10768 01:01:17.916286 <6>[ 9.123528] IP-Config: Complete:
10769 01:01:17.929604 <6>[ 9.127029] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10770 01:01:17.935951 <6>[ 9.137778] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10771 01:01:17.942654 <6>[ 9.146400] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10772 01:01:17.949613 <6>[ 9.146410] nameserver0=192.168.201.1
10773 01:01:17.952539 <6>[ 9.158550] clk: Disabling unused clocks
10774 01:01:17.956123 <6>[ 9.164122] ALSA device list:
10775 01:01:17.962629 <6>[ 9.167392] No soundcards found.
10776 01:01:17.970435 <6>[ 9.175020] Freeing unused kernel memory: 8512K
10777 01:01:17.973943 <6>[ 9.179928] Run /init as init process
10778 01:01:18.003465 <6>[ 9.208019] NET: Registered PF_INET6 protocol family
10779 01:01:18.010270 <6>[ 9.214782] Segment Routing with IPv6
10780 01:01:18.013471 <6>[ 9.218819] In-situ OAM (IOAM) with IPv6
10781 01:01:18.056874 <30>[ 9.234978] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10782 01:01:18.063349 <30>[ 9.268058] systemd[1]: Detected architecture arm64.
10783 01:01:18.063642
10784 01:01:18.070151 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10785 01:01:18.070621
10786 01:01:18.082813 <30>[ 9.287201] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10787 01:01:18.205675 <30>[ 9.406933] systemd[1]: Queued start job for default target graphical.target.
10788 01:01:18.255781 <30>[ 9.456988] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10789 01:01:18.262482 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10790 01:01:18.282342 <30>[ 9.483576] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10791 01:01:18.292247 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10792 01:01:18.311130 <30>[ 9.512164] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10793 01:01:18.321126 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10794 01:01:18.340092 <30>[ 9.540833] systemd[1]: Created slice user.slice - User and Session Slice.
10795 01:01:18.346534 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10796 01:01:18.369931 <30>[ 9.567995] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10797 01:01:18.379836 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10798 01:01:18.397245 <30>[ 9.595320] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10799 01:01:18.404255 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10800 01:01:18.432718 <30>[ 9.623656] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10801 01:01:18.442668 <30>[ 9.643558] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10802 01:01:18.449114 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10803 01:01:18.466601 <30>[ 9.667482] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10804 01:01:18.476531 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10805 01:01:18.494564 <30>[ 9.695612] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10806 01:01:18.504434 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10807 01:01:18.518977 <30>[ 9.723621] systemd[1]: Reached target paths.target - Path Units.
10808 01:01:18.529583 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10809 01:01:18.546177 <30>[ 9.747252] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10810 01:01:18.552743 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10811 01:01:18.566550 <30>[ 9.771082] systemd[1]: Reached target slices.target - Slice Units.
10812 01:01:18.576749 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10813 01:01:18.591295 <30>[ 9.795592] systemd[1]: Reached target swap.target - Swaps.
10814 01:01:18.597689 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10815 01:01:18.618695 <30>[ 9.819633] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10816 01:01:18.628287 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10817 01:01:18.646226 <30>[ 9.847614] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10818 01:01:18.656594 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10819 01:01:18.676256 <30>[ 9.877193] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10820 01:01:18.686059 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10821 01:01:18.702733 <30>[ 9.903811] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10822 01:01:18.712714 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10823 01:01:18.731448 <30>[ 9.932318] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10824 01:01:18.737733 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10825 01:01:18.759804 <30>[ 9.960575] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10826 01:01:18.769161 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10827 01:01:18.786819 <30>[ 9.987817] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10828 01:01:18.796632 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10829 01:01:18.814232 <30>[ 10.015542] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10830 01:01:18.824242 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10831 01:01:18.870698 <30>[ 10.071363] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10832 01:01:18.876942 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10833 01:01:18.897390 <30>[ 10.098300] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10834 01:01:18.903780 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10835 01:01:18.924036 <30>[ 10.125277] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10836 01:01:18.930790 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10837 01:01:18.956525 <30>[ 10.151339] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10838 01:01:18.986819 <30>[ 10.187752] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10839 01:01:18.996740 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10840 01:01:19.019496 <30>[ 10.220637] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10841 01:01:19.025989 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10842 01:01:19.051572 <30>[ 10.252538] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10843 01:01:19.061412 Startin<6>[ 10.261956] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10844 01:01:19.067742 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10845 01:01:19.130875 <30>[ 10.331943] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10846 01:01:19.137429 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10847 01:01:19.163311 <30>[ 10.364524] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10848 01:01:19.172964 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10849 01:01:19.195288 <30>[ 10.396243] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10850 01:01:19.201761 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10851 01:01:19.230579 <30>[ 10.431810] systemd[1]: Starting systemd-journald.service - Journal Service...
10852 01:01:19.237156 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10853 01:01:19.256518 <30>[ 10.457809] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10854 01:01:19.263385 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10855 01:01:19.288588 <30>[ 10.486200] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10856 01:01:19.294921 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10857 01:01:19.318204 <30>[ 10.519209] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10858 01:01:19.328246 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10859 01:01:19.349323 <30>[ 10.550405] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10860 01:01:19.356291 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10861 01:01:19.378137 <30>[ 10.578970] systemd[1]: Started systemd-journald.service - Journal Service.
10862 01:01:19.384630 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10863 01:01:19.406527 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10864 01:01:19.422722 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10865 01:01:19.438874 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10866 01:01:19.458719 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10867 01:01:19.475149 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10868 01:01:19.495668 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10869 01:01:19.520788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10870 01:01:19.540366 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10871 01:01:19.560694 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10872 01:01:19.579577 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10873 01:01:19.600189 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10874 01:01:19.621023 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10875 01:01:19.634702 See 'systemctl status systemd-remount-fs.service' for details.
10876 01:01:19.644968 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10877 01:01:19.664965 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10878 01:01:19.718039 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10879 01:01:19.738837 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10880 01:01:19.758439 <46>[ 10.959531] systemd-journald[196]: Received client request to flush runtime journal.
10881 01:01:19.764862 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10882 01:01:19.789781 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10883 01:01:19.810322 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10884 01:01:19.836182 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10885 01:01:19.855024 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10886 01:01:19.875155 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10887 01:01:19.895404 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10888 01:01:19.915441 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10889 01:01:19.966946 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10890 01:01:19.992800 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10891 01:01:20.014057 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10892 01:01:20.029781 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10893 01:01:20.078218 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10894 01:01:20.102896 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10895 01:01:20.132510 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10896 01:01:20.154359 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10897 01:01:20.198105 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10898 01:01:20.233681 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10899 01:01:20.268397 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10900 01:01:20.293897 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10901 01:01:20.324219 <5>[ 11.524922] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10902 01:01:20.339315 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10903 01:01:20.359722 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10904 01:01:20.379217 <5>[ 11.580596] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10905 01:01:20.385956 <5>[ 11.588119] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10906 01:01:20.396675 <4>[ 11.596684] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10907 01:01:20.402471 <6>[ 11.605594] cfg80211: failed to load regulatory.db
10908 01:01:20.427934 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10909 01:01:20.476039 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10910 01:01:20.495258 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10911 01:01:20.515171 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10912 01:01:20.535135 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10913 01:01:20.554833 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10914 01:01:20.567947 <6>[ 11.768743] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10915 01:01:20.577210 <3>[ 11.778189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 01:01:20.581062 <6>[ 11.785275] remoteproc remoteproc0: scp is available
10917 01:01:20.590809 <3>[ 11.786553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 01:01:20.597229 <6>[ 11.787688] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10919 01:01:20.607205 <6>[ 11.787712] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10920 01:01:20.613878 <6>[ 11.787717] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10921 01:01:20.620416 <6>[ 11.792115] remoteproc remoteproc0: powering up scp
10922 01:01:20.627024 <3>[ 11.799754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 01:01:20.636907 <6>[ 11.807292] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10924 01:01:20.643367 <6>[ 11.807554] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10925 01:01:20.653441 <6>[ 11.819259] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10926 01:01:20.659988 <6>[ 11.824675] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10927 01:01:20.667075 <6>[ 11.829791] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10928 01:01:20.673310 <3>[ 11.851320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 01:01:20.683691 <4>[ 11.854682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10930 01:01:20.692970 <3>[ 11.862971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 01:01:20.699444 <6>[ 11.868840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10932 01:01:20.705964 <6>[ 11.869305] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10933 01:01:20.712691 <6>[ 11.869464] mc: Linux media interface: v0.10
10934 01:01:20.719692 <3>[ 11.875939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 01:01:20.729493 <3>[ 11.875967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 01:01:20.735964 <6>[ 11.884688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10937 01:01:20.742818 <4>[ 11.886146] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10938 01:01:20.752601 <4>[ 11.893404] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10939 01:01:20.759383 <3>[ 11.894176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10940 01:01:20.769434 <4>[ 11.905788] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10941 01:01:20.772553 <4>[ 11.905788] Fallback method does not support PEC.
10942 01:01:20.782519 <6>[ 11.907413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10943 01:01:20.789799 <6>[ 11.907430] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10944 01:01:20.795880 <6>[ 11.907433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10945 01:01:20.806070 <6>[ 11.907437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10946 01:01:20.812536 <3>[ 11.907610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10947 01:01:20.823048 <3>[ 11.913538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 01:01:20.829332 <6>[ 11.918257] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10949 01:01:20.836199 <3>[ 11.922329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10950 01:01:20.842731 <6>[ 11.926370] videodev: Linux video capture interface: v2.00
10951 01:01:20.849308 <6>[ 11.930478] pci_bus 0000:00: root bus resource [bus 00-ff]
10952 01:01:20.855842 <3>[ 11.938382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10953 01:01:20.862990 <6>[ 11.946225] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10954 01:01:20.872492 <6>[ 11.946236] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10955 01:01:20.878847 <6>[ 11.946423] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10956 01:01:20.889576 <3>[ 11.953992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10957 01:01:20.895693 <6>[ 11.960936] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10958 01:01:20.902853 <6>[ 11.963068] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10959 01:01:20.909350 <6>[ 11.963102] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10960 01:01:20.915981 <6>[ 11.963111] remoteproc remoteproc0: remote processor scp is now up
10961 01:01:20.926638 <3>[ 11.969015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10962 01:01:20.932936 <6>[ 11.970386] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10963 01:01:20.942695 <6>[ 11.973058] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10964 01:01:20.946255 <6>[ 11.982768] pci 0000:00:00.0: supports D1 D2
10965 01:01:20.956121 <3>[ 11.990685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10966 01:01:20.963034 <6>[ 11.998477] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10967 01:01:20.969832 <6>[ 11.999398] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10968 01:01:20.980075 <6>[ 11.999977] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10969 01:01:20.989982 <3>[ 12.005447] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 01:01:20.997101 <3>[ 12.006230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10971 01:01:21.006956 <3>[ 12.006237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10972 01:01:21.014356 <3>[ 12.006286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10973 01:01:21.021271 <6>[ 12.016429] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10974 01:01:21.031781 <6>[ 12.020158] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10975 01:01:21.035183 <6>[ 12.052797] Bluetooth: Core ver 2.22
10976 01:01:21.041640 <6>[ 12.058128] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10977 01:01:21.048188 <6>[ 12.066129] NET: Registered PF_BLUETOOTH protocol family
10978 01:01:21.055020 <6>[ 12.073198] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10979 01:01:21.061958 <6>[ 12.083075] Bluetooth: HCI device and connection manager initialized
10980 01:01:21.065291 <6>[ 12.083104] Bluetooth: HCI socket layer initialized
10981 01:01:21.072751 <6>[ 12.084796] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10982 01:01:21.085558 <6>[ 12.086034] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10983 01:01:21.092786 <6>[ 12.086198] usbcore: registered new interface driver uvcvideo
10984 01:01:21.099455 <6>[ 12.089373] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10985 01:01:21.102421 <6>[ 12.097441] Bluetooth: L2CAP socket layer initialized
10986 01:01:21.112592 <6>[ 12.104921] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10987 01:01:21.115974 <6>[ 12.111951] Bluetooth: SCO socket layer initialized
10988 01:01:21.123238 <6>[ 12.121191] pci 0000:01:00.0: supports D1 D2
10989 01:01:21.126158 <6>[ 12.128207] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10990 01:01:21.136287 <6>[ 12.135099] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10991 01:01:21.139332 <6>[ 12.164859] usbcore: registered new interface driver btusb
10992 01:01:21.149931 <4>[ 12.165493] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10993 01:01:21.156580 <3>[ 12.165499] Bluetooth: hci0: Failed to load firmware file (-2)
10994 01:01:21.163100 <3>[ 12.165501] Bluetooth: hci0: Failed to set up firmware (-2)
10995 01:01:21.173292 <4>[ 12.165502] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10996 01:01:21.183922 <3>[ 12.179525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 01:01:21.187673 <6>[ 12.183087] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10998 01:01:21.197504 <3>[ 12.191157] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 01:01:21.204461 <6>[ 12.198984] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11000 01:01:21.214458 <3>[ 12.225966] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 01:01:21.222081 <3>[ 12.226779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11002 01:01:21.231946 <6>[ 12.231466] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11003 01:01:21.238494 <6>[ 12.231475] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11004 01:01:21.249658 <3>[ 12.243263] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 01:01:21.256180 <6>[ 12.244601] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11006 01:01:21.266121 <3>[ 12.271116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 01:01:21.272742 <6>[ 12.275604] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11008 01:01:21.282452 <3>[ 12.302961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 01:01:21.285602 <6>[ 12.308519] pci 0000:00:00.0: PCI bridge to [bus 01]
11010 01:01:21.295394 <3>[ 12.333254] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 01:01:21.302291 <6>[ 12.337445] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11012 01:01:21.308825 <6>[ 12.337652] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11013 01:01:21.318833 <3>[ 12.365512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 01:01:21.325314 <6>[ 12.367336] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11015 01:01:21.332266 [[0;32m OK [<6>[ 12.534811] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11016 01:01:21.338737 0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11017 01:01:21.355726 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11018 01:01:21.374480 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11019 01:01:21.384451 [[0;32m OK [<6>[ 12.584026] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11020 01:01:21.391459 0m] Reached targ<6>[ 12.592937] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11021 01:01:21.394935 et [0;1;39mbasic.target[0m - Basic System.
11022 01:01:21.416219 <6>[ 12.620946] mt7921e 0000:01:00.0: ASIC revision: 79610010
11023 01:01:21.451089 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11024 01:01:21.480369 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11025 01:01:21.506718 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11026 01:01:21.519824 <6>[ 12.721165] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11027 01:01:21.523658 <6>[ 12.721165]
11028 01:01:21.532864 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11029 01:01:21.557375 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11030 01:01:21.610256 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11031 01:01:21.630430 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11032 01:01:21.646791 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11033 01:01:21.667399 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11034 01:01:21.727842 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11035 01:01:21.748812 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11036 01:01:21.766668 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11037 01:01:21.788909 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0<6>[ 12.988965] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11038 01:01:21.789416 m - Multi-User System.
11039 01:01:21.810294 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11040 01:01:21.872072 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11041 01:01:21.895848 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11042 01:01:21.921615 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11043 01:01:22.004468 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11044 01:01:22.024793 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11045 01:01:22.048871 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11046 01:01:22.101576
11047 01:01:22.105025 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11048 01:01:22.105507
11049 01:01:22.107683 debian-bookworm-arm64 login: root (automatic login)
11050 01:01:22.108073
11051 01:01:22.131644 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11052 01:01:22.132174
11053 01:01:22.138196 The programs included with the Debian GNU/Linux system are free software;
11054 01:01:22.144979 the exact distribution terms for each program are described in the
11055 01:01:22.147854 individual files in /usr/share/doc/*/copyright.
11056 01:01:22.148326
11057 01:01:22.154359 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11058 01:01:22.158205 permitted by applicable law.
11059 01:01:22.159553 Matched prompt #10: / #
11061 01:01:22.160460 Setting prompt string to ['/ #']
11062 01:01:22.160900 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11064 01:01:22.161808 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11065 01:01:22.162213 start: 2.2.6 expect-shell-connection (timeout 00:02:26) [common]
11066 01:01:22.162540 Setting prompt string to ['/ #']
11067 01:01:22.162824 Forcing a shell prompt, looking for ['/ #']
11069 01:01:22.213534 / #
11070 01:01:22.214383 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11071 01:01:22.214786 Waiting using forced prompt support (timeout 00:02:30)
11072 01:01:22.220457
11073 01:01:22.221357 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11074 01:01:22.221860 start: 2.2.7 export-device-env (timeout 00:02:26) [common]
11075 01:01:22.222327 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11076 01:01:22.222757 end: 2.2 depthcharge-retry (duration 00:02:34) [common]
11077 01:01:22.223206 end: 2 depthcharge-action (duration 00:02:34) [common]
11078 01:01:22.223672 start: 3 lava-test-retry (timeout 00:05:00) [common]
11079 01:01:22.224143 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11080 01:01:22.224801 Using namespace: common
11082 01:01:22.326059 / # #
11083 01:01:22.326729 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11084 01:01:22.333004 #
11085 01:01:22.333796 Using /lava-14368605
11087 01:01:22.434845 / # export SHELL=/bin/sh
11088 01:01:22.440721 export SHELL=/bin/sh
11090 01:01:22.542096 / # . /lava-14368605/environment
11091 01:01:22.548549 . /lava-14368605/environment
11093 01:01:22.650213 / # /lava-14368605/bin/lava-test-runner /lava-14368605/0
11094 01:01:22.650871 Test shell timeout: 10s (minimum of the action and connection timeout)
11095 01:01:22.654914 /lava-14368605/bin/lava-test-runner /lava-14368605/0<6>[ 13.859217] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11096 01:01:22.655450
11097 01:01:22.676384 + export TESTRUN_ID=0_cros-ec
11098 01:01:22.683178 +<8>[ 13.886605] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14368605_1.5.2.3.1>
11099 01:01:22.684055 Received signal: <STARTRUN> 0_cros-ec 14368605_1.5.2.3.1
11100 01:01:22.684460 Starting test lava.0_cros-ec (14368605_1.5.2.3.1)
11101 01:01:22.684933 Skipping test definition patterns.
11102 01:01:22.686218 cd /lava-14368605/0/tests/0_cros-ec
11103 01:01:22.689832 + cat uuid
11104 01:01:22.690385 + UUID=14368605_1.5.2.3.1
11105 01:01:22.690743 + set +x
11106 01:01:22.696682 + python3 -m cros.runners.lava_runner -v
11107 01:01:23.172194 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11108 01:01:23.178279 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11109 01:01:23.178796
11110 01:01:23.185228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11111 01:01:23.186017 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11113 01:01:23.195631 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11114 01:01:23.204957 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11115 01:01:23.205438
11116 01:01:23.211676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11117 01:01:23.212420 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11119 01:01:23.221075 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11120 01:01:23.228098 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11121 01:01:23.228251
11122 01:01:23.234795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11123 01:01:23.235133 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11125 01:01:23.241392 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11126 01:01:23.244362 Checks the standard ABI for the main Embedded Controller. ... ok
11127 01:01:23.247644
11128 01:01:23.250845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11129 01:01:23.251224 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11131 01:01:23.257469 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11132 01:01:23.264312 Checks the main Embedded controller character device. ... ok
11133 01:01:23.264563
11134 01:01:23.270799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11135 01:01:23.271296 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11137 01:01:23.277357 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11138 01:01:23.283958 Checks basic comunication with the main Embedded controller. ... ok
11139 01:01:23.284422
11140 01:01:23.290822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11141 01:01:23.291557 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11143 01:01:23.297227 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11144 01:01:23.304226 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11145 01:01:23.304748
11146 01:01:23.310391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11147 01:01:23.311109 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11149 01:01:23.317002 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11150 01:01:23.323688 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11151 01:01:23.324081
11152 01:01:23.330611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11153 01:01:23.331325 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11155 01:01:23.337066 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11156 01:01:23.343385 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11157 01:01:23.343889
11158 01:01:23.350644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11159 01:01:23.351372 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11161 01:01:23.356889 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11162 01:01:23.363987 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11163 01:01:23.366863
11164 01:01:23.370095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11165 01:01:23.370732 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11167 01:01:23.376937 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11168 01:01:23.386665 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11169 01:01:23.387153
11170 01:01:23.393527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11171 01:01:23.394261 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11173 01:01:23.400214 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11174 01:01:23.406658 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11175 01:01:23.407141
11176 01:01:23.413365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11177 01:01:23.414099 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11179 01:01:23.419942 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11180 01:01:23.426773 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11181 01:01:23.427264
11182 01:01:23.433518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11183 01:01:23.434243 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11185 01:01:23.443309 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11186 01:01:23.449646 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11187 01:01:23.450129
11188 01:01:23.455928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11189 01:01:23.456639 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11191 01:01:23.466222 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11192 01:01:23.469756 Check the cros battery ABI. ... skipped 'No BAT found'
11193 01:01:23.470249
11194 01:01:23.476332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11195 01:01:23.477103 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11197 01:01:23.485952 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11198 01:01:23.492356 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11199 01:01:23.492863
11200 01:01:23.499374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11201 01:01:23.500103 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11203 01:01:23.505675 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11204 01:01:23.512795 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11205 01:01:23.513278
11206 01:01:23.518752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11207 01:01:23.519477 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11209 01:01:23.529152 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11210 01:01:23.535742 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11211 01:01:23.536240
11212 01:01:23.542443 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8
11213 01:01:23.543021 Bad test result: ski<8
11214 01:01:23.548501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8>[ 14.751328] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14368605_1.5.2.3.1>
11215 01:01:23.548955 p>
11216 01:01:23.549356
11217 01:01:23.550016 Received signal: <ENDRUN> 0_cros-ec 14368605_1.5.2.3.1
11218 01:01:23.550439 Ending use of test pattern.
11219 01:01:23.550740 Ending test lava.0_cros-ec (14368605_1.5.2.3.1), duration 0.87
11221 01:01:23.555402 ----------------------------------------------------------------------
11222 01:01:23.555885 Ran 18 tests in 0.338s
11223 01:01:23.556193
11224 01:01:23.558534 OK (skipped=15)
11225 01:01:23.558923 + set +x
11226 01:01:23.562227 <LAVA_TEST_RUNNER EXIT>
11227 01:01:23.563226 ok: lava_test_shell seems to have completed
11228 01:01:23.564158 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11229 01:01:23.564611 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11230 01:01:23.565051 end: 3 lava-test-retry (duration 00:00:01) [common]
11231 01:01:23.565470 start: 4 finalize (timeout 00:07:02) [common]
11232 01:01:23.565874 start: 4.1 power-off (timeout 00:00:30) [common]
11233 01:01:23.566514 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11234 01:01:23.818109 >> Command sent successfully.
11235 01:01:23.831650 Returned 0 in 0 seconds
11236 01:01:23.932948 end: 4.1 power-off (duration 00:00:00) [common]
11238 01:01:23.934388 start: 4.2 read-feedback (timeout 00:07:02) [common]
11239 01:01:23.935517 Listened to connection for namespace 'common' for up to 1s
11240 01:01:24.936187 Finalising connection for namespace 'common'
11241 01:01:24.936895 Disconnecting from shell: Finalise
11242 01:01:24.937264 / #
11243 01:01:25.038133 end: 4.2 read-feedback (duration 00:00:01) [common]
11244 01:01:25.038745 end: 4 finalize (duration 00:00:01) [common]
11245 01:01:25.039263 Cleaning after the job
11246 01:01:25.039725 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/ramdisk
11247 01:01:25.064167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/kernel
11248 01:01:25.093282 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/dtb
11249 01:01:25.093525 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368605/tftp-deploy-djasquo9/modules
11250 01:01:25.100656 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368605
11251 01:01:25.183936 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368605
11252 01:01:25.184100 Job finished correctly